1 /* Subroutines used for code generation on Renesas RX processors.
2 Copyright (C) 2008, 2009, 2010, 2011, 2012
3 Free Software Foundation, Inc.
4 Contributed by Red Hat.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 * Re-enable memory-to-memory copies and fix up reload. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
44 #include "diagnostic-core.h"
52 #include "target-def.h"
53 #include "langhooks.h"
57 static unsigned int rx_gp_base_regnum_val
= INVALID_REGNUM
;
58 static unsigned int rx_pid_base_regnum_val
= INVALID_REGNUM
;
59 static unsigned int rx_num_interrupt_regs
;
62 rx_gp_base_regnum (void)
64 if (rx_gp_base_regnum_val
== INVALID_REGNUM
)
66 return rx_gp_base_regnum_val
;
70 rx_pid_base_regnum (void)
72 if (rx_pid_base_regnum_val
== INVALID_REGNUM
)
74 return rx_pid_base_regnum_val
;
77 /* Find a SYMBOL_REF in a "standard" MEM address and return its decl. */
80 rx_decl_for_addr (rtx op
)
82 if (GET_CODE (op
) == MEM
)
84 if (GET_CODE (op
) == CONST
)
86 while (GET_CODE (op
) == PLUS
)
88 if (GET_CODE (op
) == SYMBOL_REF
)
89 return SYMBOL_REF_DECL (op
);
93 static void rx_print_operand (FILE *, rtx
, int);
95 #define CC_FLAG_S (1 << 0)
96 #define CC_FLAG_Z (1 << 1)
97 #define CC_FLAG_O (1 << 2)
98 #define CC_FLAG_C (1 << 3)
99 #define CC_FLAG_FP (1 << 4) /* Fake, to differentiate CC_Fmode. */
101 static unsigned int flags_from_mode (enum machine_mode mode
);
102 static unsigned int flags_from_code (enum rtx_code code
);
104 /* Return true if OP is a reference to an object in a PID data area. */
108 PID_NOT_PID
= 0, /* The object is not in the PID data area. */
109 PID_ENCODED
, /* The object is in the PID data area. */
110 PID_UNENCODED
/* The object will be placed in the PID data area, but it has not been placed there yet. */
114 rx_pid_data_operand (rtx op
)
121 if (GET_CODE (op
) == PLUS
122 && GET_CODE (XEXP (op
, 0)) == REG
123 && GET_CODE (XEXP (op
, 1)) == CONST
124 && GET_CODE (XEXP (XEXP (op
, 1), 0)) == UNSPEC
)
127 op_decl
= rx_decl_for_addr (op
);
131 if (TREE_READONLY (op_decl
))
132 return PID_UNENCODED
;
136 /* Sigh, some special cases. */
137 if (GET_CODE (op
) == SYMBOL_REF
138 || GET_CODE (op
) == LABEL_REF
)
139 return PID_UNENCODED
;
146 rx_legitimize_address (rtx x
,
147 rtx oldx ATTRIBUTE_UNUSED
,
148 enum machine_mode mode ATTRIBUTE_UNUSED
)
150 if (rx_pid_data_operand (x
) == PID_UNENCODED
)
152 rtx rv
= gen_pid_addr (gen_rtx_REG (SImode
, rx_pid_base_regnum ()), x
);
156 if (GET_CODE (x
) == PLUS
157 && GET_CODE (XEXP (x
, 0)) == PLUS
158 && REG_P (XEXP (XEXP (x
, 0), 0))
159 && REG_P (XEXP (x
, 1)))
160 return force_reg (SImode
, x
);
165 /* Return true if OP is a reference to an object in a small data area. */
168 rx_small_data_operand (rtx op
)
170 if (rx_small_data_limit
== 0)
173 if (GET_CODE (op
) == SYMBOL_REF
)
174 return SYMBOL_REF_SMALL_P (op
);
180 rx_is_legitimate_address (enum machine_mode mode
, rtx x
,
181 bool strict ATTRIBUTE_UNUSED
)
183 if (RTX_OK_FOR_BASE (x
, strict
))
184 /* Register Indirect. */
187 if ((GET_MODE_SIZE (mode
) == 4
188 || GET_MODE_SIZE (mode
) == 2
189 || GET_MODE_SIZE (mode
) == 1)
190 && (GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
))
191 /* Pre-decrement Register Indirect or
192 Post-increment Register Indirect. */
193 return RTX_OK_FOR_BASE (XEXP (x
, 0), strict
);
195 switch (rx_pid_data_operand (x
))
205 if (GET_CODE (x
) == PLUS
)
207 rtx arg1
= XEXP (x
, 0);
208 rtx arg2
= XEXP (x
, 1);
209 rtx index
= NULL_RTX
;
211 if (REG_P (arg1
) && RTX_OK_FOR_BASE (arg1
, strict
))
213 else if (REG_P (arg2
) && RTX_OK_FOR_BASE (arg2
, strict
))
218 switch (GET_CODE (index
))
222 /* Register Relative: REG + INT.
223 Only positive, mode-aligned, mode-sized
224 displacements are allowed. */
225 HOST_WIDE_INT val
= INTVAL (index
);
231 switch (GET_MODE_SIZE (mode
))
234 case 4: factor
= 4; break;
235 case 2: factor
= 2; break;
236 case 1: factor
= 1; break;
239 if (val
> (65535 * factor
))
241 return (val
% factor
) == 0;
245 /* Unscaled Indexed Register Indirect: REG + REG
246 Size has to be "QI", REG has to be valid. */
247 return GET_MODE_SIZE (mode
) == 1 && RTX_OK_FOR_BASE (index
, strict
);
251 /* Scaled Indexed Register Indirect: REG + (REG * FACTOR)
252 Factor has to equal the mode size, REG has to be valid. */
255 factor
= XEXP (index
, 1);
256 index
= XEXP (index
, 0);
259 && RTX_OK_FOR_BASE (index
, strict
)
260 && CONST_INT_P (factor
)
261 && GET_MODE_SIZE (mode
) == INTVAL (factor
);
269 /* Small data area accesses turn into register relative offsets. */
270 return rx_small_data_operand (x
);
273 /* Returns TRUE for simple memory addreses, ie ones
274 that do not involve register indirect addressing
275 or pre/post increment/decrement. */
278 rx_is_restricted_memory_address (rtx mem
, enum machine_mode mode
)
280 if (! rx_is_legitimate_address
281 (mode
, mem
, reload_in_progress
|| reload_completed
))
284 switch (GET_CODE (mem
))
287 /* Simple memory addresses are OK. */
298 /* Only allow REG+INT addressing. */
299 base
= XEXP (mem
, 0);
300 index
= XEXP (mem
, 1);
302 if (! RX_REG_P (base
) || ! CONST_INT_P (index
))
305 return IN_RANGE (INTVAL (index
), 0, (0x10000 * GET_MODE_SIZE (mode
)) - 1);
309 /* Can happen when small data is being supported.
310 Assume that it will be resolved into GP+INT. */
318 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
321 rx_mode_dependent_address_p (const_rtx addr
)
323 if (GET_CODE (addr
) == CONST
)
324 addr
= XEXP (addr
, 0);
326 switch (GET_CODE (addr
))
328 /* --REG and REG++ only work in SImode. */
335 if (! REG_P (XEXP (addr
, 0)))
338 addr
= XEXP (addr
, 1);
340 switch (GET_CODE (addr
))
343 /* REG+REG only works in SImode. */
347 /* REG+INT is only mode independent if INT is a
348 multiple of 4, positive and will fit into 8-bits. */
349 if (((INTVAL (addr
) & 3) == 0)
350 && IN_RANGE (INTVAL (addr
), 4, 252))
359 gcc_assert (REG_P (XEXP (addr
, 0)));
360 gcc_assert (CONST_INT_P (XEXP (addr
, 1)));
361 /* REG+REG*SCALE is always mode dependent. */
365 /* Not recognized, so treat as mode dependent. */
373 /* These are all mode independent. */
377 /* Everything else is unrecognized,
378 so treat as mode dependent. */
383 /* A C compound statement to output to stdio stream FILE the
384 assembler syntax for an instruction operand that is a memory
385 reference whose address is ADDR. */
388 rx_print_operand_address (FILE * file
, rtx addr
)
390 switch (GET_CODE (addr
))
394 rx_print_operand (file
, addr
, 0);
399 fprintf (file
, "[-");
400 rx_print_operand (file
, XEXP (addr
, 0), 0);
406 rx_print_operand (file
, XEXP (addr
, 0), 0);
407 fprintf (file
, "+]");
412 rtx arg1
= XEXP (addr
, 0);
413 rtx arg2
= XEXP (addr
, 1);
416 if (REG_P (arg1
) && RTX_OK_FOR_BASE (arg1
, true))
417 base
= arg1
, index
= arg2
;
418 else if (REG_P (arg2
) && RTX_OK_FOR_BASE (arg2
, true))
419 base
= arg2
, index
= arg1
;
422 rx_print_operand (file
, arg1
, 0);
423 fprintf (file
, " + ");
424 rx_print_operand (file
, arg2
, 0);
428 if (REG_P (index
) || GET_CODE (index
) == MULT
)
431 rx_print_operand (file
, index
, 'A');
434 else /* GET_CODE (index) == CONST_INT */
436 rx_print_operand (file
, index
, 'A');
439 rx_print_operand (file
, base
, 0);
445 if (GET_CODE (XEXP (addr
, 0)) == UNSPEC
)
447 addr
= XEXP (addr
, 0);
448 gcc_assert (XINT (addr
, 1) == UNSPEC_CONST
);
450 /* FIXME: Putting this case label here is an appalling abuse of the C language. */
452 addr
= XVECEXP (addr
, 0, 0);
453 gcc_assert (CONST_INT_P (addr
));
461 output_addr_const (file
, addr
);
467 rx_print_integer (FILE * file
, HOST_WIDE_INT val
)
469 if (IN_RANGE (val
, -64, 64))
470 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, val
);
474 ? "0%" HOST_WIDE_INT_PRINT
"xH" : HOST_WIDE_INT_PRINT_HEX
,
479 rx_assemble_integer (rtx x
, unsigned int size
, int is_aligned
)
481 const char * op
= integer_asm_op (size
, is_aligned
);
483 if (! CONST_INT_P (x
))
484 return default_assemble_integer (x
, size
, is_aligned
);
488 fputs (op
, asm_out_file
);
490 rx_print_integer (asm_out_file
, INTVAL (x
));
491 fputc ('\n', asm_out_file
);
496 /* Handles the insertion of a single operand into the assembler output.
497 The %<letter> directives supported are:
499 %A Print an operand without a leading # character.
500 %B Print an integer comparison name.
501 %C Print a control register name.
502 %F Print a condition code flag name.
503 %G Register used for small-data-area addressing
504 %H Print high part of a DImode register, integer or address.
505 %L Print low part of a DImode register, integer or address.
506 %N Print the negation of the immediate value.
507 %P Register used for PID addressing
508 %Q If the operand is a MEM, then correctly generate
509 register indirect or register relative addressing.
510 %R Like %Q but for zero-extending loads. */
513 rx_print_operand (FILE * file
, rtx op
, int letter
)
515 bool unsigned_load
= false;
516 bool print_hash
= true;
519 && ((GET_CODE (op
) == CONST
520 && GET_CODE (XEXP (op
, 0)) == UNSPEC
)
521 || GET_CODE (op
) == UNSPEC
))
530 /* Print an operand without a leading #. */
534 switch (GET_CODE (op
))
538 output_addr_const (file
, op
);
541 fprintf (file
, "%ld", (long) INTVAL (op
));
544 rx_print_operand (file
, op
, 0);
551 enum rtx_code code
= GET_CODE (op
);
552 enum machine_mode mode
= GET_MODE (XEXP (op
, 0));
555 if (mode
== CC_Fmode
)
557 /* C flag is undefined, and O flag carries unordered. None of the
558 branch combinations that include O use it helpfully. */
585 unsigned int flags
= flags_from_mode (mode
);
590 ret
= (flags
& CC_FLAG_O
? "lt" : "n");
593 ret
= (flags
& CC_FLAG_O
? "ge" : "pz");
622 gcc_checking_assert ((flags_from_code (code
) & ~flags
) == 0);
629 gcc_assert (CONST_INT_P (op
));
632 case 0: fprintf (file
, "psw"); break;
633 case 2: fprintf (file
, "usp"); break;
634 case 3: fprintf (file
, "fpsw"); break;
635 case 4: fprintf (file
, "cpen"); break;
636 case 8: fprintf (file
, "bpsw"); break;
637 case 9: fprintf (file
, "bpc"); break;
638 case 0xa: fprintf (file
, "isp"); break;
639 case 0xb: fprintf (file
, "fintv"); break;
640 case 0xc: fprintf (file
, "intb"); break;
642 warning (0, "unrecognized control register number: %d - using 'psw'",
644 fprintf (file
, "psw");
650 gcc_assert (CONST_INT_P (op
));
653 case 0: case 'c': case 'C': fprintf (file
, "C"); break;
654 case 1: case 'z': case 'Z': fprintf (file
, "Z"); break;
655 case 2: case 's': case 'S': fprintf (file
, "S"); break;
656 case 3: case 'o': case 'O': fprintf (file
, "O"); break;
657 case 8: case 'i': case 'I': fprintf (file
, "I"); break;
658 case 9: case 'u': case 'U': fprintf (file
, "U"); break;
665 fprintf (file
, "%s", reg_names
[rx_gp_base_regnum ()]);
669 switch (GET_CODE (op
))
672 fprintf (file
, "%s", reg_names
[REGNO (op
) + (WORDS_BIG_ENDIAN
? 0 : 1)]);
676 HOST_WIDE_INT v
= INTVAL (op
);
679 /* Trickery to avoid problems with shifting 32 bits at a time. */
682 rx_print_integer (file
, v
);
687 rx_print_integer (file
, CONST_DOUBLE_HIGH (op
));
690 if (! WORDS_BIG_ENDIAN
)
691 op
= adjust_address (op
, SImode
, 4);
692 output_address (XEXP (op
, 0));
700 switch (GET_CODE (op
))
703 fprintf (file
, "%s", reg_names
[REGNO (op
) + (WORDS_BIG_ENDIAN
? 1 : 0)]);
707 rx_print_integer (file
, INTVAL (op
) & 0xffffffff);
711 rx_print_integer (file
, CONST_DOUBLE_LOW (op
));
714 if (WORDS_BIG_ENDIAN
)
715 op
= adjust_address (op
, SImode
, 4);
716 output_address (XEXP (op
, 0));
724 gcc_assert (CONST_INT_P (op
));
726 rx_print_integer (file
, - INTVAL (op
));
730 fprintf (file
, "%s", reg_names
[rx_pid_base_regnum ()]);
734 gcc_assert (GET_MODE_SIZE (GET_MODE (op
)) < 4);
735 unsigned_load
= true;
740 HOST_WIDE_INT offset
;
747 else if (GET_CODE (op
) == PLUS
)
751 if (REG_P (XEXP (op
, 0)))
753 displacement
= XEXP (op
, 1);
758 displacement
= XEXP (op
, 0);
760 gcc_assert (REG_P (op
));
763 gcc_assert (CONST_INT_P (displacement
));
764 offset
= INTVAL (displacement
);
765 gcc_assert (offset
>= 0);
767 fprintf (file
, "%ld", offset
);
773 rx_print_operand (file
, op
, 0);
774 fprintf (file
, "].");
776 switch (GET_MODE_SIZE (GET_MODE (mem
)))
779 gcc_assert (offset
<= 65535 * 1);
780 fprintf (file
, unsigned_load
? "UB" : "B");
783 gcc_assert (offset
% 2 == 0);
784 gcc_assert (offset
<= 65535 * 2);
785 fprintf (file
, unsigned_load
? "UW" : "W");
788 gcc_assert (offset
% 4 == 0);
789 gcc_assert (offset
<= 65535 * 4);
801 if (GET_CODE (op
) == CONST
802 && GET_CODE (XEXP (op
, 0)) == UNSPEC
)
804 else if (GET_CODE (op
) == CONST
805 && GET_CODE (XEXP (op
, 0)) == PLUS
806 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == UNSPEC
807 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
)
812 rx_print_operand (file
, XEXP (XEXP (op
, 0), 0), 'A');
813 fprintf (file
, " + ");
814 output_addr_const (file
, XEXP (XEXP (op
, 0), 1));
819 switch (GET_CODE (op
))
822 /* Should be the scaled part of an
823 indexed register indirect address. */
825 rtx base
= XEXP (op
, 0);
826 rtx index
= XEXP (op
, 1);
828 /* Check for a swaped index register and scaling factor.
829 Not sure if this can happen, but be prepared to handle it. */
830 if (CONST_INT_P (base
) && REG_P (index
))
837 gcc_assert (REG_P (base
));
838 gcc_assert (REGNO (base
) < FIRST_PSEUDO_REGISTER
);
839 gcc_assert (CONST_INT_P (index
));
840 /* Do not try to verify the value of the scalar as it is based
841 on the mode of the MEM not the mode of the MULT. (Which
842 will always be SImode). */
843 fprintf (file
, "%s", reg_names
[REGNO (base
)]);
848 output_address (XEXP (op
, 0));
856 gcc_assert (REGNO (op
) < FIRST_PSEUDO_REGISTER
);
857 fprintf (file
, "%s", reg_names
[REGNO (op
)]);
861 gcc_assert (subreg_regno (op
) < FIRST_PSEUDO_REGISTER
);
862 fprintf (file
, "%s", reg_names
[subreg_regno (op
)]);
865 /* This will only be single precision.... */
871 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
872 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
875 fprintf (file
, TARGET_AS100_SYNTAX
? "0%lxH" : "0x%lx", val
);
882 rx_print_integer (file
, INTVAL (op
));
886 switch (XINT (op
, 1))
888 case UNSPEC_PID_ADDR
:
894 sym
= XVECEXP (op
, 0, 0);
897 if (GET_CODE (sym
) == PLUS
)
902 output_addr_const (file
, sym
);
906 output_addr_const (file
, add
);
908 fprintf (file
, "-__pid_base");
919 rx_print_operand_address (file
, op
);
929 /* Maybe convert an operand into its PID format. */
932 rx_maybe_pidify_operand (rtx op
, int copy_to_reg
)
934 if (rx_pid_data_operand (op
) == PID_UNENCODED
)
936 if (GET_CODE (op
) == MEM
)
938 rtx a
= gen_pid_addr (gen_rtx_REG (SImode
, rx_pid_base_regnum ()), XEXP (op
, 0));
939 op
= replace_equiv_address (op
, a
);
943 op
= gen_pid_addr (gen_rtx_REG (SImode
, rx_pid_base_regnum ()), op
);
947 op
= copy_to_mode_reg (GET_MODE (op
), op
);
952 /* Returns an assembler template for a move instruction. */
955 rx_gen_move_template (rtx
* operands
, bool is_movu
)
957 static char out_template
[64];
958 const char * extension
= TARGET_AS100_SYNTAX
? ".L" : "";
959 const char * src_template
;
960 const char * dst_template
;
961 rtx dest
= operands
[0];
962 rtx src
= operands
[1];
964 /* Decide which extension, if any, should be given to the move instruction. */
965 switch (CONST_INT_P (src
) ? GET_MODE (dest
) : GET_MODE (src
))
968 /* The .B extension is not valid when
969 loading an immediate into a register. */
970 if (! REG_P (dest
) || ! CONST_INT_P (src
))
974 if (! REG_P (dest
) || ! CONST_INT_P (src
))
975 /* The .W extension is not valid when
976 loading an immediate into a register. */
984 /* This mode is used by constants. */
991 if (MEM_P (src
) && rx_pid_data_operand (XEXP (src
, 0)) == PID_UNENCODED
)
992 src_template
= "(%A1-__pid_base)[%P1]";
993 else if (MEM_P (src
) && rx_small_data_operand (XEXP (src
, 0)))
994 src_template
= "%%gp(%A1)[%G1]";
998 if (MEM_P (dest
) && rx_small_data_operand (XEXP (dest
, 0)))
999 dst_template
= "%%gp(%A0)[%G0]";
1001 dst_template
= "%0";
1003 sprintf (out_template
, "%s%s\t%s, %s", is_movu
? "movu" : "mov",
1004 extension
, src_template
, dst_template
);
1005 return out_template
;
1008 /* Return VALUE rounded up to the next ALIGNMENT boundary. */
1010 static inline unsigned int
1011 rx_round_up (unsigned int value
, unsigned int alignment
)
1014 return (value
+ alignment
) & (~ alignment
);
1017 /* Return the number of bytes in the argument registers
1018 occupied by an argument of type TYPE and mode MODE. */
1021 rx_function_arg_size (enum machine_mode mode
, const_tree type
)
1023 unsigned int num_bytes
;
1025 num_bytes
= (mode
== BLKmode
)
1026 ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
1027 return rx_round_up (num_bytes
, UNITS_PER_WORD
);
1030 #define NUM_ARG_REGS 4
1031 #define MAX_NUM_ARG_BYTES (NUM_ARG_REGS * UNITS_PER_WORD)
1033 /* Return an RTL expression describing the register holding a function
1034 parameter of mode MODE and type TYPE or NULL_RTX if the parameter should
1035 be passed on the stack. CUM describes the previous parameters to the
1036 function and NAMED is false if the parameter is part of a variable
1037 parameter list, or the last named parameter before the start of a
1038 variable parameter list. */
1041 rx_function_arg (cumulative_args_t cum
, enum machine_mode mode
,
1042 const_tree type
, bool named
)
1044 unsigned int next_reg
;
1045 unsigned int bytes_so_far
= *get_cumulative_args (cum
);
1047 unsigned int rounded_size
;
1049 /* An exploded version of rx_function_arg_size. */
1050 size
= (mode
== BLKmode
) ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
1051 /* If the size is not known it cannot be passed in registers. */
1055 rounded_size
= rx_round_up (size
, UNITS_PER_WORD
);
1057 /* Don't pass this arg via registers if there
1058 are insufficient registers to hold all of it. */
1059 if (rounded_size
+ bytes_so_far
> MAX_NUM_ARG_BYTES
)
1062 /* Unnamed arguments and the last named argument in a
1063 variadic function are always passed on the stack. */
1067 /* Structures must occupy an exact number of registers,
1068 otherwise they are passed on the stack. */
1069 if ((type
== NULL
|| AGGREGATE_TYPE_P (type
))
1070 && (size
% UNITS_PER_WORD
) != 0)
1073 next_reg
= (bytes_so_far
/ UNITS_PER_WORD
) + 1;
1075 return gen_rtx_REG (mode
, next_reg
);
1079 rx_function_arg_advance (cumulative_args_t cum
, enum machine_mode mode
,
1080 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1082 *get_cumulative_args (cum
) += rx_function_arg_size (mode
, type
);
1086 rx_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED
,
1087 const_tree type ATTRIBUTE_UNUSED
)
1092 /* Return an RTL describing where a function return value of type RET_TYPE
1096 rx_function_value (const_tree ret_type
,
1097 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
1098 bool outgoing ATTRIBUTE_UNUSED
)
1100 enum machine_mode mode
= TYPE_MODE (ret_type
);
1102 /* RX ABI specifies that small integer types are
1103 promoted to int when returned by a function. */
1104 if (GET_MODE_SIZE (mode
) > 0
1105 && GET_MODE_SIZE (mode
) < 4
1106 && ! COMPLEX_MODE_P (mode
)
1108 return gen_rtx_REG (SImode
, FUNC_RETURN_REGNUM
);
1110 return gen_rtx_REG (mode
, FUNC_RETURN_REGNUM
);
1113 /* TARGET_PROMOTE_FUNCTION_MODE must behave in the same way with
1114 regard to function returns as does TARGET_FUNCTION_VALUE. */
1116 static enum machine_mode
1117 rx_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
1118 enum machine_mode mode
,
1119 int * punsignedp ATTRIBUTE_UNUSED
,
1120 const_tree funtype ATTRIBUTE_UNUSED
,
1124 || GET_MODE_SIZE (mode
) >= 4
1125 || COMPLEX_MODE_P (mode
)
1126 || GET_MODE_SIZE (mode
) < 1)
1133 rx_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
1137 if (TYPE_MODE (type
) != BLKmode
1138 && ! AGGREGATE_TYPE_P (type
))
1141 size
= int_size_in_bytes (type
);
1142 /* Large structs and those whose size is not an
1143 exact multiple of 4 are returned in memory. */
1146 || (size
% UNITS_PER_WORD
) != 0;
1150 rx_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED
,
1151 int incoming ATTRIBUTE_UNUSED
)
1153 return gen_rtx_REG (Pmode
, STRUCT_VAL_REGNUM
);
1157 rx_return_in_msb (const_tree valtype
)
1159 return TARGET_BIG_ENDIAN_DATA
1160 && (AGGREGATE_TYPE_P (valtype
) || TREE_CODE (valtype
) == COMPLEX_TYPE
);
1163 /* Returns true if the provided function has the specified attribute. */
1166 has_func_attr (const_tree decl
, const char * func_attr
)
1168 if (decl
== NULL_TREE
)
1169 decl
= current_function_decl
;
1171 return lookup_attribute (func_attr
, DECL_ATTRIBUTES (decl
)) != NULL_TREE
;
1174 /* Returns true if the provided function has the "fast_interrupt" attribute. */
1177 is_fast_interrupt_func (const_tree decl
)
1179 return has_func_attr (decl
, "fast_interrupt");
1182 /* Returns true if the provided function has the "interrupt" attribute. */
1185 is_interrupt_func (const_tree decl
)
1187 return has_func_attr (decl
, "interrupt");
1190 /* Returns true if the provided function has the "naked" attribute. */
1193 is_naked_func (const_tree decl
)
1195 return has_func_attr (decl
, "naked");
1198 static bool use_fixed_regs
= false;
1201 rx_conditional_register_usage (void)
1203 static bool using_fixed_regs
= false;
1207 rx_pid_base_regnum_val
= GP_BASE_REGNUM
- rx_num_interrupt_regs
;
1208 fixed_regs
[rx_pid_base_regnum_val
] = call_used_regs
[rx_pid_base_regnum_val
] = 1;
1211 if (rx_small_data_limit
> 0)
1214 rx_gp_base_regnum_val
= rx_pid_base_regnum_val
- 1;
1216 rx_gp_base_regnum_val
= GP_BASE_REGNUM
- rx_num_interrupt_regs
;
1218 fixed_regs
[rx_gp_base_regnum_val
] = call_used_regs
[rx_gp_base_regnum_val
] = 1;
1221 if (use_fixed_regs
!= using_fixed_regs
)
1223 static char saved_fixed_regs
[FIRST_PSEUDO_REGISTER
];
1224 static char saved_call_used_regs
[FIRST_PSEUDO_REGISTER
];
1230 memcpy (saved_fixed_regs
, fixed_regs
, sizeof fixed_regs
);
1231 memcpy (saved_call_used_regs
, call_used_regs
, sizeof call_used_regs
);
1233 /* This is for fast interrupt handlers. Any register in
1234 the range r10 to r13 (inclusive) that is currently
1235 marked as fixed is now a viable, call-used register. */
1236 for (r
= 10; r
<= 13; r
++)
1240 call_used_regs
[r
] = 1;
1243 /* Mark r7 as fixed. This is just a hack to avoid
1244 altering the reg_alloc_order array so that the newly
1245 freed r10-r13 registers are the preferred registers. */
1246 fixed_regs
[7] = call_used_regs
[7] = 1;
1250 /* Restore the normal register masks. */
1251 memcpy (fixed_regs
, saved_fixed_regs
, sizeof fixed_regs
);
1252 memcpy (call_used_regs
, saved_call_used_regs
, sizeof call_used_regs
);
1255 using_fixed_regs
= use_fixed_regs
;
1259 /* Perform any actions necessary before starting to compile FNDECL.
1260 For the RX we use this to make sure that we have the correct
1261 set of register masks selected. If FNDECL is NULL then we are
1262 compiling top level things. */
1265 rx_set_current_function (tree fndecl
)
1267 /* Remember the last target of rx_set_current_function. */
1268 static tree rx_previous_fndecl
;
1269 bool prev_was_fast_interrupt
;
1270 bool current_is_fast_interrupt
;
1272 /* Only change the context if the function changes. This hook is called
1273 several times in the course of compiling a function, and we don't want
1274 to slow things down too much or call target_reinit when it isn't safe. */
1275 if (fndecl
== rx_previous_fndecl
)
1278 prev_was_fast_interrupt
1279 = rx_previous_fndecl
1280 ? is_fast_interrupt_func (rx_previous_fndecl
) : false;
1282 current_is_fast_interrupt
1283 = fndecl
? is_fast_interrupt_func (fndecl
) : false;
1285 if (prev_was_fast_interrupt
!= current_is_fast_interrupt
)
1287 use_fixed_regs
= current_is_fast_interrupt
;
1291 rx_previous_fndecl
= fndecl
;
1294 /* Typical stack layout should looks like this after the function's prologue:
1299 | | arguments saved | Increasing
1300 | | on the stack | addresses
1301 PARENT arg pointer -> | | /
1302 -------------------------- ---- -------------------
1303 CHILD |ret | return address
1313 frame pointer -> | | /
1316 | | outgoing | Decreasing
1317 | | arguments | addresses
1318 current stack pointer -> | | / |
1319 -------------------------- ---- ------------------ V
1323 bit_count (unsigned int x
)
1325 const unsigned int m1
= 0x55555555;
1326 const unsigned int m2
= 0x33333333;
1327 const unsigned int m4
= 0x0f0f0f0f;
1330 x
= (x
& m2
) + ((x
>> 2) & m2
);
1331 x
= (x
+ (x
>> 4)) & m4
;
1334 return (x
+ (x
>> 16)) & 0x3f;
1337 #define MUST_SAVE_ACC_REGISTER \
1338 (TARGET_SAVE_ACC_REGISTER \
1339 && (is_interrupt_func (NULL_TREE) \
1340 || is_fast_interrupt_func (NULL_TREE)))
1342 /* Returns either the lowest numbered and highest numbered registers that
1343 occupy the call-saved area of the stack frame, if the registers are
1344 stored as a contiguous block, or else a bitmask of the individual
1345 registers if they are stored piecemeal.
1347 Also computes the size of the frame and the size of the outgoing
1348 arguments block (in bytes). */
1351 rx_get_stack_layout (unsigned int * lowest
,
1352 unsigned int * highest
,
1353 unsigned int * register_mask
,
1354 unsigned int * frame_size
,
1355 unsigned int * stack_size
)
1360 unsigned int fixed_reg
= 0;
1361 unsigned int save_mask
;
1362 unsigned int pushed_mask
;
1363 unsigned int unneeded_pushes
;
1365 if (is_naked_func (NULL_TREE
))
1367 /* Naked functions do not create their own stack frame.
1368 Instead the programmer must do that for us. */
1371 * register_mask
= 0;
1377 for (save_mask
= high
= low
= 0, reg
= 1; reg
< CC_REGNUM
; reg
++)
1379 if ((df_regs_ever_live_p (reg
)
1380 /* Always save all call clobbered registers inside non-leaf
1381 interrupt handlers, even if they are not live - they may
1382 be used in (non-interrupt aware) routines called from this one. */
1383 || (call_used_regs
[reg
]
1384 && is_interrupt_func (NULL_TREE
)
1385 && ! crtl
->is_leaf
))
1386 && (! call_used_regs
[reg
]
1387 /* Even call clobbered registered must
1388 be pushed inside interrupt handlers. */
1389 || is_interrupt_func (NULL_TREE
)
1390 /* Likewise for fast interrupt handlers, except registers r10 -
1391 r13. These are normally call-saved, but may have been set
1392 to call-used by rx_conditional_register_usage. If so then
1393 they can be used in the fast interrupt handler without
1394 saving them on the stack. */
1395 || (is_fast_interrupt_func (NULL_TREE
)
1396 && ! IN_RANGE (reg
, 10, 13))))
1402 save_mask
|= 1 << reg
;
1405 /* Remember if we see a fixed register
1406 after having found the low register. */
1407 if (low
!= 0 && fixed_reg
== 0 && fixed_regs
[reg
])
1411 /* If we have to save the accumulator register, make sure
1412 that at least two registers are pushed into the frame. */
1413 if (MUST_SAVE_ACC_REGISTER
1414 && bit_count (save_mask
) < 2)
1416 save_mask
|= (1 << 13) | (1 << 14);
1419 if (high
== 0 || low
== high
)
1423 /* Decide if it would be faster fill in the call-saved area of the stack
1424 frame using multiple PUSH instructions instead of a single PUSHM
1427 SAVE_MASK is a bitmask of the registers that must be stored in the
1428 call-save area. PUSHED_MASK is a bitmask of the registers that would
1429 be pushed into the area if we used a PUSHM instruction. UNNEEDED_PUSHES
1430 is a bitmask of those registers in pushed_mask that are not in
1433 We use a simple heuristic that says that it is better to use
1434 multiple PUSH instructions if the number of unnecessary pushes is
1435 greater than the number of necessary pushes.
1437 We also use multiple PUSH instructions if there are any fixed registers
1438 between LOW and HIGH. The only way that this can happen is if the user
1439 has specified --fixed-<reg-name> on the command line and in such
1440 circumstances we do not want to touch the fixed registers at all.
1442 FIXME: Is it worth improving this heuristic ? */
1443 pushed_mask
= (-1 << low
) & ~(-1 << (high
+ 1));
1444 unneeded_pushes
= (pushed_mask
& (~ save_mask
)) & pushed_mask
;
1446 if ((fixed_reg
&& fixed_reg
<= high
)
1447 || (optimize_function_for_speed_p (cfun
)
1448 && bit_count (save_mask
) < bit_count (unneeded_pushes
)))
1450 /* Use multiple pushes. */
1453 * register_mask
= save_mask
;
1457 /* Use one push multiple instruction. */
1460 * register_mask
= 0;
1463 * frame_size
= rx_round_up
1464 (get_frame_size (), STACK_BOUNDARY
/ BITS_PER_UNIT
);
1466 if (crtl
->args
.size
> 0)
1467 * frame_size
+= rx_round_up
1468 (crtl
->args
.size
, STACK_BOUNDARY
/ BITS_PER_UNIT
);
1470 * stack_size
= rx_round_up
1471 (crtl
->outgoing_args_size
, STACK_BOUNDARY
/ BITS_PER_UNIT
);
1474 /* Generate a PUSHM instruction that matches the given operands. */
1477 rx_emit_stack_pushm (rtx
* operands
)
1479 HOST_WIDE_INT last_reg
;
1482 gcc_assert (CONST_INT_P (operands
[0]));
1483 last_reg
= (INTVAL (operands
[0]) / UNITS_PER_WORD
) - 1;
1485 gcc_assert (GET_CODE (operands
[1]) == PARALLEL
);
1486 first_push
= XVECEXP (operands
[1], 0, 1);
1487 gcc_assert (SET_P (first_push
));
1488 first_push
= SET_SRC (first_push
);
1489 gcc_assert (REG_P (first_push
));
1491 asm_fprintf (asm_out_file
, "\tpushm\t%s-%s\n",
1492 reg_names
[REGNO (first_push
) - last_reg
],
1493 reg_names
[REGNO (first_push
)]);
1496 /* Generate a PARALLEL that will pass the rx_store_multiple_vector predicate. */
1499 gen_rx_store_vector (unsigned int low
, unsigned int high
)
1502 unsigned int count
= (high
- low
) + 2;
1505 vector
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
1507 XVECEXP (vector
, 0, 0) =
1508 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
1509 gen_rtx_MINUS (SImode
, stack_pointer_rtx
,
1510 GEN_INT ((count
- 1) * UNITS_PER_WORD
)));
1512 for (i
= 0; i
< count
- 1; i
++)
1513 XVECEXP (vector
, 0, i
+ 1) =
1514 gen_rtx_SET (VOIDmode
,
1515 gen_rtx_MEM (SImode
,
1516 gen_rtx_MINUS (SImode
, stack_pointer_rtx
,
1517 GEN_INT ((i
+ 1) * UNITS_PER_WORD
))),
1518 gen_rtx_REG (SImode
, high
- i
));
1522 /* Mark INSN as being frame related. If it is a PARALLEL
1523 then mark each element as being frame related as well. */
1526 mark_frame_related (rtx insn
)
1528 RTX_FRAME_RELATED_P (insn
) = 1;
1529 insn
= PATTERN (insn
);
1531 if (GET_CODE (insn
) == PARALLEL
)
1535 for (i
= 0; i
< (unsigned) XVECLEN (insn
, 0); i
++)
1536 RTX_FRAME_RELATED_P (XVECEXP (insn
, 0, i
)) = 1;
1541 ok_for_max_constant (HOST_WIDE_INT val
)
1543 if (rx_max_constant_size
== 0 || rx_max_constant_size
== 4)
1544 /* If there is no constraint on the size of constants
1545 used as operands, then any value is legitimate. */
1548 /* rx_max_constant_size specifies the maximum number
1549 of bytes that can be used to hold a signed value. */
1550 return IN_RANGE (val
, (-1 << (rx_max_constant_size
* 8)),
1551 ( 1 << (rx_max_constant_size
* 8)));
1554 /* Generate an ADD of SRC plus VAL into DEST.
1555 Handles the case where VAL is too big for max_constant_value.
1556 Sets FRAME_RELATED_P on the insn if IS_FRAME_RELATED is true. */
1559 gen_safe_add (rtx dest
, rtx src
, rtx val
, bool is_frame_related
)
1563 if (val
== NULL_RTX
|| INTVAL (val
) == 0)
1565 gcc_assert (dest
!= src
);
1567 insn
= emit_move_insn (dest
, src
);
1569 else if (ok_for_max_constant (INTVAL (val
)))
1570 insn
= emit_insn (gen_addsi3 (dest
, src
, val
));
1573 /* Wrap VAL in an UNSPEC so that rx_is_legitimate_constant
1574 will not reject it. */
1575 val
= gen_rtx_CONST (SImode
, gen_rtx_UNSPEC (SImode
, gen_rtvec (1, val
), UNSPEC_CONST
));
1576 insn
= emit_insn (gen_addsi3 (dest
, src
, val
));
1578 if (is_frame_related
)
1579 /* We have to provide our own frame related note here
1580 as the dwarf2out code cannot be expected to grok
1582 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
1583 gen_rtx_SET (SImode
, dest
,
1584 gen_rtx_PLUS (SImode
, src
, val
)));
1588 if (is_frame_related
)
1589 RTX_FRAME_RELATED_P (insn
) = 1;
1594 rx_expand_prologue (void)
1596 unsigned int stack_size
;
1597 unsigned int frame_size
;
1604 /* Naked functions use their own, programmer provided prologues. */
1605 if (is_naked_func (NULL_TREE
))
1608 rx_get_stack_layout (& low
, & high
, & mask
, & frame_size
, & stack_size
);
1610 if (flag_stack_usage_info
)
1611 current_function_static_stack_size
= frame_size
+ stack_size
;
1613 /* If we use any of the callee-saved registers, save them now. */
1616 /* Push registers in reverse order. */
1617 for (reg
= CC_REGNUM
; reg
--;)
1618 if (mask
& (1 << reg
))
1620 insn
= emit_insn (gen_stack_push (gen_rtx_REG (SImode
, reg
)));
1621 mark_frame_related (insn
);
1627 insn
= emit_insn (gen_stack_push (gen_rtx_REG (SImode
, low
)));
1629 insn
= emit_insn (gen_stack_pushm (GEN_INT (((high
- low
) + 1)
1631 gen_rx_store_vector (low
, high
)));
1632 mark_frame_related (insn
);
1635 if (MUST_SAVE_ACC_REGISTER
)
1637 unsigned int acc_high
, acc_low
;
1639 /* Interrupt handlers have to preserve the accumulator
1640 register if so requested by the user. Use the first
1641 two pushed registers as intermediaries. */
1644 acc_low
= acc_high
= 0;
1646 for (reg
= 1; reg
< CC_REGNUM
; reg
++)
1647 if (mask
& (1 << reg
))
1658 /* We have assumed that there are at least two registers pushed... */
1659 gcc_assert (acc_high
!= 0);
1661 /* Note - the bottom 16 bits of the accumulator are inaccessible.
1662 We just assume that they are zero. */
1663 emit_insn (gen_mvfacmi (gen_rtx_REG (SImode
, acc_low
)));
1664 emit_insn (gen_mvfachi (gen_rtx_REG (SImode
, acc_high
)));
1665 emit_insn (gen_stack_push (gen_rtx_REG (SImode
, acc_low
)));
1666 emit_insn (gen_stack_push (gen_rtx_REG (SImode
, acc_high
)));
1673 /* We have assumed that there are at least two registers pushed... */
1674 gcc_assert (acc_high
<= high
);
1676 emit_insn (gen_mvfacmi (gen_rtx_REG (SImode
, acc_low
)));
1677 emit_insn (gen_mvfachi (gen_rtx_REG (SImode
, acc_high
)));
1678 emit_insn (gen_stack_pushm (GEN_INT (2 * UNITS_PER_WORD
),
1679 gen_rx_store_vector (acc_low
, acc_high
)));
1683 /* If needed, set up the frame pointer. */
1684 if (frame_pointer_needed
)
1685 gen_safe_add (frame_pointer_rtx
, stack_pointer_rtx
,
1686 GEN_INT (- (HOST_WIDE_INT
) frame_size
), true);
1688 /* Allocate space for the outgoing args.
1689 If the stack frame has not already been set up then handle this as well. */
1694 if (frame_pointer_needed
)
1695 gen_safe_add (stack_pointer_rtx
, frame_pointer_rtx
,
1696 GEN_INT (- (HOST_WIDE_INT
) stack_size
), true);
1698 gen_safe_add (stack_pointer_rtx
, stack_pointer_rtx
,
1699 GEN_INT (- (HOST_WIDE_INT
) (frame_size
+ stack_size
)),
1703 gen_safe_add (stack_pointer_rtx
, stack_pointer_rtx
,
1704 GEN_INT (- (HOST_WIDE_INT
) stack_size
), true);
1706 else if (frame_size
)
1708 if (! frame_pointer_needed
)
1709 gen_safe_add (stack_pointer_rtx
, stack_pointer_rtx
,
1710 GEN_INT (- (HOST_WIDE_INT
) frame_size
), true);
1712 gen_safe_add (stack_pointer_rtx
, frame_pointer_rtx
, NULL_RTX
,
1718 rx_output_function_prologue (FILE * file
,
1719 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED
)
1721 if (is_fast_interrupt_func (NULL_TREE
))
1722 asm_fprintf (file
, "\t; Note: Fast Interrupt Handler\n");
1724 if (is_interrupt_func (NULL_TREE
))
1725 asm_fprintf (file
, "\t; Note: Interrupt Handler\n");
1727 if (is_naked_func (NULL_TREE
))
1728 asm_fprintf (file
, "\t; Note: Naked Function\n");
1730 if (cfun
->static_chain_decl
!= NULL
)
1731 asm_fprintf (file
, "\t; Note: Nested function declared "
1732 "inside another function.\n");
1734 if (crtl
->calls_eh_return
)
1735 asm_fprintf (file
, "\t; Note: Calls __builtin_eh_return.\n");
1738 /* Generate a POPM or RTSD instruction that matches the given operands. */
1741 rx_emit_stack_popm (rtx
* operands
, bool is_popm
)
1743 HOST_WIDE_INT stack_adjust
;
1744 HOST_WIDE_INT last_reg
;
1747 gcc_assert (CONST_INT_P (operands
[0]));
1748 stack_adjust
= INTVAL (operands
[0]);
1750 gcc_assert (GET_CODE (operands
[1]) == PARALLEL
);
1751 last_reg
= XVECLEN (operands
[1], 0) - (is_popm
? 2 : 3);
1753 first_push
= XVECEXP (operands
[1], 0, 1);
1754 gcc_assert (SET_P (first_push
));
1755 first_push
= SET_DEST (first_push
);
1756 gcc_assert (REG_P (first_push
));
1759 asm_fprintf (asm_out_file
, "\tpopm\t%s-%s\n",
1760 reg_names
[REGNO (first_push
)],
1761 reg_names
[REGNO (first_push
) + last_reg
]);
1763 asm_fprintf (asm_out_file
, "\trtsd\t#%d, %s-%s\n",
1765 reg_names
[REGNO (first_push
)],
1766 reg_names
[REGNO (first_push
) + last_reg
]);
1769 /* Generate a PARALLEL which will satisfy the rx_rtsd_vector predicate. */
1772 gen_rx_rtsd_vector (unsigned int adjust
, unsigned int low
, unsigned int high
)
1775 unsigned int bias
= 3;
1776 unsigned int count
= (high
- low
) + bias
;
1779 vector
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
1781 XVECEXP (vector
, 0, 0) =
1782 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
1783 plus_constant (Pmode
, stack_pointer_rtx
, adjust
));
1785 for (i
= 0; i
< count
- 2; i
++)
1786 XVECEXP (vector
, 0, i
+ 1) =
1787 gen_rtx_SET (VOIDmode
,
1788 gen_rtx_REG (SImode
, low
+ i
),
1789 gen_rtx_MEM (SImode
,
1790 i
== 0 ? stack_pointer_rtx
1791 : plus_constant (Pmode
, stack_pointer_rtx
,
1792 i
* UNITS_PER_WORD
)));
1794 XVECEXP (vector
, 0, count
- 1) = ret_rtx
;
1799 /* Generate a PARALLEL which will satisfy the rx_load_multiple_vector predicate. */
1802 gen_rx_popm_vector (unsigned int low
, unsigned int high
)
1805 unsigned int count
= (high
- low
) + 2;
1808 vector
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
1810 XVECEXP (vector
, 0, 0) =
1811 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
1812 plus_constant (Pmode
, stack_pointer_rtx
,
1813 (count
- 1) * UNITS_PER_WORD
));
1815 for (i
= 0; i
< count
- 1; i
++)
1816 XVECEXP (vector
, 0, i
+ 1) =
1817 gen_rtx_SET (VOIDmode
,
1818 gen_rtx_REG (SImode
, low
+ i
),
1819 gen_rtx_MEM (SImode
,
1820 i
== 0 ? stack_pointer_rtx
1821 : plus_constant (Pmode
, stack_pointer_rtx
,
1822 i
* UNITS_PER_WORD
)));
1827 /* Returns true if a simple return insn can be used. */
1830 rx_can_use_simple_return (void)
1834 unsigned int frame_size
;
1835 unsigned int stack_size
;
1836 unsigned int register_mask
;
1838 if (is_naked_func (NULL_TREE
)
1839 || is_fast_interrupt_func (NULL_TREE
)
1840 || is_interrupt_func (NULL_TREE
))
1843 rx_get_stack_layout (& low
, & high
, & register_mask
,
1844 & frame_size
, & stack_size
);
1846 return (register_mask
== 0
1847 && (frame_size
+ stack_size
) == 0
1852 rx_expand_epilogue (bool is_sibcall
)
1856 unsigned int frame_size
;
1857 unsigned int stack_size
;
1858 unsigned int register_mask
;
1859 unsigned int regs_size
;
1861 unsigned HOST_WIDE_INT total_size
;
1863 /* FIXME: We do not support indirect sibcalls at the moment becaause we
1864 cannot guarantee that the register holding the function address is a
1865 call-used register. If it is a call-saved register then the stack
1866 pop instructions generated in the epilogue will corrupt the address
1869 Creating a new call-used-only register class works but then the
1870 reload pass gets stuck because it cannot always find a call-used
1871 register for spilling sibcalls.
1873 The other possible solution is for this pass to scan forward for the
1874 sibcall instruction (if it has been generated) and work out if it
1875 is an indirect sibcall using a call-saved register. If it is then
1876 the address can copied into a call-used register in this epilogue
1877 code and the sibcall instruction modified to use that register. */
1879 if (is_naked_func (NULL_TREE
))
1881 gcc_assert (! is_sibcall
);
1883 /* Naked functions use their own, programmer provided epilogues.
1884 But, in order to keep gcc happy we have to generate some kind of
1886 emit_jump_insn (gen_naked_return ());
1890 rx_get_stack_layout (& low
, & high
, & register_mask
,
1891 & frame_size
, & stack_size
);
1893 total_size
= frame_size
+ stack_size
;
1894 regs_size
= ((high
- low
) + 1) * UNITS_PER_WORD
;
1896 /* See if we are unable to use the special stack frame deconstruct and
1897 return instructions. In most cases we can use them, but the exceptions
1900 - Sibling calling functions deconstruct the frame but do not return to
1901 their caller. Instead they branch to their sibling and allow their
1902 return instruction to return to this function's parent.
1904 - Fast and normal interrupt handling functions have to use special
1905 return instructions.
1907 - Functions where we have pushed a fragmented set of registers into the
1908 call-save area must have the same set of registers popped. */
1910 || is_fast_interrupt_func (NULL_TREE
)
1911 || is_interrupt_func (NULL_TREE
)
1914 /* Cannot use the special instructions - deconstruct by hand. */
1916 gen_safe_add (stack_pointer_rtx
, stack_pointer_rtx
,
1917 GEN_INT (total_size
), false);
1919 if (MUST_SAVE_ACC_REGISTER
)
1921 unsigned int acc_low
, acc_high
;
1923 /* Reverse the saving of the accumulator register onto the stack.
1924 Note we must adjust the saved "low" accumulator value as it
1925 is really the middle 32-bits of the accumulator. */
1928 acc_low
= acc_high
= 0;
1930 for (reg
= 1; reg
< CC_REGNUM
; reg
++)
1931 if (register_mask
& (1 << reg
))
1941 emit_insn (gen_stack_pop (gen_rtx_REG (SImode
, acc_high
)));
1942 emit_insn (gen_stack_pop (gen_rtx_REG (SImode
, acc_low
)));
1948 emit_insn (gen_stack_popm (GEN_INT (2 * UNITS_PER_WORD
),
1949 gen_rx_popm_vector (acc_low
, acc_high
)));
1952 emit_insn (gen_ashlsi3 (gen_rtx_REG (SImode
, acc_low
),
1953 gen_rtx_REG (SImode
, acc_low
),
1955 emit_insn (gen_mvtaclo (gen_rtx_REG (SImode
, acc_low
)));
1956 emit_insn (gen_mvtachi (gen_rtx_REG (SImode
, acc_high
)));
1961 for (reg
= 0; reg
< CC_REGNUM
; reg
++)
1962 if (register_mask
& (1 << reg
))
1963 emit_insn (gen_stack_pop (gen_rtx_REG (SImode
, reg
)));
1968 emit_insn (gen_stack_pop (gen_rtx_REG (SImode
, low
)));
1970 emit_insn (gen_stack_popm (GEN_INT (regs_size
),
1971 gen_rx_popm_vector (low
, high
)));
1974 if (is_fast_interrupt_func (NULL_TREE
))
1976 gcc_assert (! is_sibcall
);
1977 emit_jump_insn (gen_fast_interrupt_return ());
1979 else if (is_interrupt_func (NULL_TREE
))
1981 gcc_assert (! is_sibcall
);
1982 emit_jump_insn (gen_exception_return ());
1984 else if (! is_sibcall
)
1985 emit_jump_insn (gen_simple_return ());
1990 /* If we allocated space on the stack, free it now. */
1993 unsigned HOST_WIDE_INT rtsd_size
;
1995 /* See if we can use the RTSD instruction. */
1996 rtsd_size
= total_size
+ regs_size
;
1997 if (rtsd_size
< 1024 && (rtsd_size
% 4) == 0)
2000 emit_jump_insn (gen_pop_and_return
2001 (GEN_INT (rtsd_size
),
2002 gen_rx_rtsd_vector (rtsd_size
, low
, high
)));
2004 emit_jump_insn (gen_deallocate_and_return (GEN_INT (total_size
)));
2009 gen_safe_add (stack_pointer_rtx
, stack_pointer_rtx
,
2010 GEN_INT (total_size
), false);
2014 emit_jump_insn (gen_pop_and_return (GEN_INT (regs_size
),
2015 gen_rx_rtsd_vector (regs_size
,
2018 emit_jump_insn (gen_simple_return ());
2022 /* Compute the offset (in words) between FROM (arg pointer
2023 or frame pointer) and TO (frame pointer or stack pointer).
2024 See ASCII art comment at the start of rx_expand_prologue
2025 for more information. */
2028 rx_initial_elimination_offset (int from
, int to
)
2032 unsigned int frame_size
;
2033 unsigned int stack_size
;
2036 rx_get_stack_layout (& low
, & high
, & mask
, & frame_size
, & stack_size
);
2038 if (from
== ARG_POINTER_REGNUM
)
2040 /* Extend the computed size of the stack frame to
2041 include the registers pushed in the prologue. */
2043 frame_size
+= ((high
- low
) + 1) * UNITS_PER_WORD
;
2045 frame_size
+= bit_count (mask
) * UNITS_PER_WORD
;
2047 /* Remember to include the return address. */
2048 frame_size
+= 1 * UNITS_PER_WORD
;
2050 if (to
== FRAME_POINTER_REGNUM
)
2053 gcc_assert (to
== STACK_POINTER_REGNUM
);
2054 return frame_size
+ stack_size
;
2057 gcc_assert (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
);
2061 /* Decide if a variable should go into one of the small data sections. */
2064 rx_in_small_data (const_tree decl
)
2069 if (rx_small_data_limit
== 0)
2072 if (TREE_CODE (decl
) != VAR_DECL
)
2075 /* We do not put read-only variables into a small data area because
2076 they would be placed with the other read-only sections, far away
2077 from the read-write data sections, and we only have one small
2079 Similarly commons are placed in the .bss section which might be
2080 far away (and out of alignment with respect to) the .data section. */
2081 if (TREE_READONLY (decl
) || DECL_COMMON (decl
))
2084 section
= DECL_SECTION_NAME (decl
);
2087 const char * const name
= TREE_STRING_POINTER (section
);
2089 return (strcmp (name
, "D_2") == 0) || (strcmp (name
, "B_2") == 0);
2092 size
= int_size_in_bytes (TREE_TYPE (decl
));
2094 return (size
> 0) && (size
<= rx_small_data_limit
);
2097 /* Return a section for X.
2098 The only special thing we do here is to honor small data. */
2101 rx_select_rtx_section (enum machine_mode mode
,
2103 unsigned HOST_WIDE_INT align
)
2105 if (rx_small_data_limit
> 0
2106 && GET_MODE_SIZE (mode
) <= rx_small_data_limit
2107 && align
<= (unsigned HOST_WIDE_INT
) rx_small_data_limit
* BITS_PER_UNIT
)
2108 return sdata_section
;
2110 return default_elf_select_rtx_section (mode
, x
, align
);
2114 rx_select_section (tree decl
,
2116 unsigned HOST_WIDE_INT align
)
2118 if (rx_small_data_limit
> 0)
2120 switch (categorize_decl_for_section (decl
, reloc
))
2122 case SECCAT_SDATA
: return sdata_section
;
2123 case SECCAT_SBSS
: return sbss_section
;
2124 case SECCAT_SRODATA
:
2125 /* Fall through. We do not put small, read only
2126 data into the C_2 section because we are not
2127 using the C_2 section. We do not use the C_2
2128 section because it is located with the other
2129 read-only data sections, far away from the read-write
2130 data sections and we only have one small data
2137 /* If we are supporting the Renesas assembler
2138 we cannot use mergeable sections. */
2139 if (TARGET_AS100_SYNTAX
)
2140 switch (categorize_decl_for_section (decl
, reloc
))
2142 case SECCAT_RODATA_MERGE_CONST
:
2143 case SECCAT_RODATA_MERGE_STR_INIT
:
2144 case SECCAT_RODATA_MERGE_STR
:
2145 return readonly_data_section
;
2151 return default_elf_select_section (decl
, reloc
, align
);
2179 static GTY(()) tree rx_builtins
[(int) RX_BUILTIN_max
];
2182 rx_init_builtins (void)
2184 #define ADD_RX_BUILTIN1(UC_NAME, LC_NAME, RET_TYPE, ARG_TYPE) \
2185 rx_builtins[RX_BUILTIN_##UC_NAME] = \
2186 add_builtin_function ("__builtin_rx_" LC_NAME, \
2187 build_function_type_list (RET_TYPE##_type_node, \
2188 ARG_TYPE##_type_node, \
2190 RX_BUILTIN_##UC_NAME, \
2191 BUILT_IN_MD, NULL, NULL_TREE)
2193 #define ADD_RX_BUILTIN2(UC_NAME, LC_NAME, RET_TYPE, ARG_TYPE1, ARG_TYPE2) \
2194 rx_builtins[RX_BUILTIN_##UC_NAME] = \
2195 add_builtin_function ("__builtin_rx_" LC_NAME, \
2196 build_function_type_list (RET_TYPE##_type_node, \
2197 ARG_TYPE1##_type_node,\
2198 ARG_TYPE2##_type_node,\
2200 RX_BUILTIN_##UC_NAME, \
2201 BUILT_IN_MD, NULL, NULL_TREE)
2203 #define ADD_RX_BUILTIN3(UC_NAME,LC_NAME,RET_TYPE,ARG_TYPE1,ARG_TYPE2,ARG_TYPE3) \
2204 rx_builtins[RX_BUILTIN_##UC_NAME] = \
2205 add_builtin_function ("__builtin_rx_" LC_NAME, \
2206 build_function_type_list (RET_TYPE##_type_node, \
2207 ARG_TYPE1##_type_node,\
2208 ARG_TYPE2##_type_node,\
2209 ARG_TYPE3##_type_node,\
2211 RX_BUILTIN_##UC_NAME, \
2212 BUILT_IN_MD, NULL, NULL_TREE)
2214 ADD_RX_BUILTIN1 (BRK
, "brk", void, void);
2215 ADD_RX_BUILTIN1 (CLRPSW
, "clrpsw", void, integer
);
2216 ADD_RX_BUILTIN1 (SETPSW
, "setpsw", void, integer
);
2217 ADD_RX_BUILTIN1 (INT
, "int", void, integer
);
2218 ADD_RX_BUILTIN2 (MACHI
, "machi", void, intSI
, intSI
);
2219 ADD_RX_BUILTIN2 (MACLO
, "maclo", void, intSI
, intSI
);
2220 ADD_RX_BUILTIN2 (MULHI
, "mulhi", void, intSI
, intSI
);
2221 ADD_RX_BUILTIN2 (MULLO
, "mullo", void, intSI
, intSI
);
2222 ADD_RX_BUILTIN1 (MVFACHI
, "mvfachi", intSI
, void);
2223 ADD_RX_BUILTIN1 (MVFACMI
, "mvfacmi", intSI
, void);
2224 ADD_RX_BUILTIN1 (MVTACHI
, "mvtachi", void, intSI
);
2225 ADD_RX_BUILTIN1 (MVTACLO
, "mvtaclo", void, intSI
);
2226 ADD_RX_BUILTIN1 (RMPA
, "rmpa", void, void);
2227 ADD_RX_BUILTIN1 (MVFC
, "mvfc", intSI
, integer
);
2228 ADD_RX_BUILTIN2 (MVTC
, "mvtc", void, integer
, integer
);
2229 ADD_RX_BUILTIN1 (MVTIPL
, "mvtipl", void, integer
);
2230 ADD_RX_BUILTIN1 (RACW
, "racw", void, integer
);
2231 ADD_RX_BUILTIN1 (ROUND
, "round", intSI
, float);
2232 ADD_RX_BUILTIN1 (REVW
, "revw", intSI
, intSI
);
2233 ADD_RX_BUILTIN1 (WAIT
, "wait", void, void);
2236 /* Return the RX builtin for CODE. */
2239 rx_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
2241 if (code
>= RX_BUILTIN_max
)
2242 return error_mark_node
;
2244 return rx_builtins
[code
];
2248 rx_expand_void_builtin_1_arg (rtx arg
, rtx (* gen_func
)(rtx
), bool reg
)
2250 if (reg
&& ! REG_P (arg
))
2251 arg
= force_reg (SImode
, arg
);
2253 emit_insn (gen_func (arg
));
2259 rx_expand_builtin_mvtc (tree exp
)
2261 rtx arg1
= expand_normal (CALL_EXPR_ARG (exp
, 0));
2262 rtx arg2
= expand_normal (CALL_EXPR_ARG (exp
, 1));
2264 if (! CONST_INT_P (arg1
))
2268 arg2
= force_reg (SImode
, arg2
);
2270 emit_insn (gen_mvtc (arg1
, arg2
));
2276 rx_expand_builtin_mvfc (tree t_arg
, rtx target
)
2278 rtx arg
= expand_normal (t_arg
);
2280 if (! CONST_INT_P (arg
))
2283 if (target
== NULL_RTX
)
2286 if (! REG_P (target
))
2287 target
= force_reg (SImode
, target
);
2289 emit_insn (gen_mvfc (target
, arg
));
2295 rx_expand_builtin_mvtipl (rtx arg
)
2297 /* The RX610 does not support the MVTIPL instruction. */
2298 if (rx_cpu_type
== RX610
)
2301 if (! CONST_INT_P (arg
) || ! IN_RANGE (INTVAL (arg
), 0, (1 << 4) - 1))
2304 emit_insn (gen_mvtipl (arg
));
2310 rx_expand_builtin_mac (tree exp
, rtx (* gen_func
)(rtx
, rtx
))
2312 rtx arg1
= expand_normal (CALL_EXPR_ARG (exp
, 0));
2313 rtx arg2
= expand_normal (CALL_EXPR_ARG (exp
, 1));
2316 arg1
= force_reg (SImode
, arg1
);
2319 arg2
= force_reg (SImode
, arg2
);
2321 emit_insn (gen_func (arg1
, arg2
));
2327 rx_expand_int_builtin_1_arg (rtx arg
,
2329 rtx (* gen_func
)(rtx
, rtx
),
2333 if (!mem_ok
|| ! MEM_P (arg
))
2334 arg
= force_reg (SImode
, arg
);
2336 if (target
== NULL_RTX
|| ! REG_P (target
))
2337 target
= gen_reg_rtx (SImode
);
2339 emit_insn (gen_func (target
, arg
));
2345 rx_expand_int_builtin_0_arg (rtx target
, rtx (* gen_func
)(rtx
))
2347 if (target
== NULL_RTX
|| ! REG_P (target
))
2348 target
= gen_reg_rtx (SImode
);
2350 emit_insn (gen_func (target
));
2356 rx_expand_builtin_round (rtx arg
, rtx target
)
2358 if ((! REG_P (arg
) && ! MEM_P (arg
))
2359 || GET_MODE (arg
) != SFmode
)
2360 arg
= force_reg (SFmode
, arg
);
2362 if (target
== NULL_RTX
|| ! REG_P (target
))
2363 target
= gen_reg_rtx (SImode
);
2365 emit_insn (gen_lrintsf2 (target
, arg
));
2371 valid_psw_flag (rtx op
, const char *which
)
2373 static int mvtc_inform_done
= 0;
2375 if (GET_CODE (op
) == CONST_INT
)
2376 switch (INTVAL (op
))
2378 case 0: case 'c': case 'C':
2379 case 1: case 'z': case 'Z':
2380 case 2: case 's': case 'S':
2381 case 3: case 'o': case 'O':
2382 case 8: case 'i': case 'I':
2383 case 9: case 'u': case 'U':
2387 error ("__builtin_rx_%s takes 'C', 'Z', 'S', 'O', 'I', or 'U'", which
);
2388 if (!mvtc_inform_done
)
2389 error ("use __builtin_rx_mvtc (0, ... ) to write arbitrary values to PSW");
2390 mvtc_inform_done
= 1;
2396 rx_expand_builtin (tree exp
,
2398 rtx subtarget ATTRIBUTE_UNUSED
,
2399 enum machine_mode mode ATTRIBUTE_UNUSED
,
2400 int ignore ATTRIBUTE_UNUSED
)
2402 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
2403 tree arg
= call_expr_nargs (exp
) >= 1 ? CALL_EXPR_ARG (exp
, 0) : NULL_TREE
;
2404 rtx op
= arg
? expand_normal (arg
) : NULL_RTX
;
2405 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
2409 case RX_BUILTIN_BRK
: emit_insn (gen_brk ()); return NULL_RTX
;
2410 case RX_BUILTIN_CLRPSW
:
2411 if (!valid_psw_flag (op
, "clrpsw"))
2413 return rx_expand_void_builtin_1_arg (op
, gen_clrpsw
, false);
2414 case RX_BUILTIN_SETPSW
:
2415 if (!valid_psw_flag (op
, "setpsw"))
2417 return rx_expand_void_builtin_1_arg (op
, gen_setpsw
, false);
2418 case RX_BUILTIN_INT
: return rx_expand_void_builtin_1_arg
2419 (op
, gen_int
, false);
2420 case RX_BUILTIN_MACHI
: return rx_expand_builtin_mac (exp
, gen_machi
);
2421 case RX_BUILTIN_MACLO
: return rx_expand_builtin_mac (exp
, gen_maclo
);
2422 case RX_BUILTIN_MULHI
: return rx_expand_builtin_mac (exp
, gen_mulhi
);
2423 case RX_BUILTIN_MULLO
: return rx_expand_builtin_mac (exp
, gen_mullo
);
2424 case RX_BUILTIN_MVFACHI
: return rx_expand_int_builtin_0_arg
2425 (target
, gen_mvfachi
);
2426 case RX_BUILTIN_MVFACMI
: return rx_expand_int_builtin_0_arg
2427 (target
, gen_mvfacmi
);
2428 case RX_BUILTIN_MVTACHI
: return rx_expand_void_builtin_1_arg
2429 (op
, gen_mvtachi
, true);
2430 case RX_BUILTIN_MVTACLO
: return rx_expand_void_builtin_1_arg
2431 (op
, gen_mvtaclo
, true);
2432 case RX_BUILTIN_RMPA
: emit_insn (gen_rmpa ()); return NULL_RTX
;
2433 case RX_BUILTIN_MVFC
: return rx_expand_builtin_mvfc (arg
, target
);
2434 case RX_BUILTIN_MVTC
: return rx_expand_builtin_mvtc (exp
);
2435 case RX_BUILTIN_MVTIPL
: return rx_expand_builtin_mvtipl (op
);
2436 case RX_BUILTIN_RACW
: return rx_expand_void_builtin_1_arg
2437 (op
, gen_racw
, false);
2438 case RX_BUILTIN_ROUND
: return rx_expand_builtin_round (op
, target
);
2439 case RX_BUILTIN_REVW
: return rx_expand_int_builtin_1_arg
2440 (op
, target
, gen_revw
, false);
2441 case RX_BUILTIN_WAIT
: emit_insn (gen_wait ()); return NULL_RTX
;
2444 internal_error ("bad builtin code");
2451 /* Place an element into a constructor or destructor section.
2452 Like default_ctor_section_asm_out_constructor in varasm.c
2453 except that it uses .init_array (or .fini_array) and it
2454 handles constructor priorities. */
2457 rx_elf_asm_cdtor (rtx symbol
, int priority
, bool is_ctor
)
2461 if (priority
!= DEFAULT_INIT_PRIORITY
)
2465 sprintf (buf
, "%s.%.5u",
2466 is_ctor
? ".init_array" : ".fini_array",
2468 s
= get_section (buf
, SECTION_WRITE
, NULL_TREE
);
2475 switch_to_section (s
);
2476 assemble_align (POINTER_SIZE
);
2477 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
2481 rx_elf_asm_constructor (rtx symbol
, int priority
)
2483 rx_elf_asm_cdtor (symbol
, priority
, /* is_ctor= */true);
2487 rx_elf_asm_destructor (rtx symbol
, int priority
)
2489 rx_elf_asm_cdtor (symbol
, priority
, /* is_ctor= */false);
2492 /* Check "fast_interrupt", "interrupt" and "naked" attributes. */
2495 rx_handle_func_attribute (tree
* node
,
2498 int flags ATTRIBUTE_UNUSED
,
2499 bool * no_add_attrs
)
2501 gcc_assert (DECL_P (* node
));
2502 gcc_assert (args
== NULL_TREE
);
2504 if (TREE_CODE (* node
) != FUNCTION_DECL
)
2506 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
2508 * no_add_attrs
= true;
2511 /* FIXME: We ought to check for conflicting attributes. */
2513 /* FIXME: We ought to check that the interrupt and exception
2514 handler attributes have been applied to void functions. */
2518 /* Table of RX specific attributes. */
2519 const struct attribute_spec rx_attribute_table
[] =
2521 /* Name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
2522 affects_type_identity. */
2523 { "fast_interrupt", 0, 0, true, false, false, rx_handle_func_attribute
,
2525 { "interrupt", 0, 0, true, false, false, rx_handle_func_attribute
,
2527 { "naked", 0, 0, true, false, false, rx_handle_func_attribute
,
2529 { NULL
, 0, 0, false, false, false, NULL
, false }
2532 /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE. */
2535 rx_override_options_after_change (void)
2537 static bool first_time
= TRUE
;
2541 /* If this is the first time through and the user has not disabled
2542 the use of RX FPU hardware then enable -ffinite-math-only,
2543 since the FPU instructions do not support NaNs and infinities. */
2545 flag_finite_math_only
= 1;
2551 /* Alert the user if they are changing the optimization options
2552 to use IEEE compliant floating point arithmetic with RX FPU insns. */
2554 && !flag_finite_math_only
)
2555 warning (0, "RX FPU instructions do not support NaNs and infinities");
2560 rx_option_override (void)
2563 cl_deferred_option
*opt
;
2564 VEC(cl_deferred_option
,heap
) *vec
2565 = (VEC(cl_deferred_option
,heap
) *) rx_deferred_options
;
2567 FOR_EACH_VEC_ELT (cl_deferred_option
, vec
, i
, opt
)
2569 switch (opt
->opt_index
)
2571 case OPT_mint_register_
:
2575 fixed_regs
[10] = call_used_regs
[10] = 1;
2578 fixed_regs
[11] = call_used_regs
[11] = 1;
2581 fixed_regs
[12] = call_used_regs
[12] = 1;
2584 fixed_regs
[13] = call_used_regs
[13] = 1;
2587 rx_num_interrupt_regs
= opt
->value
;
2590 rx_num_interrupt_regs
= 0;
2591 /* Error message already given because rx_handle_option
2602 /* This target defaults to strict volatile bitfields. */
2603 if (flag_strict_volatile_bitfields
< 0 && abi_version_at_least(2))
2604 flag_strict_volatile_bitfields
= 1;
2606 rx_override_options_after_change ();
2608 if (align_jumps
== 0 && ! optimize_size
)
2610 if (align_loops
== 0 && ! optimize_size
)
2612 if (align_labels
== 0 && ! optimize_size
)
2618 rx_allocate_stack_slots_for_args (void)
2620 /* Naked functions should not allocate stack slots for arguments. */
2621 return ! is_naked_func (NULL_TREE
);
2625 rx_func_attr_inlinable (const_tree decl
)
2627 return ! is_fast_interrupt_func (decl
)
2628 && ! is_interrupt_func (decl
)
2629 && ! is_naked_func (decl
);
2633 rx_warn_func_return (tree decl
)
2635 /* Naked functions are implemented entirely in assembly, including the
2636 return sequence, so suppress warnings about this. */
2637 return !is_naked_func (decl
);
2640 /* Return nonzero if it is ok to make a tail-call to DECL,
2641 a function_decl or NULL if this is an indirect call, using EXP */
2644 rx_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
2646 /* Do not allow indirect tailcalls. The
2647 sibcall patterns do not support them. */
2651 /* Never tailcall from inside interrupt handlers or naked functions. */
2652 if (is_fast_interrupt_func (NULL_TREE
)
2653 || is_interrupt_func (NULL_TREE
)
2654 || is_naked_func (NULL_TREE
))
2661 rx_file_start (void)
2663 if (! TARGET_AS100_SYNTAX
)
2664 default_file_start ();
2668 rx_is_ms_bitfield_layout (const_tree record_type ATTRIBUTE_UNUSED
)
2670 /* The packed attribute overrides the MS behaviour. */
2671 return ! TYPE_PACKED (record_type
);
2674 /* Returns true if X a legitimate constant for an immediate
2675 operand on the RX. X is already known to satisfy CONSTANT_P. */
2678 rx_is_legitimate_constant (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
2680 switch (GET_CODE (x
))
2685 if (GET_CODE (x
) == PLUS
)
2687 if (! CONST_INT_P (XEXP (x
, 1)))
2690 /* GCC would not pass us CONST_INT + CONST_INT so we
2691 know that we have {SYMBOL|LABEL} + CONST_INT. */
2693 gcc_assert (! CONST_INT_P (x
));
2696 switch (GET_CODE (x
))
2703 return XINT (x
, 1) == UNSPEC_CONST
|| XINT (x
, 1) == UNSPEC_PID_ADDR
;
2706 /* FIXME: Can this ever happen ? */
2715 return (rx_max_constant_size
== 0 || rx_max_constant_size
== 4);
2719 gcc_assert (CONST_INT_P (x
));
2723 return ok_for_max_constant (INTVAL (x
));
2727 rx_address_cost (rtx addr
, enum machine_mode mode ATTRIBUTE_UNUSED
,
2728 addr_space_t as ATTRIBUTE_UNUSED
, bool speed
)
2732 if (GET_CODE (addr
) != PLUS
)
2733 return COSTS_N_INSNS (1);
2738 if (REG_P (a
) && REG_P (b
))
2739 /* Try to discourage REG+REG addressing as it keeps two registers live. */
2740 return COSTS_N_INSNS (4);
2743 /* [REG+OFF] is just as fast as [REG]. */
2744 return COSTS_N_INSNS (1);
2747 && ((INTVAL (b
) > 128) || INTVAL (b
) < -127))
2748 /* Try to discourage REG + <large OFF> when optimizing for size. */
2749 return COSTS_N_INSNS (2);
2751 return COSTS_N_INSNS (1);
2755 rx_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
2757 /* We can always eliminate to the frame pointer.
2758 We can eliminate to the stack pointer unless a frame
2759 pointer is needed. */
2761 return to
== FRAME_POINTER_REGNUM
2762 || ( to
== STACK_POINTER_REGNUM
&& ! frame_pointer_needed
);
2767 rx_trampoline_template (FILE * file
)
2769 /* Output assembler code for a block containing the constant
2770 part of a trampoline, leaving space for the variable parts.
2772 On the RX, (where r8 is the static chain regnum) the trampoline
2775 mov #<static chain value>, r8
2776 mov #<function's address>, r9
2779 In big-endian-data-mode however instructions are read into the CPU
2780 4 bytes at a time. These bytes are then swapped around before being
2781 passed to the decoder. So...we must partition our trampoline into
2782 4 byte packets and swap these packets around so that the instruction
2783 reader will reverse the process. But, in order to avoid splitting
2784 the 32-bit constants across these packet boundaries, (making inserting
2785 them into the constructed trampoline very difficult) we have to pad the
2786 instruction sequence with NOP insns. ie:
2798 if (! TARGET_BIG_ENDIAN_DATA
)
2800 asm_fprintf (file
, "\tmov.L\t#0deadbeefH, r%d\n", STATIC_CHAIN_REGNUM
);
2801 asm_fprintf (file
, "\tmov.L\t#0deadbeefH, r%d\n", TRAMPOLINE_TEMP_REGNUM
);
2802 asm_fprintf (file
, "\tjmp\tr%d\n", TRAMPOLINE_TEMP_REGNUM
);
2806 char r8
= '0' + STATIC_CHAIN_REGNUM
;
2807 char r9
= '0' + TRAMPOLINE_TEMP_REGNUM
;
2809 if (TARGET_AS100_SYNTAX
)
2811 asm_fprintf (file
, "\t.BYTE 0%c2H, 0fbH, 003H, 003H\n", r8
);
2812 asm_fprintf (file
, "\t.BYTE 0deH, 0adH, 0beH, 0efH\n");
2813 asm_fprintf (file
, "\t.BYTE 0%c2H, 0fbH, 003H, 003H\n", r9
);
2814 asm_fprintf (file
, "\t.BYTE 0deH, 0adH, 0beH, 0efH\n");
2815 asm_fprintf (file
, "\t.BYTE 003H, 003H, 00%cH, 07fH\n", r9
);
2819 asm_fprintf (file
, "\t.byte 0x%c2, 0xfb, 0x03, 0x03\n", r8
);
2820 asm_fprintf (file
, "\t.byte 0xde, 0xad, 0xbe, 0xef\n");
2821 asm_fprintf (file
, "\t.byte 0x%c2, 0xfb, 0x03, 0x03\n", r9
);
2822 asm_fprintf (file
, "\t.byte 0xde, 0xad, 0xbe, 0xef\n");
2823 asm_fprintf (file
, "\t.byte 0x03, 0x03, 0x0%c, 0x7f\n", r9
);
2829 rx_trampoline_init (rtx tramp
, tree fndecl
, rtx chain
)
2831 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
2833 emit_block_move (tramp
, assemble_trampoline_template (),
2834 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
2836 if (TARGET_BIG_ENDIAN_DATA
)
2838 emit_move_insn (adjust_address (tramp
, SImode
, 4), chain
);
2839 emit_move_insn (adjust_address (tramp
, SImode
, 12), fnaddr
);
2843 emit_move_insn (adjust_address (tramp
, SImode
, 2), chain
);
2844 emit_move_insn (adjust_address (tramp
, SImode
, 6 + 2), fnaddr
);
2849 rx_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
2850 reg_class_t regclass ATTRIBUTE_UNUSED
,
2853 return (in
? 2 : 0) + REGISTER_MOVE_COST (mode
, regclass
, regclass
);
2856 /* Convert a CC_MODE to the set of flags that it represents. */
2859 flags_from_mode (enum machine_mode mode
)
2864 return CC_FLAG_S
| CC_FLAG_Z
;
2866 return CC_FLAG_S
| CC_FLAG_Z
| CC_FLAG_O
;
2868 return CC_FLAG_S
| CC_FLAG_Z
| CC_FLAG_C
;
2870 return CC_FLAG_S
| CC_FLAG_Z
| CC_FLAG_O
| CC_FLAG_C
;
2878 /* Convert a set of flags to a CC_MODE that can implement it. */
2880 static enum machine_mode
2881 mode_from_flags (unsigned int f
)
2892 else if (f
& CC_FLAG_C
)
2898 /* Convert an RTX_CODE to the set of flags needed to implement it.
2899 This assumes an integer comparison. */
2902 flags_from_code (enum rtx_code code
)
2911 return CC_FLAG_S
| CC_FLAG_O
| CC_FLAG_Z
;
2917 return CC_FLAG_C
| CC_FLAG_Z
;
2926 /* Return a CC_MODE of which both M1 and M2 are subsets. */
2928 static enum machine_mode
2929 rx_cc_modes_compatible (enum machine_mode m1
, enum machine_mode m2
)
2933 /* Early out for identical modes. */
2937 /* There's no valid combination for FP vs non-FP. */
2938 f
= flags_from_mode (m1
) | flags_from_mode (m2
);
2942 /* Otherwise, see what mode can implement all the flags. */
2943 return mode_from_flags (f
);
2946 /* Return the minimal CC mode needed to implement (CMP_CODE X Y). */
2949 rx_select_cc_mode (enum rtx_code cmp_code
, rtx x
, rtx y
)
2951 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2954 if (y
!= const0_rtx
)
2957 return mode_from_flags (flags_from_code (cmp_code
));
2960 /* Split the conditional branch. Emit (COMPARE C1 C2) into CC_REG with
2961 CC_MODE, and use that in branches based on that compare. */
2964 rx_split_cbranch (enum machine_mode cc_mode
, enum rtx_code cmp1
,
2965 rtx c1
, rtx c2
, rtx label
)
2969 flags
= gen_rtx_REG (cc_mode
, CC_REG
);
2970 x
= gen_rtx_COMPARE (cc_mode
, c1
, c2
);
2971 x
= gen_rtx_SET (VOIDmode
, flags
, x
);
2974 x
= gen_rtx_fmt_ee (cmp1
, VOIDmode
, flags
, const0_rtx
);
2975 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, x
, label
, pc_rtx
);
2976 x
= gen_rtx_SET (VOIDmode
, pc_rtx
, x
);
2980 /* A helper function for matching parallels that set the flags. */
2983 rx_match_ccmode (rtx insn
, enum machine_mode cc_mode
)
2986 enum machine_mode flags_mode
;
2988 gcc_checking_assert (XVECLEN (PATTERN (insn
), 0) == 2);
2990 op1
= XVECEXP (PATTERN (insn
), 0, 1);
2991 gcc_checking_assert (GET_CODE (SET_SRC (op1
)) == COMPARE
);
2993 flags
= SET_DEST (op1
);
2994 flags_mode
= GET_MODE (flags
);
2996 if (GET_MODE (SET_SRC (op1
)) != flags_mode
)
2998 if (GET_MODE_CLASS (flags_mode
) != MODE_CC
)
3001 /* Ensure that the mode of FLAGS is compatible with CC_MODE. */
3002 if (flags_from_mode (flags_mode
) & ~flags_from_mode (cc_mode
))
3009 rx_align_for_label (rtx lab
, int uses_threshold
)
3011 /* This is a simple heuristic to guess when an alignment would not be useful
3012 because the delay due to the inserted NOPs would be greater than the delay
3013 due to the misaligned branch. If uses_threshold is zero then the alignment
3014 is always useful. */
3015 if (LABEL_P (lab
) && LABEL_NUSES (lab
) < uses_threshold
)
3018 return optimize_size
? 1 : 3;
3022 rx_max_skip_for_label (rtx lab
)
3027 if (lab
== NULL_RTX
)
3033 op
= next_nonnote_nondebug_insn (op
);
3035 while (op
&& (LABEL_P (op
)
3036 || (INSN_P (op
) && GET_CODE (PATTERN (op
)) == USE
)));
3040 opsize
= get_attr_length (op
);
3041 if (opsize
>= 0 && opsize
< 8)
3046 /* Compute the real length of the extending load-and-op instructions. */
3049 rx_adjust_insn_length (rtx insn
, int current_length
)
3051 rtx extend
, mem
, offset
;
3055 switch (INSN_CODE (insn
))
3058 return current_length
;
3060 case CODE_FOR_plussi3_zero_extendhi
:
3061 case CODE_FOR_andsi3_zero_extendhi
:
3062 case CODE_FOR_iorsi3_zero_extendhi
:
3063 case CODE_FOR_xorsi3_zero_extendhi
:
3064 case CODE_FOR_divsi3_zero_extendhi
:
3065 case CODE_FOR_udivsi3_zero_extendhi
:
3066 case CODE_FOR_minussi3_zero_extendhi
:
3067 case CODE_FOR_smaxsi3_zero_extendhi
:
3068 case CODE_FOR_sminsi3_zero_extendhi
:
3069 case CODE_FOR_multsi3_zero_extendhi
:
3070 case CODE_FOR_comparesi3_zero_extendhi
:
3075 case CODE_FOR_plussi3_sign_extendhi
:
3076 case CODE_FOR_andsi3_sign_extendhi
:
3077 case CODE_FOR_iorsi3_sign_extendhi
:
3078 case CODE_FOR_xorsi3_sign_extendhi
:
3079 case CODE_FOR_divsi3_sign_extendhi
:
3080 case CODE_FOR_udivsi3_sign_extendhi
:
3081 case CODE_FOR_minussi3_sign_extendhi
:
3082 case CODE_FOR_smaxsi3_sign_extendhi
:
3083 case CODE_FOR_sminsi3_sign_extendhi
:
3084 case CODE_FOR_multsi3_sign_extendhi
:
3085 case CODE_FOR_comparesi3_sign_extendhi
:
3090 case CODE_FOR_plussi3_zero_extendqi
:
3091 case CODE_FOR_andsi3_zero_extendqi
:
3092 case CODE_FOR_iorsi3_zero_extendqi
:
3093 case CODE_FOR_xorsi3_zero_extendqi
:
3094 case CODE_FOR_divsi3_zero_extendqi
:
3095 case CODE_FOR_udivsi3_zero_extendqi
:
3096 case CODE_FOR_minussi3_zero_extendqi
:
3097 case CODE_FOR_smaxsi3_zero_extendqi
:
3098 case CODE_FOR_sminsi3_zero_extendqi
:
3099 case CODE_FOR_multsi3_zero_extendqi
:
3100 case CODE_FOR_comparesi3_zero_extendqi
:
3105 case CODE_FOR_plussi3_sign_extendqi
:
3106 case CODE_FOR_andsi3_sign_extendqi
:
3107 case CODE_FOR_iorsi3_sign_extendqi
:
3108 case CODE_FOR_xorsi3_sign_extendqi
:
3109 case CODE_FOR_divsi3_sign_extendqi
:
3110 case CODE_FOR_udivsi3_sign_extendqi
:
3111 case CODE_FOR_minussi3_sign_extendqi
:
3112 case CODE_FOR_smaxsi3_sign_extendqi
:
3113 case CODE_FOR_sminsi3_sign_extendqi
:
3114 case CODE_FOR_multsi3_sign_extendqi
:
3115 case CODE_FOR_comparesi3_sign_extendqi
:
3121 /* We are expecting: (SET (REG) (<OP> (REG) (<EXTEND> (MEM)))). */
3122 extend
= single_set (insn
);
3123 gcc_assert (extend
!= NULL_RTX
);
3125 extend
= SET_SRC (extend
);
3126 if (GET_CODE (XEXP (extend
, 0)) == ZERO_EXTEND
3127 || GET_CODE (XEXP (extend
, 0)) == SIGN_EXTEND
)
3128 extend
= XEXP (extend
, 0);
3130 extend
= XEXP (extend
, 1);
3132 gcc_assert ((zero
&& (GET_CODE (extend
) == ZERO_EXTEND
))
3133 || (! zero
&& (GET_CODE (extend
) == SIGN_EXTEND
)));
3135 mem
= XEXP (extend
, 0);
3136 gcc_checking_assert (MEM_P (mem
));
3137 if (REG_P (XEXP (mem
, 0)))
3138 return (zero
&& factor
== 1) ? 2 : 3;
3140 /* We are expecting: (MEM (PLUS (REG) (CONST_INT))). */
3141 gcc_checking_assert (GET_CODE (XEXP (mem
, 0)) == PLUS
);
3142 gcc_checking_assert (REG_P (XEXP (XEXP (mem
, 0), 0)));
3144 offset
= XEXP (XEXP (mem
, 0), 1);
3145 gcc_checking_assert (GET_CODE (offset
) == CONST_INT
);
3147 if (IN_RANGE (INTVAL (offset
), 0, 255 * factor
))
3148 return (zero
&& factor
== 1) ? 3 : 4;
3150 return (zero
&& factor
== 1) ? 4 : 5;
3153 #undef TARGET_ASM_JUMP_ALIGN_MAX_SKIP
3154 #define TARGET_ASM_JUMP_ALIGN_MAX_SKIP rx_max_skip_for_label
3155 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
3156 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rx_max_skip_for_label
3157 #undef TARGET_LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP
3158 #define TARGET_LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP rx_max_skip_for_label
3159 #undef TARGET_ASM_LABEL_ALIGN_MAX_SKIP
3160 #define TARGET_ASM_LABEL_ALIGN_MAX_SKIP rx_max_skip_for_label
3162 #undef TARGET_FUNCTION_VALUE
3163 #define TARGET_FUNCTION_VALUE rx_function_value
3165 #undef TARGET_RETURN_IN_MSB
3166 #define TARGET_RETURN_IN_MSB rx_return_in_msb
3168 #undef TARGET_IN_SMALL_DATA_P
3169 #define TARGET_IN_SMALL_DATA_P rx_in_small_data
3171 #undef TARGET_RETURN_IN_MEMORY
3172 #define TARGET_RETURN_IN_MEMORY rx_return_in_memory
3174 #undef TARGET_HAVE_SRODATA_SECTION
3175 #define TARGET_HAVE_SRODATA_SECTION true
3177 #undef TARGET_ASM_SELECT_RTX_SECTION
3178 #define TARGET_ASM_SELECT_RTX_SECTION rx_select_rtx_section
3180 #undef TARGET_ASM_SELECT_SECTION
3181 #define TARGET_ASM_SELECT_SECTION rx_select_section
3183 #undef TARGET_INIT_BUILTINS
3184 #define TARGET_INIT_BUILTINS rx_init_builtins
3186 #undef TARGET_BUILTIN_DECL
3187 #define TARGET_BUILTIN_DECL rx_builtin_decl
3189 #undef TARGET_EXPAND_BUILTIN
3190 #define TARGET_EXPAND_BUILTIN rx_expand_builtin
3192 #undef TARGET_ASM_CONSTRUCTOR
3193 #define TARGET_ASM_CONSTRUCTOR rx_elf_asm_constructor
3195 #undef TARGET_ASM_DESTRUCTOR
3196 #define TARGET_ASM_DESTRUCTOR rx_elf_asm_destructor
3198 #undef TARGET_STRUCT_VALUE_RTX
3199 #define TARGET_STRUCT_VALUE_RTX rx_struct_value_rtx
3201 #undef TARGET_ATTRIBUTE_TABLE
3202 #define TARGET_ATTRIBUTE_TABLE rx_attribute_table
3204 #undef TARGET_ASM_FILE_START
3205 #define TARGET_ASM_FILE_START rx_file_start
3207 #undef TARGET_MS_BITFIELD_LAYOUT_P
3208 #define TARGET_MS_BITFIELD_LAYOUT_P rx_is_ms_bitfield_layout
3210 #undef TARGET_LEGITIMATE_ADDRESS_P
3211 #define TARGET_LEGITIMATE_ADDRESS_P rx_is_legitimate_address
3213 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
3214 #define TARGET_MODE_DEPENDENT_ADDRESS_P rx_mode_dependent_address_p
3216 #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
3217 #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS rx_allocate_stack_slots_for_args
3219 #undef TARGET_ASM_FUNCTION_PROLOGUE
3220 #define TARGET_ASM_FUNCTION_PROLOGUE rx_output_function_prologue
3222 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
3223 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P rx_func_attr_inlinable
3225 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
3226 #define TARGET_FUNCTION_OK_FOR_SIBCALL rx_function_ok_for_sibcall
3228 #undef TARGET_FUNCTION_ARG
3229 #define TARGET_FUNCTION_ARG rx_function_arg
3231 #undef TARGET_FUNCTION_ARG_ADVANCE
3232 #define TARGET_FUNCTION_ARG_ADVANCE rx_function_arg_advance
3234 #undef TARGET_FUNCTION_ARG_BOUNDARY
3235 #define TARGET_FUNCTION_ARG_BOUNDARY rx_function_arg_boundary
3237 #undef TARGET_SET_CURRENT_FUNCTION
3238 #define TARGET_SET_CURRENT_FUNCTION rx_set_current_function
3240 #undef TARGET_ASM_INTEGER
3241 #define TARGET_ASM_INTEGER rx_assemble_integer
3243 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
3244 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
3246 #undef TARGET_MAX_ANCHOR_OFFSET
3247 #define TARGET_MAX_ANCHOR_OFFSET 32
3249 #undef TARGET_ADDRESS_COST
3250 #define TARGET_ADDRESS_COST rx_address_cost
3252 #undef TARGET_CAN_ELIMINATE
3253 #define TARGET_CAN_ELIMINATE rx_can_eliminate
3255 #undef TARGET_CONDITIONAL_REGISTER_USAGE
3256 #define TARGET_CONDITIONAL_REGISTER_USAGE rx_conditional_register_usage
3258 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
3259 #define TARGET_ASM_TRAMPOLINE_TEMPLATE rx_trampoline_template
3261 #undef TARGET_TRAMPOLINE_INIT
3262 #define TARGET_TRAMPOLINE_INIT rx_trampoline_init
3264 #undef TARGET_PRINT_OPERAND
3265 #define TARGET_PRINT_OPERAND rx_print_operand
3267 #undef TARGET_PRINT_OPERAND_ADDRESS
3268 #define TARGET_PRINT_OPERAND_ADDRESS rx_print_operand_address
3270 #undef TARGET_CC_MODES_COMPATIBLE
3271 #define TARGET_CC_MODES_COMPATIBLE rx_cc_modes_compatible
3273 #undef TARGET_MEMORY_MOVE_COST
3274 #define TARGET_MEMORY_MOVE_COST rx_memory_move_cost
3276 #undef TARGET_OPTION_OVERRIDE
3277 #define TARGET_OPTION_OVERRIDE rx_option_override
3279 #undef TARGET_PROMOTE_FUNCTION_MODE
3280 #define TARGET_PROMOTE_FUNCTION_MODE rx_promote_function_mode
3282 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
3283 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE rx_override_options_after_change
3285 #undef TARGET_FLAGS_REGNUM
3286 #define TARGET_FLAGS_REGNUM CC_REG
3288 #undef TARGET_LEGITIMATE_CONSTANT_P
3289 #define TARGET_LEGITIMATE_CONSTANT_P rx_is_legitimate_constant
3291 #undef TARGET_LEGITIMIZE_ADDRESS
3292 #define TARGET_LEGITIMIZE_ADDRESS rx_legitimize_address
3294 #undef TARGET_WARN_FUNC_RETURN
3295 #define TARGET_WARN_FUNC_RETURN rx_warn_func_return
3297 struct gcc_target targetm
= TARGET_INITIALIZER
;