1 /* Subroutines used for code generation on Renesas RX processors.
2 Copyright (C) 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
3 Contributed by Red Hat.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 * Re-enable memory-to-memory copies and fix up reload. */
27 #include "coretypes.h"
32 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "diagnostic-core.h"
51 #include "target-def.h"
52 #include "langhooks.h"
55 static void rx_print_operand (FILE *, rtx
, int);
57 #define CC_FLAG_S (1 << 0)
58 #define CC_FLAG_Z (1 << 1)
59 #define CC_FLAG_O (1 << 2)
60 #define CC_FLAG_C (1 << 3)
61 #define CC_FLAG_FP (1 << 4) /* fake, to differentiate CC_Fmode */
63 static unsigned int flags_from_mode (enum machine_mode mode
);
64 static unsigned int flags_from_code (enum rtx_code code
);
66 enum rx_cpu_types rx_cpu_type
= RX600
;
68 /* Return true if OP is a reference to an object in a small data area. */
71 rx_small_data_operand (rtx op
)
73 if (rx_small_data_limit
== 0)
76 if (GET_CODE (op
) == SYMBOL_REF
)
77 return SYMBOL_REF_SMALL_P (op
);
83 rx_is_legitimate_address (Mmode mode
, rtx x
, bool strict ATTRIBUTE_UNUSED
)
85 if (RTX_OK_FOR_BASE (x
, strict
))
86 /* Register Indirect. */
89 if (GET_MODE_SIZE (mode
) == 4
90 && (GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
))
91 /* Pre-decrement Register Indirect or
92 Post-increment Register Indirect. */
93 return RTX_OK_FOR_BASE (XEXP (x
, 0), strict
);
95 if (GET_CODE (x
) == PLUS
)
97 rtx arg1
= XEXP (x
, 0);
98 rtx arg2
= XEXP (x
, 1);
101 if (REG_P (arg1
) && RTX_OK_FOR_BASE (arg1
, strict
))
103 else if (REG_P (arg2
) && RTX_OK_FOR_BASE (arg2
, strict
))
108 switch (GET_CODE (index
))
112 /* Register Relative: REG + INT.
113 Only positive, mode-aligned, mode-sized
114 displacements are allowed. */
115 HOST_WIDE_INT val
= INTVAL (index
);
121 switch (GET_MODE_SIZE (mode
))
124 case 4: factor
= 4; break;
125 case 2: factor
= 2; break;
126 case 1: factor
= 1; break;
129 if (val
> (65535 * factor
))
131 return (val
% factor
) == 0;
135 /* Unscaled Indexed Register Indirect: REG + REG
136 Size has to be "QI", REG has to be valid. */
137 return GET_MODE_SIZE (mode
) == 1 && RTX_OK_FOR_BASE (index
, strict
);
141 /* Scaled Indexed Register Indirect: REG + (REG * FACTOR)
142 Factor has to equal the mode size, REG has to be valid. */
145 factor
= XEXP (index
, 1);
146 index
= XEXP (index
, 0);
149 && RTX_OK_FOR_BASE (index
, strict
)
150 && CONST_INT_P (factor
)
151 && GET_MODE_SIZE (mode
) == INTVAL (factor
);
159 /* Small data area accesses turn into register relative offsets. */
160 return rx_small_data_operand (x
);
163 /* Returns TRUE for simple memory addreses, ie ones
164 that do not involve register indirect addressing
165 or pre/post increment/decrement. */
168 rx_is_restricted_memory_address (rtx mem
, enum machine_mode mode
)
172 if (! rx_is_legitimate_address
173 (mode
, mem
, reload_in_progress
|| reload_completed
))
176 switch (GET_CODE (mem
))
179 /* Simple memory addresses are OK. */
187 /* Only allow REG+INT addressing. */
188 base
= XEXP (mem
, 0);
189 index
= XEXP (mem
, 1);
191 return RX_REG_P (base
) && CONST_INT_P (index
);
194 /* Can happen when small data is being supported.
195 Assume that it will be resolved into GP+INT. */
203 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
206 rx_mode_dependent_address_p (const_rtx addr
)
208 if (GET_CODE (addr
) == CONST
)
209 addr
= XEXP (addr
, 0);
211 switch (GET_CODE (addr
))
213 /* --REG and REG++ only work in SImode. */
220 if (! REG_P (XEXP (addr
, 0)))
223 addr
= XEXP (addr
, 1);
225 switch (GET_CODE (addr
))
228 /* REG+REG only works in SImode. */
232 /* REG+INT is only mode independent if INT is a
233 multiple of 4, positive and will fit into 8-bits. */
234 if (((INTVAL (addr
) & 3) == 0)
235 && IN_RANGE (INTVAL (addr
), 4, 252))
244 gcc_assert (REG_P (XEXP (addr
, 0)));
245 gcc_assert (CONST_INT_P (XEXP (addr
, 1)));
246 /* REG+REG*SCALE is always mode dependent. */
250 /* Not recognized, so treat as mode dependent. */
258 /* These are all mode independent. */
262 /* Everything else is unrecognized,
263 so treat as mode dependent. */
268 /* A C compound statement to output to stdio stream FILE the
269 assembler syntax for an instruction operand that is a memory
270 reference whose address is ADDR. */
273 rx_print_operand_address (FILE * file
, rtx addr
)
275 switch (GET_CODE (addr
))
279 rx_print_operand (file
, addr
, 0);
284 fprintf (file
, "[-");
285 rx_print_operand (file
, XEXP (addr
, 0), 0);
291 rx_print_operand (file
, XEXP (addr
, 0), 0);
292 fprintf (file
, "+]");
297 rtx arg1
= XEXP (addr
, 0);
298 rtx arg2
= XEXP (addr
, 1);
301 if (REG_P (arg1
) && RTX_OK_FOR_BASE (arg1
, true))
302 base
= arg1
, index
= arg2
;
303 else if (REG_P (arg2
) && RTX_OK_FOR_BASE (arg2
, true))
304 base
= arg2
, index
= arg1
;
307 rx_print_operand (file
, arg1
, 0);
308 fprintf (file
, " + ");
309 rx_print_operand (file
, arg2
, 0);
313 if (REG_P (index
) || GET_CODE (index
) == MULT
)
316 rx_print_operand (file
, index
, 'A');
319 else /* GET_CODE (index) == CONST_INT */
321 rx_print_operand (file
, index
, 'A');
324 rx_print_operand (file
, base
, 0);
330 if (GET_CODE (XEXP (addr
, 0)) == UNSPEC
)
332 addr
= XEXP (addr
, 0);
333 gcc_assert (XINT (addr
, 1) == UNSPEC_CONST
);
335 addr
= XVECEXP (addr
, 0, 0);
336 gcc_assert (CONST_INT_P (addr
));
344 output_addr_const (file
, addr
);
350 rx_print_integer (FILE * file
, HOST_WIDE_INT val
)
352 if (IN_RANGE (val
, -64, 64))
353 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, val
);
357 ? "0%" HOST_WIDE_INT_PRINT
"xH" : HOST_WIDE_INT_PRINT_HEX
,
362 rx_assemble_integer (rtx x
, unsigned int size
, int is_aligned
)
364 const char * op
= integer_asm_op (size
, is_aligned
);
366 if (! CONST_INT_P (x
))
367 return default_assemble_integer (x
, size
, is_aligned
);
371 fputs (op
, asm_out_file
);
373 rx_print_integer (asm_out_file
, INTVAL (x
));
374 fputc ('\n', asm_out_file
);
379 /* Handles the insertion of a single operand into the assembler output.
380 The %<letter> directives supported are:
382 %A Print an operand without a leading # character.
383 %B Print an integer comparison name.
384 %C Print a control register name.
385 %F Print a condition code flag name.
386 %H Print high part of a DImode register, integer or address.
387 %L Print low part of a DImode register, integer or address.
388 %N Print the negation of the immediate value.
389 %Q If the operand is a MEM, then correctly generate
390 register indirect or register relative addressing. */
393 rx_print_operand (FILE * file
, rtx op
, int letter
)
398 /* Print an operand without a leading #. */
402 switch (GET_CODE (op
))
406 output_addr_const (file
, op
);
409 fprintf (file
, "%ld", (long) INTVAL (op
));
412 rx_print_operand (file
, op
, 0);
419 enum rtx_code code
= GET_CODE (op
);
420 enum machine_mode mode
= GET_MODE (XEXP (op
, 0));
423 if (mode
== CC_Fmode
)
425 /* C flag is undefined, and O flag carries unordered. None of the
426 branch combinations that include O use it helpfully. */
453 unsigned int flags
= flags_from_mode (mode
);
457 ret
= (flags
& CC_FLAG_O
? "lt" : "n");
460 ret
= (flags
& CC_FLAG_O
? "ge" : "pz");
489 gcc_checking_assert ((flags_from_code (code
) & ~flags
) == 0);
496 gcc_assert (CONST_INT_P (op
));
499 case 0: fprintf (file
, "psw"); break;
500 case 2: fprintf (file
, "usp"); break;
501 case 3: fprintf (file
, "fpsw"); break;
502 case 4: fprintf (file
, "cpen"); break;
503 case 8: fprintf (file
, "bpsw"); break;
504 case 9: fprintf (file
, "bpc"); break;
505 case 0xa: fprintf (file
, "isp"); break;
506 case 0xb: fprintf (file
, "fintv"); break;
507 case 0xc: fprintf (file
, "intb"); break;
509 warning (0, "unreocgnized control register number: %d - using 'psw'",
511 fprintf (file
, "psw");
517 gcc_assert (CONST_INT_P (op
));
520 case 0: case 'c': case 'C': fprintf (file
, "C"); break;
521 case 1: case 'z': case 'Z': fprintf (file
, "Z"); break;
522 case 2: case 's': case 'S': fprintf (file
, "S"); break;
523 case 3: case 'o': case 'O': fprintf (file
, "O"); break;
524 case 8: case 'i': case 'I': fprintf (file
, "I"); break;
525 case 9: case 'u': case 'U': fprintf (file
, "U"); break;
532 switch (GET_CODE (op
))
535 fprintf (file
, "%s", reg_names
[REGNO (op
) + (WORDS_BIG_ENDIAN
? 0 : 1)]);
539 HOST_WIDE_INT v
= INTVAL (op
);
542 /* Trickery to avoid problems with shifting 32 bits at a time. */
545 rx_print_integer (file
, v
);
550 rx_print_integer (file
, CONST_DOUBLE_HIGH (op
));
553 if (! WORDS_BIG_ENDIAN
)
554 op
= adjust_address (op
, SImode
, 4);
555 output_address (XEXP (op
, 0));
563 switch (GET_CODE (op
))
566 fprintf (file
, "%s", reg_names
[REGNO (op
) + (WORDS_BIG_ENDIAN
? 1 : 0)]);
570 rx_print_integer (file
, INTVAL (op
) & 0xffffffff);
574 rx_print_integer (file
, CONST_DOUBLE_LOW (op
));
577 if (WORDS_BIG_ENDIAN
)
578 op
= adjust_address (op
, SImode
, 4);
579 output_address (XEXP (op
, 0));
587 gcc_assert (CONST_INT_P (op
));
589 rx_print_integer (file
, - INTVAL (op
));
595 HOST_WIDE_INT offset
;
601 else if (GET_CODE (op
) == PLUS
)
605 if (REG_P (XEXP (op
, 0)))
607 displacement
= XEXP (op
, 1);
612 displacement
= XEXP (op
, 0);
614 gcc_assert (REG_P (op
));
617 gcc_assert (CONST_INT_P (displacement
));
618 offset
= INTVAL (displacement
);
619 gcc_assert (offset
>= 0);
621 fprintf (file
, "%ld", offset
);
627 rx_print_operand (file
, op
, 0);
628 fprintf (file
, "].");
630 switch (GET_MODE_SIZE (GET_MODE (op
)))
633 gcc_assert (offset
< 65535 * 1);
637 gcc_assert (offset
% 2 == 0);
638 gcc_assert (offset
< 65535 * 2);
642 gcc_assert (offset
% 4 == 0);
643 gcc_assert (offset
< 65535 * 4);
653 switch (GET_CODE (op
))
656 /* Should be the scaled part of an
657 indexed register indirect address. */
659 rtx base
= XEXP (op
, 0);
660 rtx index
= XEXP (op
, 1);
662 /* Check for a swaped index register and scaling factor.
663 Not sure if this can happen, but be prepared to handle it. */
664 if (CONST_INT_P (base
) && REG_P (index
))
671 gcc_assert (REG_P (base
));
672 gcc_assert (REGNO (base
) < FIRST_PSEUDO_REGISTER
);
673 gcc_assert (CONST_INT_P (index
));
674 /* Do not try to verify the value of the scalar as it is based
675 on the mode of the MEM not the mode of the MULT. (Which
676 will always be SImode). */
677 fprintf (file
, "%s", reg_names
[REGNO (base
)]);
682 output_address (XEXP (op
, 0));
690 gcc_assert (REGNO (op
) < FIRST_PSEUDO_REGISTER
);
691 fprintf (file
, "%s", reg_names
[REGNO (op
)]);
695 gcc_assert (subreg_regno (op
) < FIRST_PSEUDO_REGISTER
);
696 fprintf (file
, "%s", reg_names
[subreg_regno (op
)]);
699 /* This will only be single precision.... */
705 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
706 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
707 fprintf (file
, TARGET_AS100_SYNTAX
? "#0%lxH" : "#0x%lx", val
);
713 rx_print_integer (file
, INTVAL (op
));
721 rx_print_operand_address (file
, op
);
731 /* Returns an assembler template for a move instruction. */
734 rx_gen_move_template (rtx
* operands
, bool is_movu
)
736 static char out_template
[64];
737 const char * extension
= TARGET_AS100_SYNTAX
? ".L" : "";
738 const char * src_template
;
739 const char * dst_template
;
740 rtx dest
= operands
[0];
741 rtx src
= operands
[1];
743 /* Decide which extension, if any, should be given to the move instruction. */
744 switch (CONST_INT_P (src
) ? GET_MODE (dest
) : GET_MODE (src
))
747 /* The .B extension is not valid when
748 loading an immediate into a register. */
749 if (! REG_P (dest
) || ! CONST_INT_P (src
))
753 if (! REG_P (dest
) || ! CONST_INT_P (src
))
754 /* The .W extension is not valid when
755 loading an immediate into a register. */
763 /* This mode is used by constants. */
770 if (MEM_P (src
) && rx_small_data_operand (XEXP (src
, 0)))
771 src_template
= "%%gp(%A1)[r13]";
775 if (MEM_P (dest
) && rx_small_data_operand (XEXP (dest
, 0)))
776 dst_template
= "%%gp(%A0)[r13]";
780 sprintf (out_template
, "%s%s\t%s, %s", is_movu
? "movu" : "mov",
781 extension
, src_template
, dst_template
);
785 /* Return VALUE rounded up to the next ALIGNMENT boundary. */
787 static inline unsigned int
788 rx_round_up (unsigned int value
, unsigned int alignment
)
791 return (value
+ alignment
) & (~ alignment
);
794 /* Return the number of bytes in the argument registers
795 occupied by an argument of type TYPE and mode MODE. */
798 rx_function_arg_size (Mmode mode
, const_tree type
)
800 unsigned int num_bytes
;
802 num_bytes
= (mode
== BLKmode
)
803 ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
804 return rx_round_up (num_bytes
, UNITS_PER_WORD
);
807 #define NUM_ARG_REGS 4
808 #define MAX_NUM_ARG_BYTES (NUM_ARG_REGS * UNITS_PER_WORD)
810 /* Return an RTL expression describing the register holding a function
811 parameter of mode MODE and type TYPE or NULL_RTX if the parameter should
812 be passed on the stack. CUM describes the previous parameters to the
813 function and NAMED is false if the parameter is part of a variable
814 parameter list, or the last named parameter before the start of a
815 variable parameter list. */
818 rx_function_arg (Fargs
* cum
, Mmode mode
, const_tree type
, bool named
)
820 unsigned int next_reg
;
821 unsigned int bytes_so_far
= *cum
;
823 unsigned int rounded_size
;
825 /* An exploded version of rx_function_arg_size. */
826 size
= (mode
== BLKmode
) ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
827 /* If the size is not known it cannot be passed in registers. */
831 rounded_size
= rx_round_up (size
, UNITS_PER_WORD
);
833 /* Don't pass this arg via registers if there
834 are insufficient registers to hold all of it. */
835 if (rounded_size
+ bytes_so_far
> MAX_NUM_ARG_BYTES
)
838 /* Unnamed arguments and the last named argument in a
839 variadic function are always passed on the stack. */
843 /* Structures must occupy an exact number of registers,
844 otherwise they are passed on the stack. */
845 if ((type
== NULL
|| AGGREGATE_TYPE_P (type
))
846 && (size
% UNITS_PER_WORD
) != 0)
849 next_reg
= (bytes_so_far
/ UNITS_PER_WORD
) + 1;
851 return gen_rtx_REG (mode
, next_reg
);
855 rx_function_arg_advance (Fargs
* cum
, Mmode mode
, const_tree type
,
856 bool named ATTRIBUTE_UNUSED
)
858 *cum
+= rx_function_arg_size (mode
, type
);
862 rx_function_arg_boundary (Mmode mode ATTRIBUTE_UNUSED
,
863 const_tree type ATTRIBUTE_UNUSED
)
868 /* Return an RTL describing where a function return value of type RET_TYPE
872 rx_function_value (const_tree ret_type
,
873 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
874 bool outgoing ATTRIBUTE_UNUSED
)
876 enum machine_mode mode
= TYPE_MODE (ret_type
);
878 /* RX ABI specifies that small integer types are
879 promoted to int when returned by a function. */
880 if (GET_MODE_SIZE (mode
) > 0
881 && GET_MODE_SIZE (mode
) < 4
882 && ! COMPLEX_MODE_P (mode
)
884 return gen_rtx_REG (SImode
, FUNC_RETURN_REGNUM
);
886 return gen_rtx_REG (mode
, FUNC_RETURN_REGNUM
);
889 /* TARGET_PROMOTE_FUNCTION_MODE must behave in the same way with
890 regard to function returns as does TARGET_FUNCTION_VALUE. */
892 static enum machine_mode
893 rx_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
894 enum machine_mode mode
,
895 int * punsignedp ATTRIBUTE_UNUSED
,
896 const_tree funtype ATTRIBUTE_UNUSED
,
900 || GET_MODE_SIZE (mode
) >= 4
901 || COMPLEX_MODE_P (mode
)
902 || GET_MODE_SIZE (mode
) < 1)
909 rx_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
913 if (TYPE_MODE (type
) != BLKmode
914 && ! AGGREGATE_TYPE_P (type
))
917 size
= int_size_in_bytes (type
);
918 /* Large structs and those whose size is not an
919 exact multiple of 4 are returned in memory. */
922 || (size
% UNITS_PER_WORD
) != 0;
926 rx_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED
,
927 int incoming ATTRIBUTE_UNUSED
)
929 return gen_rtx_REG (Pmode
, STRUCT_VAL_REGNUM
);
933 rx_return_in_msb (const_tree valtype
)
935 return TARGET_BIG_ENDIAN_DATA
936 && (AGGREGATE_TYPE_P (valtype
) || TREE_CODE (valtype
) == COMPLEX_TYPE
);
939 /* Returns true if the provided function has the specified attribute. */
942 has_func_attr (const_tree decl
, const char * func_attr
)
944 if (decl
== NULL_TREE
)
945 decl
= current_function_decl
;
947 return lookup_attribute (func_attr
, DECL_ATTRIBUTES (decl
)) != NULL_TREE
;
950 /* Returns true if the provided function has the "fast_interrupt" attribute. */
953 is_fast_interrupt_func (const_tree decl
)
955 return has_func_attr (decl
, "fast_interrupt");
958 /* Returns true if the provided function has the "interrupt" attribute. */
961 is_interrupt_func (const_tree decl
)
963 return has_func_attr (decl
, "interrupt");
966 /* Returns true if the provided function has the "naked" attribute. */
969 is_naked_func (const_tree decl
)
971 return has_func_attr (decl
, "naked");
974 static bool use_fixed_regs
= false;
977 rx_conditional_register_usage (void)
979 static bool using_fixed_regs
= false;
981 if (rx_small_data_limit
> 0)
982 fixed_regs
[GP_BASE_REGNUM
] = call_used_regs
[GP_BASE_REGNUM
] = 1;
984 if (use_fixed_regs
!= using_fixed_regs
)
986 static char saved_fixed_regs
[FIRST_PSEUDO_REGISTER
];
987 static char saved_call_used_regs
[FIRST_PSEUDO_REGISTER
];
993 memcpy (saved_fixed_regs
, fixed_regs
, sizeof fixed_regs
);
994 memcpy (saved_call_used_regs
, call_used_regs
, sizeof call_used_regs
);
996 /* This is for fast interrupt handlers. Any register in
997 the range r10 to r13 (inclusive) that is currently
998 marked as fixed is now a viable, call-used register. */
999 for (r
= 10; r
<= 13; r
++)
1003 call_used_regs
[r
] = 1;
1006 /* Mark r7 as fixed. This is just a hack to avoid
1007 altering the reg_alloc_order array so that the newly
1008 freed r10-r13 registers are the preferred registers. */
1009 fixed_regs
[7] = call_used_regs
[7] = 1;
1013 /* Restore the normal register masks. */
1014 memcpy (fixed_regs
, saved_fixed_regs
, sizeof fixed_regs
);
1015 memcpy (call_used_regs
, saved_call_used_regs
, sizeof call_used_regs
);
1018 using_fixed_regs
= use_fixed_regs
;
1022 /* Perform any actions necessary before starting to compile FNDECL.
1023 For the RX we use this to make sure that we have the correct
1024 set of register masks selected. If FNDECL is NULL then we are
1025 compiling top level things. */
1028 rx_set_current_function (tree fndecl
)
1030 /* Remember the last target of rx_set_current_function. */
1031 static tree rx_previous_fndecl
;
1032 bool prev_was_fast_interrupt
;
1033 bool current_is_fast_interrupt
;
1035 /* Only change the context if the function changes. This hook is called
1036 several times in the course of compiling a function, and we don't want
1037 to slow things down too much or call target_reinit when it isn't safe. */
1038 if (fndecl
== rx_previous_fndecl
)
1041 prev_was_fast_interrupt
1042 = rx_previous_fndecl
1043 ? is_fast_interrupt_func (rx_previous_fndecl
) : false;
1045 current_is_fast_interrupt
1046 = fndecl
? is_fast_interrupt_func (fndecl
) : false;
1048 if (prev_was_fast_interrupt
!= current_is_fast_interrupt
)
1050 use_fixed_regs
= current_is_fast_interrupt
;
1054 rx_previous_fndecl
= fndecl
;
1057 /* Typical stack layout should looks like this after the function's prologue:
1062 | | arguments saved | Increasing
1063 | | on the stack | addresses
1064 PARENT arg pointer -> | | /
1065 -------------------------- ---- -------------------
1066 CHILD |ret | return address
1076 frame pointer -> | | /
1079 | | outgoing | Decreasing
1080 | | arguments | addresses
1081 current stack pointer -> | | / |
1082 -------------------------- ---- ------------------ V
1086 bit_count (unsigned int x
)
1088 const unsigned int m1
= 0x55555555;
1089 const unsigned int m2
= 0x33333333;
1090 const unsigned int m4
= 0x0f0f0f0f;
1093 x
= (x
& m2
) + ((x
>> 2) & m2
);
1094 x
= (x
+ (x
>> 4)) & m4
;
1097 return (x
+ (x
>> 16)) & 0x3f;
1100 #define MUST_SAVE_ACC_REGISTER \
1101 (TARGET_SAVE_ACC_REGISTER \
1102 && (is_interrupt_func (NULL_TREE) \
1103 || is_fast_interrupt_func (NULL_TREE)))
1105 /* Returns either the lowest numbered and highest numbered registers that
1106 occupy the call-saved area of the stack frame, if the registers are
1107 stored as a contiguous block, or else a bitmask of the individual
1108 registers if they are stored piecemeal.
1110 Also computes the size of the frame and the size of the outgoing
1111 arguments block (in bytes). */
1114 rx_get_stack_layout (unsigned int * lowest
,
1115 unsigned int * highest
,
1116 unsigned int * register_mask
,
1117 unsigned int * frame_size
,
1118 unsigned int * stack_size
)
1123 unsigned int fixed_reg
= 0;
1124 unsigned int save_mask
;
1125 unsigned int pushed_mask
;
1126 unsigned int unneeded_pushes
;
1128 if (is_naked_func (NULL_TREE
))
1130 /* Naked functions do not create their own stack frame.
1131 Instead the programmer must do that for us. */
1134 * register_mask
= 0;
1140 for (save_mask
= high
= low
= 0, reg
= 1; reg
< CC_REGNUM
; reg
++)
1142 if ((df_regs_ever_live_p (reg
)
1143 /* Always save all call clobbered registers inside non-leaf
1144 interrupt handlers, even if they are not live - they may
1145 be used in (non-interrupt aware) routines called from this one. */
1146 || (call_used_regs
[reg
]
1147 && is_interrupt_func (NULL_TREE
)
1148 && ! current_function_is_leaf
))
1149 && (! call_used_regs
[reg
]
1150 /* Even call clobbered registered must
1151 be pushed inside interrupt handlers. */
1152 || is_interrupt_func (NULL_TREE
)
1153 /* Likewise for fast interrupt handlers, except registers r10 -
1154 r13. These are normally call-saved, but may have been set
1155 to call-used by rx_conditional_register_usage. If so then
1156 they can be used in the fast interrupt handler without
1157 saving them on the stack. */
1158 || (is_fast_interrupt_func (NULL_TREE
)
1159 && ! IN_RANGE (reg
, 10, 13))))
1165 save_mask
|= 1 << reg
;
1168 /* Remember if we see a fixed register
1169 after having found the low register. */
1170 if (low
!= 0 && fixed_reg
== 0 && fixed_regs
[reg
])
1174 /* If we have to save the accumulator register, make sure
1175 that at least two registers are pushed into the frame. */
1176 if (MUST_SAVE_ACC_REGISTER
1177 && bit_count (save_mask
) < 2)
1179 save_mask
|= (1 << 13) | (1 << 14);
1182 if (high
== 0 || low
== high
)
1186 /* Decide if it would be faster fill in the call-saved area of the stack
1187 frame using multiple PUSH instructions instead of a single PUSHM
1190 SAVE_MASK is a bitmask of the registers that must be stored in the
1191 call-save area. PUSHED_MASK is a bitmask of the registers that would
1192 be pushed into the area if we used a PUSHM instruction. UNNEEDED_PUSHES
1193 is a bitmask of those registers in pushed_mask that are not in
1196 We use a simple heuristic that says that it is better to use
1197 multiple PUSH instructions if the number of unnecessary pushes is
1198 greater than the number of necessary pushes.
1200 We also use multiple PUSH instructions if there are any fixed registers
1201 between LOW and HIGH. The only way that this can happen is if the user
1202 has specified --fixed-<reg-name> on the command line and in such
1203 circumstances we do not want to touch the fixed registers at all.
1205 FIXME: Is it worth improving this heuristic ? */
1206 pushed_mask
= (-1 << low
) & ~(-1 << (high
+ 1));
1207 unneeded_pushes
= (pushed_mask
& (~ save_mask
)) & pushed_mask
;
1209 if ((fixed_reg
&& fixed_reg
<= high
)
1210 || (optimize_function_for_speed_p (cfun
)
1211 && bit_count (save_mask
) < bit_count (unneeded_pushes
)))
1213 /* Use multiple pushes. */
1216 * register_mask
= save_mask
;
1220 /* Use one push multiple instruction. */
1223 * register_mask
= 0;
1226 * frame_size
= rx_round_up
1227 (get_frame_size (), STACK_BOUNDARY
/ BITS_PER_UNIT
);
1229 if (crtl
->args
.size
> 0)
1230 * frame_size
+= rx_round_up
1231 (crtl
->args
.size
, STACK_BOUNDARY
/ BITS_PER_UNIT
);
1233 * stack_size
= rx_round_up
1234 (crtl
->outgoing_args_size
, STACK_BOUNDARY
/ BITS_PER_UNIT
);
1237 /* Generate a PUSHM instruction that matches the given operands. */
1240 rx_emit_stack_pushm (rtx
* operands
)
1242 HOST_WIDE_INT last_reg
;
1245 gcc_assert (CONST_INT_P (operands
[0]));
1246 last_reg
= (INTVAL (operands
[0]) / UNITS_PER_WORD
) - 1;
1248 gcc_assert (GET_CODE (operands
[1]) == PARALLEL
);
1249 first_push
= XVECEXP (operands
[1], 0, 1);
1250 gcc_assert (SET_P (first_push
));
1251 first_push
= SET_SRC (first_push
);
1252 gcc_assert (REG_P (first_push
));
1254 asm_fprintf (asm_out_file
, "\tpushm\t%s-%s\n",
1255 reg_names
[REGNO (first_push
) - last_reg
],
1256 reg_names
[REGNO (first_push
)]);
1259 /* Generate a PARALLEL that will pass the rx_store_multiple_vector predicate. */
1262 gen_rx_store_vector (unsigned int low
, unsigned int high
)
1265 unsigned int count
= (high
- low
) + 2;
1268 vector
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
1270 XVECEXP (vector
, 0, 0) =
1271 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
1272 gen_rtx_MINUS (SImode
, stack_pointer_rtx
,
1273 GEN_INT ((count
- 1) * UNITS_PER_WORD
)));
1275 for (i
= 0; i
< count
- 1; i
++)
1276 XVECEXP (vector
, 0, i
+ 1) =
1277 gen_rtx_SET (VOIDmode
,
1278 gen_rtx_MEM (SImode
,
1279 gen_rtx_MINUS (SImode
, stack_pointer_rtx
,
1280 GEN_INT ((i
+ 1) * UNITS_PER_WORD
))),
1281 gen_rtx_REG (SImode
, high
- i
));
1285 /* Mark INSN as being frame related. If it is a PARALLEL
1286 then mark each element as being frame related as well. */
1289 mark_frame_related (rtx insn
)
1291 RTX_FRAME_RELATED_P (insn
) = 1;
1292 insn
= PATTERN (insn
);
1294 if (GET_CODE (insn
) == PARALLEL
)
1298 for (i
= 0; i
< (unsigned) XVECLEN (insn
, 0); i
++)
1299 RTX_FRAME_RELATED_P (XVECEXP (insn
, 0, i
)) = 1;
1304 ok_for_max_constant (HOST_WIDE_INT val
)
1306 if (rx_max_constant_size
== 0 || rx_max_constant_size
== 4)
1307 /* If there is no constraint on the size of constants
1308 used as operands, then any value is legitimate. */
1311 /* rx_max_constant_size specifies the maximum number
1312 of bytes that can be used to hold a signed value. */
1313 return IN_RANGE (val
, (-1 << (rx_max_constant_size
* 8)),
1314 ( 1 << (rx_max_constant_size
* 8)));
1317 /* Generate an ADD of SRC plus VAL into DEST.
1318 Handles the case where VAL is too big for max_constant_value.
1319 Sets FRAME_RELATED_P on the insn if IS_FRAME_RELATED is true. */
1322 gen_safe_add (rtx dest
, rtx src
, rtx val
, bool is_frame_related
)
1326 if (val
== NULL_RTX
|| INTVAL (val
) == 0)
1328 gcc_assert (dest
!= src
);
1330 insn
= emit_move_insn (dest
, src
);
1332 else if (ok_for_max_constant (INTVAL (val
)))
1333 insn
= emit_insn (gen_addsi3 (dest
, src
, val
));
1336 /* Wrap VAL in an UNSPEC so that rx_is_legitimate_constant
1337 will not reject it. */
1338 val
= gen_rtx_CONST (SImode
, gen_rtx_UNSPEC (SImode
, gen_rtvec (1, val
), UNSPEC_CONST
));
1339 insn
= emit_insn (gen_addsi3 (dest
, src
, val
));
1341 if (is_frame_related
)
1342 /* We have to provide our own frame related note here
1343 as the dwarf2out code cannot be expected to grok
1345 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
1346 gen_rtx_SET (SImode
, dest
,
1347 gen_rtx_PLUS (SImode
, src
, val
)));
1351 if (is_frame_related
)
1352 RTX_FRAME_RELATED_P (insn
) = 1;
1357 rx_expand_prologue (void)
1359 unsigned int stack_size
;
1360 unsigned int frame_size
;
1367 /* Naked functions use their own, programmer provided prologues. */
1368 if (is_naked_func (NULL_TREE
))
1371 rx_get_stack_layout (& low
, & high
, & mask
, & frame_size
, & stack_size
);
1373 /* If we use any of the callee-saved registers, save them now. */
1376 /* Push registers in reverse order. */
1377 for (reg
= CC_REGNUM
; reg
--;)
1378 if (mask
& (1 << reg
))
1380 insn
= emit_insn (gen_stack_push (gen_rtx_REG (SImode
, reg
)));
1381 mark_frame_related (insn
);
1387 insn
= emit_insn (gen_stack_push (gen_rtx_REG (SImode
, low
)));
1389 insn
= emit_insn (gen_stack_pushm (GEN_INT (((high
- low
) + 1)
1391 gen_rx_store_vector (low
, high
)));
1392 mark_frame_related (insn
);
1395 if (MUST_SAVE_ACC_REGISTER
)
1397 unsigned int acc_high
, acc_low
;
1399 /* Interrupt handlers have to preserve the accumulator
1400 register if so requested by the user. Use the first
1401 two pushed registers as intermediaries. */
1404 acc_low
= acc_high
= 0;
1406 for (reg
= 1; reg
< CC_REGNUM
; reg
++)
1407 if (mask
& (1 << reg
))
1418 /* We have assumed that there are at least two registers pushed... */
1419 gcc_assert (acc_high
!= 0);
1421 /* Note - the bottom 16 bits of the accumulator are inaccessible.
1422 We just assume that they are zero. */
1423 emit_insn (gen_mvfacmi (gen_rtx_REG (SImode
, acc_low
)));
1424 emit_insn (gen_mvfachi (gen_rtx_REG (SImode
, acc_high
)));
1425 emit_insn (gen_stack_push (gen_rtx_REG (SImode
, acc_low
)));
1426 emit_insn (gen_stack_push (gen_rtx_REG (SImode
, acc_high
)));
1433 /* We have assumed that there are at least two registers pushed... */
1434 gcc_assert (acc_high
<= high
);
1436 emit_insn (gen_mvfacmi (gen_rtx_REG (SImode
, acc_low
)));
1437 emit_insn (gen_mvfachi (gen_rtx_REG (SImode
, acc_high
)));
1438 emit_insn (gen_stack_pushm (GEN_INT (2 * UNITS_PER_WORD
),
1439 gen_rx_store_vector (acc_low
, acc_high
)));
1443 /* If needed, set up the frame pointer. */
1444 if (frame_pointer_needed
)
1445 gen_safe_add (frame_pointer_rtx
, stack_pointer_rtx
,
1446 GEN_INT (- (HOST_WIDE_INT
) frame_size
), true);
1448 /* Allocate space for the outgoing args.
1449 If the stack frame has not already been set up then handle this as well. */
1454 if (frame_pointer_needed
)
1455 gen_safe_add (stack_pointer_rtx
, frame_pointer_rtx
,
1456 GEN_INT (- (HOST_WIDE_INT
) stack_size
), true);
1458 gen_safe_add (stack_pointer_rtx
, stack_pointer_rtx
,
1459 GEN_INT (- (HOST_WIDE_INT
) (frame_size
+ stack_size
)),
1463 gen_safe_add (stack_pointer_rtx
, stack_pointer_rtx
,
1464 GEN_INT (- (HOST_WIDE_INT
) stack_size
), true);
1466 else if (frame_size
)
1468 if (! frame_pointer_needed
)
1469 gen_safe_add (stack_pointer_rtx
, stack_pointer_rtx
,
1470 GEN_INT (- (HOST_WIDE_INT
) frame_size
), true);
1472 gen_safe_add (stack_pointer_rtx
, frame_pointer_rtx
, NULL_RTX
,
1478 rx_output_function_prologue (FILE * file
,
1479 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED
)
1481 if (is_fast_interrupt_func (NULL_TREE
))
1482 asm_fprintf (file
, "\t; Note: Fast Interrupt Handler\n");
1484 if (is_interrupt_func (NULL_TREE
))
1485 asm_fprintf (file
, "\t; Note: Interrupt Handler\n");
1487 if (is_naked_func (NULL_TREE
))
1488 asm_fprintf (file
, "\t; Note: Naked Function\n");
1490 if (cfun
->static_chain_decl
!= NULL
)
1491 asm_fprintf (file
, "\t; Note: Nested function declared "
1492 "inside another function.\n");
1494 if (crtl
->calls_eh_return
)
1495 asm_fprintf (file
, "\t; Note: Calls __builtin_eh_return.\n");
1498 /* Generate a POPM or RTSD instruction that matches the given operands. */
1501 rx_emit_stack_popm (rtx
* operands
, bool is_popm
)
1503 HOST_WIDE_INT stack_adjust
;
1504 HOST_WIDE_INT last_reg
;
1507 gcc_assert (CONST_INT_P (operands
[0]));
1508 stack_adjust
= INTVAL (operands
[0]);
1510 gcc_assert (GET_CODE (operands
[1]) == PARALLEL
);
1511 last_reg
= XVECLEN (operands
[1], 0) - (is_popm
? 2 : 3);
1513 first_push
= XVECEXP (operands
[1], 0, 1);
1514 gcc_assert (SET_P (first_push
));
1515 first_push
= SET_DEST (first_push
);
1516 gcc_assert (REG_P (first_push
));
1519 asm_fprintf (asm_out_file
, "\tpopm\t%s-%s\n",
1520 reg_names
[REGNO (first_push
)],
1521 reg_names
[REGNO (first_push
) + last_reg
]);
1523 asm_fprintf (asm_out_file
, "\trtsd\t#%d, %s-%s\n",
1525 reg_names
[REGNO (first_push
)],
1526 reg_names
[REGNO (first_push
) + last_reg
]);
1529 /* Generate a PARALLEL which will satisfy the rx_rtsd_vector predicate. */
1532 gen_rx_rtsd_vector (unsigned int adjust
, unsigned int low
, unsigned int high
)
1535 unsigned int bias
= 3;
1536 unsigned int count
= (high
- low
) + bias
;
1539 vector
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
1541 XVECEXP (vector
, 0, 0) =
1542 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
1543 plus_constant (stack_pointer_rtx
, adjust
));
1545 for (i
= 0; i
< count
- 2; i
++)
1546 XVECEXP (vector
, 0, i
+ 1) =
1547 gen_rtx_SET (VOIDmode
,
1548 gen_rtx_REG (SImode
, low
+ i
),
1549 gen_rtx_MEM (SImode
,
1550 i
== 0 ? stack_pointer_rtx
1551 : plus_constant (stack_pointer_rtx
,
1552 i
* UNITS_PER_WORD
)));
1554 XVECEXP (vector
, 0, count
- 1) = gen_rtx_RETURN (VOIDmode
);
1559 /* Generate a PARALLEL which will satisfy the rx_load_multiple_vector predicate. */
1562 gen_rx_popm_vector (unsigned int low
, unsigned int high
)
1565 unsigned int count
= (high
- low
) + 2;
1568 vector
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
1570 XVECEXP (vector
, 0, 0) =
1571 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
1572 plus_constant (stack_pointer_rtx
,
1573 (count
- 1) * UNITS_PER_WORD
));
1575 for (i
= 0; i
< count
- 1; i
++)
1576 XVECEXP (vector
, 0, i
+ 1) =
1577 gen_rtx_SET (VOIDmode
,
1578 gen_rtx_REG (SImode
, low
+ i
),
1579 gen_rtx_MEM (SImode
,
1580 i
== 0 ? stack_pointer_rtx
1581 : plus_constant (stack_pointer_rtx
,
1582 i
* UNITS_PER_WORD
)));
1588 rx_expand_epilogue (bool is_sibcall
)
1592 unsigned int frame_size
;
1593 unsigned int stack_size
;
1594 unsigned int register_mask
;
1595 unsigned int regs_size
;
1597 unsigned HOST_WIDE_INT total_size
;
1599 /* FIXME: We do not support indirect sibcalls at the moment becaause we
1600 cannot guarantee that the register holding the function address is a
1601 call-used register. If it is a call-saved register then the stack
1602 pop instructions generated in the epilogue will corrupt the address
1605 Creating a new call-used-only register class works but then the
1606 reload pass gets stuck because it cannot always find a call-used
1607 register for spilling sibcalls.
1609 The other possible solution is for this pass to scan forward for the
1610 sibcall instruction (if it has been generated) and work out if it
1611 is an indirect sibcall using a call-saved register. If it is then
1612 the address can copied into a call-used register in this epilogue
1613 code and the sibcall instruction modified to use that register. */
1615 if (is_naked_func (NULL_TREE
))
1617 gcc_assert (! is_sibcall
);
1619 /* Naked functions use their own, programmer provided epilogues.
1620 But, in order to keep gcc happy we have to generate some kind of
1622 emit_jump_insn (gen_naked_return ());
1626 rx_get_stack_layout (& low
, & high
, & register_mask
,
1627 & frame_size
, & stack_size
);
1629 total_size
= frame_size
+ stack_size
;
1630 regs_size
= ((high
- low
) + 1) * UNITS_PER_WORD
;
1632 /* See if we are unable to use the special stack frame deconstruct and
1633 return instructions. In most cases we can use them, but the exceptions
1636 - Sibling calling functions deconstruct the frame but do not return to
1637 their caller. Instead they branch to their sibling and allow their
1638 return instruction to return to this function's parent.
1640 - Fast and normal interrupt handling functions have to use special
1641 return instructions.
1643 - Functions where we have pushed a fragmented set of registers into the
1644 call-save area must have the same set of registers popped. */
1646 || is_fast_interrupt_func (NULL_TREE
)
1647 || is_interrupt_func (NULL_TREE
)
1650 /* Cannot use the special instructions - deconstruct by hand. */
1652 gen_safe_add (stack_pointer_rtx
, stack_pointer_rtx
,
1653 GEN_INT (total_size
), false);
1655 if (MUST_SAVE_ACC_REGISTER
)
1657 unsigned int acc_low
, acc_high
;
1659 /* Reverse the saving of the accumulator register onto the stack.
1660 Note we must adjust the saved "low" accumulator value as it
1661 is really the middle 32-bits of the accumulator. */
1664 acc_low
= acc_high
= 0;
1666 for (reg
= 1; reg
< CC_REGNUM
; reg
++)
1667 if (register_mask
& (1 << reg
))
1677 emit_insn (gen_stack_pop (gen_rtx_REG (SImode
, acc_high
)));
1678 emit_insn (gen_stack_pop (gen_rtx_REG (SImode
, acc_low
)));
1684 emit_insn (gen_stack_popm (GEN_INT (2 * UNITS_PER_WORD
),
1685 gen_rx_popm_vector (acc_low
, acc_high
)));
1688 emit_insn (gen_ashlsi3 (gen_rtx_REG (SImode
, acc_low
),
1689 gen_rtx_REG (SImode
, acc_low
),
1691 emit_insn (gen_mvtaclo (gen_rtx_REG (SImode
, acc_low
)));
1692 emit_insn (gen_mvtachi (gen_rtx_REG (SImode
, acc_high
)));
1697 for (reg
= 0; reg
< CC_REGNUM
; reg
++)
1698 if (register_mask
& (1 << reg
))
1699 emit_insn (gen_stack_pop (gen_rtx_REG (SImode
, reg
)));
1704 emit_insn (gen_stack_pop (gen_rtx_REG (SImode
, low
)));
1706 emit_insn (gen_stack_popm (GEN_INT (regs_size
),
1707 gen_rx_popm_vector (low
, high
)));
1710 if (is_fast_interrupt_func (NULL_TREE
))
1712 gcc_assert (! is_sibcall
);
1713 emit_jump_insn (gen_fast_interrupt_return ());
1715 else if (is_interrupt_func (NULL_TREE
))
1717 gcc_assert (! is_sibcall
);
1718 emit_jump_insn (gen_exception_return ());
1720 else if (! is_sibcall
)
1721 emit_jump_insn (gen_simple_return ());
1726 /* If we allocated space on the stack, free it now. */
1729 unsigned HOST_WIDE_INT rtsd_size
;
1731 /* See if we can use the RTSD instruction. */
1732 rtsd_size
= total_size
+ regs_size
;
1733 if (rtsd_size
< 1024 && (rtsd_size
% 4) == 0)
1736 emit_jump_insn (gen_pop_and_return
1737 (GEN_INT (rtsd_size
),
1738 gen_rx_rtsd_vector (rtsd_size
, low
, high
)));
1740 emit_jump_insn (gen_deallocate_and_return (GEN_INT (total_size
)));
1745 gen_safe_add (stack_pointer_rtx
, stack_pointer_rtx
,
1746 GEN_INT (total_size
), false);
1750 emit_jump_insn (gen_pop_and_return (GEN_INT (regs_size
),
1751 gen_rx_rtsd_vector (regs_size
,
1754 emit_jump_insn (gen_simple_return ());
1758 /* Compute the offset (in words) between FROM (arg pointer
1759 or frame pointer) and TO (frame pointer or stack pointer).
1760 See ASCII art comment at the start of rx_expand_prologue
1761 for more information. */
1764 rx_initial_elimination_offset (int from
, int to
)
1768 unsigned int frame_size
;
1769 unsigned int stack_size
;
1772 rx_get_stack_layout (& low
, & high
, & mask
, & frame_size
, & stack_size
);
1774 if (from
== ARG_POINTER_REGNUM
)
1776 /* Extend the computed size of the stack frame to
1777 include the registers pushed in the prologue. */
1779 frame_size
+= ((high
- low
) + 1) * UNITS_PER_WORD
;
1781 frame_size
+= bit_count (mask
) * UNITS_PER_WORD
;
1783 /* Remember to include the return address. */
1784 frame_size
+= 1 * UNITS_PER_WORD
;
1786 if (to
== FRAME_POINTER_REGNUM
)
1789 gcc_assert (to
== STACK_POINTER_REGNUM
);
1790 return frame_size
+ stack_size
;
1793 gcc_assert (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
);
1797 /* Decide if a variable should go into one of the small data sections. */
1800 rx_in_small_data (const_tree decl
)
1805 if (rx_small_data_limit
== 0)
1808 if (TREE_CODE (decl
) != VAR_DECL
)
1811 /* We do not put read-only variables into a small data area because
1812 they would be placed with the other read-only sections, far away
1813 from the read-write data sections, and we only have one small
1815 Similarly commons are placed in the .bss section which might be
1816 far away (and out of alignment with respect to) the .data section. */
1817 if (TREE_READONLY (decl
) || DECL_COMMON (decl
))
1820 section
= DECL_SECTION_NAME (decl
);
1823 const char * const name
= TREE_STRING_POINTER (section
);
1825 return (strcmp (name
, "D_2") == 0) || (strcmp (name
, "B_2") == 0);
1828 size
= int_size_in_bytes (TREE_TYPE (decl
));
1830 return (size
> 0) && (size
<= rx_small_data_limit
);
1833 /* Return a section for X.
1834 The only special thing we do here is to honor small data. */
1837 rx_select_rtx_section (enum machine_mode mode
,
1839 unsigned HOST_WIDE_INT align
)
1841 if (rx_small_data_limit
> 0
1842 && GET_MODE_SIZE (mode
) <= rx_small_data_limit
1843 && align
<= (unsigned HOST_WIDE_INT
) rx_small_data_limit
* BITS_PER_UNIT
)
1844 return sdata_section
;
1846 return default_elf_select_rtx_section (mode
, x
, align
);
1850 rx_select_section (tree decl
,
1852 unsigned HOST_WIDE_INT align
)
1854 if (rx_small_data_limit
> 0)
1856 switch (categorize_decl_for_section (decl
, reloc
))
1858 case SECCAT_SDATA
: return sdata_section
;
1859 case SECCAT_SBSS
: return sbss_section
;
1860 case SECCAT_SRODATA
:
1861 /* Fall through. We do not put small, read only
1862 data into the C_2 section because we are not
1863 using the C_2 section. We do not use the C_2
1864 section because it is located with the other
1865 read-only data sections, far away from the read-write
1866 data sections and we only have one small data
1873 /* If we are supporting the Renesas assembler
1874 we cannot use mergeable sections. */
1875 if (TARGET_AS100_SYNTAX
)
1876 switch (categorize_decl_for_section (decl
, reloc
))
1878 case SECCAT_RODATA_MERGE_CONST
:
1879 case SECCAT_RODATA_MERGE_STR_INIT
:
1880 case SECCAT_RODATA_MERGE_STR
:
1881 return readonly_data_section
;
1887 return default_elf_select_section (decl
, reloc
, align
);
1916 rx_init_builtins (void)
1918 #define ADD_RX_BUILTIN1(UC_NAME, LC_NAME, RET_TYPE, ARG_TYPE) \
1919 add_builtin_function ("__builtin_rx_" LC_NAME, \
1920 build_function_type_list (RET_TYPE##_type_node, \
1921 ARG_TYPE##_type_node, \
1923 RX_BUILTIN_##UC_NAME, \
1924 BUILT_IN_MD, NULL, NULL_TREE)
1926 #define ADD_RX_BUILTIN2(UC_NAME, LC_NAME, RET_TYPE, ARG_TYPE1, ARG_TYPE2) \
1927 add_builtin_function ("__builtin_rx_" LC_NAME, \
1928 build_function_type_list (RET_TYPE##_type_node, \
1929 ARG_TYPE1##_type_node,\
1930 ARG_TYPE2##_type_node,\
1932 RX_BUILTIN_##UC_NAME, \
1933 BUILT_IN_MD, NULL, NULL_TREE)
1935 #define ADD_RX_BUILTIN3(UC_NAME,LC_NAME,RET_TYPE,ARG_TYPE1,ARG_TYPE2,ARG_TYPE3) \
1936 add_builtin_function ("__builtin_rx_" LC_NAME, \
1937 build_function_type_list (RET_TYPE##_type_node, \
1938 ARG_TYPE1##_type_node,\
1939 ARG_TYPE2##_type_node,\
1940 ARG_TYPE3##_type_node,\
1942 RX_BUILTIN_##UC_NAME, \
1943 BUILT_IN_MD, NULL, NULL_TREE)
1945 ADD_RX_BUILTIN1 (BRK
, "brk", void, void);
1946 ADD_RX_BUILTIN1 (CLRPSW
, "clrpsw", void, integer
);
1947 ADD_RX_BUILTIN1 (SETPSW
, "setpsw", void, integer
);
1948 ADD_RX_BUILTIN1 (INT
, "int", void, integer
);
1949 ADD_RX_BUILTIN2 (MACHI
, "machi", void, intSI
, intSI
);
1950 ADD_RX_BUILTIN2 (MACLO
, "maclo", void, intSI
, intSI
);
1951 ADD_RX_BUILTIN2 (MULHI
, "mulhi", void, intSI
, intSI
);
1952 ADD_RX_BUILTIN2 (MULLO
, "mullo", void, intSI
, intSI
);
1953 ADD_RX_BUILTIN1 (MVFACHI
, "mvfachi", intSI
, void);
1954 ADD_RX_BUILTIN1 (MVFACMI
, "mvfacmi", intSI
, void);
1955 ADD_RX_BUILTIN1 (MVTACHI
, "mvtachi", void, intSI
);
1956 ADD_RX_BUILTIN1 (MVTACLO
, "mvtaclo", void, intSI
);
1957 ADD_RX_BUILTIN1 (RMPA
, "rmpa", void, void);
1958 ADD_RX_BUILTIN1 (MVFC
, "mvfc", intSI
, integer
);
1959 ADD_RX_BUILTIN2 (MVTC
, "mvtc", void, integer
, integer
);
1960 ADD_RX_BUILTIN1 (MVTIPL
, "mvtipl", void, integer
);
1961 ADD_RX_BUILTIN1 (RACW
, "racw", void, integer
);
1962 ADD_RX_BUILTIN1 (ROUND
, "round", intSI
, float);
1963 ADD_RX_BUILTIN1 (REVW
, "revw", intSI
, intSI
);
1964 ADD_RX_BUILTIN1 (WAIT
, "wait", void, void);
1968 rx_expand_void_builtin_1_arg (rtx arg
, rtx (* gen_func
)(rtx
), bool reg
)
1970 if (reg
&& ! REG_P (arg
))
1971 arg
= force_reg (SImode
, arg
);
1973 emit_insn (gen_func (arg
));
1979 rx_expand_builtin_mvtc (tree exp
)
1981 rtx arg1
= expand_normal (CALL_EXPR_ARG (exp
, 0));
1982 rtx arg2
= expand_normal (CALL_EXPR_ARG (exp
, 1));
1984 if (! CONST_INT_P (arg1
))
1988 arg2
= force_reg (SImode
, arg2
);
1990 emit_insn (gen_mvtc (arg1
, arg2
));
1996 rx_expand_builtin_mvfc (tree t_arg
, rtx target
)
1998 rtx arg
= expand_normal (t_arg
);
2000 if (! CONST_INT_P (arg
))
2003 if (target
== NULL_RTX
)
2006 if (! REG_P (target
))
2007 target
= force_reg (SImode
, target
);
2009 emit_insn (gen_mvfc (target
, arg
));
2015 rx_expand_builtin_mvtipl (rtx arg
)
2017 /* The RX610 does not support the MVTIPL instruction. */
2018 if (rx_cpu_type
== RX610
)
2021 if (! CONST_INT_P (arg
) || ! IN_RANGE (INTVAL (arg
), 0, (1 << 4) - 1))
2024 emit_insn (gen_mvtipl (arg
));
2030 rx_expand_builtin_mac (tree exp
, rtx (* gen_func
)(rtx
, rtx
))
2032 rtx arg1
= expand_normal (CALL_EXPR_ARG (exp
, 0));
2033 rtx arg2
= expand_normal (CALL_EXPR_ARG (exp
, 1));
2036 arg1
= force_reg (SImode
, arg1
);
2039 arg2
= force_reg (SImode
, arg2
);
2041 emit_insn (gen_func (arg1
, arg2
));
2047 rx_expand_int_builtin_1_arg (rtx arg
,
2049 rtx (* gen_func
)(rtx
, rtx
),
2053 if (!mem_ok
|| ! MEM_P (arg
))
2054 arg
= force_reg (SImode
, arg
);
2056 if (target
== NULL_RTX
|| ! REG_P (target
))
2057 target
= gen_reg_rtx (SImode
);
2059 emit_insn (gen_func (target
, arg
));
2065 rx_expand_int_builtin_0_arg (rtx target
, rtx (* gen_func
)(rtx
))
2067 if (target
== NULL_RTX
|| ! REG_P (target
))
2068 target
= gen_reg_rtx (SImode
);
2070 emit_insn (gen_func (target
));
2076 rx_expand_builtin_round (rtx arg
, rtx target
)
2078 if ((! REG_P (arg
) && ! MEM_P (arg
))
2079 || GET_MODE (arg
) != SFmode
)
2080 arg
= force_reg (SFmode
, arg
);
2082 if (target
== NULL_RTX
|| ! REG_P (target
))
2083 target
= gen_reg_rtx (SImode
);
2085 emit_insn (gen_lrintsf2 (target
, arg
));
2091 valid_psw_flag (rtx op
, const char *which
)
2093 static int mvtc_inform_done
= 0;
2095 if (GET_CODE (op
) == CONST_INT
)
2096 switch (INTVAL (op
))
2098 case 0: case 'c': case 'C':
2099 case 1: case 'z': case 'Z':
2100 case 2: case 's': case 'S':
2101 case 3: case 'o': case 'O':
2102 case 8: case 'i': case 'I':
2103 case 9: case 'u': case 'U':
2107 error ("__builtin_rx_%s takes 'C', 'Z', 'S', 'O', 'I', or 'U'", which
);
2108 if (!mvtc_inform_done
)
2109 error ("use __builtin_rx_mvtc (0, ... ) to write arbitrary values to PSW");
2110 mvtc_inform_done
= 1;
2116 rx_expand_builtin (tree exp
,
2118 rtx subtarget ATTRIBUTE_UNUSED
,
2119 enum machine_mode mode ATTRIBUTE_UNUSED
,
2120 int ignore ATTRIBUTE_UNUSED
)
2122 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
2123 tree arg
= call_expr_nargs (exp
) >= 1 ? CALL_EXPR_ARG (exp
, 0) : NULL_TREE
;
2124 rtx op
= arg
? expand_normal (arg
) : NULL_RTX
;
2125 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
2129 case RX_BUILTIN_BRK
: emit_insn (gen_brk ()); return NULL_RTX
;
2130 case RX_BUILTIN_CLRPSW
:
2131 if (!valid_psw_flag (op
, "clrpsw"))
2133 return rx_expand_void_builtin_1_arg (op
, gen_clrpsw
, false);
2134 case RX_BUILTIN_SETPSW
:
2135 if (!valid_psw_flag (op
, "setpsw"))
2137 return rx_expand_void_builtin_1_arg (op
, gen_setpsw
, false);
2138 case RX_BUILTIN_INT
: return rx_expand_void_builtin_1_arg
2139 (op
, gen_int
, false);
2140 case RX_BUILTIN_MACHI
: return rx_expand_builtin_mac (exp
, gen_machi
);
2141 case RX_BUILTIN_MACLO
: return rx_expand_builtin_mac (exp
, gen_maclo
);
2142 case RX_BUILTIN_MULHI
: return rx_expand_builtin_mac (exp
, gen_mulhi
);
2143 case RX_BUILTIN_MULLO
: return rx_expand_builtin_mac (exp
, gen_mullo
);
2144 case RX_BUILTIN_MVFACHI
: return rx_expand_int_builtin_0_arg
2145 (target
, gen_mvfachi
);
2146 case RX_BUILTIN_MVFACMI
: return rx_expand_int_builtin_0_arg
2147 (target
, gen_mvfacmi
);
2148 case RX_BUILTIN_MVTACHI
: return rx_expand_void_builtin_1_arg
2149 (op
, gen_mvtachi
, true);
2150 case RX_BUILTIN_MVTACLO
: return rx_expand_void_builtin_1_arg
2151 (op
, gen_mvtaclo
, true);
2152 case RX_BUILTIN_RMPA
: emit_insn (gen_rmpa ()); return NULL_RTX
;
2153 case RX_BUILTIN_MVFC
: return rx_expand_builtin_mvfc (arg
, target
);
2154 case RX_BUILTIN_MVTC
: return rx_expand_builtin_mvtc (exp
);
2155 case RX_BUILTIN_MVTIPL
: return rx_expand_builtin_mvtipl (op
);
2156 case RX_BUILTIN_RACW
: return rx_expand_void_builtin_1_arg
2157 (op
, gen_racw
, false);
2158 case RX_BUILTIN_ROUND
: return rx_expand_builtin_round (op
, target
);
2159 case RX_BUILTIN_REVW
: return rx_expand_int_builtin_1_arg
2160 (op
, target
, gen_revw
, false);
2161 case RX_BUILTIN_WAIT
: emit_insn (gen_wait ()); return NULL_RTX
;
2164 internal_error ("bad builtin code");
2171 /* Place an element into a constructor or destructor section.
2172 Like default_ctor_section_asm_out_constructor in varasm.c
2173 except that it uses .init_array (or .fini_array) and it
2174 handles constructor priorities. */
2177 rx_elf_asm_cdtor (rtx symbol
, int priority
, bool is_ctor
)
2181 if (priority
!= DEFAULT_INIT_PRIORITY
)
2185 sprintf (buf
, "%s.%.5u",
2186 is_ctor
? ".init_array" : ".fini_array",
2188 s
= get_section (buf
, SECTION_WRITE
, NULL_TREE
);
2195 switch_to_section (s
);
2196 assemble_align (POINTER_SIZE
);
2197 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
2201 rx_elf_asm_constructor (rtx symbol
, int priority
)
2203 rx_elf_asm_cdtor (symbol
, priority
, /* is_ctor= */true);
2207 rx_elf_asm_destructor (rtx symbol
, int priority
)
2209 rx_elf_asm_cdtor (symbol
, priority
, /* is_ctor= */false);
2212 /* Check "fast_interrupt", "interrupt" and "naked" attributes. */
2215 rx_handle_func_attribute (tree
* node
,
2218 int flags ATTRIBUTE_UNUSED
,
2219 bool * no_add_attrs
)
2221 gcc_assert (DECL_P (* node
));
2222 gcc_assert (args
== NULL_TREE
);
2224 if (TREE_CODE (* node
) != FUNCTION_DECL
)
2226 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
2228 * no_add_attrs
= true;
2231 /* FIXME: We ought to check for conflicting attributes. */
2233 /* FIXME: We ought to check that the interrupt and exception
2234 handler attributes have been applied to void functions. */
2238 /* Table of RX specific attributes. */
2239 const struct attribute_spec rx_attribute_table
[] =
2241 /* Name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
2242 affects_type_identity. */
2243 { "fast_interrupt", 0, 0, true, false, false, rx_handle_func_attribute
,
2245 { "interrupt", 0, 0, true, false, false, rx_handle_func_attribute
,
2247 { "naked", 0, 0, true, false, false, rx_handle_func_attribute
,
2249 { NULL
, 0, 0, false, false, false, NULL
, false }
2252 /* Extra processing for target specific command line options. */
2255 rx_handle_option (struct gcc_options
*opts
, struct gcc_options
*opts_set
,
2256 const struct cl_decoded_option
*decoded
,
2257 location_t loc ATTRIBUTE_UNUSED
)
2259 size_t code
= decoded
->opt_index
;
2260 const char *arg
= decoded
->arg
;
2261 int value
= decoded
->value
;
2263 gcc_assert (opts
== &global_options
);
2264 gcc_assert (opts_set
== &global_options_set
);
2268 case OPT_mint_register_
:
2272 fixed_regs
[10] = call_used_regs
[10] = 1;
2275 fixed_regs
[11] = call_used_regs
[11] = 1;
2278 fixed_regs
[12] = call_used_regs
[12] = 1;
2281 fixed_regs
[13] = call_used_regs
[13] = 1;
2290 case OPT_mmax_constant_size_
:
2291 /* Make sure that the -mmax-constant_size option is in range. */
2292 return value
>= 0 && value
<= 4;
2295 if (strcasecmp (arg
, "RX610") == 0)
2296 rx_cpu_type
= RX610
;
2297 else if (strcasecmp (arg
, "RX200") == 0)
2299 target_flags
|= MASK_NO_USE_FPU
;
2300 rx_cpu_type
= RX200
;
2302 else if (strcasecmp (arg
, "RX600") != 0)
2303 warning (0, "unrecognized argument '%s' to -mcpu= option", arg
);
2307 if (rx_cpu_type
== RX200
)
2308 error ("the RX200 cpu does not have FPU hardware");
2318 /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE. */
2321 rx_override_options_after_change (void)
2323 static bool first_time
= TRUE
;
2327 /* If this is the first time through and the user has not disabled
2328 the use of RX FPU hardware then enable -ffinite-math-only,
2329 since the FPU instructions do not support NaNs and infinities. */
2331 flag_finite_math_only
= 1;
2337 /* Alert the user if they are changing the optimization options
2338 to use IEEE compliant floating point arithmetic with RX FPU insns. */
2340 && !flag_finite_math_only
)
2341 warning (0, "RX FPU instructions do not support NaNs and infinities");
2346 rx_option_override (void)
2348 /* This target defaults to strict volatile bitfields. */
2349 if (flag_strict_volatile_bitfields
< 0)
2350 flag_strict_volatile_bitfields
= 1;
2352 rx_override_options_after_change ();
2355 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
2356 static const struct default_options rx_option_optimization_table
[] =
2358 { OPT_LEVELS_1_PLUS
, OPT_fomit_frame_pointer
, NULL
, 1 },
2359 { OPT_LEVELS_NONE
, 0, NULL
, 0 }
2364 rx_allocate_stack_slots_for_args (void)
2366 /* Naked functions should not allocate stack slots for arguments. */
2367 return ! is_naked_func (NULL_TREE
);
2371 rx_func_attr_inlinable (const_tree decl
)
2373 return ! is_fast_interrupt_func (decl
)
2374 && ! is_interrupt_func (decl
)
2375 && ! is_naked_func (decl
);
2378 /* Return nonzero if it is ok to make a tail-call to DECL,
2379 a function_decl or NULL if this is an indirect call, using EXP */
2382 rx_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
2384 /* Do not allow indirect tailcalls. The
2385 sibcall patterns do not support them. */
2389 /* Never tailcall from inside interrupt handlers or naked functions. */
2390 if (is_fast_interrupt_func (NULL_TREE
)
2391 || is_interrupt_func (NULL_TREE
)
2392 || is_naked_func (NULL_TREE
))
2399 rx_file_start (void)
2401 if (! TARGET_AS100_SYNTAX
)
2402 default_file_start ();
2406 rx_is_ms_bitfield_layout (const_tree record_type ATTRIBUTE_UNUSED
)
2408 /* The packed attribute overrides the MS behaviour. */
2409 return ! TYPE_PACKED (record_type
);
2412 /* Returns true if X a legitimate constant for an immediate
2413 operand on the RX. X is already known to satisfy CONSTANT_P. */
2416 rx_is_legitimate_constant (rtx x
)
2418 switch (GET_CODE (x
))
2423 if (GET_CODE (x
) == PLUS
)
2425 if (! CONST_INT_P (XEXP (x
, 1)))
2428 /* GCC would not pass us CONST_INT + CONST_INT so we
2429 know that we have {SYMBOL|LABEL} + CONST_INT. */
2431 gcc_assert (! CONST_INT_P (x
));
2434 switch (GET_CODE (x
))
2441 return XINT (x
, 1) == UNSPEC_CONST
;
2444 /* FIXME: Can this ever happen ? */
2454 return (rx_max_constant_size
== 0 || rx_max_constant_size
== 4);
2458 gcc_assert (CONST_INT_P (x
));
2462 return ok_for_max_constant (INTVAL (x
));
2466 rx_address_cost (rtx addr
, bool speed
)
2470 if (GET_CODE (addr
) != PLUS
)
2471 return COSTS_N_INSNS (1);
2476 if (REG_P (a
) && REG_P (b
))
2477 /* Try to discourage REG+REG addressing as it keeps two registers live. */
2478 return COSTS_N_INSNS (4);
2481 /* [REG+OFF] is just as fast as [REG]. */
2482 return COSTS_N_INSNS (1);
2485 && ((INTVAL (b
) > 128) || INTVAL (b
) < -127))
2486 /* Try to discourage REG + <large OFF> when optimizing for size. */
2487 return COSTS_N_INSNS (2);
2489 return COSTS_N_INSNS (1);
2493 rx_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
2495 /* We can always eliminate to the frame pointer.
2496 We can eliminate to the stack pointer unless a frame
2497 pointer is needed. */
2499 return to
== FRAME_POINTER_REGNUM
2500 || ( to
== STACK_POINTER_REGNUM
&& ! frame_pointer_needed
);
2505 rx_trampoline_template (FILE * file
)
2507 /* Output assembler code for a block containing the constant
2508 part of a trampoline, leaving space for the variable parts.
2510 On the RX, (where r8 is the static chain regnum) the trampoline
2513 mov #<static chain value>, r8
2514 mov #<function's address>, r9
2517 In big-endian-data-mode however instructions are read into the CPU
2518 4 bytes at a time. These bytes are then swapped around before being
2519 passed to the decoder. So...we must partition our trampoline into
2520 4 byte packets and swap these packets around so that the instruction
2521 reader will reverse the process. But, in order to avoid splitting
2522 the 32-bit constants across these packet boundaries, (making inserting
2523 them into the constructed trampoline very difficult) we have to pad the
2524 instruction sequence with NOP insns. ie:
2536 if (! TARGET_BIG_ENDIAN_DATA
)
2538 asm_fprintf (file
, "\tmov.L\t#0deadbeefH, r%d\n", STATIC_CHAIN_REGNUM
);
2539 asm_fprintf (file
, "\tmov.L\t#0deadbeefH, r%d\n", TRAMPOLINE_TEMP_REGNUM
);
2540 asm_fprintf (file
, "\tjmp\tr%d\n", TRAMPOLINE_TEMP_REGNUM
);
2544 char r8
= '0' + STATIC_CHAIN_REGNUM
;
2545 char r9
= '0' + TRAMPOLINE_TEMP_REGNUM
;
2547 if (TARGET_AS100_SYNTAX
)
2549 asm_fprintf (file
, "\t.BYTE 0%c2H, 0fbH, 003H, 003H\n", r8
);
2550 asm_fprintf (file
, "\t.BYTE 0deH, 0adH, 0beH, 0efH\n");
2551 asm_fprintf (file
, "\t.BYTE 0%c2H, 0fbH, 003H, 003H\n", r9
);
2552 asm_fprintf (file
, "\t.BYTE 0deH, 0adH, 0beH, 0efH\n");
2553 asm_fprintf (file
, "\t.BYTE 003H, 003H, 00%cH, 07fH\n", r9
);
2557 asm_fprintf (file
, "\t.byte 0x%c2, 0xfb, 0x03, 0x03\n", r8
);
2558 asm_fprintf (file
, "\t.byte 0xde, 0xad, 0xbe, 0xef\n");
2559 asm_fprintf (file
, "\t.byte 0x%c2, 0xfb, 0x03, 0x03\n", r9
);
2560 asm_fprintf (file
, "\t.byte 0xde, 0xad, 0xbe, 0xef\n");
2561 asm_fprintf (file
, "\t.byte 0x03, 0x03, 0x0%c, 0x7f\n", r9
);
2567 rx_trampoline_init (rtx tramp
, tree fndecl
, rtx chain
)
2569 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
2571 emit_block_move (tramp
, assemble_trampoline_template (),
2572 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
2574 if (TARGET_BIG_ENDIAN_DATA
)
2576 emit_move_insn (adjust_address (tramp
, SImode
, 4), chain
);
2577 emit_move_insn (adjust_address (tramp
, SImode
, 12), fnaddr
);
2581 emit_move_insn (adjust_address (tramp
, SImode
, 2), chain
);
2582 emit_move_insn (adjust_address (tramp
, SImode
, 6 + 2), fnaddr
);
2587 rx_memory_move_cost (enum machine_mode mode
, reg_class_t regclass
, bool in
)
2589 return 2 + memory_move_secondary_cost (mode
, regclass
, in
);
2592 /* Convert a CC_MODE to the set of flags that it represents. */
2595 flags_from_mode (enum machine_mode mode
)
2600 return CC_FLAG_S
| CC_FLAG_Z
;
2602 return CC_FLAG_S
| CC_FLAG_Z
| CC_FLAG_O
;
2604 return CC_FLAG_S
| CC_FLAG_Z
| CC_FLAG_C
;
2606 return CC_FLAG_S
| CC_FLAG_Z
| CC_FLAG_O
| CC_FLAG_C
;
2614 /* Convert a set of flags to a CC_MODE that can implement it. */
2616 static enum machine_mode
2617 mode_from_flags (unsigned int f
)
2628 else if (f
& CC_FLAG_C
)
2634 /* Convert an RTX_CODE to the set of flags needed to implement it.
2635 This assumes an integer comparison. */
2638 flags_from_code (enum rtx_code code
)
2647 return CC_FLAG_S
| CC_FLAG_O
| CC_FLAG_Z
;
2653 return CC_FLAG_C
| CC_FLAG_Z
;
2662 /* Return a CC_MODE of which both M1 and M2 are subsets. */
2664 static enum machine_mode
2665 rx_cc_modes_compatible (enum machine_mode m1
, enum machine_mode m2
)
2669 /* Early out for identical modes. */
2673 /* There's no valid combination for FP vs non-FP. */
2674 f
= flags_from_mode (m1
) | flags_from_mode (m2
);
2678 /* Otherwise, see what mode can implement all the flags. */
2679 return mode_from_flags (f
);
2682 /* Return the minimal CC mode needed to implement (CMP_CODE X Y). */
2685 rx_select_cc_mode (enum rtx_code cmp_code
, rtx x
, rtx y
)
2687 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2690 if (y
!= const0_rtx
)
2693 return mode_from_flags (flags_from_code (cmp_code
));
2696 /* Split the conditional branch. Emit (COMPARE C1 C2) into CC_REG with
2697 CC_MODE, and use that in branches based on that compare. */
2700 rx_split_cbranch (enum machine_mode cc_mode
, enum rtx_code cmp1
,
2701 rtx c1
, rtx c2
, rtx label
)
2705 flags
= gen_rtx_REG (cc_mode
, CC_REG
);
2706 x
= gen_rtx_COMPARE (cc_mode
, c1
, c2
);
2707 x
= gen_rtx_SET (VOIDmode
, flags
, x
);
2710 x
= gen_rtx_fmt_ee (cmp1
, VOIDmode
, flags
, const0_rtx
);
2711 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, x
, label
, pc_rtx
);
2712 x
= gen_rtx_SET (VOIDmode
, pc_rtx
, x
);
2716 /* A helper function for matching parallels that set the flags. */
2719 rx_match_ccmode (rtx insn
, enum machine_mode cc_mode
)
2722 enum machine_mode flags_mode
;
2724 gcc_checking_assert (XVECLEN (PATTERN (insn
), 0) == 2);
2726 op1
= XVECEXP (PATTERN (insn
), 0, 1);
2727 gcc_checking_assert (GET_CODE (SET_SRC (op1
)) == COMPARE
);
2729 flags
= SET_DEST (op1
);
2730 flags_mode
= GET_MODE (flags
);
2732 if (GET_MODE (SET_SRC (op1
)) != flags_mode
)
2734 if (GET_MODE_CLASS (flags_mode
) != MODE_CC
)
2737 /* Ensure that the mode of FLAGS is compatible with CC_MODE. */
2738 if (flags_from_mode (flags_mode
) & ~flags_from_mode (cc_mode
))
2745 #undef TARGET_FUNCTION_VALUE
2746 #define TARGET_FUNCTION_VALUE rx_function_value
2748 #undef TARGET_RETURN_IN_MSB
2749 #define TARGET_RETURN_IN_MSB rx_return_in_msb
2751 #undef TARGET_IN_SMALL_DATA_P
2752 #define TARGET_IN_SMALL_DATA_P rx_in_small_data
2754 #undef TARGET_RETURN_IN_MEMORY
2755 #define TARGET_RETURN_IN_MEMORY rx_return_in_memory
2757 #undef TARGET_HAVE_SRODATA_SECTION
2758 #define TARGET_HAVE_SRODATA_SECTION true
2760 #undef TARGET_ASM_SELECT_RTX_SECTION
2761 #define TARGET_ASM_SELECT_RTX_SECTION rx_select_rtx_section
2763 #undef TARGET_ASM_SELECT_SECTION
2764 #define TARGET_ASM_SELECT_SECTION rx_select_section
2766 #undef TARGET_INIT_BUILTINS
2767 #define TARGET_INIT_BUILTINS rx_init_builtins
2769 #undef TARGET_EXPAND_BUILTIN
2770 #define TARGET_EXPAND_BUILTIN rx_expand_builtin
2772 #undef TARGET_ASM_CONSTRUCTOR
2773 #define TARGET_ASM_CONSTRUCTOR rx_elf_asm_constructor
2775 #undef TARGET_ASM_DESTRUCTOR
2776 #define TARGET_ASM_DESTRUCTOR rx_elf_asm_destructor
2778 #undef TARGET_STRUCT_VALUE_RTX
2779 #define TARGET_STRUCT_VALUE_RTX rx_struct_value_rtx
2781 #undef TARGET_ATTRIBUTE_TABLE
2782 #define TARGET_ATTRIBUTE_TABLE rx_attribute_table
2784 #undef TARGET_ASM_FILE_START
2785 #define TARGET_ASM_FILE_START rx_file_start
2787 #undef TARGET_MS_BITFIELD_LAYOUT_P
2788 #define TARGET_MS_BITFIELD_LAYOUT_P rx_is_ms_bitfield_layout
2790 #undef TARGET_LEGITIMATE_ADDRESS_P
2791 #define TARGET_LEGITIMATE_ADDRESS_P rx_is_legitimate_address
2793 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
2794 #define TARGET_MODE_DEPENDENT_ADDRESS_P rx_mode_dependent_address_p
2796 #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
2797 #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS rx_allocate_stack_slots_for_args
2799 #undef TARGET_ASM_FUNCTION_PROLOGUE
2800 #define TARGET_ASM_FUNCTION_PROLOGUE rx_output_function_prologue
2802 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
2803 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P rx_func_attr_inlinable
2805 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
2806 #define TARGET_FUNCTION_OK_FOR_SIBCALL rx_function_ok_for_sibcall
2808 #undef TARGET_FUNCTION_ARG
2809 #define TARGET_FUNCTION_ARG rx_function_arg
2811 #undef TARGET_FUNCTION_ARG_ADVANCE
2812 #define TARGET_FUNCTION_ARG_ADVANCE rx_function_arg_advance
2814 #undef TARGET_FUNCTION_ARG_BOUNDARY
2815 #define TARGET_FUNCTION_ARG_BOUNDARY rx_function_arg_boundary
2817 #undef TARGET_SET_CURRENT_FUNCTION
2818 #define TARGET_SET_CURRENT_FUNCTION rx_set_current_function
2820 #undef TARGET_HANDLE_OPTION
2821 #define TARGET_HANDLE_OPTION rx_handle_option
2823 #undef TARGET_ASM_INTEGER
2824 #define TARGET_ASM_INTEGER rx_assemble_integer
2826 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
2827 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
2829 #undef TARGET_MAX_ANCHOR_OFFSET
2830 #define TARGET_MAX_ANCHOR_OFFSET 32
2832 #undef TARGET_ADDRESS_COST
2833 #define TARGET_ADDRESS_COST rx_address_cost
2835 #undef TARGET_CAN_ELIMINATE
2836 #define TARGET_CAN_ELIMINATE rx_can_eliminate
2838 #undef TARGET_CONDITIONAL_REGISTER_USAGE
2839 #define TARGET_CONDITIONAL_REGISTER_USAGE rx_conditional_register_usage
2841 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
2842 #define TARGET_ASM_TRAMPOLINE_TEMPLATE rx_trampoline_template
2844 #undef TARGET_TRAMPOLINE_INIT
2845 #define TARGET_TRAMPOLINE_INIT rx_trampoline_init
2847 #undef TARGET_PRINT_OPERAND
2848 #define TARGET_PRINT_OPERAND rx_print_operand
2850 #undef TARGET_PRINT_OPERAND_ADDRESS
2851 #define TARGET_PRINT_OPERAND_ADDRESS rx_print_operand_address
2853 #undef TARGET_CC_MODES_COMPATIBLE
2854 #define TARGET_CC_MODES_COMPATIBLE rx_cc_modes_compatible
2856 #undef TARGET_MEMORY_MOVE_COST
2857 #define TARGET_MEMORY_MOVE_COST rx_memory_move_cost
2859 #undef TARGET_OPTION_OVERRIDE
2860 #define TARGET_OPTION_OVERRIDE rx_option_override
2862 #undef TARGET_OPTION_OPTIMIZATION_TABLE
2863 #define TARGET_OPTION_OPTIMIZATION_TABLE rx_option_optimization_table
2865 #undef TARGET_PROMOTE_FUNCTION_MODE
2866 #define TARGET_PROMOTE_FUNCTION_MODE rx_promote_function_mode
2868 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
2869 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE rx_override_options_after_change
2871 #undef TARGET_EXCEPT_UNWIND_INFO
2872 #define TARGET_EXCEPT_UNWIND_INFO sjlj_except_unwind_info
2874 #undef TARGET_FLAGS_REGNUM
2875 #define TARGET_FLAGS_REGNUM CC_REG
2877 struct gcc_target targetm
= TARGET_INITIALIZER
;
2879 /* #include "gt-rx.h" */