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1 /* GCC backend definitions for the Renesas RX processor.
2 Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc.
3 Contributed by Red Hat.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20 \f
21
22 #define TARGET_CPU_CPP_BUILTINS() \
23 do \
24 { \
25 builtin_define ("__RX__"); \
26 builtin_assert ("cpu=RX"); \
27 if (rx_cpu_type == RX610) \
28 { \
29 builtin_define ("__RX610__"); \
30 builtin_assert ("machine=RX610"); \
31 } \
32 else \
33 builtin_assert ("machine=RX600"); \
34 \
35 if (TARGET_BIG_ENDIAN_DATA) \
36 builtin_define ("__RX_BIG_ENDIAN__"); \
37 else \
38 builtin_define ("__RX_LITTLE_ENDIAN__");\
39 \
40 if (TARGET_64BIT_DOUBLES) \
41 builtin_define ("__RX_64BIT_DOUBLES__");\
42 else \
43 builtin_define ("__RX_32BIT_DOUBLES__");\
44 \
45 if (ALLOW_RX_FPU_INSNS) \
46 builtin_define ("__RX_FPU_INSNS__"); \
47 \
48 if (TARGET_AS100_SYNTAX) \
49 builtin_define ("__RX_AS100_SYNTAX__"); \
50 else \
51 builtin_define ("__RX_GAS_SYNTAX__"); \
52 } \
53 while (0)
54
55 enum rx_cpu_types
56 {
57 RX600,
58 RX610,
59 RX200
60 };
61
62 extern enum rx_cpu_types rx_cpu_type;
63
64 #undef CC1_SPEC
65 #define CC1_SPEC "\
66 %{mas100-syntax:%{gdwarf*:%e-mas100-syntax is incompatible with -gdwarf}} \
67 %{mcpu=rx200:%{fpu:%erx200 cpu does not have FPU hardware}}"
68
69 #undef STARTFILE_SPEC
70 #define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:crt0.o%s} crtbegin.o%s"
71
72 #undef ENDFILE_SPEC
73 #define ENDFILE_SPEC "crtend.o%s crtn.o%s"
74
75 #undef ASM_SPEC
76 #define ASM_SPEC "\
77 %{mbig-endian-data:-mbig-endian-data} \
78 %{m64bit-doubles:-m64bit-doubles} \
79 %{!m64bit-doubles:-m32bit-doubles} \
80 %{msmall-data-limit*:-msmall-data-limit} \
81 %{mrelax:-relax} \
82 "
83
84 #undef LIB_SPEC
85 #define LIB_SPEC " \
86 --start-group \
87 -lc \
88 %{msim*:-lsim}%{!msim*:-lnosys} \
89 %{fprofile-arcs|fprofile-generate|coverage:-lgcov} \
90 --end-group \
91 %{!T*: %{msim*:%Trx-sim.ld}%{!msim*:%Trx.ld}} \
92 "
93
94 #undef LINK_SPEC
95 #define LINK_SPEC "%{mbig-endian-data:--oformat elf32-rx-be} %{mrelax:-relax}"
96 \f
97
98 #define BITS_BIG_ENDIAN 0
99 #define BYTES_BIG_ENDIAN TARGET_BIG_ENDIAN_DATA
100 #define WORDS_BIG_ENDIAN TARGET_BIG_ENDIAN_DATA
101
102 #define UNITS_PER_WORD 4
103
104 #define INT_TYPE_SIZE 32
105 #define LONG_TYPE_SIZE 32
106 #define LONG_LONG_TYPE_SIZE 64
107
108 #define FLOAT_TYPE_SIZE 32
109 #define DOUBLE_TYPE_SIZE (TARGET_64BIT_DOUBLES ? 64 : 32)
110 #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE
111
112 #ifdef __RX_32BIT_DOUBLES__
113 #define LIBGCC2_HAS_DF_MODE 0
114 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 32
115 #else
116 #define LIBGCC2_HAS_DF_MODE 1
117 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
118 #endif
119
120 #define DEFAULT_SIGNED_CHAR 0
121
122 #define STRICT_ALIGNMENT 1
123 #define FUNCTION_BOUNDARY 8
124 #define BIGGEST_ALIGNMENT 32
125 #define STACK_BOUNDARY 32
126 #define PARM_BOUNDARY 8
127
128 #define STACK_GROWS_DOWNWARD 1
129 #define FRAME_GROWS_DOWNWARD 0
130 #define FIRST_PARM_OFFSET(FNDECL) 0
131
132 #define MAX_REGS_PER_ADDRESS 2
133
134 #define Pmode SImode
135 #define POINTER_SIZE 32
136 #undef SIZE_TYPE
137 #define SIZE_TYPE "long unsigned int"
138 #undef PTRDIFF_TYPE
139 #define PTRDIFF_TYPE "long int"
140 #define POINTERS_EXTEND_UNSIGNED 1
141 #define FUNCTION_MODE QImode
142 #define CASE_VECTOR_MODE Pmode
143 #define WORD_REGISTER_OPERATIONS 1
144 #define HAS_LONG_COND_BRANCH 0
145 #define HAS_LONG_UNCOND_BRANCH 0
146
147 #define MOVE_MAX 4
148 #define STARTING_FRAME_OFFSET 0
149
150 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
151
152 #define LEGITIMATE_CONSTANT_P(X) rx_is_legitimate_constant (X)
153
154 #define HAVE_PRE_DECCREMENT 1
155 #define HAVE_POST_INCREMENT 1
156
157 #define MOVE_RATIO(SPEED) ((SPEED) ? 4 : 2)
158 #define SLOW_BYTE_ACCESS 1
159
160 #define STORE_FLAG_VALUE 1
161 #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
162 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
163 \f
164 enum reg_class
165 {
166 NO_REGS, /* No registers in set. */
167 GR_REGS, /* Integer registers. */
168 ALL_REGS, /* All registers. */
169 LIM_REG_CLASSES /* Max value + 1. */
170 };
171
172 #define REG_CLASS_NAMES \
173 { \
174 "NO_REGS", \
175 "GR_REGS", \
176 "ALL_REGS" \
177 }
178
179 #define REG_CLASS_CONTENTS \
180 { \
181 { 0x00000000 }, /* No registers, */ \
182 { 0x0000ffff }, /* Integer registers. */ \
183 { 0x0000ffff } /* All registers. */ \
184 }
185
186 #define IRA_COVER_CLASSES \
187 { \
188 GR_REGS, LIM_REG_CLASSES \
189 }
190
191 #define SMALL_REGISTER_CLASSES 0
192 #define N_REG_CLASSES (int) LIM_REG_CLASSES
193 #define CLASS_MAX_NREGS(CLASS, MODE) ((GET_MODE_SIZE (MODE) \
194 + UNITS_PER_WORD - 1) \
195 / UNITS_PER_WORD)
196
197 #define GENERAL_REGS GR_REGS
198 #define BASE_REG_CLASS GR_REGS
199 #define INDEX_REG_CLASS GR_REGS
200
201 #define FIRST_PSEUDO_REGISTER 17
202
203 #define REGNO_REG_CLASS(REGNO) ((REGNO) < FIRST_PSEUDO_REGISTER \
204 ? GR_REGS : NO_REGS)
205
206 #define STACK_POINTER_REGNUM 0
207 #define FUNC_RETURN_REGNUM 1
208 #define FRAME_POINTER_REGNUM 6
209 #define ARG_POINTER_REGNUM 7
210 #define STATIC_CHAIN_REGNUM 8
211 #define TRAMPOLINE_TEMP_REGNUM 9
212 #define STRUCT_VAL_REGNUM 15
213 #define CC_REGNUM 16
214
215 /* This is the register which is used to hold the address of the start
216 of the small data area, if that feature is being used. Note - this
217 register must not be call_used because otherwise library functions
218 that are compiled without small data support might clobber it.
219
220 FIXME: The function gcc/config/rx/rx.c:rx_gen_move_template() has a
221 built in copy of this register's name, rather than constructing the
222 name from this #define. */
223 #define GP_BASE_REGNUM 13
224
225 #define ELIMINABLE_REGS \
226 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
227 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
228 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
229
230 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
231 (OFFSET) = rx_initial_elimination_offset ((FROM), (TO))
232
233
234 #define FUNCTION_ARG_REGNO_P(N) (((N) >= 1) && ((N) <= 4))
235 #define FUNCTION_VALUE_REGNO_P(N) ((N) == FUNC_RETURN_REGNUM)
236 #define DEFAULT_PCC_STRUCT_RETURN 0
237
238 #define FIXED_REGISTERS \
239 { \
240 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
241 }
242
243 #define CALL_USED_REGISTERS \
244 { \
245 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1 \
246 }
247
248 #define CONDITIONAL_REGISTER_USAGE \
249 rx_conditional_register_usage ()
250
251 #define LIBCALL_VALUE(MODE) \
252 gen_rtx_REG (((GET_MODE_CLASS (MODE) != MODE_INT \
253 || GET_MODE_SIZE (MODE) >= 4) \
254 ? (MODE) \
255 : SImode), \
256 FUNC_RETURN_REGNUM)
257
258 /* Order of allocation of registers. */
259
260 #define REG_ALLOC_ORDER \
261 { 7, 10, 11, 12, 13, 14, 4, 3, 2, 1, 9, 8, 6, 5, 15 \
262 }
263
264 #define REGNO_IN_RANGE(REGNO, MIN, MAX) \
265 (IN_RANGE ((REGNO), (MIN), (MAX)) \
266 || (reg_renumber != NULL \
267 && reg_renumber[(REGNO)] >= (MIN) \
268 && reg_renumber[(REGNO)] <= (MAX)))
269
270 #ifdef REG_OK_STRICT
271 #define REGNO_OK_FOR_BASE_P(regno) REGNO_IN_RANGE (regno, 0, 15)
272 #else
273 #define REGNO_OK_FOR_BASE_P(regno) 1
274 #endif
275
276 #define REGNO_OK_FOR_INDEX_P(regno) REGNO_OK_FOR_BASE_P (regno)
277
278 #define RTX_OK_FOR_BASE(X, STRICT) \
279 ((STRICT) ? \
280 ( (REG_P (X) \
281 && REGNO_IN_RANGE (REGNO (X), 0, 15)) \
282 || (GET_CODE (X) == SUBREG \
283 && REG_P (SUBREG_REG (X)) \
284 && REGNO_IN_RANGE (REGNO (SUBREG_REG (X)), 0, 15))) \
285 : \
286 ( (REG_P (X) \
287 || (GET_CODE (X) == SUBREG \
288 && REG_P (SUBREG_REG (X))))))
289
290 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
291 do \
292 { \
293 if (rx_is_mode_dependent_addr (ADDR)) \
294 goto LABEL; \
295 } \
296 while (0)
297 \f
298
299 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \
300 ((COUNT) == 0 \
301 ? gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, arg_pointer_rtx, GEN_INT (-4))) \
302 : NULL_RTX)
303
304 #define INCOMING_RETURN_ADDR_RTX gen_rtx_MEM (Pmode, stack_pointer_rtx)
305
306 #define ACCUMULATE_OUTGOING_ARGS 1
307
308 typedef unsigned int CUMULATIVE_ARGS;
309
310 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
311 (CUM) = 0
312
313 \f
314 #define TRAMPOLINE_SIZE (! TARGET_BIG_ENDIAN_DATA ? 14 : 20)
315 #define TRAMPOLINE_ALIGNMENT 32
316 \f
317 #define NO_PROFILE_COUNTERS 1
318 #define PROFILE_BEFORE_PROLOGUE 1
319
320 #define FUNCTION_PROFILER(FILE, LABELNO) \
321 fprintf (FILE, "\tbsr\t__mcount\n");
322 \f
323
324 #define HARD_REGNO_NREGS(REGNO, MODE) CLASS_MAX_NREGS (0, MODE)
325
326 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
327 REGNO_REG_CLASS (REGNO) == GR_REGS
328
329 #define MODES_TIEABLE_P(MODE1, MODE2) \
330 ( ( GET_MODE_CLASS (MODE1) == MODE_FLOAT \
331 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
332 == ( GET_MODE_CLASS (MODE2) == MODE_FLOAT \
333 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
334 \f
335
336 #define REGISTER_NAMES \
337 { \
338 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
339 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", "cc" \
340 }
341
342 #define ADDITIONAL_REGISTER_NAMES \
343 { \
344 { "sp", STACK_POINTER_REGNUM } \
345 , { "fp", FRAME_POINTER_REGNUM } \
346 , { "arg", ARG_POINTER_REGNUM } \
347 , { "chain", STATIC_CHAIN_REGNUM } \
348 }
349
350 #define DATA_SECTION_ASM_OP \
351 (TARGET_AS100_SYNTAX ? "\t.SECTION D,DATA" \
352 : "\t.section D,\"aw\",@progbits\n\t.p2align 2")
353
354 #define SDATA_SECTION_ASM_OP \
355 (TARGET_AS100_SYNTAX ? "\t.SECTION D_2,DATA,ALIGN=2" \
356 : "\t.section D_2,\"aw\",@progbits\n\t.p2align 1")
357
358 #undef READONLY_DATA_SECTION_ASM_OP
359 #define READONLY_DATA_SECTION_ASM_OP \
360 (TARGET_AS100_SYNTAX ? "\t.SECTION C,ROMDATA,ALIGN=4" \
361 : "\t.section C,\"a\",@progbits\n\t.p2align 2")
362
363 #define BSS_SECTION_ASM_OP \
364 (TARGET_AS100_SYNTAX ? "\t.SECTION B,DATA,ALIGN=4" \
365 : "\t.section B,\"w\",@nobits\n\t.p2align 2")
366
367 #define SBSS_SECTION_ASM_OP \
368 (TARGET_AS100_SYNTAX ? "\t.SECTION B_2,DATA,ALIGN=2" \
369 : "\t.section B_2,\"w\",@nobits\n\t.p2align 1")
370
371 /* The following definitions are conditional depending upon whether the
372 compiler is being built or crtstuff.c is being compiled by the built
373 compiler. */
374 #if defined CRT_BEGIN || defined CRT_END
375 # ifdef __RX_AS100_SYNTAX
376 # define TEXT_SECTION_ASM_OP "\t.SECTION P,CODE"
377 # define CTORS_SECTION_ASM_OP "\t.SECTION init_array,CODE"
378 # define DTORS_SECTION_ASM_OP "\t.SECTION fini_array,CODE"
379 # define INIT_ARRAY_SECTION_ASM_OP "\t.SECTION init_array,CODE"
380 # define FINI_ARRAY_SECTION_ASM_OP "\t.SECTION fini_array,CODE"
381 # else
382 # define TEXT_SECTION_ASM_OP "\t.section P,\"ax\""
383 # define CTORS_SECTION_ASM_OP \
384 "\t.section\t.init_array,\"aw\",@init_array"
385 # define DTORS_SECTION_ASM_OP \
386 "\t.section\t.fini_array,\"aw\",@fini_array"
387 # define INIT_ARRAY_SECTION_ASM_OP \
388 "\t.section\t.init_array,\"aw\",@init_array"
389 # define FINI_ARRAY_SECTION_ASM_OP \
390 "\t.section\t.fini_array,\"aw\",@fini_array"
391 # endif
392 #else
393 # define TEXT_SECTION_ASM_OP \
394 (TARGET_AS100_SYNTAX ? "\t.SECTION P,CODE" : "\t.section P,\"ax\"")
395
396 # define CTORS_SECTION_ASM_OP \
397 (TARGET_AS100_SYNTAX ? "\t.SECTION init_array,CODE" \
398 : "\t.section\t.init_array,\"aw\",@init_array")
399
400 # define DTORS_SECTION_ASM_OP \
401 (TARGET_AS100_SYNTAX ? "\t.SECTION fini_array,CODE" \
402 : "\t.section\t.fini_array,\"aw\",@fini_array")
403
404 # define INIT_ARRAY_SECTION_ASM_OP \
405 (TARGET_AS100_SYNTAX ? "\t.SECTION init_array,CODE" \
406 : "\t.section\t.init_array,\"aw\",@init_array")
407
408 # define FINI_ARRAY_SECTION_ASM_OP \
409 (TARGET_AS100_SYNTAX ? "\t.SECTION fini_array,CODE" \
410 : "\t.section\t.fini_array,\"aw\",@fini_array")
411 #endif
412
413 #define GLOBAL_ASM_OP \
414 (TARGET_AS100_SYNTAX ? "\t.GLB\t" : "\t.global\t")
415 #define ASM_COMMENT_START " ;"
416 #define ASM_APP_ON ""
417 #define ASM_APP_OFF ""
418 #define LOCAL_LABEL_PREFIX "L"
419 #undef USER_LABEL_PREFIX
420 #define USER_LABEL_PREFIX "_"
421
422 #define ASM_OUTPUT_ALIGN(STREAM, LOG) \
423 do \
424 { \
425 if ((LOG) == 0) \
426 break; \
427 if (TARGET_AS100_SYNTAX) \
428 { \
429 if ((LOG) >= 2) \
430 fprintf (STREAM, "\t.ALIGN 4\t; %d alignment actually requested\n", 1 << (LOG)); \
431 else \
432 fprintf (STREAM, "\t.ALIGN 2\n"); \
433 } \
434 else \
435 fprintf (STREAM, "\t.balign %d\n", 1 << (LOG)); \
436 } \
437 while (0)
438
439 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
440 fprintf (FILE, TARGET_AS100_SYNTAX ? "\t.LWORD L%d\n" : "\t.long .L%d\n", \
441 VALUE)
442
443 /* This is how to output an element of a case-vector that is relative.
444 Note: The local label referenced by the "3b" below is emitted by
445 the tablejump insn. */
446
447 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
448 fprintf (FILE, TARGET_AS100_SYNTAX \
449 ? "\t.LWORD L%d - ?-\n" : "\t.long .L%d - 1b\n", VALUE)
450
451 #define ASM_OUTPUT_SIZE_DIRECTIVE(STREAM, NAME, SIZE) \
452 do \
453 { \
454 HOST_WIDE_INT size_ = (SIZE); \
455 \
456 /* The as100 assembler does not have an equivalent of the SVR4 \
457 .size pseudo-op. */ \
458 if (TARGET_AS100_SYNTAX) \
459 break; \
460 \
461 fputs (SIZE_ASM_OP, STREAM); \
462 assemble_name (STREAM, NAME); \
463 fprintf (STREAM, ", " HOST_WIDE_INT_PRINT_DEC "\n", size_); \
464 } \
465 while (0)
466
467 #define ASM_OUTPUT_MEASURED_SIZE(STREAM, NAME) \
468 do \
469 { \
470 /* The as100 assembler does not have an equivalent of the SVR4 \
471 .size pseudo-op. */ \
472 if (TARGET_AS100_SYNTAX) \
473 break; \
474 fputs (SIZE_ASM_OP, STREAM); \
475 assemble_name (STREAM, NAME); \
476 fputs (", .-", STREAM); \
477 assemble_name (STREAM, NAME); \
478 putc ('\n', STREAM); \
479 } \
480 while (0)
481
482 #define ASM_OUTPUT_TYPE_DIRECTIVE(STREAM, NAME, TYPE) \
483 do \
484 { \
485 /* The as100 assembler does not have an equivalent of the SVR4 \
486 .size pseudo-op. */ \
487 if (TARGET_AS100_SYNTAX) \
488 break; \
489 fputs (TYPE_ASM_OP, STREAM); \
490 assemble_name (STREAM, NAME); \
491 fputs (", ", STREAM); \
492 fprintf (STREAM, TYPE_OPERAND_FMT, TYPE); \
493 putc ('\n', STREAM); \
494 } \
495 while (0)
496
497 #undef ASM_GENERATE_INTERNAL_LABEL
498 #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \
499 do \
500 { \
501 sprintf (LABEL, TARGET_AS100_SYNTAX ? "*%s%u" : "*.%s%u", \
502 PREFIX, (unsigned) (NUM)); \
503 } \
504 while (0)
505
506 #undef ASM_OUTPUT_EXTERNAL
507 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
508 do \
509 { \
510 if (TARGET_AS100_SYNTAX) \
511 targetm.asm_out.globalize_label (FILE, NAME); \
512 default_elf_asm_output_external (FILE, DECL, NAME); \
513 } \
514 while (0)
515
516 #undef ASM_OUTPUT_ALIGNED_COMMON
517 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
518 do \
519 { \
520 if (TARGET_AS100_SYNTAX) \
521 { \
522 fprintf ((FILE), "\t.GLB\t"); \
523 assemble_name ((FILE), (NAME)); \
524 fprintf ((FILE), "\n"); \
525 assemble_name ((FILE), (NAME)); \
526 switch ((ALIGN) / BITS_PER_UNIT) \
527 { \
528 case 4: \
529 fprintf ((FILE), ":\t.BLKL\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n",\
530 (SIZE) / 4); \
531 break; \
532 case 2: \
533 fprintf ((FILE), ":\t.BLKW\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n",\
534 (SIZE) / 2); \
535 break; \
536 default: \
537 fprintf ((FILE), ":\t.BLKB\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n",\
538 (SIZE)); \
539 break; \
540 } \
541 } \
542 else \
543 { \
544 fprintf ((FILE), "%s", COMMON_ASM_OP); \
545 assemble_name ((FILE), (NAME)); \
546 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", \
547 (SIZE), (ALIGN) / BITS_PER_UNIT); \
548 } \
549 } \
550 while (0)
551
552 #undef SKIP_ASM_OP
553 #define SKIP_ASM_OP (TARGET_AS100_SYNTAX ? "\t.BLKB\t" : "\t.zero\t")
554
555 #undef ASM_OUTPUT_LIMITED_STRING
556 #define ASM_OUTPUT_LIMITED_STRING(FILE, STR) \
557 do \
558 { \
559 const unsigned char *_limited_str = \
560 (const unsigned char *) (STR); \
561 unsigned ch; \
562 \
563 fprintf ((FILE), TARGET_AS100_SYNTAX \
564 ? "\t.BYTE\t\"" : "\t.string\t\""); \
565 \
566 for (; (ch = *_limited_str); _limited_str++) \
567 { \
568 int escape; \
569 \
570 switch (escape = ESCAPES[ch]) \
571 { \
572 case 0: \
573 putc (ch, (FILE)); \
574 break; \
575 case 1: \
576 fprintf ((FILE), "\\%03o", ch); \
577 break; \
578 default: \
579 putc ('\\', (FILE)); \
580 putc (escape, (FILE)); \
581 break; \
582 } \
583 } \
584 \
585 fprintf ((FILE), TARGET_AS100_SYNTAX ? "\"\n\t.BYTE\t0\n" : "\"\n");\
586 } \
587 while (0)
588
589 #undef IDENT_ASM_OP
590 #define IDENT_ASM_OP (TARGET_AS100_SYNTAX \
591 ? "\t.END\t; Built by: ": "\t.ident\t")
592
593 /* For PIC put jump tables into the text section so that the offsets that
594 they contain are always computed between two same-section symbols. */
595 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
596 \f
597 extern int rx_float_compare_mode;
598 \f
599 /* This is a version of REG_P that also returns TRUE for SUBREGs. */
600 #define RX_REG_P(rtl) (REG_P (rtl) || GET_CODE (rtl) == SUBREG)
601
602 /* Like REG_P except that this macro is true for SET expressions. */
603 #define SET_P(rtl) (GET_CODE (rtl) == SET)
604 \f
605 /* The AS100 assembler does not support .leb128 and .uleb128, but
606 the compiler-build-time configure tests will have enabled their
607 use because GAS supports them. So default to generating STABS
608 debug information instead of DWARF2 when generating AS100
609 compatible output. */
610 #undef PREFERRED_DEBUGGING_TYPE
611 #define PREFERRED_DEBUGGING_TYPE (TARGET_AS100_SYNTAX \
612 ? DBX_DEBUG : DWARF2_DEBUG)
613
614 #define INCOMING_FRAME_SP_OFFSET 4
615 #define ARG_POINTER_CFA_OFFSET(FNDECL) 4
616 #define FRAME_POINTER_CFA_OFFSET(FNDECL) 4
617 \f
618 #define TARGET_USE_FPU (! TARGET_NO_USE_FPU)
619
620 /* This macro is used to decide when RX FPU instructions can be used. */
621 #define ALLOW_RX_FPU_INSNS (TARGET_USE_FPU)
622
623 #define BRANCH_COST(SPEED,PREDICT) 1
624 #define REGISTER_MOVE_COST(MODE,FROM,TO) 2
625
626 #define SELECT_CC_MODE(OP,X,Y) \
627 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CC_ZSmode : \
628 (GET_CODE (X) == PLUS || GET_CODE (X) == MINUS ? CC_ZSCmode : \
629 (GET_CODE (X) == ABS ? CC_ZSOmode : \
630 (GET_CODE (X) == AND || GET_CODE (X) == NOT || GET_CODE (X) == IOR \
631 || GET_CODE (X) == XOR || GET_CODE (X) == ROTATE \
632 || GET_CODE (X) == ROTATERT || GET_CODE (X) == ASHIFTRT \
633 || GET_CODE (X) == LSHIFTRT || GET_CODE (X) == ASHIFT ? CC_ZSmode : \
634 CCmode))))