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1 /* GCC backend definitions for the Renesas RX processor.
2 Copyright (C) 2008-2023 Free Software Foundation, Inc.
3 Contributed by Red Hat.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 #define TARGET_CPU_CPP_BUILTINS() \
25 builtin_define ("__RX__"); \
26 builtin_assert ("cpu=RX"); \
27 if (rx_cpu_type == RX610) \
29 builtin_define ("__RX610__"); \
30 builtin_assert ("machine=RX610"); \
32 else if (rx_cpu_type == RX100) \
34 builtin_define ("__RX100__"); \
35 builtin_assert ("machine=RX100"); \
37 else if (rx_cpu_type == RX200) \
39 builtin_define ("__RX200__"); \
40 builtin_assert ("machine=RX200"); \
42 else if (rx_cpu_type == RX600) \
44 builtin_define ("__RX600__"); \
45 builtin_assert ("machine=RX600"); \
48 if (TARGET_BIG_ENDIAN_DATA) \
49 builtin_define ("__RX_BIG_ENDIAN__"); \
51 builtin_define ("__RX_LITTLE_ENDIAN__");\
53 if (TARGET_64BIT_DOUBLES) \
54 builtin_define ("__RX_64BIT_DOUBLES__");\
56 builtin_define ("__RX_32BIT_DOUBLES__");\
58 if (ALLOW_RX_FPU_INSNS) \
59 builtin_define ("__RX_FPU_INSNS__"); \
61 if (TARGET_AS100_SYNTAX) \
62 builtin_define ("__RX_AS100_SYNTAX__"); \
64 builtin_define ("__RX_GAS_SYNTAX__"); \
67 builtin_define ("__RX_GCC_ABI__"); \
69 builtin_define ("__RX_ABI__"); \
71 if (rx_allow_string_insns) \
72 builtin_define ("__RX_ALLOW_STRING_INSNS__"); \
74 builtin_define ("__RX_DISALLOW_STRING_INSNS__");\
80 %{mas100-syntax:%{gdwarf*:%e-mas100-syntax is incompatible with -gdwarf}} \
81 %{mcpu=rx100:%{fpu:%erx100 cpu does not have FPU hardware}} \
82 %{mcpu=rx200:%{fpu:%erx200 cpu does not have FPU hardware}}"
85 #define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:crt0.o%s} crtbegin.o%s"
88 #define ENDFILE_SPEC "crtend.o%s crtn.o%s"
93 %{mint-register=*:-D_RX_INT_REGISTERS=%*} \
94 %{msmall-data-limit*:-D_RX_SMALL_DATA} \
99 %{mbig-endian-data:-mbig-endian-data} \
100 %{m64bit-doubles:-m64bit-doubles} \
101 %{!m64bit-doubles:-m32bit-doubles} \
102 %{msmall-data-limit*:-msmall-data-limit} \
105 %{mno-allow-string-insns} \
107 %{mgcc-abi:-mgcc-abi} %{!mgcc-abi:-mrx-abi} \
115 %{msim:-lsim}%{!msim:-lnosys} \
116 %{fprofile-arcs|fprofile-generate|coverage:-lgcov} \
118 %{!T*: %{msim:%Trx-sim.ld}%{!msim:%Trx.ld}} \
122 #define LINK_SPEC "%{mbig-endian-data:--oformat elf32-rx-be} %{mrelax:-relax}"
125 #define BITS_BIG_ENDIAN 0
126 #define BYTES_BIG_ENDIAN TARGET_BIG_ENDIAN_DATA
127 #define WORDS_BIG_ENDIAN TARGET_BIG_ENDIAN_DATA
129 #define UNITS_PER_WORD 4
131 #define INT_TYPE_SIZE 32
132 #define LONG_TYPE_SIZE 32
133 #define LONG_LONG_TYPE_SIZE 64
135 #define FLOAT_TYPE_SIZE 32
136 #define DOUBLE_TYPE_SIZE (TARGET_64BIT_DOUBLES ? 64 : 32)
137 #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE
139 #define DEFAULT_SIGNED_CHAR 0
141 /* RX load/store instructions can handle unaligned addresses. */
142 #define STRICT_ALIGNMENT 0
143 #define FUNCTION_BOUNDARY ((rx_cpu_type == RX100 || rx_cpu_type == RX200) ? 4 : 8)
144 #define BIGGEST_ALIGNMENT 32
145 #define STACK_BOUNDARY 32
146 #define PARM_BOUNDARY 8
148 #define STACK_GROWS_DOWNWARD 1
149 #define FRAME_GROWS_DOWNWARD 0
150 #define FIRST_PARM_OFFSET(FNDECL) 0
152 #define MAX_REGS_PER_ADDRESS 2
155 #define POINTER_SIZE 32
157 #define SIZE_TYPE "long unsigned int"
159 #define PTRDIFF_TYPE "long int"
161 #define WCHAR_TYPE "long int"
162 #undef WCHAR_TYPE_SIZE
163 #define WCHAR_TYPE_SIZE BITS_PER_WORD
164 #define POINTERS_EXTEND_UNSIGNED 1
165 #define FUNCTION_MODE QImode
166 #define CASE_VECTOR_MODE Pmode
167 #define WORD_REGISTER_OPERATIONS 1
168 #define HAS_LONG_COND_BRANCH 0
169 #define HAS_LONG_UNCOND_BRANCH 0
173 #define HAVE_PRE_DECREMENT 1
174 #define HAVE_POST_INCREMENT 1
176 #define MOVE_RATIO(SPEED) ((SPEED) ? 4 : 2)
177 #define SLOW_BYTE_ACCESS 1
179 #define STORE_FLAG_VALUE 1
180 #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
181 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
185 NO_REGS
, /* No registers in set. */
186 GR_REGS
, /* Integer registers. */
187 ALL_REGS
, /* All registers. */
188 LIM_REG_CLASSES
/* Max value + 1. */
191 #define REG_CLASS_NAMES \
198 #define REG_CLASS_CONTENTS \
200 { 0x00000000 }, /* No registers, */ \
201 { 0x0000ffff }, /* Integer registers. */ \
202 { 0x0000ffff } /* All registers. */ \
205 #define N_REG_CLASSES (int) LIM_REG_CLASSES
206 #define CLASS_MAX_NREGS(CLASS, MODE) ((GET_MODE_SIZE (MODE) \
207 + UNITS_PER_WORD - 1) \
210 #define GENERAL_REGS GR_REGS
211 #define BASE_REG_CLASS GR_REGS
212 #define INDEX_REG_CLASS GR_REGS
214 #define FIRST_PSEUDO_REGISTER 17
216 #define REGNO_REG_CLASS(REGNO) ((REGNO) < FIRST_PSEUDO_REGISTER \
219 #define STACK_POINTER_REGNUM 0
220 #define FUNC_RETURN_REGNUM 1
221 #define FRAME_POINTER_REGNUM 6
222 #define ARG_POINTER_REGNUM 7
223 #define STATIC_CHAIN_REGNUM 8
224 #define TRAMPOLINE_TEMP_REGNUM 9
225 #define STRUCT_VAL_REGNUM 15
228 /* This is the register which will probably be used to hold the address of
229 the start of the small data area, if -msmall-data-limit is being used,
230 or the address of the constant data area if -mpid is being used. If both
231 features are in use then two consecutive registers will be used.
233 Note - these registers must not be call_used because otherwise library
234 functions that are compiled without -msmall-data-limit/-mpid support
237 Note that the actual values used depends on other options; use
238 rx_gp_base_regnum() and rx_pid_base_regnum() instead. */
239 #define GP_BASE_REGNUM 13
241 #define ELIMINABLE_REGS \
242 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
243 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
244 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
246 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
247 (OFFSET) = rx_initial_elimination_offset ((FROM), (TO))
250 #define FUNCTION_ARG_REGNO_P(N) (((N) >= 1) && ((N) <= 4))
251 #define FUNCTION_VALUE_REGNO_P(N) ((N) == FUNC_RETURN_REGNUM)
252 #define DEFAULT_PCC_STRUCT_RETURN 0
254 #define FIXED_REGISTERS \
256 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
259 #define CALL_USED_REGISTERS \
261 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1 \
264 #define LIBCALL_VALUE(MODE) \
265 gen_rtx_REG (((GET_MODE_CLASS (MODE) != MODE_INT \
266 || COMPLEX_MODE_P (MODE) \
267 || VECTOR_MODE_P (MODE) \
268 || GET_MODE_SIZE (MODE) >= 4) \
273 /* Order of allocation of registers. */
275 #define REG_ALLOC_ORDER \
276 { 7, 10, 11, 12, 13, 14, 4, 3, 2, 1, 9, 8, 6, 5, 15 \
279 #define REGNO_IN_RANGE(REGNO, MIN, MAX) \
280 (IN_RANGE ((REGNO), (MIN), (MAX)) \
281 || (reg_renumber != NULL \
282 && reg_renumber[(REGNO)] >= (MIN) \
283 && reg_renumber[(REGNO)] <= (MAX)))
286 #define REGNO_OK_FOR_BASE_P(regno) REGNO_IN_RANGE (regno, 0, 15)
288 #define REGNO_OK_FOR_BASE_P(regno) 1
291 #define REGNO_OK_FOR_INDEX_P(regno) REGNO_OK_FOR_BASE_P (regno)
293 #define RTX_OK_FOR_BASE(X, STRICT) \
296 && REGNO_IN_RANGE (REGNO (X), 0, 15)) \
297 || (GET_CODE (X) == SUBREG \
298 && REG_P (SUBREG_REG (X)) \
299 && REGNO_IN_RANGE (REGNO (SUBREG_REG (X)), 0, 15))) \
302 || (GET_CODE (X) == SUBREG \
303 && REG_P (SUBREG_REG (X))))))
306 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \
308 ? gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, arg_pointer_rtx, GEN_INT (-4))) \
311 #define INCOMING_RETURN_ADDR_RTX gen_rtx_MEM (Pmode, stack_pointer_rtx)
313 #define ACCUMULATE_OUTGOING_ARGS 1
315 typedef unsigned int CUMULATIVE_ARGS
;
317 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
321 #define TRAMPOLINE_SIZE (! TARGET_BIG_ENDIAN_DATA ? 14 : 20)
322 #define TRAMPOLINE_ALIGNMENT 32
324 #define NO_PROFILE_COUNTERS 1
325 #define PROFILE_BEFORE_PROLOGUE 1
327 #define FUNCTION_PROFILER(FILE, LABELNO) \
328 fprintf (FILE, "\tbsr\t__mcount\n");
331 #define REGISTER_NAMES \
333 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
334 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", "cc" \
337 #define ADDITIONAL_REGISTER_NAMES \
339 { "sp", STACK_POINTER_REGNUM } \
340 , { "fp", FRAME_POINTER_REGNUM } \
341 , { "arg", ARG_POINTER_REGNUM } \
342 , { "chain", STATIC_CHAIN_REGNUM } \
345 #define DATA_SECTION_ASM_OP \
346 (TARGET_AS100_SYNTAX ? "\t.SECTION D,DATA" \
347 : "\t.section D,\"aw\",@progbits\n\t.p2align 2")
349 #define SDATA_SECTION_ASM_OP \
350 (TARGET_AS100_SYNTAX ? "\t.SECTION D_2,DATA,ALIGN=2" \
351 : "\t.section D_2,\"aw\",@progbits\n\t.p2align 1")
353 #undef READONLY_DATA_SECTION_ASM_OP
354 #define READONLY_DATA_SECTION_ASM_OP \
355 (TARGET_AS100_SYNTAX ? "\t.SECTION C,ROMDATA,ALIGN=4" \
356 : "\t.section C,\"a\",@progbits\n\t.p2align 2")
358 #define BSS_SECTION_ASM_OP \
359 (TARGET_AS100_SYNTAX ? "\t.SECTION B,DATA,ALIGN=4" \
360 : "\t.section B,\"w\",@nobits\n\t.p2align 2")
362 #define SBSS_SECTION_ASM_OP \
363 (TARGET_AS100_SYNTAX ? "\t.SECTION B_2,DATA,ALIGN=2" \
364 : "\t.section B_2,\"w\",@nobits\n\t.p2align 1")
366 /* The following definitions are conditional depending upon whether the
367 compiler is being built or crtstuff.c is being compiled by the built
369 #if defined CRT_BEGIN || defined CRT_END
370 # ifdef __RX_AS100_SYNTAX
371 # define TEXT_SECTION_ASM_OP "\t.SECTION P,CODE"
372 # define CTORS_SECTION_ASM_OP "\t.SECTION init_array,CODE"
373 # define DTORS_SECTION_ASM_OP "\t.SECTION fini_array,CODE"
374 # define INIT_ARRAY_SECTION_ASM_OP "\t.SECTION init_array,CODE"
375 # define FINI_ARRAY_SECTION_ASM_OP "\t.SECTION fini_array,CODE"
377 # define TEXT_SECTION_ASM_OP "\t.section P,\"ax\""
378 # define CTORS_SECTION_ASM_OP \
379 "\t.section\t.init_array,\"awx\",@init_array"
380 # define DTORS_SECTION_ASM_OP \
381 "\t.section\t.fini_array,\"awx\",@fini_array"
382 # define INIT_ARRAY_SECTION_ASM_OP \
383 "\t.section\t.init_array,\"awx\",@init_array"
384 # define FINI_ARRAY_SECTION_ASM_OP \
385 "\t.section\t.fini_array,\"awx\",@fini_array"
388 # define TEXT_SECTION_ASM_OP \
389 (TARGET_AS100_SYNTAX ? "\t.SECTION P,CODE" : "\t.section P,\"ax\"")
391 # define CTORS_SECTION_ASM_OP \
392 (TARGET_AS100_SYNTAX ? "\t.SECTION init_array,CODE" \
393 : "\t.section\t.init_array,\"awx\",@init_array")
395 # define DTORS_SECTION_ASM_OP \
396 (TARGET_AS100_SYNTAX ? "\t.SECTION fini_array,CODE" \
397 : "\t.section\t.fini_array,\"awx\",@fini_array")
399 # define INIT_ARRAY_SECTION_ASM_OP \
400 (TARGET_AS100_SYNTAX ? "\t.SECTION init_array,CODE" \
401 : "\t.section\t.init_array,\"awx\",@init_array")
403 # define FINI_ARRAY_SECTION_ASM_OP \
404 (TARGET_AS100_SYNTAX ? "\t.SECTION fini_array,CODE" \
405 : "\t.section\t.fini_array,\"awx\",@fini_array")
408 #define GLOBAL_ASM_OP \
409 (TARGET_AS100_SYNTAX ? "\t.GLB\t" : "\t.global\t")
410 #define ASM_COMMENT_START " ;"
412 #define ASM_APP_ON ""
414 #define ASM_APP_OFF ""
415 #define LOCAL_LABEL_PREFIX "L"
416 #undef USER_LABEL_PREFIX
417 #define USER_LABEL_PREFIX "_"
419 /* Compute the alignment needed for label X in various situations.
420 If the user has specified an alignment then honour that, otherwise
421 use rx_align_for_label. */
422 #define JUMP_ALIGN(x) (align_jumps.levels[0].log > 0 ? align_jumps : align_flags (rx_align_for_label (x, 0)))
423 #define LABEL_ALIGN(x) (align_labels.levels[0].log > 0 ? align_labels : align_flags (rx_align_for_label (x, 3)))
424 #define LOOP_ALIGN(x) (align_loops.levels[0].log > 0 ? align_loops : align_flags (rx_align_for_label (x, 2)))
425 #define LABEL_ALIGN_AFTER_BARRIER(x) rx_align_for_label (x, 0)
427 #define ASM_OUTPUT_MAX_SKIP_ALIGN(STREAM, LOG, MAX_SKIP) \
430 if ((LOG) == 0 || (MAX_SKIP) == 0) \
432 if (TARGET_AS100_SYNTAX) \
435 fprintf (STREAM, "\t.ALIGN 4\t; %d alignment actually requested\n", 1 << (LOG)); \
437 fprintf (STREAM, "\t.ALIGN 2\n"); \
440 fprintf (STREAM, "\t.balign %d,3,%d\n", 1 << (LOG), (MAX_SKIP)); \
444 #define ASM_OUTPUT_ALIGN(STREAM, LOG) \
449 if (TARGET_AS100_SYNTAX) \
452 fprintf (STREAM, "\t.ALIGN 4\t; %d alignment actually requested\n", 1 << (LOG)); \
454 fprintf (STREAM, "\t.ALIGN 2\n"); \
457 fprintf (STREAM, "\t.balign %d\n", 1 << (LOG)); \
461 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
462 fprintf (FILE, TARGET_AS100_SYNTAX ? "\t.LWORD L%d\n" : "\t.long .L%d\n", \
465 /* This is how to output an element of a case-vector that is relative.
466 Note: The local label referenced by the "1b" below is emitted by
467 the tablejump insn. */
469 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
470 fprintf (FILE, TARGET_AS100_SYNTAX \
471 ? "\t.LWORD L%d - ?-\n" : "\t.long .L%d - 1b\n", VALUE)
473 #define CASE_VECTOR_PC_RELATIVE (TARGET_PID)
475 #define ASM_OUTPUT_SIZE_DIRECTIVE(STREAM, NAME, SIZE) \
478 HOST_WIDE_INT size_ = (SIZE); \
480 /* The as100 assembler does not have an equivalent of the SVR4 \
481 .size pseudo-op. */ \
482 if (TARGET_AS100_SYNTAX) \
485 fputs (SIZE_ASM_OP, STREAM); \
486 assemble_name (STREAM, NAME); \
487 fprintf (STREAM, ", " HOST_WIDE_INT_PRINT_DEC "\n", size_); \
491 #define ASM_OUTPUT_MEASURED_SIZE(STREAM, NAME) \
494 /* The as100 assembler does not have an equivalent of the SVR4 \
495 .size pseudo-op. */ \
496 if (TARGET_AS100_SYNTAX) \
498 fputs (SIZE_ASM_OP, STREAM); \
499 assemble_name (STREAM, NAME); \
500 fputs (", .-", STREAM); \
501 assemble_name (STREAM, NAME); \
502 putc ('\n', STREAM); \
506 #define ASM_OUTPUT_TYPE_DIRECTIVE(STREAM, NAME, TYPE) \
509 /* The as100 assembler does not have an equivalent of the SVR4 \
510 .size pseudo-op. */ \
511 if (TARGET_AS100_SYNTAX) \
513 fputs (TYPE_ASM_OP, STREAM); \
514 assemble_name (STREAM, NAME); \
515 fputs (", ", STREAM); \
516 fprintf (STREAM, TYPE_OPERAND_FMT, TYPE); \
517 putc ('\n', STREAM); \
521 #undef ASM_GENERATE_INTERNAL_LABEL
522 #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \
525 sprintf (LABEL, TARGET_AS100_SYNTAX ? "*%s%u" : "*.%s%u", \
526 PREFIX, (unsigned) (NUM)); \
530 #undef ASM_OUTPUT_EXTERNAL
531 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
534 if (TARGET_AS100_SYNTAX) \
535 targetm.asm_out.globalize_label (FILE, NAME); \
536 default_elf_asm_output_external (FILE, DECL, NAME); \
540 #undef ASM_OUTPUT_ALIGNED_COMMON
541 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
544 if (TARGET_AS100_SYNTAX) \
546 fprintf ((FILE), "\t.GLB\t"); \
547 assemble_name ((FILE), (NAME)); \
548 fprintf ((FILE), "\n"); \
549 assemble_name ((FILE), (NAME)); \
550 switch ((ALIGN) / BITS_PER_UNIT) \
553 fprintf ((FILE), ":\t.BLKL\t" HOST_WIDE_INT_PRINT_UNSIGNED"\n",\
557 fprintf ((FILE), ":\t.BLKW\t" HOST_WIDE_INT_PRINT_UNSIGNED"\n",\
561 fprintf ((FILE), ":\t.BLKB\t" HOST_WIDE_INT_PRINT_UNSIGNED"\n",\
568 fprintf ((FILE), "%s", COMMON_ASM_OP); \
569 assemble_name ((FILE), (NAME)); \
570 fprintf ((FILE), "," HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", \
571 (SIZE), (ALIGN) / BITS_PER_UNIT); \
577 #define SKIP_ASM_OP (TARGET_AS100_SYNTAX ? "\t.BLKB\t" : "\t.zero\t")
579 #undef ASM_OUTPUT_LIMITED_STRING
580 #define ASM_OUTPUT_LIMITED_STRING(FILE, STR) \
583 const unsigned char *_limited_str = \
584 (const unsigned char *) (STR); \
587 fprintf ((FILE), TARGET_AS100_SYNTAX \
588 ? "\t.BYTE\t\"" : "\t.string\t\""); \
590 for (; (ch = *_limited_str); _limited_str++) \
594 switch (escape = ESCAPES[ch]) \
600 fprintf ((FILE), "\\%03o", ch); \
603 putc ('\\', (FILE)); \
604 putc (escape, (FILE)); \
609 fprintf ((FILE), TARGET_AS100_SYNTAX ? "\"\n\t.BYTE\t0\n" : "\"\n");\
613 /* For PIC put jump tables into the text section so that the offsets that
614 they contain are always computed between two same-section symbols. */
615 #define JUMP_TABLES_IN_TEXT_SECTION (TARGET_PID || flag_pic)
617 /* This is a version of REG_P that also returns TRUE for SUBREGs. */
618 #define RX_REG_P(rtl) (REG_P (rtl) || GET_CODE (rtl) == SUBREG)
620 /* Like REG_P except that this macro is true for SET expressions. */
621 #define SET_P(rtl) (GET_CODE (rtl) == SET)
623 #undef PREFERRED_DEBUGGING_TYPE
624 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
626 #define DWARF2_DEBUGGING_INFO 1
628 #define INCOMING_FRAME_SP_OFFSET 4
629 #define ARG_POINTER_CFA_OFFSET(FNDECL) 4
631 #define TARGET_USE_FPU (! TARGET_NO_USE_FPU)
633 /* This macro is used to decide when RX FPU instructions can be used. */
634 #define ALLOW_RX_FPU_INSNS (TARGET_USE_FPU)
636 #define BRANCH_COST(SPEED,PREDICT) 1
637 #define REGISTER_MOVE_COST(MODE,FROM,TO) 2
639 #define SELECT_CC_MODE(OP,X,Y) rx_select_cc_mode(OP, X, Y)
641 #define ADJUST_INSN_LENGTH(INSN,LENGTH) \
644 (LENGTH) = rx_adjust_insn_length ((INSN), (LENGTH)); \