1 ;; Scheduling description for z900 (cpu 2064).
2 ;; Copyright (C) 2003 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com).
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it under
9 ;; the terms of the GNU General Public License as published by the Free
10 ;; Software Foundation; either version 2, or (at your option) any later
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to the Free
20 ;; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
25 ;; The microarchitecture of the IBM eServer z900 processor.
26 ;; E.M. Schwarz et al.
27 ;; IBM Journal of Research and Development Vol. 46 No 4/5, 2002.
29 ;; z900 (cpu 2064) pipeline
35 ;; --- c1 | Load bypass
43 (define_automaton "z_ipu")
44 (define_cpu_unit "z_e1" "z_ipu")
45 (define_cpu_unit "z_wr" "z_ipu")
48 (define_insn_reservation "z_la" 1
49 (and (eq_attr "cpu" "z900")
50 (eq_attr "type" "la"))
53 (define_insn_reservation "z_larl" 1
54 (and (eq_attr "cpu" "z900")
55 (eq_attr "type" "larl"))
58 (define_insn_reservation "z_load" 1
59 (and (eq_attr "cpu" "z900")
60 (eq_attr "type" "load"))
63 (define_insn_reservation "z_store" 1
64 (and (eq_attr "cpu" "z900")
65 (eq_attr "type" "store"))
68 (define_insn_reservation "z_call" 5
69 (and (eq_attr "cpu" "z900")
70 (eq_attr "type" "jsr"))
73 (define_insn_reservation "z_o2" 2
74 (and (eq_attr "cpu" "z900")
75 (eq_attr "type" "o2"))
78 (define_insn_reservation "z_o3" 3
79 (and (eq_attr "cpu" "z900")
80 (eq_attr "type" "o3"))
84 ; Insn still not mentioned are check for
85 ; the usage of the agen unit
88 (define_insn_reservation "z_int" 1
89 (and (eq_attr "cpu" "z900")
90 (eq_attr "atype" "reg"))
93 (define_insn_reservation "z_agen" 1
94 (and (eq_attr "cpu" "z900")
95 (eq_attr "atype" "agen"))
100 ;; s390_agen_dep_p returns 1, if a register is set in the
101 ;; first insn and used in the dependent insn to form a address.
105 ;; If an instruction uses a register to address memory, it needs
106 ;; to be set 5 cycles in advance.
109 (define_bypass 5 "z_int,z_agen"
110 "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")
113 ;; A load type instruction uses a bypass to feed the result back
114 ;; to the address generation pipeline stage.
117 (define_bypass 3 "z_load"
118 "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")
121 ;; A load address type instruction uses a bypass to feed the
122 ;; result back to the address generation pipeline stage.
125 (define_bypass 2 "z_larl,z_la"
126 "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")