gcc/config/s390/2064.md

   1 ;; Scheduling description for z900 (cpu 2064).
   2 ;;   Copyright (C) 2003, 2004 Free Software Foundation, Inc.
   3 ;;   Contributed by Hartmut Penner (hpenner@de.ibm.com) and
   4 ;;                  Ulrich Weigand (uweigand@de.ibm.com).
   5
   6 ;; This file is part of GCC.
   7
   8 ;; GCC is free software; you can redistribute it and/or modify it under
   9 ;; the terms of the GNU General Public License as published by the Free
  10 ;; Software Foundation; either version 2, or (at your option) any later
  11 ;; version.
  12
  13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  14 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15 ;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16 ;; for more details.
  17
  18 ;; You should have received a copy of the GNU General Public License
  19 ;; along with GCC; see the file COPYING.  If not, write to the Free
  20 ;; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  21 ;; 02111-1307, USA.
  22
  23 ;;
  24 ;; References:
  25 ;;   The microarchitecture of the IBM eServer z900 processor.
  26 ;;   E.M. Schwarz et al.
  27 ;;   IBM Journal of Research and Development Vol. 46 No 4/5, 2002.
  28 ;;
  29 ;;            z900 (cpu 2064) pipeline
  30 ;;
  31 ;;                 dec
  32 ;;              --> | <---
  33 ;;  LA bypass  |  agen    |
  34 ;;             |    |     |
  35 ;;              --- c1    |  Load bypass
  36 ;;                  |     |
  37 ;;                  c2----
  38 ;;                  |
  39 ;;                  e1
  40 ;;                  |
  41 ;;                  wr
  42
  43 ;; This scheduler description is also used for the g5 and g6.
  44
  45 (define_automaton "z_ipu")
  46 (define_cpu_unit "z_e1"   "z_ipu")
  47 (define_cpu_unit "z_wr"   "z_ipu")
  48
  49
  50 (define_insn_reservation "z_la" 1
  51   (and (eq_attr "cpu" "z900,g5,g6")
  52        (eq_attr "type" "la"))
  53   "z_e1,z_wr")
  54
  55 (define_insn_reservation "z_larl" 1
  56   (and (eq_attr "cpu" "z900,g5,g6")
  57        (eq_attr "type" "larl"))
  58   "z_e1,z_wr")
  59
  60 (define_insn_reservation "z_load" 1
  61   (and (eq_attr "cpu" "z900,g5,g6")
  62        (eq_attr "type" "load"))
  63   "z_e1,z_wr")
  64
  65 (define_insn_reservation "z_store" 1
  66   (and (eq_attr "cpu" "z900,g5,g6")
  67        (eq_attr "type" "store"))
  68   "z_e1,z_wr")
  69
  70 (define_insn_reservation "z_call" 5
  71   (and (eq_attr "cpu" "z900,g5,g6")
  72        (eq_attr "type" "jsr"))
  73   "z_e1*5,z_wr")
  74
  75 ;
  76 ; Insn still not mentioned are check for
  77 ; the usage of the agen unit
  78 ;
  79
  80 (define_insn_reservation "z_int" 1
  81   (and (eq_attr "cpu" "z900,g5,g6")
  82        (eq_attr "atype" "reg"))
  83   "z_e1,z_wr")
  84
  85 (define_insn_reservation "z_agen" 1
  86   (and (eq_attr "cpu" "z900,g5,g6")
  87        (eq_attr "atype" "agen"))
  88   "z_e1,z_wr")
  89
  90
  91 ;;
  92 ;; s390_agen_dep_p returns 1, if a register is set in the
  93 ;; first insn and used in the dependent insn to form a address.
  94 ;;
  95
  96 ;;
  97 ;; If an instruction uses a register to address memory, it needs
  98 ;; to be set 5 cycles in advance.
  99 ;;
 100
 101 (define_bypass 5 "z_int,z_agen"
 102                "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")
 103
 104 ;;
 105 ;; A load type instruction uses a bypass to feed the result back
 106 ;; to the address generation pipeline stage.
 107 ;;
 108
 109 (define_bypass 3 "z_load"
 110                  "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")
 111
 112 ;;
 113 ;; A load address type instruction uses a bypass to feed the
 114 ;; result back to the address generation pipeline stage.
 115 ;;
 116
 117 (define_bypass 2 "z_larl,z_la"
 118                  "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")
 119
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