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[thirdparty/gcc.git] / gcc / config / s390 / 2064.md
1 ;; Scheduling description for z900 (cpu 2064).
2 ;; Copyright (C) 2003 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com).
5 ;;
6 ;; This file is part of GNU CC.
7 ;;
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; any later version.
12 ;;
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
17 ;;
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
22
23 ;;
24 ;; References:
25 ;; The microarchitecture of the IBM eServer z900 processor.
26 ;; E.M. Schwarz et al.
27 ;; IBM Journal of Research and Development Vol. 46 No 4/5, 2002.
28 ;;
29 ;; z900 (cpu 2064) pipeline
30 ;;
31 ;; dec
32 ;; --> | <---
33 ;; LA bypass | agen |
34 ;; | | |
35 ;; --- c1 | Load bypass
36 ;; | |
37 ;; c2----
38 ;; |
39 ;; e1
40 ;; |
41 ;; wr
42
43 (define_automaton "z_ipu")
44 (define_cpu_unit "z_e1" "z_ipu")
45 (define_cpu_unit "z_wr" "z_ipu")
46
47
48 (define_insn_reservation "z_la" 1
49 (and (eq_attr "cpu" "z900")
50 (eq_attr "type" "la"))
51 "z_e1,z_wr")
52
53 (define_insn_reservation "z_larl" 1
54 (and (eq_attr "cpu" "z900")
55 (eq_attr "type" "larl"))
56 "z_e1,z_wr")
57
58 (define_insn_reservation "z_load" 1
59 (and (eq_attr "cpu" "z900")
60 (eq_attr "type" "load"))
61 "z_e1,z_wr")
62
63 (define_insn_reservation "z_store" 1
64 (and (eq_attr "cpu" "z900")
65 (eq_attr "type" "store"))
66 "z_e1,z_wr")
67
68 (define_insn_reservation "z_call" 5
69 (and (eq_attr "cpu" "z900")
70 (eq_attr "type" "jsr"))
71 "z_e1*5,z_wr")
72
73 (define_insn_reservation "z_o2" 2
74 (and (eq_attr "cpu" "z900")
75 (eq_attr "type" "o2"))
76 "z_e1*2,z_wr")
77
78 (define_insn_reservation "z_o3" 3
79 (and (eq_attr "cpu" "z900")
80 (eq_attr "type" "o3"))
81 "z_e1*3,z_wr")
82
83 ;
84 ; Insn still not mentioned are check for
85 ; the usage of the agen unit
86 ;
87
88 (define_insn_reservation "z_int" 1
89 (and (eq_attr "cpu" "z900")
90 (eq_attr "atype" "reg"))
91 "z_e1,z_wr")
92
93 (define_insn_reservation "z_agen" 1
94 (and (eq_attr "cpu" "z900")
95 (eq_attr "atype" "agen"))
96 "z_e1,z_wr")
97
98
99 ;;
100 ;; s390_agen_dep_p returns 1, if a register is set in the
101 ;; first insn and used in the dependend insn to form a address.
102 ;;
103
104 ;;
105 ;; If a intruction uses a register to address memory, it needs
106 ;; to be set 5 cycles in advance.
107 ;;
108
109 (define_bypass 5 "z_int,z_agen"
110 "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")
111
112 ;;
113 ;; A load type instruction uses a bypass to feed the result back
114 ;; to the address generation pipeline stage.
115 ;;
116
117 (define_bypass 3 "z_load"
118 "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")
119
120 ;;
121 ;; A load address type instruction uses a bypass to feed the
122 ;; result back to the address generation pipeline stage.
123 ;;
124
125 (define_bypass 2 "z_larl,z_la"
126 "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")
127
128
129
130
131