gcc/config/s390/2084.md

   1 ;; Scheduling description for z990 (cpu 2084).
   2 ;;   Copyright (C) 2003-2020 Free Software Foundation, Inc.
   3 ;;   Contributed by Hartmut Penner (hpenner@de.ibm.com) and
   4 ;;                  Ulrich Weigand (uweigand@de.ibm.com).
   5
   6 ;; This file is part of GCC.
   7
   8 ;; GCC is free software; you can redistribute it and/or modify it under
   9 ;; the terms of the GNU General Public License as published by the Free
  10 ;; Software Foundation; either version 3, or (at your option) any later
  11 ;; version.
  12
  13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  14 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15 ;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16 ;; for more details.
  17
  18 ;; You should have received a copy of the GNU General Public License
  19 ;; along with GCC; see the file COPYING3.  If not see
  20 ;; <http://www.gnu.org/licenses/>.
  21
  22 (define_automaton "x_ipu")
  23
  24 (define_cpu_unit "x_e1_r,x_e1_s,x_e1_t"  "x_ipu")
  25 (define_cpu_unit "x_wr_r,x_wr_s,x_wr_t,x_wr_fp" "x_ipu")
  26 (define_cpu_unit "x_s1,x_s2,x_s3,x_s4"   "x_ipu")
  27 (define_cpu_unit "x_t1,x_t2,x_t3,x_t4"   "x_ipu")
  28 (define_cpu_unit "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6"   "x_ipu")
  29 (define_cpu_unit "x_store_tok"   "x_ipu")
  30 (define_cpu_unit "x_ms,x_mt"   "x_ipu")
  31
  32 (define_reservation "x-e1-st" "(x_e1_s | x_e1_t)")
  33
  34 (define_reservation "x-e1-np" "(x_e1_r + x_e1_s + x_e1_t)")
  35
  36 (absence_set "x_e1_r" "x_e1_s,x_e1_t")
  37 (absence_set "x_e1_s" "x_e1_t")
  38
  39 ;; Try to avoid int <-> fp transitions.
  40
  41 (define_reservation "x-x" "x_s1|x_t1,x_s2|x_t2,x_s3|x_t3,x_s4|x_t4")
  42 (define_reservation "x-f" "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6")
  43 (define_reservation "x-wr-st" "((x_wr_s | x_wr_t),x-x)")
  44 (define_reservation "x-wr-np" "((x_wr_r + x_wr_s + x_wr_t),x-x)")
  45 (define_reservation "x-wr-fp" "x_wr_fp,x-f")
  46 (define_reservation "x-mem"   "x_ms|x_mt")
  47
  48 (absence_set "x_wr_fp"
  49              "x_s1,x_s2,x_s3,x_s4,x_t1,x_t2,x_t3,x_t4,x_wr_s,x_wr_t")
  50
  51 (absence_set "x_e1_r,x_wr_r,x_wr_s,x_wr_t"
  52              "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6,x_wr_fp")
  53
  54 ;; Don't have any load type insn in same group as store
  55
  56 (absence_set "x_ms,x_mt" "x_store_tok")
  57
  58
  59 ;;
  60 ;; Simple insns
  61 ;;
  62
  63 (define_insn_reservation "x_int" 1
  64   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
  65        (and (eq_attr "type" "integer")
  66             (eq_attr "atype" "reg")))
  67   "x-e1-st,x-wr-st")
  68
  69 (define_insn_reservation "x_agen" 1
  70   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
  71        (and (eq_attr "type" "integer")
  72             (eq_attr "atype" "agen")))
  73   "x-e1-st,x-wr-st")
  74
  75 (define_insn_reservation "x_lr" 1
  76   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
  77        (eq_attr "type" "lr"))
  78   "x-e1-st,x-wr-st")
  79
  80 (define_insn_reservation "x_la" 1
  81   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
  82        (eq_attr "type" "la"))
  83   "x-e1-st,x-wr-st")
  84
  85 (define_insn_reservation "x_larl" 1
  86   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
  87        (eq_attr "type" "larl"))
  88   "x-e1-st,x-wr-st")
  89
  90 (define_insn_reservation "x_load" 1
  91   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
  92        (eq_attr "type" "load"))
  93   "x-e1-st+x-mem,x-wr-st")
  94
  95 (define_insn_reservation "x_store" 1
  96   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
  97        (eq_attr "type" "store"))
  98   "x-e1-st+x_store_tok,x-wr-st")
  99
 100 (define_insn_reservation "x_branch" 1
 101   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
 102        (eq_attr "type" "branch"))
 103   "x_e1_r,x_wr_r")
 104
 105 (define_insn_reservation "x_call" 5
 106   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
 107        (eq_attr "type" "jsr"))
 108   "x-e1-np*5,x-wr-np")
 109
 110 (define_insn_reservation "x_mul_hi" 2
 111   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
 112        (eq_attr "type" "imulhi"))
 113   "x-e1-np*2,x-wr-np")
 114
 115 (define_insn_reservation "x_mul_sidi" 4
 116   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
 117        (eq_attr "type" "imulsi,imuldi"))
 118   "x-e1-np*4,x-wr-np")
 119
 120 (define_insn_reservation "x_div" 10
 121   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
 122        (eq_attr "type" "idiv"))
 123   "x-e1-np*10,x-wr-np")
 124
 125 (define_insn_reservation "x_sem" 17
 126   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
 127        (eq_attr "type" "sem"))
 128   "x-e1-np+x-mem,x-e1-np*16,x-wr-st")
 129
 130 ;;
 131 ;; Multicycle insns
 132 ;;
 133
 134 (define_insn_reservation "x_cs" 1
 135   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
 136        (eq_attr "type" "cs"))
 137   "x-e1-np,x-wr-np")
 138
 139 (define_insn_reservation "x_vs" 1
 140   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
 141        (eq_attr "type" "vs"))
 142   "x-e1-np*10,x-wr-np")
 143
 144 (define_insn_reservation "x_stm" 1
 145   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
 146        (eq_attr "type" "stm"))
 147   "(x-e1-np+x_store_tok)*10,x-wr-np")
 148
 149 (define_insn_reservation "x_lm" 1
 150   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
 151        (eq_attr "type" "lm"))
 152   "x-e1-np*10,x-wr-np")
 153
 154 (define_insn_reservation "x_other" 1
 155   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
 156        (eq_attr "type" "other"))
 157   "x-e1-np,x-wr-np")
 158
 159 ;;
 160 ;; Floating point insns
 161 ;;
 162
 163 (define_insn_reservation "x_fsimptf" 7
 164   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
 165        (eq_attr "type" "fsimptf,fhex"))
 166   "x_e1_t*2,x-wr-fp")
 167
 168 (define_insn_reservation "x_fsimpdf" 6
 169   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
 170        (eq_attr "type" "fsimpdf,fmuldf,fmadddf,fhex"))
 171   "x_e1_t,x-wr-fp")
 172
 173 (define_insn_reservation "x_fsimpsf" 6
 174   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
 175        (eq_attr "type" "fsimpsf,fmulsf,fmaddsf,fhex"))
 176   "x_e1_t,x-wr-fp")
 177
 178
 179 (define_insn_reservation "x_fmultf" 33
 180   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
 181        (eq_attr "type" "fmultf"))
 182   "x_e1_t*27,x-wr-fp")
 183
 184
 185 (define_insn_reservation "x_fdivtf" 82
 186   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
 187        (eq_attr "type" "fdivtf,fsqrttf"))
 188   "x_e1_t*76,x-wr-fp")
 189
 190 (define_insn_reservation "x_fdivdf" 36
 191   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
 192        (eq_attr "type" "fdivdf,fsqrtdf"))
 193   "x_e1_t*30,x-wr-fp")
 194
 195 (define_insn_reservation "x_fdivsf" 36
 196   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
 197        (eq_attr "type" "fdivsf,fsqrtsf"))
 198   "x_e1_t*30,x-wr-fp")
 199
 200
 201 (define_insn_reservation "x_floadtf" 6
 202   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
 203        (eq_attr "type" "floadtf"))
 204   "x_e1_t,x-wr-fp")
 205
 206 (define_insn_reservation "x_floaddf" 6
 207   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
 208        (eq_attr "type" "floaddf"))
 209   "x_e1_t,x-wr-fp")
 210
 211 (define_insn_reservation "x_floadsf" 6
 212   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
 213        (eq_attr "type" "floadsf"))
 214   "x_e1_t,x-wr-fp")
 215
 216
 217 (define_insn_reservation "x_fstoredf" 1
 218   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
 219        (eq_attr "type" "fstoredf"))
 220   "x_e1_t,x-wr-fp")
 221
 222 (define_insn_reservation "x_fstoresf" 1
 223   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
 224        (eq_attr "type" "fstoresf"))
 225   "x_e1_t,x-wr-fp")
 226
 227
 228 (define_insn_reservation "x_ftrunctf" 16
 229   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
 230        (eq_attr "type" "ftrunctf"))
 231   "x_e1_t*10,x-wr-fp")
 232
 233 (define_insn_reservation "x_ftruncdf" 11
 234   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
 235        (eq_attr "type" "ftruncdf"))
 236   "x_e1_t*5,x-wr-fp")
 237
 238
 239 (define_insn_reservation "x_ftoi" 1
 240   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
 241        (eq_attr "type" "ftoi"))
 242   "x_e1_t*3,x-wr-fp")
 243
 244 (define_insn_reservation "x_itof" 7
 245   (and (eq_attr "cpu" "z990,z9_109,z9_ec")
 246        (eq_attr "type" "itoftf,itofdf,itofsf"))
 247   "x_e1_t*3,x-wr-fp")
 248
 249 (define_bypass 1 "x_fsimpdf" "x_fstoredf")
 250
 251 (define_bypass 1 "x_fsimpsf" "x_fstoresf")
 252
 253 (define_bypass 1 "x_floaddf" "x_fsimpdf,x_fstoredf,x_floaddf")
 254
 255 (define_bypass 1 "x_floadsf" "x_fsimpsf,x_fstoresf,x_floadsf")
 256
 257 ;;
 258 ;; s390_agen_dep_p returns 1, if a register is set in the
 259 ;; first insn and used in the dependent insn to form a address.
 260 ;;
 261
 262 ;;
 263 ;; If an instruction uses a register to address memory, it needs
 264 ;; to be set 5 cycles in advance.
 265 ;;
 266
 267 (define_bypass 5 "x_int,x_agen,x_lr"
 268                  "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other"
 269                  "s390_agen_dep_p")
 270
 271 (define_bypass 9 "x_int,x_agen,x_lr"
 272                  "x_floadtf, x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\
 273                   x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf"
 274                  "s390_agen_dep_p")
 275 ;;
 276 ;; A load type instruction uses a bypass to feed the result back
 277 ;; to the address generation pipeline stage.
 278 ;;
 279
 280 (define_bypass 4 "x_load"
 281                  "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other"
 282                  "s390_agen_dep_p")
 283
 284 (define_bypass 5 "x_load"
 285                  "x_floadtf, x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\
 286                   x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf"
 287                  "s390_agen_dep_p")
 288
 289 ;;
 290 ;; A load address type instruction uses a bypass to feed the
 291 ;; result back to the address generation pipeline stage.
 292 ;;
 293
 294 (define_bypass 3 "x_larl,x_la"
 295                  "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other"
 296                  "s390_agen_dep_p")
 297
 298 (define_bypass 5 "x_larl, x_la"
 299                  "x_floadtf, x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\
 300                   x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf"
 301                  "s390_agen_dep_p")
 302
 303 ;;
 304 ;; Operand forwarding
 305 ;;
 306
 307 (define_bypass 0 "x_lr,x_la,x_load" "x_int,x_lr")
 308
 309