gcc/config/s390/2084.md

   1 ;; Scheduling description for z990 (cpu 2084).
   2 ;;   Copyright (C) 2003 Free Software Foundation, Inc.
   3 ;;   Contributed by Hartmut Penner (hpenner@de.ibm.com) and
   4 ;;                  Ulrich Weigand (uweigand@de.ibm.com).
   5
   6 ;; This file is part of GCC.
   7
   8 ;; GCC is free software; you can redistribute it and/or modify it under
   9 ;; the terms of the GNU General Public License as published by the Free
  10 ;; Software Foundation; either version 2, or (at your option) any later
  11 ;; version.
  12
  13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  14 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15 ;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16 ;; for more details.
  17
  18 ;; You should have received a copy of the GNU General Public License
  19 ;; along with GCC; see the file COPYING.  If not, write to the Free
  20 ;; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  21 ;; 02111-1307, USA.
  22
  23 (define_automaton "x_ipu")
  24
  25 (define_cpu_unit "x_e1_r,x_e1_s,x_e1_t"  "x_ipu")
  26 (define_cpu_unit "x_wr_r,x_wr_s,x_wr_t,x_wr_fp" "x_ipu")
  27 (define_cpu_unit "x_s1,x_s2,x_s3,x_s4"   "x_ipu")
  28 (define_cpu_unit "x_t1,x_t2,x_t3,x_t4"   "x_ipu")
  29 (define_cpu_unit "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6"   "x_ipu")
  30 (define_cpu_unit "x_store_tok"   "x_ipu")
  31 (define_cpu_unit "x_ms,x_mt"   "x_ipu")
  32
  33 (define_reservation "x-e1-st" "(x_e1_s | x_e1_t)")
  34
  35 (define_reservation "x-e1-np" "(x_e1_r + x_e1_s + x_e1_t)")
  36
  37 (absence_set "x_e1_r" "x_e1_s,x_e1_t")
  38 (absence_set "x_e1_s" "x_e1_t")
  39
  40 ;; Try to avoid int <-> fp transitions.
  41
  42 (define_reservation "x-x" "x_s1|x_t1,x_s2|x_t2,x_s3|x_t3,x_s4|x_t4")
  43 (define_reservation "x-f" "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6")
  44 (define_reservation "x-wr-st" "((x_wr_s | x_wr_t),x-x)")
  45 (define_reservation "x-wr-np" "((x_wr_r + x_wr_s + x_wr_t),x-x)")
  46 (define_reservation "x-wr-fp" "x_wr_fp,x-f")
  47 (define_reservation "x-mem"   "x_ms|x_mt")
  48
  49 (absence_set "x_wr_fp"
  50              "x_s1,x_s2,x_s3,x_s4,x_t1,x_t2,x_t3,x_t4,x_wr_s,x_wr_t")
  51
  52 (absence_set "x_e1_r,x_wr_r,x_wr_s,x_wr_t"
  53              "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6,x_wr_fp")
  54
  55 ;; Don't have any load type insn in same group as store
  56
  57 (absence_set "x_ms,x_mt" "x_store_tok")
  58
  59
  60 ;;
  61 ;; Simple insns
  62 ;;
  63
  64 (define_insn_reservation "x_lr" 1
  65   (and (eq_attr "cpu" "z990")
  66        (eq_attr "type" "lr"))
  67   "x-e1-st,x-wr-st")
  68
  69 (define_insn_reservation "x_la" 1
  70   (and (eq_attr "cpu" "z990")
  71        (eq_attr "type" "la"))
  72   "x-e1-st,x-wr-st")
  73
  74 (define_insn_reservation "x_larl" 1
  75   (and (eq_attr "cpu" "z990")
  76        (eq_attr "type" "larl"))
  77   "x-e1-st,x-wr-st")
  78
  79 (define_insn_reservation "x_load" 1
  80   (and (eq_attr "cpu" "z990")
  81        (eq_attr "type" "load"))
  82   "x-e1-st+x-mem,x-wr-st")
  83
  84 (define_insn_reservation "x_store" 1
  85   (and (eq_attr "cpu" "z990")
  86        (eq_attr "type" "store"))
  87   "x-e1-st+x_store_tok,x-wr-st")
  88
  89 (define_insn_reservation "x_branch" 1
  90   (and (eq_attr "cpu" "z990")
  91        (eq_attr "type" "branch"))
  92   "x_e1_r,x_wr_r")
  93
  94 (define_insn_reservation "x_call" 5
  95   (and (eq_attr "cpu" "z990")
  96        (eq_attr "type" "jsr"))
  97   "x-e1-np*5,x-wr-np")
  98
  99 ;;
 100 ;; Multicycle insns
 101 ;;
 102
 103 (define_insn_reservation "x_ss" 1
 104   (and (eq_attr "cpu" "z990")
 105        (eq_attr "op_type" "SS"))
 106   "x-e1-np,x-wr-np")
 107
 108 (define_insn_reservation "x_stm" 1
 109   (and (eq_attr "cpu" "z990")
 110        (eq_attr "type" "stm"))
 111   "(x-e1-np+x_store_tok)*10,x-wr-np")
 112
 113 (define_insn_reservation "x_lm" 1
 114   (and (eq_attr "cpu" "z990")
 115        (eq_attr "type" "lm"))
 116   "x-e1-np*10,x-wr-np")
 117
 118 (define_insn_reservation "x_nn" 1
 119   (and (eq_attr "cpu" "z990")
 120        (eq_attr "op_type" "NN"))
 121   "x-e1-np,x-wr-np")
 122
 123 (define_insn_reservation "x_o2" 2
 124   (and (eq_attr "cpu" "z990")
 125        (eq_attr "type" "o2"))
 126   "x-e1-np*2,x-wr-np")
 127
 128 (define_insn_reservation "x_o3" 3
 129   (and (eq_attr "cpu" "z990")
 130        (eq_attr "type" "o3"))
 131   "x-e1-np*3,x-wr-np")
 132
 133 ;;
 134 ;; Floating point insns
 135 ;;
 136
 137 (define_insn_reservation "x_fsimpd" 6
 138   (and (eq_attr "cpu" "z990")
 139        (eq_attr "type" "fsimpd,fmuld"))
 140   "x_e1_t,x-wr-fp")
 141
 142 (define_insn_reservation "x_fsimps" 6
 143   (and (eq_attr "cpu" "z990")
 144        (eq_attr "type" "fsimps,fmuls"))
 145   "x_e1_t,x-wr-fp")
 146
 147 (define_insn_reservation "x_fdivd" 36
 148   (and (eq_attr "cpu" "z990")
 149        (eq_attr "type" "fdivd"))
 150   "x_e1_t*30,x-wr-fp")
 151
 152 (define_insn_reservation "x_fdivs" 36
 153   (and (eq_attr "cpu" "z990")
 154        (eq_attr "type" "fdivs"))
 155   "x_e1_t*30,x-wr-fp")
 156
 157 (define_insn_reservation "x_floadd" 6
 158   (and (eq_attr "cpu" "z990")
 159        (eq_attr "type" "floadd"))
 160   "x_e1_t,x-wr-fp")
 161
 162 (define_insn_reservation "x_floads" 6
 163   (and (eq_attr "cpu" "z990")
 164        (eq_attr "type" "floads"))
 165   "x_e1_t,x-wr-fp")
 166
 167 (define_insn_reservation "x_fstored" 1
 168   (and (eq_attr "cpu" "z990")
 169        (eq_attr "type" "fstored"))
 170   "x_e1_t,x-wr-fp")
 171
 172 (define_insn_reservation "x_fstores" 1
 173   (and (eq_attr "cpu" "z990")
 174        (eq_attr "type" "fstores"))
 175   "x_e1_t,x-wr-fp")
 176
 177 (define_insn_reservation "x_ftoi" 1
 178   (and (eq_attr "cpu" "z990")
 179        (eq_attr "type" "ftoi"))
 180   "x_e1_t*3,x-wr-fp")
 181
 182 (define_insn_reservation "x_itof" 7
 183   (and (eq_attr "cpu" "z990")
 184        (eq_attr "type" "itof"))
 185   "x_e1_t*3,x-wr-fp")
 186
 187 (define_bypass 1 "x_fsimpd" "x_fstored")
 188
 189 (define_bypass 1 "x_fsimps" "x_fstores")
 190
 191 (define_bypass 1 "x_floadd" "x_fsimpd,x_fstored,x_floadd")
 192
 193 (define_bypass 1 "x_floads" "x_fsimps,x_fstores,x_floads")
 194
 195 ;;
 196 ;; Insns still not mentioned are checked for
 197 ;; the usage of the agen unit
 198 ;;
 199
 200 (define_insn_reservation "x_int" 1
 201   (and (eq_attr "cpu" "z990")
 202        (eq_attr "atype" "reg"))
 203   "x-e1-st,x-wr-st")
 204
 205 (define_insn_reservation "x_agen" 1
 206   (and (eq_attr "cpu" "z990")
 207        (eq_attr "atype" "agen"))
 208   "x-e1-st+x-mem,x-wr-st")
 209
 210 ;;
 211 ;; s390_agen_dep_p returns 1, if a register is set in the
 212 ;; first insn and used in the dependent insn to form a address.
 213 ;;
 214
 215 ;;
 216 ;; If an instruction uses a register to address memory, it needs
 217 ;; to be set 5 cycles in advance.
 218 ;;
 219
 220 (define_bypass 5 "x_int,x_agen,x_lr"
 221                  "x_agen,x_la,x_call,x_load,x_store,x_ss,x_stm,x_lm"
 222                  "s390_agen_dep_p")
 223
 224 (define_bypass 9 "x_int,x_agen,x_lr"
 225                  "x_floadd, x_floads, x_fstored, x_fstores,\
 226                   x_fsimpd, x_fsimps, x_fdivd, x_fdivs"
 227                  "s390_agen_dep_p")
 228 ;;
 229 ;; A load type instruction uses a bypass to feed the result back
 230 ;; to the address generation pipeline stage.
 231 ;;
 232
 233 (define_bypass 4 "x_load"
 234                  "x_agen,x_la,x_call,x_load,x_store,x_ss,x_stm,x_lm"
 235                  "s390_agen_dep_p")
 236
 237 (define_bypass 5 "x_load"
 238                  "x_floadd, x_floads, x_fstored, x_fstores,\
 239                   x_fsimpd, x_fsimps, x_fdivd, x_fdivs"
 240                  "s390_agen_dep_p")
 241
 242 ;;
 243 ;; A load address type instruction uses a bypass to feed the
 244 ;; result back to the address generation pipeline stage.
 245 ;;
 246
 247 (define_bypass 3 "x_larl,x_la"
 248                  "x_agen,x_la,x_call,x_load,x_store,x_ss,x_stm,x_lm"
 249                  "s390_agen_dep_p")
 250
 251 (define_bypass 5 "x_larl, x_la"
 252                  "x_floadd, x_floads, x_fstored, x_fstores,\
 253                   x_fsimpd, x_fsimps, x_fdivd, x_fdivs"
 254                  "s390_agen_dep_p")
 255
 256 ;;
 257 ;; Operand forwarding
 258 ;;
 259
 260 (define_bypass 0 "x_lr,x_la,x_load" "x_int,x_lr")
 261
 262