gcc/config/s390/2084.md

   1 ;; Scheduling description for z990 (cpu 2084).
   2 ;;   Copyright (C) 2003,2004 Free Software Foundation, Inc.
   3 ;;   Contributed by Hartmut Penner (hpenner@de.ibm.com) and
   4 ;;                  Ulrich Weigand (uweigand@de.ibm.com).
   5
   6 ;; This file is part of GCC.
   7
   8 ;; GCC is free software; you can redistribute it and/or modify it under
   9 ;; the terms of the GNU General Public License as published by the Free
  10 ;; Software Foundation; either version 2, or (at your option) any later
  11 ;; version.
  12
  13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  14 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15 ;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16 ;; for more details.
  17
  18 ;; You should have received a copy of the GNU General Public License
  19 ;; along with GCC; see the file COPYING.  If not, write to the Free
  20 ;; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  21 ;; 02111-1307, USA.
  22
  23 (define_automaton "x_ipu")
  24
  25 (define_cpu_unit "x_e1_r,x_e1_s,x_e1_t"  "x_ipu")
  26 (define_cpu_unit "x_wr_r,x_wr_s,x_wr_t,x_wr_fp" "x_ipu")
  27 (define_cpu_unit "x_s1,x_s2,x_s3,x_s4"   "x_ipu")
  28 (define_cpu_unit "x_t1,x_t2,x_t3,x_t4"   "x_ipu")
  29 (define_cpu_unit "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6"   "x_ipu")
  30 (define_cpu_unit "x_store_tok"   "x_ipu")
  31 (define_cpu_unit "x_ms,x_mt"   "x_ipu")
  32
  33 (define_reservation "x-e1-st" "(x_e1_s | x_e1_t)")
  34
  35 (define_reservation "x-e1-np" "(x_e1_r + x_e1_s + x_e1_t)")
  36
  37 (absence_set "x_e1_r" "x_e1_s,x_e1_t")
  38 (absence_set "x_e1_s" "x_e1_t")
  39
  40 ;; Try to avoid int <-> fp transitions.
  41
  42 (define_reservation "x-x" "x_s1|x_t1,x_s2|x_t2,x_s3|x_t3,x_s4|x_t4")
  43 (define_reservation "x-f" "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6")
  44 (define_reservation "x-wr-st" "((x_wr_s | x_wr_t),x-x)")
  45 (define_reservation "x-wr-np" "((x_wr_r + x_wr_s + x_wr_t),x-x)")
  46 (define_reservation "x-wr-fp" "x_wr_fp,x-f")
  47 (define_reservation "x-mem"   "x_ms|x_mt")
  48
  49 (absence_set "x_wr_fp"
  50              "x_s1,x_s2,x_s3,x_s4,x_t1,x_t2,x_t3,x_t4,x_wr_s,x_wr_t")
  51
  52 (absence_set "x_e1_r,x_wr_r,x_wr_s,x_wr_t"
  53              "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6,x_wr_fp")
  54
  55 ;; Don't have any load type insn in same group as store
  56
  57 (absence_set "x_ms,x_mt" "x_store_tok")
  58
  59
  60 ;;
  61 ;; Simple insns
  62 ;;
  63
  64 (define_insn_reservation "x_int" 1
  65   (and (eq_attr "cpu" "z990")
  66        (and (eq_attr "type" "integer")
  67             (eq_attr "atype" "reg")))
  68   "x-e1-st,x-wr-st")
  69
  70 (define_insn_reservation "x_agen" 1
  71   (and (eq_attr "cpu" "z990")
  72        (and (eq_attr "type" "integer")
  73             (eq_attr "atype" "agen")))
  74   "x-e1-st,x-wr-st")
  75
  76 (define_insn_reservation "x_lr" 1
  77   (and (eq_attr "cpu" "z990")
  78        (eq_attr "type" "lr"))
  79   "x-e1-st,x-wr-st")
  80
  81 (define_insn_reservation "x_la" 1
  82   (and (eq_attr "cpu" "z990")
  83        (eq_attr "type" "la"))
  84   "x-e1-st,x-wr-st")
  85
  86 (define_insn_reservation "x_larl" 1
  87   (and (eq_attr "cpu" "z990")
  88        (eq_attr "type" "larl"))
  89   "x-e1-st,x-wr-st")
  90
  91 (define_insn_reservation "x_load" 1
  92   (and (eq_attr "cpu" "z990")
  93        (eq_attr "type" "load"))
  94   "x-e1-st+x-mem,x-wr-st")
  95
  96 (define_insn_reservation "x_store" 1
  97   (and (eq_attr "cpu" "z990")
  98        (eq_attr "type" "store"))
  99   "x-e1-st+x_store_tok,x-wr-st")
 100
 101 (define_insn_reservation "x_branch" 1
 102   (and (eq_attr "cpu" "z990")
 103        (eq_attr "type" "branch"))
 104   "x_e1_r,x_wr_r")
 105
 106 (define_insn_reservation "x_call" 5
 107   (and (eq_attr "cpu" "z990")
 108        (eq_attr "type" "jsr"))
 109   "x-e1-np*5,x-wr-np")
 110
 111 (define_insn_reservation "x_mul_hi" 2
 112   (and (eq_attr "cpu" "z990")
 113        (eq_attr "type" "imulhi"))
 114   "x-e1-np*2,x-wr-np")
 115
 116 (define_insn_reservation "x_mul_sidi" 4
 117   (and (eq_attr "cpu" "z990")
 118        (eq_attr "type" "imulsi,imuldi"))
 119   "x-e1-np*4,x-wr-np")
 120
 121 (define_insn_reservation "x_div" 10
 122   (and (eq_attr "cpu" "z990")
 123        (eq_attr "type" "idiv"))
 124   "x-e1-np*10,x-wr-np")
 125
 126 ;;
 127 ;; Multicycle insns
 128 ;;
 129
 130 (define_insn_reservation "x_cs" 1
 131   (and (eq_attr "cpu" "z990")
 132        (eq_attr "type" "cs"))
 133   "x-e1-np,x-wr-np")
 134
 135 (define_insn_reservation "x_vs" 1
 136   (and (eq_attr "cpu" "z990")
 137        (eq_attr "type" "vs"))
 138   "x-e1-np*10,x-wr-np")
 139
 140 (define_insn_reservation "x_stm" 1
 141   (and (eq_attr "cpu" "z990")
 142        (eq_attr "type" "stm"))
 143   "(x-e1-np+x_store_tok)*10,x-wr-np")
 144
 145 (define_insn_reservation "x_lm" 1
 146   (and (eq_attr "cpu" "z990")
 147        (eq_attr "type" "lm"))
 148   "x-e1-np*10,x-wr-np")
 149
 150 (define_insn_reservation "x_other" 1
 151   (and (eq_attr "cpu" "z990")
 152        (eq_attr "type" "other"))
 153   "x-e1-np,x-wr-np")
 154
 155 ;;
 156 ;; Floating point insns
 157 ;;
 158
 159 (define_insn_reservation "x_fsimpd" 6
 160   (and (eq_attr "cpu" "z990")
 161        (eq_attr "type" "fsimpd,fmuld"))
 162   "x_e1_t,x-wr-fp")
 163
 164 (define_insn_reservation "x_fsimps" 6
 165   (and (eq_attr "cpu" "z990")
 166        (eq_attr "type" "fsimps,fmuls"))
 167   "x_e1_t,x-wr-fp")
 168
 169 (define_insn_reservation "x_fdivd" 36
 170   (and (eq_attr "cpu" "z990")
 171        (eq_attr "type" "fdivd,fsqrtd"))
 172   "x_e1_t*30,x-wr-fp")
 173
 174 (define_insn_reservation "x_fdivs" 36
 175   (and (eq_attr "cpu" "z990")
 176        (eq_attr "type" "fdivs,fsqrts"))
 177   "x_e1_t*30,x-wr-fp")
 178
 179 (define_insn_reservation "x_floadd" 6
 180   (and (eq_attr "cpu" "z990")
 181        (eq_attr "type" "floadd"))
 182   "x_e1_t,x-wr-fp")
 183
 184 (define_insn_reservation "x_floads" 6
 185   (and (eq_attr "cpu" "z990")
 186        (eq_attr "type" "floads"))
 187   "x_e1_t,x-wr-fp")
 188
 189 (define_insn_reservation "x_fstored" 1
 190   (and (eq_attr "cpu" "z990")
 191        (eq_attr "type" "fstored"))
 192   "x_e1_t,x-wr-fp")
 193
 194 (define_insn_reservation "x_fstores" 1
 195   (and (eq_attr "cpu" "z990")
 196        (eq_attr "type" "fstores"))
 197   "x_e1_t,x-wr-fp")
 198
 199 (define_insn_reservation "x_ftoi" 1
 200   (and (eq_attr "cpu" "z990")
 201        (eq_attr "type" "ftoi"))
 202   "x_e1_t*3,x-wr-fp")
 203
 204 (define_insn_reservation "x_itof" 7
 205   (and (eq_attr "cpu" "z990")
 206        (eq_attr "type" "itof"))
 207   "x_e1_t*3,x-wr-fp")
 208
 209 (define_bypass 1 "x_fsimpd" "x_fstored")
 210
 211 (define_bypass 1 "x_fsimps" "x_fstores")
 212
 213 (define_bypass 1 "x_floadd" "x_fsimpd,x_fstored,x_floadd")
 214
 215 (define_bypass 1 "x_floads" "x_fsimps,x_fstores,x_floads")
 216
 217 ;;
 218 ;; s390_agen_dep_p returns 1, if a register is set in the
 219 ;; first insn and used in the dependent insn to form a address.
 220 ;;
 221
 222 ;;
 223 ;; If an instruction uses a register to address memory, it needs
 224 ;; to be set 5 cycles in advance.
 225 ;;
 226
 227 (define_bypass 5 "x_int,x_agen,x_lr"
 228                  "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other"
 229                  "s390_agen_dep_p")
 230
 231 (define_bypass 9 "x_int,x_agen,x_lr"
 232                  "x_floadd, x_floads, x_fstored, x_fstores,\
 233                   x_fsimpd, x_fsimps, x_fdivd, x_fdivs"
 234                  "s390_agen_dep_p")
 235 ;;
 236 ;; A load type instruction uses a bypass to feed the result back
 237 ;; to the address generation pipeline stage.
 238 ;;
 239
 240 (define_bypass 4 "x_load"
 241                  "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other"
 242                  "s390_agen_dep_p")
 243
 244 (define_bypass 5 "x_load"
 245                  "x_floadd, x_floads, x_fstored, x_fstores,\
 246                   x_fsimpd, x_fsimps, x_fdivd, x_fdivs"
 247                  "s390_agen_dep_p")
 248
 249 ;;
 250 ;; A load address type instruction uses a bypass to feed the
 251 ;; result back to the address generation pipeline stage.
 252 ;;
 253
 254 (define_bypass 3 "x_larl,x_la"
 255                  "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other"
 256                  "s390_agen_dep_p")
 257
 258 (define_bypass 5 "x_larl, x_la"
 259                  "x_floadd, x_floads, x_fstored, x_fstores,\
 260                   x_fsimpd, x_fsimps, x_fdivd, x_fdivs"
 261                  "s390_agen_dep_p")
 262
 263 ;;
 264 ;; Operand forwarding
 265 ;;
 266
 267 (define_bypass 0 "x_lr,x_la,x_load" "x_int,x_lr")
 268
 269