1 ;; Predicate definitions for S/390 and zSeries.
2 ;; Copyright (C) 2005-2019 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com).
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 ;; OP is the current operation.
23 ;; MODE is the current operation mode.
25 ;; operands --------------------------------------------------------------
27 ;; Return true if OP a const 0 operand (int/float/vector).
28 (define_predicate "const0_operand"
29 (and (match_code "const_int,const_wide_int,const_double,const_vector")
30 (match_test "op == CONST0_RTX (mode)")))
32 ;; Return true if OP an all ones operand (int/vector).
33 (define_predicate "all_ones_operand"
34 (and (match_code "const_int, const_wide_int, const_vector")
35 (match_test "INTEGRAL_MODE_P (GET_MODE (op))")
36 (match_test "op == CONSTM1_RTX (mode)")))
38 ;; Return true if OP is a 4 bit mask operand
39 (define_predicate "const_mask_operand"
40 (and (match_code "const_int")
41 (match_test "UINTVAL (op) < 16")))
43 ;; Return true if OP is constant.
45 (define_special_predicate "consttable_operand"
46 (and (match_code "symbol_ref, label_ref, const, const_int, const_wide_int, const_double, const_vector")
47 (match_test "CONSTANT_P (op)")))
49 ; An operand used as vector permutation pattern
51 ; This in particular accepts constants which would otherwise be
52 ; rejected. These constants require special post reload handling
54 (define_special_predicate "permute_pattern_operand"
55 (and (match_code "const_vector,mem,reg,subreg")
56 (match_test "GET_MODE (op) == V16QImode")
57 (match_test "!MEM_P (op) || s390_mem_constraint (\"R\", op)")))
59 ;; Return true if OP is a valid S-type operand.
61 (define_predicate "s_operand"
62 (and (match_code "subreg, mem")
63 (match_operand 0 "general_operand"))
65 /* Just like memory_operand, allow (subreg (mem ...))
68 && GET_CODE (op) == SUBREG
69 && GET_CODE (SUBREG_REG (op)) == MEM)
72 if (GET_CODE (op) != MEM)
74 if (!s390_legitimate_address_without_index_p (op))
80 ;; Return true of the address of the mem operand plus 16 is still a
81 ;; valid Q constraint address.
83 (define_predicate "plus16_Q_operand"
84 (and (match_code "mem")
85 (match_operand 0 "general_operand"))
87 rtx addr = XEXP (op, 0);
91 if (GET_CODE (addr) != PLUS
92 || !REG_P (XEXP (addr, 0))
93 || !CONST_INT_P (XEXP (addr, 1)))
96 return SHORT_DISP_IN_RANGE (INTVAL (XEXP (addr, 1)) + 16);
99 ;; Return true if OP is a valid operand for the BRAS instruction.
100 ;; Allow SYMBOL_REFs and @PLT stubs.
102 (define_special_predicate "bras_sym_operand"
103 (ior (and (match_code "symbol_ref")
104 (match_test "!flag_pic || SYMBOL_REF_LOCAL_P (op)"))
105 (and (match_code "const")
106 (and (match_test "GET_CODE (XEXP (op, 0)) == UNSPEC")
107 (match_test "XINT (XEXP (op, 0), 1) == UNSPEC_PLT")))))
109 ;; Return true if OP is a PLUS that is not a legitimate
110 ;; operand for the LA instruction.
112 (define_predicate "s390_plus_operand"
113 (and (match_code "plus")
114 (and (match_test "mode == Pmode")
115 (match_test "!legitimate_la_operand_p (op)"))))
117 ;; Return true if OP is a valid operand as scalar shift count or setmem.
119 (define_predicate "setmem_operand"
120 (match_code "reg, subreg, plus, const_int")
122 HOST_WIDE_INT offset;
125 if (GET_MODE (op) != VOIDmode
126 && GET_MODE_CLASS (GET_MODE (op)) != MODE_INT)
129 /* Extract base register and offset. */
130 if (!s390_decompose_addrstyle_without_index (op, &base, &offset))
133 /* Don't allow any non-base hard registers. Doing so without
134 confusing reload and/or regrename would be tricky, and doesn't
135 buy us much anyway. */
136 if (base && REGNO (base) < FIRST_PSEUDO_REGISTER && !ADDR_REG_P (base))
139 /* Unfortunately we have to reject constants that are invalid
140 for an address, or else reload will get confused. */
141 if (!DISP_IN_RANGE (offset))
147 ; An integer operand with the lowest order 6 bits all ones.
148 (define_predicate "const_int_6bitset_operand"
149 (and (match_code "const_int")
150 (match_test "(INTVAL (op) & 63) == 63")))
151 (define_predicate "nonzero_shift_count_operand"
152 (and (match_code "const_int")
153 (match_test "IN_RANGE (INTVAL (op), 1, GET_MODE_BITSIZE (mode) - 1)")))
155 ;; Return true if OP a valid operand for the LARL instruction.
157 (define_predicate "larl_operand"
158 (match_code "label_ref, symbol_ref, const")
160 /* Allow labels and local symbols. */
161 if (GET_CODE (op) == LABEL_REF)
163 if (SYMBOL_REF_P (op))
164 return (!SYMBOL_FLAG_NOTALIGN2_P (op)
165 && SYMBOL_REF_TLS_MODEL (op) == 0
166 && s390_rel_address_ok_p (op));
168 /* Everything else must have a CONST, so strip it. */
169 if (GET_CODE (op) != CONST)
173 /* Allow adding *even* in-range constants. */
174 if (GET_CODE (op) == PLUS)
176 if (GET_CODE (XEXP (op, 1)) != CONST_INT
177 || (INTVAL (XEXP (op, 1)) & 1) != 0)
179 if (INTVAL (XEXP (op, 1)) >= HOST_WIDE_INT_1 << 31
180 || INTVAL (XEXP (op, 1)) < -(HOST_WIDE_INT_1 << 31))
185 /* Labels and local symbols allowed here as well. */
186 if (GET_CODE (op) == LABEL_REF)
188 if (SYMBOL_REF_P (op))
189 return (!SYMBOL_FLAG_NOTALIGN2_P (op)
190 && SYMBOL_REF_TLS_MODEL (op) == 0
191 && s390_rel_address_ok_p (op));
194 /* Now we must have a @GOTENT offset or @PLT stub
195 or an @INDNTPOFF TLS offset. */
196 if (GET_CODE (op) == UNSPEC
197 && XINT (op, 1) == UNSPEC_GOTENT)
199 if (GET_CODE (op) == UNSPEC
200 && XINT (op, 1) == UNSPEC_PLT)
202 if (GET_CODE (op) == UNSPEC
203 && XINT (op, 1) == UNSPEC_INDNTPOFF)
209 ; Predicate that always allows wraparound of the one-bit range.
210 (define_predicate "contiguous_bitmask_operand"
211 (match_code "const_int")
213 return s390_contiguous_bitmask_p (INTVAL (op), true,
214 GET_MODE_BITSIZE (mode), NULL, NULL);
217 ; Same without wraparound.
218 (define_predicate "contiguous_bitmask_nowrap_operand"
219 (match_code "const_int")
221 return s390_contiguous_bitmask_p
222 (INTVAL (op), false, GET_MODE_BITSIZE (mode), NULL, NULL);
225 ;; Return true if OP is legitimate for any LOC instruction.
227 (define_predicate "loc_operand"
228 (ior (match_operand 0 "nonimmediate_operand")
229 (and (match_code "const_int")
230 (match_test "INTVAL (op) <= 32767 && INTVAL (op) >= -32768"))))
232 (define_predicate "reload_const_wide_int_operand"
233 (and (match_code "const_wide_int")
234 (match_test "legitimate_reload_constant_p (op)")))
237 ;; operators --------------------------------------------------------------
239 ;; Return nonzero if OP is a valid comparison operator
240 ;; for a branch condition.
242 (define_predicate "s390_comparison"
243 (match_code "eq, ne, lt, gt, le, ge, ltu, gtu, leu, geu,
244 uneq, unlt, ungt, unle, unge, ltgt,
247 if (GET_CODE (XEXP (op, 0)) != REG
248 || REGNO (XEXP (op, 0)) != CC_REGNUM
249 || (XEXP (op, 1) != const0_rtx
250 && !(CONST_INT_P (XEXP (op, 1))
251 && GET_MODE (XEXP (op, 0)) == CCRAWmode
252 && INTVAL (XEXP (op, 1)) >= 0
253 && INTVAL (XEXP (op, 1)) <= 15)))
256 return (s390_branch_condition_mask (op) >= 0);
259 ;; Return true if op is the cc register.
260 (define_predicate "cc_reg_operand"
261 (and (match_code "reg")
262 (match_test "REGNO (op) == CC_REGNUM")))
264 (define_predicate "s390_signed_integer_comparison"
265 (match_code "eq, ne, lt, gt, le, ge")
267 return (s390_compare_and_branch_condition_mask (op) >= 0);
270 (define_predicate "s390_unsigned_integer_comparison"
271 (match_code "eq, ne, ltu, gtu, leu, geu")
273 return (s390_compare_and_branch_condition_mask (op) >= 0);
276 ;; Return nonzero if OP is a valid comparison operator for the
277 ;; cstore expanders -- respectively cstorecc4 and integer cstore.
278 (define_predicate "s390_eqne_operator"
279 (match_code "eq, ne"))
281 (define_predicate "s390_scond_operator"
282 (match_code "ltu, gtu, leu, geu"))
284 (define_predicate "s390_brx_operator"
285 (match_code "le, gt"))
287 ;; Return nonzero if OP is a valid comparison operator
288 ;; for an ALC condition.
290 (define_predicate "s390_alc_comparison"
291 (match_code "zero_extend, sign_extend, ltu, gtu, leu, geu")
293 while (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND)
296 if (!COMPARISON_P (op))
299 if (GET_CODE (XEXP (op, 0)) != REG
300 || REGNO (XEXP (op, 0)) != CC_REGNUM
301 || (XEXP (op, 1) != const0_rtx
302 && !(CONST_INT_P (XEXP (op, 1))
303 && GET_MODE (XEXP (op, 0)) == CCRAWmode
304 && INTVAL (XEXP (op, 1)) >= 0
305 && INTVAL (XEXP (op, 1)) <= 15)))
308 switch (GET_MODE (XEXP (op, 0)))
311 return GET_CODE (op) == LTU;
314 return GET_CODE (op) == LEU;
317 return GET_CODE (op) == GEU;
320 return GET_CODE (op) == GTU;
323 return GET_CODE (op) == LTU;
326 return GET_CODE (op) == UNGT;
329 return GET_CODE (op) == UNLT;
336 ;; Return nonzero if OP is a valid comparison operator
337 ;; for an SLB condition.
339 (define_predicate "s390_slb_comparison"
340 (match_code "zero_extend, sign_extend, ltu, gtu, leu, geu")
342 while (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND)
345 if (!COMPARISON_P (op))
348 if (GET_CODE (XEXP (op, 0)) != REG
349 || REGNO (XEXP (op, 0)) != CC_REGNUM
350 || XEXP (op, 1) != const0_rtx)
353 switch (GET_MODE (XEXP (op, 0)))
356 return GET_CODE (op) == GEU;
359 return GET_CODE (op) == GTU;
362 return GET_CODE (op) == LTU;
365 return GET_CODE (op) == LEU;
368 return GET_CODE (op) == GEU;
371 return GET_CODE (op) == LE;
374 return GET_CODE (op) == GE;
381 ;; Return true if OP is a load multiple operation. It is known to be a
382 ;; PARALLEL and the first section will be tested.
384 (define_special_predicate "load_multiple_operation"
385 (match_code "parallel")
387 machine_mode elt_mode;
388 int count = XVECLEN (op, 0);
389 unsigned int dest_regno;
393 /* Perform a quick check so we don't blow up below. */
395 || GET_CODE (XVECEXP (op, 0, 0)) != SET
396 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
397 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
400 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
401 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
402 elt_mode = GET_MODE (SET_DEST (XVECEXP (op, 0, 0)));
404 /* Check, is base, or base + displacement. */
406 if (GET_CODE (src_addr) == REG)
408 else if (GET_CODE (src_addr) == PLUS
409 && GET_CODE (XEXP (src_addr, 0)) == REG
410 && GET_CODE (XEXP (src_addr, 1)) == CONST_INT)
412 off = INTVAL (XEXP (src_addr, 1));
413 src_addr = XEXP (src_addr, 0);
418 for (i = 1; i < count; i++)
420 rtx elt = XVECEXP (op, 0, i);
422 if (GET_CODE (elt) != SET
423 || GET_CODE (SET_DEST (elt)) != REG
424 || GET_MODE (SET_DEST (elt)) != elt_mode
425 || REGNO (SET_DEST (elt)) != dest_regno + i
426 || GET_CODE (SET_SRC (elt)) != MEM
427 || GET_MODE (SET_SRC (elt)) != elt_mode
428 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
429 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
430 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
431 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1))
432 != off + i * GET_MODE_SIZE (elt_mode))
439 ;; For an execute pattern the target instruction is embedded into the
440 ;; RTX but will not get checked for validity by recog automatically.
441 ;; The execute_operation predicate extracts the target RTX and invokes
443 (define_special_predicate "execute_operation"
444 (match_code "parallel")
450 /* This is redundant but since this predicate is evaluated
451 first when recognizing the insn we can prevent the more
452 expensive code below from being executed for many cases. */
453 if (GET_CODE (XVECEXP (pattern, 0, 0)) != UNSPEC
454 || XINT (XVECEXP (pattern, 0, 0), 1) != UNSPEC_EXECUTE)
457 /* Keep in sync with s390_execute_target. */
458 if (XVECLEN (pattern, 0) == 2)
460 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
464 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
467 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
468 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
470 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
473 /* Since we do not have the wrapping insn here we have to build one. */
474 insn = make_insn_raw (pattern);
475 icode = recog_memoized (insn);
479 extract_constrain_insn (insn);
481 return which_alternative >= 0;
484 ;; Return true if OP is a store multiple operation. It is known to be a
485 ;; PARALLEL and the first section will be tested.
487 (define_special_predicate "store_multiple_operation"
488 (match_code "parallel")
490 machine_mode elt_mode;
491 int count = XVECLEN (op, 0);
492 unsigned int src_regno;
496 /* Perform a quick check so we don't blow up below. */
498 || GET_CODE (XVECEXP (op, 0, 0)) != SET
499 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
500 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
503 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
504 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
505 elt_mode = GET_MODE (SET_SRC (XVECEXP (op, 0, 0)));
507 /* Check, is base, or base + displacement. */
509 if (GET_CODE (dest_addr) == REG)
511 else if (GET_CODE (dest_addr) == PLUS
512 && GET_CODE (XEXP (dest_addr, 0)) == REG
513 && GET_CODE (XEXP (dest_addr, 1)) == CONST_INT)
515 off = INTVAL (XEXP (dest_addr, 1));
516 dest_addr = XEXP (dest_addr, 0);
521 for (i = 1; i < count; i++)
523 rtx elt = XVECEXP (op, 0, i);
525 if (GET_CODE (elt) != SET
526 || GET_CODE (SET_SRC (elt)) != REG
527 || GET_MODE (SET_SRC (elt)) != elt_mode
528 || REGNO (SET_SRC (elt)) != src_regno + i
529 || GET_CODE (SET_DEST (elt)) != MEM
530 || GET_MODE (SET_DEST (elt)) != elt_mode
531 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
532 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
533 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
534 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1))
535 != off + i * GET_MODE_SIZE (elt_mode))
541 (define_predicate "const_shift_by_byte_operand"
542 (match_code "const_int")
544 unsigned HOST_WIDE_INT val = INTVAL (op);
545 return val <= 128 && val % 8 == 0;
548 ;; Certain operations (e.g. CS) cannot access SYMBOL_REF directly, it needs to
549 ;; be loaded into some register first. In theory, if we put a SYMBOL_REF into
550 ;; a corresponding insn anyway, reload will generate a load for it, but, when
551 ;; coupled with constant propagation, this will lead to an inefficient code
554 (define_predicate "nonsym_memory_operand"
557 return memory_operand (op, mode) && !contains_symbol_ref_p (op);
560 ;; Check for a valid shift count operand with an implicit
561 ;; shift truncation mask of 63.
563 (define_predicate "shift_count_operand"
564 (and (match_code "reg, subreg, and, plus, const_int")
565 (match_test "CONST_INT_P (op) || GET_MODE (op) == E_QImode"))
567 return s390_valid_shift_count (op, 63);
571 ;; This is used as operand predicate. As we do not know
572 ;; the mode of the first operand here and the shift truncation
573 ;; mask depends on the mode, we cannot check the mask.
574 ;; This is supposed to happen in the insn condition which
575 ;; calls s390_valid_shift_count with the proper mode size.
576 ;; We need two separate predicates for non-vector and vector
577 ;; shifts since the (less restrictive) insn condition is checked
578 ;; after the more restrictive operand predicate which will
579 ;; disallow the operand before we can check the condition.
581 (define_predicate "shift_count_operand_vec"
582 (and (match_code "reg, subreg, and, plus, const_int")
583 (match_test "CONST_INT_P (op) || GET_MODE (op) == E_QImode"))
585 return s390_valid_shift_count (op, 0);
589 ; An integer constant which can be used in a signed add with overflow
590 ; pattern without being reloaded.
591 (define_predicate "addv_const_operand"
592 (and (match_code "const_int")
593 (match_test "INTVAL (op) >= -32768 && INTVAL (op) <= 32767")))