gcc/config/s390/predicates.md

   1 ;; Predicate definitions for S/390 and zSeries.
   2 ;; Copyright (C) 2005-2016 Free Software Foundation, Inc.
   3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
   4 ;;                Ulrich Weigand (uweigand@de.ibm.com).
   5 ;;
   6 ;; This file is part of GCC.
   7 ;;
   8 ;; GCC is free software; you can redistribute it and/or modify
   9 ;; it under the terms of the GNU General Public License as published by
  10 ;; the Free Software Foundation; either version 3, or (at your option)
  11 ;; any later version.
  12 ;;
  13 ;; GCC is distributed in the hope that it will be useful,
  14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 ;; GNU General Public License for more details.
  17 ;;
  18 ;; You should have received a copy of the GNU General Public License
  19 ;; along with GCC; see the file COPYING3.  If not see
  20 ;; <http://www.gnu.org/licenses/>.
  21
  22 ;; OP is the current operation.
  23 ;; MODE is the current operation mode.
  24
  25 ;; operands --------------------------------------------------------------
  26
  27 ;; Return true if OP a const 0 operand (int/float/vector).
  28 (define_predicate "const0_operand"
  29   (and (match_code "const_int,const_wide_int,const_double,const_vector")
  30        (match_test "op == CONST0_RTX (mode)")))
  31
  32 ;; Return true if OP an all ones operand (int/vector).
  33 (define_predicate "all_ones_operand"
  34   (and (match_code "const_int, const_wide_int, const_vector")
  35        (match_test "INTEGRAL_MODE_P (GET_MODE (op))")
  36        (match_test "op == CONSTM1_RTX (mode)")))
  37
  38 ;; Return true if OP is a 4 bit mask operand
  39 (define_predicate "const_mask_operand"
  40   (and (match_code "const_int")
  41        (match_test "UINTVAL (op) < 16")))
  42
  43 ;; Return true if OP is constant.
  44
  45 (define_special_predicate "consttable_operand"
  46   (and (match_code "symbol_ref, label_ref, const, const_int, const_wide_int, const_double, const_vector")
  47        (match_test "CONSTANT_P (op)")))
  48
  49 ;; Return true if OP is a valid S-type operand.
  50
  51 (define_predicate "s_operand"
  52   (and (match_code "subreg, mem")
  53        (match_operand 0 "general_operand"))
  54 {
  55   /* Just like memory_operand, allow (subreg (mem ...))
  56      after reload.  */
  57   if (reload_completed
  58       && GET_CODE (op) == SUBREG
  59       && GET_CODE (SUBREG_REG (op)) == MEM)
  60     op = SUBREG_REG (op);
  61
  62   if (GET_CODE (op) != MEM)
  63     return false;
  64   if (!s390_legitimate_address_without_index_p (op))
  65     return false;
  66
  67   return true;
  68 })
  69
  70 ;; Return true if OP is a valid operand for the BRAS instruction.
  71 ;; Allow SYMBOL_REFs and @PLT stubs.
  72
  73 (define_special_predicate "bras_sym_operand"
  74   (ior (and (match_code "symbol_ref")
  75             (match_test "!flag_pic || SYMBOL_REF_LOCAL_P (op)"))
  76        (and (match_code "const")
  77             (and (match_test "GET_CODE (XEXP (op, 0)) == UNSPEC")
  78                  (match_test "XINT (XEXP (op, 0), 1) == UNSPEC_PLT")))))
  79
  80 ;; Return true if OP is a PLUS that is not a legitimate
  81 ;; operand for the LA instruction.
  82
  83 (define_predicate "s390_plus_operand"
  84   (and (match_code "plus")
  85        (and (match_test "mode == Pmode")
  86             (match_test "!legitimate_la_operand_p (op)"))))
  87
  88 ;; Return true if OP is a valid operand as scalar shift count or setmem.
  89
  90 (define_predicate "shift_count_or_setmem_operand"
  91   (match_code "reg, subreg, plus, const_int")
  92 {
  93   HOST_WIDE_INT offset;
  94   rtx base;
  95
  96   if (GET_MODE (op) != VOIDmode
  97       && GET_MODE_CLASS (GET_MODE (op)) != MODE_INT)
  98     return false;
  99
 100   /* Extract base register and offset.  */
 101   if (!s390_decompose_shift_count (op, &base, &offset))
 102     return false;
 103
 104   /* Don't allow any non-base hard registers.  Doing so without
 105      confusing reload and/or regrename would be tricky, and doesn't
 106      buy us much anyway.  */
 107   if (base && REGNO (base) < FIRST_PSEUDO_REGISTER && !ADDR_REG_P (base))
 108     return false;
 109
 110   /* Unfortunately we have to reject constants that are invalid
 111      for an address, or else reload will get confused.  */
 112   if (!DISP_IN_RANGE (offset))
 113     return false;
 114
 115   return true;
 116 })
 117
 118 (define_predicate "nonzero_shift_count_operand"
 119   (and (match_code "const_int")
 120        (match_test "IN_RANGE (INTVAL (op), 1, GET_MODE_BITSIZE (mode) - 1)")))
 121
 122 ;;  Return true if OP a valid operand for the LARL instruction.
 123
 124 (define_predicate "larl_operand"
 125   (match_code "label_ref, symbol_ref, const")
 126 {
 127   /* Allow labels and local symbols.  */
 128   if (GET_CODE (op) == LABEL_REF)
 129     return true;
 130   if (GET_CODE (op) == SYMBOL_REF)
 131     return (!SYMBOL_FLAG_NOTALIGN2_P (op)
 132             && SYMBOL_REF_TLS_MODEL (op) == 0
 133             && (!flag_pic || SYMBOL_REF_LOCAL_P (op)));
 134
 135   /* Everything else must have a CONST, so strip it.  */
 136   if (GET_CODE (op) != CONST)
 137     return false;
 138   op = XEXP (op, 0);
 139
 140   /* Allow adding *even* in-range constants.  */
 141   if (GET_CODE (op) == PLUS)
 142     {
 143       if (GET_CODE (XEXP (op, 1)) != CONST_INT
 144           || (INTVAL (XEXP (op, 1)) & 1) != 0)
 145         return false;
 146       if (INTVAL (XEXP (op, 1)) >= (HOST_WIDE_INT)1 << 31
 147           || INTVAL (XEXP (op, 1)) < -((HOST_WIDE_INT)1 << 31))
 148         return false;
 149       op = XEXP (op, 0);
 150     }
 151
 152   /* Labels and local symbols allowed here as well.  */
 153   if (GET_CODE (op) == LABEL_REF)
 154     return true;
 155   if (GET_CODE (op) == SYMBOL_REF)
 156     return (!SYMBOL_FLAG_NOTALIGN2_P (op)
 157             && SYMBOL_REF_TLS_MODEL (op) == 0
 158             && (!flag_pic || SYMBOL_REF_LOCAL_P (op)));
 159
 160   /* Now we must have a @GOTENT offset or @PLT stub
 161      or an @INDNTPOFF TLS offset.  */
 162   if (GET_CODE (op) == UNSPEC
 163       && XINT (op, 1) == UNSPEC_GOTENT)
 164     return true;
 165   if (GET_CODE (op) == UNSPEC
 166       && XINT (op, 1) == UNSPEC_PLT)
 167     return true;
 168   if (GET_CODE (op) == UNSPEC
 169       && XINT (op, 1) == UNSPEC_INDNTPOFF)
 170     return true;
 171
 172   return false;
 173 })
 174
 175 (define_predicate "contiguous_bitmask_operand"
 176   (match_code "const_int")
 177 {
 178   return s390_contiguous_bitmask_p (INTVAL (op), GET_MODE_BITSIZE (mode), NULL, NULL);
 179 })
 180
 181 ;; operators --------------------------------------------------------------
 182
 183 ;; Return nonzero if OP is a valid comparison operator
 184 ;; for a branch condition.
 185
 186 (define_predicate "s390_comparison"
 187   (match_code "eq, ne, lt, gt, le, ge, ltu, gtu, leu, geu,
 188                uneq, unlt, ungt, unle, unge, ltgt,
 189                unordered, ordered")
 190 {
 191   if (GET_CODE (XEXP (op, 0)) != REG
 192       || REGNO (XEXP (op, 0)) != CC_REGNUM
 193       || (XEXP (op, 1) != const0_rtx
 194           && !(CONST_INT_P (XEXP (op, 1))
 195                && GET_MODE (XEXP (op, 0)) == CCRAWmode
 196                && INTVAL (XEXP (op, 1)) >= 0
 197                && INTVAL (XEXP (op, 1)) <= 15)))
 198     return false;
 199
 200   return (s390_branch_condition_mask (op) >= 0);
 201 })
 202
 203 ;; Return true if op is the cc register.
 204 (define_predicate "cc_reg_operand"
 205   (and (match_code "reg")
 206        (match_test "REGNO (op) == CC_REGNUM")))
 207
 208 (define_predicate "s390_signed_integer_comparison"
 209   (match_code "eq, ne, lt, gt, le, ge")
 210 {
 211   return (s390_compare_and_branch_condition_mask (op) >= 0);
 212 })
 213
 214 (define_predicate "s390_unsigned_integer_comparison"
 215   (match_code "eq, ne, ltu, gtu, leu, geu")
 216 {
 217   return (s390_compare_and_branch_condition_mask (op) >= 0);
 218 })
 219
 220 ;; Return nonzero if OP is a valid comparison operator for the
 221 ;; cstore expanders -- respectively cstorecc4 and integer cstore.
 222 (define_predicate "s390_eqne_operator"
 223   (match_code "eq, ne"))
 224
 225 (define_predicate "s390_scond_operator"
 226   (match_code "ltu, gtu, leu, geu"))
 227
 228 (define_predicate "s390_brx_operator"
 229   (match_code "le, gt"))
 230
 231 ;; Return nonzero if OP is a valid comparison operator
 232 ;; for an ALC condition.
 233
 234 (define_predicate "s390_alc_comparison"
 235   (match_code "zero_extend, sign_extend, ltu, gtu, leu, geu")
 236 {
 237   while (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND)
 238     op = XEXP (op, 0);
 239
 240   if (!COMPARISON_P (op))
 241     return false;
 242
 243   if (GET_CODE (XEXP (op, 0)) != REG
 244       || REGNO (XEXP (op, 0)) != CC_REGNUM
 245       || (XEXP (op, 1) != const0_rtx
 246           && !(CONST_INT_P (XEXP (op, 1))
 247                && GET_MODE (XEXP (op, 0)) == CCRAWmode
 248                && INTVAL (XEXP (op, 1)) >= 0
 249                && INTVAL (XEXP (op, 1)) <= 15)))
 250     return false;
 251
 252   switch (GET_MODE (XEXP (op, 0)))
 253     {
 254     case CCL1mode:
 255       return GET_CODE (op) == LTU;
 256
 257     case CCL2mode:
 258       return GET_CODE (op) == LEU;
 259
 260     case CCL3mode:
 261       return GET_CODE (op) == GEU;
 262
 263     case CCUmode:
 264       return GET_CODE (op) == GTU;
 265
 266     case CCURmode:
 267       return GET_CODE (op) == LTU;
 268
 269     case CCSmode:
 270       return GET_CODE (op) == UNGT;
 271
 272     case CCSRmode:
 273       return GET_CODE (op) == UNLT;
 274
 275     default:
 276       return false;
 277     }
 278 })
 279
 280 ;; Return nonzero if OP is a valid comparison operator
 281 ;; for an SLB condition.
 282
 283 (define_predicate "s390_slb_comparison"
 284   (match_code "zero_extend, sign_extend, ltu, gtu, leu, geu")
 285 {
 286   while (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND)
 287     op = XEXP (op, 0);
 288
 289   if (!COMPARISON_P (op))
 290     return false;
 291
 292   if (GET_CODE (XEXP (op, 0)) != REG
 293       || REGNO (XEXP (op, 0)) != CC_REGNUM
 294       || XEXP (op, 1) != const0_rtx)
 295     return false;
 296
 297   switch (GET_MODE (XEXP (op, 0)))
 298     {
 299     case CCL1mode:
 300       return GET_CODE (op) == GEU;
 301
 302     case CCL2mode:
 303       return GET_CODE (op) == GTU;
 304
 305     case CCL3mode:
 306       return GET_CODE (op) == LTU;
 307
 308     case CCUmode:
 309       return GET_CODE (op) == LEU;
 310
 311     case CCURmode:
 312       return GET_CODE (op) == GEU;
 313
 314     case CCSmode:
 315       return GET_CODE (op) == LE;
 316
 317     case CCSRmode:
 318       return GET_CODE (op) == GE;
 319
 320     default:
 321       return false;
 322     }
 323 })
 324
 325 ;; Return true if OP is a load multiple operation.  It is known to be a
 326 ;; PARALLEL and the first section will be tested.
 327
 328 (define_special_predicate "load_multiple_operation"
 329   (match_code "parallel")
 330 {
 331   machine_mode elt_mode;
 332   int count = XVECLEN (op, 0);
 333   unsigned int dest_regno;
 334   rtx src_addr;
 335   int i, off;
 336
 337   /* Perform a quick check so we don't blow up below.  */
 338   if (count <= 1
 339       || GET_CODE (XVECEXP (op, 0, 0)) != SET
 340       || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
 341       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
 342     return false;
 343
 344   dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
 345   src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
 346   elt_mode = GET_MODE (SET_DEST (XVECEXP (op, 0, 0)));
 347
 348   /* Check, is base, or base + displacement.  */
 349
 350   if (GET_CODE (src_addr) == REG)
 351     off = 0;
 352   else if (GET_CODE (src_addr) == PLUS
 353            && GET_CODE (XEXP (src_addr, 0)) == REG
 354            && GET_CODE (XEXP (src_addr, 1)) == CONST_INT)
 355     {
 356       off = INTVAL (XEXP (src_addr, 1));
 357       src_addr = XEXP (src_addr, 0);
 358     }
 359   else
 360     return false;
 361
 362   for (i = 1; i < count; i++)
 363     {
 364       rtx elt = XVECEXP (op, 0, i);
 365
 366       if (GET_CODE (elt) != SET
 367           || GET_CODE (SET_DEST (elt)) != REG
 368           || GET_MODE (SET_DEST (elt)) != elt_mode
 369           || REGNO (SET_DEST (elt)) != dest_regno + i
 370           || GET_CODE (SET_SRC (elt)) != MEM
 371           || GET_MODE (SET_SRC (elt)) != elt_mode
 372           || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
 373           || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
 374           || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
 375           || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1))
 376              != off + i * GET_MODE_SIZE (elt_mode))
 377         return false;
 378     }
 379
 380   return true;
 381 })
 382
 383 ;; For an execute pattern the target instruction is embedded into the
 384 ;; RTX but will not get checked for validity by recog automatically.
 385 ;; The execute_operation predicate extracts the target RTX and invokes
 386 ;; recog.
 387 (define_special_predicate "execute_operation"
 388   (match_code "parallel")
 389 {
 390   rtx pattern = op;
 391   rtx_insn *insn;
 392   int icode;
 393
 394   /* This is redundant but since this predicate is evaluated
 395      first when recognizing the insn we can prevent the more
 396      expensive code below from being executed for many cases.  */
 397   if (GET_CODE (XVECEXP (pattern, 0, 0)) != UNSPEC
 398       || XINT (XVECEXP (pattern, 0, 0), 1) != UNSPEC_EXECUTE)
 399     return false;
 400
 401   /* Keep in sync with s390_execute_target.  */
 402   if (XVECLEN (pattern, 0) == 2)
 403     {
 404       pattern = copy_rtx (XVECEXP (pattern, 0, 1));
 405     }
 406   else
 407     {
 408       rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
 409       int i;
 410
 411       for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
 412         RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
 413
 414       pattern = gen_rtx_PARALLEL (VOIDmode, vec);
 415     }
 416
 417   /* Since we do not have the wrapping insn here we have to build one.  */
 418   insn = make_insn_raw (pattern);
 419   icode = recog_memoized (insn);
 420   if (icode < 0)
 421     return false;
 422
 423   extract_constrain_insn (insn);
 424
 425   return which_alternative >= 0;
 426 })
 427
 428 ;; Return true if OP is a store multiple operation.  It is known to be a
 429 ;; PARALLEL and the first section will be tested.
 430
 431 (define_special_predicate "store_multiple_operation"
 432   (match_code "parallel")
 433 {
 434   machine_mode elt_mode;
 435   int count = XVECLEN (op, 0);
 436   unsigned int src_regno;
 437   rtx dest_addr;
 438   int i, off;
 439
 440   /* Perform a quick check so we don't blow up below.  */
 441   if (count <= 1
 442       || GET_CODE (XVECEXP (op, 0, 0)) != SET
 443       || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
 444       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
 445     return false;
 446
 447   src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
 448   dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
 449   elt_mode = GET_MODE (SET_SRC (XVECEXP (op, 0, 0)));
 450
 451   /* Check, is base, or base + displacement.  */
 452
 453   if (GET_CODE (dest_addr) == REG)
 454     off = 0;
 455   else if (GET_CODE (dest_addr) == PLUS
 456            && GET_CODE (XEXP (dest_addr, 0)) == REG
 457            && GET_CODE (XEXP (dest_addr, 1)) == CONST_INT)
 458     {
 459       off = INTVAL (XEXP (dest_addr, 1));
 460       dest_addr = XEXP (dest_addr, 0);
 461     }
 462   else
 463     return false;
 464
 465   for (i = 1; i < count; i++)
 466     {
 467       rtx elt = XVECEXP (op, 0, i);
 468
 469       if (GET_CODE (elt) != SET
 470           || GET_CODE (SET_SRC (elt)) != REG
 471           || GET_MODE (SET_SRC (elt)) != elt_mode
 472           || REGNO (SET_SRC (elt)) != src_regno + i
 473           || GET_CODE (SET_DEST (elt)) != MEM
 474           || GET_MODE (SET_DEST (elt)) != elt_mode
 475           || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
 476           || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
 477           || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
 478           || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1))
 479              != off + i * GET_MODE_SIZE (elt_mode))
 480         return false;
 481     }
 482   return true;
 483 })