gcc/config/s390/predicates.md

   1 ;; Predicate definitions for S/390 and zSeries.
   2 ;; Copyright (C) 2005, 2007, 2008 Free Software Foundation, Inc.
   3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
   4 ;;                Ulrich Weigand (uweigand@de.ibm.com).
   5 ;;
   6 ;; This file is part of GCC.
   7 ;;
   8 ;; GCC is free software; you can redistribute it and/or modify
   9 ;; it under the terms of the GNU General Public License as published by
  10 ;; the Free Software Foundation; either version 3, or (at your option)
  11 ;; any later version.
  12 ;;
  13 ;; GCC is distributed in the hope that it will be useful,
  14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 ;; GNU General Public License for more details.
  17 ;;
  18 ;; You should have received a copy of the GNU General Public License
  19 ;; along with GCC; see the file COPYING3.  If not see
  20 ;; <http://www.gnu.org/licenses/>.
  21
  22 ;; OP is the current operation.
  23 ;; MODE is the current operation mode.
  24
  25 ;; operands --------------------------------------------------------------
  26
  27 ;; Return true if OP a (const_int 0) operand.
  28
  29 (define_predicate "const0_operand"
  30   (and (match_code "const_int, const_double")
  31        (match_test "op == CONST0_RTX (mode)")))
  32
  33 ;; Return true if OP is constant.
  34
  35 (define_special_predicate "consttable_operand"
  36   (and (match_code "symbol_ref, label_ref, const, const_int, const_double")
  37        (match_test "CONSTANT_P (op)")))
  38
  39 ;; Return true if OP is a valid S-type operand.
  40
  41 (define_predicate "s_operand"
  42   (and (match_code "subreg, mem")
  43        (match_operand 0 "general_operand"))
  44 {
  45   /* Just like memory_operand, allow (subreg (mem ...))
  46      after reload.  */
  47   if (reload_completed
  48       && GET_CODE (op) == SUBREG
  49       && GET_CODE (SUBREG_REG (op)) == MEM)
  50     op = SUBREG_REG (op);
  51
  52   if (GET_CODE (op) != MEM)
  53     return false;
  54   if (!s390_legitimate_address_without_index_p (op))
  55     return false;
  56
  57   return true;
  58 })
  59
  60 ;; Return true if OP is a valid operand for the BRAS instruction.
  61 ;; Allow SYMBOL_REFs and @PLT stubs.
  62
  63 (define_special_predicate "bras_sym_operand"
  64   (ior (and (match_code "symbol_ref")
  65             (match_test "!flag_pic || SYMBOL_REF_LOCAL_P (op)"))
  66        (and (match_code "const")
  67             (and (match_test "GET_CODE (XEXP (op, 0)) == UNSPEC")
  68                  (match_test "XINT (XEXP (op, 0), 1) == UNSPEC_PLT")))))
  69
  70 ;; Return true if OP is a PLUS that is not a legitimate
  71 ;; operand for the LA instruction.
  72
  73 (define_predicate "s390_plus_operand"
  74   (and (match_code "plus")
  75        (and (match_test "mode == Pmode")
  76             (match_test "!legitimate_la_operand_p (op)"))))
  77
  78 ;; Return true if OP is a valid operand as shift count or setmem.
  79
  80 (define_predicate "shift_count_or_setmem_operand"
  81   (match_code "reg, subreg, plus, const_int")
  82 {
  83   HOST_WIDE_INT offset;
  84   rtx base;
  85
  86   /* Extract base register and offset.  */
  87   if (!s390_decompose_shift_count (op, &base, &offset))
  88     return false;
  89
  90   /* Don't allow any non-base hard registers.  Doing so without
  91      confusing reload and/or regrename would be tricky, and doesn't
  92      buy us much anyway.  */
  93   if (base && REGNO (base) < FIRST_PSEUDO_REGISTER && !ADDR_REG_P (base))
  94     return false;
  95
  96   /* Unfortunately we have to reject constants that are invalid
  97      for an address, or else reload will get confused.  */
  98   if (!DISP_IN_RANGE (offset))
  99     return false;
 100
 101   return true;
 102 })
 103
 104 ;;  Return true if OP a valid operand for the LARL instruction.
 105
 106 (define_predicate "larl_operand"
 107   (match_code "label_ref, symbol_ref, const, const_int, const_double")
 108 {
 109   /* Allow labels and local symbols.  */
 110   if (GET_CODE (op) == LABEL_REF)
 111     return true;
 112   if (GET_CODE (op) == SYMBOL_REF)
 113     return (!SYMBOL_REF_ALIGN1_P (op)
 114             && SYMBOL_REF_TLS_MODEL (op) == 0
 115             && (!flag_pic || SYMBOL_REF_LOCAL_P (op)));
 116
 117   /* Everything else must have a CONST, so strip it.  */
 118   if (GET_CODE (op) != CONST)
 119     return false;
 120   op = XEXP (op, 0);
 121
 122   /* Allow adding *even* in-range constants.  */
 123   if (GET_CODE (op) == PLUS)
 124     {
 125       if (GET_CODE (XEXP (op, 1)) != CONST_INT
 126           || (INTVAL (XEXP (op, 1)) & 1) != 0)
 127         return false;
 128       if (INTVAL (XEXP (op, 1)) >= (HOST_WIDE_INT)1 << 31
 129           || INTVAL (XEXP (op, 1)) < -((HOST_WIDE_INT)1 << 31))
 130         return false;
 131       op = XEXP (op, 0);
 132     }
 133
 134   /* Labels and local symbols allowed here as well.  */
 135   if (GET_CODE (op) == LABEL_REF)
 136     return true;
 137   if (GET_CODE (op) == SYMBOL_REF)
 138     return ((SYMBOL_REF_FLAGS (op) & SYMBOL_FLAG_ALIGN1) == 0
 139             && SYMBOL_REF_TLS_MODEL (op) == 0
 140             && (!flag_pic || SYMBOL_REF_LOCAL_P (op)));
 141
 142   /* Now we must have a @GOTENT offset or @PLT stub
 143      or an @INDNTPOFF TLS offset.  */
 144   if (GET_CODE (op) == UNSPEC
 145       && XINT (op, 1) == UNSPEC_GOTENT)
 146     return true;
 147   if (GET_CODE (op) == UNSPEC
 148       && XINT (op, 1) == UNSPEC_PLT)
 149     return true;
 150   if (GET_CODE (op) == UNSPEC
 151       && XINT (op, 1) == UNSPEC_INDNTPOFF)
 152     return true;
 153
 154   return false;
 155 })
 156
 157 ;; operators --------------------------------------------------------------
 158
 159 ;; Return nonzero if OP is a valid comparison operator
 160 ;; for a branch condition.
 161
 162 (define_predicate "s390_comparison"
 163   (match_code "eq, ne, lt, gt, le, ge, ltu, gtu, leu, geu,
 164                uneq, unlt, ungt, unle, unge, ltgt,
 165                unordered, ordered")
 166 {
 167   if (GET_CODE (XEXP (op, 0)) != REG
 168       || REGNO (XEXP (op, 0)) != CC_REGNUM
 169       || XEXP (op, 1) != const0_rtx)
 170     return false;
 171
 172   return (s390_branch_condition_mask (op) >= 0);
 173 })
 174
 175 (define_predicate "s390_signed_integer_comparison"
 176   (match_code "eq, ne, lt, gt, le, ge")
 177 {
 178   return (s390_compare_and_branch_condition_mask (op) >= 0);
 179 })
 180
 181 (define_predicate "s390_unsigned_integer_comparison"
 182   (match_code "eq, ne, ltu, gtu, leu, geu")
 183 {
 184   return (s390_compare_and_branch_condition_mask (op) >= 0);
 185 })
 186
 187 ;; Return nonzero if OP is a valid comparison operator
 188 ;; for an ALC condition.
 189
 190 (define_predicate "s390_alc_comparison"
 191   (match_code "zero_extend, sign_extend, ltu, gtu, leu, geu")
 192 {
 193   while (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND)
 194     op = XEXP (op, 0);
 195
 196   if (!COMPARISON_P (op))
 197     return false;
 198
 199   if (GET_CODE (XEXP (op, 0)) != REG
 200       || REGNO (XEXP (op, 0)) != CC_REGNUM
 201       || XEXP (op, 1) != const0_rtx)
 202     return false;
 203
 204   switch (GET_MODE (XEXP (op, 0)))
 205     {
 206     case CCL1mode:
 207       return GET_CODE (op) == LTU;
 208
 209     case CCL2mode:
 210       return GET_CODE (op) == LEU;
 211
 212     case CCL3mode:
 213       return GET_CODE (op) == GEU;
 214
 215     case CCUmode:
 216       return GET_CODE (op) == GTU;
 217
 218     case CCURmode:
 219       return GET_CODE (op) == LTU;
 220
 221     case CCSmode:
 222       return GET_CODE (op) == UNGT;
 223
 224     case CCSRmode:
 225       return GET_CODE (op) == UNLT;
 226
 227     default:
 228       return false;
 229     }
 230 })
 231
 232 ;; Return nonzero if OP is a valid comparison operator
 233 ;; for an SLB condition.
 234
 235 (define_predicate "s390_slb_comparison"
 236   (match_code "zero_extend, sign_extend, ltu, gtu, leu, geu")
 237 {
 238   while (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND)
 239     op = XEXP (op, 0);
 240
 241   if (!COMPARISON_P (op))
 242     return false;
 243
 244   if (GET_CODE (XEXP (op, 0)) != REG
 245       || REGNO (XEXP (op, 0)) != CC_REGNUM
 246       || XEXP (op, 1) != const0_rtx)
 247     return false;
 248
 249   switch (GET_MODE (XEXP (op, 0)))
 250     {
 251     case CCL1mode:
 252       return GET_CODE (op) == GEU;
 253
 254     case CCL2mode:
 255       return GET_CODE (op) == GTU;
 256
 257     case CCL3mode:
 258       return GET_CODE (op) == LTU;
 259
 260     case CCUmode:
 261       return GET_CODE (op) == LEU;
 262
 263     case CCURmode:
 264       return GET_CODE (op) == GEU;
 265
 266     case CCSmode:
 267       return GET_CODE (op) == LE;
 268
 269     case CCSRmode:
 270       return GET_CODE (op) == GE;
 271
 272     default:
 273       return false;
 274     }
 275 })
 276
 277 ;; Return true if OP is a load multiple operation.  It is known to be a
 278 ;; PARALLEL and the first section will be tested.
 279
 280 (define_special_predicate "load_multiple_operation"
 281   (match_code "parallel")
 282 {
 283   enum machine_mode elt_mode;
 284   int count = XVECLEN (op, 0);
 285   unsigned int dest_regno;
 286   rtx src_addr;
 287   int i, off;
 288
 289   /* Perform a quick check so we don't blow up below.  */
 290   if (count <= 1
 291       || GET_CODE (XVECEXP (op, 0, 0)) != SET
 292       || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
 293       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
 294     return false;
 295
 296   dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
 297   src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
 298   elt_mode = GET_MODE (SET_DEST (XVECEXP (op, 0, 0)));
 299
 300   /* Check, is base, or base + displacement.  */
 301
 302   if (GET_CODE (src_addr) == REG)
 303     off = 0;
 304   else if (GET_CODE (src_addr) == PLUS
 305            && GET_CODE (XEXP (src_addr, 0)) == REG
 306            && GET_CODE (XEXP (src_addr, 1)) == CONST_INT)
 307     {
 308       off = INTVAL (XEXP (src_addr, 1));
 309       src_addr = XEXP (src_addr, 0);
 310     }
 311   else
 312     return false;
 313
 314   for (i = 1; i < count; i++)
 315     {
 316       rtx elt = XVECEXP (op, 0, i);
 317
 318       if (GET_CODE (elt) != SET
 319           || GET_CODE (SET_DEST (elt)) != REG
 320           || GET_MODE (SET_DEST (elt)) != elt_mode
 321           || REGNO (SET_DEST (elt)) != dest_regno + i
 322           || GET_CODE (SET_SRC (elt)) != MEM
 323           || GET_MODE (SET_SRC (elt)) != elt_mode
 324           || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
 325           || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
 326           || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
 327           || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1))
 328              != off + i * GET_MODE_SIZE (elt_mode))
 329         return false;
 330     }
 331
 332   return true;
 333 })
 334
 335 ;; Return true if OP is a store multiple operation.  It is known to be a
 336 ;; PARALLEL and the first section will be tested.
 337
 338 (define_special_predicate "store_multiple_operation"
 339   (match_code "parallel")
 340 {
 341   enum machine_mode elt_mode;
 342   int count = XVECLEN (op, 0);
 343   unsigned int src_regno;
 344   rtx dest_addr;
 345   int i, off;
 346
 347   /* Perform a quick check so we don't blow up below.  */
 348   if (count <= 1
 349       || GET_CODE (XVECEXP (op, 0, 0)) != SET
 350       || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
 351       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
 352     return false;
 353
 354   src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
 355   dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
 356   elt_mode = GET_MODE (SET_SRC (XVECEXP (op, 0, 0)));
 357
 358   /* Check, is base, or base + displacement.  */
 359
 360   if (GET_CODE (dest_addr) == REG)
 361     off = 0;
 362   else if (GET_CODE (dest_addr) == PLUS
 363            && GET_CODE (XEXP (dest_addr, 0)) == REG
 364            && GET_CODE (XEXP (dest_addr, 1)) == CONST_INT)
 365     {
 366       off = INTVAL (XEXP (dest_addr, 1));
 367       dest_addr = XEXP (dest_addr, 0);
 368     }
 369   else
 370     return false;
 371
 372   for (i = 1; i < count; i++)
 373     {
 374       rtx elt = XVECEXP (op, 0, i);
 375
 376       if (GET_CODE (elt) != SET
 377           || GET_CODE (SET_SRC (elt)) != REG
 378           || GET_MODE (SET_SRC (elt)) != elt_mode
 379           || REGNO (SET_SRC (elt)) != src_regno + i
 380           || GET_CODE (SET_DEST (elt)) != MEM
 381           || GET_MODE (SET_DEST (elt)) != elt_mode
 382           || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
 383           || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
 384           || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
 385           || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1))
 386              != off + i * GET_MODE_SIZE (elt_mode))
 387         return false;
 388     }
 389   return true;
 390 })