gcc/config/s390/predicates.md

   1 ;; Predicate definitions for S/390 and zSeries.
   2 ;; Copyright (C) 2005-2015 Free Software Foundation, Inc.
   3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
   4 ;;                Ulrich Weigand (uweigand@de.ibm.com).
   5 ;;
   6 ;; This file is part of GCC.
   7 ;;
   8 ;; GCC is free software; you can redistribute it and/or modify
   9 ;; it under the terms of the GNU General Public License as published by
  10 ;; the Free Software Foundation; either version 3, or (at your option)
  11 ;; any later version.
  12 ;;
  13 ;; GCC is distributed in the hope that it will be useful,
  14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 ;; GNU General Public License for more details.
  17 ;;
  18 ;; You should have received a copy of the GNU General Public License
  19 ;; along with GCC; see the file COPYING3.  If not see
  20 ;; <http://www.gnu.org/licenses/>.
  21
  22 ;; OP is the current operation.
  23 ;; MODE is the current operation mode.
  24
  25 ;; operands --------------------------------------------------------------
  26
  27 ;; Return true if OP a (const_int 0) operand.
  28
  29 (define_predicate "const0_operand"
  30   (and (match_code "const_int, const_double")
  31        (match_test "op == CONST0_RTX (mode)")))
  32
  33 ;; Return true if OP is constant.
  34
  35 (define_special_predicate "consttable_operand"
  36   (and (match_code "symbol_ref, label_ref, const, const_int, const_double")
  37        (match_test "CONSTANT_P (op)")))
  38
  39 ;; Return true if OP is a valid S-type operand.
  40
  41 (define_predicate "s_operand"
  42   (and (match_code "subreg, mem")
  43        (match_operand 0 "general_operand"))
  44 {
  45   /* Just like memory_operand, allow (subreg (mem ...))
  46      after reload.  */
  47   if (reload_completed
  48       && GET_CODE (op) == SUBREG
  49       && GET_CODE (SUBREG_REG (op)) == MEM)
  50     op = SUBREG_REG (op);
  51
  52   if (GET_CODE (op) != MEM)
  53     return false;
  54   if (!s390_legitimate_address_without_index_p (op))
  55     return false;
  56
  57   return true;
  58 })
  59
  60 ;; Return true if OP is a valid operand for the BRAS instruction.
  61 ;; Allow SYMBOL_REFs and @PLT stubs.
  62
  63 (define_special_predicate "bras_sym_operand"
  64   (ior (and (match_code "symbol_ref")
  65             (match_test "!flag_pic || SYMBOL_REF_LOCAL_P (op)"))
  66        (and (match_code "const")
  67             (and (match_test "GET_CODE (XEXP (op, 0)) == UNSPEC")
  68                  (match_test "XINT (XEXP (op, 0), 1) == UNSPEC_PLT")))))
  69
  70 ;; Return true if OP is a PLUS that is not a legitimate
  71 ;; operand for the LA instruction.
  72
  73 (define_predicate "s390_plus_operand"
  74   (and (match_code "plus")
  75        (and (match_test "mode == Pmode")
  76             (match_test "!legitimate_la_operand_p (op)"))))
  77
  78 ;; Return true if OP is a valid operand as scalar shift count or setmem.
  79
  80 (define_predicate "shift_count_or_setmem_operand"
  81   (match_code "reg, subreg, plus, const_int")
  82 {
  83   HOST_WIDE_INT offset;
  84   rtx base;
  85
  86   if (GET_MODE (op) != VOIDmode
  87       && GET_MODE_CLASS (GET_MODE (op)) != MODE_INT)
  88     return false;
  89
  90   /* Extract base register and offset.  */
  91   if (!s390_decompose_shift_count (op, &base, &offset))
  92     return false;
  93
  94   /* Don't allow any non-base hard registers.  Doing so without
  95      confusing reload and/or regrename would be tricky, and doesn't
  96      buy us much anyway.  */
  97   if (base && REGNO (base) < FIRST_PSEUDO_REGISTER && !ADDR_REG_P (base))
  98     return false;
  99
 100   /* Unfortunately we have to reject constants that are invalid
 101      for an address, or else reload will get confused.  */
 102   if (!DISP_IN_RANGE (offset))
 103     return false;
 104
 105   return true;
 106 })
 107
 108 (define_predicate "nonzero_shift_count_operand"
 109   (and (match_code "const_int")
 110        (match_test "IN_RANGE (INTVAL (op), 1, GET_MODE_BITSIZE (mode) - 1)")))
 111
 112 ;;  Return true if OP a valid operand for the LARL instruction.
 113
 114 (define_predicate "larl_operand"
 115   (match_code "label_ref, symbol_ref, const, const_int, const_double")
 116 {
 117   /* Allow labels and local symbols.  */
 118   if (GET_CODE (op) == LABEL_REF)
 119     return true;
 120   if (GET_CODE (op) == SYMBOL_REF)
 121     return (!SYMBOL_REF_ALIGN1_P (op)
 122             && SYMBOL_REF_TLS_MODEL (op) == 0
 123             && (!flag_pic || SYMBOL_REF_LOCAL_P (op)));
 124
 125   /* Everything else must have a CONST, so strip it.  */
 126   if (GET_CODE (op) != CONST)
 127     return false;
 128   op = XEXP (op, 0);
 129
 130   /* Allow adding *even* in-range constants.  */
 131   if (GET_CODE (op) == PLUS)
 132     {
 133       if (GET_CODE (XEXP (op, 1)) != CONST_INT
 134           || (INTVAL (XEXP (op, 1)) & 1) != 0)
 135         return false;
 136       if (INTVAL (XEXP (op, 1)) >= (HOST_WIDE_INT)1 << 31
 137           || INTVAL (XEXP (op, 1)) < -((HOST_WIDE_INT)1 << 31))
 138         return false;
 139       op = XEXP (op, 0);
 140     }
 141
 142   /* Labels and local symbols allowed here as well.  */
 143   if (GET_CODE (op) == LABEL_REF)
 144     return true;
 145   if (GET_CODE (op) == SYMBOL_REF)
 146     return ((SYMBOL_REF_FLAGS (op) & SYMBOL_FLAG_ALIGN1) == 0
 147             && SYMBOL_REF_TLS_MODEL (op) == 0
 148             && (!flag_pic || SYMBOL_REF_LOCAL_P (op)));
 149
 150   /* Now we must have a @GOTENT offset or @PLT stub
 151      or an @INDNTPOFF TLS offset.  */
 152   if (GET_CODE (op) == UNSPEC
 153       && XINT (op, 1) == UNSPEC_GOTENT)
 154     return true;
 155   if (GET_CODE (op) == UNSPEC
 156       && XINT (op, 1) == UNSPEC_PLT)
 157     return true;
 158   if (GET_CODE (op) == UNSPEC
 159       && XINT (op, 1) == UNSPEC_INDNTPOFF)
 160     return true;
 161
 162   return false;
 163 })
 164
 165 (define_predicate "contiguous_bitmask_operand"
 166   (match_code "const_int")
 167 {
 168   return s390_contiguous_bitmask_p (INTVAL (op), GET_MODE_BITSIZE (mode), NULL, NULL);
 169 })
 170
 171 ;; operators --------------------------------------------------------------
 172
 173 ;; Return nonzero if OP is a valid comparison operator
 174 ;; for a branch condition.
 175
 176 (define_predicate "s390_comparison"
 177   (match_code "eq, ne, lt, gt, le, ge, ltu, gtu, leu, geu,
 178                uneq, unlt, ungt, unle, unge, ltgt,
 179                unordered, ordered")
 180 {
 181   if (GET_CODE (XEXP (op, 0)) != REG
 182       || REGNO (XEXP (op, 0)) != CC_REGNUM
 183       || (XEXP (op, 1) != const0_rtx
 184           && !(CONST_INT_P (XEXP (op, 1))
 185                && GET_MODE (XEXP (op, 0)) == CCRAWmode
 186                && INTVAL (XEXP (op, 1)) >= 0
 187                && INTVAL (XEXP (op, 1)) <= 15)))
 188     return false;
 189
 190   return (s390_branch_condition_mask (op) >= 0);
 191 })
 192
 193 ;; Return true if op is the cc register.
 194 (define_predicate "cc_reg_operand"
 195   (and (match_code "reg")
 196        (match_test "REGNO (op) == CC_REGNUM")))
 197
 198 (define_predicate "s390_signed_integer_comparison"
 199   (match_code "eq, ne, lt, gt, le, ge")
 200 {
 201   return (s390_compare_and_branch_condition_mask (op) >= 0);
 202 })
 203
 204 (define_predicate "s390_unsigned_integer_comparison"
 205   (match_code "eq, ne, ltu, gtu, leu, geu")
 206 {
 207   return (s390_compare_and_branch_condition_mask (op) >= 0);
 208 })
 209
 210 ;; Return nonzero if OP is a valid comparison operator for the
 211 ;; cstore expanders -- respectively cstorecc4 and integer cstore.
 212 (define_predicate "s390_eqne_operator"
 213   (match_code "eq, ne"))
 214
 215 (define_predicate "s390_scond_operator"
 216   (match_code "ltu, gtu, leu, geu"))
 217
 218 (define_predicate "s390_brx_operator"
 219   (match_code "le, gt"))
 220
 221 ;; Return nonzero if OP is a valid comparison operator
 222 ;; for an ALC condition.
 223
 224 (define_predicate "s390_alc_comparison"
 225   (match_code "zero_extend, sign_extend, ltu, gtu, leu, geu")
 226 {
 227   while (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND)
 228     op = XEXP (op, 0);
 229
 230   if (!COMPARISON_P (op))
 231     return false;
 232
 233   if (GET_CODE (XEXP (op, 0)) != REG
 234       || REGNO (XEXP (op, 0)) != CC_REGNUM
 235       || (XEXP (op, 1) != const0_rtx
 236           && !(CONST_INT_P (XEXP (op, 1))
 237                && GET_MODE (XEXP (op, 0)) == CCRAWmode
 238                && INTVAL (XEXP (op, 1)) >= 0
 239                && INTVAL (XEXP (op, 1)) <= 15)))
 240     return false;
 241
 242   switch (GET_MODE (XEXP (op, 0)))
 243     {
 244     case CCL1mode:
 245       return GET_CODE (op) == LTU;
 246
 247     case CCL2mode:
 248       return GET_CODE (op) == LEU;
 249
 250     case CCL3mode:
 251       return GET_CODE (op) == GEU;
 252
 253     case CCUmode:
 254       return GET_CODE (op) == GTU;
 255
 256     case CCURmode:
 257       return GET_CODE (op) == LTU;
 258
 259     case CCSmode:
 260       return GET_CODE (op) == UNGT;
 261
 262     case CCSRmode:
 263       return GET_CODE (op) == UNLT;
 264
 265     default:
 266       return false;
 267     }
 268 })
 269
 270 ;; Return nonzero if OP is a valid comparison operator
 271 ;; for an SLB condition.
 272
 273 (define_predicate "s390_slb_comparison"
 274   (match_code "zero_extend, sign_extend, ltu, gtu, leu, geu")
 275 {
 276   while (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND)
 277     op = XEXP (op, 0);
 278
 279   if (!COMPARISON_P (op))
 280     return false;
 281
 282   if (GET_CODE (XEXP (op, 0)) != REG
 283       || REGNO (XEXP (op, 0)) != CC_REGNUM
 284       || XEXP (op, 1) != const0_rtx)
 285     return false;
 286
 287   switch (GET_MODE (XEXP (op, 0)))
 288     {
 289     case CCL1mode:
 290       return GET_CODE (op) == GEU;
 291
 292     case CCL2mode:
 293       return GET_CODE (op) == GTU;
 294
 295     case CCL3mode:
 296       return GET_CODE (op) == LTU;
 297
 298     case CCUmode:
 299       return GET_CODE (op) == LEU;
 300
 301     case CCURmode:
 302       return GET_CODE (op) == GEU;
 303
 304     case CCSmode:
 305       return GET_CODE (op) == LE;
 306
 307     case CCSRmode:
 308       return GET_CODE (op) == GE;
 309
 310     default:
 311       return false;
 312     }
 313 })
 314
 315 ;; Return true if OP is a load multiple operation.  It is known to be a
 316 ;; PARALLEL and the first section will be tested.
 317
 318 (define_special_predicate "load_multiple_operation"
 319   (match_code "parallel")
 320 {
 321   machine_mode elt_mode;
 322   int count = XVECLEN (op, 0);
 323   unsigned int dest_regno;
 324   rtx src_addr;
 325   int i, off;
 326
 327   /* Perform a quick check so we don't blow up below.  */
 328   if (count <= 1
 329       || GET_CODE (XVECEXP (op, 0, 0)) != SET
 330       || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
 331       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
 332     return false;
 333
 334   dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
 335   src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
 336   elt_mode = GET_MODE (SET_DEST (XVECEXP (op, 0, 0)));
 337
 338   /* Check, is base, or base + displacement.  */
 339
 340   if (GET_CODE (src_addr) == REG)
 341     off = 0;
 342   else if (GET_CODE (src_addr) == PLUS
 343            && GET_CODE (XEXP (src_addr, 0)) == REG
 344            && GET_CODE (XEXP (src_addr, 1)) == CONST_INT)
 345     {
 346       off = INTVAL (XEXP (src_addr, 1));
 347       src_addr = XEXP (src_addr, 0);
 348     }
 349   else
 350     return false;
 351
 352   for (i = 1; i < count; i++)
 353     {
 354       rtx elt = XVECEXP (op, 0, i);
 355
 356       if (GET_CODE (elt) != SET
 357           || GET_CODE (SET_DEST (elt)) != REG
 358           || GET_MODE (SET_DEST (elt)) != elt_mode
 359           || REGNO (SET_DEST (elt)) != dest_regno + i
 360           || GET_CODE (SET_SRC (elt)) != MEM
 361           || GET_MODE (SET_SRC (elt)) != elt_mode
 362           || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
 363           || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
 364           || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
 365           || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1))
 366              != off + i * GET_MODE_SIZE (elt_mode))
 367         return false;
 368     }
 369
 370   return true;
 371 })
 372
 373 ;; For an execute pattern the target instruction is embedded into the
 374 ;; RTX but will not get checked for validity by recog automatically.
 375 ;; The execute_operation predicate extracts the target RTX and invokes
 376 ;; recog.
 377 (define_special_predicate "execute_operation"
 378   (match_code "parallel")
 379 {
 380   rtx pattern = op;
 381   rtx_insn *insn;
 382   int icode;
 383
 384   /* This is redundant but since this predicate is evaluated
 385      first when recognizing the insn we can prevent the more
 386      expensive code below from being executed for many cases.  */
 387   if (GET_CODE (XVECEXP (pattern, 0, 0)) != UNSPEC
 388       || XINT (XVECEXP (pattern, 0, 0), 1) != UNSPEC_EXECUTE)
 389     return false;
 390
 391   /* Keep in sync with s390_execute_target.  */
 392   if (XVECLEN (pattern, 0) == 2)
 393     {
 394       pattern = copy_rtx (XVECEXP (pattern, 0, 1));
 395     }
 396   else
 397     {
 398       rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
 399       int i;
 400
 401       for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
 402         RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
 403
 404       pattern = gen_rtx_PARALLEL (VOIDmode, vec);
 405     }
 406
 407   /* Since we do not have the wrapping insn here we have to build one.  */
 408   insn = make_insn_raw (pattern);
 409   icode = recog_memoized (insn);
 410   if (icode < 0)
 411     return false;
 412
 413   extract_constrain_insn (insn);
 414
 415   return which_alternative >= 0;
 416 })
 417
 418 ;; Return true if OP is a store multiple operation.  It is known to be a
 419 ;; PARALLEL and the first section will be tested.
 420
 421 (define_special_predicate "store_multiple_operation"
 422   (match_code "parallel")
 423 {
 424   machine_mode elt_mode;
 425   int count = XVECLEN (op, 0);
 426   unsigned int src_regno;
 427   rtx dest_addr;
 428   int i, off;
 429
 430   /* Perform a quick check so we don't blow up below.  */
 431   if (count <= 1
 432       || GET_CODE (XVECEXP (op, 0, 0)) != SET
 433       || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
 434       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
 435     return false;
 436
 437   src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
 438   dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
 439   elt_mode = GET_MODE (SET_SRC (XVECEXP (op, 0, 0)));
 440
 441   /* Check, is base, or base + displacement.  */
 442
 443   if (GET_CODE (dest_addr) == REG)
 444     off = 0;
 445   else if (GET_CODE (dest_addr) == PLUS
 446            && GET_CODE (XEXP (dest_addr, 0)) == REG
 447            && GET_CODE (XEXP (dest_addr, 1)) == CONST_INT)
 448     {
 449       off = INTVAL (XEXP (dest_addr, 1));
 450       dest_addr = XEXP (dest_addr, 0);
 451     }
 452   else
 453     return false;
 454
 455   for (i = 1; i < count; i++)
 456     {
 457       rtx elt = XVECEXP (op, 0, i);
 458
 459       if (GET_CODE (elt) != SET
 460           || GET_CODE (SET_SRC (elt)) != REG
 461           || GET_MODE (SET_SRC (elt)) != elt_mode
 462           || REGNO (SET_SRC (elt)) != src_regno + i
 463           || GET_CODE (SET_DEST (elt)) != MEM
 464           || GET_MODE (SET_DEST (elt)) != elt_mode
 465           || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
 466           || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
 467           || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
 468           || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1))
 469              != off + i * GET_MODE_SIZE (elt_mode))
 470         return false;
 471     }
 472   return true;
 473 })