gcc/config/s390/predicates.md

   1 ;; Predicate definitions for S/390 and zSeries.
   2 ;; Copyright (C) 2005-2016 Free Software Foundation, Inc.
   3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
   4 ;;                Ulrich Weigand (uweigand@de.ibm.com).
   5 ;;
   6 ;; This file is part of GCC.
   7 ;;
   8 ;; GCC is free software; you can redistribute it and/or modify
   9 ;; it under the terms of the GNU General Public License as published by
  10 ;; the Free Software Foundation; either version 3, or (at your option)
  11 ;; any later version.
  12 ;;
  13 ;; GCC is distributed in the hope that it will be useful,
  14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 ;; GNU General Public License for more details.
  17 ;;
  18 ;; You should have received a copy of the GNU General Public License
  19 ;; along with GCC; see the file COPYING3.  If not see
  20 ;; <http://www.gnu.org/licenses/>.
  21
  22 ;; OP is the current operation.
  23 ;; MODE is the current operation mode.
  24
  25 ;; operands --------------------------------------------------------------
  26
  27 ;; Return true if OP a const 0 operand (int/float/vector).
  28 (define_predicate "const0_operand"
  29   (and (match_code "const_int,const_wide_int,const_double,const_vector")
  30        (match_test "op == CONST0_RTX (mode)")))
  31
  32 ;; Return true if OP an all ones operand (int/vector).
  33 (define_predicate "all_ones_operand"
  34   (and (match_code "const_int, const_wide_int, const_vector")
  35        (match_test "INTEGRAL_MODE_P (GET_MODE (op))")
  36        (match_test "op == CONSTM1_RTX (mode)")))
  37
  38 ;; Return true if OP is a 4 bit mask operand
  39 (define_predicate "const_mask_operand"
  40   (and (match_code "const_int")
  41        (match_test "UINTVAL (op) < 16")))
  42
  43 ;; Return true if OP is constant.
  44
  45 (define_special_predicate "consttable_operand"
  46   (and (match_code "symbol_ref, label_ref, const, const_int, const_wide_int, const_double, const_vector")
  47        (match_test "CONSTANT_P (op)")))
  48
  49 ;; Return true if OP is a valid S-type operand.
  50
  51 (define_predicate "s_operand"
  52   (and (match_code "subreg, mem")
  53        (match_operand 0 "general_operand"))
  54 {
  55   /* Just like memory_operand, allow (subreg (mem ...))
  56      after reload.  */
  57   if (reload_completed
  58       && GET_CODE (op) == SUBREG
  59       && GET_CODE (SUBREG_REG (op)) == MEM)
  60     op = SUBREG_REG (op);
  61
  62   if (GET_CODE (op) != MEM)
  63     return false;
  64   if (!s390_legitimate_address_without_index_p (op))
  65     return false;
  66
  67   return true;
  68 })
  69
  70 ;; Return true if OP is a valid operand for the BRAS instruction.
  71 ;; Allow SYMBOL_REFs and @PLT stubs.
  72
  73 (define_special_predicate "bras_sym_operand"
  74   (ior (and (match_code "symbol_ref")
  75             (match_test "!flag_pic || SYMBOL_REF_LOCAL_P (op)"))
  76        (and (match_code "const")
  77             (and (match_test "GET_CODE (XEXP (op, 0)) == UNSPEC")
  78                  (match_test "XINT (XEXP (op, 0), 1) == UNSPEC_PLT")))))
  79
  80 ;; Return true if OP is a PLUS that is not a legitimate
  81 ;; operand for the LA instruction.
  82
  83 (define_predicate "s390_plus_operand"
  84   (and (match_code "plus")
  85        (and (match_test "mode == Pmode")
  86             (match_test "!legitimate_la_operand_p (op)"))))
  87
  88 ;; Return true if OP is a valid operand as scalar shift count or setmem.
  89
  90 (define_predicate "setmem_operand"
  91   (match_code "reg, subreg, plus, const_int")
  92 {
  93   HOST_WIDE_INT offset;
  94   rtx base;
  95
  96   if (GET_MODE (op) != VOIDmode
  97       && GET_MODE_CLASS (GET_MODE (op)) != MODE_INT)
  98     return false;
  99
 100   /* Extract base register and offset.  */
 101   if (!s390_decompose_addrstyle_without_index (op, &base, &offset))
 102     return false;
 103
 104   /* Don't allow any non-base hard registers.  Doing so without
 105      confusing reload and/or regrename would be tricky, and doesn't
 106      buy us much anyway.  */
 107   if (base && REGNO (base) < FIRST_PSEUDO_REGISTER && !ADDR_REG_P (base))
 108     return false;
 109
 110   /* Unfortunately we have to reject constants that are invalid
 111      for an address, or else reload will get confused.  */
 112   if (!DISP_IN_RANGE (offset))
 113     return false;
 114
 115   return true;
 116 })
 117
 118 ; An integer operand with the lowest order 6 bits all ones.
 119 (define_predicate "const_int_6bitset_operand"
 120  (and (match_code "const_int")
 121       (match_test "(INTVAL (op) & 63) == 63")))
 122 (define_predicate "nonzero_shift_count_operand"
 123   (and (match_code "const_int")
 124        (match_test "IN_RANGE (INTVAL (op), 1, GET_MODE_BITSIZE (mode) - 1)")))
 125
 126 ;;  Return true if OP a valid operand for the LARL instruction.
 127
 128 (define_predicate "larl_operand"
 129   (match_code "label_ref, symbol_ref, const")
 130 {
 131   /* Allow labels and local symbols.  */
 132   if (GET_CODE (op) == LABEL_REF)
 133     return true;
 134   if (GET_CODE (op) == SYMBOL_REF)
 135     return (!SYMBOL_FLAG_NOTALIGN2_P (op)
 136             && SYMBOL_REF_TLS_MODEL (op) == 0
 137             && (!flag_pic || SYMBOL_REF_LOCAL_P (op)));
 138
 139   /* Everything else must have a CONST, so strip it.  */
 140   if (GET_CODE (op) != CONST)
 141     return false;
 142   op = XEXP (op, 0);
 143
 144   /* Allow adding *even* in-range constants.  */
 145   if (GET_CODE (op) == PLUS)
 146     {
 147       if (GET_CODE (XEXP (op, 1)) != CONST_INT
 148           || (INTVAL (XEXP (op, 1)) & 1) != 0)
 149         return false;
 150       if (INTVAL (XEXP (op, 1)) >= (HOST_WIDE_INT)1 << 31
 151           || INTVAL (XEXP (op, 1)) < -((HOST_WIDE_INT)1 << 31))
 152         return false;
 153       op = XEXP (op, 0);
 154     }
 155
 156   /* Labels and local symbols allowed here as well.  */
 157   if (GET_CODE (op) == LABEL_REF)
 158     return true;
 159   if (GET_CODE (op) == SYMBOL_REF)
 160     return (!SYMBOL_FLAG_NOTALIGN2_P (op)
 161             && SYMBOL_REF_TLS_MODEL (op) == 0
 162             && (!flag_pic || SYMBOL_REF_LOCAL_P (op)));
 163
 164   /* Now we must have a @GOTENT offset or @PLT stub
 165      or an @INDNTPOFF TLS offset.  */
 166   if (GET_CODE (op) == UNSPEC
 167       && XINT (op, 1) == UNSPEC_GOTENT)
 168     return true;
 169   if (GET_CODE (op) == UNSPEC
 170       && XINT (op, 1) == UNSPEC_PLT)
 171     return true;
 172   if (GET_CODE (op) == UNSPEC
 173       && XINT (op, 1) == UNSPEC_INDNTPOFF)
 174     return true;
 175
 176   return false;
 177 })
 178
 179 ; Predicate that always allows wraparound of the one-bit range.
 180 (define_predicate "contiguous_bitmask_operand"
 181   (match_code "const_int")
 182 {
 183   return s390_contiguous_bitmask_p (INTVAL (op), true,
 184                                     GET_MODE_BITSIZE (mode), NULL, NULL);
 185 })
 186
 187 ; Same without wraparound.
 188 (define_predicate "contiguous_bitmask_nowrap_operand"
 189   (match_code "const_int")
 190 {
 191   return s390_contiguous_bitmask_p
 192     (INTVAL (op), false, GET_MODE_BITSIZE (mode), NULL, NULL);
 193 })
 194
 195 ;; Return true if OP is ligitimate for any LOC instruction.
 196
 197 (define_predicate "loc_operand"
 198   (ior (match_operand 0 "nonimmediate_operand")
 199       (and (match_code "const_int")
 200            (match_test "INTVAL (op) <= 32767 && INTVAL (op) >= -32768"))))
 201
 202 ;; operators --------------------------------------------------------------
 203
 204 ;; Return nonzero if OP is a valid comparison operator
 205 ;; for a branch condition.
 206
 207 (define_predicate "s390_comparison"
 208   (match_code "eq, ne, lt, gt, le, ge, ltu, gtu, leu, geu,
 209                uneq, unlt, ungt, unle, unge, ltgt,
 210                unordered, ordered")
 211 {
 212   if (GET_CODE (XEXP (op, 0)) != REG
 213       || REGNO (XEXP (op, 0)) != CC_REGNUM
 214       || (XEXP (op, 1) != const0_rtx
 215           && !(CONST_INT_P (XEXP (op, 1))
 216                && GET_MODE (XEXP (op, 0)) == CCRAWmode
 217                && INTVAL (XEXP (op, 1)) >= 0
 218                && INTVAL (XEXP (op, 1)) <= 15)))
 219     return false;
 220
 221   return (s390_branch_condition_mask (op) >= 0);
 222 })
 223
 224 ;; Return true if op is the cc register.
 225 (define_predicate "cc_reg_operand"
 226   (and (match_code "reg")
 227        (match_test "REGNO (op) == CC_REGNUM")))
 228
 229 (define_predicate "s390_signed_integer_comparison"
 230   (match_code "eq, ne, lt, gt, le, ge")
 231 {
 232   return (s390_compare_and_branch_condition_mask (op) >= 0);
 233 })
 234
 235 (define_predicate "s390_unsigned_integer_comparison"
 236   (match_code "eq, ne, ltu, gtu, leu, geu")
 237 {
 238   return (s390_compare_and_branch_condition_mask (op) >= 0);
 239 })
 240
 241 ;; Return nonzero if OP is a valid comparison operator for the
 242 ;; cstore expanders -- respectively cstorecc4 and integer cstore.
 243 (define_predicate "s390_eqne_operator"
 244   (match_code "eq, ne"))
 245
 246 (define_predicate "s390_scond_operator"
 247   (match_code "ltu, gtu, leu, geu"))
 248
 249 (define_predicate "s390_brx_operator"
 250   (match_code "le, gt"))
 251
 252 ;; Return nonzero if OP is a valid comparison operator
 253 ;; for an ALC condition.
 254
 255 (define_predicate "s390_alc_comparison"
 256   (match_code "zero_extend, sign_extend, ltu, gtu, leu, geu")
 257 {
 258   while (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND)
 259     op = XEXP (op, 0);
 260
 261   if (!COMPARISON_P (op))
 262     return false;
 263
 264   if (GET_CODE (XEXP (op, 0)) != REG
 265       || REGNO (XEXP (op, 0)) != CC_REGNUM
 266       || (XEXP (op, 1) != const0_rtx
 267           && !(CONST_INT_P (XEXP (op, 1))
 268                && GET_MODE (XEXP (op, 0)) == CCRAWmode
 269                && INTVAL (XEXP (op, 1)) >= 0
 270                && INTVAL (XEXP (op, 1)) <= 15)))
 271     return false;
 272
 273   switch (GET_MODE (XEXP (op, 0)))
 274     {
 275     case CCL1mode:
 276       return GET_CODE (op) == LTU;
 277
 278     case CCL2mode:
 279       return GET_CODE (op) == LEU;
 280
 281     case CCL3mode:
 282       return GET_CODE (op) == GEU;
 283
 284     case CCUmode:
 285       return GET_CODE (op) == GTU;
 286
 287     case CCURmode:
 288       return GET_CODE (op) == LTU;
 289
 290     case CCSmode:
 291       return GET_CODE (op) == UNGT;
 292
 293     case CCSRmode:
 294       return GET_CODE (op) == UNLT;
 295
 296     default:
 297       return false;
 298     }
 299 })
 300
 301 ;; Return nonzero if OP is a valid comparison operator
 302 ;; for an SLB condition.
 303
 304 (define_predicate "s390_slb_comparison"
 305   (match_code "zero_extend, sign_extend, ltu, gtu, leu, geu")
 306 {
 307   while (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND)
 308     op = XEXP (op, 0);
 309
 310   if (!COMPARISON_P (op))
 311     return false;
 312
 313   if (GET_CODE (XEXP (op, 0)) != REG
 314       || REGNO (XEXP (op, 0)) != CC_REGNUM
 315       || XEXP (op, 1) != const0_rtx)
 316     return false;
 317
 318   switch (GET_MODE (XEXP (op, 0)))
 319     {
 320     case CCL1mode:
 321       return GET_CODE (op) == GEU;
 322
 323     case CCL2mode:
 324       return GET_CODE (op) == GTU;
 325
 326     case CCL3mode:
 327       return GET_CODE (op) == LTU;
 328
 329     case CCUmode:
 330       return GET_CODE (op) == LEU;
 331
 332     case CCURmode:
 333       return GET_CODE (op) == GEU;
 334
 335     case CCSmode:
 336       return GET_CODE (op) == LE;
 337
 338     case CCSRmode:
 339       return GET_CODE (op) == GE;
 340
 341     default:
 342       return false;
 343     }
 344 })
 345
 346 ;; Return true if OP is a load multiple operation.  It is known to be a
 347 ;; PARALLEL and the first section will be tested.
 348
 349 (define_special_predicate "load_multiple_operation"
 350   (match_code "parallel")
 351 {
 352   machine_mode elt_mode;
 353   int count = XVECLEN (op, 0);
 354   unsigned int dest_regno;
 355   rtx src_addr;
 356   int i, off;
 357
 358   /* Perform a quick check so we don't blow up below.  */
 359   if (count <= 1
 360       || GET_CODE (XVECEXP (op, 0, 0)) != SET
 361       || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
 362       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
 363     return false;
 364
 365   dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
 366   src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
 367   elt_mode = GET_MODE (SET_DEST (XVECEXP (op, 0, 0)));
 368
 369   /* Check, is base, or base + displacement.  */
 370
 371   if (GET_CODE (src_addr) == REG)
 372     off = 0;
 373   else if (GET_CODE (src_addr) == PLUS
 374            && GET_CODE (XEXP (src_addr, 0)) == REG
 375            && GET_CODE (XEXP (src_addr, 1)) == CONST_INT)
 376     {
 377       off = INTVAL (XEXP (src_addr, 1));
 378       src_addr = XEXP (src_addr, 0);
 379     }
 380   else
 381     return false;
 382
 383   for (i = 1; i < count; i++)
 384     {
 385       rtx elt = XVECEXP (op, 0, i);
 386
 387       if (GET_CODE (elt) != SET
 388           || GET_CODE (SET_DEST (elt)) != REG
 389           || GET_MODE (SET_DEST (elt)) != elt_mode
 390           || REGNO (SET_DEST (elt)) != dest_regno + i
 391           || GET_CODE (SET_SRC (elt)) != MEM
 392           || GET_MODE (SET_SRC (elt)) != elt_mode
 393           || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
 394           || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
 395           || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
 396           || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1))
 397              != off + i * GET_MODE_SIZE (elt_mode))
 398         return false;
 399     }
 400
 401   return true;
 402 })
 403
 404 ;; For an execute pattern the target instruction is embedded into the
 405 ;; RTX but will not get checked for validity by recog automatically.
 406 ;; The execute_operation predicate extracts the target RTX and invokes
 407 ;; recog.
 408 (define_special_predicate "execute_operation"
 409   (match_code "parallel")
 410 {
 411   rtx pattern = op;
 412   rtx_insn *insn;
 413   int icode;
 414
 415   /* This is redundant but since this predicate is evaluated
 416      first when recognizing the insn we can prevent the more
 417      expensive code below from being executed for many cases.  */
 418   if (GET_CODE (XVECEXP (pattern, 0, 0)) != UNSPEC
 419       || XINT (XVECEXP (pattern, 0, 0), 1) != UNSPEC_EXECUTE)
 420     return false;
 421
 422   /* Keep in sync with s390_execute_target.  */
 423   if (XVECLEN (pattern, 0) == 2)
 424     {
 425       pattern = copy_rtx (XVECEXP (pattern, 0, 1));
 426     }
 427   else
 428     {
 429       rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
 430       int i;
 431
 432       for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
 433         RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
 434
 435       pattern = gen_rtx_PARALLEL (VOIDmode, vec);
 436     }
 437
 438   /* Since we do not have the wrapping insn here we have to build one.  */
 439   insn = make_insn_raw (pattern);
 440   icode = recog_memoized (insn);
 441   if (icode < 0)
 442     return false;
 443
 444   extract_constrain_insn (insn);
 445
 446   return which_alternative >= 0;
 447 })
 448
 449 ;; Return true if OP is a store multiple operation.  It is known to be a
 450 ;; PARALLEL and the first section will be tested.
 451
 452 (define_special_predicate "store_multiple_operation"
 453   (match_code "parallel")
 454 {
 455   machine_mode elt_mode;
 456   int count = XVECLEN (op, 0);
 457   unsigned int src_regno;
 458   rtx dest_addr;
 459   int i, off;
 460
 461   /* Perform a quick check so we don't blow up below.  */
 462   if (count <= 1
 463       || GET_CODE (XVECEXP (op, 0, 0)) != SET
 464       || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
 465       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
 466     return false;
 467
 468   src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
 469   dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
 470   elt_mode = GET_MODE (SET_SRC (XVECEXP (op, 0, 0)));
 471
 472   /* Check, is base, or base + displacement.  */
 473
 474   if (GET_CODE (dest_addr) == REG)
 475     off = 0;
 476   else if (GET_CODE (dest_addr) == PLUS
 477            && GET_CODE (XEXP (dest_addr, 0)) == REG
 478            && GET_CODE (XEXP (dest_addr, 1)) == CONST_INT)
 479     {
 480       off = INTVAL (XEXP (dest_addr, 1));
 481       dest_addr = XEXP (dest_addr, 0);
 482     }
 483   else
 484     return false;
 485
 486   for (i = 1; i < count; i++)
 487     {
 488       rtx elt = XVECEXP (op, 0, i);
 489
 490       if (GET_CODE (elt) != SET
 491           || GET_CODE (SET_SRC (elt)) != REG
 492           || GET_MODE (SET_SRC (elt)) != elt_mode
 493           || REGNO (SET_SRC (elt)) != src_regno + i
 494           || GET_CODE (SET_DEST (elt)) != MEM
 495           || GET_MODE (SET_DEST (elt)) != elt_mode
 496           || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
 497           || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
 498           || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
 499           || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1))
 500              != off + i * GET_MODE_SIZE (elt_mode))
 501         return false;
 502     }
 503   return true;
 504 })