gcc/config/s390/predicates.md

   1 ;; Predicate definitions for S/390 and zSeries.
   2 ;; Copyright (C) 2005 Free Software Foundation, Inc.
   3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
   4 ;;                Ulrich Weigand (uweigand@de.ibm.com).
   5 ;;
   6 ;; This file is part of GCC.
   7 ;;
   8 ;; GCC is free software; you can redistribute it and/or modify
   9 ;; it under the terms of the GNU General Public License as published by
  10 ;; the Free Software Foundation; either version 2, or (at your option)
  11 ;; any later version.
  12 ;;
  13 ;; GCC is distributed in the hope that it will be useful,
  14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 ;; GNU General Public License for more details.
  17 ;;
  18 ;; You should have received a copy of the GNU General Public License
  19 ;; along with GCC; see the file COPYING.  If not, write to
  20 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
  21 ;; Boston, MA 02110-1301, USA.
  22
  23 ;; OP is the current operation.
  24 ;; MODE is the current operation mode.
  25
  26 ;; operands --------------------------------------------------------------
  27
  28 ;; Return true if OP a (const_int 0) operand.
  29
  30 (define_predicate "const0_operand"
  31   (and (match_code "const_int, const_double")
  32        (match_test "op == CONST0_RTX (mode)")))
  33
  34 ;; Return true if OP is constant.
  35
  36 (define_special_predicate "consttable_operand"
  37   (and (match_code "symbol_ref, label_ref, const, const_int, const_double")
  38        (match_test "CONSTANT_P (op)")))
  39
  40 ;; Return true if OP is a valid S-type operand.
  41
  42 (define_predicate "s_operand"
  43   (and (match_code "subreg, mem")
  44        (match_operand 0 "general_operand"))
  45 {
  46   /* Just like memory_operand, allow (subreg (mem ...))
  47      after reload.  */
  48   if (reload_completed
  49       && GET_CODE (op) == SUBREG
  50       && GET_CODE (SUBREG_REG (op)) == MEM)
  51     op = SUBREG_REG (op);
  52
  53   if (GET_CODE (op) != MEM)
  54     return false;
  55   if (!s390_legitimate_address_without_index_p (op))
  56     return false;
  57
  58   return true;
  59 })
  60
  61 ;; Return true if OP is a valid operand for the BRAS instruction.
  62 ;; Allow SYMBOL_REFs and @PLT stubs.
  63
  64 (define_special_predicate "bras_sym_operand"
  65   (ior (match_code "symbol_ref")
  66        (and (match_code "const")
  67             (and (match_test "GET_CODE (XEXP (op, 0)) == UNSPEC")
  68                  (match_test "XINT (XEXP (op, 0), 1) == UNSPEC_PLT")))))
  69
  70 ;; Return true if OP is a PLUS that is not a legitimate
  71 ;; operand for the LA instruction.
  72
  73 (define_predicate "s390_plus_operand"
  74   (and (match_code "plus")
  75        (and (match_test "mode == Pmode")
  76             (match_test "!legitimate_la_operand_p (op)"))))
  77
  78 ;; Return true if OP is a valid operand for setmem.
  79
  80 (define_predicate "setmem_operand"
  81   (match_code "reg, subreg, plus, const_int")
  82 {
  83   HOST_WIDE_INT offset;
  84   rtx base;
  85
  86   /* Extract base register and offset.  Use 8 significant bits.  */
  87   if (!s390_decompose_shift_count (op, &base, &offset, 8))
  88     return false;
  89
  90   /* Don't allow any non-base hard registers.  Doing so without
  91      confusing reload and/or regrename would be tricky, and doesn't
  92      buy us much anyway.  */
  93   if (base && REGNO (base) < FIRST_PSEUDO_REGISTER && !ADDR_REG_P (base))
  94     return false;
  95
  96   /* Unfortunately we have to reject constants that are invalid
  97      for an address, or else reload will get confused.  */
  98   if (!DISP_IN_RANGE (offset))
  99     return false;
 100
 101   return true;
 102 })
 103
 104 ;; Return true if OP is a valid shift count operand.
 105
 106 (define_predicate "shift_count_operand"
 107   (match_code "reg, subreg, plus, const_int, and")
 108 {
 109   HOST_WIDE_INT offset;
 110   rtx base;
 111
 112   /* Extract base register and offset.  Use 6 significant bits.  */
 113   if (!s390_decompose_shift_count (op, &base, &offset, 6))
 114     return false;
 115
 116   /* Don't allow any non-base hard registers.  Doing so without
 117      confusing reload and/or regrename would be tricky, and doesn't
 118      buy us much anyway.  */
 119   if (base && REGNO (base) < FIRST_PSEUDO_REGISTER && !ADDR_REG_P (base))
 120     return false;
 121
 122   /* Unfortunately we have to reject constants that are invalid
 123      for an address, or else reload will get confused.  */
 124   if (!DISP_IN_RANGE (offset))
 125     return false;
 126
 127   return true;
 128 })
 129
 130 ;;  Return true if OP a valid operand for the LARL instruction.
 131
 132 (define_predicate "larl_operand"
 133   (match_code "label_ref, symbol_ref, const, const_int, const_double")
 134 {
 135   /* Allow labels and local symbols.  */
 136   if (GET_CODE (op) == LABEL_REF)
 137     return true;
 138   if (GET_CODE (op) == SYMBOL_REF)
 139     return ((SYMBOL_REF_FLAGS (op) & SYMBOL_FLAG_ALIGN1) == 0
 140             && SYMBOL_REF_TLS_MODEL (op) == 0
 141             && (!flag_pic || SYMBOL_REF_LOCAL_P (op)));
 142
 143   /* Everything else must have a CONST, so strip it.  */
 144   if (GET_CODE (op) != CONST)
 145     return false;
 146   op = XEXP (op, 0);
 147
 148   /* Allow adding *even* in-range constants.  */
 149   if (GET_CODE (op) == PLUS)
 150     {
 151       if (GET_CODE (XEXP (op, 1)) != CONST_INT
 152           || (INTVAL (XEXP (op, 1)) & 1) != 0)
 153         return false;
 154       if (INTVAL (XEXP (op, 1)) >= (HOST_WIDE_INT)1 << 32
 155           || INTVAL (XEXP (op, 1)) < -((HOST_WIDE_INT)1 << 32))
 156         return false;
 157       op = XEXP (op, 0);
 158     }
 159
 160   /* Labels and local symbols allowed here as well.  */
 161   if (GET_CODE (op) == LABEL_REF)
 162     return true;
 163   if (GET_CODE (op) == SYMBOL_REF)
 164     return ((SYMBOL_REF_FLAGS (op) & SYMBOL_FLAG_ALIGN1) == 0
 165             && SYMBOL_REF_TLS_MODEL (op) == 0
 166             && (!flag_pic || SYMBOL_REF_LOCAL_P (op)));
 167
 168   /* Now we must have a @GOTENT offset or @PLT stub
 169      or an @INDNTPOFF TLS offset.  */
 170   if (GET_CODE (op) == UNSPEC
 171       && XINT (op, 1) == UNSPEC_GOTENT)
 172     return true;
 173   if (GET_CODE (op) == UNSPEC
 174       && XINT (op, 1) == UNSPEC_PLT)
 175     return true;
 176   if (GET_CODE (op) == UNSPEC
 177       && XINT (op, 1) == UNSPEC_INDNTPOFF)
 178     return true;
 179
 180   return false;
 181 })
 182
 183 ;; operators --------------------------------------------------------------
 184
 185 ;; Return nonzero if OP is a valid comparison operator
 186 ;; for a branch condition.
 187
 188 (define_predicate "s390_comparison"
 189   (match_code "eq, ne, lt, gt, le, ge, ltu, gtu, leu, geu,
 190                uneq, unlt, ungt, unle, unge, ltgt,
 191                unordered, ordered")
 192 {
 193   if (GET_CODE (XEXP (op, 0)) != REG
 194       || REGNO (XEXP (op, 0)) != CC_REGNUM
 195       || XEXP (op, 1) != const0_rtx)
 196     return false;
 197
 198   return (s390_branch_condition_mask (op) >= 0);
 199 })
 200
 201 ;; Return nonzero if OP is a valid comparison operator
 202 ;; for an ALC condition.
 203
 204 (define_predicate "s390_alc_comparison"
 205   (match_code "zero_extend, sign_extend, ltu, gtu, leu, geu")
 206 {
 207   while (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND)
 208     op = XEXP (op, 0);
 209
 210   if (!COMPARISON_P (op))
 211     return false;
 212
 213   if (GET_CODE (XEXP (op, 0)) != REG
 214       || REGNO (XEXP (op, 0)) != CC_REGNUM
 215       || XEXP (op, 1) != const0_rtx)
 216     return false;
 217
 218   switch (GET_MODE (XEXP (op, 0)))
 219     {
 220     case CCL1mode:
 221       return GET_CODE (op) == LTU;
 222
 223     case CCL2mode:
 224       return GET_CODE (op) == LEU;
 225
 226     case CCL3mode:
 227       return GET_CODE (op) == GEU;
 228
 229     case CCUmode:
 230       return GET_CODE (op) == GTU;
 231
 232     case CCURmode:
 233       return GET_CODE (op) == LTU;
 234
 235     case CCSmode:
 236       return GET_CODE (op) == UNGT;
 237
 238     case CCSRmode:
 239       return GET_CODE (op) == UNLT;
 240
 241     default:
 242       return false;
 243     }
 244 })
 245
 246 ;; Return nonzero if OP is a valid comparison operator
 247 ;; for an SLB condition.
 248
 249 (define_predicate "s390_slb_comparison"
 250   (match_code "zero_extend, sign_extend, ltu, gtu, leu, geu")
 251 {
 252   while (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND)
 253     op = XEXP (op, 0);
 254
 255   if (!COMPARISON_P (op))
 256     return false;
 257
 258   if (GET_CODE (XEXP (op, 0)) != REG
 259       || REGNO (XEXP (op, 0)) != CC_REGNUM
 260       || XEXP (op, 1) != const0_rtx)
 261     return false;
 262
 263   switch (GET_MODE (XEXP (op, 0)))
 264     {
 265     case CCL1mode:
 266       return GET_CODE (op) == GEU;
 267
 268     case CCL2mode:
 269       return GET_CODE (op) == GTU;
 270
 271     case CCL3mode:
 272       return GET_CODE (op) == LTU;
 273
 274     case CCUmode:
 275       return GET_CODE (op) == LEU;
 276
 277     case CCURmode:
 278       return GET_CODE (op) == GEU;
 279
 280     case CCSmode:
 281       return GET_CODE (op) == LE;
 282
 283     case CCSRmode:
 284       return GET_CODE (op) == GE;
 285
 286     default:
 287       return false;
 288     }
 289 })
 290
 291 ;; Return true if OP is a load multiple operation.  It is known to be a
 292 ;; PARALLEL and the first section will be tested.
 293
 294 (define_special_predicate "load_multiple_operation"
 295   (match_code "parallel")
 296 {
 297   enum machine_mode elt_mode;
 298   int count = XVECLEN (op, 0);
 299   unsigned int dest_regno;
 300   rtx src_addr;
 301   int i, off;
 302
 303   /* Perform a quick check so we don't blow up below.  */
 304   if (count <= 1
 305       || GET_CODE (XVECEXP (op, 0, 0)) != SET
 306       || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
 307       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
 308     return false;
 309
 310   dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
 311   src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
 312   elt_mode = GET_MODE (SET_DEST (XVECEXP (op, 0, 0)));
 313
 314   /* Check, is base, or base + displacement.  */
 315
 316   if (GET_CODE (src_addr) == REG)
 317     off = 0;
 318   else if (GET_CODE (src_addr) == PLUS
 319            && GET_CODE (XEXP (src_addr, 0)) == REG
 320            && GET_CODE (XEXP (src_addr, 1)) == CONST_INT)
 321     {
 322       off = INTVAL (XEXP (src_addr, 1));
 323       src_addr = XEXP (src_addr, 0);
 324     }
 325   else
 326     return false;
 327
 328   for (i = 1; i < count; i++)
 329     {
 330       rtx elt = XVECEXP (op, 0, i);
 331
 332       if (GET_CODE (elt) != SET
 333           || GET_CODE (SET_DEST (elt)) != REG
 334           || GET_MODE (SET_DEST (elt)) != elt_mode
 335           || REGNO (SET_DEST (elt)) != dest_regno + i
 336           || GET_CODE (SET_SRC (elt)) != MEM
 337           || GET_MODE (SET_SRC (elt)) != elt_mode
 338           || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
 339           || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
 340           || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
 341           || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1))
 342              != off + i * GET_MODE_SIZE (elt_mode))
 343         return false;
 344     }
 345
 346   return true;
 347 })
 348
 349 ;; Return true if OP is a store multiple operation.  It is known to be a
 350 ;; PARALLEL and the first section will be tested.
 351
 352 (define_special_predicate "store_multiple_operation"
 353   (match_code "parallel")
 354 {
 355   enum machine_mode elt_mode;
 356   int count = XVECLEN (op, 0);
 357   unsigned int src_regno;
 358   rtx dest_addr;
 359   int i, off;
 360
 361   /* Perform a quick check so we don't blow up below.  */
 362   if (count <= 1
 363       || GET_CODE (XVECEXP (op, 0, 0)) != SET
 364       || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
 365       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
 366     return false;
 367
 368   src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
 369   dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
 370   elt_mode = GET_MODE (SET_SRC (XVECEXP (op, 0, 0)));
 371
 372   /* Check, is base, or base + displacement.  */
 373
 374   if (GET_CODE (dest_addr) == REG)
 375     off = 0;
 376   else if (GET_CODE (dest_addr) == PLUS
 377            && GET_CODE (XEXP (dest_addr, 0)) == REG
 378            && GET_CODE (XEXP (dest_addr, 1)) == CONST_INT)
 379     {
 380       off = INTVAL (XEXP (dest_addr, 1));
 381       dest_addr = XEXP (dest_addr, 0);
 382     }
 383   else
 384     return false;
 385
 386   for (i = 1; i < count; i++)
 387     {
 388       rtx elt = XVECEXP (op, 0, i);
 389
 390       if (GET_CODE (elt) != SET
 391           || GET_CODE (SET_SRC (elt)) != REG
 392           || GET_MODE (SET_SRC (elt)) != elt_mode
 393           || REGNO (SET_SRC (elt)) != src_regno + i
 394           || GET_CODE (SET_DEST (elt)) != MEM
 395           || GET_MODE (SET_DEST (elt)) != elt_mode
 396           || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
 397           || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
 398           || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
 399           || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1))
 400              != off + i * GET_MODE_SIZE (elt_mode))
 401         return false;
 402     }
 403   return true;
 404 })