gcc/config/s390/predicates.md

   1 ;; Predicate definitions for S/390 and zSeries.
   2 ;; Copyright (C) 2005 Free Software Foundation, Inc.
   3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
   4 ;;                Ulrich Weigand (uweigand@de.ibm.com).
   5 ;;
   6 ;; This file is part of GCC.
   7 ;;
   8 ;; GCC is free software; you can redistribute it and/or modify
   9 ;; it under the terms of the GNU General Public License as published by
  10 ;; the Free Software Foundation; either version 2, or (at your option)
  11 ;; any later version.
  12 ;;
  13 ;; GCC is distributed in the hope that it will be useful,
  14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 ;; GNU General Public License for more details.
  17 ;;
  18 ;; You should have received a copy of the GNU General Public License
  19 ;; along with GCC; see the file COPYING.  If not, write to
  20 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
  21 ;; Boston, MA 02110-1301, USA.
  22
  23 ;; OP is the current operation.
  24 ;; MODE is the current operation mode.
  25
  26 ;; operands --------------------------------------------------------------
  27
  28 ;; Return true if OP a (const_int 0) operand.
  29
  30 (define_predicate "const0_operand"
  31   (and (match_code "const_int, const_double")
  32        (match_test "op == CONST0_RTX (mode)")))
  33
  34 ;; Return true if OP is constant.
  35
  36 (define_special_predicate "consttable_operand"
  37   (and (match_code "symbol_ref, label_ref, const, const_int, const_double")
  38        (match_test "CONSTANT_P (op)")))
  39
  40 ;; Return true if OP is a valid S-type operand.
  41
  42 (define_predicate "s_operand"
  43   (and (match_code "subreg, mem")
  44        (match_operand 0 "general_operand"))
  45 {
  46   /* Just like memory_operand, allow (subreg (mem ...))
  47      after reload.  */
  48   if (reload_completed
  49       && GET_CODE (op) == SUBREG
  50       && GET_CODE (SUBREG_REG (op)) == MEM)
  51     op = SUBREG_REG (op);
  52
  53   if (GET_CODE (op) != MEM)
  54     return false;
  55   if (!s390_legitimate_address_without_index_p (op))
  56     return false;
  57
  58   return true;
  59 })
  60
  61 ;; Return true if OP is a valid operand for the BRAS instruction.
  62 ;; Allow SYMBOL_REFs and @PLT stubs.
  63
  64 (define_special_predicate "bras_sym_operand"
  65   (ior (match_code "symbol_ref")
  66        (and (match_code "const")
  67             (and (match_test "GET_CODE (XEXP (op, 0)) == UNSPEC")
  68                  (match_test "XINT (XEXP (op, 0), 1) == UNSPEC_PLT")))))
  69
  70 ;; Return true if OP is a PLUS that is not a legitimate
  71 ;; operand for the LA instruction.
  72
  73 (define_predicate "s390_plus_operand"
  74   (and (match_code "plus")
  75        (and (match_test "mode == Pmode")
  76             (match_test "!legitimate_la_operand_p (op)"))))
  77
  78 ;; Return true if OP is a valid operand for setmem.
  79
  80 (define_predicate "setmem_operand"
  81   (match_code "reg, subreg, plus, const_int")
  82 {
  83   HOST_WIDE_INT offset = 0;
  84
  85   /* The padding byte operand of the mvcle instruction is always truncated
  86      to the 8 least significant bits.  */
  87   if (GET_CODE (op) == AND && GET_CODE (XEXP (op, 1)) == CONST_INT
  88       && (INTVAL (XEXP (op, 1)) & 255) == 255)
  89     op = XEXP (op, 0);
  90
  91   /* We can have an integer constant, an address register,
  92      or a sum of the two.  Note that reload already checks
  93      that any register present is an address register, so
  94      we just check for any register here.  */
  95   if (GET_CODE (op) == CONST_INT)
  96     {
  97       offset = INTVAL (op);
  98       op = NULL_RTX;
  99     }
 100   if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
 101     {
 102       offset = INTVAL (XEXP (op, 1));
 103       op = XEXP (op, 0);
 104     }
 105   while (op && GET_CODE (op) == SUBREG)
 106     op = SUBREG_REG (op);
 107   if (op && GET_CODE (op) != REG)
 108     return false;
 109
 110   if (op && REGNO (op) < FIRST_PSEUDO_REGISTER
 111       && !GENERAL_REGNO_P (REGNO (op)))
 112     return false;
 113
 114   /* Unfortunately we have to reject constants that are invalid
 115      for an address, or else reload will get confused.  */
 116   if (!DISP_IN_RANGE (offset))
 117     return false;
 118
 119   return true;
 120 })
 121
 122 ;; Return true if OP is a valid shift count operand.
 123
 124 (define_predicate "shift_count_operand"
 125   (match_code "reg, subreg, plus, const_int, and")
 126 {
 127   HOST_WIDE_INT offset = 0;
 128
 129   /* Shift count operands are always truncated to the 6 least significant bits.
 130      So we can accept pointless ANDs here.  */
 131   if (GET_CODE (op) == AND && GET_CODE (XEXP (op, 1)) == CONST_INT
 132       && (INTVAL (XEXP (op, 1)) & 63) == 63)
 133     op = XEXP (op, 0);
 134
 135   /* We can have an integer constant, an address register,
 136      or a sum of the two.  Note that reload already checks
 137      that any register present is an address register, so
 138      we just check for any register here.  */
 139   if (GET_CODE (op) == CONST_INT)
 140     {
 141       offset = INTVAL (op);
 142       op = NULL_RTX;
 143     }
 144   if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
 145     {
 146       offset = INTVAL (XEXP (op, 1));
 147       op = XEXP (op, 0);
 148     }
 149   while (op && GET_CODE (op) == SUBREG)
 150     op = SUBREG_REG (op);
 151   if (op && GET_CODE (op) != REG)
 152     return false;
 153
 154   if (op && REGNO (op) < FIRST_PSEUDO_REGISTER
 155       && !GENERAL_REGNO_P (REGNO (op)))
 156     return false;
 157
 158   /* Unfortunately we have to reject constants that are invalid
 159      for an address, or else reload will get confused.  */
 160   if (!DISP_IN_RANGE (offset))
 161     return false;
 162
 163   return true;
 164 })
 165
 166 ;;  Return true if OP a valid operand for the LARL instruction.
 167
 168 (define_predicate "larl_operand"
 169   (match_code "label_ref, symbol_ref, const, const_int, const_double")
 170 {
 171   /* Allow labels and local symbols.  */
 172   if (GET_CODE (op) == LABEL_REF)
 173     return true;
 174   if (GET_CODE (op) == SYMBOL_REF)
 175     return ((SYMBOL_REF_FLAGS (op) & SYMBOL_FLAG_ALIGN1) == 0
 176             && SYMBOL_REF_TLS_MODEL (op) == 0
 177             && (!flag_pic || SYMBOL_REF_LOCAL_P (op)));
 178
 179   /* Everything else must have a CONST, so strip it.  */
 180   if (GET_CODE (op) != CONST)
 181     return false;
 182   op = XEXP (op, 0);
 183
 184   /* Allow adding *even* in-range constants.  */
 185   if (GET_CODE (op) == PLUS)
 186     {
 187       if (GET_CODE (XEXP (op, 1)) != CONST_INT
 188           || (INTVAL (XEXP (op, 1)) & 1) != 0)
 189         return false;
 190       if (INTVAL (XEXP (op, 1)) >= (HOST_WIDE_INT)1 << 32
 191           || INTVAL (XEXP (op, 1)) < -((HOST_WIDE_INT)1 << 32))
 192         return false;
 193       op = XEXP (op, 0);
 194     }
 195
 196   /* Labels and local symbols allowed here as well.  */
 197   if (GET_CODE (op) == LABEL_REF)
 198     return true;
 199   if (GET_CODE (op) == SYMBOL_REF)
 200     return ((SYMBOL_REF_FLAGS (op) & SYMBOL_FLAG_ALIGN1) == 0
 201             && SYMBOL_REF_TLS_MODEL (op) == 0
 202             && (!flag_pic || SYMBOL_REF_LOCAL_P (op)));
 203
 204   /* Now we must have a @GOTENT offset or @PLT stub
 205      or an @INDNTPOFF TLS offset.  */
 206   if (GET_CODE (op) == UNSPEC
 207       && XINT (op, 1) == UNSPEC_GOTENT)
 208     return true;
 209   if (GET_CODE (op) == UNSPEC
 210       && XINT (op, 1) == UNSPEC_PLT)
 211     return true;
 212   if (GET_CODE (op) == UNSPEC
 213       && XINT (op, 1) == UNSPEC_INDNTPOFF)
 214     return true;
 215
 216   return false;
 217 })
 218
 219 ;; operators --------------------------------------------------------------
 220
 221 ;; Return nonzero if OP is a valid comparison operator
 222 ;; for a branch condition.
 223
 224 (define_predicate "s390_comparison"
 225   (match_code "eq, ne, lt, gt, le, ge, ltu, gtu, leu, geu,
 226                uneq, unlt, ungt, unle, unge, ltgt,
 227                unordered, ordered")
 228 {
 229   if (GET_CODE (XEXP (op, 0)) != REG
 230       || REGNO (XEXP (op, 0)) != CC_REGNUM
 231       || XEXP (op, 1) != const0_rtx)
 232     return false;
 233
 234   return (s390_branch_condition_mask (op) >= 0);
 235 })
 236
 237 ;; Return nonzero if OP is a valid comparison operator
 238 ;; for an ALC condition.
 239
 240 (define_predicate "s390_alc_comparison"
 241   (match_code "zero_extend, sign_extend, ltu, gtu, leu, geu")
 242 {
 243   while (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND)
 244     op = XEXP (op, 0);
 245
 246   if (!COMPARISON_P (op))
 247     return false;
 248
 249   if (GET_CODE (XEXP (op, 0)) != REG
 250       || REGNO (XEXP (op, 0)) != CC_REGNUM
 251       || XEXP (op, 1) != const0_rtx)
 252     return false;
 253
 254   switch (GET_MODE (XEXP (op, 0)))
 255     {
 256     case CCL1mode:
 257       return GET_CODE (op) == LTU;
 258
 259     case CCL2mode:
 260       return GET_CODE (op) == LEU;
 261
 262     case CCL3mode:
 263       return GET_CODE (op) == GEU;
 264
 265     case CCUmode:
 266       return GET_CODE (op) == GTU;
 267
 268     case CCURmode:
 269       return GET_CODE (op) == LTU;
 270
 271     case CCSmode:
 272       return GET_CODE (op) == UNGT;
 273
 274     case CCSRmode:
 275       return GET_CODE (op) == UNLT;
 276
 277     default:
 278       return false;
 279     }
 280 })
 281
 282 ;; Return nonzero if OP is a valid comparison operator
 283 ;; for an SLB condition.
 284
 285 (define_predicate "s390_slb_comparison"
 286   (match_code "zero_extend, sign_extend, ltu, gtu, leu, geu")
 287 {
 288   while (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND)
 289     op = XEXP (op, 0);
 290
 291   if (!COMPARISON_P (op))
 292     return false;
 293
 294   if (GET_CODE (XEXP (op, 0)) != REG
 295       || REGNO (XEXP (op, 0)) != CC_REGNUM
 296       || XEXP (op, 1) != const0_rtx)
 297     return false;
 298
 299   switch (GET_MODE (XEXP (op, 0)))
 300     {
 301     case CCL1mode:
 302       return GET_CODE (op) == GEU;
 303
 304     case CCL2mode:
 305       return GET_CODE (op) == GTU;
 306
 307     case CCL3mode:
 308       return GET_CODE (op) == LTU;
 309
 310     case CCUmode:
 311       return GET_CODE (op) == LEU;
 312
 313     case CCURmode:
 314       return GET_CODE (op) == GEU;
 315
 316     case CCSmode:
 317       return GET_CODE (op) == LE;
 318
 319     case CCSRmode:
 320       return GET_CODE (op) == GE;
 321
 322     default:
 323       return false;
 324     }
 325 })
 326
 327 ;; Return true if OP is a load multiple operation.  It is known to be a
 328 ;; PARALLEL and the first section will be tested.
 329
 330 (define_special_predicate "load_multiple_operation"
 331   (match_code "parallel")
 332 {
 333   enum machine_mode elt_mode;
 334   int count = XVECLEN (op, 0);
 335   unsigned int dest_regno;
 336   rtx src_addr;
 337   int i, off;
 338
 339   /* Perform a quick check so we don't blow up below.  */
 340   if (count <= 1
 341       || GET_CODE (XVECEXP (op, 0, 0)) != SET
 342       || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
 343       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
 344     return false;
 345
 346   dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
 347   src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
 348   elt_mode = GET_MODE (SET_DEST (XVECEXP (op, 0, 0)));
 349
 350   /* Check, is base, or base + displacement.  */
 351
 352   if (GET_CODE (src_addr) == REG)
 353     off = 0;
 354   else if (GET_CODE (src_addr) == PLUS
 355            && GET_CODE (XEXP (src_addr, 0)) == REG
 356            && GET_CODE (XEXP (src_addr, 1)) == CONST_INT)
 357     {
 358       off = INTVAL (XEXP (src_addr, 1));
 359       src_addr = XEXP (src_addr, 0);
 360     }
 361   else
 362     return false;
 363
 364   for (i = 1; i < count; i++)
 365     {
 366       rtx elt = XVECEXP (op, 0, i);
 367
 368       if (GET_CODE (elt) != SET
 369           || GET_CODE (SET_DEST (elt)) != REG
 370           || GET_MODE (SET_DEST (elt)) != elt_mode
 371           || REGNO (SET_DEST (elt)) != dest_regno + i
 372           || GET_CODE (SET_SRC (elt)) != MEM
 373           || GET_MODE (SET_SRC (elt)) != elt_mode
 374           || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
 375           || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
 376           || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
 377           || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1))
 378              != off + i * GET_MODE_SIZE (elt_mode))
 379         return false;
 380     }
 381
 382   return true;
 383 })
 384
 385 ;; Return true if OP is a store multiple operation.  It is known to be a
 386 ;; PARALLEL and the first section will be tested.
 387
 388 (define_special_predicate "store_multiple_operation"
 389   (match_code "parallel")
 390 {
 391   enum machine_mode elt_mode;
 392   int count = XVECLEN (op, 0);
 393   unsigned int src_regno;
 394   rtx dest_addr;
 395   int i, off;
 396
 397   /* Perform a quick check so we don't blow up below.  */
 398   if (count <= 1
 399       || GET_CODE (XVECEXP (op, 0, 0)) != SET
 400       || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
 401       || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
 402     return false;
 403
 404   src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
 405   dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
 406   elt_mode = GET_MODE (SET_SRC (XVECEXP (op, 0, 0)));
 407
 408   /* Check, is base, or base + displacement.  */
 409
 410   if (GET_CODE (dest_addr) == REG)
 411     off = 0;
 412   else if (GET_CODE (dest_addr) == PLUS
 413            && GET_CODE (XEXP (dest_addr, 0)) == REG
 414            && GET_CODE (XEXP (dest_addr, 1)) == CONST_INT)
 415     {
 416       off = INTVAL (XEXP (dest_addr, 1));
 417       dest_addr = XEXP (dest_addr, 0);
 418     }
 419   else
 420     return false;
 421
 422   for (i = 1; i < count; i++)
 423     {
 424       rtx elt = XVECEXP (op, 0, i);
 425
 426       if (GET_CODE (elt) != SET
 427           || GET_CODE (SET_SRC (elt)) != REG
 428           || GET_MODE (SET_SRC (elt)) != elt_mode
 429           || REGNO (SET_SRC (elt)) != src_regno + i
 430           || GET_CODE (SET_DEST (elt)) != MEM
 431           || GET_MODE (SET_DEST (elt)) != elt_mode
 432           || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
 433           || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
 434           || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
 435           || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1))
 436              != off + i * GET_MODE_SIZE (elt_mode))
 437         return false;
 438     }
 439   return true;
 440 })