gcc/config/s390/s390-modes.def

   1 /* Definitions of target machine for GNU compiler, for IBM S/390
   2    Copyright (C) 2002-2015 Free Software Foundation, Inc.
   3    Contributed by Hartmut Penner (hpenner@de.ibm.com) and
   4                   Ulrich Weigand (uweigand@de.ibm.com).
   5
   6 This file is part of GCC.
   7
   8 GCC is free software; you can redistribute it and/or modify it under
   9 the terms of the GNU General Public License as published by the Free
  10 Software Foundation; either version 3, or (at your option) any later
  11 version.
  12
  13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16 for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GCC; see the file COPYING3.  If not see
  20 <http://www.gnu.org/licenses/>.  */
  21
  22 /* 256-bit integer mode is needed for STACK_SAVEAREA_MODE.  */
  23 INT_MODE (OI, 32);
  24
  25 /* Define TFmode to work around reload problem PR 20927.  */
  26 FLOAT_MODE (TF, 16, ieee_quad_format);
  27
  28 /* Add any extra modes needed to represent the condition code.  */
  29
  30 /*
  31
  32 Condition Codes
  33
  34 Check for zero
  35
  36 CCZ:  EQ          NE           NE          NE
  37 CCZ1: EQ          NE                                  (CS)
  38
  39 Unsigned compares
  40
  41 CCU:  EQ          LTU          GTU         NE         (CLG/R, CL/R/Y, CLM/Y, CLI/Y)
  42 CCUR: EQ          GTU          LTU         NE         (CLGF/R)
  43
  44 Signed compares
  45
  46 CCS:  EQ          LT           GT          UNORDERED  (LTGFR, LTGR, LTR, ICM/Y,
  47                                                        LTDBR, LTDR, LTEBR, LTER,
  48                                                        CG/R, C/R/Y, CGHI, CHI,
  49                                                        CDB/R, CD/R, CEB/R, CE/R,
  50                                                        ADB/R, AEB/R, SDB/R, SEB/R,
  51                                                        SRAG, SRA, SRDA)
  52 CCSR: EQ          GT           LT          UNORDERED  (CGF/R, CH/Y)
  53
  54 Condition codes resulting from add with overflow
  55
  56 CCA:  EQ          LT           GT          Overflow
  57 CCAP: EQ          LT           GT          LT         (AGHI, AHI)
  58 CCAN: EQ          LT           GT          GT         (AGHI, AHI)
  59
  60 Condition codes of unsigned adds and subs
  61
  62 CCL:  EQ          NE           EQ          NE         (ALGF/R, ALG/R, AL/R/Y,
  63                                                        ALCG/R, ALC/R,
  64                                                        SLGF/R, SLG/R, SL/R/Y,
  65                                                        SLBG/R, SLB/R)
  66 CCL1: GEU         GEU          LTU         LTU        (ALG/R, AL/R/Y)
  67 CCL2: GTU         GTU          LEU         LEU        (SLG/R, SL/R/Y)
  68 CCL3: EQ          LTU          EQ          GTU        (SLG/R, SL/R/Y)
  69
  70 Test under mask checks
  71
  72 CCT:  EQ          NE           NE          NE         (ICM/Y, TML, CG/R, CGHI,
  73                                                        C/R/Y, CHI, NG/R, N/R/Y,
  74                                                        OG/R, O/R/Y, XG/R, X/R/Y)
  75 CCT1: NE          EQ           NE          NE         (TMH, TML)
  76 CCT2: NE          NE           EQ          NE         (TMH, TML)
  77 CCT3: NE          NE           NE          EQ         (TMH, TML)
  78
  79 CCA and CCT modes are request only modes. These modes are never returned by
  80 s390_select_cc_mode. They are only intended to match other modes.
  81
  82 Requested mode            -> Destination CC register mode
  83
  84 CCS, CCU, CCT, CCSR, CCUR -> CCZ
  85 CCA                       -> CCAP, CCAN
  86
  87 Vector comparison modes
  88
  89 CCVEQ     EQ      -            -           NE         (VCEQ)
  90 CCVEQANY  EQ      EQ           -           NE         (VCEQ)
  91
  92 CCVH      GT      -            -           LE         (VCH)
  93 CCVHANY   GT      GT           -           LE         (VCH)
  94 CCVHU     GTU     -            -           LEU        (VCHL)
  95 CCVHUANY  GTU     GTU          -           LEU        (VCHL)
  96
  97 CCVFH     GT      -            -           UNLE       (VFCH)
  98 CCVFHANY  GT      GT           -           UNLE       (VFCH)
  99 CCVFHE    GE      -            -           UNLT       (VFCHE)
 100 CCVFHEANY GE      GE           -           UNLT       (VFCHE)
 101
 102
 103
 104
 105 *** Comments ***
 106
 107 CCAP, CCAN
 108
 109 The CC obtained from add instruction usually can't be used for comparisons
 110 because its coupling with overflow flag. In case of an overflow the
 111 less than/greater than data are lost. Nevertheless a comparison can be done
 112 whenever immediate values are involved because they are known at compile time.
 113 If you know whether the used constant is positive or negative you can predict
 114 the sign of the result even in case of an overflow.
 115
 116
 117 CCT, CCT1, CCT2, CCT3
 118
 119 If bits of an integer masked with an AND instruction are checked, the test under
 120 mask instructions turn out to be very handy for a set of special cases.
 121 The simple cases are checks whether all masked bits are zero or ones:
 122
 123   int a;
 124   if ((a & (16 + 128)) == 0)          -> CCT/CCZ
 125   if ((a & (16 + 128)) == 16 + 128)   -> CCT3
 126
 127 Using two extra modes makes it possible to do complete checks on two bits of an
 128 integer (This is possible on register operands only. TM does not provide the
 129 information necessary for CCT1 and CCT2 modes.):
 130
 131   int a;
 132   if ((a & (16 + 128)) == 16)         -> CCT1
 133   if ((a & (16 + 128)) == 128)        -> CCT2
 134
 135
 136 CCSR, CCUR
 137
 138 There are several instructions comparing 32 bit with 64-bit unsigned/signed
 139 values. Such instructions can be considered to have a builtin zero/sign_extend.
 140 The problem is that in the RTL (to be canonical) the zero/sign extended operand
 141 has to be the first one but the machine instructions like it the other way
 142 around. The following both modes can be considered as CCS and CCU modes with
 143 exchanged operands.
 144
 145
 146 CCL1, CCL2
 147
 148 These modes represent the result of overflow checks.
 149
 150 if (a + b < a) -> CCL1 state of the carry bit   (CC2 | CC3)
 151 if (a - b > a) -> CCL2 state of the borrow bit  (CC0 | CC1)
 152
 153 They are used when multi word numbers are computed dealing one SImode part after
 154 another or whenever manual overflow checks like the examples above are
 155 compiled.
 156
 157
 158 CCL3
 159
 160 A logical subtract instruction sets the borrow bit in case of an overflow.
 161 The resulting condition code of those instructions is represented by the
 162 CCL3 mode. Together with the CCU mode this mode is used for jumpless
 163 implementations of several if-constructs - see s390_expand_addcc for more
 164 details.
 165
 166 CCZ1
 167
 168 The compare and swap instructions sets the condition code to 0/1 if the
 169 operands were equal/unequal. The CCZ1 mode ensures the result can be
 170 effectively placed into a register.
 171
 172
 173 CCV*
 174
 175 The variants with and without ANY are generated by the same
 176 instructions and therefore are holding the same information.  However,
 177 when generating a condition code mask they require checking different
 178 bits of CC.  In that case the variants without ANY represent the
 179 results for *all* elements.
 180
 181 CCRAW
 182
 183 The cc mode generated by a non-compare instruction.  The condition
 184 code mask for the CC consumer is determined by the comparison operator
 185 (only EQ and NE allowed) and the immediate value given as second
 186 operand to the operator.  For the other CC modes this value used to be
 187 0.
 188
 189 */
 190
 191
 192 CC_MODE (CCZ);
 193 CC_MODE (CCZ1);
 194 CC_MODE (CCA);
 195 CC_MODE (CCAP);
 196 CC_MODE (CCAN);
 197 CC_MODE (CCL);
 198 CC_MODE (CCL1);
 199 CC_MODE (CCL2);
 200 CC_MODE (CCL3);
 201 CC_MODE (CCU);
 202 CC_MODE (CCUR);
 203 CC_MODE (CCS);
 204 CC_MODE (CCSR);
 205 CC_MODE (CCT);
 206 CC_MODE (CCT1);
 207 CC_MODE (CCT2);
 208 CC_MODE (CCT3);
 209 CC_MODE (CCRAW);
 210
 211 CC_MODE (CCVEQ);
 212 CC_MODE (CCVEQANY);
 213
 214 CC_MODE (CCVH);
 215 CC_MODE (CCVHANY);
 216 CC_MODE (CCVHU);
 217 CC_MODE (CCVHUANY);
 218
 219 CC_MODE (CCVFH);
 220 CC_MODE (CCVFHANY);
 221 CC_MODE (CCVFHE);
 222 CC_MODE (CCVFHEANY);
 223
 224
 225 /* Vector modes.  */
 226
 227 VECTOR_MODES (INT, 2);        /*                 V2QI */
 228 VECTOR_MODES (INT, 4);        /*            V4QI V2HI */
 229 VECTOR_MODES (INT, 8);        /*       V8QI V4HI V2SI */
 230 VECTOR_MODES (INT, 16);       /* V16QI V8HI V4SI V2DI */
 231
 232 VECTOR_MODE (FLOAT, SF, 2);   /* V2SF */
 233 VECTOR_MODE (FLOAT, SF, 4);   /* V4SF */
 234 VECTOR_MODE (FLOAT, DF, 2);   /* V2DF */
 235
 236 VECTOR_MODE (INT, QI, 1);     /* V1QI */
 237 VECTOR_MODE (INT, HI, 1);     /* V1HI */
 238 VECTOR_MODE (INT, SI, 1);     /* V1SI */
 239 VECTOR_MODE (INT, DI, 1);     /* V1DI */
 240 VECTOR_MODE (INT, TI, 1);     /* V1TI */
 241
 242 VECTOR_MODE (FLOAT, SF, 1);   /* V1SF */
 243 VECTOR_MODE (FLOAT, DF, 1);   /* V1DF */
 244 VECTOR_MODE (FLOAT, TF, 1);   /* V1TF */