gcc/config/s390/s390-modes.def

   1 /* Definitions of target machine for GNU compiler, for IBM S/390
   2    Copyright (C) 2002-2021 Free Software Foundation, Inc.
   3    Contributed by Hartmut Penner (hpenner@de.ibm.com) and
   4                   Ulrich Weigand (uweigand@de.ibm.com).
   5
   6 This file is part of GCC.
   7
   8 GCC is free software; you can redistribute it and/or modify it under
   9 the terms of the GNU General Public License as published by the Free
  10 Software Foundation; either version 3, or (at your option) any later
  11 version.
  12
  13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16 for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GCC; see the file COPYING3.  If not see
  20 <http://www.gnu.org/licenses/>.  */
  21
  22 /* 256-bit integer mode is needed for STACK_SAVEAREA_MODE.  */
  23 INT_MODE (OI, 32);
  24
  25 /* 128-bit float stored in a VR on z14+ or a FPR pair on older machines.  */
  26 FLOAT_MODE (TF, 16, ieee_quad_format);
  27
  28 /* 128-bit float stored in a FPR pair.  */
  29 FLOAT_MODE (FPRX2, 16, ieee_quad_format);
  30
  31 /* Add any extra modes needed to represent the condition code.  */
  32
  33 /*
  34
  35 Condition Codes
  36
  37       CC0         CC1          CC2         CC3
  38
  39 Check for zero
  40
  41 CCZ:  EQ          NE           NE          NE
  42 CCZ1: EQ          NE                                  (CS)
  43
  44 Unsigned compares
  45
  46 CCU:  EQ          LTU          GTU         NE         (CLG/R, CL/R/Y, CLM/Y, CLI/Y)
  47 CCUR: EQ          GTU          LTU         NE         (CLGF/R)
  48
  49 Signed compares
  50
  51 CCS:  EQ          LT           GT          UNORDERED  (LTGFR, LTGR, LTR, ICM/Y,
  52                                                        LTDBR, LTDR, LTEBR, LTER,
  53                                                        CG/R, C/R/Y, CGHI, CHI,
  54                                                        CDB/R, CD/R, CEB/R, CE/R,
  55                                                        ADB/R, AEB/R, SDB/R, SEB/R,
  56                                                        SRAG, SRA, SRDA)
  57 CCSR: EQ          GT           LT          UNORDERED  (CGF/R, CH/Y)
  58 CCSFPS: EQ        LT           GT          UNORDERED  (KEB/R, KDB/R, KXBR, KDTR,
  59                                                        KXTR, WFK)
  60
  61 Condition codes resulting from add with overflow
  62
  63 CCA:  EQ          LT           GT          Overflow
  64 CCAP: EQ          LT           GT          LT         (AGHI, AHI)
  65 CCAN: EQ          LT           GT          GT         (AGHI, AHI)
  66
  67 Condition codes for overflow checking resulting from signed adds/subs/mults
  68
  69 CCO:  EQ          EQ           EQ          NE         (AGR, AGHI, SGR, MSC, ...)
  70
  71 Condition codes of unsigned adds and subs
  72
  73 CCL:  EQ          NE           EQ          NE         (ALGF/R, ALG/R, AL/R/Y,
  74                                                        ALCG/R, ALC/R,
  75                                                        SLGF/R, SLG/R, SL/R/Y,
  76                                                        SLBG/R, SLB/R)
  77 CCL1: GEU         GEU          LTU         LTU        (ALG/R, AL/R/Y)
  78 CCL2: GTU         GTU          LEU         LEU        (SLG/R, SL/R/Y)
  79 CCL3: EQ          LTU          EQ          GTU        (SLG/R, SL/R/Y)
  80
  81 Test under mask checks
  82
  83 CCT:  EQ          NE           NE          NE         (ICM/Y, TML, CG/R, CGHI,
  84                                                        C/R/Y, CHI, NG/R, N/R/Y,
  85                                                        OG/R, O/R/Y, XG/R, X/R/Y)
  86 CCT1: NE          EQ           NE          NE         (TMH, TML)
  87 CCT2: NE          NE           EQ          NE         (TMH, TML)
  88 CCT3: NE          NE           NE          EQ         (TMH, TML)
  89
  90 CCA and CCT modes are request only modes. These modes are never returned by
  91 s390_select_cc_mode. They are only intended to match other modes.
  92
  93 Requested mode            -> Destination CC register mode
  94
  95 CCS, CCU, CCT, CCSR, CCUR -> CCZ
  96 CCA                       -> CCAP, CCAN
  97
  98
  99
 100 *** Comments ***
 101
 102 CCAP, CCAN
 103
 104 The CC obtained from add instruction usually can't be used for comparisons
 105 because its coupling with overflow flag. In case of an overflow the
 106 less than/greater than data are lost. Nevertheless a comparison can be done
 107 whenever immediate values are involved because they are known at compile time.
 108 If you know whether the used constant is positive or negative you can predict
 109 the sign of the result even in case of an overflow.
 110
 111
 112 CCO
 113
 114 This mode is used to check whether there was an overflow condition in
 115 a signed add, sub, or mul operation.  See (addv<mode>4, subv<mode>4,
 116 mulv<mode>4 patterns).
 117
 118
 119 CCT, CCT1, CCT2, CCT3
 120
 121 If bits of an integer masked with an AND instruction are checked, the test under
 122 mask instructions turn out to be very handy for a set of special cases.
 123 The simple cases are checks whether all masked bits are zero or ones:
 124
 125   int a;
 126   if ((a & (16 + 128)) == 0)          -> CCT/CCZ
 127   if ((a & (16 + 128)) == 16 + 128)   -> CCT3
 128
 129 Using two extra modes makes it possible to do complete checks on two bits of an
 130 integer (This is possible on register operands only. TM does not provide the
 131 information necessary for CCT1 and CCT2 modes.):
 132
 133   int a;
 134   if ((a & (16 + 128)) == 16)         -> CCT1
 135   if ((a & (16 + 128)) == 128)        -> CCT2
 136
 137
 138 CCSR, CCUR
 139
 140 There are several instructions comparing 32 bit with 64-bit unsigned/signed
 141 values. Such instructions can be considered to have a builtin zero/sign_extend.
 142 The problem is that in the RTL (to be canonical) the zero/sign extended operand
 143 has to be the first one but the machine instructions like it the other way
 144 around. The following both modes can be considered as CCS and CCU modes with
 145 exchanged operands.
 146
 147
 148 CCSFPS
 149
 150 This mode is used for signaling rtxes: LT, LE, GT, GE and LTGT.
 151
 152
 153 CCL1, CCL2
 154
 155 These modes represent the result of overflow checks.
 156
 157 if (a + b < a) -> CCL1 state of the carry bit   (CC2 | CC3)
 158 if (a - b > a) -> CCL2 state of the borrow bit  (CC0 | CC1)
 159
 160 They are used when multi word numbers are computed dealing one SImode part after
 161 another or whenever manual overflow checks like the examples above are
 162 compiled.
 163
 164
 165 CCL3
 166
 167 A logical subtract instruction sets the borrow bit in case of an overflow.
 168 The resulting condition code of those instructions is represented by the
 169 CCL3 mode. Together with the CCU mode this mode is used for jumpless
 170 implementations of several if-constructs - see s390_expand_addcc for more
 171 details.
 172
 173 CCZ1
 174
 175 The compare and swap instructions sets the condition code to 0/1 if the
 176 operands were equal/unequal. The CCZ1 mode ensures the result can be
 177 effectively placed into a register.
 178
 179 CCVIH, CCVIHU, CCVFH, CCVFHE
 180
 181 These are condition code modes used in instructions setting the
 182 condition code.  The mode determines which comparison to perform (H -
 183 high, HU - high unsigned, HE - high or equal) and whether it is a
 184 floating point comparison or not (I - int, F - float).
 185
 186 The comparison operation to be performed needs to be encoded into the
 187 condition code mode since the comparison operator is not available in
 188 compare style patterns (set cc (compare (op0) (op1))).  So the
 189 condition code mode is the only information to determine the
 190 instruction to be used.
 191
 192 CCVIALL, CCVIANY, CCVFALL, CCVFANY
 193
 194 These modes are used in instructions reading the condition code.
 195 Opposed to the CC producer patterns the comparison operator is
 196 available.  Hence the comparison operation does not need to be part of
 197 the CC mode.  However, we still need to know whether CC has been
 198 generated by a float or an integer comparison in order to be able to
 199 invert the condition correctly (int: GT -> LE, float: GT -> UNLE).
 200
 201 The ALL and ANY variants differ only in the usage of CC1 which
 202 indicates a mixed result across the vector elements.  Be aware that
 203 depending on the comparison code the ALL and ANY variants might
 204 actually refer to their opposite meaning.  I.e. while inverting the
 205 comparison in (EQ (reg:CCVIALL 33) (const_int 0)) results in (NE
 206 (reg:CCVIALL 33) (const_int 0)) it in fact describes an ANY comparison
 207 (inverting "all equal" should be "any not equal") However, the
 208 middle-end does invert only the comparison operator without touching
 209 the mode.
 210 Hence, the ALL/ANY in the mode names refer to the meaning in the
 211 context of EQ, GT, GE while for the inverted codes it actually means
 212 ANY/ALL.
 213
 214 CCRAW
 215
 216 The cc mode generated by a non-compare instruction.  The condition
 217 code mask for the CC consumer is determined by the comparison operator
 218 (only EQ and NE allowed) and the immediate value given as second
 219 operand to the operator.  For the other CC modes this value used to be
 220 0.
 221
 222 */
 223
 224
 225 CC_MODE (CCZ);
 226 CC_MODE (CCZ1);
 227 CC_MODE (CCA);
 228 CC_MODE (CCAP);
 229 CC_MODE (CCAN);
 230 CC_MODE (CCO);
 231 CC_MODE (CCL);
 232 CC_MODE (CCL1);
 233 CC_MODE (CCL2);
 234 CC_MODE (CCL3);
 235 CC_MODE (CCU);
 236 CC_MODE (CCUR);
 237 CC_MODE (CCS);
 238 CC_MODE (CCSR);
 239 CC_MODE (CCSFPS);
 240 CC_MODE (CCT);
 241 CC_MODE (CCT1);
 242 CC_MODE (CCT2);
 243 CC_MODE (CCT3);
 244 CC_MODE (CCRAW);
 245
 246 CC_MODE (CCVEQ);
 247
 248 CC_MODE (CCVIH);
 249 CC_MODE (CCVIHU);
 250
 251 CC_MODE (CCVFH);
 252 CC_MODE (CCVFHE);
 253
 254 CC_MODE (CCVIALL);
 255 CC_MODE (CCVIANY);
 256
 257 CC_MODE (CCVFALL);
 258 CC_MODE (CCVFANY);
 259
 260 /* Vector modes.  */
 261
 262 VECTOR_MODES (INT, 2);        /*                 V2QI */
 263 VECTOR_MODES (INT, 4);        /*            V4QI V2HI */
 264 VECTOR_MODES (INT, 8);        /*       V8QI V4HI V2SI */
 265 VECTOR_MODES (INT, 16);       /* V16QI V8HI V4SI V2DI */
 266
 267 VECTOR_MODE (FLOAT, SF, 2);   /* V2SF */
 268 VECTOR_MODE (FLOAT, SF, 4);   /* V4SF */
 269 VECTOR_MODE (FLOAT, DF, 2);   /* V2DF */
 270
 271 VECTOR_MODE (INT, QI, 1);     /* V1QI */
 272 VECTOR_MODE (INT, HI, 1);     /* V1HI */
 273 VECTOR_MODE (INT, SI, 1);     /* V1SI */
 274 VECTOR_MODE (INT, DI, 1);     /* V1DI */
 275 VECTOR_MODE (INT, TI, 1);     /* V1TI */
 276
 277 VECTOR_MODE (FLOAT, SF, 1);   /* V1SF */
 278 VECTOR_MODE (FLOAT, DF, 1);   /* V1DF */
 279 VECTOR_MODE (FLOAT, TF, 1);   /* V1TF */