1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com) and
6 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
32 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "diagnostic-core.h"
45 #include "basic-block.h"
46 #include "integrate.h"
49 #include "target-def.h"
51 #include "langhooks.h"
59 /* Define the specific costs for a given cpu. */
61 struct processor_costs
64 const int m
; /* cost of an M instruction. */
65 const int mghi
; /* cost of an MGHI instruction. */
66 const int mh
; /* cost of an MH instruction. */
67 const int mhi
; /* cost of an MHI instruction. */
68 const int ml
; /* cost of an ML instruction. */
69 const int mr
; /* cost of an MR instruction. */
70 const int ms
; /* cost of an MS instruction. */
71 const int msg
; /* cost of an MSG instruction. */
72 const int msgf
; /* cost of an MSGF instruction. */
73 const int msgfr
; /* cost of an MSGFR instruction. */
74 const int msgr
; /* cost of an MSGR instruction. */
75 const int msr
; /* cost of an MSR instruction. */
76 const int mult_df
; /* cost of multiplication in DFmode. */
79 const int sqxbr
; /* cost of square root in TFmode. */
80 const int sqdbr
; /* cost of square root in DFmode. */
81 const int sqebr
; /* cost of square root in SFmode. */
82 /* multiply and add */
83 const int madbr
; /* cost of multiply and add in DFmode. */
84 const int maebr
; /* cost of multiply and add in SFmode. */
96 const struct processor_costs
*s390_cost
;
99 struct processor_costs z900_cost
=
101 COSTS_N_INSNS (5), /* M */
102 COSTS_N_INSNS (10), /* MGHI */
103 COSTS_N_INSNS (5), /* MH */
104 COSTS_N_INSNS (4), /* MHI */
105 COSTS_N_INSNS (5), /* ML */
106 COSTS_N_INSNS (5), /* MR */
107 COSTS_N_INSNS (4), /* MS */
108 COSTS_N_INSNS (15), /* MSG */
109 COSTS_N_INSNS (7), /* MSGF */
110 COSTS_N_INSNS (7), /* MSGFR */
111 COSTS_N_INSNS (10), /* MSGR */
112 COSTS_N_INSNS (4), /* MSR */
113 COSTS_N_INSNS (7), /* multiplication in DFmode */
114 COSTS_N_INSNS (13), /* MXBR */
115 COSTS_N_INSNS (136), /* SQXBR */
116 COSTS_N_INSNS (44), /* SQDBR */
117 COSTS_N_INSNS (35), /* SQEBR */
118 COSTS_N_INSNS (18), /* MADBR */
119 COSTS_N_INSNS (13), /* MAEBR */
120 COSTS_N_INSNS (134), /* DXBR */
121 COSTS_N_INSNS (30), /* DDBR */
122 COSTS_N_INSNS (27), /* DEBR */
123 COSTS_N_INSNS (220), /* DLGR */
124 COSTS_N_INSNS (34), /* DLR */
125 COSTS_N_INSNS (34), /* DR */
126 COSTS_N_INSNS (32), /* DSGFR */
127 COSTS_N_INSNS (32), /* DSGR */
131 struct processor_costs z990_cost
=
133 COSTS_N_INSNS (4), /* M */
134 COSTS_N_INSNS (2), /* MGHI */
135 COSTS_N_INSNS (2), /* MH */
136 COSTS_N_INSNS (2), /* MHI */
137 COSTS_N_INSNS (4), /* ML */
138 COSTS_N_INSNS (4), /* MR */
139 COSTS_N_INSNS (5), /* MS */
140 COSTS_N_INSNS (6), /* MSG */
141 COSTS_N_INSNS (4), /* MSGF */
142 COSTS_N_INSNS (4), /* MSGFR */
143 COSTS_N_INSNS (4), /* MSGR */
144 COSTS_N_INSNS (4), /* MSR */
145 COSTS_N_INSNS (1), /* multiplication in DFmode */
146 COSTS_N_INSNS (28), /* MXBR */
147 COSTS_N_INSNS (130), /* SQXBR */
148 COSTS_N_INSNS (66), /* SQDBR */
149 COSTS_N_INSNS (38), /* SQEBR */
150 COSTS_N_INSNS (1), /* MADBR */
151 COSTS_N_INSNS (1), /* MAEBR */
152 COSTS_N_INSNS (60), /* DXBR */
153 COSTS_N_INSNS (40), /* DDBR */
154 COSTS_N_INSNS (26), /* DEBR */
155 COSTS_N_INSNS (176), /* DLGR */
156 COSTS_N_INSNS (31), /* DLR */
157 COSTS_N_INSNS (31), /* DR */
158 COSTS_N_INSNS (31), /* DSGFR */
159 COSTS_N_INSNS (31), /* DSGR */
163 struct processor_costs z9_109_cost
=
165 COSTS_N_INSNS (4), /* M */
166 COSTS_N_INSNS (2), /* MGHI */
167 COSTS_N_INSNS (2), /* MH */
168 COSTS_N_INSNS (2), /* MHI */
169 COSTS_N_INSNS (4), /* ML */
170 COSTS_N_INSNS (4), /* MR */
171 COSTS_N_INSNS (5), /* MS */
172 COSTS_N_INSNS (6), /* MSG */
173 COSTS_N_INSNS (4), /* MSGF */
174 COSTS_N_INSNS (4), /* MSGFR */
175 COSTS_N_INSNS (4), /* MSGR */
176 COSTS_N_INSNS (4), /* MSR */
177 COSTS_N_INSNS (1), /* multiplication in DFmode */
178 COSTS_N_INSNS (28), /* MXBR */
179 COSTS_N_INSNS (130), /* SQXBR */
180 COSTS_N_INSNS (66), /* SQDBR */
181 COSTS_N_INSNS (38), /* SQEBR */
182 COSTS_N_INSNS (1), /* MADBR */
183 COSTS_N_INSNS (1), /* MAEBR */
184 COSTS_N_INSNS (60), /* DXBR */
185 COSTS_N_INSNS (40), /* DDBR */
186 COSTS_N_INSNS (26), /* DEBR */
187 COSTS_N_INSNS (30), /* DLGR */
188 COSTS_N_INSNS (23), /* DLR */
189 COSTS_N_INSNS (23), /* DR */
190 COSTS_N_INSNS (24), /* DSGFR */
191 COSTS_N_INSNS (24), /* DSGR */
195 struct processor_costs z10_cost
=
197 COSTS_N_INSNS (10), /* M */
198 COSTS_N_INSNS (10), /* MGHI */
199 COSTS_N_INSNS (10), /* MH */
200 COSTS_N_INSNS (10), /* MHI */
201 COSTS_N_INSNS (10), /* ML */
202 COSTS_N_INSNS (10), /* MR */
203 COSTS_N_INSNS (10), /* MS */
204 COSTS_N_INSNS (10), /* MSG */
205 COSTS_N_INSNS (10), /* MSGF */
206 COSTS_N_INSNS (10), /* MSGFR */
207 COSTS_N_INSNS (10), /* MSGR */
208 COSTS_N_INSNS (10), /* MSR */
209 COSTS_N_INSNS (1) , /* multiplication in DFmode */
210 COSTS_N_INSNS (50), /* MXBR */
211 COSTS_N_INSNS (120), /* SQXBR */
212 COSTS_N_INSNS (52), /* SQDBR */
213 COSTS_N_INSNS (38), /* SQEBR */
214 COSTS_N_INSNS (1), /* MADBR */
215 COSTS_N_INSNS (1), /* MAEBR */
216 COSTS_N_INSNS (111), /* DXBR */
217 COSTS_N_INSNS (39), /* DDBR */
218 COSTS_N_INSNS (32), /* DEBR */
219 COSTS_N_INSNS (160), /* DLGR */
220 COSTS_N_INSNS (71), /* DLR */
221 COSTS_N_INSNS (71), /* DR */
222 COSTS_N_INSNS (71), /* DSGFR */
223 COSTS_N_INSNS (71), /* DSGR */
227 struct processor_costs z196_cost
=
229 COSTS_N_INSNS (7), /* M */
230 COSTS_N_INSNS (5), /* MGHI */
231 COSTS_N_INSNS (5), /* MH */
232 COSTS_N_INSNS (5), /* MHI */
233 COSTS_N_INSNS (7), /* ML */
234 COSTS_N_INSNS (7), /* MR */
235 COSTS_N_INSNS (6), /* MS */
236 COSTS_N_INSNS (8), /* MSG */
237 COSTS_N_INSNS (6), /* MSGF */
238 COSTS_N_INSNS (6), /* MSGFR */
239 COSTS_N_INSNS (8), /* MSGR */
240 COSTS_N_INSNS (6), /* MSR */
241 COSTS_N_INSNS (1) , /* multiplication in DFmode */
242 COSTS_N_INSNS (40), /* MXBR B+40 */
243 COSTS_N_INSNS (100), /* SQXBR B+100 */
244 COSTS_N_INSNS (42), /* SQDBR B+42 */
245 COSTS_N_INSNS (28), /* SQEBR B+28 */
246 COSTS_N_INSNS (1), /* MADBR B */
247 COSTS_N_INSNS (1), /* MAEBR B */
248 COSTS_N_INSNS (101), /* DXBR B+101 */
249 COSTS_N_INSNS (29), /* DDBR */
250 COSTS_N_INSNS (22), /* DEBR */
251 COSTS_N_INSNS (160), /* DLGR cracked */
252 COSTS_N_INSNS (160), /* DLR cracked */
253 COSTS_N_INSNS (160), /* DR expanded */
254 COSTS_N_INSNS (160), /* DSGFR cracked */
255 COSTS_N_INSNS (160), /* DSGR cracked */
258 extern int reload_completed
;
260 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
261 static rtx last_scheduled_insn
;
263 /* Structure used to hold the components of a S/390 memory
264 address. A legitimate address on S/390 is of the general
266 base + index + displacement
267 where any of the components is optional.
269 base and index are registers of the class ADDR_REGS,
270 displacement is an unsigned 12-bit immediate constant. */
281 /* Which cpu are we tuning for. */
282 enum processor_type s390_tune
= PROCESSOR_max
;
284 /* Which instruction set architecture to use. */
285 enum processor_type s390_arch
;
288 HOST_WIDE_INT s390_warn_framesize
= 0;
289 HOST_WIDE_INT s390_stack_size
= 0;
290 HOST_WIDE_INT s390_stack_guard
= 0;
292 /* The following structure is embedded in the machine
293 specific part of struct function. */
295 struct GTY (()) s390_frame_layout
297 /* Offset within stack frame. */
298 HOST_WIDE_INT gprs_offset
;
299 HOST_WIDE_INT f0_offset
;
300 HOST_WIDE_INT f4_offset
;
301 HOST_WIDE_INT f8_offset
;
302 HOST_WIDE_INT backchain_offset
;
304 /* Number of first and last gpr where slots in the register
305 save area are reserved for. */
306 int first_save_gpr_slot
;
307 int last_save_gpr_slot
;
309 /* Number of first and last gpr to be saved, restored. */
311 int first_restore_gpr
;
313 int last_restore_gpr
;
315 /* Bits standing for floating point registers. Set, if the
316 respective register has to be saved. Starting with reg 16 (f0)
317 at the rightmost bit.
318 Bit 15 - 8 7 6 5 4 3 2 1 0
319 fpr 15 - 8 7 5 3 1 6 4 2 0
320 reg 31 - 24 23 22 21 20 19 18 17 16 */
321 unsigned int fpr_bitmap
;
323 /* Number of floating point registers f8-f15 which must be saved. */
326 /* Set if return address needs to be saved.
327 This flag is set by s390_return_addr_rtx if it could not use
328 the initial value of r14 and therefore depends on r14 saved
330 bool save_return_addr_p
;
332 /* Size of stack frame. */
333 HOST_WIDE_INT frame_size
;
336 /* Define the structure for the machine field in struct function. */
338 struct GTY(()) machine_function
340 struct s390_frame_layout frame_layout
;
342 /* Literal pool base register. */
345 /* True if we may need to perform branch splitting. */
346 bool split_branches_pending_p
;
348 /* Some local-dynamic TLS symbol name. */
349 const char *some_ld_name
;
351 bool has_landing_pad_p
;
354 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
356 #define cfun_frame_layout (cfun->machine->frame_layout)
357 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
358 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
359 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
360 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
362 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
365 /* Number of GPRs and FPRs used for argument passing. */
366 #define GP_ARG_NUM_REG 5
367 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
369 /* A couple of shortcuts. */
370 #define CONST_OK_FOR_J(x) \
371 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
372 #define CONST_OK_FOR_K(x) \
373 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
374 #define CONST_OK_FOR_Os(x) \
375 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
376 #define CONST_OK_FOR_Op(x) \
377 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
378 #define CONST_OK_FOR_On(x) \
379 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
381 #define REGNO_PAIR_OK(REGNO, MODE) \
382 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
384 /* That's the read ahead of the dynamic branch prediction unit in
385 bytes on a z10 (or higher) CPU. */
386 #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
388 static enum machine_mode
389 s390_libgcc_cmp_return_mode (void)
391 return TARGET_64BIT
? DImode
: SImode
;
394 static enum machine_mode
395 s390_libgcc_shift_count_mode (void)
397 return TARGET_64BIT
? DImode
: SImode
;
400 static enum machine_mode
401 s390_unwind_word_mode (void)
403 return TARGET_64BIT
? DImode
: SImode
;
406 /* Return true if the back end supports mode MODE. */
408 s390_scalar_mode_supported_p (enum machine_mode mode
)
410 /* In contrast to the default implementation reject TImode constants on 31bit
411 TARGET_ZARCH for ABI compliance. */
412 if (!TARGET_64BIT
&& TARGET_ZARCH
&& mode
== TImode
)
415 if (DECIMAL_FLOAT_MODE_P (mode
))
416 return default_decimal_float_supported_p ();
418 return default_scalar_mode_supported_p (mode
);
421 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
424 s390_set_has_landing_pad_p (bool value
)
426 cfun
->machine
->has_landing_pad_p
= value
;
429 /* If two condition code modes are compatible, return a condition code
430 mode which is compatible with both. Otherwise, return
433 static enum machine_mode
434 s390_cc_modes_compatible (enum machine_mode m1
, enum machine_mode m2
)
442 if (m2
== CCUmode
|| m2
== CCTmode
|| m2
== CCZ1mode
443 || m2
== CCSmode
|| m2
== CCSRmode
|| m2
== CCURmode
)
464 /* Return true if SET either doesn't set the CC register, or else
465 the source and destination have matching CC modes and that
466 CC mode is at least as constrained as REQ_MODE. */
469 s390_match_ccmode_set (rtx set
, enum machine_mode req_mode
)
471 enum machine_mode set_mode
;
473 gcc_assert (GET_CODE (set
) == SET
);
475 if (GET_CODE (SET_DEST (set
)) != REG
|| !CC_REGNO_P (REGNO (SET_DEST (set
))))
478 set_mode
= GET_MODE (SET_DEST (set
));
492 if (req_mode
!= set_mode
)
497 if (req_mode
!= CCSmode
&& req_mode
!= CCUmode
&& req_mode
!= CCTmode
498 && req_mode
!= CCSRmode
&& req_mode
!= CCURmode
)
504 if (req_mode
!= CCAmode
)
512 return (GET_MODE (SET_SRC (set
)) == set_mode
);
515 /* Return true if every SET in INSN that sets the CC register
516 has source and destination with matching CC modes and that
517 CC mode is at least as constrained as REQ_MODE.
518 If REQ_MODE is VOIDmode, always return false. */
521 s390_match_ccmode (rtx insn
, enum machine_mode req_mode
)
525 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
526 if (req_mode
== VOIDmode
)
529 if (GET_CODE (PATTERN (insn
)) == SET
)
530 return s390_match_ccmode_set (PATTERN (insn
), req_mode
);
532 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
533 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
535 rtx set
= XVECEXP (PATTERN (insn
), 0, i
);
536 if (GET_CODE (set
) == SET
)
537 if (!s390_match_ccmode_set (set
, req_mode
))
544 /* If a test-under-mask instruction can be used to implement
545 (compare (and ... OP1) OP2), return the CC mode required
546 to do that. Otherwise, return VOIDmode.
547 MIXED is true if the instruction can distinguish between
548 CC1 and CC2 for mixed selected bits (TMxx), it is false
549 if the instruction cannot (TM). */
552 s390_tm_ccmode (rtx op1
, rtx op2
, bool mixed
)
556 /* ??? Fixme: should work on CONST_DOUBLE as well. */
557 if (GET_CODE (op1
) != CONST_INT
|| GET_CODE (op2
) != CONST_INT
)
560 /* Selected bits all zero: CC0.
561 e.g.: int a; if ((a & (16 + 128)) == 0) */
562 if (INTVAL (op2
) == 0)
565 /* Selected bits all one: CC3.
566 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
567 if (INTVAL (op2
) == INTVAL (op1
))
570 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
572 if ((a & (16 + 128)) == 16) -> CCT1
573 if ((a & (16 + 128)) == 128) -> CCT2 */
576 bit1
= exact_log2 (INTVAL (op2
));
577 bit0
= exact_log2 (INTVAL (op1
) ^ INTVAL (op2
));
578 if (bit0
!= -1 && bit1
!= -1)
579 return bit0
> bit1
? CCT1mode
: CCT2mode
;
585 /* Given a comparison code OP (EQ, NE, etc.) and the operands
586 OP0 and OP1 of a COMPARE, return the mode to be used for the
590 s390_select_ccmode (enum rtx_code code
, rtx op0
, rtx op1
)
596 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
597 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
599 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
600 && CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1))))
602 if ((GET_CODE (op0
) == PLUS
|| GET_CODE (op0
) == MINUS
603 || GET_CODE (op1
) == NEG
)
604 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
607 if (GET_CODE (op0
) == AND
)
609 /* Check whether we can potentially do it via TM. */
610 enum machine_mode ccmode
;
611 ccmode
= s390_tm_ccmode (XEXP (op0
, 1), op1
, 1);
612 if (ccmode
!= VOIDmode
)
614 /* Relax CCTmode to CCZmode to allow fall-back to AND
615 if that turns out to be beneficial. */
616 return ccmode
== CCTmode
? CCZmode
: ccmode
;
620 if (register_operand (op0
, HImode
)
621 && GET_CODE (op1
) == CONST_INT
622 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 65535))
624 if (register_operand (op0
, QImode
)
625 && GET_CODE (op1
) == CONST_INT
626 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 255))
635 /* The only overflow condition of NEG and ABS happens when
636 -INT_MAX is used as parameter, which stays negative. So
637 we have an overflow from a positive value to a negative.
638 Using CCAP mode the resulting cc can be used for comparisons. */
639 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
640 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
643 /* If constants are involved in an add instruction it is possible to use
644 the resulting cc for comparisons with zero. Knowing the sign of the
645 constant the overflow behavior gets predictable. e.g.:
646 int a, b; if ((b = a + c) > 0)
647 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
648 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
649 && CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1))))
651 if (INTVAL (XEXP((op0
), 1)) < 0)
665 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
666 && GET_CODE (op1
) != CONST_INT
)
672 if (GET_CODE (op0
) == PLUS
673 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
676 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
677 && GET_CODE (op1
) != CONST_INT
)
683 if (GET_CODE (op0
) == MINUS
684 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
687 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
688 && GET_CODE (op1
) != CONST_INT
)
697 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
698 that we can implement more efficiently. */
701 s390_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
)
703 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
704 if ((*code
== EQ
|| *code
== NE
)
705 && *op1
== const0_rtx
706 && GET_CODE (*op0
) == ZERO_EXTRACT
707 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
708 && GET_CODE (XEXP (*op0
, 2)) == CONST_INT
709 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
711 rtx inner
= XEXP (*op0
, 0);
712 HOST_WIDE_INT modesize
= GET_MODE_BITSIZE (GET_MODE (inner
));
713 HOST_WIDE_INT len
= INTVAL (XEXP (*op0
, 1));
714 HOST_WIDE_INT pos
= INTVAL (XEXP (*op0
, 2));
716 if (len
> 0 && len
< modesize
717 && pos
>= 0 && pos
+ len
<= modesize
718 && modesize
<= HOST_BITS_PER_WIDE_INT
)
720 unsigned HOST_WIDE_INT block
;
721 block
= ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
722 block
<<= modesize
- pos
- len
;
724 *op0
= gen_rtx_AND (GET_MODE (inner
), inner
,
725 gen_int_mode (block
, GET_MODE (inner
)));
729 /* Narrow AND of memory against immediate to enable TM. */
730 if ((*code
== EQ
|| *code
== NE
)
731 && *op1
== const0_rtx
732 && GET_CODE (*op0
) == AND
733 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
734 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
736 rtx inner
= XEXP (*op0
, 0);
737 rtx mask
= XEXP (*op0
, 1);
739 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
740 if (GET_CODE (inner
) == SUBREG
741 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner
)))
742 && (GET_MODE_SIZE (GET_MODE (inner
))
743 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner
))))
745 & GET_MODE_MASK (GET_MODE (inner
))
746 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner
))))
748 inner
= SUBREG_REG (inner
);
750 /* Do not change volatile MEMs. */
751 if (MEM_P (inner
) && !MEM_VOLATILE_P (inner
))
753 int part
= s390_single_part (XEXP (*op0
, 1),
754 GET_MODE (inner
), QImode
, 0);
757 mask
= gen_int_mode (s390_extract_part (mask
, QImode
, 0), QImode
);
758 inner
= adjust_address_nv (inner
, QImode
, part
);
759 *op0
= gen_rtx_AND (QImode
, inner
, mask
);
764 /* Narrow comparisons against 0xffff to HImode if possible. */
765 if ((*code
== EQ
|| *code
== NE
)
766 && GET_CODE (*op1
) == CONST_INT
767 && INTVAL (*op1
) == 0xffff
768 && SCALAR_INT_MODE_P (GET_MODE (*op0
))
769 && (nonzero_bits (*op0
, GET_MODE (*op0
))
770 & ~(unsigned HOST_WIDE_INT
) 0xffff) == 0)
772 *op0
= gen_lowpart (HImode
, *op0
);
776 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
777 if (GET_CODE (*op0
) == UNSPEC
778 && XINT (*op0
, 1) == UNSPEC_CCU_TO_INT
779 && XVECLEN (*op0
, 0) == 1
780 && GET_MODE (XVECEXP (*op0
, 0, 0)) == CCUmode
781 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
782 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
783 && *op1
== const0_rtx
)
785 enum rtx_code new_code
= UNKNOWN
;
788 case EQ
: new_code
= EQ
; break;
789 case NE
: new_code
= NE
; break;
790 case LT
: new_code
= GTU
; break;
791 case GT
: new_code
= LTU
; break;
792 case LE
: new_code
= GEU
; break;
793 case GE
: new_code
= LEU
; break;
797 if (new_code
!= UNKNOWN
)
799 *op0
= XVECEXP (*op0
, 0, 0);
804 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
805 if (GET_CODE (*op0
) == UNSPEC
806 && XINT (*op0
, 1) == UNSPEC_CCZ_TO_INT
807 && XVECLEN (*op0
, 0) == 1
808 && GET_MODE (XVECEXP (*op0
, 0, 0)) == CCZmode
809 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
810 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
811 && *op1
== const0_rtx
)
813 enum rtx_code new_code
= UNKNOWN
;
816 case EQ
: new_code
= EQ
; break;
817 case NE
: new_code
= NE
; break;
821 if (new_code
!= UNKNOWN
)
823 *op0
= XVECEXP (*op0
, 0, 0);
828 /* Simplify cascaded EQ, NE with const0_rtx. */
829 if ((*code
== NE
|| *code
== EQ
)
830 && (GET_CODE (*op0
) == EQ
|| GET_CODE (*op0
) == NE
)
831 && GET_MODE (*op0
) == SImode
832 && GET_MODE (XEXP (*op0
, 0)) == CCZ1mode
833 && REG_P (XEXP (*op0
, 0))
834 && XEXP (*op0
, 1) == const0_rtx
835 && *op1
== const0_rtx
)
837 if ((*code
== EQ
&& GET_CODE (*op0
) == NE
)
838 || (*code
== NE
&& GET_CODE (*op0
) == EQ
))
842 *op0
= XEXP (*op0
, 0);
845 /* Prefer register over memory as first operand. */
846 if (MEM_P (*op0
) && REG_P (*op1
))
848 rtx tem
= *op0
; *op0
= *op1
; *op1
= tem
;
849 *code
= swap_condition (*code
);
853 /* Emit a compare instruction suitable to implement the comparison
854 OP0 CODE OP1. Return the correct condition RTL to be placed in
855 the IF_THEN_ELSE of the conditional branch testing the result. */
858 s390_emit_compare (enum rtx_code code
, rtx op0
, rtx op1
)
860 enum machine_mode mode
= s390_select_ccmode (code
, op0
, op1
);
863 /* Do not output a redundant compare instruction if a compare_and_swap
864 pattern already computed the result and the machine modes are compatible. */
865 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
867 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0
), mode
)
873 cc
= gen_rtx_REG (mode
, CC_REGNUM
);
874 emit_insn (gen_rtx_SET (VOIDmode
, cc
, gen_rtx_COMPARE (mode
, op0
, op1
)));
877 return gen_rtx_fmt_ee (code
, VOIDmode
, cc
, const0_rtx
);
880 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
882 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
883 conditional branch testing the result. */
886 s390_emit_compare_and_swap (enum rtx_code code
, rtx old
, rtx mem
, rtx cmp
, rtx new_rtx
)
888 emit_insn (gen_sync_compare_and_swapsi (old
, mem
, cmp
, new_rtx
));
889 return s390_emit_compare (code
, gen_rtx_REG (CCZ1mode
, CC_REGNUM
), const0_rtx
);
892 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
893 unconditional jump, else a conditional jump under condition COND. */
896 s390_emit_jump (rtx target
, rtx cond
)
900 target
= gen_rtx_LABEL_REF (VOIDmode
, target
);
902 target
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, target
, pc_rtx
);
904 insn
= gen_rtx_SET (VOIDmode
, pc_rtx
, target
);
905 emit_jump_insn (insn
);
908 /* Return branch condition mask to implement a branch
909 specified by CODE. Return -1 for invalid comparisons. */
912 s390_branch_condition_mask (rtx code
)
914 const int CC0
= 1 << 3;
915 const int CC1
= 1 << 2;
916 const int CC2
= 1 << 1;
917 const int CC3
= 1 << 0;
919 gcc_assert (GET_CODE (XEXP (code
, 0)) == REG
);
920 gcc_assert (REGNO (XEXP (code
, 0)) == CC_REGNUM
);
921 gcc_assert (XEXP (code
, 1) == const0_rtx
);
923 switch (GET_MODE (XEXP (code
, 0)))
927 switch (GET_CODE (code
))
930 case NE
: return CC1
| CC2
| CC3
;
936 switch (GET_CODE (code
))
939 case NE
: return CC0
| CC2
| CC3
;
945 switch (GET_CODE (code
))
948 case NE
: return CC0
| CC1
| CC3
;
954 switch (GET_CODE (code
))
957 case NE
: return CC0
| CC1
| CC2
;
963 switch (GET_CODE (code
))
965 case EQ
: return CC0
| CC2
;
966 case NE
: return CC1
| CC3
;
972 switch (GET_CODE (code
))
974 case LTU
: return CC2
| CC3
; /* carry */
975 case GEU
: return CC0
| CC1
; /* no carry */
981 switch (GET_CODE (code
))
983 case GTU
: return CC0
| CC1
; /* borrow */
984 case LEU
: return CC2
| CC3
; /* no borrow */
990 switch (GET_CODE (code
))
992 case EQ
: return CC0
| CC2
;
993 case NE
: return CC1
| CC3
;
994 case LTU
: return CC1
;
995 case GTU
: return CC3
;
996 case LEU
: return CC1
| CC2
;
997 case GEU
: return CC2
| CC3
;
1002 switch (GET_CODE (code
))
1004 case EQ
: return CC0
;
1005 case NE
: return CC1
| CC2
| CC3
;
1006 case LTU
: return CC1
;
1007 case GTU
: return CC2
;
1008 case LEU
: return CC0
| CC1
;
1009 case GEU
: return CC0
| CC2
;
1015 switch (GET_CODE (code
))
1017 case EQ
: return CC0
;
1018 case NE
: return CC2
| CC1
| CC3
;
1019 case LTU
: return CC2
;
1020 case GTU
: return CC1
;
1021 case LEU
: return CC0
| CC2
;
1022 case GEU
: return CC0
| CC1
;
1028 switch (GET_CODE (code
))
1030 case EQ
: return CC0
;
1031 case NE
: return CC1
| CC2
| CC3
;
1032 case LT
: return CC1
| CC3
;
1033 case GT
: return CC2
;
1034 case LE
: return CC0
| CC1
| CC3
;
1035 case GE
: return CC0
| CC2
;
1041 switch (GET_CODE (code
))
1043 case EQ
: return CC0
;
1044 case NE
: return CC1
| CC2
| CC3
;
1045 case LT
: return CC1
;
1046 case GT
: return CC2
| CC3
;
1047 case LE
: return CC0
| CC1
;
1048 case GE
: return CC0
| CC2
| CC3
;
1054 switch (GET_CODE (code
))
1056 case EQ
: return CC0
;
1057 case NE
: return CC1
| CC2
| CC3
;
1058 case LT
: return CC1
;
1059 case GT
: return CC2
;
1060 case LE
: return CC0
| CC1
;
1061 case GE
: return CC0
| CC2
;
1062 case UNORDERED
: return CC3
;
1063 case ORDERED
: return CC0
| CC1
| CC2
;
1064 case UNEQ
: return CC0
| CC3
;
1065 case UNLT
: return CC1
| CC3
;
1066 case UNGT
: return CC2
| CC3
;
1067 case UNLE
: return CC0
| CC1
| CC3
;
1068 case UNGE
: return CC0
| CC2
| CC3
;
1069 case LTGT
: return CC1
| CC2
;
1075 switch (GET_CODE (code
))
1077 case EQ
: return CC0
;
1078 case NE
: return CC2
| CC1
| CC3
;
1079 case LT
: return CC2
;
1080 case GT
: return CC1
;
1081 case LE
: return CC0
| CC2
;
1082 case GE
: return CC0
| CC1
;
1083 case UNORDERED
: return CC3
;
1084 case ORDERED
: return CC0
| CC2
| CC1
;
1085 case UNEQ
: return CC0
| CC3
;
1086 case UNLT
: return CC2
| CC3
;
1087 case UNGT
: return CC1
| CC3
;
1088 case UNLE
: return CC0
| CC2
| CC3
;
1089 case UNGE
: return CC0
| CC1
| CC3
;
1090 case LTGT
: return CC2
| CC1
;
1101 /* Return branch condition mask to implement a compare and branch
1102 specified by CODE. Return -1 for invalid comparisons. */
1105 s390_compare_and_branch_condition_mask (rtx code
)
1107 const int CC0
= 1 << 3;
1108 const int CC1
= 1 << 2;
1109 const int CC2
= 1 << 1;
1111 switch (GET_CODE (code
))
1135 /* If INV is false, return assembler mnemonic string to implement
1136 a branch specified by CODE. If INV is true, return mnemonic
1137 for the corresponding inverted branch. */
1140 s390_branch_condition_mnemonic (rtx code
, int inv
)
1144 static const char *const mnemonic
[16] =
1146 NULL
, "o", "h", "nle",
1147 "l", "nhe", "lh", "ne",
1148 "e", "nlh", "he", "nl",
1149 "le", "nh", "no", NULL
1152 if (GET_CODE (XEXP (code
, 0)) == REG
1153 && REGNO (XEXP (code
, 0)) == CC_REGNUM
1154 && XEXP (code
, 1) == const0_rtx
)
1155 mask
= s390_branch_condition_mask (code
);
1157 mask
= s390_compare_and_branch_condition_mask (code
);
1159 gcc_assert (mask
>= 0);
1164 gcc_assert (mask
>= 1 && mask
<= 14);
1166 return mnemonic
[mask
];
1169 /* Return the part of op which has a value different from def.
1170 The size of the part is determined by mode.
1171 Use this function only if you already know that op really
1172 contains such a part. */
1174 unsigned HOST_WIDE_INT
1175 s390_extract_part (rtx op
, enum machine_mode mode
, int def
)
1177 unsigned HOST_WIDE_INT value
= 0;
1178 int max_parts
= HOST_BITS_PER_WIDE_INT
/ GET_MODE_BITSIZE (mode
);
1179 int part_bits
= GET_MODE_BITSIZE (mode
);
1180 unsigned HOST_WIDE_INT part_mask
1181 = ((unsigned HOST_WIDE_INT
)1 << part_bits
) - 1;
1184 for (i
= 0; i
< max_parts
; i
++)
1187 value
= (unsigned HOST_WIDE_INT
) INTVAL (op
);
1189 value
>>= part_bits
;
1191 if ((value
& part_mask
) != (def
& part_mask
))
1192 return value
& part_mask
;
1198 /* If OP is an integer constant of mode MODE with exactly one
1199 part of mode PART_MODE unequal to DEF, return the number of that
1200 part. Otherwise, return -1. */
1203 s390_single_part (rtx op
,
1204 enum machine_mode mode
,
1205 enum machine_mode part_mode
,
1208 unsigned HOST_WIDE_INT value
= 0;
1209 int n_parts
= GET_MODE_SIZE (mode
) / GET_MODE_SIZE (part_mode
);
1210 unsigned HOST_WIDE_INT part_mask
1211 = ((unsigned HOST_WIDE_INT
)1 << GET_MODE_BITSIZE (part_mode
)) - 1;
1214 if (GET_CODE (op
) != CONST_INT
)
1217 for (i
= 0; i
< n_parts
; i
++)
1220 value
= (unsigned HOST_WIDE_INT
) INTVAL (op
);
1222 value
>>= GET_MODE_BITSIZE (part_mode
);
1224 if ((value
& part_mask
) != (def
& part_mask
))
1232 return part
== -1 ? -1 : n_parts
- 1 - part
;
1235 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1236 bits and no other bits are set in IN. POS and LENGTH can be used
1237 to obtain the start position and the length of the bitfield.
1239 POS gives the position of the first bit of the bitfield counting
1240 from the lowest order bit starting with zero. In order to use this
1241 value for S/390 instructions this has to be converted to "bits big
1245 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in
, int size
,
1246 int *pos
, int *length
)
1251 unsigned HOST_WIDE_INT mask
= 1ULL;
1252 bool contiguous
= false;
1254 for (i
= 0; i
< size
; mask
<<= 1, i
++)
1278 /* Calculate a mask for all bits beyond the contiguous bits. */
1279 mask
= (-1LL & ~(((1ULL << (tmp_length
+ tmp_pos
- 1)) << 1) - 1));
1284 if (tmp_length
+ tmp_pos
- 1 > size
)
1288 *length
= tmp_length
;
1296 /* Check whether we can (and want to) split a double-word
1297 move in mode MODE from SRC to DST into two single-word
1298 moves, moving the subword FIRST_SUBWORD first. */
1301 s390_split_ok_p (rtx dst
, rtx src
, enum machine_mode mode
, int first_subword
)
1303 /* Floating point registers cannot be split. */
1304 if (FP_REG_P (src
) || FP_REG_P (dst
))
1307 /* We don't need to split if operands are directly accessible. */
1308 if (s_operand (src
, mode
) || s_operand (dst
, mode
))
1311 /* Non-offsettable memory references cannot be split. */
1312 if ((GET_CODE (src
) == MEM
&& !offsettable_memref_p (src
))
1313 || (GET_CODE (dst
) == MEM
&& !offsettable_memref_p (dst
)))
1316 /* Moving the first subword must not clobber a register
1317 needed to move the second subword. */
1318 if (register_operand (dst
, mode
))
1320 rtx subreg
= operand_subword (dst
, first_subword
, 0, mode
);
1321 if (reg_overlap_mentioned_p (subreg
, src
))
1328 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1329 and [MEM2, MEM2 + SIZE] do overlap and false
1333 s390_overlap_p (rtx mem1
, rtx mem2
, HOST_WIDE_INT size
)
1335 rtx addr1
, addr2
, addr_delta
;
1336 HOST_WIDE_INT delta
;
1338 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
1344 addr1
= XEXP (mem1
, 0);
1345 addr2
= XEXP (mem2
, 0);
1347 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
1349 /* This overlapping check is used by peepholes merging memory block operations.
1350 Overlapping operations would otherwise be recognized by the S/390 hardware
1351 and would fall back to a slower implementation. Allowing overlapping
1352 operations would lead to slow code but not to wrong code. Therefore we are
1353 somewhat optimistic if we cannot prove that the memory blocks are
1355 That's why we return false here although this may accept operations on
1356 overlapping memory areas. */
1357 if (!addr_delta
|| GET_CODE (addr_delta
) != CONST_INT
)
1360 delta
= INTVAL (addr_delta
);
1363 || (delta
> 0 && delta
< size
)
1364 || (delta
< 0 && -delta
< size
))
1370 /* Check whether the address of memory reference MEM2 equals exactly
1371 the address of memory reference MEM1 plus DELTA. Return true if
1372 we can prove this to be the case, false otherwise. */
1375 s390_offset_p (rtx mem1
, rtx mem2
, rtx delta
)
1377 rtx addr1
, addr2
, addr_delta
;
1379 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
1382 addr1
= XEXP (mem1
, 0);
1383 addr2
= XEXP (mem2
, 0);
1385 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
1386 if (!addr_delta
|| !rtx_equal_p (addr_delta
, delta
))
1392 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1395 s390_expand_logical_operator (enum rtx_code code
, enum machine_mode mode
,
1398 enum machine_mode wmode
= mode
;
1399 rtx dst
= operands
[0];
1400 rtx src1
= operands
[1];
1401 rtx src2
= operands
[2];
1404 /* If we cannot handle the operation directly, use a temp register. */
1405 if (!s390_logical_operator_ok_p (operands
))
1406 dst
= gen_reg_rtx (mode
);
1408 /* QImode and HImode patterns make sense only if we have a destination
1409 in memory. Otherwise perform the operation in SImode. */
1410 if ((mode
== QImode
|| mode
== HImode
) && GET_CODE (dst
) != MEM
)
1413 /* Widen operands if required. */
1416 if (GET_CODE (dst
) == SUBREG
1417 && (tem
= simplify_subreg (wmode
, dst
, mode
, 0)) != 0)
1419 else if (REG_P (dst
))
1420 dst
= gen_rtx_SUBREG (wmode
, dst
, 0);
1422 dst
= gen_reg_rtx (wmode
);
1424 if (GET_CODE (src1
) == SUBREG
1425 && (tem
= simplify_subreg (wmode
, src1
, mode
, 0)) != 0)
1427 else if (GET_MODE (src1
) != VOIDmode
)
1428 src1
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src1
), 0);
1430 if (GET_CODE (src2
) == SUBREG
1431 && (tem
= simplify_subreg (wmode
, src2
, mode
, 0)) != 0)
1433 else if (GET_MODE (src2
) != VOIDmode
)
1434 src2
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src2
), 0);
1437 /* Emit the instruction. */
1438 op
= gen_rtx_SET (VOIDmode
, dst
, gen_rtx_fmt_ee (code
, wmode
, src1
, src2
));
1439 clob
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
1440 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clob
)));
1442 /* Fix up the destination if needed. */
1443 if (dst
!= operands
[0])
1444 emit_move_insn (operands
[0], gen_lowpart (mode
, dst
));
1447 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1450 s390_logical_operator_ok_p (rtx
*operands
)
1452 /* If the destination operand is in memory, it needs to coincide
1453 with one of the source operands. After reload, it has to be
1454 the first source operand. */
1455 if (GET_CODE (operands
[0]) == MEM
)
1456 return rtx_equal_p (operands
[0], operands
[1])
1457 || (!reload_completed
&& rtx_equal_p (operands
[0], operands
[2]));
1462 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1463 operand IMMOP to switch from SS to SI type instructions. */
1466 s390_narrow_logical_operator (enum rtx_code code
, rtx
*memop
, rtx
*immop
)
1468 int def
= code
== AND
? -1 : 0;
1472 gcc_assert (GET_CODE (*memop
) == MEM
);
1473 gcc_assert (!MEM_VOLATILE_P (*memop
));
1475 mask
= s390_extract_part (*immop
, QImode
, def
);
1476 part
= s390_single_part (*immop
, GET_MODE (*memop
), QImode
, def
);
1477 gcc_assert (part
>= 0);
1479 *memop
= adjust_address (*memop
, QImode
, part
);
1480 *immop
= gen_int_mode (mask
, QImode
);
1484 /* How to allocate a 'struct machine_function'. */
1486 static struct machine_function
*
1487 s390_init_machine_status (void)
1489 return ggc_alloc_cleared_machine_function ();
1492 /* Change optimizations to be performed, depending on the
1493 optimization level. */
1495 static const struct default_options s390_option_optimization_table
[] =
1497 { OPT_LEVELS_1_PLUS
, OPT_fomit_frame_pointer
, NULL
, 1 },
1499 /* ??? There are apparently still problems with -fcaller-saves. */
1500 { OPT_LEVELS_ALL
, OPT_fcaller_saves
, NULL
, 0 },
1502 /* Use MVCLE instructions to decrease code size if requested. */
1503 { OPT_LEVELS_SIZE
, OPT_mmvcle
, NULL
, 1 },
1505 { OPT_LEVELS_NONE
, 0, NULL
, 0 }
1508 /* Implement TARGET_OPTION_INIT_STRUCT. */
1511 s390_option_init_struct (struct gcc_options
*opts
)
1513 /* By default, always emit DWARF-2 unwind info. This allows debugging
1514 without maintaining a stack frame back-chain. */
1515 opts
->x_flag_asynchronous_unwind_tables
= 1;
1518 /* Return true if ARG is the name of a processor. Set *TYPE and *FLAGS
1519 to the associated processor_type and processor_flags if so. */
1522 s390_handle_arch_option (const char *arg
,
1523 enum processor_type
*type
,
1528 const char *const name
; /* processor name or nickname. */
1529 const enum processor_type processor
;
1530 const int flags
; /* From enum processor_flags. */
1532 const processor_alias_table
[] =
1534 {"g5", PROCESSOR_9672_G5
, PF_IEEE_FLOAT
},
1535 {"g6", PROCESSOR_9672_G6
, PF_IEEE_FLOAT
},
1536 {"z900", PROCESSOR_2064_Z900
, PF_IEEE_FLOAT
| PF_ZARCH
},
1537 {"z990", PROCESSOR_2084_Z990
, PF_IEEE_FLOAT
| PF_ZARCH
1538 | PF_LONG_DISPLACEMENT
},
1539 {"z9-109", PROCESSOR_2094_Z9_109
, PF_IEEE_FLOAT
| PF_ZARCH
1540 | PF_LONG_DISPLACEMENT
| PF_EXTIMM
},
1541 {"z9-ec", PROCESSOR_2094_Z9_109
, PF_IEEE_FLOAT
| PF_ZARCH
1542 | PF_LONG_DISPLACEMENT
| PF_EXTIMM
| PF_DFP
},
1543 {"z10", PROCESSOR_2097_Z10
, PF_IEEE_FLOAT
| PF_ZARCH
1544 | PF_LONG_DISPLACEMENT
| PF_EXTIMM
| PF_DFP
| PF_Z10
},
1545 {"z196", PROCESSOR_2817_Z196
, PF_IEEE_FLOAT
| PF_ZARCH
1546 | PF_LONG_DISPLACEMENT
| PF_EXTIMM
| PF_DFP
| PF_Z10
| PF_Z196
},
1550 for (i
= 0; i
< ARRAY_SIZE (processor_alias_table
); i
++)
1551 if (strcmp (arg
, processor_alias_table
[i
].name
) == 0)
1553 *type
= processor_alias_table
[i
].processor
;
1554 *flags
= processor_alias_table
[i
].flags
;
1558 *type
= PROCESSOR_max
;
1563 /* Implement TARGET_HANDLE_OPTION. */
1566 s390_handle_option (size_t code
, const char *arg
, int value ATTRIBUTE_UNUSED
)
1571 return s390_handle_arch_option (arg
, &s390_arch
, &s390_arch_flags
);
1573 case OPT_mstack_guard_
:
1574 if (sscanf (arg
, HOST_WIDE_INT_PRINT_DEC
, &s390_stack_guard
) != 1)
1576 if (exact_log2 (s390_stack_guard
) == -1)
1577 error ("stack guard value must be an exact power of 2");
1580 case OPT_mstack_size_
:
1581 if (sscanf (arg
, HOST_WIDE_INT_PRINT_DEC
, &s390_stack_size
) != 1)
1583 if (exact_log2 (s390_stack_size
) == -1)
1584 error ("stack size must be an exact power of 2");
1588 return s390_handle_arch_option (arg
, &s390_tune
, &s390_tune_flags
);
1590 case OPT_mwarn_framesize_
:
1591 return sscanf (arg
, HOST_WIDE_INT_PRINT_DEC
, &s390_warn_framesize
) == 1;
1599 s390_option_override (void)
1601 /* Set up function hooks. */
1602 init_machine_status
= s390_init_machine_status
;
1604 /* Architecture mode defaults according to ABI. */
1605 if (!(target_flags_explicit
& MASK_ZARCH
))
1608 target_flags
|= MASK_ZARCH
;
1610 target_flags
&= ~MASK_ZARCH
;
1613 /* Determine processor architectural level. */
1614 if (!s390_arch_string
)
1616 s390_arch_string
= TARGET_ZARCH
? "z900" : "g5";
1617 s390_handle_arch_option (s390_arch_string
, &s390_arch
, &s390_arch_flags
);
1620 /* This check is triggered when the user specified a wrong -march=
1621 string and prevents subsequent error messages from being
1623 if (s390_arch
== PROCESSOR_max
)
1626 /* Determine processor to tune for. */
1627 if (s390_tune
== PROCESSOR_max
)
1629 s390_tune
= s390_arch
;
1630 s390_tune_flags
= s390_arch_flags
;
1633 /* Sanity checks. */
1634 if (TARGET_ZARCH
&& !TARGET_CPU_ZARCH
)
1635 error ("z/Architecture mode not supported on %s", s390_arch_string
);
1636 if (TARGET_64BIT
&& !TARGET_ZARCH
)
1637 error ("64-bit ABI not supported in ESA/390 mode");
1639 if (TARGET_HARD_DFP
&& !TARGET_DFP
)
1641 if (target_flags_explicit
& MASK_HARD_DFP
)
1643 if (!TARGET_CPU_DFP
)
1644 error ("hardware decimal floating point instructions"
1645 " not available on %s", s390_arch_string
);
1647 error ("hardware decimal floating point instructions"
1648 " not available in ESA/390 mode");
1651 target_flags
&= ~MASK_HARD_DFP
;
1654 if ((target_flags_explicit
& MASK_SOFT_FLOAT
) && TARGET_SOFT_FLOAT
)
1656 if ((target_flags_explicit
& MASK_HARD_DFP
) && TARGET_HARD_DFP
)
1657 error ("-mhard-dfp can%'t be used in conjunction with -msoft-float");
1659 target_flags
&= ~MASK_HARD_DFP
;
1662 /* Set processor cost function. */
1665 case PROCESSOR_2084_Z990
:
1666 s390_cost
= &z990_cost
;
1668 case PROCESSOR_2094_Z9_109
:
1669 s390_cost
= &z9_109_cost
;
1671 case PROCESSOR_2097_Z10
:
1672 s390_cost
= &z10_cost
;
1673 case PROCESSOR_2817_Z196
:
1674 s390_cost
= &z196_cost
;
1677 s390_cost
= &z900_cost
;
1680 if (TARGET_BACKCHAIN
&& TARGET_PACKED_STACK
&& TARGET_HARD_FLOAT
)
1681 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1684 if (s390_stack_size
)
1686 if (s390_stack_guard
>= s390_stack_size
)
1687 error ("stack size must be greater than the stack guard value");
1688 else if (s390_stack_size
> 1 << 16)
1689 error ("stack size must not be greater than 64k");
1691 else if (s390_stack_guard
)
1692 error ("-mstack-guard implies use of -mstack-size");
1694 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1695 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
1696 target_flags
|= MASK_LONG_DOUBLE_128
;
1699 if (s390_tune
== PROCESSOR_2097_Z10
1700 || s390_tune
== PROCESSOR_2817_Z196
)
1702 maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS
, 100,
1703 global_options
.x_param_values
,
1704 global_options_set
.x_param_values
);
1705 maybe_set_param_value (PARAM_MAX_UNROLL_TIMES
, 32,
1706 global_options
.x_param_values
,
1707 global_options_set
.x_param_values
);
1708 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS
, 2000,
1709 global_options
.x_param_values
,
1710 global_options_set
.x_param_values
);
1711 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES
, 64,
1712 global_options
.x_param_values
,
1713 global_options_set
.x_param_values
);
1716 maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH
, 256,
1717 global_options
.x_param_values
,
1718 global_options_set
.x_param_values
);
1719 /* values for loop prefetching */
1720 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
, 256,
1721 global_options
.x_param_values
,
1722 global_options_set
.x_param_values
);
1723 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, 128,
1724 global_options
.x_param_values
,
1725 global_options_set
.x_param_values
);
1726 /* s390 has more than 2 levels and the size is much larger. Since
1727 we are always running virtualized assume that we only get a small
1728 part of the caches above l1. */
1729 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, 1500,
1730 global_options
.x_param_values
,
1731 global_options_set
.x_param_values
);
1732 maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO
, 2,
1733 global_options
.x_param_values
,
1734 global_options_set
.x_param_values
);
1735 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
, 6,
1736 global_options
.x_param_values
,
1737 global_options_set
.x_param_values
);
1739 /* This cannot reside in s390_option_optimization_table since HAVE_prefetch
1740 requires the arch flags to be evaluated already. Since prefetching
1741 is beneficial on s390, we enable it if available. */
1742 if (flag_prefetch_loop_arrays
< 0 && HAVE_prefetch
&& optimize
>= 3)
1743 flag_prefetch_loop_arrays
= 1;
1746 /* Map for smallest class containing reg regno. */
1748 const enum reg_class regclass_map
[FIRST_PSEUDO_REGISTER
] =
1749 { GENERAL_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1750 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1751 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1752 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1753 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1754 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1755 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1756 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1757 ADDR_REGS
, CC_REGS
, ADDR_REGS
, ADDR_REGS
,
1758 ACCESS_REGS
, ACCESS_REGS
1761 /* Return attribute type of insn. */
1763 static enum attr_type
1764 s390_safe_attr_type (rtx insn
)
1766 if (recog_memoized (insn
) >= 0)
1767 return get_attr_type (insn
);
1772 /* Return true if DISP is a valid short displacement. */
1775 s390_short_displacement (rtx disp
)
1777 /* No displacement is OK. */
1781 /* Without the long displacement facility we don't need to
1782 distingiush between long and short displacement. */
1783 if (!TARGET_LONG_DISPLACEMENT
)
1786 /* Integer displacement in range. */
1787 if (GET_CODE (disp
) == CONST_INT
)
1788 return INTVAL (disp
) >= 0 && INTVAL (disp
) < 4096;
1790 /* GOT offset is not OK, the GOT can be large. */
1791 if (GET_CODE (disp
) == CONST
1792 && GET_CODE (XEXP (disp
, 0)) == UNSPEC
1793 && (XINT (XEXP (disp
, 0), 1) == UNSPEC_GOT
1794 || XINT (XEXP (disp
, 0), 1) == UNSPEC_GOTNTPOFF
))
1797 /* All other symbolic constants are literal pool references,
1798 which are OK as the literal pool must be small. */
1799 if (GET_CODE (disp
) == CONST
)
1805 /* Decompose a RTL expression ADDR for a memory address into
1806 its components, returned in OUT.
1808 Returns false if ADDR is not a valid memory address, true
1809 otherwise. If OUT is NULL, don't return the components,
1810 but check for validity only.
1812 Note: Only addresses in canonical form are recognized.
1813 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1814 canonical form so that they will be recognized. */
1817 s390_decompose_address (rtx addr
, struct s390_address
*out
)
1819 HOST_WIDE_INT offset
= 0;
1820 rtx base
= NULL_RTX
;
1821 rtx indx
= NULL_RTX
;
1822 rtx disp
= NULL_RTX
;
1824 bool pointer
= false;
1825 bool base_ptr
= false;
1826 bool indx_ptr
= false;
1827 bool literal_pool
= false;
1829 /* We may need to substitute the literal pool base register into the address
1830 below. However, at this point we do not know which register is going to
1831 be used as base, so we substitute the arg pointer register. This is going
1832 to be treated as holding a pointer below -- it shouldn't be used for any
1834 rtx fake_pool_base
= gen_rtx_REG (Pmode
, ARG_POINTER_REGNUM
);
1836 /* Decompose address into base + index + displacement. */
1838 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == UNSPEC
)
1841 else if (GET_CODE (addr
) == PLUS
)
1843 rtx op0
= XEXP (addr
, 0);
1844 rtx op1
= XEXP (addr
, 1);
1845 enum rtx_code code0
= GET_CODE (op0
);
1846 enum rtx_code code1
= GET_CODE (op1
);
1848 if (code0
== REG
|| code0
== UNSPEC
)
1850 if (code1
== REG
|| code1
== UNSPEC
)
1852 indx
= op0
; /* index + base */
1858 base
= op0
; /* base + displacement */
1863 else if (code0
== PLUS
)
1865 indx
= XEXP (op0
, 0); /* index + base + disp */
1866 base
= XEXP (op0
, 1);
1877 disp
= addr
; /* displacement */
1879 /* Extract integer part of displacement. */
1883 if (GET_CODE (disp
) == CONST_INT
)
1885 offset
= INTVAL (disp
);
1888 else if (GET_CODE (disp
) == CONST
1889 && GET_CODE (XEXP (disp
, 0)) == PLUS
1890 && GET_CODE (XEXP (XEXP (disp
, 0), 1)) == CONST_INT
)
1892 offset
= INTVAL (XEXP (XEXP (disp
, 0), 1));
1893 disp
= XEXP (XEXP (disp
, 0), 0);
1897 /* Strip off CONST here to avoid special case tests later. */
1898 if (disp
&& GET_CODE (disp
) == CONST
)
1899 disp
= XEXP (disp
, 0);
1901 /* We can convert literal pool addresses to
1902 displacements by basing them off the base register. */
1903 if (disp
&& GET_CODE (disp
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (disp
))
1905 /* Either base or index must be free to hold the base register. */
1907 base
= fake_pool_base
, literal_pool
= true;
1909 indx
= fake_pool_base
, literal_pool
= true;
1913 /* Mark up the displacement. */
1914 disp
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, disp
),
1915 UNSPEC_LTREL_OFFSET
);
1918 /* Validate base register. */
1921 if (GET_CODE (base
) == UNSPEC
)
1922 switch (XINT (base
, 1))
1926 disp
= gen_rtx_UNSPEC (Pmode
,
1927 gen_rtvec (1, XVECEXP (base
, 0, 0)),
1928 UNSPEC_LTREL_OFFSET
);
1932 base
= XVECEXP (base
, 0, 1);
1935 case UNSPEC_LTREL_BASE
:
1936 if (XVECLEN (base
, 0) == 1)
1937 base
= fake_pool_base
, literal_pool
= true;
1939 base
= XVECEXP (base
, 0, 1);
1947 || (GET_MODE (base
) != SImode
1948 && GET_MODE (base
) != Pmode
))
1951 if (REGNO (base
) == STACK_POINTER_REGNUM
1952 || REGNO (base
) == FRAME_POINTER_REGNUM
1953 || ((reload_completed
|| reload_in_progress
)
1954 && frame_pointer_needed
1955 && REGNO (base
) == HARD_FRAME_POINTER_REGNUM
)
1956 || REGNO (base
) == ARG_POINTER_REGNUM
1958 && REGNO (base
) == PIC_OFFSET_TABLE_REGNUM
))
1959 pointer
= base_ptr
= true;
1961 if ((reload_completed
|| reload_in_progress
)
1962 && base
== cfun
->machine
->base_reg
)
1963 pointer
= base_ptr
= literal_pool
= true;
1966 /* Validate index register. */
1969 if (GET_CODE (indx
) == UNSPEC
)
1970 switch (XINT (indx
, 1))
1974 disp
= gen_rtx_UNSPEC (Pmode
,
1975 gen_rtvec (1, XVECEXP (indx
, 0, 0)),
1976 UNSPEC_LTREL_OFFSET
);
1980 indx
= XVECEXP (indx
, 0, 1);
1983 case UNSPEC_LTREL_BASE
:
1984 if (XVECLEN (indx
, 0) == 1)
1985 indx
= fake_pool_base
, literal_pool
= true;
1987 indx
= XVECEXP (indx
, 0, 1);
1995 || (GET_MODE (indx
) != SImode
1996 && GET_MODE (indx
) != Pmode
))
1999 if (REGNO (indx
) == STACK_POINTER_REGNUM
2000 || REGNO (indx
) == FRAME_POINTER_REGNUM
2001 || ((reload_completed
|| reload_in_progress
)
2002 && frame_pointer_needed
2003 && REGNO (indx
) == HARD_FRAME_POINTER_REGNUM
)
2004 || REGNO (indx
) == ARG_POINTER_REGNUM
2006 && REGNO (indx
) == PIC_OFFSET_TABLE_REGNUM
))
2007 pointer
= indx_ptr
= true;
2009 if ((reload_completed
|| reload_in_progress
)
2010 && indx
== cfun
->machine
->base_reg
)
2011 pointer
= indx_ptr
= literal_pool
= true;
2014 /* Prefer to use pointer as base, not index. */
2015 if (base
&& indx
&& !base_ptr
2016 && (indx_ptr
|| (!REG_POINTER (base
) && REG_POINTER (indx
))))
2023 /* Validate displacement. */
2026 /* If virtual registers are involved, the displacement will change later
2027 anyway as the virtual registers get eliminated. This could make a
2028 valid displacement invalid, but it is more likely to make an invalid
2029 displacement valid, because we sometimes access the register save area
2030 via negative offsets to one of those registers.
2031 Thus we don't check the displacement for validity here. If after
2032 elimination the displacement turns out to be invalid after all,
2033 this is fixed up by reload in any case. */
2034 if (base
!= arg_pointer_rtx
2035 && indx
!= arg_pointer_rtx
2036 && base
!= return_address_pointer_rtx
2037 && indx
!= return_address_pointer_rtx
2038 && base
!= frame_pointer_rtx
2039 && indx
!= frame_pointer_rtx
2040 && base
!= virtual_stack_vars_rtx
2041 && indx
!= virtual_stack_vars_rtx
)
2042 if (!DISP_IN_RANGE (offset
))
2047 /* All the special cases are pointers. */
2050 /* In the small-PIC case, the linker converts @GOT
2051 and @GOTNTPOFF offsets to possible displacements. */
2052 if (GET_CODE (disp
) == UNSPEC
2053 && (XINT (disp
, 1) == UNSPEC_GOT
2054 || XINT (disp
, 1) == UNSPEC_GOTNTPOFF
)
2060 /* Accept pool label offsets. */
2061 else if (GET_CODE (disp
) == UNSPEC
2062 && XINT (disp
, 1) == UNSPEC_POOL_OFFSET
)
2065 /* Accept literal pool references. */
2066 else if (GET_CODE (disp
) == UNSPEC
2067 && XINT (disp
, 1) == UNSPEC_LTREL_OFFSET
)
2069 orig_disp
= gen_rtx_CONST (Pmode
, disp
);
2072 /* If we have an offset, make sure it does not
2073 exceed the size of the constant pool entry. */
2074 rtx sym
= XVECEXP (disp
, 0, 0);
2075 if (offset
>= GET_MODE_SIZE (get_pool_mode (sym
)))
2078 orig_disp
= plus_constant (orig_disp
, offset
);
2093 out
->disp
= orig_disp
;
2094 out
->pointer
= pointer
;
2095 out
->literal_pool
= literal_pool
;
2101 /* Decompose a RTL expression OP for a shift count into its components,
2102 and return the base register in BASE and the offset in OFFSET.
2104 Return true if OP is a valid shift count, false if not. */
2107 s390_decompose_shift_count (rtx op
, rtx
*base
, HOST_WIDE_INT
*offset
)
2109 HOST_WIDE_INT off
= 0;
2111 /* We can have an integer constant, an address register,
2112 or a sum of the two. */
2113 if (GET_CODE (op
) == CONST_INT
)
2118 if (op
&& GET_CODE (op
) == PLUS
&& GET_CODE (XEXP (op
, 1)) == CONST_INT
)
2120 off
= INTVAL (XEXP (op
, 1));
2123 while (op
&& GET_CODE (op
) == SUBREG
)
2124 op
= SUBREG_REG (op
);
2126 if (op
&& GET_CODE (op
) != REG
)
2138 /* Return true if CODE is a valid address without index. */
2141 s390_legitimate_address_without_index_p (rtx op
)
2143 struct s390_address addr
;
2145 if (!s390_decompose_address (XEXP (op
, 0), &addr
))
2154 /* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
2155 and return these parts in SYMREF and ADDEND. You can pass NULL in
2156 SYMREF and/or ADDEND if you are not interested in these values.
2157 Literal pool references are *not* considered symbol references. */
2160 s390_symref_operand_p (rtx addr
, rtx
*symref
, HOST_WIDE_INT
*addend
)
2162 HOST_WIDE_INT tmpaddend
= 0;
2164 if (GET_CODE (addr
) == CONST
)
2165 addr
= XEXP (addr
, 0);
2167 if (GET_CODE (addr
) == PLUS
)
2169 if (GET_CODE (XEXP (addr
, 0)) == SYMBOL_REF
2170 && !CONSTANT_POOL_ADDRESS_P (XEXP (addr
, 0))
2171 && CONST_INT_P (XEXP (addr
, 1)))
2173 tmpaddend
= INTVAL (XEXP (addr
, 1));
2174 addr
= XEXP (addr
, 0);
2180 if (GET_CODE (addr
) != SYMBOL_REF
|| CONSTANT_POOL_ADDRESS_P (addr
))
2186 *addend
= tmpaddend
;
2192 /* Return true if the address in OP is valid for constraint letter C
2193 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2194 pool MEMs should be accepted. Only the Q, R, S, T constraint
2195 letters are allowed for C. */
2198 s390_check_qrst_address (char c
, rtx op
, bool lit_pool_ok
)
2200 struct s390_address addr
;
2201 bool decomposed
= false;
2203 /* This check makes sure that no symbolic address (except literal
2204 pool references) are accepted by the R or T constraints. */
2205 if (s390_symref_operand_p (op
, NULL
, NULL
))
2208 /* Ensure literal pool references are only accepted if LIT_POOL_OK. */
2211 if (!s390_decompose_address (op
, &addr
))
2213 if (addr
.literal_pool
)
2220 case 'Q': /* no index short displacement */
2221 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
2225 if (!s390_short_displacement (addr
.disp
))
2229 case 'R': /* with index short displacement */
2230 if (TARGET_LONG_DISPLACEMENT
)
2232 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
2234 if (!s390_short_displacement (addr
.disp
))
2237 /* Any invalid address here will be fixed up by reload,
2238 so accept it for the most generic constraint. */
2241 case 'S': /* no index long displacement */
2242 if (!TARGET_LONG_DISPLACEMENT
)
2244 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
2248 if (s390_short_displacement (addr
.disp
))
2252 case 'T': /* with index long displacement */
2253 if (!TARGET_LONG_DISPLACEMENT
)
2255 /* Any invalid address here will be fixed up by reload,
2256 so accept it for the most generic constraint. */
2257 if ((decomposed
|| s390_decompose_address (op
, &addr
))
2258 && s390_short_displacement (addr
.disp
))
2268 /* Evaluates constraint strings described by the regular expression
2269 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2270 the constraint given in STR, or 0 else. */
2273 s390_mem_constraint (const char *str
, rtx op
)
2280 /* Check for offsettable variants of memory constraints. */
2281 if (!MEM_P (op
) || MEM_VOLATILE_P (op
))
2283 if ((reload_completed
|| reload_in_progress
)
2284 ? !offsettable_memref_p (op
) : !offsettable_nonstrict_memref_p (op
))
2286 return s390_check_qrst_address (str
[1], XEXP (op
, 0), true);
2288 /* Check for non-literal-pool variants of memory constraints. */
2291 return s390_check_qrst_address (str
[1], XEXP (op
, 0), false);
2296 if (GET_CODE (op
) != MEM
)
2298 return s390_check_qrst_address (c
, XEXP (op
, 0), true);
2300 return (s390_check_qrst_address ('Q', op
, true)
2301 || s390_check_qrst_address ('R', op
, true));
2303 return (s390_check_qrst_address ('S', op
, true)
2304 || s390_check_qrst_address ('T', op
, true));
2306 /* Simply check for the basic form of a shift count. Reload will
2307 take care of making sure we have a proper base register. */
2308 if (!s390_decompose_shift_count (op
, NULL
, NULL
))
2312 return s390_check_qrst_address (str
[1], op
, true);
2320 /* Evaluates constraint strings starting with letter O. Input
2321 parameter C is the second letter following the "O" in the constraint
2322 string. Returns 1 if VALUE meets the respective constraint and 0
2326 s390_O_constraint_str (const char c
, HOST_WIDE_INT value
)
2334 return trunc_int_for_mode (value
, SImode
) == value
;
2338 || s390_single_part (GEN_INT (value
), DImode
, SImode
, 0) == 1;
2341 return s390_single_part (GEN_INT (value
- 1), DImode
, SImode
, -1) == 1;
2349 /* Evaluates constraint strings starting with letter N. Parameter STR
2350 contains the letters following letter "N" in the constraint string.
2351 Returns true if VALUE matches the constraint. */
2354 s390_N_constraint_str (const char *str
, HOST_WIDE_INT value
)
2356 enum machine_mode mode
, part_mode
;
2358 int part
, part_goal
;
2364 part_goal
= str
[0] - '0';
2408 if (GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (part_mode
))
2411 part
= s390_single_part (GEN_INT (value
), mode
, part_mode
, def
);
2414 if (part_goal
!= -1 && part_goal
!= part
)
2421 /* Returns true if the input parameter VALUE is a float zero. */
2424 s390_float_const_zero_p (rtx value
)
2426 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
2427 && value
== CONST0_RTX (GET_MODE (value
)));
2431 /* Compute a (partial) cost for rtx X. Return true if the complete
2432 cost has been computed, and false if subexpressions should be
2433 scanned. In either case, *TOTAL contains the cost result.
2434 CODE contains GET_CODE (x), OUTER_CODE contains the code
2435 of the superexpression of x. */
2438 s390_rtx_costs (rtx x
, int code
, int outer_code
, int *total
,
2439 bool speed ATTRIBUTE_UNUSED
)
2462 *total
= COSTS_N_INSNS (1);
2467 /* Check for multiply and add. */
2468 if ((GET_MODE (x
) == DFmode
|| GET_MODE (x
) == SFmode
)
2469 && GET_CODE (XEXP (x
, 0)) == MULT
2470 && TARGET_HARD_FLOAT
&& TARGET_FUSED_MADD
)
2472 /* This is the multiply and add case. */
2473 if (GET_MODE (x
) == DFmode
)
2474 *total
= s390_cost
->madbr
;
2476 *total
= s390_cost
->maebr
;
2477 *total
+= (rtx_cost (XEXP (XEXP (x
, 0), 0), MULT
, speed
)
2478 + rtx_cost (XEXP (XEXP (x
, 0), 1), MULT
, speed
)
2479 + rtx_cost (XEXP (x
, 1), (enum rtx_code
) code
, speed
));
2480 return true; /* Do not do an additional recursive descent. */
2482 *total
= COSTS_N_INSNS (1);
2486 switch (GET_MODE (x
))
2490 rtx left
= XEXP (x
, 0);
2491 rtx right
= XEXP (x
, 1);
2492 if (GET_CODE (right
) == CONST_INT
2493 && CONST_OK_FOR_K (INTVAL (right
)))
2494 *total
= s390_cost
->mhi
;
2495 else if (GET_CODE (left
) == SIGN_EXTEND
)
2496 *total
= s390_cost
->mh
;
2498 *total
= s390_cost
->ms
; /* msr, ms, msy */
2503 rtx left
= XEXP (x
, 0);
2504 rtx right
= XEXP (x
, 1);
2507 if (GET_CODE (right
) == CONST_INT
2508 && CONST_OK_FOR_K (INTVAL (right
)))
2509 *total
= s390_cost
->mghi
;
2510 else if (GET_CODE (left
) == SIGN_EXTEND
)
2511 *total
= s390_cost
->msgf
;
2513 *total
= s390_cost
->msg
; /* msgr, msg */
2515 else /* TARGET_31BIT */
2517 if (GET_CODE (left
) == SIGN_EXTEND
2518 && GET_CODE (right
) == SIGN_EXTEND
)
2519 /* mulsidi case: mr, m */
2520 *total
= s390_cost
->m
;
2521 else if (GET_CODE (left
) == ZERO_EXTEND
2522 && GET_CODE (right
) == ZERO_EXTEND
2523 && TARGET_CPU_ZARCH
)
2524 /* umulsidi case: ml, mlr */
2525 *total
= s390_cost
->ml
;
2527 /* Complex calculation is required. */
2528 *total
= COSTS_N_INSNS (40);
2534 *total
= s390_cost
->mult_df
;
2537 *total
= s390_cost
->mxbr
;
2546 if (GET_MODE (x
) == TImode
) /* 128 bit division */
2547 *total
= s390_cost
->dlgr
;
2548 else if (GET_MODE (x
) == DImode
)
2550 rtx right
= XEXP (x
, 1);
2551 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
2552 *total
= s390_cost
->dlr
;
2553 else /* 64 by 64 bit division */
2554 *total
= s390_cost
->dlgr
;
2556 else if (GET_MODE (x
) == SImode
) /* 32 bit division */
2557 *total
= s390_cost
->dlr
;
2562 if (GET_MODE (x
) == DImode
)
2564 rtx right
= XEXP (x
, 1);
2565 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
2567 *total
= s390_cost
->dsgfr
;
2569 *total
= s390_cost
->dr
;
2570 else /* 64 by 64 bit division */
2571 *total
= s390_cost
->dsgr
;
2573 else if (GET_MODE (x
) == SImode
) /* 32 bit division */
2574 *total
= s390_cost
->dlr
;
2575 else if (GET_MODE (x
) == SFmode
)
2577 *total
= s390_cost
->debr
;
2579 else if (GET_MODE (x
) == DFmode
)
2581 *total
= s390_cost
->ddbr
;
2583 else if (GET_MODE (x
) == TFmode
)
2585 *total
= s390_cost
->dxbr
;
2590 if (GET_MODE (x
) == SFmode
)
2591 *total
= s390_cost
->sqebr
;
2592 else if (GET_MODE (x
) == DFmode
)
2593 *total
= s390_cost
->sqdbr
;
2595 *total
= s390_cost
->sqxbr
;
2600 if (outer_code
== MULT
|| outer_code
== DIV
|| outer_code
== MOD
2601 || outer_code
== PLUS
|| outer_code
== MINUS
2602 || outer_code
== COMPARE
)
2607 *total
= COSTS_N_INSNS (1);
2608 if (GET_CODE (XEXP (x
, 0)) == AND
2609 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2610 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
2612 rtx op0
= XEXP (XEXP (x
, 0), 0);
2613 rtx op1
= XEXP (XEXP (x
, 0), 1);
2614 rtx op2
= XEXP (x
, 1);
2616 if (memory_operand (op0
, GET_MODE (op0
))
2617 && s390_tm_ccmode (op1
, op2
, 0) != VOIDmode
)
2619 if (register_operand (op0
, GET_MODE (op0
))
2620 && s390_tm_ccmode (op1
, op2
, 1) != VOIDmode
)
2630 /* Return the cost of an address rtx ADDR. */
2633 s390_address_cost (rtx addr
, bool speed ATTRIBUTE_UNUSED
)
2635 struct s390_address ad
;
2636 if (!s390_decompose_address (addr
, &ad
))
2639 return ad
.indx
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2642 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2643 otherwise return 0. */
2646 tls_symbolic_operand (rtx op
)
2648 if (GET_CODE (op
) != SYMBOL_REF
)
2650 return SYMBOL_REF_TLS_MODEL (op
);
2653 /* Split DImode access register reference REG (on 64-bit) into its constituent
2654 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2655 gen_highpart cannot be used as they assume all registers are word-sized,
2656 while our access registers have only half that size. */
2659 s390_split_access_reg (rtx reg
, rtx
*lo
, rtx
*hi
)
2661 gcc_assert (TARGET_64BIT
);
2662 gcc_assert (ACCESS_REG_P (reg
));
2663 gcc_assert (GET_MODE (reg
) == DImode
);
2664 gcc_assert (!(REGNO (reg
) & 1));
2666 *lo
= gen_rtx_REG (SImode
, REGNO (reg
) + 1);
2667 *hi
= gen_rtx_REG (SImode
, REGNO (reg
));
2670 /* Return true if OP contains a symbol reference */
2673 symbolic_reference_mentioned_p (rtx op
)
2678 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
2681 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
2682 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
2688 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
2689 if (symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
2693 else if (fmt
[i
] == 'e' && symbolic_reference_mentioned_p (XEXP (op
, i
)))
2700 /* Return true if OP contains a reference to a thread-local symbol. */
2703 tls_symbolic_reference_mentioned_p (rtx op
)
2708 if (GET_CODE (op
) == SYMBOL_REF
)
2709 return tls_symbolic_operand (op
);
2711 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
2712 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
2718 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
2719 if (tls_symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
2723 else if (fmt
[i
] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op
, i
)))
2731 /* Return true if OP is a legitimate general operand when
2732 generating PIC code. It is given that flag_pic is on
2733 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2736 legitimate_pic_operand_p (rtx op
)
2738 /* Accept all non-symbolic constants. */
2739 if (!SYMBOLIC_CONST (op
))
2742 /* Reject everything else; must be handled
2743 via emit_symbolic_move. */
2747 /* Returns true if the constant value OP is a legitimate general operand.
2748 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2751 legitimate_constant_p (rtx op
)
2753 /* Accept all non-symbolic constants. */
2754 if (!SYMBOLIC_CONST (op
))
2757 /* Accept immediate LARL operands. */
2758 if (TARGET_CPU_ZARCH
&& larl_operand (op
, VOIDmode
))
2761 /* Thread-local symbols are never legal constants. This is
2762 so that emit_call knows that computing such addresses
2763 might require a function call. */
2764 if (TLS_SYMBOLIC_CONST (op
))
2767 /* In the PIC case, symbolic constants must *not* be
2768 forced into the literal pool. We accept them here,
2769 so that they will be handled by emit_symbolic_move. */
2773 /* All remaining non-PIC symbolic constants are
2774 forced into the literal pool. */
2778 /* Determine if it's legal to put X into the constant pool. This
2779 is not possible if X contains the address of a symbol that is
2780 not constant (TLS) or not known at final link time (PIC). */
2783 s390_cannot_force_const_mem (rtx x
)
2785 switch (GET_CODE (x
))
2789 /* Accept all non-symbolic constants. */
2793 /* Labels are OK iff we are non-PIC. */
2794 return flag_pic
!= 0;
2797 /* 'Naked' TLS symbol references are never OK,
2798 non-TLS symbols are OK iff we are non-PIC. */
2799 if (tls_symbolic_operand (x
))
2802 return flag_pic
!= 0;
2805 return s390_cannot_force_const_mem (XEXP (x
, 0));
2808 return s390_cannot_force_const_mem (XEXP (x
, 0))
2809 || s390_cannot_force_const_mem (XEXP (x
, 1));
2812 switch (XINT (x
, 1))
2814 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2815 case UNSPEC_LTREL_OFFSET
:
2823 case UNSPEC_GOTNTPOFF
:
2824 case UNSPEC_INDNTPOFF
:
2827 /* If the literal pool shares the code section, be put
2828 execute template placeholders into the pool as well. */
2830 return TARGET_CPU_ZARCH
;
2842 /* Returns true if the constant value OP is a legitimate general
2843 operand during and after reload. The difference to
2844 legitimate_constant_p is that this function will not accept
2845 a constant that would need to be forced to the literal pool
2846 before it can be used as operand.
2847 This function accepts all constants which can be loaded directly
2851 legitimate_reload_constant_p (rtx op
)
2853 /* Accept la(y) operands. */
2854 if (GET_CODE (op
) == CONST_INT
2855 && DISP_IN_RANGE (INTVAL (op
)))
2858 /* Accept l(g)hi/l(g)fi operands. */
2859 if (GET_CODE (op
) == CONST_INT
2860 && (CONST_OK_FOR_K (INTVAL (op
)) || CONST_OK_FOR_Os (INTVAL (op
))))
2863 /* Accept lliXX operands. */
2865 && GET_CODE (op
) == CONST_INT
2866 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
2867 && s390_single_part (op
, word_mode
, HImode
, 0) >= 0)
2871 && GET_CODE (op
) == CONST_INT
2872 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
2873 && s390_single_part (op
, word_mode
, SImode
, 0) >= 0)
2876 /* Accept larl operands. */
2877 if (TARGET_CPU_ZARCH
2878 && larl_operand (op
, VOIDmode
))
2881 /* Accept floating-point zero operands that fit into a single GPR. */
2882 if (GET_CODE (op
) == CONST_DOUBLE
2883 && s390_float_const_zero_p (op
)
2884 && GET_MODE_SIZE (GET_MODE (op
)) <= UNITS_PER_WORD
)
2887 /* Accept double-word operands that can be split. */
2888 if (GET_CODE (op
) == CONST_INT
2889 && trunc_int_for_mode (INTVAL (op
), word_mode
) != INTVAL (op
))
2891 enum machine_mode dword_mode
= word_mode
== SImode
? DImode
: TImode
;
2892 rtx hi
= operand_subword (op
, 0, 0, dword_mode
);
2893 rtx lo
= operand_subword (op
, 1, 0, dword_mode
);
2894 return legitimate_reload_constant_p (hi
)
2895 && legitimate_reload_constant_p (lo
);
2898 /* Everything else cannot be handled without reload. */
2902 /* Returns true if the constant value OP is a legitimate fp operand
2903 during and after reload.
2904 This function accepts all constants which can be loaded directly
2908 legitimate_reload_fp_constant_p (rtx op
)
2910 /* Accept floating-point zero operands if the load zero instruction
2913 && GET_CODE (op
) == CONST_DOUBLE
2914 && s390_float_const_zero_p (op
))
2920 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2921 return the class of reg to actually use. */
2924 s390_preferred_reload_class (rtx op
, enum reg_class rclass
)
2926 switch (GET_CODE (op
))
2928 /* Constants we cannot reload into general registers
2929 must be forced into the literal pool. */
2932 if (reg_class_subset_p (GENERAL_REGS
, rclass
)
2933 && legitimate_reload_constant_p (op
))
2934 return GENERAL_REGS
;
2935 else if (reg_class_subset_p (ADDR_REGS
, rclass
)
2936 && legitimate_reload_constant_p (op
))
2938 else if (reg_class_subset_p (FP_REGS
, rclass
)
2939 && legitimate_reload_fp_constant_p (op
))
2943 /* If a symbolic constant or a PLUS is reloaded,
2944 it is most likely being used as an address, so
2945 prefer ADDR_REGS. If 'class' is not a superset
2946 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2951 if (reg_class_subset_p (ADDR_REGS
, rclass
))
2963 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2964 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2968 s390_check_symref_alignment (rtx addr
, HOST_WIDE_INT alignment
)
2970 HOST_WIDE_INT addend
;
2973 if (!s390_symref_operand_p (addr
, &symref
, &addend
))
2976 return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref
)
2977 && !(addend
& (alignment
- 1)));
2980 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
2981 operand SCRATCH is used to reload the even part of the address and
2985 s390_reload_larl_operand (rtx reg
, rtx addr
, rtx scratch
)
2987 HOST_WIDE_INT addend
;
2990 if (!s390_symref_operand_p (addr
, &symref
, &addend
))
2994 /* Easy case. The addend is even so larl will do fine. */
2995 emit_move_insn (reg
, addr
);
2998 /* We can leave the scratch register untouched if the target
2999 register is a valid base register. */
3000 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
3001 && REGNO_REG_CLASS (REGNO (reg
)) == ADDR_REGS
)
3004 gcc_assert (REGNO (scratch
) < FIRST_PSEUDO_REGISTER
);
3005 gcc_assert (REGNO_REG_CLASS (REGNO (scratch
)) == ADDR_REGS
);
3008 emit_move_insn (scratch
,
3009 gen_rtx_CONST (Pmode
,
3010 gen_rtx_PLUS (Pmode
, symref
,
3011 GEN_INT (addend
- 1))));
3013 emit_move_insn (scratch
, symref
);
3015 /* Increment the address using la in order to avoid clobbering cc. */
3016 emit_move_insn (reg
, gen_rtx_PLUS (Pmode
, scratch
, const1_rtx
));
3020 /* Generate what is necessary to move between REG and MEM using
3021 SCRATCH. The direction is given by TOMEM. */
3024 s390_reload_symref_address (rtx reg
, rtx mem
, rtx scratch
, bool tomem
)
3026 /* Reload might have pulled a constant out of the literal pool.
3027 Force it back in. */
3028 if (CONST_INT_P (mem
) || GET_CODE (mem
) == CONST_DOUBLE
3029 || GET_CODE (mem
) == CONST
)
3030 mem
= force_const_mem (GET_MODE (reg
), mem
);
3032 gcc_assert (MEM_P (mem
));
3034 /* For a load from memory we can leave the scratch register
3035 untouched if the target register is a valid base register. */
3037 && REGNO (reg
) < FIRST_PSEUDO_REGISTER
3038 && REGNO_REG_CLASS (REGNO (reg
)) == ADDR_REGS
3039 && GET_MODE (reg
) == GET_MODE (scratch
))
3042 /* Load address into scratch register. Since we can't have a
3043 secondary reload for a secondary reload we have to cover the case
3044 where larl would need a secondary reload here as well. */
3045 s390_reload_larl_operand (scratch
, XEXP (mem
, 0), scratch
);
3047 /* Now we can use a standard load/store to do the move. */
3049 emit_move_insn (replace_equiv_address (mem
, scratch
), reg
);
3051 emit_move_insn (reg
, replace_equiv_address (mem
, scratch
));
3054 /* Inform reload about cases where moving X with a mode MODE to a register in
3055 RCLASS requires an extra scratch or immediate register. Return the class
3056 needed for the immediate register. */
3059 s390_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
3060 enum machine_mode mode
, secondary_reload_info
*sri
)
3062 enum reg_class rclass
= (enum reg_class
) rclass_i
;
3064 /* Intermediate register needed. */
3065 if (reg_classes_intersect_p (CC_REGS
, rclass
))
3066 return GENERAL_REGS
;
3070 /* On z10 several optimizer steps may generate larl operands with
3073 && s390_symref_operand_p (x
, NULL
, NULL
)
3075 && !s390_check_symref_alignment (x
, 2))
3076 sri
->icode
= ((mode
== DImode
) ? CODE_FOR_reloaddi_larl_odd_addend_z10
3077 : CODE_FOR_reloadsi_larl_odd_addend_z10
);
3079 /* On z10 we need a scratch register when moving QI, TI or floating
3080 point mode values from or to a memory location with a SYMBOL_REF
3081 or if the symref addend of a SI or DI move is not aligned to the
3082 width of the access. */
3084 && s390_symref_operand_p (XEXP (x
, 0), NULL
, NULL
)
3085 && (mode
== QImode
|| mode
== TImode
|| FLOAT_MODE_P (mode
)
3086 || (!TARGET_ZARCH
&& mode
== DImode
)
3087 || ((mode
== HImode
|| mode
== SImode
|| mode
== DImode
)
3088 && (!s390_check_symref_alignment (XEXP (x
, 0),
3089 GET_MODE_SIZE (mode
))))))
3091 #define __SECONDARY_RELOAD_CASE(M,m) \
3094 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
3095 CODE_FOR_reload##m##di_tomem_z10; \
3097 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
3098 CODE_FOR_reload##m##si_tomem_z10; \
3101 switch (GET_MODE (x
))
3103 __SECONDARY_RELOAD_CASE (QI
, qi
);
3104 __SECONDARY_RELOAD_CASE (HI
, hi
);
3105 __SECONDARY_RELOAD_CASE (SI
, si
);
3106 __SECONDARY_RELOAD_CASE (DI
, di
);
3107 __SECONDARY_RELOAD_CASE (TI
, ti
);
3108 __SECONDARY_RELOAD_CASE (SF
, sf
);
3109 __SECONDARY_RELOAD_CASE (DF
, df
);
3110 __SECONDARY_RELOAD_CASE (TF
, tf
);
3111 __SECONDARY_RELOAD_CASE (SD
, sd
);
3112 __SECONDARY_RELOAD_CASE (DD
, dd
);
3113 __SECONDARY_RELOAD_CASE (TD
, td
);
3118 #undef __SECONDARY_RELOAD_CASE
3122 /* We need a scratch register when loading a PLUS expression which
3123 is not a legitimate operand of the LOAD ADDRESS instruction. */
3124 if (in_p
&& s390_plus_operand (x
, mode
))
3125 sri
->icode
= (TARGET_64BIT
?
3126 CODE_FOR_reloaddi_plus
: CODE_FOR_reloadsi_plus
);
3128 /* Performing a multiword move from or to memory we have to make sure the
3129 second chunk in memory is addressable without causing a displacement
3130 overflow. If that would be the case we calculate the address in
3131 a scratch register. */
3133 && GET_CODE (XEXP (x
, 0)) == PLUS
3134 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3135 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x
, 0), 1))
3136 + GET_MODE_SIZE (mode
) - 1))
3138 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3139 in a s_operand address since we may fallback to lm/stm. So we only
3140 have to care about overflows in the b+i+d case. */
3141 if ((reg_classes_intersect_p (GENERAL_REGS
, rclass
)
3142 && s390_class_max_nregs (GENERAL_REGS
, mode
) > 1
3143 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
3144 /* For FP_REGS no lm/stm is available so this check is triggered
3145 for displacement overflows in b+i+d and b+d like addresses. */
3146 || (reg_classes_intersect_p (FP_REGS
, rclass
)
3147 && s390_class_max_nregs (FP_REGS
, mode
) > 1))
3150 sri
->icode
= (TARGET_64BIT
?
3151 CODE_FOR_reloaddi_nonoffmem_in
:
3152 CODE_FOR_reloadsi_nonoffmem_in
);
3154 sri
->icode
= (TARGET_64BIT
?
3155 CODE_FOR_reloaddi_nonoffmem_out
:
3156 CODE_FOR_reloadsi_nonoffmem_out
);
3160 /* A scratch address register is needed when a symbolic constant is
3161 copied to r0 compiling with -fPIC. In other cases the target
3162 register might be used as temporary (see legitimize_pic_address). */
3163 if (in_p
&& SYMBOLIC_CONST (x
) && flag_pic
== 2 && rclass
!= ADDR_REGS
)
3164 sri
->icode
= (TARGET_64BIT
?
3165 CODE_FOR_reloaddi_PIC_addr
:
3166 CODE_FOR_reloadsi_PIC_addr
);
3168 /* Either scratch or no register needed. */
3172 /* Generate code to load SRC, which is PLUS that is not a
3173 legitimate operand for the LA instruction, into TARGET.
3174 SCRATCH may be used as scratch register. */
3177 s390_expand_plus_operand (rtx target
, rtx src
,
3181 struct s390_address ad
;
3183 /* src must be a PLUS; get its two operands. */
3184 gcc_assert (GET_CODE (src
) == PLUS
);
3185 gcc_assert (GET_MODE (src
) == Pmode
);
3187 /* Check if any of the two operands is already scheduled
3188 for replacement by reload. This can happen e.g. when
3189 float registers occur in an address. */
3190 sum1
= find_replacement (&XEXP (src
, 0));
3191 sum2
= find_replacement (&XEXP (src
, 1));
3192 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
3194 /* If the address is already strictly valid, there's nothing to do. */
3195 if (!s390_decompose_address (src
, &ad
)
3196 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
3197 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
3199 /* Otherwise, one of the operands cannot be an address register;
3200 we reload its value into the scratch register. */
3201 if (true_regnum (sum1
) < 1 || true_regnum (sum1
) > 15)
3203 emit_move_insn (scratch
, sum1
);
3206 if (true_regnum (sum2
) < 1 || true_regnum (sum2
) > 15)
3208 emit_move_insn (scratch
, sum2
);
3212 /* According to the way these invalid addresses are generated
3213 in reload.c, it should never happen (at least on s390) that
3214 *neither* of the PLUS components, after find_replacements
3215 was applied, is an address register. */
3216 if (sum1
== scratch
&& sum2
== scratch
)
3222 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
3225 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3226 is only ever performed on addresses, so we can mark the
3227 sum as legitimate for LA in any case. */
3228 s390_load_address (target
, src
);
3232 /* Return true if ADDR is a valid memory address.
3233 STRICT specifies whether strict register checking applies. */
3236 s390_legitimate_address_p (enum machine_mode mode
, rtx addr
, bool strict
)
3238 struct s390_address ad
;
3241 && larl_operand (addr
, VOIDmode
)
3242 && (mode
== VOIDmode
3243 || s390_check_symref_alignment (addr
, GET_MODE_SIZE (mode
))))
3246 if (!s390_decompose_address (addr
, &ad
))
3251 if (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
3254 if (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
)))
3260 && !(REGNO (ad
.base
) >= FIRST_PSEUDO_REGISTER
3261 || REGNO_REG_CLASS (REGNO (ad
.base
)) == ADDR_REGS
))
3265 && !(REGNO (ad
.indx
) >= FIRST_PSEUDO_REGISTER
3266 || REGNO_REG_CLASS (REGNO (ad
.indx
)) == ADDR_REGS
))
3272 /* Return true if OP is a valid operand for the LA instruction.
3273 In 31-bit, we need to prove that the result is used as an
3274 address, as LA performs only a 31-bit addition. */
3277 legitimate_la_operand_p (rtx op
)
3279 struct s390_address addr
;
3280 if (!s390_decompose_address (op
, &addr
))
3283 return (TARGET_64BIT
|| addr
.pointer
);
3286 /* Return true if it is valid *and* preferable to use LA to
3287 compute the sum of OP1 and OP2. */
3290 preferred_la_operand_p (rtx op1
, rtx op2
)
3292 struct s390_address addr
;
3294 if (op2
!= const0_rtx
)
3295 op1
= gen_rtx_PLUS (Pmode
, op1
, op2
);
3297 if (!s390_decompose_address (op1
, &addr
))
3299 if (addr
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (addr
.base
)))
3301 if (addr
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (addr
.indx
)))
3304 /* Avoid LA instructions with index register on z196; it is
3305 preferable to use regular add instructions when possible. */
3306 if (addr
.indx
&& s390_tune
== PROCESSOR_2817_Z196
)
3309 if (!TARGET_64BIT
&& !addr
.pointer
)
3315 if ((addr
.base
&& REG_P (addr
.base
) && REG_POINTER (addr
.base
))
3316 || (addr
.indx
&& REG_P (addr
.indx
) && REG_POINTER (addr
.indx
)))
3322 /* Emit a forced load-address operation to load SRC into DST.
3323 This will use the LOAD ADDRESS instruction even in situations
3324 where legitimate_la_operand_p (SRC) returns false. */
3327 s390_load_address (rtx dst
, rtx src
)
3330 emit_move_insn (dst
, src
);
3332 emit_insn (gen_force_la_31 (dst
, src
));
3335 /* Return a legitimate reference for ORIG (an address) using the
3336 register REG. If REG is 0, a new pseudo is generated.
3338 There are two types of references that must be handled:
3340 1. Global data references must load the address from the GOT, via
3341 the PIC reg. An insn is emitted to do this load, and the reg is
3344 2. Static data references, constant pool addresses, and code labels
3345 compute the address as an offset from the GOT, whose base is in
3346 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3347 differentiate them from global data objects. The returned
3348 address is the PIC reg + an unspec constant.
3350 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3351 reg also appears in the address. */
3354 legitimize_pic_address (rtx orig
, rtx reg
)
3360 gcc_assert (!TLS_SYMBOLIC_CONST (addr
));
3362 if (GET_CODE (addr
) == LABEL_REF
3363 || (GET_CODE (addr
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (addr
)))
3365 /* This is a local symbol. */
3366 if (TARGET_CPU_ZARCH
&& larl_operand (addr
, VOIDmode
))
3368 /* Access local symbols PC-relative via LARL.
3369 This is the same as in the non-PIC case, so it is
3370 handled automatically ... */
3374 /* Access local symbols relative to the GOT. */
3376 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3378 if (reload_in_progress
|| reload_completed
)
3379 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3381 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTOFF
);
3382 addr
= gen_rtx_CONST (Pmode
, addr
);
3383 addr
= force_const_mem (Pmode
, addr
);
3384 emit_move_insn (temp
, addr
);
3386 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3389 s390_load_address (reg
, new_rtx
);
3394 else if (GET_CODE (addr
) == SYMBOL_REF
)
3397 reg
= gen_reg_rtx (Pmode
);
3401 /* Assume GOT offset < 4k. This is handled the same way
3402 in both 31- and 64-bit code (@GOT). */
3404 if (reload_in_progress
|| reload_completed
)
3405 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3407 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
3408 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3409 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new_rtx
);
3410 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3411 emit_move_insn (reg
, new_rtx
);
3414 else if (TARGET_CPU_ZARCH
)
3416 /* If the GOT offset might be >= 4k, we determine the position
3417 of the GOT entry via a PC-relative LARL (@GOTENT). */
3419 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3421 gcc_assert (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
3422 || REGNO_REG_CLASS (REGNO (temp
)) == ADDR_REGS
);
3424 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTENT
);
3425 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3426 emit_move_insn (temp
, new_rtx
);
3428 new_rtx
= gen_const_mem (Pmode
, temp
);
3429 emit_move_insn (reg
, new_rtx
);
3434 /* If the GOT offset might be >= 4k, we have to load it
3435 from the literal pool (@GOT). */
3437 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3439 gcc_assert (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
3440 || REGNO_REG_CLASS (REGNO (temp
)) == ADDR_REGS
);
3442 if (reload_in_progress
|| reload_completed
)
3443 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3445 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
3446 addr
= gen_rtx_CONST (Pmode
, addr
);
3447 addr
= force_const_mem (Pmode
, addr
);
3448 emit_move_insn (temp
, addr
);
3450 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3451 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3452 emit_move_insn (reg
, new_rtx
);
3458 if (GET_CODE (addr
) == CONST
)
3460 addr
= XEXP (addr
, 0);
3461 if (GET_CODE (addr
) == UNSPEC
)
3463 gcc_assert (XVECLEN (addr
, 0) == 1);
3464 switch (XINT (addr
, 1))
3466 /* If someone moved a GOT-relative UNSPEC
3467 out of the literal pool, force them back in. */
3470 new_rtx
= force_const_mem (Pmode
, orig
);
3473 /* @GOT is OK as is if small. */
3476 new_rtx
= force_const_mem (Pmode
, orig
);
3479 /* @GOTENT is OK as is. */
3483 /* @PLT is OK as is on 64-bit, must be converted to
3484 GOT-relative @PLTOFF on 31-bit. */
3486 if (!TARGET_CPU_ZARCH
)
3488 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3490 if (reload_in_progress
|| reload_completed
)
3491 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3493 addr
= XVECEXP (addr
, 0, 0);
3494 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
),
3496 addr
= gen_rtx_CONST (Pmode
, addr
);
3497 addr
= force_const_mem (Pmode
, addr
);
3498 emit_move_insn (temp
, addr
);
3500 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3503 s390_load_address (reg
, new_rtx
);
3509 /* Everything else cannot happen. */
3515 gcc_assert (GET_CODE (addr
) == PLUS
);
3517 if (GET_CODE (addr
) == PLUS
)
3519 rtx op0
= XEXP (addr
, 0), op1
= XEXP (addr
, 1);
3521 gcc_assert (!TLS_SYMBOLIC_CONST (op0
));
3522 gcc_assert (!TLS_SYMBOLIC_CONST (op1
));
3524 /* Check first to see if this is a constant offset
3525 from a local symbol reference. */
3526 if ((GET_CODE (op0
) == LABEL_REF
3527 || (GET_CODE (op0
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op0
)))
3528 && GET_CODE (op1
) == CONST_INT
)
3530 if (TARGET_CPU_ZARCH
3531 && larl_operand (op0
, VOIDmode
)
3532 && INTVAL (op1
) < (HOST_WIDE_INT
)1 << 31
3533 && INTVAL (op1
) >= -((HOST_WIDE_INT
)1 << 31))
3535 if (INTVAL (op1
) & 1)
3537 /* LARL can't handle odd offsets, so emit a
3538 pair of LARL and LA. */
3539 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3541 if (!DISP_IN_RANGE (INTVAL (op1
)))
3543 HOST_WIDE_INT even
= INTVAL (op1
) - 1;
3544 op0
= gen_rtx_PLUS (Pmode
, op0
, GEN_INT (even
));
3545 op0
= gen_rtx_CONST (Pmode
, op0
);
3549 emit_move_insn (temp
, op0
);
3550 new_rtx
= gen_rtx_PLUS (Pmode
, temp
, op1
);
3554 s390_load_address (reg
, new_rtx
);
3560 /* If the offset is even, we can just use LARL.
3561 This will happen automatically. */
3566 /* Access local symbols relative to the GOT. */
3568 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3570 if (reload_in_progress
|| reload_completed
)
3571 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3573 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op0
),
3575 addr
= gen_rtx_PLUS (Pmode
, addr
, op1
);
3576 addr
= gen_rtx_CONST (Pmode
, addr
);
3577 addr
= force_const_mem (Pmode
, addr
);
3578 emit_move_insn (temp
, addr
);
3580 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3583 s390_load_address (reg
, new_rtx
);
3589 /* Now, check whether it is a GOT relative symbol plus offset
3590 that was pulled out of the literal pool. Force it back in. */
3592 else if (GET_CODE (op0
) == UNSPEC
3593 && GET_CODE (op1
) == CONST_INT
3594 && XINT (op0
, 1) == UNSPEC_GOTOFF
)
3596 gcc_assert (XVECLEN (op0
, 0) == 1);
3598 new_rtx
= force_const_mem (Pmode
, orig
);
3601 /* Otherwise, compute the sum. */
3604 base
= legitimize_pic_address (XEXP (addr
, 0), reg
);
3605 new_rtx
= legitimize_pic_address (XEXP (addr
, 1),
3606 base
== reg
? NULL_RTX
: reg
);
3607 if (GET_CODE (new_rtx
) == CONST_INT
)
3608 new_rtx
= plus_constant (base
, INTVAL (new_rtx
));
3611 if (GET_CODE (new_rtx
) == PLUS
&& CONSTANT_P (XEXP (new_rtx
, 1)))
3613 base
= gen_rtx_PLUS (Pmode
, base
, XEXP (new_rtx
, 0));
3614 new_rtx
= XEXP (new_rtx
, 1);
3616 new_rtx
= gen_rtx_PLUS (Pmode
, base
, new_rtx
);
3619 if (GET_CODE (new_rtx
) == CONST
)
3620 new_rtx
= XEXP (new_rtx
, 0);
3621 new_rtx
= force_operand (new_rtx
, 0);
3628 /* Load the thread pointer into a register. */
3631 s390_get_thread_pointer (void)
3633 rtx tp
= gen_reg_rtx (Pmode
);
3635 emit_move_insn (tp
, gen_rtx_REG (Pmode
, TP_REGNUM
));
3636 mark_reg_pointer (tp
, BITS_PER_WORD
);
3641 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3642 in s390_tls_symbol which always refers to __tls_get_offset.
3643 The returned offset is written to RESULT_REG and an USE rtx is
3644 generated for TLS_CALL. */
3646 static GTY(()) rtx s390_tls_symbol
;
3649 s390_emit_tls_call_insn (rtx result_reg
, rtx tls_call
)
3653 gcc_assert (flag_pic
);
3655 if (!s390_tls_symbol
)
3656 s390_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_offset");
3658 insn
= s390_emit_call (s390_tls_symbol
, tls_call
, result_reg
,
3659 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
3661 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), result_reg
);
3662 RTL_CONST_CALL_P (insn
) = 1;
3665 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3666 this (thread-local) address. REG may be used as temporary. */
3669 legitimize_tls_address (rtx addr
, rtx reg
)
3671 rtx new_rtx
, tls_call
, temp
, base
, r2
, insn
;
3673 if (GET_CODE (addr
) == SYMBOL_REF
)
3674 switch (tls_symbolic_operand (addr
))
3676 case TLS_MODEL_GLOBAL_DYNAMIC
:
3678 r2
= gen_rtx_REG (Pmode
, 2);
3679 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_TLSGD
);
3680 new_rtx
= gen_rtx_CONST (Pmode
, tls_call
);
3681 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3682 emit_move_insn (r2
, new_rtx
);
3683 s390_emit_tls_call_insn (r2
, tls_call
);
3684 insn
= get_insns ();
3687 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
3688 temp
= gen_reg_rtx (Pmode
);
3689 emit_libcall_block (insn
, temp
, r2
, new_rtx
);
3691 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3694 s390_load_address (reg
, new_rtx
);
3699 case TLS_MODEL_LOCAL_DYNAMIC
:
3701 r2
= gen_rtx_REG (Pmode
, 2);
3702 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM
);
3703 new_rtx
= gen_rtx_CONST (Pmode
, tls_call
);
3704 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3705 emit_move_insn (r2
, new_rtx
);
3706 s390_emit_tls_call_insn (r2
, tls_call
);
3707 insn
= get_insns ();
3710 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM_NTPOFF
);
3711 temp
= gen_reg_rtx (Pmode
);
3712 emit_libcall_block (insn
, temp
, r2
, new_rtx
);
3714 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3715 base
= gen_reg_rtx (Pmode
);
3716 s390_load_address (base
, new_rtx
);
3718 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_DTPOFF
);
3719 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3720 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3721 temp
= gen_reg_rtx (Pmode
);
3722 emit_move_insn (temp
, new_rtx
);
3724 new_rtx
= gen_rtx_PLUS (Pmode
, base
, temp
);
3727 s390_load_address (reg
, new_rtx
);
3732 case TLS_MODEL_INITIAL_EXEC
:
3735 /* Assume GOT offset < 4k. This is handled the same way
3736 in both 31- and 64-bit code. */
3738 if (reload_in_progress
|| reload_completed
)
3739 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3741 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
3742 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3743 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new_rtx
);
3744 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3745 temp
= gen_reg_rtx (Pmode
);
3746 emit_move_insn (temp
, new_rtx
);
3748 else if (TARGET_CPU_ZARCH
)
3750 /* If the GOT offset might be >= 4k, we determine the position
3751 of the GOT entry via a PC-relative LARL. */
3753 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
3754 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3755 temp
= gen_reg_rtx (Pmode
);
3756 emit_move_insn (temp
, new_rtx
);
3758 new_rtx
= gen_const_mem (Pmode
, temp
);
3759 temp
= gen_reg_rtx (Pmode
);
3760 emit_move_insn (temp
, new_rtx
);
3764 /* If the GOT offset might be >= 4k, we have to load it
3765 from the literal pool. */
3767 if (reload_in_progress
|| reload_completed
)
3768 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3770 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
3771 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3772 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3773 temp
= gen_reg_rtx (Pmode
);
3774 emit_move_insn (temp
, new_rtx
);
3776 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3777 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3779 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new_rtx
, addr
), UNSPEC_TLS_LOAD
);
3780 temp
= gen_reg_rtx (Pmode
);
3781 emit_insn (gen_rtx_SET (Pmode
, temp
, new_rtx
));
3785 /* In position-dependent code, load the absolute address of
3786 the GOT entry from the literal pool. */
3788 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
3789 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3790 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3791 temp
= gen_reg_rtx (Pmode
);
3792 emit_move_insn (temp
, new_rtx
);
3795 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3796 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new_rtx
, addr
), UNSPEC_TLS_LOAD
);
3797 temp
= gen_reg_rtx (Pmode
);
3798 emit_insn (gen_rtx_SET (Pmode
, temp
, new_rtx
));
3801 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3804 s390_load_address (reg
, new_rtx
);
3809 case TLS_MODEL_LOCAL_EXEC
:
3810 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
3811 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3812 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3813 temp
= gen_reg_rtx (Pmode
);
3814 emit_move_insn (temp
, new_rtx
);
3816 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3819 s390_load_address (reg
, new_rtx
);
3828 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == UNSPEC
)
3830 switch (XINT (XEXP (addr
, 0), 1))
3832 case UNSPEC_INDNTPOFF
:
3833 gcc_assert (TARGET_CPU_ZARCH
);
3842 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == PLUS
3843 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST_INT
)
3845 new_rtx
= XEXP (XEXP (addr
, 0), 0);
3846 if (GET_CODE (new_rtx
) != SYMBOL_REF
)
3847 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3849 new_rtx
= legitimize_tls_address (new_rtx
, reg
);
3850 new_rtx
= plus_constant (new_rtx
, INTVAL (XEXP (XEXP (addr
, 0), 1)));
3851 new_rtx
= force_operand (new_rtx
, 0);
3855 gcc_unreachable (); /* for now ... */
3860 /* Emit insns making the address in operands[1] valid for a standard
3861 move to operands[0]. operands[1] is replaced by an address which
3862 should be used instead of the former RTX to emit the move
3866 emit_symbolic_move (rtx
*operands
)
3868 rtx temp
= !can_create_pseudo_p () ? operands
[0] : gen_reg_rtx (Pmode
);
3870 if (GET_CODE (operands
[0]) == MEM
)
3871 operands
[1] = force_reg (Pmode
, operands
[1]);
3872 else if (TLS_SYMBOLIC_CONST (operands
[1]))
3873 operands
[1] = legitimize_tls_address (operands
[1], temp
);
3875 operands
[1] = legitimize_pic_address (operands
[1], temp
);
3878 /* Try machine-dependent ways of modifying an illegitimate address X
3879 to be legitimate. If we find one, return the new, valid address.
3881 OLDX is the address as it was before break_out_memory_refs was called.
3882 In some cases it is useful to look at this to decide what needs to be done.
3884 MODE is the mode of the operand pointed to by X.
3886 When -fpic is used, special handling is needed for symbolic references.
3887 See comments by legitimize_pic_address for details. */
3890 s390_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3891 enum machine_mode mode ATTRIBUTE_UNUSED
)
3893 rtx constant_term
= const0_rtx
;
3895 if (TLS_SYMBOLIC_CONST (x
))
3897 x
= legitimize_tls_address (x
, 0);
3899 if (s390_legitimate_address_p (mode
, x
, FALSE
))
3902 else if (GET_CODE (x
) == PLUS
3903 && (TLS_SYMBOLIC_CONST (XEXP (x
, 0))
3904 || TLS_SYMBOLIC_CONST (XEXP (x
, 1))))
3910 if (SYMBOLIC_CONST (x
)
3911 || (GET_CODE (x
) == PLUS
3912 && (SYMBOLIC_CONST (XEXP (x
, 0))
3913 || SYMBOLIC_CONST (XEXP (x
, 1)))))
3914 x
= legitimize_pic_address (x
, 0);
3916 if (s390_legitimate_address_p (mode
, x
, FALSE
))
3920 x
= eliminate_constant_term (x
, &constant_term
);
3922 /* Optimize loading of large displacements by splitting them
3923 into the multiple of 4K and the rest; this allows the
3924 former to be CSE'd if possible.
3926 Don't do this if the displacement is added to a register
3927 pointing into the stack frame, as the offsets will
3928 change later anyway. */
3930 if (GET_CODE (constant_term
) == CONST_INT
3931 && !TARGET_LONG_DISPLACEMENT
3932 && !DISP_IN_RANGE (INTVAL (constant_term
))
3933 && !(REG_P (x
) && REGNO_PTR_FRAME_P (REGNO (x
))))
3935 HOST_WIDE_INT lower
= INTVAL (constant_term
) & 0xfff;
3936 HOST_WIDE_INT upper
= INTVAL (constant_term
) ^ lower
;
3938 rtx temp
= gen_reg_rtx (Pmode
);
3939 rtx val
= force_operand (GEN_INT (upper
), temp
);
3941 emit_move_insn (temp
, val
);
3943 x
= gen_rtx_PLUS (Pmode
, x
, temp
);
3944 constant_term
= GEN_INT (lower
);
3947 if (GET_CODE (x
) == PLUS
)
3949 if (GET_CODE (XEXP (x
, 0)) == REG
)
3951 rtx temp
= gen_reg_rtx (Pmode
);
3952 rtx val
= force_operand (XEXP (x
, 1), temp
);
3954 emit_move_insn (temp
, val
);
3956 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0), temp
);
3959 else if (GET_CODE (XEXP (x
, 1)) == REG
)
3961 rtx temp
= gen_reg_rtx (Pmode
);
3962 rtx val
= force_operand (XEXP (x
, 0), temp
);
3964 emit_move_insn (temp
, val
);
3966 x
= gen_rtx_PLUS (Pmode
, temp
, XEXP (x
, 1));
3970 if (constant_term
!= const0_rtx
)
3971 x
= gen_rtx_PLUS (Pmode
, x
, constant_term
);
3976 /* Try a machine-dependent way of reloading an illegitimate address AD
3977 operand. If we find one, push the reload and and return the new address.
3979 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3980 and TYPE is the reload type of the current reload. */
3983 legitimize_reload_address (rtx ad
, enum machine_mode mode ATTRIBUTE_UNUSED
,
3984 int opnum
, int type
)
3986 if (!optimize
|| TARGET_LONG_DISPLACEMENT
)
3989 if (GET_CODE (ad
) == PLUS
)
3991 rtx tem
= simplify_binary_operation (PLUS
, Pmode
,
3992 XEXP (ad
, 0), XEXP (ad
, 1));
3997 if (GET_CODE (ad
) == PLUS
3998 && GET_CODE (XEXP (ad
, 0)) == REG
3999 && GET_CODE (XEXP (ad
, 1)) == CONST_INT
4000 && !DISP_IN_RANGE (INTVAL (XEXP (ad
, 1))))
4002 HOST_WIDE_INT lower
= INTVAL (XEXP (ad
, 1)) & 0xfff;
4003 HOST_WIDE_INT upper
= INTVAL (XEXP (ad
, 1)) ^ lower
;
4004 rtx cst
, tem
, new_rtx
;
4006 cst
= GEN_INT (upper
);
4007 if (!legitimate_reload_constant_p (cst
))
4008 cst
= force_const_mem (Pmode
, cst
);
4010 tem
= gen_rtx_PLUS (Pmode
, XEXP (ad
, 0), cst
);
4011 new_rtx
= gen_rtx_PLUS (Pmode
, tem
, GEN_INT (lower
));
4013 push_reload (XEXP (tem
, 1), 0, &XEXP (tem
, 1), 0,
4014 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
4015 opnum
, (enum reload_type
) type
);
4022 /* Emit code to move LEN bytes from DST to SRC. */
4025 s390_expand_movmem (rtx dst
, rtx src
, rtx len
)
4027 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
4029 if (INTVAL (len
) > 0)
4030 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (INTVAL (len
) - 1)));
4033 else if (TARGET_MVCLE
)
4035 emit_insn (gen_movmem_long (dst
, src
, convert_to_mode (Pmode
, len
, 1)));
4040 rtx dst_addr
, src_addr
, count
, blocks
, temp
;
4041 rtx loop_start_label
= gen_label_rtx ();
4042 rtx loop_end_label
= gen_label_rtx ();
4043 rtx end_label
= gen_label_rtx ();
4044 enum machine_mode mode
;
4046 mode
= GET_MODE (len
);
4047 if (mode
== VOIDmode
)
4050 dst_addr
= gen_reg_rtx (Pmode
);
4051 src_addr
= gen_reg_rtx (Pmode
);
4052 count
= gen_reg_rtx (mode
);
4053 blocks
= gen_reg_rtx (mode
);
4055 convert_move (count
, len
, 1);
4056 emit_cmp_and_jump_insns (count
, const0_rtx
,
4057 EQ
, NULL_RTX
, mode
, 1, end_label
);
4059 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
4060 emit_move_insn (src_addr
, force_operand (XEXP (src
, 0), NULL_RTX
));
4061 dst
= change_address (dst
, VOIDmode
, dst_addr
);
4062 src
= change_address (src
, VOIDmode
, src_addr
);
4064 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4067 emit_move_insn (count
, temp
);
4069 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4072 emit_move_insn (blocks
, temp
);
4074 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4075 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4077 emit_label (loop_start_label
);
4080 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 768))
4084 /* Issue a read prefetch for the +3 cache line. */
4085 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, src_addr
, GEN_INT (768)),
4086 const0_rtx
, const0_rtx
);
4087 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4088 emit_insn (prefetch
);
4090 /* Issue a write prefetch for the +3 cache line. */
4091 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (768)),
4092 const1_rtx
, const0_rtx
);
4093 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4094 emit_insn (prefetch
);
4097 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (255)));
4098 s390_load_address (dst_addr
,
4099 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
4100 s390_load_address (src_addr
,
4101 gen_rtx_PLUS (Pmode
, src_addr
, GEN_INT (256)));
4103 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4106 emit_move_insn (blocks
, temp
);
4108 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4109 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4111 emit_jump (loop_start_label
);
4112 emit_label (loop_end_label
);
4114 emit_insn (gen_movmem_short (dst
, src
,
4115 convert_to_mode (Pmode
, count
, 1)));
4116 emit_label (end_label
);
4120 /* Emit code to set LEN bytes at DST to VAL.
4121 Make use of clrmem if VAL is zero. */
4124 s390_expand_setmem (rtx dst
, rtx len
, rtx val
)
4126 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) == 0)
4129 gcc_assert (GET_CODE (val
) == CONST_INT
|| GET_MODE (val
) == QImode
);
4131 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) > 0 && INTVAL (len
) <= 257)
4133 if (val
== const0_rtx
&& INTVAL (len
) <= 256)
4134 emit_insn (gen_clrmem_short (dst
, GEN_INT (INTVAL (len
) - 1)));
4137 /* Initialize memory by storing the first byte. */
4138 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
4140 if (INTVAL (len
) > 1)
4142 /* Initiate 1 byte overlap move.
4143 The first byte of DST is propagated through DSTP1.
4144 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
4145 DST is set to size 1 so the rest of the memory location
4146 does not count as source operand. */
4147 rtx dstp1
= adjust_address (dst
, VOIDmode
, 1);
4148 set_mem_size (dst
, const1_rtx
);
4150 emit_insn (gen_movmem_short (dstp1
, dst
,
4151 GEN_INT (INTVAL (len
) - 2)));
4156 else if (TARGET_MVCLE
)
4158 val
= force_not_mem (convert_modes (Pmode
, QImode
, val
, 1));
4159 emit_insn (gen_setmem_long (dst
, convert_to_mode (Pmode
, len
, 1), val
));
4164 rtx dst_addr
, count
, blocks
, temp
, dstp1
= NULL_RTX
;
4165 rtx loop_start_label
= gen_label_rtx ();
4166 rtx loop_end_label
= gen_label_rtx ();
4167 rtx end_label
= gen_label_rtx ();
4168 enum machine_mode mode
;
4170 mode
= GET_MODE (len
);
4171 if (mode
== VOIDmode
)
4174 dst_addr
= gen_reg_rtx (Pmode
);
4175 count
= gen_reg_rtx (mode
);
4176 blocks
= gen_reg_rtx (mode
);
4178 convert_move (count
, len
, 1);
4179 emit_cmp_and_jump_insns (count
, const0_rtx
,
4180 EQ
, NULL_RTX
, mode
, 1, end_label
);
4182 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
4183 dst
= change_address (dst
, VOIDmode
, dst_addr
);
4185 if (val
== const0_rtx
)
4186 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4190 dstp1
= adjust_address (dst
, VOIDmode
, 1);
4191 set_mem_size (dst
, const1_rtx
);
4193 /* Initialize memory by storing the first byte. */
4194 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
4196 /* If count is 1 we are done. */
4197 emit_cmp_and_jump_insns (count
, const1_rtx
,
4198 EQ
, NULL_RTX
, mode
, 1, end_label
);
4200 temp
= expand_binop (mode
, add_optab
, count
, GEN_INT (-2), count
, 1,
4204 emit_move_insn (count
, temp
);
4206 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4209 emit_move_insn (blocks
, temp
);
4211 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4212 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4214 emit_label (loop_start_label
);
4217 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 1024))
4219 /* Issue a write prefetch for the +4 cache line. */
4220 rtx prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, dst_addr
,
4222 const1_rtx
, const0_rtx
);
4223 emit_insn (prefetch
);
4224 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4227 if (val
== const0_rtx
)
4228 emit_insn (gen_clrmem_short (dst
, GEN_INT (255)));
4230 emit_insn (gen_movmem_short (dstp1
, dst
, GEN_INT (255)));
4231 s390_load_address (dst_addr
,
4232 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
4234 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4237 emit_move_insn (blocks
, temp
);
4239 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4240 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4242 emit_jump (loop_start_label
);
4243 emit_label (loop_end_label
);
4245 if (val
== const0_rtx
)
4246 emit_insn (gen_clrmem_short (dst
, convert_to_mode (Pmode
, count
, 1)));
4248 emit_insn (gen_movmem_short (dstp1
, dst
, convert_to_mode (Pmode
, count
, 1)));
4249 emit_label (end_label
);
4253 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4254 and return the result in TARGET. */
4257 s390_expand_cmpmem (rtx target
, rtx op0
, rtx op1
, rtx len
)
4259 rtx ccreg
= gen_rtx_REG (CCUmode
, CC_REGNUM
);
4262 /* As the result of CMPINT is inverted compared to what we need,
4263 we have to swap the operands. */
4264 tmp
= op0
; op0
= op1
; op1
= tmp
;
4266 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
4268 if (INTVAL (len
) > 0)
4270 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (INTVAL (len
) - 1)));
4271 emit_insn (gen_cmpint (target
, ccreg
));
4274 emit_move_insn (target
, const0_rtx
);
4276 else if (TARGET_MVCLE
)
4278 emit_insn (gen_cmpmem_long (op0
, op1
, convert_to_mode (Pmode
, len
, 1)));
4279 emit_insn (gen_cmpint (target
, ccreg
));
4283 rtx addr0
, addr1
, count
, blocks
, temp
;
4284 rtx loop_start_label
= gen_label_rtx ();
4285 rtx loop_end_label
= gen_label_rtx ();
4286 rtx end_label
= gen_label_rtx ();
4287 enum machine_mode mode
;
4289 mode
= GET_MODE (len
);
4290 if (mode
== VOIDmode
)
4293 addr0
= gen_reg_rtx (Pmode
);
4294 addr1
= gen_reg_rtx (Pmode
);
4295 count
= gen_reg_rtx (mode
);
4296 blocks
= gen_reg_rtx (mode
);
4298 convert_move (count
, len
, 1);
4299 emit_cmp_and_jump_insns (count
, const0_rtx
,
4300 EQ
, NULL_RTX
, mode
, 1, end_label
);
4302 emit_move_insn (addr0
, force_operand (XEXP (op0
, 0), NULL_RTX
));
4303 emit_move_insn (addr1
, force_operand (XEXP (op1
, 0), NULL_RTX
));
4304 op0
= change_address (op0
, VOIDmode
, addr0
);
4305 op1
= change_address (op1
, VOIDmode
, addr1
);
4307 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4310 emit_move_insn (count
, temp
);
4312 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4315 emit_move_insn (blocks
, temp
);
4317 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4318 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4320 emit_label (loop_start_label
);
4323 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 512))
4327 /* Issue a read prefetch for the +2 cache line of operand 1. */
4328 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, addr0
, GEN_INT (512)),
4329 const0_rtx
, const0_rtx
);
4330 emit_insn (prefetch
);
4331 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4333 /* Issue a read prefetch for the +2 cache line of operand 2. */
4334 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, addr1
, GEN_INT (512)),
4335 const0_rtx
, const0_rtx
);
4336 emit_insn (prefetch
);
4337 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4340 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (255)));
4341 temp
= gen_rtx_NE (VOIDmode
, ccreg
, const0_rtx
);
4342 temp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, temp
,
4343 gen_rtx_LABEL_REF (VOIDmode
, end_label
), pc_rtx
);
4344 temp
= gen_rtx_SET (VOIDmode
, pc_rtx
, temp
);
4345 emit_jump_insn (temp
);
4347 s390_load_address (addr0
,
4348 gen_rtx_PLUS (Pmode
, addr0
, GEN_INT (256)));
4349 s390_load_address (addr1
,
4350 gen_rtx_PLUS (Pmode
, addr1
, GEN_INT (256)));
4352 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4355 emit_move_insn (blocks
, temp
);
4357 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4358 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4360 emit_jump (loop_start_label
);
4361 emit_label (loop_end_label
);
4363 emit_insn (gen_cmpmem_short (op0
, op1
,
4364 convert_to_mode (Pmode
, count
, 1)));
4365 emit_label (end_label
);
4367 emit_insn (gen_cmpint (target
, ccreg
));
4372 /* Expand conditional increment or decrement using alc/slb instructions.
4373 Should generate code setting DST to either SRC or SRC + INCREMENT,
4374 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4375 Returns true if successful, false otherwise.
4377 That makes it possible to implement some if-constructs without jumps e.g.:
4378 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4379 unsigned int a, b, c;
4380 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4381 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4382 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4383 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4385 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4386 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4387 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4388 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4389 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4392 s390_expand_addcc (enum rtx_code cmp_code
, rtx cmp_op0
, rtx cmp_op1
,
4393 rtx dst
, rtx src
, rtx increment
)
4395 enum machine_mode cmp_mode
;
4396 enum machine_mode cc_mode
;
4402 if ((GET_MODE (cmp_op0
) == SImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
4403 && (GET_MODE (cmp_op1
) == SImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
4405 else if ((GET_MODE (cmp_op0
) == DImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
4406 && (GET_MODE (cmp_op1
) == DImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
4411 /* Try ADD LOGICAL WITH CARRY. */
4412 if (increment
== const1_rtx
)
4414 /* Determine CC mode to use. */
4415 if (cmp_code
== EQ
|| cmp_code
== NE
)
4417 if (cmp_op1
!= const0_rtx
)
4419 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
4420 NULL_RTX
, 0, OPTAB_WIDEN
);
4421 cmp_op1
= const0_rtx
;
4424 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
4427 if (cmp_code
== LTU
|| cmp_code
== LEU
)
4432 cmp_code
= swap_condition (cmp_code
);
4449 /* Emit comparison instruction pattern. */
4450 if (!register_operand (cmp_op0
, cmp_mode
))
4451 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
4453 insn
= gen_rtx_SET (VOIDmode
, gen_rtx_REG (cc_mode
, CC_REGNUM
),
4454 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
4455 /* We use insn_invalid_p here to add clobbers if required. */
4456 ret
= insn_invalid_p (emit_insn (insn
));
4459 /* Emit ALC instruction pattern. */
4460 op_res
= gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
4461 gen_rtx_REG (cc_mode
, CC_REGNUM
),
4464 if (src
!= const0_rtx
)
4466 if (!register_operand (src
, GET_MODE (dst
)))
4467 src
= force_reg (GET_MODE (dst
), src
);
4469 op_res
= gen_rtx_PLUS (GET_MODE (dst
), op_res
, src
);
4470 op_res
= gen_rtx_PLUS (GET_MODE (dst
), op_res
, const0_rtx
);
4473 p
= rtvec_alloc (2);
4475 gen_rtx_SET (VOIDmode
, dst
, op_res
);
4477 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4478 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
4483 /* Try SUBTRACT LOGICAL WITH BORROW. */
4484 if (increment
== constm1_rtx
)
4486 /* Determine CC mode to use. */
4487 if (cmp_code
== EQ
|| cmp_code
== NE
)
4489 if (cmp_op1
!= const0_rtx
)
4491 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
4492 NULL_RTX
, 0, OPTAB_WIDEN
);
4493 cmp_op1
= const0_rtx
;
4496 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
4499 if (cmp_code
== GTU
|| cmp_code
== GEU
)
4504 cmp_code
= swap_condition (cmp_code
);
4521 /* Emit comparison instruction pattern. */
4522 if (!register_operand (cmp_op0
, cmp_mode
))
4523 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
4525 insn
= gen_rtx_SET (VOIDmode
, gen_rtx_REG (cc_mode
, CC_REGNUM
),
4526 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
4527 /* We use insn_invalid_p here to add clobbers if required. */
4528 ret
= insn_invalid_p (emit_insn (insn
));
4531 /* Emit SLB instruction pattern. */
4532 if (!register_operand (src
, GET_MODE (dst
)))
4533 src
= force_reg (GET_MODE (dst
), src
);
4535 op_res
= gen_rtx_MINUS (GET_MODE (dst
),
4536 gen_rtx_MINUS (GET_MODE (dst
), src
, const0_rtx
),
4537 gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
4538 gen_rtx_REG (cc_mode
, CC_REGNUM
),
4540 p
= rtvec_alloc (2);
4542 gen_rtx_SET (VOIDmode
, dst
, op_res
);
4544 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4545 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
4553 /* Expand code for the insv template. Return true if successful. */
4556 s390_expand_insv (rtx dest
, rtx op1
, rtx op2
, rtx src
)
4558 int bitsize
= INTVAL (op1
);
4559 int bitpos
= INTVAL (op2
);
4561 /* On z10 we can use the risbg instruction to implement insv. */
4563 && ((GET_MODE (dest
) == DImode
&& GET_MODE (src
) == DImode
)
4564 || (GET_MODE (dest
) == SImode
&& GET_MODE (src
) == SImode
)))
4569 op
= gen_rtx_SET (GET_MODE(src
),
4570 gen_rtx_ZERO_EXTRACT (GET_MODE (dest
), dest
, op1
, op2
),
4572 clobber
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4573 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clobber
)));
4578 /* We need byte alignment. */
4579 if (bitsize
% BITS_PER_UNIT
)
4583 && memory_operand (dest
, VOIDmode
)
4584 && (register_operand (src
, word_mode
)
4585 || const_int_operand (src
, VOIDmode
)))
4587 /* Emit standard pattern if possible. */
4588 enum machine_mode mode
= smallest_mode_for_size (bitsize
, MODE_INT
);
4589 if (GET_MODE_BITSIZE (mode
) == bitsize
)
4590 emit_move_insn (adjust_address (dest
, mode
, 0), gen_lowpart (mode
, src
));
4592 /* (set (ze (mem)) (const_int)). */
4593 else if (const_int_operand (src
, VOIDmode
))
4595 int size
= bitsize
/ BITS_PER_UNIT
;
4596 rtx src_mem
= adjust_address (force_const_mem (word_mode
, src
), BLKmode
,
4597 GET_MODE_SIZE (word_mode
) - size
);
4599 dest
= adjust_address (dest
, BLKmode
, 0);
4600 set_mem_size (dest
, GEN_INT (size
));
4601 s390_expand_movmem (dest
, src_mem
, GEN_INT (size
));
4604 /* (set (ze (mem)) (reg)). */
4605 else if (register_operand (src
, word_mode
))
4607 if (bitsize
<= GET_MODE_BITSIZE (SImode
))
4608 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
, op1
,
4612 /* Emit st,stcmh sequence. */
4613 int stcmh_width
= bitsize
- GET_MODE_BITSIZE (SImode
);
4614 int size
= stcmh_width
/ BITS_PER_UNIT
;
4616 emit_move_insn (adjust_address (dest
, SImode
, size
),
4617 gen_lowpart (SImode
, src
));
4618 set_mem_size (dest
, GEN_INT (size
));
4619 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
, GEN_INT
4620 (stcmh_width
), const0_rtx
),
4621 gen_rtx_LSHIFTRT (word_mode
, src
, GEN_INT
4622 (GET_MODE_BITSIZE (SImode
))));
4631 /* (set (ze (reg)) (const_int)). */
4633 && register_operand (dest
, word_mode
)
4634 && (bitpos
% 16) == 0
4635 && (bitsize
% 16) == 0
4636 && const_int_operand (src
, VOIDmode
))
4638 HOST_WIDE_INT val
= INTVAL (src
);
4639 int regpos
= bitpos
+ bitsize
;
4641 while (regpos
> bitpos
)
4643 enum machine_mode putmode
;
4646 if (TARGET_EXTIMM
&& (regpos
% 32 == 0) && (regpos
>= bitpos
+ 32))
4651 putsize
= GET_MODE_BITSIZE (putmode
);
4653 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
,
4656 gen_int_mode (val
, putmode
));
4659 gcc_assert (regpos
== bitpos
);
4666 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4667 register that holds VAL of mode MODE shifted by COUNT bits. */
4670 s390_expand_mask_and_shift (rtx val
, enum machine_mode mode
, rtx count
)
4672 val
= expand_simple_binop (SImode
, AND
, val
, GEN_INT (GET_MODE_MASK (mode
)),
4673 NULL_RTX
, 1, OPTAB_DIRECT
);
4674 return expand_simple_binop (SImode
, ASHIFT
, val
, count
,
4675 NULL_RTX
, 1, OPTAB_DIRECT
);
4678 /* Structure to hold the initial parameters for a compare_and_swap operation
4679 in HImode and QImode. */
4681 struct alignment_context
4683 rtx memsi
; /* SI aligned memory location. */
4684 rtx shift
; /* Bit offset with regard to lsb. */
4685 rtx modemask
; /* Mask of the HQImode shifted by SHIFT bits. */
4686 rtx modemaski
; /* ~modemask */
4687 bool aligned
; /* True if memory is aligned, false else. */
4690 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4691 structure AC for transparent simplifying, if the memory alignment is known
4692 to be at least 32bit. MEM is the memory location for the actual operation
4693 and MODE its mode. */
4696 init_alignment_context (struct alignment_context
*ac
, rtx mem
,
4697 enum machine_mode mode
)
4699 ac
->shift
= GEN_INT (GET_MODE_SIZE (SImode
) - GET_MODE_SIZE (mode
));
4700 ac
->aligned
= (MEM_ALIGN (mem
) >= GET_MODE_BITSIZE (SImode
));
4703 ac
->memsi
= adjust_address (mem
, SImode
, 0); /* Memory is aligned. */
4706 /* Alignment is unknown. */
4707 rtx byteoffset
, addr
, align
;
4709 /* Force the address into a register. */
4710 addr
= force_reg (Pmode
, XEXP (mem
, 0));
4712 /* Align it to SImode. */
4713 align
= expand_simple_binop (Pmode
, AND
, addr
,
4714 GEN_INT (-GET_MODE_SIZE (SImode
)),
4715 NULL_RTX
, 1, OPTAB_DIRECT
);
4717 ac
->memsi
= gen_rtx_MEM (SImode
, align
);
4718 MEM_VOLATILE_P (ac
->memsi
) = MEM_VOLATILE_P (mem
);
4719 set_mem_alias_set (ac
->memsi
, ALIAS_SET_MEMORY_BARRIER
);
4720 set_mem_align (ac
->memsi
, GET_MODE_BITSIZE (SImode
));
4722 /* Calculate shiftcount. */
4723 byteoffset
= expand_simple_binop (Pmode
, AND
, addr
,
4724 GEN_INT (GET_MODE_SIZE (SImode
) - 1),
4725 NULL_RTX
, 1, OPTAB_DIRECT
);
4726 /* As we already have some offset, evaluate the remaining distance. */
4727 ac
->shift
= expand_simple_binop (SImode
, MINUS
, ac
->shift
, byteoffset
,
4728 NULL_RTX
, 1, OPTAB_DIRECT
);
4731 /* Shift is the byte count, but we need the bitcount. */
4732 ac
->shift
= expand_simple_binop (SImode
, MULT
, ac
->shift
, GEN_INT (BITS_PER_UNIT
),
4733 NULL_RTX
, 1, OPTAB_DIRECT
);
4734 /* Calculate masks. */
4735 ac
->modemask
= expand_simple_binop (SImode
, ASHIFT
,
4736 GEN_INT (GET_MODE_MASK (mode
)), ac
->shift
,
4737 NULL_RTX
, 1, OPTAB_DIRECT
);
4738 ac
->modemaski
= expand_simple_unop (SImode
, NOT
, ac
->modemask
, NULL_RTX
, 1);
4741 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4742 the memory location, CMP the old value to compare MEM with and NEW_RTX the value
4743 to set if CMP == MEM.
4744 CMP is never in memory for compare_and_swap_cc because
4745 expand_bool_compare_and_swap puts it into a register for later compare. */
4748 s390_expand_cs_hqi (enum machine_mode mode
, rtx target
, rtx mem
, rtx cmp
, rtx new_rtx
)
4750 struct alignment_context ac
;
4751 rtx cmpv
, newv
, val
, resv
, cc
;
4752 rtx res
= gen_reg_rtx (SImode
);
4753 rtx csloop
= gen_label_rtx ();
4754 rtx csend
= gen_label_rtx ();
4756 gcc_assert (register_operand (target
, VOIDmode
));
4757 gcc_assert (MEM_P (mem
));
4759 init_alignment_context (&ac
, mem
, mode
);
4761 /* Shift the values to the correct bit positions. */
4762 if (!(ac
.aligned
&& MEM_P (cmp
)))
4763 cmp
= s390_expand_mask_and_shift (cmp
, mode
, ac
.shift
);
4764 if (!(ac
.aligned
&& MEM_P (new_rtx
)))
4765 new_rtx
= s390_expand_mask_and_shift (new_rtx
, mode
, ac
.shift
);
4767 /* Load full word. Subsequent loads are performed by CS. */
4768 val
= expand_simple_binop (SImode
, AND
, ac
.memsi
, ac
.modemaski
,
4769 NULL_RTX
, 1, OPTAB_DIRECT
);
4771 /* Start CS loop. */
4772 emit_label (csloop
);
4773 /* val = "<mem>00..0<mem>"
4774 * cmp = "00..0<cmp>00..0"
4775 * new = "00..0<new>00..0"
4778 /* Patch cmp and new with val at correct position. */
4779 if (ac
.aligned
&& MEM_P (cmp
))
4781 cmpv
= force_reg (SImode
, val
);
4782 store_bit_field (cmpv
, GET_MODE_BITSIZE (mode
), 0, SImode
, cmp
);
4785 cmpv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, cmp
, val
,
4786 NULL_RTX
, 1, OPTAB_DIRECT
));
4787 if (ac
.aligned
&& MEM_P (new_rtx
))
4789 newv
= force_reg (SImode
, val
);
4790 store_bit_field (newv
, GET_MODE_BITSIZE (mode
), 0, SImode
, new_rtx
);
4793 newv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, new_rtx
, val
,
4794 NULL_RTX
, 1, OPTAB_DIRECT
));
4796 /* Jump to end if we're done (likely?). */
4797 s390_emit_jump (csend
, s390_emit_compare_and_swap (EQ
, res
, ac
.memsi
,
4800 /* Check for changes outside mode. */
4801 resv
= expand_simple_binop (SImode
, AND
, res
, ac
.modemaski
,
4802 NULL_RTX
, 1, OPTAB_DIRECT
);
4803 cc
= s390_emit_compare (NE
, resv
, val
);
4804 emit_move_insn (val
, resv
);
4805 /* Loop internal if so. */
4806 s390_emit_jump (csloop
, cc
);
4810 /* Return the correct part of the bitfield. */
4811 convert_move (target
, expand_simple_binop (SImode
, LSHIFTRT
, res
, ac
.shift
,
4812 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
4815 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4816 and VAL the value to play with. If AFTER is true then store the value
4817 MEM holds after the operation, if AFTER is false then store the value MEM
4818 holds before the operation. If TARGET is zero then discard that value, else
4819 store it to TARGET. */
4822 s390_expand_atomic (enum machine_mode mode
, enum rtx_code code
,
4823 rtx target
, rtx mem
, rtx val
, bool after
)
4825 struct alignment_context ac
;
4827 rtx new_rtx
= gen_reg_rtx (SImode
);
4828 rtx orig
= gen_reg_rtx (SImode
);
4829 rtx csloop
= gen_label_rtx ();
4831 gcc_assert (!target
|| register_operand (target
, VOIDmode
));
4832 gcc_assert (MEM_P (mem
));
4834 init_alignment_context (&ac
, mem
, mode
);
4836 /* Shift val to the correct bit positions.
4837 Preserve "icm", but prevent "ex icm". */
4838 if (!(ac
.aligned
&& code
== SET
&& MEM_P (val
)))
4839 val
= s390_expand_mask_and_shift (val
, mode
, ac
.shift
);
4841 /* Further preparation insns. */
4842 if (code
== PLUS
|| code
== MINUS
)
4843 emit_move_insn (orig
, val
);
4844 else if (code
== MULT
|| code
== AND
) /* val = "11..1<val>11..1" */
4845 val
= expand_simple_binop (SImode
, XOR
, val
, ac
.modemaski
,
4846 NULL_RTX
, 1, OPTAB_DIRECT
);
4848 /* Load full word. Subsequent loads are performed by CS. */
4849 cmp
= force_reg (SImode
, ac
.memsi
);
4851 /* Start CS loop. */
4852 emit_label (csloop
);
4853 emit_move_insn (new_rtx
, cmp
);
4855 /* Patch new with val at correct position. */
4860 val
= expand_simple_binop (SImode
, code
, new_rtx
, orig
,
4861 NULL_RTX
, 1, OPTAB_DIRECT
);
4862 val
= expand_simple_binop (SImode
, AND
, val
, ac
.modemask
,
4863 NULL_RTX
, 1, OPTAB_DIRECT
);
4866 if (ac
.aligned
&& MEM_P (val
))
4867 store_bit_field (new_rtx
, GET_MODE_BITSIZE (mode
), 0, SImode
, val
);
4870 new_rtx
= expand_simple_binop (SImode
, AND
, new_rtx
, ac
.modemaski
,
4871 NULL_RTX
, 1, OPTAB_DIRECT
);
4872 new_rtx
= expand_simple_binop (SImode
, IOR
, new_rtx
, val
,
4873 NULL_RTX
, 1, OPTAB_DIRECT
);
4879 new_rtx
= expand_simple_binop (SImode
, code
, new_rtx
, val
,
4880 NULL_RTX
, 1, OPTAB_DIRECT
);
4882 case MULT
: /* NAND */
4883 new_rtx
= expand_simple_binop (SImode
, AND
, new_rtx
, val
,
4884 NULL_RTX
, 1, OPTAB_DIRECT
);
4885 new_rtx
= expand_simple_binop (SImode
, XOR
, new_rtx
, ac
.modemask
,
4886 NULL_RTX
, 1, OPTAB_DIRECT
);
4892 s390_emit_jump (csloop
, s390_emit_compare_and_swap (NE
, cmp
,
4893 ac
.memsi
, cmp
, new_rtx
));
4895 /* Return the correct part of the bitfield. */
4897 convert_move (target
, expand_simple_binop (SImode
, LSHIFTRT
,
4898 after
? new_rtx
: cmp
, ac
.shift
,
4899 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
4902 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4903 We need to emit DTP-relative relocations. */
4905 static void s390_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
4908 s390_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4913 fputs ("\t.long\t", file
);
4916 fputs ("\t.quad\t", file
);
4921 output_addr_const (file
, x
);
4922 fputs ("@DTPOFF", file
);
4925 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4926 /* Implement TARGET_MANGLE_TYPE. */
4929 s390_mangle_type (const_tree type
)
4931 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
4932 && TARGET_LONG_DOUBLE_128
)
4935 /* For all other types, use normal C++ mangling. */
4940 /* In the name of slightly smaller debug output, and to cater to
4941 general assembler lossage, recognize various UNSPEC sequences
4942 and turn them back into a direct symbol reference. */
4945 s390_delegitimize_address (rtx orig_x
)
4949 orig_x
= delegitimize_mem_from_attrs (orig_x
);
4951 if (GET_CODE (x
) != MEM
)
4955 if (GET_CODE (x
) == PLUS
4956 && GET_CODE (XEXP (x
, 1)) == CONST
4957 && GET_CODE (XEXP (x
, 0)) == REG
4958 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
)
4960 y
= XEXP (XEXP (x
, 1), 0);
4961 if (GET_CODE (y
) == UNSPEC
4962 && XINT (y
, 1) == UNSPEC_GOT
)
4963 return XVECEXP (y
, 0, 0);
4967 if (GET_CODE (x
) == CONST
)
4970 if (GET_CODE (y
) == UNSPEC
4971 && XINT (y
, 1) == UNSPEC_GOTENT
)
4972 return XVECEXP (y
, 0, 0);
4979 /* Output operand OP to stdio stream FILE.
4980 OP is an address (register + offset) which is not used to address data;
4981 instead the rightmost bits are interpreted as the value. */
4984 print_shift_count_operand (FILE *file
, rtx op
)
4986 HOST_WIDE_INT offset
;
4989 /* Extract base register and offset. */
4990 if (!s390_decompose_shift_count (op
, &base
, &offset
))
4996 gcc_assert (GET_CODE (base
) == REG
);
4997 gcc_assert (REGNO (base
) < FIRST_PSEUDO_REGISTER
);
4998 gcc_assert (REGNO_REG_CLASS (REGNO (base
)) == ADDR_REGS
);
5001 /* Offsets are constricted to twelve bits. */
5002 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
& ((1 << 12) - 1));
5004 fprintf (file
, "(%s)", reg_names
[REGNO (base
)]);
5007 /* See 'get_some_local_dynamic_name'. */
5010 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
5014 if (GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
5016 x
= get_pool_constant (x
);
5017 return for_each_rtx (&x
, get_some_local_dynamic_name_1
, 0);
5020 if (GET_CODE (x
) == SYMBOL_REF
5021 && tls_symbolic_operand (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
5023 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
5030 /* Locate some local-dynamic symbol still in use by this function
5031 so that we can print its name in local-dynamic base patterns. */
5034 get_some_local_dynamic_name (void)
5038 if (cfun
->machine
->some_ld_name
)
5039 return cfun
->machine
->some_ld_name
;
5041 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5043 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
5044 return cfun
->machine
->some_ld_name
;
5049 /* Output machine-dependent UNSPECs occurring in address constant X
5050 in assembler syntax to stdio stream FILE. Returns true if the
5051 constant X could be recognized, false otherwise. */
5054 s390_output_addr_const_extra (FILE *file
, rtx x
)
5056 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 1)
5057 switch (XINT (x
, 1))
5060 output_addr_const (file
, XVECEXP (x
, 0, 0));
5061 fprintf (file
, "@GOTENT");
5064 output_addr_const (file
, XVECEXP (x
, 0, 0));
5065 fprintf (file
, "@GOT");
5068 output_addr_const (file
, XVECEXP (x
, 0, 0));
5069 fprintf (file
, "@GOTOFF");
5072 output_addr_const (file
, XVECEXP (x
, 0, 0));
5073 fprintf (file
, "@PLT");
5076 output_addr_const (file
, XVECEXP (x
, 0, 0));
5077 fprintf (file
, "@PLTOFF");
5080 output_addr_const (file
, XVECEXP (x
, 0, 0));
5081 fprintf (file
, "@TLSGD");
5084 assemble_name (file
, get_some_local_dynamic_name ());
5085 fprintf (file
, "@TLSLDM");
5088 output_addr_const (file
, XVECEXP (x
, 0, 0));
5089 fprintf (file
, "@DTPOFF");
5092 output_addr_const (file
, XVECEXP (x
, 0, 0));
5093 fprintf (file
, "@NTPOFF");
5095 case UNSPEC_GOTNTPOFF
:
5096 output_addr_const (file
, XVECEXP (x
, 0, 0));
5097 fprintf (file
, "@GOTNTPOFF");
5099 case UNSPEC_INDNTPOFF
:
5100 output_addr_const (file
, XVECEXP (x
, 0, 0));
5101 fprintf (file
, "@INDNTPOFF");
5105 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 2)
5106 switch (XINT (x
, 1))
5108 case UNSPEC_POOL_OFFSET
:
5109 x
= gen_rtx_MINUS (GET_MODE (x
), XVECEXP (x
, 0, 0), XVECEXP (x
, 0, 1));
5110 output_addr_const (file
, x
);
5116 /* Output address operand ADDR in assembler syntax to
5117 stdio stream FILE. */
5120 print_operand_address (FILE *file
, rtx addr
)
5122 struct s390_address ad
;
5124 if (s390_symref_operand_p (addr
, NULL
, NULL
))
5126 gcc_assert (TARGET_Z10
);
5127 output_addr_const (file
, addr
);
5131 if (!s390_decompose_address (addr
, &ad
)
5132 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
5133 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
5134 output_operand_lossage ("cannot decompose address");
5137 output_addr_const (file
, ad
.disp
);
5139 fprintf (file
, "0");
5141 if (ad
.base
&& ad
.indx
)
5142 fprintf (file
, "(%s,%s)", reg_names
[REGNO (ad
.indx
)],
5143 reg_names
[REGNO (ad
.base
)]);
5145 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
5148 /* Output operand X in assembler syntax to stdio stream FILE.
5149 CODE specified the format flag. The following format flags
5152 'C': print opcode suffix for branch condition.
5153 'D': print opcode suffix for inverse branch condition.
5154 'E': print opcode suffix for branch on index instruction.
5155 'J': print tls_load/tls_gdcall/tls_ldcall suffix
5156 'G': print the size of the operand in bytes.
5157 'O': print only the displacement of a memory reference.
5158 'R': print only the base register of a memory reference.
5159 'S': print S-type memory reference (base+displacement).
5160 'N': print the second word of a DImode operand.
5161 'M': print the second word of a TImode operand.
5162 'Y': print shift count operand.
5164 'b': print integer X as if it's an unsigned byte.
5165 'c': print integer X as if it's an signed byte.
5166 'x': print integer X as if it's an unsigned halfword.
5167 'h': print integer X as if it's a signed halfword.
5168 'i': print the first nonzero HImode part of X.
5169 'j': print the first HImode part unequal to -1 of X.
5170 'k': print the first nonzero SImode part of X.
5171 'm': print the first SImode part unequal to -1 of X.
5172 'o': print integer X as if it's an unsigned 32bit word. */
5175 print_operand (FILE *file
, rtx x
, int code
)
5180 fprintf (file
, s390_branch_condition_mnemonic (x
, FALSE
));
5184 fprintf (file
, s390_branch_condition_mnemonic (x
, TRUE
));
5188 if (GET_CODE (x
) == LE
)
5189 fprintf (file
, "l");
5190 else if (GET_CODE (x
) == GT
)
5191 fprintf (file
, "h");
5197 if (GET_CODE (x
) == SYMBOL_REF
)
5199 fprintf (file
, "%s", ":tls_load:");
5200 output_addr_const (file
, x
);
5202 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD
)
5204 fprintf (file
, "%s", ":tls_gdcall:");
5205 output_addr_const (file
, XVECEXP (x
, 0, 0));
5207 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM
)
5209 fprintf (file
, "%s", ":tls_ldcall:");
5210 assemble_name (file
, get_some_local_dynamic_name ());
5217 fprintf (file
, "%u", GET_MODE_SIZE (GET_MODE (x
)));
5222 struct s390_address ad
;
5225 gcc_assert (GET_CODE (x
) == MEM
);
5226 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5228 gcc_assert (!ad
.base
|| REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)));
5229 gcc_assert (!ad
.indx
);
5232 output_addr_const (file
, ad
.disp
);
5234 fprintf (file
, "0");
5240 struct s390_address ad
;
5243 gcc_assert (GET_CODE (x
) == MEM
);
5244 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5246 gcc_assert (!ad
.base
|| REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)));
5247 gcc_assert (!ad
.indx
);
5250 fprintf (file
, "%s", reg_names
[REGNO (ad
.base
)]);
5252 fprintf (file
, "0");
5258 struct s390_address ad
;
5261 gcc_assert (GET_CODE (x
) == MEM
);
5262 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5264 gcc_assert (!ad
.base
|| REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)));
5265 gcc_assert (!ad
.indx
);
5268 output_addr_const (file
, ad
.disp
);
5270 fprintf (file
, "0");
5273 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
5278 if (GET_CODE (x
) == REG
)
5279 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
5280 else if (GET_CODE (x
) == MEM
)
5281 x
= change_address (x
, VOIDmode
, plus_constant (XEXP (x
, 0), 4));
5287 if (GET_CODE (x
) == REG
)
5288 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
5289 else if (GET_CODE (x
) == MEM
)
5290 x
= change_address (x
, VOIDmode
, plus_constant (XEXP (x
, 0), 8));
5296 print_shift_count_operand (file
, x
);
5300 switch (GET_CODE (x
))
5303 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5307 output_address (XEXP (x
, 0));
5314 output_addr_const (file
, x
);
5319 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xff);
5320 else if (code
== 'c')
5321 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ((INTVAL (x
) & 0xff) ^ 0x80) - 0x80);
5322 else if (code
== 'x')
5323 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffff);
5324 else if (code
== 'h')
5325 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ((INTVAL (x
) & 0xffff) ^ 0x8000) - 0x8000);
5326 else if (code
== 'i')
5327 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5328 s390_extract_part (x
, HImode
, 0));
5329 else if (code
== 'j')
5330 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5331 s390_extract_part (x
, HImode
, -1));
5332 else if (code
== 'k')
5333 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5334 s390_extract_part (x
, SImode
, 0));
5335 else if (code
== 'm')
5336 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5337 s390_extract_part (x
, SImode
, -1));
5338 else if (code
== 'o')
5339 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffffffff);
5341 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
5345 gcc_assert (GET_MODE (x
) == VOIDmode
);
5347 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
) & 0xff);
5348 else if (code
== 'x')
5349 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
) & 0xffff);
5350 else if (code
== 'h')
5351 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ((CONST_DOUBLE_LOW (x
) & 0xffff) ^ 0x8000) - 0x8000);
5357 fatal_insn ("UNKNOWN in print_operand !?", x
);
5362 /* Target hook for assembling integer objects. We need to define it
5363 here to work a round a bug in some versions of GAS, which couldn't
5364 handle values smaller than INT_MIN when printed in decimal. */
5367 s390_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
5369 if (size
== 8 && aligned_p
5370 && GET_CODE (x
) == CONST_INT
&& INTVAL (x
) < INT_MIN
)
5372 fprintf (asm_out_file
, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX
"\n",
5376 return default_assemble_integer (x
, size
, aligned_p
);
5379 /* Returns true if register REGNO is used for forming
5380 a memory address in expression X. */
5383 reg_used_in_mem_p (int regno
, rtx x
)
5385 enum rtx_code code
= GET_CODE (x
);
5391 if (refers_to_regno_p (regno
, regno
+1,
5395 else if (code
== SET
5396 && GET_CODE (SET_DEST (x
)) == PC
)
5398 if (refers_to_regno_p (regno
, regno
+1,
5403 fmt
= GET_RTX_FORMAT (code
);
5404 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5407 && reg_used_in_mem_p (regno
, XEXP (x
, i
)))
5410 else if (fmt
[i
] == 'E')
5411 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
5412 if (reg_used_in_mem_p (regno
, XVECEXP (x
, i
, j
)))
5418 /* Returns true if expression DEP_RTX sets an address register
5419 used by instruction INSN to address memory. */
5422 addr_generation_dependency_p (rtx dep_rtx
, rtx insn
)
5426 if (GET_CODE (dep_rtx
) == INSN
)
5427 dep_rtx
= PATTERN (dep_rtx
);
5429 if (GET_CODE (dep_rtx
) == SET
)
5431 target
= SET_DEST (dep_rtx
);
5432 if (GET_CODE (target
) == STRICT_LOW_PART
)
5433 target
= XEXP (target
, 0);
5434 while (GET_CODE (target
) == SUBREG
)
5435 target
= SUBREG_REG (target
);
5437 if (GET_CODE (target
) == REG
)
5439 int regno
= REGNO (target
);
5441 if (s390_safe_attr_type (insn
) == TYPE_LA
)
5443 pat
= PATTERN (insn
);
5444 if (GET_CODE (pat
) == PARALLEL
)
5446 gcc_assert (XVECLEN (pat
, 0) == 2);
5447 pat
= XVECEXP (pat
, 0, 0);
5449 gcc_assert (GET_CODE (pat
) == SET
);
5450 return refers_to_regno_p (regno
, regno
+1, SET_SRC (pat
), 0);
5452 else if (get_attr_atype (insn
) == ATYPE_AGEN
)
5453 return reg_used_in_mem_p (regno
, PATTERN (insn
));
5459 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5462 s390_agen_dep_p (rtx dep_insn
, rtx insn
)
5464 rtx dep_rtx
= PATTERN (dep_insn
);
5467 if (GET_CODE (dep_rtx
) == SET
5468 && addr_generation_dependency_p (dep_rtx
, insn
))
5470 else if (GET_CODE (dep_rtx
) == PARALLEL
)
5472 for (i
= 0; i
< XVECLEN (dep_rtx
, 0); i
++)
5474 if (addr_generation_dependency_p (XVECEXP (dep_rtx
, 0, i
), insn
))
5482 /* A C statement (sans semicolon) to update the integer scheduling priority
5483 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5484 reduce the priority to execute INSN later. Do not define this macro if
5485 you do not need to adjust the scheduling priorities of insns.
5487 A STD instruction should be scheduled earlier,
5488 in order to use the bypass. */
5490 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
5492 if (! INSN_P (insn
))
5495 if (s390_tune
!= PROCESSOR_2084_Z990
5496 && s390_tune
!= PROCESSOR_2094_Z9_109
5497 && s390_tune
!= PROCESSOR_2097_Z10
5498 && s390_tune
!= PROCESSOR_2817_Z196
)
5501 switch (s390_safe_attr_type (insn
))
5505 priority
= priority
<< 3;
5509 priority
= priority
<< 1;
5518 /* The number of instructions that can be issued per cycle. */
5521 s390_issue_rate (void)
5525 case PROCESSOR_2084_Z990
:
5526 case PROCESSOR_2094_Z9_109
:
5527 case PROCESSOR_2817_Z196
:
5529 case PROCESSOR_2097_Z10
:
5537 s390_first_cycle_multipass_dfa_lookahead (void)
5542 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5543 Fix up MEMs as required. */
5546 annotate_constant_pool_refs (rtx
*x
)
5551 gcc_assert (GET_CODE (*x
) != SYMBOL_REF
5552 || !CONSTANT_POOL_ADDRESS_P (*x
));
5554 /* Literal pool references can only occur inside a MEM ... */
5555 if (GET_CODE (*x
) == MEM
)
5557 rtx memref
= XEXP (*x
, 0);
5559 if (GET_CODE (memref
) == SYMBOL_REF
5560 && CONSTANT_POOL_ADDRESS_P (memref
))
5562 rtx base
= cfun
->machine
->base_reg
;
5563 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, memref
, base
),
5566 *x
= replace_equiv_address (*x
, addr
);
5570 if (GET_CODE (memref
) == CONST
5571 && GET_CODE (XEXP (memref
, 0)) == PLUS
5572 && GET_CODE (XEXP (XEXP (memref
, 0), 1)) == CONST_INT
5573 && GET_CODE (XEXP (XEXP (memref
, 0), 0)) == SYMBOL_REF
5574 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref
, 0), 0)))
5576 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (memref
, 0), 1));
5577 rtx sym
= XEXP (XEXP (memref
, 0), 0);
5578 rtx base
= cfun
->machine
->base_reg
;
5579 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
5582 *x
= replace_equiv_address (*x
, plus_constant (addr
, off
));
5587 /* ... or a load-address type pattern. */
5588 if (GET_CODE (*x
) == SET
)
5590 rtx addrref
= SET_SRC (*x
);
5592 if (GET_CODE (addrref
) == SYMBOL_REF
5593 && CONSTANT_POOL_ADDRESS_P (addrref
))
5595 rtx base
= cfun
->machine
->base_reg
;
5596 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, addrref
, base
),
5599 SET_SRC (*x
) = addr
;
5603 if (GET_CODE (addrref
) == CONST
5604 && GET_CODE (XEXP (addrref
, 0)) == PLUS
5605 && GET_CODE (XEXP (XEXP (addrref
, 0), 1)) == CONST_INT
5606 && GET_CODE (XEXP (XEXP (addrref
, 0), 0)) == SYMBOL_REF
5607 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref
, 0), 0)))
5609 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (addrref
, 0), 1));
5610 rtx sym
= XEXP (XEXP (addrref
, 0), 0);
5611 rtx base
= cfun
->machine
->base_reg
;
5612 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
5615 SET_SRC (*x
) = plus_constant (addr
, off
);
5620 /* Annotate LTREL_BASE as well. */
5621 if (GET_CODE (*x
) == UNSPEC
5622 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
5624 rtx base
= cfun
->machine
->base_reg
;
5625 *x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XVECEXP (*x
, 0, 0), base
),
5630 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5631 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5635 annotate_constant_pool_refs (&XEXP (*x
, i
));
5637 else if (fmt
[i
] == 'E')
5639 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
5640 annotate_constant_pool_refs (&XVECEXP (*x
, i
, j
));
5645 /* Split all branches that exceed the maximum distance.
5646 Returns true if this created a new literal pool entry. */
5649 s390_split_branches (void)
5651 rtx temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
5652 int new_literal
= 0, ret
;
5653 rtx insn
, pat
, tmp
, target
;
5656 /* We need correct insn addresses. */
5658 shorten_branches (get_insns ());
5660 /* Find all branches that exceed 64KB, and split them. */
5662 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5664 if (GET_CODE (insn
) != JUMP_INSN
)
5667 pat
= PATTERN (insn
);
5668 if (GET_CODE (pat
) == PARALLEL
&& XVECLEN (pat
, 0) > 2)
5669 pat
= XVECEXP (pat
, 0, 0);
5670 if (GET_CODE (pat
) != SET
|| SET_DEST (pat
) != pc_rtx
)
5673 if (GET_CODE (SET_SRC (pat
)) == LABEL_REF
)
5675 label
= &SET_SRC (pat
);
5677 else if (GET_CODE (SET_SRC (pat
)) == IF_THEN_ELSE
)
5679 if (GET_CODE (XEXP (SET_SRC (pat
), 1)) == LABEL_REF
)
5680 label
= &XEXP (SET_SRC (pat
), 1);
5681 else if (GET_CODE (XEXP (SET_SRC (pat
), 2)) == LABEL_REF
)
5682 label
= &XEXP (SET_SRC (pat
), 2);
5689 if (get_attr_length (insn
) <= 4)
5692 /* We are going to use the return register as scratch register,
5693 make sure it will be saved/restored by the prologue/epilogue. */
5694 cfun_frame_layout
.save_return_addr_p
= 1;
5699 tmp
= force_const_mem (Pmode
, *label
);
5700 tmp
= emit_insn_before (gen_rtx_SET (Pmode
, temp_reg
, tmp
), insn
);
5701 INSN_ADDRESSES_NEW (tmp
, -1);
5702 annotate_constant_pool_refs (&PATTERN (tmp
));
5709 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, *label
),
5710 UNSPEC_LTREL_OFFSET
);
5711 target
= gen_rtx_CONST (Pmode
, target
);
5712 target
= force_const_mem (Pmode
, target
);
5713 tmp
= emit_insn_before (gen_rtx_SET (Pmode
, temp_reg
, target
), insn
);
5714 INSN_ADDRESSES_NEW (tmp
, -1);
5715 annotate_constant_pool_refs (&PATTERN (tmp
));
5717 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XEXP (target
, 0),
5718 cfun
->machine
->base_reg
),
5720 target
= gen_rtx_PLUS (Pmode
, temp_reg
, target
);
5723 ret
= validate_change (insn
, label
, target
, 0);
5731 /* Find an annotated literal pool symbol referenced in RTX X,
5732 and store it at REF. Will abort if X contains references to
5733 more than one such pool symbol; multiple references to the same
5734 symbol are allowed, however.
5736 The rtx pointed to by REF must be initialized to NULL_RTX
5737 by the caller before calling this routine. */
5740 find_constant_pool_ref (rtx x
, rtx
*ref
)
5745 /* Ignore LTREL_BASE references. */
5746 if (GET_CODE (x
) == UNSPEC
5747 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
5749 /* Likewise POOL_ENTRY insns. */
5750 if (GET_CODE (x
) == UNSPEC_VOLATILE
5751 && XINT (x
, 1) == UNSPECV_POOL_ENTRY
)
5754 gcc_assert (GET_CODE (x
) != SYMBOL_REF
5755 || !CONSTANT_POOL_ADDRESS_P (x
));
5757 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_LTREF
)
5759 rtx sym
= XVECEXP (x
, 0, 0);
5760 gcc_assert (GET_CODE (sym
) == SYMBOL_REF
5761 && CONSTANT_POOL_ADDRESS_P (sym
));
5763 if (*ref
== NULL_RTX
)
5766 gcc_assert (*ref
== sym
);
5771 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5772 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5776 find_constant_pool_ref (XEXP (x
, i
), ref
);
5778 else if (fmt
[i
] == 'E')
5780 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
5781 find_constant_pool_ref (XVECEXP (x
, i
, j
), ref
);
5786 /* Replace every reference to the annotated literal pool
5787 symbol REF in X by its base plus OFFSET. */
5790 replace_constant_pool_ref (rtx
*x
, rtx ref
, rtx offset
)
5795 gcc_assert (*x
!= ref
);
5797 if (GET_CODE (*x
) == UNSPEC
5798 && XINT (*x
, 1) == UNSPEC_LTREF
5799 && XVECEXP (*x
, 0, 0) == ref
)
5801 *x
= gen_rtx_PLUS (Pmode
, XVECEXP (*x
, 0, 1), offset
);
5805 if (GET_CODE (*x
) == PLUS
5806 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
5807 && GET_CODE (XEXP (*x
, 0)) == UNSPEC
5808 && XINT (XEXP (*x
, 0), 1) == UNSPEC_LTREF
5809 && XVECEXP (XEXP (*x
, 0), 0, 0) == ref
)
5811 rtx addr
= gen_rtx_PLUS (Pmode
, XVECEXP (XEXP (*x
, 0), 0, 1), offset
);
5812 *x
= plus_constant (addr
, INTVAL (XEXP (*x
, 1)));
5816 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5817 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5821 replace_constant_pool_ref (&XEXP (*x
, i
), ref
, offset
);
5823 else if (fmt
[i
] == 'E')
5825 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
5826 replace_constant_pool_ref (&XVECEXP (*x
, i
, j
), ref
, offset
);
5831 /* Check whether X contains an UNSPEC_LTREL_BASE.
5832 Return its constant pool symbol if found, NULL_RTX otherwise. */
5835 find_ltrel_base (rtx x
)
5840 if (GET_CODE (x
) == UNSPEC
5841 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
5842 return XVECEXP (x
, 0, 0);
5844 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5845 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5849 rtx fnd
= find_ltrel_base (XEXP (x
, i
));
5853 else if (fmt
[i
] == 'E')
5855 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
5857 rtx fnd
= find_ltrel_base (XVECEXP (x
, i
, j
));
5867 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5870 replace_ltrel_base (rtx
*x
)
5875 if (GET_CODE (*x
) == UNSPEC
5876 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
5878 *x
= XVECEXP (*x
, 0, 1);
5882 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5883 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5887 replace_ltrel_base (&XEXP (*x
, i
));
5889 else if (fmt
[i
] == 'E')
5891 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
5892 replace_ltrel_base (&XVECEXP (*x
, i
, j
));
5898 /* We keep a list of constants which we have to add to internal
5899 constant tables in the middle of large functions. */
5901 #define NR_C_MODES 11
5902 enum machine_mode constant_modes
[NR_C_MODES
] =
5904 TFmode
, TImode
, TDmode
,
5905 DFmode
, DImode
, DDmode
,
5906 SFmode
, SImode
, SDmode
,
5913 struct constant
*next
;
5918 struct constant_pool
5920 struct constant_pool
*next
;
5924 rtx emit_pool_after
;
5926 struct constant
*constants
[NR_C_MODES
];
5927 struct constant
*execute
;
5932 /* Allocate new constant_pool structure. */
5934 static struct constant_pool
*
5935 s390_alloc_pool (void)
5937 struct constant_pool
*pool
;
5940 pool
= (struct constant_pool
*) xmalloc (sizeof *pool
);
5942 for (i
= 0; i
< NR_C_MODES
; i
++)
5943 pool
->constants
[i
] = NULL
;
5945 pool
->execute
= NULL
;
5946 pool
->label
= gen_label_rtx ();
5947 pool
->first_insn
= NULL_RTX
;
5948 pool
->pool_insn
= NULL_RTX
;
5949 pool
->insns
= BITMAP_ALLOC (NULL
);
5951 pool
->emit_pool_after
= NULL_RTX
;
5956 /* Create new constant pool covering instructions starting at INSN
5957 and chain it to the end of POOL_LIST. */
5959 static struct constant_pool
*
5960 s390_start_pool (struct constant_pool
**pool_list
, rtx insn
)
5962 struct constant_pool
*pool
, **prev
;
5964 pool
= s390_alloc_pool ();
5965 pool
->first_insn
= insn
;
5967 for (prev
= pool_list
; *prev
; prev
= &(*prev
)->next
)
5974 /* End range of instructions covered by POOL at INSN and emit
5975 placeholder insn representing the pool. */
5978 s390_end_pool (struct constant_pool
*pool
, rtx insn
)
5980 rtx pool_size
= GEN_INT (pool
->size
+ 8 /* alignment slop */);
5983 insn
= get_last_insn ();
5985 pool
->pool_insn
= emit_insn_after (gen_pool (pool_size
), insn
);
5986 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
5989 /* Add INSN to the list of insns covered by POOL. */
5992 s390_add_pool_insn (struct constant_pool
*pool
, rtx insn
)
5994 bitmap_set_bit (pool
->insns
, INSN_UID (insn
));
5997 /* Return pool out of POOL_LIST that covers INSN. */
5999 static struct constant_pool
*
6000 s390_find_pool (struct constant_pool
*pool_list
, rtx insn
)
6002 struct constant_pool
*pool
;
6004 for (pool
= pool_list
; pool
; pool
= pool
->next
)
6005 if (bitmap_bit_p (pool
->insns
, INSN_UID (insn
)))
6011 /* Add constant VAL of mode MODE to the constant pool POOL. */
6014 s390_add_constant (struct constant_pool
*pool
, rtx val
, enum machine_mode mode
)
6019 for (i
= 0; i
< NR_C_MODES
; i
++)
6020 if (constant_modes
[i
] == mode
)
6022 gcc_assert (i
!= NR_C_MODES
);
6024 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
6025 if (rtx_equal_p (val
, c
->value
))
6030 c
= (struct constant
*) xmalloc (sizeof *c
);
6032 c
->label
= gen_label_rtx ();
6033 c
->next
= pool
->constants
[i
];
6034 pool
->constants
[i
] = c
;
6035 pool
->size
+= GET_MODE_SIZE (mode
);
6039 /* Return an rtx that represents the offset of X from the start of
6043 s390_pool_offset (struct constant_pool
*pool
, rtx x
)
6047 label
= gen_rtx_LABEL_REF (GET_MODE (x
), pool
->label
);
6048 x
= gen_rtx_UNSPEC (GET_MODE (x
), gen_rtvec (2, x
, label
),
6049 UNSPEC_POOL_OFFSET
);
6050 return gen_rtx_CONST (GET_MODE (x
), x
);
6053 /* Find constant VAL of mode MODE in the constant pool POOL.
6054 Return an RTX describing the distance from the start of
6055 the pool to the location of the new constant. */
6058 s390_find_constant (struct constant_pool
*pool
, rtx val
,
6059 enum machine_mode mode
)
6064 for (i
= 0; i
< NR_C_MODES
; i
++)
6065 if (constant_modes
[i
] == mode
)
6067 gcc_assert (i
!= NR_C_MODES
);
6069 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
6070 if (rtx_equal_p (val
, c
->value
))
6075 return s390_pool_offset (pool
, gen_rtx_LABEL_REF (Pmode
, c
->label
));
6078 /* Check whether INSN is an execute. Return the label_ref to its
6079 execute target template if so, NULL_RTX otherwise. */
6082 s390_execute_label (rtx insn
)
6084 if (GET_CODE (insn
) == INSN
6085 && GET_CODE (PATTERN (insn
)) == PARALLEL
6086 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == UNSPEC
6087 && XINT (XVECEXP (PATTERN (insn
), 0, 0), 1) == UNSPEC_EXECUTE
)
6088 return XVECEXP (XVECEXP (PATTERN (insn
), 0, 0), 0, 2);
6093 /* Add execute target for INSN to the constant pool POOL. */
6096 s390_add_execute (struct constant_pool
*pool
, rtx insn
)
6100 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
6101 if (INSN_UID (insn
) == INSN_UID (c
->value
))
6106 c
= (struct constant
*) xmalloc (sizeof *c
);
6108 c
->label
= gen_label_rtx ();
6109 c
->next
= pool
->execute
;
6115 /* Find execute target for INSN in the constant pool POOL.
6116 Return an RTX describing the distance from the start of
6117 the pool to the location of the execute target. */
6120 s390_find_execute (struct constant_pool
*pool
, rtx insn
)
6124 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
6125 if (INSN_UID (insn
) == INSN_UID (c
->value
))
6130 return s390_pool_offset (pool
, gen_rtx_LABEL_REF (Pmode
, c
->label
));
6133 /* For an execute INSN, extract the execute target template. */
6136 s390_execute_target (rtx insn
)
6138 rtx pattern
= PATTERN (insn
);
6139 gcc_assert (s390_execute_label (insn
));
6141 if (XVECLEN (pattern
, 0) == 2)
6143 pattern
= copy_rtx (XVECEXP (pattern
, 0, 1));
6147 rtvec vec
= rtvec_alloc (XVECLEN (pattern
, 0) - 1);
6150 for (i
= 0; i
< XVECLEN (pattern
, 0) - 1; i
++)
6151 RTVEC_ELT (vec
, i
) = copy_rtx (XVECEXP (pattern
, 0, i
+ 1));
6153 pattern
= gen_rtx_PARALLEL (VOIDmode
, vec
);
6159 /* Indicate that INSN cannot be duplicated. This is the case for
6160 execute insns that carry a unique label. */
6163 s390_cannot_copy_insn_p (rtx insn
)
6165 rtx label
= s390_execute_label (insn
);
6166 return label
&& label
!= const0_rtx
;
6169 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
6170 do not emit the pool base label. */
6173 s390_dump_pool (struct constant_pool
*pool
, bool remote_label
)
6176 rtx insn
= pool
->pool_insn
;
6179 /* Switch to rodata section. */
6180 if (TARGET_CPU_ZARCH
)
6182 insn
= emit_insn_after (gen_pool_section_start (), insn
);
6183 INSN_ADDRESSES_NEW (insn
, -1);
6186 /* Ensure minimum pool alignment. */
6187 if (TARGET_CPU_ZARCH
)
6188 insn
= emit_insn_after (gen_pool_align (GEN_INT (8)), insn
);
6190 insn
= emit_insn_after (gen_pool_align (GEN_INT (4)), insn
);
6191 INSN_ADDRESSES_NEW (insn
, -1);
6193 /* Emit pool base label. */
6196 insn
= emit_label_after (pool
->label
, insn
);
6197 INSN_ADDRESSES_NEW (insn
, -1);
6200 /* Dump constants in descending alignment requirement order,
6201 ensuring proper alignment for every constant. */
6202 for (i
= 0; i
< NR_C_MODES
; i
++)
6203 for (c
= pool
->constants
[i
]; c
; c
= c
->next
)
6205 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6206 rtx value
= copy_rtx (c
->value
);
6207 if (GET_CODE (value
) == CONST
6208 && GET_CODE (XEXP (value
, 0)) == UNSPEC
6209 && XINT (XEXP (value
, 0), 1) == UNSPEC_LTREL_OFFSET
6210 && XVECLEN (XEXP (value
, 0), 0) == 1)
6211 value
= s390_pool_offset (pool
, XVECEXP (XEXP (value
, 0), 0, 0));
6213 insn
= emit_label_after (c
->label
, insn
);
6214 INSN_ADDRESSES_NEW (insn
, -1);
6216 value
= gen_rtx_UNSPEC_VOLATILE (constant_modes
[i
],
6217 gen_rtvec (1, value
),
6218 UNSPECV_POOL_ENTRY
);
6219 insn
= emit_insn_after (value
, insn
);
6220 INSN_ADDRESSES_NEW (insn
, -1);
6223 /* Ensure minimum alignment for instructions. */
6224 insn
= emit_insn_after (gen_pool_align (GEN_INT (2)), insn
);
6225 INSN_ADDRESSES_NEW (insn
, -1);
6227 /* Output in-pool execute template insns. */
6228 for (c
= pool
->execute
; c
; c
= c
->next
)
6230 insn
= emit_label_after (c
->label
, insn
);
6231 INSN_ADDRESSES_NEW (insn
, -1);
6233 insn
= emit_insn_after (s390_execute_target (c
->value
), insn
);
6234 INSN_ADDRESSES_NEW (insn
, -1);
6237 /* Switch back to previous section. */
6238 if (TARGET_CPU_ZARCH
)
6240 insn
= emit_insn_after (gen_pool_section_end (), insn
);
6241 INSN_ADDRESSES_NEW (insn
, -1);
6244 insn
= emit_barrier_after (insn
);
6245 INSN_ADDRESSES_NEW (insn
, -1);
6247 /* Remove placeholder insn. */
6248 remove_insn (pool
->pool_insn
);
6251 /* Free all memory used by POOL. */
6254 s390_free_pool (struct constant_pool
*pool
)
6256 struct constant
*c
, *next
;
6259 for (i
= 0; i
< NR_C_MODES
; i
++)
6260 for (c
= pool
->constants
[i
]; c
; c
= next
)
6266 for (c
= pool
->execute
; c
; c
= next
)
6272 BITMAP_FREE (pool
->insns
);
6277 /* Collect main literal pool. Return NULL on overflow. */
6279 static struct constant_pool
*
6280 s390_mainpool_start (void)
6282 struct constant_pool
*pool
;
6285 pool
= s390_alloc_pool ();
6287 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6289 if (GET_CODE (insn
) == INSN
6290 && GET_CODE (PATTERN (insn
)) == SET
6291 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC_VOLATILE
6292 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPECV_MAIN_POOL
)
6294 gcc_assert (!pool
->pool_insn
);
6295 pool
->pool_insn
= insn
;
6298 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
6300 s390_add_execute (pool
, insn
);
6302 else if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6304 rtx pool_ref
= NULL_RTX
;
6305 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6308 rtx constant
= get_pool_constant (pool_ref
);
6309 enum machine_mode mode
= get_pool_mode (pool_ref
);
6310 s390_add_constant (pool
, constant
, mode
);
6314 /* If hot/cold partitioning is enabled we have to make sure that
6315 the literal pool is emitted in the same section where the
6316 initialization of the literal pool base pointer takes place.
6317 emit_pool_after is only used in the non-overflow case on non
6318 Z cpus where we can emit the literal pool at the end of the
6319 function body within the text section. */
6321 && NOTE_KIND (insn
) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6322 && !pool
->emit_pool_after
)
6323 pool
->emit_pool_after
= PREV_INSN (insn
);
6326 gcc_assert (pool
->pool_insn
|| pool
->size
== 0);
6328 if (pool
->size
>= 4096)
6330 /* We're going to chunkify the pool, so remove the main
6331 pool placeholder insn. */
6332 remove_insn (pool
->pool_insn
);
6334 s390_free_pool (pool
);
6338 /* If the functions ends with the section where the literal pool
6339 should be emitted set the marker to its end. */
6340 if (pool
&& !pool
->emit_pool_after
)
6341 pool
->emit_pool_after
= get_last_insn ();
6346 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6347 Modify the current function to output the pool constants as well as
6348 the pool register setup instruction. */
6351 s390_mainpool_finish (struct constant_pool
*pool
)
6353 rtx base_reg
= cfun
->machine
->base_reg
;
6356 /* If the pool is empty, we're done. */
6357 if (pool
->size
== 0)
6359 /* We don't actually need a base register after all. */
6360 cfun
->machine
->base_reg
= NULL_RTX
;
6362 if (pool
->pool_insn
)
6363 remove_insn (pool
->pool_insn
);
6364 s390_free_pool (pool
);
6368 /* We need correct insn addresses. */
6369 shorten_branches (get_insns ());
6371 /* On zSeries, we use a LARL to load the pool register. The pool is
6372 located in the .rodata section, so we emit it after the function. */
6373 if (TARGET_CPU_ZARCH
)
6375 insn
= gen_main_base_64 (base_reg
, pool
->label
);
6376 insn
= emit_insn_after (insn
, pool
->pool_insn
);
6377 INSN_ADDRESSES_NEW (insn
, -1);
6378 remove_insn (pool
->pool_insn
);
6380 insn
= get_last_insn ();
6381 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6382 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6384 s390_dump_pool (pool
, 0);
6387 /* On S/390, if the total size of the function's code plus literal pool
6388 does not exceed 4096 bytes, we use BASR to set up a function base
6389 pointer, and emit the literal pool at the end of the function. */
6390 else if (INSN_ADDRESSES (INSN_UID (pool
->emit_pool_after
))
6391 + pool
->size
+ 8 /* alignment slop */ < 4096)
6393 insn
= gen_main_base_31_small (base_reg
, pool
->label
);
6394 insn
= emit_insn_after (insn
, pool
->pool_insn
);
6395 INSN_ADDRESSES_NEW (insn
, -1);
6396 remove_insn (pool
->pool_insn
);
6398 insn
= emit_label_after (pool
->label
, insn
);
6399 INSN_ADDRESSES_NEW (insn
, -1);
6401 /* emit_pool_after will be set by s390_mainpool_start to the
6402 last insn of the section where the literal pool should be
6404 insn
= pool
->emit_pool_after
;
6406 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6407 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6409 s390_dump_pool (pool
, 1);
6412 /* Otherwise, we emit an inline literal pool and use BASR to branch
6413 over it, setting up the pool register at the same time. */
6416 rtx pool_end
= gen_label_rtx ();
6418 insn
= gen_main_base_31_large (base_reg
, pool
->label
, pool_end
);
6419 insn
= emit_insn_after (insn
, pool
->pool_insn
);
6420 INSN_ADDRESSES_NEW (insn
, -1);
6421 remove_insn (pool
->pool_insn
);
6423 insn
= emit_label_after (pool
->label
, insn
);
6424 INSN_ADDRESSES_NEW (insn
, -1);
6426 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6427 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6429 insn
= emit_label_after (pool_end
, pool
->pool_insn
);
6430 INSN_ADDRESSES_NEW (insn
, -1);
6432 s390_dump_pool (pool
, 1);
6436 /* Replace all literal pool references. */
6438 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6441 replace_ltrel_base (&PATTERN (insn
));
6443 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6445 rtx addr
, pool_ref
= NULL_RTX
;
6446 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6449 if (s390_execute_label (insn
))
6450 addr
= s390_find_execute (pool
, insn
);
6452 addr
= s390_find_constant (pool
, get_pool_constant (pool_ref
),
6453 get_pool_mode (pool_ref
));
6455 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
6456 INSN_CODE (insn
) = -1;
6462 /* Free the pool. */
6463 s390_free_pool (pool
);
6466 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6467 We have decided we cannot use this pool, so revert all changes
6468 to the current function that were done by s390_mainpool_start. */
6470 s390_mainpool_cancel (struct constant_pool
*pool
)
6472 /* We didn't actually change the instruction stream, so simply
6473 free the pool memory. */
6474 s390_free_pool (pool
);
6478 /* Chunkify the literal pool. */
6480 #define S390_POOL_CHUNK_MIN 0xc00
6481 #define S390_POOL_CHUNK_MAX 0xe00
6483 static struct constant_pool
*
6484 s390_chunkify_start (void)
6486 struct constant_pool
*curr_pool
= NULL
, *pool_list
= NULL
;
6489 rtx pending_ltrel
= NULL_RTX
;
6492 rtx (*gen_reload_base
) (rtx
, rtx
) =
6493 TARGET_CPU_ZARCH
? gen_reload_base_64
: gen_reload_base_31
;
6496 /* We need correct insn addresses. */
6498 shorten_branches (get_insns ());
6500 /* Scan all insns and move literals to pool chunks. */
6502 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6504 bool section_switch_p
= false;
6506 /* Check for pending LTREL_BASE. */
6509 rtx ltrel_base
= find_ltrel_base (PATTERN (insn
));
6512 gcc_assert (ltrel_base
== pending_ltrel
);
6513 pending_ltrel
= NULL_RTX
;
6517 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
6520 curr_pool
= s390_start_pool (&pool_list
, insn
);
6522 s390_add_execute (curr_pool
, insn
);
6523 s390_add_pool_insn (curr_pool
, insn
);
6525 else if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6527 rtx pool_ref
= NULL_RTX
;
6528 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6531 rtx constant
= get_pool_constant (pool_ref
);
6532 enum machine_mode mode
= get_pool_mode (pool_ref
);
6535 curr_pool
= s390_start_pool (&pool_list
, insn
);
6537 s390_add_constant (curr_pool
, constant
, mode
);
6538 s390_add_pool_insn (curr_pool
, insn
);
6540 /* Don't split the pool chunk between a LTREL_OFFSET load
6541 and the corresponding LTREL_BASE. */
6542 if (GET_CODE (constant
) == CONST
6543 && GET_CODE (XEXP (constant
, 0)) == UNSPEC
6544 && XINT (XEXP (constant
, 0), 1) == UNSPEC_LTREL_OFFSET
)
6546 gcc_assert (!pending_ltrel
);
6547 pending_ltrel
= pool_ref
;
6552 if (GET_CODE (insn
) == JUMP_INSN
|| GET_CODE (insn
) == CODE_LABEL
)
6555 s390_add_pool_insn (curr_pool
, insn
);
6556 /* An LTREL_BASE must follow within the same basic block. */
6557 gcc_assert (!pending_ltrel
);
6560 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_SWITCH_TEXT_SECTIONS
)
6561 section_switch_p
= true;
6564 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn
)
6565 || INSN_ADDRESSES (INSN_UID (insn
)) == -1)
6568 if (TARGET_CPU_ZARCH
)
6570 if (curr_pool
->size
< S390_POOL_CHUNK_MAX
)
6573 s390_end_pool (curr_pool
, NULL_RTX
);
6578 int chunk_size
= INSN_ADDRESSES (INSN_UID (insn
))
6579 - INSN_ADDRESSES (INSN_UID (curr_pool
->first_insn
))
6582 /* We will later have to insert base register reload insns.
6583 Those will have an effect on code size, which we need to
6584 consider here. This calculation makes rather pessimistic
6585 worst-case assumptions. */
6586 if (GET_CODE (insn
) == CODE_LABEL
)
6589 if (chunk_size
< S390_POOL_CHUNK_MIN
6590 && curr_pool
->size
< S390_POOL_CHUNK_MIN
6591 && !section_switch_p
)
6594 /* Pool chunks can only be inserted after BARRIERs ... */
6595 if (GET_CODE (insn
) == BARRIER
)
6597 s390_end_pool (curr_pool
, insn
);
6602 /* ... so if we don't find one in time, create one. */
6603 else if (chunk_size
> S390_POOL_CHUNK_MAX
6604 || curr_pool
->size
> S390_POOL_CHUNK_MAX
6605 || section_switch_p
)
6607 rtx label
, jump
, barrier
;
6609 if (!section_switch_p
)
6611 /* We can insert the barrier only after a 'real' insn. */
6612 if (GET_CODE (insn
) != INSN
&& GET_CODE (insn
) != CALL_INSN
)
6614 if (get_attr_length (insn
) == 0)
6616 /* Don't separate LTREL_BASE from the corresponding
6617 LTREL_OFFSET load. */
6623 gcc_assert (!pending_ltrel
);
6625 /* The old pool has to end before the section switch
6626 note in order to make it part of the current
6628 insn
= PREV_INSN (insn
);
6631 label
= gen_label_rtx ();
6632 jump
= emit_jump_insn_after (gen_jump (label
), insn
);
6633 barrier
= emit_barrier_after (jump
);
6634 insn
= emit_label_after (label
, barrier
);
6635 JUMP_LABEL (jump
) = label
;
6636 LABEL_NUSES (label
) = 1;
6638 INSN_ADDRESSES_NEW (jump
, -1);
6639 INSN_ADDRESSES_NEW (barrier
, -1);
6640 INSN_ADDRESSES_NEW (insn
, -1);
6642 s390_end_pool (curr_pool
, barrier
);
6650 s390_end_pool (curr_pool
, NULL_RTX
);
6651 gcc_assert (!pending_ltrel
);
6653 /* Find all labels that are branched into
6654 from an insn belonging to a different chunk. */
6656 far_labels
= BITMAP_ALLOC (NULL
);
6658 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6660 /* Labels marked with LABEL_PRESERVE_P can be target
6661 of non-local jumps, so we have to mark them.
6662 The same holds for named labels.
6664 Don't do that, however, if it is the label before
6667 if (GET_CODE (insn
) == CODE_LABEL
6668 && (LABEL_PRESERVE_P (insn
) || LABEL_NAME (insn
)))
6670 rtx vec_insn
= next_real_insn (insn
);
6671 rtx vec_pat
= vec_insn
&& GET_CODE (vec_insn
) == JUMP_INSN
?
6672 PATTERN (vec_insn
) : NULL_RTX
;
6674 || !(GET_CODE (vec_pat
) == ADDR_VEC
6675 || GET_CODE (vec_pat
) == ADDR_DIFF_VEC
))
6676 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (insn
));
6679 /* If we have a direct jump (conditional or unconditional)
6680 or a casesi jump, check all potential targets. */
6681 else if (GET_CODE (insn
) == JUMP_INSN
)
6683 rtx pat
= PATTERN (insn
);
6684 if (GET_CODE (pat
) == PARALLEL
&& XVECLEN (pat
, 0) > 2)
6685 pat
= XVECEXP (pat
, 0, 0);
6687 if (GET_CODE (pat
) == SET
)
6689 rtx label
= JUMP_LABEL (insn
);
6692 if (s390_find_pool (pool_list
, label
)
6693 != s390_find_pool (pool_list
, insn
))
6694 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
6697 else if (GET_CODE (pat
) == PARALLEL
6698 && XVECLEN (pat
, 0) == 2
6699 && GET_CODE (XVECEXP (pat
, 0, 0)) == SET
6700 && GET_CODE (XVECEXP (pat
, 0, 1)) == USE
6701 && GET_CODE (XEXP (XVECEXP (pat
, 0, 1), 0)) == LABEL_REF
)
6703 /* Find the jump table used by this casesi jump. */
6704 rtx vec_label
= XEXP (XEXP (XVECEXP (pat
, 0, 1), 0), 0);
6705 rtx vec_insn
= next_real_insn (vec_label
);
6706 rtx vec_pat
= vec_insn
&& GET_CODE (vec_insn
) == JUMP_INSN
?
6707 PATTERN (vec_insn
) : NULL_RTX
;
6709 && (GET_CODE (vec_pat
) == ADDR_VEC
6710 || GET_CODE (vec_pat
) == ADDR_DIFF_VEC
))
6712 int i
, diff_p
= GET_CODE (vec_pat
) == ADDR_DIFF_VEC
;
6714 for (i
= 0; i
< XVECLEN (vec_pat
, diff_p
); i
++)
6716 rtx label
= XEXP (XVECEXP (vec_pat
, diff_p
, i
), 0);
6718 if (s390_find_pool (pool_list
, label
)
6719 != s390_find_pool (pool_list
, insn
))
6720 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
6727 /* Insert base register reload insns before every pool. */
6729 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
6731 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
6733 rtx insn
= curr_pool
->first_insn
;
6734 INSN_ADDRESSES_NEW (emit_insn_before (new_insn
, insn
), -1);
6737 /* Insert base register reload insns at every far label. */
6739 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6740 if (GET_CODE (insn
) == CODE_LABEL
6741 && bitmap_bit_p (far_labels
, CODE_LABEL_NUMBER (insn
)))
6743 struct constant_pool
*pool
= s390_find_pool (pool_list
, insn
);
6746 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
6748 INSN_ADDRESSES_NEW (emit_insn_after (new_insn
, insn
), -1);
6753 BITMAP_FREE (far_labels
);
6756 /* Recompute insn addresses. */
6758 init_insn_lengths ();
6759 shorten_branches (get_insns ());
6764 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6765 After we have decided to use this list, finish implementing
6766 all changes to the current function as required. */
6769 s390_chunkify_finish (struct constant_pool
*pool_list
)
6771 struct constant_pool
*curr_pool
= NULL
;
6775 /* Replace all literal pool references. */
6777 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6780 replace_ltrel_base (&PATTERN (insn
));
6782 curr_pool
= s390_find_pool (pool_list
, insn
);
6786 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6788 rtx addr
, pool_ref
= NULL_RTX
;
6789 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6792 if (s390_execute_label (insn
))
6793 addr
= s390_find_execute (curr_pool
, insn
);
6795 addr
= s390_find_constant (curr_pool
,
6796 get_pool_constant (pool_ref
),
6797 get_pool_mode (pool_ref
));
6799 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
6800 INSN_CODE (insn
) = -1;
6805 /* Dump out all literal pools. */
6807 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
6808 s390_dump_pool (curr_pool
, 0);
6810 /* Free pool list. */
6814 struct constant_pool
*next
= pool_list
->next
;
6815 s390_free_pool (pool_list
);
6820 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6821 We have decided we cannot use this list, so revert all changes
6822 to the current function that were done by s390_chunkify_start. */
6825 s390_chunkify_cancel (struct constant_pool
*pool_list
)
6827 struct constant_pool
*curr_pool
= NULL
;
6830 /* Remove all pool placeholder insns. */
6832 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
6834 /* Did we insert an extra barrier? Remove it. */
6835 rtx barrier
= PREV_INSN (curr_pool
->pool_insn
);
6836 rtx jump
= barrier
? PREV_INSN (barrier
) : NULL_RTX
;
6837 rtx label
= NEXT_INSN (curr_pool
->pool_insn
);
6839 if (jump
&& GET_CODE (jump
) == JUMP_INSN
6840 && barrier
&& GET_CODE (barrier
) == BARRIER
6841 && label
&& GET_CODE (label
) == CODE_LABEL
6842 && GET_CODE (PATTERN (jump
)) == SET
6843 && SET_DEST (PATTERN (jump
)) == pc_rtx
6844 && GET_CODE (SET_SRC (PATTERN (jump
))) == LABEL_REF
6845 && XEXP (SET_SRC (PATTERN (jump
)), 0) == label
)
6848 remove_insn (barrier
);
6849 remove_insn (label
);
6852 remove_insn (curr_pool
->pool_insn
);
6855 /* Remove all base register reload insns. */
6857 for (insn
= get_insns (); insn
; )
6859 rtx next_insn
= NEXT_INSN (insn
);
6861 if (GET_CODE (insn
) == INSN
6862 && GET_CODE (PATTERN (insn
)) == SET
6863 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC
6864 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPEC_RELOAD_BASE
)
6870 /* Free pool list. */
6874 struct constant_pool
*next
= pool_list
->next
;
6875 s390_free_pool (pool_list
);
6880 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
6883 s390_output_pool_entry (rtx exp
, enum machine_mode mode
, unsigned int align
)
6887 switch (GET_MODE_CLASS (mode
))
6890 case MODE_DECIMAL_FLOAT
:
6891 gcc_assert (GET_CODE (exp
) == CONST_DOUBLE
);
6893 REAL_VALUE_FROM_CONST_DOUBLE (r
, exp
);
6894 assemble_real (r
, mode
, align
);
6898 assemble_integer (exp
, GET_MODE_SIZE (mode
), align
, 1);
6899 mark_symbol_refs_as_used (exp
);
6908 /* Return an RTL expression representing the value of the return address
6909 for the frame COUNT steps up from the current frame. FRAME is the
6910 frame pointer of that frame. */
6913 s390_return_addr_rtx (int count
, rtx frame ATTRIBUTE_UNUSED
)
6918 /* Without backchain, we fail for all but the current frame. */
6920 if (!TARGET_BACKCHAIN
&& count
> 0)
6923 /* For the current frame, we need to make sure the initial
6924 value of RETURN_REGNUM is actually saved. */
6928 /* On non-z architectures branch splitting could overwrite r14. */
6929 if (TARGET_CPU_ZARCH
)
6930 return get_hard_reg_initial_val (Pmode
, RETURN_REGNUM
);
6933 cfun_frame_layout
.save_return_addr_p
= true;
6934 return gen_rtx_MEM (Pmode
, return_address_pointer_rtx
);
6938 if (TARGET_PACKED_STACK
)
6939 offset
= -2 * UNITS_PER_LONG
;
6941 offset
= RETURN_REGNUM
* UNITS_PER_LONG
;
6943 addr
= plus_constant (frame
, offset
);
6944 addr
= memory_address (Pmode
, addr
);
6945 return gen_rtx_MEM (Pmode
, addr
);
6948 /* Return an RTL expression representing the back chain stored in
6949 the current stack frame. */
6952 s390_back_chain_rtx (void)
6956 gcc_assert (TARGET_BACKCHAIN
);
6958 if (TARGET_PACKED_STACK
)
6959 chain
= plus_constant (stack_pointer_rtx
,
6960 STACK_POINTER_OFFSET
- UNITS_PER_LONG
);
6962 chain
= stack_pointer_rtx
;
6964 chain
= gen_rtx_MEM (Pmode
, chain
);
6968 /* Find first call clobbered register unused in a function.
6969 This could be used as base register in a leaf function
6970 or for holding the return address before epilogue. */
6973 find_unused_clobbered_reg (void)
6976 for (i
= 0; i
< 6; i
++)
6977 if (!df_regs_ever_live_p (i
))
6983 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
6984 clobbered hard regs in SETREG. */
6987 s390_reg_clobbered_rtx (rtx setreg
, const_rtx set_insn ATTRIBUTE_UNUSED
, void *data
)
6989 int *regs_ever_clobbered
= (int *)data
;
6990 unsigned int i
, regno
;
6991 enum machine_mode mode
= GET_MODE (setreg
);
6993 if (GET_CODE (setreg
) == SUBREG
)
6995 rtx inner
= SUBREG_REG (setreg
);
6996 if (!GENERAL_REG_P (inner
))
6998 regno
= subreg_regno (setreg
);
7000 else if (GENERAL_REG_P (setreg
))
7001 regno
= REGNO (setreg
);
7006 i
< regno
+ HARD_REGNO_NREGS (regno
, mode
);
7008 regs_ever_clobbered
[i
] = 1;
7011 /* Walks through all basic blocks of the current function looking
7012 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
7013 of the passed integer array REGS_EVER_CLOBBERED are set to one for
7014 each of those regs. */
7017 s390_regs_ever_clobbered (int *regs_ever_clobbered
)
7023 memset (regs_ever_clobbered
, 0, 16 * sizeof (int));
7025 /* For non-leaf functions we have to consider all call clobbered regs to be
7027 if (!current_function_is_leaf
)
7029 for (i
= 0; i
< 16; i
++)
7030 regs_ever_clobbered
[i
] = call_really_used_regs
[i
];
7033 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
7034 this work is done by liveness analysis (mark_regs_live_at_end).
7035 Special care is needed for functions containing landing pads. Landing pads
7036 may use the eh registers, but the code which sets these registers is not
7037 contained in that function. Hence s390_regs_ever_clobbered is not able to
7038 deal with this automatically. */
7039 if (crtl
->calls_eh_return
|| cfun
->machine
->has_landing_pad_p
)
7040 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
7041 if (crtl
->calls_eh_return
7042 || (cfun
->machine
->has_landing_pad_p
7043 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i
))))
7044 regs_ever_clobbered
[EH_RETURN_DATA_REGNO (i
)] = 1;
7046 /* For nonlocal gotos all call-saved registers have to be saved.
7047 This flag is also set for the unwinding code in libgcc.
7048 See expand_builtin_unwind_init. For regs_ever_live this is done by
7050 if (cfun
->has_nonlocal_label
)
7051 for (i
= 0; i
< 16; i
++)
7052 if (!call_really_used_regs
[i
])
7053 regs_ever_clobbered
[i
] = 1;
7055 FOR_EACH_BB (cur_bb
)
7057 FOR_BB_INSNS (cur_bb
, cur_insn
)
7059 if (INSN_P (cur_insn
))
7060 note_stores (PATTERN (cur_insn
),
7061 s390_reg_clobbered_rtx
,
7062 regs_ever_clobbered
);
7067 /* Determine the frame area which actually has to be accessed
7068 in the function epilogue. The values are stored at the
7069 given pointers AREA_BOTTOM (address of the lowest used stack
7070 address) and AREA_TOP (address of the first item which does
7071 not belong to the stack frame). */
7074 s390_frame_area (int *area_bottom
, int *area_top
)
7082 if (cfun_frame_layout
.first_restore_gpr
!= -1)
7084 b
= (cfun_frame_layout
.gprs_offset
7085 + cfun_frame_layout
.first_restore_gpr
* UNITS_PER_LONG
);
7086 t
= b
+ (cfun_frame_layout
.last_restore_gpr
7087 - cfun_frame_layout
.first_restore_gpr
+ 1) * UNITS_PER_LONG
;
7090 if (TARGET_64BIT
&& cfun_save_high_fprs_p
)
7092 b
= MIN (b
, cfun_frame_layout
.f8_offset
);
7093 t
= MAX (t
, (cfun_frame_layout
.f8_offset
7094 + cfun_frame_layout
.high_fprs
* 8));
7098 for (i
= 2; i
< 4; i
++)
7099 if (cfun_fpr_bit_p (i
))
7101 b
= MIN (b
, cfun_frame_layout
.f4_offset
+ (i
- 2) * 8);
7102 t
= MAX (t
, cfun_frame_layout
.f4_offset
+ (i
- 1) * 8);
7109 /* Fill cfun->machine with info about register usage of current function.
7110 Return in CLOBBERED_REGS which GPRs are currently considered set. */
7113 s390_register_info (int clobbered_regs
[])
7117 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
7118 cfun_frame_layout
.fpr_bitmap
= 0;
7119 cfun_frame_layout
.high_fprs
= 0;
7121 for (i
= 24; i
< 32; i
++)
7122 if (df_regs_ever_live_p (i
) && !global_regs
[i
])
7124 cfun_set_fpr_bit (i
- 16);
7125 cfun_frame_layout
.high_fprs
++;
7128 /* Find first and last gpr to be saved. We trust regs_ever_live
7129 data, except that we don't save and restore global registers.
7131 Also, all registers with special meaning to the compiler need
7132 to be handled extra. */
7134 s390_regs_ever_clobbered (clobbered_regs
);
7136 for (i
= 0; i
< 16; i
++)
7137 clobbered_regs
[i
] = clobbered_regs
[i
] && !global_regs
[i
] && !fixed_regs
[i
];
7139 if (frame_pointer_needed
)
7140 clobbered_regs
[HARD_FRAME_POINTER_REGNUM
] = 1;
7143 clobbered_regs
[PIC_OFFSET_TABLE_REGNUM
]
7144 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
);
7146 clobbered_regs
[BASE_REGNUM
]
7147 |= (cfun
->machine
->base_reg
7148 && REGNO (cfun
->machine
->base_reg
) == BASE_REGNUM
);
7150 clobbered_regs
[RETURN_REGNUM
]
7151 |= (!current_function_is_leaf
7152 || TARGET_TPF_PROFILING
7153 || cfun
->machine
->split_branches_pending_p
7154 || cfun_frame_layout
.save_return_addr_p
7155 || crtl
->calls_eh_return
7158 clobbered_regs
[STACK_POINTER_REGNUM
]
7159 |= (!current_function_is_leaf
7160 || TARGET_TPF_PROFILING
7161 || cfun_save_high_fprs_p
7162 || get_frame_size () > 0
7163 || cfun
->calls_alloca
7166 for (i
= 6; i
< 16; i
++)
7167 if (df_regs_ever_live_p (i
) || clobbered_regs
[i
])
7169 for (j
= 15; j
> i
; j
--)
7170 if (df_regs_ever_live_p (j
) || clobbered_regs
[j
])
7175 /* Nothing to save/restore. */
7176 cfun_frame_layout
.first_save_gpr_slot
= -1;
7177 cfun_frame_layout
.last_save_gpr_slot
= -1;
7178 cfun_frame_layout
.first_save_gpr
= -1;
7179 cfun_frame_layout
.first_restore_gpr
= -1;
7180 cfun_frame_layout
.last_save_gpr
= -1;
7181 cfun_frame_layout
.last_restore_gpr
= -1;
7185 /* Save slots for gprs from i to j. */
7186 cfun_frame_layout
.first_save_gpr_slot
= i
;
7187 cfun_frame_layout
.last_save_gpr_slot
= j
;
7189 for (i
= cfun_frame_layout
.first_save_gpr_slot
;
7190 i
< cfun_frame_layout
.last_save_gpr_slot
+ 1;
7192 if (clobbered_regs
[i
])
7195 for (j
= cfun_frame_layout
.last_save_gpr_slot
; j
> i
; j
--)
7196 if (clobbered_regs
[j
])
7199 if (i
== cfun_frame_layout
.last_save_gpr_slot
+ 1)
7201 /* Nothing to save/restore. */
7202 cfun_frame_layout
.first_save_gpr
= -1;
7203 cfun_frame_layout
.first_restore_gpr
= -1;
7204 cfun_frame_layout
.last_save_gpr
= -1;
7205 cfun_frame_layout
.last_restore_gpr
= -1;
7209 /* Save / Restore from gpr i to j. */
7210 cfun_frame_layout
.first_save_gpr
= i
;
7211 cfun_frame_layout
.first_restore_gpr
= i
;
7212 cfun_frame_layout
.last_save_gpr
= j
;
7213 cfun_frame_layout
.last_restore_gpr
= j
;
7219 /* Varargs functions need to save gprs 2 to 6. */
7220 if (cfun
->va_list_gpr_size
7221 && crtl
->args
.info
.gprs
< GP_ARG_NUM_REG
)
7223 int min_gpr
= crtl
->args
.info
.gprs
;
7224 int max_gpr
= min_gpr
+ cfun
->va_list_gpr_size
;
7225 if (max_gpr
> GP_ARG_NUM_REG
)
7226 max_gpr
= GP_ARG_NUM_REG
;
7228 if (cfun_frame_layout
.first_save_gpr
== -1
7229 || cfun_frame_layout
.first_save_gpr
> 2 + min_gpr
)
7231 cfun_frame_layout
.first_save_gpr
= 2 + min_gpr
;
7232 cfun_frame_layout
.first_save_gpr_slot
= 2 + min_gpr
;
7235 if (cfun_frame_layout
.last_save_gpr
== -1
7236 || cfun_frame_layout
.last_save_gpr
< 2 + max_gpr
- 1)
7238 cfun_frame_layout
.last_save_gpr
= 2 + max_gpr
- 1;
7239 cfun_frame_layout
.last_save_gpr_slot
= 2 + max_gpr
- 1;
7243 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
7244 if (TARGET_HARD_FLOAT
&& cfun
->va_list_fpr_size
7245 && crtl
->args
.info
.fprs
< FP_ARG_NUM_REG
)
7247 int min_fpr
= crtl
->args
.info
.fprs
;
7248 int max_fpr
= min_fpr
+ cfun
->va_list_fpr_size
;
7249 if (max_fpr
> FP_ARG_NUM_REG
)
7250 max_fpr
= FP_ARG_NUM_REG
;
7252 /* ??? This is currently required to ensure proper location
7253 of the fpr save slots within the va_list save area. */
7254 if (TARGET_PACKED_STACK
)
7257 for (i
= min_fpr
; i
< max_fpr
; i
++)
7258 cfun_set_fpr_bit (i
);
7263 for (i
= 2; i
< 4; i
++)
7264 if (df_regs_ever_live_p (i
+ 16) && !global_regs
[i
+ 16])
7265 cfun_set_fpr_bit (i
);
7268 /* Fill cfun->machine with info about frame of current function. */
7271 s390_frame_info (void)
7275 cfun_frame_layout
.frame_size
= get_frame_size ();
7276 if (!TARGET_64BIT
&& cfun_frame_layout
.frame_size
> 0x7fff0000)
7277 fatal_error ("total size of local variables exceeds architecture limit");
7279 if (!TARGET_PACKED_STACK
)
7281 cfun_frame_layout
.backchain_offset
= 0;
7282 cfun_frame_layout
.f0_offset
= 16 * UNITS_PER_LONG
;
7283 cfun_frame_layout
.f4_offset
= cfun_frame_layout
.f0_offset
+ 2 * 8;
7284 cfun_frame_layout
.f8_offset
= -cfun_frame_layout
.high_fprs
* 8;
7285 cfun_frame_layout
.gprs_offset
= (cfun_frame_layout
.first_save_gpr_slot
7288 else if (TARGET_BACKCHAIN
) /* kernel stack layout */
7290 cfun_frame_layout
.backchain_offset
= (STACK_POINTER_OFFSET
7292 cfun_frame_layout
.gprs_offset
7293 = (cfun_frame_layout
.backchain_offset
7294 - (STACK_POINTER_REGNUM
- cfun_frame_layout
.first_save_gpr_slot
+ 1)
7299 cfun_frame_layout
.f4_offset
7300 = (cfun_frame_layout
.gprs_offset
7301 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7303 cfun_frame_layout
.f0_offset
7304 = (cfun_frame_layout
.f4_offset
7305 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7309 /* On 31 bit we have to care about alignment of the
7310 floating point regs to provide fastest access. */
7311 cfun_frame_layout
.f0_offset
7312 = ((cfun_frame_layout
.gprs_offset
7313 & ~(STACK_BOUNDARY
/ BITS_PER_UNIT
- 1))
7314 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7316 cfun_frame_layout
.f4_offset
7317 = (cfun_frame_layout
.f0_offset
7318 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7321 else /* no backchain */
7323 cfun_frame_layout
.f4_offset
7324 = (STACK_POINTER_OFFSET
7325 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7327 cfun_frame_layout
.f0_offset
7328 = (cfun_frame_layout
.f4_offset
7329 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7331 cfun_frame_layout
.gprs_offset
7332 = cfun_frame_layout
.f0_offset
- cfun_gprs_save_area_size
;
7335 if (current_function_is_leaf
7336 && !TARGET_TPF_PROFILING
7337 && cfun_frame_layout
.frame_size
== 0
7338 && !cfun_save_high_fprs_p
7339 && !cfun
->calls_alloca
7343 if (!TARGET_PACKED_STACK
)
7344 cfun_frame_layout
.frame_size
+= (STACK_POINTER_OFFSET
7345 + crtl
->outgoing_args_size
7346 + cfun_frame_layout
.high_fprs
* 8);
7349 if (TARGET_BACKCHAIN
)
7350 cfun_frame_layout
.frame_size
+= UNITS_PER_LONG
;
7352 /* No alignment trouble here because f8-f15 are only saved under
7354 cfun_frame_layout
.f8_offset
= (MIN (MIN (cfun_frame_layout
.f0_offset
,
7355 cfun_frame_layout
.f4_offset
),
7356 cfun_frame_layout
.gprs_offset
)
7357 - cfun_frame_layout
.high_fprs
* 8);
7359 cfun_frame_layout
.frame_size
+= cfun_frame_layout
.high_fprs
* 8;
7361 for (i
= 0; i
< 8; i
++)
7362 if (cfun_fpr_bit_p (i
))
7363 cfun_frame_layout
.frame_size
+= 8;
7365 cfun_frame_layout
.frame_size
+= cfun_gprs_save_area_size
;
7367 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7368 the frame size to sustain 8 byte alignment of stack frames. */
7369 cfun_frame_layout
.frame_size
= ((cfun_frame_layout
.frame_size
+
7370 STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
7371 & ~(STACK_BOUNDARY
/ BITS_PER_UNIT
- 1));
7373 cfun_frame_layout
.frame_size
+= crtl
->outgoing_args_size
;
7377 /* Generate frame layout. Fills in register and frame data for the current
7378 function in cfun->machine. This routine can be called multiple times;
7379 it will re-do the complete frame layout every time. */
7382 s390_init_frame_layout (void)
7384 HOST_WIDE_INT frame_size
;
7386 int clobbered_regs
[16];
7388 /* On S/390 machines, we may need to perform branch splitting, which
7389 will require both base and return address register. We have no
7390 choice but to assume we're going to need them until right at the
7391 end of the machine dependent reorg phase. */
7392 if (!TARGET_CPU_ZARCH
)
7393 cfun
->machine
->split_branches_pending_p
= true;
7397 frame_size
= cfun_frame_layout
.frame_size
;
7399 /* Try to predict whether we'll need the base register. */
7400 base_used
= cfun
->machine
->split_branches_pending_p
7401 || crtl
->uses_const_pool
7402 || (!DISP_IN_RANGE (frame_size
)
7403 && !CONST_OK_FOR_K (frame_size
));
7405 /* Decide which register to use as literal pool base. In small
7406 leaf functions, try to use an unused call-clobbered register
7407 as base register to avoid save/restore overhead. */
7409 cfun
->machine
->base_reg
= NULL_RTX
;
7410 else if (current_function_is_leaf
&& !df_regs_ever_live_p (5))
7411 cfun
->machine
->base_reg
= gen_rtx_REG (Pmode
, 5);
7413 cfun
->machine
->base_reg
= gen_rtx_REG (Pmode
, BASE_REGNUM
);
7415 s390_register_info (clobbered_regs
);
7418 while (frame_size
!= cfun_frame_layout
.frame_size
);
7421 /* Update frame layout. Recompute actual register save data based on
7422 current info and update regs_ever_live for the special registers.
7423 May be called multiple times, but may never cause *more* registers
7424 to be saved than s390_init_frame_layout allocated room for. */
7427 s390_update_frame_layout (void)
7429 int clobbered_regs
[16];
7431 s390_register_info (clobbered_regs
);
7433 df_set_regs_ever_live (BASE_REGNUM
,
7434 clobbered_regs
[BASE_REGNUM
] ? true : false);
7435 df_set_regs_ever_live (RETURN_REGNUM
,
7436 clobbered_regs
[RETURN_REGNUM
] ? true : false);
7437 df_set_regs_ever_live (STACK_POINTER_REGNUM
,
7438 clobbered_regs
[STACK_POINTER_REGNUM
] ? true : false);
7440 if (cfun
->machine
->base_reg
)
7441 df_set_regs_ever_live (REGNO (cfun
->machine
->base_reg
), true);
7444 /* Return true if it is legal to put a value with MODE into REGNO. */
7447 s390_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
7449 switch (REGNO_REG_CLASS (regno
))
7452 if (REGNO_PAIR_OK (regno
, mode
))
7454 if (mode
== SImode
|| mode
== DImode
)
7457 if (FLOAT_MODE_P (mode
) && GET_MODE_CLASS (mode
) != MODE_VECTOR_FLOAT
)
7462 if (FRAME_REGNO_P (regno
) && mode
== Pmode
)
7467 if (REGNO_PAIR_OK (regno
, mode
))
7470 || (mode
!= TFmode
&& mode
!= TCmode
&& mode
!= TDmode
))
7475 if (GET_MODE_CLASS (mode
) == MODE_CC
)
7479 if (REGNO_PAIR_OK (regno
, mode
))
7481 if (mode
== SImode
|| mode
== Pmode
)
7492 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
7495 s390_hard_regno_rename_ok (unsigned int old_reg
, unsigned int new_reg
)
7497 /* Once we've decided upon a register to use as base register, it must
7498 no longer be used for any other purpose. */
7499 if (cfun
->machine
->base_reg
)
7500 if (REGNO (cfun
->machine
->base_reg
) == old_reg
7501 || REGNO (cfun
->machine
->base_reg
) == new_reg
)
7507 /* Maximum number of registers to represent a value of mode MODE
7508 in a register of class RCLASS. */
7511 s390_class_max_nregs (enum reg_class rclass
, enum machine_mode mode
)
7516 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
7517 return 2 * ((GET_MODE_SIZE (mode
) / 2 + 8 - 1) / 8);
7519 return (GET_MODE_SIZE (mode
) + 8 - 1) / 8;
7521 return (GET_MODE_SIZE (mode
) + 4 - 1) / 4;
7525 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
7528 /* Return true if register FROM can be eliminated via register TO. */
7531 s390_can_eliminate (const int from
, const int to
)
7533 /* On zSeries machines, we have not marked the base register as fixed.
7534 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
7535 If a function requires the base register, we say here that this
7536 elimination cannot be performed. This will cause reload to free
7537 up the base register (as if it were fixed). On the other hand,
7538 if the current function does *not* require the base register, we
7539 say here the elimination succeeds, which in turn allows reload
7540 to allocate the base register for any other purpose. */
7541 if (from
== BASE_REGNUM
&& to
== BASE_REGNUM
)
7543 if (TARGET_CPU_ZARCH
)
7545 s390_init_frame_layout ();
7546 return cfun
->machine
->base_reg
== NULL_RTX
;
7552 /* Everything else must point into the stack frame. */
7553 gcc_assert (to
== STACK_POINTER_REGNUM
7554 || to
== HARD_FRAME_POINTER_REGNUM
);
7556 gcc_assert (from
== FRAME_POINTER_REGNUM
7557 || from
== ARG_POINTER_REGNUM
7558 || from
== RETURN_ADDRESS_POINTER_REGNUM
);
7560 /* Make sure we actually saved the return address. */
7561 if (from
== RETURN_ADDRESS_POINTER_REGNUM
)
7562 if (!crtl
->calls_eh_return
7564 && !cfun_frame_layout
.save_return_addr_p
)
7570 /* Return offset between register FROM and TO initially after prolog. */
7573 s390_initial_elimination_offset (int from
, int to
)
7575 HOST_WIDE_INT offset
;
7578 /* ??? Why are we called for non-eliminable pairs? */
7579 if (!s390_can_eliminate (from
, to
))
7584 case FRAME_POINTER_REGNUM
:
7585 offset
= (get_frame_size()
7586 + STACK_POINTER_OFFSET
7587 + crtl
->outgoing_args_size
);
7590 case ARG_POINTER_REGNUM
:
7591 s390_init_frame_layout ();
7592 offset
= cfun_frame_layout
.frame_size
+ STACK_POINTER_OFFSET
;
7595 case RETURN_ADDRESS_POINTER_REGNUM
:
7596 s390_init_frame_layout ();
7597 index
= RETURN_REGNUM
- cfun_frame_layout
.first_save_gpr_slot
;
7598 gcc_assert (index
>= 0);
7599 offset
= cfun_frame_layout
.frame_size
+ cfun_frame_layout
.gprs_offset
;
7600 offset
+= index
* UNITS_PER_LONG
;
7614 /* Emit insn to save fpr REGNUM at offset OFFSET relative
7615 to register BASE. Return generated insn. */
7618 save_fpr (rtx base
, int offset
, int regnum
)
7621 addr
= gen_rtx_MEM (DFmode
, plus_constant (base
, offset
));
7623 if (regnum
>= 16 && regnum
<= (16 + FP_ARG_NUM_REG
))
7624 set_mem_alias_set (addr
, get_varargs_alias_set ());
7626 set_mem_alias_set (addr
, get_frame_alias_set ());
7628 return emit_move_insn (addr
, gen_rtx_REG (DFmode
, regnum
));
7631 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
7632 to register BASE. Return generated insn. */
7635 restore_fpr (rtx base
, int offset
, int regnum
)
7638 addr
= gen_rtx_MEM (DFmode
, plus_constant (base
, offset
));
7639 set_mem_alias_set (addr
, get_frame_alias_set ());
7641 return emit_move_insn (gen_rtx_REG (DFmode
, regnum
), addr
);
7644 /* Return true if REGNO is a global register, but not one
7645 of the special ones that need to be saved/restored in anyway. */
7648 global_not_special_regno_p (int regno
)
7650 return (global_regs
[regno
]
7651 /* These registers are special and need to be
7652 restored in any case. */
7653 && !(regno
== STACK_POINTER_REGNUM
7654 || regno
== RETURN_REGNUM
7655 || regno
== BASE_REGNUM
7656 || (flag_pic
&& regno
== (int)PIC_OFFSET_TABLE_REGNUM
)));
7659 /* Generate insn to save registers FIRST to LAST into
7660 the register save area located at offset OFFSET
7661 relative to register BASE. */
7664 save_gprs (rtx base
, int offset
, int first
, int last
)
7666 rtx addr
, insn
, note
;
7669 addr
= plus_constant (base
, offset
);
7670 addr
= gen_rtx_MEM (Pmode
, addr
);
7672 set_mem_alias_set (addr
, get_frame_alias_set ());
7674 /* Special-case single register. */
7678 insn
= gen_movdi (addr
, gen_rtx_REG (Pmode
, first
));
7680 insn
= gen_movsi (addr
, gen_rtx_REG (Pmode
, first
));
7682 if (!global_not_special_regno_p (first
))
7683 RTX_FRAME_RELATED_P (insn
) = 1;
7688 insn
= gen_store_multiple (addr
,
7689 gen_rtx_REG (Pmode
, first
),
7690 GEN_INT (last
- first
+ 1));
7692 if (first
<= 6 && cfun
->stdarg
)
7693 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
7695 rtx mem
= XEXP (XVECEXP (PATTERN (insn
), 0, i
), 0);
7698 set_mem_alias_set (mem
, get_varargs_alias_set ());
7701 /* We need to set the FRAME_RELATED flag on all SETs
7702 inside the store-multiple pattern.
7704 However, we must not emit DWARF records for registers 2..5
7705 if they are stored for use by variable arguments ...
7707 ??? Unfortunately, it is not enough to simply not the
7708 FRAME_RELATED flags for those SETs, because the first SET
7709 of the PARALLEL is always treated as if it had the flag
7710 set, even if it does not. Therefore we emit a new pattern
7711 without those registers as REG_FRAME_RELATED_EXPR note. */
7713 if (first
>= 6 && !global_not_special_regno_p (first
))
7715 rtx pat
= PATTERN (insn
);
7717 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
7718 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
7719 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat
,
7721 RTX_FRAME_RELATED_P (XVECEXP (pat
, 0, i
)) = 1;
7723 RTX_FRAME_RELATED_P (insn
) = 1;
7729 for (start
= first
>= 6 ? first
: 6; start
<= last
; start
++)
7730 if (!global_not_special_regno_p (start
))
7736 addr
= plus_constant (base
, offset
+ (start
- first
) * UNITS_PER_LONG
);
7737 note
= gen_store_multiple (gen_rtx_MEM (Pmode
, addr
),
7738 gen_rtx_REG (Pmode
, start
),
7739 GEN_INT (last
- start
+ 1));
7740 note
= PATTERN (note
);
7742 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note
);
7744 for (i
= 0; i
< XVECLEN (note
, 0); i
++)
7745 if (GET_CODE (XVECEXP (note
, 0, i
)) == SET
7746 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note
,
7748 RTX_FRAME_RELATED_P (XVECEXP (note
, 0, i
)) = 1;
7750 RTX_FRAME_RELATED_P (insn
) = 1;
7756 /* Generate insn to restore registers FIRST to LAST from
7757 the register save area located at offset OFFSET
7758 relative to register BASE. */
7761 restore_gprs (rtx base
, int offset
, int first
, int last
)
7765 addr
= plus_constant (base
, offset
);
7766 addr
= gen_rtx_MEM (Pmode
, addr
);
7767 set_mem_alias_set (addr
, get_frame_alias_set ());
7769 /* Special-case single register. */
7773 insn
= gen_movdi (gen_rtx_REG (Pmode
, first
), addr
);
7775 insn
= gen_movsi (gen_rtx_REG (Pmode
, first
), addr
);
7780 insn
= gen_load_multiple (gen_rtx_REG (Pmode
, first
),
7782 GEN_INT (last
- first
+ 1));
7786 /* Return insn sequence to load the GOT register. */
7788 static GTY(()) rtx got_symbol
;
7790 s390_load_got (void)
7796 got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
7797 SYMBOL_REF_FLAGS (got_symbol
) = SYMBOL_FLAG_LOCAL
;
7802 if (TARGET_CPU_ZARCH
)
7804 emit_move_insn (pic_offset_table_rtx
, got_symbol
);
7810 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, got_symbol
),
7811 UNSPEC_LTREL_OFFSET
);
7812 offset
= gen_rtx_CONST (Pmode
, offset
);
7813 offset
= force_const_mem (Pmode
, offset
);
7815 emit_move_insn (pic_offset_table_rtx
, offset
);
7817 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, XEXP (offset
, 0)),
7819 offset
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, offset
);
7821 emit_move_insn (pic_offset_table_rtx
, offset
);
7824 insns
= get_insns ();
7829 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
7830 and the change to the stack pointer. */
7833 s390_emit_stack_tie (void)
7835 rtx mem
= gen_frame_mem (BLKmode
,
7836 gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
));
7838 emit_insn (gen_stack_tie (mem
));
7841 /* Expand the prologue into a bunch of separate insns. */
7844 s390_emit_prologue (void)
7852 /* Complete frame layout. */
7854 s390_update_frame_layout ();
7856 /* Annotate all constant pool references to let the scheduler know
7857 they implicitly use the base register. */
7859 push_topmost_sequence ();
7861 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
7864 annotate_constant_pool_refs (&PATTERN (insn
));
7865 df_insn_rescan (insn
);
7868 pop_topmost_sequence ();
7870 /* Choose best register to use for temp use within prologue.
7871 See below for why TPF must use the register 1. */
7873 if (!has_hard_reg_initial_val (Pmode
, RETURN_REGNUM
)
7874 && !current_function_is_leaf
7875 && !TARGET_TPF_PROFILING
)
7876 temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
7878 temp_reg
= gen_rtx_REG (Pmode
, 1);
7880 /* Save call saved gprs. */
7881 if (cfun_frame_layout
.first_save_gpr
!= -1)
7883 insn
= save_gprs (stack_pointer_rtx
,
7884 cfun_frame_layout
.gprs_offset
+
7885 UNITS_PER_LONG
* (cfun_frame_layout
.first_save_gpr
7886 - cfun_frame_layout
.first_save_gpr_slot
),
7887 cfun_frame_layout
.first_save_gpr
,
7888 cfun_frame_layout
.last_save_gpr
);
7892 /* Dummy insn to mark literal pool slot. */
7894 if (cfun
->machine
->base_reg
)
7895 emit_insn (gen_main_pool (cfun
->machine
->base_reg
));
7897 offset
= cfun_frame_layout
.f0_offset
;
7899 /* Save f0 and f2. */
7900 for (i
= 0; i
< 2; i
++)
7902 if (cfun_fpr_bit_p (i
))
7904 save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
7907 else if (!TARGET_PACKED_STACK
)
7911 /* Save f4 and f6. */
7912 offset
= cfun_frame_layout
.f4_offset
;
7913 for (i
= 2; i
< 4; i
++)
7915 if (cfun_fpr_bit_p (i
))
7917 insn
= save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
7920 /* If f4 and f6 are call clobbered they are saved due to stdargs and
7921 therefore are not frame related. */
7922 if (!call_really_used_regs
[i
+ 16])
7923 RTX_FRAME_RELATED_P (insn
) = 1;
7925 else if (!TARGET_PACKED_STACK
)
7929 if (TARGET_PACKED_STACK
7930 && cfun_save_high_fprs_p
7931 && cfun_frame_layout
.f8_offset
+ cfun_frame_layout
.high_fprs
* 8 > 0)
7933 offset
= (cfun_frame_layout
.f8_offset
7934 + (cfun_frame_layout
.high_fprs
- 1) * 8);
7936 for (i
= 15; i
> 7 && offset
>= 0; i
--)
7937 if (cfun_fpr_bit_p (i
))
7939 insn
= save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
7941 RTX_FRAME_RELATED_P (insn
) = 1;
7944 if (offset
>= cfun_frame_layout
.f8_offset
)
7948 if (!TARGET_PACKED_STACK
)
7949 next_fpr
= cfun_save_high_fprs_p
? 31 : 0;
7951 if (flag_stack_usage
)
7952 current_function_static_stack_size
= cfun_frame_layout
.frame_size
;
7954 /* Decrement stack pointer. */
7956 if (cfun_frame_layout
.frame_size
> 0)
7958 rtx frame_off
= GEN_INT (-cfun_frame_layout
.frame_size
);
7961 if (s390_stack_size
)
7963 HOST_WIDE_INT stack_guard
;
7965 if (s390_stack_guard
)
7966 stack_guard
= s390_stack_guard
;
7969 /* If no value for stack guard is provided the smallest power of 2
7970 larger than the current frame size is chosen. */
7972 while (stack_guard
< cfun_frame_layout
.frame_size
)
7976 if (cfun_frame_layout
.frame_size
>= s390_stack_size
)
7978 warning (0, "frame size of function %qs is "
7979 HOST_WIDE_INT_PRINT_DEC
7980 " bytes exceeding user provided stack limit of "
7981 HOST_WIDE_INT_PRINT_DEC
" bytes. "
7982 "An unconditional trap is added.",
7983 current_function_name(), cfun_frame_layout
.frame_size
,
7985 emit_insn (gen_trap ());
7989 /* stack_guard has to be smaller than s390_stack_size.
7990 Otherwise we would emit an AND with zero which would
7991 not match the test under mask pattern. */
7992 if (stack_guard
>= s390_stack_size
)
7994 warning (0, "frame size of function %qs is "
7995 HOST_WIDE_INT_PRINT_DEC
7996 " bytes which is more than half the stack size. "
7997 "The dynamic check would not be reliable. "
7998 "No check emitted for this function.",
7999 current_function_name(),
8000 cfun_frame_layout
.frame_size
);
8004 HOST_WIDE_INT stack_check_mask
= ((s390_stack_size
- 1)
8005 & ~(stack_guard
- 1));
8007 rtx t
= gen_rtx_AND (Pmode
, stack_pointer_rtx
,
8008 GEN_INT (stack_check_mask
));
8010 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode
,
8012 t
, const0_rtx
, const0_rtx
));
8014 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode
,
8016 t
, const0_rtx
, const0_rtx
));
8021 if (s390_warn_framesize
> 0
8022 && cfun_frame_layout
.frame_size
>= s390_warn_framesize
)
8023 warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC
" bytes",
8024 current_function_name (), cfun_frame_layout
.frame_size
);
8026 if (s390_warn_dynamicstack_p
&& cfun
->calls_alloca
)
8027 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
8029 /* Save incoming stack pointer into temp reg. */
8030 if (TARGET_BACKCHAIN
|| next_fpr
)
8031 insn
= emit_insn (gen_move_insn (temp_reg
, stack_pointer_rtx
));
8033 /* Subtract frame size from stack pointer. */
8035 if (DISP_IN_RANGE (INTVAL (frame_off
)))
8037 insn
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8038 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
8040 insn
= emit_insn (insn
);
8044 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
8045 frame_off
= force_const_mem (Pmode
, frame_off
);
8047 insn
= emit_insn (gen_add2_insn (stack_pointer_rtx
, frame_off
));
8048 annotate_constant_pool_refs (&PATTERN (insn
));
8051 RTX_FRAME_RELATED_P (insn
) = 1;
8052 real_frame_off
= GEN_INT (-cfun_frame_layout
.frame_size
);
8053 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
8054 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8055 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
8058 /* Set backchain. */
8060 if (TARGET_BACKCHAIN
)
8062 if (cfun_frame_layout
.backchain_offset
)
8063 addr
= gen_rtx_MEM (Pmode
,
8064 plus_constant (stack_pointer_rtx
,
8065 cfun_frame_layout
.backchain_offset
));
8067 addr
= gen_rtx_MEM (Pmode
, stack_pointer_rtx
);
8068 set_mem_alias_set (addr
, get_frame_alias_set ());
8069 insn
= emit_insn (gen_move_insn (addr
, temp_reg
));
8072 /* If we support non-call exceptions (e.g. for Java),
8073 we need to make sure the backchain pointer is set up
8074 before any possibly trapping memory access. */
8075 if (TARGET_BACKCHAIN
&& cfun
->can_throw_non_call_exceptions
)
8077 addr
= gen_rtx_MEM (BLKmode
, gen_rtx_SCRATCH (VOIDmode
));
8078 emit_clobber (addr
);
8082 /* Save fprs 8 - 15 (64 bit ABI). */
8084 if (cfun_save_high_fprs_p
&& next_fpr
)
8086 /* If the stack might be accessed through a different register
8087 we have to make sure that the stack pointer decrement is not
8088 moved below the use of the stack slots. */
8089 s390_emit_stack_tie ();
8091 insn
= emit_insn (gen_add2_insn (temp_reg
,
8092 GEN_INT (cfun_frame_layout
.f8_offset
)));
8096 for (i
= 24; i
<= next_fpr
; i
++)
8097 if (cfun_fpr_bit_p (i
- 16))
8099 rtx addr
= plus_constant (stack_pointer_rtx
,
8100 cfun_frame_layout
.frame_size
8101 + cfun_frame_layout
.f8_offset
8104 insn
= save_fpr (temp_reg
, offset
, i
);
8106 RTX_FRAME_RELATED_P (insn
) = 1;
8107 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
8108 gen_rtx_SET (VOIDmode
,
8109 gen_rtx_MEM (DFmode
, addr
),
8110 gen_rtx_REG (DFmode
, i
)));
8114 /* Set frame pointer, if needed. */
8116 if (frame_pointer_needed
)
8118 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
8119 RTX_FRAME_RELATED_P (insn
) = 1;
8122 /* Set up got pointer, if needed. */
8124 if (flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
8126 rtx insns
= s390_load_got ();
8128 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
8129 annotate_constant_pool_refs (&PATTERN (insn
));
8134 if (TARGET_TPF_PROFILING
)
8136 /* Generate a BAS instruction to serve as a function
8137 entry intercept to facilitate the use of tracing
8138 algorithms located at the branch target. */
8139 emit_insn (gen_prologue_tpf ());
8141 /* Emit a blockage here so that all code
8142 lies between the profiling mechanisms. */
8143 emit_insn (gen_blockage ());
8147 /* Expand the epilogue into a bunch of separate insns. */
8150 s390_emit_epilogue (bool sibcall
)
8152 rtx frame_pointer
, return_reg
, cfa_restores
= NULL_RTX
;
8153 int area_bottom
, area_top
, offset
= 0;
8158 if (TARGET_TPF_PROFILING
)
8161 /* Generate a BAS instruction to serve as a function
8162 entry intercept to facilitate the use of tracing
8163 algorithms located at the branch target. */
8165 /* Emit a blockage here so that all code
8166 lies between the profiling mechanisms. */
8167 emit_insn (gen_blockage ());
8169 emit_insn (gen_epilogue_tpf ());
8172 /* Check whether to use frame or stack pointer for restore. */
8174 frame_pointer
= (frame_pointer_needed
8175 ? hard_frame_pointer_rtx
: stack_pointer_rtx
);
8177 s390_frame_area (&area_bottom
, &area_top
);
8179 /* Check whether we can access the register save area.
8180 If not, increment the frame pointer as required. */
8182 if (area_top
<= area_bottom
)
8184 /* Nothing to restore. */
8186 else if (DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_bottom
)
8187 && DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_top
- 1))
8189 /* Area is in range. */
8190 offset
= cfun_frame_layout
.frame_size
;
8194 rtx insn
, frame_off
, cfa
;
8196 offset
= area_bottom
< 0 ? -area_bottom
: 0;
8197 frame_off
= GEN_INT (cfun_frame_layout
.frame_size
- offset
);
8199 cfa
= gen_rtx_SET (VOIDmode
, frame_pointer
,
8200 gen_rtx_PLUS (Pmode
, frame_pointer
, frame_off
));
8201 if (DISP_IN_RANGE (INTVAL (frame_off
)))
8203 insn
= gen_rtx_SET (VOIDmode
, frame_pointer
,
8204 gen_rtx_PLUS (Pmode
, frame_pointer
, frame_off
));
8205 insn
= emit_insn (insn
);
8209 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
8210 frame_off
= force_const_mem (Pmode
, frame_off
);
8212 insn
= emit_insn (gen_add2_insn (frame_pointer
, frame_off
));
8213 annotate_constant_pool_refs (&PATTERN (insn
));
8215 add_reg_note (insn
, REG_CFA_ADJUST_CFA
, cfa
);
8216 RTX_FRAME_RELATED_P (insn
) = 1;
8219 /* Restore call saved fprs. */
8223 if (cfun_save_high_fprs_p
)
8225 next_offset
= cfun_frame_layout
.f8_offset
;
8226 for (i
= 24; i
< 32; i
++)
8228 if (cfun_fpr_bit_p (i
- 16))
8230 restore_fpr (frame_pointer
,
8231 offset
+ next_offset
, i
);
8233 = alloc_reg_note (REG_CFA_RESTORE
,
8234 gen_rtx_REG (DFmode
, i
), cfa_restores
);
8243 next_offset
= cfun_frame_layout
.f4_offset
;
8244 for (i
= 18; i
< 20; i
++)
8246 if (cfun_fpr_bit_p (i
- 16))
8248 restore_fpr (frame_pointer
,
8249 offset
+ next_offset
, i
);
8251 = alloc_reg_note (REG_CFA_RESTORE
,
8252 gen_rtx_REG (DFmode
, i
), cfa_restores
);
8255 else if (!TARGET_PACKED_STACK
)
8261 /* Return register. */
8263 return_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
8265 /* Restore call saved gprs. */
8267 if (cfun_frame_layout
.first_restore_gpr
!= -1)
8272 /* Check for global register and save them
8273 to stack location from where they get restored. */
8275 for (i
= cfun_frame_layout
.first_restore_gpr
;
8276 i
<= cfun_frame_layout
.last_restore_gpr
;
8279 if (global_not_special_regno_p (i
))
8281 addr
= plus_constant (frame_pointer
,
8282 offset
+ cfun_frame_layout
.gprs_offset
8283 + (i
- cfun_frame_layout
.first_save_gpr_slot
)
8285 addr
= gen_rtx_MEM (Pmode
, addr
);
8286 set_mem_alias_set (addr
, get_frame_alias_set ());
8287 emit_move_insn (addr
, gen_rtx_REG (Pmode
, i
));
8291 = alloc_reg_note (REG_CFA_RESTORE
,
8292 gen_rtx_REG (Pmode
, i
), cfa_restores
);
8297 /* Fetch return address from stack before load multiple,
8298 this will do good for scheduling. */
8300 if (cfun_frame_layout
.save_return_addr_p
8301 || (cfun_frame_layout
.first_restore_gpr
< BASE_REGNUM
8302 && cfun_frame_layout
.last_restore_gpr
> RETURN_REGNUM
))
8304 int return_regnum
= find_unused_clobbered_reg();
8307 return_reg
= gen_rtx_REG (Pmode
, return_regnum
);
8309 addr
= plus_constant (frame_pointer
,
8310 offset
+ cfun_frame_layout
.gprs_offset
8312 - cfun_frame_layout
.first_save_gpr_slot
)
8314 addr
= gen_rtx_MEM (Pmode
, addr
);
8315 set_mem_alias_set (addr
, get_frame_alias_set ());
8316 emit_move_insn (return_reg
, addr
);
8320 insn
= restore_gprs (frame_pointer
,
8321 offset
+ cfun_frame_layout
.gprs_offset
8322 + (cfun_frame_layout
.first_restore_gpr
8323 - cfun_frame_layout
.first_save_gpr_slot
)
8325 cfun_frame_layout
.first_restore_gpr
,
8326 cfun_frame_layout
.last_restore_gpr
);
8327 insn
= emit_insn (insn
);
8328 REG_NOTES (insn
) = cfa_restores
;
8329 add_reg_note (insn
, REG_CFA_DEF_CFA
,
8330 plus_constant (stack_pointer_rtx
, STACK_POINTER_OFFSET
));
8331 RTX_FRAME_RELATED_P (insn
) = 1;
8337 /* Return to caller. */
8339 p
= rtvec_alloc (2);
8341 RTVEC_ELT (p
, 0) = gen_rtx_RETURN (VOIDmode
);
8342 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
, return_reg
);
8343 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
8348 /* Return the size in bytes of a function argument of
8349 type TYPE and/or mode MODE. At least one of TYPE or
8350 MODE must be specified. */
8353 s390_function_arg_size (enum machine_mode mode
, const_tree type
)
8356 return int_size_in_bytes (type
);
8358 /* No type info available for some library calls ... */
8359 if (mode
!= BLKmode
)
8360 return GET_MODE_SIZE (mode
);
8362 /* If we have neither type nor mode, abort */
8366 /* Return true if a function argument of type TYPE and mode MODE
8367 is to be passed in a floating-point register, if available. */
8370 s390_function_arg_float (enum machine_mode mode
, const_tree type
)
8372 int size
= s390_function_arg_size (mode
, type
);
8376 /* Soft-float changes the ABI: no floating-point registers are used. */
8377 if (TARGET_SOFT_FLOAT
)
8380 /* No type info available for some library calls ... */
8382 return mode
== SFmode
|| mode
== DFmode
|| mode
== SDmode
|| mode
== DDmode
;
8384 /* The ABI says that record types with a single member are treated
8385 just like that member would be. */
8386 while (TREE_CODE (type
) == RECORD_TYPE
)
8388 tree field
, single
= NULL_TREE
;
8390 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
8392 if (TREE_CODE (field
) != FIELD_DECL
)
8395 if (single
== NULL_TREE
)
8396 single
= TREE_TYPE (field
);
8401 if (single
== NULL_TREE
)
8407 return TREE_CODE (type
) == REAL_TYPE
;
8410 /* Return true if a function argument of type TYPE and mode MODE
8411 is to be passed in an integer register, or a pair of integer
8412 registers, if available. */
8415 s390_function_arg_integer (enum machine_mode mode
, const_tree type
)
8417 int size
= s390_function_arg_size (mode
, type
);
8421 /* No type info available for some library calls ... */
8423 return GET_MODE_CLASS (mode
) == MODE_INT
8424 || (TARGET_SOFT_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
));
8426 /* We accept small integral (and similar) types. */
8427 if (INTEGRAL_TYPE_P (type
)
8428 || POINTER_TYPE_P (type
)
8429 || TREE_CODE (type
) == OFFSET_TYPE
8430 || (TARGET_SOFT_FLOAT
&& TREE_CODE (type
) == REAL_TYPE
))
8433 /* We also accept structs of size 1, 2, 4, 8 that are not
8434 passed in floating-point registers. */
8435 if (AGGREGATE_TYPE_P (type
)
8436 && exact_log2 (size
) >= 0
8437 && !s390_function_arg_float (mode
, type
))
8443 /* Return 1 if a function argument of type TYPE and mode MODE
8444 is to be passed by reference. The ABI specifies that only
8445 structures of size 1, 2, 4, or 8 bytes are passed by value,
8446 all other structures (and complex numbers) are passed by
8450 s390_pass_by_reference (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
,
8451 enum machine_mode mode
, const_tree type
,
8452 bool named ATTRIBUTE_UNUSED
)
8454 int size
= s390_function_arg_size (mode
, type
);
8460 if (AGGREGATE_TYPE_P (type
) && exact_log2 (size
) < 0)
8463 if (TREE_CODE (type
) == COMPLEX_TYPE
8464 || TREE_CODE (type
) == VECTOR_TYPE
)
8471 /* Update the data in CUM to advance over an argument of mode MODE and
8472 data type TYPE. (TYPE is null for libcalls where that information
8473 may not be available.). The boolean NAMED specifies whether the
8474 argument is a named argument (as opposed to an unnamed argument
8475 matching an ellipsis). */
8478 s390_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
8479 const_tree type
, bool named ATTRIBUTE_UNUSED
)
8481 if (s390_function_arg_float (mode
, type
))
8485 else if (s390_function_arg_integer (mode
, type
))
8487 int size
= s390_function_arg_size (mode
, type
);
8488 cum
->gprs
+= ((size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
);
8494 /* Define where to put the arguments to a function.
8495 Value is zero to push the argument on the stack,
8496 or a hard register in which to store the argument.
8498 MODE is the argument's machine mode.
8499 TYPE is the data type of the argument (as a tree).
8500 This is null for libcalls where that information may
8502 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8503 the preceding args and about the function being called.
8504 NAMED is nonzero if this argument is a named parameter
8505 (otherwise it is an extra parameter matching an ellipsis).
8507 On S/390, we use general purpose registers 2 through 6 to
8508 pass integer, pointer, and certain structure arguments, and
8509 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
8510 to pass floating point arguments. All remaining arguments
8511 are pushed to the stack. */
8514 s390_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
8515 const_tree type
, bool named ATTRIBUTE_UNUSED
)
8517 if (s390_function_arg_float (mode
, type
))
8519 if (cum
->fprs
+ 1 > FP_ARG_NUM_REG
)
8522 return gen_rtx_REG (mode
, cum
->fprs
+ 16);
8524 else if (s390_function_arg_integer (mode
, type
))
8526 int size
= s390_function_arg_size (mode
, type
);
8527 int n_gprs
= (size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
;
8529 if (cum
->gprs
+ n_gprs
> GP_ARG_NUM_REG
)
8531 else if (n_gprs
== 1 || UNITS_PER_WORD
== UNITS_PER_LONG
)
8532 return gen_rtx_REG (mode
, cum
->gprs
+ 2);
8533 else if (n_gprs
== 2)
8535 rtvec p
= rtvec_alloc (2);
8538 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, cum
->gprs
+ 2),
8541 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, cum
->gprs
+ 3),
8544 return gen_rtx_PARALLEL (mode
, p
);
8548 /* After the real arguments, expand_call calls us once again
8549 with a void_type_node type. Whatever we return here is
8550 passed as operand 2 to the call expanders.
8552 We don't need this feature ... */
8553 else if (type
== void_type_node
)
8559 /* Return true if return values of type TYPE should be returned
8560 in a memory buffer whose address is passed by the caller as
8561 hidden first argument. */
8564 s390_return_in_memory (const_tree type
, const_tree fundecl ATTRIBUTE_UNUSED
)
8566 /* We accept small integral (and similar) types. */
8567 if (INTEGRAL_TYPE_P (type
)
8568 || POINTER_TYPE_P (type
)
8569 || TREE_CODE (type
) == OFFSET_TYPE
8570 || TREE_CODE (type
) == REAL_TYPE
)
8571 return int_size_in_bytes (type
) > 8;
8573 /* Aggregates and similar constructs are always returned
8575 if (AGGREGATE_TYPE_P (type
)
8576 || TREE_CODE (type
) == COMPLEX_TYPE
8577 || TREE_CODE (type
) == VECTOR_TYPE
)
8580 /* ??? We get called on all sorts of random stuff from
8581 aggregate_value_p. We can't abort, but it's not clear
8582 what's safe to return. Pretend it's a struct I guess. */
8586 /* Function arguments and return values are promoted to word size. */
8588 static enum machine_mode
8589 s390_promote_function_mode (const_tree type
, enum machine_mode mode
,
8591 const_tree fntype ATTRIBUTE_UNUSED
,
8592 int for_return ATTRIBUTE_UNUSED
)
8594 if (INTEGRAL_MODE_P (mode
)
8595 && GET_MODE_SIZE (mode
) < UNITS_PER_LONG
)
8597 if (POINTER_TYPE_P (type
))
8598 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
8605 /* Define where to return a (scalar) value of type TYPE.
8606 If TYPE is null, define where to return a (scalar)
8607 value of mode MODE from a libcall. */
8610 s390_function_value (const_tree type
, const_tree fn
, enum machine_mode mode
)
8614 int unsignedp
= TYPE_UNSIGNED (type
);
8615 mode
= promote_function_mode (type
, TYPE_MODE (type
), &unsignedp
, fn
, 1);
8618 gcc_assert (GET_MODE_CLASS (mode
) == MODE_INT
|| SCALAR_FLOAT_MODE_P (mode
));
8619 gcc_assert (GET_MODE_SIZE (mode
) <= 8);
8621 if (TARGET_HARD_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
))
8622 return gen_rtx_REG (mode
, 16);
8623 else if (GET_MODE_SIZE (mode
) <= UNITS_PER_LONG
8624 || UNITS_PER_LONG
== UNITS_PER_WORD
)
8625 return gen_rtx_REG (mode
, 2);
8626 else if (GET_MODE_SIZE (mode
) == 2 * UNITS_PER_LONG
)
8628 rtvec p
= rtvec_alloc (2);
8631 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, 2), const0_rtx
);
8633 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, 3), GEN_INT (4));
8635 return gen_rtx_PARALLEL (mode
, p
);
8642 /* Create and return the va_list datatype.
8644 On S/390, va_list is an array type equivalent to
8646 typedef struct __va_list_tag
8650 void *__overflow_arg_area;
8651 void *__reg_save_area;
8654 where __gpr and __fpr hold the number of general purpose
8655 or floating point arguments used up to now, respectively,
8656 __overflow_arg_area points to the stack location of the
8657 next argument passed on the stack, and __reg_save_area
8658 always points to the start of the register area in the
8659 call frame of the current function. The function prologue
8660 saves all registers used for argument passing into this
8661 area if the function uses variable arguments. */
8664 s390_build_builtin_va_list (void)
8666 tree f_gpr
, f_fpr
, f_ovf
, f_sav
, record
, type_decl
;
8668 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
8671 build_decl (BUILTINS_LOCATION
,
8672 TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
8674 f_gpr
= build_decl (BUILTINS_LOCATION
,
8675 FIELD_DECL
, get_identifier ("__gpr"),
8676 long_integer_type_node
);
8677 f_fpr
= build_decl (BUILTINS_LOCATION
,
8678 FIELD_DECL
, get_identifier ("__fpr"),
8679 long_integer_type_node
);
8680 f_ovf
= build_decl (BUILTINS_LOCATION
,
8681 FIELD_DECL
, get_identifier ("__overflow_arg_area"),
8683 f_sav
= build_decl (BUILTINS_LOCATION
,
8684 FIELD_DECL
, get_identifier ("__reg_save_area"),
8687 va_list_gpr_counter_field
= f_gpr
;
8688 va_list_fpr_counter_field
= f_fpr
;
8690 DECL_FIELD_CONTEXT (f_gpr
) = record
;
8691 DECL_FIELD_CONTEXT (f_fpr
) = record
;
8692 DECL_FIELD_CONTEXT (f_ovf
) = record
;
8693 DECL_FIELD_CONTEXT (f_sav
) = record
;
8695 TYPE_STUB_DECL (record
) = type_decl
;
8696 TYPE_NAME (record
) = type_decl
;
8697 TYPE_FIELDS (record
) = f_gpr
;
8698 DECL_CHAIN (f_gpr
) = f_fpr
;
8699 DECL_CHAIN (f_fpr
) = f_ovf
;
8700 DECL_CHAIN (f_ovf
) = f_sav
;
8702 layout_type (record
);
8704 /* The correct type is an array type of one element. */
8705 return build_array_type (record
, build_index_type (size_zero_node
));
8708 /* Implement va_start by filling the va_list structure VALIST.
8709 STDARG_P is always true, and ignored.
8710 NEXTARG points to the first anonymous stack argument.
8712 The following global variables are used to initialize
8713 the va_list structure:
8716 holds number of gprs and fprs used for named arguments.
8717 crtl->args.arg_offset_rtx:
8718 holds the offset of the first anonymous stack argument
8719 (relative to the virtual arg pointer). */
8722 s390_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
8724 HOST_WIDE_INT n_gpr
, n_fpr
;
8726 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
8727 tree gpr
, fpr
, ovf
, sav
, t
;
8729 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
8730 f_fpr
= DECL_CHAIN (f_gpr
);
8731 f_ovf
= DECL_CHAIN (f_fpr
);
8732 f_sav
= DECL_CHAIN (f_ovf
);
8734 valist
= build_simple_mem_ref (valist
);
8735 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
8736 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
8737 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
8738 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
8740 /* Count number of gp and fp argument registers used. */
8742 n_gpr
= crtl
->args
.info
.gprs
;
8743 n_fpr
= crtl
->args
.info
.fprs
;
8745 if (cfun
->va_list_gpr_size
)
8747 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
8748 build_int_cst (NULL_TREE
, n_gpr
));
8749 TREE_SIDE_EFFECTS (t
) = 1;
8750 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8753 if (cfun
->va_list_fpr_size
)
8755 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
8756 build_int_cst (NULL_TREE
, n_fpr
));
8757 TREE_SIDE_EFFECTS (t
) = 1;
8758 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8761 /* Find the overflow area. */
8762 if (n_gpr
+ cfun
->va_list_gpr_size
> GP_ARG_NUM_REG
8763 || n_fpr
+ cfun
->va_list_fpr_size
> FP_ARG_NUM_REG
)
8765 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
8767 off
= INTVAL (crtl
->args
.arg_offset_rtx
);
8768 off
= off
< 0 ? 0 : off
;
8769 if (TARGET_DEBUG_ARG
)
8770 fprintf (stderr
, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
8771 (int)n_gpr
, (int)n_fpr
, off
);
8773 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (ovf
), t
, size_int (off
));
8775 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
8776 TREE_SIDE_EFFECTS (t
) = 1;
8777 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8780 /* Find the register save area. */
8781 if ((cfun
->va_list_gpr_size
&& n_gpr
< GP_ARG_NUM_REG
)
8782 || (cfun
->va_list_fpr_size
&& n_fpr
< FP_ARG_NUM_REG
))
8784 t
= make_tree (TREE_TYPE (sav
), return_address_pointer_rtx
);
8785 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (sav
), t
,
8786 size_int (-RETURN_REGNUM
* UNITS_PER_LONG
));
8788 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
8789 TREE_SIDE_EFFECTS (t
) = 1;
8790 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8794 /* Implement va_arg by updating the va_list structure
8795 VALIST as required to retrieve an argument of type
8796 TYPE, and returning that argument.
8798 Generates code equivalent to:
8800 if (integral value) {
8801 if (size <= 4 && args.gpr < 5 ||
8802 size > 4 && args.gpr < 4 )
8803 ret = args.reg_save_area[args.gpr+8]
8805 ret = *args.overflow_arg_area++;
8806 } else if (float value) {
8808 ret = args.reg_save_area[args.fpr+64]
8810 ret = *args.overflow_arg_area++;
8811 } else if (aggregate value) {
8813 ret = *args.reg_save_area[args.gpr]
8815 ret = **args.overflow_arg_area++;
8819 s390_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
8820 gimple_seq
*post_p ATTRIBUTE_UNUSED
)
8822 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
8823 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
8824 int indirect_p
, size
, n_reg
, sav_ofs
, sav_scale
, max_reg
;
8825 tree lab_false
, lab_over
, addr
;
8827 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
8828 f_fpr
= DECL_CHAIN (f_gpr
);
8829 f_ovf
= DECL_CHAIN (f_fpr
);
8830 f_sav
= DECL_CHAIN (f_ovf
);
8832 valist
= build_va_arg_indirect_ref (valist
);
8833 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
8834 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
8835 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
8837 /* The tree for args* cannot be shared between gpr/fpr and ovf since
8838 both appear on a lhs. */
8839 valist
= unshare_expr (valist
);
8840 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
8842 size
= int_size_in_bytes (type
);
8844 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
8846 if (TARGET_DEBUG_ARG
)
8848 fprintf (stderr
, "va_arg: aggregate type");
8852 /* Aggregates are passed by reference. */
8857 /* kernel stack layout on 31 bit: It is assumed here that no padding
8858 will be added by s390_frame_info because for va_args always an even
8859 number of gprs has to be saved r15-r2 = 14 regs. */
8860 sav_ofs
= 2 * UNITS_PER_LONG
;
8861 sav_scale
= UNITS_PER_LONG
;
8862 size
= UNITS_PER_LONG
;
8863 max_reg
= GP_ARG_NUM_REG
- n_reg
;
8865 else if (s390_function_arg_float (TYPE_MODE (type
), type
))
8867 if (TARGET_DEBUG_ARG
)
8869 fprintf (stderr
, "va_arg: float type");
8873 /* FP args go in FP registers, if present. */
8877 sav_ofs
= 16 * UNITS_PER_LONG
;
8879 max_reg
= FP_ARG_NUM_REG
- n_reg
;
8883 if (TARGET_DEBUG_ARG
)
8885 fprintf (stderr
, "va_arg: other type");
8889 /* Otherwise into GP registers. */
8892 n_reg
= (size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
;
8894 /* kernel stack layout on 31 bit: It is assumed here that no padding
8895 will be added by s390_frame_info because for va_args always an even
8896 number of gprs has to be saved r15-r2 = 14 regs. */
8897 sav_ofs
= 2 * UNITS_PER_LONG
;
8899 if (size
< UNITS_PER_LONG
)
8900 sav_ofs
+= UNITS_PER_LONG
- size
;
8902 sav_scale
= UNITS_PER_LONG
;
8903 max_reg
= GP_ARG_NUM_REG
- n_reg
;
8906 /* Pull the value out of the saved registers ... */
8908 lab_false
= create_artificial_label (UNKNOWN_LOCATION
);
8909 lab_over
= create_artificial_label (UNKNOWN_LOCATION
);
8910 addr
= create_tmp_var (ptr_type_node
, "addr");
8912 t
= fold_convert (TREE_TYPE (reg
), size_int (max_reg
));
8913 t
= build2 (GT_EXPR
, boolean_type_node
, reg
, t
);
8914 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
8915 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
8916 gimplify_and_add (t
, pre_p
);
8918 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, sav
,
8919 size_int (sav_ofs
));
8920 u
= build2 (MULT_EXPR
, TREE_TYPE (reg
), reg
,
8921 fold_convert (TREE_TYPE (reg
), size_int (sav_scale
)));
8922 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, t
, fold_convert (sizetype
, u
));
8924 gimplify_assign (addr
, t
, pre_p
);
8926 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
8928 gimple_seq_add_stmt (pre_p
, gimple_build_label (lab_false
));
8931 /* ... Otherwise out of the overflow area. */
8934 if (size
< UNITS_PER_LONG
)
8935 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, t
,
8936 size_int (UNITS_PER_LONG
- size
));
8938 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
8940 gimplify_assign (addr
, t
, pre_p
);
8942 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, t
,
8944 gimplify_assign (ovf
, t
, pre_p
);
8946 gimple_seq_add_stmt (pre_p
, gimple_build_label (lab_over
));
8949 /* Increment register save count. */
8951 u
= build2 (PREINCREMENT_EXPR
, TREE_TYPE (reg
), reg
,
8952 fold_convert (TREE_TYPE (reg
), size_int (n_reg
)));
8953 gimplify_and_add (u
, pre_p
);
8957 t
= build_pointer_type_for_mode (build_pointer_type (type
),
8959 addr
= fold_convert (t
, addr
);
8960 addr
= build_va_arg_indirect_ref (addr
);
8964 t
= build_pointer_type_for_mode (type
, ptr_mode
, true);
8965 addr
= fold_convert (t
, addr
);
8968 return build_va_arg_indirect_ref (addr
);
8976 S390_BUILTIN_THREAD_POINTER
,
8977 S390_BUILTIN_SET_THREAD_POINTER
,
8982 static enum insn_code
const code_for_builtin_64
[S390_BUILTIN_max
] = {
8987 static enum insn_code
const code_for_builtin_31
[S390_BUILTIN_max
] = {
8993 s390_init_builtins (void)
8997 ftype
= build_function_type (ptr_type_node
, void_list_node
);
8998 add_builtin_function ("__builtin_thread_pointer", ftype
,
8999 S390_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
9002 ftype
= build_function_type_list (void_type_node
, ptr_type_node
, NULL_TREE
);
9003 add_builtin_function ("__builtin_set_thread_pointer", ftype
,
9004 S390_BUILTIN_SET_THREAD_POINTER
, BUILT_IN_MD
,
9008 /* Expand an expression EXP that calls a built-in function,
9009 with result going to TARGET if that's convenient
9010 (and in mode MODE if that's convenient).
9011 SUBTARGET may be used as the target for computing one of EXP's operands.
9012 IGNORE is nonzero if the value is to be ignored. */
9015 s390_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
9016 enum machine_mode mode ATTRIBUTE_UNUSED
,
9017 int ignore ATTRIBUTE_UNUSED
)
9021 enum insn_code
const *code_for_builtin
=
9022 TARGET_64BIT
? code_for_builtin_64
: code_for_builtin_31
;
9024 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
9025 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
9026 enum insn_code icode
;
9027 rtx op
[MAX_ARGS
], pat
;
9031 call_expr_arg_iterator iter
;
9033 if (fcode
>= S390_BUILTIN_max
)
9034 internal_error ("bad builtin fcode");
9035 icode
= code_for_builtin
[fcode
];
9037 internal_error ("bad builtin fcode");
9039 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
9042 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
9044 const struct insn_operand_data
*insn_op
;
9046 if (arg
== error_mark_node
)
9048 if (arity
> MAX_ARGS
)
9051 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
9053 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, EXPAND_NORMAL
);
9055 if (!(*insn_op
->predicate
) (op
[arity
], insn_op
->mode
))
9056 op
[arity
] = copy_to_mode_reg (insn_op
->mode
, op
[arity
]);
9062 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
9064 || GET_MODE (target
) != tmode
9065 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
9066 target
= gen_reg_rtx (tmode
);
9072 pat
= GEN_FCN (icode
) (target
);
9076 pat
= GEN_FCN (icode
) (target
, op
[0]);
9078 pat
= GEN_FCN (icode
) (op
[0]);
9081 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
9097 /* Output assembly code for the trampoline template to
9100 On S/390, we use gpr 1 internally in the trampoline code;
9101 gpr 0 is used to hold the static chain. */
9104 s390_asm_trampoline_template (FILE *file
)
9107 op
[0] = gen_rtx_REG (Pmode
, 0);
9108 op
[1] = gen_rtx_REG (Pmode
, 1);
9112 output_asm_insn ("basr\t%1,0", op
);
9113 output_asm_insn ("lmg\t%0,%1,14(%1)", op
);
9114 output_asm_insn ("br\t%1", op
);
9115 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 10));
9119 output_asm_insn ("basr\t%1,0", op
);
9120 output_asm_insn ("lm\t%0,%1,6(%1)", op
);
9121 output_asm_insn ("br\t%1", op
);
9122 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 8));
9126 /* Emit RTL insns to initialize the variable parts of a trampoline.
9127 FNADDR is an RTX for the address of the function's pure code.
9128 CXT is an RTX for the static chain value for the function. */
9131 s390_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
9133 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
9136 emit_block_move (m_tramp
, assemble_trampoline_template (),
9137 GEN_INT (2*UNITS_PER_WORD
), BLOCK_OP_NORMAL
);
9139 mem
= adjust_address (m_tramp
, Pmode
, 2*UNITS_PER_WORD
);
9140 emit_move_insn (mem
, cxt
);
9141 mem
= adjust_address (m_tramp
, Pmode
, 3*UNITS_PER_WORD
);
9142 emit_move_insn (mem
, fnaddr
);
9145 /* Output assembler code to FILE to increment profiler label # LABELNO
9146 for profiling a function entry. */
9149 s390_function_profiler (FILE *file
, int labelno
)
9154 ASM_GENERATE_INTERNAL_LABEL (label
, "LP", labelno
);
9156 fprintf (file
, "# function profiler \n");
9158 op
[0] = gen_rtx_REG (Pmode
, RETURN_REGNUM
);
9159 op
[1] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
9160 op
[1] = gen_rtx_MEM (Pmode
, plus_constant (op
[1], UNITS_PER_LONG
));
9162 op
[2] = gen_rtx_REG (Pmode
, 1);
9163 op
[3] = gen_rtx_SYMBOL_REF (Pmode
, label
);
9164 SYMBOL_REF_FLAGS (op
[3]) = SYMBOL_FLAG_LOCAL
;
9166 op
[4] = gen_rtx_SYMBOL_REF (Pmode
, "_mcount");
9169 op
[4] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[4]), UNSPEC_PLT
);
9170 op
[4] = gen_rtx_CONST (Pmode
, op
[4]);
9175 output_asm_insn ("stg\t%0,%1", op
);
9176 output_asm_insn ("larl\t%2,%3", op
);
9177 output_asm_insn ("brasl\t%0,%4", op
);
9178 output_asm_insn ("lg\t%0,%1", op
);
9182 op
[6] = gen_label_rtx ();
9184 output_asm_insn ("st\t%0,%1", op
);
9185 output_asm_insn ("bras\t%2,%l6", op
);
9186 output_asm_insn (".long\t%4", op
);
9187 output_asm_insn (".long\t%3", op
);
9188 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
9189 output_asm_insn ("l\t%0,0(%2)", op
);
9190 output_asm_insn ("l\t%2,4(%2)", op
);
9191 output_asm_insn ("basr\t%0,%0", op
);
9192 output_asm_insn ("l\t%0,%1", op
);
9196 op
[5] = gen_label_rtx ();
9197 op
[6] = gen_label_rtx ();
9199 output_asm_insn ("st\t%0,%1", op
);
9200 output_asm_insn ("bras\t%2,%l6", op
);
9201 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[5]));
9202 output_asm_insn (".long\t%4-%l5", op
);
9203 output_asm_insn (".long\t%3-%l5", op
);
9204 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
9205 output_asm_insn ("lr\t%0,%2", op
);
9206 output_asm_insn ("a\t%0,0(%2)", op
);
9207 output_asm_insn ("a\t%2,4(%2)", op
);
9208 output_asm_insn ("basr\t%0,%0", op
);
9209 output_asm_insn ("l\t%0,%1", op
);
9213 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
9214 into its SYMBOL_REF_FLAGS. */
9217 s390_encode_section_info (tree decl
, rtx rtl
, int first
)
9219 default_encode_section_info (decl
, rtl
, first
);
9221 if (TREE_CODE (decl
) == VAR_DECL
)
9223 /* If a variable has a forced alignment to < 2 bytes, mark it
9224 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
9226 if (DECL_USER_ALIGN (decl
) && DECL_ALIGN (decl
) < 16)
9227 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_ALIGN1
;
9228 if (!DECL_SIZE (decl
)
9229 || !DECL_ALIGN (decl
)
9230 || !host_integerp (DECL_SIZE (decl
), 0)
9231 || (DECL_ALIGN (decl
) <= 64
9232 && DECL_ALIGN (decl
) != tree_low_cst (DECL_SIZE (decl
), 0)))
9233 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED
;
9236 /* Literal pool references don't have a decl so they are handled
9237 differently here. We rely on the information in the MEM_ALIGN
9238 entry to decide upon natural alignment. */
9240 && GET_CODE (XEXP (rtl
, 0)) == SYMBOL_REF
9241 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl
, 0))
9242 && (MEM_ALIGN (rtl
) == 0
9243 || GET_MODE_BITSIZE (GET_MODE (rtl
)) == 0
9244 || MEM_ALIGN (rtl
) < GET_MODE_BITSIZE (GET_MODE (rtl
))))
9245 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED
;
9248 /* Output thunk to FILE that implements a C++ virtual function call (with
9249 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
9250 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
9251 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
9252 relative to the resulting this pointer. */
9255 s390_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
9256 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
9262 /* Make sure unwind info is emitted for the thunk if needed. */
9263 final_start_function (emit_barrier (), file
, 1);
9265 /* Operand 0 is the target function. */
9266 op
[0] = XEXP (DECL_RTL (function
), 0);
9267 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (op
[0]))
9270 op
[0] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[0]),
9271 TARGET_64BIT
? UNSPEC_PLT
: UNSPEC_GOT
);
9272 op
[0] = gen_rtx_CONST (Pmode
, op
[0]);
9275 /* Operand 1 is the 'this' pointer. */
9276 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
9277 op
[1] = gen_rtx_REG (Pmode
, 3);
9279 op
[1] = gen_rtx_REG (Pmode
, 2);
9281 /* Operand 2 is the delta. */
9282 op
[2] = GEN_INT (delta
);
9284 /* Operand 3 is the vcall_offset. */
9285 op
[3] = GEN_INT (vcall_offset
);
9287 /* Operand 4 is the temporary register. */
9288 op
[4] = gen_rtx_REG (Pmode
, 1);
9290 /* Operands 5 to 8 can be used as labels. */
9296 /* Operand 9 can be used for temporary register. */
9299 /* Generate code. */
9302 /* Setup literal pool pointer if required. */
9303 if ((!DISP_IN_RANGE (delta
)
9304 && !CONST_OK_FOR_K (delta
)
9305 && !CONST_OK_FOR_Os (delta
))
9306 || (!DISP_IN_RANGE (vcall_offset
)
9307 && !CONST_OK_FOR_K (vcall_offset
)
9308 && !CONST_OK_FOR_Os (vcall_offset
)))
9310 op
[5] = gen_label_rtx ();
9311 output_asm_insn ("larl\t%4,%5", op
);
9314 /* Add DELTA to this pointer. */
9317 if (CONST_OK_FOR_J (delta
))
9318 output_asm_insn ("la\t%1,%2(%1)", op
);
9319 else if (DISP_IN_RANGE (delta
))
9320 output_asm_insn ("lay\t%1,%2(%1)", op
);
9321 else if (CONST_OK_FOR_K (delta
))
9322 output_asm_insn ("aghi\t%1,%2", op
);
9323 else if (CONST_OK_FOR_Os (delta
))
9324 output_asm_insn ("agfi\t%1,%2", op
);
9327 op
[6] = gen_label_rtx ();
9328 output_asm_insn ("agf\t%1,%6-%5(%4)", op
);
9332 /* Perform vcall adjustment. */
9335 if (DISP_IN_RANGE (vcall_offset
))
9337 output_asm_insn ("lg\t%4,0(%1)", op
);
9338 output_asm_insn ("ag\t%1,%3(%4)", op
);
9340 else if (CONST_OK_FOR_K (vcall_offset
))
9342 output_asm_insn ("lghi\t%4,%3", op
);
9343 output_asm_insn ("ag\t%4,0(%1)", op
);
9344 output_asm_insn ("ag\t%1,0(%4)", op
);
9346 else if (CONST_OK_FOR_Os (vcall_offset
))
9348 output_asm_insn ("lgfi\t%4,%3", op
);
9349 output_asm_insn ("ag\t%4,0(%1)", op
);
9350 output_asm_insn ("ag\t%1,0(%4)", op
);
9354 op
[7] = gen_label_rtx ();
9355 output_asm_insn ("llgf\t%4,%7-%5(%4)", op
);
9356 output_asm_insn ("ag\t%4,0(%1)", op
);
9357 output_asm_insn ("ag\t%1,0(%4)", op
);
9361 /* Jump to target. */
9362 output_asm_insn ("jg\t%0", op
);
9364 /* Output literal pool if required. */
9367 output_asm_insn (".align\t4", op
);
9368 targetm
.asm_out
.internal_label (file
, "L",
9369 CODE_LABEL_NUMBER (op
[5]));
9373 targetm
.asm_out
.internal_label (file
, "L",
9374 CODE_LABEL_NUMBER (op
[6]));
9375 output_asm_insn (".long\t%2", op
);
9379 targetm
.asm_out
.internal_label (file
, "L",
9380 CODE_LABEL_NUMBER (op
[7]));
9381 output_asm_insn (".long\t%3", op
);
9386 /* Setup base pointer if required. */
9388 || (!DISP_IN_RANGE (delta
)
9389 && !CONST_OK_FOR_K (delta
)
9390 && !CONST_OK_FOR_Os (delta
))
9391 || (!DISP_IN_RANGE (delta
)
9392 && !CONST_OK_FOR_K (vcall_offset
)
9393 && !CONST_OK_FOR_Os (vcall_offset
)))
9395 op
[5] = gen_label_rtx ();
9396 output_asm_insn ("basr\t%4,0", op
);
9397 targetm
.asm_out
.internal_label (file
, "L",
9398 CODE_LABEL_NUMBER (op
[5]));
9401 /* Add DELTA to this pointer. */
9404 if (CONST_OK_FOR_J (delta
))
9405 output_asm_insn ("la\t%1,%2(%1)", op
);
9406 else if (DISP_IN_RANGE (delta
))
9407 output_asm_insn ("lay\t%1,%2(%1)", op
);
9408 else if (CONST_OK_FOR_K (delta
))
9409 output_asm_insn ("ahi\t%1,%2", op
);
9410 else if (CONST_OK_FOR_Os (delta
))
9411 output_asm_insn ("afi\t%1,%2", op
);
9414 op
[6] = gen_label_rtx ();
9415 output_asm_insn ("a\t%1,%6-%5(%4)", op
);
9419 /* Perform vcall adjustment. */
9422 if (CONST_OK_FOR_J (vcall_offset
))
9424 output_asm_insn ("l\t%4,0(%1)", op
);
9425 output_asm_insn ("a\t%1,%3(%4)", op
);
9427 else if (DISP_IN_RANGE (vcall_offset
))
9429 output_asm_insn ("l\t%4,0(%1)", op
);
9430 output_asm_insn ("ay\t%1,%3(%4)", op
);
9432 else if (CONST_OK_FOR_K (vcall_offset
))
9434 output_asm_insn ("lhi\t%4,%3", op
);
9435 output_asm_insn ("a\t%4,0(%1)", op
);
9436 output_asm_insn ("a\t%1,0(%4)", op
);
9438 else if (CONST_OK_FOR_Os (vcall_offset
))
9440 output_asm_insn ("iilf\t%4,%3", op
);
9441 output_asm_insn ("a\t%4,0(%1)", op
);
9442 output_asm_insn ("a\t%1,0(%4)", op
);
9446 op
[7] = gen_label_rtx ();
9447 output_asm_insn ("l\t%4,%7-%5(%4)", op
);
9448 output_asm_insn ("a\t%4,0(%1)", op
);
9449 output_asm_insn ("a\t%1,0(%4)", op
);
9452 /* We had to clobber the base pointer register.
9453 Re-setup the base pointer (with a different base). */
9454 op
[5] = gen_label_rtx ();
9455 output_asm_insn ("basr\t%4,0", op
);
9456 targetm
.asm_out
.internal_label (file
, "L",
9457 CODE_LABEL_NUMBER (op
[5]));
9460 /* Jump to target. */
9461 op
[8] = gen_label_rtx ();
9464 output_asm_insn ("l\t%4,%8-%5(%4)", op
);
9466 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
9467 /* We cannot call through .plt, since .plt requires %r12 loaded. */
9468 else if (flag_pic
== 1)
9470 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
9471 output_asm_insn ("l\t%4,%0(%4)", op
);
9473 else if (flag_pic
== 2)
9475 op
[9] = gen_rtx_REG (Pmode
, 0);
9476 output_asm_insn ("l\t%9,%8-4-%5(%4)", op
);
9477 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
9478 output_asm_insn ("ar\t%4,%9", op
);
9479 output_asm_insn ("l\t%4,0(%4)", op
);
9482 output_asm_insn ("br\t%4", op
);
9484 /* Output literal pool. */
9485 output_asm_insn (".align\t4", op
);
9487 if (nonlocal
&& flag_pic
== 2)
9488 output_asm_insn (".long\t%0", op
);
9491 op
[0] = gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
9492 SYMBOL_REF_FLAGS (op
[0]) = SYMBOL_FLAG_LOCAL
;
9495 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[8]));
9497 output_asm_insn (".long\t%0", op
);
9499 output_asm_insn (".long\t%0-%5", op
);
9503 targetm
.asm_out
.internal_label (file
, "L",
9504 CODE_LABEL_NUMBER (op
[6]));
9505 output_asm_insn (".long\t%2", op
);
9509 targetm
.asm_out
.internal_label (file
, "L",
9510 CODE_LABEL_NUMBER (op
[7]));
9511 output_asm_insn (".long\t%3", op
);
9514 final_end_function ();
9518 s390_valid_pointer_mode (enum machine_mode mode
)
9520 return (mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
));
9523 /* Checks whether the given CALL_EXPR would use a caller
9524 saved register. This is used to decide whether sibling call
9525 optimization could be performed on the respective function
9529 s390_call_saved_register_used (tree call_expr
)
9531 CUMULATIVE_ARGS cum
;
9533 enum machine_mode mode
;
9538 INIT_CUMULATIVE_ARGS (cum
, NULL
, NULL
, 0, 0);
9540 for (i
= 0; i
< call_expr_nargs (call_expr
); i
++)
9542 parameter
= CALL_EXPR_ARG (call_expr
, i
);
9543 gcc_assert (parameter
);
9545 /* For an undeclared variable passed as parameter we will get
9546 an ERROR_MARK node here. */
9547 if (TREE_CODE (parameter
) == ERROR_MARK
)
9550 type
= TREE_TYPE (parameter
);
9553 mode
= TYPE_MODE (type
);
9556 if (pass_by_reference (&cum
, mode
, type
, true))
9559 type
= build_pointer_type (type
);
9562 parm_rtx
= s390_function_arg (&cum
, mode
, type
, 0);
9564 s390_function_arg_advance (&cum
, mode
, type
, 0);
9569 if (REG_P (parm_rtx
))
9572 reg
< HARD_REGNO_NREGS (REGNO (parm_rtx
), GET_MODE (parm_rtx
));
9574 if (!call_used_regs
[reg
+ REGNO (parm_rtx
)])
9578 if (GET_CODE (parm_rtx
) == PARALLEL
)
9582 for (i
= 0; i
< XVECLEN (parm_rtx
, 0); i
++)
9584 rtx r
= XEXP (XVECEXP (parm_rtx
, 0, i
), 0);
9586 gcc_assert (REG_P (r
));
9589 reg
< HARD_REGNO_NREGS (REGNO (r
), GET_MODE (r
));
9591 if (!call_used_regs
[reg
+ REGNO (r
)])
9600 /* Return true if the given call expression can be
9601 turned into a sibling call.
9602 DECL holds the declaration of the function to be called whereas
9603 EXP is the call expression itself. */
9606 s390_function_ok_for_sibcall (tree decl
, tree exp
)
9608 /* The TPF epilogue uses register 1. */
9609 if (TARGET_TPF_PROFILING
)
9612 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
9613 which would have to be restored before the sibcall. */
9614 if (!TARGET_64BIT
&& flag_pic
&& decl
&& !targetm
.binds_local_p (decl
))
9617 /* Register 6 on s390 is available as an argument register but unfortunately
9618 "caller saved". This makes functions needing this register for arguments
9619 not suitable for sibcalls. */
9620 return !s390_call_saved_register_used (exp
);
9623 /* Return the fixed registers used for condition codes. */
9626 s390_fixed_condition_code_regs (unsigned int *p1
, unsigned int *p2
)
9629 *p2
= INVALID_REGNUM
;
9634 /* This function is used by the call expanders of the machine description.
9635 It emits the call insn itself together with the necessary operations
9636 to adjust the target address and returns the emitted insn.
9637 ADDR_LOCATION is the target address rtx
9638 TLS_CALL the location of the thread-local symbol
9639 RESULT_REG the register where the result of the call should be stored
9640 RETADDR_REG the register where the return address should be stored
9641 If this parameter is NULL_RTX the call is considered
9642 to be a sibling call. */
9645 s390_emit_call (rtx addr_location
, rtx tls_call
, rtx result_reg
,
9648 bool plt_call
= false;
9654 /* Direct function calls need special treatment. */
9655 if (GET_CODE (addr_location
) == SYMBOL_REF
)
9657 /* When calling a global routine in PIC mode, we must
9658 replace the symbol itself with the PLT stub. */
9659 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (addr_location
))
9661 if (retaddr_reg
!= NULL_RTX
)
9663 addr_location
= gen_rtx_UNSPEC (Pmode
,
9664 gen_rtvec (1, addr_location
),
9666 addr_location
= gen_rtx_CONST (Pmode
, addr_location
);
9670 /* For -fpic code the PLT entries might use r12 which is
9671 call-saved. Therefore we cannot do a sibcall when
9672 calling directly using a symbol ref. When reaching
9673 this point we decided (in s390_function_ok_for_sibcall)
9674 to do a sibcall for a function pointer but one of the
9675 optimizers was able to get rid of the function pointer
9676 by propagating the symbol ref into the call. This
9677 optimization is illegal for S/390 so we turn the direct
9678 call into a indirect call again. */
9679 addr_location
= force_reg (Pmode
, addr_location
);
9682 /* Unless we can use the bras(l) insn, force the
9683 routine address into a register. */
9684 if (!TARGET_SMALL_EXEC
&& !TARGET_CPU_ZARCH
)
9687 addr_location
= legitimize_pic_address (addr_location
, 0);
9689 addr_location
= force_reg (Pmode
, addr_location
);
9693 /* If it is already an indirect call or the code above moved the
9694 SYMBOL_REF to somewhere else make sure the address can be found in
9696 if (retaddr_reg
== NULL_RTX
9697 && GET_CODE (addr_location
) != SYMBOL_REF
9700 emit_move_insn (gen_rtx_REG (Pmode
, SIBCALL_REGNUM
), addr_location
);
9701 addr_location
= gen_rtx_REG (Pmode
, SIBCALL_REGNUM
);
9704 addr_location
= gen_rtx_MEM (QImode
, addr_location
);
9705 call
= gen_rtx_CALL (VOIDmode
, addr_location
, const0_rtx
);
9707 if (result_reg
!= NULL_RTX
)
9708 call
= gen_rtx_SET (VOIDmode
, result_reg
, call
);
9710 if (retaddr_reg
!= NULL_RTX
)
9712 clobber
= gen_rtx_CLOBBER (VOIDmode
, retaddr_reg
);
9714 if (tls_call
!= NULL_RTX
)
9715 vec
= gen_rtvec (3, call
, clobber
,
9716 gen_rtx_USE (VOIDmode
, tls_call
));
9718 vec
= gen_rtvec (2, call
, clobber
);
9720 call
= gen_rtx_PARALLEL (VOIDmode
, vec
);
9723 insn
= emit_call_insn (call
);
9725 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
9726 if ((!TARGET_64BIT
&& plt_call
) || tls_call
!= NULL_RTX
)
9728 /* s390_function_ok_for_sibcall should
9729 have denied sibcalls in this case. */
9730 gcc_assert (retaddr_reg
!= NULL_RTX
);
9732 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
9737 /* Implement CONDITIONAL_REGISTER_USAGE. */
9740 s390_conditional_register_usage (void)
9746 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
9747 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
9749 if (TARGET_CPU_ZARCH
)
9751 fixed_regs
[BASE_REGNUM
] = 0;
9752 call_used_regs
[BASE_REGNUM
] = 0;
9753 fixed_regs
[RETURN_REGNUM
] = 0;
9754 call_used_regs
[RETURN_REGNUM
] = 0;
9758 for (i
= 24; i
< 32; i
++)
9759 call_used_regs
[i
] = call_really_used_regs
[i
] = 0;
9763 for (i
= 18; i
< 20; i
++)
9764 call_used_regs
[i
] = call_really_used_regs
[i
] = 0;
9767 if (TARGET_SOFT_FLOAT
)
9769 for (i
= 16; i
< 32; i
++)
9770 call_used_regs
[i
] = fixed_regs
[i
] = 1;
9774 /* Corresponding function to eh_return expander. */
9776 static GTY(()) rtx s390_tpf_eh_return_symbol
;
9778 s390_emit_tpf_eh_return (rtx target
)
9782 if (!s390_tpf_eh_return_symbol
)
9783 s390_tpf_eh_return_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tpf_eh_return");
9785 reg
= gen_rtx_REG (Pmode
, 2);
9787 emit_move_insn (reg
, target
);
9788 insn
= s390_emit_call (s390_tpf_eh_return_symbol
, NULL_RTX
, reg
,
9789 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
9790 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
9792 emit_move_insn (EH_RETURN_HANDLER_RTX
, reg
);
9795 /* Rework the prologue/epilogue to avoid saving/restoring
9796 registers unnecessarily. */
9799 s390_optimize_prologue (void)
9801 rtx insn
, new_insn
, next_insn
;
9803 /* Do a final recompute of the frame-related data. */
9805 s390_update_frame_layout ();
9807 /* If all special registers are in fact used, there's nothing we
9808 can do, so no point in walking the insn list. */
9810 if (cfun_frame_layout
.first_save_gpr
<= BASE_REGNUM
9811 && cfun_frame_layout
.last_save_gpr
>= BASE_REGNUM
9812 && (TARGET_CPU_ZARCH
9813 || (cfun_frame_layout
.first_save_gpr
<= RETURN_REGNUM
9814 && cfun_frame_layout
.last_save_gpr
>= RETURN_REGNUM
)))
9817 /* Search for prologue/epilogue insns and replace them. */
9819 for (insn
= get_insns (); insn
; insn
= next_insn
)
9821 int first
, last
, off
;
9822 rtx set
, base
, offset
;
9824 next_insn
= NEXT_INSN (insn
);
9826 if (GET_CODE (insn
) != INSN
)
9829 if (GET_CODE (PATTERN (insn
)) == PARALLEL
9830 && store_multiple_operation (PATTERN (insn
), VOIDmode
))
9832 set
= XVECEXP (PATTERN (insn
), 0, 0);
9833 first
= REGNO (SET_SRC (set
));
9834 last
= first
+ XVECLEN (PATTERN (insn
), 0) - 1;
9835 offset
= const0_rtx
;
9836 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
9837 off
= INTVAL (offset
);
9839 if (GET_CODE (base
) != REG
|| off
< 0)
9841 if (cfun_frame_layout
.first_save_gpr
!= -1
9842 && (cfun_frame_layout
.first_save_gpr
< first
9843 || cfun_frame_layout
.last_save_gpr
> last
))
9845 if (REGNO (base
) != STACK_POINTER_REGNUM
9846 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
9848 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
9851 if (cfun_frame_layout
.first_save_gpr
!= -1)
9853 new_insn
= save_gprs (base
,
9854 off
+ (cfun_frame_layout
.first_save_gpr
9855 - first
) * UNITS_PER_LONG
,
9856 cfun_frame_layout
.first_save_gpr
,
9857 cfun_frame_layout
.last_save_gpr
);
9858 new_insn
= emit_insn_before (new_insn
, insn
);
9859 INSN_ADDRESSES_NEW (new_insn
, -1);
9866 if (cfun_frame_layout
.first_save_gpr
== -1
9867 && GET_CODE (PATTERN (insn
)) == SET
9868 && GET_CODE (SET_SRC (PATTERN (insn
))) == REG
9869 && (REGNO (SET_SRC (PATTERN (insn
))) == BASE_REGNUM
9870 || (!TARGET_CPU_ZARCH
9871 && REGNO (SET_SRC (PATTERN (insn
))) == RETURN_REGNUM
))
9872 && GET_CODE (SET_DEST (PATTERN (insn
))) == MEM
)
9874 set
= PATTERN (insn
);
9875 first
= REGNO (SET_SRC (set
));
9876 offset
= const0_rtx
;
9877 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
9878 off
= INTVAL (offset
);
9880 if (GET_CODE (base
) != REG
|| off
< 0)
9882 if (REGNO (base
) != STACK_POINTER_REGNUM
9883 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
9890 if (GET_CODE (PATTERN (insn
)) == PARALLEL
9891 && load_multiple_operation (PATTERN (insn
), VOIDmode
))
9893 set
= XVECEXP (PATTERN (insn
), 0, 0);
9894 first
= REGNO (SET_DEST (set
));
9895 last
= first
+ XVECLEN (PATTERN (insn
), 0) - 1;
9896 offset
= const0_rtx
;
9897 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
9898 off
= INTVAL (offset
);
9900 if (GET_CODE (base
) != REG
|| off
< 0)
9902 if (cfun_frame_layout
.first_restore_gpr
!= -1
9903 && (cfun_frame_layout
.first_restore_gpr
< first
9904 || cfun_frame_layout
.last_restore_gpr
> last
))
9906 if (REGNO (base
) != STACK_POINTER_REGNUM
9907 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
9909 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
9912 if (cfun_frame_layout
.first_restore_gpr
!= -1)
9914 new_insn
= restore_gprs (base
,
9915 off
+ (cfun_frame_layout
.first_restore_gpr
9916 - first
) * UNITS_PER_LONG
,
9917 cfun_frame_layout
.first_restore_gpr
,
9918 cfun_frame_layout
.last_restore_gpr
);
9919 new_insn
= emit_insn_before (new_insn
, insn
);
9920 INSN_ADDRESSES_NEW (new_insn
, -1);
9927 if (cfun_frame_layout
.first_restore_gpr
== -1
9928 && GET_CODE (PATTERN (insn
)) == SET
9929 && GET_CODE (SET_DEST (PATTERN (insn
))) == REG
9930 && (REGNO (SET_DEST (PATTERN (insn
))) == BASE_REGNUM
9931 || (!TARGET_CPU_ZARCH
9932 && REGNO (SET_DEST (PATTERN (insn
))) == RETURN_REGNUM
))
9933 && GET_CODE (SET_SRC (PATTERN (insn
))) == MEM
)
9935 set
= PATTERN (insn
);
9936 first
= REGNO (SET_DEST (set
));
9937 offset
= const0_rtx
;
9938 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
9939 off
= INTVAL (offset
);
9941 if (GET_CODE (base
) != REG
|| off
< 0)
9943 if (REGNO (base
) != STACK_POINTER_REGNUM
9944 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
9953 /* On z10 and later the dynamic branch prediction must see the
9954 backward jump within a certain windows. If not it falls back to
9955 the static prediction. This function rearranges the loop backward
9956 branch in a way which makes the static prediction always correct.
9957 The function returns true if it added an instruction. */
9959 s390_fix_long_loop_prediction (rtx insn
)
9961 rtx set
= single_set (insn
);
9962 rtx code_label
, label_ref
, new_label
;
9968 /* This will exclude branch on count and branch on index patterns
9969 since these are correctly statically predicted. */
9971 || SET_DEST (set
) != pc_rtx
9972 || GET_CODE (SET_SRC(set
)) != IF_THEN_ELSE
)
9975 label_ref
= (GET_CODE (XEXP (SET_SRC (set
), 1)) == LABEL_REF
?
9976 XEXP (SET_SRC (set
), 1) : XEXP (SET_SRC (set
), 2));
9978 gcc_assert (GET_CODE (label_ref
) == LABEL_REF
);
9980 code_label
= XEXP (label_ref
, 0);
9982 if (INSN_ADDRESSES (INSN_UID (code_label
)) == -1
9983 || INSN_ADDRESSES (INSN_UID (insn
)) == -1
9984 || (INSN_ADDRESSES (INSN_UID (insn
))
9985 - INSN_ADDRESSES (INSN_UID (code_label
)) < PREDICT_DISTANCE
))
9988 for (distance
= 0, cur_insn
= PREV_INSN (insn
);
9989 distance
< PREDICT_DISTANCE
- 6;
9990 distance
+= get_attr_length (cur_insn
), cur_insn
= PREV_INSN (cur_insn
))
9991 if (!cur_insn
|| JUMP_P (cur_insn
) || LABEL_P (cur_insn
))
9994 new_label
= gen_label_rtx ();
9995 uncond_jump
= emit_jump_insn_after (
9996 gen_rtx_SET (VOIDmode
, pc_rtx
,
9997 gen_rtx_LABEL_REF (VOIDmode
, code_label
)),
9999 emit_label_after (new_label
, uncond_jump
);
10001 tmp
= XEXP (SET_SRC (set
), 1);
10002 XEXP (SET_SRC (set
), 1) = XEXP (SET_SRC (set
), 2);
10003 XEXP (SET_SRC (set
), 2) = tmp
;
10004 INSN_CODE (insn
) = -1;
10006 XEXP (label_ref
, 0) = new_label
;
10007 JUMP_LABEL (insn
) = new_label
;
10008 JUMP_LABEL (uncond_jump
) = code_label
;
10013 /* Returns 1 if INSN reads the value of REG for purposes not related
10014 to addressing of memory, and 0 otherwise. */
10016 s390_non_addr_reg_read_p (rtx reg
, rtx insn
)
10018 return reg_referenced_p (reg
, PATTERN (insn
))
10019 && !reg_used_in_mem_p (REGNO (reg
), PATTERN (insn
));
10022 /* Starting from INSN find_cond_jump looks downwards in the insn
10023 stream for a single jump insn which is the last user of the
10024 condition code set in INSN. */
10026 find_cond_jump (rtx insn
)
10028 for (; insn
; insn
= NEXT_INSN (insn
))
10032 if (LABEL_P (insn
))
10035 if (!JUMP_P (insn
))
10037 if (reg_mentioned_p (gen_rtx_REG (CCmode
, CC_REGNUM
), insn
))
10042 /* This will be triggered by a return. */
10043 if (GET_CODE (PATTERN (insn
)) != SET
)
10046 gcc_assert (SET_DEST (PATTERN (insn
)) == pc_rtx
);
10047 ite
= SET_SRC (PATTERN (insn
));
10049 if (GET_CODE (ite
) != IF_THEN_ELSE
)
10052 cc
= XEXP (XEXP (ite
, 0), 0);
10053 if (!REG_P (cc
) || !CC_REGNO_P (REGNO (cc
)))
10056 if (find_reg_note (insn
, REG_DEAD
, cc
))
10064 /* Swap the condition in COND and the operands in OP0 and OP1 so that
10065 the semantics does not change. If NULL_RTX is passed as COND the
10066 function tries to find the conditional jump starting with INSN. */
10068 s390_swap_cmp (rtx cond
, rtx
*op0
, rtx
*op1
, rtx insn
)
10072 if (cond
== NULL_RTX
)
10074 rtx jump
= find_cond_jump (NEXT_INSN (insn
));
10075 jump
= jump
? single_set (jump
) : NULL_RTX
;
10077 if (jump
== NULL_RTX
)
10080 cond
= XEXP (XEXP (jump
, 1), 0);
10085 PUT_CODE (cond
, swap_condition (GET_CODE (cond
)));
10088 /* On z10, instructions of the compare-and-branch family have the
10089 property to access the register occurring as second operand with
10090 its bits complemented. If such a compare is grouped with a second
10091 instruction that accesses the same register non-complemented, and
10092 if that register's value is delivered via a bypass, then the
10093 pipeline recycles, thereby causing significant performance decline.
10094 This function locates such situations and exchanges the two
10095 operands of the compare. The function return true whenever it
10098 s390_z10_optimize_cmp (rtx insn
)
10100 rtx prev_insn
, next_insn
;
10101 bool insn_added_p
= false;
10102 rtx cond
, *op0
, *op1
;
10104 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
10106 /* Handle compare and branch and branch on count
10108 rtx pattern
= single_set (insn
);
10111 || SET_DEST (pattern
) != pc_rtx
10112 || GET_CODE (SET_SRC (pattern
)) != IF_THEN_ELSE
)
10115 cond
= XEXP (SET_SRC (pattern
), 0);
10116 op0
= &XEXP (cond
, 0);
10117 op1
= &XEXP (cond
, 1);
10119 else if (GET_CODE (PATTERN (insn
)) == SET
)
10123 /* Handle normal compare instructions. */
10124 src
= SET_SRC (PATTERN (insn
));
10125 dest
= SET_DEST (PATTERN (insn
));
10128 || !CC_REGNO_P (REGNO (dest
))
10129 || GET_CODE (src
) != COMPARE
)
10132 /* s390_swap_cmp will try to find the conditional
10133 jump when passing NULL_RTX as condition. */
10135 op0
= &XEXP (src
, 0);
10136 op1
= &XEXP (src
, 1);
10141 if (!REG_P (*op0
) || !REG_P (*op1
))
10144 if (GET_MODE_CLASS (GET_MODE (*op0
)) != MODE_INT
)
10147 /* Swap the COMPARE arguments and its mask if there is a
10148 conflicting access in the previous insn. */
10149 prev_insn
= prev_active_insn (insn
);
10150 if (prev_insn
!= NULL_RTX
&& INSN_P (prev_insn
)
10151 && reg_referenced_p (*op1
, PATTERN (prev_insn
)))
10152 s390_swap_cmp (cond
, op0
, op1
, insn
);
10154 /* Check if there is a conflict with the next insn. If there
10155 was no conflict with the previous insn, then swap the
10156 COMPARE arguments and its mask. If we already swapped
10157 the operands, or if swapping them would cause a conflict
10158 with the previous insn, issue a NOP after the COMPARE in
10159 order to separate the two instuctions. */
10160 next_insn
= next_active_insn (insn
);
10161 if (next_insn
!= NULL_RTX
&& INSN_P (next_insn
)
10162 && s390_non_addr_reg_read_p (*op1
, next_insn
))
10164 if (prev_insn
!= NULL_RTX
&& INSN_P (prev_insn
)
10165 && s390_non_addr_reg_read_p (*op0
, prev_insn
))
10167 if (REGNO (*op1
) == 0)
10168 emit_insn_after (gen_nop1 (), insn
);
10170 emit_insn_after (gen_nop (), insn
);
10171 insn_added_p
= true;
10174 s390_swap_cmp (cond
, op0
, op1
, insn
);
10176 return insn_added_p
;
10179 /* Perform machine-dependent processing. */
10184 bool pool_overflow
= false;
10186 /* Make sure all splits have been performed; splits after
10187 machine_dependent_reorg might confuse insn length counts. */
10188 split_all_insns_noflow ();
10190 /* Install the main literal pool and the associated base
10191 register load insns.
10193 In addition, there are two problematic situations we need
10196 - the literal pool might be > 4096 bytes in size, so that
10197 some of its elements cannot be directly accessed
10199 - a branch target might be > 64K away from the branch, so that
10200 it is not possible to use a PC-relative instruction.
10202 To fix those, we split the single literal pool into multiple
10203 pool chunks, reloading the pool base register at various
10204 points throughout the function to ensure it always points to
10205 the pool chunk the following code expects, and / or replace
10206 PC-relative branches by absolute branches.
10208 However, the two problems are interdependent: splitting the
10209 literal pool can move a branch further away from its target,
10210 causing the 64K limit to overflow, and on the other hand,
10211 replacing a PC-relative branch by an absolute branch means
10212 we need to put the branch target address into the literal
10213 pool, possibly causing it to overflow.
10215 So, we loop trying to fix up both problems until we manage
10216 to satisfy both conditions at the same time. Note that the
10217 loop is guaranteed to terminate as every pass of the loop
10218 strictly decreases the total number of PC-relative branches
10219 in the function. (This is not completely true as there
10220 might be branch-over-pool insns introduced by chunkify_start.
10221 Those never need to be split however.) */
10225 struct constant_pool
*pool
= NULL
;
10227 /* Collect the literal pool. */
10228 if (!pool_overflow
)
10230 pool
= s390_mainpool_start ();
10232 pool_overflow
= true;
10235 /* If literal pool overflowed, start to chunkify it. */
10237 pool
= s390_chunkify_start ();
10239 /* Split out-of-range branches. If this has created new
10240 literal pool entries, cancel current chunk list and
10241 recompute it. zSeries machines have large branch
10242 instructions, so we never need to split a branch. */
10243 if (!TARGET_CPU_ZARCH
&& s390_split_branches ())
10246 s390_chunkify_cancel (pool
);
10248 s390_mainpool_cancel (pool
);
10253 /* If we made it up to here, both conditions are satisfied.
10254 Finish up literal pool related changes. */
10256 s390_chunkify_finish (pool
);
10258 s390_mainpool_finish (pool
);
10260 /* We're done splitting branches. */
10261 cfun
->machine
->split_branches_pending_p
= false;
10265 /* Generate out-of-pool execute target insns. */
10266 if (TARGET_CPU_ZARCH
)
10268 rtx insn
, label
, target
;
10270 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10272 label
= s390_execute_label (insn
);
10276 gcc_assert (label
!= const0_rtx
);
10278 target
= emit_label (XEXP (label
, 0));
10279 INSN_ADDRESSES_NEW (target
, -1);
10281 target
= emit_insn (s390_execute_target (insn
));
10282 INSN_ADDRESSES_NEW (target
, -1);
10286 /* Try to optimize prologue and epilogue further. */
10287 s390_optimize_prologue ();
10289 /* Walk over the insns and do some >=z10 specific changes. */
10290 if (s390_tune
== PROCESSOR_2097_Z10
10291 || s390_tune
== PROCESSOR_2817_Z196
)
10294 bool insn_added_p
= false;
10296 /* The insn lengths and addresses have to be up to date for the
10297 following manipulations. */
10298 shorten_branches (get_insns ());
10300 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10302 if (!INSN_P (insn
) || INSN_CODE (insn
) <= 0)
10306 insn_added_p
|= s390_fix_long_loop_prediction (insn
);
10308 if ((GET_CODE (PATTERN (insn
)) == PARALLEL
10309 || GET_CODE (PATTERN (insn
)) == SET
)
10310 && s390_tune
== PROCESSOR_2097_Z10
)
10311 insn_added_p
|= s390_z10_optimize_cmp (insn
);
10314 /* Adjust branches if we added new instructions. */
10316 shorten_branches (get_insns ());
10320 /* Return true if INSN is a fp load insn writing register REGNO. */
10322 s390_fpload_toreg (rtx insn
, unsigned int regno
)
10325 enum attr_type flag
= s390_safe_attr_type (insn
);
10327 if (flag
!= TYPE_FLOADSF
&& flag
!= TYPE_FLOADDF
)
10330 set
= single_set (insn
);
10332 if (set
== NULL_RTX
)
10335 if (!REG_P (SET_DEST (set
)) || !MEM_P (SET_SRC (set
)))
10338 if (REGNO (SET_DEST (set
)) != regno
)
10344 /* This value describes the distance to be avoided between an
10345 aritmetic fp instruction and an fp load writing the same register.
10346 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
10347 fine but the exact value has to be avoided. Otherwise the FP
10348 pipeline will throw an exception causing a major penalty. */
10349 #define Z10_EARLYLOAD_DISTANCE 7
10351 /* Rearrange the ready list in order to avoid the situation described
10352 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
10353 moved to the very end of the ready list. */
10355 s390_z10_prevent_earlyload_conflicts (rtx
*ready
, int *nready_p
)
10357 unsigned int regno
;
10358 int nready
= *nready_p
;
10363 enum attr_type flag
;
10366 /* Skip DISTANCE - 1 active insns. */
10367 for (insn
= last_scheduled_insn
, distance
= Z10_EARLYLOAD_DISTANCE
- 1;
10368 distance
> 0 && insn
!= NULL_RTX
;
10369 distance
--, insn
= prev_active_insn (insn
))
10370 if (CALL_P (insn
) || JUMP_P (insn
))
10373 if (insn
== NULL_RTX
)
10376 set
= single_set (insn
);
10378 if (set
== NULL_RTX
|| !REG_P (SET_DEST (set
))
10379 || GET_MODE_CLASS (GET_MODE (SET_DEST (set
))) != MODE_FLOAT
)
10382 flag
= s390_safe_attr_type (insn
);
10384 if (flag
== TYPE_FLOADSF
|| flag
== TYPE_FLOADDF
)
10387 regno
= REGNO (SET_DEST (set
));
10390 while (!s390_fpload_toreg (ready
[i
], regno
) && i
> 0)
10397 memmove (&ready
[1], &ready
[0], sizeof (rtx
) * i
);
10401 /* This function is called via hook TARGET_SCHED_REORDER before
10402 issueing one insn from list READY which contains *NREADYP entries.
10403 For target z10 it reorders load instructions to avoid early load
10404 conflicts in the floating point pipeline */
10406 s390_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
10407 rtx
*ready
, int *nreadyp
, int clock ATTRIBUTE_UNUSED
)
10409 if (s390_tune
== PROCESSOR_2097_Z10
)
10410 if (reload_completed
&& *nreadyp
> 1)
10411 s390_z10_prevent_earlyload_conflicts (ready
, nreadyp
);
10413 return s390_issue_rate ();
10416 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
10417 the scheduler has issued INSN. It stores the last issued insn into
10418 last_scheduled_insn in order to make it available for
10419 s390_sched_reorder. */
10421 s390_sched_variable_issue (FILE *file ATTRIBUTE_UNUSED
,
10422 int verbose ATTRIBUTE_UNUSED
,
10423 rtx insn
, int more
)
10425 last_scheduled_insn
= insn
;
10427 if (GET_CODE (PATTERN (insn
)) != USE
10428 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
10435 s390_sched_init (FILE *file ATTRIBUTE_UNUSED
,
10436 int verbose ATTRIBUTE_UNUSED
,
10437 int max_ready ATTRIBUTE_UNUSED
)
10439 last_scheduled_insn
= NULL_RTX
;
10442 /* This function checks the whole of insn X for memory references. The
10443 function always returns zero because the framework it is called
10444 from would stop recursively analyzing the insn upon a return value
10445 other than zero. The real result of this function is updating
10446 counter variable MEM_COUNT. */
10448 check_dpu (rtx
*x
, unsigned *mem_count
)
10450 if (*x
!= NULL_RTX
&& MEM_P (*x
))
10455 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
10456 a new number struct loop *loop should be unrolled if tuned for cpus with
10457 a built-in stride prefetcher.
10458 The loop is analyzed for memory accesses by calling check_dpu for
10459 each rtx of the loop. Depending on the loop_depth and the amount of
10460 memory accesses a new number <=nunroll is returned to improve the
10461 behaviour of the hardware prefetch unit. */
10463 s390_loop_unroll_adjust (unsigned nunroll
, struct loop
*loop
)
10468 unsigned mem_count
= 0;
10470 if (s390_tune
!= PROCESSOR_2097_Z10
&& s390_tune
!= PROCESSOR_2817_Z196
)
10473 /* Count the number of memory references within the loop body. */
10474 bbs
= get_loop_body (loop
);
10475 for (i
= 0; i
< loop
->num_nodes
; i
++)
10477 for (insn
= BB_HEAD (bbs
[i
]); insn
!= BB_END (bbs
[i
]); insn
= NEXT_INSN (insn
))
10478 if (INSN_P (insn
) && INSN_CODE (insn
) != -1)
10479 for_each_rtx (&insn
, (rtx_function
) check_dpu
, &mem_count
);
10483 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
10484 if (mem_count
== 0)
10487 switch (loop_depth(loop
))
10490 return MIN (nunroll
, 28 / mem_count
);
10492 return MIN (nunroll
, 22 / mem_count
);
10494 return MIN (nunroll
, 16 / mem_count
);
10498 /* Initialize GCC target structure. */
10500 #undef TARGET_ASM_ALIGNED_HI_OP
10501 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10502 #undef TARGET_ASM_ALIGNED_DI_OP
10503 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10504 #undef TARGET_ASM_INTEGER
10505 #define TARGET_ASM_INTEGER s390_assemble_integer
10507 #undef TARGET_ASM_OPEN_PAREN
10508 #define TARGET_ASM_OPEN_PAREN ""
10510 #undef TARGET_ASM_CLOSE_PAREN
10511 #define TARGET_ASM_CLOSE_PAREN ""
10513 #undef TARGET_DEFAULT_TARGET_FLAGS
10514 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
10516 #undef TARGET_HANDLE_OPTION
10517 #define TARGET_HANDLE_OPTION s390_handle_option
10519 #undef TARGET_OPTION_OVERRIDE
10520 #define TARGET_OPTION_OVERRIDE s390_option_override
10522 #undef TARGET_OPTION_OPTIMIZATION_TABLE
10523 #define TARGET_OPTION_OPTIMIZATION_TABLE s390_option_optimization_table
10525 #undef TARGET_OPTION_INIT_STRUCT
10526 #define TARGET_OPTION_INIT_STRUCT s390_option_init_struct
10528 #undef TARGET_ENCODE_SECTION_INFO
10529 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
10531 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10532 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10535 #undef TARGET_HAVE_TLS
10536 #define TARGET_HAVE_TLS true
10538 #undef TARGET_CANNOT_FORCE_CONST_MEM
10539 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
10541 #undef TARGET_DELEGITIMIZE_ADDRESS
10542 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
10544 #undef TARGET_LEGITIMIZE_ADDRESS
10545 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
10547 #undef TARGET_RETURN_IN_MEMORY
10548 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
10550 #undef TARGET_INIT_BUILTINS
10551 #define TARGET_INIT_BUILTINS s390_init_builtins
10552 #undef TARGET_EXPAND_BUILTIN
10553 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
10555 #undef TARGET_ASM_OUTPUT_MI_THUNK
10556 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
10557 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10558 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
10560 #undef TARGET_SCHED_ADJUST_PRIORITY
10561 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
10562 #undef TARGET_SCHED_ISSUE_RATE
10563 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
10564 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10565 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
10567 #undef TARGET_SCHED_VARIABLE_ISSUE
10568 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
10569 #undef TARGET_SCHED_REORDER
10570 #define TARGET_SCHED_REORDER s390_sched_reorder
10571 #undef TARGET_SCHED_INIT
10572 #define TARGET_SCHED_INIT s390_sched_init
10574 #undef TARGET_CANNOT_COPY_INSN_P
10575 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
10576 #undef TARGET_RTX_COSTS
10577 #define TARGET_RTX_COSTS s390_rtx_costs
10578 #undef TARGET_ADDRESS_COST
10579 #define TARGET_ADDRESS_COST s390_address_cost
10581 #undef TARGET_MACHINE_DEPENDENT_REORG
10582 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
10584 #undef TARGET_VALID_POINTER_MODE
10585 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
10587 #undef TARGET_BUILD_BUILTIN_VA_LIST
10588 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
10589 #undef TARGET_EXPAND_BUILTIN_VA_START
10590 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
10591 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
10592 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
10594 #undef TARGET_PROMOTE_FUNCTION_MODE
10595 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
10596 #undef TARGET_PASS_BY_REFERENCE
10597 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
10599 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10600 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
10601 #undef TARGET_FUNCTION_ARG
10602 #define TARGET_FUNCTION_ARG s390_function_arg
10603 #undef TARGET_FUNCTION_ARG_ADVANCE
10604 #define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance
10606 #undef TARGET_FIXED_CONDITION_CODE_REGS
10607 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
10609 #undef TARGET_CC_MODES_COMPATIBLE
10610 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
10612 #undef TARGET_INVALID_WITHIN_DOLOOP
10613 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
10616 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
10617 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
10620 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10621 #undef TARGET_MANGLE_TYPE
10622 #define TARGET_MANGLE_TYPE s390_mangle_type
10625 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10626 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10628 #undef TARGET_SECONDARY_RELOAD
10629 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
10631 #undef TARGET_LIBGCC_CMP_RETURN_MODE
10632 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
10634 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
10635 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
10637 #undef TARGET_LEGITIMATE_ADDRESS_P
10638 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
10640 #undef TARGET_CAN_ELIMINATE
10641 #define TARGET_CAN_ELIMINATE s390_can_eliminate
10643 #undef TARGET_LOOP_UNROLL_ADJUST
10644 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
10646 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
10647 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
10648 #undef TARGET_TRAMPOLINE_INIT
10649 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
10651 #undef TARGET_UNWIND_WORD_MODE
10652 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
10654 struct gcc_target targetm
= TARGET_INITIALIZER
;
10656 #include "gt-s390.h"