1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com) and
6 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
32 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "diagnostic-core.h"
44 #include "basic-block.h"
45 #include "integrate.h"
48 #include "target-def.h"
50 #include "langhooks.h"
58 /* Define the specific costs for a given cpu. */
60 struct processor_costs
63 const int m
; /* cost of an M instruction. */
64 const int mghi
; /* cost of an MGHI instruction. */
65 const int mh
; /* cost of an MH instruction. */
66 const int mhi
; /* cost of an MHI instruction. */
67 const int ml
; /* cost of an ML instruction. */
68 const int mr
; /* cost of an MR instruction. */
69 const int ms
; /* cost of an MS instruction. */
70 const int msg
; /* cost of an MSG instruction. */
71 const int msgf
; /* cost of an MSGF instruction. */
72 const int msgfr
; /* cost of an MSGFR instruction. */
73 const int msgr
; /* cost of an MSGR instruction. */
74 const int msr
; /* cost of an MSR instruction. */
75 const int mult_df
; /* cost of multiplication in DFmode. */
78 const int sqxbr
; /* cost of square root in TFmode. */
79 const int sqdbr
; /* cost of square root in DFmode. */
80 const int sqebr
; /* cost of square root in SFmode. */
81 /* multiply and add */
82 const int madbr
; /* cost of multiply and add in DFmode. */
83 const int maebr
; /* cost of multiply and add in SFmode. */
95 const struct processor_costs
*s390_cost
;
98 struct processor_costs z900_cost
=
100 COSTS_N_INSNS (5), /* M */
101 COSTS_N_INSNS (10), /* MGHI */
102 COSTS_N_INSNS (5), /* MH */
103 COSTS_N_INSNS (4), /* MHI */
104 COSTS_N_INSNS (5), /* ML */
105 COSTS_N_INSNS (5), /* MR */
106 COSTS_N_INSNS (4), /* MS */
107 COSTS_N_INSNS (15), /* MSG */
108 COSTS_N_INSNS (7), /* MSGF */
109 COSTS_N_INSNS (7), /* MSGFR */
110 COSTS_N_INSNS (10), /* MSGR */
111 COSTS_N_INSNS (4), /* MSR */
112 COSTS_N_INSNS (7), /* multiplication in DFmode */
113 COSTS_N_INSNS (13), /* MXBR */
114 COSTS_N_INSNS (136), /* SQXBR */
115 COSTS_N_INSNS (44), /* SQDBR */
116 COSTS_N_INSNS (35), /* SQEBR */
117 COSTS_N_INSNS (18), /* MADBR */
118 COSTS_N_INSNS (13), /* MAEBR */
119 COSTS_N_INSNS (134), /* DXBR */
120 COSTS_N_INSNS (30), /* DDBR */
121 COSTS_N_INSNS (27), /* DEBR */
122 COSTS_N_INSNS (220), /* DLGR */
123 COSTS_N_INSNS (34), /* DLR */
124 COSTS_N_INSNS (34), /* DR */
125 COSTS_N_INSNS (32), /* DSGFR */
126 COSTS_N_INSNS (32), /* DSGR */
130 struct processor_costs z990_cost
=
132 COSTS_N_INSNS (4), /* M */
133 COSTS_N_INSNS (2), /* MGHI */
134 COSTS_N_INSNS (2), /* MH */
135 COSTS_N_INSNS (2), /* MHI */
136 COSTS_N_INSNS (4), /* ML */
137 COSTS_N_INSNS (4), /* MR */
138 COSTS_N_INSNS (5), /* MS */
139 COSTS_N_INSNS (6), /* MSG */
140 COSTS_N_INSNS (4), /* MSGF */
141 COSTS_N_INSNS (4), /* MSGFR */
142 COSTS_N_INSNS (4), /* MSGR */
143 COSTS_N_INSNS (4), /* MSR */
144 COSTS_N_INSNS (1), /* multiplication in DFmode */
145 COSTS_N_INSNS (28), /* MXBR */
146 COSTS_N_INSNS (130), /* SQXBR */
147 COSTS_N_INSNS (66), /* SQDBR */
148 COSTS_N_INSNS (38), /* SQEBR */
149 COSTS_N_INSNS (1), /* MADBR */
150 COSTS_N_INSNS (1), /* MAEBR */
151 COSTS_N_INSNS (60), /* DXBR */
152 COSTS_N_INSNS (40), /* DDBR */
153 COSTS_N_INSNS (26), /* DEBR */
154 COSTS_N_INSNS (176), /* DLGR */
155 COSTS_N_INSNS (31), /* DLR */
156 COSTS_N_INSNS (31), /* DR */
157 COSTS_N_INSNS (31), /* DSGFR */
158 COSTS_N_INSNS (31), /* DSGR */
162 struct processor_costs z9_109_cost
=
164 COSTS_N_INSNS (4), /* M */
165 COSTS_N_INSNS (2), /* MGHI */
166 COSTS_N_INSNS (2), /* MH */
167 COSTS_N_INSNS (2), /* MHI */
168 COSTS_N_INSNS (4), /* ML */
169 COSTS_N_INSNS (4), /* MR */
170 COSTS_N_INSNS (5), /* MS */
171 COSTS_N_INSNS (6), /* MSG */
172 COSTS_N_INSNS (4), /* MSGF */
173 COSTS_N_INSNS (4), /* MSGFR */
174 COSTS_N_INSNS (4), /* MSGR */
175 COSTS_N_INSNS (4), /* MSR */
176 COSTS_N_INSNS (1), /* multiplication in DFmode */
177 COSTS_N_INSNS (28), /* MXBR */
178 COSTS_N_INSNS (130), /* SQXBR */
179 COSTS_N_INSNS (66), /* SQDBR */
180 COSTS_N_INSNS (38), /* SQEBR */
181 COSTS_N_INSNS (1), /* MADBR */
182 COSTS_N_INSNS (1), /* MAEBR */
183 COSTS_N_INSNS (60), /* DXBR */
184 COSTS_N_INSNS (40), /* DDBR */
185 COSTS_N_INSNS (26), /* DEBR */
186 COSTS_N_INSNS (30), /* DLGR */
187 COSTS_N_INSNS (23), /* DLR */
188 COSTS_N_INSNS (23), /* DR */
189 COSTS_N_INSNS (24), /* DSGFR */
190 COSTS_N_INSNS (24), /* DSGR */
194 struct processor_costs z10_cost
=
196 COSTS_N_INSNS (10), /* M */
197 COSTS_N_INSNS (10), /* MGHI */
198 COSTS_N_INSNS (10), /* MH */
199 COSTS_N_INSNS (10), /* MHI */
200 COSTS_N_INSNS (10), /* ML */
201 COSTS_N_INSNS (10), /* MR */
202 COSTS_N_INSNS (10), /* MS */
203 COSTS_N_INSNS (10), /* MSG */
204 COSTS_N_INSNS (10), /* MSGF */
205 COSTS_N_INSNS (10), /* MSGFR */
206 COSTS_N_INSNS (10), /* MSGR */
207 COSTS_N_INSNS (10), /* MSR */
208 COSTS_N_INSNS (1) , /* multiplication in DFmode */
209 COSTS_N_INSNS (50), /* MXBR */
210 COSTS_N_INSNS (120), /* SQXBR */
211 COSTS_N_INSNS (52), /* SQDBR */
212 COSTS_N_INSNS (38), /* SQEBR */
213 COSTS_N_INSNS (1), /* MADBR */
214 COSTS_N_INSNS (1), /* MAEBR */
215 COSTS_N_INSNS (111), /* DXBR */
216 COSTS_N_INSNS (39), /* DDBR */
217 COSTS_N_INSNS (32), /* DEBR */
218 COSTS_N_INSNS (160), /* DLGR */
219 COSTS_N_INSNS (71), /* DLR */
220 COSTS_N_INSNS (71), /* DR */
221 COSTS_N_INSNS (71), /* DSGFR */
222 COSTS_N_INSNS (71), /* DSGR */
226 struct processor_costs z196_cost
=
228 COSTS_N_INSNS (7), /* M */
229 COSTS_N_INSNS (5), /* MGHI */
230 COSTS_N_INSNS (5), /* MH */
231 COSTS_N_INSNS (5), /* MHI */
232 COSTS_N_INSNS (7), /* ML */
233 COSTS_N_INSNS (7), /* MR */
234 COSTS_N_INSNS (6), /* MS */
235 COSTS_N_INSNS (8), /* MSG */
236 COSTS_N_INSNS (6), /* MSGF */
237 COSTS_N_INSNS (6), /* MSGFR */
238 COSTS_N_INSNS (8), /* MSGR */
239 COSTS_N_INSNS (6), /* MSR */
240 COSTS_N_INSNS (1) , /* multiplication in DFmode */
241 COSTS_N_INSNS (40), /* MXBR B+40 */
242 COSTS_N_INSNS (100), /* SQXBR B+100 */
243 COSTS_N_INSNS (42), /* SQDBR B+42 */
244 COSTS_N_INSNS (28), /* SQEBR B+28 */
245 COSTS_N_INSNS (1), /* MADBR B */
246 COSTS_N_INSNS (1), /* MAEBR B */
247 COSTS_N_INSNS (101), /* DXBR B+101 */
248 COSTS_N_INSNS (29), /* DDBR */
249 COSTS_N_INSNS (22), /* DEBR */
250 COSTS_N_INSNS (160), /* DLGR cracked */
251 COSTS_N_INSNS (160), /* DLR cracked */
252 COSTS_N_INSNS (160), /* DR expanded */
253 COSTS_N_INSNS (160), /* DSGFR cracked */
254 COSTS_N_INSNS (160), /* DSGR cracked */
257 extern int reload_completed
;
259 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
260 static rtx last_scheduled_insn
;
262 /* Structure used to hold the components of a S/390 memory
263 address. A legitimate address on S/390 is of the general
265 base + index + displacement
266 where any of the components is optional.
268 base and index are registers of the class ADDR_REGS,
269 displacement is an unsigned 12-bit immediate constant. */
280 /* The following structure is embedded in the machine
281 specific part of struct function. */
283 struct GTY (()) s390_frame_layout
285 /* Offset within stack frame. */
286 HOST_WIDE_INT gprs_offset
;
287 HOST_WIDE_INT f0_offset
;
288 HOST_WIDE_INT f4_offset
;
289 HOST_WIDE_INT f8_offset
;
290 HOST_WIDE_INT backchain_offset
;
292 /* Number of first and last gpr where slots in the register
293 save area are reserved for. */
294 int first_save_gpr_slot
;
295 int last_save_gpr_slot
;
297 /* Number of first and last gpr to be saved, restored. */
299 int first_restore_gpr
;
301 int last_restore_gpr
;
303 /* Bits standing for floating point registers. Set, if the
304 respective register has to be saved. Starting with reg 16 (f0)
305 at the rightmost bit.
306 Bit 15 - 8 7 6 5 4 3 2 1 0
307 fpr 15 - 8 7 5 3 1 6 4 2 0
308 reg 31 - 24 23 22 21 20 19 18 17 16 */
309 unsigned int fpr_bitmap
;
311 /* Number of floating point registers f8-f15 which must be saved. */
314 /* Set if return address needs to be saved.
315 This flag is set by s390_return_addr_rtx if it could not use
316 the initial value of r14 and therefore depends on r14 saved
318 bool save_return_addr_p
;
320 /* Size of stack frame. */
321 HOST_WIDE_INT frame_size
;
324 /* Define the structure for the machine field in struct function. */
326 struct GTY(()) machine_function
328 struct s390_frame_layout frame_layout
;
330 /* Literal pool base register. */
333 /* True if we may need to perform branch splitting. */
334 bool split_branches_pending_p
;
336 /* Some local-dynamic TLS symbol name. */
337 const char *some_ld_name
;
339 bool has_landing_pad_p
;
342 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
344 #define cfun_frame_layout (cfun->machine->frame_layout)
345 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
346 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
347 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
348 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
350 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
353 /* Number of GPRs and FPRs used for argument passing. */
354 #define GP_ARG_NUM_REG 5
355 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
357 /* A couple of shortcuts. */
358 #define CONST_OK_FOR_J(x) \
359 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
360 #define CONST_OK_FOR_K(x) \
361 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
362 #define CONST_OK_FOR_Os(x) \
363 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
364 #define CONST_OK_FOR_Op(x) \
365 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
366 #define CONST_OK_FOR_On(x) \
367 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
369 #define REGNO_PAIR_OK(REGNO, MODE) \
370 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
372 /* That's the read ahead of the dynamic branch prediction unit in
373 bytes on a z10 (or higher) CPU. */
374 #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
376 /* Return the alignment for LABEL. We default to the -falign-labels
377 value except for the literal pool base label. */
379 s390_label_align (rtx label
)
381 rtx prev_insn
= prev_active_insn (label
);
383 if (prev_insn
== NULL_RTX
)
386 prev_insn
= single_set (prev_insn
);
388 if (prev_insn
== NULL_RTX
)
391 prev_insn
= SET_SRC (prev_insn
);
393 /* Don't align literal pool base labels. */
394 if (GET_CODE (prev_insn
) == UNSPEC
395 && XINT (prev_insn
, 1) == UNSPEC_MAIN_BASE
)
399 return align_labels_log
;
402 static enum machine_mode
403 s390_libgcc_cmp_return_mode (void)
405 return TARGET_64BIT
? DImode
: SImode
;
408 static enum machine_mode
409 s390_libgcc_shift_count_mode (void)
411 return TARGET_64BIT
? DImode
: SImode
;
414 static enum machine_mode
415 s390_unwind_word_mode (void)
417 return TARGET_64BIT
? DImode
: SImode
;
420 /* Return true if the back end supports mode MODE. */
422 s390_scalar_mode_supported_p (enum machine_mode mode
)
424 /* In contrast to the default implementation reject TImode constants on 31bit
425 TARGET_ZARCH for ABI compliance. */
426 if (!TARGET_64BIT
&& TARGET_ZARCH
&& mode
== TImode
)
429 if (DECIMAL_FLOAT_MODE_P (mode
))
430 return default_decimal_float_supported_p ();
432 return default_scalar_mode_supported_p (mode
);
435 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
438 s390_set_has_landing_pad_p (bool value
)
440 cfun
->machine
->has_landing_pad_p
= value
;
443 /* If two condition code modes are compatible, return a condition code
444 mode which is compatible with both. Otherwise, return
447 static enum machine_mode
448 s390_cc_modes_compatible (enum machine_mode m1
, enum machine_mode m2
)
456 if (m2
== CCUmode
|| m2
== CCTmode
|| m2
== CCZ1mode
457 || m2
== CCSmode
|| m2
== CCSRmode
|| m2
== CCURmode
)
478 /* Return true if SET either doesn't set the CC register, or else
479 the source and destination have matching CC modes and that
480 CC mode is at least as constrained as REQ_MODE. */
483 s390_match_ccmode_set (rtx set
, enum machine_mode req_mode
)
485 enum machine_mode set_mode
;
487 gcc_assert (GET_CODE (set
) == SET
);
489 if (GET_CODE (SET_DEST (set
)) != REG
|| !CC_REGNO_P (REGNO (SET_DEST (set
))))
492 set_mode
= GET_MODE (SET_DEST (set
));
506 if (req_mode
!= set_mode
)
511 if (req_mode
!= CCSmode
&& req_mode
!= CCUmode
&& req_mode
!= CCTmode
512 && req_mode
!= CCSRmode
&& req_mode
!= CCURmode
)
518 if (req_mode
!= CCAmode
)
526 return (GET_MODE (SET_SRC (set
)) == set_mode
);
529 /* Return true if every SET in INSN that sets the CC register
530 has source and destination with matching CC modes and that
531 CC mode is at least as constrained as REQ_MODE.
532 If REQ_MODE is VOIDmode, always return false. */
535 s390_match_ccmode (rtx insn
, enum machine_mode req_mode
)
539 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
540 if (req_mode
== VOIDmode
)
543 if (GET_CODE (PATTERN (insn
)) == SET
)
544 return s390_match_ccmode_set (PATTERN (insn
), req_mode
);
546 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
547 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
549 rtx set
= XVECEXP (PATTERN (insn
), 0, i
);
550 if (GET_CODE (set
) == SET
)
551 if (!s390_match_ccmode_set (set
, req_mode
))
558 /* If a test-under-mask instruction can be used to implement
559 (compare (and ... OP1) OP2), return the CC mode required
560 to do that. Otherwise, return VOIDmode.
561 MIXED is true if the instruction can distinguish between
562 CC1 and CC2 for mixed selected bits (TMxx), it is false
563 if the instruction cannot (TM). */
566 s390_tm_ccmode (rtx op1
, rtx op2
, bool mixed
)
570 /* ??? Fixme: should work on CONST_DOUBLE as well. */
571 if (GET_CODE (op1
) != CONST_INT
|| GET_CODE (op2
) != CONST_INT
)
574 /* Selected bits all zero: CC0.
575 e.g.: int a; if ((a & (16 + 128)) == 0) */
576 if (INTVAL (op2
) == 0)
579 /* Selected bits all one: CC3.
580 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
581 if (INTVAL (op2
) == INTVAL (op1
))
584 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
586 if ((a & (16 + 128)) == 16) -> CCT1
587 if ((a & (16 + 128)) == 128) -> CCT2 */
590 bit1
= exact_log2 (INTVAL (op2
));
591 bit0
= exact_log2 (INTVAL (op1
) ^ INTVAL (op2
));
592 if (bit0
!= -1 && bit1
!= -1)
593 return bit0
> bit1
? CCT1mode
: CCT2mode
;
599 /* Given a comparison code OP (EQ, NE, etc.) and the operands
600 OP0 and OP1 of a COMPARE, return the mode to be used for the
604 s390_select_ccmode (enum rtx_code code
, rtx op0
, rtx op1
)
610 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
611 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
613 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
614 && CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1))))
616 if ((GET_CODE (op0
) == PLUS
|| GET_CODE (op0
) == MINUS
617 || GET_CODE (op1
) == NEG
)
618 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
621 if (GET_CODE (op0
) == AND
)
623 /* Check whether we can potentially do it via TM. */
624 enum machine_mode ccmode
;
625 ccmode
= s390_tm_ccmode (XEXP (op0
, 1), op1
, 1);
626 if (ccmode
!= VOIDmode
)
628 /* Relax CCTmode to CCZmode to allow fall-back to AND
629 if that turns out to be beneficial. */
630 return ccmode
== CCTmode
? CCZmode
: ccmode
;
634 if (register_operand (op0
, HImode
)
635 && GET_CODE (op1
) == CONST_INT
636 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 65535))
638 if (register_operand (op0
, QImode
)
639 && GET_CODE (op1
) == CONST_INT
640 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 255))
649 /* The only overflow condition of NEG and ABS happens when
650 -INT_MAX is used as parameter, which stays negative. So
651 we have an overflow from a positive value to a negative.
652 Using CCAP mode the resulting cc can be used for comparisons. */
653 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
654 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
657 /* If constants are involved in an add instruction it is possible to use
658 the resulting cc for comparisons with zero. Knowing the sign of the
659 constant the overflow behavior gets predictable. e.g.:
660 int a, b; if ((b = a + c) > 0)
661 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
662 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
663 && CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1))))
665 if (INTVAL (XEXP((op0
), 1)) < 0)
679 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
680 && GET_CODE (op1
) != CONST_INT
)
686 if (GET_CODE (op0
) == PLUS
687 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
690 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
691 && GET_CODE (op1
) != CONST_INT
)
697 if (GET_CODE (op0
) == MINUS
698 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
701 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
702 && GET_CODE (op1
) != CONST_INT
)
711 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
712 that we can implement more efficiently. */
715 s390_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
)
717 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
718 if ((*code
== EQ
|| *code
== NE
)
719 && *op1
== const0_rtx
720 && GET_CODE (*op0
) == ZERO_EXTRACT
721 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
722 && GET_CODE (XEXP (*op0
, 2)) == CONST_INT
723 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
725 rtx inner
= XEXP (*op0
, 0);
726 HOST_WIDE_INT modesize
= GET_MODE_BITSIZE (GET_MODE (inner
));
727 HOST_WIDE_INT len
= INTVAL (XEXP (*op0
, 1));
728 HOST_WIDE_INT pos
= INTVAL (XEXP (*op0
, 2));
730 if (len
> 0 && len
< modesize
731 && pos
>= 0 && pos
+ len
<= modesize
732 && modesize
<= HOST_BITS_PER_WIDE_INT
)
734 unsigned HOST_WIDE_INT block
;
735 block
= ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
736 block
<<= modesize
- pos
- len
;
738 *op0
= gen_rtx_AND (GET_MODE (inner
), inner
,
739 gen_int_mode (block
, GET_MODE (inner
)));
743 /* Narrow AND of memory against immediate to enable TM. */
744 if ((*code
== EQ
|| *code
== NE
)
745 && *op1
== const0_rtx
746 && GET_CODE (*op0
) == AND
747 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
748 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
750 rtx inner
= XEXP (*op0
, 0);
751 rtx mask
= XEXP (*op0
, 1);
753 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
754 if (GET_CODE (inner
) == SUBREG
755 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner
)))
756 && (GET_MODE_SIZE (GET_MODE (inner
))
757 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner
))))
759 & GET_MODE_MASK (GET_MODE (inner
))
760 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner
))))
762 inner
= SUBREG_REG (inner
);
764 /* Do not change volatile MEMs. */
765 if (MEM_P (inner
) && !MEM_VOLATILE_P (inner
))
767 int part
= s390_single_part (XEXP (*op0
, 1),
768 GET_MODE (inner
), QImode
, 0);
771 mask
= gen_int_mode (s390_extract_part (mask
, QImode
, 0), QImode
);
772 inner
= adjust_address_nv (inner
, QImode
, part
);
773 *op0
= gen_rtx_AND (QImode
, inner
, mask
);
778 /* Narrow comparisons against 0xffff to HImode if possible. */
779 if ((*code
== EQ
|| *code
== NE
)
780 && GET_CODE (*op1
) == CONST_INT
781 && INTVAL (*op1
) == 0xffff
782 && SCALAR_INT_MODE_P (GET_MODE (*op0
))
783 && (nonzero_bits (*op0
, GET_MODE (*op0
))
784 & ~(unsigned HOST_WIDE_INT
) 0xffff) == 0)
786 *op0
= gen_lowpart (HImode
, *op0
);
790 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
791 if (GET_CODE (*op0
) == UNSPEC
792 && XINT (*op0
, 1) == UNSPEC_CCU_TO_INT
793 && XVECLEN (*op0
, 0) == 1
794 && GET_MODE (XVECEXP (*op0
, 0, 0)) == CCUmode
795 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
796 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
797 && *op1
== const0_rtx
)
799 enum rtx_code new_code
= UNKNOWN
;
802 case EQ
: new_code
= EQ
; break;
803 case NE
: new_code
= NE
; break;
804 case LT
: new_code
= GTU
; break;
805 case GT
: new_code
= LTU
; break;
806 case LE
: new_code
= GEU
; break;
807 case GE
: new_code
= LEU
; break;
811 if (new_code
!= UNKNOWN
)
813 *op0
= XVECEXP (*op0
, 0, 0);
818 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
819 if (GET_CODE (*op0
) == UNSPEC
820 && XINT (*op0
, 1) == UNSPEC_CCZ_TO_INT
821 && XVECLEN (*op0
, 0) == 1
822 && GET_MODE (XVECEXP (*op0
, 0, 0)) == CCZmode
823 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
824 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
825 && *op1
== const0_rtx
)
827 enum rtx_code new_code
= UNKNOWN
;
830 case EQ
: new_code
= EQ
; break;
831 case NE
: new_code
= NE
; break;
835 if (new_code
!= UNKNOWN
)
837 *op0
= XVECEXP (*op0
, 0, 0);
842 /* Simplify cascaded EQ, NE with const0_rtx. */
843 if ((*code
== NE
|| *code
== EQ
)
844 && (GET_CODE (*op0
) == EQ
|| GET_CODE (*op0
) == NE
)
845 && GET_MODE (*op0
) == SImode
846 && GET_MODE (XEXP (*op0
, 0)) == CCZ1mode
847 && REG_P (XEXP (*op0
, 0))
848 && XEXP (*op0
, 1) == const0_rtx
849 && *op1
== const0_rtx
)
851 if ((*code
== EQ
&& GET_CODE (*op0
) == NE
)
852 || (*code
== NE
&& GET_CODE (*op0
) == EQ
))
856 *op0
= XEXP (*op0
, 0);
859 /* Prefer register over memory as first operand. */
860 if (MEM_P (*op0
) && REG_P (*op1
))
862 rtx tem
= *op0
; *op0
= *op1
; *op1
= tem
;
863 *code
= swap_condition (*code
);
867 /* Emit a compare instruction suitable to implement the comparison
868 OP0 CODE OP1. Return the correct condition RTL to be placed in
869 the IF_THEN_ELSE of the conditional branch testing the result. */
872 s390_emit_compare (enum rtx_code code
, rtx op0
, rtx op1
)
874 enum machine_mode mode
= s390_select_ccmode (code
, op0
, op1
);
877 /* Do not output a redundant compare instruction if a compare_and_swap
878 pattern already computed the result and the machine modes are compatible. */
879 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
881 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0
), mode
)
887 cc
= gen_rtx_REG (mode
, CC_REGNUM
);
888 emit_insn (gen_rtx_SET (VOIDmode
, cc
, gen_rtx_COMPARE (mode
, op0
, op1
)));
891 return gen_rtx_fmt_ee (code
, VOIDmode
, cc
, const0_rtx
);
894 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
896 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
897 conditional branch testing the result. */
900 s390_emit_compare_and_swap (enum rtx_code code
, rtx old
, rtx mem
, rtx cmp
, rtx new_rtx
)
902 emit_insn (gen_sync_compare_and_swapsi (old
, mem
, cmp
, new_rtx
));
903 return s390_emit_compare (code
, gen_rtx_REG (CCZ1mode
, CC_REGNUM
), const0_rtx
);
906 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
907 unconditional jump, else a conditional jump under condition COND. */
910 s390_emit_jump (rtx target
, rtx cond
)
914 target
= gen_rtx_LABEL_REF (VOIDmode
, target
);
916 target
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, target
, pc_rtx
);
918 insn
= gen_rtx_SET (VOIDmode
, pc_rtx
, target
);
919 emit_jump_insn (insn
);
922 /* Return branch condition mask to implement a branch
923 specified by CODE. Return -1 for invalid comparisons. */
926 s390_branch_condition_mask (rtx code
)
928 const int CC0
= 1 << 3;
929 const int CC1
= 1 << 2;
930 const int CC2
= 1 << 1;
931 const int CC3
= 1 << 0;
933 gcc_assert (GET_CODE (XEXP (code
, 0)) == REG
);
934 gcc_assert (REGNO (XEXP (code
, 0)) == CC_REGNUM
);
935 gcc_assert (XEXP (code
, 1) == const0_rtx
);
937 switch (GET_MODE (XEXP (code
, 0)))
941 switch (GET_CODE (code
))
944 case NE
: return CC1
| CC2
| CC3
;
950 switch (GET_CODE (code
))
953 case NE
: return CC0
| CC2
| CC3
;
959 switch (GET_CODE (code
))
962 case NE
: return CC0
| CC1
| CC3
;
968 switch (GET_CODE (code
))
971 case NE
: return CC0
| CC1
| CC2
;
977 switch (GET_CODE (code
))
979 case EQ
: return CC0
| CC2
;
980 case NE
: return CC1
| CC3
;
986 switch (GET_CODE (code
))
988 case LTU
: return CC2
| CC3
; /* carry */
989 case GEU
: return CC0
| CC1
; /* no carry */
995 switch (GET_CODE (code
))
997 case GTU
: return CC0
| CC1
; /* borrow */
998 case LEU
: return CC2
| CC3
; /* no borrow */
1004 switch (GET_CODE (code
))
1006 case EQ
: return CC0
| CC2
;
1007 case NE
: return CC1
| CC3
;
1008 case LTU
: return CC1
;
1009 case GTU
: return CC3
;
1010 case LEU
: return CC1
| CC2
;
1011 case GEU
: return CC2
| CC3
;
1016 switch (GET_CODE (code
))
1018 case EQ
: return CC0
;
1019 case NE
: return CC1
| CC2
| CC3
;
1020 case LTU
: return CC1
;
1021 case GTU
: return CC2
;
1022 case LEU
: return CC0
| CC1
;
1023 case GEU
: return CC0
| CC2
;
1029 switch (GET_CODE (code
))
1031 case EQ
: return CC0
;
1032 case NE
: return CC2
| CC1
| CC3
;
1033 case LTU
: return CC2
;
1034 case GTU
: return CC1
;
1035 case LEU
: return CC0
| CC2
;
1036 case GEU
: return CC0
| CC1
;
1042 switch (GET_CODE (code
))
1044 case EQ
: return CC0
;
1045 case NE
: return CC1
| CC2
| CC3
;
1046 case LT
: return CC1
| CC3
;
1047 case GT
: return CC2
;
1048 case LE
: return CC0
| CC1
| CC3
;
1049 case GE
: return CC0
| CC2
;
1055 switch (GET_CODE (code
))
1057 case EQ
: return CC0
;
1058 case NE
: return CC1
| CC2
| CC3
;
1059 case LT
: return CC1
;
1060 case GT
: return CC2
| CC3
;
1061 case LE
: return CC0
| CC1
;
1062 case GE
: return CC0
| CC2
| CC3
;
1068 switch (GET_CODE (code
))
1070 case EQ
: return CC0
;
1071 case NE
: return CC1
| CC2
| CC3
;
1072 case LT
: return CC1
;
1073 case GT
: return CC2
;
1074 case LE
: return CC0
| CC1
;
1075 case GE
: return CC0
| CC2
;
1076 case UNORDERED
: return CC3
;
1077 case ORDERED
: return CC0
| CC1
| CC2
;
1078 case UNEQ
: return CC0
| CC3
;
1079 case UNLT
: return CC1
| CC3
;
1080 case UNGT
: return CC2
| CC3
;
1081 case UNLE
: return CC0
| CC1
| CC3
;
1082 case UNGE
: return CC0
| CC2
| CC3
;
1083 case LTGT
: return CC1
| CC2
;
1089 switch (GET_CODE (code
))
1091 case EQ
: return CC0
;
1092 case NE
: return CC2
| CC1
| CC3
;
1093 case LT
: return CC2
;
1094 case GT
: return CC1
;
1095 case LE
: return CC0
| CC2
;
1096 case GE
: return CC0
| CC1
;
1097 case UNORDERED
: return CC3
;
1098 case ORDERED
: return CC0
| CC2
| CC1
;
1099 case UNEQ
: return CC0
| CC3
;
1100 case UNLT
: return CC2
| CC3
;
1101 case UNGT
: return CC1
| CC3
;
1102 case UNLE
: return CC0
| CC2
| CC3
;
1103 case UNGE
: return CC0
| CC1
| CC3
;
1104 case LTGT
: return CC2
| CC1
;
1115 /* Return branch condition mask to implement a compare and branch
1116 specified by CODE. Return -1 for invalid comparisons. */
1119 s390_compare_and_branch_condition_mask (rtx code
)
1121 const int CC0
= 1 << 3;
1122 const int CC1
= 1 << 2;
1123 const int CC2
= 1 << 1;
1125 switch (GET_CODE (code
))
1149 /* If INV is false, return assembler mnemonic string to implement
1150 a branch specified by CODE. If INV is true, return mnemonic
1151 for the corresponding inverted branch. */
1154 s390_branch_condition_mnemonic (rtx code
, int inv
)
1158 static const char *const mnemonic
[16] =
1160 NULL
, "o", "h", "nle",
1161 "l", "nhe", "lh", "ne",
1162 "e", "nlh", "he", "nl",
1163 "le", "nh", "no", NULL
1166 if (GET_CODE (XEXP (code
, 0)) == REG
1167 && REGNO (XEXP (code
, 0)) == CC_REGNUM
1168 && XEXP (code
, 1) == const0_rtx
)
1169 mask
= s390_branch_condition_mask (code
);
1171 mask
= s390_compare_and_branch_condition_mask (code
);
1173 gcc_assert (mask
>= 0);
1178 gcc_assert (mask
>= 1 && mask
<= 14);
1180 return mnemonic
[mask
];
1183 /* Return the part of op which has a value different from def.
1184 The size of the part is determined by mode.
1185 Use this function only if you already know that op really
1186 contains such a part. */
1188 unsigned HOST_WIDE_INT
1189 s390_extract_part (rtx op
, enum machine_mode mode
, int def
)
1191 unsigned HOST_WIDE_INT value
= 0;
1192 int max_parts
= HOST_BITS_PER_WIDE_INT
/ GET_MODE_BITSIZE (mode
);
1193 int part_bits
= GET_MODE_BITSIZE (mode
);
1194 unsigned HOST_WIDE_INT part_mask
1195 = ((unsigned HOST_WIDE_INT
)1 << part_bits
) - 1;
1198 for (i
= 0; i
< max_parts
; i
++)
1201 value
= (unsigned HOST_WIDE_INT
) INTVAL (op
);
1203 value
>>= part_bits
;
1205 if ((value
& part_mask
) != (def
& part_mask
))
1206 return value
& part_mask
;
1212 /* If OP is an integer constant of mode MODE with exactly one
1213 part of mode PART_MODE unequal to DEF, return the number of that
1214 part. Otherwise, return -1. */
1217 s390_single_part (rtx op
,
1218 enum machine_mode mode
,
1219 enum machine_mode part_mode
,
1222 unsigned HOST_WIDE_INT value
= 0;
1223 int n_parts
= GET_MODE_SIZE (mode
) / GET_MODE_SIZE (part_mode
);
1224 unsigned HOST_WIDE_INT part_mask
1225 = ((unsigned HOST_WIDE_INT
)1 << GET_MODE_BITSIZE (part_mode
)) - 1;
1228 if (GET_CODE (op
) != CONST_INT
)
1231 for (i
= 0; i
< n_parts
; i
++)
1234 value
= (unsigned HOST_WIDE_INT
) INTVAL (op
);
1236 value
>>= GET_MODE_BITSIZE (part_mode
);
1238 if ((value
& part_mask
) != (def
& part_mask
))
1246 return part
== -1 ? -1 : n_parts
- 1 - part
;
1249 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1250 bits and no other bits are set in IN. POS and LENGTH can be used
1251 to obtain the start position and the length of the bitfield.
1253 POS gives the position of the first bit of the bitfield counting
1254 from the lowest order bit starting with zero. In order to use this
1255 value for S/390 instructions this has to be converted to "bits big
1259 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in
, int size
,
1260 int *pos
, int *length
)
1265 unsigned HOST_WIDE_INT mask
= 1ULL;
1266 bool contiguous
= false;
1268 for (i
= 0; i
< size
; mask
<<= 1, i
++)
1292 /* Calculate a mask for all bits beyond the contiguous bits. */
1293 mask
= (-1LL & ~(((1ULL << (tmp_length
+ tmp_pos
- 1)) << 1) - 1));
1298 if (tmp_length
+ tmp_pos
- 1 > size
)
1302 *length
= tmp_length
;
1310 /* Check whether we can (and want to) split a double-word
1311 move in mode MODE from SRC to DST into two single-word
1312 moves, moving the subword FIRST_SUBWORD first. */
1315 s390_split_ok_p (rtx dst
, rtx src
, enum machine_mode mode
, int first_subword
)
1317 /* Floating point registers cannot be split. */
1318 if (FP_REG_P (src
) || FP_REG_P (dst
))
1321 /* We don't need to split if operands are directly accessible. */
1322 if (s_operand (src
, mode
) || s_operand (dst
, mode
))
1325 /* Non-offsettable memory references cannot be split. */
1326 if ((GET_CODE (src
) == MEM
&& !offsettable_memref_p (src
))
1327 || (GET_CODE (dst
) == MEM
&& !offsettable_memref_p (dst
)))
1330 /* Moving the first subword must not clobber a register
1331 needed to move the second subword. */
1332 if (register_operand (dst
, mode
))
1334 rtx subreg
= operand_subword (dst
, first_subword
, 0, mode
);
1335 if (reg_overlap_mentioned_p (subreg
, src
))
1342 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1343 and [MEM2, MEM2 + SIZE] do overlap and false
1347 s390_overlap_p (rtx mem1
, rtx mem2
, HOST_WIDE_INT size
)
1349 rtx addr1
, addr2
, addr_delta
;
1350 HOST_WIDE_INT delta
;
1352 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
1358 addr1
= XEXP (mem1
, 0);
1359 addr2
= XEXP (mem2
, 0);
1361 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
1363 /* This overlapping check is used by peepholes merging memory block operations.
1364 Overlapping operations would otherwise be recognized by the S/390 hardware
1365 and would fall back to a slower implementation. Allowing overlapping
1366 operations would lead to slow code but not to wrong code. Therefore we are
1367 somewhat optimistic if we cannot prove that the memory blocks are
1369 That's why we return false here although this may accept operations on
1370 overlapping memory areas. */
1371 if (!addr_delta
|| GET_CODE (addr_delta
) != CONST_INT
)
1374 delta
= INTVAL (addr_delta
);
1377 || (delta
> 0 && delta
< size
)
1378 || (delta
< 0 && -delta
< size
))
1384 /* Check whether the address of memory reference MEM2 equals exactly
1385 the address of memory reference MEM1 plus DELTA. Return true if
1386 we can prove this to be the case, false otherwise. */
1389 s390_offset_p (rtx mem1
, rtx mem2
, rtx delta
)
1391 rtx addr1
, addr2
, addr_delta
;
1393 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
1396 addr1
= XEXP (mem1
, 0);
1397 addr2
= XEXP (mem2
, 0);
1399 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
1400 if (!addr_delta
|| !rtx_equal_p (addr_delta
, delta
))
1406 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1409 s390_expand_logical_operator (enum rtx_code code
, enum machine_mode mode
,
1412 enum machine_mode wmode
= mode
;
1413 rtx dst
= operands
[0];
1414 rtx src1
= operands
[1];
1415 rtx src2
= operands
[2];
1418 /* If we cannot handle the operation directly, use a temp register. */
1419 if (!s390_logical_operator_ok_p (operands
))
1420 dst
= gen_reg_rtx (mode
);
1422 /* QImode and HImode patterns make sense only if we have a destination
1423 in memory. Otherwise perform the operation in SImode. */
1424 if ((mode
== QImode
|| mode
== HImode
) && GET_CODE (dst
) != MEM
)
1427 /* Widen operands if required. */
1430 if (GET_CODE (dst
) == SUBREG
1431 && (tem
= simplify_subreg (wmode
, dst
, mode
, 0)) != 0)
1433 else if (REG_P (dst
))
1434 dst
= gen_rtx_SUBREG (wmode
, dst
, 0);
1436 dst
= gen_reg_rtx (wmode
);
1438 if (GET_CODE (src1
) == SUBREG
1439 && (tem
= simplify_subreg (wmode
, src1
, mode
, 0)) != 0)
1441 else if (GET_MODE (src1
) != VOIDmode
)
1442 src1
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src1
), 0);
1444 if (GET_CODE (src2
) == SUBREG
1445 && (tem
= simplify_subreg (wmode
, src2
, mode
, 0)) != 0)
1447 else if (GET_MODE (src2
) != VOIDmode
)
1448 src2
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src2
), 0);
1451 /* Emit the instruction. */
1452 op
= gen_rtx_SET (VOIDmode
, dst
, gen_rtx_fmt_ee (code
, wmode
, src1
, src2
));
1453 clob
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
1454 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clob
)));
1456 /* Fix up the destination if needed. */
1457 if (dst
!= operands
[0])
1458 emit_move_insn (operands
[0], gen_lowpart (mode
, dst
));
1461 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1464 s390_logical_operator_ok_p (rtx
*operands
)
1466 /* If the destination operand is in memory, it needs to coincide
1467 with one of the source operands. After reload, it has to be
1468 the first source operand. */
1469 if (GET_CODE (operands
[0]) == MEM
)
1470 return rtx_equal_p (operands
[0], operands
[1])
1471 || (!reload_completed
&& rtx_equal_p (operands
[0], operands
[2]));
1476 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1477 operand IMMOP to switch from SS to SI type instructions. */
1480 s390_narrow_logical_operator (enum rtx_code code
, rtx
*memop
, rtx
*immop
)
1482 int def
= code
== AND
? -1 : 0;
1486 gcc_assert (GET_CODE (*memop
) == MEM
);
1487 gcc_assert (!MEM_VOLATILE_P (*memop
));
1489 mask
= s390_extract_part (*immop
, QImode
, def
);
1490 part
= s390_single_part (*immop
, GET_MODE (*memop
), QImode
, def
);
1491 gcc_assert (part
>= 0);
1493 *memop
= adjust_address (*memop
, QImode
, part
);
1494 *immop
= gen_int_mode (mask
, QImode
);
1498 /* How to allocate a 'struct machine_function'. */
1500 static struct machine_function
*
1501 s390_init_machine_status (void)
1503 return ggc_alloc_cleared_machine_function ();
1507 s390_option_override (void)
1509 /* Set up function hooks. */
1510 init_machine_status
= s390_init_machine_status
;
1512 /* Architecture mode defaults according to ABI. */
1513 if (!(target_flags_explicit
& MASK_ZARCH
))
1516 target_flags
|= MASK_ZARCH
;
1518 target_flags
&= ~MASK_ZARCH
;
1521 /* Set the march default in case it hasn't been specified on
1523 if (s390_arch
== PROCESSOR_max
)
1525 s390_arch_string
= TARGET_ZARCH
? "z900" : "g5";
1526 s390_arch
= TARGET_ZARCH
? PROCESSOR_2064_Z900
: PROCESSOR_9672_G5
;
1527 s390_arch_flags
= processor_flags_table
[(int)s390_arch
];
1530 /* Determine processor to tune for. */
1531 if (s390_tune
== PROCESSOR_max
)
1533 s390_tune
= s390_arch
;
1534 s390_tune_flags
= s390_arch_flags
;
1537 /* Sanity checks. */
1538 if (TARGET_ZARCH
&& !TARGET_CPU_ZARCH
)
1539 error ("z/Architecture mode not supported on %s", s390_arch_string
);
1540 if (TARGET_64BIT
&& !TARGET_ZARCH
)
1541 error ("64-bit ABI not supported in ESA/390 mode");
1543 if (TARGET_HARD_DFP
&& !TARGET_DFP
)
1545 if (target_flags_explicit
& MASK_HARD_DFP
)
1547 if (!TARGET_CPU_DFP
)
1548 error ("hardware decimal floating point instructions"
1549 " not available on %s", s390_arch_string
);
1551 error ("hardware decimal floating point instructions"
1552 " not available in ESA/390 mode");
1555 target_flags
&= ~MASK_HARD_DFP
;
1558 if ((target_flags_explicit
& MASK_SOFT_FLOAT
) && TARGET_SOFT_FLOAT
)
1560 if ((target_flags_explicit
& MASK_HARD_DFP
) && TARGET_HARD_DFP
)
1561 error ("-mhard-dfp can%'t be used in conjunction with -msoft-float");
1563 target_flags
&= ~MASK_HARD_DFP
;
1566 /* Set processor cost function. */
1569 case PROCESSOR_2084_Z990
:
1570 s390_cost
= &z990_cost
;
1572 case PROCESSOR_2094_Z9_109
:
1573 s390_cost
= &z9_109_cost
;
1575 case PROCESSOR_2097_Z10
:
1576 s390_cost
= &z10_cost
;
1577 case PROCESSOR_2817_Z196
:
1578 s390_cost
= &z196_cost
;
1581 s390_cost
= &z900_cost
;
1584 if (TARGET_BACKCHAIN
&& TARGET_PACKED_STACK
&& TARGET_HARD_FLOAT
)
1585 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1588 if (s390_stack_size
)
1590 if (s390_stack_guard
>= s390_stack_size
)
1591 error ("stack size must be greater than the stack guard value");
1592 else if (s390_stack_size
> 1 << 16)
1593 error ("stack size must not be greater than 64k");
1595 else if (s390_stack_guard
)
1596 error ("-mstack-guard implies use of -mstack-size");
1598 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1599 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
1600 target_flags
|= MASK_LONG_DOUBLE_128
;
1603 if (s390_tune
== PROCESSOR_2097_Z10
1604 || s390_tune
== PROCESSOR_2817_Z196
)
1606 maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS
, 100,
1607 global_options
.x_param_values
,
1608 global_options_set
.x_param_values
);
1609 maybe_set_param_value (PARAM_MAX_UNROLL_TIMES
, 32,
1610 global_options
.x_param_values
,
1611 global_options_set
.x_param_values
);
1612 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS
, 2000,
1613 global_options
.x_param_values
,
1614 global_options_set
.x_param_values
);
1615 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES
, 64,
1616 global_options
.x_param_values
,
1617 global_options_set
.x_param_values
);
1620 maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH
, 256,
1621 global_options
.x_param_values
,
1622 global_options_set
.x_param_values
);
1623 /* values for loop prefetching */
1624 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
, 256,
1625 global_options
.x_param_values
,
1626 global_options_set
.x_param_values
);
1627 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, 128,
1628 global_options
.x_param_values
,
1629 global_options_set
.x_param_values
);
1630 /* s390 has more than 2 levels and the size is much larger. Since
1631 we are always running virtualized assume that we only get a small
1632 part of the caches above l1. */
1633 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, 1500,
1634 global_options
.x_param_values
,
1635 global_options_set
.x_param_values
);
1636 maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO
, 2,
1637 global_options
.x_param_values
,
1638 global_options_set
.x_param_values
);
1639 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
, 6,
1640 global_options
.x_param_values
,
1641 global_options_set
.x_param_values
);
1643 /* This cannot reside in s390_option_optimization_table since HAVE_prefetch
1644 requires the arch flags to be evaluated already. Since prefetching
1645 is beneficial on s390, we enable it if available. */
1646 if (flag_prefetch_loop_arrays
< 0 && HAVE_prefetch
&& optimize
>= 3)
1647 flag_prefetch_loop_arrays
= 1;
1650 /* Map for smallest class containing reg regno. */
1652 const enum reg_class regclass_map
[FIRST_PSEUDO_REGISTER
] =
1653 { GENERAL_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1654 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1655 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1656 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1657 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1658 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1659 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1660 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1661 ADDR_REGS
, CC_REGS
, ADDR_REGS
, ADDR_REGS
,
1662 ACCESS_REGS
, ACCESS_REGS
1665 /* Return attribute type of insn. */
1667 static enum attr_type
1668 s390_safe_attr_type (rtx insn
)
1670 if (recog_memoized (insn
) >= 0)
1671 return get_attr_type (insn
);
1676 /* Return true if DISP is a valid short displacement. */
1679 s390_short_displacement (rtx disp
)
1681 /* No displacement is OK. */
1685 /* Without the long displacement facility we don't need to
1686 distingiush between long and short displacement. */
1687 if (!TARGET_LONG_DISPLACEMENT
)
1690 /* Integer displacement in range. */
1691 if (GET_CODE (disp
) == CONST_INT
)
1692 return INTVAL (disp
) >= 0 && INTVAL (disp
) < 4096;
1694 /* GOT offset is not OK, the GOT can be large. */
1695 if (GET_CODE (disp
) == CONST
1696 && GET_CODE (XEXP (disp
, 0)) == UNSPEC
1697 && (XINT (XEXP (disp
, 0), 1) == UNSPEC_GOT
1698 || XINT (XEXP (disp
, 0), 1) == UNSPEC_GOTNTPOFF
))
1701 /* All other symbolic constants are literal pool references,
1702 which are OK as the literal pool must be small. */
1703 if (GET_CODE (disp
) == CONST
)
1709 /* Decompose a RTL expression ADDR for a memory address into
1710 its components, returned in OUT.
1712 Returns false if ADDR is not a valid memory address, true
1713 otherwise. If OUT is NULL, don't return the components,
1714 but check for validity only.
1716 Note: Only addresses in canonical form are recognized.
1717 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1718 canonical form so that they will be recognized. */
1721 s390_decompose_address (rtx addr
, struct s390_address
*out
)
1723 HOST_WIDE_INT offset
= 0;
1724 rtx base
= NULL_RTX
;
1725 rtx indx
= NULL_RTX
;
1726 rtx disp
= NULL_RTX
;
1728 bool pointer
= false;
1729 bool base_ptr
= false;
1730 bool indx_ptr
= false;
1731 bool literal_pool
= false;
1733 /* We may need to substitute the literal pool base register into the address
1734 below. However, at this point we do not know which register is going to
1735 be used as base, so we substitute the arg pointer register. This is going
1736 to be treated as holding a pointer below -- it shouldn't be used for any
1738 rtx fake_pool_base
= gen_rtx_REG (Pmode
, ARG_POINTER_REGNUM
);
1740 /* Decompose address into base + index + displacement. */
1742 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == UNSPEC
)
1745 else if (GET_CODE (addr
) == PLUS
)
1747 rtx op0
= XEXP (addr
, 0);
1748 rtx op1
= XEXP (addr
, 1);
1749 enum rtx_code code0
= GET_CODE (op0
);
1750 enum rtx_code code1
= GET_CODE (op1
);
1752 if (code0
== REG
|| code0
== UNSPEC
)
1754 if (code1
== REG
|| code1
== UNSPEC
)
1756 indx
= op0
; /* index + base */
1762 base
= op0
; /* base + displacement */
1767 else if (code0
== PLUS
)
1769 indx
= XEXP (op0
, 0); /* index + base + disp */
1770 base
= XEXP (op0
, 1);
1781 disp
= addr
; /* displacement */
1783 /* Extract integer part of displacement. */
1787 if (GET_CODE (disp
) == CONST_INT
)
1789 offset
= INTVAL (disp
);
1792 else if (GET_CODE (disp
) == CONST
1793 && GET_CODE (XEXP (disp
, 0)) == PLUS
1794 && GET_CODE (XEXP (XEXP (disp
, 0), 1)) == CONST_INT
)
1796 offset
= INTVAL (XEXP (XEXP (disp
, 0), 1));
1797 disp
= XEXP (XEXP (disp
, 0), 0);
1801 /* Strip off CONST here to avoid special case tests later. */
1802 if (disp
&& GET_CODE (disp
) == CONST
)
1803 disp
= XEXP (disp
, 0);
1805 /* We can convert literal pool addresses to
1806 displacements by basing them off the base register. */
1807 if (disp
&& GET_CODE (disp
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (disp
))
1809 /* Either base or index must be free to hold the base register. */
1811 base
= fake_pool_base
, literal_pool
= true;
1813 indx
= fake_pool_base
, literal_pool
= true;
1817 /* Mark up the displacement. */
1818 disp
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, disp
),
1819 UNSPEC_LTREL_OFFSET
);
1822 /* Validate base register. */
1825 if (GET_CODE (base
) == UNSPEC
)
1826 switch (XINT (base
, 1))
1830 disp
= gen_rtx_UNSPEC (Pmode
,
1831 gen_rtvec (1, XVECEXP (base
, 0, 0)),
1832 UNSPEC_LTREL_OFFSET
);
1836 base
= XVECEXP (base
, 0, 1);
1839 case UNSPEC_LTREL_BASE
:
1840 if (XVECLEN (base
, 0) == 1)
1841 base
= fake_pool_base
, literal_pool
= true;
1843 base
= XVECEXP (base
, 0, 1);
1851 || (GET_MODE (base
) != SImode
1852 && GET_MODE (base
) != Pmode
))
1855 if (REGNO (base
) == STACK_POINTER_REGNUM
1856 || REGNO (base
) == FRAME_POINTER_REGNUM
1857 || ((reload_completed
|| reload_in_progress
)
1858 && frame_pointer_needed
1859 && REGNO (base
) == HARD_FRAME_POINTER_REGNUM
)
1860 || REGNO (base
) == ARG_POINTER_REGNUM
1862 && REGNO (base
) == PIC_OFFSET_TABLE_REGNUM
))
1863 pointer
= base_ptr
= true;
1865 if ((reload_completed
|| reload_in_progress
)
1866 && base
== cfun
->machine
->base_reg
)
1867 pointer
= base_ptr
= literal_pool
= true;
1870 /* Validate index register. */
1873 if (GET_CODE (indx
) == UNSPEC
)
1874 switch (XINT (indx
, 1))
1878 disp
= gen_rtx_UNSPEC (Pmode
,
1879 gen_rtvec (1, XVECEXP (indx
, 0, 0)),
1880 UNSPEC_LTREL_OFFSET
);
1884 indx
= XVECEXP (indx
, 0, 1);
1887 case UNSPEC_LTREL_BASE
:
1888 if (XVECLEN (indx
, 0) == 1)
1889 indx
= fake_pool_base
, literal_pool
= true;
1891 indx
= XVECEXP (indx
, 0, 1);
1899 || (GET_MODE (indx
) != SImode
1900 && GET_MODE (indx
) != Pmode
))
1903 if (REGNO (indx
) == STACK_POINTER_REGNUM
1904 || REGNO (indx
) == FRAME_POINTER_REGNUM
1905 || ((reload_completed
|| reload_in_progress
)
1906 && frame_pointer_needed
1907 && REGNO (indx
) == HARD_FRAME_POINTER_REGNUM
)
1908 || REGNO (indx
) == ARG_POINTER_REGNUM
1910 && REGNO (indx
) == PIC_OFFSET_TABLE_REGNUM
))
1911 pointer
= indx_ptr
= true;
1913 if ((reload_completed
|| reload_in_progress
)
1914 && indx
== cfun
->machine
->base_reg
)
1915 pointer
= indx_ptr
= literal_pool
= true;
1918 /* Prefer to use pointer as base, not index. */
1919 if (base
&& indx
&& !base_ptr
1920 && (indx_ptr
|| (!REG_POINTER (base
) && REG_POINTER (indx
))))
1927 /* Validate displacement. */
1930 /* If virtual registers are involved, the displacement will change later
1931 anyway as the virtual registers get eliminated. This could make a
1932 valid displacement invalid, but it is more likely to make an invalid
1933 displacement valid, because we sometimes access the register save area
1934 via negative offsets to one of those registers.
1935 Thus we don't check the displacement for validity here. If after
1936 elimination the displacement turns out to be invalid after all,
1937 this is fixed up by reload in any case. */
1938 if (base
!= arg_pointer_rtx
1939 && indx
!= arg_pointer_rtx
1940 && base
!= return_address_pointer_rtx
1941 && indx
!= return_address_pointer_rtx
1942 && base
!= frame_pointer_rtx
1943 && indx
!= frame_pointer_rtx
1944 && base
!= virtual_stack_vars_rtx
1945 && indx
!= virtual_stack_vars_rtx
)
1946 if (!DISP_IN_RANGE (offset
))
1951 /* All the special cases are pointers. */
1954 /* In the small-PIC case, the linker converts @GOT
1955 and @GOTNTPOFF offsets to possible displacements. */
1956 if (GET_CODE (disp
) == UNSPEC
1957 && (XINT (disp
, 1) == UNSPEC_GOT
1958 || XINT (disp
, 1) == UNSPEC_GOTNTPOFF
)
1964 /* Accept pool label offsets. */
1965 else if (GET_CODE (disp
) == UNSPEC
1966 && XINT (disp
, 1) == UNSPEC_POOL_OFFSET
)
1969 /* Accept literal pool references. */
1970 else if (GET_CODE (disp
) == UNSPEC
1971 && XINT (disp
, 1) == UNSPEC_LTREL_OFFSET
)
1973 /* In case CSE pulled a non literal pool reference out of
1974 the pool we have to reject the address. This is
1975 especially important when loading the GOT pointer on non
1976 zarch CPUs. In this case the literal pool contains an lt
1977 relative offset to the _GLOBAL_OFFSET_TABLE_ label which
1978 will most likely exceed the displacement. */
1979 if (GET_CODE (XVECEXP (disp
, 0, 0)) != SYMBOL_REF
1980 || !CONSTANT_POOL_ADDRESS_P (XVECEXP (disp
, 0, 0)))
1983 orig_disp
= gen_rtx_CONST (Pmode
, disp
);
1986 /* If we have an offset, make sure it does not
1987 exceed the size of the constant pool entry. */
1988 rtx sym
= XVECEXP (disp
, 0, 0);
1989 if (offset
>= GET_MODE_SIZE (get_pool_mode (sym
)))
1992 orig_disp
= plus_constant (orig_disp
, offset
);
2007 out
->disp
= orig_disp
;
2008 out
->pointer
= pointer
;
2009 out
->literal_pool
= literal_pool
;
2015 /* Decompose a RTL expression OP for a shift count into its components,
2016 and return the base register in BASE and the offset in OFFSET.
2018 Return true if OP is a valid shift count, false if not. */
2021 s390_decompose_shift_count (rtx op
, rtx
*base
, HOST_WIDE_INT
*offset
)
2023 HOST_WIDE_INT off
= 0;
2025 /* We can have an integer constant, an address register,
2026 or a sum of the two. */
2027 if (GET_CODE (op
) == CONST_INT
)
2032 if (op
&& GET_CODE (op
) == PLUS
&& GET_CODE (XEXP (op
, 1)) == CONST_INT
)
2034 off
= INTVAL (XEXP (op
, 1));
2037 while (op
&& GET_CODE (op
) == SUBREG
)
2038 op
= SUBREG_REG (op
);
2040 if (op
&& GET_CODE (op
) != REG
)
2052 /* Return true if CODE is a valid address without index. */
2055 s390_legitimate_address_without_index_p (rtx op
)
2057 struct s390_address addr
;
2059 if (!s390_decompose_address (XEXP (op
, 0), &addr
))
2068 /* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
2069 and return these parts in SYMREF and ADDEND. You can pass NULL in
2070 SYMREF and/or ADDEND if you are not interested in these values.
2071 Literal pool references are *not* considered symbol references. */
2074 s390_symref_operand_p (rtx addr
, rtx
*symref
, HOST_WIDE_INT
*addend
)
2076 HOST_WIDE_INT tmpaddend
= 0;
2078 if (GET_CODE (addr
) == CONST
)
2079 addr
= XEXP (addr
, 0);
2081 if (GET_CODE (addr
) == PLUS
)
2083 if (GET_CODE (XEXP (addr
, 0)) == SYMBOL_REF
2084 && !CONSTANT_POOL_ADDRESS_P (XEXP (addr
, 0))
2085 && CONST_INT_P (XEXP (addr
, 1)))
2087 tmpaddend
= INTVAL (XEXP (addr
, 1));
2088 addr
= XEXP (addr
, 0);
2094 if (GET_CODE (addr
) != SYMBOL_REF
|| CONSTANT_POOL_ADDRESS_P (addr
))
2100 *addend
= tmpaddend
;
2106 /* Return true if the address in OP is valid for constraint letter C
2107 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2108 pool MEMs should be accepted. Only the Q, R, S, T constraint
2109 letters are allowed for C. */
2112 s390_check_qrst_address (char c
, rtx op
, bool lit_pool_ok
)
2114 struct s390_address addr
;
2115 bool decomposed
= false;
2117 /* This check makes sure that no symbolic address (except literal
2118 pool references) are accepted by the R or T constraints. */
2119 if (s390_symref_operand_p (op
, NULL
, NULL
))
2122 /* Ensure literal pool references are only accepted if LIT_POOL_OK. */
2125 if (!s390_decompose_address (op
, &addr
))
2127 if (addr
.literal_pool
)
2134 case 'Q': /* no index short displacement */
2135 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
2139 if (!s390_short_displacement (addr
.disp
))
2143 case 'R': /* with index short displacement */
2144 if (TARGET_LONG_DISPLACEMENT
)
2146 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
2148 if (!s390_short_displacement (addr
.disp
))
2151 /* Any invalid address here will be fixed up by reload,
2152 so accept it for the most generic constraint. */
2155 case 'S': /* no index long displacement */
2156 if (!TARGET_LONG_DISPLACEMENT
)
2158 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
2162 if (s390_short_displacement (addr
.disp
))
2166 case 'T': /* with index long displacement */
2167 if (!TARGET_LONG_DISPLACEMENT
)
2169 /* Any invalid address here will be fixed up by reload,
2170 so accept it for the most generic constraint. */
2171 if ((decomposed
|| s390_decompose_address (op
, &addr
))
2172 && s390_short_displacement (addr
.disp
))
2182 /* Evaluates constraint strings described by the regular expression
2183 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2184 the constraint given in STR, or 0 else. */
2187 s390_mem_constraint (const char *str
, rtx op
)
2194 /* Check for offsettable variants of memory constraints. */
2195 if (!MEM_P (op
) || MEM_VOLATILE_P (op
))
2197 if ((reload_completed
|| reload_in_progress
)
2198 ? !offsettable_memref_p (op
) : !offsettable_nonstrict_memref_p (op
))
2200 return s390_check_qrst_address (str
[1], XEXP (op
, 0), true);
2202 /* Check for non-literal-pool variants of memory constraints. */
2205 return s390_check_qrst_address (str
[1], XEXP (op
, 0), false);
2210 if (GET_CODE (op
) != MEM
)
2212 return s390_check_qrst_address (c
, XEXP (op
, 0), true);
2214 return (s390_check_qrst_address ('Q', op
, true)
2215 || s390_check_qrst_address ('R', op
, true));
2217 return (s390_check_qrst_address ('S', op
, true)
2218 || s390_check_qrst_address ('T', op
, true));
2220 /* Simply check for the basic form of a shift count. Reload will
2221 take care of making sure we have a proper base register. */
2222 if (!s390_decompose_shift_count (op
, NULL
, NULL
))
2226 return s390_check_qrst_address (str
[1], op
, true);
2234 /* Evaluates constraint strings starting with letter O. Input
2235 parameter C is the second letter following the "O" in the constraint
2236 string. Returns 1 if VALUE meets the respective constraint and 0
2240 s390_O_constraint_str (const char c
, HOST_WIDE_INT value
)
2248 return trunc_int_for_mode (value
, SImode
) == value
;
2252 || s390_single_part (GEN_INT (value
), DImode
, SImode
, 0) == 1;
2255 return s390_single_part (GEN_INT (value
- 1), DImode
, SImode
, -1) == 1;
2263 /* Evaluates constraint strings starting with letter N. Parameter STR
2264 contains the letters following letter "N" in the constraint string.
2265 Returns true if VALUE matches the constraint. */
2268 s390_N_constraint_str (const char *str
, HOST_WIDE_INT value
)
2270 enum machine_mode mode
, part_mode
;
2272 int part
, part_goal
;
2278 part_goal
= str
[0] - '0';
2322 if (GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (part_mode
))
2325 part
= s390_single_part (GEN_INT (value
), mode
, part_mode
, def
);
2328 if (part_goal
!= -1 && part_goal
!= part
)
2335 /* Returns true if the input parameter VALUE is a float zero. */
2338 s390_float_const_zero_p (rtx value
)
2340 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
2341 && value
== CONST0_RTX (GET_MODE (value
)));
2344 /* Implement TARGET_REGISTER_MOVE_COST. */
2347 s390_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
2348 reg_class_t from
, reg_class_t to
)
2350 /* On s390, copy between fprs and gprs is expensive. */
2351 if ((reg_classes_intersect_p (from
, GENERAL_REGS
)
2352 && reg_classes_intersect_p (to
, FP_REGS
))
2353 || (reg_classes_intersect_p (from
, FP_REGS
)
2354 && reg_classes_intersect_p (to
, GENERAL_REGS
)))
2360 /* Implement TARGET_MEMORY_MOVE_COST. */
2363 s390_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
2364 reg_class_t rclass ATTRIBUTE_UNUSED
,
2365 bool in ATTRIBUTE_UNUSED
)
2370 /* Compute a (partial) cost for rtx X. Return true if the complete
2371 cost has been computed, and false if subexpressions should be
2372 scanned. In either case, *TOTAL contains the cost result.
2373 CODE contains GET_CODE (x), OUTER_CODE contains the code
2374 of the superexpression of x. */
2377 s390_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
2378 int *total
, bool speed ATTRIBUTE_UNUSED
)
2401 *total
= COSTS_N_INSNS (1);
2406 *total
= COSTS_N_INSNS (1);
2410 switch (GET_MODE (x
))
2414 rtx left
= XEXP (x
, 0);
2415 rtx right
= XEXP (x
, 1);
2416 if (GET_CODE (right
) == CONST_INT
2417 && CONST_OK_FOR_K (INTVAL (right
)))
2418 *total
= s390_cost
->mhi
;
2419 else if (GET_CODE (left
) == SIGN_EXTEND
)
2420 *total
= s390_cost
->mh
;
2422 *total
= s390_cost
->ms
; /* msr, ms, msy */
2427 rtx left
= XEXP (x
, 0);
2428 rtx right
= XEXP (x
, 1);
2431 if (GET_CODE (right
) == CONST_INT
2432 && CONST_OK_FOR_K (INTVAL (right
)))
2433 *total
= s390_cost
->mghi
;
2434 else if (GET_CODE (left
) == SIGN_EXTEND
)
2435 *total
= s390_cost
->msgf
;
2437 *total
= s390_cost
->msg
; /* msgr, msg */
2439 else /* TARGET_31BIT */
2441 if (GET_CODE (left
) == SIGN_EXTEND
2442 && GET_CODE (right
) == SIGN_EXTEND
)
2443 /* mulsidi case: mr, m */
2444 *total
= s390_cost
->m
;
2445 else if (GET_CODE (left
) == ZERO_EXTEND
2446 && GET_CODE (right
) == ZERO_EXTEND
2447 && TARGET_CPU_ZARCH
)
2448 /* umulsidi case: ml, mlr */
2449 *total
= s390_cost
->ml
;
2451 /* Complex calculation is required. */
2452 *total
= COSTS_N_INSNS (40);
2458 *total
= s390_cost
->mult_df
;
2461 *total
= s390_cost
->mxbr
;
2469 switch (GET_MODE (x
))
2472 *total
= s390_cost
->madbr
;
2475 *total
= s390_cost
->maebr
;
2480 /* Negate in the third argument is free: FMSUB. */
2481 if (GET_CODE (XEXP (x
, 2)) == NEG
)
2483 *total
+= (rtx_cost (XEXP (x
, 0), FMA
, 0, speed
)
2484 + rtx_cost (XEXP (x
, 1), FMA
, 1, speed
)
2485 + rtx_cost (XEXP (XEXP (x
, 2), 0), FMA
, 2, speed
));
2492 if (GET_MODE (x
) == TImode
) /* 128 bit division */
2493 *total
= s390_cost
->dlgr
;
2494 else if (GET_MODE (x
) == DImode
)
2496 rtx right
= XEXP (x
, 1);
2497 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
2498 *total
= s390_cost
->dlr
;
2499 else /* 64 by 64 bit division */
2500 *total
= s390_cost
->dlgr
;
2502 else if (GET_MODE (x
) == SImode
) /* 32 bit division */
2503 *total
= s390_cost
->dlr
;
2508 if (GET_MODE (x
) == DImode
)
2510 rtx right
= XEXP (x
, 1);
2511 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
2513 *total
= s390_cost
->dsgfr
;
2515 *total
= s390_cost
->dr
;
2516 else /* 64 by 64 bit division */
2517 *total
= s390_cost
->dsgr
;
2519 else if (GET_MODE (x
) == SImode
) /* 32 bit division */
2520 *total
= s390_cost
->dlr
;
2521 else if (GET_MODE (x
) == SFmode
)
2523 *total
= s390_cost
->debr
;
2525 else if (GET_MODE (x
) == DFmode
)
2527 *total
= s390_cost
->ddbr
;
2529 else if (GET_MODE (x
) == TFmode
)
2531 *total
= s390_cost
->dxbr
;
2536 if (GET_MODE (x
) == SFmode
)
2537 *total
= s390_cost
->sqebr
;
2538 else if (GET_MODE (x
) == DFmode
)
2539 *total
= s390_cost
->sqdbr
;
2541 *total
= s390_cost
->sqxbr
;
2546 if (outer_code
== MULT
|| outer_code
== DIV
|| outer_code
== MOD
2547 || outer_code
== PLUS
|| outer_code
== MINUS
2548 || outer_code
== COMPARE
)
2553 *total
= COSTS_N_INSNS (1);
2554 if (GET_CODE (XEXP (x
, 0)) == AND
2555 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2556 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
2558 rtx op0
= XEXP (XEXP (x
, 0), 0);
2559 rtx op1
= XEXP (XEXP (x
, 0), 1);
2560 rtx op2
= XEXP (x
, 1);
2562 if (memory_operand (op0
, GET_MODE (op0
))
2563 && s390_tm_ccmode (op1
, op2
, 0) != VOIDmode
)
2565 if (register_operand (op0
, GET_MODE (op0
))
2566 && s390_tm_ccmode (op1
, op2
, 1) != VOIDmode
)
2576 /* Return the cost of an address rtx ADDR. */
2579 s390_address_cost (rtx addr
, bool speed ATTRIBUTE_UNUSED
)
2581 struct s390_address ad
;
2582 if (!s390_decompose_address (addr
, &ad
))
2585 return ad
.indx
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2588 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2589 otherwise return 0. */
2592 tls_symbolic_operand (rtx op
)
2594 if (GET_CODE (op
) != SYMBOL_REF
)
2596 return SYMBOL_REF_TLS_MODEL (op
);
2599 /* Split DImode access register reference REG (on 64-bit) into its constituent
2600 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2601 gen_highpart cannot be used as they assume all registers are word-sized,
2602 while our access registers have only half that size. */
2605 s390_split_access_reg (rtx reg
, rtx
*lo
, rtx
*hi
)
2607 gcc_assert (TARGET_64BIT
);
2608 gcc_assert (ACCESS_REG_P (reg
));
2609 gcc_assert (GET_MODE (reg
) == DImode
);
2610 gcc_assert (!(REGNO (reg
) & 1));
2612 *lo
= gen_rtx_REG (SImode
, REGNO (reg
) + 1);
2613 *hi
= gen_rtx_REG (SImode
, REGNO (reg
));
2616 /* Return true if OP contains a symbol reference */
2619 symbolic_reference_mentioned_p (rtx op
)
2624 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
2627 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
2628 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
2634 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
2635 if (symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
2639 else if (fmt
[i
] == 'e' && symbolic_reference_mentioned_p (XEXP (op
, i
)))
2646 /* Return true if OP contains a reference to a thread-local symbol. */
2649 tls_symbolic_reference_mentioned_p (rtx op
)
2654 if (GET_CODE (op
) == SYMBOL_REF
)
2655 return tls_symbolic_operand (op
);
2657 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
2658 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
2664 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
2665 if (tls_symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
2669 else if (fmt
[i
] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op
, i
)))
2677 /* Return true if OP is a legitimate general operand when
2678 generating PIC code. It is given that flag_pic is on
2679 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2682 legitimate_pic_operand_p (rtx op
)
2684 /* Accept all non-symbolic constants. */
2685 if (!SYMBOLIC_CONST (op
))
2688 /* Reject everything else; must be handled
2689 via emit_symbolic_move. */
2693 /* Returns true if the constant value OP is a legitimate general operand.
2694 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2697 s390_legitimate_constant_p (enum machine_mode mode
, rtx op
)
2699 /* Accept all non-symbolic constants. */
2700 if (!SYMBOLIC_CONST (op
))
2703 /* Accept immediate LARL operands. */
2704 if (TARGET_CPU_ZARCH
&& larl_operand (op
, mode
))
2707 /* Thread-local symbols are never legal constants. This is
2708 so that emit_call knows that computing such addresses
2709 might require a function call. */
2710 if (TLS_SYMBOLIC_CONST (op
))
2713 /* In the PIC case, symbolic constants must *not* be
2714 forced into the literal pool. We accept them here,
2715 so that they will be handled by emit_symbolic_move. */
2719 /* All remaining non-PIC symbolic constants are
2720 forced into the literal pool. */
2724 /* Determine if it's legal to put X into the constant pool. This
2725 is not possible if X contains the address of a symbol that is
2726 not constant (TLS) or not known at final link time (PIC). */
2729 s390_cannot_force_const_mem (enum machine_mode mode
, rtx x
)
2731 switch (GET_CODE (x
))
2735 /* Accept all non-symbolic constants. */
2739 /* Labels are OK iff we are non-PIC. */
2740 return flag_pic
!= 0;
2743 /* 'Naked' TLS symbol references are never OK,
2744 non-TLS symbols are OK iff we are non-PIC. */
2745 if (tls_symbolic_operand (x
))
2748 return flag_pic
!= 0;
2751 return s390_cannot_force_const_mem (mode
, XEXP (x
, 0));
2754 return s390_cannot_force_const_mem (mode
, XEXP (x
, 0))
2755 || s390_cannot_force_const_mem (mode
, XEXP (x
, 1));
2758 switch (XINT (x
, 1))
2760 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2761 case UNSPEC_LTREL_OFFSET
:
2769 case UNSPEC_GOTNTPOFF
:
2770 case UNSPEC_INDNTPOFF
:
2773 /* If the literal pool shares the code section, be put
2774 execute template placeholders into the pool as well. */
2776 return TARGET_CPU_ZARCH
;
2788 /* Returns true if the constant value OP is a legitimate general
2789 operand during and after reload. The difference to
2790 legitimate_constant_p is that this function will not accept
2791 a constant that would need to be forced to the literal pool
2792 before it can be used as operand.
2793 This function accepts all constants which can be loaded directly
2797 legitimate_reload_constant_p (rtx op
)
2799 /* Accept la(y) operands. */
2800 if (GET_CODE (op
) == CONST_INT
2801 && DISP_IN_RANGE (INTVAL (op
)))
2804 /* Accept l(g)hi/l(g)fi operands. */
2805 if (GET_CODE (op
) == CONST_INT
2806 && (CONST_OK_FOR_K (INTVAL (op
)) || CONST_OK_FOR_Os (INTVAL (op
))))
2809 /* Accept lliXX operands. */
2811 && GET_CODE (op
) == CONST_INT
2812 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
2813 && s390_single_part (op
, word_mode
, HImode
, 0) >= 0)
2817 && GET_CODE (op
) == CONST_INT
2818 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
2819 && s390_single_part (op
, word_mode
, SImode
, 0) >= 0)
2822 /* Accept larl operands. */
2823 if (TARGET_CPU_ZARCH
2824 && larl_operand (op
, VOIDmode
))
2827 /* Accept floating-point zero operands that fit into a single GPR. */
2828 if (GET_CODE (op
) == CONST_DOUBLE
2829 && s390_float_const_zero_p (op
)
2830 && GET_MODE_SIZE (GET_MODE (op
)) <= UNITS_PER_WORD
)
2833 /* Accept double-word operands that can be split. */
2834 if (GET_CODE (op
) == CONST_INT
2835 && trunc_int_for_mode (INTVAL (op
), word_mode
) != INTVAL (op
))
2837 enum machine_mode dword_mode
= word_mode
== SImode
? DImode
: TImode
;
2838 rtx hi
= operand_subword (op
, 0, 0, dword_mode
);
2839 rtx lo
= operand_subword (op
, 1, 0, dword_mode
);
2840 return legitimate_reload_constant_p (hi
)
2841 && legitimate_reload_constant_p (lo
);
2844 /* Everything else cannot be handled without reload. */
2848 /* Returns true if the constant value OP is a legitimate fp operand
2849 during and after reload.
2850 This function accepts all constants which can be loaded directly
2854 legitimate_reload_fp_constant_p (rtx op
)
2856 /* Accept floating-point zero operands if the load zero instruction
2859 && GET_CODE (op
) == CONST_DOUBLE
2860 && s390_float_const_zero_p (op
))
2866 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2867 return the class of reg to actually use. */
2870 s390_preferred_reload_class (rtx op
, reg_class_t rclass
)
2872 switch (GET_CODE (op
))
2874 /* Constants we cannot reload into general registers
2875 must be forced into the literal pool. */
2878 if (reg_class_subset_p (GENERAL_REGS
, rclass
)
2879 && legitimate_reload_constant_p (op
))
2880 return GENERAL_REGS
;
2881 else if (reg_class_subset_p (ADDR_REGS
, rclass
)
2882 && legitimate_reload_constant_p (op
))
2884 else if (reg_class_subset_p (FP_REGS
, rclass
)
2885 && legitimate_reload_fp_constant_p (op
))
2889 /* If a symbolic constant or a PLUS is reloaded,
2890 it is most likely being used as an address, so
2891 prefer ADDR_REGS. If 'class' is not a superset
2892 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2896 if (!legitimate_reload_constant_p (op
))
2900 /* load address will be used. */
2901 if (reg_class_subset_p (ADDR_REGS
, rclass
))
2913 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2914 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2918 s390_check_symref_alignment (rtx addr
, HOST_WIDE_INT alignment
)
2920 HOST_WIDE_INT addend
;
2923 if (!s390_symref_operand_p (addr
, &symref
, &addend
))
2926 return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref
)
2927 && !(addend
& (alignment
- 1)));
2930 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
2931 operand SCRATCH is used to reload the even part of the address and
2935 s390_reload_larl_operand (rtx reg
, rtx addr
, rtx scratch
)
2937 HOST_WIDE_INT addend
;
2940 if (!s390_symref_operand_p (addr
, &symref
, &addend
))
2944 /* Easy case. The addend is even so larl will do fine. */
2945 emit_move_insn (reg
, addr
);
2948 /* We can leave the scratch register untouched if the target
2949 register is a valid base register. */
2950 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
2951 && REGNO_REG_CLASS (REGNO (reg
)) == ADDR_REGS
)
2954 gcc_assert (REGNO (scratch
) < FIRST_PSEUDO_REGISTER
);
2955 gcc_assert (REGNO_REG_CLASS (REGNO (scratch
)) == ADDR_REGS
);
2958 emit_move_insn (scratch
,
2959 gen_rtx_CONST (Pmode
,
2960 gen_rtx_PLUS (Pmode
, symref
,
2961 GEN_INT (addend
- 1))));
2963 emit_move_insn (scratch
, symref
);
2965 /* Increment the address using la in order to avoid clobbering cc. */
2966 emit_move_insn (reg
, gen_rtx_PLUS (Pmode
, scratch
, const1_rtx
));
2970 /* Generate what is necessary to move between REG and MEM using
2971 SCRATCH. The direction is given by TOMEM. */
2974 s390_reload_symref_address (rtx reg
, rtx mem
, rtx scratch
, bool tomem
)
2976 /* Reload might have pulled a constant out of the literal pool.
2977 Force it back in. */
2978 if (CONST_INT_P (mem
) || GET_CODE (mem
) == CONST_DOUBLE
2979 || GET_CODE (mem
) == CONST
)
2980 mem
= force_const_mem (GET_MODE (reg
), mem
);
2982 gcc_assert (MEM_P (mem
));
2984 /* For a load from memory we can leave the scratch register
2985 untouched if the target register is a valid base register. */
2987 && REGNO (reg
) < FIRST_PSEUDO_REGISTER
2988 && REGNO_REG_CLASS (REGNO (reg
)) == ADDR_REGS
2989 && GET_MODE (reg
) == GET_MODE (scratch
))
2992 /* Load address into scratch register. Since we can't have a
2993 secondary reload for a secondary reload we have to cover the case
2994 where larl would need a secondary reload here as well. */
2995 s390_reload_larl_operand (scratch
, XEXP (mem
, 0), scratch
);
2997 /* Now we can use a standard load/store to do the move. */
2999 emit_move_insn (replace_equiv_address (mem
, scratch
), reg
);
3001 emit_move_insn (reg
, replace_equiv_address (mem
, scratch
));
3004 /* Inform reload about cases where moving X with a mode MODE to a register in
3005 RCLASS requires an extra scratch or immediate register. Return the class
3006 needed for the immediate register. */
3009 s390_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
3010 enum machine_mode mode
, secondary_reload_info
*sri
)
3012 enum reg_class rclass
= (enum reg_class
) rclass_i
;
3014 /* Intermediate register needed. */
3015 if (reg_classes_intersect_p (CC_REGS
, rclass
))
3016 return GENERAL_REGS
;
3020 HOST_WIDE_INT offset
;
3023 /* On z10 several optimizer steps may generate larl operands with
3026 && s390_symref_operand_p (x
, &symref
, &offset
)
3028 && !SYMBOL_REF_ALIGN1_P (symref
)
3029 && (offset
& 1) == 1)
3030 sri
->icode
= ((mode
== DImode
) ? CODE_FOR_reloaddi_larl_odd_addend_z10
3031 : CODE_FOR_reloadsi_larl_odd_addend_z10
);
3033 /* On z10 we need a scratch register when moving QI, TI or floating
3034 point mode values from or to a memory location with a SYMBOL_REF
3035 or if the symref addend of a SI or DI move is not aligned to the
3036 width of the access. */
3038 && s390_symref_operand_p (XEXP (x
, 0), NULL
, NULL
)
3039 && (mode
== QImode
|| mode
== TImode
|| FLOAT_MODE_P (mode
)
3040 || (!TARGET_ZARCH
&& mode
== DImode
)
3041 || ((mode
== HImode
|| mode
== SImode
|| mode
== DImode
)
3042 && (!s390_check_symref_alignment (XEXP (x
, 0),
3043 GET_MODE_SIZE (mode
))))))
3045 #define __SECONDARY_RELOAD_CASE(M,m) \
3048 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
3049 CODE_FOR_reload##m##di_tomem_z10; \
3051 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
3052 CODE_FOR_reload##m##si_tomem_z10; \
3055 switch (GET_MODE (x
))
3057 __SECONDARY_RELOAD_CASE (QI
, qi
);
3058 __SECONDARY_RELOAD_CASE (HI
, hi
);
3059 __SECONDARY_RELOAD_CASE (SI
, si
);
3060 __SECONDARY_RELOAD_CASE (DI
, di
);
3061 __SECONDARY_RELOAD_CASE (TI
, ti
);
3062 __SECONDARY_RELOAD_CASE (SF
, sf
);
3063 __SECONDARY_RELOAD_CASE (DF
, df
);
3064 __SECONDARY_RELOAD_CASE (TF
, tf
);
3065 __SECONDARY_RELOAD_CASE (SD
, sd
);
3066 __SECONDARY_RELOAD_CASE (DD
, dd
);
3067 __SECONDARY_RELOAD_CASE (TD
, td
);
3072 #undef __SECONDARY_RELOAD_CASE
3076 /* We need a scratch register when loading a PLUS expression which
3077 is not a legitimate operand of the LOAD ADDRESS instruction. */
3078 if (in_p
&& s390_plus_operand (x
, mode
))
3079 sri
->icode
= (TARGET_64BIT
?
3080 CODE_FOR_reloaddi_plus
: CODE_FOR_reloadsi_plus
);
3082 /* Performing a multiword move from or to memory we have to make sure the
3083 second chunk in memory is addressable without causing a displacement
3084 overflow. If that would be the case we calculate the address in
3085 a scratch register. */
3087 && GET_CODE (XEXP (x
, 0)) == PLUS
3088 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3089 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x
, 0), 1))
3090 + GET_MODE_SIZE (mode
) - 1))
3092 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3093 in a s_operand address since we may fallback to lm/stm. So we only
3094 have to care about overflows in the b+i+d case. */
3095 if ((reg_classes_intersect_p (GENERAL_REGS
, rclass
)
3096 && s390_class_max_nregs (GENERAL_REGS
, mode
) > 1
3097 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
3098 /* For FP_REGS no lm/stm is available so this check is triggered
3099 for displacement overflows in b+i+d and b+d like addresses. */
3100 || (reg_classes_intersect_p (FP_REGS
, rclass
)
3101 && s390_class_max_nregs (FP_REGS
, mode
) > 1))
3104 sri
->icode
= (TARGET_64BIT
?
3105 CODE_FOR_reloaddi_nonoffmem_in
:
3106 CODE_FOR_reloadsi_nonoffmem_in
);
3108 sri
->icode
= (TARGET_64BIT
?
3109 CODE_FOR_reloaddi_nonoffmem_out
:
3110 CODE_FOR_reloadsi_nonoffmem_out
);
3114 /* A scratch address register is needed when a symbolic constant is
3115 copied to r0 compiling with -fPIC. In other cases the target
3116 register might be used as temporary (see legitimize_pic_address). */
3117 if (in_p
&& SYMBOLIC_CONST (x
) && flag_pic
== 2 && rclass
!= ADDR_REGS
)
3118 sri
->icode
= (TARGET_64BIT
?
3119 CODE_FOR_reloaddi_PIC_addr
:
3120 CODE_FOR_reloadsi_PIC_addr
);
3122 /* Either scratch or no register needed. */
3126 /* Generate code to load SRC, which is PLUS that is not a
3127 legitimate operand for the LA instruction, into TARGET.
3128 SCRATCH may be used as scratch register. */
3131 s390_expand_plus_operand (rtx target
, rtx src
,
3135 struct s390_address ad
;
3137 /* src must be a PLUS; get its two operands. */
3138 gcc_assert (GET_CODE (src
) == PLUS
);
3139 gcc_assert (GET_MODE (src
) == Pmode
);
3141 /* Check if any of the two operands is already scheduled
3142 for replacement by reload. This can happen e.g. when
3143 float registers occur in an address. */
3144 sum1
= find_replacement (&XEXP (src
, 0));
3145 sum2
= find_replacement (&XEXP (src
, 1));
3146 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
3148 /* If the address is already strictly valid, there's nothing to do. */
3149 if (!s390_decompose_address (src
, &ad
)
3150 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
3151 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
3153 /* Otherwise, one of the operands cannot be an address register;
3154 we reload its value into the scratch register. */
3155 if (true_regnum (sum1
) < 1 || true_regnum (sum1
) > 15)
3157 emit_move_insn (scratch
, sum1
);
3160 if (true_regnum (sum2
) < 1 || true_regnum (sum2
) > 15)
3162 emit_move_insn (scratch
, sum2
);
3166 /* According to the way these invalid addresses are generated
3167 in reload.c, it should never happen (at least on s390) that
3168 *neither* of the PLUS components, after find_replacements
3169 was applied, is an address register. */
3170 if (sum1
== scratch
&& sum2
== scratch
)
3176 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
3179 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3180 is only ever performed on addresses, so we can mark the
3181 sum as legitimate for LA in any case. */
3182 s390_load_address (target
, src
);
3186 /* Return true if ADDR is a valid memory address.
3187 STRICT specifies whether strict register checking applies. */
3190 s390_legitimate_address_p (enum machine_mode mode
, rtx addr
, bool strict
)
3192 struct s390_address ad
;
3195 && larl_operand (addr
, VOIDmode
)
3196 && (mode
== VOIDmode
3197 || s390_check_symref_alignment (addr
, GET_MODE_SIZE (mode
))))
3200 if (!s390_decompose_address (addr
, &ad
))
3205 if (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
3208 if (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
)))
3214 && !(REGNO (ad
.base
) >= FIRST_PSEUDO_REGISTER
3215 || REGNO_REG_CLASS (REGNO (ad
.base
)) == ADDR_REGS
))
3219 && !(REGNO (ad
.indx
) >= FIRST_PSEUDO_REGISTER
3220 || REGNO_REG_CLASS (REGNO (ad
.indx
)) == ADDR_REGS
))
3226 /* Return true if OP is a valid operand for the LA instruction.
3227 In 31-bit, we need to prove that the result is used as an
3228 address, as LA performs only a 31-bit addition. */
3231 legitimate_la_operand_p (rtx op
)
3233 struct s390_address addr
;
3234 if (!s390_decompose_address (op
, &addr
))
3237 return (TARGET_64BIT
|| addr
.pointer
);
3240 /* Return true if it is valid *and* preferable to use LA to
3241 compute the sum of OP1 and OP2. */
3244 preferred_la_operand_p (rtx op1
, rtx op2
)
3246 struct s390_address addr
;
3248 if (op2
!= const0_rtx
)
3249 op1
= gen_rtx_PLUS (Pmode
, op1
, op2
);
3251 if (!s390_decompose_address (op1
, &addr
))
3253 if (addr
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (addr
.base
)))
3255 if (addr
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (addr
.indx
)))
3258 /* Avoid LA instructions with index register on z196; it is
3259 preferable to use regular add instructions when possible. */
3260 if (addr
.indx
&& s390_tune
== PROCESSOR_2817_Z196
)
3263 if (!TARGET_64BIT
&& !addr
.pointer
)
3269 if ((addr
.base
&& REG_P (addr
.base
) && REG_POINTER (addr
.base
))
3270 || (addr
.indx
&& REG_P (addr
.indx
) && REG_POINTER (addr
.indx
)))
3276 /* Emit a forced load-address operation to load SRC into DST.
3277 This will use the LOAD ADDRESS instruction even in situations
3278 where legitimate_la_operand_p (SRC) returns false. */
3281 s390_load_address (rtx dst
, rtx src
)
3284 emit_move_insn (dst
, src
);
3286 emit_insn (gen_force_la_31 (dst
, src
));
3289 /* Return a legitimate reference for ORIG (an address) using the
3290 register REG. If REG is 0, a new pseudo is generated.
3292 There are two types of references that must be handled:
3294 1. Global data references must load the address from the GOT, via
3295 the PIC reg. An insn is emitted to do this load, and the reg is
3298 2. Static data references, constant pool addresses, and code labels
3299 compute the address as an offset from the GOT, whose base is in
3300 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3301 differentiate them from global data objects. The returned
3302 address is the PIC reg + an unspec constant.
3304 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3305 reg also appears in the address. */
3308 legitimize_pic_address (rtx orig
, rtx reg
)
3314 gcc_assert (!TLS_SYMBOLIC_CONST (addr
));
3316 if (GET_CODE (addr
) == LABEL_REF
3317 || (GET_CODE (addr
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (addr
)))
3319 /* This is a local symbol. */
3320 if (TARGET_CPU_ZARCH
&& larl_operand (addr
, VOIDmode
))
3322 /* Access local symbols PC-relative via LARL.
3323 This is the same as in the non-PIC case, so it is
3324 handled automatically ... */
3328 /* Access local symbols relative to the GOT. */
3330 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3332 if (reload_in_progress
|| reload_completed
)
3333 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3335 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTOFF
);
3336 addr
= gen_rtx_CONST (Pmode
, addr
);
3337 addr
= force_const_mem (Pmode
, addr
);
3338 emit_move_insn (temp
, addr
);
3340 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3343 s390_load_address (reg
, new_rtx
);
3348 else if (GET_CODE (addr
) == SYMBOL_REF
)
3351 reg
= gen_reg_rtx (Pmode
);
3355 /* Assume GOT offset < 4k. This is handled the same way
3356 in both 31- and 64-bit code (@GOT). */
3358 if (reload_in_progress
|| reload_completed
)
3359 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3361 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
3362 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3363 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new_rtx
);
3364 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3365 emit_move_insn (reg
, new_rtx
);
3368 else if (TARGET_CPU_ZARCH
)
3370 /* If the GOT offset might be >= 4k, we determine the position
3371 of the GOT entry via a PC-relative LARL (@GOTENT). */
3373 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3375 gcc_assert (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
3376 || REGNO_REG_CLASS (REGNO (temp
)) == ADDR_REGS
);
3378 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTENT
);
3379 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3380 emit_move_insn (temp
, new_rtx
);
3382 new_rtx
= gen_const_mem (Pmode
, temp
);
3383 emit_move_insn (reg
, new_rtx
);
3388 /* If the GOT offset might be >= 4k, we have to load it
3389 from the literal pool (@GOT). */
3391 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3393 gcc_assert (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
3394 || REGNO_REG_CLASS (REGNO (temp
)) == ADDR_REGS
);
3396 if (reload_in_progress
|| reload_completed
)
3397 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3399 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
3400 addr
= gen_rtx_CONST (Pmode
, addr
);
3401 addr
= force_const_mem (Pmode
, addr
);
3402 emit_move_insn (temp
, addr
);
3404 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3405 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3406 emit_move_insn (reg
, new_rtx
);
3412 if (GET_CODE (addr
) == CONST
)
3414 addr
= XEXP (addr
, 0);
3415 if (GET_CODE (addr
) == UNSPEC
)
3417 gcc_assert (XVECLEN (addr
, 0) == 1);
3418 switch (XINT (addr
, 1))
3420 /* If someone moved a GOT-relative UNSPEC
3421 out of the literal pool, force them back in. */
3424 new_rtx
= force_const_mem (Pmode
, orig
);
3427 /* @GOT is OK as is if small. */
3430 new_rtx
= force_const_mem (Pmode
, orig
);
3433 /* @GOTENT is OK as is. */
3437 /* @PLT is OK as is on 64-bit, must be converted to
3438 GOT-relative @PLTOFF on 31-bit. */
3440 if (!TARGET_CPU_ZARCH
)
3442 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3444 if (reload_in_progress
|| reload_completed
)
3445 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3447 addr
= XVECEXP (addr
, 0, 0);
3448 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
),
3450 addr
= gen_rtx_CONST (Pmode
, addr
);
3451 addr
= force_const_mem (Pmode
, addr
);
3452 emit_move_insn (temp
, addr
);
3454 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3457 s390_load_address (reg
, new_rtx
);
3463 /* Everything else cannot happen. */
3469 gcc_assert (GET_CODE (addr
) == PLUS
);
3471 if (GET_CODE (addr
) == PLUS
)
3473 rtx op0
= XEXP (addr
, 0), op1
= XEXP (addr
, 1);
3475 gcc_assert (!TLS_SYMBOLIC_CONST (op0
));
3476 gcc_assert (!TLS_SYMBOLIC_CONST (op1
));
3478 /* Check first to see if this is a constant offset
3479 from a local symbol reference. */
3480 if ((GET_CODE (op0
) == LABEL_REF
3481 || (GET_CODE (op0
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op0
)))
3482 && GET_CODE (op1
) == CONST_INT
)
3484 if (TARGET_CPU_ZARCH
3485 && larl_operand (op0
, VOIDmode
)
3486 && INTVAL (op1
) < (HOST_WIDE_INT
)1 << 31
3487 && INTVAL (op1
) >= -((HOST_WIDE_INT
)1 << 31))
3489 if (INTVAL (op1
) & 1)
3491 /* LARL can't handle odd offsets, so emit a
3492 pair of LARL and LA. */
3493 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3495 if (!DISP_IN_RANGE (INTVAL (op1
)))
3497 HOST_WIDE_INT even
= INTVAL (op1
) - 1;
3498 op0
= gen_rtx_PLUS (Pmode
, op0
, GEN_INT (even
));
3499 op0
= gen_rtx_CONST (Pmode
, op0
);
3503 emit_move_insn (temp
, op0
);
3504 new_rtx
= gen_rtx_PLUS (Pmode
, temp
, op1
);
3508 s390_load_address (reg
, new_rtx
);
3514 /* If the offset is even, we can just use LARL.
3515 This will happen automatically. */
3520 /* Access local symbols relative to the GOT. */
3522 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3524 if (reload_in_progress
|| reload_completed
)
3525 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3527 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op0
),
3529 addr
= gen_rtx_PLUS (Pmode
, addr
, op1
);
3530 addr
= gen_rtx_CONST (Pmode
, addr
);
3531 addr
= force_const_mem (Pmode
, addr
);
3532 emit_move_insn (temp
, addr
);
3534 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3537 s390_load_address (reg
, new_rtx
);
3543 /* Now, check whether it is a GOT relative symbol plus offset
3544 that was pulled out of the literal pool. Force it back in. */
3546 else if (GET_CODE (op0
) == UNSPEC
3547 && GET_CODE (op1
) == CONST_INT
3548 && XINT (op0
, 1) == UNSPEC_GOTOFF
)
3550 gcc_assert (XVECLEN (op0
, 0) == 1);
3552 new_rtx
= force_const_mem (Pmode
, orig
);
3555 /* Otherwise, compute the sum. */
3558 base
= legitimize_pic_address (XEXP (addr
, 0), reg
);
3559 new_rtx
= legitimize_pic_address (XEXP (addr
, 1),
3560 base
== reg
? NULL_RTX
: reg
);
3561 if (GET_CODE (new_rtx
) == CONST_INT
)
3562 new_rtx
= plus_constant (base
, INTVAL (new_rtx
));
3565 if (GET_CODE (new_rtx
) == PLUS
&& CONSTANT_P (XEXP (new_rtx
, 1)))
3567 base
= gen_rtx_PLUS (Pmode
, base
, XEXP (new_rtx
, 0));
3568 new_rtx
= XEXP (new_rtx
, 1);
3570 new_rtx
= gen_rtx_PLUS (Pmode
, base
, new_rtx
);
3573 if (GET_CODE (new_rtx
) == CONST
)
3574 new_rtx
= XEXP (new_rtx
, 0);
3575 new_rtx
= force_operand (new_rtx
, 0);
3582 /* Load the thread pointer into a register. */
3585 s390_get_thread_pointer (void)
3587 rtx tp
= gen_reg_rtx (Pmode
);
3589 emit_move_insn (tp
, gen_rtx_REG (Pmode
, TP_REGNUM
));
3590 mark_reg_pointer (tp
, BITS_PER_WORD
);
3595 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3596 in s390_tls_symbol which always refers to __tls_get_offset.
3597 The returned offset is written to RESULT_REG and an USE rtx is
3598 generated for TLS_CALL. */
3600 static GTY(()) rtx s390_tls_symbol
;
3603 s390_emit_tls_call_insn (rtx result_reg
, rtx tls_call
)
3607 gcc_assert (flag_pic
);
3609 if (!s390_tls_symbol
)
3610 s390_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_offset");
3612 insn
= s390_emit_call (s390_tls_symbol
, tls_call
, result_reg
,
3613 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
3615 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), result_reg
);
3616 RTL_CONST_CALL_P (insn
) = 1;
3619 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3620 this (thread-local) address. REG may be used as temporary. */
3623 legitimize_tls_address (rtx addr
, rtx reg
)
3625 rtx new_rtx
, tls_call
, temp
, base
, r2
, insn
;
3627 if (GET_CODE (addr
) == SYMBOL_REF
)
3628 switch (tls_symbolic_operand (addr
))
3630 case TLS_MODEL_GLOBAL_DYNAMIC
:
3632 r2
= gen_rtx_REG (Pmode
, 2);
3633 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_TLSGD
);
3634 new_rtx
= gen_rtx_CONST (Pmode
, tls_call
);
3635 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3636 emit_move_insn (r2
, new_rtx
);
3637 s390_emit_tls_call_insn (r2
, tls_call
);
3638 insn
= get_insns ();
3641 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
3642 temp
= gen_reg_rtx (Pmode
);
3643 emit_libcall_block (insn
, temp
, r2
, new_rtx
);
3645 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3648 s390_load_address (reg
, new_rtx
);
3653 case TLS_MODEL_LOCAL_DYNAMIC
:
3655 r2
= gen_rtx_REG (Pmode
, 2);
3656 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM
);
3657 new_rtx
= gen_rtx_CONST (Pmode
, tls_call
);
3658 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3659 emit_move_insn (r2
, new_rtx
);
3660 s390_emit_tls_call_insn (r2
, tls_call
);
3661 insn
= get_insns ();
3664 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM_NTPOFF
);
3665 temp
= gen_reg_rtx (Pmode
);
3666 emit_libcall_block (insn
, temp
, r2
, new_rtx
);
3668 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3669 base
= gen_reg_rtx (Pmode
);
3670 s390_load_address (base
, new_rtx
);
3672 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_DTPOFF
);
3673 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3674 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3675 temp
= gen_reg_rtx (Pmode
);
3676 emit_move_insn (temp
, new_rtx
);
3678 new_rtx
= gen_rtx_PLUS (Pmode
, base
, temp
);
3681 s390_load_address (reg
, new_rtx
);
3686 case TLS_MODEL_INITIAL_EXEC
:
3689 /* Assume GOT offset < 4k. This is handled the same way
3690 in both 31- and 64-bit code. */
3692 if (reload_in_progress
|| reload_completed
)
3693 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3695 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
3696 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3697 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new_rtx
);
3698 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3699 temp
= gen_reg_rtx (Pmode
);
3700 emit_move_insn (temp
, new_rtx
);
3702 else if (TARGET_CPU_ZARCH
)
3704 /* If the GOT offset might be >= 4k, we determine the position
3705 of the GOT entry via a PC-relative LARL. */
3707 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
3708 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3709 temp
= gen_reg_rtx (Pmode
);
3710 emit_move_insn (temp
, new_rtx
);
3712 new_rtx
= gen_const_mem (Pmode
, temp
);
3713 temp
= gen_reg_rtx (Pmode
);
3714 emit_move_insn (temp
, new_rtx
);
3718 /* If the GOT offset might be >= 4k, we have to load it
3719 from the literal pool. */
3721 if (reload_in_progress
|| reload_completed
)
3722 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3724 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
3725 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3726 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3727 temp
= gen_reg_rtx (Pmode
);
3728 emit_move_insn (temp
, new_rtx
);
3730 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3731 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3733 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new_rtx
, addr
), UNSPEC_TLS_LOAD
);
3734 temp
= gen_reg_rtx (Pmode
);
3735 emit_insn (gen_rtx_SET (Pmode
, temp
, new_rtx
));
3739 /* In position-dependent code, load the absolute address of
3740 the GOT entry from the literal pool. */
3742 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
3743 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3744 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3745 temp
= gen_reg_rtx (Pmode
);
3746 emit_move_insn (temp
, new_rtx
);
3749 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3750 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new_rtx
, addr
), UNSPEC_TLS_LOAD
);
3751 temp
= gen_reg_rtx (Pmode
);
3752 emit_insn (gen_rtx_SET (Pmode
, temp
, new_rtx
));
3755 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3758 s390_load_address (reg
, new_rtx
);
3763 case TLS_MODEL_LOCAL_EXEC
:
3764 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
3765 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3766 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3767 temp
= gen_reg_rtx (Pmode
);
3768 emit_move_insn (temp
, new_rtx
);
3770 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3773 s390_load_address (reg
, new_rtx
);
3782 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == UNSPEC
)
3784 switch (XINT (XEXP (addr
, 0), 1))
3786 case UNSPEC_INDNTPOFF
:
3787 gcc_assert (TARGET_CPU_ZARCH
);
3796 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == PLUS
3797 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST_INT
)
3799 new_rtx
= XEXP (XEXP (addr
, 0), 0);
3800 if (GET_CODE (new_rtx
) != SYMBOL_REF
)
3801 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3803 new_rtx
= legitimize_tls_address (new_rtx
, reg
);
3804 new_rtx
= plus_constant (new_rtx
, INTVAL (XEXP (XEXP (addr
, 0), 1)));
3805 new_rtx
= force_operand (new_rtx
, 0);
3809 gcc_unreachable (); /* for now ... */
3814 /* Emit insns making the address in operands[1] valid for a standard
3815 move to operands[0]. operands[1] is replaced by an address which
3816 should be used instead of the former RTX to emit the move
3820 emit_symbolic_move (rtx
*operands
)
3822 rtx temp
= !can_create_pseudo_p () ? operands
[0] : gen_reg_rtx (Pmode
);
3824 if (GET_CODE (operands
[0]) == MEM
)
3825 operands
[1] = force_reg (Pmode
, operands
[1]);
3826 else if (TLS_SYMBOLIC_CONST (operands
[1]))
3827 operands
[1] = legitimize_tls_address (operands
[1], temp
);
3829 operands
[1] = legitimize_pic_address (operands
[1], temp
);
3832 /* Try machine-dependent ways of modifying an illegitimate address X
3833 to be legitimate. If we find one, return the new, valid address.
3835 OLDX is the address as it was before break_out_memory_refs was called.
3836 In some cases it is useful to look at this to decide what needs to be done.
3838 MODE is the mode of the operand pointed to by X.
3840 When -fpic is used, special handling is needed for symbolic references.
3841 See comments by legitimize_pic_address for details. */
3844 s390_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3845 enum machine_mode mode ATTRIBUTE_UNUSED
)
3847 rtx constant_term
= const0_rtx
;
3849 if (TLS_SYMBOLIC_CONST (x
))
3851 x
= legitimize_tls_address (x
, 0);
3853 if (s390_legitimate_address_p (mode
, x
, FALSE
))
3856 else if (GET_CODE (x
) == PLUS
3857 && (TLS_SYMBOLIC_CONST (XEXP (x
, 0))
3858 || TLS_SYMBOLIC_CONST (XEXP (x
, 1))))
3864 if (SYMBOLIC_CONST (x
)
3865 || (GET_CODE (x
) == PLUS
3866 && (SYMBOLIC_CONST (XEXP (x
, 0))
3867 || SYMBOLIC_CONST (XEXP (x
, 1)))))
3868 x
= legitimize_pic_address (x
, 0);
3870 if (s390_legitimate_address_p (mode
, x
, FALSE
))
3874 x
= eliminate_constant_term (x
, &constant_term
);
3876 /* Optimize loading of large displacements by splitting them
3877 into the multiple of 4K and the rest; this allows the
3878 former to be CSE'd if possible.
3880 Don't do this if the displacement is added to a register
3881 pointing into the stack frame, as the offsets will
3882 change later anyway. */
3884 if (GET_CODE (constant_term
) == CONST_INT
3885 && !TARGET_LONG_DISPLACEMENT
3886 && !DISP_IN_RANGE (INTVAL (constant_term
))
3887 && !(REG_P (x
) && REGNO_PTR_FRAME_P (REGNO (x
))))
3889 HOST_WIDE_INT lower
= INTVAL (constant_term
) & 0xfff;
3890 HOST_WIDE_INT upper
= INTVAL (constant_term
) ^ lower
;
3892 rtx temp
= gen_reg_rtx (Pmode
);
3893 rtx val
= force_operand (GEN_INT (upper
), temp
);
3895 emit_move_insn (temp
, val
);
3897 x
= gen_rtx_PLUS (Pmode
, x
, temp
);
3898 constant_term
= GEN_INT (lower
);
3901 if (GET_CODE (x
) == PLUS
)
3903 if (GET_CODE (XEXP (x
, 0)) == REG
)
3905 rtx temp
= gen_reg_rtx (Pmode
);
3906 rtx val
= force_operand (XEXP (x
, 1), temp
);
3908 emit_move_insn (temp
, val
);
3910 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0), temp
);
3913 else if (GET_CODE (XEXP (x
, 1)) == REG
)
3915 rtx temp
= gen_reg_rtx (Pmode
);
3916 rtx val
= force_operand (XEXP (x
, 0), temp
);
3918 emit_move_insn (temp
, val
);
3920 x
= gen_rtx_PLUS (Pmode
, temp
, XEXP (x
, 1));
3924 if (constant_term
!= const0_rtx
)
3925 x
= gen_rtx_PLUS (Pmode
, x
, constant_term
);
3930 /* Try a machine-dependent way of reloading an illegitimate address AD
3931 operand. If we find one, push the reload and return the new address.
3933 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3934 and TYPE is the reload type of the current reload. */
3937 legitimize_reload_address (rtx ad
, enum machine_mode mode ATTRIBUTE_UNUSED
,
3938 int opnum
, int type
)
3940 if (!optimize
|| TARGET_LONG_DISPLACEMENT
)
3943 if (GET_CODE (ad
) == PLUS
)
3945 rtx tem
= simplify_binary_operation (PLUS
, Pmode
,
3946 XEXP (ad
, 0), XEXP (ad
, 1));
3951 if (GET_CODE (ad
) == PLUS
3952 && GET_CODE (XEXP (ad
, 0)) == REG
3953 && GET_CODE (XEXP (ad
, 1)) == CONST_INT
3954 && !DISP_IN_RANGE (INTVAL (XEXP (ad
, 1))))
3956 HOST_WIDE_INT lower
= INTVAL (XEXP (ad
, 1)) & 0xfff;
3957 HOST_WIDE_INT upper
= INTVAL (XEXP (ad
, 1)) ^ lower
;
3958 rtx cst
, tem
, new_rtx
;
3960 cst
= GEN_INT (upper
);
3961 if (!legitimate_reload_constant_p (cst
))
3962 cst
= force_const_mem (Pmode
, cst
);
3964 tem
= gen_rtx_PLUS (Pmode
, XEXP (ad
, 0), cst
);
3965 new_rtx
= gen_rtx_PLUS (Pmode
, tem
, GEN_INT (lower
));
3967 push_reload (XEXP (tem
, 1), 0, &XEXP (tem
, 1), 0,
3968 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
3969 opnum
, (enum reload_type
) type
);
3976 /* Emit code to move LEN bytes from DST to SRC. */
3979 s390_expand_movmem (rtx dst
, rtx src
, rtx len
)
3981 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
3983 if (INTVAL (len
) > 0)
3984 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (INTVAL (len
) - 1)));
3987 else if (TARGET_MVCLE
)
3989 emit_insn (gen_movmem_long (dst
, src
, convert_to_mode (Pmode
, len
, 1)));
3994 rtx dst_addr
, src_addr
, count
, blocks
, temp
;
3995 rtx loop_start_label
= gen_label_rtx ();
3996 rtx loop_end_label
= gen_label_rtx ();
3997 rtx end_label
= gen_label_rtx ();
3998 enum machine_mode mode
;
4000 mode
= GET_MODE (len
);
4001 if (mode
== VOIDmode
)
4004 dst_addr
= gen_reg_rtx (Pmode
);
4005 src_addr
= gen_reg_rtx (Pmode
);
4006 count
= gen_reg_rtx (mode
);
4007 blocks
= gen_reg_rtx (mode
);
4009 convert_move (count
, len
, 1);
4010 emit_cmp_and_jump_insns (count
, const0_rtx
,
4011 EQ
, NULL_RTX
, mode
, 1, end_label
);
4013 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
4014 emit_move_insn (src_addr
, force_operand (XEXP (src
, 0), NULL_RTX
));
4015 dst
= change_address (dst
, VOIDmode
, dst_addr
);
4016 src
= change_address (src
, VOIDmode
, src_addr
);
4018 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4021 emit_move_insn (count
, temp
);
4023 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4026 emit_move_insn (blocks
, temp
);
4028 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4029 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4031 emit_label (loop_start_label
);
4034 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 768))
4038 /* Issue a read prefetch for the +3 cache line. */
4039 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, src_addr
, GEN_INT (768)),
4040 const0_rtx
, const0_rtx
);
4041 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4042 emit_insn (prefetch
);
4044 /* Issue a write prefetch for the +3 cache line. */
4045 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (768)),
4046 const1_rtx
, const0_rtx
);
4047 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4048 emit_insn (prefetch
);
4051 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (255)));
4052 s390_load_address (dst_addr
,
4053 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
4054 s390_load_address (src_addr
,
4055 gen_rtx_PLUS (Pmode
, src_addr
, GEN_INT (256)));
4057 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4060 emit_move_insn (blocks
, temp
);
4062 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4063 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4065 emit_jump (loop_start_label
);
4066 emit_label (loop_end_label
);
4068 emit_insn (gen_movmem_short (dst
, src
,
4069 convert_to_mode (Pmode
, count
, 1)));
4070 emit_label (end_label
);
4074 /* Emit code to set LEN bytes at DST to VAL.
4075 Make use of clrmem if VAL is zero. */
4078 s390_expand_setmem (rtx dst
, rtx len
, rtx val
)
4080 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) == 0)
4083 gcc_assert (GET_CODE (val
) == CONST_INT
|| GET_MODE (val
) == QImode
);
4085 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) > 0 && INTVAL (len
) <= 257)
4087 if (val
== const0_rtx
&& INTVAL (len
) <= 256)
4088 emit_insn (gen_clrmem_short (dst
, GEN_INT (INTVAL (len
) - 1)));
4091 /* Initialize memory by storing the first byte. */
4092 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
4094 if (INTVAL (len
) > 1)
4096 /* Initiate 1 byte overlap move.
4097 The first byte of DST is propagated through DSTP1.
4098 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
4099 DST is set to size 1 so the rest of the memory location
4100 does not count as source operand. */
4101 rtx dstp1
= adjust_address (dst
, VOIDmode
, 1);
4102 set_mem_size (dst
, 1);
4104 emit_insn (gen_movmem_short (dstp1
, dst
,
4105 GEN_INT (INTVAL (len
) - 2)));
4110 else if (TARGET_MVCLE
)
4112 val
= force_not_mem (convert_modes (Pmode
, QImode
, val
, 1));
4113 emit_insn (gen_setmem_long (dst
, convert_to_mode (Pmode
, len
, 1), val
));
4118 rtx dst_addr
, count
, blocks
, temp
, dstp1
= NULL_RTX
;
4119 rtx loop_start_label
= gen_label_rtx ();
4120 rtx loop_end_label
= gen_label_rtx ();
4121 rtx end_label
= gen_label_rtx ();
4122 enum machine_mode mode
;
4124 mode
= GET_MODE (len
);
4125 if (mode
== VOIDmode
)
4128 dst_addr
= gen_reg_rtx (Pmode
);
4129 count
= gen_reg_rtx (mode
);
4130 blocks
= gen_reg_rtx (mode
);
4132 convert_move (count
, len
, 1);
4133 emit_cmp_and_jump_insns (count
, const0_rtx
,
4134 EQ
, NULL_RTX
, mode
, 1, end_label
);
4136 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
4137 dst
= change_address (dst
, VOIDmode
, dst_addr
);
4139 if (val
== const0_rtx
)
4140 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4144 dstp1
= adjust_address (dst
, VOIDmode
, 1);
4145 set_mem_size (dst
, 1);
4147 /* Initialize memory by storing the first byte. */
4148 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
4150 /* If count is 1 we are done. */
4151 emit_cmp_and_jump_insns (count
, const1_rtx
,
4152 EQ
, NULL_RTX
, mode
, 1, end_label
);
4154 temp
= expand_binop (mode
, add_optab
, count
, GEN_INT (-2), count
, 1,
4158 emit_move_insn (count
, temp
);
4160 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4163 emit_move_insn (blocks
, temp
);
4165 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4166 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4168 emit_label (loop_start_label
);
4171 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 1024))
4173 /* Issue a write prefetch for the +4 cache line. */
4174 rtx prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, dst_addr
,
4176 const1_rtx
, const0_rtx
);
4177 emit_insn (prefetch
);
4178 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4181 if (val
== const0_rtx
)
4182 emit_insn (gen_clrmem_short (dst
, GEN_INT (255)));
4184 emit_insn (gen_movmem_short (dstp1
, dst
, GEN_INT (255)));
4185 s390_load_address (dst_addr
,
4186 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
4188 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4191 emit_move_insn (blocks
, temp
);
4193 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4194 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4196 emit_jump (loop_start_label
);
4197 emit_label (loop_end_label
);
4199 if (val
== const0_rtx
)
4200 emit_insn (gen_clrmem_short (dst
, convert_to_mode (Pmode
, count
, 1)));
4202 emit_insn (gen_movmem_short (dstp1
, dst
, convert_to_mode (Pmode
, count
, 1)));
4203 emit_label (end_label
);
4207 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4208 and return the result in TARGET. */
4211 s390_expand_cmpmem (rtx target
, rtx op0
, rtx op1
, rtx len
)
4213 rtx ccreg
= gen_rtx_REG (CCUmode
, CC_REGNUM
);
4216 /* As the result of CMPINT is inverted compared to what we need,
4217 we have to swap the operands. */
4218 tmp
= op0
; op0
= op1
; op1
= tmp
;
4220 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
4222 if (INTVAL (len
) > 0)
4224 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (INTVAL (len
) - 1)));
4225 emit_insn (gen_cmpint (target
, ccreg
));
4228 emit_move_insn (target
, const0_rtx
);
4230 else if (TARGET_MVCLE
)
4232 emit_insn (gen_cmpmem_long (op0
, op1
, convert_to_mode (Pmode
, len
, 1)));
4233 emit_insn (gen_cmpint (target
, ccreg
));
4237 rtx addr0
, addr1
, count
, blocks
, temp
;
4238 rtx loop_start_label
= gen_label_rtx ();
4239 rtx loop_end_label
= gen_label_rtx ();
4240 rtx end_label
= gen_label_rtx ();
4241 enum machine_mode mode
;
4243 mode
= GET_MODE (len
);
4244 if (mode
== VOIDmode
)
4247 addr0
= gen_reg_rtx (Pmode
);
4248 addr1
= gen_reg_rtx (Pmode
);
4249 count
= gen_reg_rtx (mode
);
4250 blocks
= gen_reg_rtx (mode
);
4252 convert_move (count
, len
, 1);
4253 emit_cmp_and_jump_insns (count
, const0_rtx
,
4254 EQ
, NULL_RTX
, mode
, 1, end_label
);
4256 emit_move_insn (addr0
, force_operand (XEXP (op0
, 0), NULL_RTX
));
4257 emit_move_insn (addr1
, force_operand (XEXP (op1
, 0), NULL_RTX
));
4258 op0
= change_address (op0
, VOIDmode
, addr0
);
4259 op1
= change_address (op1
, VOIDmode
, addr1
);
4261 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4264 emit_move_insn (count
, temp
);
4266 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4269 emit_move_insn (blocks
, temp
);
4271 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4272 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4274 emit_label (loop_start_label
);
4277 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 512))
4281 /* Issue a read prefetch for the +2 cache line of operand 1. */
4282 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, addr0
, GEN_INT (512)),
4283 const0_rtx
, const0_rtx
);
4284 emit_insn (prefetch
);
4285 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4287 /* Issue a read prefetch for the +2 cache line of operand 2. */
4288 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, addr1
, GEN_INT (512)),
4289 const0_rtx
, const0_rtx
);
4290 emit_insn (prefetch
);
4291 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4294 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (255)));
4295 temp
= gen_rtx_NE (VOIDmode
, ccreg
, const0_rtx
);
4296 temp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, temp
,
4297 gen_rtx_LABEL_REF (VOIDmode
, end_label
), pc_rtx
);
4298 temp
= gen_rtx_SET (VOIDmode
, pc_rtx
, temp
);
4299 emit_jump_insn (temp
);
4301 s390_load_address (addr0
,
4302 gen_rtx_PLUS (Pmode
, addr0
, GEN_INT (256)));
4303 s390_load_address (addr1
,
4304 gen_rtx_PLUS (Pmode
, addr1
, GEN_INT (256)));
4306 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4309 emit_move_insn (blocks
, temp
);
4311 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4312 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4314 emit_jump (loop_start_label
);
4315 emit_label (loop_end_label
);
4317 emit_insn (gen_cmpmem_short (op0
, op1
,
4318 convert_to_mode (Pmode
, count
, 1)));
4319 emit_label (end_label
);
4321 emit_insn (gen_cmpint (target
, ccreg
));
4326 /* Expand conditional increment or decrement using alc/slb instructions.
4327 Should generate code setting DST to either SRC or SRC + INCREMENT,
4328 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4329 Returns true if successful, false otherwise.
4331 That makes it possible to implement some if-constructs without jumps e.g.:
4332 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4333 unsigned int a, b, c;
4334 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4335 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4336 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4337 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4339 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4340 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4341 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4342 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4343 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4346 s390_expand_addcc (enum rtx_code cmp_code
, rtx cmp_op0
, rtx cmp_op1
,
4347 rtx dst
, rtx src
, rtx increment
)
4349 enum machine_mode cmp_mode
;
4350 enum machine_mode cc_mode
;
4356 if ((GET_MODE (cmp_op0
) == SImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
4357 && (GET_MODE (cmp_op1
) == SImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
4359 else if ((GET_MODE (cmp_op0
) == DImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
4360 && (GET_MODE (cmp_op1
) == DImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
4365 /* Try ADD LOGICAL WITH CARRY. */
4366 if (increment
== const1_rtx
)
4368 /* Determine CC mode to use. */
4369 if (cmp_code
== EQ
|| cmp_code
== NE
)
4371 if (cmp_op1
!= const0_rtx
)
4373 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
4374 NULL_RTX
, 0, OPTAB_WIDEN
);
4375 cmp_op1
= const0_rtx
;
4378 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
4381 if (cmp_code
== LTU
|| cmp_code
== LEU
)
4386 cmp_code
= swap_condition (cmp_code
);
4403 /* Emit comparison instruction pattern. */
4404 if (!register_operand (cmp_op0
, cmp_mode
))
4405 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
4407 insn
= gen_rtx_SET (VOIDmode
, gen_rtx_REG (cc_mode
, CC_REGNUM
),
4408 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
4409 /* We use insn_invalid_p here to add clobbers if required. */
4410 ret
= insn_invalid_p (emit_insn (insn
));
4413 /* Emit ALC instruction pattern. */
4414 op_res
= gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
4415 gen_rtx_REG (cc_mode
, CC_REGNUM
),
4418 if (src
!= const0_rtx
)
4420 if (!register_operand (src
, GET_MODE (dst
)))
4421 src
= force_reg (GET_MODE (dst
), src
);
4423 op_res
= gen_rtx_PLUS (GET_MODE (dst
), op_res
, src
);
4424 op_res
= gen_rtx_PLUS (GET_MODE (dst
), op_res
, const0_rtx
);
4427 p
= rtvec_alloc (2);
4429 gen_rtx_SET (VOIDmode
, dst
, op_res
);
4431 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4432 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
4437 /* Try SUBTRACT LOGICAL WITH BORROW. */
4438 if (increment
== constm1_rtx
)
4440 /* Determine CC mode to use. */
4441 if (cmp_code
== EQ
|| cmp_code
== NE
)
4443 if (cmp_op1
!= const0_rtx
)
4445 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
4446 NULL_RTX
, 0, OPTAB_WIDEN
);
4447 cmp_op1
= const0_rtx
;
4450 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
4453 if (cmp_code
== GTU
|| cmp_code
== GEU
)
4458 cmp_code
= swap_condition (cmp_code
);
4475 /* Emit comparison instruction pattern. */
4476 if (!register_operand (cmp_op0
, cmp_mode
))
4477 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
4479 insn
= gen_rtx_SET (VOIDmode
, gen_rtx_REG (cc_mode
, CC_REGNUM
),
4480 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
4481 /* We use insn_invalid_p here to add clobbers if required. */
4482 ret
= insn_invalid_p (emit_insn (insn
));
4485 /* Emit SLB instruction pattern. */
4486 if (!register_operand (src
, GET_MODE (dst
)))
4487 src
= force_reg (GET_MODE (dst
), src
);
4489 op_res
= gen_rtx_MINUS (GET_MODE (dst
),
4490 gen_rtx_MINUS (GET_MODE (dst
), src
, const0_rtx
),
4491 gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
4492 gen_rtx_REG (cc_mode
, CC_REGNUM
),
4494 p
= rtvec_alloc (2);
4496 gen_rtx_SET (VOIDmode
, dst
, op_res
);
4498 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4499 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
4507 /* Expand code for the insv template. Return true if successful. */
4510 s390_expand_insv (rtx dest
, rtx op1
, rtx op2
, rtx src
)
4512 int bitsize
= INTVAL (op1
);
4513 int bitpos
= INTVAL (op2
);
4515 /* On z10 we can use the risbg instruction to implement insv. */
4517 && ((GET_MODE (dest
) == DImode
&& GET_MODE (src
) == DImode
)
4518 || (GET_MODE (dest
) == SImode
&& GET_MODE (src
) == SImode
)))
4523 op
= gen_rtx_SET (GET_MODE(src
),
4524 gen_rtx_ZERO_EXTRACT (GET_MODE (dest
), dest
, op1
, op2
),
4526 clobber
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4527 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clobber
)));
4532 /* We need byte alignment. */
4533 if (bitsize
% BITS_PER_UNIT
)
4537 && memory_operand (dest
, VOIDmode
)
4538 && (register_operand (src
, word_mode
)
4539 || const_int_operand (src
, VOIDmode
)))
4541 /* Emit standard pattern if possible. */
4542 enum machine_mode mode
= smallest_mode_for_size (bitsize
, MODE_INT
);
4543 if (GET_MODE_BITSIZE (mode
) == bitsize
)
4544 emit_move_insn (adjust_address (dest
, mode
, 0), gen_lowpart (mode
, src
));
4546 /* (set (ze (mem)) (const_int)). */
4547 else if (const_int_operand (src
, VOIDmode
))
4549 int size
= bitsize
/ BITS_PER_UNIT
;
4550 rtx src_mem
= adjust_address (force_const_mem (word_mode
, src
), BLKmode
,
4551 GET_MODE_SIZE (word_mode
) - size
);
4553 dest
= adjust_address (dest
, BLKmode
, 0);
4554 set_mem_size (dest
, size
);
4555 s390_expand_movmem (dest
, src_mem
, GEN_INT (size
));
4558 /* (set (ze (mem)) (reg)). */
4559 else if (register_operand (src
, word_mode
))
4561 if (bitsize
<= GET_MODE_BITSIZE (SImode
))
4562 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
, op1
,
4566 /* Emit st,stcmh sequence. */
4567 int stcmh_width
= bitsize
- GET_MODE_BITSIZE (SImode
);
4568 int size
= stcmh_width
/ BITS_PER_UNIT
;
4570 emit_move_insn (adjust_address (dest
, SImode
, size
),
4571 gen_lowpart (SImode
, src
));
4572 set_mem_size (dest
, size
);
4573 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
, GEN_INT
4574 (stcmh_width
), const0_rtx
),
4575 gen_rtx_LSHIFTRT (word_mode
, src
, GEN_INT
4576 (GET_MODE_BITSIZE (SImode
))));
4585 /* (set (ze (reg)) (const_int)). */
4587 && register_operand (dest
, word_mode
)
4588 && (bitpos
% 16) == 0
4589 && (bitsize
% 16) == 0
4590 && const_int_operand (src
, VOIDmode
))
4592 HOST_WIDE_INT val
= INTVAL (src
);
4593 int regpos
= bitpos
+ bitsize
;
4595 while (regpos
> bitpos
)
4597 enum machine_mode putmode
;
4600 if (TARGET_EXTIMM
&& (regpos
% 32 == 0) && (regpos
>= bitpos
+ 32))
4605 putsize
= GET_MODE_BITSIZE (putmode
);
4607 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
,
4610 gen_int_mode (val
, putmode
));
4613 gcc_assert (regpos
== bitpos
);
4620 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4621 register that holds VAL of mode MODE shifted by COUNT bits. */
4624 s390_expand_mask_and_shift (rtx val
, enum machine_mode mode
, rtx count
)
4626 val
= expand_simple_binop (SImode
, AND
, val
, GEN_INT (GET_MODE_MASK (mode
)),
4627 NULL_RTX
, 1, OPTAB_DIRECT
);
4628 return expand_simple_binop (SImode
, ASHIFT
, val
, count
,
4629 NULL_RTX
, 1, OPTAB_DIRECT
);
4632 /* Structure to hold the initial parameters for a compare_and_swap operation
4633 in HImode and QImode. */
4635 struct alignment_context
4637 rtx memsi
; /* SI aligned memory location. */
4638 rtx shift
; /* Bit offset with regard to lsb. */
4639 rtx modemask
; /* Mask of the HQImode shifted by SHIFT bits. */
4640 rtx modemaski
; /* ~modemask */
4641 bool aligned
; /* True if memory is aligned, false else. */
4644 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4645 structure AC for transparent simplifying, if the memory alignment is known
4646 to be at least 32bit. MEM is the memory location for the actual operation
4647 and MODE its mode. */
4650 init_alignment_context (struct alignment_context
*ac
, rtx mem
,
4651 enum machine_mode mode
)
4653 ac
->shift
= GEN_INT (GET_MODE_SIZE (SImode
) - GET_MODE_SIZE (mode
));
4654 ac
->aligned
= (MEM_ALIGN (mem
) >= GET_MODE_BITSIZE (SImode
));
4657 ac
->memsi
= adjust_address (mem
, SImode
, 0); /* Memory is aligned. */
4660 /* Alignment is unknown. */
4661 rtx byteoffset
, addr
, align
;
4663 /* Force the address into a register. */
4664 addr
= force_reg (Pmode
, XEXP (mem
, 0));
4666 /* Align it to SImode. */
4667 align
= expand_simple_binop (Pmode
, AND
, addr
,
4668 GEN_INT (-GET_MODE_SIZE (SImode
)),
4669 NULL_RTX
, 1, OPTAB_DIRECT
);
4671 ac
->memsi
= gen_rtx_MEM (SImode
, align
);
4672 MEM_VOLATILE_P (ac
->memsi
) = MEM_VOLATILE_P (mem
);
4673 set_mem_alias_set (ac
->memsi
, ALIAS_SET_MEMORY_BARRIER
);
4674 set_mem_align (ac
->memsi
, GET_MODE_BITSIZE (SImode
));
4676 /* Calculate shiftcount. */
4677 byteoffset
= expand_simple_binop (Pmode
, AND
, addr
,
4678 GEN_INT (GET_MODE_SIZE (SImode
) - 1),
4679 NULL_RTX
, 1, OPTAB_DIRECT
);
4680 /* As we already have some offset, evaluate the remaining distance. */
4681 ac
->shift
= expand_simple_binop (SImode
, MINUS
, ac
->shift
, byteoffset
,
4682 NULL_RTX
, 1, OPTAB_DIRECT
);
4685 /* Shift is the byte count, but we need the bitcount. */
4686 ac
->shift
= expand_simple_binop (SImode
, MULT
, ac
->shift
, GEN_INT (BITS_PER_UNIT
),
4687 NULL_RTX
, 1, OPTAB_DIRECT
);
4688 /* Calculate masks. */
4689 ac
->modemask
= expand_simple_binop (SImode
, ASHIFT
,
4690 GEN_INT (GET_MODE_MASK (mode
)), ac
->shift
,
4691 NULL_RTX
, 1, OPTAB_DIRECT
);
4692 ac
->modemaski
= expand_simple_unop (SImode
, NOT
, ac
->modemask
, NULL_RTX
, 1);
4695 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4696 the memory location, CMP the old value to compare MEM with and NEW_RTX the value
4697 to set if CMP == MEM.
4698 CMP is never in memory for compare_and_swap_cc because
4699 expand_bool_compare_and_swap puts it into a register for later compare. */
4702 s390_expand_cs_hqi (enum machine_mode mode
, rtx target
, rtx mem
, rtx cmp
, rtx new_rtx
)
4704 struct alignment_context ac
;
4705 rtx cmpv
, newv
, val
, resv
, cc
;
4706 rtx res
= gen_reg_rtx (SImode
);
4707 rtx csloop
= gen_label_rtx ();
4708 rtx csend
= gen_label_rtx ();
4710 gcc_assert (register_operand (target
, VOIDmode
));
4711 gcc_assert (MEM_P (mem
));
4713 init_alignment_context (&ac
, mem
, mode
);
4715 /* Shift the values to the correct bit positions. */
4716 if (!(ac
.aligned
&& MEM_P (cmp
)))
4717 cmp
= s390_expand_mask_and_shift (cmp
, mode
, ac
.shift
);
4718 if (!(ac
.aligned
&& MEM_P (new_rtx
)))
4719 new_rtx
= s390_expand_mask_and_shift (new_rtx
, mode
, ac
.shift
);
4721 /* Load full word. Subsequent loads are performed by CS. */
4722 val
= expand_simple_binop (SImode
, AND
, ac
.memsi
, ac
.modemaski
,
4723 NULL_RTX
, 1, OPTAB_DIRECT
);
4725 /* Start CS loop. */
4726 emit_label (csloop
);
4727 /* val = "<mem>00..0<mem>"
4728 * cmp = "00..0<cmp>00..0"
4729 * new = "00..0<new>00..0"
4732 /* Patch cmp and new with val at correct position. */
4733 if (ac
.aligned
&& MEM_P (cmp
))
4735 cmpv
= force_reg (SImode
, val
);
4736 store_bit_field (cmpv
, GET_MODE_BITSIZE (mode
), 0,
4740 cmpv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, cmp
, val
,
4741 NULL_RTX
, 1, OPTAB_DIRECT
));
4742 if (ac
.aligned
&& MEM_P (new_rtx
))
4744 newv
= force_reg (SImode
, val
);
4745 store_bit_field (newv
, GET_MODE_BITSIZE (mode
), 0,
4746 0, 0, SImode
, new_rtx
);
4749 newv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, new_rtx
, val
,
4750 NULL_RTX
, 1, OPTAB_DIRECT
));
4752 /* Jump to end if we're done (likely?). */
4753 s390_emit_jump (csend
, s390_emit_compare_and_swap (EQ
, res
, ac
.memsi
,
4756 /* Check for changes outside mode. */
4757 resv
= expand_simple_binop (SImode
, AND
, res
, ac
.modemaski
,
4758 NULL_RTX
, 1, OPTAB_DIRECT
);
4759 cc
= s390_emit_compare (NE
, resv
, val
);
4760 emit_move_insn (val
, resv
);
4761 /* Loop internal if so. */
4762 s390_emit_jump (csloop
, cc
);
4766 /* Return the correct part of the bitfield. */
4767 convert_move (target
, expand_simple_binop (SImode
, LSHIFTRT
, res
, ac
.shift
,
4768 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
4771 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4772 and VAL the value to play with. If AFTER is true then store the value
4773 MEM holds after the operation, if AFTER is false then store the value MEM
4774 holds before the operation. If TARGET is zero then discard that value, else
4775 store it to TARGET. */
4778 s390_expand_atomic (enum machine_mode mode
, enum rtx_code code
,
4779 rtx target
, rtx mem
, rtx val
, bool after
)
4781 struct alignment_context ac
;
4783 rtx new_rtx
= gen_reg_rtx (SImode
);
4784 rtx orig
= gen_reg_rtx (SImode
);
4785 rtx csloop
= gen_label_rtx ();
4787 gcc_assert (!target
|| register_operand (target
, VOIDmode
));
4788 gcc_assert (MEM_P (mem
));
4790 init_alignment_context (&ac
, mem
, mode
);
4792 /* Shift val to the correct bit positions.
4793 Preserve "icm", but prevent "ex icm". */
4794 if (!(ac
.aligned
&& code
== SET
&& MEM_P (val
)))
4795 val
= s390_expand_mask_and_shift (val
, mode
, ac
.shift
);
4797 /* Further preparation insns. */
4798 if (code
== PLUS
|| code
== MINUS
)
4799 emit_move_insn (orig
, val
);
4800 else if (code
== MULT
|| code
== AND
) /* val = "11..1<val>11..1" */
4801 val
= expand_simple_binop (SImode
, XOR
, val
, ac
.modemaski
,
4802 NULL_RTX
, 1, OPTAB_DIRECT
);
4804 /* Load full word. Subsequent loads are performed by CS. */
4805 cmp
= force_reg (SImode
, ac
.memsi
);
4807 /* Start CS loop. */
4808 emit_label (csloop
);
4809 emit_move_insn (new_rtx
, cmp
);
4811 /* Patch new with val at correct position. */
4816 val
= expand_simple_binop (SImode
, code
, new_rtx
, orig
,
4817 NULL_RTX
, 1, OPTAB_DIRECT
);
4818 val
= expand_simple_binop (SImode
, AND
, val
, ac
.modemask
,
4819 NULL_RTX
, 1, OPTAB_DIRECT
);
4822 if (ac
.aligned
&& MEM_P (val
))
4823 store_bit_field (new_rtx
, GET_MODE_BITSIZE (mode
), 0,
4827 new_rtx
= expand_simple_binop (SImode
, AND
, new_rtx
, ac
.modemaski
,
4828 NULL_RTX
, 1, OPTAB_DIRECT
);
4829 new_rtx
= expand_simple_binop (SImode
, IOR
, new_rtx
, val
,
4830 NULL_RTX
, 1, OPTAB_DIRECT
);
4836 new_rtx
= expand_simple_binop (SImode
, code
, new_rtx
, val
,
4837 NULL_RTX
, 1, OPTAB_DIRECT
);
4839 case MULT
: /* NAND */
4840 new_rtx
= expand_simple_binop (SImode
, AND
, new_rtx
, val
,
4841 NULL_RTX
, 1, OPTAB_DIRECT
);
4842 new_rtx
= expand_simple_binop (SImode
, XOR
, new_rtx
, ac
.modemask
,
4843 NULL_RTX
, 1, OPTAB_DIRECT
);
4849 s390_emit_jump (csloop
, s390_emit_compare_and_swap (NE
, cmp
,
4850 ac
.memsi
, cmp
, new_rtx
));
4852 /* Return the correct part of the bitfield. */
4854 convert_move (target
, expand_simple_binop (SImode
, LSHIFTRT
,
4855 after
? new_rtx
: cmp
, ac
.shift
,
4856 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
4859 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4860 We need to emit DTP-relative relocations. */
4862 static void s390_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
4865 s390_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4870 fputs ("\t.long\t", file
);
4873 fputs ("\t.quad\t", file
);
4878 output_addr_const (file
, x
);
4879 fputs ("@DTPOFF", file
);
4882 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4883 /* Implement TARGET_MANGLE_TYPE. */
4886 s390_mangle_type (const_tree type
)
4888 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
4889 && TARGET_LONG_DOUBLE_128
)
4892 /* For all other types, use normal C++ mangling. */
4897 /* In the name of slightly smaller debug output, and to cater to
4898 general assembler lossage, recognize various UNSPEC sequences
4899 and turn them back into a direct symbol reference. */
4902 s390_delegitimize_address (rtx orig_x
)
4906 orig_x
= delegitimize_mem_from_attrs (orig_x
);
4909 /* Extract the symbol ref from:
4910 (plus:SI (reg:SI 12 %r12)
4911 (const:SI (unspec:SI [(symbol_ref/f:SI ("*.LC0"))]
4912 UNSPEC_GOTOFF/PLTOFF)))
4914 (plus:SI (reg:SI 12 %r12)
4915 (const:SI (plus:SI (unspec:SI [(symbol_ref:SI ("L"))]
4916 UNSPEC_GOTOFF/PLTOFF)
4917 (const_int 4 [0x4])))) */
4918 if (GET_CODE (x
) == PLUS
4919 && REG_P (XEXP (x
, 0))
4920 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
4921 && GET_CODE (XEXP (x
, 1)) == CONST
)
4923 HOST_WIDE_INT offset
= 0;
4925 /* The const operand. */
4926 y
= XEXP (XEXP (x
, 1), 0);
4928 if (GET_CODE (y
) == PLUS
4929 && GET_CODE (XEXP (y
, 1)) == CONST_INT
)
4931 offset
= INTVAL (XEXP (y
, 1));
4935 if (GET_CODE (y
) == UNSPEC
4936 && (XINT (y
, 1) == UNSPEC_GOTOFF
4937 || XINT (y
, 1) == UNSPEC_PLTOFF
))
4938 return plus_constant (XVECEXP (y
, 0, 0), offset
);
4941 if (GET_CODE (x
) != MEM
)
4945 if (GET_CODE (x
) == PLUS
4946 && GET_CODE (XEXP (x
, 1)) == CONST
4947 && GET_CODE (XEXP (x
, 0)) == REG
4948 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
)
4950 y
= XEXP (XEXP (x
, 1), 0);
4951 if (GET_CODE (y
) == UNSPEC
4952 && XINT (y
, 1) == UNSPEC_GOT
)
4953 y
= XVECEXP (y
, 0, 0);
4957 else if (GET_CODE (x
) == CONST
)
4959 /* Extract the symbol ref from:
4960 (mem:QI (const:DI (unspec:DI [(symbol_ref:DI ("foo"))]
4961 UNSPEC_PLT/GOTENT))) */
4964 if (GET_CODE (y
) == UNSPEC
4965 && (XINT (y
, 1) == UNSPEC_GOTENT
4966 || XINT (y
, 1) == UNSPEC_PLT
))
4967 y
= XVECEXP (y
, 0, 0);
4974 if (GET_MODE (orig_x
) != Pmode
)
4976 if (GET_MODE (orig_x
) == BLKmode
)
4978 y
= lowpart_subreg (GET_MODE (orig_x
), y
, Pmode
);
4985 /* Output operand OP to stdio stream FILE.
4986 OP is an address (register + offset) which is not used to address data;
4987 instead the rightmost bits are interpreted as the value. */
4990 print_shift_count_operand (FILE *file
, rtx op
)
4992 HOST_WIDE_INT offset
;
4995 /* Extract base register and offset. */
4996 if (!s390_decompose_shift_count (op
, &base
, &offset
))
5002 gcc_assert (GET_CODE (base
) == REG
);
5003 gcc_assert (REGNO (base
) < FIRST_PSEUDO_REGISTER
);
5004 gcc_assert (REGNO_REG_CLASS (REGNO (base
)) == ADDR_REGS
);
5007 /* Offsets are constricted to twelve bits. */
5008 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
& ((1 << 12) - 1));
5010 fprintf (file
, "(%s)", reg_names
[REGNO (base
)]);
5013 /* See 'get_some_local_dynamic_name'. */
5016 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
5020 if (GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
5022 x
= get_pool_constant (x
);
5023 return for_each_rtx (&x
, get_some_local_dynamic_name_1
, 0);
5026 if (GET_CODE (x
) == SYMBOL_REF
5027 && tls_symbolic_operand (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
5029 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
5036 /* Locate some local-dynamic symbol still in use by this function
5037 so that we can print its name in local-dynamic base patterns. */
5040 get_some_local_dynamic_name (void)
5044 if (cfun
->machine
->some_ld_name
)
5045 return cfun
->machine
->some_ld_name
;
5047 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5049 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
5050 return cfun
->machine
->some_ld_name
;
5055 /* Output machine-dependent UNSPECs occurring in address constant X
5056 in assembler syntax to stdio stream FILE. Returns true if the
5057 constant X could be recognized, false otherwise. */
5060 s390_output_addr_const_extra (FILE *file
, rtx x
)
5062 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 1)
5063 switch (XINT (x
, 1))
5066 output_addr_const (file
, XVECEXP (x
, 0, 0));
5067 fprintf (file
, "@GOTENT");
5070 output_addr_const (file
, XVECEXP (x
, 0, 0));
5071 fprintf (file
, "@GOT");
5074 output_addr_const (file
, XVECEXP (x
, 0, 0));
5075 fprintf (file
, "@GOTOFF");
5078 output_addr_const (file
, XVECEXP (x
, 0, 0));
5079 fprintf (file
, "@PLT");
5082 output_addr_const (file
, XVECEXP (x
, 0, 0));
5083 fprintf (file
, "@PLTOFF");
5086 output_addr_const (file
, XVECEXP (x
, 0, 0));
5087 fprintf (file
, "@TLSGD");
5090 assemble_name (file
, get_some_local_dynamic_name ());
5091 fprintf (file
, "@TLSLDM");
5094 output_addr_const (file
, XVECEXP (x
, 0, 0));
5095 fprintf (file
, "@DTPOFF");
5098 output_addr_const (file
, XVECEXP (x
, 0, 0));
5099 fprintf (file
, "@NTPOFF");
5101 case UNSPEC_GOTNTPOFF
:
5102 output_addr_const (file
, XVECEXP (x
, 0, 0));
5103 fprintf (file
, "@GOTNTPOFF");
5105 case UNSPEC_INDNTPOFF
:
5106 output_addr_const (file
, XVECEXP (x
, 0, 0));
5107 fprintf (file
, "@INDNTPOFF");
5111 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 2)
5112 switch (XINT (x
, 1))
5114 case UNSPEC_POOL_OFFSET
:
5115 x
= gen_rtx_MINUS (GET_MODE (x
), XVECEXP (x
, 0, 0), XVECEXP (x
, 0, 1));
5116 output_addr_const (file
, x
);
5122 /* Output address operand ADDR in assembler syntax to
5123 stdio stream FILE. */
5126 print_operand_address (FILE *file
, rtx addr
)
5128 struct s390_address ad
;
5130 if (s390_symref_operand_p (addr
, NULL
, NULL
))
5134 output_operand_lossage ("symbolic memory references are "
5135 "only supported on z10 or later");
5138 output_addr_const (file
, addr
);
5142 if (!s390_decompose_address (addr
, &ad
)
5143 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
5144 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
5145 output_operand_lossage ("cannot decompose address");
5148 output_addr_const (file
, ad
.disp
);
5150 fprintf (file
, "0");
5152 if (ad
.base
&& ad
.indx
)
5153 fprintf (file
, "(%s,%s)", reg_names
[REGNO (ad
.indx
)],
5154 reg_names
[REGNO (ad
.base
)]);
5156 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
5159 /* Output operand X in assembler syntax to stdio stream FILE.
5160 CODE specified the format flag. The following format flags
5163 'C': print opcode suffix for branch condition.
5164 'D': print opcode suffix for inverse branch condition.
5165 'E': print opcode suffix for branch on index instruction.
5166 'J': print tls_load/tls_gdcall/tls_ldcall suffix
5167 'G': print the size of the operand in bytes.
5168 'O': print only the displacement of a memory reference.
5169 'R': print only the base register of a memory reference.
5170 'S': print S-type memory reference (base+displacement).
5171 'N': print the second word of a DImode operand.
5172 'M': print the second word of a TImode operand.
5173 'Y': print shift count operand.
5175 'b': print integer X as if it's an unsigned byte.
5176 'c': print integer X as if it's an signed byte.
5177 'x': print integer X as if it's an unsigned halfword.
5178 'h': print integer X as if it's a signed halfword.
5179 'i': print the first nonzero HImode part of X.
5180 'j': print the first HImode part unequal to -1 of X.
5181 'k': print the first nonzero SImode part of X.
5182 'm': print the first SImode part unequal to -1 of X.
5183 'o': print integer X as if it's an unsigned 32bit word. */
5186 print_operand (FILE *file
, rtx x
, int code
)
5191 fprintf (file
, s390_branch_condition_mnemonic (x
, FALSE
));
5195 fprintf (file
, s390_branch_condition_mnemonic (x
, TRUE
));
5199 if (GET_CODE (x
) == LE
)
5200 fprintf (file
, "l");
5201 else if (GET_CODE (x
) == GT
)
5202 fprintf (file
, "h");
5204 output_operand_lossage ("invalid comparison operator "
5205 "for 'E' output modifier");
5209 if (GET_CODE (x
) == SYMBOL_REF
)
5211 fprintf (file
, "%s", ":tls_load:");
5212 output_addr_const (file
, x
);
5214 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD
)
5216 fprintf (file
, "%s", ":tls_gdcall:");
5217 output_addr_const (file
, XVECEXP (x
, 0, 0));
5219 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM
)
5221 fprintf (file
, "%s", ":tls_ldcall:");
5222 assemble_name (file
, get_some_local_dynamic_name ());
5225 output_operand_lossage ("invalid reference for 'J' output modifier");
5229 fprintf (file
, "%u", GET_MODE_SIZE (GET_MODE (x
)));
5234 struct s390_address ad
;
5239 output_operand_lossage ("memory reference expected for "
5240 "'O' output modifier");
5244 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5247 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
5250 output_operand_lossage ("invalid address for 'O' output modifier");
5255 output_addr_const (file
, ad
.disp
);
5257 fprintf (file
, "0");
5263 struct s390_address ad
;
5268 output_operand_lossage ("memory reference expected for "
5269 "'R' output modifier");
5273 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5276 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
5279 output_operand_lossage ("invalid address for 'R' output modifier");
5284 fprintf (file
, "%s", reg_names
[REGNO (ad
.base
)]);
5286 fprintf (file
, "0");
5292 struct s390_address ad
;
5297 output_operand_lossage ("memory reference expected for "
5298 "'S' output modifier");
5301 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5304 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
5307 output_operand_lossage ("invalid address for 'S' output modifier");
5312 output_addr_const (file
, ad
.disp
);
5314 fprintf (file
, "0");
5317 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
5322 if (GET_CODE (x
) == REG
)
5323 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
5324 else if (GET_CODE (x
) == MEM
)
5325 x
= change_address (x
, VOIDmode
, plus_constant (XEXP (x
, 0), 4));
5327 output_operand_lossage ("register or memory expression expected "
5328 "for 'N' output modifier");
5332 if (GET_CODE (x
) == REG
)
5333 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
5334 else if (GET_CODE (x
) == MEM
)
5335 x
= change_address (x
, VOIDmode
, plus_constant (XEXP (x
, 0), 8));
5337 output_operand_lossage ("register or memory expression expected "
5338 "for 'M' output modifier");
5342 print_shift_count_operand (file
, x
);
5346 switch (GET_CODE (x
))
5349 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5353 output_address (XEXP (x
, 0));
5360 output_addr_const (file
, x
);
5365 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xff);
5366 else if (code
== 'c')
5367 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ((INTVAL (x
) & 0xff) ^ 0x80) - 0x80);
5368 else if (code
== 'x')
5369 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffff);
5370 else if (code
== 'h')
5371 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ((INTVAL (x
) & 0xffff) ^ 0x8000) - 0x8000);
5372 else if (code
== 'i')
5373 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5374 s390_extract_part (x
, HImode
, 0));
5375 else if (code
== 'j')
5376 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5377 s390_extract_part (x
, HImode
, -1));
5378 else if (code
== 'k')
5379 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5380 s390_extract_part (x
, SImode
, 0));
5381 else if (code
== 'm')
5382 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5383 s390_extract_part (x
, SImode
, -1));
5384 else if (code
== 'o')
5385 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffffffff);
5387 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
5391 gcc_assert (GET_MODE (x
) == VOIDmode
);
5393 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
) & 0xff);
5394 else if (code
== 'x')
5395 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
) & 0xffff);
5396 else if (code
== 'h')
5397 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5398 ((CONST_DOUBLE_LOW (x
) & 0xffff) ^ 0x8000) - 0x8000);
5402 output_operand_lossage ("invalid constant - try using "
5403 "an output modifier");
5405 output_operand_lossage ("invalid constant for output modifier '%c'",
5412 output_operand_lossage ("invalid expression - try using "
5413 "an output modifier");
5415 output_operand_lossage ("invalid expression for output "
5416 "modifier '%c'", code
);
5421 /* Target hook for assembling integer objects. We need to define it
5422 here to work a round a bug in some versions of GAS, which couldn't
5423 handle values smaller than INT_MIN when printed in decimal. */
5426 s390_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
5428 if (size
== 8 && aligned_p
5429 && GET_CODE (x
) == CONST_INT
&& INTVAL (x
) < INT_MIN
)
5431 fprintf (asm_out_file
, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX
"\n",
5435 return default_assemble_integer (x
, size
, aligned_p
);
5438 /* Returns true if register REGNO is used for forming
5439 a memory address in expression X. */
5442 reg_used_in_mem_p (int regno
, rtx x
)
5444 enum rtx_code code
= GET_CODE (x
);
5450 if (refers_to_regno_p (regno
, regno
+1,
5454 else if (code
== SET
5455 && GET_CODE (SET_DEST (x
)) == PC
)
5457 if (refers_to_regno_p (regno
, regno
+1,
5462 fmt
= GET_RTX_FORMAT (code
);
5463 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5466 && reg_used_in_mem_p (regno
, XEXP (x
, i
)))
5469 else if (fmt
[i
] == 'E')
5470 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
5471 if (reg_used_in_mem_p (regno
, XVECEXP (x
, i
, j
)))
5477 /* Returns true if expression DEP_RTX sets an address register
5478 used by instruction INSN to address memory. */
5481 addr_generation_dependency_p (rtx dep_rtx
, rtx insn
)
5485 if (GET_CODE (dep_rtx
) == INSN
)
5486 dep_rtx
= PATTERN (dep_rtx
);
5488 if (GET_CODE (dep_rtx
) == SET
)
5490 target
= SET_DEST (dep_rtx
);
5491 if (GET_CODE (target
) == STRICT_LOW_PART
)
5492 target
= XEXP (target
, 0);
5493 while (GET_CODE (target
) == SUBREG
)
5494 target
= SUBREG_REG (target
);
5496 if (GET_CODE (target
) == REG
)
5498 int regno
= REGNO (target
);
5500 if (s390_safe_attr_type (insn
) == TYPE_LA
)
5502 pat
= PATTERN (insn
);
5503 if (GET_CODE (pat
) == PARALLEL
)
5505 gcc_assert (XVECLEN (pat
, 0) == 2);
5506 pat
= XVECEXP (pat
, 0, 0);
5508 gcc_assert (GET_CODE (pat
) == SET
);
5509 return refers_to_regno_p (regno
, regno
+1, SET_SRC (pat
), 0);
5511 else if (get_attr_atype (insn
) == ATYPE_AGEN
)
5512 return reg_used_in_mem_p (regno
, PATTERN (insn
));
5518 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5521 s390_agen_dep_p (rtx dep_insn
, rtx insn
)
5523 rtx dep_rtx
= PATTERN (dep_insn
);
5526 if (GET_CODE (dep_rtx
) == SET
5527 && addr_generation_dependency_p (dep_rtx
, insn
))
5529 else if (GET_CODE (dep_rtx
) == PARALLEL
)
5531 for (i
= 0; i
< XVECLEN (dep_rtx
, 0); i
++)
5533 if (addr_generation_dependency_p (XVECEXP (dep_rtx
, 0, i
), insn
))
5541 /* A C statement (sans semicolon) to update the integer scheduling priority
5542 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5543 reduce the priority to execute INSN later. Do not define this macro if
5544 you do not need to adjust the scheduling priorities of insns.
5546 A STD instruction should be scheduled earlier,
5547 in order to use the bypass. */
5549 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
5551 if (! INSN_P (insn
))
5554 if (s390_tune
!= PROCESSOR_2084_Z990
5555 && s390_tune
!= PROCESSOR_2094_Z9_109
5556 && s390_tune
!= PROCESSOR_2097_Z10
5557 && s390_tune
!= PROCESSOR_2817_Z196
)
5560 switch (s390_safe_attr_type (insn
))
5564 priority
= priority
<< 3;
5568 priority
= priority
<< 1;
5577 /* The number of instructions that can be issued per cycle. */
5580 s390_issue_rate (void)
5584 case PROCESSOR_2084_Z990
:
5585 case PROCESSOR_2094_Z9_109
:
5586 case PROCESSOR_2817_Z196
:
5588 case PROCESSOR_2097_Z10
:
5596 s390_first_cycle_multipass_dfa_lookahead (void)
5601 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5602 Fix up MEMs as required. */
5605 annotate_constant_pool_refs (rtx
*x
)
5610 gcc_assert (GET_CODE (*x
) != SYMBOL_REF
5611 || !CONSTANT_POOL_ADDRESS_P (*x
));
5613 /* Literal pool references can only occur inside a MEM ... */
5614 if (GET_CODE (*x
) == MEM
)
5616 rtx memref
= XEXP (*x
, 0);
5618 if (GET_CODE (memref
) == SYMBOL_REF
5619 && CONSTANT_POOL_ADDRESS_P (memref
))
5621 rtx base
= cfun
->machine
->base_reg
;
5622 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, memref
, base
),
5625 *x
= replace_equiv_address (*x
, addr
);
5629 if (GET_CODE (memref
) == CONST
5630 && GET_CODE (XEXP (memref
, 0)) == PLUS
5631 && GET_CODE (XEXP (XEXP (memref
, 0), 1)) == CONST_INT
5632 && GET_CODE (XEXP (XEXP (memref
, 0), 0)) == SYMBOL_REF
5633 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref
, 0), 0)))
5635 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (memref
, 0), 1));
5636 rtx sym
= XEXP (XEXP (memref
, 0), 0);
5637 rtx base
= cfun
->machine
->base_reg
;
5638 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
5641 *x
= replace_equiv_address (*x
, plus_constant (addr
, off
));
5646 /* ... or a load-address type pattern. */
5647 if (GET_CODE (*x
) == SET
)
5649 rtx addrref
= SET_SRC (*x
);
5651 if (GET_CODE (addrref
) == SYMBOL_REF
5652 && CONSTANT_POOL_ADDRESS_P (addrref
))
5654 rtx base
= cfun
->machine
->base_reg
;
5655 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, addrref
, base
),
5658 SET_SRC (*x
) = addr
;
5662 if (GET_CODE (addrref
) == CONST
5663 && GET_CODE (XEXP (addrref
, 0)) == PLUS
5664 && GET_CODE (XEXP (XEXP (addrref
, 0), 1)) == CONST_INT
5665 && GET_CODE (XEXP (XEXP (addrref
, 0), 0)) == SYMBOL_REF
5666 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref
, 0), 0)))
5668 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (addrref
, 0), 1));
5669 rtx sym
= XEXP (XEXP (addrref
, 0), 0);
5670 rtx base
= cfun
->machine
->base_reg
;
5671 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
5674 SET_SRC (*x
) = plus_constant (addr
, off
);
5679 /* Annotate LTREL_BASE as well. */
5680 if (GET_CODE (*x
) == UNSPEC
5681 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
5683 rtx base
= cfun
->machine
->base_reg
;
5684 *x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XVECEXP (*x
, 0, 0), base
),
5689 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5690 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5694 annotate_constant_pool_refs (&XEXP (*x
, i
));
5696 else if (fmt
[i
] == 'E')
5698 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
5699 annotate_constant_pool_refs (&XVECEXP (*x
, i
, j
));
5704 /* Split all branches that exceed the maximum distance.
5705 Returns true if this created a new literal pool entry. */
5708 s390_split_branches (void)
5710 rtx temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
5711 int new_literal
= 0, ret
;
5712 rtx insn
, pat
, tmp
, target
;
5715 /* We need correct insn addresses. */
5717 shorten_branches (get_insns ());
5719 /* Find all branches that exceed 64KB, and split them. */
5721 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5723 if (GET_CODE (insn
) != JUMP_INSN
)
5726 pat
= PATTERN (insn
);
5727 if (GET_CODE (pat
) == PARALLEL
&& XVECLEN (pat
, 0) > 2)
5728 pat
= XVECEXP (pat
, 0, 0);
5729 if (GET_CODE (pat
) != SET
|| SET_DEST (pat
) != pc_rtx
)
5732 if (GET_CODE (SET_SRC (pat
)) == LABEL_REF
)
5734 label
= &SET_SRC (pat
);
5736 else if (GET_CODE (SET_SRC (pat
)) == IF_THEN_ELSE
)
5738 if (GET_CODE (XEXP (SET_SRC (pat
), 1)) == LABEL_REF
)
5739 label
= &XEXP (SET_SRC (pat
), 1);
5740 else if (GET_CODE (XEXP (SET_SRC (pat
), 2)) == LABEL_REF
)
5741 label
= &XEXP (SET_SRC (pat
), 2);
5748 if (get_attr_length (insn
) <= 4)
5751 /* We are going to use the return register as scratch register,
5752 make sure it will be saved/restored by the prologue/epilogue. */
5753 cfun_frame_layout
.save_return_addr_p
= 1;
5758 tmp
= force_const_mem (Pmode
, *label
);
5759 tmp
= emit_insn_before (gen_rtx_SET (Pmode
, temp_reg
, tmp
), insn
);
5760 INSN_ADDRESSES_NEW (tmp
, -1);
5761 annotate_constant_pool_refs (&PATTERN (tmp
));
5768 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, *label
),
5769 UNSPEC_LTREL_OFFSET
);
5770 target
= gen_rtx_CONST (Pmode
, target
);
5771 target
= force_const_mem (Pmode
, target
);
5772 tmp
= emit_insn_before (gen_rtx_SET (Pmode
, temp_reg
, target
), insn
);
5773 INSN_ADDRESSES_NEW (tmp
, -1);
5774 annotate_constant_pool_refs (&PATTERN (tmp
));
5776 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XEXP (target
, 0),
5777 cfun
->machine
->base_reg
),
5779 target
= gen_rtx_PLUS (Pmode
, temp_reg
, target
);
5782 ret
= validate_change (insn
, label
, target
, 0);
5790 /* Find an annotated literal pool symbol referenced in RTX X,
5791 and store it at REF. Will abort if X contains references to
5792 more than one such pool symbol; multiple references to the same
5793 symbol are allowed, however.
5795 The rtx pointed to by REF must be initialized to NULL_RTX
5796 by the caller before calling this routine. */
5799 find_constant_pool_ref (rtx x
, rtx
*ref
)
5804 /* Ignore LTREL_BASE references. */
5805 if (GET_CODE (x
) == UNSPEC
5806 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
5808 /* Likewise POOL_ENTRY insns. */
5809 if (GET_CODE (x
) == UNSPEC_VOLATILE
5810 && XINT (x
, 1) == UNSPECV_POOL_ENTRY
)
5813 gcc_assert (GET_CODE (x
) != SYMBOL_REF
5814 || !CONSTANT_POOL_ADDRESS_P (x
));
5816 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_LTREF
)
5818 rtx sym
= XVECEXP (x
, 0, 0);
5819 gcc_assert (GET_CODE (sym
) == SYMBOL_REF
5820 && CONSTANT_POOL_ADDRESS_P (sym
));
5822 if (*ref
== NULL_RTX
)
5825 gcc_assert (*ref
== sym
);
5830 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5831 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5835 find_constant_pool_ref (XEXP (x
, i
), ref
);
5837 else if (fmt
[i
] == 'E')
5839 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
5840 find_constant_pool_ref (XVECEXP (x
, i
, j
), ref
);
5845 /* Replace every reference to the annotated literal pool
5846 symbol REF in X by its base plus OFFSET. */
5849 replace_constant_pool_ref (rtx
*x
, rtx ref
, rtx offset
)
5854 gcc_assert (*x
!= ref
);
5856 if (GET_CODE (*x
) == UNSPEC
5857 && XINT (*x
, 1) == UNSPEC_LTREF
5858 && XVECEXP (*x
, 0, 0) == ref
)
5860 *x
= gen_rtx_PLUS (Pmode
, XVECEXP (*x
, 0, 1), offset
);
5864 if (GET_CODE (*x
) == PLUS
5865 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
5866 && GET_CODE (XEXP (*x
, 0)) == UNSPEC
5867 && XINT (XEXP (*x
, 0), 1) == UNSPEC_LTREF
5868 && XVECEXP (XEXP (*x
, 0), 0, 0) == ref
)
5870 rtx addr
= gen_rtx_PLUS (Pmode
, XVECEXP (XEXP (*x
, 0), 0, 1), offset
);
5871 *x
= plus_constant (addr
, INTVAL (XEXP (*x
, 1)));
5875 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5876 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5880 replace_constant_pool_ref (&XEXP (*x
, i
), ref
, offset
);
5882 else if (fmt
[i
] == 'E')
5884 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
5885 replace_constant_pool_ref (&XVECEXP (*x
, i
, j
), ref
, offset
);
5890 /* Check whether X contains an UNSPEC_LTREL_BASE.
5891 Return its constant pool symbol if found, NULL_RTX otherwise. */
5894 find_ltrel_base (rtx x
)
5899 if (GET_CODE (x
) == UNSPEC
5900 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
5901 return XVECEXP (x
, 0, 0);
5903 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5904 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5908 rtx fnd
= find_ltrel_base (XEXP (x
, i
));
5912 else if (fmt
[i
] == 'E')
5914 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
5916 rtx fnd
= find_ltrel_base (XVECEXP (x
, i
, j
));
5926 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5929 replace_ltrel_base (rtx
*x
)
5934 if (GET_CODE (*x
) == UNSPEC
5935 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
5937 *x
= XVECEXP (*x
, 0, 1);
5941 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5942 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5946 replace_ltrel_base (&XEXP (*x
, i
));
5948 else if (fmt
[i
] == 'E')
5950 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
5951 replace_ltrel_base (&XVECEXP (*x
, i
, j
));
5957 /* We keep a list of constants which we have to add to internal
5958 constant tables in the middle of large functions. */
5960 #define NR_C_MODES 11
5961 enum machine_mode constant_modes
[NR_C_MODES
] =
5963 TFmode
, TImode
, TDmode
,
5964 DFmode
, DImode
, DDmode
,
5965 SFmode
, SImode
, SDmode
,
5972 struct constant
*next
;
5977 struct constant_pool
5979 struct constant_pool
*next
;
5983 rtx emit_pool_after
;
5985 struct constant
*constants
[NR_C_MODES
];
5986 struct constant
*execute
;
5991 /* Allocate new constant_pool structure. */
5993 static struct constant_pool
*
5994 s390_alloc_pool (void)
5996 struct constant_pool
*pool
;
5999 pool
= (struct constant_pool
*) xmalloc (sizeof *pool
);
6001 for (i
= 0; i
< NR_C_MODES
; i
++)
6002 pool
->constants
[i
] = NULL
;
6004 pool
->execute
= NULL
;
6005 pool
->label
= gen_label_rtx ();
6006 pool
->first_insn
= NULL_RTX
;
6007 pool
->pool_insn
= NULL_RTX
;
6008 pool
->insns
= BITMAP_ALLOC (NULL
);
6010 pool
->emit_pool_after
= NULL_RTX
;
6015 /* Create new constant pool covering instructions starting at INSN
6016 and chain it to the end of POOL_LIST. */
6018 static struct constant_pool
*
6019 s390_start_pool (struct constant_pool
**pool_list
, rtx insn
)
6021 struct constant_pool
*pool
, **prev
;
6023 pool
= s390_alloc_pool ();
6024 pool
->first_insn
= insn
;
6026 for (prev
= pool_list
; *prev
; prev
= &(*prev
)->next
)
6033 /* End range of instructions covered by POOL at INSN and emit
6034 placeholder insn representing the pool. */
6037 s390_end_pool (struct constant_pool
*pool
, rtx insn
)
6039 rtx pool_size
= GEN_INT (pool
->size
+ 8 /* alignment slop */);
6042 insn
= get_last_insn ();
6044 pool
->pool_insn
= emit_insn_after (gen_pool (pool_size
), insn
);
6045 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6048 /* Add INSN to the list of insns covered by POOL. */
6051 s390_add_pool_insn (struct constant_pool
*pool
, rtx insn
)
6053 bitmap_set_bit (pool
->insns
, INSN_UID (insn
));
6056 /* Return pool out of POOL_LIST that covers INSN. */
6058 static struct constant_pool
*
6059 s390_find_pool (struct constant_pool
*pool_list
, rtx insn
)
6061 struct constant_pool
*pool
;
6063 for (pool
= pool_list
; pool
; pool
= pool
->next
)
6064 if (bitmap_bit_p (pool
->insns
, INSN_UID (insn
)))
6070 /* Add constant VAL of mode MODE to the constant pool POOL. */
6073 s390_add_constant (struct constant_pool
*pool
, rtx val
, enum machine_mode mode
)
6078 for (i
= 0; i
< NR_C_MODES
; i
++)
6079 if (constant_modes
[i
] == mode
)
6081 gcc_assert (i
!= NR_C_MODES
);
6083 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
6084 if (rtx_equal_p (val
, c
->value
))
6089 c
= (struct constant
*) xmalloc (sizeof *c
);
6091 c
->label
= gen_label_rtx ();
6092 c
->next
= pool
->constants
[i
];
6093 pool
->constants
[i
] = c
;
6094 pool
->size
+= GET_MODE_SIZE (mode
);
6098 /* Return an rtx that represents the offset of X from the start of
6102 s390_pool_offset (struct constant_pool
*pool
, rtx x
)
6106 label
= gen_rtx_LABEL_REF (GET_MODE (x
), pool
->label
);
6107 x
= gen_rtx_UNSPEC (GET_MODE (x
), gen_rtvec (2, x
, label
),
6108 UNSPEC_POOL_OFFSET
);
6109 return gen_rtx_CONST (GET_MODE (x
), x
);
6112 /* Find constant VAL of mode MODE in the constant pool POOL.
6113 Return an RTX describing the distance from the start of
6114 the pool to the location of the new constant. */
6117 s390_find_constant (struct constant_pool
*pool
, rtx val
,
6118 enum machine_mode mode
)
6123 for (i
= 0; i
< NR_C_MODES
; i
++)
6124 if (constant_modes
[i
] == mode
)
6126 gcc_assert (i
!= NR_C_MODES
);
6128 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
6129 if (rtx_equal_p (val
, c
->value
))
6134 return s390_pool_offset (pool
, gen_rtx_LABEL_REF (Pmode
, c
->label
));
6137 /* Check whether INSN is an execute. Return the label_ref to its
6138 execute target template if so, NULL_RTX otherwise. */
6141 s390_execute_label (rtx insn
)
6143 if (GET_CODE (insn
) == INSN
6144 && GET_CODE (PATTERN (insn
)) == PARALLEL
6145 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == UNSPEC
6146 && XINT (XVECEXP (PATTERN (insn
), 0, 0), 1) == UNSPEC_EXECUTE
)
6147 return XVECEXP (XVECEXP (PATTERN (insn
), 0, 0), 0, 2);
6152 /* Add execute target for INSN to the constant pool POOL. */
6155 s390_add_execute (struct constant_pool
*pool
, rtx insn
)
6159 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
6160 if (INSN_UID (insn
) == INSN_UID (c
->value
))
6165 c
= (struct constant
*) xmalloc (sizeof *c
);
6167 c
->label
= gen_label_rtx ();
6168 c
->next
= pool
->execute
;
6174 /* Find execute target for INSN in the constant pool POOL.
6175 Return an RTX describing the distance from the start of
6176 the pool to the location of the execute target. */
6179 s390_find_execute (struct constant_pool
*pool
, rtx insn
)
6183 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
6184 if (INSN_UID (insn
) == INSN_UID (c
->value
))
6189 return s390_pool_offset (pool
, gen_rtx_LABEL_REF (Pmode
, c
->label
));
6192 /* For an execute INSN, extract the execute target template. */
6195 s390_execute_target (rtx insn
)
6197 rtx pattern
= PATTERN (insn
);
6198 gcc_assert (s390_execute_label (insn
));
6200 if (XVECLEN (pattern
, 0) == 2)
6202 pattern
= copy_rtx (XVECEXP (pattern
, 0, 1));
6206 rtvec vec
= rtvec_alloc (XVECLEN (pattern
, 0) - 1);
6209 for (i
= 0; i
< XVECLEN (pattern
, 0) - 1; i
++)
6210 RTVEC_ELT (vec
, i
) = copy_rtx (XVECEXP (pattern
, 0, i
+ 1));
6212 pattern
= gen_rtx_PARALLEL (VOIDmode
, vec
);
6218 /* Indicate that INSN cannot be duplicated. This is the case for
6219 execute insns that carry a unique label. */
6222 s390_cannot_copy_insn_p (rtx insn
)
6224 rtx label
= s390_execute_label (insn
);
6225 return label
&& label
!= const0_rtx
;
6228 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
6229 do not emit the pool base label. */
6232 s390_dump_pool (struct constant_pool
*pool
, bool remote_label
)
6235 rtx insn
= pool
->pool_insn
;
6238 /* Switch to rodata section. */
6239 if (TARGET_CPU_ZARCH
)
6241 insn
= emit_insn_after (gen_pool_section_start (), insn
);
6242 INSN_ADDRESSES_NEW (insn
, -1);
6245 /* Ensure minimum pool alignment. */
6246 if (TARGET_CPU_ZARCH
)
6247 insn
= emit_insn_after (gen_pool_align (GEN_INT (8)), insn
);
6249 insn
= emit_insn_after (gen_pool_align (GEN_INT (4)), insn
);
6250 INSN_ADDRESSES_NEW (insn
, -1);
6252 /* Emit pool base label. */
6255 insn
= emit_label_after (pool
->label
, insn
);
6256 INSN_ADDRESSES_NEW (insn
, -1);
6259 /* Dump constants in descending alignment requirement order,
6260 ensuring proper alignment for every constant. */
6261 for (i
= 0; i
< NR_C_MODES
; i
++)
6262 for (c
= pool
->constants
[i
]; c
; c
= c
->next
)
6264 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6265 rtx value
= copy_rtx (c
->value
);
6266 if (GET_CODE (value
) == CONST
6267 && GET_CODE (XEXP (value
, 0)) == UNSPEC
6268 && XINT (XEXP (value
, 0), 1) == UNSPEC_LTREL_OFFSET
6269 && XVECLEN (XEXP (value
, 0), 0) == 1)
6270 value
= s390_pool_offset (pool
, XVECEXP (XEXP (value
, 0), 0, 0));
6272 insn
= emit_label_after (c
->label
, insn
);
6273 INSN_ADDRESSES_NEW (insn
, -1);
6275 value
= gen_rtx_UNSPEC_VOLATILE (constant_modes
[i
],
6276 gen_rtvec (1, value
),
6277 UNSPECV_POOL_ENTRY
);
6278 insn
= emit_insn_after (value
, insn
);
6279 INSN_ADDRESSES_NEW (insn
, -1);
6282 /* Ensure minimum alignment for instructions. */
6283 insn
= emit_insn_after (gen_pool_align (GEN_INT (2)), insn
);
6284 INSN_ADDRESSES_NEW (insn
, -1);
6286 /* Output in-pool execute template insns. */
6287 for (c
= pool
->execute
; c
; c
= c
->next
)
6289 insn
= emit_label_after (c
->label
, insn
);
6290 INSN_ADDRESSES_NEW (insn
, -1);
6292 insn
= emit_insn_after (s390_execute_target (c
->value
), insn
);
6293 INSN_ADDRESSES_NEW (insn
, -1);
6296 /* Switch back to previous section. */
6297 if (TARGET_CPU_ZARCH
)
6299 insn
= emit_insn_after (gen_pool_section_end (), insn
);
6300 INSN_ADDRESSES_NEW (insn
, -1);
6303 insn
= emit_barrier_after (insn
);
6304 INSN_ADDRESSES_NEW (insn
, -1);
6306 /* Remove placeholder insn. */
6307 remove_insn (pool
->pool_insn
);
6310 /* Free all memory used by POOL. */
6313 s390_free_pool (struct constant_pool
*pool
)
6315 struct constant
*c
, *next
;
6318 for (i
= 0; i
< NR_C_MODES
; i
++)
6319 for (c
= pool
->constants
[i
]; c
; c
= next
)
6325 for (c
= pool
->execute
; c
; c
= next
)
6331 BITMAP_FREE (pool
->insns
);
6336 /* Collect main literal pool. Return NULL on overflow. */
6338 static struct constant_pool
*
6339 s390_mainpool_start (void)
6341 struct constant_pool
*pool
;
6344 pool
= s390_alloc_pool ();
6346 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6348 if (GET_CODE (insn
) == INSN
6349 && GET_CODE (PATTERN (insn
)) == SET
6350 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC_VOLATILE
6351 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPECV_MAIN_POOL
)
6353 gcc_assert (!pool
->pool_insn
);
6354 pool
->pool_insn
= insn
;
6357 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
6359 s390_add_execute (pool
, insn
);
6361 else if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6363 rtx pool_ref
= NULL_RTX
;
6364 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6367 rtx constant
= get_pool_constant (pool_ref
);
6368 enum machine_mode mode
= get_pool_mode (pool_ref
);
6369 s390_add_constant (pool
, constant
, mode
);
6373 /* If hot/cold partitioning is enabled we have to make sure that
6374 the literal pool is emitted in the same section where the
6375 initialization of the literal pool base pointer takes place.
6376 emit_pool_after is only used in the non-overflow case on non
6377 Z cpus where we can emit the literal pool at the end of the
6378 function body within the text section. */
6380 && NOTE_KIND (insn
) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6381 && !pool
->emit_pool_after
)
6382 pool
->emit_pool_after
= PREV_INSN (insn
);
6385 gcc_assert (pool
->pool_insn
|| pool
->size
== 0);
6387 if (pool
->size
>= 4096)
6389 /* We're going to chunkify the pool, so remove the main
6390 pool placeholder insn. */
6391 remove_insn (pool
->pool_insn
);
6393 s390_free_pool (pool
);
6397 /* If the functions ends with the section where the literal pool
6398 should be emitted set the marker to its end. */
6399 if (pool
&& !pool
->emit_pool_after
)
6400 pool
->emit_pool_after
= get_last_insn ();
6405 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6406 Modify the current function to output the pool constants as well as
6407 the pool register setup instruction. */
6410 s390_mainpool_finish (struct constant_pool
*pool
)
6412 rtx base_reg
= cfun
->machine
->base_reg
;
6415 /* If the pool is empty, we're done. */
6416 if (pool
->size
== 0)
6418 /* We don't actually need a base register after all. */
6419 cfun
->machine
->base_reg
= NULL_RTX
;
6421 if (pool
->pool_insn
)
6422 remove_insn (pool
->pool_insn
);
6423 s390_free_pool (pool
);
6427 /* We need correct insn addresses. */
6428 shorten_branches (get_insns ());
6430 /* On zSeries, we use a LARL to load the pool register. The pool is
6431 located in the .rodata section, so we emit it after the function. */
6432 if (TARGET_CPU_ZARCH
)
6434 insn
= gen_main_base_64 (base_reg
, pool
->label
);
6435 insn
= emit_insn_after (insn
, pool
->pool_insn
);
6436 INSN_ADDRESSES_NEW (insn
, -1);
6437 remove_insn (pool
->pool_insn
);
6439 insn
= get_last_insn ();
6440 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6441 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6443 s390_dump_pool (pool
, 0);
6446 /* On S/390, if the total size of the function's code plus literal pool
6447 does not exceed 4096 bytes, we use BASR to set up a function base
6448 pointer, and emit the literal pool at the end of the function. */
6449 else if (INSN_ADDRESSES (INSN_UID (pool
->emit_pool_after
))
6450 + pool
->size
+ 8 /* alignment slop */ < 4096)
6452 insn
= gen_main_base_31_small (base_reg
, pool
->label
);
6453 insn
= emit_insn_after (insn
, pool
->pool_insn
);
6454 INSN_ADDRESSES_NEW (insn
, -1);
6455 remove_insn (pool
->pool_insn
);
6457 insn
= emit_label_after (pool
->label
, insn
);
6458 INSN_ADDRESSES_NEW (insn
, -1);
6460 /* emit_pool_after will be set by s390_mainpool_start to the
6461 last insn of the section where the literal pool should be
6463 insn
= pool
->emit_pool_after
;
6465 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6466 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6468 s390_dump_pool (pool
, 1);
6471 /* Otherwise, we emit an inline literal pool and use BASR to branch
6472 over it, setting up the pool register at the same time. */
6475 rtx pool_end
= gen_label_rtx ();
6477 insn
= gen_main_base_31_large (base_reg
, pool
->label
, pool_end
);
6478 insn
= emit_insn_after (insn
, pool
->pool_insn
);
6479 INSN_ADDRESSES_NEW (insn
, -1);
6480 remove_insn (pool
->pool_insn
);
6482 insn
= emit_label_after (pool
->label
, insn
);
6483 INSN_ADDRESSES_NEW (insn
, -1);
6485 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6486 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6488 insn
= emit_label_after (pool_end
, pool
->pool_insn
);
6489 INSN_ADDRESSES_NEW (insn
, -1);
6491 s390_dump_pool (pool
, 1);
6495 /* Replace all literal pool references. */
6497 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6500 replace_ltrel_base (&PATTERN (insn
));
6502 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6504 rtx addr
, pool_ref
= NULL_RTX
;
6505 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6508 if (s390_execute_label (insn
))
6509 addr
= s390_find_execute (pool
, insn
);
6511 addr
= s390_find_constant (pool
, get_pool_constant (pool_ref
),
6512 get_pool_mode (pool_ref
));
6514 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
6515 INSN_CODE (insn
) = -1;
6521 /* Free the pool. */
6522 s390_free_pool (pool
);
6525 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6526 We have decided we cannot use this pool, so revert all changes
6527 to the current function that were done by s390_mainpool_start. */
6529 s390_mainpool_cancel (struct constant_pool
*pool
)
6531 /* We didn't actually change the instruction stream, so simply
6532 free the pool memory. */
6533 s390_free_pool (pool
);
6537 /* Chunkify the literal pool. */
6539 #define S390_POOL_CHUNK_MIN 0xc00
6540 #define S390_POOL_CHUNK_MAX 0xe00
6542 static struct constant_pool
*
6543 s390_chunkify_start (void)
6545 struct constant_pool
*curr_pool
= NULL
, *pool_list
= NULL
;
6548 rtx pending_ltrel
= NULL_RTX
;
6551 rtx (*gen_reload_base
) (rtx
, rtx
) =
6552 TARGET_CPU_ZARCH
? gen_reload_base_64
: gen_reload_base_31
;
6555 /* We need correct insn addresses. */
6557 shorten_branches (get_insns ());
6559 /* Scan all insns and move literals to pool chunks. */
6561 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6563 bool section_switch_p
= false;
6565 /* Check for pending LTREL_BASE. */
6568 rtx ltrel_base
= find_ltrel_base (PATTERN (insn
));
6571 gcc_assert (ltrel_base
== pending_ltrel
);
6572 pending_ltrel
= NULL_RTX
;
6576 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
6579 curr_pool
= s390_start_pool (&pool_list
, insn
);
6581 s390_add_execute (curr_pool
, insn
);
6582 s390_add_pool_insn (curr_pool
, insn
);
6584 else if (GET_CODE (insn
) == INSN
|| CALL_P (insn
))
6586 rtx pool_ref
= NULL_RTX
;
6587 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6590 rtx constant
= get_pool_constant (pool_ref
);
6591 enum machine_mode mode
= get_pool_mode (pool_ref
);
6594 curr_pool
= s390_start_pool (&pool_list
, insn
);
6596 s390_add_constant (curr_pool
, constant
, mode
);
6597 s390_add_pool_insn (curr_pool
, insn
);
6599 /* Don't split the pool chunk between a LTREL_OFFSET load
6600 and the corresponding LTREL_BASE. */
6601 if (GET_CODE (constant
) == CONST
6602 && GET_CODE (XEXP (constant
, 0)) == UNSPEC
6603 && XINT (XEXP (constant
, 0), 1) == UNSPEC_LTREL_OFFSET
)
6605 gcc_assert (!pending_ltrel
);
6606 pending_ltrel
= pool_ref
;
6609 /* Make sure we do not split between a call and its
6610 corresponding CALL_ARG_LOCATION note. */
6613 rtx next
= NEXT_INSN (insn
);
6614 if (next
&& NOTE_P (next
)
6615 && NOTE_KIND (next
) == NOTE_INSN_CALL_ARG_LOCATION
)
6620 if (GET_CODE (insn
) == JUMP_INSN
|| GET_CODE (insn
) == CODE_LABEL
)
6623 s390_add_pool_insn (curr_pool
, insn
);
6624 /* An LTREL_BASE must follow within the same basic block. */
6625 gcc_assert (!pending_ltrel
);
6628 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_SWITCH_TEXT_SECTIONS
)
6629 section_switch_p
= true;
6632 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn
)
6633 || INSN_ADDRESSES (INSN_UID (insn
)) == -1)
6636 if (TARGET_CPU_ZARCH
)
6638 if (curr_pool
->size
< S390_POOL_CHUNK_MAX
)
6641 s390_end_pool (curr_pool
, NULL_RTX
);
6646 int chunk_size
= INSN_ADDRESSES (INSN_UID (insn
))
6647 - INSN_ADDRESSES (INSN_UID (curr_pool
->first_insn
))
6650 /* We will later have to insert base register reload insns.
6651 Those will have an effect on code size, which we need to
6652 consider here. This calculation makes rather pessimistic
6653 worst-case assumptions. */
6654 if (GET_CODE (insn
) == CODE_LABEL
)
6657 if (chunk_size
< S390_POOL_CHUNK_MIN
6658 && curr_pool
->size
< S390_POOL_CHUNK_MIN
6659 && !section_switch_p
)
6662 /* Pool chunks can only be inserted after BARRIERs ... */
6663 if (GET_CODE (insn
) == BARRIER
)
6665 s390_end_pool (curr_pool
, insn
);
6670 /* ... so if we don't find one in time, create one. */
6671 else if (chunk_size
> S390_POOL_CHUNK_MAX
6672 || curr_pool
->size
> S390_POOL_CHUNK_MAX
6673 || section_switch_p
)
6675 rtx label
, jump
, barrier
;
6677 if (!section_switch_p
)
6679 /* We can insert the barrier only after a 'real' insn. */
6680 if (GET_CODE (insn
) != INSN
&& GET_CODE (insn
) != CALL_INSN
)
6682 if (get_attr_length (insn
) == 0)
6684 /* Don't separate LTREL_BASE from the corresponding
6685 LTREL_OFFSET load. */
6691 gcc_assert (!pending_ltrel
);
6693 /* The old pool has to end before the section switch
6694 note in order to make it part of the current
6696 insn
= PREV_INSN (insn
);
6699 label
= gen_label_rtx ();
6700 jump
= emit_jump_insn_after (gen_jump (label
), insn
);
6701 barrier
= emit_barrier_after (jump
);
6702 insn
= emit_label_after (label
, barrier
);
6703 JUMP_LABEL (jump
) = label
;
6704 LABEL_NUSES (label
) = 1;
6706 INSN_ADDRESSES_NEW (jump
, -1);
6707 INSN_ADDRESSES_NEW (barrier
, -1);
6708 INSN_ADDRESSES_NEW (insn
, -1);
6710 s390_end_pool (curr_pool
, barrier
);
6718 s390_end_pool (curr_pool
, NULL_RTX
);
6719 gcc_assert (!pending_ltrel
);
6721 /* Find all labels that are branched into
6722 from an insn belonging to a different chunk. */
6724 far_labels
= BITMAP_ALLOC (NULL
);
6726 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6728 /* Labels marked with LABEL_PRESERVE_P can be target
6729 of non-local jumps, so we have to mark them.
6730 The same holds for named labels.
6732 Don't do that, however, if it is the label before
6735 if (GET_CODE (insn
) == CODE_LABEL
6736 && (LABEL_PRESERVE_P (insn
) || LABEL_NAME (insn
)))
6738 rtx vec_insn
= next_real_insn (insn
);
6739 rtx vec_pat
= vec_insn
&& GET_CODE (vec_insn
) == JUMP_INSN
?
6740 PATTERN (vec_insn
) : NULL_RTX
;
6742 || !(GET_CODE (vec_pat
) == ADDR_VEC
6743 || GET_CODE (vec_pat
) == ADDR_DIFF_VEC
))
6744 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (insn
));
6747 /* If we have a direct jump (conditional or unconditional)
6748 or a casesi jump, check all potential targets. */
6749 else if (GET_CODE (insn
) == JUMP_INSN
)
6751 rtx pat
= PATTERN (insn
);
6752 if (GET_CODE (pat
) == PARALLEL
&& XVECLEN (pat
, 0) > 2)
6753 pat
= XVECEXP (pat
, 0, 0);
6755 if (GET_CODE (pat
) == SET
)
6757 rtx label
= JUMP_LABEL (insn
);
6760 if (s390_find_pool (pool_list
, label
)
6761 != s390_find_pool (pool_list
, insn
))
6762 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
6765 else if (GET_CODE (pat
) == PARALLEL
6766 && XVECLEN (pat
, 0) == 2
6767 && GET_CODE (XVECEXP (pat
, 0, 0)) == SET
6768 && GET_CODE (XVECEXP (pat
, 0, 1)) == USE
6769 && GET_CODE (XEXP (XVECEXP (pat
, 0, 1), 0)) == LABEL_REF
)
6771 /* Find the jump table used by this casesi jump. */
6772 rtx vec_label
= XEXP (XEXP (XVECEXP (pat
, 0, 1), 0), 0);
6773 rtx vec_insn
= next_real_insn (vec_label
);
6774 rtx vec_pat
= vec_insn
&& GET_CODE (vec_insn
) == JUMP_INSN
?
6775 PATTERN (vec_insn
) : NULL_RTX
;
6777 && (GET_CODE (vec_pat
) == ADDR_VEC
6778 || GET_CODE (vec_pat
) == ADDR_DIFF_VEC
))
6780 int i
, diff_p
= GET_CODE (vec_pat
) == ADDR_DIFF_VEC
;
6782 for (i
= 0; i
< XVECLEN (vec_pat
, diff_p
); i
++)
6784 rtx label
= XEXP (XVECEXP (vec_pat
, diff_p
, i
), 0);
6786 if (s390_find_pool (pool_list
, label
)
6787 != s390_find_pool (pool_list
, insn
))
6788 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
6795 /* Insert base register reload insns before every pool. */
6797 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
6799 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
6801 rtx insn
= curr_pool
->first_insn
;
6802 INSN_ADDRESSES_NEW (emit_insn_before (new_insn
, insn
), -1);
6805 /* Insert base register reload insns at every far label. */
6807 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6808 if (GET_CODE (insn
) == CODE_LABEL
6809 && bitmap_bit_p (far_labels
, CODE_LABEL_NUMBER (insn
)))
6811 struct constant_pool
*pool
= s390_find_pool (pool_list
, insn
);
6814 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
6816 INSN_ADDRESSES_NEW (emit_insn_after (new_insn
, insn
), -1);
6821 BITMAP_FREE (far_labels
);
6824 /* Recompute insn addresses. */
6826 init_insn_lengths ();
6827 shorten_branches (get_insns ());
6832 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6833 After we have decided to use this list, finish implementing
6834 all changes to the current function as required. */
6837 s390_chunkify_finish (struct constant_pool
*pool_list
)
6839 struct constant_pool
*curr_pool
= NULL
;
6843 /* Replace all literal pool references. */
6845 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6848 replace_ltrel_base (&PATTERN (insn
));
6850 curr_pool
= s390_find_pool (pool_list
, insn
);
6854 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6856 rtx addr
, pool_ref
= NULL_RTX
;
6857 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6860 if (s390_execute_label (insn
))
6861 addr
= s390_find_execute (curr_pool
, insn
);
6863 addr
= s390_find_constant (curr_pool
,
6864 get_pool_constant (pool_ref
),
6865 get_pool_mode (pool_ref
));
6867 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
6868 INSN_CODE (insn
) = -1;
6873 /* Dump out all literal pools. */
6875 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
6876 s390_dump_pool (curr_pool
, 0);
6878 /* Free pool list. */
6882 struct constant_pool
*next
= pool_list
->next
;
6883 s390_free_pool (pool_list
);
6888 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6889 We have decided we cannot use this list, so revert all changes
6890 to the current function that were done by s390_chunkify_start. */
6893 s390_chunkify_cancel (struct constant_pool
*pool_list
)
6895 struct constant_pool
*curr_pool
= NULL
;
6898 /* Remove all pool placeholder insns. */
6900 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
6902 /* Did we insert an extra barrier? Remove it. */
6903 rtx barrier
= PREV_INSN (curr_pool
->pool_insn
);
6904 rtx jump
= barrier
? PREV_INSN (barrier
) : NULL_RTX
;
6905 rtx label
= NEXT_INSN (curr_pool
->pool_insn
);
6907 if (jump
&& GET_CODE (jump
) == JUMP_INSN
6908 && barrier
&& GET_CODE (barrier
) == BARRIER
6909 && label
&& GET_CODE (label
) == CODE_LABEL
6910 && GET_CODE (PATTERN (jump
)) == SET
6911 && SET_DEST (PATTERN (jump
)) == pc_rtx
6912 && GET_CODE (SET_SRC (PATTERN (jump
))) == LABEL_REF
6913 && XEXP (SET_SRC (PATTERN (jump
)), 0) == label
)
6916 remove_insn (barrier
);
6917 remove_insn (label
);
6920 remove_insn (curr_pool
->pool_insn
);
6923 /* Remove all base register reload insns. */
6925 for (insn
= get_insns (); insn
; )
6927 rtx next_insn
= NEXT_INSN (insn
);
6929 if (GET_CODE (insn
) == INSN
6930 && GET_CODE (PATTERN (insn
)) == SET
6931 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC
6932 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPEC_RELOAD_BASE
)
6938 /* Free pool list. */
6942 struct constant_pool
*next
= pool_list
->next
;
6943 s390_free_pool (pool_list
);
6948 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
6951 s390_output_pool_entry (rtx exp
, enum machine_mode mode
, unsigned int align
)
6955 switch (GET_MODE_CLASS (mode
))
6958 case MODE_DECIMAL_FLOAT
:
6959 gcc_assert (GET_CODE (exp
) == CONST_DOUBLE
);
6961 REAL_VALUE_FROM_CONST_DOUBLE (r
, exp
);
6962 assemble_real (r
, mode
, align
);
6966 assemble_integer (exp
, GET_MODE_SIZE (mode
), align
, 1);
6967 mark_symbol_refs_as_used (exp
);
6976 /* Return an RTL expression representing the value of the return address
6977 for the frame COUNT steps up from the current frame. FRAME is the
6978 frame pointer of that frame. */
6981 s390_return_addr_rtx (int count
, rtx frame ATTRIBUTE_UNUSED
)
6986 /* Without backchain, we fail for all but the current frame. */
6988 if (!TARGET_BACKCHAIN
&& count
> 0)
6991 /* For the current frame, we need to make sure the initial
6992 value of RETURN_REGNUM is actually saved. */
6996 /* On non-z architectures branch splitting could overwrite r14. */
6997 if (TARGET_CPU_ZARCH
)
6998 return get_hard_reg_initial_val (Pmode
, RETURN_REGNUM
);
7001 cfun_frame_layout
.save_return_addr_p
= true;
7002 return gen_rtx_MEM (Pmode
, return_address_pointer_rtx
);
7006 if (TARGET_PACKED_STACK
)
7007 offset
= -2 * UNITS_PER_LONG
;
7009 offset
= RETURN_REGNUM
* UNITS_PER_LONG
;
7011 addr
= plus_constant (frame
, offset
);
7012 addr
= memory_address (Pmode
, addr
);
7013 return gen_rtx_MEM (Pmode
, addr
);
7016 /* Return an RTL expression representing the back chain stored in
7017 the current stack frame. */
7020 s390_back_chain_rtx (void)
7024 gcc_assert (TARGET_BACKCHAIN
);
7026 if (TARGET_PACKED_STACK
)
7027 chain
= plus_constant (stack_pointer_rtx
,
7028 STACK_POINTER_OFFSET
- UNITS_PER_LONG
);
7030 chain
= stack_pointer_rtx
;
7032 chain
= gen_rtx_MEM (Pmode
, chain
);
7036 /* Find first call clobbered register unused in a function.
7037 This could be used as base register in a leaf function
7038 or for holding the return address before epilogue. */
7041 find_unused_clobbered_reg (void)
7044 for (i
= 0; i
< 6; i
++)
7045 if (!df_regs_ever_live_p (i
))
7051 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
7052 clobbered hard regs in SETREG. */
7055 s390_reg_clobbered_rtx (rtx setreg
, const_rtx set_insn ATTRIBUTE_UNUSED
, void *data
)
7057 int *regs_ever_clobbered
= (int *)data
;
7058 unsigned int i
, regno
;
7059 enum machine_mode mode
= GET_MODE (setreg
);
7061 if (GET_CODE (setreg
) == SUBREG
)
7063 rtx inner
= SUBREG_REG (setreg
);
7064 if (!GENERAL_REG_P (inner
))
7066 regno
= subreg_regno (setreg
);
7068 else if (GENERAL_REG_P (setreg
))
7069 regno
= REGNO (setreg
);
7074 i
< regno
+ HARD_REGNO_NREGS (regno
, mode
);
7076 regs_ever_clobbered
[i
] = 1;
7079 /* Walks through all basic blocks of the current function looking
7080 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
7081 of the passed integer array REGS_EVER_CLOBBERED are set to one for
7082 each of those regs. */
7085 s390_regs_ever_clobbered (int *regs_ever_clobbered
)
7091 memset (regs_ever_clobbered
, 0, 16 * sizeof (int));
7093 /* For non-leaf functions we have to consider all call clobbered regs to be
7095 if (!current_function_is_leaf
)
7097 for (i
= 0; i
< 16; i
++)
7098 regs_ever_clobbered
[i
] = call_really_used_regs
[i
];
7101 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
7102 this work is done by liveness analysis (mark_regs_live_at_end).
7103 Special care is needed for functions containing landing pads. Landing pads
7104 may use the eh registers, but the code which sets these registers is not
7105 contained in that function. Hence s390_regs_ever_clobbered is not able to
7106 deal with this automatically. */
7107 if (crtl
->calls_eh_return
|| cfun
->machine
->has_landing_pad_p
)
7108 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
7109 if (crtl
->calls_eh_return
7110 || (cfun
->machine
->has_landing_pad_p
7111 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i
))))
7112 regs_ever_clobbered
[EH_RETURN_DATA_REGNO (i
)] = 1;
7114 /* For nonlocal gotos all call-saved registers have to be saved.
7115 This flag is also set for the unwinding code in libgcc.
7116 See expand_builtin_unwind_init. For regs_ever_live this is done by
7118 if (cfun
->has_nonlocal_label
)
7119 for (i
= 0; i
< 16; i
++)
7120 if (!call_really_used_regs
[i
])
7121 regs_ever_clobbered
[i
] = 1;
7123 FOR_EACH_BB (cur_bb
)
7125 FOR_BB_INSNS (cur_bb
, cur_insn
)
7127 if (INSN_P (cur_insn
))
7128 note_stores (PATTERN (cur_insn
),
7129 s390_reg_clobbered_rtx
,
7130 regs_ever_clobbered
);
7135 /* Determine the frame area which actually has to be accessed
7136 in the function epilogue. The values are stored at the
7137 given pointers AREA_BOTTOM (address of the lowest used stack
7138 address) and AREA_TOP (address of the first item which does
7139 not belong to the stack frame). */
7142 s390_frame_area (int *area_bottom
, int *area_top
)
7150 if (cfun_frame_layout
.first_restore_gpr
!= -1)
7152 b
= (cfun_frame_layout
.gprs_offset
7153 + cfun_frame_layout
.first_restore_gpr
* UNITS_PER_LONG
);
7154 t
= b
+ (cfun_frame_layout
.last_restore_gpr
7155 - cfun_frame_layout
.first_restore_gpr
+ 1) * UNITS_PER_LONG
;
7158 if (TARGET_64BIT
&& cfun_save_high_fprs_p
)
7160 b
= MIN (b
, cfun_frame_layout
.f8_offset
);
7161 t
= MAX (t
, (cfun_frame_layout
.f8_offset
7162 + cfun_frame_layout
.high_fprs
* 8));
7166 for (i
= 2; i
< 4; i
++)
7167 if (cfun_fpr_bit_p (i
))
7169 b
= MIN (b
, cfun_frame_layout
.f4_offset
+ (i
- 2) * 8);
7170 t
= MAX (t
, cfun_frame_layout
.f4_offset
+ (i
- 1) * 8);
7177 /* Fill cfun->machine with info about register usage of current function.
7178 Return in CLOBBERED_REGS which GPRs are currently considered set. */
7181 s390_register_info (int clobbered_regs
[])
7185 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
7186 cfun_frame_layout
.fpr_bitmap
= 0;
7187 cfun_frame_layout
.high_fprs
= 0;
7189 for (i
= 24; i
< 32; i
++)
7190 if (df_regs_ever_live_p (i
) && !global_regs
[i
])
7192 cfun_set_fpr_bit (i
- 16);
7193 cfun_frame_layout
.high_fprs
++;
7196 /* Find first and last gpr to be saved. We trust regs_ever_live
7197 data, except that we don't save and restore global registers.
7199 Also, all registers with special meaning to the compiler need
7200 to be handled extra. */
7202 s390_regs_ever_clobbered (clobbered_regs
);
7204 for (i
= 0; i
< 16; i
++)
7205 clobbered_regs
[i
] = clobbered_regs
[i
] && !global_regs
[i
] && !fixed_regs
[i
];
7207 if (frame_pointer_needed
)
7208 clobbered_regs
[HARD_FRAME_POINTER_REGNUM
] = 1;
7211 clobbered_regs
[PIC_OFFSET_TABLE_REGNUM
]
7212 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
);
7214 clobbered_regs
[BASE_REGNUM
]
7215 |= (cfun
->machine
->base_reg
7216 && REGNO (cfun
->machine
->base_reg
) == BASE_REGNUM
);
7218 clobbered_regs
[RETURN_REGNUM
]
7219 |= (!current_function_is_leaf
7220 || TARGET_TPF_PROFILING
7221 || cfun
->machine
->split_branches_pending_p
7222 || cfun_frame_layout
.save_return_addr_p
7223 || crtl
->calls_eh_return
7226 clobbered_regs
[STACK_POINTER_REGNUM
]
7227 |= (!current_function_is_leaf
7228 || TARGET_TPF_PROFILING
7229 || cfun_save_high_fprs_p
7230 || get_frame_size () > 0
7231 || cfun
->calls_alloca
7234 for (i
= 6; i
< 16; i
++)
7235 if (df_regs_ever_live_p (i
) || clobbered_regs
[i
])
7237 for (j
= 15; j
> i
; j
--)
7238 if (df_regs_ever_live_p (j
) || clobbered_regs
[j
])
7243 /* Nothing to save/restore. */
7244 cfun_frame_layout
.first_save_gpr_slot
= -1;
7245 cfun_frame_layout
.last_save_gpr_slot
= -1;
7246 cfun_frame_layout
.first_save_gpr
= -1;
7247 cfun_frame_layout
.first_restore_gpr
= -1;
7248 cfun_frame_layout
.last_save_gpr
= -1;
7249 cfun_frame_layout
.last_restore_gpr
= -1;
7253 /* Save slots for gprs from i to j. */
7254 cfun_frame_layout
.first_save_gpr_slot
= i
;
7255 cfun_frame_layout
.last_save_gpr_slot
= j
;
7257 for (i
= cfun_frame_layout
.first_save_gpr_slot
;
7258 i
< cfun_frame_layout
.last_save_gpr_slot
+ 1;
7260 if (clobbered_regs
[i
])
7263 for (j
= cfun_frame_layout
.last_save_gpr_slot
; j
> i
; j
--)
7264 if (clobbered_regs
[j
])
7267 if (i
== cfun_frame_layout
.last_save_gpr_slot
+ 1)
7269 /* Nothing to save/restore. */
7270 cfun_frame_layout
.first_save_gpr
= -1;
7271 cfun_frame_layout
.first_restore_gpr
= -1;
7272 cfun_frame_layout
.last_save_gpr
= -1;
7273 cfun_frame_layout
.last_restore_gpr
= -1;
7277 /* Save / Restore from gpr i to j. */
7278 cfun_frame_layout
.first_save_gpr
= i
;
7279 cfun_frame_layout
.first_restore_gpr
= i
;
7280 cfun_frame_layout
.last_save_gpr
= j
;
7281 cfun_frame_layout
.last_restore_gpr
= j
;
7287 /* Varargs functions need to save gprs 2 to 6. */
7288 if (cfun
->va_list_gpr_size
7289 && crtl
->args
.info
.gprs
< GP_ARG_NUM_REG
)
7291 int min_gpr
= crtl
->args
.info
.gprs
;
7292 int max_gpr
= min_gpr
+ cfun
->va_list_gpr_size
;
7293 if (max_gpr
> GP_ARG_NUM_REG
)
7294 max_gpr
= GP_ARG_NUM_REG
;
7296 if (cfun_frame_layout
.first_save_gpr
== -1
7297 || cfun_frame_layout
.first_save_gpr
> 2 + min_gpr
)
7299 cfun_frame_layout
.first_save_gpr
= 2 + min_gpr
;
7300 cfun_frame_layout
.first_save_gpr_slot
= 2 + min_gpr
;
7303 if (cfun_frame_layout
.last_save_gpr
== -1
7304 || cfun_frame_layout
.last_save_gpr
< 2 + max_gpr
- 1)
7306 cfun_frame_layout
.last_save_gpr
= 2 + max_gpr
- 1;
7307 cfun_frame_layout
.last_save_gpr_slot
= 2 + max_gpr
- 1;
7311 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
7312 if (TARGET_HARD_FLOAT
&& cfun
->va_list_fpr_size
7313 && crtl
->args
.info
.fprs
< FP_ARG_NUM_REG
)
7315 int min_fpr
= crtl
->args
.info
.fprs
;
7316 int max_fpr
= min_fpr
+ cfun
->va_list_fpr_size
;
7317 if (max_fpr
> FP_ARG_NUM_REG
)
7318 max_fpr
= FP_ARG_NUM_REG
;
7320 /* ??? This is currently required to ensure proper location
7321 of the fpr save slots within the va_list save area. */
7322 if (TARGET_PACKED_STACK
)
7325 for (i
= min_fpr
; i
< max_fpr
; i
++)
7326 cfun_set_fpr_bit (i
);
7331 for (i
= 2; i
< 4; i
++)
7332 if (df_regs_ever_live_p (i
+ 16) && !global_regs
[i
+ 16])
7333 cfun_set_fpr_bit (i
);
7336 /* Fill cfun->machine with info about frame of current function. */
7339 s390_frame_info (void)
7343 cfun_frame_layout
.frame_size
= get_frame_size ();
7344 if (!TARGET_64BIT
&& cfun_frame_layout
.frame_size
> 0x7fff0000)
7345 fatal_error ("total size of local variables exceeds architecture limit");
7347 if (!TARGET_PACKED_STACK
)
7349 cfun_frame_layout
.backchain_offset
= 0;
7350 cfun_frame_layout
.f0_offset
= 16 * UNITS_PER_LONG
;
7351 cfun_frame_layout
.f4_offset
= cfun_frame_layout
.f0_offset
+ 2 * 8;
7352 cfun_frame_layout
.f8_offset
= -cfun_frame_layout
.high_fprs
* 8;
7353 cfun_frame_layout
.gprs_offset
= (cfun_frame_layout
.first_save_gpr_slot
7356 else if (TARGET_BACKCHAIN
) /* kernel stack layout */
7358 cfun_frame_layout
.backchain_offset
= (STACK_POINTER_OFFSET
7360 cfun_frame_layout
.gprs_offset
7361 = (cfun_frame_layout
.backchain_offset
7362 - (STACK_POINTER_REGNUM
- cfun_frame_layout
.first_save_gpr_slot
+ 1)
7367 cfun_frame_layout
.f4_offset
7368 = (cfun_frame_layout
.gprs_offset
7369 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7371 cfun_frame_layout
.f0_offset
7372 = (cfun_frame_layout
.f4_offset
7373 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7377 /* On 31 bit we have to care about alignment of the
7378 floating point regs to provide fastest access. */
7379 cfun_frame_layout
.f0_offset
7380 = ((cfun_frame_layout
.gprs_offset
7381 & ~(STACK_BOUNDARY
/ BITS_PER_UNIT
- 1))
7382 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7384 cfun_frame_layout
.f4_offset
7385 = (cfun_frame_layout
.f0_offset
7386 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7389 else /* no backchain */
7391 cfun_frame_layout
.f4_offset
7392 = (STACK_POINTER_OFFSET
7393 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7395 cfun_frame_layout
.f0_offset
7396 = (cfun_frame_layout
.f4_offset
7397 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7399 cfun_frame_layout
.gprs_offset
7400 = cfun_frame_layout
.f0_offset
- cfun_gprs_save_area_size
;
7403 if (current_function_is_leaf
7404 && !TARGET_TPF_PROFILING
7405 && cfun_frame_layout
.frame_size
== 0
7406 && !cfun_save_high_fprs_p
7407 && !cfun
->calls_alloca
7411 if (!TARGET_PACKED_STACK
)
7412 cfun_frame_layout
.frame_size
+= (STACK_POINTER_OFFSET
7413 + crtl
->outgoing_args_size
7414 + cfun_frame_layout
.high_fprs
* 8);
7417 if (TARGET_BACKCHAIN
)
7418 cfun_frame_layout
.frame_size
+= UNITS_PER_LONG
;
7420 /* No alignment trouble here because f8-f15 are only saved under
7422 cfun_frame_layout
.f8_offset
= (MIN (MIN (cfun_frame_layout
.f0_offset
,
7423 cfun_frame_layout
.f4_offset
),
7424 cfun_frame_layout
.gprs_offset
)
7425 - cfun_frame_layout
.high_fprs
* 8);
7427 cfun_frame_layout
.frame_size
+= cfun_frame_layout
.high_fprs
* 8;
7429 for (i
= 0; i
< 8; i
++)
7430 if (cfun_fpr_bit_p (i
))
7431 cfun_frame_layout
.frame_size
+= 8;
7433 cfun_frame_layout
.frame_size
+= cfun_gprs_save_area_size
;
7435 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7436 the frame size to sustain 8 byte alignment of stack frames. */
7437 cfun_frame_layout
.frame_size
= ((cfun_frame_layout
.frame_size
+
7438 STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
7439 & ~(STACK_BOUNDARY
/ BITS_PER_UNIT
- 1));
7441 cfun_frame_layout
.frame_size
+= crtl
->outgoing_args_size
;
7445 /* Generate frame layout. Fills in register and frame data for the current
7446 function in cfun->machine. This routine can be called multiple times;
7447 it will re-do the complete frame layout every time. */
7450 s390_init_frame_layout (void)
7452 HOST_WIDE_INT frame_size
;
7454 int clobbered_regs
[16];
7456 /* On S/390 machines, we may need to perform branch splitting, which
7457 will require both base and return address register. We have no
7458 choice but to assume we're going to need them until right at the
7459 end of the machine dependent reorg phase. */
7460 if (!TARGET_CPU_ZARCH
)
7461 cfun
->machine
->split_branches_pending_p
= true;
7465 frame_size
= cfun_frame_layout
.frame_size
;
7467 /* Try to predict whether we'll need the base register. */
7468 base_used
= cfun
->machine
->split_branches_pending_p
7469 || crtl
->uses_const_pool
7470 || (!DISP_IN_RANGE (frame_size
)
7471 && !CONST_OK_FOR_K (frame_size
));
7473 /* Decide which register to use as literal pool base. In small
7474 leaf functions, try to use an unused call-clobbered register
7475 as base register to avoid save/restore overhead. */
7477 cfun
->machine
->base_reg
= NULL_RTX
;
7478 else if (current_function_is_leaf
&& !df_regs_ever_live_p (5))
7479 cfun
->machine
->base_reg
= gen_rtx_REG (Pmode
, 5);
7481 cfun
->machine
->base_reg
= gen_rtx_REG (Pmode
, BASE_REGNUM
);
7483 s390_register_info (clobbered_regs
);
7486 while (frame_size
!= cfun_frame_layout
.frame_size
);
7489 /* Update frame layout. Recompute actual register save data based on
7490 current info and update regs_ever_live for the special registers.
7491 May be called multiple times, but may never cause *more* registers
7492 to be saved than s390_init_frame_layout allocated room for. */
7495 s390_update_frame_layout (void)
7497 int clobbered_regs
[16];
7499 s390_register_info (clobbered_regs
);
7501 df_set_regs_ever_live (BASE_REGNUM
,
7502 clobbered_regs
[BASE_REGNUM
] ? true : false);
7503 df_set_regs_ever_live (RETURN_REGNUM
,
7504 clobbered_regs
[RETURN_REGNUM
] ? true : false);
7505 df_set_regs_ever_live (STACK_POINTER_REGNUM
,
7506 clobbered_regs
[STACK_POINTER_REGNUM
] ? true : false);
7508 if (cfun
->machine
->base_reg
)
7509 df_set_regs_ever_live (REGNO (cfun
->machine
->base_reg
), true);
7512 /* Return true if it is legal to put a value with MODE into REGNO. */
7515 s390_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
7517 switch (REGNO_REG_CLASS (regno
))
7520 if (REGNO_PAIR_OK (regno
, mode
))
7522 if (mode
== SImode
|| mode
== DImode
)
7525 if (FLOAT_MODE_P (mode
) && GET_MODE_CLASS (mode
) != MODE_VECTOR_FLOAT
)
7530 if (FRAME_REGNO_P (regno
) && mode
== Pmode
)
7535 if (REGNO_PAIR_OK (regno
, mode
))
7538 || (mode
!= TFmode
&& mode
!= TCmode
&& mode
!= TDmode
))
7543 if (GET_MODE_CLASS (mode
) == MODE_CC
)
7547 if (REGNO_PAIR_OK (regno
, mode
))
7549 if (mode
== SImode
|| mode
== Pmode
)
7560 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
7563 s390_hard_regno_rename_ok (unsigned int old_reg
, unsigned int new_reg
)
7565 /* Once we've decided upon a register to use as base register, it must
7566 no longer be used for any other purpose. */
7567 if (cfun
->machine
->base_reg
)
7568 if (REGNO (cfun
->machine
->base_reg
) == old_reg
7569 || REGNO (cfun
->machine
->base_reg
) == new_reg
)
7575 /* Maximum number of registers to represent a value of mode MODE
7576 in a register of class RCLASS. */
7579 s390_class_max_nregs (enum reg_class rclass
, enum machine_mode mode
)
7584 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
7585 return 2 * ((GET_MODE_SIZE (mode
) / 2 + 8 - 1) / 8);
7587 return (GET_MODE_SIZE (mode
) + 8 - 1) / 8;
7589 return (GET_MODE_SIZE (mode
) + 4 - 1) / 4;
7593 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
7596 /* Return true if register FROM can be eliminated via register TO. */
7599 s390_can_eliminate (const int from
, const int to
)
7601 /* On zSeries machines, we have not marked the base register as fixed.
7602 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
7603 If a function requires the base register, we say here that this
7604 elimination cannot be performed. This will cause reload to free
7605 up the base register (as if it were fixed). On the other hand,
7606 if the current function does *not* require the base register, we
7607 say here the elimination succeeds, which in turn allows reload
7608 to allocate the base register for any other purpose. */
7609 if (from
== BASE_REGNUM
&& to
== BASE_REGNUM
)
7611 if (TARGET_CPU_ZARCH
)
7613 s390_init_frame_layout ();
7614 return cfun
->machine
->base_reg
== NULL_RTX
;
7620 /* Everything else must point into the stack frame. */
7621 gcc_assert (to
== STACK_POINTER_REGNUM
7622 || to
== HARD_FRAME_POINTER_REGNUM
);
7624 gcc_assert (from
== FRAME_POINTER_REGNUM
7625 || from
== ARG_POINTER_REGNUM
7626 || from
== RETURN_ADDRESS_POINTER_REGNUM
);
7628 /* Make sure we actually saved the return address. */
7629 if (from
== RETURN_ADDRESS_POINTER_REGNUM
)
7630 if (!crtl
->calls_eh_return
7632 && !cfun_frame_layout
.save_return_addr_p
)
7638 /* Return offset between register FROM and TO initially after prolog. */
7641 s390_initial_elimination_offset (int from
, int to
)
7643 HOST_WIDE_INT offset
;
7646 /* ??? Why are we called for non-eliminable pairs? */
7647 if (!s390_can_eliminate (from
, to
))
7652 case FRAME_POINTER_REGNUM
:
7653 offset
= (get_frame_size()
7654 + STACK_POINTER_OFFSET
7655 + crtl
->outgoing_args_size
);
7658 case ARG_POINTER_REGNUM
:
7659 s390_init_frame_layout ();
7660 offset
= cfun_frame_layout
.frame_size
+ STACK_POINTER_OFFSET
;
7663 case RETURN_ADDRESS_POINTER_REGNUM
:
7664 s390_init_frame_layout ();
7665 index
= RETURN_REGNUM
- cfun_frame_layout
.first_save_gpr_slot
;
7666 gcc_assert (index
>= 0);
7667 offset
= cfun_frame_layout
.frame_size
+ cfun_frame_layout
.gprs_offset
;
7668 offset
+= index
* UNITS_PER_LONG
;
7682 /* Emit insn to save fpr REGNUM at offset OFFSET relative
7683 to register BASE. Return generated insn. */
7686 save_fpr (rtx base
, int offset
, int regnum
)
7689 addr
= gen_rtx_MEM (DFmode
, plus_constant (base
, offset
));
7691 if (regnum
>= 16 && regnum
<= (16 + FP_ARG_NUM_REG
))
7692 set_mem_alias_set (addr
, get_varargs_alias_set ());
7694 set_mem_alias_set (addr
, get_frame_alias_set ());
7696 return emit_move_insn (addr
, gen_rtx_REG (DFmode
, regnum
));
7699 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
7700 to register BASE. Return generated insn. */
7703 restore_fpr (rtx base
, int offset
, int regnum
)
7706 addr
= gen_rtx_MEM (DFmode
, plus_constant (base
, offset
));
7707 set_mem_alias_set (addr
, get_frame_alias_set ());
7709 return emit_move_insn (gen_rtx_REG (DFmode
, regnum
), addr
);
7712 /* Return true if REGNO is a global register, but not one
7713 of the special ones that need to be saved/restored in anyway. */
7716 global_not_special_regno_p (int regno
)
7718 return (global_regs
[regno
]
7719 /* These registers are special and need to be
7720 restored in any case. */
7721 && !(regno
== STACK_POINTER_REGNUM
7722 || regno
== RETURN_REGNUM
7723 || regno
== BASE_REGNUM
7724 || (flag_pic
&& regno
== (int)PIC_OFFSET_TABLE_REGNUM
)));
7727 /* Generate insn to save registers FIRST to LAST into
7728 the register save area located at offset OFFSET
7729 relative to register BASE. */
7732 save_gprs (rtx base
, int offset
, int first
, int last
)
7734 rtx addr
, insn
, note
;
7737 addr
= plus_constant (base
, offset
);
7738 addr
= gen_rtx_MEM (Pmode
, addr
);
7740 set_mem_alias_set (addr
, get_frame_alias_set ());
7742 /* Special-case single register. */
7746 insn
= gen_movdi (addr
, gen_rtx_REG (Pmode
, first
));
7748 insn
= gen_movsi (addr
, gen_rtx_REG (Pmode
, first
));
7750 if (!global_not_special_regno_p (first
))
7751 RTX_FRAME_RELATED_P (insn
) = 1;
7756 insn
= gen_store_multiple (addr
,
7757 gen_rtx_REG (Pmode
, first
),
7758 GEN_INT (last
- first
+ 1));
7760 if (first
<= 6 && cfun
->stdarg
)
7761 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
7763 rtx mem
= XEXP (XVECEXP (PATTERN (insn
), 0, i
), 0);
7766 set_mem_alias_set (mem
, get_varargs_alias_set ());
7769 /* We need to set the FRAME_RELATED flag on all SETs
7770 inside the store-multiple pattern.
7772 However, we must not emit DWARF records for registers 2..5
7773 if they are stored for use by variable arguments ...
7775 ??? Unfortunately, it is not enough to simply not the
7776 FRAME_RELATED flags for those SETs, because the first SET
7777 of the PARALLEL is always treated as if it had the flag
7778 set, even if it does not. Therefore we emit a new pattern
7779 without those registers as REG_FRAME_RELATED_EXPR note. */
7781 if (first
>= 6 && !global_not_special_regno_p (first
))
7783 rtx pat
= PATTERN (insn
);
7785 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
7786 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
7787 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat
,
7789 RTX_FRAME_RELATED_P (XVECEXP (pat
, 0, i
)) = 1;
7791 RTX_FRAME_RELATED_P (insn
) = 1;
7797 for (start
= first
>= 6 ? first
: 6; start
<= last
; start
++)
7798 if (!global_not_special_regno_p (start
))
7804 addr
= plus_constant (base
, offset
+ (start
- first
) * UNITS_PER_LONG
);
7805 note
= gen_store_multiple (gen_rtx_MEM (Pmode
, addr
),
7806 gen_rtx_REG (Pmode
, start
),
7807 GEN_INT (last
- start
+ 1));
7808 note
= PATTERN (note
);
7810 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note
);
7812 for (i
= 0; i
< XVECLEN (note
, 0); i
++)
7813 if (GET_CODE (XVECEXP (note
, 0, i
)) == SET
7814 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note
,
7816 RTX_FRAME_RELATED_P (XVECEXP (note
, 0, i
)) = 1;
7818 RTX_FRAME_RELATED_P (insn
) = 1;
7824 /* Generate insn to restore registers FIRST to LAST from
7825 the register save area located at offset OFFSET
7826 relative to register BASE. */
7829 restore_gprs (rtx base
, int offset
, int first
, int last
)
7833 addr
= plus_constant (base
, offset
);
7834 addr
= gen_rtx_MEM (Pmode
, addr
);
7835 set_mem_alias_set (addr
, get_frame_alias_set ());
7837 /* Special-case single register. */
7841 insn
= gen_movdi (gen_rtx_REG (Pmode
, first
), addr
);
7843 insn
= gen_movsi (gen_rtx_REG (Pmode
, first
), addr
);
7848 insn
= gen_load_multiple (gen_rtx_REG (Pmode
, first
),
7850 GEN_INT (last
- first
+ 1));
7854 /* Return insn sequence to load the GOT register. */
7856 static GTY(()) rtx got_symbol
;
7858 s390_load_got (void)
7864 got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
7865 SYMBOL_REF_FLAGS (got_symbol
) = SYMBOL_FLAG_LOCAL
;
7870 if (TARGET_CPU_ZARCH
)
7872 emit_move_insn (pic_offset_table_rtx
, got_symbol
);
7878 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, got_symbol
),
7879 UNSPEC_LTREL_OFFSET
);
7880 offset
= gen_rtx_CONST (Pmode
, offset
);
7881 offset
= force_const_mem (Pmode
, offset
);
7883 emit_move_insn (pic_offset_table_rtx
, offset
);
7885 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, XEXP (offset
, 0)),
7887 offset
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, offset
);
7889 emit_move_insn (pic_offset_table_rtx
, offset
);
7892 insns
= get_insns ();
7897 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
7898 and the change to the stack pointer. */
7901 s390_emit_stack_tie (void)
7903 rtx mem
= gen_frame_mem (BLKmode
,
7904 gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
));
7906 emit_insn (gen_stack_tie (mem
));
7909 /* Expand the prologue into a bunch of separate insns. */
7912 s390_emit_prologue (void)
7920 /* Complete frame layout. */
7922 s390_update_frame_layout ();
7924 /* Annotate all constant pool references to let the scheduler know
7925 they implicitly use the base register. */
7927 push_topmost_sequence ();
7929 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
7932 annotate_constant_pool_refs (&PATTERN (insn
));
7933 df_insn_rescan (insn
);
7936 pop_topmost_sequence ();
7938 /* Choose best register to use for temp use within prologue.
7939 See below for why TPF must use the register 1. */
7941 if (!has_hard_reg_initial_val (Pmode
, RETURN_REGNUM
)
7942 && !current_function_is_leaf
7943 && !TARGET_TPF_PROFILING
)
7944 temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
7946 temp_reg
= gen_rtx_REG (Pmode
, 1);
7948 /* Save call saved gprs. */
7949 if (cfun_frame_layout
.first_save_gpr
!= -1)
7951 insn
= save_gprs (stack_pointer_rtx
,
7952 cfun_frame_layout
.gprs_offset
+
7953 UNITS_PER_LONG
* (cfun_frame_layout
.first_save_gpr
7954 - cfun_frame_layout
.first_save_gpr_slot
),
7955 cfun_frame_layout
.first_save_gpr
,
7956 cfun_frame_layout
.last_save_gpr
);
7960 /* Dummy insn to mark literal pool slot. */
7962 if (cfun
->machine
->base_reg
)
7963 emit_insn (gen_main_pool (cfun
->machine
->base_reg
));
7965 offset
= cfun_frame_layout
.f0_offset
;
7967 /* Save f0 and f2. */
7968 for (i
= 0; i
< 2; i
++)
7970 if (cfun_fpr_bit_p (i
))
7972 save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
7975 else if (!TARGET_PACKED_STACK
)
7979 /* Save f4 and f6. */
7980 offset
= cfun_frame_layout
.f4_offset
;
7981 for (i
= 2; i
< 4; i
++)
7983 if (cfun_fpr_bit_p (i
))
7985 insn
= save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
7988 /* If f4 and f6 are call clobbered they are saved due to stdargs and
7989 therefore are not frame related. */
7990 if (!call_really_used_regs
[i
+ 16])
7991 RTX_FRAME_RELATED_P (insn
) = 1;
7993 else if (!TARGET_PACKED_STACK
)
7997 if (TARGET_PACKED_STACK
7998 && cfun_save_high_fprs_p
7999 && cfun_frame_layout
.f8_offset
+ cfun_frame_layout
.high_fprs
* 8 > 0)
8001 offset
= (cfun_frame_layout
.f8_offset
8002 + (cfun_frame_layout
.high_fprs
- 1) * 8);
8004 for (i
= 15; i
> 7 && offset
>= 0; i
--)
8005 if (cfun_fpr_bit_p (i
))
8007 insn
= save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
8009 RTX_FRAME_RELATED_P (insn
) = 1;
8012 if (offset
>= cfun_frame_layout
.f8_offset
)
8016 if (!TARGET_PACKED_STACK
)
8017 next_fpr
= cfun_save_high_fprs_p
? 31 : 0;
8019 if (flag_stack_usage_info
)
8020 current_function_static_stack_size
= cfun_frame_layout
.frame_size
;
8022 /* Decrement stack pointer. */
8024 if (cfun_frame_layout
.frame_size
> 0)
8026 rtx frame_off
= GEN_INT (-cfun_frame_layout
.frame_size
);
8029 if (s390_stack_size
)
8031 HOST_WIDE_INT stack_guard
;
8033 if (s390_stack_guard
)
8034 stack_guard
= s390_stack_guard
;
8037 /* If no value for stack guard is provided the smallest power of 2
8038 larger than the current frame size is chosen. */
8040 while (stack_guard
< cfun_frame_layout
.frame_size
)
8044 if (cfun_frame_layout
.frame_size
>= s390_stack_size
)
8046 warning (0, "frame size of function %qs is %wd"
8047 " bytes exceeding user provided stack limit of "
8049 "An unconditional trap is added.",
8050 current_function_name(), cfun_frame_layout
.frame_size
,
8052 emit_insn (gen_trap ());
8056 /* stack_guard has to be smaller than s390_stack_size.
8057 Otherwise we would emit an AND with zero which would
8058 not match the test under mask pattern. */
8059 if (stack_guard
>= s390_stack_size
)
8061 warning (0, "frame size of function %qs is %wd"
8062 " bytes which is more than half the stack size. "
8063 "The dynamic check would not be reliable. "
8064 "No check emitted for this function.",
8065 current_function_name(),
8066 cfun_frame_layout
.frame_size
);
8070 HOST_WIDE_INT stack_check_mask
= ((s390_stack_size
- 1)
8071 & ~(stack_guard
- 1));
8073 rtx t
= gen_rtx_AND (Pmode
, stack_pointer_rtx
,
8074 GEN_INT (stack_check_mask
));
8076 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode
,
8078 t
, const0_rtx
, const0_rtx
));
8080 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode
,
8082 t
, const0_rtx
, const0_rtx
));
8087 if (s390_warn_framesize
> 0
8088 && cfun_frame_layout
.frame_size
>= s390_warn_framesize
)
8089 warning (0, "frame size of %qs is %wd bytes",
8090 current_function_name (), cfun_frame_layout
.frame_size
);
8092 if (s390_warn_dynamicstack_p
&& cfun
->calls_alloca
)
8093 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
8095 /* Save incoming stack pointer into temp reg. */
8096 if (TARGET_BACKCHAIN
|| next_fpr
)
8097 insn
= emit_insn (gen_move_insn (temp_reg
, stack_pointer_rtx
));
8099 /* Subtract frame size from stack pointer. */
8101 if (DISP_IN_RANGE (INTVAL (frame_off
)))
8103 insn
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8104 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
8106 insn
= emit_insn (insn
);
8110 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
8111 frame_off
= force_const_mem (Pmode
, frame_off
);
8113 insn
= emit_insn (gen_add2_insn (stack_pointer_rtx
, frame_off
));
8114 annotate_constant_pool_refs (&PATTERN (insn
));
8117 RTX_FRAME_RELATED_P (insn
) = 1;
8118 real_frame_off
= GEN_INT (-cfun_frame_layout
.frame_size
);
8119 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
8120 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8121 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
8124 /* Set backchain. */
8126 if (TARGET_BACKCHAIN
)
8128 if (cfun_frame_layout
.backchain_offset
)
8129 addr
= gen_rtx_MEM (Pmode
,
8130 plus_constant (stack_pointer_rtx
,
8131 cfun_frame_layout
.backchain_offset
));
8133 addr
= gen_rtx_MEM (Pmode
, stack_pointer_rtx
);
8134 set_mem_alias_set (addr
, get_frame_alias_set ());
8135 insn
= emit_insn (gen_move_insn (addr
, temp_reg
));
8138 /* If we support non-call exceptions (e.g. for Java),
8139 we need to make sure the backchain pointer is set up
8140 before any possibly trapping memory access. */
8141 if (TARGET_BACKCHAIN
&& cfun
->can_throw_non_call_exceptions
)
8143 addr
= gen_rtx_MEM (BLKmode
, gen_rtx_SCRATCH (VOIDmode
));
8144 emit_clobber (addr
);
8148 /* Save fprs 8 - 15 (64 bit ABI). */
8150 if (cfun_save_high_fprs_p
&& next_fpr
)
8152 /* If the stack might be accessed through a different register
8153 we have to make sure that the stack pointer decrement is not
8154 moved below the use of the stack slots. */
8155 s390_emit_stack_tie ();
8157 insn
= emit_insn (gen_add2_insn (temp_reg
,
8158 GEN_INT (cfun_frame_layout
.f8_offset
)));
8162 for (i
= 24; i
<= next_fpr
; i
++)
8163 if (cfun_fpr_bit_p (i
- 16))
8165 rtx addr
= plus_constant (stack_pointer_rtx
,
8166 cfun_frame_layout
.frame_size
8167 + cfun_frame_layout
.f8_offset
8170 insn
= save_fpr (temp_reg
, offset
, i
);
8172 RTX_FRAME_RELATED_P (insn
) = 1;
8173 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
8174 gen_rtx_SET (VOIDmode
,
8175 gen_rtx_MEM (DFmode
, addr
),
8176 gen_rtx_REG (DFmode
, i
)));
8180 /* Set frame pointer, if needed. */
8182 if (frame_pointer_needed
)
8184 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
8185 RTX_FRAME_RELATED_P (insn
) = 1;
8188 /* Set up got pointer, if needed. */
8190 if (flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
8192 rtx insns
= s390_load_got ();
8194 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
8195 annotate_constant_pool_refs (&PATTERN (insn
));
8200 if (TARGET_TPF_PROFILING
)
8202 /* Generate a BAS instruction to serve as a function
8203 entry intercept to facilitate the use of tracing
8204 algorithms located at the branch target. */
8205 emit_insn (gen_prologue_tpf ());
8207 /* Emit a blockage here so that all code
8208 lies between the profiling mechanisms. */
8209 emit_insn (gen_blockage ());
8213 /* Expand the epilogue into a bunch of separate insns. */
8216 s390_emit_epilogue (bool sibcall
)
8218 rtx frame_pointer
, return_reg
, cfa_restores
= NULL_RTX
;
8219 int area_bottom
, area_top
, offset
= 0;
8224 if (TARGET_TPF_PROFILING
)
8227 /* Generate a BAS instruction to serve as a function
8228 entry intercept to facilitate the use of tracing
8229 algorithms located at the branch target. */
8231 /* Emit a blockage here so that all code
8232 lies between the profiling mechanisms. */
8233 emit_insn (gen_blockage ());
8235 emit_insn (gen_epilogue_tpf ());
8238 /* Check whether to use frame or stack pointer for restore. */
8240 frame_pointer
= (frame_pointer_needed
8241 ? hard_frame_pointer_rtx
: stack_pointer_rtx
);
8243 s390_frame_area (&area_bottom
, &area_top
);
8245 /* Check whether we can access the register save area.
8246 If not, increment the frame pointer as required. */
8248 if (area_top
<= area_bottom
)
8250 /* Nothing to restore. */
8252 else if (DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_bottom
)
8253 && DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_top
- 1))
8255 /* Area is in range. */
8256 offset
= cfun_frame_layout
.frame_size
;
8260 rtx insn
, frame_off
, cfa
;
8262 offset
= area_bottom
< 0 ? -area_bottom
: 0;
8263 frame_off
= GEN_INT (cfun_frame_layout
.frame_size
- offset
);
8265 cfa
= gen_rtx_SET (VOIDmode
, frame_pointer
,
8266 gen_rtx_PLUS (Pmode
, frame_pointer
, frame_off
));
8267 if (DISP_IN_RANGE (INTVAL (frame_off
)))
8269 insn
= gen_rtx_SET (VOIDmode
, frame_pointer
,
8270 gen_rtx_PLUS (Pmode
, frame_pointer
, frame_off
));
8271 insn
= emit_insn (insn
);
8275 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
8276 frame_off
= force_const_mem (Pmode
, frame_off
);
8278 insn
= emit_insn (gen_add2_insn (frame_pointer
, frame_off
));
8279 annotate_constant_pool_refs (&PATTERN (insn
));
8281 add_reg_note (insn
, REG_CFA_ADJUST_CFA
, cfa
);
8282 RTX_FRAME_RELATED_P (insn
) = 1;
8285 /* Restore call saved fprs. */
8289 if (cfun_save_high_fprs_p
)
8291 next_offset
= cfun_frame_layout
.f8_offset
;
8292 for (i
= 24; i
< 32; i
++)
8294 if (cfun_fpr_bit_p (i
- 16))
8296 restore_fpr (frame_pointer
,
8297 offset
+ next_offset
, i
);
8299 = alloc_reg_note (REG_CFA_RESTORE
,
8300 gen_rtx_REG (DFmode
, i
), cfa_restores
);
8309 next_offset
= cfun_frame_layout
.f4_offset
;
8310 for (i
= 18; i
< 20; i
++)
8312 if (cfun_fpr_bit_p (i
- 16))
8314 restore_fpr (frame_pointer
,
8315 offset
+ next_offset
, i
);
8317 = alloc_reg_note (REG_CFA_RESTORE
,
8318 gen_rtx_REG (DFmode
, i
), cfa_restores
);
8321 else if (!TARGET_PACKED_STACK
)
8327 /* Return register. */
8329 return_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
8331 /* Restore call saved gprs. */
8333 if (cfun_frame_layout
.first_restore_gpr
!= -1)
8338 /* Check for global register and save them
8339 to stack location from where they get restored. */
8341 for (i
= cfun_frame_layout
.first_restore_gpr
;
8342 i
<= cfun_frame_layout
.last_restore_gpr
;
8345 if (global_not_special_regno_p (i
))
8347 addr
= plus_constant (frame_pointer
,
8348 offset
+ cfun_frame_layout
.gprs_offset
8349 + (i
- cfun_frame_layout
.first_save_gpr_slot
)
8351 addr
= gen_rtx_MEM (Pmode
, addr
);
8352 set_mem_alias_set (addr
, get_frame_alias_set ());
8353 emit_move_insn (addr
, gen_rtx_REG (Pmode
, i
));
8357 = alloc_reg_note (REG_CFA_RESTORE
,
8358 gen_rtx_REG (Pmode
, i
), cfa_restores
);
8363 /* Fetch return address from stack before load multiple,
8364 this will do good for scheduling. */
8366 if (cfun_frame_layout
.save_return_addr_p
8367 || (cfun_frame_layout
.first_restore_gpr
< BASE_REGNUM
8368 && cfun_frame_layout
.last_restore_gpr
> RETURN_REGNUM
))
8370 int return_regnum
= find_unused_clobbered_reg();
8373 return_reg
= gen_rtx_REG (Pmode
, return_regnum
);
8375 addr
= plus_constant (frame_pointer
,
8376 offset
+ cfun_frame_layout
.gprs_offset
8378 - cfun_frame_layout
.first_save_gpr_slot
)
8380 addr
= gen_rtx_MEM (Pmode
, addr
);
8381 set_mem_alias_set (addr
, get_frame_alias_set ());
8382 emit_move_insn (return_reg
, addr
);
8386 insn
= restore_gprs (frame_pointer
,
8387 offset
+ cfun_frame_layout
.gprs_offset
8388 + (cfun_frame_layout
.first_restore_gpr
8389 - cfun_frame_layout
.first_save_gpr_slot
)
8391 cfun_frame_layout
.first_restore_gpr
,
8392 cfun_frame_layout
.last_restore_gpr
);
8393 insn
= emit_insn (insn
);
8394 REG_NOTES (insn
) = cfa_restores
;
8395 add_reg_note (insn
, REG_CFA_DEF_CFA
,
8396 plus_constant (stack_pointer_rtx
, STACK_POINTER_OFFSET
));
8397 RTX_FRAME_RELATED_P (insn
) = 1;
8403 /* Return to caller. */
8405 p
= rtvec_alloc (2);
8407 RTVEC_ELT (p
, 0) = ret_rtx
;
8408 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
, return_reg
);
8409 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
8414 /* Return the size in bytes of a function argument of
8415 type TYPE and/or mode MODE. At least one of TYPE or
8416 MODE must be specified. */
8419 s390_function_arg_size (enum machine_mode mode
, const_tree type
)
8422 return int_size_in_bytes (type
);
8424 /* No type info available for some library calls ... */
8425 if (mode
!= BLKmode
)
8426 return GET_MODE_SIZE (mode
);
8428 /* If we have neither type nor mode, abort */
8432 /* Return true if a function argument of type TYPE and mode MODE
8433 is to be passed in a floating-point register, if available. */
8436 s390_function_arg_float (enum machine_mode mode
, const_tree type
)
8438 int size
= s390_function_arg_size (mode
, type
);
8442 /* Soft-float changes the ABI: no floating-point registers are used. */
8443 if (TARGET_SOFT_FLOAT
)
8446 /* No type info available for some library calls ... */
8448 return mode
== SFmode
|| mode
== DFmode
|| mode
== SDmode
|| mode
== DDmode
;
8450 /* The ABI says that record types with a single member are treated
8451 just like that member would be. */
8452 while (TREE_CODE (type
) == RECORD_TYPE
)
8454 tree field
, single
= NULL_TREE
;
8456 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
8458 if (TREE_CODE (field
) != FIELD_DECL
)
8461 if (single
== NULL_TREE
)
8462 single
= TREE_TYPE (field
);
8467 if (single
== NULL_TREE
)
8473 return TREE_CODE (type
) == REAL_TYPE
;
8476 /* Return true if a function argument of type TYPE and mode MODE
8477 is to be passed in an integer register, or a pair of integer
8478 registers, if available. */
8481 s390_function_arg_integer (enum machine_mode mode
, const_tree type
)
8483 int size
= s390_function_arg_size (mode
, type
);
8487 /* No type info available for some library calls ... */
8489 return GET_MODE_CLASS (mode
) == MODE_INT
8490 || (TARGET_SOFT_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
));
8492 /* We accept small integral (and similar) types. */
8493 if (INTEGRAL_TYPE_P (type
)
8494 || POINTER_TYPE_P (type
)
8495 || TREE_CODE (type
) == NULLPTR_TYPE
8496 || TREE_CODE (type
) == OFFSET_TYPE
8497 || (TARGET_SOFT_FLOAT
&& TREE_CODE (type
) == REAL_TYPE
))
8500 /* We also accept structs of size 1, 2, 4, 8 that are not
8501 passed in floating-point registers. */
8502 if (AGGREGATE_TYPE_P (type
)
8503 && exact_log2 (size
) >= 0
8504 && !s390_function_arg_float (mode
, type
))
8510 /* Return 1 if a function argument of type TYPE and mode MODE
8511 is to be passed by reference. The ABI specifies that only
8512 structures of size 1, 2, 4, or 8 bytes are passed by value,
8513 all other structures (and complex numbers) are passed by
8517 s390_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED
,
8518 enum machine_mode mode
, const_tree type
,
8519 bool named ATTRIBUTE_UNUSED
)
8521 int size
= s390_function_arg_size (mode
, type
);
8527 if (AGGREGATE_TYPE_P (type
) && exact_log2 (size
) < 0)
8530 if (TREE_CODE (type
) == COMPLEX_TYPE
8531 || TREE_CODE (type
) == VECTOR_TYPE
)
8538 /* Update the data in CUM to advance over an argument of mode MODE and
8539 data type TYPE. (TYPE is null for libcalls where that information
8540 may not be available.). The boolean NAMED specifies whether the
8541 argument is a named argument (as opposed to an unnamed argument
8542 matching an ellipsis). */
8545 s390_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
8546 const_tree type
, bool named ATTRIBUTE_UNUSED
)
8548 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
8550 if (s390_function_arg_float (mode
, type
))
8554 else if (s390_function_arg_integer (mode
, type
))
8556 int size
= s390_function_arg_size (mode
, type
);
8557 cum
->gprs
+= ((size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
);
8563 /* Define where to put the arguments to a function.
8564 Value is zero to push the argument on the stack,
8565 or a hard register in which to store the argument.
8567 MODE is the argument's machine mode.
8568 TYPE is the data type of the argument (as a tree).
8569 This is null for libcalls where that information may
8571 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8572 the preceding args and about the function being called.
8573 NAMED is nonzero if this argument is a named parameter
8574 (otherwise it is an extra parameter matching an ellipsis).
8576 On S/390, we use general purpose registers 2 through 6 to
8577 pass integer, pointer, and certain structure arguments, and
8578 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
8579 to pass floating point arguments. All remaining arguments
8580 are pushed to the stack. */
8583 s390_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
8584 const_tree type
, bool named ATTRIBUTE_UNUSED
)
8586 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
8588 if (s390_function_arg_float (mode
, type
))
8590 if (cum
->fprs
+ 1 > FP_ARG_NUM_REG
)
8593 return gen_rtx_REG (mode
, cum
->fprs
+ 16);
8595 else if (s390_function_arg_integer (mode
, type
))
8597 int size
= s390_function_arg_size (mode
, type
);
8598 int n_gprs
= (size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
;
8600 if (cum
->gprs
+ n_gprs
> GP_ARG_NUM_REG
)
8602 else if (n_gprs
== 1 || UNITS_PER_WORD
== UNITS_PER_LONG
)
8603 return gen_rtx_REG (mode
, cum
->gprs
+ 2);
8604 else if (n_gprs
== 2)
8606 rtvec p
= rtvec_alloc (2);
8609 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, cum
->gprs
+ 2),
8612 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, cum
->gprs
+ 3),
8615 return gen_rtx_PARALLEL (mode
, p
);
8619 /* After the real arguments, expand_call calls us once again
8620 with a void_type_node type. Whatever we return here is
8621 passed as operand 2 to the call expanders.
8623 We don't need this feature ... */
8624 else if (type
== void_type_node
)
8630 /* Return true if return values of type TYPE should be returned
8631 in a memory buffer whose address is passed by the caller as
8632 hidden first argument. */
8635 s390_return_in_memory (const_tree type
, const_tree fundecl ATTRIBUTE_UNUSED
)
8637 /* We accept small integral (and similar) types. */
8638 if (INTEGRAL_TYPE_P (type
)
8639 || POINTER_TYPE_P (type
)
8640 || TREE_CODE (type
) == OFFSET_TYPE
8641 || TREE_CODE (type
) == REAL_TYPE
)
8642 return int_size_in_bytes (type
) > 8;
8644 /* Aggregates and similar constructs are always returned
8646 if (AGGREGATE_TYPE_P (type
)
8647 || TREE_CODE (type
) == COMPLEX_TYPE
8648 || TREE_CODE (type
) == VECTOR_TYPE
)
8651 /* ??? We get called on all sorts of random stuff from
8652 aggregate_value_p. We can't abort, but it's not clear
8653 what's safe to return. Pretend it's a struct I guess. */
8657 /* Function arguments and return values are promoted to word size. */
8659 static enum machine_mode
8660 s390_promote_function_mode (const_tree type
, enum machine_mode mode
,
8662 const_tree fntype ATTRIBUTE_UNUSED
,
8663 int for_return ATTRIBUTE_UNUSED
)
8665 if (INTEGRAL_MODE_P (mode
)
8666 && GET_MODE_SIZE (mode
) < UNITS_PER_LONG
)
8668 if (type
!= NULL_TREE
&& POINTER_TYPE_P (type
))
8669 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
8676 /* Define where to return a (scalar) value of type RET_TYPE.
8677 If RET_TYPE is null, define where to return a (scalar)
8678 value of mode MODE from a libcall. */
8681 s390_function_and_libcall_value (enum machine_mode mode
,
8682 const_tree ret_type
,
8683 const_tree fntype_or_decl
,
8684 bool outgoing ATTRIBUTE_UNUSED
)
8686 /* For normal functions perform the promotion as
8687 promote_function_mode would do. */
8690 int unsignedp
= TYPE_UNSIGNED (ret_type
);
8691 mode
= promote_function_mode (ret_type
, mode
, &unsignedp
,
8695 gcc_assert (GET_MODE_CLASS (mode
) == MODE_INT
|| SCALAR_FLOAT_MODE_P (mode
));
8696 gcc_assert (GET_MODE_SIZE (mode
) <= 8);
8698 if (TARGET_HARD_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
))
8699 return gen_rtx_REG (mode
, 16);
8700 else if (GET_MODE_SIZE (mode
) <= UNITS_PER_LONG
8701 || UNITS_PER_LONG
== UNITS_PER_WORD
)
8702 return gen_rtx_REG (mode
, 2);
8703 else if (GET_MODE_SIZE (mode
) == 2 * UNITS_PER_LONG
)
8705 /* This case is triggered when returning a 64 bit value with
8706 -m31 -mzarch. Although the value would fit into a single
8707 register it has to be forced into a 32 bit register pair in
8708 order to match the ABI. */
8709 rtvec p
= rtvec_alloc (2);
8712 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, 2), const0_rtx
);
8714 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, 3), GEN_INT (4));
8716 return gen_rtx_PARALLEL (mode
, p
);
8722 /* Define where to return a scalar return value of type RET_TYPE. */
8725 s390_function_value (const_tree ret_type
, const_tree fn_decl_or_type
,
8728 return s390_function_and_libcall_value (TYPE_MODE (ret_type
), ret_type
,
8729 fn_decl_or_type
, outgoing
);
8732 /* Define where to return a scalar libcall return value of mode
8736 s390_libcall_value (enum machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
8738 return s390_function_and_libcall_value (mode
, NULL_TREE
,
8743 /* Create and return the va_list datatype.
8745 On S/390, va_list is an array type equivalent to
8747 typedef struct __va_list_tag
8751 void *__overflow_arg_area;
8752 void *__reg_save_area;
8755 where __gpr and __fpr hold the number of general purpose
8756 or floating point arguments used up to now, respectively,
8757 __overflow_arg_area points to the stack location of the
8758 next argument passed on the stack, and __reg_save_area
8759 always points to the start of the register area in the
8760 call frame of the current function. The function prologue
8761 saves all registers used for argument passing into this
8762 area if the function uses variable arguments. */
8765 s390_build_builtin_va_list (void)
8767 tree f_gpr
, f_fpr
, f_ovf
, f_sav
, record
, type_decl
;
8769 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
8772 build_decl (BUILTINS_LOCATION
,
8773 TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
8775 f_gpr
= build_decl (BUILTINS_LOCATION
,
8776 FIELD_DECL
, get_identifier ("__gpr"),
8777 long_integer_type_node
);
8778 f_fpr
= build_decl (BUILTINS_LOCATION
,
8779 FIELD_DECL
, get_identifier ("__fpr"),
8780 long_integer_type_node
);
8781 f_ovf
= build_decl (BUILTINS_LOCATION
,
8782 FIELD_DECL
, get_identifier ("__overflow_arg_area"),
8784 f_sav
= build_decl (BUILTINS_LOCATION
,
8785 FIELD_DECL
, get_identifier ("__reg_save_area"),
8788 va_list_gpr_counter_field
= f_gpr
;
8789 va_list_fpr_counter_field
= f_fpr
;
8791 DECL_FIELD_CONTEXT (f_gpr
) = record
;
8792 DECL_FIELD_CONTEXT (f_fpr
) = record
;
8793 DECL_FIELD_CONTEXT (f_ovf
) = record
;
8794 DECL_FIELD_CONTEXT (f_sav
) = record
;
8796 TYPE_STUB_DECL (record
) = type_decl
;
8797 TYPE_NAME (record
) = type_decl
;
8798 TYPE_FIELDS (record
) = f_gpr
;
8799 DECL_CHAIN (f_gpr
) = f_fpr
;
8800 DECL_CHAIN (f_fpr
) = f_ovf
;
8801 DECL_CHAIN (f_ovf
) = f_sav
;
8803 layout_type (record
);
8805 /* The correct type is an array type of one element. */
8806 return build_array_type (record
, build_index_type (size_zero_node
));
8809 /* Implement va_start by filling the va_list structure VALIST.
8810 STDARG_P is always true, and ignored.
8811 NEXTARG points to the first anonymous stack argument.
8813 The following global variables are used to initialize
8814 the va_list structure:
8817 holds number of gprs and fprs used for named arguments.
8818 crtl->args.arg_offset_rtx:
8819 holds the offset of the first anonymous stack argument
8820 (relative to the virtual arg pointer). */
8823 s390_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
8825 HOST_WIDE_INT n_gpr
, n_fpr
;
8827 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
8828 tree gpr
, fpr
, ovf
, sav
, t
;
8830 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
8831 f_fpr
= DECL_CHAIN (f_gpr
);
8832 f_ovf
= DECL_CHAIN (f_fpr
);
8833 f_sav
= DECL_CHAIN (f_ovf
);
8835 valist
= build_simple_mem_ref (valist
);
8836 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
8837 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
8838 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
8839 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
8841 /* Count number of gp and fp argument registers used. */
8843 n_gpr
= crtl
->args
.info
.gprs
;
8844 n_fpr
= crtl
->args
.info
.fprs
;
8846 if (cfun
->va_list_gpr_size
)
8848 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
8849 build_int_cst (NULL_TREE
, n_gpr
));
8850 TREE_SIDE_EFFECTS (t
) = 1;
8851 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8854 if (cfun
->va_list_fpr_size
)
8856 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
8857 build_int_cst (NULL_TREE
, n_fpr
));
8858 TREE_SIDE_EFFECTS (t
) = 1;
8859 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8862 /* Find the overflow area. */
8863 if (n_gpr
+ cfun
->va_list_gpr_size
> GP_ARG_NUM_REG
8864 || n_fpr
+ cfun
->va_list_fpr_size
> FP_ARG_NUM_REG
)
8866 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
8868 off
= INTVAL (crtl
->args
.arg_offset_rtx
);
8869 off
= off
< 0 ? 0 : off
;
8870 if (TARGET_DEBUG_ARG
)
8871 fprintf (stderr
, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
8872 (int)n_gpr
, (int)n_fpr
, off
);
8874 t
= fold_build_pointer_plus_hwi (t
, off
);
8876 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
8877 TREE_SIDE_EFFECTS (t
) = 1;
8878 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8881 /* Find the register save area. */
8882 if ((cfun
->va_list_gpr_size
&& n_gpr
< GP_ARG_NUM_REG
)
8883 || (cfun
->va_list_fpr_size
&& n_fpr
< FP_ARG_NUM_REG
))
8885 t
= make_tree (TREE_TYPE (sav
), return_address_pointer_rtx
);
8886 t
= fold_build_pointer_plus_hwi (t
, -RETURN_REGNUM
* UNITS_PER_LONG
);
8888 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
8889 TREE_SIDE_EFFECTS (t
) = 1;
8890 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8894 /* Implement va_arg by updating the va_list structure
8895 VALIST as required to retrieve an argument of type
8896 TYPE, and returning that argument.
8898 Generates code equivalent to:
8900 if (integral value) {
8901 if (size <= 4 && args.gpr < 5 ||
8902 size > 4 && args.gpr < 4 )
8903 ret = args.reg_save_area[args.gpr+8]
8905 ret = *args.overflow_arg_area++;
8906 } else if (float value) {
8908 ret = args.reg_save_area[args.fpr+64]
8910 ret = *args.overflow_arg_area++;
8911 } else if (aggregate value) {
8913 ret = *args.reg_save_area[args.gpr]
8915 ret = **args.overflow_arg_area++;
8919 s390_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
8920 gimple_seq
*post_p ATTRIBUTE_UNUSED
)
8922 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
8923 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
8924 int indirect_p
, size
, n_reg
, sav_ofs
, sav_scale
, max_reg
;
8925 tree lab_false
, lab_over
, addr
;
8927 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
8928 f_fpr
= DECL_CHAIN (f_gpr
);
8929 f_ovf
= DECL_CHAIN (f_fpr
);
8930 f_sav
= DECL_CHAIN (f_ovf
);
8932 valist
= build_va_arg_indirect_ref (valist
);
8933 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
8934 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
8935 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
8937 /* The tree for args* cannot be shared between gpr/fpr and ovf since
8938 both appear on a lhs. */
8939 valist
= unshare_expr (valist
);
8940 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
8942 size
= int_size_in_bytes (type
);
8944 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
8946 if (TARGET_DEBUG_ARG
)
8948 fprintf (stderr
, "va_arg: aggregate type");
8952 /* Aggregates are passed by reference. */
8957 /* kernel stack layout on 31 bit: It is assumed here that no padding
8958 will be added by s390_frame_info because for va_args always an even
8959 number of gprs has to be saved r15-r2 = 14 regs. */
8960 sav_ofs
= 2 * UNITS_PER_LONG
;
8961 sav_scale
= UNITS_PER_LONG
;
8962 size
= UNITS_PER_LONG
;
8963 max_reg
= GP_ARG_NUM_REG
- n_reg
;
8965 else if (s390_function_arg_float (TYPE_MODE (type
), type
))
8967 if (TARGET_DEBUG_ARG
)
8969 fprintf (stderr
, "va_arg: float type");
8973 /* FP args go in FP registers, if present. */
8977 sav_ofs
= 16 * UNITS_PER_LONG
;
8979 max_reg
= FP_ARG_NUM_REG
- n_reg
;
8983 if (TARGET_DEBUG_ARG
)
8985 fprintf (stderr
, "va_arg: other type");
8989 /* Otherwise into GP registers. */
8992 n_reg
= (size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
;
8994 /* kernel stack layout on 31 bit: It is assumed here that no padding
8995 will be added by s390_frame_info because for va_args always an even
8996 number of gprs has to be saved r15-r2 = 14 regs. */
8997 sav_ofs
= 2 * UNITS_PER_LONG
;
8999 if (size
< UNITS_PER_LONG
)
9000 sav_ofs
+= UNITS_PER_LONG
- size
;
9002 sav_scale
= UNITS_PER_LONG
;
9003 max_reg
= GP_ARG_NUM_REG
- n_reg
;
9006 /* Pull the value out of the saved registers ... */
9008 lab_false
= create_artificial_label (UNKNOWN_LOCATION
);
9009 lab_over
= create_artificial_label (UNKNOWN_LOCATION
);
9010 addr
= create_tmp_var (ptr_type_node
, "addr");
9012 t
= fold_convert (TREE_TYPE (reg
), size_int (max_reg
));
9013 t
= build2 (GT_EXPR
, boolean_type_node
, reg
, t
);
9014 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
9015 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
9016 gimplify_and_add (t
, pre_p
);
9018 t
= fold_build_pointer_plus_hwi (sav
, sav_ofs
);
9019 u
= build2 (MULT_EXPR
, TREE_TYPE (reg
), reg
,
9020 fold_convert (TREE_TYPE (reg
), size_int (sav_scale
)));
9021 t
= fold_build_pointer_plus (t
, u
);
9023 gimplify_assign (addr
, t
, pre_p
);
9025 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
9027 gimple_seq_add_stmt (pre_p
, gimple_build_label (lab_false
));
9030 /* ... Otherwise out of the overflow area. */
9033 if (size
< UNITS_PER_LONG
)
9034 t
= fold_build_pointer_plus_hwi (t
, UNITS_PER_LONG
- size
);
9036 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
9038 gimplify_assign (addr
, t
, pre_p
);
9040 t
= fold_build_pointer_plus_hwi (t
, size
);
9041 gimplify_assign (ovf
, t
, pre_p
);
9043 gimple_seq_add_stmt (pre_p
, gimple_build_label (lab_over
));
9046 /* Increment register save count. */
9048 u
= build2 (PREINCREMENT_EXPR
, TREE_TYPE (reg
), reg
,
9049 fold_convert (TREE_TYPE (reg
), size_int (n_reg
)));
9050 gimplify_and_add (u
, pre_p
);
9054 t
= build_pointer_type_for_mode (build_pointer_type (type
),
9056 addr
= fold_convert (t
, addr
);
9057 addr
= build_va_arg_indirect_ref (addr
);
9061 t
= build_pointer_type_for_mode (type
, ptr_mode
, true);
9062 addr
= fold_convert (t
, addr
);
9065 return build_va_arg_indirect_ref (addr
);
9073 S390_BUILTIN_THREAD_POINTER
,
9074 S390_BUILTIN_SET_THREAD_POINTER
,
9079 static enum insn_code
const code_for_builtin_64
[S390_BUILTIN_max
] = {
9084 static enum insn_code
const code_for_builtin_31
[S390_BUILTIN_max
] = {
9090 s390_init_builtins (void)
9094 ftype
= build_function_type_list (ptr_type_node
, NULL_TREE
);
9095 add_builtin_function ("__builtin_thread_pointer", ftype
,
9096 S390_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
9099 ftype
= build_function_type_list (void_type_node
, ptr_type_node
, NULL_TREE
);
9100 add_builtin_function ("__builtin_set_thread_pointer", ftype
,
9101 S390_BUILTIN_SET_THREAD_POINTER
, BUILT_IN_MD
,
9105 /* Expand an expression EXP that calls a built-in function,
9106 with result going to TARGET if that's convenient
9107 (and in mode MODE if that's convenient).
9108 SUBTARGET may be used as the target for computing one of EXP's operands.
9109 IGNORE is nonzero if the value is to be ignored. */
9112 s390_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
9113 enum machine_mode mode ATTRIBUTE_UNUSED
,
9114 int ignore ATTRIBUTE_UNUSED
)
9118 enum insn_code
const *code_for_builtin
=
9119 TARGET_64BIT
? code_for_builtin_64
: code_for_builtin_31
;
9121 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
9122 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
9123 enum insn_code icode
;
9124 rtx op
[MAX_ARGS
], pat
;
9128 call_expr_arg_iterator iter
;
9130 if (fcode
>= S390_BUILTIN_max
)
9131 internal_error ("bad builtin fcode");
9132 icode
= code_for_builtin
[fcode
];
9134 internal_error ("bad builtin fcode");
9136 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
9139 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
9141 const struct insn_operand_data
*insn_op
;
9143 if (arg
== error_mark_node
)
9145 if (arity
> MAX_ARGS
)
9148 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
9150 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, EXPAND_NORMAL
);
9152 if (!(*insn_op
->predicate
) (op
[arity
], insn_op
->mode
))
9153 op
[arity
] = copy_to_mode_reg (insn_op
->mode
, op
[arity
]);
9159 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
9161 || GET_MODE (target
) != tmode
9162 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
9163 target
= gen_reg_rtx (tmode
);
9169 pat
= GEN_FCN (icode
) (target
);
9173 pat
= GEN_FCN (icode
) (target
, op
[0]);
9175 pat
= GEN_FCN (icode
) (op
[0]);
9178 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
9194 /* Output assembly code for the trampoline template to
9197 On S/390, we use gpr 1 internally in the trampoline code;
9198 gpr 0 is used to hold the static chain. */
9201 s390_asm_trampoline_template (FILE *file
)
9204 op
[0] = gen_rtx_REG (Pmode
, 0);
9205 op
[1] = gen_rtx_REG (Pmode
, 1);
9209 output_asm_insn ("basr\t%1,0", op
); /* 2 byte */
9210 output_asm_insn ("lmg\t%0,%1,14(%1)", op
); /* 6 byte */
9211 output_asm_insn ("br\t%1", op
); /* 2 byte */
9212 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 10));
9216 output_asm_insn ("basr\t%1,0", op
); /* 2 byte */
9217 output_asm_insn ("lm\t%0,%1,6(%1)", op
); /* 4 byte */
9218 output_asm_insn ("br\t%1", op
); /* 2 byte */
9219 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 8));
9223 /* Emit RTL insns to initialize the variable parts of a trampoline.
9224 FNADDR is an RTX for the address of the function's pure code.
9225 CXT is an RTX for the static chain value for the function. */
9228 s390_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
9230 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
9233 emit_block_move (m_tramp
, assemble_trampoline_template (),
9234 GEN_INT (2 * UNITS_PER_LONG
), BLOCK_OP_NORMAL
);
9236 mem
= adjust_address (m_tramp
, Pmode
, 2 * UNITS_PER_LONG
);
9237 emit_move_insn (mem
, cxt
);
9238 mem
= adjust_address (m_tramp
, Pmode
, 3 * UNITS_PER_LONG
);
9239 emit_move_insn (mem
, fnaddr
);
9242 /* Output assembler code to FILE to increment profiler label # LABELNO
9243 for profiling a function entry. */
9246 s390_function_profiler (FILE *file
, int labelno
)
9251 ASM_GENERATE_INTERNAL_LABEL (label
, "LP", labelno
);
9253 fprintf (file
, "# function profiler \n");
9255 op
[0] = gen_rtx_REG (Pmode
, RETURN_REGNUM
);
9256 op
[1] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
9257 op
[1] = gen_rtx_MEM (Pmode
, plus_constant (op
[1], UNITS_PER_LONG
));
9259 op
[2] = gen_rtx_REG (Pmode
, 1);
9260 op
[3] = gen_rtx_SYMBOL_REF (Pmode
, label
);
9261 SYMBOL_REF_FLAGS (op
[3]) = SYMBOL_FLAG_LOCAL
;
9263 op
[4] = gen_rtx_SYMBOL_REF (Pmode
, "_mcount");
9266 op
[4] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[4]), UNSPEC_PLT
);
9267 op
[4] = gen_rtx_CONST (Pmode
, op
[4]);
9272 output_asm_insn ("stg\t%0,%1", op
);
9273 output_asm_insn ("larl\t%2,%3", op
);
9274 output_asm_insn ("brasl\t%0,%4", op
);
9275 output_asm_insn ("lg\t%0,%1", op
);
9279 op
[6] = gen_label_rtx ();
9281 output_asm_insn ("st\t%0,%1", op
);
9282 output_asm_insn ("bras\t%2,%l6", op
);
9283 output_asm_insn (".long\t%4", op
);
9284 output_asm_insn (".long\t%3", op
);
9285 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
9286 output_asm_insn ("l\t%0,0(%2)", op
);
9287 output_asm_insn ("l\t%2,4(%2)", op
);
9288 output_asm_insn ("basr\t%0,%0", op
);
9289 output_asm_insn ("l\t%0,%1", op
);
9293 op
[5] = gen_label_rtx ();
9294 op
[6] = gen_label_rtx ();
9296 output_asm_insn ("st\t%0,%1", op
);
9297 output_asm_insn ("bras\t%2,%l6", op
);
9298 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[5]));
9299 output_asm_insn (".long\t%4-%l5", op
);
9300 output_asm_insn (".long\t%3-%l5", op
);
9301 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
9302 output_asm_insn ("lr\t%0,%2", op
);
9303 output_asm_insn ("a\t%0,0(%2)", op
);
9304 output_asm_insn ("a\t%2,4(%2)", op
);
9305 output_asm_insn ("basr\t%0,%0", op
);
9306 output_asm_insn ("l\t%0,%1", op
);
9310 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
9311 into its SYMBOL_REF_FLAGS. */
9314 s390_encode_section_info (tree decl
, rtx rtl
, int first
)
9316 default_encode_section_info (decl
, rtl
, first
);
9318 if (TREE_CODE (decl
) == VAR_DECL
)
9320 /* If a variable has a forced alignment to < 2 bytes, mark it
9321 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
9323 if (DECL_USER_ALIGN (decl
) && DECL_ALIGN (decl
) < 16)
9324 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_ALIGN1
;
9325 if (!DECL_SIZE (decl
)
9326 || !DECL_ALIGN (decl
)
9327 || !host_integerp (DECL_SIZE (decl
), 0)
9328 || (DECL_ALIGN (decl
) <= 64
9329 && DECL_ALIGN (decl
) != tree_low_cst (DECL_SIZE (decl
), 0)))
9330 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED
;
9333 /* Literal pool references don't have a decl so they are handled
9334 differently here. We rely on the information in the MEM_ALIGN
9335 entry to decide upon natural alignment. */
9337 && GET_CODE (XEXP (rtl
, 0)) == SYMBOL_REF
9338 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl
, 0))
9339 && (MEM_ALIGN (rtl
) == 0
9340 || GET_MODE_BITSIZE (GET_MODE (rtl
)) == 0
9341 || MEM_ALIGN (rtl
) < GET_MODE_BITSIZE (GET_MODE (rtl
))))
9342 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED
;
9345 /* Output thunk to FILE that implements a C++ virtual function call (with
9346 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
9347 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
9348 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
9349 relative to the resulting this pointer. */
9352 s390_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
9353 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
9359 /* Make sure unwind info is emitted for the thunk if needed. */
9360 final_start_function (emit_barrier (), file
, 1);
9362 /* Operand 0 is the target function. */
9363 op
[0] = XEXP (DECL_RTL (function
), 0);
9364 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (op
[0]))
9367 op
[0] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[0]),
9368 TARGET_64BIT
? UNSPEC_PLT
: UNSPEC_GOT
);
9369 op
[0] = gen_rtx_CONST (Pmode
, op
[0]);
9372 /* Operand 1 is the 'this' pointer. */
9373 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
9374 op
[1] = gen_rtx_REG (Pmode
, 3);
9376 op
[1] = gen_rtx_REG (Pmode
, 2);
9378 /* Operand 2 is the delta. */
9379 op
[2] = GEN_INT (delta
);
9381 /* Operand 3 is the vcall_offset. */
9382 op
[3] = GEN_INT (vcall_offset
);
9384 /* Operand 4 is the temporary register. */
9385 op
[4] = gen_rtx_REG (Pmode
, 1);
9387 /* Operands 5 to 8 can be used as labels. */
9393 /* Operand 9 can be used for temporary register. */
9396 /* Generate code. */
9399 /* Setup literal pool pointer if required. */
9400 if ((!DISP_IN_RANGE (delta
)
9401 && !CONST_OK_FOR_K (delta
)
9402 && !CONST_OK_FOR_Os (delta
))
9403 || (!DISP_IN_RANGE (vcall_offset
)
9404 && !CONST_OK_FOR_K (vcall_offset
)
9405 && !CONST_OK_FOR_Os (vcall_offset
)))
9407 op
[5] = gen_label_rtx ();
9408 output_asm_insn ("larl\t%4,%5", op
);
9411 /* Add DELTA to this pointer. */
9414 if (CONST_OK_FOR_J (delta
))
9415 output_asm_insn ("la\t%1,%2(%1)", op
);
9416 else if (DISP_IN_RANGE (delta
))
9417 output_asm_insn ("lay\t%1,%2(%1)", op
);
9418 else if (CONST_OK_FOR_K (delta
))
9419 output_asm_insn ("aghi\t%1,%2", op
);
9420 else if (CONST_OK_FOR_Os (delta
))
9421 output_asm_insn ("agfi\t%1,%2", op
);
9424 op
[6] = gen_label_rtx ();
9425 output_asm_insn ("agf\t%1,%6-%5(%4)", op
);
9429 /* Perform vcall adjustment. */
9432 if (DISP_IN_RANGE (vcall_offset
))
9434 output_asm_insn ("lg\t%4,0(%1)", op
);
9435 output_asm_insn ("ag\t%1,%3(%4)", op
);
9437 else if (CONST_OK_FOR_K (vcall_offset
))
9439 output_asm_insn ("lghi\t%4,%3", op
);
9440 output_asm_insn ("ag\t%4,0(%1)", op
);
9441 output_asm_insn ("ag\t%1,0(%4)", op
);
9443 else if (CONST_OK_FOR_Os (vcall_offset
))
9445 output_asm_insn ("lgfi\t%4,%3", op
);
9446 output_asm_insn ("ag\t%4,0(%1)", op
);
9447 output_asm_insn ("ag\t%1,0(%4)", op
);
9451 op
[7] = gen_label_rtx ();
9452 output_asm_insn ("llgf\t%4,%7-%5(%4)", op
);
9453 output_asm_insn ("ag\t%4,0(%1)", op
);
9454 output_asm_insn ("ag\t%1,0(%4)", op
);
9458 /* Jump to target. */
9459 output_asm_insn ("jg\t%0", op
);
9461 /* Output literal pool if required. */
9464 output_asm_insn (".align\t4", op
);
9465 targetm
.asm_out
.internal_label (file
, "L",
9466 CODE_LABEL_NUMBER (op
[5]));
9470 targetm
.asm_out
.internal_label (file
, "L",
9471 CODE_LABEL_NUMBER (op
[6]));
9472 output_asm_insn (".long\t%2", op
);
9476 targetm
.asm_out
.internal_label (file
, "L",
9477 CODE_LABEL_NUMBER (op
[7]));
9478 output_asm_insn (".long\t%3", op
);
9483 /* Setup base pointer if required. */
9485 || (!DISP_IN_RANGE (delta
)
9486 && !CONST_OK_FOR_K (delta
)
9487 && !CONST_OK_FOR_Os (delta
))
9488 || (!DISP_IN_RANGE (delta
)
9489 && !CONST_OK_FOR_K (vcall_offset
)
9490 && !CONST_OK_FOR_Os (vcall_offset
)))
9492 op
[5] = gen_label_rtx ();
9493 output_asm_insn ("basr\t%4,0", op
);
9494 targetm
.asm_out
.internal_label (file
, "L",
9495 CODE_LABEL_NUMBER (op
[5]));
9498 /* Add DELTA to this pointer. */
9501 if (CONST_OK_FOR_J (delta
))
9502 output_asm_insn ("la\t%1,%2(%1)", op
);
9503 else if (DISP_IN_RANGE (delta
))
9504 output_asm_insn ("lay\t%1,%2(%1)", op
);
9505 else if (CONST_OK_FOR_K (delta
))
9506 output_asm_insn ("ahi\t%1,%2", op
);
9507 else if (CONST_OK_FOR_Os (delta
))
9508 output_asm_insn ("afi\t%1,%2", op
);
9511 op
[6] = gen_label_rtx ();
9512 output_asm_insn ("a\t%1,%6-%5(%4)", op
);
9516 /* Perform vcall adjustment. */
9519 if (CONST_OK_FOR_J (vcall_offset
))
9521 output_asm_insn ("l\t%4,0(%1)", op
);
9522 output_asm_insn ("a\t%1,%3(%4)", op
);
9524 else if (DISP_IN_RANGE (vcall_offset
))
9526 output_asm_insn ("l\t%4,0(%1)", op
);
9527 output_asm_insn ("ay\t%1,%3(%4)", op
);
9529 else if (CONST_OK_FOR_K (vcall_offset
))
9531 output_asm_insn ("lhi\t%4,%3", op
);
9532 output_asm_insn ("a\t%4,0(%1)", op
);
9533 output_asm_insn ("a\t%1,0(%4)", op
);
9535 else if (CONST_OK_FOR_Os (vcall_offset
))
9537 output_asm_insn ("iilf\t%4,%3", op
);
9538 output_asm_insn ("a\t%4,0(%1)", op
);
9539 output_asm_insn ("a\t%1,0(%4)", op
);
9543 op
[7] = gen_label_rtx ();
9544 output_asm_insn ("l\t%4,%7-%5(%4)", op
);
9545 output_asm_insn ("a\t%4,0(%1)", op
);
9546 output_asm_insn ("a\t%1,0(%4)", op
);
9549 /* We had to clobber the base pointer register.
9550 Re-setup the base pointer (with a different base). */
9551 op
[5] = gen_label_rtx ();
9552 output_asm_insn ("basr\t%4,0", op
);
9553 targetm
.asm_out
.internal_label (file
, "L",
9554 CODE_LABEL_NUMBER (op
[5]));
9557 /* Jump to target. */
9558 op
[8] = gen_label_rtx ();
9561 output_asm_insn ("l\t%4,%8-%5(%4)", op
);
9563 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
9564 /* We cannot call through .plt, since .plt requires %r12 loaded. */
9565 else if (flag_pic
== 1)
9567 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
9568 output_asm_insn ("l\t%4,%0(%4)", op
);
9570 else if (flag_pic
== 2)
9572 op
[9] = gen_rtx_REG (Pmode
, 0);
9573 output_asm_insn ("l\t%9,%8-4-%5(%4)", op
);
9574 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
9575 output_asm_insn ("ar\t%4,%9", op
);
9576 output_asm_insn ("l\t%4,0(%4)", op
);
9579 output_asm_insn ("br\t%4", op
);
9581 /* Output literal pool. */
9582 output_asm_insn (".align\t4", op
);
9584 if (nonlocal
&& flag_pic
== 2)
9585 output_asm_insn (".long\t%0", op
);
9588 op
[0] = gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
9589 SYMBOL_REF_FLAGS (op
[0]) = SYMBOL_FLAG_LOCAL
;
9592 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[8]));
9594 output_asm_insn (".long\t%0", op
);
9596 output_asm_insn (".long\t%0-%5", op
);
9600 targetm
.asm_out
.internal_label (file
, "L",
9601 CODE_LABEL_NUMBER (op
[6]));
9602 output_asm_insn (".long\t%2", op
);
9606 targetm
.asm_out
.internal_label (file
, "L",
9607 CODE_LABEL_NUMBER (op
[7]));
9608 output_asm_insn (".long\t%3", op
);
9611 final_end_function ();
9615 s390_valid_pointer_mode (enum machine_mode mode
)
9617 return (mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
));
9620 /* Checks whether the given CALL_EXPR would use a caller
9621 saved register. This is used to decide whether sibling call
9622 optimization could be performed on the respective function
9626 s390_call_saved_register_used (tree call_expr
)
9628 CUMULATIVE_ARGS cum_v
;
9629 cumulative_args_t cum
;
9631 enum machine_mode mode
;
9636 INIT_CUMULATIVE_ARGS (cum_v
, NULL
, NULL
, 0, 0);
9637 cum
= pack_cumulative_args (&cum_v
);
9639 for (i
= 0; i
< call_expr_nargs (call_expr
); i
++)
9641 parameter
= CALL_EXPR_ARG (call_expr
, i
);
9642 gcc_assert (parameter
);
9644 /* For an undeclared variable passed as parameter we will get
9645 an ERROR_MARK node here. */
9646 if (TREE_CODE (parameter
) == ERROR_MARK
)
9649 type
= TREE_TYPE (parameter
);
9652 mode
= TYPE_MODE (type
);
9655 if (pass_by_reference (&cum_v
, mode
, type
, true))
9658 type
= build_pointer_type (type
);
9661 parm_rtx
= s390_function_arg (cum
, mode
, type
, 0);
9663 s390_function_arg_advance (cum
, mode
, type
, 0);
9668 if (REG_P (parm_rtx
))
9671 reg
< HARD_REGNO_NREGS (REGNO (parm_rtx
), GET_MODE (parm_rtx
));
9673 if (!call_used_regs
[reg
+ REGNO (parm_rtx
)])
9677 if (GET_CODE (parm_rtx
) == PARALLEL
)
9681 for (i
= 0; i
< XVECLEN (parm_rtx
, 0); i
++)
9683 rtx r
= XEXP (XVECEXP (parm_rtx
, 0, i
), 0);
9685 gcc_assert (REG_P (r
));
9688 reg
< HARD_REGNO_NREGS (REGNO (r
), GET_MODE (r
));
9690 if (!call_used_regs
[reg
+ REGNO (r
)])
9699 /* Return true if the given call expression can be
9700 turned into a sibling call.
9701 DECL holds the declaration of the function to be called whereas
9702 EXP is the call expression itself. */
9705 s390_function_ok_for_sibcall (tree decl
, tree exp
)
9707 /* The TPF epilogue uses register 1. */
9708 if (TARGET_TPF_PROFILING
)
9711 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
9712 which would have to be restored before the sibcall. */
9713 if (!TARGET_64BIT
&& flag_pic
&& decl
&& !targetm
.binds_local_p (decl
))
9716 /* Register 6 on s390 is available as an argument register but unfortunately
9717 "caller saved". This makes functions needing this register for arguments
9718 not suitable for sibcalls. */
9719 return !s390_call_saved_register_used (exp
);
9722 /* Return the fixed registers used for condition codes. */
9725 s390_fixed_condition_code_regs (unsigned int *p1
, unsigned int *p2
)
9728 *p2
= INVALID_REGNUM
;
9733 /* This function is used by the call expanders of the machine description.
9734 It emits the call insn itself together with the necessary operations
9735 to adjust the target address and returns the emitted insn.
9736 ADDR_LOCATION is the target address rtx
9737 TLS_CALL the location of the thread-local symbol
9738 RESULT_REG the register where the result of the call should be stored
9739 RETADDR_REG the register where the return address should be stored
9740 If this parameter is NULL_RTX the call is considered
9741 to be a sibling call. */
9744 s390_emit_call (rtx addr_location
, rtx tls_call
, rtx result_reg
,
9747 bool plt_call
= false;
9753 /* Direct function calls need special treatment. */
9754 if (GET_CODE (addr_location
) == SYMBOL_REF
)
9756 /* When calling a global routine in PIC mode, we must
9757 replace the symbol itself with the PLT stub. */
9758 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (addr_location
))
9760 if (retaddr_reg
!= NULL_RTX
)
9762 addr_location
= gen_rtx_UNSPEC (Pmode
,
9763 gen_rtvec (1, addr_location
),
9765 addr_location
= gen_rtx_CONST (Pmode
, addr_location
);
9769 /* For -fpic code the PLT entries might use r12 which is
9770 call-saved. Therefore we cannot do a sibcall when
9771 calling directly using a symbol ref. When reaching
9772 this point we decided (in s390_function_ok_for_sibcall)
9773 to do a sibcall for a function pointer but one of the
9774 optimizers was able to get rid of the function pointer
9775 by propagating the symbol ref into the call. This
9776 optimization is illegal for S/390 so we turn the direct
9777 call into a indirect call again. */
9778 addr_location
= force_reg (Pmode
, addr_location
);
9781 /* Unless we can use the bras(l) insn, force the
9782 routine address into a register. */
9783 if (!TARGET_SMALL_EXEC
&& !TARGET_CPU_ZARCH
)
9786 addr_location
= legitimize_pic_address (addr_location
, 0);
9788 addr_location
= force_reg (Pmode
, addr_location
);
9792 /* If it is already an indirect call or the code above moved the
9793 SYMBOL_REF to somewhere else make sure the address can be found in
9795 if (retaddr_reg
== NULL_RTX
9796 && GET_CODE (addr_location
) != SYMBOL_REF
9799 emit_move_insn (gen_rtx_REG (Pmode
, SIBCALL_REGNUM
), addr_location
);
9800 addr_location
= gen_rtx_REG (Pmode
, SIBCALL_REGNUM
);
9803 addr_location
= gen_rtx_MEM (QImode
, addr_location
);
9804 call
= gen_rtx_CALL (VOIDmode
, addr_location
, const0_rtx
);
9806 if (result_reg
!= NULL_RTX
)
9807 call
= gen_rtx_SET (VOIDmode
, result_reg
, call
);
9809 if (retaddr_reg
!= NULL_RTX
)
9811 clobber
= gen_rtx_CLOBBER (VOIDmode
, retaddr_reg
);
9813 if (tls_call
!= NULL_RTX
)
9814 vec
= gen_rtvec (3, call
, clobber
,
9815 gen_rtx_USE (VOIDmode
, tls_call
));
9817 vec
= gen_rtvec (2, call
, clobber
);
9819 call
= gen_rtx_PARALLEL (VOIDmode
, vec
);
9822 insn
= emit_call_insn (call
);
9824 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
9825 if ((!TARGET_64BIT
&& plt_call
) || tls_call
!= NULL_RTX
)
9827 /* s390_function_ok_for_sibcall should
9828 have denied sibcalls in this case. */
9829 gcc_assert (retaddr_reg
!= NULL_RTX
);
9831 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
9836 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
9839 s390_conditional_register_usage (void)
9845 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
9846 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
9848 if (TARGET_CPU_ZARCH
)
9850 fixed_regs
[BASE_REGNUM
] = 0;
9851 call_used_regs
[BASE_REGNUM
] = 0;
9852 fixed_regs
[RETURN_REGNUM
] = 0;
9853 call_used_regs
[RETURN_REGNUM
] = 0;
9857 for (i
= 24; i
< 32; i
++)
9858 call_used_regs
[i
] = call_really_used_regs
[i
] = 0;
9862 for (i
= 18; i
< 20; i
++)
9863 call_used_regs
[i
] = call_really_used_regs
[i
] = 0;
9866 if (TARGET_SOFT_FLOAT
)
9868 for (i
= 16; i
< 32; i
++)
9869 call_used_regs
[i
] = fixed_regs
[i
] = 1;
9873 /* Corresponding function to eh_return expander. */
9875 static GTY(()) rtx s390_tpf_eh_return_symbol
;
9877 s390_emit_tpf_eh_return (rtx target
)
9881 if (!s390_tpf_eh_return_symbol
)
9882 s390_tpf_eh_return_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tpf_eh_return");
9884 reg
= gen_rtx_REG (Pmode
, 2);
9886 emit_move_insn (reg
, target
);
9887 insn
= s390_emit_call (s390_tpf_eh_return_symbol
, NULL_RTX
, reg
,
9888 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
9889 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
9891 emit_move_insn (EH_RETURN_HANDLER_RTX
, reg
);
9894 /* Rework the prologue/epilogue to avoid saving/restoring
9895 registers unnecessarily. */
9898 s390_optimize_prologue (void)
9900 rtx insn
, new_insn
, next_insn
;
9902 /* Do a final recompute of the frame-related data. */
9904 s390_update_frame_layout ();
9906 /* If all special registers are in fact used, there's nothing we
9907 can do, so no point in walking the insn list. */
9909 if (cfun_frame_layout
.first_save_gpr
<= BASE_REGNUM
9910 && cfun_frame_layout
.last_save_gpr
>= BASE_REGNUM
9911 && (TARGET_CPU_ZARCH
9912 || (cfun_frame_layout
.first_save_gpr
<= RETURN_REGNUM
9913 && cfun_frame_layout
.last_save_gpr
>= RETURN_REGNUM
)))
9916 /* Search for prologue/epilogue insns and replace them. */
9918 for (insn
= get_insns (); insn
; insn
= next_insn
)
9920 int first
, last
, off
;
9921 rtx set
, base
, offset
;
9923 next_insn
= NEXT_INSN (insn
);
9925 if (GET_CODE (insn
) != INSN
)
9928 if (GET_CODE (PATTERN (insn
)) == PARALLEL
9929 && store_multiple_operation (PATTERN (insn
), VOIDmode
))
9931 set
= XVECEXP (PATTERN (insn
), 0, 0);
9932 first
= REGNO (SET_SRC (set
));
9933 last
= first
+ XVECLEN (PATTERN (insn
), 0) - 1;
9934 offset
= const0_rtx
;
9935 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
9936 off
= INTVAL (offset
);
9938 if (GET_CODE (base
) != REG
|| off
< 0)
9940 if (cfun_frame_layout
.first_save_gpr
!= -1
9941 && (cfun_frame_layout
.first_save_gpr
< first
9942 || cfun_frame_layout
.last_save_gpr
> last
))
9944 if (REGNO (base
) != STACK_POINTER_REGNUM
9945 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
9947 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
9950 if (cfun_frame_layout
.first_save_gpr
!= -1)
9952 new_insn
= save_gprs (base
,
9953 off
+ (cfun_frame_layout
.first_save_gpr
9954 - first
) * UNITS_PER_LONG
,
9955 cfun_frame_layout
.first_save_gpr
,
9956 cfun_frame_layout
.last_save_gpr
);
9957 new_insn
= emit_insn_before (new_insn
, insn
);
9958 INSN_ADDRESSES_NEW (new_insn
, -1);
9965 if (cfun_frame_layout
.first_save_gpr
== -1
9966 && GET_CODE (PATTERN (insn
)) == SET
9967 && GET_CODE (SET_SRC (PATTERN (insn
))) == REG
9968 && (REGNO (SET_SRC (PATTERN (insn
))) == BASE_REGNUM
9969 || (!TARGET_CPU_ZARCH
9970 && REGNO (SET_SRC (PATTERN (insn
))) == RETURN_REGNUM
))
9971 && GET_CODE (SET_DEST (PATTERN (insn
))) == MEM
)
9973 set
= PATTERN (insn
);
9974 first
= REGNO (SET_SRC (set
));
9975 offset
= const0_rtx
;
9976 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
9977 off
= INTVAL (offset
);
9979 if (GET_CODE (base
) != REG
|| off
< 0)
9981 if (REGNO (base
) != STACK_POINTER_REGNUM
9982 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
9989 if (GET_CODE (PATTERN (insn
)) == PARALLEL
9990 && load_multiple_operation (PATTERN (insn
), VOIDmode
))
9992 set
= XVECEXP (PATTERN (insn
), 0, 0);
9993 first
= REGNO (SET_DEST (set
));
9994 last
= first
+ XVECLEN (PATTERN (insn
), 0) - 1;
9995 offset
= const0_rtx
;
9996 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
9997 off
= INTVAL (offset
);
9999 if (GET_CODE (base
) != REG
|| off
< 0)
10001 if (cfun_frame_layout
.first_restore_gpr
!= -1
10002 && (cfun_frame_layout
.first_restore_gpr
< first
10003 || cfun_frame_layout
.last_restore_gpr
> last
))
10005 if (REGNO (base
) != STACK_POINTER_REGNUM
10006 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
10008 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
10011 if (cfun_frame_layout
.first_restore_gpr
!= -1)
10013 new_insn
= restore_gprs (base
,
10014 off
+ (cfun_frame_layout
.first_restore_gpr
10015 - first
) * UNITS_PER_LONG
,
10016 cfun_frame_layout
.first_restore_gpr
,
10017 cfun_frame_layout
.last_restore_gpr
);
10018 new_insn
= emit_insn_before (new_insn
, insn
);
10019 INSN_ADDRESSES_NEW (new_insn
, -1);
10022 remove_insn (insn
);
10026 if (cfun_frame_layout
.first_restore_gpr
== -1
10027 && GET_CODE (PATTERN (insn
)) == SET
10028 && GET_CODE (SET_DEST (PATTERN (insn
))) == REG
10029 && (REGNO (SET_DEST (PATTERN (insn
))) == BASE_REGNUM
10030 || (!TARGET_CPU_ZARCH
10031 && REGNO (SET_DEST (PATTERN (insn
))) == RETURN_REGNUM
))
10032 && GET_CODE (SET_SRC (PATTERN (insn
))) == MEM
)
10034 set
= PATTERN (insn
);
10035 first
= REGNO (SET_DEST (set
));
10036 offset
= const0_rtx
;
10037 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
10038 off
= INTVAL (offset
);
10040 if (GET_CODE (base
) != REG
|| off
< 0)
10042 if (REGNO (base
) != STACK_POINTER_REGNUM
10043 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
10046 remove_insn (insn
);
10052 /* On z10 and later the dynamic branch prediction must see the
10053 backward jump within a certain windows. If not it falls back to
10054 the static prediction. This function rearranges the loop backward
10055 branch in a way which makes the static prediction always correct.
10056 The function returns true if it added an instruction. */
10058 s390_fix_long_loop_prediction (rtx insn
)
10060 rtx set
= single_set (insn
);
10061 rtx code_label
, label_ref
, new_label
;
10067 /* This will exclude branch on count and branch on index patterns
10068 since these are correctly statically predicted. */
10070 || SET_DEST (set
) != pc_rtx
10071 || GET_CODE (SET_SRC(set
)) != IF_THEN_ELSE
)
10074 label_ref
= (GET_CODE (XEXP (SET_SRC (set
), 1)) == LABEL_REF
?
10075 XEXP (SET_SRC (set
), 1) : XEXP (SET_SRC (set
), 2));
10077 gcc_assert (GET_CODE (label_ref
) == LABEL_REF
);
10079 code_label
= XEXP (label_ref
, 0);
10081 if (INSN_ADDRESSES (INSN_UID (code_label
)) == -1
10082 || INSN_ADDRESSES (INSN_UID (insn
)) == -1
10083 || (INSN_ADDRESSES (INSN_UID (insn
))
10084 - INSN_ADDRESSES (INSN_UID (code_label
)) < PREDICT_DISTANCE
))
10087 for (distance
= 0, cur_insn
= PREV_INSN (insn
);
10088 distance
< PREDICT_DISTANCE
- 6;
10089 distance
+= get_attr_length (cur_insn
), cur_insn
= PREV_INSN (cur_insn
))
10090 if (!cur_insn
|| JUMP_P (cur_insn
) || LABEL_P (cur_insn
))
10093 new_label
= gen_label_rtx ();
10094 uncond_jump
= emit_jump_insn_after (
10095 gen_rtx_SET (VOIDmode
, pc_rtx
,
10096 gen_rtx_LABEL_REF (VOIDmode
, code_label
)),
10098 emit_label_after (new_label
, uncond_jump
);
10100 tmp
= XEXP (SET_SRC (set
), 1);
10101 XEXP (SET_SRC (set
), 1) = XEXP (SET_SRC (set
), 2);
10102 XEXP (SET_SRC (set
), 2) = tmp
;
10103 INSN_CODE (insn
) = -1;
10105 XEXP (label_ref
, 0) = new_label
;
10106 JUMP_LABEL (insn
) = new_label
;
10107 JUMP_LABEL (uncond_jump
) = code_label
;
10112 /* Returns 1 if INSN reads the value of REG for purposes not related
10113 to addressing of memory, and 0 otherwise. */
10115 s390_non_addr_reg_read_p (rtx reg
, rtx insn
)
10117 return reg_referenced_p (reg
, PATTERN (insn
))
10118 && !reg_used_in_mem_p (REGNO (reg
), PATTERN (insn
));
10121 /* Starting from INSN find_cond_jump looks downwards in the insn
10122 stream for a single jump insn which is the last user of the
10123 condition code set in INSN. */
10125 find_cond_jump (rtx insn
)
10127 for (; insn
; insn
= NEXT_INSN (insn
))
10131 if (LABEL_P (insn
))
10134 if (!JUMP_P (insn
))
10136 if (reg_mentioned_p (gen_rtx_REG (CCmode
, CC_REGNUM
), insn
))
10141 /* This will be triggered by a return. */
10142 if (GET_CODE (PATTERN (insn
)) != SET
)
10145 gcc_assert (SET_DEST (PATTERN (insn
)) == pc_rtx
);
10146 ite
= SET_SRC (PATTERN (insn
));
10148 if (GET_CODE (ite
) != IF_THEN_ELSE
)
10151 cc
= XEXP (XEXP (ite
, 0), 0);
10152 if (!REG_P (cc
) || !CC_REGNO_P (REGNO (cc
)))
10155 if (find_reg_note (insn
, REG_DEAD
, cc
))
10163 /* Swap the condition in COND and the operands in OP0 and OP1 so that
10164 the semantics does not change. If NULL_RTX is passed as COND the
10165 function tries to find the conditional jump starting with INSN. */
10167 s390_swap_cmp (rtx cond
, rtx
*op0
, rtx
*op1
, rtx insn
)
10171 if (cond
== NULL_RTX
)
10173 rtx jump
= find_cond_jump (NEXT_INSN (insn
));
10174 jump
= jump
? single_set (jump
) : NULL_RTX
;
10176 if (jump
== NULL_RTX
)
10179 cond
= XEXP (XEXP (jump
, 1), 0);
10184 PUT_CODE (cond
, swap_condition (GET_CODE (cond
)));
10187 /* On z10, instructions of the compare-and-branch family have the
10188 property to access the register occurring as second operand with
10189 its bits complemented. If such a compare is grouped with a second
10190 instruction that accesses the same register non-complemented, and
10191 if that register's value is delivered via a bypass, then the
10192 pipeline recycles, thereby causing significant performance decline.
10193 This function locates such situations and exchanges the two
10194 operands of the compare. The function return true whenever it
10197 s390_z10_optimize_cmp (rtx insn
)
10199 rtx prev_insn
, next_insn
;
10200 bool insn_added_p
= false;
10201 rtx cond
, *op0
, *op1
;
10203 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
10205 /* Handle compare and branch and branch on count
10207 rtx pattern
= single_set (insn
);
10210 || SET_DEST (pattern
) != pc_rtx
10211 || GET_CODE (SET_SRC (pattern
)) != IF_THEN_ELSE
)
10214 cond
= XEXP (SET_SRC (pattern
), 0);
10215 op0
= &XEXP (cond
, 0);
10216 op1
= &XEXP (cond
, 1);
10218 else if (GET_CODE (PATTERN (insn
)) == SET
)
10222 /* Handle normal compare instructions. */
10223 src
= SET_SRC (PATTERN (insn
));
10224 dest
= SET_DEST (PATTERN (insn
));
10227 || !CC_REGNO_P (REGNO (dest
))
10228 || GET_CODE (src
) != COMPARE
)
10231 /* s390_swap_cmp will try to find the conditional
10232 jump when passing NULL_RTX as condition. */
10234 op0
= &XEXP (src
, 0);
10235 op1
= &XEXP (src
, 1);
10240 if (!REG_P (*op0
) || !REG_P (*op1
))
10243 if (GET_MODE_CLASS (GET_MODE (*op0
)) != MODE_INT
)
10246 /* Swap the COMPARE arguments and its mask if there is a
10247 conflicting access in the previous insn. */
10248 prev_insn
= prev_active_insn (insn
);
10249 if (prev_insn
!= NULL_RTX
&& INSN_P (prev_insn
)
10250 && reg_referenced_p (*op1
, PATTERN (prev_insn
)))
10251 s390_swap_cmp (cond
, op0
, op1
, insn
);
10253 /* Check if there is a conflict with the next insn. If there
10254 was no conflict with the previous insn, then swap the
10255 COMPARE arguments and its mask. If we already swapped
10256 the operands, or if swapping them would cause a conflict
10257 with the previous insn, issue a NOP after the COMPARE in
10258 order to separate the two instuctions. */
10259 next_insn
= next_active_insn (insn
);
10260 if (next_insn
!= NULL_RTX
&& INSN_P (next_insn
)
10261 && s390_non_addr_reg_read_p (*op1
, next_insn
))
10263 if (prev_insn
!= NULL_RTX
&& INSN_P (prev_insn
)
10264 && s390_non_addr_reg_read_p (*op0
, prev_insn
))
10266 if (REGNO (*op1
) == 0)
10267 emit_insn_after (gen_nop1 (), insn
);
10269 emit_insn_after (gen_nop (), insn
);
10270 insn_added_p
= true;
10273 s390_swap_cmp (cond
, op0
, op1
, insn
);
10275 return insn_added_p
;
10278 /* Perform machine-dependent processing. */
10283 bool pool_overflow
= false;
10285 /* Make sure all splits have been performed; splits after
10286 machine_dependent_reorg might confuse insn length counts. */
10287 split_all_insns_noflow ();
10289 /* Install the main literal pool and the associated base
10290 register load insns.
10292 In addition, there are two problematic situations we need
10295 - the literal pool might be > 4096 bytes in size, so that
10296 some of its elements cannot be directly accessed
10298 - a branch target might be > 64K away from the branch, so that
10299 it is not possible to use a PC-relative instruction.
10301 To fix those, we split the single literal pool into multiple
10302 pool chunks, reloading the pool base register at various
10303 points throughout the function to ensure it always points to
10304 the pool chunk the following code expects, and / or replace
10305 PC-relative branches by absolute branches.
10307 However, the two problems are interdependent: splitting the
10308 literal pool can move a branch further away from its target,
10309 causing the 64K limit to overflow, and on the other hand,
10310 replacing a PC-relative branch by an absolute branch means
10311 we need to put the branch target address into the literal
10312 pool, possibly causing it to overflow.
10314 So, we loop trying to fix up both problems until we manage
10315 to satisfy both conditions at the same time. Note that the
10316 loop is guaranteed to terminate as every pass of the loop
10317 strictly decreases the total number of PC-relative branches
10318 in the function. (This is not completely true as there
10319 might be branch-over-pool insns introduced by chunkify_start.
10320 Those never need to be split however.) */
10324 struct constant_pool
*pool
= NULL
;
10326 /* Collect the literal pool. */
10327 if (!pool_overflow
)
10329 pool
= s390_mainpool_start ();
10331 pool_overflow
= true;
10334 /* If literal pool overflowed, start to chunkify it. */
10336 pool
= s390_chunkify_start ();
10338 /* Split out-of-range branches. If this has created new
10339 literal pool entries, cancel current chunk list and
10340 recompute it. zSeries machines have large branch
10341 instructions, so we never need to split a branch. */
10342 if (!TARGET_CPU_ZARCH
&& s390_split_branches ())
10345 s390_chunkify_cancel (pool
);
10347 s390_mainpool_cancel (pool
);
10352 /* If we made it up to here, both conditions are satisfied.
10353 Finish up literal pool related changes. */
10355 s390_chunkify_finish (pool
);
10357 s390_mainpool_finish (pool
);
10359 /* We're done splitting branches. */
10360 cfun
->machine
->split_branches_pending_p
= false;
10364 /* Generate out-of-pool execute target insns. */
10365 if (TARGET_CPU_ZARCH
)
10367 rtx insn
, label
, target
;
10369 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10371 label
= s390_execute_label (insn
);
10375 gcc_assert (label
!= const0_rtx
);
10377 target
= emit_label (XEXP (label
, 0));
10378 INSN_ADDRESSES_NEW (target
, -1);
10380 target
= emit_insn (s390_execute_target (insn
));
10381 INSN_ADDRESSES_NEW (target
, -1);
10385 /* Try to optimize prologue and epilogue further. */
10386 s390_optimize_prologue ();
10388 /* Walk over the insns and do some >=z10 specific changes. */
10389 if (s390_tune
== PROCESSOR_2097_Z10
10390 || s390_tune
== PROCESSOR_2817_Z196
)
10393 bool insn_added_p
= false;
10395 /* The insn lengths and addresses have to be up to date for the
10396 following manipulations. */
10397 shorten_branches (get_insns ());
10399 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10401 if (!INSN_P (insn
) || INSN_CODE (insn
) <= 0)
10405 insn_added_p
|= s390_fix_long_loop_prediction (insn
);
10407 if ((GET_CODE (PATTERN (insn
)) == PARALLEL
10408 || GET_CODE (PATTERN (insn
)) == SET
)
10409 && s390_tune
== PROCESSOR_2097_Z10
)
10410 insn_added_p
|= s390_z10_optimize_cmp (insn
);
10413 /* Adjust branches if we added new instructions. */
10415 shorten_branches (get_insns ());
10419 /* Return true if INSN is a fp load insn writing register REGNO. */
10421 s390_fpload_toreg (rtx insn
, unsigned int regno
)
10424 enum attr_type flag
= s390_safe_attr_type (insn
);
10426 if (flag
!= TYPE_FLOADSF
&& flag
!= TYPE_FLOADDF
)
10429 set
= single_set (insn
);
10431 if (set
== NULL_RTX
)
10434 if (!REG_P (SET_DEST (set
)) || !MEM_P (SET_SRC (set
)))
10437 if (REGNO (SET_DEST (set
)) != regno
)
10443 /* This value describes the distance to be avoided between an
10444 aritmetic fp instruction and an fp load writing the same register.
10445 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
10446 fine but the exact value has to be avoided. Otherwise the FP
10447 pipeline will throw an exception causing a major penalty. */
10448 #define Z10_EARLYLOAD_DISTANCE 7
10450 /* Rearrange the ready list in order to avoid the situation described
10451 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
10452 moved to the very end of the ready list. */
10454 s390_z10_prevent_earlyload_conflicts (rtx
*ready
, int *nready_p
)
10456 unsigned int regno
;
10457 int nready
= *nready_p
;
10462 enum attr_type flag
;
10465 /* Skip DISTANCE - 1 active insns. */
10466 for (insn
= last_scheduled_insn
, distance
= Z10_EARLYLOAD_DISTANCE
- 1;
10467 distance
> 0 && insn
!= NULL_RTX
;
10468 distance
--, insn
= prev_active_insn (insn
))
10469 if (CALL_P (insn
) || JUMP_P (insn
))
10472 if (insn
== NULL_RTX
)
10475 set
= single_set (insn
);
10477 if (set
== NULL_RTX
|| !REG_P (SET_DEST (set
))
10478 || GET_MODE_CLASS (GET_MODE (SET_DEST (set
))) != MODE_FLOAT
)
10481 flag
= s390_safe_attr_type (insn
);
10483 if (flag
== TYPE_FLOADSF
|| flag
== TYPE_FLOADDF
)
10486 regno
= REGNO (SET_DEST (set
));
10489 while (!s390_fpload_toreg (ready
[i
], regno
) && i
> 0)
10496 memmove (&ready
[1], &ready
[0], sizeof (rtx
) * i
);
10500 /* This function is called via hook TARGET_SCHED_REORDER before
10501 issueing one insn from list READY which contains *NREADYP entries.
10502 For target z10 it reorders load instructions to avoid early load
10503 conflicts in the floating point pipeline */
10505 s390_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
10506 rtx
*ready
, int *nreadyp
, int clock ATTRIBUTE_UNUSED
)
10508 if (s390_tune
== PROCESSOR_2097_Z10
)
10509 if (reload_completed
&& *nreadyp
> 1)
10510 s390_z10_prevent_earlyload_conflicts (ready
, nreadyp
);
10512 return s390_issue_rate ();
10515 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
10516 the scheduler has issued INSN. It stores the last issued insn into
10517 last_scheduled_insn in order to make it available for
10518 s390_sched_reorder. */
10520 s390_sched_variable_issue (FILE *file ATTRIBUTE_UNUSED
,
10521 int verbose ATTRIBUTE_UNUSED
,
10522 rtx insn
, int more
)
10524 last_scheduled_insn
= insn
;
10526 if (GET_CODE (PATTERN (insn
)) != USE
10527 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
10534 s390_sched_init (FILE *file ATTRIBUTE_UNUSED
,
10535 int verbose ATTRIBUTE_UNUSED
,
10536 int max_ready ATTRIBUTE_UNUSED
)
10538 last_scheduled_insn
= NULL_RTX
;
10541 /* This function checks the whole of insn X for memory references. The
10542 function always returns zero because the framework it is called
10543 from would stop recursively analyzing the insn upon a return value
10544 other than zero. The real result of this function is updating
10545 counter variable MEM_COUNT. */
10547 check_dpu (rtx
*x
, unsigned *mem_count
)
10549 if (*x
!= NULL_RTX
&& MEM_P (*x
))
10554 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
10555 a new number struct loop *loop should be unrolled if tuned for cpus with
10556 a built-in stride prefetcher.
10557 The loop is analyzed for memory accesses by calling check_dpu for
10558 each rtx of the loop. Depending on the loop_depth and the amount of
10559 memory accesses a new number <=nunroll is returned to improve the
10560 behaviour of the hardware prefetch unit. */
10562 s390_loop_unroll_adjust (unsigned nunroll
, struct loop
*loop
)
10567 unsigned mem_count
= 0;
10569 if (s390_tune
!= PROCESSOR_2097_Z10
&& s390_tune
!= PROCESSOR_2817_Z196
)
10572 /* Count the number of memory references within the loop body. */
10573 bbs
= get_loop_body (loop
);
10574 for (i
= 0; i
< loop
->num_nodes
; i
++)
10576 for (insn
= BB_HEAD (bbs
[i
]); insn
!= BB_END (bbs
[i
]); insn
= NEXT_INSN (insn
))
10577 if (INSN_P (insn
) && INSN_CODE (insn
) != -1)
10578 for_each_rtx (&insn
, (rtx_function
) check_dpu
, &mem_count
);
10582 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
10583 if (mem_count
== 0)
10586 switch (loop_depth(loop
))
10589 return MIN (nunroll
, 28 / mem_count
);
10591 return MIN (nunroll
, 22 / mem_count
);
10593 return MIN (nunroll
, 16 / mem_count
);
10597 /* Initialize GCC target structure. */
10599 #undef TARGET_ASM_ALIGNED_HI_OP
10600 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10601 #undef TARGET_ASM_ALIGNED_DI_OP
10602 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10603 #undef TARGET_ASM_INTEGER
10604 #define TARGET_ASM_INTEGER s390_assemble_integer
10606 #undef TARGET_ASM_OPEN_PAREN
10607 #define TARGET_ASM_OPEN_PAREN ""
10609 #undef TARGET_ASM_CLOSE_PAREN
10610 #define TARGET_ASM_CLOSE_PAREN ""
10612 #undef TARGET_OPTION_OVERRIDE
10613 #define TARGET_OPTION_OVERRIDE s390_option_override
10615 #undef TARGET_ENCODE_SECTION_INFO
10616 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
10618 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10619 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10622 #undef TARGET_HAVE_TLS
10623 #define TARGET_HAVE_TLS true
10625 #undef TARGET_CANNOT_FORCE_CONST_MEM
10626 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
10628 #undef TARGET_DELEGITIMIZE_ADDRESS
10629 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
10631 #undef TARGET_LEGITIMIZE_ADDRESS
10632 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
10634 #undef TARGET_RETURN_IN_MEMORY
10635 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
10637 #undef TARGET_INIT_BUILTINS
10638 #define TARGET_INIT_BUILTINS s390_init_builtins
10639 #undef TARGET_EXPAND_BUILTIN
10640 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
10642 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
10643 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA s390_output_addr_const_extra
10645 #undef TARGET_ASM_OUTPUT_MI_THUNK
10646 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
10647 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10648 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
10650 #undef TARGET_SCHED_ADJUST_PRIORITY
10651 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
10652 #undef TARGET_SCHED_ISSUE_RATE
10653 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
10654 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10655 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
10657 #undef TARGET_SCHED_VARIABLE_ISSUE
10658 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
10659 #undef TARGET_SCHED_REORDER
10660 #define TARGET_SCHED_REORDER s390_sched_reorder
10661 #undef TARGET_SCHED_INIT
10662 #define TARGET_SCHED_INIT s390_sched_init
10664 #undef TARGET_CANNOT_COPY_INSN_P
10665 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
10666 #undef TARGET_RTX_COSTS
10667 #define TARGET_RTX_COSTS s390_rtx_costs
10668 #undef TARGET_ADDRESS_COST
10669 #define TARGET_ADDRESS_COST s390_address_cost
10670 #undef TARGET_REGISTER_MOVE_COST
10671 #define TARGET_REGISTER_MOVE_COST s390_register_move_cost
10672 #undef TARGET_MEMORY_MOVE_COST
10673 #define TARGET_MEMORY_MOVE_COST s390_memory_move_cost
10675 #undef TARGET_MACHINE_DEPENDENT_REORG
10676 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
10678 #undef TARGET_VALID_POINTER_MODE
10679 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
10681 #undef TARGET_BUILD_BUILTIN_VA_LIST
10682 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
10683 #undef TARGET_EXPAND_BUILTIN_VA_START
10684 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
10685 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
10686 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
10688 #undef TARGET_PROMOTE_FUNCTION_MODE
10689 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
10690 #undef TARGET_PASS_BY_REFERENCE
10691 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
10693 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10694 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
10695 #undef TARGET_FUNCTION_ARG
10696 #define TARGET_FUNCTION_ARG s390_function_arg
10697 #undef TARGET_FUNCTION_ARG_ADVANCE
10698 #define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance
10699 #undef TARGET_FUNCTION_VALUE
10700 #define TARGET_FUNCTION_VALUE s390_function_value
10701 #undef TARGET_LIBCALL_VALUE
10702 #define TARGET_LIBCALL_VALUE s390_libcall_value
10704 #undef TARGET_FIXED_CONDITION_CODE_REGS
10705 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
10707 #undef TARGET_CC_MODES_COMPATIBLE
10708 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
10710 #undef TARGET_INVALID_WITHIN_DOLOOP
10711 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
10714 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
10715 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
10718 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10719 #undef TARGET_MANGLE_TYPE
10720 #define TARGET_MANGLE_TYPE s390_mangle_type
10723 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10724 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10726 #undef TARGET_PREFERRED_RELOAD_CLASS
10727 #define TARGET_PREFERRED_RELOAD_CLASS s390_preferred_reload_class
10729 #undef TARGET_SECONDARY_RELOAD
10730 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
10732 #undef TARGET_LIBGCC_CMP_RETURN_MODE
10733 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
10735 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
10736 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
10738 #undef TARGET_LEGITIMATE_ADDRESS_P
10739 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
10741 #undef TARGET_LEGITIMATE_CONSTANT_P
10742 #define TARGET_LEGITIMATE_CONSTANT_P s390_legitimate_constant_p
10744 #undef TARGET_CAN_ELIMINATE
10745 #define TARGET_CAN_ELIMINATE s390_can_eliminate
10747 #undef TARGET_CONDITIONAL_REGISTER_USAGE
10748 #define TARGET_CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage
10750 #undef TARGET_LOOP_UNROLL_ADJUST
10751 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
10753 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
10754 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
10755 #undef TARGET_TRAMPOLINE_INIT
10756 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
10758 #undef TARGET_UNWIND_WORD_MODE
10759 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
10761 struct gcc_target targetm
= TARGET_INITIALIZER
;
10763 #include "gt-s390.h"