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[thirdparty/gcc.git] / gcc / config / s390 / s390.c
1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999-2015 Free Software Foundation, Inc.
3 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 Ulrich Weigand (uweigand@de.ibm.com) and
5 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
6
7 This file is part of GCC.
8
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 3, or (at your option) any later
12 version.
13
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
22
23 #include "config.h"
24 #include "system.h"
25 #include "coretypes.h"
26 #include "tm.h"
27 #include "rtl.h"
28 #include "hash-set.h"
29 #include "machmode.h"
30 #include "vec.h"
31 #include "double-int.h"
32 #include "input.h"
33 #include "alias.h"
34 #include "symtab.h"
35 #include "wide-int.h"
36 #include "inchash.h"
37 #include "tree.h"
38 #include "fold-const.h"
39 #include "print-tree.h"
40 #include "stringpool.h"
41 #include "stor-layout.h"
42 #include "varasm.h"
43 #include "calls.h"
44 #include "tm_p.h"
45 #include "regs.h"
46 #include "hard-reg-set.h"
47 #include "insn-config.h"
48 #include "conditions.h"
49 #include "output.h"
50 #include "insn-attr.h"
51 #include "flags.h"
52 #include "except.h"
53 #include "function.h"
54 #include "recog.h"
55 #include "hashtab.h"
56 #include "statistics.h"
57 #include "real.h"
58 #include "fixed-value.h"
59 #include "expmed.h"
60 #include "dojump.h"
61 #include "explow.h"
62 #include "emit-rtl.h"
63 #include "stmt.h"
64 #include "expr.h"
65 #include "reload.h"
66 #include "diagnostic-core.h"
67 #include "predict.h"
68 #include "dominance.h"
69 #include "cfg.h"
70 #include "cfgrtl.h"
71 #include "cfganal.h"
72 #include "lcm.h"
73 #include "cfgbuild.h"
74 #include "cfgcleanup.h"
75 #include "basic-block.h"
76 #include "ggc.h"
77 #include "target.h"
78 #include "target-def.h"
79 #include "debug.h"
80 #include "langhooks.h"
81 #include "insn-codes.h"
82 #include "optabs.h"
83 #include "hash-table.h"
84 #include "tree-ssa-alias.h"
85 #include "internal-fn.h"
86 #include "gimple-fold.h"
87 #include "tree-eh.h"
88 #include "gimple-expr.h"
89 #include "is-a.h"
90 #include "gimple.h"
91 #include "gimplify.h"
92 #include "df.h"
93 #include "params.h"
94 #include "cfgloop.h"
95 #include "opts.h"
96 #include "tree-pass.h"
97 #include "context.h"
98 #include "builtins.h"
99 #include "rtl-iter.h"
100
101 /* Define the specific costs for a given cpu. */
102
103 struct processor_costs
104 {
105 /* multiplication */
106 const int m; /* cost of an M instruction. */
107 const int mghi; /* cost of an MGHI instruction. */
108 const int mh; /* cost of an MH instruction. */
109 const int mhi; /* cost of an MHI instruction. */
110 const int ml; /* cost of an ML instruction. */
111 const int mr; /* cost of an MR instruction. */
112 const int ms; /* cost of an MS instruction. */
113 const int msg; /* cost of an MSG instruction. */
114 const int msgf; /* cost of an MSGF instruction. */
115 const int msgfr; /* cost of an MSGFR instruction. */
116 const int msgr; /* cost of an MSGR instruction. */
117 const int msr; /* cost of an MSR instruction. */
118 const int mult_df; /* cost of multiplication in DFmode. */
119 const int mxbr;
120 /* square root */
121 const int sqxbr; /* cost of square root in TFmode. */
122 const int sqdbr; /* cost of square root in DFmode. */
123 const int sqebr; /* cost of square root in SFmode. */
124 /* multiply and add */
125 const int madbr; /* cost of multiply and add in DFmode. */
126 const int maebr; /* cost of multiply and add in SFmode. */
127 /* division */
128 const int dxbr;
129 const int ddbr;
130 const int debr;
131 const int dlgr;
132 const int dlr;
133 const int dr;
134 const int dsgfr;
135 const int dsgr;
136 };
137
138 const struct processor_costs *s390_cost;
139
140 static const
141 struct processor_costs z900_cost =
142 {
143 COSTS_N_INSNS (5), /* M */
144 COSTS_N_INSNS (10), /* MGHI */
145 COSTS_N_INSNS (5), /* MH */
146 COSTS_N_INSNS (4), /* MHI */
147 COSTS_N_INSNS (5), /* ML */
148 COSTS_N_INSNS (5), /* MR */
149 COSTS_N_INSNS (4), /* MS */
150 COSTS_N_INSNS (15), /* MSG */
151 COSTS_N_INSNS (7), /* MSGF */
152 COSTS_N_INSNS (7), /* MSGFR */
153 COSTS_N_INSNS (10), /* MSGR */
154 COSTS_N_INSNS (4), /* MSR */
155 COSTS_N_INSNS (7), /* multiplication in DFmode */
156 COSTS_N_INSNS (13), /* MXBR */
157 COSTS_N_INSNS (136), /* SQXBR */
158 COSTS_N_INSNS (44), /* SQDBR */
159 COSTS_N_INSNS (35), /* SQEBR */
160 COSTS_N_INSNS (18), /* MADBR */
161 COSTS_N_INSNS (13), /* MAEBR */
162 COSTS_N_INSNS (134), /* DXBR */
163 COSTS_N_INSNS (30), /* DDBR */
164 COSTS_N_INSNS (27), /* DEBR */
165 COSTS_N_INSNS (220), /* DLGR */
166 COSTS_N_INSNS (34), /* DLR */
167 COSTS_N_INSNS (34), /* DR */
168 COSTS_N_INSNS (32), /* DSGFR */
169 COSTS_N_INSNS (32), /* DSGR */
170 };
171
172 static const
173 struct processor_costs z990_cost =
174 {
175 COSTS_N_INSNS (4), /* M */
176 COSTS_N_INSNS (2), /* MGHI */
177 COSTS_N_INSNS (2), /* MH */
178 COSTS_N_INSNS (2), /* MHI */
179 COSTS_N_INSNS (4), /* ML */
180 COSTS_N_INSNS (4), /* MR */
181 COSTS_N_INSNS (5), /* MS */
182 COSTS_N_INSNS (6), /* MSG */
183 COSTS_N_INSNS (4), /* MSGF */
184 COSTS_N_INSNS (4), /* MSGFR */
185 COSTS_N_INSNS (4), /* MSGR */
186 COSTS_N_INSNS (4), /* MSR */
187 COSTS_N_INSNS (1), /* multiplication in DFmode */
188 COSTS_N_INSNS (28), /* MXBR */
189 COSTS_N_INSNS (130), /* SQXBR */
190 COSTS_N_INSNS (66), /* SQDBR */
191 COSTS_N_INSNS (38), /* SQEBR */
192 COSTS_N_INSNS (1), /* MADBR */
193 COSTS_N_INSNS (1), /* MAEBR */
194 COSTS_N_INSNS (60), /* DXBR */
195 COSTS_N_INSNS (40), /* DDBR */
196 COSTS_N_INSNS (26), /* DEBR */
197 COSTS_N_INSNS (176), /* DLGR */
198 COSTS_N_INSNS (31), /* DLR */
199 COSTS_N_INSNS (31), /* DR */
200 COSTS_N_INSNS (31), /* DSGFR */
201 COSTS_N_INSNS (31), /* DSGR */
202 };
203
204 static const
205 struct processor_costs z9_109_cost =
206 {
207 COSTS_N_INSNS (4), /* M */
208 COSTS_N_INSNS (2), /* MGHI */
209 COSTS_N_INSNS (2), /* MH */
210 COSTS_N_INSNS (2), /* MHI */
211 COSTS_N_INSNS (4), /* ML */
212 COSTS_N_INSNS (4), /* MR */
213 COSTS_N_INSNS (5), /* MS */
214 COSTS_N_INSNS (6), /* MSG */
215 COSTS_N_INSNS (4), /* MSGF */
216 COSTS_N_INSNS (4), /* MSGFR */
217 COSTS_N_INSNS (4), /* MSGR */
218 COSTS_N_INSNS (4), /* MSR */
219 COSTS_N_INSNS (1), /* multiplication in DFmode */
220 COSTS_N_INSNS (28), /* MXBR */
221 COSTS_N_INSNS (130), /* SQXBR */
222 COSTS_N_INSNS (66), /* SQDBR */
223 COSTS_N_INSNS (38), /* SQEBR */
224 COSTS_N_INSNS (1), /* MADBR */
225 COSTS_N_INSNS (1), /* MAEBR */
226 COSTS_N_INSNS (60), /* DXBR */
227 COSTS_N_INSNS (40), /* DDBR */
228 COSTS_N_INSNS (26), /* DEBR */
229 COSTS_N_INSNS (30), /* DLGR */
230 COSTS_N_INSNS (23), /* DLR */
231 COSTS_N_INSNS (23), /* DR */
232 COSTS_N_INSNS (24), /* DSGFR */
233 COSTS_N_INSNS (24), /* DSGR */
234 };
235
236 static const
237 struct processor_costs z10_cost =
238 {
239 COSTS_N_INSNS (10), /* M */
240 COSTS_N_INSNS (10), /* MGHI */
241 COSTS_N_INSNS (10), /* MH */
242 COSTS_N_INSNS (10), /* MHI */
243 COSTS_N_INSNS (10), /* ML */
244 COSTS_N_INSNS (10), /* MR */
245 COSTS_N_INSNS (10), /* MS */
246 COSTS_N_INSNS (10), /* MSG */
247 COSTS_N_INSNS (10), /* MSGF */
248 COSTS_N_INSNS (10), /* MSGFR */
249 COSTS_N_INSNS (10), /* MSGR */
250 COSTS_N_INSNS (10), /* MSR */
251 COSTS_N_INSNS (1) , /* multiplication in DFmode */
252 COSTS_N_INSNS (50), /* MXBR */
253 COSTS_N_INSNS (120), /* SQXBR */
254 COSTS_N_INSNS (52), /* SQDBR */
255 COSTS_N_INSNS (38), /* SQEBR */
256 COSTS_N_INSNS (1), /* MADBR */
257 COSTS_N_INSNS (1), /* MAEBR */
258 COSTS_N_INSNS (111), /* DXBR */
259 COSTS_N_INSNS (39), /* DDBR */
260 COSTS_N_INSNS (32), /* DEBR */
261 COSTS_N_INSNS (160), /* DLGR */
262 COSTS_N_INSNS (71), /* DLR */
263 COSTS_N_INSNS (71), /* DR */
264 COSTS_N_INSNS (71), /* DSGFR */
265 COSTS_N_INSNS (71), /* DSGR */
266 };
267
268 static const
269 struct processor_costs z196_cost =
270 {
271 COSTS_N_INSNS (7), /* M */
272 COSTS_N_INSNS (5), /* MGHI */
273 COSTS_N_INSNS (5), /* MH */
274 COSTS_N_INSNS (5), /* MHI */
275 COSTS_N_INSNS (7), /* ML */
276 COSTS_N_INSNS (7), /* MR */
277 COSTS_N_INSNS (6), /* MS */
278 COSTS_N_INSNS (8), /* MSG */
279 COSTS_N_INSNS (6), /* MSGF */
280 COSTS_N_INSNS (6), /* MSGFR */
281 COSTS_N_INSNS (8), /* MSGR */
282 COSTS_N_INSNS (6), /* MSR */
283 COSTS_N_INSNS (1) , /* multiplication in DFmode */
284 COSTS_N_INSNS (40), /* MXBR B+40 */
285 COSTS_N_INSNS (100), /* SQXBR B+100 */
286 COSTS_N_INSNS (42), /* SQDBR B+42 */
287 COSTS_N_INSNS (28), /* SQEBR B+28 */
288 COSTS_N_INSNS (1), /* MADBR B */
289 COSTS_N_INSNS (1), /* MAEBR B */
290 COSTS_N_INSNS (101), /* DXBR B+101 */
291 COSTS_N_INSNS (29), /* DDBR */
292 COSTS_N_INSNS (22), /* DEBR */
293 COSTS_N_INSNS (160), /* DLGR cracked */
294 COSTS_N_INSNS (160), /* DLR cracked */
295 COSTS_N_INSNS (160), /* DR expanded */
296 COSTS_N_INSNS (160), /* DSGFR cracked */
297 COSTS_N_INSNS (160), /* DSGR cracked */
298 };
299
300 static const
301 struct processor_costs zEC12_cost =
302 {
303 COSTS_N_INSNS (7), /* M */
304 COSTS_N_INSNS (5), /* MGHI */
305 COSTS_N_INSNS (5), /* MH */
306 COSTS_N_INSNS (5), /* MHI */
307 COSTS_N_INSNS (7), /* ML */
308 COSTS_N_INSNS (7), /* MR */
309 COSTS_N_INSNS (6), /* MS */
310 COSTS_N_INSNS (8), /* MSG */
311 COSTS_N_INSNS (6), /* MSGF */
312 COSTS_N_INSNS (6), /* MSGFR */
313 COSTS_N_INSNS (8), /* MSGR */
314 COSTS_N_INSNS (6), /* MSR */
315 COSTS_N_INSNS (1) , /* multiplication in DFmode */
316 COSTS_N_INSNS (40), /* MXBR B+40 */
317 COSTS_N_INSNS (100), /* SQXBR B+100 */
318 COSTS_N_INSNS (42), /* SQDBR B+42 */
319 COSTS_N_INSNS (28), /* SQEBR B+28 */
320 COSTS_N_INSNS (1), /* MADBR B */
321 COSTS_N_INSNS (1), /* MAEBR B */
322 COSTS_N_INSNS (131), /* DXBR B+131 */
323 COSTS_N_INSNS (29), /* DDBR */
324 COSTS_N_INSNS (22), /* DEBR */
325 COSTS_N_INSNS (160), /* DLGR cracked */
326 COSTS_N_INSNS (160), /* DLR cracked */
327 COSTS_N_INSNS (160), /* DR expanded */
328 COSTS_N_INSNS (160), /* DSGFR cracked */
329 COSTS_N_INSNS (160), /* DSGR cracked */
330 };
331
332 extern int reload_completed;
333
334 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
335 static rtx_insn *last_scheduled_insn;
336
337 /* Structure used to hold the components of a S/390 memory
338 address. A legitimate address on S/390 is of the general
339 form
340 base + index + displacement
341 where any of the components is optional.
342
343 base and index are registers of the class ADDR_REGS,
344 displacement is an unsigned 12-bit immediate constant. */
345
346 struct s390_address
347 {
348 rtx base;
349 rtx indx;
350 rtx disp;
351 bool pointer;
352 bool literal_pool;
353 };
354
355 /* The following structure is embedded in the machine
356 specific part of struct function. */
357
358 struct GTY (()) s390_frame_layout
359 {
360 /* Offset within stack frame. */
361 HOST_WIDE_INT gprs_offset;
362 HOST_WIDE_INT f0_offset;
363 HOST_WIDE_INT f4_offset;
364 HOST_WIDE_INT f8_offset;
365 HOST_WIDE_INT backchain_offset;
366
367 /* Number of first and last gpr where slots in the register
368 save area are reserved for. */
369 int first_save_gpr_slot;
370 int last_save_gpr_slot;
371
372 /* Location (FP register number) where GPRs (r0-r15) should
373 be saved to.
374 0 - does not need to be saved at all
375 -1 - stack slot */
376 signed char gpr_save_slots[16];
377
378 /* Number of first and last gpr to be saved, restored. */
379 int first_save_gpr;
380 int first_restore_gpr;
381 int last_save_gpr;
382 int last_restore_gpr;
383
384 /* Bits standing for floating point registers. Set, if the
385 respective register has to be saved. Starting with reg 16 (f0)
386 at the rightmost bit.
387 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
388 fpr 15 13 11 9 14 12 10 8 7 5 3 1 6 4 2 0
389 reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 */
390 unsigned int fpr_bitmap;
391
392 /* Number of floating point registers f8-f15 which must be saved. */
393 int high_fprs;
394
395 /* Set if return address needs to be saved.
396 This flag is set by s390_return_addr_rtx if it could not use
397 the initial value of r14 and therefore depends on r14 saved
398 to the stack. */
399 bool save_return_addr_p;
400
401 /* Size of stack frame. */
402 HOST_WIDE_INT frame_size;
403 };
404
405 /* Define the structure for the machine field in struct function. */
406
407 struct GTY(()) machine_function
408 {
409 struct s390_frame_layout frame_layout;
410
411 /* Literal pool base register. */
412 rtx base_reg;
413
414 /* True if we may need to perform branch splitting. */
415 bool split_branches_pending_p;
416
417 bool has_landing_pad_p;
418
419 /* True if the current function may contain a tbegin clobbering
420 FPRs. */
421 bool tbegin_p;
422 };
423
424 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
425
426 #define cfun_frame_layout (cfun->machine->frame_layout)
427 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
428 #define cfun_save_arg_fprs_p (!!(TARGET_64BIT \
429 ? cfun_frame_layout.fpr_bitmap & 0x0f \
430 : cfun_frame_layout.fpr_bitmap & 0x03))
431 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
432 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
433 #define cfun_set_fpr_save(REGNO) (cfun->machine->frame_layout.fpr_bitmap |= \
434 (1 << (REGNO - FPR0_REGNUM)))
435 #define cfun_fpr_save_p(REGNO) (!!(cfun->machine->frame_layout.fpr_bitmap & \
436 (1 << (REGNO - FPR0_REGNUM))))
437 #define cfun_gpr_save_slot(REGNO) \
438 cfun->machine->frame_layout.gpr_save_slots[REGNO]
439
440 /* Number of GPRs and FPRs used for argument passing. */
441 #define GP_ARG_NUM_REG 5
442 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
443
444 /* A couple of shortcuts. */
445 #define CONST_OK_FOR_J(x) \
446 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
447 #define CONST_OK_FOR_K(x) \
448 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
449 #define CONST_OK_FOR_Os(x) \
450 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
451 #define CONST_OK_FOR_Op(x) \
452 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
453 #define CONST_OK_FOR_On(x) \
454 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
455
456 #define REGNO_PAIR_OK(REGNO, MODE) \
457 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
458
459 /* That's the read ahead of the dynamic branch prediction unit in
460 bytes on a z10 (or higher) CPU. */
461 #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
462
463 static const int s390_hotpatch_trampoline_halfwords_default = 12;
464 static const int s390_hotpatch_trampoline_halfwords_max = 1000000;
465 static int s390_hotpatch_trampoline_halfwords = -1;
466
467 /* Return the argument of the given hotpatch attribute or the default value if
468 no argument is present. */
469
470 static inline int
471 get_hotpatch_attribute (tree hotpatch_attr)
472 {
473 const_tree args;
474
475 args = TREE_VALUE (hotpatch_attr);
476
477 return (args) ?
478 TREE_INT_CST_LOW (TREE_VALUE (args)):
479 s390_hotpatch_trampoline_halfwords_default;
480 }
481
482 /* Check whether the hotpatch attribute is applied to a function and, if it has
483 an argument, the argument is valid. */
484
485 static tree
486 s390_handle_hotpatch_attribute (tree *node, tree name, tree args,
487 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
488 {
489 if (TREE_CODE (*node) != FUNCTION_DECL)
490 {
491 warning (OPT_Wattributes, "%qE attribute only applies to functions",
492 name);
493 *no_add_attrs = true;
494 }
495 else if (args)
496 {
497 tree expr = TREE_VALUE (args);
498
499 if (TREE_CODE (expr) != INTEGER_CST
500 || !INTEGRAL_TYPE_P (TREE_TYPE (expr))
501 || wi::gtu_p (expr, s390_hotpatch_trampoline_halfwords_max))
502 {
503 error ("requested %qE attribute is not a non-negative integer"
504 " constant or too large (max. %d)", name,
505 s390_hotpatch_trampoline_halfwords_max);
506 *no_add_attrs = true;
507 }
508 }
509
510 return NULL_TREE;
511 }
512
513 static const struct attribute_spec s390_attribute_table[] = {
514 { "hotpatch", 0, 1, true, false, false, s390_handle_hotpatch_attribute, false
515 },
516 /* End element. */
517 { NULL, 0, 0, false, false, false, NULL, false }
518 };
519
520 /* Return the alignment for LABEL. We default to the -falign-labels
521 value except for the literal pool base label. */
522 int
523 s390_label_align (rtx label)
524 {
525 rtx_insn *prev_insn = prev_active_insn (label);
526 rtx set, src;
527
528 if (prev_insn == NULL_RTX)
529 goto old;
530
531 set = single_set (prev_insn);
532
533 if (set == NULL_RTX)
534 goto old;
535
536 src = SET_SRC (set);
537
538 /* Don't align literal pool base labels. */
539 if (GET_CODE (src) == UNSPEC
540 && XINT (src, 1) == UNSPEC_MAIN_BASE)
541 return 0;
542
543 old:
544 return align_labels_log;
545 }
546
547 static machine_mode
548 s390_libgcc_cmp_return_mode (void)
549 {
550 return TARGET_64BIT ? DImode : SImode;
551 }
552
553 static machine_mode
554 s390_libgcc_shift_count_mode (void)
555 {
556 return TARGET_64BIT ? DImode : SImode;
557 }
558
559 static machine_mode
560 s390_unwind_word_mode (void)
561 {
562 return TARGET_64BIT ? DImode : SImode;
563 }
564
565 /* Return true if the back end supports mode MODE. */
566 static bool
567 s390_scalar_mode_supported_p (machine_mode mode)
568 {
569 /* In contrast to the default implementation reject TImode constants on 31bit
570 TARGET_ZARCH for ABI compliance. */
571 if (!TARGET_64BIT && TARGET_ZARCH && mode == TImode)
572 return false;
573
574 if (DECIMAL_FLOAT_MODE_P (mode))
575 return default_decimal_float_supported_p ();
576
577 return default_scalar_mode_supported_p (mode);
578 }
579
580 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
581
582 void
583 s390_set_has_landing_pad_p (bool value)
584 {
585 cfun->machine->has_landing_pad_p = value;
586 }
587
588 /* If two condition code modes are compatible, return a condition code
589 mode which is compatible with both. Otherwise, return
590 VOIDmode. */
591
592 static machine_mode
593 s390_cc_modes_compatible (machine_mode m1, machine_mode m2)
594 {
595 if (m1 == m2)
596 return m1;
597
598 switch (m1)
599 {
600 case CCZmode:
601 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
602 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
603 return m2;
604 return VOIDmode;
605
606 case CCSmode:
607 case CCUmode:
608 case CCTmode:
609 case CCSRmode:
610 case CCURmode:
611 case CCZ1mode:
612 if (m2 == CCZmode)
613 return m1;
614
615 return VOIDmode;
616
617 default:
618 return VOIDmode;
619 }
620 return VOIDmode;
621 }
622
623 /* Return true if SET either doesn't set the CC register, or else
624 the source and destination have matching CC modes and that
625 CC mode is at least as constrained as REQ_MODE. */
626
627 static bool
628 s390_match_ccmode_set (rtx set, machine_mode req_mode)
629 {
630 machine_mode set_mode;
631
632 gcc_assert (GET_CODE (set) == SET);
633
634 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
635 return 1;
636
637 set_mode = GET_MODE (SET_DEST (set));
638 switch (set_mode)
639 {
640 case CCSmode:
641 case CCSRmode:
642 case CCUmode:
643 case CCURmode:
644 case CCLmode:
645 case CCL1mode:
646 case CCL2mode:
647 case CCL3mode:
648 case CCT1mode:
649 case CCT2mode:
650 case CCT3mode:
651 if (req_mode != set_mode)
652 return 0;
653 break;
654
655 case CCZmode:
656 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
657 && req_mode != CCSRmode && req_mode != CCURmode)
658 return 0;
659 break;
660
661 case CCAPmode:
662 case CCANmode:
663 if (req_mode != CCAmode)
664 return 0;
665 break;
666
667 default:
668 gcc_unreachable ();
669 }
670
671 return (GET_MODE (SET_SRC (set)) == set_mode);
672 }
673
674 /* Return true if every SET in INSN that sets the CC register
675 has source and destination with matching CC modes and that
676 CC mode is at least as constrained as REQ_MODE.
677 If REQ_MODE is VOIDmode, always return false. */
678
679 bool
680 s390_match_ccmode (rtx_insn *insn, machine_mode req_mode)
681 {
682 int i;
683
684 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
685 if (req_mode == VOIDmode)
686 return false;
687
688 if (GET_CODE (PATTERN (insn)) == SET)
689 return s390_match_ccmode_set (PATTERN (insn), req_mode);
690
691 if (GET_CODE (PATTERN (insn)) == PARALLEL)
692 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
693 {
694 rtx set = XVECEXP (PATTERN (insn), 0, i);
695 if (GET_CODE (set) == SET)
696 if (!s390_match_ccmode_set (set, req_mode))
697 return false;
698 }
699
700 return true;
701 }
702
703 /* If a test-under-mask instruction can be used to implement
704 (compare (and ... OP1) OP2), return the CC mode required
705 to do that. Otherwise, return VOIDmode.
706 MIXED is true if the instruction can distinguish between
707 CC1 and CC2 for mixed selected bits (TMxx), it is false
708 if the instruction cannot (TM). */
709
710 machine_mode
711 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
712 {
713 int bit0, bit1;
714
715 /* ??? Fixme: should work on CONST_DOUBLE as well. */
716 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
717 return VOIDmode;
718
719 /* Selected bits all zero: CC0.
720 e.g.: int a; if ((a & (16 + 128)) == 0) */
721 if (INTVAL (op2) == 0)
722 return CCTmode;
723
724 /* Selected bits all one: CC3.
725 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
726 if (INTVAL (op2) == INTVAL (op1))
727 return CCT3mode;
728
729 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
730 int a;
731 if ((a & (16 + 128)) == 16) -> CCT1
732 if ((a & (16 + 128)) == 128) -> CCT2 */
733 if (mixed)
734 {
735 bit1 = exact_log2 (INTVAL (op2));
736 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
737 if (bit0 != -1 && bit1 != -1)
738 return bit0 > bit1 ? CCT1mode : CCT2mode;
739 }
740
741 return VOIDmode;
742 }
743
744 /* Given a comparison code OP (EQ, NE, etc.) and the operands
745 OP0 and OP1 of a COMPARE, return the mode to be used for the
746 comparison. */
747
748 machine_mode
749 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
750 {
751 switch (code)
752 {
753 case EQ:
754 case NE:
755 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
756 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
757 return CCAPmode;
758 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
759 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
760 return CCAPmode;
761 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
762 || GET_CODE (op1) == NEG)
763 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
764 return CCLmode;
765
766 if (GET_CODE (op0) == AND)
767 {
768 /* Check whether we can potentially do it via TM. */
769 machine_mode ccmode;
770 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
771 if (ccmode != VOIDmode)
772 {
773 /* Relax CCTmode to CCZmode to allow fall-back to AND
774 if that turns out to be beneficial. */
775 return ccmode == CCTmode ? CCZmode : ccmode;
776 }
777 }
778
779 if (register_operand (op0, HImode)
780 && GET_CODE (op1) == CONST_INT
781 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
782 return CCT3mode;
783 if (register_operand (op0, QImode)
784 && GET_CODE (op1) == CONST_INT
785 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
786 return CCT3mode;
787
788 return CCZmode;
789
790 case LE:
791 case LT:
792 case GE:
793 case GT:
794 /* The only overflow condition of NEG and ABS happens when
795 -INT_MAX is used as parameter, which stays negative. So
796 we have an overflow from a positive value to a negative.
797 Using CCAP mode the resulting cc can be used for comparisons. */
798 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
799 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
800 return CCAPmode;
801
802 /* If constants are involved in an add instruction it is possible to use
803 the resulting cc for comparisons with zero. Knowing the sign of the
804 constant the overflow behavior gets predictable. e.g.:
805 int a, b; if ((b = a + c) > 0)
806 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
807 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
808 && (CONST_OK_FOR_K (INTVAL (XEXP (op0, 1)))
809 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (XEXP (op0, 1)), 'O', "Os")
810 /* Avoid INT32_MIN on 32 bit. */
811 && (!TARGET_ZARCH || INTVAL (XEXP (op0, 1)) != -0x7fffffff - 1))))
812 {
813 if (INTVAL (XEXP((op0), 1)) < 0)
814 return CCANmode;
815 else
816 return CCAPmode;
817 }
818 /* Fall through. */
819 case UNORDERED:
820 case ORDERED:
821 case UNEQ:
822 case UNLE:
823 case UNLT:
824 case UNGE:
825 case UNGT:
826 case LTGT:
827 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
828 && GET_CODE (op1) != CONST_INT)
829 return CCSRmode;
830 return CCSmode;
831
832 case LTU:
833 case GEU:
834 if (GET_CODE (op0) == PLUS
835 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
836 return CCL1mode;
837
838 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
839 && GET_CODE (op1) != CONST_INT)
840 return CCURmode;
841 return CCUmode;
842
843 case LEU:
844 case GTU:
845 if (GET_CODE (op0) == MINUS
846 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
847 return CCL2mode;
848
849 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
850 && GET_CODE (op1) != CONST_INT)
851 return CCURmode;
852 return CCUmode;
853
854 default:
855 gcc_unreachable ();
856 }
857 }
858
859 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
860 that we can implement more efficiently. */
861
862 static void
863 s390_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
864 bool op0_preserve_value)
865 {
866 if (op0_preserve_value)
867 return;
868
869 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
870 if ((*code == EQ || *code == NE)
871 && *op1 == const0_rtx
872 && GET_CODE (*op0) == ZERO_EXTRACT
873 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
874 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
875 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
876 {
877 rtx inner = XEXP (*op0, 0);
878 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
879 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
880 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
881
882 if (len > 0 && len < modesize
883 && pos >= 0 && pos + len <= modesize
884 && modesize <= HOST_BITS_PER_WIDE_INT)
885 {
886 unsigned HOST_WIDE_INT block;
887 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
888 block <<= modesize - pos - len;
889
890 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
891 gen_int_mode (block, GET_MODE (inner)));
892 }
893 }
894
895 /* Narrow AND of memory against immediate to enable TM. */
896 if ((*code == EQ || *code == NE)
897 && *op1 == const0_rtx
898 && GET_CODE (*op0) == AND
899 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
900 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
901 {
902 rtx inner = XEXP (*op0, 0);
903 rtx mask = XEXP (*op0, 1);
904
905 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
906 if (GET_CODE (inner) == SUBREG
907 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
908 && (GET_MODE_SIZE (GET_MODE (inner))
909 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
910 && ((INTVAL (mask)
911 & GET_MODE_MASK (GET_MODE (inner))
912 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
913 == 0))
914 inner = SUBREG_REG (inner);
915
916 /* Do not change volatile MEMs. */
917 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
918 {
919 int part = s390_single_part (XEXP (*op0, 1),
920 GET_MODE (inner), QImode, 0);
921 if (part >= 0)
922 {
923 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
924 inner = adjust_address_nv (inner, QImode, part);
925 *op0 = gen_rtx_AND (QImode, inner, mask);
926 }
927 }
928 }
929
930 /* Narrow comparisons against 0xffff to HImode if possible. */
931 if ((*code == EQ || *code == NE)
932 && GET_CODE (*op1) == CONST_INT
933 && INTVAL (*op1) == 0xffff
934 && SCALAR_INT_MODE_P (GET_MODE (*op0))
935 && (nonzero_bits (*op0, GET_MODE (*op0))
936 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
937 {
938 *op0 = gen_lowpart (HImode, *op0);
939 *op1 = constm1_rtx;
940 }
941
942 /* Remove redundant UNSPEC_STRCMPCC_TO_INT conversions if possible. */
943 if (GET_CODE (*op0) == UNSPEC
944 && XINT (*op0, 1) == UNSPEC_STRCMPCC_TO_INT
945 && XVECLEN (*op0, 0) == 1
946 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
947 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
948 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
949 && *op1 == const0_rtx)
950 {
951 enum rtx_code new_code = UNKNOWN;
952 switch (*code)
953 {
954 case EQ: new_code = EQ; break;
955 case NE: new_code = NE; break;
956 case LT: new_code = GTU; break;
957 case GT: new_code = LTU; break;
958 case LE: new_code = GEU; break;
959 case GE: new_code = LEU; break;
960 default: break;
961 }
962
963 if (new_code != UNKNOWN)
964 {
965 *op0 = XVECEXP (*op0, 0, 0);
966 *code = new_code;
967 }
968 }
969
970 /* Remove redundant UNSPEC_CC_TO_INT conversions if possible. */
971 if (GET_CODE (*op0) == UNSPEC
972 && XINT (*op0, 1) == UNSPEC_CC_TO_INT
973 && XVECLEN (*op0, 0) == 1
974 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
975 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
976 && CONST_INT_P (*op1))
977 {
978 enum rtx_code new_code = UNKNOWN;
979 switch (GET_MODE (XVECEXP (*op0, 0, 0)))
980 {
981 case CCZmode:
982 case CCRAWmode:
983 switch (*code)
984 {
985 case EQ: new_code = EQ; break;
986 case NE: new_code = NE; break;
987 default: break;
988 }
989 break;
990 default: break;
991 }
992
993 if (new_code != UNKNOWN)
994 {
995 /* For CCRAWmode put the required cc mask into the second
996 operand. */
997 if (GET_MODE (XVECEXP (*op0, 0, 0)) == CCRAWmode
998 && INTVAL (*op1) >= 0 && INTVAL (*op1) <= 3)
999 *op1 = gen_rtx_CONST_INT (VOIDmode, 1 << (3 - INTVAL (*op1)));
1000 *op0 = XVECEXP (*op0, 0, 0);
1001 *code = new_code;
1002 }
1003 }
1004
1005 /* Simplify cascaded EQ, NE with const0_rtx. */
1006 if ((*code == NE || *code == EQ)
1007 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
1008 && GET_MODE (*op0) == SImode
1009 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
1010 && REG_P (XEXP (*op0, 0))
1011 && XEXP (*op0, 1) == const0_rtx
1012 && *op1 == const0_rtx)
1013 {
1014 if ((*code == EQ && GET_CODE (*op0) == NE)
1015 || (*code == NE && GET_CODE (*op0) == EQ))
1016 *code = EQ;
1017 else
1018 *code = NE;
1019 *op0 = XEXP (*op0, 0);
1020 }
1021
1022 /* Prefer register over memory as first operand. */
1023 if (MEM_P (*op0) && REG_P (*op1))
1024 {
1025 rtx tem = *op0; *op0 = *op1; *op1 = tem;
1026 *code = (int)swap_condition ((enum rtx_code)*code);
1027 }
1028 }
1029
1030 /* Emit a compare instruction suitable to implement the comparison
1031 OP0 CODE OP1. Return the correct condition RTL to be placed in
1032 the IF_THEN_ELSE of the conditional branch testing the result. */
1033
1034 rtx
1035 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
1036 {
1037 machine_mode mode = s390_select_ccmode (code, op0, op1);
1038 rtx cc;
1039
1040 /* Do not output a redundant compare instruction if a compare_and_swap
1041 pattern already computed the result and the machine modes are compatible. */
1042 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
1043 {
1044 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), mode)
1045 == GET_MODE (op0));
1046 cc = op0;
1047 }
1048 else
1049 {
1050 cc = gen_rtx_REG (mode, CC_REGNUM);
1051 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
1052 }
1053
1054 return gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
1055 }
1056
1057 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
1058 matches CMP.
1059 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
1060 conditional branch testing the result. */
1061
1062 static rtx
1063 s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem,
1064 rtx cmp, rtx new_rtx)
1065 {
1066 emit_insn (gen_atomic_compare_and_swapsi_internal (old, mem, cmp, new_rtx));
1067 return s390_emit_compare (code, gen_rtx_REG (CCZ1mode, CC_REGNUM),
1068 const0_rtx);
1069 }
1070
1071 /* Emit a jump instruction to TARGET and return it. If COND is
1072 NULL_RTX, emit an unconditional jump, else a conditional jump under
1073 condition COND. */
1074
1075 rtx_insn *
1076 s390_emit_jump (rtx target, rtx cond)
1077 {
1078 rtx insn;
1079
1080 target = gen_rtx_LABEL_REF (VOIDmode, target);
1081 if (cond)
1082 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
1083
1084 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
1085 return emit_jump_insn (insn);
1086 }
1087
1088 /* Return branch condition mask to implement a branch
1089 specified by CODE. Return -1 for invalid comparisons. */
1090
1091 int
1092 s390_branch_condition_mask (rtx code)
1093 {
1094 const int CC0 = 1 << 3;
1095 const int CC1 = 1 << 2;
1096 const int CC2 = 1 << 1;
1097 const int CC3 = 1 << 0;
1098
1099 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
1100 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
1101 gcc_assert (XEXP (code, 1) == const0_rtx
1102 || (GET_MODE (XEXP (code, 0)) == CCRAWmode
1103 && CONST_INT_P (XEXP (code, 1))));
1104
1105
1106 switch (GET_MODE (XEXP (code, 0)))
1107 {
1108 case CCZmode:
1109 case CCZ1mode:
1110 switch (GET_CODE (code))
1111 {
1112 case EQ: return CC0;
1113 case NE: return CC1 | CC2 | CC3;
1114 default: return -1;
1115 }
1116 break;
1117
1118 case CCT1mode:
1119 switch (GET_CODE (code))
1120 {
1121 case EQ: return CC1;
1122 case NE: return CC0 | CC2 | CC3;
1123 default: return -1;
1124 }
1125 break;
1126
1127 case CCT2mode:
1128 switch (GET_CODE (code))
1129 {
1130 case EQ: return CC2;
1131 case NE: return CC0 | CC1 | CC3;
1132 default: return -1;
1133 }
1134 break;
1135
1136 case CCT3mode:
1137 switch (GET_CODE (code))
1138 {
1139 case EQ: return CC3;
1140 case NE: return CC0 | CC1 | CC2;
1141 default: return -1;
1142 }
1143 break;
1144
1145 case CCLmode:
1146 switch (GET_CODE (code))
1147 {
1148 case EQ: return CC0 | CC2;
1149 case NE: return CC1 | CC3;
1150 default: return -1;
1151 }
1152 break;
1153
1154 case CCL1mode:
1155 switch (GET_CODE (code))
1156 {
1157 case LTU: return CC2 | CC3; /* carry */
1158 case GEU: return CC0 | CC1; /* no carry */
1159 default: return -1;
1160 }
1161 break;
1162
1163 case CCL2mode:
1164 switch (GET_CODE (code))
1165 {
1166 case GTU: return CC0 | CC1; /* borrow */
1167 case LEU: return CC2 | CC3; /* no borrow */
1168 default: return -1;
1169 }
1170 break;
1171
1172 case CCL3mode:
1173 switch (GET_CODE (code))
1174 {
1175 case EQ: return CC0 | CC2;
1176 case NE: return CC1 | CC3;
1177 case LTU: return CC1;
1178 case GTU: return CC3;
1179 case LEU: return CC1 | CC2;
1180 case GEU: return CC2 | CC3;
1181 default: return -1;
1182 }
1183
1184 case CCUmode:
1185 switch (GET_CODE (code))
1186 {
1187 case EQ: return CC0;
1188 case NE: return CC1 | CC2 | CC3;
1189 case LTU: return CC1;
1190 case GTU: return CC2;
1191 case LEU: return CC0 | CC1;
1192 case GEU: return CC0 | CC2;
1193 default: return -1;
1194 }
1195 break;
1196
1197 case CCURmode:
1198 switch (GET_CODE (code))
1199 {
1200 case EQ: return CC0;
1201 case NE: return CC2 | CC1 | CC3;
1202 case LTU: return CC2;
1203 case GTU: return CC1;
1204 case LEU: return CC0 | CC2;
1205 case GEU: return CC0 | CC1;
1206 default: return -1;
1207 }
1208 break;
1209
1210 case CCAPmode:
1211 switch (GET_CODE (code))
1212 {
1213 case EQ: return CC0;
1214 case NE: return CC1 | CC2 | CC3;
1215 case LT: return CC1 | CC3;
1216 case GT: return CC2;
1217 case LE: return CC0 | CC1 | CC3;
1218 case GE: return CC0 | CC2;
1219 default: return -1;
1220 }
1221 break;
1222
1223 case CCANmode:
1224 switch (GET_CODE (code))
1225 {
1226 case EQ: return CC0;
1227 case NE: return CC1 | CC2 | CC3;
1228 case LT: return CC1;
1229 case GT: return CC2 | CC3;
1230 case LE: return CC0 | CC1;
1231 case GE: return CC0 | CC2 | CC3;
1232 default: return -1;
1233 }
1234 break;
1235
1236 case CCSmode:
1237 switch (GET_CODE (code))
1238 {
1239 case EQ: return CC0;
1240 case NE: return CC1 | CC2 | CC3;
1241 case LT: return CC1;
1242 case GT: return CC2;
1243 case LE: return CC0 | CC1;
1244 case GE: return CC0 | CC2;
1245 case UNORDERED: return CC3;
1246 case ORDERED: return CC0 | CC1 | CC2;
1247 case UNEQ: return CC0 | CC3;
1248 case UNLT: return CC1 | CC3;
1249 case UNGT: return CC2 | CC3;
1250 case UNLE: return CC0 | CC1 | CC3;
1251 case UNGE: return CC0 | CC2 | CC3;
1252 case LTGT: return CC1 | CC2;
1253 default: return -1;
1254 }
1255 break;
1256
1257 case CCSRmode:
1258 switch (GET_CODE (code))
1259 {
1260 case EQ: return CC0;
1261 case NE: return CC2 | CC1 | CC3;
1262 case LT: return CC2;
1263 case GT: return CC1;
1264 case LE: return CC0 | CC2;
1265 case GE: return CC0 | CC1;
1266 case UNORDERED: return CC3;
1267 case ORDERED: return CC0 | CC2 | CC1;
1268 case UNEQ: return CC0 | CC3;
1269 case UNLT: return CC2 | CC3;
1270 case UNGT: return CC1 | CC3;
1271 case UNLE: return CC0 | CC2 | CC3;
1272 case UNGE: return CC0 | CC1 | CC3;
1273 case LTGT: return CC2 | CC1;
1274 default: return -1;
1275 }
1276 break;
1277
1278 case CCRAWmode:
1279 switch (GET_CODE (code))
1280 {
1281 case EQ:
1282 return INTVAL (XEXP (code, 1));
1283 case NE:
1284 return (INTVAL (XEXP (code, 1))) ^ 0xf;
1285 default:
1286 gcc_unreachable ();
1287 }
1288
1289 default:
1290 return -1;
1291 }
1292 }
1293
1294
1295 /* Return branch condition mask to implement a compare and branch
1296 specified by CODE. Return -1 for invalid comparisons. */
1297
1298 int
1299 s390_compare_and_branch_condition_mask (rtx code)
1300 {
1301 const int CC0 = 1 << 3;
1302 const int CC1 = 1 << 2;
1303 const int CC2 = 1 << 1;
1304
1305 switch (GET_CODE (code))
1306 {
1307 case EQ:
1308 return CC0;
1309 case NE:
1310 return CC1 | CC2;
1311 case LT:
1312 case LTU:
1313 return CC1;
1314 case GT:
1315 case GTU:
1316 return CC2;
1317 case LE:
1318 case LEU:
1319 return CC0 | CC1;
1320 case GE:
1321 case GEU:
1322 return CC0 | CC2;
1323 default:
1324 gcc_unreachable ();
1325 }
1326 return -1;
1327 }
1328
1329 /* If INV is false, return assembler mnemonic string to implement
1330 a branch specified by CODE. If INV is true, return mnemonic
1331 for the corresponding inverted branch. */
1332
1333 static const char *
1334 s390_branch_condition_mnemonic (rtx code, int inv)
1335 {
1336 int mask;
1337
1338 static const char *const mnemonic[16] =
1339 {
1340 NULL, "o", "h", "nle",
1341 "l", "nhe", "lh", "ne",
1342 "e", "nlh", "he", "nl",
1343 "le", "nh", "no", NULL
1344 };
1345
1346 if (GET_CODE (XEXP (code, 0)) == REG
1347 && REGNO (XEXP (code, 0)) == CC_REGNUM
1348 && (XEXP (code, 1) == const0_rtx
1349 || (GET_MODE (XEXP (code, 0)) == CCRAWmode
1350 && CONST_INT_P (XEXP (code, 1)))))
1351 mask = s390_branch_condition_mask (code);
1352 else
1353 mask = s390_compare_and_branch_condition_mask (code);
1354
1355 gcc_assert (mask >= 0);
1356
1357 if (inv)
1358 mask ^= 15;
1359
1360 gcc_assert (mask >= 1 && mask <= 14);
1361
1362 return mnemonic[mask];
1363 }
1364
1365 /* Return the part of op which has a value different from def.
1366 The size of the part is determined by mode.
1367 Use this function only if you already know that op really
1368 contains such a part. */
1369
1370 unsigned HOST_WIDE_INT
1371 s390_extract_part (rtx op, machine_mode mode, int def)
1372 {
1373 unsigned HOST_WIDE_INT value = 0;
1374 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1375 int part_bits = GET_MODE_BITSIZE (mode);
1376 unsigned HOST_WIDE_INT part_mask
1377 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1378 int i;
1379
1380 for (i = 0; i < max_parts; i++)
1381 {
1382 if (i == 0)
1383 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1384 else
1385 value >>= part_bits;
1386
1387 if ((value & part_mask) != (def & part_mask))
1388 return value & part_mask;
1389 }
1390
1391 gcc_unreachable ();
1392 }
1393
1394 /* If OP is an integer constant of mode MODE with exactly one
1395 part of mode PART_MODE unequal to DEF, return the number of that
1396 part. Otherwise, return -1. */
1397
1398 int
1399 s390_single_part (rtx op,
1400 machine_mode mode,
1401 machine_mode part_mode,
1402 int def)
1403 {
1404 unsigned HOST_WIDE_INT value = 0;
1405 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1406 unsigned HOST_WIDE_INT part_mask
1407 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1408 int i, part = -1;
1409
1410 if (GET_CODE (op) != CONST_INT)
1411 return -1;
1412
1413 for (i = 0; i < n_parts; i++)
1414 {
1415 if (i == 0)
1416 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1417 else
1418 value >>= GET_MODE_BITSIZE (part_mode);
1419
1420 if ((value & part_mask) != (def & part_mask))
1421 {
1422 if (part != -1)
1423 return -1;
1424 else
1425 part = i;
1426 }
1427 }
1428 return part == -1 ? -1 : n_parts - 1 - part;
1429 }
1430
1431 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1432 bits and no other bits are set in IN. POS and LENGTH can be used
1433 to obtain the start position and the length of the bitfield.
1434
1435 POS gives the position of the first bit of the bitfield counting
1436 from the lowest order bit starting with zero. In order to use this
1437 value for S/390 instructions this has to be converted to "bits big
1438 endian" style. */
1439
1440 bool
1441 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size,
1442 int *pos, int *length)
1443 {
1444 int tmp_pos = 0;
1445 int tmp_length = 0;
1446 int i;
1447 unsigned HOST_WIDE_INT mask = 1ULL;
1448 bool contiguous = false;
1449
1450 for (i = 0; i < size; mask <<= 1, i++)
1451 {
1452 if (contiguous)
1453 {
1454 if (mask & in)
1455 tmp_length++;
1456 else
1457 break;
1458 }
1459 else
1460 {
1461 if (mask & in)
1462 {
1463 contiguous = true;
1464 tmp_length++;
1465 }
1466 else
1467 tmp_pos++;
1468 }
1469 }
1470
1471 if (!tmp_length)
1472 return false;
1473
1474 /* Calculate a mask for all bits beyond the contiguous bits. */
1475 mask = (-1LL & ~(((1ULL << (tmp_length + tmp_pos - 1)) << 1) - 1));
1476
1477 if (mask & in)
1478 return false;
1479
1480 if (tmp_length + tmp_pos - 1 > size)
1481 return false;
1482
1483 if (length)
1484 *length = tmp_length;
1485
1486 if (pos)
1487 *pos = tmp_pos;
1488
1489 return true;
1490 }
1491
1492 /* Check whether a rotate of ROTL followed by an AND of CONTIG is
1493 equivalent to a shift followed by the AND. In particular, CONTIG
1494 should not overlap the (rotated) bit 0/bit 63 gap. Negative values
1495 for ROTL indicate a rotate to the right. */
1496
1497 bool
1498 s390_extzv_shift_ok (int bitsize, int rotl, unsigned HOST_WIDE_INT contig)
1499 {
1500 int pos, len;
1501 bool ok;
1502
1503 ok = s390_contiguous_bitmask_p (contig, bitsize, &pos, &len);
1504 gcc_assert (ok);
1505
1506 return ((rotl >= 0 && rotl <= pos)
1507 || (rotl < 0 && -rotl <= bitsize - len - pos));
1508 }
1509
1510 /* Check whether we can (and want to) split a double-word
1511 move in mode MODE from SRC to DST into two single-word
1512 moves, moving the subword FIRST_SUBWORD first. */
1513
1514 bool
1515 s390_split_ok_p (rtx dst, rtx src, machine_mode mode, int first_subword)
1516 {
1517 /* Floating point registers cannot be split. */
1518 if (FP_REG_P (src) || FP_REG_P (dst))
1519 return false;
1520
1521 /* We don't need to split if operands are directly accessible. */
1522 if (s_operand (src, mode) || s_operand (dst, mode))
1523 return false;
1524
1525 /* Non-offsettable memory references cannot be split. */
1526 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1527 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1528 return false;
1529
1530 /* Moving the first subword must not clobber a register
1531 needed to move the second subword. */
1532 if (register_operand (dst, mode))
1533 {
1534 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1535 if (reg_overlap_mentioned_p (subreg, src))
1536 return false;
1537 }
1538
1539 return true;
1540 }
1541
1542 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1543 and [MEM2, MEM2 + SIZE] do overlap and false
1544 otherwise. */
1545
1546 bool
1547 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1548 {
1549 rtx addr1, addr2, addr_delta;
1550 HOST_WIDE_INT delta;
1551
1552 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1553 return true;
1554
1555 if (size == 0)
1556 return false;
1557
1558 addr1 = XEXP (mem1, 0);
1559 addr2 = XEXP (mem2, 0);
1560
1561 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1562
1563 /* This overlapping check is used by peepholes merging memory block operations.
1564 Overlapping operations would otherwise be recognized by the S/390 hardware
1565 and would fall back to a slower implementation. Allowing overlapping
1566 operations would lead to slow code but not to wrong code. Therefore we are
1567 somewhat optimistic if we cannot prove that the memory blocks are
1568 overlapping.
1569 That's why we return false here although this may accept operations on
1570 overlapping memory areas. */
1571 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1572 return false;
1573
1574 delta = INTVAL (addr_delta);
1575
1576 if (delta == 0
1577 || (delta > 0 && delta < size)
1578 || (delta < 0 && -delta < size))
1579 return true;
1580
1581 return false;
1582 }
1583
1584 /* Check whether the address of memory reference MEM2 equals exactly
1585 the address of memory reference MEM1 plus DELTA. Return true if
1586 we can prove this to be the case, false otherwise. */
1587
1588 bool
1589 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1590 {
1591 rtx addr1, addr2, addr_delta;
1592
1593 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1594 return false;
1595
1596 addr1 = XEXP (mem1, 0);
1597 addr2 = XEXP (mem2, 0);
1598
1599 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1600 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1601 return false;
1602
1603 return true;
1604 }
1605
1606 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1607
1608 void
1609 s390_expand_logical_operator (enum rtx_code code, machine_mode mode,
1610 rtx *operands)
1611 {
1612 machine_mode wmode = mode;
1613 rtx dst = operands[0];
1614 rtx src1 = operands[1];
1615 rtx src2 = operands[2];
1616 rtx op, clob, tem;
1617
1618 /* If we cannot handle the operation directly, use a temp register. */
1619 if (!s390_logical_operator_ok_p (operands))
1620 dst = gen_reg_rtx (mode);
1621
1622 /* QImode and HImode patterns make sense only if we have a destination
1623 in memory. Otherwise perform the operation in SImode. */
1624 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1625 wmode = SImode;
1626
1627 /* Widen operands if required. */
1628 if (mode != wmode)
1629 {
1630 if (GET_CODE (dst) == SUBREG
1631 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1632 dst = tem;
1633 else if (REG_P (dst))
1634 dst = gen_rtx_SUBREG (wmode, dst, 0);
1635 else
1636 dst = gen_reg_rtx (wmode);
1637
1638 if (GET_CODE (src1) == SUBREG
1639 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1640 src1 = tem;
1641 else if (GET_MODE (src1) != VOIDmode)
1642 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1643
1644 if (GET_CODE (src2) == SUBREG
1645 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1646 src2 = tem;
1647 else if (GET_MODE (src2) != VOIDmode)
1648 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1649 }
1650
1651 /* Emit the instruction. */
1652 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1653 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1654 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1655
1656 /* Fix up the destination if needed. */
1657 if (dst != operands[0])
1658 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1659 }
1660
1661 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1662
1663 bool
1664 s390_logical_operator_ok_p (rtx *operands)
1665 {
1666 /* If the destination operand is in memory, it needs to coincide
1667 with one of the source operands. After reload, it has to be
1668 the first source operand. */
1669 if (GET_CODE (operands[0]) == MEM)
1670 return rtx_equal_p (operands[0], operands[1])
1671 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1672
1673 return true;
1674 }
1675
1676 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1677 operand IMMOP to switch from SS to SI type instructions. */
1678
1679 void
1680 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1681 {
1682 int def = code == AND ? -1 : 0;
1683 HOST_WIDE_INT mask;
1684 int part;
1685
1686 gcc_assert (GET_CODE (*memop) == MEM);
1687 gcc_assert (!MEM_VOLATILE_P (*memop));
1688
1689 mask = s390_extract_part (*immop, QImode, def);
1690 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1691 gcc_assert (part >= 0);
1692
1693 *memop = adjust_address (*memop, QImode, part);
1694 *immop = gen_int_mode (mask, QImode);
1695 }
1696
1697
1698 /* How to allocate a 'struct machine_function'. */
1699
1700 static struct machine_function *
1701 s390_init_machine_status (void)
1702 {
1703 return ggc_cleared_alloc<machine_function> ();
1704 }
1705
1706 /* Map for smallest class containing reg regno. */
1707
1708 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1709 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1710 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1711 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1712 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1713 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1714 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1715 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1716 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1717 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1718 ACCESS_REGS, ACCESS_REGS
1719 };
1720
1721 /* Return attribute type of insn. */
1722
1723 static enum attr_type
1724 s390_safe_attr_type (rtx_insn *insn)
1725 {
1726 if (recog_memoized (insn) >= 0)
1727 return get_attr_type (insn);
1728 else
1729 return TYPE_NONE;
1730 }
1731
1732 /* Return true if DISP is a valid short displacement. */
1733
1734 static bool
1735 s390_short_displacement (rtx disp)
1736 {
1737 /* No displacement is OK. */
1738 if (!disp)
1739 return true;
1740
1741 /* Without the long displacement facility we don't need to
1742 distingiush between long and short displacement. */
1743 if (!TARGET_LONG_DISPLACEMENT)
1744 return true;
1745
1746 /* Integer displacement in range. */
1747 if (GET_CODE (disp) == CONST_INT)
1748 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1749
1750 /* GOT offset is not OK, the GOT can be large. */
1751 if (GET_CODE (disp) == CONST
1752 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1753 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1754 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1755 return false;
1756
1757 /* All other symbolic constants are literal pool references,
1758 which are OK as the literal pool must be small. */
1759 if (GET_CODE (disp) == CONST)
1760 return true;
1761
1762 return false;
1763 }
1764
1765 /* Decompose a RTL expression ADDR for a memory address into
1766 its components, returned in OUT.
1767
1768 Returns false if ADDR is not a valid memory address, true
1769 otherwise. If OUT is NULL, don't return the components,
1770 but check for validity only.
1771
1772 Note: Only addresses in canonical form are recognized.
1773 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1774 canonical form so that they will be recognized. */
1775
1776 static int
1777 s390_decompose_address (rtx addr, struct s390_address *out)
1778 {
1779 HOST_WIDE_INT offset = 0;
1780 rtx base = NULL_RTX;
1781 rtx indx = NULL_RTX;
1782 rtx disp = NULL_RTX;
1783 rtx orig_disp;
1784 bool pointer = false;
1785 bool base_ptr = false;
1786 bool indx_ptr = false;
1787 bool literal_pool = false;
1788
1789 /* We may need to substitute the literal pool base register into the address
1790 below. However, at this point we do not know which register is going to
1791 be used as base, so we substitute the arg pointer register. This is going
1792 to be treated as holding a pointer below -- it shouldn't be used for any
1793 other purpose. */
1794 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1795
1796 /* Decompose address into base + index + displacement. */
1797
1798 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1799 base = addr;
1800
1801 else if (GET_CODE (addr) == PLUS)
1802 {
1803 rtx op0 = XEXP (addr, 0);
1804 rtx op1 = XEXP (addr, 1);
1805 enum rtx_code code0 = GET_CODE (op0);
1806 enum rtx_code code1 = GET_CODE (op1);
1807
1808 if (code0 == REG || code0 == UNSPEC)
1809 {
1810 if (code1 == REG || code1 == UNSPEC)
1811 {
1812 indx = op0; /* index + base */
1813 base = op1;
1814 }
1815
1816 else
1817 {
1818 base = op0; /* base + displacement */
1819 disp = op1;
1820 }
1821 }
1822
1823 else if (code0 == PLUS)
1824 {
1825 indx = XEXP (op0, 0); /* index + base + disp */
1826 base = XEXP (op0, 1);
1827 disp = op1;
1828 }
1829
1830 else
1831 {
1832 return false;
1833 }
1834 }
1835
1836 else
1837 disp = addr; /* displacement */
1838
1839 /* Extract integer part of displacement. */
1840 orig_disp = disp;
1841 if (disp)
1842 {
1843 if (GET_CODE (disp) == CONST_INT)
1844 {
1845 offset = INTVAL (disp);
1846 disp = NULL_RTX;
1847 }
1848 else if (GET_CODE (disp) == CONST
1849 && GET_CODE (XEXP (disp, 0)) == PLUS
1850 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1851 {
1852 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1853 disp = XEXP (XEXP (disp, 0), 0);
1854 }
1855 }
1856
1857 /* Strip off CONST here to avoid special case tests later. */
1858 if (disp && GET_CODE (disp) == CONST)
1859 disp = XEXP (disp, 0);
1860
1861 /* We can convert literal pool addresses to
1862 displacements by basing them off the base register. */
1863 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1864 {
1865 /* Either base or index must be free to hold the base register. */
1866 if (!base)
1867 base = fake_pool_base, literal_pool = true;
1868 else if (!indx)
1869 indx = fake_pool_base, literal_pool = true;
1870 else
1871 return false;
1872
1873 /* Mark up the displacement. */
1874 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1875 UNSPEC_LTREL_OFFSET);
1876 }
1877
1878 /* Validate base register. */
1879 if (base)
1880 {
1881 if (GET_CODE (base) == UNSPEC)
1882 switch (XINT (base, 1))
1883 {
1884 case UNSPEC_LTREF:
1885 if (!disp)
1886 disp = gen_rtx_UNSPEC (Pmode,
1887 gen_rtvec (1, XVECEXP (base, 0, 0)),
1888 UNSPEC_LTREL_OFFSET);
1889 else
1890 return false;
1891
1892 base = XVECEXP (base, 0, 1);
1893 break;
1894
1895 case UNSPEC_LTREL_BASE:
1896 if (XVECLEN (base, 0) == 1)
1897 base = fake_pool_base, literal_pool = true;
1898 else
1899 base = XVECEXP (base, 0, 1);
1900 break;
1901
1902 default:
1903 return false;
1904 }
1905
1906 if (!REG_P (base)
1907 || (GET_MODE (base) != SImode
1908 && GET_MODE (base) != Pmode))
1909 return false;
1910
1911 if (REGNO (base) == STACK_POINTER_REGNUM
1912 || REGNO (base) == FRAME_POINTER_REGNUM
1913 || ((reload_completed || reload_in_progress)
1914 && frame_pointer_needed
1915 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1916 || REGNO (base) == ARG_POINTER_REGNUM
1917 || (flag_pic
1918 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1919 pointer = base_ptr = true;
1920
1921 if ((reload_completed || reload_in_progress)
1922 && base == cfun->machine->base_reg)
1923 pointer = base_ptr = literal_pool = true;
1924 }
1925
1926 /* Validate index register. */
1927 if (indx)
1928 {
1929 if (GET_CODE (indx) == UNSPEC)
1930 switch (XINT (indx, 1))
1931 {
1932 case UNSPEC_LTREF:
1933 if (!disp)
1934 disp = gen_rtx_UNSPEC (Pmode,
1935 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1936 UNSPEC_LTREL_OFFSET);
1937 else
1938 return false;
1939
1940 indx = XVECEXP (indx, 0, 1);
1941 break;
1942
1943 case UNSPEC_LTREL_BASE:
1944 if (XVECLEN (indx, 0) == 1)
1945 indx = fake_pool_base, literal_pool = true;
1946 else
1947 indx = XVECEXP (indx, 0, 1);
1948 break;
1949
1950 default:
1951 return false;
1952 }
1953
1954 if (!REG_P (indx)
1955 || (GET_MODE (indx) != SImode
1956 && GET_MODE (indx) != Pmode))
1957 return false;
1958
1959 if (REGNO (indx) == STACK_POINTER_REGNUM
1960 || REGNO (indx) == FRAME_POINTER_REGNUM
1961 || ((reload_completed || reload_in_progress)
1962 && frame_pointer_needed
1963 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1964 || REGNO (indx) == ARG_POINTER_REGNUM
1965 || (flag_pic
1966 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
1967 pointer = indx_ptr = true;
1968
1969 if ((reload_completed || reload_in_progress)
1970 && indx == cfun->machine->base_reg)
1971 pointer = indx_ptr = literal_pool = true;
1972 }
1973
1974 /* Prefer to use pointer as base, not index. */
1975 if (base && indx && !base_ptr
1976 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1977 {
1978 rtx tmp = base;
1979 base = indx;
1980 indx = tmp;
1981 }
1982
1983 /* Validate displacement. */
1984 if (!disp)
1985 {
1986 /* If virtual registers are involved, the displacement will change later
1987 anyway as the virtual registers get eliminated. This could make a
1988 valid displacement invalid, but it is more likely to make an invalid
1989 displacement valid, because we sometimes access the register save area
1990 via negative offsets to one of those registers.
1991 Thus we don't check the displacement for validity here. If after
1992 elimination the displacement turns out to be invalid after all,
1993 this is fixed up by reload in any case. */
1994 /* LRA maintains always displacements up to date and we need to
1995 know the displacement is right during all LRA not only at the
1996 final elimination. */
1997 if (lra_in_progress
1998 || (base != arg_pointer_rtx
1999 && indx != arg_pointer_rtx
2000 && base != return_address_pointer_rtx
2001 && indx != return_address_pointer_rtx
2002 && base != frame_pointer_rtx
2003 && indx != frame_pointer_rtx
2004 && base != virtual_stack_vars_rtx
2005 && indx != virtual_stack_vars_rtx))
2006 if (!DISP_IN_RANGE (offset))
2007 return false;
2008 }
2009 else
2010 {
2011 /* All the special cases are pointers. */
2012 pointer = true;
2013
2014 /* In the small-PIC case, the linker converts @GOT
2015 and @GOTNTPOFF offsets to possible displacements. */
2016 if (GET_CODE (disp) == UNSPEC
2017 && (XINT (disp, 1) == UNSPEC_GOT
2018 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
2019 && flag_pic == 1)
2020 {
2021 ;
2022 }
2023
2024 /* Accept pool label offsets. */
2025 else if (GET_CODE (disp) == UNSPEC
2026 && XINT (disp, 1) == UNSPEC_POOL_OFFSET)
2027 ;
2028
2029 /* Accept literal pool references. */
2030 else if (GET_CODE (disp) == UNSPEC
2031 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
2032 {
2033 /* In case CSE pulled a non literal pool reference out of
2034 the pool we have to reject the address. This is
2035 especially important when loading the GOT pointer on non
2036 zarch CPUs. In this case the literal pool contains an lt
2037 relative offset to the _GLOBAL_OFFSET_TABLE_ label which
2038 will most likely exceed the displacement. */
2039 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
2040 || !CONSTANT_POOL_ADDRESS_P (XVECEXP (disp, 0, 0)))
2041 return false;
2042
2043 orig_disp = gen_rtx_CONST (Pmode, disp);
2044 if (offset)
2045 {
2046 /* If we have an offset, make sure it does not
2047 exceed the size of the constant pool entry. */
2048 rtx sym = XVECEXP (disp, 0, 0);
2049 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
2050 return false;
2051
2052 orig_disp = plus_constant (Pmode, orig_disp, offset);
2053 }
2054 }
2055
2056 else
2057 return false;
2058 }
2059
2060 if (!base && !indx)
2061 pointer = true;
2062
2063 if (out)
2064 {
2065 out->base = base;
2066 out->indx = indx;
2067 out->disp = orig_disp;
2068 out->pointer = pointer;
2069 out->literal_pool = literal_pool;
2070 }
2071
2072 return true;
2073 }
2074
2075 /* Decompose a RTL expression OP for a shift count into its components,
2076 and return the base register in BASE and the offset in OFFSET.
2077
2078 Return true if OP is a valid shift count, false if not. */
2079
2080 bool
2081 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
2082 {
2083 HOST_WIDE_INT off = 0;
2084
2085 /* We can have an integer constant, an address register,
2086 or a sum of the two. */
2087 if (GET_CODE (op) == CONST_INT)
2088 {
2089 off = INTVAL (op);
2090 op = NULL_RTX;
2091 }
2092 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
2093 {
2094 off = INTVAL (XEXP (op, 1));
2095 op = XEXP (op, 0);
2096 }
2097 while (op && GET_CODE (op) == SUBREG)
2098 op = SUBREG_REG (op);
2099
2100 if (op && GET_CODE (op) != REG)
2101 return false;
2102
2103 if (offset)
2104 *offset = off;
2105 if (base)
2106 *base = op;
2107
2108 return true;
2109 }
2110
2111
2112 /* Return true if CODE is a valid address without index. */
2113
2114 bool
2115 s390_legitimate_address_without_index_p (rtx op)
2116 {
2117 struct s390_address addr;
2118
2119 if (!s390_decompose_address (XEXP (op, 0), &addr))
2120 return false;
2121 if (addr.indx)
2122 return false;
2123
2124 return true;
2125 }
2126
2127
2128 /* Return TRUE if ADDR is an operand valid for a load/store relative
2129 instruction. Be aware that the alignment of the operand needs to
2130 be checked separately.
2131 Valid addresses are single references or a sum of a reference and a
2132 constant integer. Return these parts in SYMREF and ADDEND. You can
2133 pass NULL in REF and/or ADDEND if you are not interested in these
2134 values. Literal pool references are *not* considered symbol
2135 references. */
2136
2137 static bool
2138 s390_loadrelative_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend)
2139 {
2140 HOST_WIDE_INT tmpaddend = 0;
2141
2142 if (GET_CODE (addr) == CONST)
2143 addr = XEXP (addr, 0);
2144
2145 if (GET_CODE (addr) == PLUS)
2146 {
2147 if (!CONST_INT_P (XEXP (addr, 1)))
2148 return false;
2149
2150 tmpaddend = INTVAL (XEXP (addr, 1));
2151 addr = XEXP (addr, 0);
2152 }
2153
2154 if ((GET_CODE (addr) == SYMBOL_REF && !CONSTANT_POOL_ADDRESS_P (addr))
2155 || (GET_CODE (addr) == UNSPEC
2156 && (XINT (addr, 1) == UNSPEC_GOTENT
2157 || (TARGET_CPU_ZARCH && XINT (addr, 1) == UNSPEC_PLT))))
2158 {
2159 if (symref)
2160 *symref = addr;
2161 if (addend)
2162 *addend = tmpaddend;
2163
2164 return true;
2165 }
2166 return false;
2167 }
2168
2169 /* Return true if the address in OP is valid for constraint letter C
2170 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2171 pool MEMs should be accepted. Only the Q, R, S, T constraint
2172 letters are allowed for C. */
2173
2174 static int
2175 s390_check_qrst_address (char c, rtx op, bool lit_pool_ok)
2176 {
2177 struct s390_address addr;
2178 bool decomposed = false;
2179
2180 /* This check makes sure that no symbolic address (except literal
2181 pool references) are accepted by the R or T constraints. */
2182 if (s390_loadrelative_operand_p (op, NULL, NULL))
2183 return 0;
2184
2185 /* Ensure literal pool references are only accepted if LIT_POOL_OK. */
2186 if (!lit_pool_ok)
2187 {
2188 if (!s390_decompose_address (op, &addr))
2189 return 0;
2190 if (addr.literal_pool)
2191 return 0;
2192 decomposed = true;
2193 }
2194
2195 switch (c)
2196 {
2197 case 'Q': /* no index short displacement */
2198 if (!decomposed && !s390_decompose_address (op, &addr))
2199 return 0;
2200 if (addr.indx)
2201 return 0;
2202 if (!s390_short_displacement (addr.disp))
2203 return 0;
2204 break;
2205
2206 case 'R': /* with index short displacement */
2207 if (TARGET_LONG_DISPLACEMENT)
2208 {
2209 if (!decomposed && !s390_decompose_address (op, &addr))
2210 return 0;
2211 if (!s390_short_displacement (addr.disp))
2212 return 0;
2213 }
2214 /* Any invalid address here will be fixed up by reload,
2215 so accept it for the most generic constraint. */
2216 break;
2217
2218 case 'S': /* no index long displacement */
2219 if (!TARGET_LONG_DISPLACEMENT)
2220 return 0;
2221 if (!decomposed && !s390_decompose_address (op, &addr))
2222 return 0;
2223 if (addr.indx)
2224 return 0;
2225 if (s390_short_displacement (addr.disp))
2226 return 0;
2227 break;
2228
2229 case 'T': /* with index long displacement */
2230 if (!TARGET_LONG_DISPLACEMENT)
2231 return 0;
2232 /* Any invalid address here will be fixed up by reload,
2233 so accept it for the most generic constraint. */
2234 if ((decomposed || s390_decompose_address (op, &addr))
2235 && s390_short_displacement (addr.disp))
2236 return 0;
2237 break;
2238 default:
2239 return 0;
2240 }
2241 return 1;
2242 }
2243
2244
2245 /* Evaluates constraint strings described by the regular expression
2246 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2247 the constraint given in STR, or 0 else. */
2248
2249 int
2250 s390_mem_constraint (const char *str, rtx op)
2251 {
2252 char c = str[0];
2253
2254 switch (c)
2255 {
2256 case 'A':
2257 /* Check for offsettable variants of memory constraints. */
2258 if (!MEM_P (op) || MEM_VOLATILE_P (op))
2259 return 0;
2260 if ((reload_completed || reload_in_progress)
2261 ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
2262 return 0;
2263 return s390_check_qrst_address (str[1], XEXP (op, 0), true);
2264 case 'B':
2265 /* Check for non-literal-pool variants of memory constraints. */
2266 if (!MEM_P (op))
2267 return 0;
2268 return s390_check_qrst_address (str[1], XEXP (op, 0), false);
2269 case 'Q':
2270 case 'R':
2271 case 'S':
2272 case 'T':
2273 if (GET_CODE (op) != MEM)
2274 return 0;
2275 return s390_check_qrst_address (c, XEXP (op, 0), true);
2276 case 'U':
2277 return (s390_check_qrst_address ('Q', op, true)
2278 || s390_check_qrst_address ('R', op, true));
2279 case 'W':
2280 return (s390_check_qrst_address ('S', op, true)
2281 || s390_check_qrst_address ('T', op, true));
2282 case 'Y':
2283 /* Simply check for the basic form of a shift count. Reload will
2284 take care of making sure we have a proper base register. */
2285 if (!s390_decompose_shift_count (op, NULL, NULL))
2286 return 0;
2287 break;
2288 case 'Z':
2289 return s390_check_qrst_address (str[1], op, true);
2290 default:
2291 return 0;
2292 }
2293 return 1;
2294 }
2295
2296
2297 /* Evaluates constraint strings starting with letter O. Input
2298 parameter C is the second letter following the "O" in the constraint
2299 string. Returns 1 if VALUE meets the respective constraint and 0
2300 otherwise. */
2301
2302 int
2303 s390_O_constraint_str (const char c, HOST_WIDE_INT value)
2304 {
2305 if (!TARGET_EXTIMM)
2306 return 0;
2307
2308 switch (c)
2309 {
2310 case 's':
2311 return trunc_int_for_mode (value, SImode) == value;
2312
2313 case 'p':
2314 return value == 0
2315 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2316
2317 case 'n':
2318 return s390_single_part (GEN_INT (value - 1), DImode, SImode, -1) == 1;
2319
2320 default:
2321 gcc_unreachable ();
2322 }
2323 }
2324
2325
2326 /* Evaluates constraint strings starting with letter N. Parameter STR
2327 contains the letters following letter "N" in the constraint string.
2328 Returns true if VALUE matches the constraint. */
2329
2330 int
2331 s390_N_constraint_str (const char *str, HOST_WIDE_INT value)
2332 {
2333 machine_mode mode, part_mode;
2334 int def;
2335 int part, part_goal;
2336
2337
2338 if (str[0] == 'x')
2339 part_goal = -1;
2340 else
2341 part_goal = str[0] - '0';
2342
2343 switch (str[1])
2344 {
2345 case 'Q':
2346 part_mode = QImode;
2347 break;
2348 case 'H':
2349 part_mode = HImode;
2350 break;
2351 case 'S':
2352 part_mode = SImode;
2353 break;
2354 default:
2355 return 0;
2356 }
2357
2358 switch (str[2])
2359 {
2360 case 'H':
2361 mode = HImode;
2362 break;
2363 case 'S':
2364 mode = SImode;
2365 break;
2366 case 'D':
2367 mode = DImode;
2368 break;
2369 default:
2370 return 0;
2371 }
2372
2373 switch (str[3])
2374 {
2375 case '0':
2376 def = 0;
2377 break;
2378 case 'F':
2379 def = -1;
2380 break;
2381 default:
2382 return 0;
2383 }
2384
2385 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2386 return 0;
2387
2388 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2389 if (part < 0)
2390 return 0;
2391 if (part_goal != -1 && part_goal != part)
2392 return 0;
2393
2394 return 1;
2395 }
2396
2397
2398 /* Returns true if the input parameter VALUE is a float zero. */
2399
2400 int
2401 s390_float_const_zero_p (rtx value)
2402 {
2403 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
2404 && value == CONST0_RTX (GET_MODE (value)));
2405 }
2406
2407 /* Implement TARGET_REGISTER_MOVE_COST. */
2408
2409 static int
2410 s390_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
2411 reg_class_t from, reg_class_t to)
2412 {
2413 /* On s390, copy between fprs and gprs is expensive as long as no
2414 ldgr/lgdr can be used. */
2415 if ((!TARGET_Z10 || GET_MODE_SIZE (mode) != 8)
2416 && ((reg_classes_intersect_p (from, GENERAL_REGS)
2417 && reg_classes_intersect_p (to, FP_REGS))
2418 || (reg_classes_intersect_p (from, FP_REGS)
2419 && reg_classes_intersect_p (to, GENERAL_REGS))))
2420 return 10;
2421
2422 return 1;
2423 }
2424
2425 /* Implement TARGET_MEMORY_MOVE_COST. */
2426
2427 static int
2428 s390_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
2429 reg_class_t rclass ATTRIBUTE_UNUSED,
2430 bool in ATTRIBUTE_UNUSED)
2431 {
2432 return 1;
2433 }
2434
2435 /* Compute a (partial) cost for rtx X. Return true if the complete
2436 cost has been computed, and false if subexpressions should be
2437 scanned. In either case, *TOTAL contains the cost result.
2438 CODE contains GET_CODE (x), OUTER_CODE contains the code
2439 of the superexpression of x. */
2440
2441 static bool
2442 s390_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
2443 int *total, bool speed ATTRIBUTE_UNUSED)
2444 {
2445 switch (code)
2446 {
2447 case CONST:
2448 case CONST_INT:
2449 case LABEL_REF:
2450 case SYMBOL_REF:
2451 case CONST_DOUBLE:
2452 case MEM:
2453 *total = 0;
2454 return true;
2455
2456 case ASHIFT:
2457 case ASHIFTRT:
2458 case LSHIFTRT:
2459 case ROTATE:
2460 case ROTATERT:
2461 case AND:
2462 case IOR:
2463 case XOR:
2464 case NEG:
2465 case NOT:
2466 *total = COSTS_N_INSNS (1);
2467 return false;
2468
2469 case PLUS:
2470 case MINUS:
2471 *total = COSTS_N_INSNS (1);
2472 return false;
2473
2474 case MULT:
2475 switch (GET_MODE (x))
2476 {
2477 case SImode:
2478 {
2479 rtx left = XEXP (x, 0);
2480 rtx right = XEXP (x, 1);
2481 if (GET_CODE (right) == CONST_INT
2482 && CONST_OK_FOR_K (INTVAL (right)))
2483 *total = s390_cost->mhi;
2484 else if (GET_CODE (left) == SIGN_EXTEND)
2485 *total = s390_cost->mh;
2486 else
2487 *total = s390_cost->ms; /* msr, ms, msy */
2488 break;
2489 }
2490 case DImode:
2491 {
2492 rtx left = XEXP (x, 0);
2493 rtx right = XEXP (x, 1);
2494 if (TARGET_ZARCH)
2495 {
2496 if (GET_CODE (right) == CONST_INT
2497 && CONST_OK_FOR_K (INTVAL (right)))
2498 *total = s390_cost->mghi;
2499 else if (GET_CODE (left) == SIGN_EXTEND)
2500 *total = s390_cost->msgf;
2501 else
2502 *total = s390_cost->msg; /* msgr, msg */
2503 }
2504 else /* TARGET_31BIT */
2505 {
2506 if (GET_CODE (left) == SIGN_EXTEND
2507 && GET_CODE (right) == SIGN_EXTEND)
2508 /* mulsidi case: mr, m */
2509 *total = s390_cost->m;
2510 else if (GET_CODE (left) == ZERO_EXTEND
2511 && GET_CODE (right) == ZERO_EXTEND
2512 && TARGET_CPU_ZARCH)
2513 /* umulsidi case: ml, mlr */
2514 *total = s390_cost->ml;
2515 else
2516 /* Complex calculation is required. */
2517 *total = COSTS_N_INSNS (40);
2518 }
2519 break;
2520 }
2521 case SFmode:
2522 case DFmode:
2523 *total = s390_cost->mult_df;
2524 break;
2525 case TFmode:
2526 *total = s390_cost->mxbr;
2527 break;
2528 default:
2529 return false;
2530 }
2531 return false;
2532
2533 case FMA:
2534 switch (GET_MODE (x))
2535 {
2536 case DFmode:
2537 *total = s390_cost->madbr;
2538 break;
2539 case SFmode:
2540 *total = s390_cost->maebr;
2541 break;
2542 default:
2543 return false;
2544 }
2545 /* Negate in the third argument is free: FMSUB. */
2546 if (GET_CODE (XEXP (x, 2)) == NEG)
2547 {
2548 *total += (rtx_cost (XEXP (x, 0), FMA, 0, speed)
2549 + rtx_cost (XEXP (x, 1), FMA, 1, speed)
2550 + rtx_cost (XEXP (XEXP (x, 2), 0), FMA, 2, speed));
2551 return true;
2552 }
2553 return false;
2554
2555 case UDIV:
2556 case UMOD:
2557 if (GET_MODE (x) == TImode) /* 128 bit division */
2558 *total = s390_cost->dlgr;
2559 else if (GET_MODE (x) == DImode)
2560 {
2561 rtx right = XEXP (x, 1);
2562 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2563 *total = s390_cost->dlr;
2564 else /* 64 by 64 bit division */
2565 *total = s390_cost->dlgr;
2566 }
2567 else if (GET_MODE (x) == SImode) /* 32 bit division */
2568 *total = s390_cost->dlr;
2569 return false;
2570
2571 case DIV:
2572 case MOD:
2573 if (GET_MODE (x) == DImode)
2574 {
2575 rtx right = XEXP (x, 1);
2576 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2577 if (TARGET_ZARCH)
2578 *total = s390_cost->dsgfr;
2579 else
2580 *total = s390_cost->dr;
2581 else /* 64 by 64 bit division */
2582 *total = s390_cost->dsgr;
2583 }
2584 else if (GET_MODE (x) == SImode) /* 32 bit division */
2585 *total = s390_cost->dlr;
2586 else if (GET_MODE (x) == SFmode)
2587 {
2588 *total = s390_cost->debr;
2589 }
2590 else if (GET_MODE (x) == DFmode)
2591 {
2592 *total = s390_cost->ddbr;
2593 }
2594 else if (GET_MODE (x) == TFmode)
2595 {
2596 *total = s390_cost->dxbr;
2597 }
2598 return false;
2599
2600 case SQRT:
2601 if (GET_MODE (x) == SFmode)
2602 *total = s390_cost->sqebr;
2603 else if (GET_MODE (x) == DFmode)
2604 *total = s390_cost->sqdbr;
2605 else /* TFmode */
2606 *total = s390_cost->sqxbr;
2607 return false;
2608
2609 case SIGN_EXTEND:
2610 case ZERO_EXTEND:
2611 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2612 || outer_code == PLUS || outer_code == MINUS
2613 || outer_code == COMPARE)
2614 *total = 0;
2615 return false;
2616
2617 case COMPARE:
2618 *total = COSTS_N_INSNS (1);
2619 if (GET_CODE (XEXP (x, 0)) == AND
2620 && GET_CODE (XEXP (x, 1)) == CONST_INT
2621 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2622 {
2623 rtx op0 = XEXP (XEXP (x, 0), 0);
2624 rtx op1 = XEXP (XEXP (x, 0), 1);
2625 rtx op2 = XEXP (x, 1);
2626
2627 if (memory_operand (op0, GET_MODE (op0))
2628 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2629 return true;
2630 if (register_operand (op0, GET_MODE (op0))
2631 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2632 return true;
2633 }
2634 return false;
2635
2636 default:
2637 return false;
2638 }
2639 }
2640
2641 /* Return the cost of an address rtx ADDR. */
2642
2643 static int
2644 s390_address_cost (rtx addr, machine_mode mode ATTRIBUTE_UNUSED,
2645 addr_space_t as ATTRIBUTE_UNUSED,
2646 bool speed ATTRIBUTE_UNUSED)
2647 {
2648 struct s390_address ad;
2649 if (!s390_decompose_address (addr, &ad))
2650 return 1000;
2651
2652 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2653 }
2654
2655 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2656 otherwise return 0. */
2657
2658 int
2659 tls_symbolic_operand (rtx op)
2660 {
2661 if (GET_CODE (op) != SYMBOL_REF)
2662 return 0;
2663 return SYMBOL_REF_TLS_MODEL (op);
2664 }
2665 \f
2666 /* Split DImode access register reference REG (on 64-bit) into its constituent
2667 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2668 gen_highpart cannot be used as they assume all registers are word-sized,
2669 while our access registers have only half that size. */
2670
2671 void
2672 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2673 {
2674 gcc_assert (TARGET_64BIT);
2675 gcc_assert (ACCESS_REG_P (reg));
2676 gcc_assert (GET_MODE (reg) == DImode);
2677 gcc_assert (!(REGNO (reg) & 1));
2678
2679 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2680 *hi = gen_rtx_REG (SImode, REGNO (reg));
2681 }
2682
2683 /* Return true if OP contains a symbol reference */
2684
2685 bool
2686 symbolic_reference_mentioned_p (rtx op)
2687 {
2688 const char *fmt;
2689 int i;
2690
2691 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2692 return 1;
2693
2694 fmt = GET_RTX_FORMAT (GET_CODE (op));
2695 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2696 {
2697 if (fmt[i] == 'E')
2698 {
2699 int j;
2700
2701 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2702 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2703 return 1;
2704 }
2705
2706 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2707 return 1;
2708 }
2709
2710 return 0;
2711 }
2712
2713 /* Return true if OP contains a reference to a thread-local symbol. */
2714
2715 bool
2716 tls_symbolic_reference_mentioned_p (rtx op)
2717 {
2718 const char *fmt;
2719 int i;
2720
2721 if (GET_CODE (op) == SYMBOL_REF)
2722 return tls_symbolic_operand (op);
2723
2724 fmt = GET_RTX_FORMAT (GET_CODE (op));
2725 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2726 {
2727 if (fmt[i] == 'E')
2728 {
2729 int j;
2730
2731 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2732 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2733 return true;
2734 }
2735
2736 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2737 return true;
2738 }
2739
2740 return false;
2741 }
2742
2743
2744 /* Return true if OP is a legitimate general operand when
2745 generating PIC code. It is given that flag_pic is on
2746 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2747
2748 int
2749 legitimate_pic_operand_p (rtx op)
2750 {
2751 /* Accept all non-symbolic constants. */
2752 if (!SYMBOLIC_CONST (op))
2753 return 1;
2754
2755 /* Reject everything else; must be handled
2756 via emit_symbolic_move. */
2757 return 0;
2758 }
2759
2760 /* Returns true if the constant value OP is a legitimate general operand.
2761 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2762
2763 static bool
2764 s390_legitimate_constant_p (machine_mode mode, rtx op)
2765 {
2766 /* Accept all non-symbolic constants. */
2767 if (!SYMBOLIC_CONST (op))
2768 return 1;
2769
2770 /* Accept immediate LARL operands. */
2771 if (TARGET_CPU_ZARCH && larl_operand (op, mode))
2772 return 1;
2773
2774 /* Thread-local symbols are never legal constants. This is
2775 so that emit_call knows that computing such addresses
2776 might require a function call. */
2777 if (TLS_SYMBOLIC_CONST (op))
2778 return 0;
2779
2780 /* In the PIC case, symbolic constants must *not* be
2781 forced into the literal pool. We accept them here,
2782 so that they will be handled by emit_symbolic_move. */
2783 if (flag_pic)
2784 return 1;
2785
2786 /* All remaining non-PIC symbolic constants are
2787 forced into the literal pool. */
2788 return 0;
2789 }
2790
2791 /* Determine if it's legal to put X into the constant pool. This
2792 is not possible if X contains the address of a symbol that is
2793 not constant (TLS) or not known at final link time (PIC). */
2794
2795 static bool
2796 s390_cannot_force_const_mem (machine_mode mode, rtx x)
2797 {
2798 switch (GET_CODE (x))
2799 {
2800 case CONST_INT:
2801 case CONST_DOUBLE:
2802 /* Accept all non-symbolic constants. */
2803 return false;
2804
2805 case LABEL_REF:
2806 /* Labels are OK iff we are non-PIC. */
2807 return flag_pic != 0;
2808
2809 case SYMBOL_REF:
2810 /* 'Naked' TLS symbol references are never OK,
2811 non-TLS symbols are OK iff we are non-PIC. */
2812 if (tls_symbolic_operand (x))
2813 return true;
2814 else
2815 return flag_pic != 0;
2816
2817 case CONST:
2818 return s390_cannot_force_const_mem (mode, XEXP (x, 0));
2819 case PLUS:
2820 case MINUS:
2821 return s390_cannot_force_const_mem (mode, XEXP (x, 0))
2822 || s390_cannot_force_const_mem (mode, XEXP (x, 1));
2823
2824 case UNSPEC:
2825 switch (XINT (x, 1))
2826 {
2827 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2828 case UNSPEC_LTREL_OFFSET:
2829 case UNSPEC_GOT:
2830 case UNSPEC_GOTOFF:
2831 case UNSPEC_PLTOFF:
2832 case UNSPEC_TLSGD:
2833 case UNSPEC_TLSLDM:
2834 case UNSPEC_NTPOFF:
2835 case UNSPEC_DTPOFF:
2836 case UNSPEC_GOTNTPOFF:
2837 case UNSPEC_INDNTPOFF:
2838 return false;
2839
2840 /* If the literal pool shares the code section, be put
2841 execute template placeholders into the pool as well. */
2842 case UNSPEC_INSN:
2843 return TARGET_CPU_ZARCH;
2844
2845 default:
2846 return true;
2847 }
2848 break;
2849
2850 default:
2851 gcc_unreachable ();
2852 }
2853 }
2854
2855 /* Returns true if the constant value OP is a legitimate general
2856 operand during and after reload. The difference to
2857 legitimate_constant_p is that this function will not accept
2858 a constant that would need to be forced to the literal pool
2859 before it can be used as operand.
2860 This function accepts all constants which can be loaded directly
2861 into a GPR. */
2862
2863 bool
2864 legitimate_reload_constant_p (rtx op)
2865 {
2866 /* Accept la(y) operands. */
2867 if (GET_CODE (op) == CONST_INT
2868 && DISP_IN_RANGE (INTVAL (op)))
2869 return true;
2870
2871 /* Accept l(g)hi/l(g)fi operands. */
2872 if (GET_CODE (op) == CONST_INT
2873 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2874 return true;
2875
2876 /* Accept lliXX operands. */
2877 if (TARGET_ZARCH
2878 && GET_CODE (op) == CONST_INT
2879 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2880 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2881 return true;
2882
2883 if (TARGET_EXTIMM
2884 && GET_CODE (op) == CONST_INT
2885 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2886 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2887 return true;
2888
2889 /* Accept larl operands. */
2890 if (TARGET_CPU_ZARCH
2891 && larl_operand (op, VOIDmode))
2892 return true;
2893
2894 /* Accept floating-point zero operands that fit into a single GPR. */
2895 if (GET_CODE (op) == CONST_DOUBLE
2896 && s390_float_const_zero_p (op)
2897 && GET_MODE_SIZE (GET_MODE (op)) <= UNITS_PER_WORD)
2898 return true;
2899
2900 /* Accept double-word operands that can be split. */
2901 if (GET_CODE (op) == CONST_INT
2902 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2903 {
2904 machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2905 rtx hi = operand_subword (op, 0, 0, dword_mode);
2906 rtx lo = operand_subword (op, 1, 0, dword_mode);
2907 return legitimate_reload_constant_p (hi)
2908 && legitimate_reload_constant_p (lo);
2909 }
2910
2911 /* Everything else cannot be handled without reload. */
2912 return false;
2913 }
2914
2915 /* Returns true if the constant value OP is a legitimate fp operand
2916 during and after reload.
2917 This function accepts all constants which can be loaded directly
2918 into an FPR. */
2919
2920 static bool
2921 legitimate_reload_fp_constant_p (rtx op)
2922 {
2923 /* Accept floating-point zero operands if the load zero instruction
2924 can be used. Prior to z196 the load fp zero instruction caused a
2925 performance penalty if the result is used as BFP number. */
2926 if (TARGET_Z196
2927 && GET_CODE (op) == CONST_DOUBLE
2928 && s390_float_const_zero_p (op))
2929 return true;
2930
2931 return false;
2932 }
2933
2934 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2935 return the class of reg to actually use. */
2936
2937 static reg_class_t
2938 s390_preferred_reload_class (rtx op, reg_class_t rclass)
2939 {
2940 switch (GET_CODE (op))
2941 {
2942 /* Constants we cannot reload into general registers
2943 must be forced into the literal pool. */
2944 case CONST_DOUBLE:
2945 case CONST_INT:
2946 if (reg_class_subset_p (GENERAL_REGS, rclass)
2947 && legitimate_reload_constant_p (op))
2948 return GENERAL_REGS;
2949 else if (reg_class_subset_p (ADDR_REGS, rclass)
2950 && legitimate_reload_constant_p (op))
2951 return ADDR_REGS;
2952 else if (reg_class_subset_p (FP_REGS, rclass)
2953 && legitimate_reload_fp_constant_p (op))
2954 return FP_REGS;
2955 return NO_REGS;
2956
2957 /* If a symbolic constant or a PLUS is reloaded,
2958 it is most likely being used as an address, so
2959 prefer ADDR_REGS. If 'class' is not a superset
2960 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2961 case CONST:
2962 /* Symrefs cannot be pushed into the literal pool with -fPIC
2963 so we *MUST NOT* return NO_REGS for these cases
2964 (s390_cannot_force_const_mem will return true).
2965
2966 On the other hand we MUST return NO_REGS for symrefs with
2967 invalid addend which might have been pushed to the literal
2968 pool (no -fPIC). Usually we would expect them to be
2969 handled via secondary reload but this does not happen if
2970 they are used as literal pool slot replacement in reload
2971 inheritance (see emit_input_reload_insns). */
2972 if (TARGET_CPU_ZARCH
2973 && GET_CODE (XEXP (op, 0)) == PLUS
2974 && GET_CODE (XEXP (XEXP(op, 0), 0)) == SYMBOL_REF
2975 && GET_CODE (XEXP (XEXP(op, 0), 1)) == CONST_INT)
2976 {
2977 if (flag_pic && reg_class_subset_p (ADDR_REGS, rclass))
2978 return ADDR_REGS;
2979 else
2980 return NO_REGS;
2981 }
2982 /* fallthrough */
2983 case LABEL_REF:
2984 case SYMBOL_REF:
2985 if (!legitimate_reload_constant_p (op))
2986 return NO_REGS;
2987 /* fallthrough */
2988 case PLUS:
2989 /* load address will be used. */
2990 if (reg_class_subset_p (ADDR_REGS, rclass))
2991 return ADDR_REGS;
2992 else
2993 return NO_REGS;
2994
2995 default:
2996 break;
2997 }
2998
2999 return rclass;
3000 }
3001
3002 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
3003 multiple of ALIGNMENT and the SYMBOL_REF being naturally
3004 aligned. */
3005
3006 bool
3007 s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment)
3008 {
3009 HOST_WIDE_INT addend;
3010 rtx symref;
3011
3012 if (!s390_loadrelative_operand_p (addr, &symref, &addend))
3013 return false;
3014
3015 if (addend & (alignment - 1))
3016 return false;
3017
3018 if (GET_CODE (symref) == SYMBOL_REF
3019 && !SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref))
3020 return true;
3021
3022 if (GET_CODE (symref) == UNSPEC
3023 && alignment <= UNITS_PER_LONG)
3024 return true;
3025
3026 return false;
3027 }
3028
3029 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
3030 operand SCRATCH is used to reload the even part of the address and
3031 adding one. */
3032
3033 void
3034 s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch)
3035 {
3036 HOST_WIDE_INT addend;
3037 rtx symref;
3038
3039 if (!s390_loadrelative_operand_p (addr, &symref, &addend))
3040 gcc_unreachable ();
3041
3042 if (!(addend & 1))
3043 /* Easy case. The addend is even so larl will do fine. */
3044 emit_move_insn (reg, addr);
3045 else
3046 {
3047 /* We can leave the scratch register untouched if the target
3048 register is a valid base register. */
3049 if (REGNO (reg) < FIRST_PSEUDO_REGISTER
3050 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS)
3051 scratch = reg;
3052
3053 gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER);
3054 gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS);
3055
3056 if (addend != 1)
3057 emit_move_insn (scratch,
3058 gen_rtx_CONST (Pmode,
3059 gen_rtx_PLUS (Pmode, symref,
3060 GEN_INT (addend - 1))));
3061 else
3062 emit_move_insn (scratch, symref);
3063
3064 /* Increment the address using la in order to avoid clobbering cc. */
3065 s390_load_address (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx));
3066 }
3067 }
3068
3069 /* Generate what is necessary to move between REG and MEM using
3070 SCRATCH. The direction is given by TOMEM. */
3071
3072 void
3073 s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
3074 {
3075 /* Reload might have pulled a constant out of the literal pool.
3076 Force it back in. */
3077 if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE
3078 || GET_CODE (mem) == CONST)
3079 mem = force_const_mem (GET_MODE (reg), mem);
3080
3081 gcc_assert (MEM_P (mem));
3082
3083 /* For a load from memory we can leave the scratch register
3084 untouched if the target register is a valid base register. */
3085 if (!tomem
3086 && REGNO (reg) < FIRST_PSEUDO_REGISTER
3087 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS
3088 && GET_MODE (reg) == GET_MODE (scratch))
3089 scratch = reg;
3090
3091 /* Load address into scratch register. Since we can't have a
3092 secondary reload for a secondary reload we have to cover the case
3093 where larl would need a secondary reload here as well. */
3094 s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch);
3095
3096 /* Now we can use a standard load/store to do the move. */
3097 if (tomem)
3098 emit_move_insn (replace_equiv_address (mem, scratch), reg);
3099 else
3100 emit_move_insn (reg, replace_equiv_address (mem, scratch));
3101 }
3102
3103 /* Inform reload about cases where moving X with a mode MODE to a register in
3104 RCLASS requires an extra scratch or immediate register. Return the class
3105 needed for the immediate register. */
3106
3107 static reg_class_t
3108 s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
3109 machine_mode mode, secondary_reload_info *sri)
3110 {
3111 enum reg_class rclass = (enum reg_class) rclass_i;
3112
3113 /* Intermediate register needed. */
3114 if (reg_classes_intersect_p (CC_REGS, rclass))
3115 return GENERAL_REGS;
3116
3117 if (TARGET_Z10)
3118 {
3119 HOST_WIDE_INT offset;
3120 rtx symref;
3121
3122 /* On z10 several optimizer steps may generate larl operands with
3123 an odd addend. */
3124 if (in_p
3125 && s390_loadrelative_operand_p (x, &symref, &offset)
3126 && mode == Pmode
3127 && !SYMBOL_REF_ALIGN1_P (symref)
3128 && (offset & 1) == 1)
3129 sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10
3130 : CODE_FOR_reloadsi_larl_odd_addend_z10);
3131
3132 /* On z10 we need a scratch register when moving QI, TI or floating
3133 point mode values from or to a memory location with a SYMBOL_REF
3134 or if the symref addend of a SI or DI move is not aligned to the
3135 width of the access. */
3136 if (MEM_P (x)
3137 && s390_loadrelative_operand_p (XEXP (x, 0), NULL, NULL)
3138 && (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
3139 || (!TARGET_ZARCH && mode == DImode)
3140 || ((mode == HImode || mode == SImode || mode == DImode)
3141 && (!s390_check_symref_alignment (XEXP (x, 0),
3142 GET_MODE_SIZE (mode))))))
3143 {
3144 #define __SECONDARY_RELOAD_CASE(M,m) \
3145 case M##mode: \
3146 if (TARGET_64BIT) \
3147 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
3148 CODE_FOR_reload##m##di_tomem_z10; \
3149 else \
3150 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
3151 CODE_FOR_reload##m##si_tomem_z10; \
3152 break;
3153
3154 switch (GET_MODE (x))
3155 {
3156 __SECONDARY_RELOAD_CASE (QI, qi);
3157 __SECONDARY_RELOAD_CASE (HI, hi);
3158 __SECONDARY_RELOAD_CASE (SI, si);
3159 __SECONDARY_RELOAD_CASE (DI, di);
3160 __SECONDARY_RELOAD_CASE (TI, ti);
3161 __SECONDARY_RELOAD_CASE (SF, sf);
3162 __SECONDARY_RELOAD_CASE (DF, df);
3163 __SECONDARY_RELOAD_CASE (TF, tf);
3164 __SECONDARY_RELOAD_CASE (SD, sd);
3165 __SECONDARY_RELOAD_CASE (DD, dd);
3166 __SECONDARY_RELOAD_CASE (TD, td);
3167
3168 default:
3169 gcc_unreachable ();
3170 }
3171 #undef __SECONDARY_RELOAD_CASE
3172 }
3173 }
3174
3175 /* We need a scratch register when loading a PLUS expression which
3176 is not a legitimate operand of the LOAD ADDRESS instruction. */
3177 /* LRA can deal with transformation of plus op very well -- so we
3178 don't need to prompt LRA in this case. */
3179 if (! lra_in_progress && in_p && s390_plus_operand (x, mode))
3180 sri->icode = (TARGET_64BIT ?
3181 CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus);
3182
3183 /* Performing a multiword move from or to memory we have to make sure the
3184 second chunk in memory is addressable without causing a displacement
3185 overflow. If that would be the case we calculate the address in
3186 a scratch register. */
3187 if (MEM_P (x)
3188 && GET_CODE (XEXP (x, 0)) == PLUS
3189 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3190 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1))
3191 + GET_MODE_SIZE (mode) - 1))
3192 {
3193 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3194 in a s_operand address since we may fallback to lm/stm. So we only
3195 have to care about overflows in the b+i+d case. */
3196 if ((reg_classes_intersect_p (GENERAL_REGS, rclass)
3197 && s390_class_max_nregs (GENERAL_REGS, mode) > 1
3198 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
3199 /* For FP_REGS no lm/stm is available so this check is triggered
3200 for displacement overflows in b+i+d and b+d like addresses. */
3201 || (reg_classes_intersect_p (FP_REGS, rclass)
3202 && s390_class_max_nregs (FP_REGS, mode) > 1))
3203 {
3204 if (in_p)
3205 sri->icode = (TARGET_64BIT ?
3206 CODE_FOR_reloaddi_nonoffmem_in :
3207 CODE_FOR_reloadsi_nonoffmem_in);
3208 else
3209 sri->icode = (TARGET_64BIT ?
3210 CODE_FOR_reloaddi_nonoffmem_out :
3211 CODE_FOR_reloadsi_nonoffmem_out);
3212 }
3213 }
3214
3215 /* A scratch address register is needed when a symbolic constant is
3216 copied to r0 compiling with -fPIC. In other cases the target
3217 register might be used as temporary (see legitimize_pic_address). */
3218 if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS)
3219 sri->icode = (TARGET_64BIT ?
3220 CODE_FOR_reloaddi_PIC_addr :
3221 CODE_FOR_reloadsi_PIC_addr);
3222
3223 /* Either scratch or no register needed. */
3224 return NO_REGS;
3225 }
3226
3227 /* Generate code to load SRC, which is PLUS that is not a
3228 legitimate operand for the LA instruction, into TARGET.
3229 SCRATCH may be used as scratch register. */
3230
3231 void
3232 s390_expand_plus_operand (rtx target, rtx src,
3233 rtx scratch)
3234 {
3235 rtx sum1, sum2;
3236 struct s390_address ad;
3237
3238 /* src must be a PLUS; get its two operands. */
3239 gcc_assert (GET_CODE (src) == PLUS);
3240 gcc_assert (GET_MODE (src) == Pmode);
3241
3242 /* Check if any of the two operands is already scheduled
3243 for replacement by reload. This can happen e.g. when
3244 float registers occur in an address. */
3245 sum1 = find_replacement (&XEXP (src, 0));
3246 sum2 = find_replacement (&XEXP (src, 1));
3247 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3248
3249 /* If the address is already strictly valid, there's nothing to do. */
3250 if (!s390_decompose_address (src, &ad)
3251 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3252 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
3253 {
3254 /* Otherwise, one of the operands cannot be an address register;
3255 we reload its value into the scratch register. */
3256 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
3257 {
3258 emit_move_insn (scratch, sum1);
3259 sum1 = scratch;
3260 }
3261 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
3262 {
3263 emit_move_insn (scratch, sum2);
3264 sum2 = scratch;
3265 }
3266
3267 /* According to the way these invalid addresses are generated
3268 in reload.c, it should never happen (at least on s390) that
3269 *neither* of the PLUS components, after find_replacements
3270 was applied, is an address register. */
3271 if (sum1 == scratch && sum2 == scratch)
3272 {
3273 debug_rtx (src);
3274 gcc_unreachable ();
3275 }
3276
3277 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3278 }
3279
3280 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3281 is only ever performed on addresses, so we can mark the
3282 sum as legitimate for LA in any case. */
3283 s390_load_address (target, src);
3284 }
3285
3286
3287 /* Return true if ADDR is a valid memory address.
3288 STRICT specifies whether strict register checking applies. */
3289
3290 static bool
3291 s390_legitimate_address_p (machine_mode mode, rtx addr, bool strict)
3292 {
3293 struct s390_address ad;
3294
3295 if (TARGET_Z10
3296 && larl_operand (addr, VOIDmode)
3297 && (mode == VOIDmode
3298 || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode))))
3299 return true;
3300
3301 if (!s390_decompose_address (addr, &ad))
3302 return false;
3303
3304 if (strict)
3305 {
3306 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3307 return false;
3308
3309 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
3310 return false;
3311 }
3312 else
3313 {
3314 if (ad.base
3315 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
3316 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
3317 return false;
3318
3319 if (ad.indx
3320 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
3321 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
3322 return false;
3323 }
3324 return true;
3325 }
3326
3327 /* Return true if OP is a valid operand for the LA instruction.
3328 In 31-bit, we need to prove that the result is used as an
3329 address, as LA performs only a 31-bit addition. */
3330
3331 bool
3332 legitimate_la_operand_p (rtx op)
3333 {
3334 struct s390_address addr;
3335 if (!s390_decompose_address (op, &addr))
3336 return false;
3337
3338 return (TARGET_64BIT || addr.pointer);
3339 }
3340
3341 /* Return true if it is valid *and* preferable to use LA to
3342 compute the sum of OP1 and OP2. */
3343
3344 bool
3345 preferred_la_operand_p (rtx op1, rtx op2)
3346 {
3347 struct s390_address addr;
3348
3349 if (op2 != const0_rtx)
3350 op1 = gen_rtx_PLUS (Pmode, op1, op2);
3351
3352 if (!s390_decompose_address (op1, &addr))
3353 return false;
3354 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
3355 return false;
3356 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
3357 return false;
3358
3359 /* Avoid LA instructions with index register on z196; it is
3360 preferable to use regular add instructions when possible.
3361 Starting with zEC12 the la with index register is "uncracked"
3362 again. */
3363 if (addr.indx && s390_tune == PROCESSOR_2817_Z196)
3364 return false;
3365
3366 if (!TARGET_64BIT && !addr.pointer)
3367 return false;
3368
3369 if (addr.pointer)
3370 return true;
3371
3372 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
3373 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
3374 return true;
3375
3376 return false;
3377 }
3378
3379 /* Emit a forced load-address operation to load SRC into DST.
3380 This will use the LOAD ADDRESS instruction even in situations
3381 where legitimate_la_operand_p (SRC) returns false. */
3382
3383 void
3384 s390_load_address (rtx dst, rtx src)
3385 {
3386 if (TARGET_64BIT)
3387 emit_move_insn (dst, src);
3388 else
3389 emit_insn (gen_force_la_31 (dst, src));
3390 }
3391
3392 /* Return a legitimate reference for ORIG (an address) using the
3393 register REG. If REG is 0, a new pseudo is generated.
3394
3395 There are two types of references that must be handled:
3396
3397 1. Global data references must load the address from the GOT, via
3398 the PIC reg. An insn is emitted to do this load, and the reg is
3399 returned.
3400
3401 2. Static data references, constant pool addresses, and code labels
3402 compute the address as an offset from the GOT, whose base is in
3403 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3404 differentiate them from global data objects. The returned
3405 address is the PIC reg + an unspec constant.
3406
3407 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3408 reg also appears in the address. */
3409
3410 rtx
3411 legitimize_pic_address (rtx orig, rtx reg)
3412 {
3413 rtx addr = orig;
3414 rtx addend = const0_rtx;
3415 rtx new_rtx = orig;
3416
3417 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
3418
3419 if (GET_CODE (addr) == CONST)
3420 addr = XEXP (addr, 0);
3421
3422 if (GET_CODE (addr) == PLUS)
3423 {
3424 addend = XEXP (addr, 1);
3425 addr = XEXP (addr, 0);
3426 }
3427
3428 if ((GET_CODE (addr) == LABEL_REF
3429 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr))
3430 || (GET_CODE (addr) == UNSPEC &&
3431 (XINT (addr, 1) == UNSPEC_GOTENT
3432 || (TARGET_CPU_ZARCH && XINT (addr, 1) == UNSPEC_PLT))))
3433 && GET_CODE (addend) == CONST_INT)
3434 {
3435 /* This can be locally addressed. */
3436
3437 /* larl_operand requires UNSPECs to be wrapped in a const rtx. */
3438 rtx const_addr = (GET_CODE (addr) == UNSPEC ?
3439 gen_rtx_CONST (Pmode, addr) : addr);
3440
3441 if (TARGET_CPU_ZARCH
3442 && larl_operand (const_addr, VOIDmode)
3443 && INTVAL (addend) < (HOST_WIDE_INT)1 << 31
3444 && INTVAL (addend) >= -((HOST_WIDE_INT)1 << 31))
3445 {
3446 if (INTVAL (addend) & 1)
3447 {
3448 /* LARL can't handle odd offsets, so emit a pair of LARL
3449 and LA. */
3450 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3451
3452 if (!DISP_IN_RANGE (INTVAL (addend)))
3453 {
3454 HOST_WIDE_INT even = INTVAL (addend) - 1;
3455 addr = gen_rtx_PLUS (Pmode, addr, GEN_INT (even));
3456 addr = gen_rtx_CONST (Pmode, addr);
3457 addend = const1_rtx;
3458 }
3459
3460 emit_move_insn (temp, addr);
3461 new_rtx = gen_rtx_PLUS (Pmode, temp, addend);
3462
3463 if (reg != 0)
3464 {
3465 s390_load_address (reg, new_rtx);
3466 new_rtx = reg;
3467 }
3468 }
3469 else
3470 {
3471 /* If the offset is even, we can just use LARL. This
3472 will happen automatically. */
3473 }
3474 }
3475 else
3476 {
3477 /* No larl - Access local symbols relative to the GOT. */
3478
3479 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3480
3481 if (reload_in_progress || reload_completed)
3482 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3483
3484 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
3485 if (addend != const0_rtx)
3486 addr = gen_rtx_PLUS (Pmode, addr, addend);
3487 addr = gen_rtx_CONST (Pmode, addr);
3488 addr = force_const_mem (Pmode, addr);
3489 emit_move_insn (temp, addr);
3490
3491 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3492 if (reg != 0)
3493 {
3494 s390_load_address (reg, new_rtx);
3495 new_rtx = reg;
3496 }
3497 }
3498 }
3499 else if (GET_CODE (addr) == SYMBOL_REF && addend == const0_rtx)
3500 {
3501 /* A non-local symbol reference without addend.
3502
3503 The symbol ref is wrapped into an UNSPEC to make sure the
3504 proper operand modifier (@GOT or @GOTENT) will be emitted.
3505 This will tell the linker to put the symbol into the GOT.
3506
3507 Additionally the code dereferencing the GOT slot is emitted here.
3508
3509 An addend to the symref needs to be added afterwards.
3510 legitimize_pic_address calls itself recursively to handle
3511 that case. So no need to do it here. */
3512
3513 if (reg == 0)
3514 reg = gen_reg_rtx (Pmode);
3515
3516 if (TARGET_Z10)
3517 {
3518 /* Use load relative if possible.
3519 lgrl <target>, sym@GOTENT */
3520 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3521 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3522 new_rtx = gen_const_mem (GET_MODE (reg), new_rtx);
3523
3524 emit_move_insn (reg, new_rtx);
3525 new_rtx = reg;
3526 }
3527 else if (flag_pic == 1)
3528 {
3529 /* Assume GOT offset is a valid displacement operand (< 4k
3530 or < 512k with z990). This is handled the same way in
3531 both 31- and 64-bit code (@GOT).
3532 lg <target>, sym@GOT(r12) */
3533
3534 if (reload_in_progress || reload_completed)
3535 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3536
3537 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3538 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3539 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3540 new_rtx = gen_const_mem (Pmode, new_rtx);
3541 emit_move_insn (reg, new_rtx);
3542 new_rtx = reg;
3543 }
3544 else if (TARGET_CPU_ZARCH)
3545 {
3546 /* If the GOT offset might be >= 4k, we determine the position
3547 of the GOT entry via a PC-relative LARL (@GOTENT).
3548 larl temp, sym@GOTENT
3549 lg <target>, 0(temp) */
3550
3551 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3552
3553 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3554 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3555
3556 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3557 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3558 emit_move_insn (temp, new_rtx);
3559
3560 new_rtx = gen_const_mem (Pmode, temp);
3561 emit_move_insn (reg, new_rtx);
3562
3563 new_rtx = reg;
3564 }
3565 else
3566 {
3567 /* If the GOT offset might be >= 4k, we have to load it
3568 from the literal pool (@GOT).
3569
3570 lg temp, lit-litbase(r13)
3571 lg <target>, 0(temp)
3572 lit: .long sym@GOT */
3573
3574 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3575
3576 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3577 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3578
3579 if (reload_in_progress || reload_completed)
3580 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3581
3582 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3583 addr = gen_rtx_CONST (Pmode, addr);
3584 addr = force_const_mem (Pmode, addr);
3585 emit_move_insn (temp, addr);
3586
3587 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3588 new_rtx = gen_const_mem (Pmode, new_rtx);
3589 emit_move_insn (reg, new_rtx);
3590 new_rtx = reg;
3591 }
3592 }
3593 else if (GET_CODE (addr) == UNSPEC && GET_CODE (addend) == CONST_INT)
3594 {
3595 gcc_assert (XVECLEN (addr, 0) == 1);
3596 switch (XINT (addr, 1))
3597 {
3598 /* These address symbols (or PLT slots) relative to the GOT
3599 (not GOT slots!). In general this will exceed the
3600 displacement range so these value belong into the literal
3601 pool. */
3602 case UNSPEC_GOTOFF:
3603 case UNSPEC_PLTOFF:
3604 new_rtx = force_const_mem (Pmode, orig);
3605 break;
3606
3607 /* For -fPIC the GOT size might exceed the displacement
3608 range so make sure the value is in the literal pool. */
3609 case UNSPEC_GOT:
3610 if (flag_pic == 2)
3611 new_rtx = force_const_mem (Pmode, orig);
3612 break;
3613
3614 /* For @GOTENT larl is used. This is handled like local
3615 symbol refs. */
3616 case UNSPEC_GOTENT:
3617 gcc_unreachable ();
3618 break;
3619
3620 /* @PLT is OK as is on 64-bit, must be converted to
3621 GOT-relative @PLTOFF on 31-bit. */
3622 case UNSPEC_PLT:
3623 if (!TARGET_CPU_ZARCH)
3624 {
3625 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3626
3627 if (reload_in_progress || reload_completed)
3628 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3629
3630 addr = XVECEXP (addr, 0, 0);
3631 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
3632 UNSPEC_PLTOFF);
3633 if (addend != const0_rtx)
3634 addr = gen_rtx_PLUS (Pmode, addr, addend);
3635 addr = gen_rtx_CONST (Pmode, addr);
3636 addr = force_const_mem (Pmode, addr);
3637 emit_move_insn (temp, addr);
3638
3639 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3640 if (reg != 0)
3641 {
3642 s390_load_address (reg, new_rtx);
3643 new_rtx = reg;
3644 }
3645 }
3646 else
3647 /* On 64 bit larl can be used. This case is handled like
3648 local symbol refs. */
3649 gcc_unreachable ();
3650 break;
3651
3652 /* Everything else cannot happen. */
3653 default:
3654 gcc_unreachable ();
3655 }
3656 }
3657 else if (addend != const0_rtx)
3658 {
3659 /* Otherwise, compute the sum. */
3660
3661 rtx base = legitimize_pic_address (addr, reg);
3662 new_rtx = legitimize_pic_address (addend,
3663 base == reg ? NULL_RTX : reg);
3664 if (GET_CODE (new_rtx) == CONST_INT)
3665 new_rtx = plus_constant (Pmode, base, INTVAL (new_rtx));
3666 else
3667 {
3668 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
3669 {
3670 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
3671 new_rtx = XEXP (new_rtx, 1);
3672 }
3673 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
3674 }
3675
3676 if (GET_CODE (new_rtx) == CONST)
3677 new_rtx = XEXP (new_rtx, 0);
3678 new_rtx = force_operand (new_rtx, 0);
3679 }
3680
3681 return new_rtx;
3682 }
3683
3684 /* Load the thread pointer into a register. */
3685
3686 rtx
3687 s390_get_thread_pointer (void)
3688 {
3689 rtx tp = gen_reg_rtx (Pmode);
3690
3691 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3692 mark_reg_pointer (tp, BITS_PER_WORD);
3693
3694 return tp;
3695 }
3696
3697 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3698 in s390_tls_symbol which always refers to __tls_get_offset.
3699 The returned offset is written to RESULT_REG and an USE rtx is
3700 generated for TLS_CALL. */
3701
3702 static GTY(()) rtx s390_tls_symbol;
3703
3704 static void
3705 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3706 {
3707 rtx insn;
3708
3709 if (!flag_pic)
3710 emit_insn (s390_load_got ());
3711
3712 if (!s390_tls_symbol)
3713 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3714
3715 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3716 gen_rtx_REG (Pmode, RETURN_REGNUM));
3717
3718 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3719 RTL_CONST_CALL_P (insn) = 1;
3720 }
3721
3722 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3723 this (thread-local) address. REG may be used as temporary. */
3724
3725 static rtx
3726 legitimize_tls_address (rtx addr, rtx reg)
3727 {
3728 rtx new_rtx, tls_call, temp, base, r2, insn;
3729
3730 if (GET_CODE (addr) == SYMBOL_REF)
3731 switch (tls_symbolic_operand (addr))
3732 {
3733 case TLS_MODEL_GLOBAL_DYNAMIC:
3734 start_sequence ();
3735 r2 = gen_rtx_REG (Pmode, 2);
3736 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3737 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3738 new_rtx = force_const_mem (Pmode, new_rtx);
3739 emit_move_insn (r2, new_rtx);
3740 s390_emit_tls_call_insn (r2, tls_call);
3741 insn = get_insns ();
3742 end_sequence ();
3743
3744 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3745 temp = gen_reg_rtx (Pmode);
3746 emit_libcall_block (insn, temp, r2, new_rtx);
3747
3748 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3749 if (reg != 0)
3750 {
3751 s390_load_address (reg, new_rtx);
3752 new_rtx = reg;
3753 }
3754 break;
3755
3756 case TLS_MODEL_LOCAL_DYNAMIC:
3757 start_sequence ();
3758 r2 = gen_rtx_REG (Pmode, 2);
3759 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3760 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3761 new_rtx = force_const_mem (Pmode, new_rtx);
3762 emit_move_insn (r2, new_rtx);
3763 s390_emit_tls_call_insn (r2, tls_call);
3764 insn = get_insns ();
3765 end_sequence ();
3766
3767 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3768 temp = gen_reg_rtx (Pmode);
3769 emit_libcall_block (insn, temp, r2, new_rtx);
3770
3771 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3772 base = gen_reg_rtx (Pmode);
3773 s390_load_address (base, new_rtx);
3774
3775 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3776 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3777 new_rtx = force_const_mem (Pmode, new_rtx);
3778 temp = gen_reg_rtx (Pmode);
3779 emit_move_insn (temp, new_rtx);
3780
3781 new_rtx = gen_rtx_PLUS (Pmode, base, temp);
3782 if (reg != 0)
3783 {
3784 s390_load_address (reg, new_rtx);
3785 new_rtx = reg;
3786 }
3787 break;
3788
3789 case TLS_MODEL_INITIAL_EXEC:
3790 if (flag_pic == 1)
3791 {
3792 /* Assume GOT offset < 4k. This is handled the same way
3793 in both 31- and 64-bit code. */
3794
3795 if (reload_in_progress || reload_completed)
3796 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3797
3798 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3799 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3800 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3801 new_rtx = gen_const_mem (Pmode, new_rtx);
3802 temp = gen_reg_rtx (Pmode);
3803 emit_move_insn (temp, new_rtx);
3804 }
3805 else if (TARGET_CPU_ZARCH)
3806 {
3807 /* If the GOT offset might be >= 4k, we determine the position
3808 of the GOT entry via a PC-relative LARL. */
3809
3810 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3811 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3812 temp = gen_reg_rtx (Pmode);
3813 emit_move_insn (temp, new_rtx);
3814
3815 new_rtx = gen_const_mem (Pmode, temp);
3816 temp = gen_reg_rtx (Pmode);
3817 emit_move_insn (temp, new_rtx);
3818 }
3819 else if (flag_pic)
3820 {
3821 /* If the GOT offset might be >= 4k, we have to load it
3822 from the literal pool. */
3823
3824 if (reload_in_progress || reload_completed)
3825 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3826
3827 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3828 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3829 new_rtx = force_const_mem (Pmode, new_rtx);
3830 temp = gen_reg_rtx (Pmode);
3831 emit_move_insn (temp, new_rtx);
3832
3833 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3834 new_rtx = gen_const_mem (Pmode, new_rtx);
3835
3836 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3837 temp = gen_reg_rtx (Pmode);
3838 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3839 }
3840 else
3841 {
3842 /* In position-dependent code, load the absolute address of
3843 the GOT entry from the literal pool. */
3844
3845 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3846 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3847 new_rtx = force_const_mem (Pmode, new_rtx);
3848 temp = gen_reg_rtx (Pmode);
3849 emit_move_insn (temp, new_rtx);
3850
3851 new_rtx = temp;
3852 new_rtx = gen_const_mem (Pmode, new_rtx);
3853 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3854 temp = gen_reg_rtx (Pmode);
3855 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3856 }
3857
3858 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3859 if (reg != 0)
3860 {
3861 s390_load_address (reg, new_rtx);
3862 new_rtx = reg;
3863 }
3864 break;
3865
3866 case TLS_MODEL_LOCAL_EXEC:
3867 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3868 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3869 new_rtx = force_const_mem (Pmode, new_rtx);
3870 temp = gen_reg_rtx (Pmode);
3871 emit_move_insn (temp, new_rtx);
3872
3873 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3874 if (reg != 0)
3875 {
3876 s390_load_address (reg, new_rtx);
3877 new_rtx = reg;
3878 }
3879 break;
3880
3881 default:
3882 gcc_unreachable ();
3883 }
3884
3885 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3886 {
3887 switch (XINT (XEXP (addr, 0), 1))
3888 {
3889 case UNSPEC_INDNTPOFF:
3890 gcc_assert (TARGET_CPU_ZARCH);
3891 new_rtx = addr;
3892 break;
3893
3894 default:
3895 gcc_unreachable ();
3896 }
3897 }
3898
3899 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3900 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3901 {
3902 new_rtx = XEXP (XEXP (addr, 0), 0);
3903 if (GET_CODE (new_rtx) != SYMBOL_REF)
3904 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3905
3906 new_rtx = legitimize_tls_address (new_rtx, reg);
3907 new_rtx = plus_constant (Pmode, new_rtx,
3908 INTVAL (XEXP (XEXP (addr, 0), 1)));
3909 new_rtx = force_operand (new_rtx, 0);
3910 }
3911
3912 else
3913 gcc_unreachable (); /* for now ... */
3914
3915 return new_rtx;
3916 }
3917
3918 /* Emit insns making the address in operands[1] valid for a standard
3919 move to operands[0]. operands[1] is replaced by an address which
3920 should be used instead of the former RTX to emit the move
3921 pattern. */
3922
3923 void
3924 emit_symbolic_move (rtx *operands)
3925 {
3926 rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
3927
3928 if (GET_CODE (operands[0]) == MEM)
3929 operands[1] = force_reg (Pmode, operands[1]);
3930 else if (TLS_SYMBOLIC_CONST (operands[1]))
3931 operands[1] = legitimize_tls_address (operands[1], temp);
3932 else if (flag_pic)
3933 operands[1] = legitimize_pic_address (operands[1], temp);
3934 }
3935
3936 /* Try machine-dependent ways of modifying an illegitimate address X
3937 to be legitimate. If we find one, return the new, valid address.
3938
3939 OLDX is the address as it was before break_out_memory_refs was called.
3940 In some cases it is useful to look at this to decide what needs to be done.
3941
3942 MODE is the mode of the operand pointed to by X.
3943
3944 When -fpic is used, special handling is needed for symbolic references.
3945 See comments by legitimize_pic_address for details. */
3946
3947 static rtx
3948 s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3949 machine_mode mode ATTRIBUTE_UNUSED)
3950 {
3951 rtx constant_term = const0_rtx;
3952
3953 if (TLS_SYMBOLIC_CONST (x))
3954 {
3955 x = legitimize_tls_address (x, 0);
3956
3957 if (s390_legitimate_address_p (mode, x, FALSE))
3958 return x;
3959 }
3960 else if (GET_CODE (x) == PLUS
3961 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
3962 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
3963 {
3964 return x;
3965 }
3966 else if (flag_pic)
3967 {
3968 if (SYMBOLIC_CONST (x)
3969 || (GET_CODE (x) == PLUS
3970 && (SYMBOLIC_CONST (XEXP (x, 0))
3971 || SYMBOLIC_CONST (XEXP (x, 1)))))
3972 x = legitimize_pic_address (x, 0);
3973
3974 if (s390_legitimate_address_p (mode, x, FALSE))
3975 return x;
3976 }
3977
3978 x = eliminate_constant_term (x, &constant_term);
3979
3980 /* Optimize loading of large displacements by splitting them
3981 into the multiple of 4K and the rest; this allows the
3982 former to be CSE'd if possible.
3983
3984 Don't do this if the displacement is added to a register
3985 pointing into the stack frame, as the offsets will
3986 change later anyway. */
3987
3988 if (GET_CODE (constant_term) == CONST_INT
3989 && !TARGET_LONG_DISPLACEMENT
3990 && !DISP_IN_RANGE (INTVAL (constant_term))
3991 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3992 {
3993 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3994 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3995
3996 rtx temp = gen_reg_rtx (Pmode);
3997 rtx val = force_operand (GEN_INT (upper), temp);
3998 if (val != temp)
3999 emit_move_insn (temp, val);
4000
4001 x = gen_rtx_PLUS (Pmode, x, temp);
4002 constant_term = GEN_INT (lower);
4003 }
4004
4005 if (GET_CODE (x) == PLUS)
4006 {
4007 if (GET_CODE (XEXP (x, 0)) == REG)
4008 {
4009 rtx temp = gen_reg_rtx (Pmode);
4010 rtx val = force_operand (XEXP (x, 1), temp);
4011 if (val != temp)
4012 emit_move_insn (temp, val);
4013
4014 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
4015 }
4016
4017 else if (GET_CODE (XEXP (x, 1)) == REG)
4018 {
4019 rtx temp = gen_reg_rtx (Pmode);
4020 rtx val = force_operand (XEXP (x, 0), temp);
4021 if (val != temp)
4022 emit_move_insn (temp, val);
4023
4024 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
4025 }
4026 }
4027
4028 if (constant_term != const0_rtx)
4029 x = gen_rtx_PLUS (Pmode, x, constant_term);
4030
4031 return x;
4032 }
4033
4034 /* Try a machine-dependent way of reloading an illegitimate address AD
4035 operand. If we find one, push the reload and return the new address.
4036
4037 MODE is the mode of the enclosing MEM. OPNUM is the operand number
4038 and TYPE is the reload type of the current reload. */
4039
4040 rtx
4041 legitimize_reload_address (rtx ad, machine_mode mode ATTRIBUTE_UNUSED,
4042 int opnum, int type)
4043 {
4044 if (!optimize || TARGET_LONG_DISPLACEMENT)
4045 return NULL_RTX;
4046
4047 if (GET_CODE (ad) == PLUS)
4048 {
4049 rtx tem = simplify_binary_operation (PLUS, Pmode,
4050 XEXP (ad, 0), XEXP (ad, 1));
4051 if (tem)
4052 ad = tem;
4053 }
4054
4055 if (GET_CODE (ad) == PLUS
4056 && GET_CODE (XEXP (ad, 0)) == REG
4057 && GET_CODE (XEXP (ad, 1)) == CONST_INT
4058 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
4059 {
4060 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
4061 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
4062 rtx cst, tem, new_rtx;
4063
4064 cst = GEN_INT (upper);
4065 if (!legitimate_reload_constant_p (cst))
4066 cst = force_const_mem (Pmode, cst);
4067
4068 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
4069 new_rtx = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
4070
4071 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
4072 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
4073 opnum, (enum reload_type) type);
4074 return new_rtx;
4075 }
4076
4077 return NULL_RTX;
4078 }
4079
4080 /* Emit code to move LEN bytes from DST to SRC. */
4081
4082 bool
4083 s390_expand_movmem (rtx dst, rtx src, rtx len)
4084 {
4085 /* When tuning for z10 or higher we rely on the Glibc functions to
4086 do the right thing. Only for constant lengths below 64k we will
4087 generate inline code. */
4088 if (s390_tune >= PROCESSOR_2097_Z10
4089 && (GET_CODE (len) != CONST_INT || INTVAL (len) > (1<<16)))
4090 return false;
4091
4092 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4093 {
4094 if (INTVAL (len) > 0)
4095 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
4096 }
4097
4098 else if (TARGET_MVCLE)
4099 {
4100 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
4101 }
4102
4103 else
4104 {
4105 rtx dst_addr, src_addr, count, blocks, temp;
4106 rtx_code_label *loop_start_label = gen_label_rtx ();
4107 rtx_code_label *loop_end_label = gen_label_rtx ();
4108 rtx_code_label *end_label = gen_label_rtx ();
4109 machine_mode mode;
4110
4111 mode = GET_MODE (len);
4112 if (mode == VOIDmode)
4113 mode = Pmode;
4114
4115 dst_addr = gen_reg_rtx (Pmode);
4116 src_addr = gen_reg_rtx (Pmode);
4117 count = gen_reg_rtx (mode);
4118 blocks = gen_reg_rtx (mode);
4119
4120 convert_move (count, len, 1);
4121 emit_cmp_and_jump_insns (count, const0_rtx,
4122 EQ, NULL_RTX, mode, 1, end_label);
4123
4124 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4125 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
4126 dst = change_address (dst, VOIDmode, dst_addr);
4127 src = change_address (src, VOIDmode, src_addr);
4128
4129 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4130 OPTAB_DIRECT);
4131 if (temp != count)
4132 emit_move_insn (count, temp);
4133
4134 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4135 OPTAB_DIRECT);
4136 if (temp != blocks)
4137 emit_move_insn (blocks, temp);
4138
4139 emit_cmp_and_jump_insns (blocks, const0_rtx,
4140 EQ, NULL_RTX, mode, 1, loop_end_label);
4141
4142 emit_label (loop_start_label);
4143
4144 if (TARGET_Z10
4145 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 768))
4146 {
4147 rtx prefetch;
4148
4149 /* Issue a read prefetch for the +3 cache line. */
4150 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, src_addr, GEN_INT (768)),
4151 const0_rtx, const0_rtx);
4152 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4153 emit_insn (prefetch);
4154
4155 /* Issue a write prefetch for the +3 cache line. */
4156 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (768)),
4157 const1_rtx, const0_rtx);
4158 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4159 emit_insn (prefetch);
4160 }
4161
4162 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
4163 s390_load_address (dst_addr,
4164 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4165 s390_load_address (src_addr,
4166 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
4167
4168 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4169 OPTAB_DIRECT);
4170 if (temp != blocks)
4171 emit_move_insn (blocks, temp);
4172
4173 emit_cmp_and_jump_insns (blocks, const0_rtx,
4174 EQ, NULL_RTX, mode, 1, loop_end_label);
4175
4176 emit_jump (loop_start_label);
4177 emit_label (loop_end_label);
4178
4179 emit_insn (gen_movmem_short (dst, src,
4180 convert_to_mode (Pmode, count, 1)));
4181 emit_label (end_label);
4182 }
4183 return true;
4184 }
4185
4186 /* Emit code to set LEN bytes at DST to VAL.
4187 Make use of clrmem if VAL is zero. */
4188
4189 void
4190 s390_expand_setmem (rtx dst, rtx len, rtx val)
4191 {
4192 if (GET_CODE (len) == CONST_INT && INTVAL (len) == 0)
4193 return;
4194
4195 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
4196
4197 if (GET_CODE (len) == CONST_INT && INTVAL (len) > 0 && INTVAL (len) <= 257)
4198 {
4199 if (val == const0_rtx && INTVAL (len) <= 256)
4200 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
4201 else
4202 {
4203 /* Initialize memory by storing the first byte. */
4204 emit_move_insn (adjust_address (dst, QImode, 0), val);
4205
4206 if (INTVAL (len) > 1)
4207 {
4208 /* Initiate 1 byte overlap move.
4209 The first byte of DST is propagated through DSTP1.
4210 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
4211 DST is set to size 1 so the rest of the memory location
4212 does not count as source operand. */
4213 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
4214 set_mem_size (dst, 1);
4215
4216 emit_insn (gen_movmem_short (dstp1, dst,
4217 GEN_INT (INTVAL (len) - 2)));
4218 }
4219 }
4220 }
4221
4222 else if (TARGET_MVCLE)
4223 {
4224 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
4225 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
4226 }
4227
4228 else
4229 {
4230 rtx dst_addr, count, blocks, temp, dstp1 = NULL_RTX;
4231 rtx_code_label *loop_start_label = gen_label_rtx ();
4232 rtx_code_label *loop_end_label = gen_label_rtx ();
4233 rtx_code_label *end_label = gen_label_rtx ();
4234 machine_mode mode;
4235
4236 mode = GET_MODE (len);
4237 if (mode == VOIDmode)
4238 mode = Pmode;
4239
4240 dst_addr = gen_reg_rtx (Pmode);
4241 count = gen_reg_rtx (mode);
4242 blocks = gen_reg_rtx (mode);
4243
4244 convert_move (count, len, 1);
4245 emit_cmp_and_jump_insns (count, const0_rtx,
4246 EQ, NULL_RTX, mode, 1, end_label);
4247
4248 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4249 dst = change_address (dst, VOIDmode, dst_addr);
4250
4251 if (val == const0_rtx)
4252 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4253 OPTAB_DIRECT);
4254 else
4255 {
4256 dstp1 = adjust_address (dst, VOIDmode, 1);
4257 set_mem_size (dst, 1);
4258
4259 /* Initialize memory by storing the first byte. */
4260 emit_move_insn (adjust_address (dst, QImode, 0), val);
4261
4262 /* If count is 1 we are done. */
4263 emit_cmp_and_jump_insns (count, const1_rtx,
4264 EQ, NULL_RTX, mode, 1, end_label);
4265
4266 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1,
4267 OPTAB_DIRECT);
4268 }
4269 if (temp != count)
4270 emit_move_insn (count, temp);
4271
4272 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4273 OPTAB_DIRECT);
4274 if (temp != blocks)
4275 emit_move_insn (blocks, temp);
4276
4277 emit_cmp_and_jump_insns (blocks, const0_rtx,
4278 EQ, NULL_RTX, mode, 1, loop_end_label);
4279
4280 emit_label (loop_start_label);
4281
4282 if (TARGET_Z10
4283 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 1024))
4284 {
4285 /* Issue a write prefetch for the +4 cache line. */
4286 rtx prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr,
4287 GEN_INT (1024)),
4288 const1_rtx, const0_rtx);
4289 emit_insn (prefetch);
4290 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4291 }
4292
4293 if (val == const0_rtx)
4294 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
4295 else
4296 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
4297 s390_load_address (dst_addr,
4298 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4299
4300 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4301 OPTAB_DIRECT);
4302 if (temp != blocks)
4303 emit_move_insn (blocks, temp);
4304
4305 emit_cmp_and_jump_insns (blocks, const0_rtx,
4306 EQ, NULL_RTX, mode, 1, loop_end_label);
4307
4308 emit_jump (loop_start_label);
4309 emit_label (loop_end_label);
4310
4311 if (val == const0_rtx)
4312 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
4313 else
4314 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
4315 emit_label (end_label);
4316 }
4317 }
4318
4319 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4320 and return the result in TARGET. */
4321
4322 bool
4323 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
4324 {
4325 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
4326 rtx tmp;
4327
4328 /* When tuning for z10 or higher we rely on the Glibc functions to
4329 do the right thing. Only for constant lengths below 64k we will
4330 generate inline code. */
4331 if (s390_tune >= PROCESSOR_2097_Z10
4332 && (GET_CODE (len) != CONST_INT || INTVAL (len) > (1<<16)))
4333 return false;
4334
4335 /* As the result of CMPINT is inverted compared to what we need,
4336 we have to swap the operands. */
4337 tmp = op0; op0 = op1; op1 = tmp;
4338
4339 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4340 {
4341 if (INTVAL (len) > 0)
4342 {
4343 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
4344 emit_insn (gen_cmpint (target, ccreg));
4345 }
4346 else
4347 emit_move_insn (target, const0_rtx);
4348 }
4349 else if (TARGET_MVCLE)
4350 {
4351 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
4352 emit_insn (gen_cmpint (target, ccreg));
4353 }
4354 else
4355 {
4356 rtx addr0, addr1, count, blocks, temp;
4357 rtx_code_label *loop_start_label = gen_label_rtx ();
4358 rtx_code_label *loop_end_label = gen_label_rtx ();
4359 rtx_code_label *end_label = gen_label_rtx ();
4360 machine_mode mode;
4361
4362 mode = GET_MODE (len);
4363 if (mode == VOIDmode)
4364 mode = Pmode;
4365
4366 addr0 = gen_reg_rtx (Pmode);
4367 addr1 = gen_reg_rtx (Pmode);
4368 count = gen_reg_rtx (mode);
4369 blocks = gen_reg_rtx (mode);
4370
4371 convert_move (count, len, 1);
4372 emit_cmp_and_jump_insns (count, const0_rtx,
4373 EQ, NULL_RTX, mode, 1, end_label);
4374
4375 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
4376 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
4377 op0 = change_address (op0, VOIDmode, addr0);
4378 op1 = change_address (op1, VOIDmode, addr1);
4379
4380 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4381 OPTAB_DIRECT);
4382 if (temp != count)
4383 emit_move_insn (count, temp);
4384
4385 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4386 OPTAB_DIRECT);
4387 if (temp != blocks)
4388 emit_move_insn (blocks, temp);
4389
4390 emit_cmp_and_jump_insns (blocks, const0_rtx,
4391 EQ, NULL_RTX, mode, 1, loop_end_label);
4392
4393 emit_label (loop_start_label);
4394
4395 if (TARGET_Z10
4396 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 512))
4397 {
4398 rtx prefetch;
4399
4400 /* Issue a read prefetch for the +2 cache line of operand 1. */
4401 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr0, GEN_INT (512)),
4402 const0_rtx, const0_rtx);
4403 emit_insn (prefetch);
4404 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4405
4406 /* Issue a read prefetch for the +2 cache line of operand 2. */
4407 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr1, GEN_INT (512)),
4408 const0_rtx, const0_rtx);
4409 emit_insn (prefetch);
4410 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4411 }
4412
4413 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
4414 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
4415 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
4416 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
4417 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
4418 emit_jump_insn (temp);
4419
4420 s390_load_address (addr0,
4421 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
4422 s390_load_address (addr1,
4423 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
4424
4425 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4426 OPTAB_DIRECT);
4427 if (temp != blocks)
4428 emit_move_insn (blocks, temp);
4429
4430 emit_cmp_and_jump_insns (blocks, const0_rtx,
4431 EQ, NULL_RTX, mode, 1, loop_end_label);
4432
4433 emit_jump (loop_start_label);
4434 emit_label (loop_end_label);
4435
4436 emit_insn (gen_cmpmem_short (op0, op1,
4437 convert_to_mode (Pmode, count, 1)));
4438 emit_label (end_label);
4439
4440 emit_insn (gen_cmpint (target, ccreg));
4441 }
4442 return true;
4443 }
4444
4445
4446 /* Expand conditional increment or decrement using alc/slb instructions.
4447 Should generate code setting DST to either SRC or SRC + INCREMENT,
4448 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4449 Returns true if successful, false otherwise.
4450
4451 That makes it possible to implement some if-constructs without jumps e.g.:
4452 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4453 unsigned int a, b, c;
4454 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4455 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4456 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4457 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4458
4459 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4460 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4461 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4462 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4463 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4464
4465 bool
4466 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
4467 rtx dst, rtx src, rtx increment)
4468 {
4469 machine_mode cmp_mode;
4470 machine_mode cc_mode;
4471 rtx op_res;
4472 rtx insn;
4473 rtvec p;
4474 int ret;
4475
4476 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
4477 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
4478 cmp_mode = SImode;
4479 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
4480 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
4481 cmp_mode = DImode;
4482 else
4483 return false;
4484
4485 /* Try ADD LOGICAL WITH CARRY. */
4486 if (increment == const1_rtx)
4487 {
4488 /* Determine CC mode to use. */
4489 if (cmp_code == EQ || cmp_code == NE)
4490 {
4491 if (cmp_op1 != const0_rtx)
4492 {
4493 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4494 NULL_RTX, 0, OPTAB_WIDEN);
4495 cmp_op1 = const0_rtx;
4496 }
4497
4498 cmp_code = cmp_code == EQ ? LEU : GTU;
4499 }
4500
4501 if (cmp_code == LTU || cmp_code == LEU)
4502 {
4503 rtx tem = cmp_op0;
4504 cmp_op0 = cmp_op1;
4505 cmp_op1 = tem;
4506 cmp_code = swap_condition (cmp_code);
4507 }
4508
4509 switch (cmp_code)
4510 {
4511 case GTU:
4512 cc_mode = CCUmode;
4513 break;
4514
4515 case GEU:
4516 cc_mode = CCL3mode;
4517 break;
4518
4519 default:
4520 return false;
4521 }
4522
4523 /* Emit comparison instruction pattern. */
4524 if (!register_operand (cmp_op0, cmp_mode))
4525 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4526
4527 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4528 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4529 /* We use insn_invalid_p here to add clobbers if required. */
4530 ret = insn_invalid_p (emit_insn (insn), false);
4531 gcc_assert (!ret);
4532
4533 /* Emit ALC instruction pattern. */
4534 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4535 gen_rtx_REG (cc_mode, CC_REGNUM),
4536 const0_rtx);
4537
4538 if (src != const0_rtx)
4539 {
4540 if (!register_operand (src, GET_MODE (dst)))
4541 src = force_reg (GET_MODE (dst), src);
4542
4543 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src);
4544 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx);
4545 }
4546
4547 p = rtvec_alloc (2);
4548 RTVEC_ELT (p, 0) =
4549 gen_rtx_SET (VOIDmode, dst, op_res);
4550 RTVEC_ELT (p, 1) =
4551 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4552 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4553
4554 return true;
4555 }
4556
4557 /* Try SUBTRACT LOGICAL WITH BORROW. */
4558 if (increment == constm1_rtx)
4559 {
4560 /* Determine CC mode to use. */
4561 if (cmp_code == EQ || cmp_code == NE)
4562 {
4563 if (cmp_op1 != const0_rtx)
4564 {
4565 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4566 NULL_RTX, 0, OPTAB_WIDEN);
4567 cmp_op1 = const0_rtx;
4568 }
4569
4570 cmp_code = cmp_code == EQ ? LEU : GTU;
4571 }
4572
4573 if (cmp_code == GTU || cmp_code == GEU)
4574 {
4575 rtx tem = cmp_op0;
4576 cmp_op0 = cmp_op1;
4577 cmp_op1 = tem;
4578 cmp_code = swap_condition (cmp_code);
4579 }
4580
4581 switch (cmp_code)
4582 {
4583 case LEU:
4584 cc_mode = CCUmode;
4585 break;
4586
4587 case LTU:
4588 cc_mode = CCL3mode;
4589 break;
4590
4591 default:
4592 return false;
4593 }
4594
4595 /* Emit comparison instruction pattern. */
4596 if (!register_operand (cmp_op0, cmp_mode))
4597 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4598
4599 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4600 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4601 /* We use insn_invalid_p here to add clobbers if required. */
4602 ret = insn_invalid_p (emit_insn (insn), false);
4603 gcc_assert (!ret);
4604
4605 /* Emit SLB instruction pattern. */
4606 if (!register_operand (src, GET_MODE (dst)))
4607 src = force_reg (GET_MODE (dst), src);
4608
4609 op_res = gen_rtx_MINUS (GET_MODE (dst),
4610 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
4611 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4612 gen_rtx_REG (cc_mode, CC_REGNUM),
4613 const0_rtx));
4614 p = rtvec_alloc (2);
4615 RTVEC_ELT (p, 0) =
4616 gen_rtx_SET (VOIDmode, dst, op_res);
4617 RTVEC_ELT (p, 1) =
4618 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4619 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4620
4621 return true;
4622 }
4623
4624 return false;
4625 }
4626
4627 /* Expand code for the insv template. Return true if successful. */
4628
4629 bool
4630 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
4631 {
4632 int bitsize = INTVAL (op1);
4633 int bitpos = INTVAL (op2);
4634 machine_mode mode = GET_MODE (dest);
4635 machine_mode smode;
4636 int smode_bsize, mode_bsize;
4637 rtx op, clobber;
4638
4639 if (bitsize + bitpos > GET_MODE_BITSIZE (mode))
4640 return false;
4641
4642 /* Generate INSERT IMMEDIATE (IILL et al). */
4643 /* (set (ze (reg)) (const_int)). */
4644 if (TARGET_ZARCH
4645 && register_operand (dest, word_mode)
4646 && (bitpos % 16) == 0
4647 && (bitsize % 16) == 0
4648 && const_int_operand (src, VOIDmode))
4649 {
4650 HOST_WIDE_INT val = INTVAL (src);
4651 int regpos = bitpos + bitsize;
4652
4653 while (regpos > bitpos)
4654 {
4655 machine_mode putmode;
4656 int putsize;
4657
4658 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4659 putmode = SImode;
4660 else
4661 putmode = HImode;
4662
4663 putsize = GET_MODE_BITSIZE (putmode);
4664 regpos -= putsize;
4665 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4666 GEN_INT (putsize),
4667 GEN_INT (regpos)),
4668 gen_int_mode (val, putmode));
4669 val >>= putsize;
4670 }
4671 gcc_assert (regpos == bitpos);
4672 return true;
4673 }
4674
4675 smode = smallest_mode_for_size (bitsize, MODE_INT);
4676 smode_bsize = GET_MODE_BITSIZE (smode);
4677 mode_bsize = GET_MODE_BITSIZE (mode);
4678
4679 /* Generate STORE CHARACTERS UNDER MASK (STCM et al). */
4680 if (bitpos == 0
4681 && (bitsize % BITS_PER_UNIT) == 0
4682 && MEM_P (dest)
4683 && (register_operand (src, word_mode)
4684 || const_int_operand (src, VOIDmode)))
4685 {
4686 /* Emit standard pattern if possible. */
4687 if (smode_bsize == bitsize)
4688 {
4689 emit_move_insn (adjust_address (dest, smode, 0),
4690 gen_lowpart (smode, src));
4691 return true;
4692 }
4693
4694 /* (set (ze (mem)) (const_int)). */
4695 else if (const_int_operand (src, VOIDmode))
4696 {
4697 int size = bitsize / BITS_PER_UNIT;
4698 rtx src_mem = adjust_address (force_const_mem (word_mode, src),
4699 BLKmode,
4700 UNITS_PER_WORD - size);
4701
4702 dest = adjust_address (dest, BLKmode, 0);
4703 set_mem_size (dest, size);
4704 s390_expand_movmem (dest, src_mem, GEN_INT (size));
4705 return true;
4706 }
4707
4708 /* (set (ze (mem)) (reg)). */
4709 else if (register_operand (src, word_mode))
4710 {
4711 if (bitsize <= 32)
4712 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4713 const0_rtx), src);
4714 else
4715 {
4716 /* Emit st,stcmh sequence. */
4717 int stcmh_width = bitsize - 32;
4718 int size = stcmh_width / BITS_PER_UNIT;
4719
4720 emit_move_insn (adjust_address (dest, SImode, size),
4721 gen_lowpart (SImode, src));
4722 set_mem_size (dest, size);
4723 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4724 GEN_INT (stcmh_width),
4725 const0_rtx),
4726 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT (32)));
4727 }
4728 return true;
4729 }
4730 }
4731
4732 /* Generate INSERT CHARACTERS UNDER MASK (IC, ICM et al). */
4733 if ((bitpos % BITS_PER_UNIT) == 0
4734 && (bitsize % BITS_PER_UNIT) == 0
4735 && (bitpos & 32) == ((bitpos + bitsize - 1) & 32)
4736 && MEM_P (src)
4737 && (mode == DImode || mode == SImode)
4738 && register_operand (dest, mode))
4739 {
4740 /* Emit a strict_low_part pattern if possible. */
4741 if (smode_bsize == bitsize && bitpos == mode_bsize - smode_bsize)
4742 {
4743 op = gen_rtx_STRICT_LOW_PART (VOIDmode, gen_lowpart (smode, dest));
4744 op = gen_rtx_SET (VOIDmode, op, gen_lowpart (smode, src));
4745 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4746 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)));
4747 return true;
4748 }
4749
4750 /* ??? There are more powerful versions of ICM that are not
4751 completely represented in the md file. */
4752 }
4753
4754 /* For z10, generate ROTATE THEN INSERT SELECTED BITS (RISBG et al). */
4755 if (TARGET_Z10 && (mode == DImode || mode == SImode))
4756 {
4757 machine_mode mode_s = GET_MODE (src);
4758
4759 if (mode_s == VOIDmode)
4760 {
4761 /* Assume const_int etc already in the proper mode. */
4762 src = force_reg (mode, src);
4763 }
4764 else if (mode_s != mode)
4765 {
4766 gcc_assert (GET_MODE_BITSIZE (mode_s) >= bitsize);
4767 src = force_reg (mode_s, src);
4768 src = gen_lowpart (mode, src);
4769 }
4770
4771 op = gen_rtx_ZERO_EXTRACT (mode, dest, op1, op2),
4772 op = gen_rtx_SET (VOIDmode, op, src);
4773
4774 if (!TARGET_ZEC12)
4775 {
4776 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4777 op = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber));
4778 }
4779 emit_insn (op);
4780
4781 return true;
4782 }
4783
4784 return false;
4785 }
4786
4787 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4788 register that holds VAL of mode MODE shifted by COUNT bits. */
4789
4790 static inline rtx
4791 s390_expand_mask_and_shift (rtx val, machine_mode mode, rtx count)
4792 {
4793 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4794 NULL_RTX, 1, OPTAB_DIRECT);
4795 return expand_simple_binop (SImode, ASHIFT, val, count,
4796 NULL_RTX, 1, OPTAB_DIRECT);
4797 }
4798
4799 /* Structure to hold the initial parameters for a compare_and_swap operation
4800 in HImode and QImode. */
4801
4802 struct alignment_context
4803 {
4804 rtx memsi; /* SI aligned memory location. */
4805 rtx shift; /* Bit offset with regard to lsb. */
4806 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4807 rtx modemaski; /* ~modemask */
4808 bool aligned; /* True if memory is aligned, false else. */
4809 };
4810
4811 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4812 structure AC for transparent simplifying, if the memory alignment is known
4813 to be at least 32bit. MEM is the memory location for the actual operation
4814 and MODE its mode. */
4815
4816 static void
4817 init_alignment_context (struct alignment_context *ac, rtx mem,
4818 machine_mode mode)
4819 {
4820 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4821 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4822
4823 if (ac->aligned)
4824 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4825 else
4826 {
4827 /* Alignment is unknown. */
4828 rtx byteoffset, addr, align;
4829
4830 /* Force the address into a register. */
4831 addr = force_reg (Pmode, XEXP (mem, 0));
4832
4833 /* Align it to SImode. */
4834 align = expand_simple_binop (Pmode, AND, addr,
4835 GEN_INT (-GET_MODE_SIZE (SImode)),
4836 NULL_RTX, 1, OPTAB_DIRECT);
4837 /* Generate MEM. */
4838 ac->memsi = gen_rtx_MEM (SImode, align);
4839 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4840 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4841 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4842
4843 /* Calculate shiftcount. */
4844 byteoffset = expand_simple_binop (Pmode, AND, addr,
4845 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4846 NULL_RTX, 1, OPTAB_DIRECT);
4847 /* As we already have some offset, evaluate the remaining distance. */
4848 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4849 NULL_RTX, 1, OPTAB_DIRECT);
4850 }
4851
4852 /* Shift is the byte count, but we need the bitcount. */
4853 ac->shift = expand_simple_binop (SImode, ASHIFT, ac->shift, GEN_INT (3),
4854 NULL_RTX, 1, OPTAB_DIRECT);
4855
4856 /* Calculate masks. */
4857 ac->modemask = expand_simple_binop (SImode, ASHIFT,
4858 GEN_INT (GET_MODE_MASK (mode)),
4859 ac->shift, NULL_RTX, 1, OPTAB_DIRECT);
4860 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask,
4861 NULL_RTX, 1);
4862 }
4863
4864 /* A subroutine of s390_expand_cs_hqi. Insert INS into VAL. If possible,
4865 use a single insv insn into SEQ2. Otherwise, put prep insns in SEQ1 and
4866 perform the merge in SEQ2. */
4867
4868 static rtx
4869 s390_two_part_insv (struct alignment_context *ac, rtx *seq1, rtx *seq2,
4870 machine_mode mode, rtx val, rtx ins)
4871 {
4872 rtx tmp;
4873
4874 if (ac->aligned)
4875 {
4876 start_sequence ();
4877 tmp = copy_to_mode_reg (SImode, val);
4878 if (s390_expand_insv (tmp, GEN_INT (GET_MODE_BITSIZE (mode)),
4879 const0_rtx, ins))
4880 {
4881 *seq1 = NULL;
4882 *seq2 = get_insns ();
4883 end_sequence ();
4884 return tmp;
4885 }
4886 end_sequence ();
4887 }
4888
4889 /* Failed to use insv. Generate a two part shift and mask. */
4890 start_sequence ();
4891 tmp = s390_expand_mask_and_shift (ins, mode, ac->shift);
4892 *seq1 = get_insns ();
4893 end_sequence ();
4894
4895 start_sequence ();
4896 tmp = expand_simple_binop (SImode, IOR, tmp, val, NULL_RTX, 1, OPTAB_DIRECT);
4897 *seq2 = get_insns ();
4898 end_sequence ();
4899
4900 return tmp;
4901 }
4902
4903 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4904 the memory location, CMP the old value to compare MEM with and NEW_RTX the
4905 value to set if CMP == MEM. */
4906
4907 void
4908 s390_expand_cs_hqi (machine_mode mode, rtx btarget, rtx vtarget, rtx mem,
4909 rtx cmp, rtx new_rtx, bool is_weak)
4910 {
4911 struct alignment_context ac;
4912 rtx cmpv, newv, val, cc, seq0, seq1, seq2, seq3;
4913 rtx res = gen_reg_rtx (SImode);
4914 rtx_code_label *csloop = NULL, *csend = NULL;
4915
4916 gcc_assert (MEM_P (mem));
4917
4918 init_alignment_context (&ac, mem, mode);
4919
4920 /* Load full word. Subsequent loads are performed by CS. */
4921 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4922 NULL_RTX, 1, OPTAB_DIRECT);
4923
4924 /* Prepare insertions of cmp and new_rtx into the loaded value. When
4925 possible, we try to use insv to make this happen efficiently. If
4926 that fails we'll generate code both inside and outside the loop. */
4927 cmpv = s390_two_part_insv (&ac, &seq0, &seq2, mode, val, cmp);
4928 newv = s390_two_part_insv (&ac, &seq1, &seq3, mode, val, new_rtx);
4929
4930 if (seq0)
4931 emit_insn (seq0);
4932 if (seq1)
4933 emit_insn (seq1);
4934
4935 /* Start CS loop. */
4936 if (!is_weak)
4937 {
4938 /* Begin assuming success. */
4939 emit_move_insn (btarget, const1_rtx);
4940
4941 csloop = gen_label_rtx ();
4942 csend = gen_label_rtx ();
4943 emit_label (csloop);
4944 }
4945
4946 /* val = "<mem>00..0<mem>"
4947 * cmp = "00..0<cmp>00..0"
4948 * new = "00..0<new>00..0"
4949 */
4950
4951 emit_insn (seq2);
4952 emit_insn (seq3);
4953
4954 cc = s390_emit_compare_and_swap (EQ, res, ac.memsi, cmpv, newv);
4955 if (is_weak)
4956 emit_insn (gen_cstorecc4 (btarget, cc, XEXP (cc, 0), XEXP (cc, 1)));
4957 else
4958 {
4959 rtx tmp;
4960
4961 /* Jump to end if we're done (likely?). */
4962 s390_emit_jump (csend, cc);
4963
4964 /* Check for changes outside mode, and loop internal if so.
4965 Arrange the moves so that the compare is adjacent to the
4966 branch so that we can generate CRJ. */
4967 tmp = copy_to_reg (val);
4968 force_expand_binop (SImode, and_optab, res, ac.modemaski, val,
4969 1, OPTAB_DIRECT);
4970 cc = s390_emit_compare (NE, val, tmp);
4971 s390_emit_jump (csloop, cc);
4972
4973 /* Failed. */
4974 emit_move_insn (btarget, const0_rtx);
4975 emit_label (csend);
4976 }
4977
4978 /* Return the correct part of the bitfield. */
4979 convert_move (vtarget, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4980 NULL_RTX, 1, OPTAB_DIRECT), 1);
4981 }
4982
4983 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4984 and VAL the value to play with. If AFTER is true then store the value
4985 MEM holds after the operation, if AFTER is false then store the value MEM
4986 holds before the operation. If TARGET is zero then discard that value, else
4987 store it to TARGET. */
4988
4989 void
4990 s390_expand_atomic (machine_mode mode, enum rtx_code code,
4991 rtx target, rtx mem, rtx val, bool after)
4992 {
4993 struct alignment_context ac;
4994 rtx cmp;
4995 rtx new_rtx = gen_reg_rtx (SImode);
4996 rtx orig = gen_reg_rtx (SImode);
4997 rtx_code_label *csloop = gen_label_rtx ();
4998
4999 gcc_assert (!target || register_operand (target, VOIDmode));
5000 gcc_assert (MEM_P (mem));
5001
5002 init_alignment_context (&ac, mem, mode);
5003
5004 /* Shift val to the correct bit positions.
5005 Preserve "icm", but prevent "ex icm". */
5006 if (!(ac.aligned && code == SET && MEM_P (val)))
5007 val = s390_expand_mask_and_shift (val, mode, ac.shift);
5008
5009 /* Further preparation insns. */
5010 if (code == PLUS || code == MINUS)
5011 emit_move_insn (orig, val);
5012 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
5013 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
5014 NULL_RTX, 1, OPTAB_DIRECT);
5015
5016 /* Load full word. Subsequent loads are performed by CS. */
5017 cmp = force_reg (SImode, ac.memsi);
5018
5019 /* Start CS loop. */
5020 emit_label (csloop);
5021 emit_move_insn (new_rtx, cmp);
5022
5023 /* Patch new with val at correct position. */
5024 switch (code)
5025 {
5026 case PLUS:
5027 case MINUS:
5028 val = expand_simple_binop (SImode, code, new_rtx, orig,
5029 NULL_RTX, 1, OPTAB_DIRECT);
5030 val = expand_simple_binop (SImode, AND, val, ac.modemask,
5031 NULL_RTX, 1, OPTAB_DIRECT);
5032 /* FALLTHRU */
5033 case SET:
5034 if (ac.aligned && MEM_P (val))
5035 store_bit_field (new_rtx, GET_MODE_BITSIZE (mode), 0,
5036 0, 0, SImode, val);
5037 else
5038 {
5039 new_rtx = expand_simple_binop (SImode, AND, new_rtx, ac.modemaski,
5040 NULL_RTX, 1, OPTAB_DIRECT);
5041 new_rtx = expand_simple_binop (SImode, IOR, new_rtx, val,
5042 NULL_RTX, 1, OPTAB_DIRECT);
5043 }
5044 break;
5045 case AND:
5046 case IOR:
5047 case XOR:
5048 new_rtx = expand_simple_binop (SImode, code, new_rtx, val,
5049 NULL_RTX, 1, OPTAB_DIRECT);
5050 break;
5051 case MULT: /* NAND */
5052 new_rtx = expand_simple_binop (SImode, AND, new_rtx, val,
5053 NULL_RTX, 1, OPTAB_DIRECT);
5054 new_rtx = expand_simple_binop (SImode, XOR, new_rtx, ac.modemask,
5055 NULL_RTX, 1, OPTAB_DIRECT);
5056 break;
5057 default:
5058 gcc_unreachable ();
5059 }
5060
5061 s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp,
5062 ac.memsi, cmp, new_rtx));
5063
5064 /* Return the correct part of the bitfield. */
5065 if (target)
5066 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
5067 after ? new_rtx : cmp, ac.shift,
5068 NULL_RTX, 1, OPTAB_DIRECT), 1);
5069 }
5070
5071 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
5072 We need to emit DTP-relative relocations. */
5073
5074 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
5075
5076 static void
5077 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
5078 {
5079 switch (size)
5080 {
5081 case 4:
5082 fputs ("\t.long\t", file);
5083 break;
5084 case 8:
5085 fputs ("\t.quad\t", file);
5086 break;
5087 default:
5088 gcc_unreachable ();
5089 }
5090 output_addr_const (file, x);
5091 fputs ("@DTPOFF", file);
5092 }
5093
5094 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
5095 /* Implement TARGET_MANGLE_TYPE. */
5096
5097 static const char *
5098 s390_mangle_type (const_tree type)
5099 {
5100 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
5101 && TARGET_LONG_DOUBLE_128)
5102 return "g";
5103
5104 /* For all other types, use normal C++ mangling. */
5105 return NULL;
5106 }
5107 #endif
5108
5109 /* In the name of slightly smaller debug output, and to cater to
5110 general assembler lossage, recognize various UNSPEC sequences
5111 and turn them back into a direct symbol reference. */
5112
5113 static rtx
5114 s390_delegitimize_address (rtx orig_x)
5115 {
5116 rtx x, y;
5117
5118 orig_x = delegitimize_mem_from_attrs (orig_x);
5119 x = orig_x;
5120
5121 /* Extract the symbol ref from:
5122 (plus:SI (reg:SI 12 %r12)
5123 (const:SI (unspec:SI [(symbol_ref/f:SI ("*.LC0"))]
5124 UNSPEC_GOTOFF/PLTOFF)))
5125 and
5126 (plus:SI (reg:SI 12 %r12)
5127 (const:SI (plus:SI (unspec:SI [(symbol_ref:SI ("L"))]
5128 UNSPEC_GOTOFF/PLTOFF)
5129 (const_int 4 [0x4])))) */
5130 if (GET_CODE (x) == PLUS
5131 && REG_P (XEXP (x, 0))
5132 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM
5133 && GET_CODE (XEXP (x, 1)) == CONST)
5134 {
5135 HOST_WIDE_INT offset = 0;
5136
5137 /* The const operand. */
5138 y = XEXP (XEXP (x, 1), 0);
5139
5140 if (GET_CODE (y) == PLUS
5141 && GET_CODE (XEXP (y, 1)) == CONST_INT)
5142 {
5143 offset = INTVAL (XEXP (y, 1));
5144 y = XEXP (y, 0);
5145 }
5146
5147 if (GET_CODE (y) == UNSPEC
5148 && (XINT (y, 1) == UNSPEC_GOTOFF
5149 || XINT (y, 1) == UNSPEC_PLTOFF))
5150 return plus_constant (Pmode, XVECEXP (y, 0, 0), offset);
5151 }
5152
5153 if (GET_CODE (x) != MEM)
5154 return orig_x;
5155
5156 x = XEXP (x, 0);
5157 if (GET_CODE (x) == PLUS
5158 && GET_CODE (XEXP (x, 1)) == CONST
5159 && GET_CODE (XEXP (x, 0)) == REG
5160 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
5161 {
5162 y = XEXP (XEXP (x, 1), 0);
5163 if (GET_CODE (y) == UNSPEC
5164 && XINT (y, 1) == UNSPEC_GOT)
5165 y = XVECEXP (y, 0, 0);
5166 else
5167 return orig_x;
5168 }
5169 else if (GET_CODE (x) == CONST)
5170 {
5171 /* Extract the symbol ref from:
5172 (mem:QI (const:DI (unspec:DI [(symbol_ref:DI ("foo"))]
5173 UNSPEC_PLT/GOTENT))) */
5174
5175 y = XEXP (x, 0);
5176 if (GET_CODE (y) == UNSPEC
5177 && (XINT (y, 1) == UNSPEC_GOTENT
5178 || XINT (y, 1) == UNSPEC_PLT))
5179 y = XVECEXP (y, 0, 0);
5180 else
5181 return orig_x;
5182 }
5183 else
5184 return orig_x;
5185
5186 if (GET_MODE (orig_x) != Pmode)
5187 {
5188 if (GET_MODE (orig_x) == BLKmode)
5189 return orig_x;
5190 y = lowpart_subreg (GET_MODE (orig_x), y, Pmode);
5191 if (y == NULL_RTX)
5192 return orig_x;
5193 }
5194 return y;
5195 }
5196
5197 /* Output operand OP to stdio stream FILE.
5198 OP is an address (register + offset) which is not used to address data;
5199 instead the rightmost bits are interpreted as the value. */
5200
5201 static void
5202 print_shift_count_operand (FILE *file, rtx op)
5203 {
5204 HOST_WIDE_INT offset;
5205 rtx base;
5206
5207 /* Extract base register and offset. */
5208 if (!s390_decompose_shift_count (op, &base, &offset))
5209 gcc_unreachable ();
5210
5211 /* Sanity check. */
5212 if (base)
5213 {
5214 gcc_assert (GET_CODE (base) == REG);
5215 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
5216 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
5217 }
5218
5219 /* Offsets are constricted to twelve bits. */
5220 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
5221 if (base)
5222 fprintf (file, "(%s)", reg_names[REGNO (base)]);
5223 }
5224
5225 /* Returns -1 if the function should not be made hotpatchable. Otherwise it
5226 returns a number >= 0 that is the desired size of the hotpatch trampoline
5227 in halfwords. */
5228
5229 static int s390_function_num_hotpatch_trampoline_halfwords (tree decl,
5230 bool do_warn)
5231 {
5232 tree attr;
5233
5234 if (DECL_DECLARED_INLINE_P (decl)
5235 || DECL_ARTIFICIAL (decl)
5236 || MAIN_NAME_P (DECL_NAME (decl)))
5237 {
5238 /* - Explicitly inlined functions cannot be hotpatched.
5239 - Artificial functions need not be hotpatched.
5240 - Making the main function hotpatchable is useless. */
5241 return -1;
5242 }
5243 attr = lookup_attribute ("hotpatch", DECL_ATTRIBUTES (decl));
5244 if (attr || s390_hotpatch_trampoline_halfwords >= 0)
5245 {
5246 if (lookup_attribute ("always_inline", DECL_ATTRIBUTES (decl)))
5247 {
5248 if (do_warn)
5249 warning (OPT_Wattributes, "function %qE with the %qs attribute"
5250 " is not hotpatchable", DECL_NAME (decl), "always_inline");
5251 return -1;
5252 }
5253 else
5254 {
5255 return (attr) ?
5256 get_hotpatch_attribute (attr) : s390_hotpatch_trampoline_halfwords;
5257 }
5258 }
5259
5260 return -1;
5261 }
5262
5263 /* Hook to determine if one function can safely inline another. */
5264
5265 static bool
5266 s390_can_inline_p (tree caller, tree callee)
5267 {
5268 if (s390_function_num_hotpatch_trampoline_halfwords (callee, false) >= 0)
5269 return false;
5270
5271 return default_target_can_inline_p (caller, callee);
5272 }
5273
5274 /* Write the extra assembler code needed to declare a function properly. */
5275
5276 void
5277 s390_asm_output_function_label (FILE *asm_out_file, const char *fname,
5278 tree decl)
5279 {
5280 int hotpatch_trampoline_halfwords = -1;
5281
5282 if (decl)
5283 {
5284 hotpatch_trampoline_halfwords =
5285 s390_function_num_hotpatch_trampoline_halfwords (decl, true);
5286 if (hotpatch_trampoline_halfwords >= 0
5287 && decl_function_context (decl) != NULL_TREE)
5288 {
5289 warning_at (DECL_SOURCE_LOCATION (decl), OPT_mhotpatch,
5290 "hotpatching is not compatible with nested functions");
5291 hotpatch_trampoline_halfwords = -1;
5292 }
5293 }
5294
5295 if (hotpatch_trampoline_halfwords > 0)
5296 {
5297 int i;
5298
5299 /* Add a trampoline code area before the function label and initialize it
5300 with two-byte nop instructions. This area can be overwritten with code
5301 that jumps to a patched version of the function. */
5302 for (i = 0; i < hotpatch_trampoline_halfwords; i++)
5303 asm_fprintf (asm_out_file, "\tnopr\t%%r7\n");
5304 /* Note: The function label must be aligned so that (a) the bytes of the
5305 following nop do not cross a cacheline boundary, and (b) a jump address
5306 (eight bytes for 64 bit targets, 4 bytes for 32 bit targets) can be
5307 stored directly before the label without crossing a cacheline
5308 boundary. All this is necessary to make sure the trampoline code can
5309 be changed atomically. */
5310 }
5311
5312 ASM_OUTPUT_LABEL (asm_out_file, fname);
5313
5314 /* Output a four-byte nop if hotpatching is enabled. This can be overwritten
5315 atomically with a relative backwards jump to the trampoline area. */
5316 if (hotpatch_trampoline_halfwords >= 0)
5317 asm_fprintf (asm_out_file, "\tnop\t0\n");
5318 }
5319
5320 /* Output machine-dependent UNSPECs occurring in address constant X
5321 in assembler syntax to stdio stream FILE. Returns true if the
5322 constant X could be recognized, false otherwise. */
5323
5324 static bool
5325 s390_output_addr_const_extra (FILE *file, rtx x)
5326 {
5327 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
5328 switch (XINT (x, 1))
5329 {
5330 case UNSPEC_GOTENT:
5331 output_addr_const (file, XVECEXP (x, 0, 0));
5332 fprintf (file, "@GOTENT");
5333 return true;
5334 case UNSPEC_GOT:
5335 output_addr_const (file, XVECEXP (x, 0, 0));
5336 fprintf (file, "@GOT");
5337 return true;
5338 case UNSPEC_GOTOFF:
5339 output_addr_const (file, XVECEXP (x, 0, 0));
5340 fprintf (file, "@GOTOFF");
5341 return true;
5342 case UNSPEC_PLT:
5343 output_addr_const (file, XVECEXP (x, 0, 0));
5344 fprintf (file, "@PLT");
5345 return true;
5346 case UNSPEC_PLTOFF:
5347 output_addr_const (file, XVECEXP (x, 0, 0));
5348 fprintf (file, "@PLTOFF");
5349 return true;
5350 case UNSPEC_TLSGD:
5351 output_addr_const (file, XVECEXP (x, 0, 0));
5352 fprintf (file, "@TLSGD");
5353 return true;
5354 case UNSPEC_TLSLDM:
5355 assemble_name (file, get_some_local_dynamic_name ());
5356 fprintf (file, "@TLSLDM");
5357 return true;
5358 case UNSPEC_DTPOFF:
5359 output_addr_const (file, XVECEXP (x, 0, 0));
5360 fprintf (file, "@DTPOFF");
5361 return true;
5362 case UNSPEC_NTPOFF:
5363 output_addr_const (file, XVECEXP (x, 0, 0));
5364 fprintf (file, "@NTPOFF");
5365 return true;
5366 case UNSPEC_GOTNTPOFF:
5367 output_addr_const (file, XVECEXP (x, 0, 0));
5368 fprintf (file, "@GOTNTPOFF");
5369 return true;
5370 case UNSPEC_INDNTPOFF:
5371 output_addr_const (file, XVECEXP (x, 0, 0));
5372 fprintf (file, "@INDNTPOFF");
5373 return true;
5374 }
5375
5376 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 2)
5377 switch (XINT (x, 1))
5378 {
5379 case UNSPEC_POOL_OFFSET:
5380 x = gen_rtx_MINUS (GET_MODE (x), XVECEXP (x, 0, 0), XVECEXP (x, 0, 1));
5381 output_addr_const (file, x);
5382 return true;
5383 }
5384 return false;
5385 }
5386
5387 /* Output address operand ADDR in assembler syntax to
5388 stdio stream FILE. */
5389
5390 void
5391 print_operand_address (FILE *file, rtx addr)
5392 {
5393 struct s390_address ad;
5394
5395 if (s390_loadrelative_operand_p (addr, NULL, NULL))
5396 {
5397 if (!TARGET_Z10)
5398 {
5399 output_operand_lossage ("symbolic memory references are "
5400 "only supported on z10 or later");
5401 return;
5402 }
5403 output_addr_const (file, addr);
5404 return;
5405 }
5406
5407 if (!s390_decompose_address (addr, &ad)
5408 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5409 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
5410 output_operand_lossage ("cannot decompose address");
5411
5412 if (ad.disp)
5413 output_addr_const (file, ad.disp);
5414 else
5415 fprintf (file, "0");
5416
5417 if (ad.base && ad.indx)
5418 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
5419 reg_names[REGNO (ad.base)]);
5420 else if (ad.base)
5421 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5422 }
5423
5424 /* Output operand X in assembler syntax to stdio stream FILE.
5425 CODE specified the format flag. The following format flags
5426 are recognized:
5427
5428 'C': print opcode suffix for branch condition.
5429 'D': print opcode suffix for inverse branch condition.
5430 'E': print opcode suffix for branch on index instruction.
5431 'G': print the size of the operand in bytes.
5432 'J': print tls_load/tls_gdcall/tls_ldcall suffix
5433 'M': print the second word of a TImode operand.
5434 'N': print the second word of a DImode operand.
5435 'O': print only the displacement of a memory reference.
5436 'R': print only the base register of a memory reference.
5437 'S': print S-type memory reference (base+displacement).
5438 'Y': print shift count operand.
5439
5440 'b': print integer X as if it's an unsigned byte.
5441 'c': print integer X as if it's an signed byte.
5442 'e': "end" of DImode contiguous bitmask X.
5443 'f': "end" of SImode contiguous bitmask X.
5444 'h': print integer X as if it's a signed halfword.
5445 'i': print the first nonzero HImode part of X.
5446 'j': print the first HImode part unequal to -1 of X.
5447 'k': print the first nonzero SImode part of X.
5448 'm': print the first SImode part unequal to -1 of X.
5449 'o': print integer X as if it's an unsigned 32bit word.
5450 's': "start" of DImode contiguous bitmask X.
5451 't': "start" of SImode contiguous bitmask X.
5452 'x': print integer X as if it's an unsigned halfword.
5453 */
5454
5455 void
5456 print_operand (FILE *file, rtx x, int code)
5457 {
5458 HOST_WIDE_INT ival;
5459
5460 switch (code)
5461 {
5462 case 'C':
5463 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
5464 return;
5465
5466 case 'D':
5467 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
5468 return;
5469
5470 case 'E':
5471 if (GET_CODE (x) == LE)
5472 fprintf (file, "l");
5473 else if (GET_CODE (x) == GT)
5474 fprintf (file, "h");
5475 else
5476 output_operand_lossage ("invalid comparison operator "
5477 "for 'E' output modifier");
5478 return;
5479
5480 case 'J':
5481 if (GET_CODE (x) == SYMBOL_REF)
5482 {
5483 fprintf (file, "%s", ":tls_load:");
5484 output_addr_const (file, x);
5485 }
5486 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
5487 {
5488 fprintf (file, "%s", ":tls_gdcall:");
5489 output_addr_const (file, XVECEXP (x, 0, 0));
5490 }
5491 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
5492 {
5493 fprintf (file, "%s", ":tls_ldcall:");
5494 const char *name = get_some_local_dynamic_name ();
5495 gcc_assert (name);
5496 assemble_name (file, name);
5497 }
5498 else
5499 output_operand_lossage ("invalid reference for 'J' output modifier");
5500 return;
5501
5502 case 'G':
5503 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
5504 return;
5505
5506 case 'O':
5507 {
5508 struct s390_address ad;
5509 int ret;
5510
5511 if (!MEM_P (x))
5512 {
5513 output_operand_lossage ("memory reference expected for "
5514 "'O' output modifier");
5515 return;
5516 }
5517
5518 ret = s390_decompose_address (XEXP (x, 0), &ad);
5519
5520 if (!ret
5521 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5522 || ad.indx)
5523 {
5524 output_operand_lossage ("invalid address for 'O' output modifier");
5525 return;
5526 }
5527
5528 if (ad.disp)
5529 output_addr_const (file, ad.disp);
5530 else
5531 fprintf (file, "0");
5532 }
5533 return;
5534
5535 case 'R':
5536 {
5537 struct s390_address ad;
5538 int ret;
5539
5540 if (!MEM_P (x))
5541 {
5542 output_operand_lossage ("memory reference expected for "
5543 "'R' output modifier");
5544 return;
5545 }
5546
5547 ret = s390_decompose_address (XEXP (x, 0), &ad);
5548
5549 if (!ret
5550 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5551 || ad.indx)
5552 {
5553 output_operand_lossage ("invalid address for 'R' output modifier");
5554 return;
5555 }
5556
5557 if (ad.base)
5558 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
5559 else
5560 fprintf (file, "0");
5561 }
5562 return;
5563
5564 case 'S':
5565 {
5566 struct s390_address ad;
5567 int ret;
5568
5569 if (!MEM_P (x))
5570 {
5571 output_operand_lossage ("memory reference expected for "
5572 "'S' output modifier");
5573 return;
5574 }
5575 ret = s390_decompose_address (XEXP (x, 0), &ad);
5576
5577 if (!ret
5578 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5579 || ad.indx)
5580 {
5581 output_operand_lossage ("invalid address for 'S' output modifier");
5582 return;
5583 }
5584
5585 if (ad.disp)
5586 output_addr_const (file, ad.disp);
5587 else
5588 fprintf (file, "0");
5589
5590 if (ad.base)
5591 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5592 }
5593 return;
5594
5595 case 'N':
5596 if (GET_CODE (x) == REG)
5597 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5598 else if (GET_CODE (x) == MEM)
5599 x = change_address (x, VOIDmode,
5600 plus_constant (Pmode, XEXP (x, 0), 4));
5601 else
5602 output_operand_lossage ("register or memory expression expected "
5603 "for 'N' output modifier");
5604 break;
5605
5606 case 'M':
5607 if (GET_CODE (x) == REG)
5608 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5609 else if (GET_CODE (x) == MEM)
5610 x = change_address (x, VOIDmode,
5611 plus_constant (Pmode, XEXP (x, 0), 8));
5612 else
5613 output_operand_lossage ("register or memory expression expected "
5614 "for 'M' output modifier");
5615 break;
5616
5617 case 'Y':
5618 print_shift_count_operand (file, x);
5619 return;
5620 }
5621
5622 switch (GET_CODE (x))
5623 {
5624 case REG:
5625 fprintf (file, "%s", reg_names[REGNO (x)]);
5626 break;
5627
5628 case MEM:
5629 output_address (XEXP (x, 0));
5630 break;
5631
5632 case CONST:
5633 case CODE_LABEL:
5634 case LABEL_REF:
5635 case SYMBOL_REF:
5636 output_addr_const (file, x);
5637 break;
5638
5639 case CONST_INT:
5640 ival = INTVAL (x);
5641 switch (code)
5642 {
5643 case 0:
5644 break;
5645 case 'b':
5646 ival &= 0xff;
5647 break;
5648 case 'c':
5649 ival = ((ival & 0xff) ^ 0x80) - 0x80;
5650 break;
5651 case 'x':
5652 ival &= 0xffff;
5653 break;
5654 case 'h':
5655 ival = ((ival & 0xffff) ^ 0x8000) - 0x8000;
5656 break;
5657 case 'i':
5658 ival = s390_extract_part (x, HImode, 0);
5659 break;
5660 case 'j':
5661 ival = s390_extract_part (x, HImode, -1);
5662 break;
5663 case 'k':
5664 ival = s390_extract_part (x, SImode, 0);
5665 break;
5666 case 'm':
5667 ival = s390_extract_part (x, SImode, -1);
5668 break;
5669 case 'o':
5670 ival &= 0xffffffff;
5671 break;
5672 case 'e': case 'f':
5673 case 's': case 't':
5674 {
5675 int pos, len;
5676 bool ok;
5677
5678 len = (code == 's' || code == 'e' ? 64 : 32);
5679 ok = s390_contiguous_bitmask_p (ival, len, &pos, &len);
5680 gcc_assert (ok);
5681 if (code == 's' || code == 't')
5682 ival = 64 - pos - len;
5683 else
5684 ival = 64 - 1 - pos;
5685 }
5686 break;
5687 default:
5688 output_operand_lossage ("invalid constant for output modifier '%c'", code);
5689 }
5690 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
5691 break;
5692
5693 case CONST_DOUBLE:
5694 gcc_assert (GET_MODE (x) == VOIDmode);
5695 if (code == 'b')
5696 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
5697 else if (code == 'x')
5698 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
5699 else if (code == 'h')
5700 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5701 ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
5702 else
5703 {
5704 if (code == 0)
5705 output_operand_lossage ("invalid constant - try using "
5706 "an output modifier");
5707 else
5708 output_operand_lossage ("invalid constant for output modifier '%c'",
5709 code);
5710 }
5711 break;
5712
5713 default:
5714 if (code == 0)
5715 output_operand_lossage ("invalid expression - try using "
5716 "an output modifier");
5717 else
5718 output_operand_lossage ("invalid expression for output "
5719 "modifier '%c'", code);
5720 break;
5721 }
5722 }
5723
5724 /* Target hook for assembling integer objects. We need to define it
5725 here to work a round a bug in some versions of GAS, which couldn't
5726 handle values smaller than INT_MIN when printed in decimal. */
5727
5728 static bool
5729 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
5730 {
5731 if (size == 8 && aligned_p
5732 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
5733 {
5734 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
5735 INTVAL (x));
5736 return true;
5737 }
5738 return default_assemble_integer (x, size, aligned_p);
5739 }
5740
5741 /* Returns true if register REGNO is used for forming
5742 a memory address in expression X. */
5743
5744 static bool
5745 reg_used_in_mem_p (int regno, rtx x)
5746 {
5747 enum rtx_code code = GET_CODE (x);
5748 int i, j;
5749 const char *fmt;
5750
5751 if (code == MEM)
5752 {
5753 if (refers_to_regno_p (regno, XEXP (x, 0)))
5754 return true;
5755 }
5756 else if (code == SET
5757 && GET_CODE (SET_DEST (x)) == PC)
5758 {
5759 if (refers_to_regno_p (regno, SET_SRC (x)))
5760 return true;
5761 }
5762
5763 fmt = GET_RTX_FORMAT (code);
5764 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5765 {
5766 if (fmt[i] == 'e'
5767 && reg_used_in_mem_p (regno, XEXP (x, i)))
5768 return true;
5769
5770 else if (fmt[i] == 'E')
5771 for (j = 0; j < XVECLEN (x, i); j++)
5772 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
5773 return true;
5774 }
5775 return false;
5776 }
5777
5778 /* Returns true if expression DEP_RTX sets an address register
5779 used by instruction INSN to address memory. */
5780
5781 static bool
5782 addr_generation_dependency_p (rtx dep_rtx, rtx_insn *insn)
5783 {
5784 rtx target, pat;
5785
5786 if (NONJUMP_INSN_P (dep_rtx))
5787 dep_rtx = PATTERN (dep_rtx);
5788
5789 if (GET_CODE (dep_rtx) == SET)
5790 {
5791 target = SET_DEST (dep_rtx);
5792 if (GET_CODE (target) == STRICT_LOW_PART)
5793 target = XEXP (target, 0);
5794 while (GET_CODE (target) == SUBREG)
5795 target = SUBREG_REG (target);
5796
5797 if (GET_CODE (target) == REG)
5798 {
5799 int regno = REGNO (target);
5800
5801 if (s390_safe_attr_type (insn) == TYPE_LA)
5802 {
5803 pat = PATTERN (insn);
5804 if (GET_CODE (pat) == PARALLEL)
5805 {
5806 gcc_assert (XVECLEN (pat, 0) == 2);
5807 pat = XVECEXP (pat, 0, 0);
5808 }
5809 gcc_assert (GET_CODE (pat) == SET);
5810 return refers_to_regno_p (regno, SET_SRC (pat));
5811 }
5812 else if (get_attr_atype (insn) == ATYPE_AGEN)
5813 return reg_used_in_mem_p (regno, PATTERN (insn));
5814 }
5815 }
5816 return false;
5817 }
5818
5819 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5820
5821 int
5822 s390_agen_dep_p (rtx_insn *dep_insn, rtx_insn *insn)
5823 {
5824 rtx dep_rtx = PATTERN (dep_insn);
5825 int i;
5826
5827 if (GET_CODE (dep_rtx) == SET
5828 && addr_generation_dependency_p (dep_rtx, insn))
5829 return 1;
5830 else if (GET_CODE (dep_rtx) == PARALLEL)
5831 {
5832 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
5833 {
5834 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
5835 return 1;
5836 }
5837 }
5838 return 0;
5839 }
5840
5841
5842 /* A C statement (sans semicolon) to update the integer scheduling priority
5843 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5844 reduce the priority to execute INSN later. Do not define this macro if
5845 you do not need to adjust the scheduling priorities of insns.
5846
5847 A STD instruction should be scheduled earlier,
5848 in order to use the bypass. */
5849 static int
5850 s390_adjust_priority (rtx_insn *insn, int priority)
5851 {
5852 if (! INSN_P (insn))
5853 return priority;
5854
5855 if (s390_tune != PROCESSOR_2084_Z990
5856 && s390_tune != PROCESSOR_2094_Z9_109
5857 && s390_tune != PROCESSOR_2097_Z10
5858 && s390_tune != PROCESSOR_2817_Z196
5859 && s390_tune != PROCESSOR_2827_ZEC12)
5860 return priority;
5861
5862 switch (s390_safe_attr_type (insn))
5863 {
5864 case TYPE_FSTOREDF:
5865 case TYPE_FSTORESF:
5866 priority = priority << 3;
5867 break;
5868 case TYPE_STORE:
5869 case TYPE_STM:
5870 priority = priority << 1;
5871 break;
5872 default:
5873 break;
5874 }
5875 return priority;
5876 }
5877
5878
5879 /* The number of instructions that can be issued per cycle. */
5880
5881 static int
5882 s390_issue_rate (void)
5883 {
5884 switch (s390_tune)
5885 {
5886 case PROCESSOR_2084_Z990:
5887 case PROCESSOR_2094_Z9_109:
5888 case PROCESSOR_2817_Z196:
5889 return 3;
5890 case PROCESSOR_2097_Z10:
5891 case PROCESSOR_2827_ZEC12:
5892 return 2;
5893 default:
5894 return 1;
5895 }
5896 }
5897
5898 static int
5899 s390_first_cycle_multipass_dfa_lookahead (void)
5900 {
5901 return 4;
5902 }
5903
5904 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5905 Fix up MEMs as required. */
5906
5907 static void
5908 annotate_constant_pool_refs (rtx *x)
5909 {
5910 int i, j;
5911 const char *fmt;
5912
5913 gcc_assert (GET_CODE (*x) != SYMBOL_REF
5914 || !CONSTANT_POOL_ADDRESS_P (*x));
5915
5916 /* Literal pool references can only occur inside a MEM ... */
5917 if (GET_CODE (*x) == MEM)
5918 {
5919 rtx memref = XEXP (*x, 0);
5920
5921 if (GET_CODE (memref) == SYMBOL_REF
5922 && CONSTANT_POOL_ADDRESS_P (memref))
5923 {
5924 rtx base = cfun->machine->base_reg;
5925 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
5926 UNSPEC_LTREF);
5927
5928 *x = replace_equiv_address (*x, addr);
5929 return;
5930 }
5931
5932 if (GET_CODE (memref) == CONST
5933 && GET_CODE (XEXP (memref, 0)) == PLUS
5934 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
5935 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
5936 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
5937 {
5938 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
5939 rtx sym = XEXP (XEXP (memref, 0), 0);
5940 rtx base = cfun->machine->base_reg;
5941 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5942 UNSPEC_LTREF);
5943
5944 *x = replace_equiv_address (*x, plus_constant (Pmode, addr, off));
5945 return;
5946 }
5947 }
5948
5949 /* ... or a load-address type pattern. */
5950 if (GET_CODE (*x) == SET)
5951 {
5952 rtx addrref = SET_SRC (*x);
5953
5954 if (GET_CODE (addrref) == SYMBOL_REF
5955 && CONSTANT_POOL_ADDRESS_P (addrref))
5956 {
5957 rtx base = cfun->machine->base_reg;
5958 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
5959 UNSPEC_LTREF);
5960
5961 SET_SRC (*x) = addr;
5962 return;
5963 }
5964
5965 if (GET_CODE (addrref) == CONST
5966 && GET_CODE (XEXP (addrref, 0)) == PLUS
5967 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
5968 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
5969 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
5970 {
5971 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
5972 rtx sym = XEXP (XEXP (addrref, 0), 0);
5973 rtx base = cfun->machine->base_reg;
5974 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5975 UNSPEC_LTREF);
5976
5977 SET_SRC (*x) = plus_constant (Pmode, addr, off);
5978 return;
5979 }
5980 }
5981
5982 /* Annotate LTREL_BASE as well. */
5983 if (GET_CODE (*x) == UNSPEC
5984 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5985 {
5986 rtx base = cfun->machine->base_reg;
5987 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
5988 UNSPEC_LTREL_BASE);
5989 return;
5990 }
5991
5992 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5993 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5994 {
5995 if (fmt[i] == 'e')
5996 {
5997 annotate_constant_pool_refs (&XEXP (*x, i));
5998 }
5999 else if (fmt[i] == 'E')
6000 {
6001 for (j = 0; j < XVECLEN (*x, i); j++)
6002 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
6003 }
6004 }
6005 }
6006
6007 /* Split all branches that exceed the maximum distance.
6008 Returns true if this created a new literal pool entry. */
6009
6010 static int
6011 s390_split_branches (void)
6012 {
6013 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
6014 int new_literal = 0, ret;
6015 rtx_insn *insn;
6016 rtx pat, target;
6017 rtx *label;
6018
6019 /* We need correct insn addresses. */
6020
6021 shorten_branches (get_insns ());
6022
6023 /* Find all branches that exceed 64KB, and split them. */
6024
6025 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6026 {
6027 if (! JUMP_P (insn) || tablejump_p (insn, NULL, NULL))
6028 continue;
6029
6030 pat = PATTERN (insn);
6031 if (GET_CODE (pat) == PARALLEL)
6032 pat = XVECEXP (pat, 0, 0);
6033 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
6034 continue;
6035
6036 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
6037 {
6038 label = &SET_SRC (pat);
6039 }
6040 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
6041 {
6042 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
6043 label = &XEXP (SET_SRC (pat), 1);
6044 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
6045 label = &XEXP (SET_SRC (pat), 2);
6046 else
6047 continue;
6048 }
6049 else
6050 continue;
6051
6052 if (get_attr_length (insn) <= 4)
6053 continue;
6054
6055 /* We are going to use the return register as scratch register,
6056 make sure it will be saved/restored by the prologue/epilogue. */
6057 cfun_frame_layout.save_return_addr_p = 1;
6058
6059 if (!flag_pic)
6060 {
6061 new_literal = 1;
6062 rtx mem = force_const_mem (Pmode, *label);
6063 rtx_insn *set_insn = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, mem), insn);
6064 INSN_ADDRESSES_NEW (set_insn, -1);
6065 annotate_constant_pool_refs (&PATTERN (set_insn));
6066
6067 target = temp_reg;
6068 }
6069 else
6070 {
6071 new_literal = 1;
6072 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
6073 UNSPEC_LTREL_OFFSET);
6074 target = gen_rtx_CONST (Pmode, target);
6075 target = force_const_mem (Pmode, target);
6076 rtx_insn *set_insn = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
6077 INSN_ADDRESSES_NEW (set_insn, -1);
6078 annotate_constant_pool_refs (&PATTERN (set_insn));
6079
6080 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
6081 cfun->machine->base_reg),
6082 UNSPEC_LTREL_BASE);
6083 target = gen_rtx_PLUS (Pmode, temp_reg, target);
6084 }
6085
6086 ret = validate_change (insn, label, target, 0);
6087 gcc_assert (ret);
6088 }
6089
6090 return new_literal;
6091 }
6092
6093
6094 /* Find an annotated literal pool symbol referenced in RTX X,
6095 and store it at REF. Will abort if X contains references to
6096 more than one such pool symbol; multiple references to the same
6097 symbol are allowed, however.
6098
6099 The rtx pointed to by REF must be initialized to NULL_RTX
6100 by the caller before calling this routine. */
6101
6102 static void
6103 find_constant_pool_ref (rtx x, rtx *ref)
6104 {
6105 int i, j;
6106 const char *fmt;
6107
6108 /* Ignore LTREL_BASE references. */
6109 if (GET_CODE (x) == UNSPEC
6110 && XINT (x, 1) == UNSPEC_LTREL_BASE)
6111 return;
6112 /* Likewise POOL_ENTRY insns. */
6113 if (GET_CODE (x) == UNSPEC_VOLATILE
6114 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
6115 return;
6116
6117 gcc_assert (GET_CODE (x) != SYMBOL_REF
6118 || !CONSTANT_POOL_ADDRESS_P (x));
6119
6120 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
6121 {
6122 rtx sym = XVECEXP (x, 0, 0);
6123 gcc_assert (GET_CODE (sym) == SYMBOL_REF
6124 && CONSTANT_POOL_ADDRESS_P (sym));
6125
6126 if (*ref == NULL_RTX)
6127 *ref = sym;
6128 else
6129 gcc_assert (*ref == sym);
6130
6131 return;
6132 }
6133
6134 fmt = GET_RTX_FORMAT (GET_CODE (x));
6135 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6136 {
6137 if (fmt[i] == 'e')
6138 {
6139 find_constant_pool_ref (XEXP (x, i), ref);
6140 }
6141 else if (fmt[i] == 'E')
6142 {
6143 for (j = 0; j < XVECLEN (x, i); j++)
6144 find_constant_pool_ref (XVECEXP (x, i, j), ref);
6145 }
6146 }
6147 }
6148
6149 /* Replace every reference to the annotated literal pool
6150 symbol REF in X by its base plus OFFSET. */
6151
6152 static void
6153 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
6154 {
6155 int i, j;
6156 const char *fmt;
6157
6158 gcc_assert (*x != ref);
6159
6160 if (GET_CODE (*x) == UNSPEC
6161 && XINT (*x, 1) == UNSPEC_LTREF
6162 && XVECEXP (*x, 0, 0) == ref)
6163 {
6164 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
6165 return;
6166 }
6167
6168 if (GET_CODE (*x) == PLUS
6169 && GET_CODE (XEXP (*x, 1)) == CONST_INT
6170 && GET_CODE (XEXP (*x, 0)) == UNSPEC
6171 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
6172 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
6173 {
6174 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
6175 *x = plus_constant (Pmode, addr, INTVAL (XEXP (*x, 1)));
6176 return;
6177 }
6178
6179 fmt = GET_RTX_FORMAT (GET_CODE (*x));
6180 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
6181 {
6182 if (fmt[i] == 'e')
6183 {
6184 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
6185 }
6186 else if (fmt[i] == 'E')
6187 {
6188 for (j = 0; j < XVECLEN (*x, i); j++)
6189 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
6190 }
6191 }
6192 }
6193
6194 /* Check whether X contains an UNSPEC_LTREL_BASE.
6195 Return its constant pool symbol if found, NULL_RTX otherwise. */
6196
6197 static rtx
6198 find_ltrel_base (rtx x)
6199 {
6200 int i, j;
6201 const char *fmt;
6202
6203 if (GET_CODE (x) == UNSPEC
6204 && XINT (x, 1) == UNSPEC_LTREL_BASE)
6205 return XVECEXP (x, 0, 0);
6206
6207 fmt = GET_RTX_FORMAT (GET_CODE (x));
6208 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6209 {
6210 if (fmt[i] == 'e')
6211 {
6212 rtx fnd = find_ltrel_base (XEXP (x, i));
6213 if (fnd)
6214 return fnd;
6215 }
6216 else if (fmt[i] == 'E')
6217 {
6218 for (j = 0; j < XVECLEN (x, i); j++)
6219 {
6220 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
6221 if (fnd)
6222 return fnd;
6223 }
6224 }
6225 }
6226
6227 return NULL_RTX;
6228 }
6229
6230 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
6231
6232 static void
6233 replace_ltrel_base (rtx *x)
6234 {
6235 int i, j;
6236 const char *fmt;
6237
6238 if (GET_CODE (*x) == UNSPEC
6239 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
6240 {
6241 *x = XVECEXP (*x, 0, 1);
6242 return;
6243 }
6244
6245 fmt = GET_RTX_FORMAT (GET_CODE (*x));
6246 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
6247 {
6248 if (fmt[i] == 'e')
6249 {
6250 replace_ltrel_base (&XEXP (*x, i));
6251 }
6252 else if (fmt[i] == 'E')
6253 {
6254 for (j = 0; j < XVECLEN (*x, i); j++)
6255 replace_ltrel_base (&XVECEXP (*x, i, j));
6256 }
6257 }
6258 }
6259
6260
6261 /* We keep a list of constants which we have to add to internal
6262 constant tables in the middle of large functions. */
6263
6264 #define NR_C_MODES 11
6265 machine_mode constant_modes[NR_C_MODES] =
6266 {
6267 TFmode, TImode, TDmode,
6268 DFmode, DImode, DDmode,
6269 SFmode, SImode, SDmode,
6270 HImode,
6271 QImode
6272 };
6273
6274 struct constant
6275 {
6276 struct constant *next;
6277 rtx value;
6278 rtx_code_label *label;
6279 };
6280
6281 struct constant_pool
6282 {
6283 struct constant_pool *next;
6284 rtx_insn *first_insn;
6285 rtx_insn *pool_insn;
6286 bitmap insns;
6287 rtx_insn *emit_pool_after;
6288
6289 struct constant *constants[NR_C_MODES];
6290 struct constant *execute;
6291 rtx_code_label *label;
6292 int size;
6293 };
6294
6295 /* Allocate new constant_pool structure. */
6296
6297 static struct constant_pool *
6298 s390_alloc_pool (void)
6299 {
6300 struct constant_pool *pool;
6301 int i;
6302
6303 pool = (struct constant_pool *) xmalloc (sizeof *pool);
6304 pool->next = NULL;
6305 for (i = 0; i < NR_C_MODES; i++)
6306 pool->constants[i] = NULL;
6307
6308 pool->execute = NULL;
6309 pool->label = gen_label_rtx ();
6310 pool->first_insn = NULL;
6311 pool->pool_insn = NULL;
6312 pool->insns = BITMAP_ALLOC (NULL);
6313 pool->size = 0;
6314 pool->emit_pool_after = NULL;
6315
6316 return pool;
6317 }
6318
6319 /* Create new constant pool covering instructions starting at INSN
6320 and chain it to the end of POOL_LIST. */
6321
6322 static struct constant_pool *
6323 s390_start_pool (struct constant_pool **pool_list, rtx_insn *insn)
6324 {
6325 struct constant_pool *pool, **prev;
6326
6327 pool = s390_alloc_pool ();
6328 pool->first_insn = insn;
6329
6330 for (prev = pool_list; *prev; prev = &(*prev)->next)
6331 ;
6332 *prev = pool;
6333
6334 return pool;
6335 }
6336
6337 /* End range of instructions covered by POOL at INSN and emit
6338 placeholder insn representing the pool. */
6339
6340 static void
6341 s390_end_pool (struct constant_pool *pool, rtx_insn *insn)
6342 {
6343 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
6344
6345 if (!insn)
6346 insn = get_last_insn ();
6347
6348 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
6349 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6350 }
6351
6352 /* Add INSN to the list of insns covered by POOL. */
6353
6354 static void
6355 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
6356 {
6357 bitmap_set_bit (pool->insns, INSN_UID (insn));
6358 }
6359
6360 /* Return pool out of POOL_LIST that covers INSN. */
6361
6362 static struct constant_pool *
6363 s390_find_pool (struct constant_pool *pool_list, rtx insn)
6364 {
6365 struct constant_pool *pool;
6366
6367 for (pool = pool_list; pool; pool = pool->next)
6368 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
6369 break;
6370
6371 return pool;
6372 }
6373
6374 /* Add constant VAL of mode MODE to the constant pool POOL. */
6375
6376 static void
6377 s390_add_constant (struct constant_pool *pool, rtx val, machine_mode mode)
6378 {
6379 struct constant *c;
6380 int i;
6381
6382 for (i = 0; i < NR_C_MODES; i++)
6383 if (constant_modes[i] == mode)
6384 break;
6385 gcc_assert (i != NR_C_MODES);
6386
6387 for (c = pool->constants[i]; c != NULL; c = c->next)
6388 if (rtx_equal_p (val, c->value))
6389 break;
6390
6391 if (c == NULL)
6392 {
6393 c = (struct constant *) xmalloc (sizeof *c);
6394 c->value = val;
6395 c->label = gen_label_rtx ();
6396 c->next = pool->constants[i];
6397 pool->constants[i] = c;
6398 pool->size += GET_MODE_SIZE (mode);
6399 }
6400 }
6401
6402 /* Return an rtx that represents the offset of X from the start of
6403 pool POOL. */
6404
6405 static rtx
6406 s390_pool_offset (struct constant_pool *pool, rtx x)
6407 {
6408 rtx label;
6409
6410 label = gen_rtx_LABEL_REF (GET_MODE (x), pool->label);
6411 x = gen_rtx_UNSPEC (GET_MODE (x), gen_rtvec (2, x, label),
6412 UNSPEC_POOL_OFFSET);
6413 return gen_rtx_CONST (GET_MODE (x), x);
6414 }
6415
6416 /* Find constant VAL of mode MODE in the constant pool POOL.
6417 Return an RTX describing the distance from the start of
6418 the pool to the location of the new constant. */
6419
6420 static rtx
6421 s390_find_constant (struct constant_pool *pool, rtx val,
6422 machine_mode mode)
6423 {
6424 struct constant *c;
6425 int i;
6426
6427 for (i = 0; i < NR_C_MODES; i++)
6428 if (constant_modes[i] == mode)
6429 break;
6430 gcc_assert (i != NR_C_MODES);
6431
6432 for (c = pool->constants[i]; c != NULL; c = c->next)
6433 if (rtx_equal_p (val, c->value))
6434 break;
6435
6436 gcc_assert (c);
6437
6438 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6439 }
6440
6441 /* Check whether INSN is an execute. Return the label_ref to its
6442 execute target template if so, NULL_RTX otherwise. */
6443
6444 static rtx
6445 s390_execute_label (rtx insn)
6446 {
6447 if (NONJUMP_INSN_P (insn)
6448 && GET_CODE (PATTERN (insn)) == PARALLEL
6449 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
6450 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
6451 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
6452
6453 return NULL_RTX;
6454 }
6455
6456 /* Add execute target for INSN to the constant pool POOL. */
6457
6458 static void
6459 s390_add_execute (struct constant_pool *pool, rtx insn)
6460 {
6461 struct constant *c;
6462
6463 for (c = pool->execute; c != NULL; c = c->next)
6464 if (INSN_UID (insn) == INSN_UID (c->value))
6465 break;
6466
6467 if (c == NULL)
6468 {
6469 c = (struct constant *) xmalloc (sizeof *c);
6470 c->value = insn;
6471 c->label = gen_label_rtx ();
6472 c->next = pool->execute;
6473 pool->execute = c;
6474 pool->size += 6;
6475 }
6476 }
6477
6478 /* Find execute target for INSN in the constant pool POOL.
6479 Return an RTX describing the distance from the start of
6480 the pool to the location of the execute target. */
6481
6482 static rtx
6483 s390_find_execute (struct constant_pool *pool, rtx insn)
6484 {
6485 struct constant *c;
6486
6487 for (c = pool->execute; c != NULL; c = c->next)
6488 if (INSN_UID (insn) == INSN_UID (c->value))
6489 break;
6490
6491 gcc_assert (c);
6492
6493 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6494 }
6495
6496 /* For an execute INSN, extract the execute target template. */
6497
6498 static rtx
6499 s390_execute_target (rtx insn)
6500 {
6501 rtx pattern = PATTERN (insn);
6502 gcc_assert (s390_execute_label (insn));
6503
6504 if (XVECLEN (pattern, 0) == 2)
6505 {
6506 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
6507 }
6508 else
6509 {
6510 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
6511 int i;
6512
6513 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
6514 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
6515
6516 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
6517 }
6518
6519 return pattern;
6520 }
6521
6522 /* Indicate that INSN cannot be duplicated. This is the case for
6523 execute insns that carry a unique label. */
6524
6525 static bool
6526 s390_cannot_copy_insn_p (rtx_insn *insn)
6527 {
6528 rtx label = s390_execute_label (insn);
6529 return label && label != const0_rtx;
6530 }
6531
6532 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
6533 do not emit the pool base label. */
6534
6535 static void
6536 s390_dump_pool (struct constant_pool *pool, bool remote_label)
6537 {
6538 struct constant *c;
6539 rtx_insn *insn = pool->pool_insn;
6540 int i;
6541
6542 /* Switch to rodata section. */
6543 if (TARGET_CPU_ZARCH)
6544 {
6545 insn = emit_insn_after (gen_pool_section_start (), insn);
6546 INSN_ADDRESSES_NEW (insn, -1);
6547 }
6548
6549 /* Ensure minimum pool alignment. */
6550 if (TARGET_CPU_ZARCH)
6551 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
6552 else
6553 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
6554 INSN_ADDRESSES_NEW (insn, -1);
6555
6556 /* Emit pool base label. */
6557 if (!remote_label)
6558 {
6559 insn = emit_label_after (pool->label, insn);
6560 INSN_ADDRESSES_NEW (insn, -1);
6561 }
6562
6563 /* Dump constants in descending alignment requirement order,
6564 ensuring proper alignment for every constant. */
6565 for (i = 0; i < NR_C_MODES; i++)
6566 for (c = pool->constants[i]; c; c = c->next)
6567 {
6568 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6569 rtx value = copy_rtx (c->value);
6570 if (GET_CODE (value) == CONST
6571 && GET_CODE (XEXP (value, 0)) == UNSPEC
6572 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
6573 && XVECLEN (XEXP (value, 0), 0) == 1)
6574 value = s390_pool_offset (pool, XVECEXP (XEXP (value, 0), 0, 0));
6575
6576 insn = emit_label_after (c->label, insn);
6577 INSN_ADDRESSES_NEW (insn, -1);
6578
6579 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
6580 gen_rtvec (1, value),
6581 UNSPECV_POOL_ENTRY);
6582 insn = emit_insn_after (value, insn);
6583 INSN_ADDRESSES_NEW (insn, -1);
6584 }
6585
6586 /* Ensure minimum alignment for instructions. */
6587 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
6588 INSN_ADDRESSES_NEW (insn, -1);
6589
6590 /* Output in-pool execute template insns. */
6591 for (c = pool->execute; c; c = c->next)
6592 {
6593 insn = emit_label_after (c->label, insn);
6594 INSN_ADDRESSES_NEW (insn, -1);
6595
6596 insn = emit_insn_after (s390_execute_target (c->value), insn);
6597 INSN_ADDRESSES_NEW (insn, -1);
6598 }
6599
6600 /* Switch back to previous section. */
6601 if (TARGET_CPU_ZARCH)
6602 {
6603 insn = emit_insn_after (gen_pool_section_end (), insn);
6604 INSN_ADDRESSES_NEW (insn, -1);
6605 }
6606
6607 insn = emit_barrier_after (insn);
6608 INSN_ADDRESSES_NEW (insn, -1);
6609
6610 /* Remove placeholder insn. */
6611 remove_insn (pool->pool_insn);
6612 }
6613
6614 /* Free all memory used by POOL. */
6615
6616 static void
6617 s390_free_pool (struct constant_pool *pool)
6618 {
6619 struct constant *c, *next;
6620 int i;
6621
6622 for (i = 0; i < NR_C_MODES; i++)
6623 for (c = pool->constants[i]; c; c = next)
6624 {
6625 next = c->next;
6626 free (c);
6627 }
6628
6629 for (c = pool->execute; c; c = next)
6630 {
6631 next = c->next;
6632 free (c);
6633 }
6634
6635 BITMAP_FREE (pool->insns);
6636 free (pool);
6637 }
6638
6639
6640 /* Collect main literal pool. Return NULL on overflow. */
6641
6642 static struct constant_pool *
6643 s390_mainpool_start (void)
6644 {
6645 struct constant_pool *pool;
6646 rtx_insn *insn;
6647
6648 pool = s390_alloc_pool ();
6649
6650 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6651 {
6652 if (NONJUMP_INSN_P (insn)
6653 && GET_CODE (PATTERN (insn)) == SET
6654 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
6655 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
6656 {
6657 /* There might be two main_pool instructions if base_reg
6658 is call-clobbered; one for shrink-wrapped code and one
6659 for the rest. We want to keep the first. */
6660 if (pool->pool_insn)
6661 {
6662 insn = PREV_INSN (insn);
6663 delete_insn (NEXT_INSN (insn));
6664 continue;
6665 }
6666 pool->pool_insn = insn;
6667 }
6668
6669 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6670 {
6671 s390_add_execute (pool, insn);
6672 }
6673 else if (NONJUMP_INSN_P (insn) || CALL_P (insn))
6674 {
6675 rtx pool_ref = NULL_RTX;
6676 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6677 if (pool_ref)
6678 {
6679 rtx constant = get_pool_constant (pool_ref);
6680 machine_mode mode = get_pool_mode (pool_ref);
6681 s390_add_constant (pool, constant, mode);
6682 }
6683 }
6684
6685 /* If hot/cold partitioning is enabled we have to make sure that
6686 the literal pool is emitted in the same section where the
6687 initialization of the literal pool base pointer takes place.
6688 emit_pool_after is only used in the non-overflow case on non
6689 Z cpus where we can emit the literal pool at the end of the
6690 function body within the text section. */
6691 if (NOTE_P (insn)
6692 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6693 && !pool->emit_pool_after)
6694 pool->emit_pool_after = PREV_INSN (insn);
6695 }
6696
6697 gcc_assert (pool->pool_insn || pool->size == 0);
6698
6699 if (pool->size >= 4096)
6700 {
6701 /* We're going to chunkify the pool, so remove the main
6702 pool placeholder insn. */
6703 remove_insn (pool->pool_insn);
6704
6705 s390_free_pool (pool);
6706 pool = NULL;
6707 }
6708
6709 /* If the functions ends with the section where the literal pool
6710 should be emitted set the marker to its end. */
6711 if (pool && !pool->emit_pool_after)
6712 pool->emit_pool_after = get_last_insn ();
6713
6714 return pool;
6715 }
6716
6717 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6718 Modify the current function to output the pool constants as well as
6719 the pool register setup instruction. */
6720
6721 static void
6722 s390_mainpool_finish (struct constant_pool *pool)
6723 {
6724 rtx base_reg = cfun->machine->base_reg;
6725
6726 /* If the pool is empty, we're done. */
6727 if (pool->size == 0)
6728 {
6729 /* We don't actually need a base register after all. */
6730 cfun->machine->base_reg = NULL_RTX;
6731
6732 if (pool->pool_insn)
6733 remove_insn (pool->pool_insn);
6734 s390_free_pool (pool);
6735 return;
6736 }
6737
6738 /* We need correct insn addresses. */
6739 shorten_branches (get_insns ());
6740
6741 /* On zSeries, we use a LARL to load the pool register. The pool is
6742 located in the .rodata section, so we emit it after the function. */
6743 if (TARGET_CPU_ZARCH)
6744 {
6745 rtx set = gen_main_base_64 (base_reg, pool->label);
6746 rtx_insn *insn = emit_insn_after (set, pool->pool_insn);
6747 INSN_ADDRESSES_NEW (insn, -1);
6748 remove_insn (pool->pool_insn);
6749
6750 insn = get_last_insn ();
6751 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6752 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6753
6754 s390_dump_pool (pool, 0);
6755 }
6756
6757 /* On S/390, if the total size of the function's code plus literal pool
6758 does not exceed 4096 bytes, we use BASR to set up a function base
6759 pointer, and emit the literal pool at the end of the function. */
6760 else if (INSN_ADDRESSES (INSN_UID (pool->emit_pool_after))
6761 + pool->size + 8 /* alignment slop */ < 4096)
6762 {
6763 rtx set = gen_main_base_31_small (base_reg, pool->label);
6764 rtx_insn *insn = emit_insn_after (set, pool->pool_insn);
6765 INSN_ADDRESSES_NEW (insn, -1);
6766 remove_insn (pool->pool_insn);
6767
6768 insn = emit_label_after (pool->label, insn);
6769 INSN_ADDRESSES_NEW (insn, -1);
6770
6771 /* emit_pool_after will be set by s390_mainpool_start to the
6772 last insn of the section where the literal pool should be
6773 emitted. */
6774 insn = pool->emit_pool_after;
6775
6776 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6777 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6778
6779 s390_dump_pool (pool, 1);
6780 }
6781
6782 /* Otherwise, we emit an inline literal pool and use BASR to branch
6783 over it, setting up the pool register at the same time. */
6784 else
6785 {
6786 rtx_code_label *pool_end = gen_label_rtx ();
6787
6788 rtx pat = gen_main_base_31_large (base_reg, pool->label, pool_end);
6789 rtx_insn *insn = emit_jump_insn_after (pat, pool->pool_insn);
6790 JUMP_LABEL (insn) = pool_end;
6791 INSN_ADDRESSES_NEW (insn, -1);
6792 remove_insn (pool->pool_insn);
6793
6794 insn = emit_label_after (pool->label, insn);
6795 INSN_ADDRESSES_NEW (insn, -1);
6796
6797 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6798 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6799
6800 insn = emit_label_after (pool_end, pool->pool_insn);
6801 INSN_ADDRESSES_NEW (insn, -1);
6802
6803 s390_dump_pool (pool, 1);
6804 }
6805
6806
6807 /* Replace all literal pool references. */
6808
6809 for (rtx_insn *insn = get_insns (); insn; insn = NEXT_INSN (insn))
6810 {
6811 if (INSN_P (insn))
6812 replace_ltrel_base (&PATTERN (insn));
6813
6814 if (NONJUMP_INSN_P (insn) || CALL_P (insn))
6815 {
6816 rtx addr, pool_ref = NULL_RTX;
6817 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6818 if (pool_ref)
6819 {
6820 if (s390_execute_label (insn))
6821 addr = s390_find_execute (pool, insn);
6822 else
6823 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
6824 get_pool_mode (pool_ref));
6825
6826 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6827 INSN_CODE (insn) = -1;
6828 }
6829 }
6830 }
6831
6832
6833 /* Free the pool. */
6834 s390_free_pool (pool);
6835 }
6836
6837 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6838 We have decided we cannot use this pool, so revert all changes
6839 to the current function that were done by s390_mainpool_start. */
6840 static void
6841 s390_mainpool_cancel (struct constant_pool *pool)
6842 {
6843 /* We didn't actually change the instruction stream, so simply
6844 free the pool memory. */
6845 s390_free_pool (pool);
6846 }
6847
6848
6849 /* Chunkify the literal pool. */
6850
6851 #define S390_POOL_CHUNK_MIN 0xc00
6852 #define S390_POOL_CHUNK_MAX 0xe00
6853
6854 static struct constant_pool *
6855 s390_chunkify_start (void)
6856 {
6857 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
6858 int extra_size = 0;
6859 bitmap far_labels;
6860 rtx pending_ltrel = NULL_RTX;
6861 rtx_insn *insn;
6862
6863 rtx (*gen_reload_base) (rtx, rtx) =
6864 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
6865
6866
6867 /* We need correct insn addresses. */
6868
6869 shorten_branches (get_insns ());
6870
6871 /* Scan all insns and move literals to pool chunks. */
6872
6873 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6874 {
6875 bool section_switch_p = false;
6876
6877 /* Check for pending LTREL_BASE. */
6878 if (INSN_P (insn))
6879 {
6880 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
6881 if (ltrel_base)
6882 {
6883 gcc_assert (ltrel_base == pending_ltrel);
6884 pending_ltrel = NULL_RTX;
6885 }
6886 }
6887
6888 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6889 {
6890 if (!curr_pool)
6891 curr_pool = s390_start_pool (&pool_list, insn);
6892
6893 s390_add_execute (curr_pool, insn);
6894 s390_add_pool_insn (curr_pool, insn);
6895 }
6896 else if (NONJUMP_INSN_P (insn) || CALL_P (insn))
6897 {
6898 rtx pool_ref = NULL_RTX;
6899 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6900 if (pool_ref)
6901 {
6902 rtx constant = get_pool_constant (pool_ref);
6903 machine_mode mode = get_pool_mode (pool_ref);
6904
6905 if (!curr_pool)
6906 curr_pool = s390_start_pool (&pool_list, insn);
6907
6908 s390_add_constant (curr_pool, constant, mode);
6909 s390_add_pool_insn (curr_pool, insn);
6910
6911 /* Don't split the pool chunk between a LTREL_OFFSET load
6912 and the corresponding LTREL_BASE. */
6913 if (GET_CODE (constant) == CONST
6914 && GET_CODE (XEXP (constant, 0)) == UNSPEC
6915 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
6916 {
6917 gcc_assert (!pending_ltrel);
6918 pending_ltrel = pool_ref;
6919 }
6920 }
6921 }
6922
6923 if (JUMP_P (insn) || JUMP_TABLE_DATA_P (insn) || LABEL_P (insn))
6924 {
6925 if (curr_pool)
6926 s390_add_pool_insn (curr_pool, insn);
6927 /* An LTREL_BASE must follow within the same basic block. */
6928 gcc_assert (!pending_ltrel);
6929 }
6930
6931 if (NOTE_P (insn))
6932 switch (NOTE_KIND (insn))
6933 {
6934 case NOTE_INSN_SWITCH_TEXT_SECTIONS:
6935 section_switch_p = true;
6936 break;
6937 case NOTE_INSN_VAR_LOCATION:
6938 case NOTE_INSN_CALL_ARG_LOCATION:
6939 continue;
6940 default:
6941 break;
6942 }
6943
6944 if (!curr_pool
6945 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
6946 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
6947 continue;
6948
6949 if (TARGET_CPU_ZARCH)
6950 {
6951 if (curr_pool->size < S390_POOL_CHUNK_MAX)
6952 continue;
6953
6954 s390_end_pool (curr_pool, NULL);
6955 curr_pool = NULL;
6956 }
6957 else
6958 {
6959 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
6960 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
6961 + extra_size;
6962
6963 /* We will later have to insert base register reload insns.
6964 Those will have an effect on code size, which we need to
6965 consider here. This calculation makes rather pessimistic
6966 worst-case assumptions. */
6967 if (LABEL_P (insn))
6968 extra_size += 6;
6969
6970 if (chunk_size < S390_POOL_CHUNK_MIN
6971 && curr_pool->size < S390_POOL_CHUNK_MIN
6972 && !section_switch_p)
6973 continue;
6974
6975 /* Pool chunks can only be inserted after BARRIERs ... */
6976 if (BARRIER_P (insn))
6977 {
6978 s390_end_pool (curr_pool, insn);
6979 curr_pool = NULL;
6980 extra_size = 0;
6981 }
6982
6983 /* ... so if we don't find one in time, create one. */
6984 else if (chunk_size > S390_POOL_CHUNK_MAX
6985 || curr_pool->size > S390_POOL_CHUNK_MAX
6986 || section_switch_p)
6987 {
6988 rtx_insn *label, *jump, *barrier, *next, *prev;
6989
6990 if (!section_switch_p)
6991 {
6992 /* We can insert the barrier only after a 'real' insn. */
6993 if (! NONJUMP_INSN_P (insn) && ! CALL_P (insn))
6994 continue;
6995 if (get_attr_length (insn) == 0)
6996 continue;
6997 /* Don't separate LTREL_BASE from the corresponding
6998 LTREL_OFFSET load. */
6999 if (pending_ltrel)
7000 continue;
7001 next = insn;
7002 do
7003 {
7004 insn = next;
7005 next = NEXT_INSN (insn);
7006 }
7007 while (next
7008 && NOTE_P (next)
7009 && (NOTE_KIND (next) == NOTE_INSN_VAR_LOCATION
7010 || NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION));
7011 }
7012 else
7013 {
7014 gcc_assert (!pending_ltrel);
7015
7016 /* The old pool has to end before the section switch
7017 note in order to make it part of the current
7018 section. */
7019 insn = PREV_INSN (insn);
7020 }
7021
7022 label = gen_label_rtx ();
7023 prev = insn;
7024 if (prev && NOTE_P (prev))
7025 prev = prev_nonnote_insn (prev);
7026 if (prev)
7027 jump = emit_jump_insn_after_setloc (gen_jump (label), insn,
7028 INSN_LOCATION (prev));
7029 else
7030 jump = emit_jump_insn_after_noloc (gen_jump (label), insn);
7031 barrier = emit_barrier_after (jump);
7032 insn = emit_label_after (label, barrier);
7033 JUMP_LABEL (jump) = label;
7034 LABEL_NUSES (label) = 1;
7035
7036 INSN_ADDRESSES_NEW (jump, -1);
7037 INSN_ADDRESSES_NEW (barrier, -1);
7038 INSN_ADDRESSES_NEW (insn, -1);
7039
7040 s390_end_pool (curr_pool, barrier);
7041 curr_pool = NULL;
7042 extra_size = 0;
7043 }
7044 }
7045 }
7046
7047 if (curr_pool)
7048 s390_end_pool (curr_pool, NULL);
7049 gcc_assert (!pending_ltrel);
7050
7051 /* Find all labels that are branched into
7052 from an insn belonging to a different chunk. */
7053
7054 far_labels = BITMAP_ALLOC (NULL);
7055
7056 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7057 {
7058 rtx_jump_table_data *table;
7059
7060 /* Labels marked with LABEL_PRESERVE_P can be target
7061 of non-local jumps, so we have to mark them.
7062 The same holds for named labels.
7063
7064 Don't do that, however, if it is the label before
7065 a jump table. */
7066
7067 if (LABEL_P (insn)
7068 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
7069 {
7070 rtx_insn *vec_insn = NEXT_INSN (insn);
7071 if (! vec_insn || ! JUMP_TABLE_DATA_P (vec_insn))
7072 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
7073 }
7074 /* Check potential targets in a table jump (casesi_jump). */
7075 else if (tablejump_p (insn, NULL, &table))
7076 {
7077 rtx vec_pat = PATTERN (table);
7078 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
7079
7080 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
7081 {
7082 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
7083
7084 if (s390_find_pool (pool_list, label)
7085 != s390_find_pool (pool_list, insn))
7086 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
7087 }
7088 }
7089 /* If we have a direct jump (conditional or unconditional),
7090 check all potential targets. */
7091 else if (JUMP_P (insn))
7092 {
7093 rtx pat = PATTERN (insn);
7094
7095 if (GET_CODE (pat) == PARALLEL)
7096 pat = XVECEXP (pat, 0, 0);
7097
7098 if (GET_CODE (pat) == SET)
7099 {
7100 rtx label = JUMP_LABEL (insn);
7101 if (label && !ANY_RETURN_P (label))
7102 {
7103 if (s390_find_pool (pool_list, label)
7104 != s390_find_pool (pool_list, insn))
7105 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
7106 }
7107 }
7108 }
7109 }
7110
7111 /* Insert base register reload insns before every pool. */
7112
7113 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
7114 {
7115 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
7116 curr_pool->label);
7117 rtx_insn *insn = curr_pool->first_insn;
7118 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
7119 }
7120
7121 /* Insert base register reload insns at every far label. */
7122
7123 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7124 if (LABEL_P (insn)
7125 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
7126 {
7127 struct constant_pool *pool = s390_find_pool (pool_list, insn);
7128 if (pool)
7129 {
7130 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
7131 pool->label);
7132 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
7133 }
7134 }
7135
7136
7137 BITMAP_FREE (far_labels);
7138
7139
7140 /* Recompute insn addresses. */
7141
7142 init_insn_lengths ();
7143 shorten_branches (get_insns ());
7144
7145 return pool_list;
7146 }
7147
7148 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
7149 After we have decided to use this list, finish implementing
7150 all changes to the current function as required. */
7151
7152 static void
7153 s390_chunkify_finish (struct constant_pool *pool_list)
7154 {
7155 struct constant_pool *curr_pool = NULL;
7156 rtx_insn *insn;
7157
7158
7159 /* Replace all literal pool references. */
7160
7161 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7162 {
7163 if (INSN_P (insn))
7164 replace_ltrel_base (&PATTERN (insn));
7165
7166 curr_pool = s390_find_pool (pool_list, insn);
7167 if (!curr_pool)
7168 continue;
7169
7170 if (NONJUMP_INSN_P (insn) || CALL_P (insn))
7171 {
7172 rtx addr, pool_ref = NULL_RTX;
7173 find_constant_pool_ref (PATTERN (insn), &pool_ref);
7174 if (pool_ref)
7175 {
7176 if (s390_execute_label (insn))
7177 addr = s390_find_execute (curr_pool, insn);
7178 else
7179 addr = s390_find_constant (curr_pool,
7180 get_pool_constant (pool_ref),
7181 get_pool_mode (pool_ref));
7182
7183 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
7184 INSN_CODE (insn) = -1;
7185 }
7186 }
7187 }
7188
7189 /* Dump out all literal pools. */
7190
7191 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
7192 s390_dump_pool (curr_pool, 0);
7193
7194 /* Free pool list. */
7195
7196 while (pool_list)
7197 {
7198 struct constant_pool *next = pool_list->next;
7199 s390_free_pool (pool_list);
7200 pool_list = next;
7201 }
7202 }
7203
7204 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
7205 We have decided we cannot use this list, so revert all changes
7206 to the current function that were done by s390_chunkify_start. */
7207
7208 static void
7209 s390_chunkify_cancel (struct constant_pool *pool_list)
7210 {
7211 struct constant_pool *curr_pool = NULL;
7212 rtx_insn *insn;
7213
7214 /* Remove all pool placeholder insns. */
7215
7216 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
7217 {
7218 /* Did we insert an extra barrier? Remove it. */
7219 rtx_insn *barrier = PREV_INSN (curr_pool->pool_insn);
7220 rtx_insn *jump = barrier? PREV_INSN (barrier) : NULL;
7221 rtx_insn *label = NEXT_INSN (curr_pool->pool_insn);
7222
7223 if (jump && JUMP_P (jump)
7224 && barrier && BARRIER_P (barrier)
7225 && label && LABEL_P (label)
7226 && GET_CODE (PATTERN (jump)) == SET
7227 && SET_DEST (PATTERN (jump)) == pc_rtx
7228 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
7229 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
7230 {
7231 remove_insn (jump);
7232 remove_insn (barrier);
7233 remove_insn (label);
7234 }
7235
7236 remove_insn (curr_pool->pool_insn);
7237 }
7238
7239 /* Remove all base register reload insns. */
7240
7241 for (insn = get_insns (); insn; )
7242 {
7243 rtx_insn *next_insn = NEXT_INSN (insn);
7244
7245 if (NONJUMP_INSN_P (insn)
7246 && GET_CODE (PATTERN (insn)) == SET
7247 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
7248 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
7249 remove_insn (insn);
7250
7251 insn = next_insn;
7252 }
7253
7254 /* Free pool list. */
7255
7256 while (pool_list)
7257 {
7258 struct constant_pool *next = pool_list->next;
7259 s390_free_pool (pool_list);
7260 pool_list = next;
7261 }
7262 }
7263
7264 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
7265
7266 void
7267 s390_output_pool_entry (rtx exp, machine_mode mode, unsigned int align)
7268 {
7269 REAL_VALUE_TYPE r;
7270
7271 switch (GET_MODE_CLASS (mode))
7272 {
7273 case MODE_FLOAT:
7274 case MODE_DECIMAL_FLOAT:
7275 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
7276
7277 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
7278 assemble_real (r, mode, align);
7279 break;
7280
7281 case MODE_INT:
7282 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
7283 mark_symbol_refs_as_used (exp);
7284 break;
7285
7286 default:
7287 gcc_unreachable ();
7288 }
7289 }
7290
7291
7292 /* Return an RTL expression representing the value of the return address
7293 for the frame COUNT steps up from the current frame. FRAME is the
7294 frame pointer of that frame. */
7295
7296 rtx
7297 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
7298 {
7299 int offset;
7300 rtx addr;
7301
7302 /* Without backchain, we fail for all but the current frame. */
7303
7304 if (!TARGET_BACKCHAIN && count > 0)
7305 return NULL_RTX;
7306
7307 /* For the current frame, we need to make sure the initial
7308 value of RETURN_REGNUM is actually saved. */
7309
7310 if (count == 0)
7311 {
7312 /* On non-z architectures branch splitting could overwrite r14. */
7313 if (TARGET_CPU_ZARCH)
7314 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
7315 else
7316 {
7317 cfun_frame_layout.save_return_addr_p = true;
7318 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
7319 }
7320 }
7321
7322 if (TARGET_PACKED_STACK)
7323 offset = -2 * UNITS_PER_LONG;
7324 else
7325 offset = RETURN_REGNUM * UNITS_PER_LONG;
7326
7327 addr = plus_constant (Pmode, frame, offset);
7328 addr = memory_address (Pmode, addr);
7329 return gen_rtx_MEM (Pmode, addr);
7330 }
7331
7332 /* Return an RTL expression representing the back chain stored in
7333 the current stack frame. */
7334
7335 rtx
7336 s390_back_chain_rtx (void)
7337 {
7338 rtx chain;
7339
7340 gcc_assert (TARGET_BACKCHAIN);
7341
7342 if (TARGET_PACKED_STACK)
7343 chain = plus_constant (Pmode, stack_pointer_rtx,
7344 STACK_POINTER_OFFSET - UNITS_PER_LONG);
7345 else
7346 chain = stack_pointer_rtx;
7347
7348 chain = gen_rtx_MEM (Pmode, chain);
7349 return chain;
7350 }
7351
7352 /* Find first call clobbered register unused in a function.
7353 This could be used as base register in a leaf function
7354 or for holding the return address before epilogue. */
7355
7356 static int
7357 find_unused_clobbered_reg (void)
7358 {
7359 int i;
7360 for (i = 0; i < 6; i++)
7361 if (!df_regs_ever_live_p (i))
7362 return i;
7363 return 0;
7364 }
7365
7366
7367 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
7368 clobbered hard regs in SETREG. */
7369
7370 static void
7371 s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *data)
7372 {
7373 char *regs_ever_clobbered = (char *)data;
7374 unsigned int i, regno;
7375 machine_mode mode = GET_MODE (setreg);
7376
7377 if (GET_CODE (setreg) == SUBREG)
7378 {
7379 rtx inner = SUBREG_REG (setreg);
7380 if (!GENERAL_REG_P (inner) && !FP_REG_P (inner))
7381 return;
7382 regno = subreg_regno (setreg);
7383 }
7384 else if (GENERAL_REG_P (setreg) || FP_REG_P (setreg))
7385 regno = REGNO (setreg);
7386 else
7387 return;
7388
7389 for (i = regno;
7390 i < regno + HARD_REGNO_NREGS (regno, mode);
7391 i++)
7392 regs_ever_clobbered[i] = 1;
7393 }
7394
7395 /* Walks through all basic blocks of the current function looking
7396 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
7397 of the passed integer array REGS_EVER_CLOBBERED are set to one for
7398 each of those regs. */
7399
7400 static void
7401 s390_regs_ever_clobbered (char regs_ever_clobbered[])
7402 {
7403 basic_block cur_bb;
7404 rtx_insn *cur_insn;
7405 unsigned int i;
7406
7407 memset (regs_ever_clobbered, 0, 32);
7408
7409 /* For non-leaf functions we have to consider all call clobbered regs to be
7410 clobbered. */
7411 if (!crtl->is_leaf)
7412 {
7413 for (i = 0; i < 32; i++)
7414 regs_ever_clobbered[i] = call_really_used_regs[i];
7415 }
7416
7417 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
7418 this work is done by liveness analysis (mark_regs_live_at_end).
7419 Special care is needed for functions containing landing pads. Landing pads
7420 may use the eh registers, but the code which sets these registers is not
7421 contained in that function. Hence s390_regs_ever_clobbered is not able to
7422 deal with this automatically. */
7423 if (crtl->calls_eh_return || cfun->machine->has_landing_pad_p)
7424 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
7425 if (crtl->calls_eh_return
7426 || (cfun->machine->has_landing_pad_p
7427 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i))))
7428 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
7429
7430 /* For nonlocal gotos all call-saved registers have to be saved.
7431 This flag is also set for the unwinding code in libgcc.
7432 See expand_builtin_unwind_init. For regs_ever_live this is done by
7433 reload. */
7434 if (crtl->saves_all_registers)
7435 for (i = 0; i < 32; i++)
7436 if (!call_really_used_regs[i])
7437 regs_ever_clobbered[i] = 1;
7438
7439 FOR_EACH_BB_FN (cur_bb, cfun)
7440 {
7441 FOR_BB_INSNS (cur_bb, cur_insn)
7442 {
7443 rtx pat;
7444
7445 if (!INSN_P (cur_insn))
7446 continue;
7447
7448 pat = PATTERN (cur_insn);
7449
7450 /* Ignore GPR restore insns. */
7451 if (epilogue_completed && RTX_FRAME_RELATED_P (cur_insn))
7452 {
7453 if (GET_CODE (pat) == SET
7454 && GENERAL_REG_P (SET_DEST (pat)))
7455 {
7456 /* lgdr */
7457 if (GET_MODE (SET_SRC (pat)) == DImode
7458 && FP_REG_P (SET_SRC (pat)))
7459 continue;
7460
7461 /* l / lg */
7462 if (GET_CODE (SET_SRC (pat)) == MEM)
7463 continue;
7464 }
7465
7466 /* lm / lmg */
7467 if (GET_CODE (pat) == PARALLEL
7468 && load_multiple_operation (pat, VOIDmode))
7469 continue;
7470 }
7471
7472 note_stores (pat,
7473 s390_reg_clobbered_rtx,
7474 regs_ever_clobbered);
7475 }
7476 }
7477 }
7478
7479 /* Determine the frame area which actually has to be accessed
7480 in the function epilogue. The values are stored at the
7481 given pointers AREA_BOTTOM (address of the lowest used stack
7482 address) and AREA_TOP (address of the first item which does
7483 not belong to the stack frame). */
7484
7485 static void
7486 s390_frame_area (int *area_bottom, int *area_top)
7487 {
7488 int b, t;
7489
7490 b = INT_MAX;
7491 t = INT_MIN;
7492
7493 if (cfun_frame_layout.first_restore_gpr != -1)
7494 {
7495 b = (cfun_frame_layout.gprs_offset
7496 + cfun_frame_layout.first_restore_gpr * UNITS_PER_LONG);
7497 t = b + (cfun_frame_layout.last_restore_gpr
7498 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_LONG;
7499 }
7500
7501 if (TARGET_64BIT && cfun_save_high_fprs_p)
7502 {
7503 b = MIN (b, cfun_frame_layout.f8_offset);
7504 t = MAX (t, (cfun_frame_layout.f8_offset
7505 + cfun_frame_layout.high_fprs * 8));
7506 }
7507
7508 if (!TARGET_64BIT)
7509 {
7510 if (cfun_fpr_save_p (FPR4_REGNUM))
7511 {
7512 b = MIN (b, cfun_frame_layout.f4_offset);
7513 t = MAX (t, cfun_frame_layout.f4_offset + 8);
7514 }
7515 if (cfun_fpr_save_p (FPR6_REGNUM))
7516 {
7517 b = MIN (b, cfun_frame_layout.f4_offset + 8);
7518 t = MAX (t, cfun_frame_layout.f4_offset + 16);
7519 }
7520 }
7521 *area_bottom = b;
7522 *area_top = t;
7523 }
7524 /* Update gpr_save_slots in the frame layout trying to make use of
7525 FPRs as GPR save slots.
7526 This is a helper routine of s390_register_info. */
7527
7528 static void
7529 s390_register_info_gprtofpr ()
7530 {
7531 int save_reg_slot = FPR0_REGNUM;
7532 int i, j;
7533
7534 if (!TARGET_Z10 || !TARGET_HARD_FLOAT || !crtl->is_leaf)
7535 return;
7536
7537 for (i = 15; i >= 6; i--)
7538 {
7539 if (cfun_gpr_save_slot (i) == 0)
7540 continue;
7541
7542 /* Advance to the next FP register which can be used as a
7543 GPR save slot. */
7544 while ((!call_really_used_regs[save_reg_slot]
7545 || df_regs_ever_live_p (save_reg_slot)
7546 || cfun_fpr_save_p (save_reg_slot))
7547 && FP_REGNO_P (save_reg_slot))
7548 save_reg_slot++;
7549 if (!FP_REGNO_P (save_reg_slot))
7550 {
7551 /* We only want to use ldgr/lgdr if we can get rid of
7552 stm/lm entirely. So undo the gpr slot allocation in
7553 case we ran out of FPR save slots. */
7554 for (j = 6; j <= 15; j++)
7555 if (FP_REGNO_P (cfun_gpr_save_slot (j)))
7556 cfun_gpr_save_slot (j) = -1;
7557 break;
7558 }
7559 cfun_gpr_save_slot (i) = save_reg_slot++;
7560 }
7561 }
7562
7563 /* Set the bits in fpr_bitmap for FPRs which need to be saved due to
7564 stdarg.
7565 This is a helper routine for s390_register_info. */
7566
7567 static void
7568 s390_register_info_stdarg_fpr ()
7569 {
7570 int i;
7571 int min_fpr;
7572 int max_fpr;
7573
7574 /* Save the FP argument regs for stdarg. f0, f2 for 31 bit and
7575 f0-f4 for 64 bit. */
7576 if (!cfun->stdarg
7577 || !TARGET_HARD_FLOAT
7578 || !cfun->va_list_fpr_size
7579 || crtl->args.info.fprs >= FP_ARG_NUM_REG)
7580 return;
7581
7582 min_fpr = crtl->args.info.fprs;
7583 max_fpr = min_fpr + cfun->va_list_fpr_size;
7584 if (max_fpr > FP_ARG_NUM_REG)
7585 max_fpr = FP_ARG_NUM_REG;
7586
7587 for (i = min_fpr; i < max_fpr; i++)
7588 cfun_set_fpr_save (i + FPR0_REGNUM);
7589 }
7590
7591 /* Reserve the GPR save slots for GPRs which need to be saved due to
7592 stdarg.
7593 This is a helper routine for s390_register_info. */
7594
7595 static void
7596 s390_register_info_stdarg_gpr ()
7597 {
7598 int i;
7599 int min_gpr;
7600 int max_gpr;
7601
7602 if (!cfun->stdarg
7603 || !cfun->va_list_gpr_size
7604 || crtl->args.info.gprs >= GP_ARG_NUM_REG)
7605 return;
7606
7607 min_gpr = crtl->args.info.gprs;
7608 max_gpr = min_gpr + cfun->va_list_gpr_size;
7609 if (max_gpr > GP_ARG_NUM_REG)
7610 max_gpr = GP_ARG_NUM_REG;
7611
7612 for (i = min_gpr; i < max_gpr; i++)
7613 cfun_gpr_save_slot (2 + i) = -1;
7614 }
7615
7616 /* The GPR and FPR save slots in cfun->machine->frame_layout are set
7617 for registers which need to be saved in function prologue.
7618 This function can be used until the insns emitted for save/restore
7619 of the regs are visible in the RTL stream. */
7620
7621 static void
7622 s390_register_info ()
7623 {
7624 int i, j;
7625 char clobbered_regs[32];
7626
7627 gcc_assert (!epilogue_completed);
7628
7629 if (reload_completed)
7630 /* After reload we rely on our own routine to determine which
7631 registers need saving. */
7632 s390_regs_ever_clobbered (clobbered_regs);
7633 else
7634 /* During reload we use regs_ever_live as a base since reload
7635 does changes in there which we otherwise would not be aware
7636 of. */
7637 for (i = 0; i < 32; i++)
7638 clobbered_regs[i] = df_regs_ever_live_p (i);
7639
7640 for (i = 0; i < 32; i++)
7641 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i];
7642
7643 /* Mark the call-saved FPRs which need to be saved.
7644 This needs to be done before checking the special GPRs since the
7645 stack pointer usage depends on whether high FPRs have to be saved
7646 or not. */
7647 cfun_frame_layout.fpr_bitmap = 0;
7648 cfun_frame_layout.high_fprs = 0;
7649 for (i = FPR0_REGNUM; i <= FPR15_REGNUM; i++)
7650 if (clobbered_regs[i] && !call_really_used_regs[i])
7651 {
7652 cfun_set_fpr_save (i);
7653 if (i >= FPR8_REGNUM)
7654 cfun_frame_layout.high_fprs++;
7655 }
7656
7657 if (flag_pic)
7658 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
7659 |= !!df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
7660
7661 clobbered_regs[BASE_REGNUM]
7662 |= (cfun->machine->base_reg
7663 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
7664
7665 clobbered_regs[HARD_FRAME_POINTER_REGNUM]
7666 |= !!frame_pointer_needed;
7667
7668 /* On pre z900 machines this might take until machine dependent
7669 reorg to decide.
7670 save_return_addr_p will only be set on non-zarch machines so
7671 there is no risk that r14 goes into an FPR instead of a stack
7672 slot. */
7673 clobbered_regs[RETURN_REGNUM]
7674 |= (!crtl->is_leaf
7675 || TARGET_TPF_PROFILING
7676 || cfun->machine->split_branches_pending_p
7677 || cfun_frame_layout.save_return_addr_p
7678 || crtl->calls_eh_return);
7679
7680 clobbered_regs[STACK_POINTER_REGNUM]
7681 |= (!crtl->is_leaf
7682 || TARGET_TPF_PROFILING
7683 || cfun_save_high_fprs_p
7684 || get_frame_size () > 0
7685 || (reload_completed && cfun_frame_layout.frame_size > 0)
7686 || cfun->calls_alloca);
7687
7688 memset (cfun_frame_layout.gpr_save_slots, 0, 16);
7689
7690 for (i = 6; i < 16; i++)
7691 if (clobbered_regs[i])
7692 cfun_gpr_save_slot (i) = -1;
7693
7694 s390_register_info_stdarg_fpr ();
7695 s390_register_info_gprtofpr ();
7696
7697 /* First find the range of GPRs to be restored. Vararg regs don't
7698 need to be restored so we do it before assigning slots to the
7699 vararg GPRs. */
7700 for (i = 0; i < 16 && cfun_gpr_save_slot (i) != -1; i++);
7701 for (j = 15; j > i && cfun_gpr_save_slot (j) != -1; j--);
7702 cfun_frame_layout.first_restore_gpr = (i == 16) ? -1 : i;
7703 cfun_frame_layout.last_restore_gpr = (i == 16) ? -1 : j;
7704
7705 /* stdarg functions might need to save GPRs 2 to 6. This might
7706 override the GPR->FPR save decision made above for r6 since
7707 vararg regs must go to the stack. */
7708 s390_register_info_stdarg_gpr ();
7709
7710 /* Now the range of GPRs which need saving. */
7711 for (i = 0; i < 16 && cfun_gpr_save_slot (i) != -1; i++);
7712 for (j = 15; j > i && cfun_gpr_save_slot (j) != -1; j--);
7713 cfun_frame_layout.first_save_gpr = (i == 16) ? -1 : i;
7714 cfun_frame_layout.last_save_gpr = (i == 16) ? -1 : j;
7715 }
7716
7717 /* This function is called by s390_optimize_prologue in order to get
7718 rid of unnecessary GPR save/restore instructions. The register info
7719 for the GPRs is re-computed and the ranges are re-calculated. */
7720
7721 static void
7722 s390_optimize_register_info ()
7723 {
7724 char clobbered_regs[32];
7725 int i, j;
7726
7727 gcc_assert (epilogue_completed);
7728 gcc_assert (!cfun->machine->split_branches_pending_p);
7729
7730 s390_regs_ever_clobbered (clobbered_regs);
7731
7732 for (i = 0; i < 32; i++)
7733 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i];
7734
7735 /* There is still special treatment needed for cases invisible to
7736 s390_regs_ever_clobbered. */
7737 clobbered_regs[RETURN_REGNUM]
7738 |= (TARGET_TPF_PROFILING
7739 /* When expanding builtin_return_addr in ESA mode we do not
7740 know whether r14 will later be needed as scratch reg when
7741 doing branch splitting. So the builtin always accesses the
7742 r14 save slot and we need to stick to the save/restore
7743 decision for r14 even if it turns out that it didn't get
7744 clobbered. */
7745 || cfun_frame_layout.save_return_addr_p
7746 || crtl->calls_eh_return);
7747
7748 memset (cfun_frame_layout.gpr_save_slots, 0, 6);
7749
7750 for (i = 6; i < 16; i++)
7751 if (!clobbered_regs[i])
7752 cfun_gpr_save_slot (i) = 0;
7753
7754 for (i = 0; i < 16 && cfun_gpr_save_slot (i) != -1; i++);
7755 for (j = 15; j > i && cfun_gpr_save_slot (j) != -1; j--);
7756 cfun_frame_layout.first_restore_gpr = (i == 16) ? -1 : i;
7757 cfun_frame_layout.last_restore_gpr = (i == 16) ? -1 : j;
7758
7759 s390_register_info_stdarg_gpr ();
7760
7761 for (i = 0; i < 16 && cfun_gpr_save_slot (i) != -1; i++);
7762 for (j = 15; j > i && cfun_gpr_save_slot (j) != -1; j--);
7763 cfun_frame_layout.first_save_gpr = (i == 16) ? -1 : i;
7764 cfun_frame_layout.last_save_gpr = (i == 16) ? -1 : j;
7765 }
7766
7767 /* Fill cfun->machine with info about frame of current function. */
7768
7769 static void
7770 s390_frame_info (void)
7771 {
7772 HOST_WIDE_INT lowest_offset;
7773
7774 cfun_frame_layout.first_save_gpr_slot = cfun_frame_layout.first_save_gpr;
7775 cfun_frame_layout.last_save_gpr_slot = cfun_frame_layout.last_save_gpr;
7776
7777 /* The va_arg builtin uses a constant distance of 16 *
7778 UNITS_PER_LONG (r0-r15) to reach the FPRs from the reg_save_area
7779 pointer. So even if we are going to save the stack pointer in an
7780 FPR we need the stack space in order to keep the offsets
7781 correct. */
7782 if (cfun->stdarg && cfun_save_arg_fprs_p)
7783 {
7784 cfun_frame_layout.last_save_gpr_slot = STACK_POINTER_REGNUM;
7785
7786 if (cfun_frame_layout.first_save_gpr_slot == -1)
7787 cfun_frame_layout.first_save_gpr_slot = STACK_POINTER_REGNUM;
7788 }
7789
7790 cfun_frame_layout.frame_size = get_frame_size ();
7791 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
7792 fatal_error ("total size of local variables exceeds architecture limit");
7793
7794 if (!TARGET_PACKED_STACK)
7795 {
7796 /* Fixed stack layout. */
7797 cfun_frame_layout.backchain_offset = 0;
7798 cfun_frame_layout.f0_offset = 16 * UNITS_PER_LONG;
7799 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
7800 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
7801 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
7802 * UNITS_PER_LONG);
7803 }
7804 else if (TARGET_BACKCHAIN)
7805 {
7806 /* Kernel stack layout - packed stack, backchain, no float */
7807 gcc_assert (TARGET_SOFT_FLOAT);
7808 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
7809 - UNITS_PER_LONG);
7810
7811 /* The distance between the backchain and the return address
7812 save slot must not change. So we always need a slot for the
7813 stack pointer which resides in between. */
7814 cfun_frame_layout.last_save_gpr_slot = STACK_POINTER_REGNUM;
7815
7816 cfun_frame_layout.gprs_offset
7817 = cfun_frame_layout.backchain_offset - cfun_gprs_save_area_size;
7818
7819 /* FPRs will not be saved. Nevertheless pick sane values to
7820 keep area calculations valid. */
7821 cfun_frame_layout.f0_offset =
7822 cfun_frame_layout.f4_offset =
7823 cfun_frame_layout.f8_offset = cfun_frame_layout.gprs_offset;
7824 }
7825 else
7826 {
7827 int num_fprs;
7828
7829 /* Packed stack layout without backchain. */
7830
7831 /* With stdarg FPRs need their dedicated slots. */
7832 num_fprs = (TARGET_64BIT && cfun->stdarg ? 2
7833 : (cfun_fpr_save_p (FPR4_REGNUM) +
7834 cfun_fpr_save_p (FPR6_REGNUM)));
7835 cfun_frame_layout.f4_offset = STACK_POINTER_OFFSET - 8 * num_fprs;
7836
7837 num_fprs = (cfun->stdarg ? 2
7838 : (cfun_fpr_save_p (FPR0_REGNUM)
7839 + cfun_fpr_save_p (FPR2_REGNUM)));
7840 cfun_frame_layout.f0_offset = cfun_frame_layout.f4_offset - 8 * num_fprs;
7841
7842 cfun_frame_layout.gprs_offset
7843 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
7844
7845 cfun_frame_layout.f8_offset = (cfun_frame_layout.gprs_offset
7846 - cfun_frame_layout.high_fprs * 8);
7847 }
7848
7849 if (cfun_save_high_fprs_p)
7850 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
7851
7852 if (!crtl->is_leaf)
7853 cfun_frame_layout.frame_size += crtl->outgoing_args_size;
7854
7855 /* In the following cases we have to allocate a STACK_POINTER_OFFSET
7856 sized area at the bottom of the stack. This is required also for
7857 leaf functions. When GCC generates a local stack reference it
7858 will always add STACK_POINTER_OFFSET to all these references. */
7859 if (crtl->is_leaf
7860 && !TARGET_TPF_PROFILING
7861 && cfun_frame_layout.frame_size == 0
7862 && !cfun->calls_alloca)
7863 return;
7864
7865 /* Calculate the number of bytes we have used in our own register
7866 save area. With the packed stack layout we can re-use the
7867 remaining bytes for normal stack elements. */
7868
7869 if (TARGET_PACKED_STACK)
7870 lowest_offset = MIN (MIN (cfun_frame_layout.f0_offset,
7871 cfun_frame_layout.f4_offset),
7872 cfun_frame_layout.gprs_offset);
7873 else
7874 lowest_offset = 0;
7875
7876 if (TARGET_BACKCHAIN)
7877 lowest_offset = MIN (lowest_offset, cfun_frame_layout.backchain_offset);
7878
7879 cfun_frame_layout.frame_size += STACK_POINTER_OFFSET - lowest_offset;
7880
7881 /* If under 31 bit an odd number of gprs has to be saved we have to
7882 adjust the frame size to sustain 8 byte alignment of stack
7883 frames. */
7884 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
7885 STACK_BOUNDARY / BITS_PER_UNIT - 1)
7886 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
7887 }
7888
7889 /* Generate frame layout. Fills in register and frame data for the current
7890 function in cfun->machine. This routine can be called multiple times;
7891 it will re-do the complete frame layout every time. */
7892
7893 static void
7894 s390_init_frame_layout (void)
7895 {
7896 HOST_WIDE_INT frame_size;
7897 int base_used;
7898
7899 gcc_assert (!reload_completed);
7900
7901 /* On S/390 machines, we may need to perform branch splitting, which
7902 will require both base and return address register. We have no
7903 choice but to assume we're going to need them until right at the
7904 end of the machine dependent reorg phase. */
7905 if (!TARGET_CPU_ZARCH)
7906 cfun->machine->split_branches_pending_p = true;
7907
7908 do
7909 {
7910 frame_size = cfun_frame_layout.frame_size;
7911
7912 /* Try to predict whether we'll need the base register. */
7913 base_used = cfun->machine->split_branches_pending_p
7914 || crtl->uses_const_pool
7915 || (!DISP_IN_RANGE (frame_size)
7916 && !CONST_OK_FOR_K (frame_size));
7917
7918 /* Decide which register to use as literal pool base. In small
7919 leaf functions, try to use an unused call-clobbered register
7920 as base register to avoid save/restore overhead. */
7921 if (!base_used)
7922 cfun->machine->base_reg = NULL_RTX;
7923 else if (crtl->is_leaf && !df_regs_ever_live_p (5))
7924 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
7925 else
7926 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
7927
7928 s390_register_info ();
7929 s390_frame_info ();
7930 }
7931 while (frame_size != cfun_frame_layout.frame_size);
7932 }
7933
7934 /* Remove the FPR clobbers from a tbegin insn if it can be proven that
7935 the TX is nonescaping. A transaction is considered escaping if
7936 there is at least one path from tbegin returning CC0 to the
7937 function exit block without an tend.
7938
7939 The check so far has some limitations:
7940 - only single tbegin/tend BBs are supported
7941 - the first cond jump after tbegin must separate the CC0 path from ~CC0
7942 - when CC is copied to a GPR and the CC0 check is done with the GPR
7943 this is not supported
7944 */
7945
7946 static void
7947 s390_optimize_nonescaping_tx (void)
7948 {
7949 const unsigned int CC0 = 1 << 3;
7950 basic_block tbegin_bb = NULL;
7951 basic_block tend_bb = NULL;
7952 basic_block bb;
7953 rtx_insn *insn;
7954 bool result = true;
7955 int bb_index;
7956 rtx_insn *tbegin_insn = NULL;
7957
7958 if (!cfun->machine->tbegin_p)
7959 return;
7960
7961 for (bb_index = 0; bb_index < n_basic_blocks_for_fn (cfun); bb_index++)
7962 {
7963 bb = BASIC_BLOCK_FOR_FN (cfun, bb_index);
7964
7965 if (!bb)
7966 continue;
7967
7968 FOR_BB_INSNS (bb, insn)
7969 {
7970 rtx ite, cc, pat, target;
7971 unsigned HOST_WIDE_INT mask;
7972
7973 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
7974 continue;
7975
7976 pat = PATTERN (insn);
7977
7978 if (GET_CODE (pat) == PARALLEL)
7979 pat = XVECEXP (pat, 0, 0);
7980
7981 if (GET_CODE (pat) != SET
7982 || GET_CODE (SET_SRC (pat)) != UNSPEC_VOLATILE)
7983 continue;
7984
7985 if (XINT (SET_SRC (pat), 1) == UNSPECV_TBEGIN)
7986 {
7987 rtx_insn *tmp;
7988
7989 tbegin_insn = insn;
7990
7991 /* Just return if the tbegin doesn't have clobbers. */
7992 if (GET_CODE (PATTERN (insn)) != PARALLEL)
7993 return;
7994
7995 if (tbegin_bb != NULL)
7996 return;
7997
7998 /* Find the next conditional jump. */
7999 for (tmp = NEXT_INSN (insn);
8000 tmp != NULL_RTX;
8001 tmp = NEXT_INSN (tmp))
8002 {
8003 if (reg_set_p (gen_rtx_REG (CCmode, CC_REGNUM), tmp))
8004 return;
8005 if (!JUMP_P (tmp))
8006 continue;
8007
8008 ite = SET_SRC (PATTERN (tmp));
8009 if (GET_CODE (ite) != IF_THEN_ELSE)
8010 continue;
8011
8012 cc = XEXP (XEXP (ite, 0), 0);
8013 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc))
8014 || GET_MODE (cc) != CCRAWmode
8015 || GET_CODE (XEXP (XEXP (ite, 0), 1)) != CONST_INT)
8016 return;
8017
8018 if (bb->succs->length () != 2)
8019 return;
8020
8021 mask = INTVAL (XEXP (XEXP (ite, 0), 1));
8022 if (GET_CODE (XEXP (ite, 0)) == NE)
8023 mask ^= 0xf;
8024
8025 if (mask == CC0)
8026 target = XEXP (ite, 1);
8027 else if (mask == (CC0 ^ 0xf))
8028 target = XEXP (ite, 2);
8029 else
8030 return;
8031
8032 {
8033 edge_iterator ei;
8034 edge e1, e2;
8035
8036 ei = ei_start (bb->succs);
8037 e1 = ei_safe_edge (ei);
8038 ei_next (&ei);
8039 e2 = ei_safe_edge (ei);
8040
8041 if (e2->flags & EDGE_FALLTHRU)
8042 {
8043 e2 = e1;
8044 e1 = ei_safe_edge (ei);
8045 }
8046
8047 if (!(e1->flags & EDGE_FALLTHRU))
8048 return;
8049
8050 tbegin_bb = (target == pc_rtx) ? e1->dest : e2->dest;
8051 }
8052 if (tmp == BB_END (bb))
8053 break;
8054 }
8055 }
8056
8057 if (XINT (SET_SRC (pat), 1) == UNSPECV_TEND)
8058 {
8059 if (tend_bb != NULL)
8060 return;
8061 tend_bb = bb;
8062 }
8063 }
8064 }
8065
8066 /* Either we successfully remove the FPR clobbers here or we are not
8067 able to do anything for this TX. Both cases don't qualify for
8068 another look. */
8069 cfun->machine->tbegin_p = false;
8070
8071 if (tbegin_bb == NULL || tend_bb == NULL)
8072 return;
8073
8074 calculate_dominance_info (CDI_POST_DOMINATORS);
8075 result = dominated_by_p (CDI_POST_DOMINATORS, tbegin_bb, tend_bb);
8076 free_dominance_info (CDI_POST_DOMINATORS);
8077
8078 if (!result)
8079 return;
8080
8081 PATTERN (tbegin_insn) = gen_rtx_PARALLEL (VOIDmode,
8082 gen_rtvec (2,
8083 XVECEXP (PATTERN (tbegin_insn), 0, 0),
8084 XVECEXP (PATTERN (tbegin_insn), 0, 1)));
8085 INSN_CODE (tbegin_insn) = -1;
8086 df_insn_rescan (tbegin_insn);
8087
8088 return;
8089 }
8090
8091 /* Return true if it is legal to put a value with MODE into REGNO. */
8092
8093 bool
8094 s390_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
8095 {
8096 switch (REGNO_REG_CLASS (regno))
8097 {
8098 case FP_REGS:
8099 if (REGNO_PAIR_OK (regno, mode))
8100 {
8101 if (mode == SImode || mode == DImode)
8102 return true;
8103
8104 if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
8105 return true;
8106 }
8107 break;
8108 case ADDR_REGS:
8109 if (FRAME_REGNO_P (regno) && mode == Pmode)
8110 return true;
8111
8112 /* fallthrough */
8113 case GENERAL_REGS:
8114 if (REGNO_PAIR_OK (regno, mode))
8115 {
8116 if (TARGET_ZARCH
8117 || (mode != TFmode && mode != TCmode && mode != TDmode))
8118 return true;
8119 }
8120 break;
8121 case CC_REGS:
8122 if (GET_MODE_CLASS (mode) == MODE_CC)
8123 return true;
8124 break;
8125 case ACCESS_REGS:
8126 if (REGNO_PAIR_OK (regno, mode))
8127 {
8128 if (mode == SImode || mode == Pmode)
8129 return true;
8130 }
8131 break;
8132 default:
8133 return false;
8134 }
8135
8136 return false;
8137 }
8138
8139 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
8140
8141 bool
8142 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
8143 {
8144 /* Once we've decided upon a register to use as base register, it must
8145 no longer be used for any other purpose. */
8146 if (cfun->machine->base_reg)
8147 if (REGNO (cfun->machine->base_reg) == old_reg
8148 || REGNO (cfun->machine->base_reg) == new_reg)
8149 return false;
8150
8151 /* Prevent regrename from using call-saved regs which haven't
8152 actually been saved. This is necessary since regrename assumes
8153 the backend save/restore decisions are based on
8154 df_regs_ever_live. Since we have our own routine we have to tell
8155 regrename manually about it. */
8156 if (GENERAL_REGNO_P (new_reg)
8157 && !call_really_used_regs[new_reg]
8158 && cfun_gpr_save_slot (new_reg) == 0)
8159 return false;
8160
8161 return true;
8162 }
8163
8164 /* Return nonzero if register REGNO can be used as a scratch register
8165 in peephole2. */
8166
8167 static bool
8168 s390_hard_regno_scratch_ok (unsigned int regno)
8169 {
8170 /* See s390_hard_regno_rename_ok. */
8171 if (GENERAL_REGNO_P (regno)
8172 && !call_really_used_regs[regno]
8173 && cfun_gpr_save_slot (regno) == 0)
8174 return false;
8175
8176 return true;
8177 }
8178
8179 /* Maximum number of registers to represent a value of mode MODE
8180 in a register of class RCLASS. */
8181
8182 int
8183 s390_class_max_nregs (enum reg_class rclass, machine_mode mode)
8184 {
8185 switch (rclass)
8186 {
8187 case FP_REGS:
8188 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
8189 return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
8190 else
8191 return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
8192 case ACCESS_REGS:
8193 return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
8194 default:
8195 break;
8196 }
8197 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8198 }
8199
8200 /* Return true if we use LRA instead of reload pass. */
8201 static bool
8202 s390_lra_p (void)
8203 {
8204 return s390_lra_flag;
8205 }
8206
8207 /* Return true if register FROM can be eliminated via register TO. */
8208
8209 static bool
8210 s390_can_eliminate (const int from, const int to)
8211 {
8212 /* On zSeries machines, we have not marked the base register as fixed.
8213 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
8214 If a function requires the base register, we say here that this
8215 elimination cannot be performed. This will cause reload to free
8216 up the base register (as if it were fixed). On the other hand,
8217 if the current function does *not* require the base register, we
8218 say here the elimination succeeds, which in turn allows reload
8219 to allocate the base register for any other purpose. */
8220 if (from == BASE_REGNUM && to == BASE_REGNUM)
8221 {
8222 if (TARGET_CPU_ZARCH)
8223 {
8224 s390_init_frame_layout ();
8225 return cfun->machine->base_reg == NULL_RTX;
8226 }
8227
8228 return false;
8229 }
8230
8231 /* Everything else must point into the stack frame. */
8232 gcc_assert (to == STACK_POINTER_REGNUM
8233 || to == HARD_FRAME_POINTER_REGNUM);
8234
8235 gcc_assert (from == FRAME_POINTER_REGNUM
8236 || from == ARG_POINTER_REGNUM
8237 || from == RETURN_ADDRESS_POINTER_REGNUM);
8238
8239 /* Make sure we actually saved the return address. */
8240 if (from == RETURN_ADDRESS_POINTER_REGNUM)
8241 if (!crtl->calls_eh_return
8242 && !cfun->stdarg
8243 && !cfun_frame_layout.save_return_addr_p)
8244 return false;
8245
8246 return true;
8247 }
8248
8249 /* Return offset between register FROM and TO initially after prolog. */
8250
8251 HOST_WIDE_INT
8252 s390_initial_elimination_offset (int from, int to)
8253 {
8254 HOST_WIDE_INT offset;
8255
8256 /* ??? Why are we called for non-eliminable pairs? */
8257 if (!s390_can_eliminate (from, to))
8258 return 0;
8259
8260 switch (from)
8261 {
8262 case FRAME_POINTER_REGNUM:
8263 offset = (get_frame_size()
8264 + STACK_POINTER_OFFSET
8265 + crtl->outgoing_args_size);
8266 break;
8267
8268 case ARG_POINTER_REGNUM:
8269 s390_init_frame_layout ();
8270 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
8271 break;
8272
8273 case RETURN_ADDRESS_POINTER_REGNUM:
8274 s390_init_frame_layout ();
8275
8276 if (cfun_frame_layout.first_save_gpr_slot == -1)
8277 {
8278 /* If it turns out that for stdarg nothing went into the reg
8279 save area we also do not need the return address
8280 pointer. */
8281 if (cfun->stdarg && !cfun_save_arg_fprs_p)
8282 return 0;
8283
8284 gcc_unreachable ();
8285 }
8286
8287 /* In order to make the following work it is not necessary for
8288 r14 to have a save slot. It is sufficient if one other GPR
8289 got one. Since the GPRs are always stored without gaps we
8290 are able to calculate where the r14 save slot would
8291 reside. */
8292 offset = (cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset +
8293 (RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot) *
8294 UNITS_PER_LONG);
8295 break;
8296
8297 case BASE_REGNUM:
8298 offset = 0;
8299 break;
8300
8301 default:
8302 gcc_unreachable ();
8303 }
8304
8305 return offset;
8306 }
8307
8308 /* Emit insn to save fpr REGNUM at offset OFFSET relative
8309 to register BASE. Return generated insn. */
8310
8311 static rtx
8312 save_fpr (rtx base, int offset, int regnum)
8313 {
8314 rtx addr;
8315 addr = gen_rtx_MEM (DFmode, plus_constant (Pmode, base, offset));
8316
8317 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
8318 set_mem_alias_set (addr, get_varargs_alias_set ());
8319 else
8320 set_mem_alias_set (addr, get_frame_alias_set ());
8321
8322 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
8323 }
8324
8325 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
8326 to register BASE. Return generated insn. */
8327
8328 static rtx
8329 restore_fpr (rtx base, int offset, int regnum)
8330 {
8331 rtx addr;
8332 addr = gen_rtx_MEM (DFmode, plus_constant (Pmode, base, offset));
8333 set_mem_alias_set (addr, get_frame_alias_set ());
8334
8335 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
8336 }
8337
8338 /* Return true if REGNO is a global register, but not one
8339 of the special ones that need to be saved/restored in anyway. */
8340
8341 static inline bool
8342 global_not_special_regno_p (int regno)
8343 {
8344 return (global_regs[regno]
8345 /* These registers are special and need to be
8346 restored in any case. */
8347 && !(regno == STACK_POINTER_REGNUM
8348 || regno == RETURN_REGNUM
8349 || regno == BASE_REGNUM
8350 || (flag_pic && regno == (int)PIC_OFFSET_TABLE_REGNUM)));
8351 }
8352
8353 /* Generate insn to save registers FIRST to LAST into
8354 the register save area located at offset OFFSET
8355 relative to register BASE. */
8356
8357 static rtx
8358 save_gprs (rtx base, int offset, int first, int last)
8359 {
8360 rtx addr, insn, note;
8361 int i;
8362
8363 addr = plus_constant (Pmode, base, offset);
8364 addr = gen_rtx_MEM (Pmode, addr);
8365
8366 set_mem_alias_set (addr, get_frame_alias_set ());
8367
8368 /* Special-case single register. */
8369 if (first == last)
8370 {
8371 if (TARGET_64BIT)
8372 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
8373 else
8374 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
8375
8376 if (!global_not_special_regno_p (first))
8377 RTX_FRAME_RELATED_P (insn) = 1;
8378 return insn;
8379 }
8380
8381
8382 insn = gen_store_multiple (addr,
8383 gen_rtx_REG (Pmode, first),
8384 GEN_INT (last - first + 1));
8385
8386 if (first <= 6 && cfun->stdarg)
8387 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8388 {
8389 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
8390
8391 if (first + i <= 6)
8392 set_mem_alias_set (mem, get_varargs_alias_set ());
8393 }
8394
8395 /* We need to set the FRAME_RELATED flag on all SETs
8396 inside the store-multiple pattern.
8397
8398 However, we must not emit DWARF records for registers 2..5
8399 if they are stored for use by variable arguments ...
8400
8401 ??? Unfortunately, it is not enough to simply not the
8402 FRAME_RELATED flags for those SETs, because the first SET
8403 of the PARALLEL is always treated as if it had the flag
8404 set, even if it does not. Therefore we emit a new pattern
8405 without those registers as REG_FRAME_RELATED_EXPR note. */
8406
8407 if (first >= 6 && !global_not_special_regno_p (first))
8408 {
8409 rtx pat = PATTERN (insn);
8410
8411 for (i = 0; i < XVECLEN (pat, 0); i++)
8412 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
8413 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat,
8414 0, i)))))
8415 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
8416
8417 RTX_FRAME_RELATED_P (insn) = 1;
8418 }
8419 else if (last >= 6)
8420 {
8421 int start;
8422
8423 for (start = first >= 6 ? first : 6; start <= last; start++)
8424 if (!global_not_special_regno_p (start))
8425 break;
8426
8427 if (start > last)
8428 return insn;
8429
8430 addr = plus_constant (Pmode, base,
8431 offset + (start - first) * UNITS_PER_LONG);
8432
8433 if (start == last)
8434 {
8435 if (TARGET_64BIT)
8436 note = gen_movdi (gen_rtx_MEM (Pmode, addr),
8437 gen_rtx_REG (Pmode, start));
8438 else
8439 note = gen_movsi (gen_rtx_MEM (Pmode, addr),
8440 gen_rtx_REG (Pmode, start));
8441 note = PATTERN (note);
8442
8443 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
8444 RTX_FRAME_RELATED_P (insn) = 1;
8445
8446 return insn;
8447 }
8448
8449 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
8450 gen_rtx_REG (Pmode, start),
8451 GEN_INT (last - start + 1));
8452 note = PATTERN (note);
8453
8454 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
8455
8456 for (i = 0; i < XVECLEN (note, 0); i++)
8457 if (GET_CODE (XVECEXP (note, 0, i)) == SET
8458 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note,
8459 0, i)))))
8460 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
8461
8462 RTX_FRAME_RELATED_P (insn) = 1;
8463 }
8464
8465 return insn;
8466 }
8467
8468 /* Generate insn to restore registers FIRST to LAST from
8469 the register save area located at offset OFFSET
8470 relative to register BASE. */
8471
8472 static rtx
8473 restore_gprs (rtx base, int offset, int first, int last)
8474 {
8475 rtx addr, insn;
8476
8477 addr = plus_constant (Pmode, base, offset);
8478 addr = gen_rtx_MEM (Pmode, addr);
8479 set_mem_alias_set (addr, get_frame_alias_set ());
8480
8481 /* Special-case single register. */
8482 if (first == last)
8483 {
8484 if (TARGET_64BIT)
8485 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
8486 else
8487 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
8488
8489 RTX_FRAME_RELATED_P (insn) = 1;
8490 return insn;
8491 }
8492
8493 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
8494 addr,
8495 GEN_INT (last - first + 1));
8496 RTX_FRAME_RELATED_P (insn) = 1;
8497 return insn;
8498 }
8499
8500 /* Return insn sequence to load the GOT register. */
8501
8502 static GTY(()) rtx got_symbol;
8503 rtx_insn *
8504 s390_load_got (void)
8505 {
8506 rtx_insn *insns;
8507
8508 /* We cannot use pic_offset_table_rtx here since we use this
8509 function also for non-pic if __tls_get_offset is called and in
8510 that case PIC_OFFSET_TABLE_REGNUM as well as pic_offset_table_rtx
8511 aren't usable. */
8512 rtx got_rtx = gen_rtx_REG (Pmode, 12);
8513
8514 if (!got_symbol)
8515 {
8516 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
8517 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
8518 }
8519
8520 start_sequence ();
8521
8522 if (TARGET_CPU_ZARCH)
8523 {
8524 emit_move_insn (got_rtx, got_symbol);
8525 }
8526 else
8527 {
8528 rtx offset;
8529
8530 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
8531 UNSPEC_LTREL_OFFSET);
8532 offset = gen_rtx_CONST (Pmode, offset);
8533 offset = force_const_mem (Pmode, offset);
8534
8535 emit_move_insn (got_rtx, offset);
8536
8537 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
8538 UNSPEC_LTREL_BASE);
8539 offset = gen_rtx_PLUS (Pmode, got_rtx, offset);
8540
8541 emit_move_insn (got_rtx, offset);
8542 }
8543
8544 insns = get_insns ();
8545 end_sequence ();
8546 return insns;
8547 }
8548
8549 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
8550 and the change to the stack pointer. */
8551
8552 static void
8553 s390_emit_stack_tie (void)
8554 {
8555 rtx mem = gen_frame_mem (BLKmode,
8556 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
8557
8558 emit_insn (gen_stack_tie (mem));
8559 }
8560
8561 /* Copy GPRS into FPR save slots. */
8562
8563 static void
8564 s390_save_gprs_to_fprs (void)
8565 {
8566 int i;
8567
8568 if (!TARGET_Z10 || !TARGET_HARD_FLOAT || !crtl->is_leaf)
8569 return;
8570
8571 for (i = 6; i < 16; i++)
8572 {
8573 if (FP_REGNO_P (cfun_gpr_save_slot (i)))
8574 {
8575 rtx_insn *insn =
8576 emit_move_insn (gen_rtx_REG (DImode, cfun_gpr_save_slot (i)),
8577 gen_rtx_REG (DImode, i));
8578 RTX_FRAME_RELATED_P (insn) = 1;
8579 }
8580 }
8581 }
8582
8583 /* Restore GPRs from FPR save slots. */
8584
8585 static void
8586 s390_restore_gprs_from_fprs (void)
8587 {
8588 int i;
8589
8590 if (!TARGET_Z10 || !TARGET_HARD_FLOAT || !crtl->is_leaf)
8591 return;
8592
8593 for (i = 6; i < 16; i++)
8594 {
8595 if (FP_REGNO_P (cfun_gpr_save_slot (i)))
8596 {
8597 rtx_insn *insn =
8598 emit_move_insn (gen_rtx_REG (DImode, i),
8599 gen_rtx_REG (DImode, cfun_gpr_save_slot (i)));
8600 df_set_regs_ever_live (i, true);
8601 add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (DImode, i));
8602 if (i == STACK_POINTER_REGNUM)
8603 add_reg_note (insn, REG_CFA_DEF_CFA,
8604 plus_constant (Pmode, stack_pointer_rtx,
8605 STACK_POINTER_OFFSET));
8606 RTX_FRAME_RELATED_P (insn) = 1;
8607 }
8608 }
8609 }
8610
8611
8612 /* A pass run immediately before shrink-wrapping and prologue and epilogue
8613 generation. */
8614
8615 namespace {
8616
8617 const pass_data pass_data_s390_early_mach =
8618 {
8619 RTL_PASS, /* type */
8620 "early_mach", /* name */
8621 OPTGROUP_NONE, /* optinfo_flags */
8622 TV_MACH_DEP, /* tv_id */
8623 0, /* properties_required */
8624 0, /* properties_provided */
8625 0, /* properties_destroyed */
8626 0, /* todo_flags_start */
8627 ( TODO_df_verify | TODO_df_finish ), /* todo_flags_finish */
8628 };
8629
8630 class pass_s390_early_mach : public rtl_opt_pass
8631 {
8632 public:
8633 pass_s390_early_mach (gcc::context *ctxt)
8634 : rtl_opt_pass (pass_data_s390_early_mach, ctxt)
8635 {}
8636
8637 /* opt_pass methods: */
8638 virtual unsigned int execute (function *);
8639
8640 }; // class pass_s390_early_mach
8641
8642 unsigned int
8643 pass_s390_early_mach::execute (function *fun)
8644 {
8645 rtx_insn *insn;
8646
8647 /* Try to get rid of the FPR clobbers. */
8648 s390_optimize_nonescaping_tx ();
8649
8650 /* Re-compute register info. */
8651 s390_register_info ();
8652
8653 /* If we're using a base register, ensure that it is always valid for
8654 the first non-prologue instruction. */
8655 if (fun->machine->base_reg)
8656 emit_insn_at_entry (gen_main_pool (fun->machine->base_reg));
8657
8658 /* Annotate all constant pool references to let the scheduler know
8659 they implicitly use the base register. */
8660 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8661 if (INSN_P (insn))
8662 {
8663 annotate_constant_pool_refs (&PATTERN (insn));
8664 df_insn_rescan (insn);
8665 }
8666 return 0;
8667 }
8668
8669 } // anon namespace
8670
8671 /* Expand the prologue into a bunch of separate insns. */
8672
8673 void
8674 s390_emit_prologue (void)
8675 {
8676 rtx insn, addr;
8677 rtx temp_reg;
8678 int i;
8679 int offset;
8680 int next_fpr = 0;
8681
8682 /* Choose best register to use for temp use within prologue.
8683 See below for why TPF must use the register 1. */
8684
8685 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
8686 && !crtl->is_leaf
8687 && !TARGET_TPF_PROFILING)
8688 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
8689 else
8690 temp_reg = gen_rtx_REG (Pmode, 1);
8691
8692 s390_save_gprs_to_fprs ();
8693
8694 /* Save call saved gprs. */
8695 if (cfun_frame_layout.first_save_gpr != -1)
8696 {
8697 insn = save_gprs (stack_pointer_rtx,
8698 cfun_frame_layout.gprs_offset +
8699 UNITS_PER_LONG * (cfun_frame_layout.first_save_gpr
8700 - cfun_frame_layout.first_save_gpr_slot),
8701 cfun_frame_layout.first_save_gpr,
8702 cfun_frame_layout.last_save_gpr);
8703 emit_insn (insn);
8704 }
8705
8706 /* Dummy insn to mark literal pool slot. */
8707
8708 if (cfun->machine->base_reg)
8709 emit_insn (gen_main_pool (cfun->machine->base_reg));
8710
8711 offset = cfun_frame_layout.f0_offset;
8712
8713 /* Save f0 and f2. */
8714 for (i = FPR0_REGNUM; i <= FPR0_REGNUM + 1; i++)
8715 {
8716 if (cfun_fpr_save_p (i))
8717 {
8718 save_fpr (stack_pointer_rtx, offset, i);
8719 offset += 8;
8720 }
8721 else if (!TARGET_PACKED_STACK || cfun->stdarg)
8722 offset += 8;
8723 }
8724
8725 /* Save f4 and f6. */
8726 offset = cfun_frame_layout.f4_offset;
8727 for (i = FPR4_REGNUM; i <= FPR4_REGNUM + 1; i++)
8728 {
8729 if (cfun_fpr_save_p (i))
8730 {
8731 insn = save_fpr (stack_pointer_rtx, offset, i);
8732 offset += 8;
8733
8734 /* If f4 and f6 are call clobbered they are saved due to
8735 stdargs and therefore are not frame related. */
8736 if (!call_really_used_regs[i])
8737 RTX_FRAME_RELATED_P (insn) = 1;
8738 }
8739 else if (!TARGET_PACKED_STACK || call_really_used_regs[i])
8740 offset += 8;
8741 }
8742
8743 if (TARGET_PACKED_STACK
8744 && cfun_save_high_fprs_p
8745 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
8746 {
8747 offset = (cfun_frame_layout.f8_offset
8748 + (cfun_frame_layout.high_fprs - 1) * 8);
8749
8750 for (i = FPR15_REGNUM; i >= FPR8_REGNUM && offset >= 0; i--)
8751 if (cfun_fpr_save_p (i))
8752 {
8753 insn = save_fpr (stack_pointer_rtx, offset, i);
8754
8755 RTX_FRAME_RELATED_P (insn) = 1;
8756 offset -= 8;
8757 }
8758 if (offset >= cfun_frame_layout.f8_offset)
8759 next_fpr = i;
8760 }
8761
8762 if (!TARGET_PACKED_STACK)
8763 next_fpr = cfun_save_high_fprs_p ? FPR15_REGNUM : 0;
8764
8765 if (flag_stack_usage_info)
8766 current_function_static_stack_size = cfun_frame_layout.frame_size;
8767
8768 /* Decrement stack pointer. */
8769
8770 if (cfun_frame_layout.frame_size > 0)
8771 {
8772 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
8773 rtx real_frame_off;
8774
8775 if (s390_stack_size)
8776 {
8777 HOST_WIDE_INT stack_guard;
8778
8779 if (s390_stack_guard)
8780 stack_guard = s390_stack_guard;
8781 else
8782 {
8783 /* If no value for stack guard is provided the smallest power of 2
8784 larger than the current frame size is chosen. */
8785 stack_guard = 1;
8786 while (stack_guard < cfun_frame_layout.frame_size)
8787 stack_guard <<= 1;
8788 }
8789
8790 if (cfun_frame_layout.frame_size >= s390_stack_size)
8791 {
8792 warning (0, "frame size of function %qs is %wd"
8793 " bytes exceeding user provided stack limit of "
8794 "%d bytes. "
8795 "An unconditional trap is added.",
8796 current_function_name(), cfun_frame_layout.frame_size,
8797 s390_stack_size);
8798 emit_insn (gen_trap ());
8799 }
8800 else
8801 {
8802 /* stack_guard has to be smaller than s390_stack_size.
8803 Otherwise we would emit an AND with zero which would
8804 not match the test under mask pattern. */
8805 if (stack_guard >= s390_stack_size)
8806 {
8807 warning (0, "frame size of function %qs is %wd"
8808 " bytes which is more than half the stack size. "
8809 "The dynamic check would not be reliable. "
8810 "No check emitted for this function.",
8811 current_function_name(),
8812 cfun_frame_layout.frame_size);
8813 }
8814 else
8815 {
8816 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
8817 & ~(stack_guard - 1));
8818
8819 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
8820 GEN_INT (stack_check_mask));
8821 if (TARGET_64BIT)
8822 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode,
8823 t, const0_rtx),
8824 t, const0_rtx, const0_rtx));
8825 else
8826 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode,
8827 t, const0_rtx),
8828 t, const0_rtx, const0_rtx));
8829 }
8830 }
8831 }
8832
8833 if (s390_warn_framesize > 0
8834 && cfun_frame_layout.frame_size >= s390_warn_framesize)
8835 warning (0, "frame size of %qs is %wd bytes",
8836 current_function_name (), cfun_frame_layout.frame_size);
8837
8838 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
8839 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
8840
8841 /* Save incoming stack pointer into temp reg. */
8842 if (TARGET_BACKCHAIN || next_fpr)
8843 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
8844
8845 /* Subtract frame size from stack pointer. */
8846
8847 if (DISP_IN_RANGE (INTVAL (frame_off)))
8848 {
8849 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8850 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8851 frame_off));
8852 insn = emit_insn (insn);
8853 }
8854 else
8855 {
8856 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8857 frame_off = force_const_mem (Pmode, frame_off);
8858
8859 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
8860 annotate_constant_pool_refs (&PATTERN (insn));
8861 }
8862
8863 RTX_FRAME_RELATED_P (insn) = 1;
8864 real_frame_off = GEN_INT (-cfun_frame_layout.frame_size);
8865 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8866 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8867 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8868 real_frame_off)));
8869
8870 /* Set backchain. */
8871
8872 if (TARGET_BACKCHAIN)
8873 {
8874 if (cfun_frame_layout.backchain_offset)
8875 addr = gen_rtx_MEM (Pmode,
8876 plus_constant (Pmode, stack_pointer_rtx,
8877 cfun_frame_layout.backchain_offset));
8878 else
8879 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
8880 set_mem_alias_set (addr, get_frame_alias_set ());
8881 insn = emit_insn (gen_move_insn (addr, temp_reg));
8882 }
8883
8884 /* If we support non-call exceptions (e.g. for Java),
8885 we need to make sure the backchain pointer is set up
8886 before any possibly trapping memory access. */
8887 if (TARGET_BACKCHAIN && cfun->can_throw_non_call_exceptions)
8888 {
8889 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
8890 emit_clobber (addr);
8891 }
8892 }
8893
8894 /* Save fprs 8 - 15 (64 bit ABI). */
8895
8896 if (cfun_save_high_fprs_p && next_fpr)
8897 {
8898 /* If the stack might be accessed through a different register
8899 we have to make sure that the stack pointer decrement is not
8900 moved below the use of the stack slots. */
8901 s390_emit_stack_tie ();
8902
8903 insn = emit_insn (gen_add2_insn (temp_reg,
8904 GEN_INT (cfun_frame_layout.f8_offset)));
8905
8906 offset = 0;
8907
8908 for (i = FPR8_REGNUM; i <= next_fpr; i++)
8909 if (cfun_fpr_save_p (i))
8910 {
8911 rtx addr = plus_constant (Pmode, stack_pointer_rtx,
8912 cfun_frame_layout.frame_size
8913 + cfun_frame_layout.f8_offset
8914 + offset);
8915
8916 insn = save_fpr (temp_reg, offset, i);
8917 offset += 8;
8918 RTX_FRAME_RELATED_P (insn) = 1;
8919 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8920 gen_rtx_SET (VOIDmode,
8921 gen_rtx_MEM (DFmode, addr),
8922 gen_rtx_REG (DFmode, i)));
8923 }
8924 }
8925
8926 /* Set frame pointer, if needed. */
8927
8928 if (frame_pointer_needed)
8929 {
8930 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8931 RTX_FRAME_RELATED_P (insn) = 1;
8932 }
8933
8934 /* Set up got pointer, if needed. */
8935
8936 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
8937 {
8938 rtx_insn *insns = s390_load_got ();
8939
8940 for (rtx_insn *insn = insns; insn; insn = NEXT_INSN (insn))
8941 annotate_constant_pool_refs (&PATTERN (insn));
8942
8943 emit_insn (insns);
8944 }
8945
8946 if (TARGET_TPF_PROFILING)
8947 {
8948 /* Generate a BAS instruction to serve as a function
8949 entry intercept to facilitate the use of tracing
8950 algorithms located at the branch target. */
8951 emit_insn (gen_prologue_tpf ());
8952
8953 /* Emit a blockage here so that all code
8954 lies between the profiling mechanisms. */
8955 emit_insn (gen_blockage ());
8956 }
8957 }
8958
8959 /* Expand the epilogue into a bunch of separate insns. */
8960
8961 void
8962 s390_emit_epilogue (bool sibcall)
8963 {
8964 rtx frame_pointer, return_reg, cfa_restores = NULL_RTX;
8965 int area_bottom, area_top, offset = 0;
8966 int next_offset;
8967 rtvec p;
8968 int i;
8969
8970 if (TARGET_TPF_PROFILING)
8971 {
8972
8973 /* Generate a BAS instruction to serve as a function
8974 entry intercept to facilitate the use of tracing
8975 algorithms located at the branch target. */
8976
8977 /* Emit a blockage here so that all code
8978 lies between the profiling mechanisms. */
8979 emit_insn (gen_blockage ());
8980
8981 emit_insn (gen_epilogue_tpf ());
8982 }
8983
8984 /* Check whether to use frame or stack pointer for restore. */
8985
8986 frame_pointer = (frame_pointer_needed
8987 ? hard_frame_pointer_rtx : stack_pointer_rtx);
8988
8989 s390_frame_area (&area_bottom, &area_top);
8990
8991 /* Check whether we can access the register save area.
8992 If not, increment the frame pointer as required. */
8993
8994 if (area_top <= area_bottom)
8995 {
8996 /* Nothing to restore. */
8997 }
8998 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
8999 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
9000 {
9001 /* Area is in range. */
9002 offset = cfun_frame_layout.frame_size;
9003 }
9004 else
9005 {
9006 rtx insn, frame_off, cfa;
9007
9008 offset = area_bottom < 0 ? -area_bottom : 0;
9009 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
9010
9011 cfa = gen_rtx_SET (VOIDmode, frame_pointer,
9012 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
9013 if (DISP_IN_RANGE (INTVAL (frame_off)))
9014 {
9015 insn = gen_rtx_SET (VOIDmode, frame_pointer,
9016 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
9017 insn = emit_insn (insn);
9018 }
9019 else
9020 {
9021 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
9022 frame_off = force_const_mem (Pmode, frame_off);
9023
9024 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
9025 annotate_constant_pool_refs (&PATTERN (insn));
9026 }
9027 add_reg_note (insn, REG_CFA_ADJUST_CFA, cfa);
9028 RTX_FRAME_RELATED_P (insn) = 1;
9029 }
9030
9031 /* Restore call saved fprs. */
9032
9033 if (TARGET_64BIT)
9034 {
9035 if (cfun_save_high_fprs_p)
9036 {
9037 next_offset = cfun_frame_layout.f8_offset;
9038 for (i = FPR8_REGNUM; i <= FPR15_REGNUM; i++)
9039 {
9040 if (cfun_fpr_save_p (i))
9041 {
9042 restore_fpr (frame_pointer,
9043 offset + next_offset, i);
9044 cfa_restores
9045 = alloc_reg_note (REG_CFA_RESTORE,
9046 gen_rtx_REG (DFmode, i), cfa_restores);
9047 next_offset += 8;
9048 }
9049 }
9050 }
9051
9052 }
9053 else
9054 {
9055 next_offset = cfun_frame_layout.f4_offset;
9056 /* f4, f6 */
9057 for (i = FPR4_REGNUM; i <= FPR4_REGNUM + 1; i++)
9058 {
9059 if (cfun_fpr_save_p (i))
9060 {
9061 restore_fpr (frame_pointer,
9062 offset + next_offset, i);
9063 cfa_restores
9064 = alloc_reg_note (REG_CFA_RESTORE,
9065 gen_rtx_REG (DFmode, i), cfa_restores);
9066 next_offset += 8;
9067 }
9068 else if (!TARGET_PACKED_STACK)
9069 next_offset += 8;
9070 }
9071
9072 }
9073
9074 /* Return register. */
9075
9076 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
9077
9078 /* Restore call saved gprs. */
9079
9080 if (cfun_frame_layout.first_restore_gpr != -1)
9081 {
9082 rtx insn, addr;
9083 int i;
9084
9085 /* Check for global register and save them
9086 to stack location from where they get restored. */
9087
9088 for (i = cfun_frame_layout.first_restore_gpr;
9089 i <= cfun_frame_layout.last_restore_gpr;
9090 i++)
9091 {
9092 if (global_not_special_regno_p (i))
9093 {
9094 addr = plus_constant (Pmode, frame_pointer,
9095 offset + cfun_frame_layout.gprs_offset
9096 + (i - cfun_frame_layout.first_save_gpr_slot)
9097 * UNITS_PER_LONG);
9098 addr = gen_rtx_MEM (Pmode, addr);
9099 set_mem_alias_set (addr, get_frame_alias_set ());
9100 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
9101 }
9102 else
9103 cfa_restores
9104 = alloc_reg_note (REG_CFA_RESTORE,
9105 gen_rtx_REG (Pmode, i), cfa_restores);
9106 }
9107
9108 if (! sibcall)
9109 {
9110 /* Fetch return address from stack before load multiple,
9111 this will do good for scheduling.
9112
9113 Only do this if we already decided that r14 needs to be
9114 saved to a stack slot. (And not just because r14 happens to
9115 be in between two GPRs which need saving.) Otherwise it
9116 would be difficult to take that decision back in
9117 s390_optimize_prologue. */
9118 if (cfun_gpr_save_slot (RETURN_REGNUM) == -1)
9119 {
9120 int return_regnum = find_unused_clobbered_reg();
9121 if (!return_regnum)
9122 return_regnum = 4;
9123 return_reg = gen_rtx_REG (Pmode, return_regnum);
9124
9125 addr = plus_constant (Pmode, frame_pointer,
9126 offset + cfun_frame_layout.gprs_offset
9127 + (RETURN_REGNUM
9128 - cfun_frame_layout.first_save_gpr_slot)
9129 * UNITS_PER_LONG);
9130 addr = gen_rtx_MEM (Pmode, addr);
9131 set_mem_alias_set (addr, get_frame_alias_set ());
9132 emit_move_insn (return_reg, addr);
9133
9134 /* Once we did that optimization we have to make sure
9135 s390_optimize_prologue does not try to remove the
9136 store of r14 since we will not be able to find the
9137 load issued here. */
9138 cfun_frame_layout.save_return_addr_p = true;
9139 }
9140 }
9141
9142 insn = restore_gprs (frame_pointer,
9143 offset + cfun_frame_layout.gprs_offset
9144 + (cfun_frame_layout.first_restore_gpr
9145 - cfun_frame_layout.first_save_gpr_slot)
9146 * UNITS_PER_LONG,
9147 cfun_frame_layout.first_restore_gpr,
9148 cfun_frame_layout.last_restore_gpr);
9149 insn = emit_insn (insn);
9150 REG_NOTES (insn) = cfa_restores;
9151 add_reg_note (insn, REG_CFA_DEF_CFA,
9152 plus_constant (Pmode, stack_pointer_rtx,
9153 STACK_POINTER_OFFSET));
9154 RTX_FRAME_RELATED_P (insn) = 1;
9155 }
9156
9157 s390_restore_gprs_from_fprs ();
9158
9159 if (! sibcall)
9160 {
9161
9162 /* Return to caller. */
9163
9164 p = rtvec_alloc (2);
9165
9166 RTVEC_ELT (p, 0) = ret_rtx;
9167 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
9168 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
9169 }
9170 }
9171
9172 /* Implement TARGET_SET_UP_BY_PROLOGUE. */
9173
9174 static void
9175 s300_set_up_by_prologue (hard_reg_set_container *regs)
9176 {
9177 if (cfun->machine->base_reg
9178 && !call_really_used_regs[REGNO (cfun->machine->base_reg)])
9179 SET_HARD_REG_BIT (regs->set, REGNO (cfun->machine->base_reg));
9180 }
9181
9182 /* Return true if the function can use simple_return to return outside
9183 of a shrink-wrapped region. At present shrink-wrapping is supported
9184 in all cases. */
9185
9186 bool
9187 s390_can_use_simple_return_insn (void)
9188 {
9189 return true;
9190 }
9191
9192 /* Return true if the epilogue is guaranteed to contain only a return
9193 instruction and if a direct return can therefore be used instead.
9194 One of the main advantages of using direct return instructions
9195 is that we can then use conditional returns. */
9196
9197 bool
9198 s390_can_use_return_insn (void)
9199 {
9200 int i;
9201
9202 if (!reload_completed)
9203 return false;
9204
9205 if (crtl->profile)
9206 return false;
9207
9208 if (TARGET_TPF_PROFILING)
9209 return false;
9210
9211 for (i = 0; i < 16; i++)
9212 if (cfun_gpr_save_slot (i))
9213 return false;
9214
9215 /* For 31 bit this is not covered by the frame_size check below
9216 since f4, f6 are saved in the register save area without needing
9217 additional stack space. */
9218 if (!TARGET_64BIT
9219 && (cfun_fpr_save_p (FPR4_REGNUM) || cfun_fpr_save_p (FPR6_REGNUM)))
9220 return false;
9221
9222 if (cfun->machine->base_reg
9223 && !call_really_used_regs[REGNO (cfun->machine->base_reg)])
9224 return false;
9225
9226 return cfun_frame_layout.frame_size == 0;
9227 }
9228
9229 /* Return the size in bytes of a function argument of
9230 type TYPE and/or mode MODE. At least one of TYPE or
9231 MODE must be specified. */
9232
9233 static int
9234 s390_function_arg_size (machine_mode mode, const_tree type)
9235 {
9236 if (type)
9237 return int_size_in_bytes (type);
9238
9239 /* No type info available for some library calls ... */
9240 if (mode != BLKmode)
9241 return GET_MODE_SIZE (mode);
9242
9243 /* If we have neither type nor mode, abort */
9244 gcc_unreachable ();
9245 }
9246
9247 /* Return true if a function argument of type TYPE and mode MODE
9248 is to be passed in a floating-point register, if available. */
9249
9250 static bool
9251 s390_function_arg_float (machine_mode mode, const_tree type)
9252 {
9253 int size = s390_function_arg_size (mode, type);
9254 if (size > 8)
9255 return false;
9256
9257 /* Soft-float changes the ABI: no floating-point registers are used. */
9258 if (TARGET_SOFT_FLOAT)
9259 return false;
9260
9261 /* No type info available for some library calls ... */
9262 if (!type)
9263 return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode;
9264
9265 /* The ABI says that record types with a single member are treated
9266 just like that member would be. */
9267 while (TREE_CODE (type) == RECORD_TYPE)
9268 {
9269 tree field, single = NULL_TREE;
9270
9271 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
9272 {
9273 if (TREE_CODE (field) != FIELD_DECL)
9274 continue;
9275
9276 if (single == NULL_TREE)
9277 single = TREE_TYPE (field);
9278 else
9279 return false;
9280 }
9281
9282 if (single == NULL_TREE)
9283 return false;
9284 else
9285 type = single;
9286 }
9287
9288 return TREE_CODE (type) == REAL_TYPE;
9289 }
9290
9291 /* Return true if a function argument of type TYPE and mode MODE
9292 is to be passed in an integer register, or a pair of integer
9293 registers, if available. */
9294
9295 static bool
9296 s390_function_arg_integer (machine_mode mode, const_tree type)
9297 {
9298 int size = s390_function_arg_size (mode, type);
9299 if (size > 8)
9300 return false;
9301
9302 /* No type info available for some library calls ... */
9303 if (!type)
9304 return GET_MODE_CLASS (mode) == MODE_INT
9305 || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode));
9306
9307 /* We accept small integral (and similar) types. */
9308 if (INTEGRAL_TYPE_P (type)
9309 || POINTER_TYPE_P (type)
9310 || TREE_CODE (type) == NULLPTR_TYPE
9311 || TREE_CODE (type) == OFFSET_TYPE
9312 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
9313 return true;
9314
9315 /* We also accept structs of size 1, 2, 4, 8 that are not
9316 passed in floating-point registers. */
9317 if (AGGREGATE_TYPE_P (type)
9318 && exact_log2 (size) >= 0
9319 && !s390_function_arg_float (mode, type))
9320 return true;
9321
9322 return false;
9323 }
9324
9325 /* Return 1 if a function argument of type TYPE and mode MODE
9326 is to be passed by reference. The ABI specifies that only
9327 structures of size 1, 2, 4, or 8 bytes are passed by value,
9328 all other structures (and complex numbers) are passed by
9329 reference. */
9330
9331 static bool
9332 s390_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED,
9333 machine_mode mode, const_tree type,
9334 bool named ATTRIBUTE_UNUSED)
9335 {
9336 int size = s390_function_arg_size (mode, type);
9337 if (size > 8)
9338 return true;
9339
9340 if (type)
9341 {
9342 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
9343 return 1;
9344
9345 if (TREE_CODE (type) == COMPLEX_TYPE
9346 || TREE_CODE (type) == VECTOR_TYPE)
9347 return 1;
9348 }
9349
9350 return 0;
9351 }
9352
9353 /* Update the data in CUM to advance over an argument of mode MODE and
9354 data type TYPE. (TYPE is null for libcalls where that information
9355 may not be available.). The boolean NAMED specifies whether the
9356 argument is a named argument (as opposed to an unnamed argument
9357 matching an ellipsis). */
9358
9359 static void
9360 s390_function_arg_advance (cumulative_args_t cum_v, machine_mode mode,
9361 const_tree type, bool named ATTRIBUTE_UNUSED)
9362 {
9363 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
9364
9365 if (s390_function_arg_float (mode, type))
9366 {
9367 cum->fprs += 1;
9368 }
9369 else if (s390_function_arg_integer (mode, type))
9370 {
9371 int size = s390_function_arg_size (mode, type);
9372 cum->gprs += ((size + UNITS_PER_LONG - 1) / UNITS_PER_LONG);
9373 }
9374 else
9375 gcc_unreachable ();
9376 }
9377
9378 /* Define where to put the arguments to a function.
9379 Value is zero to push the argument on the stack,
9380 or a hard register in which to store the argument.
9381
9382 MODE is the argument's machine mode.
9383 TYPE is the data type of the argument (as a tree).
9384 This is null for libcalls where that information may
9385 not be available.
9386 CUM is a variable of type CUMULATIVE_ARGS which gives info about
9387 the preceding args and about the function being called.
9388 NAMED is nonzero if this argument is a named parameter
9389 (otherwise it is an extra parameter matching an ellipsis).
9390
9391 On S/390, we use general purpose registers 2 through 6 to
9392 pass integer, pointer, and certain structure arguments, and
9393 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
9394 to pass floating point arguments. All remaining arguments
9395 are pushed to the stack. */
9396
9397 static rtx
9398 s390_function_arg (cumulative_args_t cum_v, machine_mode mode,
9399 const_tree type, bool named ATTRIBUTE_UNUSED)
9400 {
9401 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
9402
9403 if (s390_function_arg_float (mode, type))
9404 {
9405 if (cum->fprs + 1 > FP_ARG_NUM_REG)
9406 return 0;
9407 else
9408 return gen_rtx_REG (mode, cum->fprs + 16);
9409 }
9410 else if (s390_function_arg_integer (mode, type))
9411 {
9412 int size = s390_function_arg_size (mode, type);
9413 int n_gprs = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
9414
9415 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
9416 return 0;
9417 else if (n_gprs == 1 || UNITS_PER_WORD == UNITS_PER_LONG)
9418 return gen_rtx_REG (mode, cum->gprs + 2);
9419 else if (n_gprs == 2)
9420 {
9421 rtvec p = rtvec_alloc (2);
9422
9423 RTVEC_ELT (p, 0)
9424 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 2),
9425 const0_rtx);
9426 RTVEC_ELT (p, 1)
9427 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 3),
9428 GEN_INT (4));
9429
9430 return gen_rtx_PARALLEL (mode, p);
9431 }
9432 }
9433
9434 /* After the real arguments, expand_call calls us once again
9435 with a void_type_node type. Whatever we return here is
9436 passed as operand 2 to the call expanders.
9437
9438 We don't need this feature ... */
9439 else if (type == void_type_node)
9440 return const0_rtx;
9441
9442 gcc_unreachable ();
9443 }
9444
9445 /* Return true if return values of type TYPE should be returned
9446 in a memory buffer whose address is passed by the caller as
9447 hidden first argument. */
9448
9449 static bool
9450 s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED)
9451 {
9452 /* We accept small integral (and similar) types. */
9453 if (INTEGRAL_TYPE_P (type)
9454 || POINTER_TYPE_P (type)
9455 || TREE_CODE (type) == OFFSET_TYPE
9456 || TREE_CODE (type) == REAL_TYPE)
9457 return int_size_in_bytes (type) > 8;
9458
9459 /* Aggregates and similar constructs are always returned
9460 in memory. */
9461 if (AGGREGATE_TYPE_P (type)
9462 || TREE_CODE (type) == COMPLEX_TYPE
9463 || TREE_CODE (type) == VECTOR_TYPE)
9464 return true;
9465
9466 /* ??? We get called on all sorts of random stuff from
9467 aggregate_value_p. We can't abort, but it's not clear
9468 what's safe to return. Pretend it's a struct I guess. */
9469 return true;
9470 }
9471
9472 /* Function arguments and return values are promoted to word size. */
9473
9474 static machine_mode
9475 s390_promote_function_mode (const_tree type, machine_mode mode,
9476 int *punsignedp,
9477 const_tree fntype ATTRIBUTE_UNUSED,
9478 int for_return ATTRIBUTE_UNUSED)
9479 {
9480 if (INTEGRAL_MODE_P (mode)
9481 && GET_MODE_SIZE (mode) < UNITS_PER_LONG)
9482 {
9483 if (type != NULL_TREE && POINTER_TYPE_P (type))
9484 *punsignedp = POINTERS_EXTEND_UNSIGNED;
9485 return Pmode;
9486 }
9487
9488 return mode;
9489 }
9490
9491 /* Define where to return a (scalar) value of type RET_TYPE.
9492 If RET_TYPE is null, define where to return a (scalar)
9493 value of mode MODE from a libcall. */
9494
9495 static rtx
9496 s390_function_and_libcall_value (machine_mode mode,
9497 const_tree ret_type,
9498 const_tree fntype_or_decl,
9499 bool outgoing ATTRIBUTE_UNUSED)
9500 {
9501 /* For normal functions perform the promotion as
9502 promote_function_mode would do. */
9503 if (ret_type)
9504 {
9505 int unsignedp = TYPE_UNSIGNED (ret_type);
9506 mode = promote_function_mode (ret_type, mode, &unsignedp,
9507 fntype_or_decl, 1);
9508 }
9509
9510 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode));
9511 gcc_assert (GET_MODE_SIZE (mode) <= 8);
9512
9513 if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
9514 return gen_rtx_REG (mode, 16);
9515 else if (GET_MODE_SIZE (mode) <= UNITS_PER_LONG
9516 || UNITS_PER_LONG == UNITS_PER_WORD)
9517 return gen_rtx_REG (mode, 2);
9518 else if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_LONG)
9519 {
9520 /* This case is triggered when returning a 64 bit value with
9521 -m31 -mzarch. Although the value would fit into a single
9522 register it has to be forced into a 32 bit register pair in
9523 order to match the ABI. */
9524 rtvec p = rtvec_alloc (2);
9525
9526 RTVEC_ELT (p, 0)
9527 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 2), const0_rtx);
9528 RTVEC_ELT (p, 1)
9529 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 3), GEN_INT (4));
9530
9531 return gen_rtx_PARALLEL (mode, p);
9532 }
9533
9534 gcc_unreachable ();
9535 }
9536
9537 /* Define where to return a scalar return value of type RET_TYPE. */
9538
9539 static rtx
9540 s390_function_value (const_tree ret_type, const_tree fn_decl_or_type,
9541 bool outgoing)
9542 {
9543 return s390_function_and_libcall_value (TYPE_MODE (ret_type), ret_type,
9544 fn_decl_or_type, outgoing);
9545 }
9546
9547 /* Define where to return a scalar libcall return value of mode
9548 MODE. */
9549
9550 static rtx
9551 s390_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
9552 {
9553 return s390_function_and_libcall_value (mode, NULL_TREE,
9554 NULL_TREE, true);
9555 }
9556
9557
9558 /* Create and return the va_list datatype.
9559
9560 On S/390, va_list is an array type equivalent to
9561
9562 typedef struct __va_list_tag
9563 {
9564 long __gpr;
9565 long __fpr;
9566 void *__overflow_arg_area;
9567 void *__reg_save_area;
9568 } va_list[1];
9569
9570 where __gpr and __fpr hold the number of general purpose
9571 or floating point arguments used up to now, respectively,
9572 __overflow_arg_area points to the stack location of the
9573 next argument passed on the stack, and __reg_save_area
9574 always points to the start of the register area in the
9575 call frame of the current function. The function prologue
9576 saves all registers used for argument passing into this
9577 area if the function uses variable arguments. */
9578
9579 static tree
9580 s390_build_builtin_va_list (void)
9581 {
9582 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
9583
9584 record = lang_hooks.types.make_type (RECORD_TYPE);
9585
9586 type_decl =
9587 build_decl (BUILTINS_LOCATION,
9588 TYPE_DECL, get_identifier ("__va_list_tag"), record);
9589
9590 f_gpr = build_decl (BUILTINS_LOCATION,
9591 FIELD_DECL, get_identifier ("__gpr"),
9592 long_integer_type_node);
9593 f_fpr = build_decl (BUILTINS_LOCATION,
9594 FIELD_DECL, get_identifier ("__fpr"),
9595 long_integer_type_node);
9596 f_ovf = build_decl (BUILTINS_LOCATION,
9597 FIELD_DECL, get_identifier ("__overflow_arg_area"),
9598 ptr_type_node);
9599 f_sav = build_decl (BUILTINS_LOCATION,
9600 FIELD_DECL, get_identifier ("__reg_save_area"),
9601 ptr_type_node);
9602
9603 va_list_gpr_counter_field = f_gpr;
9604 va_list_fpr_counter_field = f_fpr;
9605
9606 DECL_FIELD_CONTEXT (f_gpr) = record;
9607 DECL_FIELD_CONTEXT (f_fpr) = record;
9608 DECL_FIELD_CONTEXT (f_ovf) = record;
9609 DECL_FIELD_CONTEXT (f_sav) = record;
9610
9611 TYPE_STUB_DECL (record) = type_decl;
9612 TYPE_NAME (record) = type_decl;
9613 TYPE_FIELDS (record) = f_gpr;
9614 DECL_CHAIN (f_gpr) = f_fpr;
9615 DECL_CHAIN (f_fpr) = f_ovf;
9616 DECL_CHAIN (f_ovf) = f_sav;
9617
9618 layout_type (record);
9619
9620 /* The correct type is an array type of one element. */
9621 return build_array_type (record, build_index_type (size_zero_node));
9622 }
9623
9624 /* Implement va_start by filling the va_list structure VALIST.
9625 STDARG_P is always true, and ignored.
9626 NEXTARG points to the first anonymous stack argument.
9627
9628 The following global variables are used to initialize
9629 the va_list structure:
9630
9631 crtl->args.info:
9632 holds number of gprs and fprs used for named arguments.
9633 crtl->args.arg_offset_rtx:
9634 holds the offset of the first anonymous stack argument
9635 (relative to the virtual arg pointer). */
9636
9637 static void
9638 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
9639 {
9640 HOST_WIDE_INT n_gpr, n_fpr;
9641 int off;
9642 tree f_gpr, f_fpr, f_ovf, f_sav;
9643 tree gpr, fpr, ovf, sav, t;
9644
9645 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
9646 f_fpr = DECL_CHAIN (f_gpr);
9647 f_ovf = DECL_CHAIN (f_fpr);
9648 f_sav = DECL_CHAIN (f_ovf);
9649
9650 valist = build_simple_mem_ref (valist);
9651 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9652 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
9653 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
9654 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
9655
9656 /* Count number of gp and fp argument registers used. */
9657
9658 n_gpr = crtl->args.info.gprs;
9659 n_fpr = crtl->args.info.fprs;
9660
9661 if (cfun->va_list_gpr_size)
9662 {
9663 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
9664 build_int_cst (NULL_TREE, n_gpr));
9665 TREE_SIDE_EFFECTS (t) = 1;
9666 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9667 }
9668
9669 if (cfun->va_list_fpr_size)
9670 {
9671 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
9672 build_int_cst (NULL_TREE, n_fpr));
9673 TREE_SIDE_EFFECTS (t) = 1;
9674 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9675 }
9676
9677 /* Find the overflow area. */
9678 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
9679 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
9680 {
9681 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
9682
9683 off = INTVAL (crtl->args.arg_offset_rtx);
9684 off = off < 0 ? 0 : off;
9685 if (TARGET_DEBUG_ARG)
9686 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
9687 (int)n_gpr, (int)n_fpr, off);
9688
9689 t = fold_build_pointer_plus_hwi (t, off);
9690
9691 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
9692 TREE_SIDE_EFFECTS (t) = 1;
9693 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9694 }
9695
9696 /* Find the register save area. */
9697 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
9698 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
9699 {
9700 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
9701 t = fold_build_pointer_plus_hwi (t, -RETURN_REGNUM * UNITS_PER_LONG);
9702
9703 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
9704 TREE_SIDE_EFFECTS (t) = 1;
9705 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9706 }
9707 }
9708
9709 /* Implement va_arg by updating the va_list structure
9710 VALIST as required to retrieve an argument of type
9711 TYPE, and returning that argument.
9712
9713 Generates code equivalent to:
9714
9715 if (integral value) {
9716 if (size <= 4 && args.gpr < 5 ||
9717 size > 4 && args.gpr < 4 )
9718 ret = args.reg_save_area[args.gpr+8]
9719 else
9720 ret = *args.overflow_arg_area++;
9721 } else if (float value) {
9722 if (args.fgpr < 2)
9723 ret = args.reg_save_area[args.fpr+64]
9724 else
9725 ret = *args.overflow_arg_area++;
9726 } else if (aggregate value) {
9727 if (args.gpr < 5)
9728 ret = *args.reg_save_area[args.gpr]
9729 else
9730 ret = **args.overflow_arg_area++;
9731 } */
9732
9733 static tree
9734 s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
9735 gimple_seq *post_p ATTRIBUTE_UNUSED)
9736 {
9737 tree f_gpr, f_fpr, f_ovf, f_sav;
9738 tree gpr, fpr, ovf, sav, reg, t, u;
9739 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
9740 tree lab_false, lab_over, addr;
9741
9742 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
9743 f_fpr = DECL_CHAIN (f_gpr);
9744 f_ovf = DECL_CHAIN (f_fpr);
9745 f_sav = DECL_CHAIN (f_ovf);
9746
9747 valist = build_va_arg_indirect_ref (valist);
9748 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9749 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
9750 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
9751
9752 /* The tree for args* cannot be shared between gpr/fpr and ovf since
9753 both appear on a lhs. */
9754 valist = unshare_expr (valist);
9755 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
9756
9757 size = int_size_in_bytes (type);
9758
9759 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
9760 {
9761 if (TARGET_DEBUG_ARG)
9762 {
9763 fprintf (stderr, "va_arg: aggregate type");
9764 debug_tree (type);
9765 }
9766
9767 /* Aggregates are passed by reference. */
9768 indirect_p = 1;
9769 reg = gpr;
9770 n_reg = 1;
9771
9772 /* kernel stack layout on 31 bit: It is assumed here that no padding
9773 will be added by s390_frame_info because for va_args always an even
9774 number of gprs has to be saved r15-r2 = 14 regs. */
9775 sav_ofs = 2 * UNITS_PER_LONG;
9776 sav_scale = UNITS_PER_LONG;
9777 size = UNITS_PER_LONG;
9778 max_reg = GP_ARG_NUM_REG - n_reg;
9779 }
9780 else if (s390_function_arg_float (TYPE_MODE (type), type))
9781 {
9782 if (TARGET_DEBUG_ARG)
9783 {
9784 fprintf (stderr, "va_arg: float type");
9785 debug_tree (type);
9786 }
9787
9788 /* FP args go in FP registers, if present. */
9789 indirect_p = 0;
9790 reg = fpr;
9791 n_reg = 1;
9792 sav_ofs = 16 * UNITS_PER_LONG;
9793 sav_scale = 8;
9794 max_reg = FP_ARG_NUM_REG - n_reg;
9795 }
9796 else
9797 {
9798 if (TARGET_DEBUG_ARG)
9799 {
9800 fprintf (stderr, "va_arg: other type");
9801 debug_tree (type);
9802 }
9803
9804 /* Otherwise into GP registers. */
9805 indirect_p = 0;
9806 reg = gpr;
9807 n_reg = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
9808
9809 /* kernel stack layout on 31 bit: It is assumed here that no padding
9810 will be added by s390_frame_info because for va_args always an even
9811 number of gprs has to be saved r15-r2 = 14 regs. */
9812 sav_ofs = 2 * UNITS_PER_LONG;
9813
9814 if (size < UNITS_PER_LONG)
9815 sav_ofs += UNITS_PER_LONG - size;
9816
9817 sav_scale = UNITS_PER_LONG;
9818 max_reg = GP_ARG_NUM_REG - n_reg;
9819 }
9820
9821 /* Pull the value out of the saved registers ... */
9822
9823 lab_false = create_artificial_label (UNKNOWN_LOCATION);
9824 lab_over = create_artificial_label (UNKNOWN_LOCATION);
9825 addr = create_tmp_var (ptr_type_node, "addr");
9826
9827 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
9828 t = build2 (GT_EXPR, boolean_type_node, reg, t);
9829 u = build1 (GOTO_EXPR, void_type_node, lab_false);
9830 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
9831 gimplify_and_add (t, pre_p);
9832
9833 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
9834 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
9835 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
9836 t = fold_build_pointer_plus (t, u);
9837
9838 gimplify_assign (addr, t, pre_p);
9839
9840 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
9841
9842 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
9843
9844
9845 /* ... Otherwise out of the overflow area. */
9846
9847 t = ovf;
9848 if (size < UNITS_PER_LONG)
9849 t = fold_build_pointer_plus_hwi (t, UNITS_PER_LONG - size);
9850
9851 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
9852
9853 gimplify_assign (addr, t, pre_p);
9854
9855 t = fold_build_pointer_plus_hwi (t, size);
9856 gimplify_assign (ovf, t, pre_p);
9857
9858 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
9859
9860
9861 /* Increment register save count. */
9862
9863 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
9864 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
9865 gimplify_and_add (u, pre_p);
9866
9867 if (indirect_p)
9868 {
9869 t = build_pointer_type_for_mode (build_pointer_type (type),
9870 ptr_mode, true);
9871 addr = fold_convert (t, addr);
9872 addr = build_va_arg_indirect_ref (addr);
9873 }
9874 else
9875 {
9876 t = build_pointer_type_for_mode (type, ptr_mode, true);
9877 addr = fold_convert (t, addr);
9878 }
9879
9880 return build_va_arg_indirect_ref (addr);
9881 }
9882
9883 /* Emit rtl for the tbegin or tbegin_retry (RETRY != NULL_RTX)
9884 expanders.
9885 DEST - Register location where CC will be stored.
9886 TDB - Pointer to a 256 byte area where to store the transaction.
9887 diagnostic block. NULL if TDB is not needed.
9888 RETRY - Retry count value. If non-NULL a retry loop for CC2
9889 is emitted
9890 CLOBBER_FPRS_P - If true clobbers for all FPRs are emitted as part
9891 of the tbegin instruction pattern. */
9892
9893 void
9894 s390_expand_tbegin (rtx dest, rtx tdb, rtx retry, bool clobber_fprs_p)
9895 {
9896 rtx retry_plus_two = gen_reg_rtx (SImode);
9897 rtx retry_reg = gen_reg_rtx (SImode);
9898 rtx_code_label *retry_label = NULL;
9899
9900 if (retry != NULL_RTX)
9901 {
9902 emit_move_insn (retry_reg, retry);
9903 emit_insn (gen_addsi3 (retry_plus_two, retry_reg, const2_rtx));
9904 emit_insn (gen_addsi3 (retry_reg, retry_reg, const1_rtx));
9905 retry_label = gen_label_rtx ();
9906 emit_label (retry_label);
9907 }
9908
9909 if (clobber_fprs_p)
9910 emit_insn (gen_tbegin_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK), tdb));
9911 else
9912 emit_insn (gen_tbegin_nofloat_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK),
9913 tdb));
9914
9915 emit_move_insn (dest, gen_rtx_UNSPEC (SImode,
9916 gen_rtvec (1, gen_rtx_REG (CCRAWmode,
9917 CC_REGNUM)),
9918 UNSPEC_CC_TO_INT));
9919 if (retry != NULL_RTX)
9920 {
9921 const int CC0 = 1 << 3;
9922 const int CC1 = 1 << 2;
9923 const int CC3 = 1 << 0;
9924 rtx jump;
9925 rtx count = gen_reg_rtx (SImode);
9926 rtx_code_label *leave_label = gen_label_rtx ();
9927
9928 /* Exit for success and permanent failures. */
9929 jump = s390_emit_jump (leave_label,
9930 gen_rtx_EQ (VOIDmode,
9931 gen_rtx_REG (CCRAWmode, CC_REGNUM),
9932 gen_rtx_CONST_INT (VOIDmode, CC0 | CC1 | CC3)));
9933 LABEL_NUSES (leave_label) = 1;
9934
9935 /* CC2 - transient failure. Perform retry with ppa. */
9936 emit_move_insn (count, retry_plus_two);
9937 emit_insn (gen_subsi3 (count, count, retry_reg));
9938 emit_insn (gen_tx_assist (count));
9939 jump = emit_jump_insn (gen_doloop_si64 (retry_label,
9940 retry_reg,
9941 retry_reg));
9942 JUMP_LABEL (jump) = retry_label;
9943 LABEL_NUSES (retry_label) = 1;
9944 emit_label (leave_label);
9945 }
9946 }
9947
9948 /* Builtins. */
9949
9950 enum s390_builtin
9951 {
9952 S390_BUILTIN_TBEGIN,
9953 S390_BUILTIN_TBEGIN_NOFLOAT,
9954 S390_BUILTIN_TBEGIN_RETRY,
9955 S390_BUILTIN_TBEGIN_RETRY_NOFLOAT,
9956 S390_BUILTIN_TBEGINC,
9957 S390_BUILTIN_TEND,
9958 S390_BUILTIN_TABORT,
9959 S390_BUILTIN_NON_TX_STORE,
9960 S390_BUILTIN_TX_NESTING_DEPTH,
9961 S390_BUILTIN_TX_ASSIST,
9962
9963 S390_BUILTIN_max
9964 };
9965
9966 static enum insn_code const code_for_builtin[S390_BUILTIN_max] = {
9967 CODE_FOR_tbegin,
9968 CODE_FOR_tbegin_nofloat,
9969 CODE_FOR_tbegin_retry,
9970 CODE_FOR_tbegin_retry_nofloat,
9971 CODE_FOR_tbeginc,
9972 CODE_FOR_tend,
9973 CODE_FOR_tabort,
9974 CODE_FOR_ntstg,
9975 CODE_FOR_etnd,
9976 CODE_FOR_tx_assist
9977 };
9978
9979 static void
9980 s390_init_builtins (void)
9981 {
9982 tree ftype, uint64_type;
9983 tree returns_twice_attr = tree_cons (get_identifier ("returns_twice"),
9984 NULL, NULL);
9985 tree noreturn_attr = tree_cons (get_identifier ("noreturn"), NULL, NULL);
9986
9987 /* void foo (void) */
9988 ftype = build_function_type_list (void_type_node, NULL_TREE);
9989 add_builtin_function ("__builtin_tbeginc", ftype, S390_BUILTIN_TBEGINC,
9990 BUILT_IN_MD, NULL, NULL_TREE);
9991
9992 /* void foo (int) */
9993 ftype = build_function_type_list (void_type_node, integer_type_node,
9994 NULL_TREE);
9995 add_builtin_function ("__builtin_tabort", ftype,
9996 S390_BUILTIN_TABORT, BUILT_IN_MD, NULL, noreturn_attr);
9997 add_builtin_function ("__builtin_tx_assist", ftype,
9998 S390_BUILTIN_TX_ASSIST, BUILT_IN_MD, NULL, NULL_TREE);
9999
10000 /* int foo (void *) */
10001 ftype = build_function_type_list (integer_type_node, ptr_type_node, NULL_TREE);
10002 add_builtin_function ("__builtin_tbegin", ftype, S390_BUILTIN_TBEGIN,
10003 BUILT_IN_MD, NULL, returns_twice_attr);
10004 add_builtin_function ("__builtin_tbegin_nofloat", ftype,
10005 S390_BUILTIN_TBEGIN_NOFLOAT,
10006 BUILT_IN_MD, NULL, returns_twice_attr);
10007
10008 /* int foo (void *, int) */
10009 ftype = build_function_type_list (integer_type_node, ptr_type_node,
10010 integer_type_node, NULL_TREE);
10011 add_builtin_function ("__builtin_tbegin_retry", ftype,
10012 S390_BUILTIN_TBEGIN_RETRY,
10013 BUILT_IN_MD,
10014 NULL, returns_twice_attr);
10015 add_builtin_function ("__builtin_tbegin_retry_nofloat", ftype,
10016 S390_BUILTIN_TBEGIN_RETRY_NOFLOAT,
10017 BUILT_IN_MD,
10018 NULL, returns_twice_attr);
10019
10020 /* int foo (void) */
10021 ftype = build_function_type_list (integer_type_node, NULL_TREE);
10022 add_builtin_function ("__builtin_tx_nesting_depth", ftype,
10023 S390_BUILTIN_TX_NESTING_DEPTH,
10024 BUILT_IN_MD, NULL, NULL_TREE);
10025 add_builtin_function ("__builtin_tend", ftype,
10026 S390_BUILTIN_TEND, BUILT_IN_MD, NULL, NULL_TREE);
10027
10028 /* void foo (uint64_t *, uint64_t) */
10029 if (TARGET_64BIT)
10030 uint64_type = long_unsigned_type_node;
10031 else
10032 uint64_type = long_long_unsigned_type_node;
10033
10034 ftype = build_function_type_list (void_type_node,
10035 build_pointer_type (uint64_type),
10036 uint64_type, NULL_TREE);
10037 add_builtin_function ("__builtin_non_tx_store", ftype,
10038 S390_BUILTIN_NON_TX_STORE,
10039 BUILT_IN_MD, NULL, NULL_TREE);
10040 }
10041
10042 /* Expand an expression EXP that calls a built-in function,
10043 with result going to TARGET if that's convenient
10044 (and in mode MODE if that's convenient).
10045 SUBTARGET may be used as the target for computing one of EXP's operands.
10046 IGNORE is nonzero if the value is to be ignored. */
10047
10048 static rtx
10049 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10050 machine_mode mode ATTRIBUTE_UNUSED,
10051 int ignore ATTRIBUTE_UNUSED)
10052 {
10053 #define MAX_ARGS 2
10054
10055 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10056 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10057 enum insn_code icode;
10058 rtx op[MAX_ARGS], pat;
10059 int arity;
10060 bool nonvoid;
10061 tree arg;
10062 call_expr_arg_iterator iter;
10063
10064 if (fcode >= S390_BUILTIN_max)
10065 internal_error ("bad builtin fcode");
10066 icode = code_for_builtin[fcode];
10067 if (icode == 0)
10068 internal_error ("bad builtin fcode");
10069
10070 if (!TARGET_HTM)
10071 error ("Transactional execution builtins not enabled (-mhtm)\n");
10072
10073 /* Set a flag in the machine specific cfun part in order to support
10074 saving/restoring of FPRs. */
10075 if (fcode == S390_BUILTIN_TBEGIN || fcode == S390_BUILTIN_TBEGIN_RETRY)
10076 cfun->machine->tbegin_p = true;
10077
10078 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
10079
10080 arity = 0;
10081 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
10082 {
10083 const struct insn_operand_data *insn_op;
10084
10085 if (arg == error_mark_node)
10086 return NULL_RTX;
10087 if (arity >= MAX_ARGS)
10088 return NULL_RTX;
10089
10090 insn_op = &insn_data[icode].operand[arity + nonvoid];
10091
10092 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL);
10093
10094 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
10095 {
10096 if (insn_op->predicate == memory_operand)
10097 {
10098 /* Don't move a NULL pointer into a register. Otherwise
10099 we have to rely on combine being able to move it back
10100 in order to get an immediate 0 in the instruction. */
10101 if (op[arity] != const0_rtx)
10102 op[arity] = copy_to_mode_reg (Pmode, op[arity]);
10103 op[arity] = gen_rtx_MEM (insn_op->mode, op[arity]);
10104 }
10105 else
10106 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
10107 }
10108
10109 arity++;
10110 }
10111
10112 if (nonvoid)
10113 {
10114 machine_mode tmode = insn_data[icode].operand[0].mode;
10115 if (!target
10116 || GET_MODE (target) != tmode
10117 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
10118 target = gen_reg_rtx (tmode);
10119 }
10120
10121 switch (arity)
10122 {
10123 case 0:
10124 pat = GEN_FCN (icode) (target);
10125 break;
10126 case 1:
10127 if (nonvoid)
10128 pat = GEN_FCN (icode) (target, op[0]);
10129 else
10130 pat = GEN_FCN (icode) (op[0]);
10131 break;
10132 case 2:
10133 if (nonvoid)
10134 pat = GEN_FCN (icode) (target, op[0], op[1]);
10135 else
10136 pat = GEN_FCN (icode) (op[0], op[1]);
10137 break;
10138 default:
10139 gcc_unreachable ();
10140 }
10141 if (!pat)
10142 return NULL_RTX;
10143 emit_insn (pat);
10144
10145 if (nonvoid)
10146 return target;
10147 else
10148 return const0_rtx;
10149 }
10150
10151 /* We call mcount before the function prologue. So a profiled leaf
10152 function should stay a leaf function. */
10153
10154 static bool
10155 s390_keep_leaf_when_profiled ()
10156 {
10157 return true;
10158 }
10159
10160 /* Output assembly code for the trampoline template to
10161 stdio stream FILE.
10162
10163 On S/390, we use gpr 1 internally in the trampoline code;
10164 gpr 0 is used to hold the static chain. */
10165
10166 static void
10167 s390_asm_trampoline_template (FILE *file)
10168 {
10169 rtx op[2];
10170 op[0] = gen_rtx_REG (Pmode, 0);
10171 op[1] = gen_rtx_REG (Pmode, 1);
10172
10173 if (TARGET_64BIT)
10174 {
10175 output_asm_insn ("basr\t%1,0", op); /* 2 byte */
10176 output_asm_insn ("lmg\t%0,%1,14(%1)", op); /* 6 byte */
10177 output_asm_insn ("br\t%1", op); /* 2 byte */
10178 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
10179 }
10180 else
10181 {
10182 output_asm_insn ("basr\t%1,0", op); /* 2 byte */
10183 output_asm_insn ("lm\t%0,%1,6(%1)", op); /* 4 byte */
10184 output_asm_insn ("br\t%1", op); /* 2 byte */
10185 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
10186 }
10187 }
10188
10189 /* Emit RTL insns to initialize the variable parts of a trampoline.
10190 FNADDR is an RTX for the address of the function's pure code.
10191 CXT is an RTX for the static chain value for the function. */
10192
10193 static void
10194 s390_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
10195 {
10196 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
10197 rtx mem;
10198
10199 emit_block_move (m_tramp, assemble_trampoline_template (),
10200 GEN_INT (2 * UNITS_PER_LONG), BLOCK_OP_NORMAL);
10201
10202 mem = adjust_address (m_tramp, Pmode, 2 * UNITS_PER_LONG);
10203 emit_move_insn (mem, cxt);
10204 mem = adjust_address (m_tramp, Pmode, 3 * UNITS_PER_LONG);
10205 emit_move_insn (mem, fnaddr);
10206 }
10207
10208 /* Output assembler code to FILE to increment profiler label # LABELNO
10209 for profiling a function entry. */
10210
10211 void
10212 s390_function_profiler (FILE *file, int labelno)
10213 {
10214 rtx op[7];
10215
10216 char label[128];
10217 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
10218
10219 fprintf (file, "# function profiler \n");
10220
10221 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
10222 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
10223 op[1] = gen_rtx_MEM (Pmode, plus_constant (Pmode, op[1], UNITS_PER_LONG));
10224
10225 op[2] = gen_rtx_REG (Pmode, 1);
10226 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
10227 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
10228
10229 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
10230 if (flag_pic)
10231 {
10232 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
10233 op[4] = gen_rtx_CONST (Pmode, op[4]);
10234 }
10235
10236 if (TARGET_64BIT)
10237 {
10238 output_asm_insn ("stg\t%0,%1", op);
10239 output_asm_insn ("larl\t%2,%3", op);
10240 output_asm_insn ("brasl\t%0,%4", op);
10241 output_asm_insn ("lg\t%0,%1", op);
10242 }
10243 else if (!flag_pic)
10244 {
10245 op[6] = gen_label_rtx ();
10246
10247 output_asm_insn ("st\t%0,%1", op);
10248 output_asm_insn ("bras\t%2,%l6", op);
10249 output_asm_insn (".long\t%4", op);
10250 output_asm_insn (".long\t%3", op);
10251 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
10252 output_asm_insn ("l\t%0,0(%2)", op);
10253 output_asm_insn ("l\t%2,4(%2)", op);
10254 output_asm_insn ("basr\t%0,%0", op);
10255 output_asm_insn ("l\t%0,%1", op);
10256 }
10257 else
10258 {
10259 op[5] = gen_label_rtx ();
10260 op[6] = gen_label_rtx ();
10261
10262 output_asm_insn ("st\t%0,%1", op);
10263 output_asm_insn ("bras\t%2,%l6", op);
10264 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
10265 output_asm_insn (".long\t%4-%l5", op);
10266 output_asm_insn (".long\t%3-%l5", op);
10267 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
10268 output_asm_insn ("lr\t%0,%2", op);
10269 output_asm_insn ("a\t%0,0(%2)", op);
10270 output_asm_insn ("a\t%2,4(%2)", op);
10271 output_asm_insn ("basr\t%0,%0", op);
10272 output_asm_insn ("l\t%0,%1", op);
10273 }
10274 }
10275
10276 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
10277 into its SYMBOL_REF_FLAGS. */
10278
10279 static void
10280 s390_encode_section_info (tree decl, rtx rtl, int first)
10281 {
10282 default_encode_section_info (decl, rtl, first);
10283
10284 if (TREE_CODE (decl) == VAR_DECL)
10285 {
10286 /* If a variable has a forced alignment to < 2 bytes, mark it
10287 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
10288 operand. */
10289 if (DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
10290 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
10291 if (!DECL_SIZE (decl)
10292 || !DECL_ALIGN (decl)
10293 || !tree_fits_shwi_p (DECL_SIZE (decl))
10294 || (DECL_ALIGN (decl) <= 64
10295 && DECL_ALIGN (decl) != tree_to_shwi (DECL_SIZE (decl))))
10296 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
10297 }
10298
10299 /* Literal pool references don't have a decl so they are handled
10300 differently here. We rely on the information in the MEM_ALIGN
10301 entry to decide upon natural alignment. */
10302 if (MEM_P (rtl)
10303 && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
10304 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0))
10305 && (MEM_ALIGN (rtl) == 0
10306 || GET_MODE_BITSIZE (GET_MODE (rtl)) == 0
10307 || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl))))
10308 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
10309 }
10310
10311 /* Output thunk to FILE that implements a C++ virtual function call (with
10312 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
10313 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
10314 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
10315 relative to the resulting this pointer. */
10316
10317 static void
10318 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
10319 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
10320 tree function)
10321 {
10322 rtx op[10];
10323 int nonlocal = 0;
10324
10325 /* Make sure unwind info is emitted for the thunk if needed. */
10326 final_start_function (emit_barrier (), file, 1);
10327
10328 /* Operand 0 is the target function. */
10329 op[0] = XEXP (DECL_RTL (function), 0);
10330 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
10331 {
10332 nonlocal = 1;
10333 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
10334 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
10335 op[0] = gen_rtx_CONST (Pmode, op[0]);
10336 }
10337
10338 /* Operand 1 is the 'this' pointer. */
10339 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
10340 op[1] = gen_rtx_REG (Pmode, 3);
10341 else
10342 op[1] = gen_rtx_REG (Pmode, 2);
10343
10344 /* Operand 2 is the delta. */
10345 op[2] = GEN_INT (delta);
10346
10347 /* Operand 3 is the vcall_offset. */
10348 op[3] = GEN_INT (vcall_offset);
10349
10350 /* Operand 4 is the temporary register. */
10351 op[4] = gen_rtx_REG (Pmode, 1);
10352
10353 /* Operands 5 to 8 can be used as labels. */
10354 op[5] = NULL_RTX;
10355 op[6] = NULL_RTX;
10356 op[7] = NULL_RTX;
10357 op[8] = NULL_RTX;
10358
10359 /* Operand 9 can be used for temporary register. */
10360 op[9] = NULL_RTX;
10361
10362 /* Generate code. */
10363 if (TARGET_64BIT)
10364 {
10365 /* Setup literal pool pointer if required. */
10366 if ((!DISP_IN_RANGE (delta)
10367 && !CONST_OK_FOR_K (delta)
10368 && !CONST_OK_FOR_Os (delta))
10369 || (!DISP_IN_RANGE (vcall_offset)
10370 && !CONST_OK_FOR_K (vcall_offset)
10371 && !CONST_OK_FOR_Os (vcall_offset)))
10372 {
10373 op[5] = gen_label_rtx ();
10374 output_asm_insn ("larl\t%4,%5", op);
10375 }
10376
10377 /* Add DELTA to this pointer. */
10378 if (delta)
10379 {
10380 if (CONST_OK_FOR_J (delta))
10381 output_asm_insn ("la\t%1,%2(%1)", op);
10382 else if (DISP_IN_RANGE (delta))
10383 output_asm_insn ("lay\t%1,%2(%1)", op);
10384 else if (CONST_OK_FOR_K (delta))
10385 output_asm_insn ("aghi\t%1,%2", op);
10386 else if (CONST_OK_FOR_Os (delta))
10387 output_asm_insn ("agfi\t%1,%2", op);
10388 else
10389 {
10390 op[6] = gen_label_rtx ();
10391 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
10392 }
10393 }
10394
10395 /* Perform vcall adjustment. */
10396 if (vcall_offset)
10397 {
10398 if (DISP_IN_RANGE (vcall_offset))
10399 {
10400 output_asm_insn ("lg\t%4,0(%1)", op);
10401 output_asm_insn ("ag\t%1,%3(%4)", op);
10402 }
10403 else if (CONST_OK_FOR_K (vcall_offset))
10404 {
10405 output_asm_insn ("lghi\t%4,%3", op);
10406 output_asm_insn ("ag\t%4,0(%1)", op);
10407 output_asm_insn ("ag\t%1,0(%4)", op);
10408 }
10409 else if (CONST_OK_FOR_Os (vcall_offset))
10410 {
10411 output_asm_insn ("lgfi\t%4,%3", op);
10412 output_asm_insn ("ag\t%4,0(%1)", op);
10413 output_asm_insn ("ag\t%1,0(%4)", op);
10414 }
10415 else
10416 {
10417 op[7] = gen_label_rtx ();
10418 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
10419 output_asm_insn ("ag\t%4,0(%1)", op);
10420 output_asm_insn ("ag\t%1,0(%4)", op);
10421 }
10422 }
10423
10424 /* Jump to target. */
10425 output_asm_insn ("jg\t%0", op);
10426
10427 /* Output literal pool if required. */
10428 if (op[5])
10429 {
10430 output_asm_insn (".align\t4", op);
10431 targetm.asm_out.internal_label (file, "L",
10432 CODE_LABEL_NUMBER (op[5]));
10433 }
10434 if (op[6])
10435 {
10436 targetm.asm_out.internal_label (file, "L",
10437 CODE_LABEL_NUMBER (op[6]));
10438 output_asm_insn (".long\t%2", op);
10439 }
10440 if (op[7])
10441 {
10442 targetm.asm_out.internal_label (file, "L",
10443 CODE_LABEL_NUMBER (op[7]));
10444 output_asm_insn (".long\t%3", op);
10445 }
10446 }
10447 else
10448 {
10449 /* Setup base pointer if required. */
10450 if (!vcall_offset
10451 || (!DISP_IN_RANGE (delta)
10452 && !CONST_OK_FOR_K (delta)
10453 && !CONST_OK_FOR_Os (delta))
10454 || (!DISP_IN_RANGE (delta)
10455 && !CONST_OK_FOR_K (vcall_offset)
10456 && !CONST_OK_FOR_Os (vcall_offset)))
10457 {
10458 op[5] = gen_label_rtx ();
10459 output_asm_insn ("basr\t%4,0", op);
10460 targetm.asm_out.internal_label (file, "L",
10461 CODE_LABEL_NUMBER (op[5]));
10462 }
10463
10464 /* Add DELTA to this pointer. */
10465 if (delta)
10466 {
10467 if (CONST_OK_FOR_J (delta))
10468 output_asm_insn ("la\t%1,%2(%1)", op);
10469 else if (DISP_IN_RANGE (delta))
10470 output_asm_insn ("lay\t%1,%2(%1)", op);
10471 else if (CONST_OK_FOR_K (delta))
10472 output_asm_insn ("ahi\t%1,%2", op);
10473 else if (CONST_OK_FOR_Os (delta))
10474 output_asm_insn ("afi\t%1,%2", op);
10475 else
10476 {
10477 op[6] = gen_label_rtx ();
10478 output_asm_insn ("a\t%1,%6-%5(%4)", op);
10479 }
10480 }
10481
10482 /* Perform vcall adjustment. */
10483 if (vcall_offset)
10484 {
10485 if (CONST_OK_FOR_J (vcall_offset))
10486 {
10487 output_asm_insn ("l\t%4,0(%1)", op);
10488 output_asm_insn ("a\t%1,%3(%4)", op);
10489 }
10490 else if (DISP_IN_RANGE (vcall_offset))
10491 {
10492 output_asm_insn ("l\t%4,0(%1)", op);
10493 output_asm_insn ("ay\t%1,%3(%4)", op);
10494 }
10495 else if (CONST_OK_FOR_K (vcall_offset))
10496 {
10497 output_asm_insn ("lhi\t%4,%3", op);
10498 output_asm_insn ("a\t%4,0(%1)", op);
10499 output_asm_insn ("a\t%1,0(%4)", op);
10500 }
10501 else if (CONST_OK_FOR_Os (vcall_offset))
10502 {
10503 output_asm_insn ("iilf\t%4,%3", op);
10504 output_asm_insn ("a\t%4,0(%1)", op);
10505 output_asm_insn ("a\t%1,0(%4)", op);
10506 }
10507 else
10508 {
10509 op[7] = gen_label_rtx ();
10510 output_asm_insn ("l\t%4,%7-%5(%4)", op);
10511 output_asm_insn ("a\t%4,0(%1)", op);
10512 output_asm_insn ("a\t%1,0(%4)", op);
10513 }
10514
10515 /* We had to clobber the base pointer register.
10516 Re-setup the base pointer (with a different base). */
10517 op[5] = gen_label_rtx ();
10518 output_asm_insn ("basr\t%4,0", op);
10519 targetm.asm_out.internal_label (file, "L",
10520 CODE_LABEL_NUMBER (op[5]));
10521 }
10522
10523 /* Jump to target. */
10524 op[8] = gen_label_rtx ();
10525
10526 if (!flag_pic)
10527 output_asm_insn ("l\t%4,%8-%5(%4)", op);
10528 else if (!nonlocal)
10529 output_asm_insn ("a\t%4,%8-%5(%4)", op);
10530 /* We cannot call through .plt, since .plt requires %r12 loaded. */
10531 else if (flag_pic == 1)
10532 {
10533 output_asm_insn ("a\t%4,%8-%5(%4)", op);
10534 output_asm_insn ("l\t%4,%0(%4)", op);
10535 }
10536 else if (flag_pic == 2)
10537 {
10538 op[9] = gen_rtx_REG (Pmode, 0);
10539 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
10540 output_asm_insn ("a\t%4,%8-%5(%4)", op);
10541 output_asm_insn ("ar\t%4,%9", op);
10542 output_asm_insn ("l\t%4,0(%4)", op);
10543 }
10544
10545 output_asm_insn ("br\t%4", op);
10546
10547 /* Output literal pool. */
10548 output_asm_insn (".align\t4", op);
10549
10550 if (nonlocal && flag_pic == 2)
10551 output_asm_insn (".long\t%0", op);
10552 if (nonlocal)
10553 {
10554 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
10555 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
10556 }
10557
10558 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
10559 if (!flag_pic)
10560 output_asm_insn (".long\t%0", op);
10561 else
10562 output_asm_insn (".long\t%0-%5", op);
10563
10564 if (op[6])
10565 {
10566 targetm.asm_out.internal_label (file, "L",
10567 CODE_LABEL_NUMBER (op[6]));
10568 output_asm_insn (".long\t%2", op);
10569 }
10570 if (op[7])
10571 {
10572 targetm.asm_out.internal_label (file, "L",
10573 CODE_LABEL_NUMBER (op[7]));
10574 output_asm_insn (".long\t%3", op);
10575 }
10576 }
10577 final_end_function ();
10578 }
10579
10580 static bool
10581 s390_valid_pointer_mode (machine_mode mode)
10582 {
10583 return (mode == SImode || (TARGET_64BIT && mode == DImode));
10584 }
10585
10586 /* Checks whether the given CALL_EXPR would use a caller
10587 saved register. This is used to decide whether sibling call
10588 optimization could be performed on the respective function
10589 call. */
10590
10591 static bool
10592 s390_call_saved_register_used (tree call_expr)
10593 {
10594 CUMULATIVE_ARGS cum_v;
10595 cumulative_args_t cum;
10596 tree parameter;
10597 machine_mode mode;
10598 tree type;
10599 rtx parm_rtx;
10600 int reg, i;
10601
10602 INIT_CUMULATIVE_ARGS (cum_v, NULL, NULL, 0, 0);
10603 cum = pack_cumulative_args (&cum_v);
10604
10605 for (i = 0; i < call_expr_nargs (call_expr); i++)
10606 {
10607 parameter = CALL_EXPR_ARG (call_expr, i);
10608 gcc_assert (parameter);
10609
10610 /* For an undeclared variable passed as parameter we will get
10611 an ERROR_MARK node here. */
10612 if (TREE_CODE (parameter) == ERROR_MARK)
10613 return true;
10614
10615 type = TREE_TYPE (parameter);
10616 gcc_assert (type);
10617
10618 mode = TYPE_MODE (type);
10619 gcc_assert (mode);
10620
10621 if (pass_by_reference (&cum_v, mode, type, true))
10622 {
10623 mode = Pmode;
10624 type = build_pointer_type (type);
10625 }
10626
10627 parm_rtx = s390_function_arg (cum, mode, type, 0);
10628
10629 s390_function_arg_advance (cum, mode, type, 0);
10630
10631 if (!parm_rtx)
10632 continue;
10633
10634 if (REG_P (parm_rtx))
10635 {
10636 for (reg = 0;
10637 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
10638 reg++)
10639 if (!call_used_regs[reg + REGNO (parm_rtx)])
10640 return true;
10641 }
10642
10643 if (GET_CODE (parm_rtx) == PARALLEL)
10644 {
10645 int i;
10646
10647 for (i = 0; i < XVECLEN (parm_rtx, 0); i++)
10648 {
10649 rtx r = XEXP (XVECEXP (parm_rtx, 0, i), 0);
10650
10651 gcc_assert (REG_P (r));
10652
10653 for (reg = 0;
10654 reg < HARD_REGNO_NREGS (REGNO (r), GET_MODE (r));
10655 reg++)
10656 if (!call_used_regs[reg + REGNO (r)])
10657 return true;
10658 }
10659 }
10660
10661 }
10662 return false;
10663 }
10664
10665 /* Return true if the given call expression can be
10666 turned into a sibling call.
10667 DECL holds the declaration of the function to be called whereas
10668 EXP is the call expression itself. */
10669
10670 static bool
10671 s390_function_ok_for_sibcall (tree decl, tree exp)
10672 {
10673 /* The TPF epilogue uses register 1. */
10674 if (TARGET_TPF_PROFILING)
10675 return false;
10676
10677 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
10678 which would have to be restored before the sibcall. */
10679 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
10680 return false;
10681
10682 /* Register 6 on s390 is available as an argument register but unfortunately
10683 "caller saved". This makes functions needing this register for arguments
10684 not suitable for sibcalls. */
10685 return !s390_call_saved_register_used (exp);
10686 }
10687
10688 /* Return the fixed registers used for condition codes. */
10689
10690 static bool
10691 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
10692 {
10693 *p1 = CC_REGNUM;
10694 *p2 = INVALID_REGNUM;
10695
10696 return true;
10697 }
10698
10699 /* This function is used by the call expanders of the machine description.
10700 It emits the call insn itself together with the necessary operations
10701 to adjust the target address and returns the emitted insn.
10702 ADDR_LOCATION is the target address rtx
10703 TLS_CALL the location of the thread-local symbol
10704 RESULT_REG the register where the result of the call should be stored
10705 RETADDR_REG the register where the return address should be stored
10706 If this parameter is NULL_RTX the call is considered
10707 to be a sibling call. */
10708
10709 rtx_insn *
10710 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
10711 rtx retaddr_reg)
10712 {
10713 bool plt_call = false;
10714 rtx_insn *insn;
10715 rtx call;
10716 rtx clobber;
10717 rtvec vec;
10718
10719 /* Direct function calls need special treatment. */
10720 if (GET_CODE (addr_location) == SYMBOL_REF)
10721 {
10722 /* When calling a global routine in PIC mode, we must
10723 replace the symbol itself with the PLT stub. */
10724 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
10725 {
10726 if (retaddr_reg != NULL_RTX)
10727 {
10728 addr_location = gen_rtx_UNSPEC (Pmode,
10729 gen_rtvec (1, addr_location),
10730 UNSPEC_PLT);
10731 addr_location = gen_rtx_CONST (Pmode, addr_location);
10732 plt_call = true;
10733 }
10734 else
10735 /* For -fpic code the PLT entries might use r12 which is
10736 call-saved. Therefore we cannot do a sibcall when
10737 calling directly using a symbol ref. When reaching
10738 this point we decided (in s390_function_ok_for_sibcall)
10739 to do a sibcall for a function pointer but one of the
10740 optimizers was able to get rid of the function pointer
10741 by propagating the symbol ref into the call. This
10742 optimization is illegal for S/390 so we turn the direct
10743 call into a indirect call again. */
10744 addr_location = force_reg (Pmode, addr_location);
10745 }
10746
10747 /* Unless we can use the bras(l) insn, force the
10748 routine address into a register. */
10749 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
10750 {
10751 if (flag_pic)
10752 addr_location = legitimize_pic_address (addr_location, 0);
10753 else
10754 addr_location = force_reg (Pmode, addr_location);
10755 }
10756 }
10757
10758 /* If it is already an indirect call or the code above moved the
10759 SYMBOL_REF to somewhere else make sure the address can be found in
10760 register 1. */
10761 if (retaddr_reg == NULL_RTX
10762 && GET_CODE (addr_location) != SYMBOL_REF
10763 && !plt_call)
10764 {
10765 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
10766 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
10767 }
10768
10769 addr_location = gen_rtx_MEM (QImode, addr_location);
10770 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
10771
10772 if (result_reg != NULL_RTX)
10773 call = gen_rtx_SET (VOIDmode, result_reg, call);
10774
10775 if (retaddr_reg != NULL_RTX)
10776 {
10777 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
10778
10779 if (tls_call != NULL_RTX)
10780 vec = gen_rtvec (3, call, clobber,
10781 gen_rtx_USE (VOIDmode, tls_call));
10782 else
10783 vec = gen_rtvec (2, call, clobber);
10784
10785 call = gen_rtx_PARALLEL (VOIDmode, vec);
10786 }
10787
10788 insn = emit_call_insn (call);
10789
10790 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
10791 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
10792 {
10793 /* s390_function_ok_for_sibcall should
10794 have denied sibcalls in this case. */
10795 gcc_assert (retaddr_reg != NULL_RTX);
10796 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, 12));
10797 }
10798 return insn;
10799 }
10800
10801 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
10802
10803 static void
10804 s390_conditional_register_usage (void)
10805 {
10806 int i;
10807
10808 if (flag_pic)
10809 {
10810 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
10811 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
10812 }
10813 if (TARGET_CPU_ZARCH)
10814 {
10815 fixed_regs[BASE_REGNUM] = 0;
10816 call_used_regs[BASE_REGNUM] = 0;
10817 fixed_regs[RETURN_REGNUM] = 0;
10818 call_used_regs[RETURN_REGNUM] = 0;
10819 }
10820 if (TARGET_64BIT)
10821 {
10822 for (i = FPR8_REGNUM; i <= FPR15_REGNUM; i++)
10823 call_used_regs[i] = call_really_used_regs[i] = 0;
10824 }
10825 else
10826 {
10827 call_used_regs[FPR4_REGNUM] = call_really_used_regs[FPR4_REGNUM] = 0;
10828 call_used_regs[FPR6_REGNUM] = call_really_used_regs[FPR6_REGNUM] = 0;
10829 }
10830
10831 if (TARGET_SOFT_FLOAT)
10832 {
10833 for (i = FPR0_REGNUM; i <= FPR15_REGNUM; i++)
10834 call_used_regs[i] = fixed_regs[i] = 1;
10835 }
10836 }
10837
10838 /* Corresponding function to eh_return expander. */
10839
10840 static GTY(()) rtx s390_tpf_eh_return_symbol;
10841 void
10842 s390_emit_tpf_eh_return (rtx target)
10843 {
10844 rtx_insn *insn;
10845 rtx reg, orig_ra;
10846
10847 if (!s390_tpf_eh_return_symbol)
10848 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
10849
10850 reg = gen_rtx_REG (Pmode, 2);
10851 orig_ra = gen_rtx_REG (Pmode, 3);
10852
10853 emit_move_insn (reg, target);
10854 emit_move_insn (orig_ra, get_hard_reg_initial_val (Pmode, RETURN_REGNUM));
10855 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
10856 gen_rtx_REG (Pmode, RETURN_REGNUM));
10857 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
10858 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), orig_ra);
10859
10860 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
10861 }
10862
10863 /* Rework the prologue/epilogue to avoid saving/restoring
10864 registers unnecessarily. */
10865
10866 static void
10867 s390_optimize_prologue (void)
10868 {
10869 rtx_insn *insn, *new_insn, *next_insn;
10870
10871 /* Do a final recompute of the frame-related data. */
10872 s390_optimize_register_info ();
10873
10874 /* If all special registers are in fact used, there's nothing we
10875 can do, so no point in walking the insn list. */
10876
10877 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
10878 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
10879 && (TARGET_CPU_ZARCH
10880 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
10881 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
10882 return;
10883
10884 /* Search for prologue/epilogue insns and replace them. */
10885
10886 for (insn = get_insns (); insn; insn = next_insn)
10887 {
10888 int first, last, off;
10889 rtx set, base, offset;
10890 rtx pat;
10891
10892 next_insn = NEXT_INSN (insn);
10893
10894 if (! NONJUMP_INSN_P (insn) || ! RTX_FRAME_RELATED_P (insn))
10895 continue;
10896
10897 pat = PATTERN (insn);
10898
10899 /* Remove ldgr/lgdr instructions used for saving and restore
10900 GPRs if possible. */
10901 if (TARGET_Z10
10902 && GET_CODE (pat) == SET
10903 && GET_MODE (SET_SRC (pat)) == DImode
10904 && REG_P (SET_SRC (pat))
10905 && REG_P (SET_DEST (pat)))
10906 {
10907 int src_regno = REGNO (SET_SRC (pat));
10908 int dest_regno = REGNO (SET_DEST (pat));
10909 int gpr_regno;
10910 int fpr_regno;
10911
10912 if (!((GENERAL_REGNO_P (src_regno) && FP_REGNO_P (dest_regno))
10913 || (FP_REGNO_P (src_regno) && GENERAL_REGNO_P (dest_regno))))
10914 continue;
10915
10916 gpr_regno = GENERAL_REGNO_P (src_regno) ? src_regno : dest_regno;
10917 fpr_regno = FP_REGNO_P (src_regno) ? src_regno : dest_regno;
10918
10919 /* GPR must be call-saved, FPR must be call-clobbered. */
10920 if (!call_really_used_regs[fpr_regno]
10921 || call_really_used_regs[gpr_regno])
10922 continue;
10923
10924 /* It must not happen that what we once saved in an FPR now
10925 needs a stack slot. */
10926 gcc_assert (cfun_gpr_save_slot (gpr_regno) != -1);
10927
10928 if (cfun_gpr_save_slot (gpr_regno) == 0)
10929 {
10930 remove_insn (insn);
10931 continue;
10932 }
10933 }
10934
10935 if (GET_CODE (pat) == PARALLEL
10936 && store_multiple_operation (pat, VOIDmode))
10937 {
10938 set = XVECEXP (pat, 0, 0);
10939 first = REGNO (SET_SRC (set));
10940 last = first + XVECLEN (pat, 0) - 1;
10941 offset = const0_rtx;
10942 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
10943 off = INTVAL (offset);
10944
10945 if (GET_CODE (base) != REG || off < 0)
10946 continue;
10947 if (cfun_frame_layout.first_save_gpr != -1
10948 && (cfun_frame_layout.first_save_gpr < first
10949 || cfun_frame_layout.last_save_gpr > last))
10950 continue;
10951 if (REGNO (base) != STACK_POINTER_REGNUM
10952 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10953 continue;
10954 if (first > BASE_REGNUM || last < BASE_REGNUM)
10955 continue;
10956
10957 if (cfun_frame_layout.first_save_gpr != -1)
10958 {
10959 rtx s_pat = save_gprs (base,
10960 off + (cfun_frame_layout.first_save_gpr
10961 - first) * UNITS_PER_LONG,
10962 cfun_frame_layout.first_save_gpr,
10963 cfun_frame_layout.last_save_gpr);
10964 new_insn = emit_insn_before (s_pat, insn);
10965 INSN_ADDRESSES_NEW (new_insn, -1);
10966 }
10967
10968 remove_insn (insn);
10969 continue;
10970 }
10971
10972 if (cfun_frame_layout.first_save_gpr == -1
10973 && GET_CODE (pat) == SET
10974 && GENERAL_REG_P (SET_SRC (pat))
10975 && GET_CODE (SET_DEST (pat)) == MEM)
10976 {
10977 set = pat;
10978 first = REGNO (SET_SRC (set));
10979 offset = const0_rtx;
10980 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
10981 off = INTVAL (offset);
10982
10983 if (GET_CODE (base) != REG || off < 0)
10984 continue;
10985 if (REGNO (base) != STACK_POINTER_REGNUM
10986 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10987 continue;
10988
10989 remove_insn (insn);
10990 continue;
10991 }
10992
10993 if (GET_CODE (pat) == PARALLEL
10994 && load_multiple_operation (pat, VOIDmode))
10995 {
10996 set = XVECEXP (pat, 0, 0);
10997 first = REGNO (SET_DEST (set));
10998 last = first + XVECLEN (pat, 0) - 1;
10999 offset = const0_rtx;
11000 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
11001 off = INTVAL (offset);
11002
11003 if (GET_CODE (base) != REG || off < 0)
11004 continue;
11005
11006 if (cfun_frame_layout.first_restore_gpr != -1
11007 && (cfun_frame_layout.first_restore_gpr < first
11008 || cfun_frame_layout.last_restore_gpr > last))
11009 continue;
11010 if (REGNO (base) != STACK_POINTER_REGNUM
11011 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
11012 continue;
11013 if (first > BASE_REGNUM || last < BASE_REGNUM)
11014 continue;
11015
11016 if (cfun_frame_layout.first_restore_gpr != -1)
11017 {
11018 rtx rpat = restore_gprs (base,
11019 off + (cfun_frame_layout.first_restore_gpr
11020 - first) * UNITS_PER_LONG,
11021 cfun_frame_layout.first_restore_gpr,
11022 cfun_frame_layout.last_restore_gpr);
11023
11024 /* Remove REG_CFA_RESTOREs for registers that we no
11025 longer need to save. */
11026 REG_NOTES (rpat) = REG_NOTES (insn);
11027 for (rtx *ptr = &REG_NOTES (rpat); *ptr; )
11028 if (REG_NOTE_KIND (*ptr) == REG_CFA_RESTORE
11029 && ((int) REGNO (XEXP (*ptr, 0))
11030 < cfun_frame_layout.first_restore_gpr))
11031 *ptr = XEXP (*ptr, 1);
11032 else
11033 ptr = &XEXP (*ptr, 1);
11034 new_insn = emit_insn_before (rpat, insn);
11035 RTX_FRAME_RELATED_P (new_insn) = 1;
11036 INSN_ADDRESSES_NEW (new_insn, -1);
11037 }
11038
11039 remove_insn (insn);
11040 continue;
11041 }
11042
11043 if (cfun_frame_layout.first_restore_gpr == -1
11044 && GET_CODE (pat) == SET
11045 && GENERAL_REG_P (SET_DEST (pat))
11046 && GET_CODE (SET_SRC (pat)) == MEM)
11047 {
11048 set = pat;
11049 first = REGNO (SET_DEST (set));
11050 offset = const0_rtx;
11051 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
11052 off = INTVAL (offset);
11053
11054 if (GET_CODE (base) != REG || off < 0)
11055 continue;
11056
11057 if (REGNO (base) != STACK_POINTER_REGNUM
11058 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
11059 continue;
11060
11061 remove_insn (insn);
11062 continue;
11063 }
11064 }
11065 }
11066
11067 /* On z10 and later the dynamic branch prediction must see the
11068 backward jump within a certain windows. If not it falls back to
11069 the static prediction. This function rearranges the loop backward
11070 branch in a way which makes the static prediction always correct.
11071 The function returns true if it added an instruction. */
11072 static bool
11073 s390_fix_long_loop_prediction (rtx_insn *insn)
11074 {
11075 rtx set = single_set (insn);
11076 rtx code_label, label_ref, new_label;
11077 rtx_insn *uncond_jump;
11078 rtx_insn *cur_insn;
11079 rtx tmp;
11080 int distance;
11081
11082 /* This will exclude branch on count and branch on index patterns
11083 since these are correctly statically predicted. */
11084 if (!set
11085 || SET_DEST (set) != pc_rtx
11086 || GET_CODE (SET_SRC(set)) != IF_THEN_ELSE)
11087 return false;
11088
11089 /* Skip conditional returns. */
11090 if (ANY_RETURN_P (XEXP (SET_SRC (set), 1))
11091 && XEXP (SET_SRC (set), 2) == pc_rtx)
11092 return false;
11093
11094 label_ref = (GET_CODE (XEXP (SET_SRC (set), 1)) == LABEL_REF ?
11095 XEXP (SET_SRC (set), 1) : XEXP (SET_SRC (set), 2));
11096
11097 gcc_assert (GET_CODE (label_ref) == LABEL_REF);
11098
11099 code_label = XEXP (label_ref, 0);
11100
11101 if (INSN_ADDRESSES (INSN_UID (code_label)) == -1
11102 || INSN_ADDRESSES (INSN_UID (insn)) == -1
11103 || (INSN_ADDRESSES (INSN_UID (insn))
11104 - INSN_ADDRESSES (INSN_UID (code_label)) < PREDICT_DISTANCE))
11105 return false;
11106
11107 for (distance = 0, cur_insn = PREV_INSN (insn);
11108 distance < PREDICT_DISTANCE - 6;
11109 distance += get_attr_length (cur_insn), cur_insn = PREV_INSN (cur_insn))
11110 if (!cur_insn || JUMP_P (cur_insn) || LABEL_P (cur_insn))
11111 return false;
11112
11113 new_label = gen_label_rtx ();
11114 uncond_jump = emit_jump_insn_after (
11115 gen_rtx_SET (VOIDmode, pc_rtx,
11116 gen_rtx_LABEL_REF (VOIDmode, code_label)),
11117 insn);
11118 emit_label_after (new_label, uncond_jump);
11119
11120 tmp = XEXP (SET_SRC (set), 1);
11121 XEXP (SET_SRC (set), 1) = XEXP (SET_SRC (set), 2);
11122 XEXP (SET_SRC (set), 2) = tmp;
11123 INSN_CODE (insn) = -1;
11124
11125 XEXP (label_ref, 0) = new_label;
11126 JUMP_LABEL (insn) = new_label;
11127 JUMP_LABEL (uncond_jump) = code_label;
11128
11129 return true;
11130 }
11131
11132 /* Returns 1 if INSN reads the value of REG for purposes not related
11133 to addressing of memory, and 0 otherwise. */
11134 static int
11135 s390_non_addr_reg_read_p (rtx reg, rtx_insn *insn)
11136 {
11137 return reg_referenced_p (reg, PATTERN (insn))
11138 && !reg_used_in_mem_p (REGNO (reg), PATTERN (insn));
11139 }
11140
11141 /* Starting from INSN find_cond_jump looks downwards in the insn
11142 stream for a single jump insn which is the last user of the
11143 condition code set in INSN. */
11144 static rtx_insn *
11145 find_cond_jump (rtx_insn *insn)
11146 {
11147 for (; insn; insn = NEXT_INSN (insn))
11148 {
11149 rtx ite, cc;
11150
11151 if (LABEL_P (insn))
11152 break;
11153
11154 if (!JUMP_P (insn))
11155 {
11156 if (reg_mentioned_p (gen_rtx_REG (CCmode, CC_REGNUM), insn))
11157 break;
11158 continue;
11159 }
11160
11161 /* This will be triggered by a return. */
11162 if (GET_CODE (PATTERN (insn)) != SET)
11163 break;
11164
11165 gcc_assert (SET_DEST (PATTERN (insn)) == pc_rtx);
11166 ite = SET_SRC (PATTERN (insn));
11167
11168 if (GET_CODE (ite) != IF_THEN_ELSE)
11169 break;
11170
11171 cc = XEXP (XEXP (ite, 0), 0);
11172 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc)))
11173 break;
11174
11175 if (find_reg_note (insn, REG_DEAD, cc))
11176 return insn;
11177 break;
11178 }
11179
11180 return NULL;
11181 }
11182
11183 /* Swap the condition in COND and the operands in OP0 and OP1 so that
11184 the semantics does not change. If NULL_RTX is passed as COND the
11185 function tries to find the conditional jump starting with INSN. */
11186 static void
11187 s390_swap_cmp (rtx cond, rtx *op0, rtx *op1, rtx_insn *insn)
11188 {
11189 rtx tmp = *op0;
11190
11191 if (cond == NULL_RTX)
11192 {
11193 rtx_insn *jump = find_cond_jump (NEXT_INSN (insn));
11194 rtx set = jump ? single_set (jump) : NULL_RTX;
11195
11196 if (set == NULL_RTX)
11197 return;
11198
11199 cond = XEXP (SET_SRC (set), 0);
11200 }
11201
11202 *op0 = *op1;
11203 *op1 = tmp;
11204 PUT_CODE (cond, swap_condition (GET_CODE (cond)));
11205 }
11206
11207 /* On z10, instructions of the compare-and-branch family have the
11208 property to access the register occurring as second operand with
11209 its bits complemented. If such a compare is grouped with a second
11210 instruction that accesses the same register non-complemented, and
11211 if that register's value is delivered via a bypass, then the
11212 pipeline recycles, thereby causing significant performance decline.
11213 This function locates such situations and exchanges the two
11214 operands of the compare. The function return true whenever it
11215 added an insn. */
11216 static bool
11217 s390_z10_optimize_cmp (rtx_insn *insn)
11218 {
11219 rtx_insn *prev_insn, *next_insn;
11220 bool insn_added_p = false;
11221 rtx cond, *op0, *op1;
11222
11223 if (GET_CODE (PATTERN (insn)) == PARALLEL)
11224 {
11225 /* Handle compare and branch and branch on count
11226 instructions. */
11227 rtx pattern = single_set (insn);
11228
11229 if (!pattern
11230 || SET_DEST (pattern) != pc_rtx
11231 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE)
11232 return false;
11233
11234 cond = XEXP (SET_SRC (pattern), 0);
11235 op0 = &XEXP (cond, 0);
11236 op1 = &XEXP (cond, 1);
11237 }
11238 else if (GET_CODE (PATTERN (insn)) == SET)
11239 {
11240 rtx src, dest;
11241
11242 /* Handle normal compare instructions. */
11243 src = SET_SRC (PATTERN (insn));
11244 dest = SET_DEST (PATTERN (insn));
11245
11246 if (!REG_P (dest)
11247 || !CC_REGNO_P (REGNO (dest))
11248 || GET_CODE (src) != COMPARE)
11249 return false;
11250
11251 /* s390_swap_cmp will try to find the conditional
11252 jump when passing NULL_RTX as condition. */
11253 cond = NULL_RTX;
11254 op0 = &XEXP (src, 0);
11255 op1 = &XEXP (src, 1);
11256 }
11257 else
11258 return false;
11259
11260 if (!REG_P (*op0) || !REG_P (*op1))
11261 return false;
11262
11263 if (GET_MODE_CLASS (GET_MODE (*op0)) != MODE_INT)
11264 return false;
11265
11266 /* Swap the COMPARE arguments and its mask if there is a
11267 conflicting access in the previous insn. */
11268 prev_insn = prev_active_insn (insn);
11269 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
11270 && reg_referenced_p (*op1, PATTERN (prev_insn)))
11271 s390_swap_cmp (cond, op0, op1, insn);
11272
11273 /* Check if there is a conflict with the next insn. If there
11274 was no conflict with the previous insn, then swap the
11275 COMPARE arguments and its mask. If we already swapped
11276 the operands, or if swapping them would cause a conflict
11277 with the previous insn, issue a NOP after the COMPARE in
11278 order to separate the two instuctions. */
11279 next_insn = next_active_insn (insn);
11280 if (next_insn != NULL_RTX && INSN_P (next_insn)
11281 && s390_non_addr_reg_read_p (*op1, next_insn))
11282 {
11283 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
11284 && s390_non_addr_reg_read_p (*op0, prev_insn))
11285 {
11286 if (REGNO (*op1) == 0)
11287 emit_insn_after (gen_nop1 (), insn);
11288 else
11289 emit_insn_after (gen_nop (), insn);
11290 insn_added_p = true;
11291 }
11292 else
11293 s390_swap_cmp (cond, op0, op1, insn);
11294 }
11295 return insn_added_p;
11296 }
11297
11298 /* Perform machine-dependent processing. */
11299
11300 static void
11301 s390_reorg (void)
11302 {
11303 bool pool_overflow = false;
11304
11305 /* Make sure all splits have been performed; splits after
11306 machine_dependent_reorg might confuse insn length counts. */
11307 split_all_insns_noflow ();
11308
11309 /* Install the main literal pool and the associated base
11310 register load insns.
11311
11312 In addition, there are two problematic situations we need
11313 to correct:
11314
11315 - the literal pool might be > 4096 bytes in size, so that
11316 some of its elements cannot be directly accessed
11317
11318 - a branch target might be > 64K away from the branch, so that
11319 it is not possible to use a PC-relative instruction.
11320
11321 To fix those, we split the single literal pool into multiple
11322 pool chunks, reloading the pool base register at various
11323 points throughout the function to ensure it always points to
11324 the pool chunk the following code expects, and / or replace
11325 PC-relative branches by absolute branches.
11326
11327 However, the two problems are interdependent: splitting the
11328 literal pool can move a branch further away from its target,
11329 causing the 64K limit to overflow, and on the other hand,
11330 replacing a PC-relative branch by an absolute branch means
11331 we need to put the branch target address into the literal
11332 pool, possibly causing it to overflow.
11333
11334 So, we loop trying to fix up both problems until we manage
11335 to satisfy both conditions at the same time. Note that the
11336 loop is guaranteed to terminate as every pass of the loop
11337 strictly decreases the total number of PC-relative branches
11338 in the function. (This is not completely true as there
11339 might be branch-over-pool insns introduced by chunkify_start.
11340 Those never need to be split however.) */
11341
11342 for (;;)
11343 {
11344 struct constant_pool *pool = NULL;
11345
11346 /* Collect the literal pool. */
11347 if (!pool_overflow)
11348 {
11349 pool = s390_mainpool_start ();
11350 if (!pool)
11351 pool_overflow = true;
11352 }
11353
11354 /* If literal pool overflowed, start to chunkify it. */
11355 if (pool_overflow)
11356 pool = s390_chunkify_start ();
11357
11358 /* Split out-of-range branches. If this has created new
11359 literal pool entries, cancel current chunk list and
11360 recompute it. zSeries machines have large branch
11361 instructions, so we never need to split a branch. */
11362 if (!TARGET_CPU_ZARCH && s390_split_branches ())
11363 {
11364 if (pool_overflow)
11365 s390_chunkify_cancel (pool);
11366 else
11367 s390_mainpool_cancel (pool);
11368
11369 continue;
11370 }
11371
11372 /* If we made it up to here, both conditions are satisfied.
11373 Finish up literal pool related changes. */
11374 if (pool_overflow)
11375 s390_chunkify_finish (pool);
11376 else
11377 s390_mainpool_finish (pool);
11378
11379 /* We're done splitting branches. */
11380 cfun->machine->split_branches_pending_p = false;
11381 break;
11382 }
11383
11384 /* Generate out-of-pool execute target insns. */
11385 if (TARGET_CPU_ZARCH)
11386 {
11387 rtx_insn *insn, *target;
11388 rtx label;
11389
11390 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11391 {
11392 label = s390_execute_label (insn);
11393 if (!label)
11394 continue;
11395
11396 gcc_assert (label != const0_rtx);
11397
11398 target = emit_label (XEXP (label, 0));
11399 INSN_ADDRESSES_NEW (target, -1);
11400
11401 target = emit_insn (s390_execute_target (insn));
11402 INSN_ADDRESSES_NEW (target, -1);
11403 }
11404 }
11405
11406 /* Try to optimize prologue and epilogue further. */
11407 s390_optimize_prologue ();
11408
11409 /* Walk over the insns and do some >=z10 specific changes. */
11410 if (s390_tune == PROCESSOR_2097_Z10
11411 || s390_tune == PROCESSOR_2817_Z196
11412 || s390_tune == PROCESSOR_2827_ZEC12)
11413 {
11414 rtx_insn *insn;
11415 bool insn_added_p = false;
11416
11417 /* The insn lengths and addresses have to be up to date for the
11418 following manipulations. */
11419 shorten_branches (get_insns ());
11420
11421 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11422 {
11423 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
11424 continue;
11425
11426 if (JUMP_P (insn))
11427 insn_added_p |= s390_fix_long_loop_prediction (insn);
11428
11429 if ((GET_CODE (PATTERN (insn)) == PARALLEL
11430 || GET_CODE (PATTERN (insn)) == SET)
11431 && s390_tune == PROCESSOR_2097_Z10)
11432 insn_added_p |= s390_z10_optimize_cmp (insn);
11433 }
11434
11435 /* Adjust branches if we added new instructions. */
11436 if (insn_added_p)
11437 shorten_branches (get_insns ());
11438 }
11439 }
11440
11441 /* Return true if INSN is a fp load insn writing register REGNO. */
11442 static inline bool
11443 s390_fpload_toreg (rtx_insn *insn, unsigned int regno)
11444 {
11445 rtx set;
11446 enum attr_type flag = s390_safe_attr_type (insn);
11447
11448 if (flag != TYPE_FLOADSF && flag != TYPE_FLOADDF)
11449 return false;
11450
11451 set = single_set (insn);
11452
11453 if (set == NULL_RTX)
11454 return false;
11455
11456 if (!REG_P (SET_DEST (set)) || !MEM_P (SET_SRC (set)))
11457 return false;
11458
11459 if (REGNO (SET_DEST (set)) != regno)
11460 return false;
11461
11462 return true;
11463 }
11464
11465 /* This value describes the distance to be avoided between an
11466 aritmetic fp instruction and an fp load writing the same register.
11467 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
11468 fine but the exact value has to be avoided. Otherwise the FP
11469 pipeline will throw an exception causing a major penalty. */
11470 #define Z10_EARLYLOAD_DISTANCE 7
11471
11472 /* Rearrange the ready list in order to avoid the situation described
11473 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
11474 moved to the very end of the ready list. */
11475 static void
11476 s390_z10_prevent_earlyload_conflicts (rtx_insn **ready, int *nready_p)
11477 {
11478 unsigned int regno;
11479 int nready = *nready_p;
11480 rtx_insn *tmp;
11481 int i;
11482 rtx_insn *insn;
11483 rtx set;
11484 enum attr_type flag;
11485 int distance;
11486
11487 /* Skip DISTANCE - 1 active insns. */
11488 for (insn = last_scheduled_insn, distance = Z10_EARLYLOAD_DISTANCE - 1;
11489 distance > 0 && insn != NULL_RTX;
11490 distance--, insn = prev_active_insn (insn))
11491 if (CALL_P (insn) || JUMP_P (insn))
11492 return;
11493
11494 if (insn == NULL_RTX)
11495 return;
11496
11497 set = single_set (insn);
11498
11499 if (set == NULL_RTX || !REG_P (SET_DEST (set))
11500 || GET_MODE_CLASS (GET_MODE (SET_DEST (set))) != MODE_FLOAT)
11501 return;
11502
11503 flag = s390_safe_attr_type (insn);
11504
11505 if (flag == TYPE_FLOADSF || flag == TYPE_FLOADDF)
11506 return;
11507
11508 regno = REGNO (SET_DEST (set));
11509 i = nready - 1;
11510
11511 while (!s390_fpload_toreg (ready[i], regno) && i > 0)
11512 i--;
11513
11514 if (!i)
11515 return;
11516
11517 tmp = ready[i];
11518 memmove (&ready[1], &ready[0], sizeof (rtx_insn *) * i);
11519 ready[0] = tmp;
11520 }
11521
11522
11523 /* The s390_sched_state variable tracks the state of the current or
11524 the last instruction group.
11525
11526 0,1,2 number of instructions scheduled in the current group
11527 3 the last group is complete - normal insns
11528 4 the last group was a cracked/expanded insn */
11529
11530 static int s390_sched_state;
11531
11532 #define S390_OOO_SCHED_STATE_NORMAL 3
11533 #define S390_OOO_SCHED_STATE_CRACKED 4
11534
11535 #define S390_OOO_SCHED_ATTR_MASK_CRACKED 0x1
11536 #define S390_OOO_SCHED_ATTR_MASK_EXPANDED 0x2
11537 #define S390_OOO_SCHED_ATTR_MASK_ENDGROUP 0x4
11538 #define S390_OOO_SCHED_ATTR_MASK_GROUPALONE 0x8
11539
11540 static unsigned int
11541 s390_get_sched_attrmask (rtx_insn *insn)
11542 {
11543 unsigned int mask = 0;
11544
11545 if (get_attr_ooo_cracked (insn))
11546 mask |= S390_OOO_SCHED_ATTR_MASK_CRACKED;
11547 if (get_attr_ooo_expanded (insn))
11548 mask |= S390_OOO_SCHED_ATTR_MASK_EXPANDED;
11549 if (get_attr_ooo_endgroup (insn))
11550 mask |= S390_OOO_SCHED_ATTR_MASK_ENDGROUP;
11551 if (get_attr_ooo_groupalone (insn))
11552 mask |= S390_OOO_SCHED_ATTR_MASK_GROUPALONE;
11553 return mask;
11554 }
11555
11556 /* Return the scheduling score for INSN. The higher the score the
11557 better. The score is calculated from the OOO scheduling attributes
11558 of INSN and the scheduling state s390_sched_state. */
11559 static int
11560 s390_sched_score (rtx_insn *insn)
11561 {
11562 unsigned int mask = s390_get_sched_attrmask (insn);
11563 int score = 0;
11564
11565 switch (s390_sched_state)
11566 {
11567 case 0:
11568 /* Try to put insns into the first slot which would otherwise
11569 break a group. */
11570 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) != 0
11571 || (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) != 0)
11572 score += 5;
11573 if ((mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) != 0)
11574 score += 10;
11575 case 1:
11576 /* Prefer not cracked insns while trying to put together a
11577 group. */
11578 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) == 0
11579 && (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) == 0
11580 && (mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) == 0)
11581 score += 10;
11582 if ((mask & S390_OOO_SCHED_ATTR_MASK_ENDGROUP) == 0)
11583 score += 5;
11584 break;
11585 case 2:
11586 /* Prefer not cracked insns while trying to put together a
11587 group. */
11588 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) == 0
11589 && (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) == 0
11590 && (mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) == 0)
11591 score += 10;
11592 /* Prefer endgroup insns in the last slot. */
11593 if ((mask & S390_OOO_SCHED_ATTR_MASK_ENDGROUP) != 0)
11594 score += 10;
11595 break;
11596 case S390_OOO_SCHED_STATE_NORMAL:
11597 /* Prefer not cracked insns if the last was not cracked. */
11598 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) == 0
11599 && (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) == 0)
11600 score += 5;
11601 if ((mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) != 0)
11602 score += 10;
11603 break;
11604 case S390_OOO_SCHED_STATE_CRACKED:
11605 /* Try to keep cracked insns together to prevent them from
11606 interrupting groups. */
11607 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) != 0
11608 || (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) != 0)
11609 score += 5;
11610 break;
11611 }
11612 return score;
11613 }
11614
11615 /* This function is called via hook TARGET_SCHED_REORDER before
11616 issuing one insn from list READY which contains *NREADYP entries.
11617 For target z10 it reorders load instructions to avoid early load
11618 conflicts in the floating point pipeline */
11619 static int
11620 s390_sched_reorder (FILE *file, int verbose,
11621 rtx_insn **ready, int *nreadyp, int clock ATTRIBUTE_UNUSED)
11622 {
11623 if (s390_tune == PROCESSOR_2097_Z10)
11624 if (reload_completed && *nreadyp > 1)
11625 s390_z10_prevent_earlyload_conflicts (ready, nreadyp);
11626
11627 if (s390_tune == PROCESSOR_2827_ZEC12
11628 && reload_completed
11629 && *nreadyp > 1)
11630 {
11631 int i;
11632 int last_index = *nreadyp - 1;
11633 int max_index = -1;
11634 int max_score = -1;
11635 rtx_insn *tmp;
11636
11637 /* Just move the insn with the highest score to the top (the
11638 end) of the list. A full sort is not needed since a conflict
11639 in the hazard recognition cannot happen. So the top insn in
11640 the ready list will always be taken. */
11641 for (i = last_index; i >= 0; i--)
11642 {
11643 int score;
11644
11645 if (recog_memoized (ready[i]) < 0)
11646 continue;
11647
11648 score = s390_sched_score (ready[i]);
11649 if (score > max_score)
11650 {
11651 max_score = score;
11652 max_index = i;
11653 }
11654 }
11655
11656 if (max_index != -1)
11657 {
11658 if (max_index != last_index)
11659 {
11660 tmp = ready[max_index];
11661 ready[max_index] = ready[last_index];
11662 ready[last_index] = tmp;
11663
11664 if (verbose > 5)
11665 fprintf (file,
11666 "move insn %d to the top of list\n",
11667 INSN_UID (ready[last_index]));
11668 }
11669 else if (verbose > 5)
11670 fprintf (file,
11671 "best insn %d already on top\n",
11672 INSN_UID (ready[last_index]));
11673 }
11674
11675 if (verbose > 5)
11676 {
11677 fprintf (file, "ready list ooo attributes - sched state: %d\n",
11678 s390_sched_state);
11679
11680 for (i = last_index; i >= 0; i--)
11681 {
11682 if (recog_memoized (ready[i]) < 0)
11683 continue;
11684 fprintf (file, "insn %d score: %d: ", INSN_UID (ready[i]),
11685 s390_sched_score (ready[i]));
11686 #define PRINT_OOO_ATTR(ATTR) fprintf (file, "%s ", get_attr_##ATTR (ready[i]) ? #ATTR : "!" #ATTR);
11687 PRINT_OOO_ATTR (ooo_cracked);
11688 PRINT_OOO_ATTR (ooo_expanded);
11689 PRINT_OOO_ATTR (ooo_endgroup);
11690 PRINT_OOO_ATTR (ooo_groupalone);
11691 #undef PRINT_OOO_ATTR
11692 fprintf (file, "\n");
11693 }
11694 }
11695 }
11696
11697 return s390_issue_rate ();
11698 }
11699
11700
11701 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
11702 the scheduler has issued INSN. It stores the last issued insn into
11703 last_scheduled_insn in order to make it available for
11704 s390_sched_reorder. */
11705 static int
11706 s390_sched_variable_issue (FILE *file, int verbose, rtx_insn *insn, int more)
11707 {
11708 last_scheduled_insn = insn;
11709
11710 if (s390_tune == PROCESSOR_2827_ZEC12
11711 && reload_completed
11712 && recog_memoized (insn) >= 0)
11713 {
11714 unsigned int mask = s390_get_sched_attrmask (insn);
11715
11716 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) != 0
11717 || (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) != 0)
11718 s390_sched_state = S390_OOO_SCHED_STATE_CRACKED;
11719 else if ((mask & S390_OOO_SCHED_ATTR_MASK_ENDGROUP) != 0
11720 || (mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) != 0)
11721 s390_sched_state = S390_OOO_SCHED_STATE_NORMAL;
11722 else
11723 {
11724 /* Only normal insns are left (mask == 0). */
11725 switch (s390_sched_state)
11726 {
11727 case 0:
11728 case 1:
11729 case 2:
11730 case S390_OOO_SCHED_STATE_NORMAL:
11731 if (s390_sched_state == S390_OOO_SCHED_STATE_NORMAL)
11732 s390_sched_state = 1;
11733 else
11734 s390_sched_state++;
11735
11736 break;
11737 case S390_OOO_SCHED_STATE_CRACKED:
11738 s390_sched_state = S390_OOO_SCHED_STATE_NORMAL;
11739 break;
11740 }
11741 }
11742 if (verbose > 5)
11743 {
11744 fprintf (file, "insn %d: ", INSN_UID (insn));
11745 #define PRINT_OOO_ATTR(ATTR) \
11746 fprintf (file, "%s ", get_attr_##ATTR (insn) ? #ATTR : "");
11747 PRINT_OOO_ATTR (ooo_cracked);
11748 PRINT_OOO_ATTR (ooo_expanded);
11749 PRINT_OOO_ATTR (ooo_endgroup);
11750 PRINT_OOO_ATTR (ooo_groupalone);
11751 #undef PRINT_OOO_ATTR
11752 fprintf (file, "\n");
11753 fprintf (file, "sched state: %d\n", s390_sched_state);
11754 }
11755 }
11756
11757 if (GET_CODE (PATTERN (insn)) != USE
11758 && GET_CODE (PATTERN (insn)) != CLOBBER)
11759 return more - 1;
11760 else
11761 return more;
11762 }
11763
11764 static void
11765 s390_sched_init (FILE *file ATTRIBUTE_UNUSED,
11766 int verbose ATTRIBUTE_UNUSED,
11767 int max_ready ATTRIBUTE_UNUSED)
11768 {
11769 last_scheduled_insn = NULL;
11770 s390_sched_state = 0;
11771 }
11772
11773 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
11774 a new number struct loop *loop should be unrolled if tuned for cpus with
11775 a built-in stride prefetcher.
11776 The loop is analyzed for memory accesses by calling check_dpu for
11777 each rtx of the loop. Depending on the loop_depth and the amount of
11778 memory accesses a new number <=nunroll is returned to improve the
11779 behaviour of the hardware prefetch unit. */
11780 static unsigned
11781 s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop)
11782 {
11783 basic_block *bbs;
11784 rtx_insn *insn;
11785 unsigned i;
11786 unsigned mem_count = 0;
11787
11788 if (s390_tune != PROCESSOR_2097_Z10
11789 && s390_tune != PROCESSOR_2817_Z196
11790 && s390_tune != PROCESSOR_2827_ZEC12)
11791 return nunroll;
11792
11793 /* Count the number of memory references within the loop body. */
11794 bbs = get_loop_body (loop);
11795 subrtx_iterator::array_type array;
11796 for (i = 0; i < loop->num_nodes; i++)
11797 FOR_BB_INSNS (bbs[i], insn)
11798 if (INSN_P (insn) && INSN_CODE (insn) != -1)
11799 FOR_EACH_SUBRTX (iter, array, PATTERN (insn), NONCONST)
11800 if (MEM_P (*iter))
11801 mem_count += 1;
11802 free (bbs);
11803
11804 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
11805 if (mem_count == 0)
11806 return nunroll;
11807
11808 switch (loop_depth(loop))
11809 {
11810 case 1:
11811 return MIN (nunroll, 28 / mem_count);
11812 case 2:
11813 return MIN (nunroll, 22 / mem_count);
11814 default:
11815 return MIN (nunroll, 16 / mem_count);
11816 }
11817 }
11818
11819 static void
11820 s390_option_override (void)
11821 {
11822 unsigned int i;
11823 cl_deferred_option *opt;
11824 vec<cl_deferred_option> *v =
11825 (vec<cl_deferred_option> *) s390_deferred_options;
11826
11827 if (v)
11828 FOR_EACH_VEC_ELT (*v, i, opt)
11829 {
11830 switch (opt->opt_index)
11831 {
11832 case OPT_mhotpatch:
11833 s390_hotpatch_trampoline_halfwords = (opt->value) ?
11834 s390_hotpatch_trampoline_halfwords_default : -1;
11835 break;
11836 case OPT_mhotpatch_:
11837 {
11838 int val;
11839
11840 val = integral_argument (opt->arg);
11841 if (val == -1)
11842 {
11843 /* argument is not a plain number */
11844 error ("argument to %qs should be a non-negative integer",
11845 "-mhotpatch=");
11846 break;
11847 }
11848 else if (val > s390_hotpatch_trampoline_halfwords_max)
11849 {
11850 error ("argument to %qs is too large (max. %d)",
11851 "-mhotpatch=", s390_hotpatch_trampoline_halfwords_max);
11852 break;
11853 }
11854 s390_hotpatch_trampoline_halfwords = val;
11855 break;
11856 }
11857 default:
11858 gcc_unreachable ();
11859 }
11860 }
11861
11862 /* Set up function hooks. */
11863 init_machine_status = s390_init_machine_status;
11864
11865 /* Architecture mode defaults according to ABI. */
11866 if (!(target_flags_explicit & MASK_ZARCH))
11867 {
11868 if (TARGET_64BIT)
11869 target_flags |= MASK_ZARCH;
11870 else
11871 target_flags &= ~MASK_ZARCH;
11872 }
11873
11874 /* Set the march default in case it hasn't been specified on
11875 cmdline. */
11876 if (s390_arch == PROCESSOR_max)
11877 {
11878 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
11879 s390_arch = TARGET_ZARCH ? PROCESSOR_2064_Z900 : PROCESSOR_9672_G5;
11880 s390_arch_flags = processor_flags_table[(int)s390_arch];
11881 }
11882
11883 /* Determine processor to tune for. */
11884 if (s390_tune == PROCESSOR_max)
11885 {
11886 s390_tune = s390_arch;
11887 s390_tune_flags = s390_arch_flags;
11888 }
11889
11890 /* Sanity checks. */
11891 if (TARGET_ZARCH && !TARGET_CPU_ZARCH)
11892 error ("z/Architecture mode not supported on %s", s390_arch_string);
11893 if (TARGET_64BIT && !TARGET_ZARCH)
11894 error ("64-bit ABI not supported in ESA/390 mode");
11895
11896 /* Use hardware DFP if available and not explicitly disabled by
11897 user. E.g. with -m31 -march=z10 -mzarch */
11898 if (!(target_flags_explicit & MASK_HARD_DFP) && TARGET_DFP)
11899 target_flags |= MASK_HARD_DFP;
11900
11901 /* Enable hardware transactions if available and not explicitly
11902 disabled by user. E.g. with -m31 -march=zEC12 -mzarch */
11903 if (!(target_flags_explicit & MASK_OPT_HTM) && TARGET_CPU_HTM && TARGET_ZARCH)
11904 target_flags |= MASK_OPT_HTM;
11905
11906 if (TARGET_HARD_DFP && !TARGET_DFP)
11907 {
11908 if (target_flags_explicit & MASK_HARD_DFP)
11909 {
11910 if (!TARGET_CPU_DFP)
11911 error ("hardware decimal floating point instructions"
11912 " not available on %s", s390_arch_string);
11913 if (!TARGET_ZARCH)
11914 error ("hardware decimal floating point instructions"
11915 " not available in ESA/390 mode");
11916 }
11917 else
11918 target_flags &= ~MASK_HARD_DFP;
11919 }
11920
11921 if ((target_flags_explicit & MASK_SOFT_FLOAT) && TARGET_SOFT_FLOAT)
11922 {
11923 if ((target_flags_explicit & MASK_HARD_DFP) && TARGET_HARD_DFP)
11924 error ("-mhard-dfp can%'t be used in conjunction with -msoft-float");
11925
11926 target_flags &= ~MASK_HARD_DFP;
11927 }
11928
11929 /* Set processor cost function. */
11930 switch (s390_tune)
11931 {
11932 case PROCESSOR_2084_Z990:
11933 s390_cost = &z990_cost;
11934 break;
11935 case PROCESSOR_2094_Z9_109:
11936 s390_cost = &z9_109_cost;
11937 break;
11938 case PROCESSOR_2097_Z10:
11939 s390_cost = &z10_cost;
11940 break;
11941 case PROCESSOR_2817_Z196:
11942 s390_cost = &z196_cost;
11943 break;
11944 case PROCESSOR_2827_ZEC12:
11945 s390_cost = &zEC12_cost;
11946 break;
11947 default:
11948 s390_cost = &z900_cost;
11949 }
11950
11951 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
11952 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
11953 "in combination");
11954
11955 if (s390_stack_size)
11956 {
11957 if (s390_stack_guard >= s390_stack_size)
11958 error ("stack size must be greater than the stack guard value");
11959 else if (s390_stack_size > 1 << 16)
11960 error ("stack size must not be greater than 64k");
11961 }
11962 else if (s390_stack_guard)
11963 error ("-mstack-guard implies use of -mstack-size");
11964
11965 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
11966 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
11967 target_flags |= MASK_LONG_DOUBLE_128;
11968 #endif
11969
11970 if (s390_tune == PROCESSOR_2097_Z10
11971 || s390_tune == PROCESSOR_2817_Z196
11972 || s390_tune == PROCESSOR_2827_ZEC12)
11973 {
11974 maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS, 100,
11975 global_options.x_param_values,
11976 global_options_set.x_param_values);
11977 maybe_set_param_value (PARAM_MAX_UNROLL_TIMES, 32,
11978 global_options.x_param_values,
11979 global_options_set.x_param_values);
11980 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 2000,
11981 global_options.x_param_values,
11982 global_options_set.x_param_values);
11983 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES, 64,
11984 global_options.x_param_values,
11985 global_options_set.x_param_values);
11986 }
11987
11988 maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH, 256,
11989 global_options.x_param_values,
11990 global_options_set.x_param_values);
11991 /* values for loop prefetching */
11992 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE, 256,
11993 global_options.x_param_values,
11994 global_options_set.x_param_values);
11995 maybe_set_param_value (PARAM_L1_CACHE_SIZE, 128,
11996 global_options.x_param_values,
11997 global_options_set.x_param_values);
11998 /* s390 has more than 2 levels and the size is much larger. Since
11999 we are always running virtualized assume that we only get a small
12000 part of the caches above l1. */
12001 maybe_set_param_value (PARAM_L2_CACHE_SIZE, 1500,
12002 global_options.x_param_values,
12003 global_options_set.x_param_values);
12004 maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO, 2,
12005 global_options.x_param_values,
12006 global_options_set.x_param_values);
12007 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES, 6,
12008 global_options.x_param_values,
12009 global_options_set.x_param_values);
12010
12011 /* This cannot reside in s390_option_optimization_table since HAVE_prefetch
12012 requires the arch flags to be evaluated already. Since prefetching
12013 is beneficial on s390, we enable it if available. */
12014 if (flag_prefetch_loop_arrays < 0 && HAVE_prefetch && optimize >= 3)
12015 flag_prefetch_loop_arrays = 1;
12016
12017 /* Use the alternative scheduling-pressure algorithm by default. */
12018 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM, 2,
12019 global_options.x_param_values,
12020 global_options_set.x_param_values);
12021
12022 if (TARGET_TPF)
12023 {
12024 /* Don't emit DWARF3/4 unless specifically selected. The TPF
12025 debuggers do not yet support DWARF 3/4. */
12026 if (!global_options_set.x_dwarf_strict)
12027 dwarf_strict = 1;
12028 if (!global_options_set.x_dwarf_version)
12029 dwarf_version = 2;
12030 }
12031
12032 /* Register a target-specific optimization-and-lowering pass
12033 to run immediately before prologue and epilogue generation.
12034
12035 Registering the pass must be done at start up. It's
12036 convenient to do it here. */
12037 opt_pass *new_pass = new pass_s390_early_mach (g);
12038 struct register_pass_info insert_pass_s390_early_mach =
12039 {
12040 new_pass, /* pass */
12041 "pro_and_epilogue", /* reference_pass_name */
12042 1, /* ref_pass_instance_number */
12043 PASS_POS_INSERT_BEFORE /* po_op */
12044 };
12045 register_pass (&insert_pass_s390_early_mach);
12046 }
12047
12048 /* Implement TARGET_USE_BY_PIECES_INFRASTRUCTURE_P. */
12049
12050 static bool
12051 s390_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size,
12052 unsigned int align ATTRIBUTE_UNUSED,
12053 enum by_pieces_operation op ATTRIBUTE_UNUSED,
12054 bool speed_p ATTRIBUTE_UNUSED)
12055 {
12056 return (size == 1 || size == 2
12057 || size == 4 || (TARGET_ZARCH && size == 8));
12058 }
12059
12060 /* Initialize GCC target structure. */
12061
12062 #undef TARGET_ASM_ALIGNED_HI_OP
12063 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
12064 #undef TARGET_ASM_ALIGNED_DI_OP
12065 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
12066 #undef TARGET_ASM_INTEGER
12067 #define TARGET_ASM_INTEGER s390_assemble_integer
12068
12069 #undef TARGET_ASM_OPEN_PAREN
12070 #define TARGET_ASM_OPEN_PAREN ""
12071
12072 #undef TARGET_ASM_CLOSE_PAREN
12073 #define TARGET_ASM_CLOSE_PAREN ""
12074
12075 #undef TARGET_OPTION_OVERRIDE
12076 #define TARGET_OPTION_OVERRIDE s390_option_override
12077
12078 #undef TARGET_ENCODE_SECTION_INFO
12079 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
12080
12081 #undef TARGET_SCALAR_MODE_SUPPORTED_P
12082 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
12083
12084 #ifdef HAVE_AS_TLS
12085 #undef TARGET_HAVE_TLS
12086 #define TARGET_HAVE_TLS true
12087 #endif
12088 #undef TARGET_CANNOT_FORCE_CONST_MEM
12089 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
12090
12091 #undef TARGET_DELEGITIMIZE_ADDRESS
12092 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
12093
12094 #undef TARGET_LEGITIMIZE_ADDRESS
12095 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
12096
12097 #undef TARGET_RETURN_IN_MEMORY
12098 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
12099
12100 #undef TARGET_INIT_BUILTINS
12101 #define TARGET_INIT_BUILTINS s390_init_builtins
12102 #undef TARGET_EXPAND_BUILTIN
12103 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
12104
12105 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
12106 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA s390_output_addr_const_extra
12107
12108 #undef TARGET_ASM_OUTPUT_MI_THUNK
12109 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
12110 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
12111 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
12112
12113 #undef TARGET_SCHED_ADJUST_PRIORITY
12114 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
12115 #undef TARGET_SCHED_ISSUE_RATE
12116 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
12117 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
12118 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
12119
12120 #undef TARGET_SCHED_VARIABLE_ISSUE
12121 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
12122 #undef TARGET_SCHED_REORDER
12123 #define TARGET_SCHED_REORDER s390_sched_reorder
12124 #undef TARGET_SCHED_INIT
12125 #define TARGET_SCHED_INIT s390_sched_init
12126
12127 #undef TARGET_CANNOT_COPY_INSN_P
12128 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
12129 #undef TARGET_RTX_COSTS
12130 #define TARGET_RTX_COSTS s390_rtx_costs
12131 #undef TARGET_ADDRESS_COST
12132 #define TARGET_ADDRESS_COST s390_address_cost
12133 #undef TARGET_REGISTER_MOVE_COST
12134 #define TARGET_REGISTER_MOVE_COST s390_register_move_cost
12135 #undef TARGET_MEMORY_MOVE_COST
12136 #define TARGET_MEMORY_MOVE_COST s390_memory_move_cost
12137
12138 #undef TARGET_MACHINE_DEPENDENT_REORG
12139 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
12140
12141 #undef TARGET_VALID_POINTER_MODE
12142 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
12143
12144 #undef TARGET_BUILD_BUILTIN_VA_LIST
12145 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
12146 #undef TARGET_EXPAND_BUILTIN_VA_START
12147 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
12148 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
12149 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
12150
12151 #undef TARGET_PROMOTE_FUNCTION_MODE
12152 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
12153 #undef TARGET_PASS_BY_REFERENCE
12154 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
12155
12156 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
12157 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
12158 #undef TARGET_FUNCTION_ARG
12159 #define TARGET_FUNCTION_ARG s390_function_arg
12160 #undef TARGET_FUNCTION_ARG_ADVANCE
12161 #define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance
12162 #undef TARGET_FUNCTION_VALUE
12163 #define TARGET_FUNCTION_VALUE s390_function_value
12164 #undef TARGET_LIBCALL_VALUE
12165 #define TARGET_LIBCALL_VALUE s390_libcall_value
12166
12167 #undef TARGET_KEEP_LEAF_WHEN_PROFILED
12168 #define TARGET_KEEP_LEAF_WHEN_PROFILED s390_keep_leaf_when_profiled
12169
12170 #undef TARGET_FIXED_CONDITION_CODE_REGS
12171 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
12172
12173 #undef TARGET_CC_MODES_COMPATIBLE
12174 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
12175
12176 #undef TARGET_INVALID_WITHIN_DOLOOP
12177 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_insn_null
12178
12179 #ifdef HAVE_AS_TLS
12180 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
12181 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
12182 #endif
12183
12184 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
12185 #undef TARGET_MANGLE_TYPE
12186 #define TARGET_MANGLE_TYPE s390_mangle_type
12187 #endif
12188
12189 #undef TARGET_SCALAR_MODE_SUPPORTED_P
12190 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
12191
12192 #undef TARGET_PREFERRED_RELOAD_CLASS
12193 #define TARGET_PREFERRED_RELOAD_CLASS s390_preferred_reload_class
12194
12195 #undef TARGET_SECONDARY_RELOAD
12196 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
12197
12198 #undef TARGET_LIBGCC_CMP_RETURN_MODE
12199 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
12200
12201 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
12202 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
12203
12204 #undef TARGET_LEGITIMATE_ADDRESS_P
12205 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
12206
12207 #undef TARGET_LEGITIMATE_CONSTANT_P
12208 #define TARGET_LEGITIMATE_CONSTANT_P s390_legitimate_constant_p
12209
12210 #undef TARGET_LRA_P
12211 #define TARGET_LRA_P s390_lra_p
12212
12213 #undef TARGET_CAN_ELIMINATE
12214 #define TARGET_CAN_ELIMINATE s390_can_eliminate
12215
12216 #undef TARGET_CONDITIONAL_REGISTER_USAGE
12217 #define TARGET_CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage
12218
12219 #undef TARGET_LOOP_UNROLL_ADJUST
12220 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
12221
12222 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
12223 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
12224 #undef TARGET_TRAMPOLINE_INIT
12225 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
12226
12227 #undef TARGET_UNWIND_WORD_MODE
12228 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
12229
12230 #undef TARGET_CANONICALIZE_COMPARISON
12231 #define TARGET_CANONICALIZE_COMPARISON s390_canonicalize_comparison
12232
12233 #undef TARGET_HARD_REGNO_SCRATCH_OK
12234 #define TARGET_HARD_REGNO_SCRATCH_OK s390_hard_regno_scratch_ok
12235
12236 #undef TARGET_ATTRIBUTE_TABLE
12237 #define TARGET_ATTRIBUTE_TABLE s390_attribute_table
12238
12239 #undef TARGET_CAN_INLINE_P
12240 #define TARGET_CAN_INLINE_P s390_can_inline_p
12241
12242 #undef TARGET_SET_UP_BY_PROLOGUE
12243 #define TARGET_SET_UP_BY_PROLOGUE s300_set_up_by_prologue
12244
12245 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
12246 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
12247 s390_use_by_pieces_infrastructure_p
12248
12249 struct gcc_target targetm = TARGET_INITIALIZER;
12250
12251 #include "gt-s390.h"
Mirror of https://gcc.gnu.org/git/gcc.git