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2014-10-16 Andrew MacLeod <amacleod@redhat.com>
[thirdparty/gcc.git] / gcc / config / s390 / s390.c
1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999-2014 Free Software Foundation, Inc.
3 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 Ulrich Weigand (uweigand@de.ibm.com) and
5 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
6
7 This file is part of GCC.
8
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 3, or (at your option) any later
12 version.
13
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
22
23 #include "config.h"
24 #include "system.h"
25 #include "coretypes.h"
26 #include "tm.h"
27 #include "rtl.h"
28 #include "tree.h"
29 #include "print-tree.h"
30 #include "stringpool.h"
31 #include "stor-layout.h"
32 #include "varasm.h"
33 #include "calls.h"
34 #include "tm_p.h"
35 #include "regs.h"
36 #include "hard-reg-set.h"
37 #include "insn-config.h"
38 #include "conditions.h"
39 #include "output.h"
40 #include "insn-attr.h"
41 #include "flags.h"
42 #include "except.h"
43 #include "hashtab.h"
44 #include "hash-set.h"
45 #include "vec.h"
46 #include "machmode.h"
47 #include "input.h"
48 #include "function.h"
49 #include "recog.h"
50 #include "expr.h"
51 #include "reload.h"
52 #include "diagnostic-core.h"
53 #include "basic-block.h"
54 #include "ggc.h"
55 #include "target.h"
56 #include "target-def.h"
57 #include "debug.h"
58 #include "langhooks.h"
59 #include "optabs.h"
60 #include "hash-table.h"
61 #include "basic-block.h"
62 #include "tree-ssa-alias.h"
63 #include "internal-fn.h"
64 #include "gimple-fold.h"
65 #include "tree-eh.h"
66 #include "gimple-expr.h"
67 #include "is-a.h"
68 #include "gimple.h"
69 #include "gimplify.h"
70 #include "df.h"
71 #include "params.h"
72 #include "cfgloop.h"
73 #include "opts.h"
74 #include "tree-pass.h"
75 #include "context.h"
76 #include "builtins.h"
77
78 /* Define the specific costs for a given cpu. */
79
80 struct processor_costs
81 {
82 /* multiplication */
83 const int m; /* cost of an M instruction. */
84 const int mghi; /* cost of an MGHI instruction. */
85 const int mh; /* cost of an MH instruction. */
86 const int mhi; /* cost of an MHI instruction. */
87 const int ml; /* cost of an ML instruction. */
88 const int mr; /* cost of an MR instruction. */
89 const int ms; /* cost of an MS instruction. */
90 const int msg; /* cost of an MSG instruction. */
91 const int msgf; /* cost of an MSGF instruction. */
92 const int msgfr; /* cost of an MSGFR instruction. */
93 const int msgr; /* cost of an MSGR instruction. */
94 const int msr; /* cost of an MSR instruction. */
95 const int mult_df; /* cost of multiplication in DFmode. */
96 const int mxbr;
97 /* square root */
98 const int sqxbr; /* cost of square root in TFmode. */
99 const int sqdbr; /* cost of square root in DFmode. */
100 const int sqebr; /* cost of square root in SFmode. */
101 /* multiply and add */
102 const int madbr; /* cost of multiply and add in DFmode. */
103 const int maebr; /* cost of multiply and add in SFmode. */
104 /* division */
105 const int dxbr;
106 const int ddbr;
107 const int debr;
108 const int dlgr;
109 const int dlr;
110 const int dr;
111 const int dsgfr;
112 const int dsgr;
113 };
114
115 const struct processor_costs *s390_cost;
116
117 static const
118 struct processor_costs z900_cost =
119 {
120 COSTS_N_INSNS (5), /* M */
121 COSTS_N_INSNS (10), /* MGHI */
122 COSTS_N_INSNS (5), /* MH */
123 COSTS_N_INSNS (4), /* MHI */
124 COSTS_N_INSNS (5), /* ML */
125 COSTS_N_INSNS (5), /* MR */
126 COSTS_N_INSNS (4), /* MS */
127 COSTS_N_INSNS (15), /* MSG */
128 COSTS_N_INSNS (7), /* MSGF */
129 COSTS_N_INSNS (7), /* MSGFR */
130 COSTS_N_INSNS (10), /* MSGR */
131 COSTS_N_INSNS (4), /* MSR */
132 COSTS_N_INSNS (7), /* multiplication in DFmode */
133 COSTS_N_INSNS (13), /* MXBR */
134 COSTS_N_INSNS (136), /* SQXBR */
135 COSTS_N_INSNS (44), /* SQDBR */
136 COSTS_N_INSNS (35), /* SQEBR */
137 COSTS_N_INSNS (18), /* MADBR */
138 COSTS_N_INSNS (13), /* MAEBR */
139 COSTS_N_INSNS (134), /* DXBR */
140 COSTS_N_INSNS (30), /* DDBR */
141 COSTS_N_INSNS (27), /* DEBR */
142 COSTS_N_INSNS (220), /* DLGR */
143 COSTS_N_INSNS (34), /* DLR */
144 COSTS_N_INSNS (34), /* DR */
145 COSTS_N_INSNS (32), /* DSGFR */
146 COSTS_N_INSNS (32), /* DSGR */
147 };
148
149 static const
150 struct processor_costs z990_cost =
151 {
152 COSTS_N_INSNS (4), /* M */
153 COSTS_N_INSNS (2), /* MGHI */
154 COSTS_N_INSNS (2), /* MH */
155 COSTS_N_INSNS (2), /* MHI */
156 COSTS_N_INSNS (4), /* ML */
157 COSTS_N_INSNS (4), /* MR */
158 COSTS_N_INSNS (5), /* MS */
159 COSTS_N_INSNS (6), /* MSG */
160 COSTS_N_INSNS (4), /* MSGF */
161 COSTS_N_INSNS (4), /* MSGFR */
162 COSTS_N_INSNS (4), /* MSGR */
163 COSTS_N_INSNS (4), /* MSR */
164 COSTS_N_INSNS (1), /* multiplication in DFmode */
165 COSTS_N_INSNS (28), /* MXBR */
166 COSTS_N_INSNS (130), /* SQXBR */
167 COSTS_N_INSNS (66), /* SQDBR */
168 COSTS_N_INSNS (38), /* SQEBR */
169 COSTS_N_INSNS (1), /* MADBR */
170 COSTS_N_INSNS (1), /* MAEBR */
171 COSTS_N_INSNS (60), /* DXBR */
172 COSTS_N_INSNS (40), /* DDBR */
173 COSTS_N_INSNS (26), /* DEBR */
174 COSTS_N_INSNS (176), /* DLGR */
175 COSTS_N_INSNS (31), /* DLR */
176 COSTS_N_INSNS (31), /* DR */
177 COSTS_N_INSNS (31), /* DSGFR */
178 COSTS_N_INSNS (31), /* DSGR */
179 };
180
181 static const
182 struct processor_costs z9_109_cost =
183 {
184 COSTS_N_INSNS (4), /* M */
185 COSTS_N_INSNS (2), /* MGHI */
186 COSTS_N_INSNS (2), /* MH */
187 COSTS_N_INSNS (2), /* MHI */
188 COSTS_N_INSNS (4), /* ML */
189 COSTS_N_INSNS (4), /* MR */
190 COSTS_N_INSNS (5), /* MS */
191 COSTS_N_INSNS (6), /* MSG */
192 COSTS_N_INSNS (4), /* MSGF */
193 COSTS_N_INSNS (4), /* MSGFR */
194 COSTS_N_INSNS (4), /* MSGR */
195 COSTS_N_INSNS (4), /* MSR */
196 COSTS_N_INSNS (1), /* multiplication in DFmode */
197 COSTS_N_INSNS (28), /* MXBR */
198 COSTS_N_INSNS (130), /* SQXBR */
199 COSTS_N_INSNS (66), /* SQDBR */
200 COSTS_N_INSNS (38), /* SQEBR */
201 COSTS_N_INSNS (1), /* MADBR */
202 COSTS_N_INSNS (1), /* MAEBR */
203 COSTS_N_INSNS (60), /* DXBR */
204 COSTS_N_INSNS (40), /* DDBR */
205 COSTS_N_INSNS (26), /* DEBR */
206 COSTS_N_INSNS (30), /* DLGR */
207 COSTS_N_INSNS (23), /* DLR */
208 COSTS_N_INSNS (23), /* DR */
209 COSTS_N_INSNS (24), /* DSGFR */
210 COSTS_N_INSNS (24), /* DSGR */
211 };
212
213 static const
214 struct processor_costs z10_cost =
215 {
216 COSTS_N_INSNS (10), /* M */
217 COSTS_N_INSNS (10), /* MGHI */
218 COSTS_N_INSNS (10), /* MH */
219 COSTS_N_INSNS (10), /* MHI */
220 COSTS_N_INSNS (10), /* ML */
221 COSTS_N_INSNS (10), /* MR */
222 COSTS_N_INSNS (10), /* MS */
223 COSTS_N_INSNS (10), /* MSG */
224 COSTS_N_INSNS (10), /* MSGF */
225 COSTS_N_INSNS (10), /* MSGFR */
226 COSTS_N_INSNS (10), /* MSGR */
227 COSTS_N_INSNS (10), /* MSR */
228 COSTS_N_INSNS (1) , /* multiplication in DFmode */
229 COSTS_N_INSNS (50), /* MXBR */
230 COSTS_N_INSNS (120), /* SQXBR */
231 COSTS_N_INSNS (52), /* SQDBR */
232 COSTS_N_INSNS (38), /* SQEBR */
233 COSTS_N_INSNS (1), /* MADBR */
234 COSTS_N_INSNS (1), /* MAEBR */
235 COSTS_N_INSNS (111), /* DXBR */
236 COSTS_N_INSNS (39), /* DDBR */
237 COSTS_N_INSNS (32), /* DEBR */
238 COSTS_N_INSNS (160), /* DLGR */
239 COSTS_N_INSNS (71), /* DLR */
240 COSTS_N_INSNS (71), /* DR */
241 COSTS_N_INSNS (71), /* DSGFR */
242 COSTS_N_INSNS (71), /* DSGR */
243 };
244
245 static const
246 struct processor_costs z196_cost =
247 {
248 COSTS_N_INSNS (7), /* M */
249 COSTS_N_INSNS (5), /* MGHI */
250 COSTS_N_INSNS (5), /* MH */
251 COSTS_N_INSNS (5), /* MHI */
252 COSTS_N_INSNS (7), /* ML */
253 COSTS_N_INSNS (7), /* MR */
254 COSTS_N_INSNS (6), /* MS */
255 COSTS_N_INSNS (8), /* MSG */
256 COSTS_N_INSNS (6), /* MSGF */
257 COSTS_N_INSNS (6), /* MSGFR */
258 COSTS_N_INSNS (8), /* MSGR */
259 COSTS_N_INSNS (6), /* MSR */
260 COSTS_N_INSNS (1) , /* multiplication in DFmode */
261 COSTS_N_INSNS (40), /* MXBR B+40 */
262 COSTS_N_INSNS (100), /* SQXBR B+100 */
263 COSTS_N_INSNS (42), /* SQDBR B+42 */
264 COSTS_N_INSNS (28), /* SQEBR B+28 */
265 COSTS_N_INSNS (1), /* MADBR B */
266 COSTS_N_INSNS (1), /* MAEBR B */
267 COSTS_N_INSNS (101), /* DXBR B+101 */
268 COSTS_N_INSNS (29), /* DDBR */
269 COSTS_N_INSNS (22), /* DEBR */
270 COSTS_N_INSNS (160), /* DLGR cracked */
271 COSTS_N_INSNS (160), /* DLR cracked */
272 COSTS_N_INSNS (160), /* DR expanded */
273 COSTS_N_INSNS (160), /* DSGFR cracked */
274 COSTS_N_INSNS (160), /* DSGR cracked */
275 };
276
277 static const
278 struct processor_costs zEC12_cost =
279 {
280 COSTS_N_INSNS (7), /* M */
281 COSTS_N_INSNS (5), /* MGHI */
282 COSTS_N_INSNS (5), /* MH */
283 COSTS_N_INSNS (5), /* MHI */
284 COSTS_N_INSNS (7), /* ML */
285 COSTS_N_INSNS (7), /* MR */
286 COSTS_N_INSNS (6), /* MS */
287 COSTS_N_INSNS (8), /* MSG */
288 COSTS_N_INSNS (6), /* MSGF */
289 COSTS_N_INSNS (6), /* MSGFR */
290 COSTS_N_INSNS (8), /* MSGR */
291 COSTS_N_INSNS (6), /* MSR */
292 COSTS_N_INSNS (1) , /* multiplication in DFmode */
293 COSTS_N_INSNS (40), /* MXBR B+40 */
294 COSTS_N_INSNS (100), /* SQXBR B+100 */
295 COSTS_N_INSNS (42), /* SQDBR B+42 */
296 COSTS_N_INSNS (28), /* SQEBR B+28 */
297 COSTS_N_INSNS (1), /* MADBR B */
298 COSTS_N_INSNS (1), /* MAEBR B */
299 COSTS_N_INSNS (131), /* DXBR B+131 */
300 COSTS_N_INSNS (29), /* DDBR */
301 COSTS_N_INSNS (22), /* DEBR */
302 COSTS_N_INSNS (160), /* DLGR cracked */
303 COSTS_N_INSNS (160), /* DLR cracked */
304 COSTS_N_INSNS (160), /* DR expanded */
305 COSTS_N_INSNS (160), /* DSGFR cracked */
306 COSTS_N_INSNS (160), /* DSGR cracked */
307 };
308
309 extern int reload_completed;
310
311 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
312 static rtx_insn *last_scheduled_insn;
313
314 /* Structure used to hold the components of a S/390 memory
315 address. A legitimate address on S/390 is of the general
316 form
317 base + index + displacement
318 where any of the components is optional.
319
320 base and index are registers of the class ADDR_REGS,
321 displacement is an unsigned 12-bit immediate constant. */
322
323 struct s390_address
324 {
325 rtx base;
326 rtx indx;
327 rtx disp;
328 bool pointer;
329 bool literal_pool;
330 };
331
332 /* The following structure is embedded in the machine
333 specific part of struct function. */
334
335 struct GTY (()) s390_frame_layout
336 {
337 /* Offset within stack frame. */
338 HOST_WIDE_INT gprs_offset;
339 HOST_WIDE_INT f0_offset;
340 HOST_WIDE_INT f4_offset;
341 HOST_WIDE_INT f8_offset;
342 HOST_WIDE_INT backchain_offset;
343
344 /* Number of first and last gpr where slots in the register
345 save area are reserved for. */
346 int first_save_gpr_slot;
347 int last_save_gpr_slot;
348
349 /* Location (FP register number) where GPRs (r0-r15) should
350 be saved to.
351 0 - does not need to be saved at all
352 -1 - stack slot */
353 signed char gpr_save_slots[16];
354
355 /* Number of first and last gpr to be saved, restored. */
356 int first_save_gpr;
357 int first_restore_gpr;
358 int last_save_gpr;
359 int last_restore_gpr;
360
361 /* Bits standing for floating point registers. Set, if the
362 respective register has to be saved. Starting with reg 16 (f0)
363 at the rightmost bit.
364 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
365 fpr 15 13 11 9 14 12 10 8 7 5 3 1 6 4 2 0
366 reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 */
367 unsigned int fpr_bitmap;
368
369 /* Number of floating point registers f8-f15 which must be saved. */
370 int high_fprs;
371
372 /* Set if return address needs to be saved.
373 This flag is set by s390_return_addr_rtx if it could not use
374 the initial value of r14 and therefore depends on r14 saved
375 to the stack. */
376 bool save_return_addr_p;
377
378 /* Size of stack frame. */
379 HOST_WIDE_INT frame_size;
380 };
381
382 /* Define the structure for the machine field in struct function. */
383
384 struct GTY(()) machine_function
385 {
386 struct s390_frame_layout frame_layout;
387
388 /* Literal pool base register. */
389 rtx base_reg;
390
391 /* True if we may need to perform branch splitting. */
392 bool split_branches_pending_p;
393
394 bool has_landing_pad_p;
395
396 /* True if the current function may contain a tbegin clobbering
397 FPRs. */
398 bool tbegin_p;
399 };
400
401 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
402
403 #define cfun_frame_layout (cfun->machine->frame_layout)
404 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
405 #define cfun_save_arg_fprs_p (!!(TARGET_64BIT \
406 ? cfun_frame_layout.fpr_bitmap & 0x0f \
407 : cfun_frame_layout.fpr_bitmap & 0x03))
408 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
409 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
410 #define cfun_set_fpr_save(REGNO) (cfun->machine->frame_layout.fpr_bitmap |= \
411 (1 << (REGNO - FPR0_REGNUM)))
412 #define cfun_fpr_save_p(REGNO) (!!(cfun->machine->frame_layout.fpr_bitmap & \
413 (1 << (REGNO - FPR0_REGNUM))))
414 #define cfun_gpr_save_slot(REGNO) \
415 cfun->machine->frame_layout.gpr_save_slots[REGNO]
416
417 /* Number of GPRs and FPRs used for argument passing. */
418 #define GP_ARG_NUM_REG 5
419 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
420
421 /* A couple of shortcuts. */
422 #define CONST_OK_FOR_J(x) \
423 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
424 #define CONST_OK_FOR_K(x) \
425 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
426 #define CONST_OK_FOR_Os(x) \
427 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
428 #define CONST_OK_FOR_Op(x) \
429 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
430 #define CONST_OK_FOR_On(x) \
431 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
432
433 #define REGNO_PAIR_OK(REGNO, MODE) \
434 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
435
436 /* That's the read ahead of the dynamic branch prediction unit in
437 bytes on a z10 (or higher) CPU. */
438 #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
439
440 static const int s390_hotpatch_trampoline_halfwords_default = 12;
441 static const int s390_hotpatch_trampoline_halfwords_max = 1000000;
442 static int s390_hotpatch_trampoline_halfwords = -1;
443
444 /* Return the argument of the given hotpatch attribute or the default value if
445 no argument is present. */
446
447 static inline int
448 get_hotpatch_attribute (tree hotpatch_attr)
449 {
450 const_tree args;
451
452 args = TREE_VALUE (hotpatch_attr);
453
454 return (args) ?
455 TREE_INT_CST_LOW (TREE_VALUE (args)):
456 s390_hotpatch_trampoline_halfwords_default;
457 }
458
459 /* Check whether the hotpatch attribute is applied to a function and, if it has
460 an argument, the argument is valid. */
461
462 static tree
463 s390_handle_hotpatch_attribute (tree *node, tree name, tree args,
464 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
465 {
466 if (TREE_CODE (*node) != FUNCTION_DECL)
467 {
468 warning (OPT_Wattributes, "%qE attribute only applies to functions",
469 name);
470 *no_add_attrs = true;
471 }
472 else if (args)
473 {
474 tree expr = TREE_VALUE (args);
475
476 if (TREE_CODE (expr) != INTEGER_CST
477 || !INTEGRAL_TYPE_P (TREE_TYPE (expr))
478 || wi::gtu_p (expr, s390_hotpatch_trampoline_halfwords_max))
479 {
480 error ("requested %qE attribute is not a non-negative integer"
481 " constant or too large (max. %d)", name,
482 s390_hotpatch_trampoline_halfwords_max);
483 *no_add_attrs = true;
484 }
485 }
486
487 return NULL_TREE;
488 }
489
490 static const struct attribute_spec s390_attribute_table[] = {
491 { "hotpatch", 0, 1, true, false, false, s390_handle_hotpatch_attribute, false
492 },
493 /* End element. */
494 { NULL, 0, 0, false, false, false, NULL, false }
495 };
496
497 /* Return the alignment for LABEL. We default to the -falign-labels
498 value except for the literal pool base label. */
499 int
500 s390_label_align (rtx label)
501 {
502 rtx_insn *prev_insn = prev_active_insn (label);
503 rtx set, src;
504
505 if (prev_insn == NULL_RTX)
506 goto old;
507
508 set = single_set (prev_insn);
509
510 if (set == NULL_RTX)
511 goto old;
512
513 src = SET_SRC (set);
514
515 /* Don't align literal pool base labels. */
516 if (GET_CODE (src) == UNSPEC
517 && XINT (src, 1) == UNSPEC_MAIN_BASE)
518 return 0;
519
520 old:
521 return align_labels_log;
522 }
523
524 static enum machine_mode
525 s390_libgcc_cmp_return_mode (void)
526 {
527 return TARGET_64BIT ? DImode : SImode;
528 }
529
530 static enum machine_mode
531 s390_libgcc_shift_count_mode (void)
532 {
533 return TARGET_64BIT ? DImode : SImode;
534 }
535
536 static enum machine_mode
537 s390_unwind_word_mode (void)
538 {
539 return TARGET_64BIT ? DImode : SImode;
540 }
541
542 /* Return true if the back end supports mode MODE. */
543 static bool
544 s390_scalar_mode_supported_p (enum machine_mode mode)
545 {
546 /* In contrast to the default implementation reject TImode constants on 31bit
547 TARGET_ZARCH for ABI compliance. */
548 if (!TARGET_64BIT && TARGET_ZARCH && mode == TImode)
549 return false;
550
551 if (DECIMAL_FLOAT_MODE_P (mode))
552 return default_decimal_float_supported_p ();
553
554 return default_scalar_mode_supported_p (mode);
555 }
556
557 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
558
559 void
560 s390_set_has_landing_pad_p (bool value)
561 {
562 cfun->machine->has_landing_pad_p = value;
563 }
564
565 /* If two condition code modes are compatible, return a condition code
566 mode which is compatible with both. Otherwise, return
567 VOIDmode. */
568
569 static enum machine_mode
570 s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
571 {
572 if (m1 == m2)
573 return m1;
574
575 switch (m1)
576 {
577 case CCZmode:
578 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
579 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
580 return m2;
581 return VOIDmode;
582
583 case CCSmode:
584 case CCUmode:
585 case CCTmode:
586 case CCSRmode:
587 case CCURmode:
588 case CCZ1mode:
589 if (m2 == CCZmode)
590 return m1;
591
592 return VOIDmode;
593
594 default:
595 return VOIDmode;
596 }
597 return VOIDmode;
598 }
599
600 /* Return true if SET either doesn't set the CC register, or else
601 the source and destination have matching CC modes and that
602 CC mode is at least as constrained as REQ_MODE. */
603
604 static bool
605 s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
606 {
607 enum machine_mode set_mode;
608
609 gcc_assert (GET_CODE (set) == SET);
610
611 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
612 return 1;
613
614 set_mode = GET_MODE (SET_DEST (set));
615 switch (set_mode)
616 {
617 case CCSmode:
618 case CCSRmode:
619 case CCUmode:
620 case CCURmode:
621 case CCLmode:
622 case CCL1mode:
623 case CCL2mode:
624 case CCL3mode:
625 case CCT1mode:
626 case CCT2mode:
627 case CCT3mode:
628 if (req_mode != set_mode)
629 return 0;
630 break;
631
632 case CCZmode:
633 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
634 && req_mode != CCSRmode && req_mode != CCURmode)
635 return 0;
636 break;
637
638 case CCAPmode:
639 case CCANmode:
640 if (req_mode != CCAmode)
641 return 0;
642 break;
643
644 default:
645 gcc_unreachable ();
646 }
647
648 return (GET_MODE (SET_SRC (set)) == set_mode);
649 }
650
651 /* Return true if every SET in INSN that sets the CC register
652 has source and destination with matching CC modes and that
653 CC mode is at least as constrained as REQ_MODE.
654 If REQ_MODE is VOIDmode, always return false. */
655
656 bool
657 s390_match_ccmode (rtx_insn *insn, enum machine_mode req_mode)
658 {
659 int i;
660
661 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
662 if (req_mode == VOIDmode)
663 return false;
664
665 if (GET_CODE (PATTERN (insn)) == SET)
666 return s390_match_ccmode_set (PATTERN (insn), req_mode);
667
668 if (GET_CODE (PATTERN (insn)) == PARALLEL)
669 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
670 {
671 rtx set = XVECEXP (PATTERN (insn), 0, i);
672 if (GET_CODE (set) == SET)
673 if (!s390_match_ccmode_set (set, req_mode))
674 return false;
675 }
676
677 return true;
678 }
679
680 /* If a test-under-mask instruction can be used to implement
681 (compare (and ... OP1) OP2), return the CC mode required
682 to do that. Otherwise, return VOIDmode.
683 MIXED is true if the instruction can distinguish between
684 CC1 and CC2 for mixed selected bits (TMxx), it is false
685 if the instruction cannot (TM). */
686
687 enum machine_mode
688 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
689 {
690 int bit0, bit1;
691
692 /* ??? Fixme: should work on CONST_DOUBLE as well. */
693 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
694 return VOIDmode;
695
696 /* Selected bits all zero: CC0.
697 e.g.: int a; if ((a & (16 + 128)) == 0) */
698 if (INTVAL (op2) == 0)
699 return CCTmode;
700
701 /* Selected bits all one: CC3.
702 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
703 if (INTVAL (op2) == INTVAL (op1))
704 return CCT3mode;
705
706 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
707 int a;
708 if ((a & (16 + 128)) == 16) -> CCT1
709 if ((a & (16 + 128)) == 128) -> CCT2 */
710 if (mixed)
711 {
712 bit1 = exact_log2 (INTVAL (op2));
713 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
714 if (bit0 != -1 && bit1 != -1)
715 return bit0 > bit1 ? CCT1mode : CCT2mode;
716 }
717
718 return VOIDmode;
719 }
720
721 /* Given a comparison code OP (EQ, NE, etc.) and the operands
722 OP0 and OP1 of a COMPARE, return the mode to be used for the
723 comparison. */
724
725 enum machine_mode
726 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
727 {
728 switch (code)
729 {
730 case EQ:
731 case NE:
732 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
733 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
734 return CCAPmode;
735 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
736 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
737 return CCAPmode;
738 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
739 || GET_CODE (op1) == NEG)
740 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
741 return CCLmode;
742
743 if (GET_CODE (op0) == AND)
744 {
745 /* Check whether we can potentially do it via TM. */
746 enum machine_mode ccmode;
747 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
748 if (ccmode != VOIDmode)
749 {
750 /* Relax CCTmode to CCZmode to allow fall-back to AND
751 if that turns out to be beneficial. */
752 return ccmode == CCTmode ? CCZmode : ccmode;
753 }
754 }
755
756 if (register_operand (op0, HImode)
757 && GET_CODE (op1) == CONST_INT
758 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
759 return CCT3mode;
760 if (register_operand (op0, QImode)
761 && GET_CODE (op1) == CONST_INT
762 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
763 return CCT3mode;
764
765 return CCZmode;
766
767 case LE:
768 case LT:
769 case GE:
770 case GT:
771 /* The only overflow condition of NEG and ABS happens when
772 -INT_MAX is used as parameter, which stays negative. So
773 we have an overflow from a positive value to a negative.
774 Using CCAP mode the resulting cc can be used for comparisons. */
775 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
776 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
777 return CCAPmode;
778
779 /* If constants are involved in an add instruction it is possible to use
780 the resulting cc for comparisons with zero. Knowing the sign of the
781 constant the overflow behavior gets predictable. e.g.:
782 int a, b; if ((b = a + c) > 0)
783 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
784 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
785 && (CONST_OK_FOR_K (INTVAL (XEXP (op0, 1)))
786 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (XEXP (op0, 1)), 'O', "Os")
787 /* Avoid INT32_MIN on 32 bit. */
788 && (!TARGET_ZARCH || INTVAL (XEXP (op0, 1)) != -0x7fffffff - 1))))
789 {
790 if (INTVAL (XEXP((op0), 1)) < 0)
791 return CCANmode;
792 else
793 return CCAPmode;
794 }
795 /* Fall through. */
796 case UNORDERED:
797 case ORDERED:
798 case UNEQ:
799 case UNLE:
800 case UNLT:
801 case UNGE:
802 case UNGT:
803 case LTGT:
804 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
805 && GET_CODE (op1) != CONST_INT)
806 return CCSRmode;
807 return CCSmode;
808
809 case LTU:
810 case GEU:
811 if (GET_CODE (op0) == PLUS
812 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
813 return CCL1mode;
814
815 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
816 && GET_CODE (op1) != CONST_INT)
817 return CCURmode;
818 return CCUmode;
819
820 case LEU:
821 case GTU:
822 if (GET_CODE (op0) == MINUS
823 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
824 return CCL2mode;
825
826 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
827 && GET_CODE (op1) != CONST_INT)
828 return CCURmode;
829 return CCUmode;
830
831 default:
832 gcc_unreachable ();
833 }
834 }
835
836 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
837 that we can implement more efficiently. */
838
839 static void
840 s390_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
841 bool op0_preserve_value)
842 {
843 if (op0_preserve_value)
844 return;
845
846 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
847 if ((*code == EQ || *code == NE)
848 && *op1 == const0_rtx
849 && GET_CODE (*op0) == ZERO_EXTRACT
850 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
851 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
852 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
853 {
854 rtx inner = XEXP (*op0, 0);
855 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
856 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
857 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
858
859 if (len > 0 && len < modesize
860 && pos >= 0 && pos + len <= modesize
861 && modesize <= HOST_BITS_PER_WIDE_INT)
862 {
863 unsigned HOST_WIDE_INT block;
864 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
865 block <<= modesize - pos - len;
866
867 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
868 gen_int_mode (block, GET_MODE (inner)));
869 }
870 }
871
872 /* Narrow AND of memory against immediate to enable TM. */
873 if ((*code == EQ || *code == NE)
874 && *op1 == const0_rtx
875 && GET_CODE (*op0) == AND
876 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
877 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
878 {
879 rtx inner = XEXP (*op0, 0);
880 rtx mask = XEXP (*op0, 1);
881
882 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
883 if (GET_CODE (inner) == SUBREG
884 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
885 && (GET_MODE_SIZE (GET_MODE (inner))
886 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
887 && ((INTVAL (mask)
888 & GET_MODE_MASK (GET_MODE (inner))
889 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
890 == 0))
891 inner = SUBREG_REG (inner);
892
893 /* Do not change volatile MEMs. */
894 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
895 {
896 int part = s390_single_part (XEXP (*op0, 1),
897 GET_MODE (inner), QImode, 0);
898 if (part >= 0)
899 {
900 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
901 inner = adjust_address_nv (inner, QImode, part);
902 *op0 = gen_rtx_AND (QImode, inner, mask);
903 }
904 }
905 }
906
907 /* Narrow comparisons against 0xffff to HImode if possible. */
908 if ((*code == EQ || *code == NE)
909 && GET_CODE (*op1) == CONST_INT
910 && INTVAL (*op1) == 0xffff
911 && SCALAR_INT_MODE_P (GET_MODE (*op0))
912 && (nonzero_bits (*op0, GET_MODE (*op0))
913 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
914 {
915 *op0 = gen_lowpart (HImode, *op0);
916 *op1 = constm1_rtx;
917 }
918
919 /* Remove redundant UNSPEC_STRCMPCC_TO_INT conversions if possible. */
920 if (GET_CODE (*op0) == UNSPEC
921 && XINT (*op0, 1) == UNSPEC_STRCMPCC_TO_INT
922 && XVECLEN (*op0, 0) == 1
923 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
924 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
925 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
926 && *op1 == const0_rtx)
927 {
928 enum rtx_code new_code = UNKNOWN;
929 switch (*code)
930 {
931 case EQ: new_code = EQ; break;
932 case NE: new_code = NE; break;
933 case LT: new_code = GTU; break;
934 case GT: new_code = LTU; break;
935 case LE: new_code = GEU; break;
936 case GE: new_code = LEU; break;
937 default: break;
938 }
939
940 if (new_code != UNKNOWN)
941 {
942 *op0 = XVECEXP (*op0, 0, 0);
943 *code = new_code;
944 }
945 }
946
947 /* Remove redundant UNSPEC_CC_TO_INT conversions if possible. */
948 if (GET_CODE (*op0) == UNSPEC
949 && XINT (*op0, 1) == UNSPEC_CC_TO_INT
950 && XVECLEN (*op0, 0) == 1
951 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
952 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
953 && CONST_INT_P (*op1))
954 {
955 enum rtx_code new_code = UNKNOWN;
956 switch (GET_MODE (XVECEXP (*op0, 0, 0)))
957 {
958 case CCZmode:
959 case CCRAWmode:
960 switch (*code)
961 {
962 case EQ: new_code = EQ; break;
963 case NE: new_code = NE; break;
964 default: break;
965 }
966 break;
967 default: break;
968 }
969
970 if (new_code != UNKNOWN)
971 {
972 /* For CCRAWmode put the required cc mask into the second
973 operand. */
974 if (GET_MODE (XVECEXP (*op0, 0, 0)) == CCRAWmode
975 && INTVAL (*op1) >= 0 && INTVAL (*op1) <= 3)
976 *op1 = gen_rtx_CONST_INT (VOIDmode, 1 << (3 - INTVAL (*op1)));
977 *op0 = XVECEXP (*op0, 0, 0);
978 *code = new_code;
979 }
980 }
981
982 /* Simplify cascaded EQ, NE with const0_rtx. */
983 if ((*code == NE || *code == EQ)
984 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
985 && GET_MODE (*op0) == SImode
986 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
987 && REG_P (XEXP (*op0, 0))
988 && XEXP (*op0, 1) == const0_rtx
989 && *op1 == const0_rtx)
990 {
991 if ((*code == EQ && GET_CODE (*op0) == NE)
992 || (*code == NE && GET_CODE (*op0) == EQ))
993 *code = EQ;
994 else
995 *code = NE;
996 *op0 = XEXP (*op0, 0);
997 }
998
999 /* Prefer register over memory as first operand. */
1000 if (MEM_P (*op0) && REG_P (*op1))
1001 {
1002 rtx tem = *op0; *op0 = *op1; *op1 = tem;
1003 *code = (int)swap_condition ((enum rtx_code)*code);
1004 }
1005 }
1006
1007 /* Emit a compare instruction suitable to implement the comparison
1008 OP0 CODE OP1. Return the correct condition RTL to be placed in
1009 the IF_THEN_ELSE of the conditional branch testing the result. */
1010
1011 rtx
1012 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
1013 {
1014 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
1015 rtx cc;
1016
1017 /* Do not output a redundant compare instruction if a compare_and_swap
1018 pattern already computed the result and the machine modes are compatible. */
1019 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
1020 {
1021 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), mode)
1022 == GET_MODE (op0));
1023 cc = op0;
1024 }
1025 else
1026 {
1027 cc = gen_rtx_REG (mode, CC_REGNUM);
1028 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
1029 }
1030
1031 return gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
1032 }
1033
1034 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
1035 matches CMP.
1036 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
1037 conditional branch testing the result. */
1038
1039 static rtx
1040 s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem,
1041 rtx cmp, rtx new_rtx)
1042 {
1043 emit_insn (gen_atomic_compare_and_swapsi_internal (old, mem, cmp, new_rtx));
1044 return s390_emit_compare (code, gen_rtx_REG (CCZ1mode, CC_REGNUM),
1045 const0_rtx);
1046 }
1047
1048 /* Emit a jump instruction to TARGET and return it. If COND is
1049 NULL_RTX, emit an unconditional jump, else a conditional jump under
1050 condition COND. */
1051
1052 rtx_insn *
1053 s390_emit_jump (rtx target, rtx cond)
1054 {
1055 rtx insn;
1056
1057 target = gen_rtx_LABEL_REF (VOIDmode, target);
1058 if (cond)
1059 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
1060
1061 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
1062 return emit_jump_insn (insn);
1063 }
1064
1065 /* Return branch condition mask to implement a branch
1066 specified by CODE. Return -1 for invalid comparisons. */
1067
1068 int
1069 s390_branch_condition_mask (rtx code)
1070 {
1071 const int CC0 = 1 << 3;
1072 const int CC1 = 1 << 2;
1073 const int CC2 = 1 << 1;
1074 const int CC3 = 1 << 0;
1075
1076 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
1077 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
1078 gcc_assert (XEXP (code, 1) == const0_rtx
1079 || (GET_MODE (XEXP (code, 0)) == CCRAWmode
1080 && CONST_INT_P (XEXP (code, 1))));
1081
1082
1083 switch (GET_MODE (XEXP (code, 0)))
1084 {
1085 case CCZmode:
1086 case CCZ1mode:
1087 switch (GET_CODE (code))
1088 {
1089 case EQ: return CC0;
1090 case NE: return CC1 | CC2 | CC3;
1091 default: return -1;
1092 }
1093 break;
1094
1095 case CCT1mode:
1096 switch (GET_CODE (code))
1097 {
1098 case EQ: return CC1;
1099 case NE: return CC0 | CC2 | CC3;
1100 default: return -1;
1101 }
1102 break;
1103
1104 case CCT2mode:
1105 switch (GET_CODE (code))
1106 {
1107 case EQ: return CC2;
1108 case NE: return CC0 | CC1 | CC3;
1109 default: return -1;
1110 }
1111 break;
1112
1113 case CCT3mode:
1114 switch (GET_CODE (code))
1115 {
1116 case EQ: return CC3;
1117 case NE: return CC0 | CC1 | CC2;
1118 default: return -1;
1119 }
1120 break;
1121
1122 case CCLmode:
1123 switch (GET_CODE (code))
1124 {
1125 case EQ: return CC0 | CC2;
1126 case NE: return CC1 | CC3;
1127 default: return -1;
1128 }
1129 break;
1130
1131 case CCL1mode:
1132 switch (GET_CODE (code))
1133 {
1134 case LTU: return CC2 | CC3; /* carry */
1135 case GEU: return CC0 | CC1; /* no carry */
1136 default: return -1;
1137 }
1138 break;
1139
1140 case CCL2mode:
1141 switch (GET_CODE (code))
1142 {
1143 case GTU: return CC0 | CC1; /* borrow */
1144 case LEU: return CC2 | CC3; /* no borrow */
1145 default: return -1;
1146 }
1147 break;
1148
1149 case CCL3mode:
1150 switch (GET_CODE (code))
1151 {
1152 case EQ: return CC0 | CC2;
1153 case NE: return CC1 | CC3;
1154 case LTU: return CC1;
1155 case GTU: return CC3;
1156 case LEU: return CC1 | CC2;
1157 case GEU: return CC2 | CC3;
1158 default: return -1;
1159 }
1160
1161 case CCUmode:
1162 switch (GET_CODE (code))
1163 {
1164 case EQ: return CC0;
1165 case NE: return CC1 | CC2 | CC3;
1166 case LTU: return CC1;
1167 case GTU: return CC2;
1168 case LEU: return CC0 | CC1;
1169 case GEU: return CC0 | CC2;
1170 default: return -1;
1171 }
1172 break;
1173
1174 case CCURmode:
1175 switch (GET_CODE (code))
1176 {
1177 case EQ: return CC0;
1178 case NE: return CC2 | CC1 | CC3;
1179 case LTU: return CC2;
1180 case GTU: return CC1;
1181 case LEU: return CC0 | CC2;
1182 case GEU: return CC0 | CC1;
1183 default: return -1;
1184 }
1185 break;
1186
1187 case CCAPmode:
1188 switch (GET_CODE (code))
1189 {
1190 case EQ: return CC0;
1191 case NE: return CC1 | CC2 | CC3;
1192 case LT: return CC1 | CC3;
1193 case GT: return CC2;
1194 case LE: return CC0 | CC1 | CC3;
1195 case GE: return CC0 | CC2;
1196 default: return -1;
1197 }
1198 break;
1199
1200 case CCANmode:
1201 switch (GET_CODE (code))
1202 {
1203 case EQ: return CC0;
1204 case NE: return CC1 | CC2 | CC3;
1205 case LT: return CC1;
1206 case GT: return CC2 | CC3;
1207 case LE: return CC0 | CC1;
1208 case GE: return CC0 | CC2 | CC3;
1209 default: return -1;
1210 }
1211 break;
1212
1213 case CCSmode:
1214 switch (GET_CODE (code))
1215 {
1216 case EQ: return CC0;
1217 case NE: return CC1 | CC2 | CC3;
1218 case LT: return CC1;
1219 case GT: return CC2;
1220 case LE: return CC0 | CC1;
1221 case GE: return CC0 | CC2;
1222 case UNORDERED: return CC3;
1223 case ORDERED: return CC0 | CC1 | CC2;
1224 case UNEQ: return CC0 | CC3;
1225 case UNLT: return CC1 | CC3;
1226 case UNGT: return CC2 | CC3;
1227 case UNLE: return CC0 | CC1 | CC3;
1228 case UNGE: return CC0 | CC2 | CC3;
1229 case LTGT: return CC1 | CC2;
1230 default: return -1;
1231 }
1232 break;
1233
1234 case CCSRmode:
1235 switch (GET_CODE (code))
1236 {
1237 case EQ: return CC0;
1238 case NE: return CC2 | CC1 | CC3;
1239 case LT: return CC2;
1240 case GT: return CC1;
1241 case LE: return CC0 | CC2;
1242 case GE: return CC0 | CC1;
1243 case UNORDERED: return CC3;
1244 case ORDERED: return CC0 | CC2 | CC1;
1245 case UNEQ: return CC0 | CC3;
1246 case UNLT: return CC2 | CC3;
1247 case UNGT: return CC1 | CC3;
1248 case UNLE: return CC0 | CC2 | CC3;
1249 case UNGE: return CC0 | CC1 | CC3;
1250 case LTGT: return CC2 | CC1;
1251 default: return -1;
1252 }
1253 break;
1254
1255 case CCRAWmode:
1256 switch (GET_CODE (code))
1257 {
1258 case EQ:
1259 return INTVAL (XEXP (code, 1));
1260 case NE:
1261 return (INTVAL (XEXP (code, 1))) ^ 0xf;
1262 default:
1263 gcc_unreachable ();
1264 }
1265
1266 default:
1267 return -1;
1268 }
1269 }
1270
1271
1272 /* Return branch condition mask to implement a compare and branch
1273 specified by CODE. Return -1 for invalid comparisons. */
1274
1275 int
1276 s390_compare_and_branch_condition_mask (rtx code)
1277 {
1278 const int CC0 = 1 << 3;
1279 const int CC1 = 1 << 2;
1280 const int CC2 = 1 << 1;
1281
1282 switch (GET_CODE (code))
1283 {
1284 case EQ:
1285 return CC0;
1286 case NE:
1287 return CC1 | CC2;
1288 case LT:
1289 case LTU:
1290 return CC1;
1291 case GT:
1292 case GTU:
1293 return CC2;
1294 case LE:
1295 case LEU:
1296 return CC0 | CC1;
1297 case GE:
1298 case GEU:
1299 return CC0 | CC2;
1300 default:
1301 gcc_unreachable ();
1302 }
1303 return -1;
1304 }
1305
1306 /* If INV is false, return assembler mnemonic string to implement
1307 a branch specified by CODE. If INV is true, return mnemonic
1308 for the corresponding inverted branch. */
1309
1310 static const char *
1311 s390_branch_condition_mnemonic (rtx code, int inv)
1312 {
1313 int mask;
1314
1315 static const char *const mnemonic[16] =
1316 {
1317 NULL, "o", "h", "nle",
1318 "l", "nhe", "lh", "ne",
1319 "e", "nlh", "he", "nl",
1320 "le", "nh", "no", NULL
1321 };
1322
1323 if (GET_CODE (XEXP (code, 0)) == REG
1324 && REGNO (XEXP (code, 0)) == CC_REGNUM
1325 && (XEXP (code, 1) == const0_rtx
1326 || (GET_MODE (XEXP (code, 0)) == CCRAWmode
1327 && CONST_INT_P (XEXP (code, 1)))))
1328 mask = s390_branch_condition_mask (code);
1329 else
1330 mask = s390_compare_and_branch_condition_mask (code);
1331
1332 gcc_assert (mask >= 0);
1333
1334 if (inv)
1335 mask ^= 15;
1336
1337 gcc_assert (mask >= 1 && mask <= 14);
1338
1339 return mnemonic[mask];
1340 }
1341
1342 /* Return the part of op which has a value different from def.
1343 The size of the part is determined by mode.
1344 Use this function only if you already know that op really
1345 contains such a part. */
1346
1347 unsigned HOST_WIDE_INT
1348 s390_extract_part (rtx op, enum machine_mode mode, int def)
1349 {
1350 unsigned HOST_WIDE_INT value = 0;
1351 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1352 int part_bits = GET_MODE_BITSIZE (mode);
1353 unsigned HOST_WIDE_INT part_mask
1354 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1355 int i;
1356
1357 for (i = 0; i < max_parts; i++)
1358 {
1359 if (i == 0)
1360 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1361 else
1362 value >>= part_bits;
1363
1364 if ((value & part_mask) != (def & part_mask))
1365 return value & part_mask;
1366 }
1367
1368 gcc_unreachable ();
1369 }
1370
1371 /* If OP is an integer constant of mode MODE with exactly one
1372 part of mode PART_MODE unequal to DEF, return the number of that
1373 part. Otherwise, return -1. */
1374
1375 int
1376 s390_single_part (rtx op,
1377 enum machine_mode mode,
1378 enum machine_mode part_mode,
1379 int def)
1380 {
1381 unsigned HOST_WIDE_INT value = 0;
1382 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1383 unsigned HOST_WIDE_INT part_mask
1384 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1385 int i, part = -1;
1386
1387 if (GET_CODE (op) != CONST_INT)
1388 return -1;
1389
1390 for (i = 0; i < n_parts; i++)
1391 {
1392 if (i == 0)
1393 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1394 else
1395 value >>= GET_MODE_BITSIZE (part_mode);
1396
1397 if ((value & part_mask) != (def & part_mask))
1398 {
1399 if (part != -1)
1400 return -1;
1401 else
1402 part = i;
1403 }
1404 }
1405 return part == -1 ? -1 : n_parts - 1 - part;
1406 }
1407
1408 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1409 bits and no other bits are set in IN. POS and LENGTH can be used
1410 to obtain the start position and the length of the bitfield.
1411
1412 POS gives the position of the first bit of the bitfield counting
1413 from the lowest order bit starting with zero. In order to use this
1414 value for S/390 instructions this has to be converted to "bits big
1415 endian" style. */
1416
1417 bool
1418 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size,
1419 int *pos, int *length)
1420 {
1421 int tmp_pos = 0;
1422 int tmp_length = 0;
1423 int i;
1424 unsigned HOST_WIDE_INT mask = 1ULL;
1425 bool contiguous = false;
1426
1427 for (i = 0; i < size; mask <<= 1, i++)
1428 {
1429 if (contiguous)
1430 {
1431 if (mask & in)
1432 tmp_length++;
1433 else
1434 break;
1435 }
1436 else
1437 {
1438 if (mask & in)
1439 {
1440 contiguous = true;
1441 tmp_length++;
1442 }
1443 else
1444 tmp_pos++;
1445 }
1446 }
1447
1448 if (!tmp_length)
1449 return false;
1450
1451 /* Calculate a mask for all bits beyond the contiguous bits. */
1452 mask = (-1LL & ~(((1ULL << (tmp_length + tmp_pos - 1)) << 1) - 1));
1453
1454 if (mask & in)
1455 return false;
1456
1457 if (tmp_length + tmp_pos - 1 > size)
1458 return false;
1459
1460 if (length)
1461 *length = tmp_length;
1462
1463 if (pos)
1464 *pos = tmp_pos;
1465
1466 return true;
1467 }
1468
1469 /* Check whether a rotate of ROTL followed by an AND of CONTIG is
1470 equivalent to a shift followed by the AND. In particular, CONTIG
1471 should not overlap the (rotated) bit 0/bit 63 gap. Negative values
1472 for ROTL indicate a rotate to the right. */
1473
1474 bool
1475 s390_extzv_shift_ok (int bitsize, int rotl, unsigned HOST_WIDE_INT contig)
1476 {
1477 int pos, len;
1478 bool ok;
1479
1480 ok = s390_contiguous_bitmask_p (contig, bitsize, &pos, &len);
1481 gcc_assert (ok);
1482
1483 return ((rotl >= 0 && rotl <= pos)
1484 || (rotl < 0 && -rotl <= bitsize - len - pos));
1485 }
1486
1487 /* Check whether we can (and want to) split a double-word
1488 move in mode MODE from SRC to DST into two single-word
1489 moves, moving the subword FIRST_SUBWORD first. */
1490
1491 bool
1492 s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
1493 {
1494 /* Floating point registers cannot be split. */
1495 if (FP_REG_P (src) || FP_REG_P (dst))
1496 return false;
1497
1498 /* We don't need to split if operands are directly accessible. */
1499 if (s_operand (src, mode) || s_operand (dst, mode))
1500 return false;
1501
1502 /* Non-offsettable memory references cannot be split. */
1503 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1504 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1505 return false;
1506
1507 /* Moving the first subword must not clobber a register
1508 needed to move the second subword. */
1509 if (register_operand (dst, mode))
1510 {
1511 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1512 if (reg_overlap_mentioned_p (subreg, src))
1513 return false;
1514 }
1515
1516 return true;
1517 }
1518
1519 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1520 and [MEM2, MEM2 + SIZE] do overlap and false
1521 otherwise. */
1522
1523 bool
1524 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1525 {
1526 rtx addr1, addr2, addr_delta;
1527 HOST_WIDE_INT delta;
1528
1529 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1530 return true;
1531
1532 if (size == 0)
1533 return false;
1534
1535 addr1 = XEXP (mem1, 0);
1536 addr2 = XEXP (mem2, 0);
1537
1538 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1539
1540 /* This overlapping check is used by peepholes merging memory block operations.
1541 Overlapping operations would otherwise be recognized by the S/390 hardware
1542 and would fall back to a slower implementation. Allowing overlapping
1543 operations would lead to slow code but not to wrong code. Therefore we are
1544 somewhat optimistic if we cannot prove that the memory blocks are
1545 overlapping.
1546 That's why we return false here although this may accept operations on
1547 overlapping memory areas. */
1548 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1549 return false;
1550
1551 delta = INTVAL (addr_delta);
1552
1553 if (delta == 0
1554 || (delta > 0 && delta < size)
1555 || (delta < 0 && -delta < size))
1556 return true;
1557
1558 return false;
1559 }
1560
1561 /* Check whether the address of memory reference MEM2 equals exactly
1562 the address of memory reference MEM1 plus DELTA. Return true if
1563 we can prove this to be the case, false otherwise. */
1564
1565 bool
1566 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1567 {
1568 rtx addr1, addr2, addr_delta;
1569
1570 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1571 return false;
1572
1573 addr1 = XEXP (mem1, 0);
1574 addr2 = XEXP (mem2, 0);
1575
1576 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1577 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1578 return false;
1579
1580 return true;
1581 }
1582
1583 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1584
1585 void
1586 s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1587 rtx *operands)
1588 {
1589 enum machine_mode wmode = mode;
1590 rtx dst = operands[0];
1591 rtx src1 = operands[1];
1592 rtx src2 = operands[2];
1593 rtx op, clob, tem;
1594
1595 /* If we cannot handle the operation directly, use a temp register. */
1596 if (!s390_logical_operator_ok_p (operands))
1597 dst = gen_reg_rtx (mode);
1598
1599 /* QImode and HImode patterns make sense only if we have a destination
1600 in memory. Otherwise perform the operation in SImode. */
1601 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1602 wmode = SImode;
1603
1604 /* Widen operands if required. */
1605 if (mode != wmode)
1606 {
1607 if (GET_CODE (dst) == SUBREG
1608 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1609 dst = tem;
1610 else if (REG_P (dst))
1611 dst = gen_rtx_SUBREG (wmode, dst, 0);
1612 else
1613 dst = gen_reg_rtx (wmode);
1614
1615 if (GET_CODE (src1) == SUBREG
1616 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1617 src1 = tem;
1618 else if (GET_MODE (src1) != VOIDmode)
1619 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1620
1621 if (GET_CODE (src2) == SUBREG
1622 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1623 src2 = tem;
1624 else if (GET_MODE (src2) != VOIDmode)
1625 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1626 }
1627
1628 /* Emit the instruction. */
1629 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1630 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1631 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1632
1633 /* Fix up the destination if needed. */
1634 if (dst != operands[0])
1635 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1636 }
1637
1638 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1639
1640 bool
1641 s390_logical_operator_ok_p (rtx *operands)
1642 {
1643 /* If the destination operand is in memory, it needs to coincide
1644 with one of the source operands. After reload, it has to be
1645 the first source operand. */
1646 if (GET_CODE (operands[0]) == MEM)
1647 return rtx_equal_p (operands[0], operands[1])
1648 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1649
1650 return true;
1651 }
1652
1653 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1654 operand IMMOP to switch from SS to SI type instructions. */
1655
1656 void
1657 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1658 {
1659 int def = code == AND ? -1 : 0;
1660 HOST_WIDE_INT mask;
1661 int part;
1662
1663 gcc_assert (GET_CODE (*memop) == MEM);
1664 gcc_assert (!MEM_VOLATILE_P (*memop));
1665
1666 mask = s390_extract_part (*immop, QImode, def);
1667 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1668 gcc_assert (part >= 0);
1669
1670 *memop = adjust_address (*memop, QImode, part);
1671 *immop = gen_int_mode (mask, QImode);
1672 }
1673
1674
1675 /* How to allocate a 'struct machine_function'. */
1676
1677 static struct machine_function *
1678 s390_init_machine_status (void)
1679 {
1680 return ggc_cleared_alloc<machine_function> ();
1681 }
1682
1683 /* Map for smallest class containing reg regno. */
1684
1685 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1686 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1687 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1688 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1689 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1690 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1691 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1692 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1693 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1694 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1695 ACCESS_REGS, ACCESS_REGS
1696 };
1697
1698 /* Return attribute type of insn. */
1699
1700 static enum attr_type
1701 s390_safe_attr_type (rtx_insn *insn)
1702 {
1703 if (recog_memoized (insn) >= 0)
1704 return get_attr_type (insn);
1705 else
1706 return TYPE_NONE;
1707 }
1708
1709 /* Return true if DISP is a valid short displacement. */
1710
1711 static bool
1712 s390_short_displacement (rtx disp)
1713 {
1714 /* No displacement is OK. */
1715 if (!disp)
1716 return true;
1717
1718 /* Without the long displacement facility we don't need to
1719 distingiush between long and short displacement. */
1720 if (!TARGET_LONG_DISPLACEMENT)
1721 return true;
1722
1723 /* Integer displacement in range. */
1724 if (GET_CODE (disp) == CONST_INT)
1725 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1726
1727 /* GOT offset is not OK, the GOT can be large. */
1728 if (GET_CODE (disp) == CONST
1729 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1730 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1731 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1732 return false;
1733
1734 /* All other symbolic constants are literal pool references,
1735 which are OK as the literal pool must be small. */
1736 if (GET_CODE (disp) == CONST)
1737 return true;
1738
1739 return false;
1740 }
1741
1742 /* Decompose a RTL expression ADDR for a memory address into
1743 its components, returned in OUT.
1744
1745 Returns false if ADDR is not a valid memory address, true
1746 otherwise. If OUT is NULL, don't return the components,
1747 but check for validity only.
1748
1749 Note: Only addresses in canonical form are recognized.
1750 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1751 canonical form so that they will be recognized. */
1752
1753 static int
1754 s390_decompose_address (rtx addr, struct s390_address *out)
1755 {
1756 HOST_WIDE_INT offset = 0;
1757 rtx base = NULL_RTX;
1758 rtx indx = NULL_RTX;
1759 rtx disp = NULL_RTX;
1760 rtx orig_disp;
1761 bool pointer = false;
1762 bool base_ptr = false;
1763 bool indx_ptr = false;
1764 bool literal_pool = false;
1765
1766 /* We may need to substitute the literal pool base register into the address
1767 below. However, at this point we do not know which register is going to
1768 be used as base, so we substitute the arg pointer register. This is going
1769 to be treated as holding a pointer below -- it shouldn't be used for any
1770 other purpose. */
1771 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1772
1773 /* Decompose address into base + index + displacement. */
1774
1775 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1776 base = addr;
1777
1778 else if (GET_CODE (addr) == PLUS)
1779 {
1780 rtx op0 = XEXP (addr, 0);
1781 rtx op1 = XEXP (addr, 1);
1782 enum rtx_code code0 = GET_CODE (op0);
1783 enum rtx_code code1 = GET_CODE (op1);
1784
1785 if (code0 == REG || code0 == UNSPEC)
1786 {
1787 if (code1 == REG || code1 == UNSPEC)
1788 {
1789 indx = op0; /* index + base */
1790 base = op1;
1791 }
1792
1793 else
1794 {
1795 base = op0; /* base + displacement */
1796 disp = op1;
1797 }
1798 }
1799
1800 else if (code0 == PLUS)
1801 {
1802 indx = XEXP (op0, 0); /* index + base + disp */
1803 base = XEXP (op0, 1);
1804 disp = op1;
1805 }
1806
1807 else
1808 {
1809 return false;
1810 }
1811 }
1812
1813 else
1814 disp = addr; /* displacement */
1815
1816 /* Extract integer part of displacement. */
1817 orig_disp = disp;
1818 if (disp)
1819 {
1820 if (GET_CODE (disp) == CONST_INT)
1821 {
1822 offset = INTVAL (disp);
1823 disp = NULL_RTX;
1824 }
1825 else if (GET_CODE (disp) == CONST
1826 && GET_CODE (XEXP (disp, 0)) == PLUS
1827 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1828 {
1829 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1830 disp = XEXP (XEXP (disp, 0), 0);
1831 }
1832 }
1833
1834 /* Strip off CONST here to avoid special case tests later. */
1835 if (disp && GET_CODE (disp) == CONST)
1836 disp = XEXP (disp, 0);
1837
1838 /* We can convert literal pool addresses to
1839 displacements by basing them off the base register. */
1840 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1841 {
1842 /* Either base or index must be free to hold the base register. */
1843 if (!base)
1844 base = fake_pool_base, literal_pool = true;
1845 else if (!indx)
1846 indx = fake_pool_base, literal_pool = true;
1847 else
1848 return false;
1849
1850 /* Mark up the displacement. */
1851 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1852 UNSPEC_LTREL_OFFSET);
1853 }
1854
1855 /* Validate base register. */
1856 if (base)
1857 {
1858 if (GET_CODE (base) == UNSPEC)
1859 switch (XINT (base, 1))
1860 {
1861 case UNSPEC_LTREF:
1862 if (!disp)
1863 disp = gen_rtx_UNSPEC (Pmode,
1864 gen_rtvec (1, XVECEXP (base, 0, 0)),
1865 UNSPEC_LTREL_OFFSET);
1866 else
1867 return false;
1868
1869 base = XVECEXP (base, 0, 1);
1870 break;
1871
1872 case UNSPEC_LTREL_BASE:
1873 if (XVECLEN (base, 0) == 1)
1874 base = fake_pool_base, literal_pool = true;
1875 else
1876 base = XVECEXP (base, 0, 1);
1877 break;
1878
1879 default:
1880 return false;
1881 }
1882
1883 if (!REG_P (base)
1884 || (GET_MODE (base) != SImode
1885 && GET_MODE (base) != Pmode))
1886 return false;
1887
1888 if (REGNO (base) == STACK_POINTER_REGNUM
1889 || REGNO (base) == FRAME_POINTER_REGNUM
1890 || ((reload_completed || reload_in_progress)
1891 && frame_pointer_needed
1892 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1893 || REGNO (base) == ARG_POINTER_REGNUM
1894 || (flag_pic
1895 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1896 pointer = base_ptr = true;
1897
1898 if ((reload_completed || reload_in_progress)
1899 && base == cfun->machine->base_reg)
1900 pointer = base_ptr = literal_pool = true;
1901 }
1902
1903 /* Validate index register. */
1904 if (indx)
1905 {
1906 if (GET_CODE (indx) == UNSPEC)
1907 switch (XINT (indx, 1))
1908 {
1909 case UNSPEC_LTREF:
1910 if (!disp)
1911 disp = gen_rtx_UNSPEC (Pmode,
1912 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1913 UNSPEC_LTREL_OFFSET);
1914 else
1915 return false;
1916
1917 indx = XVECEXP (indx, 0, 1);
1918 break;
1919
1920 case UNSPEC_LTREL_BASE:
1921 if (XVECLEN (indx, 0) == 1)
1922 indx = fake_pool_base, literal_pool = true;
1923 else
1924 indx = XVECEXP (indx, 0, 1);
1925 break;
1926
1927 default:
1928 return false;
1929 }
1930
1931 if (!REG_P (indx)
1932 || (GET_MODE (indx) != SImode
1933 && GET_MODE (indx) != Pmode))
1934 return false;
1935
1936 if (REGNO (indx) == STACK_POINTER_REGNUM
1937 || REGNO (indx) == FRAME_POINTER_REGNUM
1938 || ((reload_completed || reload_in_progress)
1939 && frame_pointer_needed
1940 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1941 || REGNO (indx) == ARG_POINTER_REGNUM
1942 || (flag_pic
1943 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
1944 pointer = indx_ptr = true;
1945
1946 if ((reload_completed || reload_in_progress)
1947 && indx == cfun->machine->base_reg)
1948 pointer = indx_ptr = literal_pool = true;
1949 }
1950
1951 /* Prefer to use pointer as base, not index. */
1952 if (base && indx && !base_ptr
1953 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1954 {
1955 rtx tmp = base;
1956 base = indx;
1957 indx = tmp;
1958 }
1959
1960 /* Validate displacement. */
1961 if (!disp)
1962 {
1963 /* If virtual registers are involved, the displacement will change later
1964 anyway as the virtual registers get eliminated. This could make a
1965 valid displacement invalid, but it is more likely to make an invalid
1966 displacement valid, because we sometimes access the register save area
1967 via negative offsets to one of those registers.
1968 Thus we don't check the displacement for validity here. If after
1969 elimination the displacement turns out to be invalid after all,
1970 this is fixed up by reload in any case. */
1971 /* LRA maintains always displacements up to date and we need to
1972 know the displacement is right during all LRA not only at the
1973 final elimination. */
1974 if (lra_in_progress
1975 || (base != arg_pointer_rtx
1976 && indx != arg_pointer_rtx
1977 && base != return_address_pointer_rtx
1978 && indx != return_address_pointer_rtx
1979 && base != frame_pointer_rtx
1980 && indx != frame_pointer_rtx
1981 && base != virtual_stack_vars_rtx
1982 && indx != virtual_stack_vars_rtx))
1983 if (!DISP_IN_RANGE (offset))
1984 return false;
1985 }
1986 else
1987 {
1988 /* All the special cases are pointers. */
1989 pointer = true;
1990
1991 /* In the small-PIC case, the linker converts @GOT
1992 and @GOTNTPOFF offsets to possible displacements. */
1993 if (GET_CODE (disp) == UNSPEC
1994 && (XINT (disp, 1) == UNSPEC_GOT
1995 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
1996 && flag_pic == 1)
1997 {
1998 ;
1999 }
2000
2001 /* Accept pool label offsets. */
2002 else if (GET_CODE (disp) == UNSPEC
2003 && XINT (disp, 1) == UNSPEC_POOL_OFFSET)
2004 ;
2005
2006 /* Accept literal pool references. */
2007 else if (GET_CODE (disp) == UNSPEC
2008 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
2009 {
2010 /* In case CSE pulled a non literal pool reference out of
2011 the pool we have to reject the address. This is
2012 especially important when loading the GOT pointer on non
2013 zarch CPUs. In this case the literal pool contains an lt
2014 relative offset to the _GLOBAL_OFFSET_TABLE_ label which
2015 will most likely exceed the displacement. */
2016 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
2017 || !CONSTANT_POOL_ADDRESS_P (XVECEXP (disp, 0, 0)))
2018 return false;
2019
2020 orig_disp = gen_rtx_CONST (Pmode, disp);
2021 if (offset)
2022 {
2023 /* If we have an offset, make sure it does not
2024 exceed the size of the constant pool entry. */
2025 rtx sym = XVECEXP (disp, 0, 0);
2026 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
2027 return false;
2028
2029 orig_disp = plus_constant (Pmode, orig_disp, offset);
2030 }
2031 }
2032
2033 else
2034 return false;
2035 }
2036
2037 if (!base && !indx)
2038 pointer = true;
2039
2040 if (out)
2041 {
2042 out->base = base;
2043 out->indx = indx;
2044 out->disp = orig_disp;
2045 out->pointer = pointer;
2046 out->literal_pool = literal_pool;
2047 }
2048
2049 return true;
2050 }
2051
2052 /* Decompose a RTL expression OP for a shift count into its components,
2053 and return the base register in BASE and the offset in OFFSET.
2054
2055 Return true if OP is a valid shift count, false if not. */
2056
2057 bool
2058 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
2059 {
2060 HOST_WIDE_INT off = 0;
2061
2062 /* We can have an integer constant, an address register,
2063 or a sum of the two. */
2064 if (GET_CODE (op) == CONST_INT)
2065 {
2066 off = INTVAL (op);
2067 op = NULL_RTX;
2068 }
2069 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
2070 {
2071 off = INTVAL (XEXP (op, 1));
2072 op = XEXP (op, 0);
2073 }
2074 while (op && GET_CODE (op) == SUBREG)
2075 op = SUBREG_REG (op);
2076
2077 if (op && GET_CODE (op) != REG)
2078 return false;
2079
2080 if (offset)
2081 *offset = off;
2082 if (base)
2083 *base = op;
2084
2085 return true;
2086 }
2087
2088
2089 /* Return true if CODE is a valid address without index. */
2090
2091 bool
2092 s390_legitimate_address_without_index_p (rtx op)
2093 {
2094 struct s390_address addr;
2095
2096 if (!s390_decompose_address (XEXP (op, 0), &addr))
2097 return false;
2098 if (addr.indx)
2099 return false;
2100
2101 return true;
2102 }
2103
2104
2105 /* Return TRUE if ADDR is an operand valid for a load/store relative
2106 instruction. Be aware that the alignment of the operand needs to
2107 be checked separately.
2108 Valid addresses are single references or a sum of a reference and a
2109 constant integer. Return these parts in SYMREF and ADDEND. You can
2110 pass NULL in REF and/or ADDEND if you are not interested in these
2111 values. Literal pool references are *not* considered symbol
2112 references. */
2113
2114 static bool
2115 s390_loadrelative_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend)
2116 {
2117 HOST_WIDE_INT tmpaddend = 0;
2118
2119 if (GET_CODE (addr) == CONST)
2120 addr = XEXP (addr, 0);
2121
2122 if (GET_CODE (addr) == PLUS)
2123 {
2124 if (!CONST_INT_P (XEXP (addr, 1)))
2125 return false;
2126
2127 tmpaddend = INTVAL (XEXP (addr, 1));
2128 addr = XEXP (addr, 0);
2129 }
2130
2131 if ((GET_CODE (addr) == SYMBOL_REF && !CONSTANT_POOL_ADDRESS_P (addr))
2132 || (GET_CODE (addr) == UNSPEC
2133 && (XINT (addr, 1) == UNSPEC_GOTENT
2134 || (TARGET_CPU_ZARCH && XINT (addr, 1) == UNSPEC_PLT))))
2135 {
2136 if (symref)
2137 *symref = addr;
2138 if (addend)
2139 *addend = tmpaddend;
2140
2141 return true;
2142 }
2143 return false;
2144 }
2145
2146 /* Return true if the address in OP is valid for constraint letter C
2147 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2148 pool MEMs should be accepted. Only the Q, R, S, T constraint
2149 letters are allowed for C. */
2150
2151 static int
2152 s390_check_qrst_address (char c, rtx op, bool lit_pool_ok)
2153 {
2154 struct s390_address addr;
2155 bool decomposed = false;
2156
2157 /* This check makes sure that no symbolic address (except literal
2158 pool references) are accepted by the R or T constraints. */
2159 if (s390_loadrelative_operand_p (op, NULL, NULL))
2160 return 0;
2161
2162 /* Ensure literal pool references are only accepted if LIT_POOL_OK. */
2163 if (!lit_pool_ok)
2164 {
2165 if (!s390_decompose_address (op, &addr))
2166 return 0;
2167 if (addr.literal_pool)
2168 return 0;
2169 decomposed = true;
2170 }
2171
2172 switch (c)
2173 {
2174 case 'Q': /* no index short displacement */
2175 if (!decomposed && !s390_decompose_address (op, &addr))
2176 return 0;
2177 if (addr.indx)
2178 return 0;
2179 if (!s390_short_displacement (addr.disp))
2180 return 0;
2181 break;
2182
2183 case 'R': /* with index short displacement */
2184 if (TARGET_LONG_DISPLACEMENT)
2185 {
2186 if (!decomposed && !s390_decompose_address (op, &addr))
2187 return 0;
2188 if (!s390_short_displacement (addr.disp))
2189 return 0;
2190 }
2191 /* Any invalid address here will be fixed up by reload,
2192 so accept it for the most generic constraint. */
2193 break;
2194
2195 case 'S': /* no index long displacement */
2196 if (!TARGET_LONG_DISPLACEMENT)
2197 return 0;
2198 if (!decomposed && !s390_decompose_address (op, &addr))
2199 return 0;
2200 if (addr.indx)
2201 return 0;
2202 if (s390_short_displacement (addr.disp))
2203 return 0;
2204 break;
2205
2206 case 'T': /* with index long displacement */
2207 if (!TARGET_LONG_DISPLACEMENT)
2208 return 0;
2209 /* Any invalid address here will be fixed up by reload,
2210 so accept it for the most generic constraint. */
2211 if ((decomposed || s390_decompose_address (op, &addr))
2212 && s390_short_displacement (addr.disp))
2213 return 0;
2214 break;
2215 default:
2216 return 0;
2217 }
2218 return 1;
2219 }
2220
2221
2222 /* Evaluates constraint strings described by the regular expression
2223 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2224 the constraint given in STR, or 0 else. */
2225
2226 int
2227 s390_mem_constraint (const char *str, rtx op)
2228 {
2229 char c = str[0];
2230
2231 switch (c)
2232 {
2233 case 'A':
2234 /* Check for offsettable variants of memory constraints. */
2235 if (!MEM_P (op) || MEM_VOLATILE_P (op))
2236 return 0;
2237 if ((reload_completed || reload_in_progress)
2238 ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
2239 return 0;
2240 return s390_check_qrst_address (str[1], XEXP (op, 0), true);
2241 case 'B':
2242 /* Check for non-literal-pool variants of memory constraints. */
2243 if (!MEM_P (op))
2244 return 0;
2245 return s390_check_qrst_address (str[1], XEXP (op, 0), false);
2246 case 'Q':
2247 case 'R':
2248 case 'S':
2249 case 'T':
2250 if (GET_CODE (op) != MEM)
2251 return 0;
2252 return s390_check_qrst_address (c, XEXP (op, 0), true);
2253 case 'U':
2254 return (s390_check_qrst_address ('Q', op, true)
2255 || s390_check_qrst_address ('R', op, true));
2256 case 'W':
2257 return (s390_check_qrst_address ('S', op, true)
2258 || s390_check_qrst_address ('T', op, true));
2259 case 'Y':
2260 /* Simply check for the basic form of a shift count. Reload will
2261 take care of making sure we have a proper base register. */
2262 if (!s390_decompose_shift_count (op, NULL, NULL))
2263 return 0;
2264 break;
2265 case 'Z':
2266 return s390_check_qrst_address (str[1], op, true);
2267 default:
2268 return 0;
2269 }
2270 return 1;
2271 }
2272
2273
2274 /* Evaluates constraint strings starting with letter O. Input
2275 parameter C is the second letter following the "O" in the constraint
2276 string. Returns 1 if VALUE meets the respective constraint and 0
2277 otherwise. */
2278
2279 int
2280 s390_O_constraint_str (const char c, HOST_WIDE_INT value)
2281 {
2282 if (!TARGET_EXTIMM)
2283 return 0;
2284
2285 switch (c)
2286 {
2287 case 's':
2288 return trunc_int_for_mode (value, SImode) == value;
2289
2290 case 'p':
2291 return value == 0
2292 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2293
2294 case 'n':
2295 return s390_single_part (GEN_INT (value - 1), DImode, SImode, -1) == 1;
2296
2297 default:
2298 gcc_unreachable ();
2299 }
2300 }
2301
2302
2303 /* Evaluates constraint strings starting with letter N. Parameter STR
2304 contains the letters following letter "N" in the constraint string.
2305 Returns true if VALUE matches the constraint. */
2306
2307 int
2308 s390_N_constraint_str (const char *str, HOST_WIDE_INT value)
2309 {
2310 enum machine_mode mode, part_mode;
2311 int def;
2312 int part, part_goal;
2313
2314
2315 if (str[0] == 'x')
2316 part_goal = -1;
2317 else
2318 part_goal = str[0] - '0';
2319
2320 switch (str[1])
2321 {
2322 case 'Q':
2323 part_mode = QImode;
2324 break;
2325 case 'H':
2326 part_mode = HImode;
2327 break;
2328 case 'S':
2329 part_mode = SImode;
2330 break;
2331 default:
2332 return 0;
2333 }
2334
2335 switch (str[2])
2336 {
2337 case 'H':
2338 mode = HImode;
2339 break;
2340 case 'S':
2341 mode = SImode;
2342 break;
2343 case 'D':
2344 mode = DImode;
2345 break;
2346 default:
2347 return 0;
2348 }
2349
2350 switch (str[3])
2351 {
2352 case '0':
2353 def = 0;
2354 break;
2355 case 'F':
2356 def = -1;
2357 break;
2358 default:
2359 return 0;
2360 }
2361
2362 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2363 return 0;
2364
2365 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2366 if (part < 0)
2367 return 0;
2368 if (part_goal != -1 && part_goal != part)
2369 return 0;
2370
2371 return 1;
2372 }
2373
2374
2375 /* Returns true if the input parameter VALUE is a float zero. */
2376
2377 int
2378 s390_float_const_zero_p (rtx value)
2379 {
2380 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
2381 && value == CONST0_RTX (GET_MODE (value)));
2382 }
2383
2384 /* Implement TARGET_REGISTER_MOVE_COST. */
2385
2386 static int
2387 s390_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2388 reg_class_t from, reg_class_t to)
2389 {
2390 /* On s390, copy between fprs and gprs is expensive as long as no
2391 ldgr/lgdr can be used. */
2392 if ((!TARGET_Z10 || GET_MODE_SIZE (mode) != 8)
2393 && ((reg_classes_intersect_p (from, GENERAL_REGS)
2394 && reg_classes_intersect_p (to, FP_REGS))
2395 || (reg_classes_intersect_p (from, FP_REGS)
2396 && reg_classes_intersect_p (to, GENERAL_REGS))))
2397 return 10;
2398
2399 return 1;
2400 }
2401
2402 /* Implement TARGET_MEMORY_MOVE_COST. */
2403
2404 static int
2405 s390_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2406 reg_class_t rclass ATTRIBUTE_UNUSED,
2407 bool in ATTRIBUTE_UNUSED)
2408 {
2409 return 1;
2410 }
2411
2412 /* Compute a (partial) cost for rtx X. Return true if the complete
2413 cost has been computed, and false if subexpressions should be
2414 scanned. In either case, *TOTAL contains the cost result.
2415 CODE contains GET_CODE (x), OUTER_CODE contains the code
2416 of the superexpression of x. */
2417
2418 static bool
2419 s390_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
2420 int *total, bool speed ATTRIBUTE_UNUSED)
2421 {
2422 switch (code)
2423 {
2424 case CONST:
2425 case CONST_INT:
2426 case LABEL_REF:
2427 case SYMBOL_REF:
2428 case CONST_DOUBLE:
2429 case MEM:
2430 *total = 0;
2431 return true;
2432
2433 case ASHIFT:
2434 case ASHIFTRT:
2435 case LSHIFTRT:
2436 case ROTATE:
2437 case ROTATERT:
2438 case AND:
2439 case IOR:
2440 case XOR:
2441 case NEG:
2442 case NOT:
2443 *total = COSTS_N_INSNS (1);
2444 return false;
2445
2446 case PLUS:
2447 case MINUS:
2448 *total = COSTS_N_INSNS (1);
2449 return false;
2450
2451 case MULT:
2452 switch (GET_MODE (x))
2453 {
2454 case SImode:
2455 {
2456 rtx left = XEXP (x, 0);
2457 rtx right = XEXP (x, 1);
2458 if (GET_CODE (right) == CONST_INT
2459 && CONST_OK_FOR_K (INTVAL (right)))
2460 *total = s390_cost->mhi;
2461 else if (GET_CODE (left) == SIGN_EXTEND)
2462 *total = s390_cost->mh;
2463 else
2464 *total = s390_cost->ms; /* msr, ms, msy */
2465 break;
2466 }
2467 case DImode:
2468 {
2469 rtx left = XEXP (x, 0);
2470 rtx right = XEXP (x, 1);
2471 if (TARGET_ZARCH)
2472 {
2473 if (GET_CODE (right) == CONST_INT
2474 && CONST_OK_FOR_K (INTVAL (right)))
2475 *total = s390_cost->mghi;
2476 else if (GET_CODE (left) == SIGN_EXTEND)
2477 *total = s390_cost->msgf;
2478 else
2479 *total = s390_cost->msg; /* msgr, msg */
2480 }
2481 else /* TARGET_31BIT */
2482 {
2483 if (GET_CODE (left) == SIGN_EXTEND
2484 && GET_CODE (right) == SIGN_EXTEND)
2485 /* mulsidi case: mr, m */
2486 *total = s390_cost->m;
2487 else if (GET_CODE (left) == ZERO_EXTEND
2488 && GET_CODE (right) == ZERO_EXTEND
2489 && TARGET_CPU_ZARCH)
2490 /* umulsidi case: ml, mlr */
2491 *total = s390_cost->ml;
2492 else
2493 /* Complex calculation is required. */
2494 *total = COSTS_N_INSNS (40);
2495 }
2496 break;
2497 }
2498 case SFmode:
2499 case DFmode:
2500 *total = s390_cost->mult_df;
2501 break;
2502 case TFmode:
2503 *total = s390_cost->mxbr;
2504 break;
2505 default:
2506 return false;
2507 }
2508 return false;
2509
2510 case FMA:
2511 switch (GET_MODE (x))
2512 {
2513 case DFmode:
2514 *total = s390_cost->madbr;
2515 break;
2516 case SFmode:
2517 *total = s390_cost->maebr;
2518 break;
2519 default:
2520 return false;
2521 }
2522 /* Negate in the third argument is free: FMSUB. */
2523 if (GET_CODE (XEXP (x, 2)) == NEG)
2524 {
2525 *total += (rtx_cost (XEXP (x, 0), FMA, 0, speed)
2526 + rtx_cost (XEXP (x, 1), FMA, 1, speed)
2527 + rtx_cost (XEXP (XEXP (x, 2), 0), FMA, 2, speed));
2528 return true;
2529 }
2530 return false;
2531
2532 case UDIV:
2533 case UMOD:
2534 if (GET_MODE (x) == TImode) /* 128 bit division */
2535 *total = s390_cost->dlgr;
2536 else if (GET_MODE (x) == DImode)
2537 {
2538 rtx right = XEXP (x, 1);
2539 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2540 *total = s390_cost->dlr;
2541 else /* 64 by 64 bit division */
2542 *total = s390_cost->dlgr;
2543 }
2544 else if (GET_MODE (x) == SImode) /* 32 bit division */
2545 *total = s390_cost->dlr;
2546 return false;
2547
2548 case DIV:
2549 case MOD:
2550 if (GET_MODE (x) == DImode)
2551 {
2552 rtx right = XEXP (x, 1);
2553 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2554 if (TARGET_ZARCH)
2555 *total = s390_cost->dsgfr;
2556 else
2557 *total = s390_cost->dr;
2558 else /* 64 by 64 bit division */
2559 *total = s390_cost->dsgr;
2560 }
2561 else if (GET_MODE (x) == SImode) /* 32 bit division */
2562 *total = s390_cost->dlr;
2563 else if (GET_MODE (x) == SFmode)
2564 {
2565 *total = s390_cost->debr;
2566 }
2567 else if (GET_MODE (x) == DFmode)
2568 {
2569 *total = s390_cost->ddbr;
2570 }
2571 else if (GET_MODE (x) == TFmode)
2572 {
2573 *total = s390_cost->dxbr;
2574 }
2575 return false;
2576
2577 case SQRT:
2578 if (GET_MODE (x) == SFmode)
2579 *total = s390_cost->sqebr;
2580 else if (GET_MODE (x) == DFmode)
2581 *total = s390_cost->sqdbr;
2582 else /* TFmode */
2583 *total = s390_cost->sqxbr;
2584 return false;
2585
2586 case SIGN_EXTEND:
2587 case ZERO_EXTEND:
2588 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2589 || outer_code == PLUS || outer_code == MINUS
2590 || outer_code == COMPARE)
2591 *total = 0;
2592 return false;
2593
2594 case COMPARE:
2595 *total = COSTS_N_INSNS (1);
2596 if (GET_CODE (XEXP (x, 0)) == AND
2597 && GET_CODE (XEXP (x, 1)) == CONST_INT
2598 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2599 {
2600 rtx op0 = XEXP (XEXP (x, 0), 0);
2601 rtx op1 = XEXP (XEXP (x, 0), 1);
2602 rtx op2 = XEXP (x, 1);
2603
2604 if (memory_operand (op0, GET_MODE (op0))
2605 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2606 return true;
2607 if (register_operand (op0, GET_MODE (op0))
2608 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2609 return true;
2610 }
2611 return false;
2612
2613 default:
2614 return false;
2615 }
2616 }
2617
2618 /* Return the cost of an address rtx ADDR. */
2619
2620 static int
2621 s390_address_cost (rtx addr, enum machine_mode mode ATTRIBUTE_UNUSED,
2622 addr_space_t as ATTRIBUTE_UNUSED,
2623 bool speed ATTRIBUTE_UNUSED)
2624 {
2625 struct s390_address ad;
2626 if (!s390_decompose_address (addr, &ad))
2627 return 1000;
2628
2629 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2630 }
2631
2632 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2633 otherwise return 0. */
2634
2635 int
2636 tls_symbolic_operand (rtx op)
2637 {
2638 if (GET_CODE (op) != SYMBOL_REF)
2639 return 0;
2640 return SYMBOL_REF_TLS_MODEL (op);
2641 }
2642 \f
2643 /* Split DImode access register reference REG (on 64-bit) into its constituent
2644 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2645 gen_highpart cannot be used as they assume all registers are word-sized,
2646 while our access registers have only half that size. */
2647
2648 void
2649 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2650 {
2651 gcc_assert (TARGET_64BIT);
2652 gcc_assert (ACCESS_REG_P (reg));
2653 gcc_assert (GET_MODE (reg) == DImode);
2654 gcc_assert (!(REGNO (reg) & 1));
2655
2656 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2657 *hi = gen_rtx_REG (SImode, REGNO (reg));
2658 }
2659
2660 /* Return true if OP contains a symbol reference */
2661
2662 bool
2663 symbolic_reference_mentioned_p (rtx op)
2664 {
2665 const char *fmt;
2666 int i;
2667
2668 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2669 return 1;
2670
2671 fmt = GET_RTX_FORMAT (GET_CODE (op));
2672 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2673 {
2674 if (fmt[i] == 'E')
2675 {
2676 int j;
2677
2678 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2679 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2680 return 1;
2681 }
2682
2683 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2684 return 1;
2685 }
2686
2687 return 0;
2688 }
2689
2690 /* Return true if OP contains a reference to a thread-local symbol. */
2691
2692 bool
2693 tls_symbolic_reference_mentioned_p (rtx op)
2694 {
2695 const char *fmt;
2696 int i;
2697
2698 if (GET_CODE (op) == SYMBOL_REF)
2699 return tls_symbolic_operand (op);
2700
2701 fmt = GET_RTX_FORMAT (GET_CODE (op));
2702 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2703 {
2704 if (fmt[i] == 'E')
2705 {
2706 int j;
2707
2708 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2709 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2710 return true;
2711 }
2712
2713 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2714 return true;
2715 }
2716
2717 return false;
2718 }
2719
2720
2721 /* Return true if OP is a legitimate general operand when
2722 generating PIC code. It is given that flag_pic is on
2723 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2724
2725 int
2726 legitimate_pic_operand_p (rtx op)
2727 {
2728 /* Accept all non-symbolic constants. */
2729 if (!SYMBOLIC_CONST (op))
2730 return 1;
2731
2732 /* Reject everything else; must be handled
2733 via emit_symbolic_move. */
2734 return 0;
2735 }
2736
2737 /* Returns true if the constant value OP is a legitimate general operand.
2738 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2739
2740 static bool
2741 s390_legitimate_constant_p (enum machine_mode mode, rtx op)
2742 {
2743 /* Accept all non-symbolic constants. */
2744 if (!SYMBOLIC_CONST (op))
2745 return 1;
2746
2747 /* Accept immediate LARL operands. */
2748 if (TARGET_CPU_ZARCH && larl_operand (op, mode))
2749 return 1;
2750
2751 /* Thread-local symbols are never legal constants. This is
2752 so that emit_call knows that computing such addresses
2753 might require a function call. */
2754 if (TLS_SYMBOLIC_CONST (op))
2755 return 0;
2756
2757 /* In the PIC case, symbolic constants must *not* be
2758 forced into the literal pool. We accept them here,
2759 so that they will be handled by emit_symbolic_move. */
2760 if (flag_pic)
2761 return 1;
2762
2763 /* All remaining non-PIC symbolic constants are
2764 forced into the literal pool. */
2765 return 0;
2766 }
2767
2768 /* Determine if it's legal to put X into the constant pool. This
2769 is not possible if X contains the address of a symbol that is
2770 not constant (TLS) or not known at final link time (PIC). */
2771
2772 static bool
2773 s390_cannot_force_const_mem (enum machine_mode mode, rtx x)
2774 {
2775 switch (GET_CODE (x))
2776 {
2777 case CONST_INT:
2778 case CONST_DOUBLE:
2779 /* Accept all non-symbolic constants. */
2780 return false;
2781
2782 case LABEL_REF:
2783 /* Labels are OK iff we are non-PIC. */
2784 return flag_pic != 0;
2785
2786 case SYMBOL_REF:
2787 /* 'Naked' TLS symbol references are never OK,
2788 non-TLS symbols are OK iff we are non-PIC. */
2789 if (tls_symbolic_operand (x))
2790 return true;
2791 else
2792 return flag_pic != 0;
2793
2794 case CONST:
2795 return s390_cannot_force_const_mem (mode, XEXP (x, 0));
2796 case PLUS:
2797 case MINUS:
2798 return s390_cannot_force_const_mem (mode, XEXP (x, 0))
2799 || s390_cannot_force_const_mem (mode, XEXP (x, 1));
2800
2801 case UNSPEC:
2802 switch (XINT (x, 1))
2803 {
2804 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2805 case UNSPEC_LTREL_OFFSET:
2806 case UNSPEC_GOT:
2807 case UNSPEC_GOTOFF:
2808 case UNSPEC_PLTOFF:
2809 case UNSPEC_TLSGD:
2810 case UNSPEC_TLSLDM:
2811 case UNSPEC_NTPOFF:
2812 case UNSPEC_DTPOFF:
2813 case UNSPEC_GOTNTPOFF:
2814 case UNSPEC_INDNTPOFF:
2815 return false;
2816
2817 /* If the literal pool shares the code section, be put
2818 execute template placeholders into the pool as well. */
2819 case UNSPEC_INSN:
2820 return TARGET_CPU_ZARCH;
2821
2822 default:
2823 return true;
2824 }
2825 break;
2826
2827 default:
2828 gcc_unreachable ();
2829 }
2830 }
2831
2832 /* Returns true if the constant value OP is a legitimate general
2833 operand during and after reload. The difference to
2834 legitimate_constant_p is that this function will not accept
2835 a constant that would need to be forced to the literal pool
2836 before it can be used as operand.
2837 This function accepts all constants which can be loaded directly
2838 into a GPR. */
2839
2840 bool
2841 legitimate_reload_constant_p (rtx op)
2842 {
2843 /* Accept la(y) operands. */
2844 if (GET_CODE (op) == CONST_INT
2845 && DISP_IN_RANGE (INTVAL (op)))
2846 return true;
2847
2848 /* Accept l(g)hi/l(g)fi operands. */
2849 if (GET_CODE (op) == CONST_INT
2850 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2851 return true;
2852
2853 /* Accept lliXX operands. */
2854 if (TARGET_ZARCH
2855 && GET_CODE (op) == CONST_INT
2856 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2857 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2858 return true;
2859
2860 if (TARGET_EXTIMM
2861 && GET_CODE (op) == CONST_INT
2862 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2863 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2864 return true;
2865
2866 /* Accept larl operands. */
2867 if (TARGET_CPU_ZARCH
2868 && larl_operand (op, VOIDmode))
2869 return true;
2870
2871 /* Accept floating-point zero operands that fit into a single GPR. */
2872 if (GET_CODE (op) == CONST_DOUBLE
2873 && s390_float_const_zero_p (op)
2874 && GET_MODE_SIZE (GET_MODE (op)) <= UNITS_PER_WORD)
2875 return true;
2876
2877 /* Accept double-word operands that can be split. */
2878 if (GET_CODE (op) == CONST_INT
2879 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2880 {
2881 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2882 rtx hi = operand_subword (op, 0, 0, dword_mode);
2883 rtx lo = operand_subword (op, 1, 0, dword_mode);
2884 return legitimate_reload_constant_p (hi)
2885 && legitimate_reload_constant_p (lo);
2886 }
2887
2888 /* Everything else cannot be handled without reload. */
2889 return false;
2890 }
2891
2892 /* Returns true if the constant value OP is a legitimate fp operand
2893 during and after reload.
2894 This function accepts all constants which can be loaded directly
2895 into an FPR. */
2896
2897 static bool
2898 legitimate_reload_fp_constant_p (rtx op)
2899 {
2900 /* Accept floating-point zero operands if the load zero instruction
2901 can be used. Prior to z196 the load fp zero instruction caused a
2902 performance penalty if the result is used as BFP number. */
2903 if (TARGET_Z196
2904 && GET_CODE (op) == CONST_DOUBLE
2905 && s390_float_const_zero_p (op))
2906 return true;
2907
2908 return false;
2909 }
2910
2911 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2912 return the class of reg to actually use. */
2913
2914 static reg_class_t
2915 s390_preferred_reload_class (rtx op, reg_class_t rclass)
2916 {
2917 switch (GET_CODE (op))
2918 {
2919 /* Constants we cannot reload into general registers
2920 must be forced into the literal pool. */
2921 case CONST_DOUBLE:
2922 case CONST_INT:
2923 if (reg_class_subset_p (GENERAL_REGS, rclass)
2924 && legitimate_reload_constant_p (op))
2925 return GENERAL_REGS;
2926 else if (reg_class_subset_p (ADDR_REGS, rclass)
2927 && legitimate_reload_constant_p (op))
2928 return ADDR_REGS;
2929 else if (reg_class_subset_p (FP_REGS, rclass)
2930 && legitimate_reload_fp_constant_p (op))
2931 return FP_REGS;
2932 return NO_REGS;
2933
2934 /* If a symbolic constant or a PLUS is reloaded,
2935 it is most likely being used as an address, so
2936 prefer ADDR_REGS. If 'class' is not a superset
2937 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2938 case CONST:
2939 /* Symrefs cannot be pushed into the literal pool with -fPIC
2940 so we *MUST NOT* return NO_REGS for these cases
2941 (s390_cannot_force_const_mem will return true).
2942
2943 On the other hand we MUST return NO_REGS for symrefs with
2944 invalid addend which might have been pushed to the literal
2945 pool (no -fPIC). Usually we would expect them to be
2946 handled via secondary reload but this does not happen if
2947 they are used as literal pool slot replacement in reload
2948 inheritance (see emit_input_reload_insns). */
2949 if (TARGET_CPU_ZARCH
2950 && GET_CODE (XEXP (op, 0)) == PLUS
2951 && GET_CODE (XEXP (XEXP(op, 0), 0)) == SYMBOL_REF
2952 && GET_CODE (XEXP (XEXP(op, 0), 1)) == CONST_INT)
2953 {
2954 if (flag_pic && reg_class_subset_p (ADDR_REGS, rclass))
2955 return ADDR_REGS;
2956 else
2957 return NO_REGS;
2958 }
2959 /* fallthrough */
2960 case LABEL_REF:
2961 case SYMBOL_REF:
2962 if (!legitimate_reload_constant_p (op))
2963 return NO_REGS;
2964 /* fallthrough */
2965 case PLUS:
2966 /* load address will be used. */
2967 if (reg_class_subset_p (ADDR_REGS, rclass))
2968 return ADDR_REGS;
2969 else
2970 return NO_REGS;
2971
2972 default:
2973 break;
2974 }
2975
2976 return rclass;
2977 }
2978
2979 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2980 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2981 aligned. */
2982
2983 bool
2984 s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment)
2985 {
2986 HOST_WIDE_INT addend;
2987 rtx symref;
2988
2989 if (!s390_loadrelative_operand_p (addr, &symref, &addend))
2990 return false;
2991
2992 if (addend & (alignment - 1))
2993 return false;
2994
2995 if (GET_CODE (symref) == SYMBOL_REF
2996 && !SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref))
2997 return true;
2998
2999 if (GET_CODE (symref) == UNSPEC
3000 && alignment <= UNITS_PER_LONG)
3001 return true;
3002
3003 return false;
3004 }
3005
3006 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
3007 operand SCRATCH is used to reload the even part of the address and
3008 adding one. */
3009
3010 void
3011 s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch)
3012 {
3013 HOST_WIDE_INT addend;
3014 rtx symref;
3015
3016 if (!s390_loadrelative_operand_p (addr, &symref, &addend))
3017 gcc_unreachable ();
3018
3019 if (!(addend & 1))
3020 /* Easy case. The addend is even so larl will do fine. */
3021 emit_move_insn (reg, addr);
3022 else
3023 {
3024 /* We can leave the scratch register untouched if the target
3025 register is a valid base register. */
3026 if (REGNO (reg) < FIRST_PSEUDO_REGISTER
3027 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS)
3028 scratch = reg;
3029
3030 gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER);
3031 gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS);
3032
3033 if (addend != 1)
3034 emit_move_insn (scratch,
3035 gen_rtx_CONST (Pmode,
3036 gen_rtx_PLUS (Pmode, symref,
3037 GEN_INT (addend - 1))));
3038 else
3039 emit_move_insn (scratch, symref);
3040
3041 /* Increment the address using la in order to avoid clobbering cc. */
3042 s390_load_address (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx));
3043 }
3044 }
3045
3046 /* Generate what is necessary to move between REG and MEM using
3047 SCRATCH. The direction is given by TOMEM. */
3048
3049 void
3050 s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
3051 {
3052 /* Reload might have pulled a constant out of the literal pool.
3053 Force it back in. */
3054 if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE
3055 || GET_CODE (mem) == CONST)
3056 mem = force_const_mem (GET_MODE (reg), mem);
3057
3058 gcc_assert (MEM_P (mem));
3059
3060 /* For a load from memory we can leave the scratch register
3061 untouched if the target register is a valid base register. */
3062 if (!tomem
3063 && REGNO (reg) < FIRST_PSEUDO_REGISTER
3064 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS
3065 && GET_MODE (reg) == GET_MODE (scratch))
3066 scratch = reg;
3067
3068 /* Load address into scratch register. Since we can't have a
3069 secondary reload for a secondary reload we have to cover the case
3070 where larl would need a secondary reload here as well. */
3071 s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch);
3072
3073 /* Now we can use a standard load/store to do the move. */
3074 if (tomem)
3075 emit_move_insn (replace_equiv_address (mem, scratch), reg);
3076 else
3077 emit_move_insn (reg, replace_equiv_address (mem, scratch));
3078 }
3079
3080 /* Inform reload about cases where moving X with a mode MODE to a register in
3081 RCLASS requires an extra scratch or immediate register. Return the class
3082 needed for the immediate register. */
3083
3084 static reg_class_t
3085 s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
3086 enum machine_mode mode, secondary_reload_info *sri)
3087 {
3088 enum reg_class rclass = (enum reg_class) rclass_i;
3089
3090 /* Intermediate register needed. */
3091 if (reg_classes_intersect_p (CC_REGS, rclass))
3092 return GENERAL_REGS;
3093
3094 if (TARGET_Z10)
3095 {
3096 HOST_WIDE_INT offset;
3097 rtx symref;
3098
3099 /* On z10 several optimizer steps may generate larl operands with
3100 an odd addend. */
3101 if (in_p
3102 && s390_loadrelative_operand_p (x, &symref, &offset)
3103 && mode == Pmode
3104 && !SYMBOL_REF_ALIGN1_P (symref)
3105 && (offset & 1) == 1)
3106 sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10
3107 : CODE_FOR_reloadsi_larl_odd_addend_z10);
3108
3109 /* On z10 we need a scratch register when moving QI, TI or floating
3110 point mode values from or to a memory location with a SYMBOL_REF
3111 or if the symref addend of a SI or DI move is not aligned to the
3112 width of the access. */
3113 if (MEM_P (x)
3114 && s390_loadrelative_operand_p (XEXP (x, 0), NULL, NULL)
3115 && (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
3116 || (!TARGET_ZARCH && mode == DImode)
3117 || ((mode == HImode || mode == SImode || mode == DImode)
3118 && (!s390_check_symref_alignment (XEXP (x, 0),
3119 GET_MODE_SIZE (mode))))))
3120 {
3121 #define __SECONDARY_RELOAD_CASE(M,m) \
3122 case M##mode: \
3123 if (TARGET_64BIT) \
3124 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
3125 CODE_FOR_reload##m##di_tomem_z10; \
3126 else \
3127 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
3128 CODE_FOR_reload##m##si_tomem_z10; \
3129 break;
3130
3131 switch (GET_MODE (x))
3132 {
3133 __SECONDARY_RELOAD_CASE (QI, qi);
3134 __SECONDARY_RELOAD_CASE (HI, hi);
3135 __SECONDARY_RELOAD_CASE (SI, si);
3136 __SECONDARY_RELOAD_CASE (DI, di);
3137 __SECONDARY_RELOAD_CASE (TI, ti);
3138 __SECONDARY_RELOAD_CASE (SF, sf);
3139 __SECONDARY_RELOAD_CASE (DF, df);
3140 __SECONDARY_RELOAD_CASE (TF, tf);
3141 __SECONDARY_RELOAD_CASE (SD, sd);
3142 __SECONDARY_RELOAD_CASE (DD, dd);
3143 __SECONDARY_RELOAD_CASE (TD, td);
3144
3145 default:
3146 gcc_unreachable ();
3147 }
3148 #undef __SECONDARY_RELOAD_CASE
3149 }
3150 }
3151
3152 /* We need a scratch register when loading a PLUS expression which
3153 is not a legitimate operand of the LOAD ADDRESS instruction. */
3154 /* LRA can deal with transformation of plus op very well -- so we
3155 don't need to prompt LRA in this case. */
3156 if (! lra_in_progress && in_p && s390_plus_operand (x, mode))
3157 sri->icode = (TARGET_64BIT ?
3158 CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus);
3159
3160 /* Performing a multiword move from or to memory we have to make sure the
3161 second chunk in memory is addressable without causing a displacement
3162 overflow. If that would be the case we calculate the address in
3163 a scratch register. */
3164 if (MEM_P (x)
3165 && GET_CODE (XEXP (x, 0)) == PLUS
3166 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3167 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1))
3168 + GET_MODE_SIZE (mode) - 1))
3169 {
3170 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3171 in a s_operand address since we may fallback to lm/stm. So we only
3172 have to care about overflows in the b+i+d case. */
3173 if ((reg_classes_intersect_p (GENERAL_REGS, rclass)
3174 && s390_class_max_nregs (GENERAL_REGS, mode) > 1
3175 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
3176 /* For FP_REGS no lm/stm is available so this check is triggered
3177 for displacement overflows in b+i+d and b+d like addresses. */
3178 || (reg_classes_intersect_p (FP_REGS, rclass)
3179 && s390_class_max_nregs (FP_REGS, mode) > 1))
3180 {
3181 if (in_p)
3182 sri->icode = (TARGET_64BIT ?
3183 CODE_FOR_reloaddi_nonoffmem_in :
3184 CODE_FOR_reloadsi_nonoffmem_in);
3185 else
3186 sri->icode = (TARGET_64BIT ?
3187 CODE_FOR_reloaddi_nonoffmem_out :
3188 CODE_FOR_reloadsi_nonoffmem_out);
3189 }
3190 }
3191
3192 /* A scratch address register is needed when a symbolic constant is
3193 copied to r0 compiling with -fPIC. In other cases the target
3194 register might be used as temporary (see legitimize_pic_address). */
3195 if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS)
3196 sri->icode = (TARGET_64BIT ?
3197 CODE_FOR_reloaddi_PIC_addr :
3198 CODE_FOR_reloadsi_PIC_addr);
3199
3200 /* Either scratch or no register needed. */
3201 return NO_REGS;
3202 }
3203
3204 /* Generate code to load SRC, which is PLUS that is not a
3205 legitimate operand for the LA instruction, into TARGET.
3206 SCRATCH may be used as scratch register. */
3207
3208 void
3209 s390_expand_plus_operand (rtx target, rtx src,
3210 rtx scratch)
3211 {
3212 rtx sum1, sum2;
3213 struct s390_address ad;
3214
3215 /* src must be a PLUS; get its two operands. */
3216 gcc_assert (GET_CODE (src) == PLUS);
3217 gcc_assert (GET_MODE (src) == Pmode);
3218
3219 /* Check if any of the two operands is already scheduled
3220 for replacement by reload. This can happen e.g. when
3221 float registers occur in an address. */
3222 sum1 = find_replacement (&XEXP (src, 0));
3223 sum2 = find_replacement (&XEXP (src, 1));
3224 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3225
3226 /* If the address is already strictly valid, there's nothing to do. */
3227 if (!s390_decompose_address (src, &ad)
3228 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3229 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
3230 {
3231 /* Otherwise, one of the operands cannot be an address register;
3232 we reload its value into the scratch register. */
3233 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
3234 {
3235 emit_move_insn (scratch, sum1);
3236 sum1 = scratch;
3237 }
3238 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
3239 {
3240 emit_move_insn (scratch, sum2);
3241 sum2 = scratch;
3242 }
3243
3244 /* According to the way these invalid addresses are generated
3245 in reload.c, it should never happen (at least on s390) that
3246 *neither* of the PLUS components, after find_replacements
3247 was applied, is an address register. */
3248 if (sum1 == scratch && sum2 == scratch)
3249 {
3250 debug_rtx (src);
3251 gcc_unreachable ();
3252 }
3253
3254 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3255 }
3256
3257 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3258 is only ever performed on addresses, so we can mark the
3259 sum as legitimate for LA in any case. */
3260 s390_load_address (target, src);
3261 }
3262
3263
3264 /* Return true if ADDR is a valid memory address.
3265 STRICT specifies whether strict register checking applies. */
3266
3267 static bool
3268 s390_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
3269 {
3270 struct s390_address ad;
3271
3272 if (TARGET_Z10
3273 && larl_operand (addr, VOIDmode)
3274 && (mode == VOIDmode
3275 || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode))))
3276 return true;
3277
3278 if (!s390_decompose_address (addr, &ad))
3279 return false;
3280
3281 if (strict)
3282 {
3283 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3284 return false;
3285
3286 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
3287 return false;
3288 }
3289 else
3290 {
3291 if (ad.base
3292 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
3293 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
3294 return false;
3295
3296 if (ad.indx
3297 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
3298 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
3299 return false;
3300 }
3301 return true;
3302 }
3303
3304 /* Return true if OP is a valid operand for the LA instruction.
3305 In 31-bit, we need to prove that the result is used as an
3306 address, as LA performs only a 31-bit addition. */
3307
3308 bool
3309 legitimate_la_operand_p (rtx op)
3310 {
3311 struct s390_address addr;
3312 if (!s390_decompose_address (op, &addr))
3313 return false;
3314
3315 return (TARGET_64BIT || addr.pointer);
3316 }
3317
3318 /* Return true if it is valid *and* preferable to use LA to
3319 compute the sum of OP1 and OP2. */
3320
3321 bool
3322 preferred_la_operand_p (rtx op1, rtx op2)
3323 {
3324 struct s390_address addr;
3325
3326 if (op2 != const0_rtx)
3327 op1 = gen_rtx_PLUS (Pmode, op1, op2);
3328
3329 if (!s390_decompose_address (op1, &addr))
3330 return false;
3331 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
3332 return false;
3333 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
3334 return false;
3335
3336 /* Avoid LA instructions with index register on z196; it is
3337 preferable to use regular add instructions when possible.
3338 Starting with zEC12 the la with index register is "uncracked"
3339 again. */
3340 if (addr.indx && s390_tune == PROCESSOR_2817_Z196)
3341 return false;
3342
3343 if (!TARGET_64BIT && !addr.pointer)
3344 return false;
3345
3346 if (addr.pointer)
3347 return true;
3348
3349 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
3350 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
3351 return true;
3352
3353 return false;
3354 }
3355
3356 /* Emit a forced load-address operation to load SRC into DST.
3357 This will use the LOAD ADDRESS instruction even in situations
3358 where legitimate_la_operand_p (SRC) returns false. */
3359
3360 void
3361 s390_load_address (rtx dst, rtx src)
3362 {
3363 if (TARGET_64BIT)
3364 emit_move_insn (dst, src);
3365 else
3366 emit_insn (gen_force_la_31 (dst, src));
3367 }
3368
3369 /* Return a legitimate reference for ORIG (an address) using the
3370 register REG. If REG is 0, a new pseudo is generated.
3371
3372 There are two types of references that must be handled:
3373
3374 1. Global data references must load the address from the GOT, via
3375 the PIC reg. An insn is emitted to do this load, and the reg is
3376 returned.
3377
3378 2. Static data references, constant pool addresses, and code labels
3379 compute the address as an offset from the GOT, whose base is in
3380 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3381 differentiate them from global data objects. The returned
3382 address is the PIC reg + an unspec constant.
3383
3384 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3385 reg also appears in the address. */
3386
3387 rtx
3388 legitimize_pic_address (rtx orig, rtx reg)
3389 {
3390 rtx addr = orig;
3391 rtx addend = const0_rtx;
3392 rtx new_rtx = orig;
3393
3394 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
3395
3396 if (GET_CODE (addr) == CONST)
3397 addr = XEXP (addr, 0);
3398
3399 if (GET_CODE (addr) == PLUS)
3400 {
3401 addend = XEXP (addr, 1);
3402 addr = XEXP (addr, 0);
3403 }
3404
3405 if ((GET_CODE (addr) == LABEL_REF
3406 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr))
3407 || (GET_CODE (addr) == UNSPEC &&
3408 (XINT (addr, 1) == UNSPEC_GOTENT
3409 || (TARGET_CPU_ZARCH && XINT (addr, 1) == UNSPEC_PLT))))
3410 && GET_CODE (addend) == CONST_INT)
3411 {
3412 /* This can be locally addressed. */
3413
3414 /* larl_operand requires UNSPECs to be wrapped in a const rtx. */
3415 rtx const_addr = (GET_CODE (addr) == UNSPEC ?
3416 gen_rtx_CONST (Pmode, addr) : addr);
3417
3418 if (TARGET_CPU_ZARCH
3419 && larl_operand (const_addr, VOIDmode)
3420 && INTVAL (addend) < (HOST_WIDE_INT)1 << 31
3421 && INTVAL (addend) >= -((HOST_WIDE_INT)1 << 31))
3422 {
3423 if (INTVAL (addend) & 1)
3424 {
3425 /* LARL can't handle odd offsets, so emit a pair of LARL
3426 and LA. */
3427 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3428
3429 if (!DISP_IN_RANGE (INTVAL (addend)))
3430 {
3431 HOST_WIDE_INT even = INTVAL (addend) - 1;
3432 addr = gen_rtx_PLUS (Pmode, addr, GEN_INT (even));
3433 addr = gen_rtx_CONST (Pmode, addr);
3434 addend = const1_rtx;
3435 }
3436
3437 emit_move_insn (temp, addr);
3438 new_rtx = gen_rtx_PLUS (Pmode, temp, addend);
3439
3440 if (reg != 0)
3441 {
3442 s390_load_address (reg, new_rtx);
3443 new_rtx = reg;
3444 }
3445 }
3446 else
3447 {
3448 /* If the offset is even, we can just use LARL. This
3449 will happen automatically. */
3450 }
3451 }
3452 else
3453 {
3454 /* No larl - Access local symbols relative to the GOT. */
3455
3456 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3457
3458 if (reload_in_progress || reload_completed)
3459 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3460
3461 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
3462 if (addend != const0_rtx)
3463 addr = gen_rtx_PLUS (Pmode, addr, addend);
3464 addr = gen_rtx_CONST (Pmode, addr);
3465 addr = force_const_mem (Pmode, addr);
3466 emit_move_insn (temp, addr);
3467
3468 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3469 if (reg != 0)
3470 {
3471 s390_load_address (reg, new_rtx);
3472 new_rtx = reg;
3473 }
3474 }
3475 }
3476 else if (GET_CODE (addr) == SYMBOL_REF && addend == const0_rtx)
3477 {
3478 /* A non-local symbol reference without addend.
3479
3480 The symbol ref is wrapped into an UNSPEC to make sure the
3481 proper operand modifier (@GOT or @GOTENT) will be emitted.
3482 This will tell the linker to put the symbol into the GOT.
3483
3484 Additionally the code dereferencing the GOT slot is emitted here.
3485
3486 An addend to the symref needs to be added afterwards.
3487 legitimize_pic_address calls itself recursively to handle
3488 that case. So no need to do it here. */
3489
3490 if (reg == 0)
3491 reg = gen_reg_rtx (Pmode);
3492
3493 if (TARGET_Z10)
3494 {
3495 /* Use load relative if possible.
3496 lgrl <target>, sym@GOTENT */
3497 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3498 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3499 new_rtx = gen_const_mem (GET_MODE (reg), new_rtx);
3500
3501 emit_move_insn (reg, new_rtx);
3502 new_rtx = reg;
3503 }
3504 else if (flag_pic == 1)
3505 {
3506 /* Assume GOT offset is a valid displacement operand (< 4k
3507 or < 512k with z990). This is handled the same way in
3508 both 31- and 64-bit code (@GOT).
3509 lg <target>, sym@GOT(r12) */
3510
3511 if (reload_in_progress || reload_completed)
3512 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3513
3514 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3515 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3516 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3517 new_rtx = gen_const_mem (Pmode, new_rtx);
3518 emit_move_insn (reg, new_rtx);
3519 new_rtx = reg;
3520 }
3521 else if (TARGET_CPU_ZARCH)
3522 {
3523 /* If the GOT offset might be >= 4k, we determine the position
3524 of the GOT entry via a PC-relative LARL (@GOTENT).
3525 larl temp, sym@GOTENT
3526 lg <target>, 0(temp) */
3527
3528 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3529
3530 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3531 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3532
3533 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3534 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3535 emit_move_insn (temp, new_rtx);
3536
3537 new_rtx = gen_const_mem (Pmode, temp);
3538 emit_move_insn (reg, new_rtx);
3539
3540 new_rtx = reg;
3541 }
3542 else
3543 {
3544 /* If the GOT offset might be >= 4k, we have to load it
3545 from the literal pool (@GOT).
3546
3547 lg temp, lit-litbase(r13)
3548 lg <target>, 0(temp)
3549 lit: .long sym@GOT */
3550
3551 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3552
3553 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3554 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3555
3556 if (reload_in_progress || reload_completed)
3557 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3558
3559 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3560 addr = gen_rtx_CONST (Pmode, addr);
3561 addr = force_const_mem (Pmode, addr);
3562 emit_move_insn (temp, addr);
3563
3564 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3565 new_rtx = gen_const_mem (Pmode, new_rtx);
3566 emit_move_insn (reg, new_rtx);
3567 new_rtx = reg;
3568 }
3569 }
3570 else if (GET_CODE (addr) == UNSPEC && GET_CODE (addend) == CONST_INT)
3571 {
3572 gcc_assert (XVECLEN (addr, 0) == 1);
3573 switch (XINT (addr, 1))
3574 {
3575 /* These address symbols (or PLT slots) relative to the GOT
3576 (not GOT slots!). In general this will exceed the
3577 displacement range so these value belong into the literal
3578 pool. */
3579 case UNSPEC_GOTOFF:
3580 case UNSPEC_PLTOFF:
3581 new_rtx = force_const_mem (Pmode, orig);
3582 break;
3583
3584 /* For -fPIC the GOT size might exceed the displacement
3585 range so make sure the value is in the literal pool. */
3586 case UNSPEC_GOT:
3587 if (flag_pic == 2)
3588 new_rtx = force_const_mem (Pmode, orig);
3589 break;
3590
3591 /* For @GOTENT larl is used. This is handled like local
3592 symbol refs. */
3593 case UNSPEC_GOTENT:
3594 gcc_unreachable ();
3595 break;
3596
3597 /* @PLT is OK as is on 64-bit, must be converted to
3598 GOT-relative @PLTOFF on 31-bit. */
3599 case UNSPEC_PLT:
3600 if (!TARGET_CPU_ZARCH)
3601 {
3602 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3603
3604 if (reload_in_progress || reload_completed)
3605 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3606
3607 addr = XVECEXP (addr, 0, 0);
3608 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
3609 UNSPEC_PLTOFF);
3610 if (addend != const0_rtx)
3611 addr = gen_rtx_PLUS (Pmode, addr, addend);
3612 addr = gen_rtx_CONST (Pmode, addr);
3613 addr = force_const_mem (Pmode, addr);
3614 emit_move_insn (temp, addr);
3615
3616 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3617 if (reg != 0)
3618 {
3619 s390_load_address (reg, new_rtx);
3620 new_rtx = reg;
3621 }
3622 }
3623 else
3624 /* On 64 bit larl can be used. This case is handled like
3625 local symbol refs. */
3626 gcc_unreachable ();
3627 break;
3628
3629 /* Everything else cannot happen. */
3630 default:
3631 gcc_unreachable ();
3632 }
3633 }
3634 else if (addend != const0_rtx)
3635 {
3636 /* Otherwise, compute the sum. */
3637
3638 rtx base = legitimize_pic_address (addr, reg);
3639 new_rtx = legitimize_pic_address (addend,
3640 base == reg ? NULL_RTX : reg);
3641 if (GET_CODE (new_rtx) == CONST_INT)
3642 new_rtx = plus_constant (Pmode, base, INTVAL (new_rtx));
3643 else
3644 {
3645 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
3646 {
3647 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
3648 new_rtx = XEXP (new_rtx, 1);
3649 }
3650 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
3651 }
3652
3653 if (GET_CODE (new_rtx) == CONST)
3654 new_rtx = XEXP (new_rtx, 0);
3655 new_rtx = force_operand (new_rtx, 0);
3656 }
3657
3658 return new_rtx;
3659 }
3660
3661 /* Load the thread pointer into a register. */
3662
3663 rtx
3664 s390_get_thread_pointer (void)
3665 {
3666 rtx tp = gen_reg_rtx (Pmode);
3667
3668 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3669 mark_reg_pointer (tp, BITS_PER_WORD);
3670
3671 return tp;
3672 }
3673
3674 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3675 in s390_tls_symbol which always refers to __tls_get_offset.
3676 The returned offset is written to RESULT_REG and an USE rtx is
3677 generated for TLS_CALL. */
3678
3679 static GTY(()) rtx s390_tls_symbol;
3680
3681 static void
3682 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3683 {
3684 rtx insn;
3685
3686 if (!flag_pic)
3687 emit_insn (s390_load_got ());
3688
3689 if (!s390_tls_symbol)
3690 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3691
3692 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3693 gen_rtx_REG (Pmode, RETURN_REGNUM));
3694
3695 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3696 RTL_CONST_CALL_P (insn) = 1;
3697 }
3698
3699 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3700 this (thread-local) address. REG may be used as temporary. */
3701
3702 static rtx
3703 legitimize_tls_address (rtx addr, rtx reg)
3704 {
3705 rtx new_rtx, tls_call, temp, base, r2, insn;
3706
3707 if (GET_CODE (addr) == SYMBOL_REF)
3708 switch (tls_symbolic_operand (addr))
3709 {
3710 case TLS_MODEL_GLOBAL_DYNAMIC:
3711 start_sequence ();
3712 r2 = gen_rtx_REG (Pmode, 2);
3713 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3714 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3715 new_rtx = force_const_mem (Pmode, new_rtx);
3716 emit_move_insn (r2, new_rtx);
3717 s390_emit_tls_call_insn (r2, tls_call);
3718 insn = get_insns ();
3719 end_sequence ();
3720
3721 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3722 temp = gen_reg_rtx (Pmode);
3723 emit_libcall_block (insn, temp, r2, new_rtx);
3724
3725 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3726 if (reg != 0)
3727 {
3728 s390_load_address (reg, new_rtx);
3729 new_rtx = reg;
3730 }
3731 break;
3732
3733 case TLS_MODEL_LOCAL_DYNAMIC:
3734 start_sequence ();
3735 r2 = gen_rtx_REG (Pmode, 2);
3736 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3737 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3738 new_rtx = force_const_mem (Pmode, new_rtx);
3739 emit_move_insn (r2, new_rtx);
3740 s390_emit_tls_call_insn (r2, tls_call);
3741 insn = get_insns ();
3742 end_sequence ();
3743
3744 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3745 temp = gen_reg_rtx (Pmode);
3746 emit_libcall_block (insn, temp, r2, new_rtx);
3747
3748 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3749 base = gen_reg_rtx (Pmode);
3750 s390_load_address (base, new_rtx);
3751
3752 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3753 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3754 new_rtx = force_const_mem (Pmode, new_rtx);
3755 temp = gen_reg_rtx (Pmode);
3756 emit_move_insn (temp, new_rtx);
3757
3758 new_rtx = gen_rtx_PLUS (Pmode, base, temp);
3759 if (reg != 0)
3760 {
3761 s390_load_address (reg, new_rtx);
3762 new_rtx = reg;
3763 }
3764 break;
3765
3766 case TLS_MODEL_INITIAL_EXEC:
3767 if (flag_pic == 1)
3768 {
3769 /* Assume GOT offset < 4k. This is handled the same way
3770 in both 31- and 64-bit code. */
3771
3772 if (reload_in_progress || reload_completed)
3773 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3774
3775 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3776 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3777 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3778 new_rtx = gen_const_mem (Pmode, new_rtx);
3779 temp = gen_reg_rtx (Pmode);
3780 emit_move_insn (temp, new_rtx);
3781 }
3782 else if (TARGET_CPU_ZARCH)
3783 {
3784 /* If the GOT offset might be >= 4k, we determine the position
3785 of the GOT entry via a PC-relative LARL. */
3786
3787 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3788 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3789 temp = gen_reg_rtx (Pmode);
3790 emit_move_insn (temp, new_rtx);
3791
3792 new_rtx = gen_const_mem (Pmode, temp);
3793 temp = gen_reg_rtx (Pmode);
3794 emit_move_insn (temp, new_rtx);
3795 }
3796 else if (flag_pic)
3797 {
3798 /* If the GOT offset might be >= 4k, we have to load it
3799 from the literal pool. */
3800
3801 if (reload_in_progress || reload_completed)
3802 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3803
3804 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3805 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3806 new_rtx = force_const_mem (Pmode, new_rtx);
3807 temp = gen_reg_rtx (Pmode);
3808 emit_move_insn (temp, new_rtx);
3809
3810 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3811 new_rtx = gen_const_mem (Pmode, new_rtx);
3812
3813 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3814 temp = gen_reg_rtx (Pmode);
3815 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3816 }
3817 else
3818 {
3819 /* In position-dependent code, load the absolute address of
3820 the GOT entry from the literal pool. */
3821
3822 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3823 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3824 new_rtx = force_const_mem (Pmode, new_rtx);
3825 temp = gen_reg_rtx (Pmode);
3826 emit_move_insn (temp, new_rtx);
3827
3828 new_rtx = temp;
3829 new_rtx = gen_const_mem (Pmode, new_rtx);
3830 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3831 temp = gen_reg_rtx (Pmode);
3832 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3833 }
3834
3835 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3836 if (reg != 0)
3837 {
3838 s390_load_address (reg, new_rtx);
3839 new_rtx = reg;
3840 }
3841 break;
3842
3843 case TLS_MODEL_LOCAL_EXEC:
3844 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3845 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3846 new_rtx = force_const_mem (Pmode, new_rtx);
3847 temp = gen_reg_rtx (Pmode);
3848 emit_move_insn (temp, new_rtx);
3849
3850 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3851 if (reg != 0)
3852 {
3853 s390_load_address (reg, new_rtx);
3854 new_rtx = reg;
3855 }
3856 break;
3857
3858 default:
3859 gcc_unreachable ();
3860 }
3861
3862 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3863 {
3864 switch (XINT (XEXP (addr, 0), 1))
3865 {
3866 case UNSPEC_INDNTPOFF:
3867 gcc_assert (TARGET_CPU_ZARCH);
3868 new_rtx = addr;
3869 break;
3870
3871 default:
3872 gcc_unreachable ();
3873 }
3874 }
3875
3876 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3877 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3878 {
3879 new_rtx = XEXP (XEXP (addr, 0), 0);
3880 if (GET_CODE (new_rtx) != SYMBOL_REF)
3881 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3882
3883 new_rtx = legitimize_tls_address (new_rtx, reg);
3884 new_rtx = plus_constant (Pmode, new_rtx,
3885 INTVAL (XEXP (XEXP (addr, 0), 1)));
3886 new_rtx = force_operand (new_rtx, 0);
3887 }
3888
3889 else
3890 gcc_unreachable (); /* for now ... */
3891
3892 return new_rtx;
3893 }
3894
3895 /* Emit insns making the address in operands[1] valid for a standard
3896 move to operands[0]. operands[1] is replaced by an address which
3897 should be used instead of the former RTX to emit the move
3898 pattern. */
3899
3900 void
3901 emit_symbolic_move (rtx *operands)
3902 {
3903 rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
3904
3905 if (GET_CODE (operands[0]) == MEM)
3906 operands[1] = force_reg (Pmode, operands[1]);
3907 else if (TLS_SYMBOLIC_CONST (operands[1]))
3908 operands[1] = legitimize_tls_address (operands[1], temp);
3909 else if (flag_pic)
3910 operands[1] = legitimize_pic_address (operands[1], temp);
3911 }
3912
3913 /* Try machine-dependent ways of modifying an illegitimate address X
3914 to be legitimate. If we find one, return the new, valid address.
3915
3916 OLDX is the address as it was before break_out_memory_refs was called.
3917 In some cases it is useful to look at this to decide what needs to be done.
3918
3919 MODE is the mode of the operand pointed to by X.
3920
3921 When -fpic is used, special handling is needed for symbolic references.
3922 See comments by legitimize_pic_address for details. */
3923
3924 static rtx
3925 s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3926 enum machine_mode mode ATTRIBUTE_UNUSED)
3927 {
3928 rtx constant_term = const0_rtx;
3929
3930 if (TLS_SYMBOLIC_CONST (x))
3931 {
3932 x = legitimize_tls_address (x, 0);
3933
3934 if (s390_legitimate_address_p (mode, x, FALSE))
3935 return x;
3936 }
3937 else if (GET_CODE (x) == PLUS
3938 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
3939 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
3940 {
3941 return x;
3942 }
3943 else if (flag_pic)
3944 {
3945 if (SYMBOLIC_CONST (x)
3946 || (GET_CODE (x) == PLUS
3947 && (SYMBOLIC_CONST (XEXP (x, 0))
3948 || SYMBOLIC_CONST (XEXP (x, 1)))))
3949 x = legitimize_pic_address (x, 0);
3950
3951 if (s390_legitimate_address_p (mode, x, FALSE))
3952 return x;
3953 }
3954
3955 x = eliminate_constant_term (x, &constant_term);
3956
3957 /* Optimize loading of large displacements by splitting them
3958 into the multiple of 4K and the rest; this allows the
3959 former to be CSE'd if possible.
3960
3961 Don't do this if the displacement is added to a register
3962 pointing into the stack frame, as the offsets will
3963 change later anyway. */
3964
3965 if (GET_CODE (constant_term) == CONST_INT
3966 && !TARGET_LONG_DISPLACEMENT
3967 && !DISP_IN_RANGE (INTVAL (constant_term))
3968 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3969 {
3970 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3971 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3972
3973 rtx temp = gen_reg_rtx (Pmode);
3974 rtx val = force_operand (GEN_INT (upper), temp);
3975 if (val != temp)
3976 emit_move_insn (temp, val);
3977
3978 x = gen_rtx_PLUS (Pmode, x, temp);
3979 constant_term = GEN_INT (lower);
3980 }
3981
3982 if (GET_CODE (x) == PLUS)
3983 {
3984 if (GET_CODE (XEXP (x, 0)) == REG)
3985 {
3986 rtx temp = gen_reg_rtx (Pmode);
3987 rtx val = force_operand (XEXP (x, 1), temp);
3988 if (val != temp)
3989 emit_move_insn (temp, val);
3990
3991 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
3992 }
3993
3994 else if (GET_CODE (XEXP (x, 1)) == REG)
3995 {
3996 rtx temp = gen_reg_rtx (Pmode);
3997 rtx val = force_operand (XEXP (x, 0), temp);
3998 if (val != temp)
3999 emit_move_insn (temp, val);
4000
4001 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
4002 }
4003 }
4004
4005 if (constant_term != const0_rtx)
4006 x = gen_rtx_PLUS (Pmode, x, constant_term);
4007
4008 return x;
4009 }
4010
4011 /* Try a machine-dependent way of reloading an illegitimate address AD
4012 operand. If we find one, push the reload and return the new address.
4013
4014 MODE is the mode of the enclosing MEM. OPNUM is the operand number
4015 and TYPE is the reload type of the current reload. */
4016
4017 rtx
4018 legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
4019 int opnum, int type)
4020 {
4021 if (!optimize || TARGET_LONG_DISPLACEMENT)
4022 return NULL_RTX;
4023
4024 if (GET_CODE (ad) == PLUS)
4025 {
4026 rtx tem = simplify_binary_operation (PLUS, Pmode,
4027 XEXP (ad, 0), XEXP (ad, 1));
4028 if (tem)
4029 ad = tem;
4030 }
4031
4032 if (GET_CODE (ad) == PLUS
4033 && GET_CODE (XEXP (ad, 0)) == REG
4034 && GET_CODE (XEXP (ad, 1)) == CONST_INT
4035 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
4036 {
4037 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
4038 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
4039 rtx cst, tem, new_rtx;
4040
4041 cst = GEN_INT (upper);
4042 if (!legitimate_reload_constant_p (cst))
4043 cst = force_const_mem (Pmode, cst);
4044
4045 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
4046 new_rtx = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
4047
4048 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
4049 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
4050 opnum, (enum reload_type) type);
4051 return new_rtx;
4052 }
4053
4054 return NULL_RTX;
4055 }
4056
4057 /* Emit code to move LEN bytes from DST to SRC. */
4058
4059 bool
4060 s390_expand_movmem (rtx dst, rtx src, rtx len)
4061 {
4062 /* When tuning for z10 or higher we rely on the Glibc functions to
4063 do the right thing. Only for constant lengths below 64k we will
4064 generate inline code. */
4065 if (s390_tune >= PROCESSOR_2097_Z10
4066 && (GET_CODE (len) != CONST_INT || INTVAL (len) > (1<<16)))
4067 return false;
4068
4069 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4070 {
4071 if (INTVAL (len) > 0)
4072 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
4073 }
4074
4075 else if (TARGET_MVCLE)
4076 {
4077 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
4078 }
4079
4080 else
4081 {
4082 rtx dst_addr, src_addr, count, blocks, temp;
4083 rtx_code_label *loop_start_label = gen_label_rtx ();
4084 rtx_code_label *loop_end_label = gen_label_rtx ();
4085 rtx_code_label *end_label = gen_label_rtx ();
4086 enum machine_mode mode;
4087
4088 mode = GET_MODE (len);
4089 if (mode == VOIDmode)
4090 mode = Pmode;
4091
4092 dst_addr = gen_reg_rtx (Pmode);
4093 src_addr = gen_reg_rtx (Pmode);
4094 count = gen_reg_rtx (mode);
4095 blocks = gen_reg_rtx (mode);
4096
4097 convert_move (count, len, 1);
4098 emit_cmp_and_jump_insns (count, const0_rtx,
4099 EQ, NULL_RTX, mode, 1, end_label);
4100
4101 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4102 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
4103 dst = change_address (dst, VOIDmode, dst_addr);
4104 src = change_address (src, VOIDmode, src_addr);
4105
4106 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4107 OPTAB_DIRECT);
4108 if (temp != count)
4109 emit_move_insn (count, temp);
4110
4111 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4112 OPTAB_DIRECT);
4113 if (temp != blocks)
4114 emit_move_insn (blocks, temp);
4115
4116 emit_cmp_and_jump_insns (blocks, const0_rtx,
4117 EQ, NULL_RTX, mode, 1, loop_end_label);
4118
4119 emit_label (loop_start_label);
4120
4121 if (TARGET_Z10
4122 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 768))
4123 {
4124 rtx prefetch;
4125
4126 /* Issue a read prefetch for the +3 cache line. */
4127 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, src_addr, GEN_INT (768)),
4128 const0_rtx, const0_rtx);
4129 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4130 emit_insn (prefetch);
4131
4132 /* Issue a write prefetch for the +3 cache line. */
4133 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (768)),
4134 const1_rtx, const0_rtx);
4135 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4136 emit_insn (prefetch);
4137 }
4138
4139 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
4140 s390_load_address (dst_addr,
4141 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4142 s390_load_address (src_addr,
4143 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
4144
4145 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4146 OPTAB_DIRECT);
4147 if (temp != blocks)
4148 emit_move_insn (blocks, temp);
4149
4150 emit_cmp_and_jump_insns (blocks, const0_rtx,
4151 EQ, NULL_RTX, mode, 1, loop_end_label);
4152
4153 emit_jump (loop_start_label);
4154 emit_label (loop_end_label);
4155
4156 emit_insn (gen_movmem_short (dst, src,
4157 convert_to_mode (Pmode, count, 1)));
4158 emit_label (end_label);
4159 }
4160 return true;
4161 }
4162
4163 /* Emit code to set LEN bytes at DST to VAL.
4164 Make use of clrmem if VAL is zero. */
4165
4166 void
4167 s390_expand_setmem (rtx dst, rtx len, rtx val)
4168 {
4169 if (GET_CODE (len) == CONST_INT && INTVAL (len) == 0)
4170 return;
4171
4172 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
4173
4174 if (GET_CODE (len) == CONST_INT && INTVAL (len) > 0 && INTVAL (len) <= 257)
4175 {
4176 if (val == const0_rtx && INTVAL (len) <= 256)
4177 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
4178 else
4179 {
4180 /* Initialize memory by storing the first byte. */
4181 emit_move_insn (adjust_address (dst, QImode, 0), val);
4182
4183 if (INTVAL (len) > 1)
4184 {
4185 /* Initiate 1 byte overlap move.
4186 The first byte of DST is propagated through DSTP1.
4187 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
4188 DST is set to size 1 so the rest of the memory location
4189 does not count as source operand. */
4190 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
4191 set_mem_size (dst, 1);
4192
4193 emit_insn (gen_movmem_short (dstp1, dst,
4194 GEN_INT (INTVAL (len) - 2)));
4195 }
4196 }
4197 }
4198
4199 else if (TARGET_MVCLE)
4200 {
4201 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
4202 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
4203 }
4204
4205 else
4206 {
4207 rtx dst_addr, count, blocks, temp, dstp1 = NULL_RTX;
4208 rtx_code_label *loop_start_label = gen_label_rtx ();
4209 rtx_code_label *loop_end_label = gen_label_rtx ();
4210 rtx_code_label *end_label = gen_label_rtx ();
4211 enum machine_mode mode;
4212
4213 mode = GET_MODE (len);
4214 if (mode == VOIDmode)
4215 mode = Pmode;
4216
4217 dst_addr = gen_reg_rtx (Pmode);
4218 count = gen_reg_rtx (mode);
4219 blocks = gen_reg_rtx (mode);
4220
4221 convert_move (count, len, 1);
4222 emit_cmp_and_jump_insns (count, const0_rtx,
4223 EQ, NULL_RTX, mode, 1, end_label);
4224
4225 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4226 dst = change_address (dst, VOIDmode, dst_addr);
4227
4228 if (val == const0_rtx)
4229 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4230 OPTAB_DIRECT);
4231 else
4232 {
4233 dstp1 = adjust_address (dst, VOIDmode, 1);
4234 set_mem_size (dst, 1);
4235
4236 /* Initialize memory by storing the first byte. */
4237 emit_move_insn (adjust_address (dst, QImode, 0), val);
4238
4239 /* If count is 1 we are done. */
4240 emit_cmp_and_jump_insns (count, const1_rtx,
4241 EQ, NULL_RTX, mode, 1, end_label);
4242
4243 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1,
4244 OPTAB_DIRECT);
4245 }
4246 if (temp != count)
4247 emit_move_insn (count, temp);
4248
4249 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4250 OPTAB_DIRECT);
4251 if (temp != blocks)
4252 emit_move_insn (blocks, temp);
4253
4254 emit_cmp_and_jump_insns (blocks, const0_rtx,
4255 EQ, NULL_RTX, mode, 1, loop_end_label);
4256
4257 emit_label (loop_start_label);
4258
4259 if (TARGET_Z10
4260 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 1024))
4261 {
4262 /* Issue a write prefetch for the +4 cache line. */
4263 rtx prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr,
4264 GEN_INT (1024)),
4265 const1_rtx, const0_rtx);
4266 emit_insn (prefetch);
4267 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4268 }
4269
4270 if (val == const0_rtx)
4271 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
4272 else
4273 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
4274 s390_load_address (dst_addr,
4275 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4276
4277 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4278 OPTAB_DIRECT);
4279 if (temp != blocks)
4280 emit_move_insn (blocks, temp);
4281
4282 emit_cmp_and_jump_insns (blocks, const0_rtx,
4283 EQ, NULL_RTX, mode, 1, loop_end_label);
4284
4285 emit_jump (loop_start_label);
4286 emit_label (loop_end_label);
4287
4288 if (val == const0_rtx)
4289 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
4290 else
4291 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
4292 emit_label (end_label);
4293 }
4294 }
4295
4296 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4297 and return the result in TARGET. */
4298
4299 bool
4300 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
4301 {
4302 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
4303 rtx tmp;
4304
4305 /* When tuning for z10 or higher we rely on the Glibc functions to
4306 do the right thing. Only for constant lengths below 64k we will
4307 generate inline code. */
4308 if (s390_tune >= PROCESSOR_2097_Z10
4309 && (GET_CODE (len) != CONST_INT || INTVAL (len) > (1<<16)))
4310 return false;
4311
4312 /* As the result of CMPINT is inverted compared to what we need,
4313 we have to swap the operands. */
4314 tmp = op0; op0 = op1; op1 = tmp;
4315
4316 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4317 {
4318 if (INTVAL (len) > 0)
4319 {
4320 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
4321 emit_insn (gen_cmpint (target, ccreg));
4322 }
4323 else
4324 emit_move_insn (target, const0_rtx);
4325 }
4326 else if (TARGET_MVCLE)
4327 {
4328 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
4329 emit_insn (gen_cmpint (target, ccreg));
4330 }
4331 else
4332 {
4333 rtx addr0, addr1, count, blocks, temp;
4334 rtx_code_label *loop_start_label = gen_label_rtx ();
4335 rtx_code_label *loop_end_label = gen_label_rtx ();
4336 rtx_code_label *end_label = gen_label_rtx ();
4337 enum machine_mode mode;
4338
4339 mode = GET_MODE (len);
4340 if (mode == VOIDmode)
4341 mode = Pmode;
4342
4343 addr0 = gen_reg_rtx (Pmode);
4344 addr1 = gen_reg_rtx (Pmode);
4345 count = gen_reg_rtx (mode);
4346 blocks = gen_reg_rtx (mode);
4347
4348 convert_move (count, len, 1);
4349 emit_cmp_and_jump_insns (count, const0_rtx,
4350 EQ, NULL_RTX, mode, 1, end_label);
4351
4352 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
4353 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
4354 op0 = change_address (op0, VOIDmode, addr0);
4355 op1 = change_address (op1, VOIDmode, addr1);
4356
4357 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4358 OPTAB_DIRECT);
4359 if (temp != count)
4360 emit_move_insn (count, temp);
4361
4362 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4363 OPTAB_DIRECT);
4364 if (temp != blocks)
4365 emit_move_insn (blocks, temp);
4366
4367 emit_cmp_and_jump_insns (blocks, const0_rtx,
4368 EQ, NULL_RTX, mode, 1, loop_end_label);
4369
4370 emit_label (loop_start_label);
4371
4372 if (TARGET_Z10
4373 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 512))
4374 {
4375 rtx prefetch;
4376
4377 /* Issue a read prefetch for the +2 cache line of operand 1. */
4378 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr0, GEN_INT (512)),
4379 const0_rtx, const0_rtx);
4380 emit_insn (prefetch);
4381 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4382
4383 /* Issue a read prefetch for the +2 cache line of operand 2. */
4384 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr1, GEN_INT (512)),
4385 const0_rtx, const0_rtx);
4386 emit_insn (prefetch);
4387 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4388 }
4389
4390 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
4391 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
4392 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
4393 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
4394 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
4395 emit_jump_insn (temp);
4396
4397 s390_load_address (addr0,
4398 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
4399 s390_load_address (addr1,
4400 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
4401
4402 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4403 OPTAB_DIRECT);
4404 if (temp != blocks)
4405 emit_move_insn (blocks, temp);
4406
4407 emit_cmp_and_jump_insns (blocks, const0_rtx,
4408 EQ, NULL_RTX, mode, 1, loop_end_label);
4409
4410 emit_jump (loop_start_label);
4411 emit_label (loop_end_label);
4412
4413 emit_insn (gen_cmpmem_short (op0, op1,
4414 convert_to_mode (Pmode, count, 1)));
4415 emit_label (end_label);
4416
4417 emit_insn (gen_cmpint (target, ccreg));
4418 }
4419 return true;
4420 }
4421
4422
4423 /* Expand conditional increment or decrement using alc/slb instructions.
4424 Should generate code setting DST to either SRC or SRC + INCREMENT,
4425 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4426 Returns true if successful, false otherwise.
4427
4428 That makes it possible to implement some if-constructs without jumps e.g.:
4429 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4430 unsigned int a, b, c;
4431 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4432 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4433 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4434 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4435
4436 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4437 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4438 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4439 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4440 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4441
4442 bool
4443 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
4444 rtx dst, rtx src, rtx increment)
4445 {
4446 enum machine_mode cmp_mode;
4447 enum machine_mode cc_mode;
4448 rtx op_res;
4449 rtx insn;
4450 rtvec p;
4451 int ret;
4452
4453 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
4454 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
4455 cmp_mode = SImode;
4456 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
4457 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
4458 cmp_mode = DImode;
4459 else
4460 return false;
4461
4462 /* Try ADD LOGICAL WITH CARRY. */
4463 if (increment == const1_rtx)
4464 {
4465 /* Determine CC mode to use. */
4466 if (cmp_code == EQ || cmp_code == NE)
4467 {
4468 if (cmp_op1 != const0_rtx)
4469 {
4470 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4471 NULL_RTX, 0, OPTAB_WIDEN);
4472 cmp_op1 = const0_rtx;
4473 }
4474
4475 cmp_code = cmp_code == EQ ? LEU : GTU;
4476 }
4477
4478 if (cmp_code == LTU || cmp_code == LEU)
4479 {
4480 rtx tem = cmp_op0;
4481 cmp_op0 = cmp_op1;
4482 cmp_op1 = tem;
4483 cmp_code = swap_condition (cmp_code);
4484 }
4485
4486 switch (cmp_code)
4487 {
4488 case GTU:
4489 cc_mode = CCUmode;
4490 break;
4491
4492 case GEU:
4493 cc_mode = CCL3mode;
4494 break;
4495
4496 default:
4497 return false;
4498 }
4499
4500 /* Emit comparison instruction pattern. */
4501 if (!register_operand (cmp_op0, cmp_mode))
4502 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4503
4504 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4505 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4506 /* We use insn_invalid_p here to add clobbers if required. */
4507 ret = insn_invalid_p (emit_insn (insn), false);
4508 gcc_assert (!ret);
4509
4510 /* Emit ALC instruction pattern. */
4511 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4512 gen_rtx_REG (cc_mode, CC_REGNUM),
4513 const0_rtx);
4514
4515 if (src != const0_rtx)
4516 {
4517 if (!register_operand (src, GET_MODE (dst)))
4518 src = force_reg (GET_MODE (dst), src);
4519
4520 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src);
4521 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx);
4522 }
4523
4524 p = rtvec_alloc (2);
4525 RTVEC_ELT (p, 0) =
4526 gen_rtx_SET (VOIDmode, dst, op_res);
4527 RTVEC_ELT (p, 1) =
4528 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4529 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4530
4531 return true;
4532 }
4533
4534 /* Try SUBTRACT LOGICAL WITH BORROW. */
4535 if (increment == constm1_rtx)
4536 {
4537 /* Determine CC mode to use. */
4538 if (cmp_code == EQ || cmp_code == NE)
4539 {
4540 if (cmp_op1 != const0_rtx)
4541 {
4542 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4543 NULL_RTX, 0, OPTAB_WIDEN);
4544 cmp_op1 = const0_rtx;
4545 }
4546
4547 cmp_code = cmp_code == EQ ? LEU : GTU;
4548 }
4549
4550 if (cmp_code == GTU || cmp_code == GEU)
4551 {
4552 rtx tem = cmp_op0;
4553 cmp_op0 = cmp_op1;
4554 cmp_op1 = tem;
4555 cmp_code = swap_condition (cmp_code);
4556 }
4557
4558 switch (cmp_code)
4559 {
4560 case LEU:
4561 cc_mode = CCUmode;
4562 break;
4563
4564 case LTU:
4565 cc_mode = CCL3mode;
4566 break;
4567
4568 default:
4569 return false;
4570 }
4571
4572 /* Emit comparison instruction pattern. */
4573 if (!register_operand (cmp_op0, cmp_mode))
4574 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4575
4576 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4577 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4578 /* We use insn_invalid_p here to add clobbers if required. */
4579 ret = insn_invalid_p (emit_insn (insn), false);
4580 gcc_assert (!ret);
4581
4582 /* Emit SLB instruction pattern. */
4583 if (!register_operand (src, GET_MODE (dst)))
4584 src = force_reg (GET_MODE (dst), src);
4585
4586 op_res = gen_rtx_MINUS (GET_MODE (dst),
4587 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
4588 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4589 gen_rtx_REG (cc_mode, CC_REGNUM),
4590 const0_rtx));
4591 p = rtvec_alloc (2);
4592 RTVEC_ELT (p, 0) =
4593 gen_rtx_SET (VOIDmode, dst, op_res);
4594 RTVEC_ELT (p, 1) =
4595 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4596 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4597
4598 return true;
4599 }
4600
4601 return false;
4602 }
4603
4604 /* Expand code for the insv template. Return true if successful. */
4605
4606 bool
4607 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
4608 {
4609 int bitsize = INTVAL (op1);
4610 int bitpos = INTVAL (op2);
4611 enum machine_mode mode = GET_MODE (dest);
4612 enum machine_mode smode;
4613 int smode_bsize, mode_bsize;
4614 rtx op, clobber;
4615
4616 if (bitsize + bitpos > GET_MODE_BITSIZE (mode))
4617 return false;
4618
4619 /* Generate INSERT IMMEDIATE (IILL et al). */
4620 /* (set (ze (reg)) (const_int)). */
4621 if (TARGET_ZARCH
4622 && register_operand (dest, word_mode)
4623 && (bitpos % 16) == 0
4624 && (bitsize % 16) == 0
4625 && const_int_operand (src, VOIDmode))
4626 {
4627 HOST_WIDE_INT val = INTVAL (src);
4628 int regpos = bitpos + bitsize;
4629
4630 while (regpos > bitpos)
4631 {
4632 enum machine_mode putmode;
4633 int putsize;
4634
4635 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4636 putmode = SImode;
4637 else
4638 putmode = HImode;
4639
4640 putsize = GET_MODE_BITSIZE (putmode);
4641 regpos -= putsize;
4642 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4643 GEN_INT (putsize),
4644 GEN_INT (regpos)),
4645 gen_int_mode (val, putmode));
4646 val >>= putsize;
4647 }
4648 gcc_assert (regpos == bitpos);
4649 return true;
4650 }
4651
4652 smode = smallest_mode_for_size (bitsize, MODE_INT);
4653 smode_bsize = GET_MODE_BITSIZE (smode);
4654 mode_bsize = GET_MODE_BITSIZE (mode);
4655
4656 /* Generate STORE CHARACTERS UNDER MASK (STCM et al). */
4657 if (bitpos == 0
4658 && (bitsize % BITS_PER_UNIT) == 0
4659 && MEM_P (dest)
4660 && (register_operand (src, word_mode)
4661 || const_int_operand (src, VOIDmode)))
4662 {
4663 /* Emit standard pattern if possible. */
4664 if (smode_bsize == bitsize)
4665 {
4666 emit_move_insn (adjust_address (dest, smode, 0),
4667 gen_lowpart (smode, src));
4668 return true;
4669 }
4670
4671 /* (set (ze (mem)) (const_int)). */
4672 else if (const_int_operand (src, VOIDmode))
4673 {
4674 int size = bitsize / BITS_PER_UNIT;
4675 rtx src_mem = adjust_address (force_const_mem (word_mode, src),
4676 BLKmode,
4677 UNITS_PER_WORD - size);
4678
4679 dest = adjust_address (dest, BLKmode, 0);
4680 set_mem_size (dest, size);
4681 s390_expand_movmem (dest, src_mem, GEN_INT (size));
4682 return true;
4683 }
4684
4685 /* (set (ze (mem)) (reg)). */
4686 else if (register_operand (src, word_mode))
4687 {
4688 if (bitsize <= 32)
4689 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4690 const0_rtx), src);
4691 else
4692 {
4693 /* Emit st,stcmh sequence. */
4694 int stcmh_width = bitsize - 32;
4695 int size = stcmh_width / BITS_PER_UNIT;
4696
4697 emit_move_insn (adjust_address (dest, SImode, size),
4698 gen_lowpart (SImode, src));
4699 set_mem_size (dest, size);
4700 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4701 GEN_INT (stcmh_width),
4702 const0_rtx),
4703 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT (32)));
4704 }
4705 return true;
4706 }
4707 }
4708
4709 /* Generate INSERT CHARACTERS UNDER MASK (IC, ICM et al). */
4710 if ((bitpos % BITS_PER_UNIT) == 0
4711 && (bitsize % BITS_PER_UNIT) == 0
4712 && (bitpos & 32) == ((bitpos + bitsize - 1) & 32)
4713 && MEM_P (src)
4714 && (mode == DImode || mode == SImode)
4715 && register_operand (dest, mode))
4716 {
4717 /* Emit a strict_low_part pattern if possible. */
4718 if (smode_bsize == bitsize && bitpos == mode_bsize - smode_bsize)
4719 {
4720 op = gen_rtx_STRICT_LOW_PART (VOIDmode, gen_lowpart (smode, dest));
4721 op = gen_rtx_SET (VOIDmode, op, gen_lowpart (smode, src));
4722 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4723 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)));
4724 return true;
4725 }
4726
4727 /* ??? There are more powerful versions of ICM that are not
4728 completely represented in the md file. */
4729 }
4730
4731 /* For z10, generate ROTATE THEN INSERT SELECTED BITS (RISBG et al). */
4732 if (TARGET_Z10 && (mode == DImode || mode == SImode))
4733 {
4734 enum machine_mode mode_s = GET_MODE (src);
4735
4736 if (mode_s == VOIDmode)
4737 {
4738 /* Assume const_int etc already in the proper mode. */
4739 src = force_reg (mode, src);
4740 }
4741 else if (mode_s != mode)
4742 {
4743 gcc_assert (GET_MODE_BITSIZE (mode_s) >= bitsize);
4744 src = force_reg (mode_s, src);
4745 src = gen_lowpart (mode, src);
4746 }
4747
4748 op = gen_rtx_ZERO_EXTRACT (mode, dest, op1, op2),
4749 op = gen_rtx_SET (VOIDmode, op, src);
4750
4751 if (!TARGET_ZEC12)
4752 {
4753 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4754 op = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber));
4755 }
4756 emit_insn (op);
4757
4758 return true;
4759 }
4760
4761 return false;
4762 }
4763
4764 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4765 register that holds VAL of mode MODE shifted by COUNT bits. */
4766
4767 static inline rtx
4768 s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
4769 {
4770 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4771 NULL_RTX, 1, OPTAB_DIRECT);
4772 return expand_simple_binop (SImode, ASHIFT, val, count,
4773 NULL_RTX, 1, OPTAB_DIRECT);
4774 }
4775
4776 /* Structure to hold the initial parameters for a compare_and_swap operation
4777 in HImode and QImode. */
4778
4779 struct alignment_context
4780 {
4781 rtx memsi; /* SI aligned memory location. */
4782 rtx shift; /* Bit offset with regard to lsb. */
4783 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4784 rtx modemaski; /* ~modemask */
4785 bool aligned; /* True if memory is aligned, false else. */
4786 };
4787
4788 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4789 structure AC for transparent simplifying, if the memory alignment is known
4790 to be at least 32bit. MEM is the memory location for the actual operation
4791 and MODE its mode. */
4792
4793 static void
4794 init_alignment_context (struct alignment_context *ac, rtx mem,
4795 enum machine_mode mode)
4796 {
4797 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4798 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4799
4800 if (ac->aligned)
4801 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4802 else
4803 {
4804 /* Alignment is unknown. */
4805 rtx byteoffset, addr, align;
4806
4807 /* Force the address into a register. */
4808 addr = force_reg (Pmode, XEXP (mem, 0));
4809
4810 /* Align it to SImode. */
4811 align = expand_simple_binop (Pmode, AND, addr,
4812 GEN_INT (-GET_MODE_SIZE (SImode)),
4813 NULL_RTX, 1, OPTAB_DIRECT);
4814 /* Generate MEM. */
4815 ac->memsi = gen_rtx_MEM (SImode, align);
4816 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4817 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4818 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4819
4820 /* Calculate shiftcount. */
4821 byteoffset = expand_simple_binop (Pmode, AND, addr,
4822 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4823 NULL_RTX, 1, OPTAB_DIRECT);
4824 /* As we already have some offset, evaluate the remaining distance. */
4825 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4826 NULL_RTX, 1, OPTAB_DIRECT);
4827 }
4828
4829 /* Shift is the byte count, but we need the bitcount. */
4830 ac->shift = expand_simple_binop (SImode, ASHIFT, ac->shift, GEN_INT (3),
4831 NULL_RTX, 1, OPTAB_DIRECT);
4832
4833 /* Calculate masks. */
4834 ac->modemask = expand_simple_binop (SImode, ASHIFT,
4835 GEN_INT (GET_MODE_MASK (mode)),
4836 ac->shift, NULL_RTX, 1, OPTAB_DIRECT);
4837 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask,
4838 NULL_RTX, 1);
4839 }
4840
4841 /* A subroutine of s390_expand_cs_hqi. Insert INS into VAL. If possible,
4842 use a single insv insn into SEQ2. Otherwise, put prep insns in SEQ1 and
4843 perform the merge in SEQ2. */
4844
4845 static rtx
4846 s390_two_part_insv (struct alignment_context *ac, rtx *seq1, rtx *seq2,
4847 enum machine_mode mode, rtx val, rtx ins)
4848 {
4849 rtx tmp;
4850
4851 if (ac->aligned)
4852 {
4853 start_sequence ();
4854 tmp = copy_to_mode_reg (SImode, val);
4855 if (s390_expand_insv (tmp, GEN_INT (GET_MODE_BITSIZE (mode)),
4856 const0_rtx, ins))
4857 {
4858 *seq1 = NULL;
4859 *seq2 = get_insns ();
4860 end_sequence ();
4861 return tmp;
4862 }
4863 end_sequence ();
4864 }
4865
4866 /* Failed to use insv. Generate a two part shift and mask. */
4867 start_sequence ();
4868 tmp = s390_expand_mask_and_shift (ins, mode, ac->shift);
4869 *seq1 = get_insns ();
4870 end_sequence ();
4871
4872 start_sequence ();
4873 tmp = expand_simple_binop (SImode, IOR, tmp, val, NULL_RTX, 1, OPTAB_DIRECT);
4874 *seq2 = get_insns ();
4875 end_sequence ();
4876
4877 return tmp;
4878 }
4879
4880 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4881 the memory location, CMP the old value to compare MEM with and NEW_RTX the
4882 value to set if CMP == MEM. */
4883
4884 void
4885 s390_expand_cs_hqi (enum machine_mode mode, rtx btarget, rtx vtarget, rtx mem,
4886 rtx cmp, rtx new_rtx, bool is_weak)
4887 {
4888 struct alignment_context ac;
4889 rtx cmpv, newv, val, cc, seq0, seq1, seq2, seq3;
4890 rtx res = gen_reg_rtx (SImode);
4891 rtx_code_label *csloop = NULL, *csend = NULL;
4892
4893 gcc_assert (MEM_P (mem));
4894
4895 init_alignment_context (&ac, mem, mode);
4896
4897 /* Load full word. Subsequent loads are performed by CS. */
4898 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4899 NULL_RTX, 1, OPTAB_DIRECT);
4900
4901 /* Prepare insertions of cmp and new_rtx into the loaded value. When
4902 possible, we try to use insv to make this happen efficiently. If
4903 that fails we'll generate code both inside and outside the loop. */
4904 cmpv = s390_two_part_insv (&ac, &seq0, &seq2, mode, val, cmp);
4905 newv = s390_two_part_insv (&ac, &seq1, &seq3, mode, val, new_rtx);
4906
4907 if (seq0)
4908 emit_insn (seq0);
4909 if (seq1)
4910 emit_insn (seq1);
4911
4912 /* Start CS loop. */
4913 if (!is_weak)
4914 {
4915 /* Begin assuming success. */
4916 emit_move_insn (btarget, const1_rtx);
4917
4918 csloop = gen_label_rtx ();
4919 csend = gen_label_rtx ();
4920 emit_label (csloop);
4921 }
4922
4923 /* val = "<mem>00..0<mem>"
4924 * cmp = "00..0<cmp>00..0"
4925 * new = "00..0<new>00..0"
4926 */
4927
4928 emit_insn (seq2);
4929 emit_insn (seq3);
4930
4931 cc = s390_emit_compare_and_swap (EQ, res, ac.memsi, cmpv, newv);
4932 if (is_weak)
4933 emit_insn (gen_cstorecc4 (btarget, cc, XEXP (cc, 0), XEXP (cc, 1)));
4934 else
4935 {
4936 rtx tmp;
4937
4938 /* Jump to end if we're done (likely?). */
4939 s390_emit_jump (csend, cc);
4940
4941 /* Check for changes outside mode, and loop internal if so.
4942 Arrange the moves so that the compare is adjacent to the
4943 branch so that we can generate CRJ. */
4944 tmp = copy_to_reg (val);
4945 force_expand_binop (SImode, and_optab, res, ac.modemaski, val,
4946 1, OPTAB_DIRECT);
4947 cc = s390_emit_compare (NE, val, tmp);
4948 s390_emit_jump (csloop, cc);
4949
4950 /* Failed. */
4951 emit_move_insn (btarget, const0_rtx);
4952 emit_label (csend);
4953 }
4954
4955 /* Return the correct part of the bitfield. */
4956 convert_move (vtarget, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4957 NULL_RTX, 1, OPTAB_DIRECT), 1);
4958 }
4959
4960 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4961 and VAL the value to play with. If AFTER is true then store the value
4962 MEM holds after the operation, if AFTER is false then store the value MEM
4963 holds before the operation. If TARGET is zero then discard that value, else
4964 store it to TARGET. */
4965
4966 void
4967 s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
4968 rtx target, rtx mem, rtx val, bool after)
4969 {
4970 struct alignment_context ac;
4971 rtx cmp;
4972 rtx new_rtx = gen_reg_rtx (SImode);
4973 rtx orig = gen_reg_rtx (SImode);
4974 rtx_code_label *csloop = gen_label_rtx ();
4975
4976 gcc_assert (!target || register_operand (target, VOIDmode));
4977 gcc_assert (MEM_P (mem));
4978
4979 init_alignment_context (&ac, mem, mode);
4980
4981 /* Shift val to the correct bit positions.
4982 Preserve "icm", but prevent "ex icm". */
4983 if (!(ac.aligned && code == SET && MEM_P (val)))
4984 val = s390_expand_mask_and_shift (val, mode, ac.shift);
4985
4986 /* Further preparation insns. */
4987 if (code == PLUS || code == MINUS)
4988 emit_move_insn (orig, val);
4989 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4990 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
4991 NULL_RTX, 1, OPTAB_DIRECT);
4992
4993 /* Load full word. Subsequent loads are performed by CS. */
4994 cmp = force_reg (SImode, ac.memsi);
4995
4996 /* Start CS loop. */
4997 emit_label (csloop);
4998 emit_move_insn (new_rtx, cmp);
4999
5000 /* Patch new with val at correct position. */
5001 switch (code)
5002 {
5003 case PLUS:
5004 case MINUS:
5005 val = expand_simple_binop (SImode, code, new_rtx, orig,
5006 NULL_RTX, 1, OPTAB_DIRECT);
5007 val = expand_simple_binop (SImode, AND, val, ac.modemask,
5008 NULL_RTX, 1, OPTAB_DIRECT);
5009 /* FALLTHRU */
5010 case SET:
5011 if (ac.aligned && MEM_P (val))
5012 store_bit_field (new_rtx, GET_MODE_BITSIZE (mode), 0,
5013 0, 0, SImode, val);
5014 else
5015 {
5016 new_rtx = expand_simple_binop (SImode, AND, new_rtx, ac.modemaski,
5017 NULL_RTX, 1, OPTAB_DIRECT);
5018 new_rtx = expand_simple_binop (SImode, IOR, new_rtx, val,
5019 NULL_RTX, 1, OPTAB_DIRECT);
5020 }
5021 break;
5022 case AND:
5023 case IOR:
5024 case XOR:
5025 new_rtx = expand_simple_binop (SImode, code, new_rtx, val,
5026 NULL_RTX, 1, OPTAB_DIRECT);
5027 break;
5028 case MULT: /* NAND */
5029 new_rtx = expand_simple_binop (SImode, AND, new_rtx, val,
5030 NULL_RTX, 1, OPTAB_DIRECT);
5031 new_rtx = expand_simple_binop (SImode, XOR, new_rtx, ac.modemask,
5032 NULL_RTX, 1, OPTAB_DIRECT);
5033 break;
5034 default:
5035 gcc_unreachable ();
5036 }
5037
5038 s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp,
5039 ac.memsi, cmp, new_rtx));
5040
5041 /* Return the correct part of the bitfield. */
5042 if (target)
5043 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
5044 after ? new_rtx : cmp, ac.shift,
5045 NULL_RTX, 1, OPTAB_DIRECT), 1);
5046 }
5047
5048 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
5049 We need to emit DTP-relative relocations. */
5050
5051 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
5052
5053 static void
5054 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
5055 {
5056 switch (size)
5057 {
5058 case 4:
5059 fputs ("\t.long\t", file);
5060 break;
5061 case 8:
5062 fputs ("\t.quad\t", file);
5063 break;
5064 default:
5065 gcc_unreachable ();
5066 }
5067 output_addr_const (file, x);
5068 fputs ("@DTPOFF", file);
5069 }
5070
5071 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
5072 /* Implement TARGET_MANGLE_TYPE. */
5073
5074 static const char *
5075 s390_mangle_type (const_tree type)
5076 {
5077 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
5078 && TARGET_LONG_DOUBLE_128)
5079 return "g";
5080
5081 /* For all other types, use normal C++ mangling. */
5082 return NULL;
5083 }
5084 #endif
5085
5086 /* In the name of slightly smaller debug output, and to cater to
5087 general assembler lossage, recognize various UNSPEC sequences
5088 and turn them back into a direct symbol reference. */
5089
5090 static rtx
5091 s390_delegitimize_address (rtx orig_x)
5092 {
5093 rtx x, y;
5094
5095 orig_x = delegitimize_mem_from_attrs (orig_x);
5096 x = orig_x;
5097
5098 /* Extract the symbol ref from:
5099 (plus:SI (reg:SI 12 %r12)
5100 (const:SI (unspec:SI [(symbol_ref/f:SI ("*.LC0"))]
5101 UNSPEC_GOTOFF/PLTOFF)))
5102 and
5103 (plus:SI (reg:SI 12 %r12)
5104 (const:SI (plus:SI (unspec:SI [(symbol_ref:SI ("L"))]
5105 UNSPEC_GOTOFF/PLTOFF)
5106 (const_int 4 [0x4])))) */
5107 if (GET_CODE (x) == PLUS
5108 && REG_P (XEXP (x, 0))
5109 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM
5110 && GET_CODE (XEXP (x, 1)) == CONST)
5111 {
5112 HOST_WIDE_INT offset = 0;
5113
5114 /* The const operand. */
5115 y = XEXP (XEXP (x, 1), 0);
5116
5117 if (GET_CODE (y) == PLUS
5118 && GET_CODE (XEXP (y, 1)) == CONST_INT)
5119 {
5120 offset = INTVAL (XEXP (y, 1));
5121 y = XEXP (y, 0);
5122 }
5123
5124 if (GET_CODE (y) == UNSPEC
5125 && (XINT (y, 1) == UNSPEC_GOTOFF
5126 || XINT (y, 1) == UNSPEC_PLTOFF))
5127 return plus_constant (Pmode, XVECEXP (y, 0, 0), offset);
5128 }
5129
5130 if (GET_CODE (x) != MEM)
5131 return orig_x;
5132
5133 x = XEXP (x, 0);
5134 if (GET_CODE (x) == PLUS
5135 && GET_CODE (XEXP (x, 1)) == CONST
5136 && GET_CODE (XEXP (x, 0)) == REG
5137 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
5138 {
5139 y = XEXP (XEXP (x, 1), 0);
5140 if (GET_CODE (y) == UNSPEC
5141 && XINT (y, 1) == UNSPEC_GOT)
5142 y = XVECEXP (y, 0, 0);
5143 else
5144 return orig_x;
5145 }
5146 else if (GET_CODE (x) == CONST)
5147 {
5148 /* Extract the symbol ref from:
5149 (mem:QI (const:DI (unspec:DI [(symbol_ref:DI ("foo"))]
5150 UNSPEC_PLT/GOTENT))) */
5151
5152 y = XEXP (x, 0);
5153 if (GET_CODE (y) == UNSPEC
5154 && (XINT (y, 1) == UNSPEC_GOTENT
5155 || XINT (y, 1) == UNSPEC_PLT))
5156 y = XVECEXP (y, 0, 0);
5157 else
5158 return orig_x;
5159 }
5160 else
5161 return orig_x;
5162
5163 if (GET_MODE (orig_x) != Pmode)
5164 {
5165 if (GET_MODE (orig_x) == BLKmode)
5166 return orig_x;
5167 y = lowpart_subreg (GET_MODE (orig_x), y, Pmode);
5168 if (y == NULL_RTX)
5169 return orig_x;
5170 }
5171 return y;
5172 }
5173
5174 /* Output operand OP to stdio stream FILE.
5175 OP is an address (register + offset) which is not used to address data;
5176 instead the rightmost bits are interpreted as the value. */
5177
5178 static void
5179 print_shift_count_operand (FILE *file, rtx op)
5180 {
5181 HOST_WIDE_INT offset;
5182 rtx base;
5183
5184 /* Extract base register and offset. */
5185 if (!s390_decompose_shift_count (op, &base, &offset))
5186 gcc_unreachable ();
5187
5188 /* Sanity check. */
5189 if (base)
5190 {
5191 gcc_assert (GET_CODE (base) == REG);
5192 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
5193 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
5194 }
5195
5196 /* Offsets are constricted to twelve bits. */
5197 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
5198 if (base)
5199 fprintf (file, "(%s)", reg_names[REGNO (base)]);
5200 }
5201
5202 /* Returns -1 if the function should not be made hotpatchable. Otherwise it
5203 returns a number >= 0 that is the desired size of the hotpatch trampoline
5204 in halfwords. */
5205
5206 static int s390_function_num_hotpatch_trampoline_halfwords (tree decl,
5207 bool do_warn)
5208 {
5209 tree attr;
5210
5211 if (DECL_DECLARED_INLINE_P (decl)
5212 || DECL_ARTIFICIAL (decl)
5213 || MAIN_NAME_P (DECL_NAME (decl)))
5214 {
5215 /* - Explicitly inlined functions cannot be hotpatched.
5216 - Artificial functions need not be hotpatched.
5217 - Making the main function hotpatchable is useless. */
5218 return -1;
5219 }
5220 attr = lookup_attribute ("hotpatch", DECL_ATTRIBUTES (decl));
5221 if (attr || s390_hotpatch_trampoline_halfwords >= 0)
5222 {
5223 if (lookup_attribute ("always_inline", DECL_ATTRIBUTES (decl)))
5224 {
5225 if (do_warn)
5226 warning (OPT_Wattributes, "function %qE with the %qs attribute"
5227 " is not hotpatchable", DECL_NAME (decl), "always_inline");
5228 return -1;
5229 }
5230 else
5231 {
5232 return (attr) ?
5233 get_hotpatch_attribute (attr) : s390_hotpatch_trampoline_halfwords;
5234 }
5235 }
5236
5237 return -1;
5238 }
5239
5240 /* Hook to determine if one function can safely inline another. */
5241
5242 static bool
5243 s390_can_inline_p (tree caller, tree callee)
5244 {
5245 if (s390_function_num_hotpatch_trampoline_halfwords (callee, false) >= 0)
5246 return false;
5247
5248 return default_target_can_inline_p (caller, callee);
5249 }
5250
5251 /* Write the extra assembler code needed to declare a function properly. */
5252
5253 void
5254 s390_asm_output_function_label (FILE *asm_out_file, const char *fname,
5255 tree decl)
5256 {
5257 int hotpatch_trampoline_halfwords = -1;
5258
5259 if (decl)
5260 {
5261 hotpatch_trampoline_halfwords =
5262 s390_function_num_hotpatch_trampoline_halfwords (decl, true);
5263 if (hotpatch_trampoline_halfwords >= 0
5264 && decl_function_context (decl) != NULL_TREE)
5265 {
5266 warning_at (DECL_SOURCE_LOCATION (decl), OPT_mhotpatch,
5267 "hotpatching is not compatible with nested functions");
5268 hotpatch_trampoline_halfwords = -1;
5269 }
5270 }
5271
5272 if (hotpatch_trampoline_halfwords > 0)
5273 {
5274 int i;
5275
5276 /* Add a trampoline code area before the function label and initialize it
5277 with two-byte nop instructions. This area can be overwritten with code
5278 that jumps to a patched version of the function. */
5279 for (i = 0; i < hotpatch_trampoline_halfwords; i++)
5280 asm_fprintf (asm_out_file, "\tnopr\t%%r7\n");
5281 /* Note: The function label must be aligned so that (a) the bytes of the
5282 following nop do not cross a cacheline boundary, and (b) a jump address
5283 (eight bytes for 64 bit targets, 4 bytes for 32 bit targets) can be
5284 stored directly before the label without crossing a cacheline
5285 boundary. All this is necessary to make sure the trampoline code can
5286 be changed atomically. */
5287 }
5288
5289 ASM_OUTPUT_LABEL (asm_out_file, fname);
5290
5291 /* Output a four-byte nop if hotpatching is enabled. This can be overwritten
5292 atomically with a relative backwards jump to the trampoline area. */
5293 if (hotpatch_trampoline_halfwords >= 0)
5294 asm_fprintf (asm_out_file, "\tnop\t0\n");
5295 }
5296
5297 /* Output machine-dependent UNSPECs occurring in address constant X
5298 in assembler syntax to stdio stream FILE. Returns true if the
5299 constant X could be recognized, false otherwise. */
5300
5301 static bool
5302 s390_output_addr_const_extra (FILE *file, rtx x)
5303 {
5304 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
5305 switch (XINT (x, 1))
5306 {
5307 case UNSPEC_GOTENT:
5308 output_addr_const (file, XVECEXP (x, 0, 0));
5309 fprintf (file, "@GOTENT");
5310 return true;
5311 case UNSPEC_GOT:
5312 output_addr_const (file, XVECEXP (x, 0, 0));
5313 fprintf (file, "@GOT");
5314 return true;
5315 case UNSPEC_GOTOFF:
5316 output_addr_const (file, XVECEXP (x, 0, 0));
5317 fprintf (file, "@GOTOFF");
5318 return true;
5319 case UNSPEC_PLT:
5320 output_addr_const (file, XVECEXP (x, 0, 0));
5321 fprintf (file, "@PLT");
5322 return true;
5323 case UNSPEC_PLTOFF:
5324 output_addr_const (file, XVECEXP (x, 0, 0));
5325 fprintf (file, "@PLTOFF");
5326 return true;
5327 case UNSPEC_TLSGD:
5328 output_addr_const (file, XVECEXP (x, 0, 0));
5329 fprintf (file, "@TLSGD");
5330 return true;
5331 case UNSPEC_TLSLDM:
5332 assemble_name (file, get_some_local_dynamic_name ());
5333 fprintf (file, "@TLSLDM");
5334 return true;
5335 case UNSPEC_DTPOFF:
5336 output_addr_const (file, XVECEXP (x, 0, 0));
5337 fprintf (file, "@DTPOFF");
5338 return true;
5339 case UNSPEC_NTPOFF:
5340 output_addr_const (file, XVECEXP (x, 0, 0));
5341 fprintf (file, "@NTPOFF");
5342 return true;
5343 case UNSPEC_GOTNTPOFF:
5344 output_addr_const (file, XVECEXP (x, 0, 0));
5345 fprintf (file, "@GOTNTPOFF");
5346 return true;
5347 case UNSPEC_INDNTPOFF:
5348 output_addr_const (file, XVECEXP (x, 0, 0));
5349 fprintf (file, "@INDNTPOFF");
5350 return true;
5351 }
5352
5353 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 2)
5354 switch (XINT (x, 1))
5355 {
5356 case UNSPEC_POOL_OFFSET:
5357 x = gen_rtx_MINUS (GET_MODE (x), XVECEXP (x, 0, 0), XVECEXP (x, 0, 1));
5358 output_addr_const (file, x);
5359 return true;
5360 }
5361 return false;
5362 }
5363
5364 /* Output address operand ADDR in assembler syntax to
5365 stdio stream FILE. */
5366
5367 void
5368 print_operand_address (FILE *file, rtx addr)
5369 {
5370 struct s390_address ad;
5371
5372 if (s390_loadrelative_operand_p (addr, NULL, NULL))
5373 {
5374 if (!TARGET_Z10)
5375 {
5376 output_operand_lossage ("symbolic memory references are "
5377 "only supported on z10 or later");
5378 return;
5379 }
5380 output_addr_const (file, addr);
5381 return;
5382 }
5383
5384 if (!s390_decompose_address (addr, &ad)
5385 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5386 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
5387 output_operand_lossage ("cannot decompose address");
5388
5389 if (ad.disp)
5390 output_addr_const (file, ad.disp);
5391 else
5392 fprintf (file, "0");
5393
5394 if (ad.base && ad.indx)
5395 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
5396 reg_names[REGNO (ad.base)]);
5397 else if (ad.base)
5398 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5399 }
5400
5401 /* Output operand X in assembler syntax to stdio stream FILE.
5402 CODE specified the format flag. The following format flags
5403 are recognized:
5404
5405 'C': print opcode suffix for branch condition.
5406 'D': print opcode suffix for inverse branch condition.
5407 'E': print opcode suffix for branch on index instruction.
5408 'G': print the size of the operand in bytes.
5409 'J': print tls_load/tls_gdcall/tls_ldcall suffix
5410 'M': print the second word of a TImode operand.
5411 'N': print the second word of a DImode operand.
5412 'O': print only the displacement of a memory reference.
5413 'R': print only the base register of a memory reference.
5414 'S': print S-type memory reference (base+displacement).
5415 'Y': print shift count operand.
5416
5417 'b': print integer X as if it's an unsigned byte.
5418 'c': print integer X as if it's an signed byte.
5419 'e': "end" of DImode contiguous bitmask X.
5420 'f': "end" of SImode contiguous bitmask X.
5421 'h': print integer X as if it's a signed halfword.
5422 'i': print the first nonzero HImode part of X.
5423 'j': print the first HImode part unequal to -1 of X.
5424 'k': print the first nonzero SImode part of X.
5425 'm': print the first SImode part unequal to -1 of X.
5426 'o': print integer X as if it's an unsigned 32bit word.
5427 's': "start" of DImode contiguous bitmask X.
5428 't': "start" of SImode contiguous bitmask X.
5429 'x': print integer X as if it's an unsigned halfword.
5430 */
5431
5432 void
5433 print_operand (FILE *file, rtx x, int code)
5434 {
5435 HOST_WIDE_INT ival;
5436
5437 switch (code)
5438 {
5439 case 'C':
5440 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
5441 return;
5442
5443 case 'D':
5444 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
5445 return;
5446
5447 case 'E':
5448 if (GET_CODE (x) == LE)
5449 fprintf (file, "l");
5450 else if (GET_CODE (x) == GT)
5451 fprintf (file, "h");
5452 else
5453 output_operand_lossage ("invalid comparison operator "
5454 "for 'E' output modifier");
5455 return;
5456
5457 case 'J':
5458 if (GET_CODE (x) == SYMBOL_REF)
5459 {
5460 fprintf (file, "%s", ":tls_load:");
5461 output_addr_const (file, x);
5462 }
5463 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
5464 {
5465 fprintf (file, "%s", ":tls_gdcall:");
5466 output_addr_const (file, XVECEXP (x, 0, 0));
5467 }
5468 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
5469 {
5470 fprintf (file, "%s", ":tls_ldcall:");
5471 const char *name = get_some_local_dynamic_name ();
5472 gcc_assert (name);
5473 assemble_name (file, name);
5474 }
5475 else
5476 output_operand_lossage ("invalid reference for 'J' output modifier");
5477 return;
5478
5479 case 'G':
5480 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
5481 return;
5482
5483 case 'O':
5484 {
5485 struct s390_address ad;
5486 int ret;
5487
5488 if (!MEM_P (x))
5489 {
5490 output_operand_lossage ("memory reference expected for "
5491 "'O' output modifier");
5492 return;
5493 }
5494
5495 ret = s390_decompose_address (XEXP (x, 0), &ad);
5496
5497 if (!ret
5498 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5499 || ad.indx)
5500 {
5501 output_operand_lossage ("invalid address for 'O' output modifier");
5502 return;
5503 }
5504
5505 if (ad.disp)
5506 output_addr_const (file, ad.disp);
5507 else
5508 fprintf (file, "0");
5509 }
5510 return;
5511
5512 case 'R':
5513 {
5514 struct s390_address ad;
5515 int ret;
5516
5517 if (!MEM_P (x))
5518 {
5519 output_operand_lossage ("memory reference expected for "
5520 "'R' output modifier");
5521 return;
5522 }
5523
5524 ret = s390_decompose_address (XEXP (x, 0), &ad);
5525
5526 if (!ret
5527 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5528 || ad.indx)
5529 {
5530 output_operand_lossage ("invalid address for 'R' output modifier");
5531 return;
5532 }
5533
5534 if (ad.base)
5535 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
5536 else
5537 fprintf (file, "0");
5538 }
5539 return;
5540
5541 case 'S':
5542 {
5543 struct s390_address ad;
5544 int ret;
5545
5546 if (!MEM_P (x))
5547 {
5548 output_operand_lossage ("memory reference expected for "
5549 "'S' output modifier");
5550 return;
5551 }
5552 ret = s390_decompose_address (XEXP (x, 0), &ad);
5553
5554 if (!ret
5555 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5556 || ad.indx)
5557 {
5558 output_operand_lossage ("invalid address for 'S' output modifier");
5559 return;
5560 }
5561
5562 if (ad.disp)
5563 output_addr_const (file, ad.disp);
5564 else
5565 fprintf (file, "0");
5566
5567 if (ad.base)
5568 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5569 }
5570 return;
5571
5572 case 'N':
5573 if (GET_CODE (x) == REG)
5574 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5575 else if (GET_CODE (x) == MEM)
5576 x = change_address (x, VOIDmode,
5577 plus_constant (Pmode, XEXP (x, 0), 4));
5578 else
5579 output_operand_lossage ("register or memory expression expected "
5580 "for 'N' output modifier");
5581 break;
5582
5583 case 'M':
5584 if (GET_CODE (x) == REG)
5585 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5586 else if (GET_CODE (x) == MEM)
5587 x = change_address (x, VOIDmode,
5588 plus_constant (Pmode, XEXP (x, 0), 8));
5589 else
5590 output_operand_lossage ("register or memory expression expected "
5591 "for 'M' output modifier");
5592 break;
5593
5594 case 'Y':
5595 print_shift_count_operand (file, x);
5596 return;
5597 }
5598
5599 switch (GET_CODE (x))
5600 {
5601 case REG:
5602 fprintf (file, "%s", reg_names[REGNO (x)]);
5603 break;
5604
5605 case MEM:
5606 output_address (XEXP (x, 0));
5607 break;
5608
5609 case CONST:
5610 case CODE_LABEL:
5611 case LABEL_REF:
5612 case SYMBOL_REF:
5613 output_addr_const (file, x);
5614 break;
5615
5616 case CONST_INT:
5617 ival = INTVAL (x);
5618 switch (code)
5619 {
5620 case 0:
5621 break;
5622 case 'b':
5623 ival &= 0xff;
5624 break;
5625 case 'c':
5626 ival = ((ival & 0xff) ^ 0x80) - 0x80;
5627 break;
5628 case 'x':
5629 ival &= 0xffff;
5630 break;
5631 case 'h':
5632 ival = ((ival & 0xffff) ^ 0x8000) - 0x8000;
5633 break;
5634 case 'i':
5635 ival = s390_extract_part (x, HImode, 0);
5636 break;
5637 case 'j':
5638 ival = s390_extract_part (x, HImode, -1);
5639 break;
5640 case 'k':
5641 ival = s390_extract_part (x, SImode, 0);
5642 break;
5643 case 'm':
5644 ival = s390_extract_part (x, SImode, -1);
5645 break;
5646 case 'o':
5647 ival &= 0xffffffff;
5648 break;
5649 case 'e': case 'f':
5650 case 's': case 't':
5651 {
5652 int pos, len;
5653 bool ok;
5654
5655 len = (code == 's' || code == 'e' ? 64 : 32);
5656 ok = s390_contiguous_bitmask_p (ival, len, &pos, &len);
5657 gcc_assert (ok);
5658 if (code == 's' || code == 't')
5659 ival = 64 - pos - len;
5660 else
5661 ival = 64 - 1 - pos;
5662 }
5663 break;
5664 default:
5665 output_operand_lossage ("invalid constant for output modifier '%c'", code);
5666 }
5667 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
5668 break;
5669
5670 case CONST_DOUBLE:
5671 gcc_assert (GET_MODE (x) == VOIDmode);
5672 if (code == 'b')
5673 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
5674 else if (code == 'x')
5675 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
5676 else if (code == 'h')
5677 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5678 ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
5679 else
5680 {
5681 if (code == 0)
5682 output_operand_lossage ("invalid constant - try using "
5683 "an output modifier");
5684 else
5685 output_operand_lossage ("invalid constant for output modifier '%c'",
5686 code);
5687 }
5688 break;
5689
5690 default:
5691 if (code == 0)
5692 output_operand_lossage ("invalid expression - try using "
5693 "an output modifier");
5694 else
5695 output_operand_lossage ("invalid expression for output "
5696 "modifier '%c'", code);
5697 break;
5698 }
5699 }
5700
5701 /* Target hook for assembling integer objects. We need to define it
5702 here to work a round a bug in some versions of GAS, which couldn't
5703 handle values smaller than INT_MIN when printed in decimal. */
5704
5705 static bool
5706 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
5707 {
5708 if (size == 8 && aligned_p
5709 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
5710 {
5711 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
5712 INTVAL (x));
5713 return true;
5714 }
5715 return default_assemble_integer (x, size, aligned_p);
5716 }
5717
5718 /* Returns true if register REGNO is used for forming
5719 a memory address in expression X. */
5720
5721 static bool
5722 reg_used_in_mem_p (int regno, rtx x)
5723 {
5724 enum rtx_code code = GET_CODE (x);
5725 int i, j;
5726 const char *fmt;
5727
5728 if (code == MEM)
5729 {
5730 if (refers_to_regno_p (regno, regno+1,
5731 XEXP (x, 0), 0))
5732 return true;
5733 }
5734 else if (code == SET
5735 && GET_CODE (SET_DEST (x)) == PC)
5736 {
5737 if (refers_to_regno_p (regno, regno+1,
5738 SET_SRC (x), 0))
5739 return true;
5740 }
5741
5742 fmt = GET_RTX_FORMAT (code);
5743 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5744 {
5745 if (fmt[i] == 'e'
5746 && reg_used_in_mem_p (regno, XEXP (x, i)))
5747 return true;
5748
5749 else if (fmt[i] == 'E')
5750 for (j = 0; j < XVECLEN (x, i); j++)
5751 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
5752 return true;
5753 }
5754 return false;
5755 }
5756
5757 /* Returns true if expression DEP_RTX sets an address register
5758 used by instruction INSN to address memory. */
5759
5760 static bool
5761 addr_generation_dependency_p (rtx dep_rtx, rtx_insn *insn)
5762 {
5763 rtx target, pat;
5764
5765 if (NONJUMP_INSN_P (dep_rtx))
5766 dep_rtx = PATTERN (dep_rtx);
5767
5768 if (GET_CODE (dep_rtx) == SET)
5769 {
5770 target = SET_DEST (dep_rtx);
5771 if (GET_CODE (target) == STRICT_LOW_PART)
5772 target = XEXP (target, 0);
5773 while (GET_CODE (target) == SUBREG)
5774 target = SUBREG_REG (target);
5775
5776 if (GET_CODE (target) == REG)
5777 {
5778 int regno = REGNO (target);
5779
5780 if (s390_safe_attr_type (insn) == TYPE_LA)
5781 {
5782 pat = PATTERN (insn);
5783 if (GET_CODE (pat) == PARALLEL)
5784 {
5785 gcc_assert (XVECLEN (pat, 0) == 2);
5786 pat = XVECEXP (pat, 0, 0);
5787 }
5788 gcc_assert (GET_CODE (pat) == SET);
5789 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
5790 }
5791 else if (get_attr_atype (insn) == ATYPE_AGEN)
5792 return reg_used_in_mem_p (regno, PATTERN (insn));
5793 }
5794 }
5795 return false;
5796 }
5797
5798 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5799
5800 int
5801 s390_agen_dep_p (rtx_insn *dep_insn, rtx_insn *insn)
5802 {
5803 rtx dep_rtx = PATTERN (dep_insn);
5804 int i;
5805
5806 if (GET_CODE (dep_rtx) == SET
5807 && addr_generation_dependency_p (dep_rtx, insn))
5808 return 1;
5809 else if (GET_CODE (dep_rtx) == PARALLEL)
5810 {
5811 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
5812 {
5813 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
5814 return 1;
5815 }
5816 }
5817 return 0;
5818 }
5819
5820
5821 /* A C statement (sans semicolon) to update the integer scheduling priority
5822 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5823 reduce the priority to execute INSN later. Do not define this macro if
5824 you do not need to adjust the scheduling priorities of insns.
5825
5826 A STD instruction should be scheduled earlier,
5827 in order to use the bypass. */
5828 static int
5829 s390_adjust_priority (rtx_insn *insn, int priority)
5830 {
5831 if (! INSN_P (insn))
5832 return priority;
5833
5834 if (s390_tune != PROCESSOR_2084_Z990
5835 && s390_tune != PROCESSOR_2094_Z9_109
5836 && s390_tune != PROCESSOR_2097_Z10
5837 && s390_tune != PROCESSOR_2817_Z196
5838 && s390_tune != PROCESSOR_2827_ZEC12)
5839 return priority;
5840
5841 switch (s390_safe_attr_type (insn))
5842 {
5843 case TYPE_FSTOREDF:
5844 case TYPE_FSTORESF:
5845 priority = priority << 3;
5846 break;
5847 case TYPE_STORE:
5848 case TYPE_STM:
5849 priority = priority << 1;
5850 break;
5851 default:
5852 break;
5853 }
5854 return priority;
5855 }
5856
5857
5858 /* The number of instructions that can be issued per cycle. */
5859
5860 static int
5861 s390_issue_rate (void)
5862 {
5863 switch (s390_tune)
5864 {
5865 case PROCESSOR_2084_Z990:
5866 case PROCESSOR_2094_Z9_109:
5867 case PROCESSOR_2817_Z196:
5868 return 3;
5869 case PROCESSOR_2097_Z10:
5870 case PROCESSOR_2827_ZEC12:
5871 return 2;
5872 default:
5873 return 1;
5874 }
5875 }
5876
5877 static int
5878 s390_first_cycle_multipass_dfa_lookahead (void)
5879 {
5880 return 4;
5881 }
5882
5883 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5884 Fix up MEMs as required. */
5885
5886 static void
5887 annotate_constant_pool_refs (rtx *x)
5888 {
5889 int i, j;
5890 const char *fmt;
5891
5892 gcc_assert (GET_CODE (*x) != SYMBOL_REF
5893 || !CONSTANT_POOL_ADDRESS_P (*x));
5894
5895 /* Literal pool references can only occur inside a MEM ... */
5896 if (GET_CODE (*x) == MEM)
5897 {
5898 rtx memref = XEXP (*x, 0);
5899
5900 if (GET_CODE (memref) == SYMBOL_REF
5901 && CONSTANT_POOL_ADDRESS_P (memref))
5902 {
5903 rtx base = cfun->machine->base_reg;
5904 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
5905 UNSPEC_LTREF);
5906
5907 *x = replace_equiv_address (*x, addr);
5908 return;
5909 }
5910
5911 if (GET_CODE (memref) == CONST
5912 && GET_CODE (XEXP (memref, 0)) == PLUS
5913 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
5914 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
5915 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
5916 {
5917 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
5918 rtx sym = XEXP (XEXP (memref, 0), 0);
5919 rtx base = cfun->machine->base_reg;
5920 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5921 UNSPEC_LTREF);
5922
5923 *x = replace_equiv_address (*x, plus_constant (Pmode, addr, off));
5924 return;
5925 }
5926 }
5927
5928 /* ... or a load-address type pattern. */
5929 if (GET_CODE (*x) == SET)
5930 {
5931 rtx addrref = SET_SRC (*x);
5932
5933 if (GET_CODE (addrref) == SYMBOL_REF
5934 && CONSTANT_POOL_ADDRESS_P (addrref))
5935 {
5936 rtx base = cfun->machine->base_reg;
5937 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
5938 UNSPEC_LTREF);
5939
5940 SET_SRC (*x) = addr;
5941 return;
5942 }
5943
5944 if (GET_CODE (addrref) == CONST
5945 && GET_CODE (XEXP (addrref, 0)) == PLUS
5946 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
5947 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
5948 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
5949 {
5950 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
5951 rtx sym = XEXP (XEXP (addrref, 0), 0);
5952 rtx base = cfun->machine->base_reg;
5953 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5954 UNSPEC_LTREF);
5955
5956 SET_SRC (*x) = plus_constant (Pmode, addr, off);
5957 return;
5958 }
5959 }
5960
5961 /* Annotate LTREL_BASE as well. */
5962 if (GET_CODE (*x) == UNSPEC
5963 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5964 {
5965 rtx base = cfun->machine->base_reg;
5966 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
5967 UNSPEC_LTREL_BASE);
5968 return;
5969 }
5970
5971 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5972 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5973 {
5974 if (fmt[i] == 'e')
5975 {
5976 annotate_constant_pool_refs (&XEXP (*x, i));
5977 }
5978 else if (fmt[i] == 'E')
5979 {
5980 for (j = 0; j < XVECLEN (*x, i); j++)
5981 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
5982 }
5983 }
5984 }
5985
5986 /* Split all branches that exceed the maximum distance.
5987 Returns true if this created a new literal pool entry. */
5988
5989 static int
5990 s390_split_branches (void)
5991 {
5992 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
5993 int new_literal = 0, ret;
5994 rtx_insn *insn;
5995 rtx pat, target;
5996 rtx *label;
5997
5998 /* We need correct insn addresses. */
5999
6000 shorten_branches (get_insns ());
6001
6002 /* Find all branches that exceed 64KB, and split them. */
6003
6004 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6005 {
6006 if (! JUMP_P (insn) || tablejump_p (insn, NULL, NULL))
6007 continue;
6008
6009 pat = PATTERN (insn);
6010 if (GET_CODE (pat) == PARALLEL)
6011 pat = XVECEXP (pat, 0, 0);
6012 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
6013 continue;
6014
6015 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
6016 {
6017 label = &SET_SRC (pat);
6018 }
6019 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
6020 {
6021 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
6022 label = &XEXP (SET_SRC (pat), 1);
6023 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
6024 label = &XEXP (SET_SRC (pat), 2);
6025 else
6026 continue;
6027 }
6028 else
6029 continue;
6030
6031 if (get_attr_length (insn) <= 4)
6032 continue;
6033
6034 /* We are going to use the return register as scratch register,
6035 make sure it will be saved/restored by the prologue/epilogue. */
6036 cfun_frame_layout.save_return_addr_p = 1;
6037
6038 if (!flag_pic)
6039 {
6040 new_literal = 1;
6041 rtx mem = force_const_mem (Pmode, *label);
6042 rtx_insn *set_insn = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, mem), insn);
6043 INSN_ADDRESSES_NEW (set_insn, -1);
6044 annotate_constant_pool_refs (&PATTERN (set_insn));
6045
6046 target = temp_reg;
6047 }
6048 else
6049 {
6050 new_literal = 1;
6051 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
6052 UNSPEC_LTREL_OFFSET);
6053 target = gen_rtx_CONST (Pmode, target);
6054 target = force_const_mem (Pmode, target);
6055 rtx_insn *set_insn = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
6056 INSN_ADDRESSES_NEW (set_insn, -1);
6057 annotate_constant_pool_refs (&PATTERN (set_insn));
6058
6059 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
6060 cfun->machine->base_reg),
6061 UNSPEC_LTREL_BASE);
6062 target = gen_rtx_PLUS (Pmode, temp_reg, target);
6063 }
6064
6065 ret = validate_change (insn, label, target, 0);
6066 gcc_assert (ret);
6067 }
6068
6069 return new_literal;
6070 }
6071
6072
6073 /* Find an annotated literal pool symbol referenced in RTX X,
6074 and store it at REF. Will abort if X contains references to
6075 more than one such pool symbol; multiple references to the same
6076 symbol are allowed, however.
6077
6078 The rtx pointed to by REF must be initialized to NULL_RTX
6079 by the caller before calling this routine. */
6080
6081 static void
6082 find_constant_pool_ref (rtx x, rtx *ref)
6083 {
6084 int i, j;
6085 const char *fmt;
6086
6087 /* Ignore LTREL_BASE references. */
6088 if (GET_CODE (x) == UNSPEC
6089 && XINT (x, 1) == UNSPEC_LTREL_BASE)
6090 return;
6091 /* Likewise POOL_ENTRY insns. */
6092 if (GET_CODE (x) == UNSPEC_VOLATILE
6093 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
6094 return;
6095
6096 gcc_assert (GET_CODE (x) != SYMBOL_REF
6097 || !CONSTANT_POOL_ADDRESS_P (x));
6098
6099 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
6100 {
6101 rtx sym = XVECEXP (x, 0, 0);
6102 gcc_assert (GET_CODE (sym) == SYMBOL_REF
6103 && CONSTANT_POOL_ADDRESS_P (sym));
6104
6105 if (*ref == NULL_RTX)
6106 *ref = sym;
6107 else
6108 gcc_assert (*ref == sym);
6109
6110 return;
6111 }
6112
6113 fmt = GET_RTX_FORMAT (GET_CODE (x));
6114 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6115 {
6116 if (fmt[i] == 'e')
6117 {
6118 find_constant_pool_ref (XEXP (x, i), ref);
6119 }
6120 else if (fmt[i] == 'E')
6121 {
6122 for (j = 0; j < XVECLEN (x, i); j++)
6123 find_constant_pool_ref (XVECEXP (x, i, j), ref);
6124 }
6125 }
6126 }
6127
6128 /* Replace every reference to the annotated literal pool
6129 symbol REF in X by its base plus OFFSET. */
6130
6131 static void
6132 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
6133 {
6134 int i, j;
6135 const char *fmt;
6136
6137 gcc_assert (*x != ref);
6138
6139 if (GET_CODE (*x) == UNSPEC
6140 && XINT (*x, 1) == UNSPEC_LTREF
6141 && XVECEXP (*x, 0, 0) == ref)
6142 {
6143 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
6144 return;
6145 }
6146
6147 if (GET_CODE (*x) == PLUS
6148 && GET_CODE (XEXP (*x, 1)) == CONST_INT
6149 && GET_CODE (XEXP (*x, 0)) == UNSPEC
6150 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
6151 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
6152 {
6153 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
6154 *x = plus_constant (Pmode, addr, INTVAL (XEXP (*x, 1)));
6155 return;
6156 }
6157
6158 fmt = GET_RTX_FORMAT (GET_CODE (*x));
6159 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
6160 {
6161 if (fmt[i] == 'e')
6162 {
6163 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
6164 }
6165 else if (fmt[i] == 'E')
6166 {
6167 for (j = 0; j < XVECLEN (*x, i); j++)
6168 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
6169 }
6170 }
6171 }
6172
6173 /* Check whether X contains an UNSPEC_LTREL_BASE.
6174 Return its constant pool symbol if found, NULL_RTX otherwise. */
6175
6176 static rtx
6177 find_ltrel_base (rtx x)
6178 {
6179 int i, j;
6180 const char *fmt;
6181
6182 if (GET_CODE (x) == UNSPEC
6183 && XINT (x, 1) == UNSPEC_LTREL_BASE)
6184 return XVECEXP (x, 0, 0);
6185
6186 fmt = GET_RTX_FORMAT (GET_CODE (x));
6187 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6188 {
6189 if (fmt[i] == 'e')
6190 {
6191 rtx fnd = find_ltrel_base (XEXP (x, i));
6192 if (fnd)
6193 return fnd;
6194 }
6195 else if (fmt[i] == 'E')
6196 {
6197 for (j = 0; j < XVECLEN (x, i); j++)
6198 {
6199 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
6200 if (fnd)
6201 return fnd;
6202 }
6203 }
6204 }
6205
6206 return NULL_RTX;
6207 }
6208
6209 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
6210
6211 static void
6212 replace_ltrel_base (rtx *x)
6213 {
6214 int i, j;
6215 const char *fmt;
6216
6217 if (GET_CODE (*x) == UNSPEC
6218 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
6219 {
6220 *x = XVECEXP (*x, 0, 1);
6221 return;
6222 }
6223
6224 fmt = GET_RTX_FORMAT (GET_CODE (*x));
6225 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
6226 {
6227 if (fmt[i] == 'e')
6228 {
6229 replace_ltrel_base (&XEXP (*x, i));
6230 }
6231 else if (fmt[i] == 'E')
6232 {
6233 for (j = 0; j < XVECLEN (*x, i); j++)
6234 replace_ltrel_base (&XVECEXP (*x, i, j));
6235 }
6236 }
6237 }
6238
6239
6240 /* We keep a list of constants which we have to add to internal
6241 constant tables in the middle of large functions. */
6242
6243 #define NR_C_MODES 11
6244 enum machine_mode constant_modes[NR_C_MODES] =
6245 {
6246 TFmode, TImode, TDmode,
6247 DFmode, DImode, DDmode,
6248 SFmode, SImode, SDmode,
6249 HImode,
6250 QImode
6251 };
6252
6253 struct constant
6254 {
6255 struct constant *next;
6256 rtx value;
6257 rtx_code_label *label;
6258 };
6259
6260 struct constant_pool
6261 {
6262 struct constant_pool *next;
6263 rtx_insn *first_insn;
6264 rtx_insn *pool_insn;
6265 bitmap insns;
6266 rtx_insn *emit_pool_after;
6267
6268 struct constant *constants[NR_C_MODES];
6269 struct constant *execute;
6270 rtx_code_label *label;
6271 int size;
6272 };
6273
6274 /* Allocate new constant_pool structure. */
6275
6276 static struct constant_pool *
6277 s390_alloc_pool (void)
6278 {
6279 struct constant_pool *pool;
6280 int i;
6281
6282 pool = (struct constant_pool *) xmalloc (sizeof *pool);
6283 pool->next = NULL;
6284 for (i = 0; i < NR_C_MODES; i++)
6285 pool->constants[i] = NULL;
6286
6287 pool->execute = NULL;
6288 pool->label = gen_label_rtx ();
6289 pool->first_insn = NULL;
6290 pool->pool_insn = NULL;
6291 pool->insns = BITMAP_ALLOC (NULL);
6292 pool->size = 0;
6293 pool->emit_pool_after = NULL;
6294
6295 return pool;
6296 }
6297
6298 /* Create new constant pool covering instructions starting at INSN
6299 and chain it to the end of POOL_LIST. */
6300
6301 static struct constant_pool *
6302 s390_start_pool (struct constant_pool **pool_list, rtx_insn *insn)
6303 {
6304 struct constant_pool *pool, **prev;
6305
6306 pool = s390_alloc_pool ();
6307 pool->first_insn = insn;
6308
6309 for (prev = pool_list; *prev; prev = &(*prev)->next)
6310 ;
6311 *prev = pool;
6312
6313 return pool;
6314 }
6315
6316 /* End range of instructions covered by POOL at INSN and emit
6317 placeholder insn representing the pool. */
6318
6319 static void
6320 s390_end_pool (struct constant_pool *pool, rtx_insn *insn)
6321 {
6322 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
6323
6324 if (!insn)
6325 insn = get_last_insn ();
6326
6327 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
6328 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6329 }
6330
6331 /* Add INSN to the list of insns covered by POOL. */
6332
6333 static void
6334 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
6335 {
6336 bitmap_set_bit (pool->insns, INSN_UID (insn));
6337 }
6338
6339 /* Return pool out of POOL_LIST that covers INSN. */
6340
6341 static struct constant_pool *
6342 s390_find_pool (struct constant_pool *pool_list, rtx insn)
6343 {
6344 struct constant_pool *pool;
6345
6346 for (pool = pool_list; pool; pool = pool->next)
6347 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
6348 break;
6349
6350 return pool;
6351 }
6352
6353 /* Add constant VAL of mode MODE to the constant pool POOL. */
6354
6355 static void
6356 s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
6357 {
6358 struct constant *c;
6359 int i;
6360
6361 for (i = 0; i < NR_C_MODES; i++)
6362 if (constant_modes[i] == mode)
6363 break;
6364 gcc_assert (i != NR_C_MODES);
6365
6366 for (c = pool->constants[i]; c != NULL; c = c->next)
6367 if (rtx_equal_p (val, c->value))
6368 break;
6369
6370 if (c == NULL)
6371 {
6372 c = (struct constant *) xmalloc (sizeof *c);
6373 c->value = val;
6374 c->label = gen_label_rtx ();
6375 c->next = pool->constants[i];
6376 pool->constants[i] = c;
6377 pool->size += GET_MODE_SIZE (mode);
6378 }
6379 }
6380
6381 /* Return an rtx that represents the offset of X from the start of
6382 pool POOL. */
6383
6384 static rtx
6385 s390_pool_offset (struct constant_pool *pool, rtx x)
6386 {
6387 rtx label;
6388
6389 label = gen_rtx_LABEL_REF (GET_MODE (x), pool->label);
6390 x = gen_rtx_UNSPEC (GET_MODE (x), gen_rtvec (2, x, label),
6391 UNSPEC_POOL_OFFSET);
6392 return gen_rtx_CONST (GET_MODE (x), x);
6393 }
6394
6395 /* Find constant VAL of mode MODE in the constant pool POOL.
6396 Return an RTX describing the distance from the start of
6397 the pool to the location of the new constant. */
6398
6399 static rtx
6400 s390_find_constant (struct constant_pool *pool, rtx val,
6401 enum machine_mode mode)
6402 {
6403 struct constant *c;
6404 int i;
6405
6406 for (i = 0; i < NR_C_MODES; i++)
6407 if (constant_modes[i] == mode)
6408 break;
6409 gcc_assert (i != NR_C_MODES);
6410
6411 for (c = pool->constants[i]; c != NULL; c = c->next)
6412 if (rtx_equal_p (val, c->value))
6413 break;
6414
6415 gcc_assert (c);
6416
6417 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6418 }
6419
6420 /* Check whether INSN is an execute. Return the label_ref to its
6421 execute target template if so, NULL_RTX otherwise. */
6422
6423 static rtx
6424 s390_execute_label (rtx insn)
6425 {
6426 if (NONJUMP_INSN_P (insn)
6427 && GET_CODE (PATTERN (insn)) == PARALLEL
6428 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
6429 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
6430 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
6431
6432 return NULL_RTX;
6433 }
6434
6435 /* Add execute target for INSN to the constant pool POOL. */
6436
6437 static void
6438 s390_add_execute (struct constant_pool *pool, rtx insn)
6439 {
6440 struct constant *c;
6441
6442 for (c = pool->execute; c != NULL; c = c->next)
6443 if (INSN_UID (insn) == INSN_UID (c->value))
6444 break;
6445
6446 if (c == NULL)
6447 {
6448 c = (struct constant *) xmalloc (sizeof *c);
6449 c->value = insn;
6450 c->label = gen_label_rtx ();
6451 c->next = pool->execute;
6452 pool->execute = c;
6453 pool->size += 6;
6454 }
6455 }
6456
6457 /* Find execute target for INSN in the constant pool POOL.
6458 Return an RTX describing the distance from the start of
6459 the pool to the location of the execute target. */
6460
6461 static rtx
6462 s390_find_execute (struct constant_pool *pool, rtx insn)
6463 {
6464 struct constant *c;
6465
6466 for (c = pool->execute; c != NULL; c = c->next)
6467 if (INSN_UID (insn) == INSN_UID (c->value))
6468 break;
6469
6470 gcc_assert (c);
6471
6472 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6473 }
6474
6475 /* For an execute INSN, extract the execute target template. */
6476
6477 static rtx
6478 s390_execute_target (rtx insn)
6479 {
6480 rtx pattern = PATTERN (insn);
6481 gcc_assert (s390_execute_label (insn));
6482
6483 if (XVECLEN (pattern, 0) == 2)
6484 {
6485 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
6486 }
6487 else
6488 {
6489 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
6490 int i;
6491
6492 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
6493 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
6494
6495 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
6496 }
6497
6498 return pattern;
6499 }
6500
6501 /* Indicate that INSN cannot be duplicated. This is the case for
6502 execute insns that carry a unique label. */
6503
6504 static bool
6505 s390_cannot_copy_insn_p (rtx_insn *insn)
6506 {
6507 rtx label = s390_execute_label (insn);
6508 return label && label != const0_rtx;
6509 }
6510
6511 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
6512 do not emit the pool base label. */
6513
6514 static void
6515 s390_dump_pool (struct constant_pool *pool, bool remote_label)
6516 {
6517 struct constant *c;
6518 rtx_insn *insn = pool->pool_insn;
6519 int i;
6520
6521 /* Switch to rodata section. */
6522 if (TARGET_CPU_ZARCH)
6523 {
6524 insn = emit_insn_after (gen_pool_section_start (), insn);
6525 INSN_ADDRESSES_NEW (insn, -1);
6526 }
6527
6528 /* Ensure minimum pool alignment. */
6529 if (TARGET_CPU_ZARCH)
6530 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
6531 else
6532 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
6533 INSN_ADDRESSES_NEW (insn, -1);
6534
6535 /* Emit pool base label. */
6536 if (!remote_label)
6537 {
6538 insn = emit_label_after (pool->label, insn);
6539 INSN_ADDRESSES_NEW (insn, -1);
6540 }
6541
6542 /* Dump constants in descending alignment requirement order,
6543 ensuring proper alignment for every constant. */
6544 for (i = 0; i < NR_C_MODES; i++)
6545 for (c = pool->constants[i]; c; c = c->next)
6546 {
6547 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6548 rtx value = copy_rtx (c->value);
6549 if (GET_CODE (value) == CONST
6550 && GET_CODE (XEXP (value, 0)) == UNSPEC
6551 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
6552 && XVECLEN (XEXP (value, 0), 0) == 1)
6553 value = s390_pool_offset (pool, XVECEXP (XEXP (value, 0), 0, 0));
6554
6555 insn = emit_label_after (c->label, insn);
6556 INSN_ADDRESSES_NEW (insn, -1);
6557
6558 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
6559 gen_rtvec (1, value),
6560 UNSPECV_POOL_ENTRY);
6561 insn = emit_insn_after (value, insn);
6562 INSN_ADDRESSES_NEW (insn, -1);
6563 }
6564
6565 /* Ensure minimum alignment for instructions. */
6566 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
6567 INSN_ADDRESSES_NEW (insn, -1);
6568
6569 /* Output in-pool execute template insns. */
6570 for (c = pool->execute; c; c = c->next)
6571 {
6572 insn = emit_label_after (c->label, insn);
6573 INSN_ADDRESSES_NEW (insn, -1);
6574
6575 insn = emit_insn_after (s390_execute_target (c->value), insn);
6576 INSN_ADDRESSES_NEW (insn, -1);
6577 }
6578
6579 /* Switch back to previous section. */
6580 if (TARGET_CPU_ZARCH)
6581 {
6582 insn = emit_insn_after (gen_pool_section_end (), insn);
6583 INSN_ADDRESSES_NEW (insn, -1);
6584 }
6585
6586 insn = emit_barrier_after (insn);
6587 INSN_ADDRESSES_NEW (insn, -1);
6588
6589 /* Remove placeholder insn. */
6590 remove_insn (pool->pool_insn);
6591 }
6592
6593 /* Free all memory used by POOL. */
6594
6595 static void
6596 s390_free_pool (struct constant_pool *pool)
6597 {
6598 struct constant *c, *next;
6599 int i;
6600
6601 for (i = 0; i < NR_C_MODES; i++)
6602 for (c = pool->constants[i]; c; c = next)
6603 {
6604 next = c->next;
6605 free (c);
6606 }
6607
6608 for (c = pool->execute; c; c = next)
6609 {
6610 next = c->next;
6611 free (c);
6612 }
6613
6614 BITMAP_FREE (pool->insns);
6615 free (pool);
6616 }
6617
6618
6619 /* Collect main literal pool. Return NULL on overflow. */
6620
6621 static struct constant_pool *
6622 s390_mainpool_start (void)
6623 {
6624 struct constant_pool *pool;
6625 rtx_insn *insn;
6626
6627 pool = s390_alloc_pool ();
6628
6629 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6630 {
6631 if (NONJUMP_INSN_P (insn)
6632 && GET_CODE (PATTERN (insn)) == SET
6633 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
6634 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
6635 {
6636 /* There might be two main_pool instructions if base_reg
6637 is call-clobbered; one for shrink-wrapped code and one
6638 for the rest. We want to keep the first. */
6639 if (pool->pool_insn)
6640 {
6641 insn = PREV_INSN (insn);
6642 delete_insn (NEXT_INSN (insn));
6643 continue;
6644 }
6645 pool->pool_insn = insn;
6646 }
6647
6648 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6649 {
6650 s390_add_execute (pool, insn);
6651 }
6652 else if (NONJUMP_INSN_P (insn) || CALL_P (insn))
6653 {
6654 rtx pool_ref = NULL_RTX;
6655 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6656 if (pool_ref)
6657 {
6658 rtx constant = get_pool_constant (pool_ref);
6659 enum machine_mode mode = get_pool_mode (pool_ref);
6660 s390_add_constant (pool, constant, mode);
6661 }
6662 }
6663
6664 /* If hot/cold partitioning is enabled we have to make sure that
6665 the literal pool is emitted in the same section where the
6666 initialization of the literal pool base pointer takes place.
6667 emit_pool_after is only used in the non-overflow case on non
6668 Z cpus where we can emit the literal pool at the end of the
6669 function body within the text section. */
6670 if (NOTE_P (insn)
6671 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6672 && !pool->emit_pool_after)
6673 pool->emit_pool_after = PREV_INSN (insn);
6674 }
6675
6676 gcc_assert (pool->pool_insn || pool->size == 0);
6677
6678 if (pool->size >= 4096)
6679 {
6680 /* We're going to chunkify the pool, so remove the main
6681 pool placeholder insn. */
6682 remove_insn (pool->pool_insn);
6683
6684 s390_free_pool (pool);
6685 pool = NULL;
6686 }
6687
6688 /* If the functions ends with the section where the literal pool
6689 should be emitted set the marker to its end. */
6690 if (pool && !pool->emit_pool_after)
6691 pool->emit_pool_after = get_last_insn ();
6692
6693 return pool;
6694 }
6695
6696 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6697 Modify the current function to output the pool constants as well as
6698 the pool register setup instruction. */
6699
6700 static void
6701 s390_mainpool_finish (struct constant_pool *pool)
6702 {
6703 rtx base_reg = cfun->machine->base_reg;
6704
6705 /* If the pool is empty, we're done. */
6706 if (pool->size == 0)
6707 {
6708 /* We don't actually need a base register after all. */
6709 cfun->machine->base_reg = NULL_RTX;
6710
6711 if (pool->pool_insn)
6712 remove_insn (pool->pool_insn);
6713 s390_free_pool (pool);
6714 return;
6715 }
6716
6717 /* We need correct insn addresses. */
6718 shorten_branches (get_insns ());
6719
6720 /* On zSeries, we use a LARL to load the pool register. The pool is
6721 located in the .rodata section, so we emit it after the function. */
6722 if (TARGET_CPU_ZARCH)
6723 {
6724 rtx set = gen_main_base_64 (base_reg, pool->label);
6725 rtx_insn *insn = emit_insn_after (set, pool->pool_insn);
6726 INSN_ADDRESSES_NEW (insn, -1);
6727 remove_insn (pool->pool_insn);
6728
6729 insn = get_last_insn ();
6730 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6731 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6732
6733 s390_dump_pool (pool, 0);
6734 }
6735
6736 /* On S/390, if the total size of the function's code plus literal pool
6737 does not exceed 4096 bytes, we use BASR to set up a function base
6738 pointer, and emit the literal pool at the end of the function. */
6739 else if (INSN_ADDRESSES (INSN_UID (pool->emit_pool_after))
6740 + pool->size + 8 /* alignment slop */ < 4096)
6741 {
6742 rtx set = gen_main_base_31_small (base_reg, pool->label);
6743 rtx_insn *insn = emit_insn_after (set, pool->pool_insn);
6744 INSN_ADDRESSES_NEW (insn, -1);
6745 remove_insn (pool->pool_insn);
6746
6747 insn = emit_label_after (pool->label, insn);
6748 INSN_ADDRESSES_NEW (insn, -1);
6749
6750 /* emit_pool_after will be set by s390_mainpool_start to the
6751 last insn of the section where the literal pool should be
6752 emitted. */
6753 insn = pool->emit_pool_after;
6754
6755 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6756 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6757
6758 s390_dump_pool (pool, 1);
6759 }
6760
6761 /* Otherwise, we emit an inline literal pool and use BASR to branch
6762 over it, setting up the pool register at the same time. */
6763 else
6764 {
6765 rtx_code_label *pool_end = gen_label_rtx ();
6766
6767 rtx pat = gen_main_base_31_large (base_reg, pool->label, pool_end);
6768 rtx_insn *insn = emit_jump_insn_after (pat, pool->pool_insn);
6769 JUMP_LABEL (insn) = pool_end;
6770 INSN_ADDRESSES_NEW (insn, -1);
6771 remove_insn (pool->pool_insn);
6772
6773 insn = emit_label_after (pool->label, insn);
6774 INSN_ADDRESSES_NEW (insn, -1);
6775
6776 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6777 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6778
6779 insn = emit_label_after (pool_end, pool->pool_insn);
6780 INSN_ADDRESSES_NEW (insn, -1);
6781
6782 s390_dump_pool (pool, 1);
6783 }
6784
6785
6786 /* Replace all literal pool references. */
6787
6788 for (rtx_insn *insn = get_insns (); insn; insn = NEXT_INSN (insn))
6789 {
6790 if (INSN_P (insn))
6791 replace_ltrel_base (&PATTERN (insn));
6792
6793 if (NONJUMP_INSN_P (insn) || CALL_P (insn))
6794 {
6795 rtx addr, pool_ref = NULL_RTX;
6796 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6797 if (pool_ref)
6798 {
6799 if (s390_execute_label (insn))
6800 addr = s390_find_execute (pool, insn);
6801 else
6802 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
6803 get_pool_mode (pool_ref));
6804
6805 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6806 INSN_CODE (insn) = -1;
6807 }
6808 }
6809 }
6810
6811
6812 /* Free the pool. */
6813 s390_free_pool (pool);
6814 }
6815
6816 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6817 We have decided we cannot use this pool, so revert all changes
6818 to the current function that were done by s390_mainpool_start. */
6819 static void
6820 s390_mainpool_cancel (struct constant_pool *pool)
6821 {
6822 /* We didn't actually change the instruction stream, so simply
6823 free the pool memory. */
6824 s390_free_pool (pool);
6825 }
6826
6827
6828 /* Chunkify the literal pool. */
6829
6830 #define S390_POOL_CHUNK_MIN 0xc00
6831 #define S390_POOL_CHUNK_MAX 0xe00
6832
6833 static struct constant_pool *
6834 s390_chunkify_start (void)
6835 {
6836 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
6837 int extra_size = 0;
6838 bitmap far_labels;
6839 rtx pending_ltrel = NULL_RTX;
6840 rtx_insn *insn;
6841
6842 rtx (*gen_reload_base) (rtx, rtx) =
6843 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
6844
6845
6846 /* We need correct insn addresses. */
6847
6848 shorten_branches (get_insns ());
6849
6850 /* Scan all insns and move literals to pool chunks. */
6851
6852 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6853 {
6854 bool section_switch_p = false;
6855
6856 /* Check for pending LTREL_BASE. */
6857 if (INSN_P (insn))
6858 {
6859 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
6860 if (ltrel_base)
6861 {
6862 gcc_assert (ltrel_base == pending_ltrel);
6863 pending_ltrel = NULL_RTX;
6864 }
6865 }
6866
6867 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6868 {
6869 if (!curr_pool)
6870 curr_pool = s390_start_pool (&pool_list, insn);
6871
6872 s390_add_execute (curr_pool, insn);
6873 s390_add_pool_insn (curr_pool, insn);
6874 }
6875 else if (NONJUMP_INSN_P (insn) || CALL_P (insn))
6876 {
6877 rtx pool_ref = NULL_RTX;
6878 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6879 if (pool_ref)
6880 {
6881 rtx constant = get_pool_constant (pool_ref);
6882 enum machine_mode mode = get_pool_mode (pool_ref);
6883
6884 if (!curr_pool)
6885 curr_pool = s390_start_pool (&pool_list, insn);
6886
6887 s390_add_constant (curr_pool, constant, mode);
6888 s390_add_pool_insn (curr_pool, insn);
6889
6890 /* Don't split the pool chunk between a LTREL_OFFSET load
6891 and the corresponding LTREL_BASE. */
6892 if (GET_CODE (constant) == CONST
6893 && GET_CODE (XEXP (constant, 0)) == UNSPEC
6894 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
6895 {
6896 gcc_assert (!pending_ltrel);
6897 pending_ltrel = pool_ref;
6898 }
6899 }
6900 }
6901
6902 if (JUMP_P (insn) || JUMP_TABLE_DATA_P (insn) || LABEL_P (insn))
6903 {
6904 if (curr_pool)
6905 s390_add_pool_insn (curr_pool, insn);
6906 /* An LTREL_BASE must follow within the same basic block. */
6907 gcc_assert (!pending_ltrel);
6908 }
6909
6910 if (NOTE_P (insn))
6911 switch (NOTE_KIND (insn))
6912 {
6913 case NOTE_INSN_SWITCH_TEXT_SECTIONS:
6914 section_switch_p = true;
6915 break;
6916 case NOTE_INSN_VAR_LOCATION:
6917 case NOTE_INSN_CALL_ARG_LOCATION:
6918 continue;
6919 default:
6920 break;
6921 }
6922
6923 if (!curr_pool
6924 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
6925 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
6926 continue;
6927
6928 if (TARGET_CPU_ZARCH)
6929 {
6930 if (curr_pool->size < S390_POOL_CHUNK_MAX)
6931 continue;
6932
6933 s390_end_pool (curr_pool, NULL);
6934 curr_pool = NULL;
6935 }
6936 else
6937 {
6938 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
6939 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
6940 + extra_size;
6941
6942 /* We will later have to insert base register reload insns.
6943 Those will have an effect on code size, which we need to
6944 consider here. This calculation makes rather pessimistic
6945 worst-case assumptions. */
6946 if (LABEL_P (insn))
6947 extra_size += 6;
6948
6949 if (chunk_size < S390_POOL_CHUNK_MIN
6950 && curr_pool->size < S390_POOL_CHUNK_MIN
6951 && !section_switch_p)
6952 continue;
6953
6954 /* Pool chunks can only be inserted after BARRIERs ... */
6955 if (BARRIER_P (insn))
6956 {
6957 s390_end_pool (curr_pool, insn);
6958 curr_pool = NULL;
6959 extra_size = 0;
6960 }
6961
6962 /* ... so if we don't find one in time, create one. */
6963 else if (chunk_size > S390_POOL_CHUNK_MAX
6964 || curr_pool->size > S390_POOL_CHUNK_MAX
6965 || section_switch_p)
6966 {
6967 rtx_insn *label, *jump, *barrier, *next, *prev;
6968
6969 if (!section_switch_p)
6970 {
6971 /* We can insert the barrier only after a 'real' insn. */
6972 if (! NONJUMP_INSN_P (insn) && ! CALL_P (insn))
6973 continue;
6974 if (get_attr_length (insn) == 0)
6975 continue;
6976 /* Don't separate LTREL_BASE from the corresponding
6977 LTREL_OFFSET load. */
6978 if (pending_ltrel)
6979 continue;
6980 next = insn;
6981 do
6982 {
6983 insn = next;
6984 next = NEXT_INSN (insn);
6985 }
6986 while (next
6987 && NOTE_P (next)
6988 && (NOTE_KIND (next) == NOTE_INSN_VAR_LOCATION
6989 || NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION));
6990 }
6991 else
6992 {
6993 gcc_assert (!pending_ltrel);
6994
6995 /* The old pool has to end before the section switch
6996 note in order to make it part of the current
6997 section. */
6998 insn = PREV_INSN (insn);
6999 }
7000
7001 label = gen_label_rtx ();
7002 prev = insn;
7003 if (prev && NOTE_P (prev))
7004 prev = prev_nonnote_insn (prev);
7005 if (prev)
7006 jump = emit_jump_insn_after_setloc (gen_jump (label), insn,
7007 INSN_LOCATION (prev));
7008 else
7009 jump = emit_jump_insn_after_noloc (gen_jump (label), insn);
7010 barrier = emit_barrier_after (jump);
7011 insn = emit_label_after (label, barrier);
7012 JUMP_LABEL (jump) = label;
7013 LABEL_NUSES (label) = 1;
7014
7015 INSN_ADDRESSES_NEW (jump, -1);
7016 INSN_ADDRESSES_NEW (barrier, -1);
7017 INSN_ADDRESSES_NEW (insn, -1);
7018
7019 s390_end_pool (curr_pool, barrier);
7020 curr_pool = NULL;
7021 extra_size = 0;
7022 }
7023 }
7024 }
7025
7026 if (curr_pool)
7027 s390_end_pool (curr_pool, NULL);
7028 gcc_assert (!pending_ltrel);
7029
7030 /* Find all labels that are branched into
7031 from an insn belonging to a different chunk. */
7032
7033 far_labels = BITMAP_ALLOC (NULL);
7034
7035 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7036 {
7037 rtx_jump_table_data *table;
7038
7039 /* Labels marked with LABEL_PRESERVE_P can be target
7040 of non-local jumps, so we have to mark them.
7041 The same holds for named labels.
7042
7043 Don't do that, however, if it is the label before
7044 a jump table. */
7045
7046 if (LABEL_P (insn)
7047 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
7048 {
7049 rtx_insn *vec_insn = NEXT_INSN (insn);
7050 if (! vec_insn || ! JUMP_TABLE_DATA_P (vec_insn))
7051 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
7052 }
7053 /* Check potential targets in a table jump (casesi_jump). */
7054 else if (tablejump_p (insn, NULL, &table))
7055 {
7056 rtx vec_pat = PATTERN (table);
7057 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
7058
7059 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
7060 {
7061 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
7062
7063 if (s390_find_pool (pool_list, label)
7064 != s390_find_pool (pool_list, insn))
7065 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
7066 }
7067 }
7068 /* If we have a direct jump (conditional or unconditional),
7069 check all potential targets. */
7070 else if (JUMP_P (insn))
7071 {
7072 rtx pat = PATTERN (insn);
7073
7074 if (GET_CODE (pat) == PARALLEL)
7075 pat = XVECEXP (pat, 0, 0);
7076
7077 if (GET_CODE (pat) == SET)
7078 {
7079 rtx label = JUMP_LABEL (insn);
7080 if (label && !ANY_RETURN_P (label))
7081 {
7082 if (s390_find_pool (pool_list, label)
7083 != s390_find_pool (pool_list, insn))
7084 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
7085 }
7086 }
7087 }
7088 }
7089
7090 /* Insert base register reload insns before every pool. */
7091
7092 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
7093 {
7094 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
7095 curr_pool->label);
7096 rtx_insn *insn = curr_pool->first_insn;
7097 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
7098 }
7099
7100 /* Insert base register reload insns at every far label. */
7101
7102 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7103 if (LABEL_P (insn)
7104 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
7105 {
7106 struct constant_pool *pool = s390_find_pool (pool_list, insn);
7107 if (pool)
7108 {
7109 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
7110 pool->label);
7111 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
7112 }
7113 }
7114
7115
7116 BITMAP_FREE (far_labels);
7117
7118
7119 /* Recompute insn addresses. */
7120
7121 init_insn_lengths ();
7122 shorten_branches (get_insns ());
7123
7124 return pool_list;
7125 }
7126
7127 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
7128 After we have decided to use this list, finish implementing
7129 all changes to the current function as required. */
7130
7131 static void
7132 s390_chunkify_finish (struct constant_pool *pool_list)
7133 {
7134 struct constant_pool *curr_pool = NULL;
7135 rtx_insn *insn;
7136
7137
7138 /* Replace all literal pool references. */
7139
7140 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7141 {
7142 if (INSN_P (insn))
7143 replace_ltrel_base (&PATTERN (insn));
7144
7145 curr_pool = s390_find_pool (pool_list, insn);
7146 if (!curr_pool)
7147 continue;
7148
7149 if (NONJUMP_INSN_P (insn) || CALL_P (insn))
7150 {
7151 rtx addr, pool_ref = NULL_RTX;
7152 find_constant_pool_ref (PATTERN (insn), &pool_ref);
7153 if (pool_ref)
7154 {
7155 if (s390_execute_label (insn))
7156 addr = s390_find_execute (curr_pool, insn);
7157 else
7158 addr = s390_find_constant (curr_pool,
7159 get_pool_constant (pool_ref),
7160 get_pool_mode (pool_ref));
7161
7162 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
7163 INSN_CODE (insn) = -1;
7164 }
7165 }
7166 }
7167
7168 /* Dump out all literal pools. */
7169
7170 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
7171 s390_dump_pool (curr_pool, 0);
7172
7173 /* Free pool list. */
7174
7175 while (pool_list)
7176 {
7177 struct constant_pool *next = pool_list->next;
7178 s390_free_pool (pool_list);
7179 pool_list = next;
7180 }
7181 }
7182
7183 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
7184 We have decided we cannot use this list, so revert all changes
7185 to the current function that were done by s390_chunkify_start. */
7186
7187 static void
7188 s390_chunkify_cancel (struct constant_pool *pool_list)
7189 {
7190 struct constant_pool *curr_pool = NULL;
7191 rtx_insn *insn;
7192
7193 /* Remove all pool placeholder insns. */
7194
7195 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
7196 {
7197 /* Did we insert an extra barrier? Remove it. */
7198 rtx_insn *barrier = PREV_INSN (curr_pool->pool_insn);
7199 rtx_insn *jump = barrier? PREV_INSN (barrier) : NULL;
7200 rtx_insn *label = NEXT_INSN (curr_pool->pool_insn);
7201
7202 if (jump && JUMP_P (jump)
7203 && barrier && BARRIER_P (barrier)
7204 && label && LABEL_P (label)
7205 && GET_CODE (PATTERN (jump)) == SET
7206 && SET_DEST (PATTERN (jump)) == pc_rtx
7207 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
7208 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
7209 {
7210 remove_insn (jump);
7211 remove_insn (barrier);
7212 remove_insn (label);
7213 }
7214
7215 remove_insn (curr_pool->pool_insn);
7216 }
7217
7218 /* Remove all base register reload insns. */
7219
7220 for (insn = get_insns (); insn; )
7221 {
7222 rtx_insn *next_insn = NEXT_INSN (insn);
7223
7224 if (NONJUMP_INSN_P (insn)
7225 && GET_CODE (PATTERN (insn)) == SET
7226 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
7227 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
7228 remove_insn (insn);
7229
7230 insn = next_insn;
7231 }
7232
7233 /* Free pool list. */
7234
7235 while (pool_list)
7236 {
7237 struct constant_pool *next = pool_list->next;
7238 s390_free_pool (pool_list);
7239 pool_list = next;
7240 }
7241 }
7242
7243 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
7244
7245 void
7246 s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
7247 {
7248 REAL_VALUE_TYPE r;
7249
7250 switch (GET_MODE_CLASS (mode))
7251 {
7252 case MODE_FLOAT:
7253 case MODE_DECIMAL_FLOAT:
7254 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
7255
7256 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
7257 assemble_real (r, mode, align);
7258 break;
7259
7260 case MODE_INT:
7261 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
7262 mark_symbol_refs_as_used (exp);
7263 break;
7264
7265 default:
7266 gcc_unreachable ();
7267 }
7268 }
7269
7270
7271 /* Return an RTL expression representing the value of the return address
7272 for the frame COUNT steps up from the current frame. FRAME is the
7273 frame pointer of that frame. */
7274
7275 rtx
7276 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
7277 {
7278 int offset;
7279 rtx addr;
7280
7281 /* Without backchain, we fail for all but the current frame. */
7282
7283 if (!TARGET_BACKCHAIN && count > 0)
7284 return NULL_RTX;
7285
7286 /* For the current frame, we need to make sure the initial
7287 value of RETURN_REGNUM is actually saved. */
7288
7289 if (count == 0)
7290 {
7291 /* On non-z architectures branch splitting could overwrite r14. */
7292 if (TARGET_CPU_ZARCH)
7293 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
7294 else
7295 {
7296 cfun_frame_layout.save_return_addr_p = true;
7297 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
7298 }
7299 }
7300
7301 if (TARGET_PACKED_STACK)
7302 offset = -2 * UNITS_PER_LONG;
7303 else
7304 offset = RETURN_REGNUM * UNITS_PER_LONG;
7305
7306 addr = plus_constant (Pmode, frame, offset);
7307 addr = memory_address (Pmode, addr);
7308 return gen_rtx_MEM (Pmode, addr);
7309 }
7310
7311 /* Return an RTL expression representing the back chain stored in
7312 the current stack frame. */
7313
7314 rtx
7315 s390_back_chain_rtx (void)
7316 {
7317 rtx chain;
7318
7319 gcc_assert (TARGET_BACKCHAIN);
7320
7321 if (TARGET_PACKED_STACK)
7322 chain = plus_constant (Pmode, stack_pointer_rtx,
7323 STACK_POINTER_OFFSET - UNITS_PER_LONG);
7324 else
7325 chain = stack_pointer_rtx;
7326
7327 chain = gen_rtx_MEM (Pmode, chain);
7328 return chain;
7329 }
7330
7331 /* Find first call clobbered register unused in a function.
7332 This could be used as base register in a leaf function
7333 or for holding the return address before epilogue. */
7334
7335 static int
7336 find_unused_clobbered_reg (void)
7337 {
7338 int i;
7339 for (i = 0; i < 6; i++)
7340 if (!df_regs_ever_live_p (i))
7341 return i;
7342 return 0;
7343 }
7344
7345
7346 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
7347 clobbered hard regs in SETREG. */
7348
7349 static void
7350 s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *data)
7351 {
7352 char *regs_ever_clobbered = (char *)data;
7353 unsigned int i, regno;
7354 enum machine_mode mode = GET_MODE (setreg);
7355
7356 if (GET_CODE (setreg) == SUBREG)
7357 {
7358 rtx inner = SUBREG_REG (setreg);
7359 if (!GENERAL_REG_P (inner) && !FP_REG_P (inner))
7360 return;
7361 regno = subreg_regno (setreg);
7362 }
7363 else if (GENERAL_REG_P (setreg) || FP_REG_P (setreg))
7364 regno = REGNO (setreg);
7365 else
7366 return;
7367
7368 for (i = regno;
7369 i < regno + HARD_REGNO_NREGS (regno, mode);
7370 i++)
7371 regs_ever_clobbered[i] = 1;
7372 }
7373
7374 /* Walks through all basic blocks of the current function looking
7375 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
7376 of the passed integer array REGS_EVER_CLOBBERED are set to one for
7377 each of those regs. */
7378
7379 static void
7380 s390_regs_ever_clobbered (char regs_ever_clobbered[])
7381 {
7382 basic_block cur_bb;
7383 rtx_insn *cur_insn;
7384 unsigned int i;
7385
7386 memset (regs_ever_clobbered, 0, 32);
7387
7388 /* For non-leaf functions we have to consider all call clobbered regs to be
7389 clobbered. */
7390 if (!crtl->is_leaf)
7391 {
7392 for (i = 0; i < 32; i++)
7393 regs_ever_clobbered[i] = call_really_used_regs[i];
7394 }
7395
7396 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
7397 this work is done by liveness analysis (mark_regs_live_at_end).
7398 Special care is needed for functions containing landing pads. Landing pads
7399 may use the eh registers, but the code which sets these registers is not
7400 contained in that function. Hence s390_regs_ever_clobbered is not able to
7401 deal with this automatically. */
7402 if (crtl->calls_eh_return || cfun->machine->has_landing_pad_p)
7403 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
7404 if (crtl->calls_eh_return
7405 || (cfun->machine->has_landing_pad_p
7406 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i))))
7407 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
7408
7409 /* For nonlocal gotos all call-saved registers have to be saved.
7410 This flag is also set for the unwinding code in libgcc.
7411 See expand_builtin_unwind_init. For regs_ever_live this is done by
7412 reload. */
7413 if (crtl->saves_all_registers)
7414 for (i = 0; i < 32; i++)
7415 if (!call_really_used_regs[i])
7416 regs_ever_clobbered[i] = 1;
7417
7418 FOR_EACH_BB_FN (cur_bb, cfun)
7419 {
7420 FOR_BB_INSNS (cur_bb, cur_insn)
7421 {
7422 rtx pat;
7423
7424 if (!INSN_P (cur_insn))
7425 continue;
7426
7427 pat = PATTERN (cur_insn);
7428
7429 /* Ignore GPR restore insns. */
7430 if (epilogue_completed && RTX_FRAME_RELATED_P (cur_insn))
7431 {
7432 if (GET_CODE (pat) == SET
7433 && GENERAL_REG_P (SET_DEST (pat)))
7434 {
7435 /* lgdr */
7436 if (GET_MODE (SET_SRC (pat)) == DImode
7437 && FP_REG_P (SET_SRC (pat)))
7438 continue;
7439
7440 /* l / lg */
7441 if (GET_CODE (SET_SRC (pat)) == MEM)
7442 continue;
7443 }
7444
7445 /* lm / lmg */
7446 if (GET_CODE (pat) == PARALLEL
7447 && load_multiple_operation (pat, VOIDmode))
7448 continue;
7449 }
7450
7451 note_stores (pat,
7452 s390_reg_clobbered_rtx,
7453 regs_ever_clobbered);
7454 }
7455 }
7456 }
7457
7458 /* Determine the frame area which actually has to be accessed
7459 in the function epilogue. The values are stored at the
7460 given pointers AREA_BOTTOM (address of the lowest used stack
7461 address) and AREA_TOP (address of the first item which does
7462 not belong to the stack frame). */
7463
7464 static void
7465 s390_frame_area (int *area_bottom, int *area_top)
7466 {
7467 int b, t;
7468
7469 b = INT_MAX;
7470 t = INT_MIN;
7471
7472 if (cfun_frame_layout.first_restore_gpr != -1)
7473 {
7474 b = (cfun_frame_layout.gprs_offset
7475 + cfun_frame_layout.first_restore_gpr * UNITS_PER_LONG);
7476 t = b + (cfun_frame_layout.last_restore_gpr
7477 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_LONG;
7478 }
7479
7480 if (TARGET_64BIT && cfun_save_high_fprs_p)
7481 {
7482 b = MIN (b, cfun_frame_layout.f8_offset);
7483 t = MAX (t, (cfun_frame_layout.f8_offset
7484 + cfun_frame_layout.high_fprs * 8));
7485 }
7486
7487 if (!TARGET_64BIT)
7488 {
7489 if (cfun_fpr_save_p (FPR4_REGNUM))
7490 {
7491 b = MIN (b, cfun_frame_layout.f4_offset);
7492 t = MAX (t, cfun_frame_layout.f4_offset + 8);
7493 }
7494 if (cfun_fpr_save_p (FPR6_REGNUM))
7495 {
7496 b = MIN (b, cfun_frame_layout.f4_offset + 8);
7497 t = MAX (t, cfun_frame_layout.f4_offset + 16);
7498 }
7499 }
7500 *area_bottom = b;
7501 *area_top = t;
7502 }
7503 /* Update gpr_save_slots in the frame layout trying to make use of
7504 FPRs as GPR save slots.
7505 This is a helper routine of s390_register_info. */
7506
7507 static void
7508 s390_register_info_gprtofpr ()
7509 {
7510 int save_reg_slot = FPR0_REGNUM;
7511 int i, j;
7512
7513 if (!TARGET_Z10 || !TARGET_HARD_FLOAT || !crtl->is_leaf)
7514 return;
7515
7516 for (i = 15; i >= 6; i--)
7517 {
7518 if (cfun_gpr_save_slot (i) == 0)
7519 continue;
7520
7521 /* Advance to the next FP register which can be used as a
7522 GPR save slot. */
7523 while ((!call_really_used_regs[save_reg_slot]
7524 || df_regs_ever_live_p (save_reg_slot)
7525 || cfun_fpr_save_p (save_reg_slot))
7526 && FP_REGNO_P (save_reg_slot))
7527 save_reg_slot++;
7528 if (!FP_REGNO_P (save_reg_slot))
7529 {
7530 /* We only want to use ldgr/lgdr if we can get rid of
7531 stm/lm entirely. So undo the gpr slot allocation in
7532 case we ran out of FPR save slots. */
7533 for (j = 6; j <= 15; j++)
7534 if (FP_REGNO_P (cfun_gpr_save_slot (j)))
7535 cfun_gpr_save_slot (j) = -1;
7536 break;
7537 }
7538 cfun_gpr_save_slot (i) = save_reg_slot++;
7539 }
7540 }
7541
7542 /* Set the bits in fpr_bitmap for FPRs which need to be saved due to
7543 stdarg.
7544 This is a helper routine for s390_register_info. */
7545
7546 static void
7547 s390_register_info_stdarg_fpr ()
7548 {
7549 int i;
7550 int min_fpr;
7551 int max_fpr;
7552
7553 /* Save the FP argument regs for stdarg. f0, f2 for 31 bit and
7554 f0-f4 for 64 bit. */
7555 if (!cfun->stdarg
7556 || !TARGET_HARD_FLOAT
7557 || !cfun->va_list_fpr_size
7558 || crtl->args.info.fprs >= FP_ARG_NUM_REG)
7559 return;
7560
7561 min_fpr = crtl->args.info.fprs;
7562 max_fpr = min_fpr + cfun->va_list_fpr_size;
7563 if (max_fpr > FP_ARG_NUM_REG)
7564 max_fpr = FP_ARG_NUM_REG;
7565
7566 for (i = min_fpr; i < max_fpr; i++)
7567 cfun_set_fpr_save (i + FPR0_REGNUM);
7568 }
7569
7570 /* Reserve the GPR save slots for GPRs which need to be saved due to
7571 stdarg.
7572 This is a helper routine for s390_register_info. */
7573
7574 static void
7575 s390_register_info_stdarg_gpr ()
7576 {
7577 int i;
7578 int min_gpr;
7579 int max_gpr;
7580
7581 if (!cfun->stdarg
7582 || !cfun->va_list_gpr_size
7583 || crtl->args.info.gprs >= GP_ARG_NUM_REG)
7584 return;
7585
7586 min_gpr = crtl->args.info.gprs;
7587 max_gpr = min_gpr + cfun->va_list_gpr_size;
7588 if (max_gpr > GP_ARG_NUM_REG)
7589 max_gpr = GP_ARG_NUM_REG;
7590
7591 for (i = min_gpr; i < max_gpr; i++)
7592 cfun_gpr_save_slot (2 + i) = -1;
7593 }
7594
7595 /* The GPR and FPR save slots in cfun->machine->frame_layout are set
7596 for registers which need to be saved in function prologue.
7597 This function can be used until the insns emitted for save/restore
7598 of the regs are visible in the RTL stream. */
7599
7600 static void
7601 s390_register_info ()
7602 {
7603 int i, j;
7604 char clobbered_regs[32];
7605
7606 gcc_assert (!epilogue_completed);
7607
7608 if (reload_completed)
7609 /* After reload we rely on our own routine to determine which
7610 registers need saving. */
7611 s390_regs_ever_clobbered (clobbered_regs);
7612 else
7613 /* During reload we use regs_ever_live as a base since reload
7614 does changes in there which we otherwise would not be aware
7615 of. */
7616 for (i = 0; i < 32; i++)
7617 clobbered_regs[i] = df_regs_ever_live_p (i);
7618
7619 for (i = 0; i < 32; i++)
7620 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i];
7621
7622 /* Mark the call-saved FPRs which need to be saved.
7623 This needs to be done before checking the special GPRs since the
7624 stack pointer usage depends on whether high FPRs have to be saved
7625 or not. */
7626 cfun_frame_layout.fpr_bitmap = 0;
7627 cfun_frame_layout.high_fprs = 0;
7628 for (i = FPR0_REGNUM; i <= FPR15_REGNUM; i++)
7629 if (clobbered_regs[i] && !call_really_used_regs[i])
7630 {
7631 cfun_set_fpr_save (i);
7632 if (i >= FPR8_REGNUM)
7633 cfun_frame_layout.high_fprs++;
7634 }
7635
7636 if (flag_pic)
7637 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
7638 |= !!df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
7639
7640 clobbered_regs[BASE_REGNUM]
7641 |= (cfun->machine->base_reg
7642 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
7643
7644 clobbered_regs[HARD_FRAME_POINTER_REGNUM]
7645 |= !!frame_pointer_needed;
7646
7647 /* On pre z900 machines this might take until machine dependent
7648 reorg to decide.
7649 save_return_addr_p will only be set on non-zarch machines so
7650 there is no risk that r14 goes into an FPR instead of a stack
7651 slot. */
7652 clobbered_regs[RETURN_REGNUM]
7653 |= (!crtl->is_leaf
7654 || TARGET_TPF_PROFILING
7655 || cfun->machine->split_branches_pending_p
7656 || cfun_frame_layout.save_return_addr_p
7657 || crtl->calls_eh_return);
7658
7659 clobbered_regs[STACK_POINTER_REGNUM]
7660 |= (!crtl->is_leaf
7661 || TARGET_TPF_PROFILING
7662 || cfun_save_high_fprs_p
7663 || get_frame_size () > 0
7664 || (reload_completed && cfun_frame_layout.frame_size > 0)
7665 || cfun->calls_alloca);
7666
7667 memset (cfun_frame_layout.gpr_save_slots, 0, 16);
7668
7669 for (i = 6; i < 16; i++)
7670 if (clobbered_regs[i])
7671 cfun_gpr_save_slot (i) = -1;
7672
7673 s390_register_info_stdarg_fpr ();
7674 s390_register_info_gprtofpr ();
7675
7676 /* First find the range of GPRs to be restored. Vararg regs don't
7677 need to be restored so we do it before assigning slots to the
7678 vararg GPRs. */
7679 for (i = 0; i < 16 && cfun_gpr_save_slot (i) != -1; i++);
7680 for (j = 15; j > i && cfun_gpr_save_slot (j) != -1; j--);
7681 cfun_frame_layout.first_restore_gpr = (i == 16) ? -1 : i;
7682 cfun_frame_layout.last_restore_gpr = (i == 16) ? -1 : j;
7683
7684 /* stdarg functions might need to save GPRs 2 to 6. This might
7685 override the GPR->FPR save decision made above for r6 since
7686 vararg regs must go to the stack. */
7687 s390_register_info_stdarg_gpr ();
7688
7689 /* Now the range of GPRs which need saving. */
7690 for (i = 0; i < 16 && cfun_gpr_save_slot (i) != -1; i++);
7691 for (j = 15; j > i && cfun_gpr_save_slot (j) != -1; j--);
7692 cfun_frame_layout.first_save_gpr = (i == 16) ? -1 : i;
7693 cfun_frame_layout.last_save_gpr = (i == 16) ? -1 : j;
7694 }
7695
7696 /* This function is called by s390_optimize_prologue in order to get
7697 rid of unnecessary GPR save/restore instructions. The register info
7698 for the GPRs is re-computed and the ranges are re-calculated. */
7699
7700 static void
7701 s390_optimize_register_info ()
7702 {
7703 char clobbered_regs[32];
7704 int i, j;
7705
7706 gcc_assert (epilogue_completed);
7707 gcc_assert (!cfun->machine->split_branches_pending_p);
7708
7709 s390_regs_ever_clobbered (clobbered_regs);
7710
7711 for (i = 0; i < 32; i++)
7712 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i];
7713
7714 /* There is still special treatment needed for cases invisible to
7715 s390_regs_ever_clobbered. */
7716 clobbered_regs[RETURN_REGNUM]
7717 |= (TARGET_TPF_PROFILING
7718 /* When expanding builtin_return_addr in ESA mode we do not
7719 know whether r14 will later be needed as scratch reg when
7720 doing branch splitting. So the builtin always accesses the
7721 r14 save slot and we need to stick to the save/restore
7722 decision for r14 even if it turns out that it didn't get
7723 clobbered. */
7724 || cfun_frame_layout.save_return_addr_p
7725 || crtl->calls_eh_return);
7726
7727 memset (cfun_frame_layout.gpr_save_slots, 0, 6);
7728
7729 for (i = 6; i < 16; i++)
7730 if (!clobbered_regs[i])
7731 cfun_gpr_save_slot (i) = 0;
7732
7733 for (i = 0; i < 16 && cfun_gpr_save_slot (i) != -1; i++);
7734 for (j = 15; j > i && cfun_gpr_save_slot (j) != -1; j--);
7735 cfun_frame_layout.first_restore_gpr = (i == 16) ? -1 : i;
7736 cfun_frame_layout.last_restore_gpr = (i == 16) ? -1 : j;
7737
7738 s390_register_info_stdarg_gpr ();
7739
7740 for (i = 0; i < 16 && cfun_gpr_save_slot (i) != -1; i++);
7741 for (j = 15; j > i && cfun_gpr_save_slot (j) != -1; j--);
7742 cfun_frame_layout.first_save_gpr = (i == 16) ? -1 : i;
7743 cfun_frame_layout.last_save_gpr = (i == 16) ? -1 : j;
7744 }
7745
7746 /* Fill cfun->machine with info about frame of current function. */
7747
7748 static void
7749 s390_frame_info (void)
7750 {
7751 HOST_WIDE_INT lowest_offset;
7752
7753 cfun_frame_layout.first_save_gpr_slot = cfun_frame_layout.first_save_gpr;
7754 cfun_frame_layout.last_save_gpr_slot = cfun_frame_layout.last_save_gpr;
7755
7756 /* The va_arg builtin uses a constant distance of 16 *
7757 UNITS_PER_LONG (r0-r15) to reach the FPRs from the reg_save_area
7758 pointer. So even if we are going to save the stack pointer in an
7759 FPR we need the stack space in order to keep the offsets
7760 correct. */
7761 if (cfun->stdarg && cfun_save_arg_fprs_p)
7762 {
7763 cfun_frame_layout.last_save_gpr_slot = STACK_POINTER_REGNUM;
7764
7765 if (cfun_frame_layout.first_save_gpr_slot == -1)
7766 cfun_frame_layout.first_save_gpr_slot = STACK_POINTER_REGNUM;
7767 }
7768
7769 cfun_frame_layout.frame_size = get_frame_size ();
7770 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
7771 fatal_error ("total size of local variables exceeds architecture limit");
7772
7773 if (!TARGET_PACKED_STACK)
7774 {
7775 /* Fixed stack layout. */
7776 cfun_frame_layout.backchain_offset = 0;
7777 cfun_frame_layout.f0_offset = 16 * UNITS_PER_LONG;
7778 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
7779 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
7780 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
7781 * UNITS_PER_LONG);
7782 }
7783 else if (TARGET_BACKCHAIN)
7784 {
7785 /* Kernel stack layout - packed stack, backchain, no float */
7786 gcc_assert (TARGET_SOFT_FLOAT);
7787 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
7788 - UNITS_PER_LONG);
7789
7790 /* The distance between the backchain and the return address
7791 save slot must not change. So we always need a slot for the
7792 stack pointer which resides in between. */
7793 cfun_frame_layout.last_save_gpr_slot = STACK_POINTER_REGNUM;
7794
7795 cfun_frame_layout.gprs_offset
7796 = cfun_frame_layout.backchain_offset - cfun_gprs_save_area_size;
7797
7798 /* FPRs will not be saved. Nevertheless pick sane values to
7799 keep area calculations valid. */
7800 cfun_frame_layout.f0_offset =
7801 cfun_frame_layout.f4_offset =
7802 cfun_frame_layout.f8_offset = cfun_frame_layout.gprs_offset;
7803 }
7804 else
7805 {
7806 int num_fprs;
7807
7808 /* Packed stack layout without backchain. */
7809
7810 /* With stdarg FPRs need their dedicated slots. */
7811 num_fprs = (TARGET_64BIT && cfun->stdarg ? 2
7812 : (cfun_fpr_save_p (FPR4_REGNUM) +
7813 cfun_fpr_save_p (FPR6_REGNUM)));
7814 cfun_frame_layout.f4_offset = STACK_POINTER_OFFSET - 8 * num_fprs;
7815
7816 num_fprs = (cfun->stdarg ? 2
7817 : (cfun_fpr_save_p (FPR0_REGNUM)
7818 + cfun_fpr_save_p (FPR2_REGNUM)));
7819 cfun_frame_layout.f0_offset = cfun_frame_layout.f4_offset - 8 * num_fprs;
7820
7821 cfun_frame_layout.gprs_offset
7822 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
7823
7824 cfun_frame_layout.f8_offset = (cfun_frame_layout.gprs_offset
7825 - cfun_frame_layout.high_fprs * 8);
7826 }
7827
7828 if (cfun_save_high_fprs_p)
7829 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
7830
7831 if (!crtl->is_leaf)
7832 cfun_frame_layout.frame_size += crtl->outgoing_args_size;
7833
7834 /* In the following cases we have to allocate a STACK_POINTER_OFFSET
7835 sized area at the bottom of the stack. This is required also for
7836 leaf functions. When GCC generates a local stack reference it
7837 will always add STACK_POINTER_OFFSET to all these references. */
7838 if (crtl->is_leaf
7839 && !TARGET_TPF_PROFILING
7840 && cfun_frame_layout.frame_size == 0
7841 && !cfun->calls_alloca)
7842 return;
7843
7844 /* Calculate the number of bytes we have used in our own register
7845 save area. With the packed stack layout we can re-use the
7846 remaining bytes for normal stack elements. */
7847
7848 if (TARGET_PACKED_STACK)
7849 lowest_offset = MIN (MIN (cfun_frame_layout.f0_offset,
7850 cfun_frame_layout.f4_offset),
7851 cfun_frame_layout.gprs_offset);
7852 else
7853 lowest_offset = 0;
7854
7855 if (TARGET_BACKCHAIN)
7856 lowest_offset = MIN (lowest_offset, cfun_frame_layout.backchain_offset);
7857
7858 cfun_frame_layout.frame_size += STACK_POINTER_OFFSET - lowest_offset;
7859
7860 /* If under 31 bit an odd number of gprs has to be saved we have to
7861 adjust the frame size to sustain 8 byte alignment of stack
7862 frames. */
7863 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
7864 STACK_BOUNDARY / BITS_PER_UNIT - 1)
7865 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
7866 }
7867
7868 /* Generate frame layout. Fills in register and frame data for the current
7869 function in cfun->machine. This routine can be called multiple times;
7870 it will re-do the complete frame layout every time. */
7871
7872 static void
7873 s390_init_frame_layout (void)
7874 {
7875 HOST_WIDE_INT frame_size;
7876 int base_used;
7877
7878 gcc_assert (!reload_completed);
7879
7880 /* On S/390 machines, we may need to perform branch splitting, which
7881 will require both base and return address register. We have no
7882 choice but to assume we're going to need them until right at the
7883 end of the machine dependent reorg phase. */
7884 if (!TARGET_CPU_ZARCH)
7885 cfun->machine->split_branches_pending_p = true;
7886
7887 do
7888 {
7889 frame_size = cfun_frame_layout.frame_size;
7890
7891 /* Try to predict whether we'll need the base register. */
7892 base_used = cfun->machine->split_branches_pending_p
7893 || crtl->uses_const_pool
7894 || (!DISP_IN_RANGE (frame_size)
7895 && !CONST_OK_FOR_K (frame_size));
7896
7897 /* Decide which register to use as literal pool base. In small
7898 leaf functions, try to use an unused call-clobbered register
7899 as base register to avoid save/restore overhead. */
7900 if (!base_used)
7901 cfun->machine->base_reg = NULL_RTX;
7902 else if (crtl->is_leaf && !df_regs_ever_live_p (5))
7903 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
7904 else
7905 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
7906
7907 s390_register_info ();
7908 s390_frame_info ();
7909 }
7910 while (frame_size != cfun_frame_layout.frame_size);
7911 }
7912
7913 /* Remove the FPR clobbers from a tbegin insn if it can be proven that
7914 the TX is nonescaping. A transaction is considered escaping if
7915 there is at least one path from tbegin returning CC0 to the
7916 function exit block without an tend.
7917
7918 The check so far has some limitations:
7919 - only single tbegin/tend BBs are supported
7920 - the first cond jump after tbegin must separate the CC0 path from ~CC0
7921 - when CC is copied to a GPR and the CC0 check is done with the GPR
7922 this is not supported
7923 */
7924
7925 static void
7926 s390_optimize_nonescaping_tx (void)
7927 {
7928 const unsigned int CC0 = 1 << 3;
7929 basic_block tbegin_bb = NULL;
7930 basic_block tend_bb = NULL;
7931 basic_block bb;
7932 rtx_insn *insn;
7933 bool result = true;
7934 int bb_index;
7935 rtx_insn *tbegin_insn = NULL;
7936
7937 if (!cfun->machine->tbegin_p)
7938 return;
7939
7940 for (bb_index = 0; bb_index < n_basic_blocks_for_fn (cfun); bb_index++)
7941 {
7942 bb = BASIC_BLOCK_FOR_FN (cfun, bb_index);
7943
7944 if (!bb)
7945 continue;
7946
7947 FOR_BB_INSNS (bb, insn)
7948 {
7949 rtx ite, cc, pat, target;
7950 unsigned HOST_WIDE_INT mask;
7951
7952 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
7953 continue;
7954
7955 pat = PATTERN (insn);
7956
7957 if (GET_CODE (pat) == PARALLEL)
7958 pat = XVECEXP (pat, 0, 0);
7959
7960 if (GET_CODE (pat) != SET
7961 || GET_CODE (SET_SRC (pat)) != UNSPEC_VOLATILE)
7962 continue;
7963
7964 if (XINT (SET_SRC (pat), 1) == UNSPECV_TBEGIN)
7965 {
7966 rtx_insn *tmp;
7967
7968 tbegin_insn = insn;
7969
7970 /* Just return if the tbegin doesn't have clobbers. */
7971 if (GET_CODE (PATTERN (insn)) != PARALLEL)
7972 return;
7973
7974 if (tbegin_bb != NULL)
7975 return;
7976
7977 /* Find the next conditional jump. */
7978 for (tmp = NEXT_INSN (insn);
7979 tmp != NULL_RTX;
7980 tmp = NEXT_INSN (tmp))
7981 {
7982 if (reg_set_p (gen_rtx_REG (CCmode, CC_REGNUM), tmp))
7983 return;
7984 if (!JUMP_P (tmp))
7985 continue;
7986
7987 ite = SET_SRC (PATTERN (tmp));
7988 if (GET_CODE (ite) != IF_THEN_ELSE)
7989 continue;
7990
7991 cc = XEXP (XEXP (ite, 0), 0);
7992 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc))
7993 || GET_MODE (cc) != CCRAWmode
7994 || GET_CODE (XEXP (XEXP (ite, 0), 1)) != CONST_INT)
7995 return;
7996
7997 if (bb->succs->length () != 2)
7998 return;
7999
8000 mask = INTVAL (XEXP (XEXP (ite, 0), 1));
8001 if (GET_CODE (XEXP (ite, 0)) == NE)
8002 mask ^= 0xf;
8003
8004 if (mask == CC0)
8005 target = XEXP (ite, 1);
8006 else if (mask == (CC0 ^ 0xf))
8007 target = XEXP (ite, 2);
8008 else
8009 return;
8010
8011 {
8012 edge_iterator ei;
8013 edge e1, e2;
8014
8015 ei = ei_start (bb->succs);
8016 e1 = ei_safe_edge (ei);
8017 ei_next (&ei);
8018 e2 = ei_safe_edge (ei);
8019
8020 if (e2->flags & EDGE_FALLTHRU)
8021 {
8022 e2 = e1;
8023 e1 = ei_safe_edge (ei);
8024 }
8025
8026 if (!(e1->flags & EDGE_FALLTHRU))
8027 return;
8028
8029 tbegin_bb = (target == pc_rtx) ? e1->dest : e2->dest;
8030 }
8031 if (tmp == BB_END (bb))
8032 break;
8033 }
8034 }
8035
8036 if (XINT (SET_SRC (pat), 1) == UNSPECV_TEND)
8037 {
8038 if (tend_bb != NULL)
8039 return;
8040 tend_bb = bb;
8041 }
8042 }
8043 }
8044
8045 /* Either we successfully remove the FPR clobbers here or we are not
8046 able to do anything for this TX. Both cases don't qualify for
8047 another look. */
8048 cfun->machine->tbegin_p = false;
8049
8050 if (tbegin_bb == NULL || tend_bb == NULL)
8051 return;
8052
8053 calculate_dominance_info (CDI_POST_DOMINATORS);
8054 result = dominated_by_p (CDI_POST_DOMINATORS, tbegin_bb, tend_bb);
8055 free_dominance_info (CDI_POST_DOMINATORS);
8056
8057 if (!result)
8058 return;
8059
8060 PATTERN (tbegin_insn) = gen_rtx_PARALLEL (VOIDmode,
8061 gen_rtvec (2,
8062 XVECEXP (PATTERN (tbegin_insn), 0, 0),
8063 XVECEXP (PATTERN (tbegin_insn), 0, 1)));
8064 INSN_CODE (tbegin_insn) = -1;
8065 df_insn_rescan (tbegin_insn);
8066
8067 return;
8068 }
8069
8070 /* Return true if it is legal to put a value with MODE into REGNO. */
8071
8072 bool
8073 s390_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
8074 {
8075 switch (REGNO_REG_CLASS (regno))
8076 {
8077 case FP_REGS:
8078 if (REGNO_PAIR_OK (regno, mode))
8079 {
8080 if (mode == SImode || mode == DImode)
8081 return true;
8082
8083 if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
8084 return true;
8085 }
8086 break;
8087 case ADDR_REGS:
8088 if (FRAME_REGNO_P (regno) && mode == Pmode)
8089 return true;
8090
8091 /* fallthrough */
8092 case GENERAL_REGS:
8093 if (REGNO_PAIR_OK (regno, mode))
8094 {
8095 if (TARGET_ZARCH
8096 || (mode != TFmode && mode != TCmode && mode != TDmode))
8097 return true;
8098 }
8099 break;
8100 case CC_REGS:
8101 if (GET_MODE_CLASS (mode) == MODE_CC)
8102 return true;
8103 break;
8104 case ACCESS_REGS:
8105 if (REGNO_PAIR_OK (regno, mode))
8106 {
8107 if (mode == SImode || mode == Pmode)
8108 return true;
8109 }
8110 break;
8111 default:
8112 return false;
8113 }
8114
8115 return false;
8116 }
8117
8118 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
8119
8120 bool
8121 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
8122 {
8123 /* Once we've decided upon a register to use as base register, it must
8124 no longer be used for any other purpose. */
8125 if (cfun->machine->base_reg)
8126 if (REGNO (cfun->machine->base_reg) == old_reg
8127 || REGNO (cfun->machine->base_reg) == new_reg)
8128 return false;
8129
8130 /* Prevent regrename from using call-saved regs which haven't
8131 actually been saved. This is necessary since regrename assumes
8132 the backend save/restore decisions are based on
8133 df_regs_ever_live. Since we have our own routine we have to tell
8134 regrename manually about it. */
8135 if (GENERAL_REGNO_P (new_reg)
8136 && !call_really_used_regs[new_reg]
8137 && cfun_gpr_save_slot (new_reg) == 0)
8138 return false;
8139
8140 return true;
8141 }
8142
8143 /* Return nonzero if register REGNO can be used as a scratch register
8144 in peephole2. */
8145
8146 static bool
8147 s390_hard_regno_scratch_ok (unsigned int regno)
8148 {
8149 /* See s390_hard_regno_rename_ok. */
8150 if (GENERAL_REGNO_P (regno)
8151 && !call_really_used_regs[regno]
8152 && cfun_gpr_save_slot (regno) == 0)
8153 return false;
8154
8155 return true;
8156 }
8157
8158 /* Maximum number of registers to represent a value of mode MODE
8159 in a register of class RCLASS. */
8160
8161 int
8162 s390_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
8163 {
8164 switch (rclass)
8165 {
8166 case FP_REGS:
8167 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
8168 return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
8169 else
8170 return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
8171 case ACCESS_REGS:
8172 return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
8173 default:
8174 break;
8175 }
8176 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8177 }
8178
8179 /* Return true if we use LRA instead of reload pass. */
8180 static bool
8181 s390_lra_p (void)
8182 {
8183 return s390_lra_flag;
8184 }
8185
8186 /* Return true if register FROM can be eliminated via register TO. */
8187
8188 static bool
8189 s390_can_eliminate (const int from, const int to)
8190 {
8191 /* On zSeries machines, we have not marked the base register as fixed.
8192 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
8193 If a function requires the base register, we say here that this
8194 elimination cannot be performed. This will cause reload to free
8195 up the base register (as if it were fixed). On the other hand,
8196 if the current function does *not* require the base register, we
8197 say here the elimination succeeds, which in turn allows reload
8198 to allocate the base register for any other purpose. */
8199 if (from == BASE_REGNUM && to == BASE_REGNUM)
8200 {
8201 if (TARGET_CPU_ZARCH)
8202 {
8203 s390_init_frame_layout ();
8204 return cfun->machine->base_reg == NULL_RTX;
8205 }
8206
8207 return false;
8208 }
8209
8210 /* Everything else must point into the stack frame. */
8211 gcc_assert (to == STACK_POINTER_REGNUM
8212 || to == HARD_FRAME_POINTER_REGNUM);
8213
8214 gcc_assert (from == FRAME_POINTER_REGNUM
8215 || from == ARG_POINTER_REGNUM
8216 || from == RETURN_ADDRESS_POINTER_REGNUM);
8217
8218 /* Make sure we actually saved the return address. */
8219 if (from == RETURN_ADDRESS_POINTER_REGNUM)
8220 if (!crtl->calls_eh_return
8221 && !cfun->stdarg
8222 && !cfun_frame_layout.save_return_addr_p)
8223 return false;
8224
8225 return true;
8226 }
8227
8228 /* Return offset between register FROM and TO initially after prolog. */
8229
8230 HOST_WIDE_INT
8231 s390_initial_elimination_offset (int from, int to)
8232 {
8233 HOST_WIDE_INT offset;
8234
8235 /* ??? Why are we called for non-eliminable pairs? */
8236 if (!s390_can_eliminate (from, to))
8237 return 0;
8238
8239 switch (from)
8240 {
8241 case FRAME_POINTER_REGNUM:
8242 offset = (get_frame_size()
8243 + STACK_POINTER_OFFSET
8244 + crtl->outgoing_args_size);
8245 break;
8246
8247 case ARG_POINTER_REGNUM:
8248 s390_init_frame_layout ();
8249 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
8250 break;
8251
8252 case RETURN_ADDRESS_POINTER_REGNUM:
8253 s390_init_frame_layout ();
8254
8255 if (cfun_frame_layout.first_save_gpr_slot == -1)
8256 {
8257 /* If it turns out that for stdarg nothing went into the reg
8258 save area we also do not need the return address
8259 pointer. */
8260 if (cfun->stdarg && !cfun_save_arg_fprs_p)
8261 return 0;
8262
8263 gcc_unreachable ();
8264 }
8265
8266 /* In order to make the following work it is not necessary for
8267 r14 to have a save slot. It is sufficient if one other GPR
8268 got one. Since the GPRs are always stored without gaps we
8269 are able to calculate where the r14 save slot would
8270 reside. */
8271 offset = (cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset +
8272 (RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot) *
8273 UNITS_PER_LONG);
8274 break;
8275
8276 case BASE_REGNUM:
8277 offset = 0;
8278 break;
8279
8280 default:
8281 gcc_unreachable ();
8282 }
8283
8284 return offset;
8285 }
8286
8287 /* Emit insn to save fpr REGNUM at offset OFFSET relative
8288 to register BASE. Return generated insn. */
8289
8290 static rtx
8291 save_fpr (rtx base, int offset, int regnum)
8292 {
8293 rtx addr;
8294 addr = gen_rtx_MEM (DFmode, plus_constant (Pmode, base, offset));
8295
8296 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
8297 set_mem_alias_set (addr, get_varargs_alias_set ());
8298 else
8299 set_mem_alias_set (addr, get_frame_alias_set ());
8300
8301 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
8302 }
8303
8304 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
8305 to register BASE. Return generated insn. */
8306
8307 static rtx
8308 restore_fpr (rtx base, int offset, int regnum)
8309 {
8310 rtx addr;
8311 addr = gen_rtx_MEM (DFmode, plus_constant (Pmode, base, offset));
8312 set_mem_alias_set (addr, get_frame_alias_set ());
8313
8314 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
8315 }
8316
8317 /* Return true if REGNO is a global register, but not one
8318 of the special ones that need to be saved/restored in anyway. */
8319
8320 static inline bool
8321 global_not_special_regno_p (int regno)
8322 {
8323 return (global_regs[regno]
8324 /* These registers are special and need to be
8325 restored in any case. */
8326 && !(regno == STACK_POINTER_REGNUM
8327 || regno == RETURN_REGNUM
8328 || regno == BASE_REGNUM
8329 || (flag_pic && regno == (int)PIC_OFFSET_TABLE_REGNUM)));
8330 }
8331
8332 /* Generate insn to save registers FIRST to LAST into
8333 the register save area located at offset OFFSET
8334 relative to register BASE. */
8335
8336 static rtx
8337 save_gprs (rtx base, int offset, int first, int last)
8338 {
8339 rtx addr, insn, note;
8340 int i;
8341
8342 addr = plus_constant (Pmode, base, offset);
8343 addr = gen_rtx_MEM (Pmode, addr);
8344
8345 set_mem_alias_set (addr, get_frame_alias_set ());
8346
8347 /* Special-case single register. */
8348 if (first == last)
8349 {
8350 if (TARGET_64BIT)
8351 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
8352 else
8353 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
8354
8355 if (!global_not_special_regno_p (first))
8356 RTX_FRAME_RELATED_P (insn) = 1;
8357 return insn;
8358 }
8359
8360
8361 insn = gen_store_multiple (addr,
8362 gen_rtx_REG (Pmode, first),
8363 GEN_INT (last - first + 1));
8364
8365 if (first <= 6 && cfun->stdarg)
8366 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8367 {
8368 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
8369
8370 if (first + i <= 6)
8371 set_mem_alias_set (mem, get_varargs_alias_set ());
8372 }
8373
8374 /* We need to set the FRAME_RELATED flag on all SETs
8375 inside the store-multiple pattern.
8376
8377 However, we must not emit DWARF records for registers 2..5
8378 if they are stored for use by variable arguments ...
8379
8380 ??? Unfortunately, it is not enough to simply not the
8381 FRAME_RELATED flags for those SETs, because the first SET
8382 of the PARALLEL is always treated as if it had the flag
8383 set, even if it does not. Therefore we emit a new pattern
8384 without those registers as REG_FRAME_RELATED_EXPR note. */
8385
8386 if (first >= 6 && !global_not_special_regno_p (first))
8387 {
8388 rtx pat = PATTERN (insn);
8389
8390 for (i = 0; i < XVECLEN (pat, 0); i++)
8391 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
8392 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat,
8393 0, i)))))
8394 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
8395
8396 RTX_FRAME_RELATED_P (insn) = 1;
8397 }
8398 else if (last >= 6)
8399 {
8400 int start;
8401
8402 for (start = first >= 6 ? first : 6; start <= last; start++)
8403 if (!global_not_special_regno_p (start))
8404 break;
8405
8406 if (start > last)
8407 return insn;
8408
8409 addr = plus_constant (Pmode, base,
8410 offset + (start - first) * UNITS_PER_LONG);
8411
8412 if (start == last)
8413 {
8414 if (TARGET_64BIT)
8415 note = gen_movdi (gen_rtx_MEM (Pmode, addr),
8416 gen_rtx_REG (Pmode, start));
8417 else
8418 note = gen_movsi (gen_rtx_MEM (Pmode, addr),
8419 gen_rtx_REG (Pmode, start));
8420 note = PATTERN (note);
8421
8422 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
8423 RTX_FRAME_RELATED_P (insn) = 1;
8424
8425 return insn;
8426 }
8427
8428 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
8429 gen_rtx_REG (Pmode, start),
8430 GEN_INT (last - start + 1));
8431 note = PATTERN (note);
8432
8433 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
8434
8435 for (i = 0; i < XVECLEN (note, 0); i++)
8436 if (GET_CODE (XVECEXP (note, 0, i)) == SET
8437 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note,
8438 0, i)))))
8439 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
8440
8441 RTX_FRAME_RELATED_P (insn) = 1;
8442 }
8443
8444 return insn;
8445 }
8446
8447 /* Generate insn to restore registers FIRST to LAST from
8448 the register save area located at offset OFFSET
8449 relative to register BASE. */
8450
8451 static rtx
8452 restore_gprs (rtx base, int offset, int first, int last)
8453 {
8454 rtx addr, insn;
8455
8456 addr = plus_constant (Pmode, base, offset);
8457 addr = gen_rtx_MEM (Pmode, addr);
8458 set_mem_alias_set (addr, get_frame_alias_set ());
8459
8460 /* Special-case single register. */
8461 if (first == last)
8462 {
8463 if (TARGET_64BIT)
8464 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
8465 else
8466 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
8467
8468 RTX_FRAME_RELATED_P (insn) = 1;
8469 return insn;
8470 }
8471
8472 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
8473 addr,
8474 GEN_INT (last - first + 1));
8475 RTX_FRAME_RELATED_P (insn) = 1;
8476 return insn;
8477 }
8478
8479 /* Return insn sequence to load the GOT register. */
8480
8481 static GTY(()) rtx got_symbol;
8482 rtx_insn *
8483 s390_load_got (void)
8484 {
8485 rtx_insn *insns;
8486
8487 /* We cannot use pic_offset_table_rtx here since we use this
8488 function also for non-pic if __tls_get_offset is called and in
8489 that case PIC_OFFSET_TABLE_REGNUM as well as pic_offset_table_rtx
8490 aren't usable. */
8491 rtx got_rtx = gen_rtx_REG (Pmode, 12);
8492
8493 if (!got_symbol)
8494 {
8495 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
8496 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
8497 }
8498
8499 start_sequence ();
8500
8501 if (TARGET_CPU_ZARCH)
8502 {
8503 emit_move_insn (got_rtx, got_symbol);
8504 }
8505 else
8506 {
8507 rtx offset;
8508
8509 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
8510 UNSPEC_LTREL_OFFSET);
8511 offset = gen_rtx_CONST (Pmode, offset);
8512 offset = force_const_mem (Pmode, offset);
8513
8514 emit_move_insn (got_rtx, offset);
8515
8516 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
8517 UNSPEC_LTREL_BASE);
8518 offset = gen_rtx_PLUS (Pmode, got_rtx, offset);
8519
8520 emit_move_insn (got_rtx, offset);
8521 }
8522
8523 insns = get_insns ();
8524 end_sequence ();
8525 return insns;
8526 }
8527
8528 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
8529 and the change to the stack pointer. */
8530
8531 static void
8532 s390_emit_stack_tie (void)
8533 {
8534 rtx mem = gen_frame_mem (BLKmode,
8535 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
8536
8537 emit_insn (gen_stack_tie (mem));
8538 }
8539
8540 /* Copy GPRS into FPR save slots. */
8541
8542 static void
8543 s390_save_gprs_to_fprs (void)
8544 {
8545 int i;
8546
8547 if (!TARGET_Z10 || !TARGET_HARD_FLOAT || !crtl->is_leaf)
8548 return;
8549
8550 for (i = 6; i < 16; i++)
8551 {
8552 if (FP_REGNO_P (cfun_gpr_save_slot (i)))
8553 {
8554 rtx_insn *insn =
8555 emit_move_insn (gen_rtx_REG (DImode, cfun_gpr_save_slot (i)),
8556 gen_rtx_REG (DImode, i));
8557 RTX_FRAME_RELATED_P (insn) = 1;
8558 }
8559 }
8560 }
8561
8562 /* Restore GPRs from FPR save slots. */
8563
8564 static void
8565 s390_restore_gprs_from_fprs (void)
8566 {
8567 int i;
8568
8569 if (!TARGET_Z10 || !TARGET_HARD_FLOAT || !crtl->is_leaf)
8570 return;
8571
8572 for (i = 6; i < 16; i++)
8573 {
8574 if (FP_REGNO_P (cfun_gpr_save_slot (i)))
8575 {
8576 rtx_insn *insn =
8577 emit_move_insn (gen_rtx_REG (DImode, i),
8578 gen_rtx_REG (DImode, cfun_gpr_save_slot (i)));
8579 df_set_regs_ever_live (i, true);
8580 add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (DImode, i));
8581 if (i == STACK_POINTER_REGNUM)
8582 add_reg_note (insn, REG_CFA_DEF_CFA,
8583 plus_constant (Pmode, stack_pointer_rtx,
8584 STACK_POINTER_OFFSET));
8585 RTX_FRAME_RELATED_P (insn) = 1;
8586 }
8587 }
8588 }
8589
8590
8591 /* A pass run immediately before shrink-wrapping and prologue and epilogue
8592 generation. */
8593
8594 namespace {
8595
8596 const pass_data pass_data_s390_early_mach =
8597 {
8598 RTL_PASS, /* type */
8599 "early_mach", /* name */
8600 OPTGROUP_NONE, /* optinfo_flags */
8601 TV_MACH_DEP, /* tv_id */
8602 0, /* properties_required */
8603 0, /* properties_provided */
8604 0, /* properties_destroyed */
8605 0, /* todo_flags_start */
8606 ( TODO_df_verify | TODO_df_finish ), /* todo_flags_finish */
8607 };
8608
8609 class pass_s390_early_mach : public rtl_opt_pass
8610 {
8611 public:
8612 pass_s390_early_mach (gcc::context *ctxt)
8613 : rtl_opt_pass (pass_data_s390_early_mach, ctxt)
8614 {}
8615
8616 /* opt_pass methods: */
8617 virtual unsigned int execute (function *);
8618
8619 }; // class pass_s390_early_mach
8620
8621 unsigned int
8622 pass_s390_early_mach::execute (function *fun)
8623 {
8624 rtx_insn *insn;
8625
8626 /* Try to get rid of the FPR clobbers. */
8627 s390_optimize_nonescaping_tx ();
8628
8629 /* Re-compute register info. */
8630 s390_register_info ();
8631
8632 /* If we're using a base register, ensure that it is always valid for
8633 the first non-prologue instruction. */
8634 if (fun->machine->base_reg)
8635 emit_insn_at_entry (gen_main_pool (fun->machine->base_reg));
8636
8637 /* Annotate all constant pool references to let the scheduler know
8638 they implicitly use the base register. */
8639 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8640 if (INSN_P (insn))
8641 {
8642 annotate_constant_pool_refs (&PATTERN (insn));
8643 df_insn_rescan (insn);
8644 }
8645 return 0;
8646 }
8647
8648 } // anon namespace
8649
8650 /* Expand the prologue into a bunch of separate insns. */
8651
8652 void
8653 s390_emit_prologue (void)
8654 {
8655 rtx insn, addr;
8656 rtx temp_reg;
8657 int i;
8658 int offset;
8659 int next_fpr = 0;
8660
8661 /* Choose best register to use for temp use within prologue.
8662 See below for why TPF must use the register 1. */
8663
8664 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
8665 && !crtl->is_leaf
8666 && !TARGET_TPF_PROFILING)
8667 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
8668 else
8669 temp_reg = gen_rtx_REG (Pmode, 1);
8670
8671 s390_save_gprs_to_fprs ();
8672
8673 /* Save call saved gprs. */
8674 if (cfun_frame_layout.first_save_gpr != -1)
8675 {
8676 insn = save_gprs (stack_pointer_rtx,
8677 cfun_frame_layout.gprs_offset +
8678 UNITS_PER_LONG * (cfun_frame_layout.first_save_gpr
8679 - cfun_frame_layout.first_save_gpr_slot),
8680 cfun_frame_layout.first_save_gpr,
8681 cfun_frame_layout.last_save_gpr);
8682 emit_insn (insn);
8683 }
8684
8685 /* Dummy insn to mark literal pool slot. */
8686
8687 if (cfun->machine->base_reg)
8688 emit_insn (gen_main_pool (cfun->machine->base_reg));
8689
8690 offset = cfun_frame_layout.f0_offset;
8691
8692 /* Save f0 and f2. */
8693 for (i = FPR0_REGNUM; i <= FPR0_REGNUM + 1; i++)
8694 {
8695 if (cfun_fpr_save_p (i))
8696 {
8697 save_fpr (stack_pointer_rtx, offset, i);
8698 offset += 8;
8699 }
8700 else if (!TARGET_PACKED_STACK || cfun->stdarg)
8701 offset += 8;
8702 }
8703
8704 /* Save f4 and f6. */
8705 offset = cfun_frame_layout.f4_offset;
8706 for (i = FPR4_REGNUM; i <= FPR4_REGNUM + 1; i++)
8707 {
8708 if (cfun_fpr_save_p (i))
8709 {
8710 insn = save_fpr (stack_pointer_rtx, offset, i);
8711 offset += 8;
8712
8713 /* If f4 and f6 are call clobbered they are saved due to
8714 stdargs and therefore are not frame related. */
8715 if (!call_really_used_regs[i])
8716 RTX_FRAME_RELATED_P (insn) = 1;
8717 }
8718 else if (!TARGET_PACKED_STACK || call_really_used_regs[i])
8719 offset += 8;
8720 }
8721
8722 if (TARGET_PACKED_STACK
8723 && cfun_save_high_fprs_p
8724 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
8725 {
8726 offset = (cfun_frame_layout.f8_offset
8727 + (cfun_frame_layout.high_fprs - 1) * 8);
8728
8729 for (i = FPR15_REGNUM; i >= FPR8_REGNUM && offset >= 0; i--)
8730 if (cfun_fpr_save_p (i))
8731 {
8732 insn = save_fpr (stack_pointer_rtx, offset, i);
8733
8734 RTX_FRAME_RELATED_P (insn) = 1;
8735 offset -= 8;
8736 }
8737 if (offset >= cfun_frame_layout.f8_offset)
8738 next_fpr = i;
8739 }
8740
8741 if (!TARGET_PACKED_STACK)
8742 next_fpr = cfun_save_high_fprs_p ? FPR15_REGNUM : 0;
8743
8744 if (flag_stack_usage_info)
8745 current_function_static_stack_size = cfun_frame_layout.frame_size;
8746
8747 /* Decrement stack pointer. */
8748
8749 if (cfun_frame_layout.frame_size > 0)
8750 {
8751 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
8752 rtx real_frame_off;
8753
8754 if (s390_stack_size)
8755 {
8756 HOST_WIDE_INT stack_guard;
8757
8758 if (s390_stack_guard)
8759 stack_guard = s390_stack_guard;
8760 else
8761 {
8762 /* If no value for stack guard is provided the smallest power of 2
8763 larger than the current frame size is chosen. */
8764 stack_guard = 1;
8765 while (stack_guard < cfun_frame_layout.frame_size)
8766 stack_guard <<= 1;
8767 }
8768
8769 if (cfun_frame_layout.frame_size >= s390_stack_size)
8770 {
8771 warning (0, "frame size of function %qs is %wd"
8772 " bytes exceeding user provided stack limit of "
8773 "%d bytes. "
8774 "An unconditional trap is added.",
8775 current_function_name(), cfun_frame_layout.frame_size,
8776 s390_stack_size);
8777 emit_insn (gen_trap ());
8778 }
8779 else
8780 {
8781 /* stack_guard has to be smaller than s390_stack_size.
8782 Otherwise we would emit an AND with zero which would
8783 not match the test under mask pattern. */
8784 if (stack_guard >= s390_stack_size)
8785 {
8786 warning (0, "frame size of function %qs is %wd"
8787 " bytes which is more than half the stack size. "
8788 "The dynamic check would not be reliable. "
8789 "No check emitted for this function.",
8790 current_function_name(),
8791 cfun_frame_layout.frame_size);
8792 }
8793 else
8794 {
8795 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
8796 & ~(stack_guard - 1));
8797
8798 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
8799 GEN_INT (stack_check_mask));
8800 if (TARGET_64BIT)
8801 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode,
8802 t, const0_rtx),
8803 t, const0_rtx, const0_rtx));
8804 else
8805 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode,
8806 t, const0_rtx),
8807 t, const0_rtx, const0_rtx));
8808 }
8809 }
8810 }
8811
8812 if (s390_warn_framesize > 0
8813 && cfun_frame_layout.frame_size >= s390_warn_framesize)
8814 warning (0, "frame size of %qs is %wd bytes",
8815 current_function_name (), cfun_frame_layout.frame_size);
8816
8817 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
8818 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
8819
8820 /* Save incoming stack pointer into temp reg. */
8821 if (TARGET_BACKCHAIN || next_fpr)
8822 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
8823
8824 /* Subtract frame size from stack pointer. */
8825
8826 if (DISP_IN_RANGE (INTVAL (frame_off)))
8827 {
8828 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8829 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8830 frame_off));
8831 insn = emit_insn (insn);
8832 }
8833 else
8834 {
8835 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8836 frame_off = force_const_mem (Pmode, frame_off);
8837
8838 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
8839 annotate_constant_pool_refs (&PATTERN (insn));
8840 }
8841
8842 RTX_FRAME_RELATED_P (insn) = 1;
8843 real_frame_off = GEN_INT (-cfun_frame_layout.frame_size);
8844 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8845 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8846 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8847 real_frame_off)));
8848
8849 /* Set backchain. */
8850
8851 if (TARGET_BACKCHAIN)
8852 {
8853 if (cfun_frame_layout.backchain_offset)
8854 addr = gen_rtx_MEM (Pmode,
8855 plus_constant (Pmode, stack_pointer_rtx,
8856 cfun_frame_layout.backchain_offset));
8857 else
8858 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
8859 set_mem_alias_set (addr, get_frame_alias_set ());
8860 insn = emit_insn (gen_move_insn (addr, temp_reg));
8861 }
8862
8863 /* If we support non-call exceptions (e.g. for Java),
8864 we need to make sure the backchain pointer is set up
8865 before any possibly trapping memory access. */
8866 if (TARGET_BACKCHAIN && cfun->can_throw_non_call_exceptions)
8867 {
8868 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
8869 emit_clobber (addr);
8870 }
8871 }
8872
8873 /* Save fprs 8 - 15 (64 bit ABI). */
8874
8875 if (cfun_save_high_fprs_p && next_fpr)
8876 {
8877 /* If the stack might be accessed through a different register
8878 we have to make sure that the stack pointer decrement is not
8879 moved below the use of the stack slots. */
8880 s390_emit_stack_tie ();
8881
8882 insn = emit_insn (gen_add2_insn (temp_reg,
8883 GEN_INT (cfun_frame_layout.f8_offset)));
8884
8885 offset = 0;
8886
8887 for (i = FPR8_REGNUM; i <= next_fpr; i++)
8888 if (cfun_fpr_save_p (i))
8889 {
8890 rtx addr = plus_constant (Pmode, stack_pointer_rtx,
8891 cfun_frame_layout.frame_size
8892 + cfun_frame_layout.f8_offset
8893 + offset);
8894
8895 insn = save_fpr (temp_reg, offset, i);
8896 offset += 8;
8897 RTX_FRAME_RELATED_P (insn) = 1;
8898 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8899 gen_rtx_SET (VOIDmode,
8900 gen_rtx_MEM (DFmode, addr),
8901 gen_rtx_REG (DFmode, i)));
8902 }
8903 }
8904
8905 /* Set frame pointer, if needed. */
8906
8907 if (frame_pointer_needed)
8908 {
8909 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8910 RTX_FRAME_RELATED_P (insn) = 1;
8911 }
8912
8913 /* Set up got pointer, if needed. */
8914
8915 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
8916 {
8917 rtx_insn *insns = s390_load_got ();
8918
8919 for (rtx_insn *insn = insns; insn; insn = NEXT_INSN (insn))
8920 annotate_constant_pool_refs (&PATTERN (insn));
8921
8922 emit_insn (insns);
8923 }
8924
8925 if (TARGET_TPF_PROFILING)
8926 {
8927 /* Generate a BAS instruction to serve as a function
8928 entry intercept to facilitate the use of tracing
8929 algorithms located at the branch target. */
8930 emit_insn (gen_prologue_tpf ());
8931
8932 /* Emit a blockage here so that all code
8933 lies between the profiling mechanisms. */
8934 emit_insn (gen_blockage ());
8935 }
8936 }
8937
8938 /* Expand the epilogue into a bunch of separate insns. */
8939
8940 void
8941 s390_emit_epilogue (bool sibcall)
8942 {
8943 rtx frame_pointer, return_reg, cfa_restores = NULL_RTX;
8944 int area_bottom, area_top, offset = 0;
8945 int next_offset;
8946 rtvec p;
8947 int i;
8948
8949 if (TARGET_TPF_PROFILING)
8950 {
8951
8952 /* Generate a BAS instruction to serve as a function
8953 entry intercept to facilitate the use of tracing
8954 algorithms located at the branch target. */
8955
8956 /* Emit a blockage here so that all code
8957 lies between the profiling mechanisms. */
8958 emit_insn (gen_blockage ());
8959
8960 emit_insn (gen_epilogue_tpf ());
8961 }
8962
8963 /* Check whether to use frame or stack pointer for restore. */
8964
8965 frame_pointer = (frame_pointer_needed
8966 ? hard_frame_pointer_rtx : stack_pointer_rtx);
8967
8968 s390_frame_area (&area_bottom, &area_top);
8969
8970 /* Check whether we can access the register save area.
8971 If not, increment the frame pointer as required. */
8972
8973 if (area_top <= area_bottom)
8974 {
8975 /* Nothing to restore. */
8976 }
8977 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
8978 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
8979 {
8980 /* Area is in range. */
8981 offset = cfun_frame_layout.frame_size;
8982 }
8983 else
8984 {
8985 rtx insn, frame_off, cfa;
8986
8987 offset = area_bottom < 0 ? -area_bottom : 0;
8988 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
8989
8990 cfa = gen_rtx_SET (VOIDmode, frame_pointer,
8991 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8992 if (DISP_IN_RANGE (INTVAL (frame_off)))
8993 {
8994 insn = gen_rtx_SET (VOIDmode, frame_pointer,
8995 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8996 insn = emit_insn (insn);
8997 }
8998 else
8999 {
9000 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
9001 frame_off = force_const_mem (Pmode, frame_off);
9002
9003 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
9004 annotate_constant_pool_refs (&PATTERN (insn));
9005 }
9006 add_reg_note (insn, REG_CFA_ADJUST_CFA, cfa);
9007 RTX_FRAME_RELATED_P (insn) = 1;
9008 }
9009
9010 /* Restore call saved fprs. */
9011
9012 if (TARGET_64BIT)
9013 {
9014 if (cfun_save_high_fprs_p)
9015 {
9016 next_offset = cfun_frame_layout.f8_offset;
9017 for (i = FPR8_REGNUM; i <= FPR15_REGNUM; i++)
9018 {
9019 if (cfun_fpr_save_p (i))
9020 {
9021 restore_fpr (frame_pointer,
9022 offset + next_offset, i);
9023 cfa_restores
9024 = alloc_reg_note (REG_CFA_RESTORE,
9025 gen_rtx_REG (DFmode, i), cfa_restores);
9026 next_offset += 8;
9027 }
9028 }
9029 }
9030
9031 }
9032 else
9033 {
9034 next_offset = cfun_frame_layout.f4_offset;
9035 /* f4, f6 */
9036 for (i = FPR4_REGNUM; i <= FPR4_REGNUM + 1; i++)
9037 {
9038 if (cfun_fpr_save_p (i))
9039 {
9040 restore_fpr (frame_pointer,
9041 offset + next_offset, i);
9042 cfa_restores
9043 = alloc_reg_note (REG_CFA_RESTORE,
9044 gen_rtx_REG (DFmode, i), cfa_restores);
9045 next_offset += 8;
9046 }
9047 else if (!TARGET_PACKED_STACK)
9048 next_offset += 8;
9049 }
9050
9051 }
9052
9053 /* Return register. */
9054
9055 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
9056
9057 /* Restore call saved gprs. */
9058
9059 if (cfun_frame_layout.first_restore_gpr != -1)
9060 {
9061 rtx insn, addr;
9062 int i;
9063
9064 /* Check for global register and save them
9065 to stack location from where they get restored. */
9066
9067 for (i = cfun_frame_layout.first_restore_gpr;
9068 i <= cfun_frame_layout.last_restore_gpr;
9069 i++)
9070 {
9071 if (global_not_special_regno_p (i))
9072 {
9073 addr = plus_constant (Pmode, frame_pointer,
9074 offset + cfun_frame_layout.gprs_offset
9075 + (i - cfun_frame_layout.first_save_gpr_slot)
9076 * UNITS_PER_LONG);
9077 addr = gen_rtx_MEM (Pmode, addr);
9078 set_mem_alias_set (addr, get_frame_alias_set ());
9079 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
9080 }
9081 else
9082 cfa_restores
9083 = alloc_reg_note (REG_CFA_RESTORE,
9084 gen_rtx_REG (Pmode, i), cfa_restores);
9085 }
9086
9087 if (! sibcall)
9088 {
9089 /* Fetch return address from stack before load multiple,
9090 this will do good for scheduling.
9091
9092 Only do this if we already decided that r14 needs to be
9093 saved to a stack slot. (And not just because r14 happens to
9094 be in between two GPRs which need saving.) Otherwise it
9095 would be difficult to take that decision back in
9096 s390_optimize_prologue. */
9097 if (cfun_gpr_save_slot (RETURN_REGNUM) == -1)
9098 {
9099 int return_regnum = find_unused_clobbered_reg();
9100 if (!return_regnum)
9101 return_regnum = 4;
9102 return_reg = gen_rtx_REG (Pmode, return_regnum);
9103
9104 addr = plus_constant (Pmode, frame_pointer,
9105 offset + cfun_frame_layout.gprs_offset
9106 + (RETURN_REGNUM
9107 - cfun_frame_layout.first_save_gpr_slot)
9108 * UNITS_PER_LONG);
9109 addr = gen_rtx_MEM (Pmode, addr);
9110 set_mem_alias_set (addr, get_frame_alias_set ());
9111 emit_move_insn (return_reg, addr);
9112
9113 /* Once we did that optimization we have to make sure
9114 s390_optimize_prologue does not try to remove the
9115 store of r14 since we will not be able to find the
9116 load issued here. */
9117 cfun_frame_layout.save_return_addr_p = true;
9118 }
9119 }
9120
9121 insn = restore_gprs (frame_pointer,
9122 offset + cfun_frame_layout.gprs_offset
9123 + (cfun_frame_layout.first_restore_gpr
9124 - cfun_frame_layout.first_save_gpr_slot)
9125 * UNITS_PER_LONG,
9126 cfun_frame_layout.first_restore_gpr,
9127 cfun_frame_layout.last_restore_gpr);
9128 insn = emit_insn (insn);
9129 REG_NOTES (insn) = cfa_restores;
9130 add_reg_note (insn, REG_CFA_DEF_CFA,
9131 plus_constant (Pmode, stack_pointer_rtx,
9132 STACK_POINTER_OFFSET));
9133 RTX_FRAME_RELATED_P (insn) = 1;
9134 }
9135
9136 s390_restore_gprs_from_fprs ();
9137
9138 if (! sibcall)
9139 {
9140
9141 /* Return to caller. */
9142
9143 p = rtvec_alloc (2);
9144
9145 RTVEC_ELT (p, 0) = ret_rtx;
9146 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
9147 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
9148 }
9149 }
9150
9151 /* Implement TARGET_SET_UP_BY_PROLOGUE. */
9152
9153 static void
9154 s300_set_up_by_prologue (hard_reg_set_container *regs)
9155 {
9156 if (cfun->machine->base_reg
9157 && !call_really_used_regs[REGNO (cfun->machine->base_reg)])
9158 SET_HARD_REG_BIT (regs->set, REGNO (cfun->machine->base_reg));
9159 }
9160
9161 /* Return true if the function can use simple_return to return outside
9162 of a shrink-wrapped region. At present shrink-wrapping is supported
9163 in all cases. */
9164
9165 bool
9166 s390_can_use_simple_return_insn (void)
9167 {
9168 return true;
9169 }
9170
9171 /* Return true if the epilogue is guaranteed to contain only a return
9172 instruction and if a direct return can therefore be used instead.
9173 One of the main advantages of using direct return instructions
9174 is that we can then use conditional returns. */
9175
9176 bool
9177 s390_can_use_return_insn (void)
9178 {
9179 int i;
9180
9181 if (!reload_completed)
9182 return false;
9183
9184 if (crtl->profile)
9185 return false;
9186
9187 if (TARGET_TPF_PROFILING)
9188 return false;
9189
9190 for (i = 0; i < 16; i++)
9191 if (cfun_gpr_save_slot (i))
9192 return false;
9193
9194 /* For 31 bit this is not covered by the frame_size check below
9195 since f4, f6 are saved in the register save area without needing
9196 additional stack space. */
9197 if (!TARGET_64BIT
9198 && (cfun_fpr_save_p (FPR4_REGNUM) || cfun_fpr_save_p (FPR6_REGNUM)))
9199 return false;
9200
9201 if (cfun->machine->base_reg
9202 && !call_really_used_regs[REGNO (cfun->machine->base_reg)])
9203 return false;
9204
9205 return cfun_frame_layout.frame_size == 0;
9206 }
9207
9208 /* Return the size in bytes of a function argument of
9209 type TYPE and/or mode MODE. At least one of TYPE or
9210 MODE must be specified. */
9211
9212 static int
9213 s390_function_arg_size (enum machine_mode mode, const_tree type)
9214 {
9215 if (type)
9216 return int_size_in_bytes (type);
9217
9218 /* No type info available for some library calls ... */
9219 if (mode != BLKmode)
9220 return GET_MODE_SIZE (mode);
9221
9222 /* If we have neither type nor mode, abort */
9223 gcc_unreachable ();
9224 }
9225
9226 /* Return true if a function argument of type TYPE and mode MODE
9227 is to be passed in a floating-point register, if available. */
9228
9229 static bool
9230 s390_function_arg_float (enum machine_mode mode, const_tree type)
9231 {
9232 int size = s390_function_arg_size (mode, type);
9233 if (size > 8)
9234 return false;
9235
9236 /* Soft-float changes the ABI: no floating-point registers are used. */
9237 if (TARGET_SOFT_FLOAT)
9238 return false;
9239
9240 /* No type info available for some library calls ... */
9241 if (!type)
9242 return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode;
9243
9244 /* The ABI says that record types with a single member are treated
9245 just like that member would be. */
9246 while (TREE_CODE (type) == RECORD_TYPE)
9247 {
9248 tree field, single = NULL_TREE;
9249
9250 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
9251 {
9252 if (TREE_CODE (field) != FIELD_DECL)
9253 continue;
9254
9255 if (single == NULL_TREE)
9256 single = TREE_TYPE (field);
9257 else
9258 return false;
9259 }
9260
9261 if (single == NULL_TREE)
9262 return false;
9263 else
9264 type = single;
9265 }
9266
9267 return TREE_CODE (type) == REAL_TYPE;
9268 }
9269
9270 /* Return true if a function argument of type TYPE and mode MODE
9271 is to be passed in an integer register, or a pair of integer
9272 registers, if available. */
9273
9274 static bool
9275 s390_function_arg_integer (enum machine_mode mode, const_tree type)
9276 {
9277 int size = s390_function_arg_size (mode, type);
9278 if (size > 8)
9279 return false;
9280
9281 /* No type info available for some library calls ... */
9282 if (!type)
9283 return GET_MODE_CLASS (mode) == MODE_INT
9284 || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode));
9285
9286 /* We accept small integral (and similar) types. */
9287 if (INTEGRAL_TYPE_P (type)
9288 || POINTER_TYPE_P (type)
9289 || TREE_CODE (type) == NULLPTR_TYPE
9290 || TREE_CODE (type) == OFFSET_TYPE
9291 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
9292 return true;
9293
9294 /* We also accept structs of size 1, 2, 4, 8 that are not
9295 passed in floating-point registers. */
9296 if (AGGREGATE_TYPE_P (type)
9297 && exact_log2 (size) >= 0
9298 && !s390_function_arg_float (mode, type))
9299 return true;
9300
9301 return false;
9302 }
9303
9304 /* Return 1 if a function argument of type TYPE and mode MODE
9305 is to be passed by reference. The ABI specifies that only
9306 structures of size 1, 2, 4, or 8 bytes are passed by value,
9307 all other structures (and complex numbers) are passed by
9308 reference. */
9309
9310 static bool
9311 s390_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED,
9312 enum machine_mode mode, const_tree type,
9313 bool named ATTRIBUTE_UNUSED)
9314 {
9315 int size = s390_function_arg_size (mode, type);
9316 if (size > 8)
9317 return true;
9318
9319 if (type)
9320 {
9321 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
9322 return 1;
9323
9324 if (TREE_CODE (type) == COMPLEX_TYPE
9325 || TREE_CODE (type) == VECTOR_TYPE)
9326 return 1;
9327 }
9328
9329 return 0;
9330 }
9331
9332 /* Update the data in CUM to advance over an argument of mode MODE and
9333 data type TYPE. (TYPE is null for libcalls where that information
9334 may not be available.). The boolean NAMED specifies whether the
9335 argument is a named argument (as opposed to an unnamed argument
9336 matching an ellipsis). */
9337
9338 static void
9339 s390_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
9340 const_tree type, bool named ATTRIBUTE_UNUSED)
9341 {
9342 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
9343
9344 if (s390_function_arg_float (mode, type))
9345 {
9346 cum->fprs += 1;
9347 }
9348 else if (s390_function_arg_integer (mode, type))
9349 {
9350 int size = s390_function_arg_size (mode, type);
9351 cum->gprs += ((size + UNITS_PER_LONG - 1) / UNITS_PER_LONG);
9352 }
9353 else
9354 gcc_unreachable ();
9355 }
9356
9357 /* Define where to put the arguments to a function.
9358 Value is zero to push the argument on the stack,
9359 or a hard register in which to store the argument.
9360
9361 MODE is the argument's machine mode.
9362 TYPE is the data type of the argument (as a tree).
9363 This is null for libcalls where that information may
9364 not be available.
9365 CUM is a variable of type CUMULATIVE_ARGS which gives info about
9366 the preceding args and about the function being called.
9367 NAMED is nonzero if this argument is a named parameter
9368 (otherwise it is an extra parameter matching an ellipsis).
9369
9370 On S/390, we use general purpose registers 2 through 6 to
9371 pass integer, pointer, and certain structure arguments, and
9372 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
9373 to pass floating point arguments. All remaining arguments
9374 are pushed to the stack. */
9375
9376 static rtx
9377 s390_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
9378 const_tree type, bool named ATTRIBUTE_UNUSED)
9379 {
9380 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
9381
9382 if (s390_function_arg_float (mode, type))
9383 {
9384 if (cum->fprs + 1 > FP_ARG_NUM_REG)
9385 return 0;
9386 else
9387 return gen_rtx_REG (mode, cum->fprs + 16);
9388 }
9389 else if (s390_function_arg_integer (mode, type))
9390 {
9391 int size = s390_function_arg_size (mode, type);
9392 int n_gprs = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
9393
9394 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
9395 return 0;
9396 else if (n_gprs == 1 || UNITS_PER_WORD == UNITS_PER_LONG)
9397 return gen_rtx_REG (mode, cum->gprs + 2);
9398 else if (n_gprs == 2)
9399 {
9400 rtvec p = rtvec_alloc (2);
9401
9402 RTVEC_ELT (p, 0)
9403 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 2),
9404 const0_rtx);
9405 RTVEC_ELT (p, 1)
9406 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 3),
9407 GEN_INT (4));
9408
9409 return gen_rtx_PARALLEL (mode, p);
9410 }
9411 }
9412
9413 /* After the real arguments, expand_call calls us once again
9414 with a void_type_node type. Whatever we return here is
9415 passed as operand 2 to the call expanders.
9416
9417 We don't need this feature ... */
9418 else if (type == void_type_node)
9419 return const0_rtx;
9420
9421 gcc_unreachable ();
9422 }
9423
9424 /* Return true if return values of type TYPE should be returned
9425 in a memory buffer whose address is passed by the caller as
9426 hidden first argument. */
9427
9428 static bool
9429 s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED)
9430 {
9431 /* We accept small integral (and similar) types. */
9432 if (INTEGRAL_TYPE_P (type)
9433 || POINTER_TYPE_P (type)
9434 || TREE_CODE (type) == OFFSET_TYPE
9435 || TREE_CODE (type) == REAL_TYPE)
9436 return int_size_in_bytes (type) > 8;
9437
9438 /* Aggregates and similar constructs are always returned
9439 in memory. */
9440 if (AGGREGATE_TYPE_P (type)
9441 || TREE_CODE (type) == COMPLEX_TYPE
9442 || TREE_CODE (type) == VECTOR_TYPE)
9443 return true;
9444
9445 /* ??? We get called on all sorts of random stuff from
9446 aggregate_value_p. We can't abort, but it's not clear
9447 what's safe to return. Pretend it's a struct I guess. */
9448 return true;
9449 }
9450
9451 /* Function arguments and return values are promoted to word size. */
9452
9453 static enum machine_mode
9454 s390_promote_function_mode (const_tree type, enum machine_mode mode,
9455 int *punsignedp,
9456 const_tree fntype ATTRIBUTE_UNUSED,
9457 int for_return ATTRIBUTE_UNUSED)
9458 {
9459 if (INTEGRAL_MODE_P (mode)
9460 && GET_MODE_SIZE (mode) < UNITS_PER_LONG)
9461 {
9462 if (type != NULL_TREE && POINTER_TYPE_P (type))
9463 *punsignedp = POINTERS_EXTEND_UNSIGNED;
9464 return Pmode;
9465 }
9466
9467 return mode;
9468 }
9469
9470 /* Define where to return a (scalar) value of type RET_TYPE.
9471 If RET_TYPE is null, define where to return a (scalar)
9472 value of mode MODE from a libcall. */
9473
9474 static rtx
9475 s390_function_and_libcall_value (enum machine_mode mode,
9476 const_tree ret_type,
9477 const_tree fntype_or_decl,
9478 bool outgoing ATTRIBUTE_UNUSED)
9479 {
9480 /* For normal functions perform the promotion as
9481 promote_function_mode would do. */
9482 if (ret_type)
9483 {
9484 int unsignedp = TYPE_UNSIGNED (ret_type);
9485 mode = promote_function_mode (ret_type, mode, &unsignedp,
9486 fntype_or_decl, 1);
9487 }
9488
9489 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode));
9490 gcc_assert (GET_MODE_SIZE (mode) <= 8);
9491
9492 if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
9493 return gen_rtx_REG (mode, 16);
9494 else if (GET_MODE_SIZE (mode) <= UNITS_PER_LONG
9495 || UNITS_PER_LONG == UNITS_PER_WORD)
9496 return gen_rtx_REG (mode, 2);
9497 else if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_LONG)
9498 {
9499 /* This case is triggered when returning a 64 bit value with
9500 -m31 -mzarch. Although the value would fit into a single
9501 register it has to be forced into a 32 bit register pair in
9502 order to match the ABI. */
9503 rtvec p = rtvec_alloc (2);
9504
9505 RTVEC_ELT (p, 0)
9506 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 2), const0_rtx);
9507 RTVEC_ELT (p, 1)
9508 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 3), GEN_INT (4));
9509
9510 return gen_rtx_PARALLEL (mode, p);
9511 }
9512
9513 gcc_unreachable ();
9514 }
9515
9516 /* Define where to return a scalar return value of type RET_TYPE. */
9517
9518 static rtx
9519 s390_function_value (const_tree ret_type, const_tree fn_decl_or_type,
9520 bool outgoing)
9521 {
9522 return s390_function_and_libcall_value (TYPE_MODE (ret_type), ret_type,
9523 fn_decl_or_type, outgoing);
9524 }
9525
9526 /* Define where to return a scalar libcall return value of mode
9527 MODE. */
9528
9529 static rtx
9530 s390_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
9531 {
9532 return s390_function_and_libcall_value (mode, NULL_TREE,
9533 NULL_TREE, true);
9534 }
9535
9536
9537 /* Create and return the va_list datatype.
9538
9539 On S/390, va_list is an array type equivalent to
9540
9541 typedef struct __va_list_tag
9542 {
9543 long __gpr;
9544 long __fpr;
9545 void *__overflow_arg_area;
9546 void *__reg_save_area;
9547 } va_list[1];
9548
9549 where __gpr and __fpr hold the number of general purpose
9550 or floating point arguments used up to now, respectively,
9551 __overflow_arg_area points to the stack location of the
9552 next argument passed on the stack, and __reg_save_area
9553 always points to the start of the register area in the
9554 call frame of the current function. The function prologue
9555 saves all registers used for argument passing into this
9556 area if the function uses variable arguments. */
9557
9558 static tree
9559 s390_build_builtin_va_list (void)
9560 {
9561 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
9562
9563 record = lang_hooks.types.make_type (RECORD_TYPE);
9564
9565 type_decl =
9566 build_decl (BUILTINS_LOCATION,
9567 TYPE_DECL, get_identifier ("__va_list_tag"), record);
9568
9569 f_gpr = build_decl (BUILTINS_LOCATION,
9570 FIELD_DECL, get_identifier ("__gpr"),
9571 long_integer_type_node);
9572 f_fpr = build_decl (BUILTINS_LOCATION,
9573 FIELD_DECL, get_identifier ("__fpr"),
9574 long_integer_type_node);
9575 f_ovf = build_decl (BUILTINS_LOCATION,
9576 FIELD_DECL, get_identifier ("__overflow_arg_area"),
9577 ptr_type_node);
9578 f_sav = build_decl (BUILTINS_LOCATION,
9579 FIELD_DECL, get_identifier ("__reg_save_area"),
9580 ptr_type_node);
9581
9582 va_list_gpr_counter_field = f_gpr;
9583 va_list_fpr_counter_field = f_fpr;
9584
9585 DECL_FIELD_CONTEXT (f_gpr) = record;
9586 DECL_FIELD_CONTEXT (f_fpr) = record;
9587 DECL_FIELD_CONTEXT (f_ovf) = record;
9588 DECL_FIELD_CONTEXT (f_sav) = record;
9589
9590 TYPE_STUB_DECL (record) = type_decl;
9591 TYPE_NAME (record) = type_decl;
9592 TYPE_FIELDS (record) = f_gpr;
9593 DECL_CHAIN (f_gpr) = f_fpr;
9594 DECL_CHAIN (f_fpr) = f_ovf;
9595 DECL_CHAIN (f_ovf) = f_sav;
9596
9597 layout_type (record);
9598
9599 /* The correct type is an array type of one element. */
9600 return build_array_type (record, build_index_type (size_zero_node));
9601 }
9602
9603 /* Implement va_start by filling the va_list structure VALIST.
9604 STDARG_P is always true, and ignored.
9605 NEXTARG points to the first anonymous stack argument.
9606
9607 The following global variables are used to initialize
9608 the va_list structure:
9609
9610 crtl->args.info:
9611 holds number of gprs and fprs used for named arguments.
9612 crtl->args.arg_offset_rtx:
9613 holds the offset of the first anonymous stack argument
9614 (relative to the virtual arg pointer). */
9615
9616 static void
9617 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
9618 {
9619 HOST_WIDE_INT n_gpr, n_fpr;
9620 int off;
9621 tree f_gpr, f_fpr, f_ovf, f_sav;
9622 tree gpr, fpr, ovf, sav, t;
9623
9624 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
9625 f_fpr = DECL_CHAIN (f_gpr);
9626 f_ovf = DECL_CHAIN (f_fpr);
9627 f_sav = DECL_CHAIN (f_ovf);
9628
9629 valist = build_simple_mem_ref (valist);
9630 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9631 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
9632 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
9633 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
9634
9635 /* Count number of gp and fp argument registers used. */
9636
9637 n_gpr = crtl->args.info.gprs;
9638 n_fpr = crtl->args.info.fprs;
9639
9640 if (cfun->va_list_gpr_size)
9641 {
9642 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
9643 build_int_cst (NULL_TREE, n_gpr));
9644 TREE_SIDE_EFFECTS (t) = 1;
9645 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9646 }
9647
9648 if (cfun->va_list_fpr_size)
9649 {
9650 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
9651 build_int_cst (NULL_TREE, n_fpr));
9652 TREE_SIDE_EFFECTS (t) = 1;
9653 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9654 }
9655
9656 /* Find the overflow area. */
9657 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
9658 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
9659 {
9660 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
9661
9662 off = INTVAL (crtl->args.arg_offset_rtx);
9663 off = off < 0 ? 0 : off;
9664 if (TARGET_DEBUG_ARG)
9665 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
9666 (int)n_gpr, (int)n_fpr, off);
9667
9668 t = fold_build_pointer_plus_hwi (t, off);
9669
9670 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
9671 TREE_SIDE_EFFECTS (t) = 1;
9672 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9673 }
9674
9675 /* Find the register save area. */
9676 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
9677 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
9678 {
9679 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
9680 t = fold_build_pointer_plus_hwi (t, -RETURN_REGNUM * UNITS_PER_LONG);
9681
9682 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
9683 TREE_SIDE_EFFECTS (t) = 1;
9684 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9685 }
9686 }
9687
9688 /* Implement va_arg by updating the va_list structure
9689 VALIST as required to retrieve an argument of type
9690 TYPE, and returning that argument.
9691
9692 Generates code equivalent to:
9693
9694 if (integral value) {
9695 if (size <= 4 && args.gpr < 5 ||
9696 size > 4 && args.gpr < 4 )
9697 ret = args.reg_save_area[args.gpr+8]
9698 else
9699 ret = *args.overflow_arg_area++;
9700 } else if (float value) {
9701 if (args.fgpr < 2)
9702 ret = args.reg_save_area[args.fpr+64]
9703 else
9704 ret = *args.overflow_arg_area++;
9705 } else if (aggregate value) {
9706 if (args.gpr < 5)
9707 ret = *args.reg_save_area[args.gpr]
9708 else
9709 ret = **args.overflow_arg_area++;
9710 } */
9711
9712 static tree
9713 s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
9714 gimple_seq *post_p ATTRIBUTE_UNUSED)
9715 {
9716 tree f_gpr, f_fpr, f_ovf, f_sav;
9717 tree gpr, fpr, ovf, sav, reg, t, u;
9718 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
9719 tree lab_false, lab_over, addr;
9720
9721 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
9722 f_fpr = DECL_CHAIN (f_gpr);
9723 f_ovf = DECL_CHAIN (f_fpr);
9724 f_sav = DECL_CHAIN (f_ovf);
9725
9726 valist = build_va_arg_indirect_ref (valist);
9727 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9728 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
9729 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
9730
9731 /* The tree for args* cannot be shared between gpr/fpr and ovf since
9732 both appear on a lhs. */
9733 valist = unshare_expr (valist);
9734 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
9735
9736 size = int_size_in_bytes (type);
9737
9738 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
9739 {
9740 if (TARGET_DEBUG_ARG)
9741 {
9742 fprintf (stderr, "va_arg: aggregate type");
9743 debug_tree (type);
9744 }
9745
9746 /* Aggregates are passed by reference. */
9747 indirect_p = 1;
9748 reg = gpr;
9749 n_reg = 1;
9750
9751 /* kernel stack layout on 31 bit: It is assumed here that no padding
9752 will be added by s390_frame_info because for va_args always an even
9753 number of gprs has to be saved r15-r2 = 14 regs. */
9754 sav_ofs = 2 * UNITS_PER_LONG;
9755 sav_scale = UNITS_PER_LONG;
9756 size = UNITS_PER_LONG;
9757 max_reg = GP_ARG_NUM_REG - n_reg;
9758 }
9759 else if (s390_function_arg_float (TYPE_MODE (type), type))
9760 {
9761 if (TARGET_DEBUG_ARG)
9762 {
9763 fprintf (stderr, "va_arg: float type");
9764 debug_tree (type);
9765 }
9766
9767 /* FP args go in FP registers, if present. */
9768 indirect_p = 0;
9769 reg = fpr;
9770 n_reg = 1;
9771 sav_ofs = 16 * UNITS_PER_LONG;
9772 sav_scale = 8;
9773 max_reg = FP_ARG_NUM_REG - n_reg;
9774 }
9775 else
9776 {
9777 if (TARGET_DEBUG_ARG)
9778 {
9779 fprintf (stderr, "va_arg: other type");
9780 debug_tree (type);
9781 }
9782
9783 /* Otherwise into GP registers. */
9784 indirect_p = 0;
9785 reg = gpr;
9786 n_reg = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
9787
9788 /* kernel stack layout on 31 bit: It is assumed here that no padding
9789 will be added by s390_frame_info because for va_args always an even
9790 number of gprs has to be saved r15-r2 = 14 regs. */
9791 sav_ofs = 2 * UNITS_PER_LONG;
9792
9793 if (size < UNITS_PER_LONG)
9794 sav_ofs += UNITS_PER_LONG - size;
9795
9796 sav_scale = UNITS_PER_LONG;
9797 max_reg = GP_ARG_NUM_REG - n_reg;
9798 }
9799
9800 /* Pull the value out of the saved registers ... */
9801
9802 lab_false = create_artificial_label (UNKNOWN_LOCATION);
9803 lab_over = create_artificial_label (UNKNOWN_LOCATION);
9804 addr = create_tmp_var (ptr_type_node, "addr");
9805
9806 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
9807 t = build2 (GT_EXPR, boolean_type_node, reg, t);
9808 u = build1 (GOTO_EXPR, void_type_node, lab_false);
9809 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
9810 gimplify_and_add (t, pre_p);
9811
9812 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
9813 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
9814 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
9815 t = fold_build_pointer_plus (t, u);
9816
9817 gimplify_assign (addr, t, pre_p);
9818
9819 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
9820
9821 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
9822
9823
9824 /* ... Otherwise out of the overflow area. */
9825
9826 t = ovf;
9827 if (size < UNITS_PER_LONG)
9828 t = fold_build_pointer_plus_hwi (t, UNITS_PER_LONG - size);
9829
9830 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
9831
9832 gimplify_assign (addr, t, pre_p);
9833
9834 t = fold_build_pointer_plus_hwi (t, size);
9835 gimplify_assign (ovf, t, pre_p);
9836
9837 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
9838
9839
9840 /* Increment register save count. */
9841
9842 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
9843 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
9844 gimplify_and_add (u, pre_p);
9845
9846 if (indirect_p)
9847 {
9848 t = build_pointer_type_for_mode (build_pointer_type (type),
9849 ptr_mode, true);
9850 addr = fold_convert (t, addr);
9851 addr = build_va_arg_indirect_ref (addr);
9852 }
9853 else
9854 {
9855 t = build_pointer_type_for_mode (type, ptr_mode, true);
9856 addr = fold_convert (t, addr);
9857 }
9858
9859 return build_va_arg_indirect_ref (addr);
9860 }
9861
9862 /* Emit rtl for the tbegin or tbegin_retry (RETRY != NULL_RTX)
9863 expanders.
9864 DEST - Register location where CC will be stored.
9865 TDB - Pointer to a 256 byte area where to store the transaction.
9866 diagnostic block. NULL if TDB is not needed.
9867 RETRY - Retry count value. If non-NULL a retry loop for CC2
9868 is emitted
9869 CLOBBER_FPRS_P - If true clobbers for all FPRs are emitted as part
9870 of the tbegin instruction pattern. */
9871
9872 void
9873 s390_expand_tbegin (rtx dest, rtx tdb, rtx retry, bool clobber_fprs_p)
9874 {
9875 rtx retry_plus_two = gen_reg_rtx (SImode);
9876 rtx retry_reg = gen_reg_rtx (SImode);
9877 rtx_code_label *retry_label = NULL;
9878
9879 if (retry != NULL_RTX)
9880 {
9881 emit_move_insn (retry_reg, retry);
9882 emit_insn (gen_addsi3 (retry_plus_two, retry_reg, const2_rtx));
9883 emit_insn (gen_addsi3 (retry_reg, retry_reg, const1_rtx));
9884 retry_label = gen_label_rtx ();
9885 emit_label (retry_label);
9886 }
9887
9888 if (clobber_fprs_p)
9889 emit_insn (gen_tbegin_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK), tdb));
9890 else
9891 emit_insn (gen_tbegin_nofloat_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK),
9892 tdb));
9893
9894 emit_move_insn (dest, gen_rtx_UNSPEC (SImode,
9895 gen_rtvec (1, gen_rtx_REG (CCRAWmode,
9896 CC_REGNUM)),
9897 UNSPEC_CC_TO_INT));
9898 if (retry != NULL_RTX)
9899 {
9900 const int CC0 = 1 << 3;
9901 const int CC1 = 1 << 2;
9902 const int CC3 = 1 << 0;
9903 rtx jump;
9904 rtx count = gen_reg_rtx (SImode);
9905 rtx_code_label *leave_label = gen_label_rtx ();
9906
9907 /* Exit for success and permanent failures. */
9908 jump = s390_emit_jump (leave_label,
9909 gen_rtx_EQ (VOIDmode,
9910 gen_rtx_REG (CCRAWmode, CC_REGNUM),
9911 gen_rtx_CONST_INT (VOIDmode, CC0 | CC1 | CC3)));
9912 LABEL_NUSES (leave_label) = 1;
9913
9914 /* CC2 - transient failure. Perform retry with ppa. */
9915 emit_move_insn (count, retry_plus_two);
9916 emit_insn (gen_subsi3 (count, count, retry_reg));
9917 emit_insn (gen_tx_assist (count));
9918 jump = emit_jump_insn (gen_doloop_si64 (retry_label,
9919 retry_reg,
9920 retry_reg));
9921 JUMP_LABEL (jump) = retry_label;
9922 LABEL_NUSES (retry_label) = 1;
9923 emit_label (leave_label);
9924 }
9925 }
9926
9927 /* Builtins. */
9928
9929 enum s390_builtin
9930 {
9931 S390_BUILTIN_TBEGIN,
9932 S390_BUILTIN_TBEGIN_NOFLOAT,
9933 S390_BUILTIN_TBEGIN_RETRY,
9934 S390_BUILTIN_TBEGIN_RETRY_NOFLOAT,
9935 S390_BUILTIN_TBEGINC,
9936 S390_BUILTIN_TEND,
9937 S390_BUILTIN_TABORT,
9938 S390_BUILTIN_NON_TX_STORE,
9939 S390_BUILTIN_TX_NESTING_DEPTH,
9940 S390_BUILTIN_TX_ASSIST,
9941
9942 S390_BUILTIN_max
9943 };
9944
9945 static enum insn_code const code_for_builtin[S390_BUILTIN_max] = {
9946 CODE_FOR_tbegin,
9947 CODE_FOR_tbegin_nofloat,
9948 CODE_FOR_tbegin_retry,
9949 CODE_FOR_tbegin_retry_nofloat,
9950 CODE_FOR_tbeginc,
9951 CODE_FOR_tend,
9952 CODE_FOR_tabort,
9953 CODE_FOR_ntstg,
9954 CODE_FOR_etnd,
9955 CODE_FOR_tx_assist
9956 };
9957
9958 static void
9959 s390_init_builtins (void)
9960 {
9961 tree ftype, uint64_type;
9962 tree returns_twice_attr = tree_cons (get_identifier ("returns_twice"),
9963 NULL, NULL);
9964 tree noreturn_attr = tree_cons (get_identifier ("noreturn"), NULL, NULL);
9965
9966 /* void foo (void) */
9967 ftype = build_function_type_list (void_type_node, NULL_TREE);
9968 add_builtin_function ("__builtin_tbeginc", ftype, S390_BUILTIN_TBEGINC,
9969 BUILT_IN_MD, NULL, NULL_TREE);
9970
9971 /* void foo (int) */
9972 ftype = build_function_type_list (void_type_node, integer_type_node,
9973 NULL_TREE);
9974 add_builtin_function ("__builtin_tabort", ftype,
9975 S390_BUILTIN_TABORT, BUILT_IN_MD, NULL, noreturn_attr);
9976 add_builtin_function ("__builtin_tx_assist", ftype,
9977 S390_BUILTIN_TX_ASSIST, BUILT_IN_MD, NULL, NULL_TREE);
9978
9979 /* int foo (void *) */
9980 ftype = build_function_type_list (integer_type_node, ptr_type_node, NULL_TREE);
9981 add_builtin_function ("__builtin_tbegin", ftype, S390_BUILTIN_TBEGIN,
9982 BUILT_IN_MD, NULL, returns_twice_attr);
9983 add_builtin_function ("__builtin_tbegin_nofloat", ftype,
9984 S390_BUILTIN_TBEGIN_NOFLOAT,
9985 BUILT_IN_MD, NULL, returns_twice_attr);
9986
9987 /* int foo (void *, int) */
9988 ftype = build_function_type_list (integer_type_node, ptr_type_node,
9989 integer_type_node, NULL_TREE);
9990 add_builtin_function ("__builtin_tbegin_retry", ftype,
9991 S390_BUILTIN_TBEGIN_RETRY,
9992 BUILT_IN_MD,
9993 NULL, returns_twice_attr);
9994 add_builtin_function ("__builtin_tbegin_retry_nofloat", ftype,
9995 S390_BUILTIN_TBEGIN_RETRY_NOFLOAT,
9996 BUILT_IN_MD,
9997 NULL, returns_twice_attr);
9998
9999 /* int foo (void) */
10000 ftype = build_function_type_list (integer_type_node, NULL_TREE);
10001 add_builtin_function ("__builtin_tx_nesting_depth", ftype,
10002 S390_BUILTIN_TX_NESTING_DEPTH,
10003 BUILT_IN_MD, NULL, NULL_TREE);
10004 add_builtin_function ("__builtin_tend", ftype,
10005 S390_BUILTIN_TEND, BUILT_IN_MD, NULL, NULL_TREE);
10006
10007 /* void foo (uint64_t *, uint64_t) */
10008 if (TARGET_64BIT)
10009 uint64_type = long_unsigned_type_node;
10010 else
10011 uint64_type = long_long_unsigned_type_node;
10012
10013 ftype = build_function_type_list (void_type_node,
10014 build_pointer_type (uint64_type),
10015 uint64_type, NULL_TREE);
10016 add_builtin_function ("__builtin_non_tx_store", ftype,
10017 S390_BUILTIN_NON_TX_STORE,
10018 BUILT_IN_MD, NULL, NULL_TREE);
10019 }
10020
10021 /* Expand an expression EXP that calls a built-in function,
10022 with result going to TARGET if that's convenient
10023 (and in mode MODE if that's convenient).
10024 SUBTARGET may be used as the target for computing one of EXP's operands.
10025 IGNORE is nonzero if the value is to be ignored. */
10026
10027 static rtx
10028 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10029 enum machine_mode mode ATTRIBUTE_UNUSED,
10030 int ignore ATTRIBUTE_UNUSED)
10031 {
10032 #define MAX_ARGS 2
10033
10034 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10035 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10036 enum insn_code icode;
10037 rtx op[MAX_ARGS], pat;
10038 int arity;
10039 bool nonvoid;
10040 tree arg;
10041 call_expr_arg_iterator iter;
10042
10043 if (fcode >= S390_BUILTIN_max)
10044 internal_error ("bad builtin fcode");
10045 icode = code_for_builtin[fcode];
10046 if (icode == 0)
10047 internal_error ("bad builtin fcode");
10048
10049 if (!TARGET_HTM)
10050 error ("Transactional execution builtins not enabled (-mhtm)\n");
10051
10052 /* Set a flag in the machine specific cfun part in order to support
10053 saving/restoring of FPRs. */
10054 if (fcode == S390_BUILTIN_TBEGIN || fcode == S390_BUILTIN_TBEGIN_RETRY)
10055 cfun->machine->tbegin_p = true;
10056
10057 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
10058
10059 arity = 0;
10060 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
10061 {
10062 const struct insn_operand_data *insn_op;
10063
10064 if (arg == error_mark_node)
10065 return NULL_RTX;
10066 if (arity >= MAX_ARGS)
10067 return NULL_RTX;
10068
10069 insn_op = &insn_data[icode].operand[arity + nonvoid];
10070
10071 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL);
10072
10073 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
10074 {
10075 if (insn_op->predicate == memory_operand)
10076 {
10077 /* Don't move a NULL pointer into a register. Otherwise
10078 we have to rely on combine being able to move it back
10079 in order to get an immediate 0 in the instruction. */
10080 if (op[arity] != const0_rtx)
10081 op[arity] = copy_to_mode_reg (Pmode, op[arity]);
10082 op[arity] = gen_rtx_MEM (insn_op->mode, op[arity]);
10083 }
10084 else
10085 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
10086 }
10087
10088 arity++;
10089 }
10090
10091 if (nonvoid)
10092 {
10093 enum machine_mode tmode = insn_data[icode].operand[0].mode;
10094 if (!target
10095 || GET_MODE (target) != tmode
10096 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
10097 target = gen_reg_rtx (tmode);
10098 }
10099
10100 switch (arity)
10101 {
10102 case 0:
10103 pat = GEN_FCN (icode) (target);
10104 break;
10105 case 1:
10106 if (nonvoid)
10107 pat = GEN_FCN (icode) (target, op[0]);
10108 else
10109 pat = GEN_FCN (icode) (op[0]);
10110 break;
10111 case 2:
10112 if (nonvoid)
10113 pat = GEN_FCN (icode) (target, op[0], op[1]);
10114 else
10115 pat = GEN_FCN (icode) (op[0], op[1]);
10116 break;
10117 default:
10118 gcc_unreachable ();
10119 }
10120 if (!pat)
10121 return NULL_RTX;
10122 emit_insn (pat);
10123
10124 if (nonvoid)
10125 return target;
10126 else
10127 return const0_rtx;
10128 }
10129
10130 /* We call mcount before the function prologue. So a profiled leaf
10131 function should stay a leaf function. */
10132
10133 static bool
10134 s390_keep_leaf_when_profiled ()
10135 {
10136 return true;
10137 }
10138
10139 /* Output assembly code for the trampoline template to
10140 stdio stream FILE.
10141
10142 On S/390, we use gpr 1 internally in the trampoline code;
10143 gpr 0 is used to hold the static chain. */
10144
10145 static void
10146 s390_asm_trampoline_template (FILE *file)
10147 {
10148 rtx op[2];
10149 op[0] = gen_rtx_REG (Pmode, 0);
10150 op[1] = gen_rtx_REG (Pmode, 1);
10151
10152 if (TARGET_64BIT)
10153 {
10154 output_asm_insn ("basr\t%1,0", op); /* 2 byte */
10155 output_asm_insn ("lmg\t%0,%1,14(%1)", op); /* 6 byte */
10156 output_asm_insn ("br\t%1", op); /* 2 byte */
10157 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
10158 }
10159 else
10160 {
10161 output_asm_insn ("basr\t%1,0", op); /* 2 byte */
10162 output_asm_insn ("lm\t%0,%1,6(%1)", op); /* 4 byte */
10163 output_asm_insn ("br\t%1", op); /* 2 byte */
10164 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
10165 }
10166 }
10167
10168 /* Emit RTL insns to initialize the variable parts of a trampoline.
10169 FNADDR is an RTX for the address of the function's pure code.
10170 CXT is an RTX for the static chain value for the function. */
10171
10172 static void
10173 s390_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
10174 {
10175 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
10176 rtx mem;
10177
10178 emit_block_move (m_tramp, assemble_trampoline_template (),
10179 GEN_INT (2 * UNITS_PER_LONG), BLOCK_OP_NORMAL);
10180
10181 mem = adjust_address (m_tramp, Pmode, 2 * UNITS_PER_LONG);
10182 emit_move_insn (mem, cxt);
10183 mem = adjust_address (m_tramp, Pmode, 3 * UNITS_PER_LONG);
10184 emit_move_insn (mem, fnaddr);
10185 }
10186
10187 /* Output assembler code to FILE to increment profiler label # LABELNO
10188 for profiling a function entry. */
10189
10190 void
10191 s390_function_profiler (FILE *file, int labelno)
10192 {
10193 rtx op[7];
10194
10195 char label[128];
10196 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
10197
10198 fprintf (file, "# function profiler \n");
10199
10200 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
10201 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
10202 op[1] = gen_rtx_MEM (Pmode, plus_constant (Pmode, op[1], UNITS_PER_LONG));
10203
10204 op[2] = gen_rtx_REG (Pmode, 1);
10205 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
10206 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
10207
10208 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
10209 if (flag_pic)
10210 {
10211 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
10212 op[4] = gen_rtx_CONST (Pmode, op[4]);
10213 }
10214
10215 if (TARGET_64BIT)
10216 {
10217 output_asm_insn ("stg\t%0,%1", op);
10218 output_asm_insn ("larl\t%2,%3", op);
10219 output_asm_insn ("brasl\t%0,%4", op);
10220 output_asm_insn ("lg\t%0,%1", op);
10221 }
10222 else if (!flag_pic)
10223 {
10224 op[6] = gen_label_rtx ();
10225
10226 output_asm_insn ("st\t%0,%1", op);
10227 output_asm_insn ("bras\t%2,%l6", op);
10228 output_asm_insn (".long\t%4", op);
10229 output_asm_insn (".long\t%3", op);
10230 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
10231 output_asm_insn ("l\t%0,0(%2)", op);
10232 output_asm_insn ("l\t%2,4(%2)", op);
10233 output_asm_insn ("basr\t%0,%0", op);
10234 output_asm_insn ("l\t%0,%1", op);
10235 }
10236 else
10237 {
10238 op[5] = gen_label_rtx ();
10239 op[6] = gen_label_rtx ();
10240
10241 output_asm_insn ("st\t%0,%1", op);
10242 output_asm_insn ("bras\t%2,%l6", op);
10243 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
10244 output_asm_insn (".long\t%4-%l5", op);
10245 output_asm_insn (".long\t%3-%l5", op);
10246 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
10247 output_asm_insn ("lr\t%0,%2", op);
10248 output_asm_insn ("a\t%0,0(%2)", op);
10249 output_asm_insn ("a\t%2,4(%2)", op);
10250 output_asm_insn ("basr\t%0,%0", op);
10251 output_asm_insn ("l\t%0,%1", op);
10252 }
10253 }
10254
10255 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
10256 into its SYMBOL_REF_FLAGS. */
10257
10258 static void
10259 s390_encode_section_info (tree decl, rtx rtl, int first)
10260 {
10261 default_encode_section_info (decl, rtl, first);
10262
10263 if (TREE_CODE (decl) == VAR_DECL)
10264 {
10265 /* If a variable has a forced alignment to < 2 bytes, mark it
10266 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
10267 operand. */
10268 if (DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
10269 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
10270 if (!DECL_SIZE (decl)
10271 || !DECL_ALIGN (decl)
10272 || !tree_fits_shwi_p (DECL_SIZE (decl))
10273 || (DECL_ALIGN (decl) <= 64
10274 && DECL_ALIGN (decl) != tree_to_shwi (DECL_SIZE (decl))))
10275 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
10276 }
10277
10278 /* Literal pool references don't have a decl so they are handled
10279 differently here. We rely on the information in the MEM_ALIGN
10280 entry to decide upon natural alignment. */
10281 if (MEM_P (rtl)
10282 && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
10283 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0))
10284 && (MEM_ALIGN (rtl) == 0
10285 || GET_MODE_BITSIZE (GET_MODE (rtl)) == 0
10286 || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl))))
10287 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
10288 }
10289
10290 /* Output thunk to FILE that implements a C++ virtual function call (with
10291 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
10292 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
10293 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
10294 relative to the resulting this pointer. */
10295
10296 static void
10297 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
10298 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
10299 tree function)
10300 {
10301 rtx op[10];
10302 int nonlocal = 0;
10303
10304 /* Make sure unwind info is emitted for the thunk if needed. */
10305 final_start_function (emit_barrier (), file, 1);
10306
10307 /* Operand 0 is the target function. */
10308 op[0] = XEXP (DECL_RTL (function), 0);
10309 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
10310 {
10311 nonlocal = 1;
10312 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
10313 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
10314 op[0] = gen_rtx_CONST (Pmode, op[0]);
10315 }
10316
10317 /* Operand 1 is the 'this' pointer. */
10318 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
10319 op[1] = gen_rtx_REG (Pmode, 3);
10320 else
10321 op[1] = gen_rtx_REG (Pmode, 2);
10322
10323 /* Operand 2 is the delta. */
10324 op[2] = GEN_INT (delta);
10325
10326 /* Operand 3 is the vcall_offset. */
10327 op[3] = GEN_INT (vcall_offset);
10328
10329 /* Operand 4 is the temporary register. */
10330 op[4] = gen_rtx_REG (Pmode, 1);
10331
10332 /* Operands 5 to 8 can be used as labels. */
10333 op[5] = NULL_RTX;
10334 op[6] = NULL_RTX;
10335 op[7] = NULL_RTX;
10336 op[8] = NULL_RTX;
10337
10338 /* Operand 9 can be used for temporary register. */
10339 op[9] = NULL_RTX;
10340
10341 /* Generate code. */
10342 if (TARGET_64BIT)
10343 {
10344 /* Setup literal pool pointer if required. */
10345 if ((!DISP_IN_RANGE (delta)
10346 && !CONST_OK_FOR_K (delta)
10347 && !CONST_OK_FOR_Os (delta))
10348 || (!DISP_IN_RANGE (vcall_offset)
10349 && !CONST_OK_FOR_K (vcall_offset)
10350 && !CONST_OK_FOR_Os (vcall_offset)))
10351 {
10352 op[5] = gen_label_rtx ();
10353 output_asm_insn ("larl\t%4,%5", op);
10354 }
10355
10356 /* Add DELTA to this pointer. */
10357 if (delta)
10358 {
10359 if (CONST_OK_FOR_J (delta))
10360 output_asm_insn ("la\t%1,%2(%1)", op);
10361 else if (DISP_IN_RANGE (delta))
10362 output_asm_insn ("lay\t%1,%2(%1)", op);
10363 else if (CONST_OK_FOR_K (delta))
10364 output_asm_insn ("aghi\t%1,%2", op);
10365 else if (CONST_OK_FOR_Os (delta))
10366 output_asm_insn ("agfi\t%1,%2", op);
10367 else
10368 {
10369 op[6] = gen_label_rtx ();
10370 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
10371 }
10372 }
10373
10374 /* Perform vcall adjustment. */
10375 if (vcall_offset)
10376 {
10377 if (DISP_IN_RANGE (vcall_offset))
10378 {
10379 output_asm_insn ("lg\t%4,0(%1)", op);
10380 output_asm_insn ("ag\t%1,%3(%4)", op);
10381 }
10382 else if (CONST_OK_FOR_K (vcall_offset))
10383 {
10384 output_asm_insn ("lghi\t%4,%3", op);
10385 output_asm_insn ("ag\t%4,0(%1)", op);
10386 output_asm_insn ("ag\t%1,0(%4)", op);
10387 }
10388 else if (CONST_OK_FOR_Os (vcall_offset))
10389 {
10390 output_asm_insn ("lgfi\t%4,%3", op);
10391 output_asm_insn ("ag\t%4,0(%1)", op);
10392 output_asm_insn ("ag\t%1,0(%4)", op);
10393 }
10394 else
10395 {
10396 op[7] = gen_label_rtx ();
10397 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
10398 output_asm_insn ("ag\t%4,0(%1)", op);
10399 output_asm_insn ("ag\t%1,0(%4)", op);
10400 }
10401 }
10402
10403 /* Jump to target. */
10404 output_asm_insn ("jg\t%0", op);
10405
10406 /* Output literal pool if required. */
10407 if (op[5])
10408 {
10409 output_asm_insn (".align\t4", op);
10410 targetm.asm_out.internal_label (file, "L",
10411 CODE_LABEL_NUMBER (op[5]));
10412 }
10413 if (op[6])
10414 {
10415 targetm.asm_out.internal_label (file, "L",
10416 CODE_LABEL_NUMBER (op[6]));
10417 output_asm_insn (".long\t%2", op);
10418 }
10419 if (op[7])
10420 {
10421 targetm.asm_out.internal_label (file, "L",
10422 CODE_LABEL_NUMBER (op[7]));
10423 output_asm_insn (".long\t%3", op);
10424 }
10425 }
10426 else
10427 {
10428 /* Setup base pointer if required. */
10429 if (!vcall_offset
10430 || (!DISP_IN_RANGE (delta)
10431 && !CONST_OK_FOR_K (delta)
10432 && !CONST_OK_FOR_Os (delta))
10433 || (!DISP_IN_RANGE (delta)
10434 && !CONST_OK_FOR_K (vcall_offset)
10435 && !CONST_OK_FOR_Os (vcall_offset)))
10436 {
10437 op[5] = gen_label_rtx ();
10438 output_asm_insn ("basr\t%4,0", op);
10439 targetm.asm_out.internal_label (file, "L",
10440 CODE_LABEL_NUMBER (op[5]));
10441 }
10442
10443 /* Add DELTA to this pointer. */
10444 if (delta)
10445 {
10446 if (CONST_OK_FOR_J (delta))
10447 output_asm_insn ("la\t%1,%2(%1)", op);
10448 else if (DISP_IN_RANGE (delta))
10449 output_asm_insn ("lay\t%1,%2(%1)", op);
10450 else if (CONST_OK_FOR_K (delta))
10451 output_asm_insn ("ahi\t%1,%2", op);
10452 else if (CONST_OK_FOR_Os (delta))
10453 output_asm_insn ("afi\t%1,%2", op);
10454 else
10455 {
10456 op[6] = gen_label_rtx ();
10457 output_asm_insn ("a\t%1,%6-%5(%4)", op);
10458 }
10459 }
10460
10461 /* Perform vcall adjustment. */
10462 if (vcall_offset)
10463 {
10464 if (CONST_OK_FOR_J (vcall_offset))
10465 {
10466 output_asm_insn ("l\t%4,0(%1)", op);
10467 output_asm_insn ("a\t%1,%3(%4)", op);
10468 }
10469 else if (DISP_IN_RANGE (vcall_offset))
10470 {
10471 output_asm_insn ("l\t%4,0(%1)", op);
10472 output_asm_insn ("ay\t%1,%3(%4)", op);
10473 }
10474 else if (CONST_OK_FOR_K (vcall_offset))
10475 {
10476 output_asm_insn ("lhi\t%4,%3", op);
10477 output_asm_insn ("a\t%4,0(%1)", op);
10478 output_asm_insn ("a\t%1,0(%4)", op);
10479 }
10480 else if (CONST_OK_FOR_Os (vcall_offset))
10481 {
10482 output_asm_insn ("iilf\t%4,%3", op);
10483 output_asm_insn ("a\t%4,0(%1)", op);
10484 output_asm_insn ("a\t%1,0(%4)", op);
10485 }
10486 else
10487 {
10488 op[7] = gen_label_rtx ();
10489 output_asm_insn ("l\t%4,%7-%5(%4)", op);
10490 output_asm_insn ("a\t%4,0(%1)", op);
10491 output_asm_insn ("a\t%1,0(%4)", op);
10492 }
10493
10494 /* We had to clobber the base pointer register.
10495 Re-setup the base pointer (with a different base). */
10496 op[5] = gen_label_rtx ();
10497 output_asm_insn ("basr\t%4,0", op);
10498 targetm.asm_out.internal_label (file, "L",
10499 CODE_LABEL_NUMBER (op[5]));
10500 }
10501
10502 /* Jump to target. */
10503 op[8] = gen_label_rtx ();
10504
10505 if (!flag_pic)
10506 output_asm_insn ("l\t%4,%8-%5(%4)", op);
10507 else if (!nonlocal)
10508 output_asm_insn ("a\t%4,%8-%5(%4)", op);
10509 /* We cannot call through .plt, since .plt requires %r12 loaded. */
10510 else if (flag_pic == 1)
10511 {
10512 output_asm_insn ("a\t%4,%8-%5(%4)", op);
10513 output_asm_insn ("l\t%4,%0(%4)", op);
10514 }
10515 else if (flag_pic == 2)
10516 {
10517 op[9] = gen_rtx_REG (Pmode, 0);
10518 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
10519 output_asm_insn ("a\t%4,%8-%5(%4)", op);
10520 output_asm_insn ("ar\t%4,%9", op);
10521 output_asm_insn ("l\t%4,0(%4)", op);
10522 }
10523
10524 output_asm_insn ("br\t%4", op);
10525
10526 /* Output literal pool. */
10527 output_asm_insn (".align\t4", op);
10528
10529 if (nonlocal && flag_pic == 2)
10530 output_asm_insn (".long\t%0", op);
10531 if (nonlocal)
10532 {
10533 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
10534 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
10535 }
10536
10537 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
10538 if (!flag_pic)
10539 output_asm_insn (".long\t%0", op);
10540 else
10541 output_asm_insn (".long\t%0-%5", op);
10542
10543 if (op[6])
10544 {
10545 targetm.asm_out.internal_label (file, "L",
10546 CODE_LABEL_NUMBER (op[6]));
10547 output_asm_insn (".long\t%2", op);
10548 }
10549 if (op[7])
10550 {
10551 targetm.asm_out.internal_label (file, "L",
10552 CODE_LABEL_NUMBER (op[7]));
10553 output_asm_insn (".long\t%3", op);
10554 }
10555 }
10556 final_end_function ();
10557 }
10558
10559 static bool
10560 s390_valid_pointer_mode (enum machine_mode mode)
10561 {
10562 return (mode == SImode || (TARGET_64BIT && mode == DImode));
10563 }
10564
10565 /* Checks whether the given CALL_EXPR would use a caller
10566 saved register. This is used to decide whether sibling call
10567 optimization could be performed on the respective function
10568 call. */
10569
10570 static bool
10571 s390_call_saved_register_used (tree call_expr)
10572 {
10573 CUMULATIVE_ARGS cum_v;
10574 cumulative_args_t cum;
10575 tree parameter;
10576 enum machine_mode mode;
10577 tree type;
10578 rtx parm_rtx;
10579 int reg, i;
10580
10581 INIT_CUMULATIVE_ARGS (cum_v, NULL, NULL, 0, 0);
10582 cum = pack_cumulative_args (&cum_v);
10583
10584 for (i = 0; i < call_expr_nargs (call_expr); i++)
10585 {
10586 parameter = CALL_EXPR_ARG (call_expr, i);
10587 gcc_assert (parameter);
10588
10589 /* For an undeclared variable passed as parameter we will get
10590 an ERROR_MARK node here. */
10591 if (TREE_CODE (parameter) == ERROR_MARK)
10592 return true;
10593
10594 type = TREE_TYPE (parameter);
10595 gcc_assert (type);
10596
10597 mode = TYPE_MODE (type);
10598 gcc_assert (mode);
10599
10600 if (pass_by_reference (&cum_v, mode, type, true))
10601 {
10602 mode = Pmode;
10603 type = build_pointer_type (type);
10604 }
10605
10606 parm_rtx = s390_function_arg (cum, mode, type, 0);
10607
10608 s390_function_arg_advance (cum, mode, type, 0);
10609
10610 if (!parm_rtx)
10611 continue;
10612
10613 if (REG_P (parm_rtx))
10614 {
10615 for (reg = 0;
10616 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
10617 reg++)
10618 if (!call_used_regs[reg + REGNO (parm_rtx)])
10619 return true;
10620 }
10621
10622 if (GET_CODE (parm_rtx) == PARALLEL)
10623 {
10624 int i;
10625
10626 for (i = 0; i < XVECLEN (parm_rtx, 0); i++)
10627 {
10628 rtx r = XEXP (XVECEXP (parm_rtx, 0, i), 0);
10629
10630 gcc_assert (REG_P (r));
10631
10632 for (reg = 0;
10633 reg < HARD_REGNO_NREGS (REGNO (r), GET_MODE (r));
10634 reg++)
10635 if (!call_used_regs[reg + REGNO (r)])
10636 return true;
10637 }
10638 }
10639
10640 }
10641 return false;
10642 }
10643
10644 /* Return true if the given call expression can be
10645 turned into a sibling call.
10646 DECL holds the declaration of the function to be called whereas
10647 EXP is the call expression itself. */
10648
10649 static bool
10650 s390_function_ok_for_sibcall (tree decl, tree exp)
10651 {
10652 /* The TPF epilogue uses register 1. */
10653 if (TARGET_TPF_PROFILING)
10654 return false;
10655
10656 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
10657 which would have to be restored before the sibcall. */
10658 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
10659 return false;
10660
10661 /* Register 6 on s390 is available as an argument register but unfortunately
10662 "caller saved". This makes functions needing this register for arguments
10663 not suitable for sibcalls. */
10664 return !s390_call_saved_register_used (exp);
10665 }
10666
10667 /* Return the fixed registers used for condition codes. */
10668
10669 static bool
10670 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
10671 {
10672 *p1 = CC_REGNUM;
10673 *p2 = INVALID_REGNUM;
10674
10675 return true;
10676 }
10677
10678 /* This function is used by the call expanders of the machine description.
10679 It emits the call insn itself together with the necessary operations
10680 to adjust the target address and returns the emitted insn.
10681 ADDR_LOCATION is the target address rtx
10682 TLS_CALL the location of the thread-local symbol
10683 RESULT_REG the register where the result of the call should be stored
10684 RETADDR_REG the register where the return address should be stored
10685 If this parameter is NULL_RTX the call is considered
10686 to be a sibling call. */
10687
10688 rtx_insn *
10689 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
10690 rtx retaddr_reg)
10691 {
10692 bool plt_call = false;
10693 rtx_insn *insn;
10694 rtx call;
10695 rtx clobber;
10696 rtvec vec;
10697
10698 /* Direct function calls need special treatment. */
10699 if (GET_CODE (addr_location) == SYMBOL_REF)
10700 {
10701 /* When calling a global routine in PIC mode, we must
10702 replace the symbol itself with the PLT stub. */
10703 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
10704 {
10705 if (retaddr_reg != NULL_RTX)
10706 {
10707 addr_location = gen_rtx_UNSPEC (Pmode,
10708 gen_rtvec (1, addr_location),
10709 UNSPEC_PLT);
10710 addr_location = gen_rtx_CONST (Pmode, addr_location);
10711 plt_call = true;
10712 }
10713 else
10714 /* For -fpic code the PLT entries might use r12 which is
10715 call-saved. Therefore we cannot do a sibcall when
10716 calling directly using a symbol ref. When reaching
10717 this point we decided (in s390_function_ok_for_sibcall)
10718 to do a sibcall for a function pointer but one of the
10719 optimizers was able to get rid of the function pointer
10720 by propagating the symbol ref into the call. This
10721 optimization is illegal for S/390 so we turn the direct
10722 call into a indirect call again. */
10723 addr_location = force_reg (Pmode, addr_location);
10724 }
10725
10726 /* Unless we can use the bras(l) insn, force the
10727 routine address into a register. */
10728 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
10729 {
10730 if (flag_pic)
10731 addr_location = legitimize_pic_address (addr_location, 0);
10732 else
10733 addr_location = force_reg (Pmode, addr_location);
10734 }
10735 }
10736
10737 /* If it is already an indirect call or the code above moved the
10738 SYMBOL_REF to somewhere else make sure the address can be found in
10739 register 1. */
10740 if (retaddr_reg == NULL_RTX
10741 && GET_CODE (addr_location) != SYMBOL_REF
10742 && !plt_call)
10743 {
10744 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
10745 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
10746 }
10747
10748 addr_location = gen_rtx_MEM (QImode, addr_location);
10749 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
10750
10751 if (result_reg != NULL_RTX)
10752 call = gen_rtx_SET (VOIDmode, result_reg, call);
10753
10754 if (retaddr_reg != NULL_RTX)
10755 {
10756 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
10757
10758 if (tls_call != NULL_RTX)
10759 vec = gen_rtvec (3, call, clobber,
10760 gen_rtx_USE (VOIDmode, tls_call));
10761 else
10762 vec = gen_rtvec (2, call, clobber);
10763
10764 call = gen_rtx_PARALLEL (VOIDmode, vec);
10765 }
10766
10767 insn = emit_call_insn (call);
10768
10769 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
10770 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
10771 {
10772 /* s390_function_ok_for_sibcall should
10773 have denied sibcalls in this case. */
10774 gcc_assert (retaddr_reg != NULL_RTX);
10775 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, 12));
10776 }
10777 return insn;
10778 }
10779
10780 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
10781
10782 static void
10783 s390_conditional_register_usage (void)
10784 {
10785 int i;
10786
10787 if (flag_pic)
10788 {
10789 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
10790 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
10791 }
10792 if (TARGET_CPU_ZARCH)
10793 {
10794 fixed_regs[BASE_REGNUM] = 0;
10795 call_used_regs[BASE_REGNUM] = 0;
10796 fixed_regs[RETURN_REGNUM] = 0;
10797 call_used_regs[RETURN_REGNUM] = 0;
10798 }
10799 if (TARGET_64BIT)
10800 {
10801 for (i = FPR8_REGNUM; i <= FPR15_REGNUM; i++)
10802 call_used_regs[i] = call_really_used_regs[i] = 0;
10803 }
10804 else
10805 {
10806 call_used_regs[FPR4_REGNUM] = call_really_used_regs[FPR4_REGNUM] = 0;
10807 call_used_regs[FPR6_REGNUM] = call_really_used_regs[FPR6_REGNUM] = 0;
10808 }
10809
10810 if (TARGET_SOFT_FLOAT)
10811 {
10812 for (i = FPR0_REGNUM; i <= FPR15_REGNUM; i++)
10813 call_used_regs[i] = fixed_regs[i] = 1;
10814 }
10815 }
10816
10817 /* Corresponding function to eh_return expander. */
10818
10819 static GTY(()) rtx s390_tpf_eh_return_symbol;
10820 void
10821 s390_emit_tpf_eh_return (rtx target)
10822 {
10823 rtx_insn *insn;
10824 rtx reg, orig_ra;
10825
10826 if (!s390_tpf_eh_return_symbol)
10827 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
10828
10829 reg = gen_rtx_REG (Pmode, 2);
10830 orig_ra = gen_rtx_REG (Pmode, 3);
10831
10832 emit_move_insn (reg, target);
10833 emit_move_insn (orig_ra, get_hard_reg_initial_val (Pmode, RETURN_REGNUM));
10834 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
10835 gen_rtx_REG (Pmode, RETURN_REGNUM));
10836 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
10837 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), orig_ra);
10838
10839 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
10840 }
10841
10842 /* Rework the prologue/epilogue to avoid saving/restoring
10843 registers unnecessarily. */
10844
10845 static void
10846 s390_optimize_prologue (void)
10847 {
10848 rtx_insn *insn, *new_insn, *next_insn;
10849
10850 /* Do a final recompute of the frame-related data. */
10851 s390_optimize_register_info ();
10852
10853 /* If all special registers are in fact used, there's nothing we
10854 can do, so no point in walking the insn list. */
10855
10856 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
10857 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
10858 && (TARGET_CPU_ZARCH
10859 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
10860 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
10861 return;
10862
10863 /* Search for prologue/epilogue insns and replace them. */
10864
10865 for (insn = get_insns (); insn; insn = next_insn)
10866 {
10867 int first, last, off;
10868 rtx set, base, offset;
10869 rtx pat;
10870
10871 next_insn = NEXT_INSN (insn);
10872
10873 if (! NONJUMP_INSN_P (insn) || ! RTX_FRAME_RELATED_P (insn))
10874 continue;
10875
10876 pat = PATTERN (insn);
10877
10878 /* Remove ldgr/lgdr instructions used for saving and restore
10879 GPRs if possible. */
10880 if (TARGET_Z10
10881 && GET_CODE (pat) == SET
10882 && GET_MODE (SET_SRC (pat)) == DImode
10883 && REG_P (SET_SRC (pat))
10884 && REG_P (SET_DEST (pat)))
10885 {
10886 int src_regno = REGNO (SET_SRC (pat));
10887 int dest_regno = REGNO (SET_DEST (pat));
10888 int gpr_regno;
10889 int fpr_regno;
10890
10891 if (!((GENERAL_REGNO_P (src_regno) && FP_REGNO_P (dest_regno))
10892 || (FP_REGNO_P (src_regno) && GENERAL_REGNO_P (dest_regno))))
10893 continue;
10894
10895 gpr_regno = GENERAL_REGNO_P (src_regno) ? src_regno : dest_regno;
10896 fpr_regno = FP_REGNO_P (src_regno) ? src_regno : dest_regno;
10897
10898 /* GPR must be call-saved, FPR must be call-clobbered. */
10899 if (!call_really_used_regs[fpr_regno]
10900 || call_really_used_regs[gpr_regno])
10901 continue;
10902
10903 /* It must not happen that what we once saved in an FPR now
10904 needs a stack slot. */
10905 gcc_assert (cfun_gpr_save_slot (gpr_regno) != -1);
10906
10907 if (cfun_gpr_save_slot (gpr_regno) == 0)
10908 {
10909 remove_insn (insn);
10910 continue;
10911 }
10912 }
10913
10914 if (GET_CODE (pat) == PARALLEL
10915 && store_multiple_operation (pat, VOIDmode))
10916 {
10917 set = XVECEXP (pat, 0, 0);
10918 first = REGNO (SET_SRC (set));
10919 last = first + XVECLEN (pat, 0) - 1;
10920 offset = const0_rtx;
10921 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
10922 off = INTVAL (offset);
10923
10924 if (GET_CODE (base) != REG || off < 0)
10925 continue;
10926 if (cfun_frame_layout.first_save_gpr != -1
10927 && (cfun_frame_layout.first_save_gpr < first
10928 || cfun_frame_layout.last_save_gpr > last))
10929 continue;
10930 if (REGNO (base) != STACK_POINTER_REGNUM
10931 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10932 continue;
10933 if (first > BASE_REGNUM || last < BASE_REGNUM)
10934 continue;
10935
10936 if (cfun_frame_layout.first_save_gpr != -1)
10937 {
10938 rtx s_pat = save_gprs (base,
10939 off + (cfun_frame_layout.first_save_gpr
10940 - first) * UNITS_PER_LONG,
10941 cfun_frame_layout.first_save_gpr,
10942 cfun_frame_layout.last_save_gpr);
10943 new_insn = emit_insn_before (s_pat, insn);
10944 INSN_ADDRESSES_NEW (new_insn, -1);
10945 }
10946
10947 remove_insn (insn);
10948 continue;
10949 }
10950
10951 if (cfun_frame_layout.first_save_gpr == -1
10952 && GET_CODE (pat) == SET
10953 && GENERAL_REG_P (SET_SRC (pat))
10954 && GET_CODE (SET_DEST (pat)) == MEM)
10955 {
10956 set = pat;
10957 first = REGNO (SET_SRC (set));
10958 offset = const0_rtx;
10959 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
10960 off = INTVAL (offset);
10961
10962 if (GET_CODE (base) != REG || off < 0)
10963 continue;
10964 if (REGNO (base) != STACK_POINTER_REGNUM
10965 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10966 continue;
10967
10968 remove_insn (insn);
10969 continue;
10970 }
10971
10972 if (GET_CODE (pat) == PARALLEL
10973 && load_multiple_operation (pat, VOIDmode))
10974 {
10975 set = XVECEXP (pat, 0, 0);
10976 first = REGNO (SET_DEST (set));
10977 last = first + XVECLEN (pat, 0) - 1;
10978 offset = const0_rtx;
10979 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
10980 off = INTVAL (offset);
10981
10982 if (GET_CODE (base) != REG || off < 0)
10983 continue;
10984
10985 if (cfun_frame_layout.first_restore_gpr != -1
10986 && (cfun_frame_layout.first_restore_gpr < first
10987 || cfun_frame_layout.last_restore_gpr > last))
10988 continue;
10989 if (REGNO (base) != STACK_POINTER_REGNUM
10990 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10991 continue;
10992 if (first > BASE_REGNUM || last < BASE_REGNUM)
10993 continue;
10994
10995 if (cfun_frame_layout.first_restore_gpr != -1)
10996 {
10997 rtx rpat = restore_gprs (base,
10998 off + (cfun_frame_layout.first_restore_gpr
10999 - first) * UNITS_PER_LONG,
11000 cfun_frame_layout.first_restore_gpr,
11001 cfun_frame_layout.last_restore_gpr);
11002
11003 /* Remove REG_CFA_RESTOREs for registers that we no
11004 longer need to save. */
11005 REG_NOTES (rpat) = REG_NOTES (insn);
11006 for (rtx *ptr = &REG_NOTES (rpat); *ptr; )
11007 if (REG_NOTE_KIND (*ptr) == REG_CFA_RESTORE
11008 && ((int) REGNO (XEXP (*ptr, 0))
11009 < cfun_frame_layout.first_restore_gpr))
11010 *ptr = XEXP (*ptr, 1);
11011 else
11012 ptr = &XEXP (*ptr, 1);
11013 new_insn = emit_insn_before (rpat, insn);
11014 RTX_FRAME_RELATED_P (new_insn) = 1;
11015 INSN_ADDRESSES_NEW (new_insn, -1);
11016 }
11017
11018 remove_insn (insn);
11019 continue;
11020 }
11021
11022 if (cfun_frame_layout.first_restore_gpr == -1
11023 && GET_CODE (pat) == SET
11024 && GENERAL_REG_P (SET_DEST (pat))
11025 && GET_CODE (SET_SRC (pat)) == MEM)
11026 {
11027 set = pat;
11028 first = REGNO (SET_DEST (set));
11029 offset = const0_rtx;
11030 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
11031 off = INTVAL (offset);
11032
11033 if (GET_CODE (base) != REG || off < 0)
11034 continue;
11035
11036 if (REGNO (base) != STACK_POINTER_REGNUM
11037 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
11038 continue;
11039
11040 remove_insn (insn);
11041 continue;
11042 }
11043 }
11044 }
11045
11046 /* On z10 and later the dynamic branch prediction must see the
11047 backward jump within a certain windows. If not it falls back to
11048 the static prediction. This function rearranges the loop backward
11049 branch in a way which makes the static prediction always correct.
11050 The function returns true if it added an instruction. */
11051 static bool
11052 s390_fix_long_loop_prediction (rtx_insn *insn)
11053 {
11054 rtx set = single_set (insn);
11055 rtx code_label, label_ref, new_label;
11056 rtx_insn *uncond_jump;
11057 rtx_insn *cur_insn;
11058 rtx tmp;
11059 int distance;
11060
11061 /* This will exclude branch on count and branch on index patterns
11062 since these are correctly statically predicted. */
11063 if (!set
11064 || SET_DEST (set) != pc_rtx
11065 || GET_CODE (SET_SRC(set)) != IF_THEN_ELSE)
11066 return false;
11067
11068 /* Skip conditional returns. */
11069 if (ANY_RETURN_P (XEXP (SET_SRC (set), 1))
11070 && XEXP (SET_SRC (set), 2) == pc_rtx)
11071 return false;
11072
11073 label_ref = (GET_CODE (XEXP (SET_SRC (set), 1)) == LABEL_REF ?
11074 XEXP (SET_SRC (set), 1) : XEXP (SET_SRC (set), 2));
11075
11076 gcc_assert (GET_CODE (label_ref) == LABEL_REF);
11077
11078 code_label = XEXP (label_ref, 0);
11079
11080 if (INSN_ADDRESSES (INSN_UID (code_label)) == -1
11081 || INSN_ADDRESSES (INSN_UID (insn)) == -1
11082 || (INSN_ADDRESSES (INSN_UID (insn))
11083 - INSN_ADDRESSES (INSN_UID (code_label)) < PREDICT_DISTANCE))
11084 return false;
11085
11086 for (distance = 0, cur_insn = PREV_INSN (insn);
11087 distance < PREDICT_DISTANCE - 6;
11088 distance += get_attr_length (cur_insn), cur_insn = PREV_INSN (cur_insn))
11089 if (!cur_insn || JUMP_P (cur_insn) || LABEL_P (cur_insn))
11090 return false;
11091
11092 new_label = gen_label_rtx ();
11093 uncond_jump = emit_jump_insn_after (
11094 gen_rtx_SET (VOIDmode, pc_rtx,
11095 gen_rtx_LABEL_REF (VOIDmode, code_label)),
11096 insn);
11097 emit_label_after (new_label, uncond_jump);
11098
11099 tmp = XEXP (SET_SRC (set), 1);
11100 XEXP (SET_SRC (set), 1) = XEXP (SET_SRC (set), 2);
11101 XEXP (SET_SRC (set), 2) = tmp;
11102 INSN_CODE (insn) = -1;
11103
11104 XEXP (label_ref, 0) = new_label;
11105 JUMP_LABEL (insn) = new_label;
11106 JUMP_LABEL (uncond_jump) = code_label;
11107
11108 return true;
11109 }
11110
11111 /* Returns 1 if INSN reads the value of REG for purposes not related
11112 to addressing of memory, and 0 otherwise. */
11113 static int
11114 s390_non_addr_reg_read_p (rtx reg, rtx_insn *insn)
11115 {
11116 return reg_referenced_p (reg, PATTERN (insn))
11117 && !reg_used_in_mem_p (REGNO (reg), PATTERN (insn));
11118 }
11119
11120 /* Starting from INSN find_cond_jump looks downwards in the insn
11121 stream for a single jump insn which is the last user of the
11122 condition code set in INSN. */
11123 static rtx_insn *
11124 find_cond_jump (rtx_insn *insn)
11125 {
11126 for (; insn; insn = NEXT_INSN (insn))
11127 {
11128 rtx ite, cc;
11129
11130 if (LABEL_P (insn))
11131 break;
11132
11133 if (!JUMP_P (insn))
11134 {
11135 if (reg_mentioned_p (gen_rtx_REG (CCmode, CC_REGNUM), insn))
11136 break;
11137 continue;
11138 }
11139
11140 /* This will be triggered by a return. */
11141 if (GET_CODE (PATTERN (insn)) != SET)
11142 break;
11143
11144 gcc_assert (SET_DEST (PATTERN (insn)) == pc_rtx);
11145 ite = SET_SRC (PATTERN (insn));
11146
11147 if (GET_CODE (ite) != IF_THEN_ELSE)
11148 break;
11149
11150 cc = XEXP (XEXP (ite, 0), 0);
11151 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc)))
11152 break;
11153
11154 if (find_reg_note (insn, REG_DEAD, cc))
11155 return insn;
11156 break;
11157 }
11158
11159 return NULL;
11160 }
11161
11162 /* Swap the condition in COND and the operands in OP0 and OP1 so that
11163 the semantics does not change. If NULL_RTX is passed as COND the
11164 function tries to find the conditional jump starting with INSN. */
11165 static void
11166 s390_swap_cmp (rtx cond, rtx *op0, rtx *op1, rtx_insn *insn)
11167 {
11168 rtx tmp = *op0;
11169
11170 if (cond == NULL_RTX)
11171 {
11172 rtx_insn *jump = find_cond_jump (NEXT_INSN (insn));
11173 rtx set = jump ? single_set (jump) : NULL_RTX;
11174
11175 if (set == NULL_RTX)
11176 return;
11177
11178 cond = XEXP (SET_SRC (set), 0);
11179 }
11180
11181 *op0 = *op1;
11182 *op1 = tmp;
11183 PUT_CODE (cond, swap_condition (GET_CODE (cond)));
11184 }
11185
11186 /* On z10, instructions of the compare-and-branch family have the
11187 property to access the register occurring as second operand with
11188 its bits complemented. If such a compare is grouped with a second
11189 instruction that accesses the same register non-complemented, and
11190 if that register's value is delivered via a bypass, then the
11191 pipeline recycles, thereby causing significant performance decline.
11192 This function locates such situations and exchanges the two
11193 operands of the compare. The function return true whenever it
11194 added an insn. */
11195 static bool
11196 s390_z10_optimize_cmp (rtx_insn *insn)
11197 {
11198 rtx_insn *prev_insn, *next_insn;
11199 bool insn_added_p = false;
11200 rtx cond, *op0, *op1;
11201
11202 if (GET_CODE (PATTERN (insn)) == PARALLEL)
11203 {
11204 /* Handle compare and branch and branch on count
11205 instructions. */
11206 rtx pattern = single_set (insn);
11207
11208 if (!pattern
11209 || SET_DEST (pattern) != pc_rtx
11210 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE)
11211 return false;
11212
11213 cond = XEXP (SET_SRC (pattern), 0);
11214 op0 = &XEXP (cond, 0);
11215 op1 = &XEXP (cond, 1);
11216 }
11217 else if (GET_CODE (PATTERN (insn)) == SET)
11218 {
11219 rtx src, dest;
11220
11221 /* Handle normal compare instructions. */
11222 src = SET_SRC (PATTERN (insn));
11223 dest = SET_DEST (PATTERN (insn));
11224
11225 if (!REG_P (dest)
11226 || !CC_REGNO_P (REGNO (dest))
11227 || GET_CODE (src) != COMPARE)
11228 return false;
11229
11230 /* s390_swap_cmp will try to find the conditional
11231 jump when passing NULL_RTX as condition. */
11232 cond = NULL_RTX;
11233 op0 = &XEXP (src, 0);
11234 op1 = &XEXP (src, 1);
11235 }
11236 else
11237 return false;
11238
11239 if (!REG_P (*op0) || !REG_P (*op1))
11240 return false;
11241
11242 if (GET_MODE_CLASS (GET_MODE (*op0)) != MODE_INT)
11243 return false;
11244
11245 /* Swap the COMPARE arguments and its mask if there is a
11246 conflicting access in the previous insn. */
11247 prev_insn = prev_active_insn (insn);
11248 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
11249 && reg_referenced_p (*op1, PATTERN (prev_insn)))
11250 s390_swap_cmp (cond, op0, op1, insn);
11251
11252 /* Check if there is a conflict with the next insn. If there
11253 was no conflict with the previous insn, then swap the
11254 COMPARE arguments and its mask. If we already swapped
11255 the operands, or if swapping them would cause a conflict
11256 with the previous insn, issue a NOP after the COMPARE in
11257 order to separate the two instuctions. */
11258 next_insn = next_active_insn (insn);
11259 if (next_insn != NULL_RTX && INSN_P (next_insn)
11260 && s390_non_addr_reg_read_p (*op1, next_insn))
11261 {
11262 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
11263 && s390_non_addr_reg_read_p (*op0, prev_insn))
11264 {
11265 if (REGNO (*op1) == 0)
11266 emit_insn_after (gen_nop1 (), insn);
11267 else
11268 emit_insn_after (gen_nop (), insn);
11269 insn_added_p = true;
11270 }
11271 else
11272 s390_swap_cmp (cond, op0, op1, insn);
11273 }
11274 return insn_added_p;
11275 }
11276
11277 /* Perform machine-dependent processing. */
11278
11279 static void
11280 s390_reorg (void)
11281 {
11282 bool pool_overflow = false;
11283
11284 /* Make sure all splits have been performed; splits after
11285 machine_dependent_reorg might confuse insn length counts. */
11286 split_all_insns_noflow ();
11287
11288 /* Install the main literal pool and the associated base
11289 register load insns.
11290
11291 In addition, there are two problematic situations we need
11292 to correct:
11293
11294 - the literal pool might be > 4096 bytes in size, so that
11295 some of its elements cannot be directly accessed
11296
11297 - a branch target might be > 64K away from the branch, so that
11298 it is not possible to use a PC-relative instruction.
11299
11300 To fix those, we split the single literal pool into multiple
11301 pool chunks, reloading the pool base register at various
11302 points throughout the function to ensure it always points to
11303 the pool chunk the following code expects, and / or replace
11304 PC-relative branches by absolute branches.
11305
11306 However, the two problems are interdependent: splitting the
11307 literal pool can move a branch further away from its target,
11308 causing the 64K limit to overflow, and on the other hand,
11309 replacing a PC-relative branch by an absolute branch means
11310 we need to put the branch target address into the literal
11311 pool, possibly causing it to overflow.
11312
11313 So, we loop trying to fix up both problems until we manage
11314 to satisfy both conditions at the same time. Note that the
11315 loop is guaranteed to terminate as every pass of the loop
11316 strictly decreases the total number of PC-relative branches
11317 in the function. (This is not completely true as there
11318 might be branch-over-pool insns introduced by chunkify_start.
11319 Those never need to be split however.) */
11320
11321 for (;;)
11322 {
11323 struct constant_pool *pool = NULL;
11324
11325 /* Collect the literal pool. */
11326 if (!pool_overflow)
11327 {
11328 pool = s390_mainpool_start ();
11329 if (!pool)
11330 pool_overflow = true;
11331 }
11332
11333 /* If literal pool overflowed, start to chunkify it. */
11334 if (pool_overflow)
11335 pool = s390_chunkify_start ();
11336
11337 /* Split out-of-range branches. If this has created new
11338 literal pool entries, cancel current chunk list and
11339 recompute it. zSeries machines have large branch
11340 instructions, so we never need to split a branch. */
11341 if (!TARGET_CPU_ZARCH && s390_split_branches ())
11342 {
11343 if (pool_overflow)
11344 s390_chunkify_cancel (pool);
11345 else
11346 s390_mainpool_cancel (pool);
11347
11348 continue;
11349 }
11350
11351 /* If we made it up to here, both conditions are satisfied.
11352 Finish up literal pool related changes. */
11353 if (pool_overflow)
11354 s390_chunkify_finish (pool);
11355 else
11356 s390_mainpool_finish (pool);
11357
11358 /* We're done splitting branches. */
11359 cfun->machine->split_branches_pending_p = false;
11360 break;
11361 }
11362
11363 /* Generate out-of-pool execute target insns. */
11364 if (TARGET_CPU_ZARCH)
11365 {
11366 rtx_insn *insn, *target;
11367 rtx label;
11368
11369 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11370 {
11371 label = s390_execute_label (insn);
11372 if (!label)
11373 continue;
11374
11375 gcc_assert (label != const0_rtx);
11376
11377 target = emit_label (XEXP (label, 0));
11378 INSN_ADDRESSES_NEW (target, -1);
11379
11380 target = emit_insn (s390_execute_target (insn));
11381 INSN_ADDRESSES_NEW (target, -1);
11382 }
11383 }
11384
11385 /* Try to optimize prologue and epilogue further. */
11386 s390_optimize_prologue ();
11387
11388 /* Walk over the insns and do some >=z10 specific changes. */
11389 if (s390_tune == PROCESSOR_2097_Z10
11390 || s390_tune == PROCESSOR_2817_Z196
11391 || s390_tune == PROCESSOR_2827_ZEC12)
11392 {
11393 rtx_insn *insn;
11394 bool insn_added_p = false;
11395
11396 /* The insn lengths and addresses have to be up to date for the
11397 following manipulations. */
11398 shorten_branches (get_insns ());
11399
11400 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11401 {
11402 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
11403 continue;
11404
11405 if (JUMP_P (insn))
11406 insn_added_p |= s390_fix_long_loop_prediction (insn);
11407
11408 if ((GET_CODE (PATTERN (insn)) == PARALLEL
11409 || GET_CODE (PATTERN (insn)) == SET)
11410 && s390_tune == PROCESSOR_2097_Z10)
11411 insn_added_p |= s390_z10_optimize_cmp (insn);
11412 }
11413
11414 /* Adjust branches if we added new instructions. */
11415 if (insn_added_p)
11416 shorten_branches (get_insns ());
11417 }
11418 }
11419
11420 /* Return true if INSN is a fp load insn writing register REGNO. */
11421 static inline bool
11422 s390_fpload_toreg (rtx_insn *insn, unsigned int regno)
11423 {
11424 rtx set;
11425 enum attr_type flag = s390_safe_attr_type (insn);
11426
11427 if (flag != TYPE_FLOADSF && flag != TYPE_FLOADDF)
11428 return false;
11429
11430 set = single_set (insn);
11431
11432 if (set == NULL_RTX)
11433 return false;
11434
11435 if (!REG_P (SET_DEST (set)) || !MEM_P (SET_SRC (set)))
11436 return false;
11437
11438 if (REGNO (SET_DEST (set)) != regno)
11439 return false;
11440
11441 return true;
11442 }
11443
11444 /* This value describes the distance to be avoided between an
11445 aritmetic fp instruction and an fp load writing the same register.
11446 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
11447 fine but the exact value has to be avoided. Otherwise the FP
11448 pipeline will throw an exception causing a major penalty. */
11449 #define Z10_EARLYLOAD_DISTANCE 7
11450
11451 /* Rearrange the ready list in order to avoid the situation described
11452 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
11453 moved to the very end of the ready list. */
11454 static void
11455 s390_z10_prevent_earlyload_conflicts (rtx_insn **ready, int *nready_p)
11456 {
11457 unsigned int regno;
11458 int nready = *nready_p;
11459 rtx_insn *tmp;
11460 int i;
11461 rtx_insn *insn;
11462 rtx set;
11463 enum attr_type flag;
11464 int distance;
11465
11466 /* Skip DISTANCE - 1 active insns. */
11467 for (insn = last_scheduled_insn, distance = Z10_EARLYLOAD_DISTANCE - 1;
11468 distance > 0 && insn != NULL_RTX;
11469 distance--, insn = prev_active_insn (insn))
11470 if (CALL_P (insn) || JUMP_P (insn))
11471 return;
11472
11473 if (insn == NULL_RTX)
11474 return;
11475
11476 set = single_set (insn);
11477
11478 if (set == NULL_RTX || !REG_P (SET_DEST (set))
11479 || GET_MODE_CLASS (GET_MODE (SET_DEST (set))) != MODE_FLOAT)
11480 return;
11481
11482 flag = s390_safe_attr_type (insn);
11483
11484 if (flag == TYPE_FLOADSF || flag == TYPE_FLOADDF)
11485 return;
11486
11487 regno = REGNO (SET_DEST (set));
11488 i = nready - 1;
11489
11490 while (!s390_fpload_toreg (ready[i], regno) && i > 0)
11491 i--;
11492
11493 if (!i)
11494 return;
11495
11496 tmp = ready[i];
11497 memmove (&ready[1], &ready[0], sizeof (rtx_insn *) * i);
11498 ready[0] = tmp;
11499 }
11500
11501
11502 /* The s390_sched_state variable tracks the state of the current or
11503 the last instruction group.
11504
11505 0,1,2 number of instructions scheduled in the current group
11506 3 the last group is complete - normal insns
11507 4 the last group was a cracked/expanded insn */
11508
11509 static int s390_sched_state;
11510
11511 #define S390_OOO_SCHED_STATE_NORMAL 3
11512 #define S390_OOO_SCHED_STATE_CRACKED 4
11513
11514 #define S390_OOO_SCHED_ATTR_MASK_CRACKED 0x1
11515 #define S390_OOO_SCHED_ATTR_MASK_EXPANDED 0x2
11516 #define S390_OOO_SCHED_ATTR_MASK_ENDGROUP 0x4
11517 #define S390_OOO_SCHED_ATTR_MASK_GROUPALONE 0x8
11518
11519 static unsigned int
11520 s390_get_sched_attrmask (rtx_insn *insn)
11521 {
11522 unsigned int mask = 0;
11523
11524 if (get_attr_ooo_cracked (insn))
11525 mask |= S390_OOO_SCHED_ATTR_MASK_CRACKED;
11526 if (get_attr_ooo_expanded (insn))
11527 mask |= S390_OOO_SCHED_ATTR_MASK_EXPANDED;
11528 if (get_attr_ooo_endgroup (insn))
11529 mask |= S390_OOO_SCHED_ATTR_MASK_ENDGROUP;
11530 if (get_attr_ooo_groupalone (insn))
11531 mask |= S390_OOO_SCHED_ATTR_MASK_GROUPALONE;
11532 return mask;
11533 }
11534
11535 /* Return the scheduling score for INSN. The higher the score the
11536 better. The score is calculated from the OOO scheduling attributes
11537 of INSN and the scheduling state s390_sched_state. */
11538 static int
11539 s390_sched_score (rtx_insn *insn)
11540 {
11541 unsigned int mask = s390_get_sched_attrmask (insn);
11542 int score = 0;
11543
11544 switch (s390_sched_state)
11545 {
11546 case 0:
11547 /* Try to put insns into the first slot which would otherwise
11548 break a group. */
11549 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) != 0
11550 || (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) != 0)
11551 score += 5;
11552 if ((mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) != 0)
11553 score += 10;
11554 case 1:
11555 /* Prefer not cracked insns while trying to put together a
11556 group. */
11557 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) == 0
11558 && (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) == 0
11559 && (mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) == 0)
11560 score += 10;
11561 if ((mask & S390_OOO_SCHED_ATTR_MASK_ENDGROUP) == 0)
11562 score += 5;
11563 break;
11564 case 2:
11565 /* Prefer not cracked insns while trying to put together a
11566 group. */
11567 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) == 0
11568 && (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) == 0
11569 && (mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) == 0)
11570 score += 10;
11571 /* Prefer endgroup insns in the last slot. */
11572 if ((mask & S390_OOO_SCHED_ATTR_MASK_ENDGROUP) != 0)
11573 score += 10;
11574 break;
11575 case S390_OOO_SCHED_STATE_NORMAL:
11576 /* Prefer not cracked insns if the last was not cracked. */
11577 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) == 0
11578 && (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) == 0)
11579 score += 5;
11580 if ((mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) != 0)
11581 score += 10;
11582 break;
11583 case S390_OOO_SCHED_STATE_CRACKED:
11584 /* Try to keep cracked insns together to prevent them from
11585 interrupting groups. */
11586 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) != 0
11587 || (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) != 0)
11588 score += 5;
11589 break;
11590 }
11591 return score;
11592 }
11593
11594 /* This function is called via hook TARGET_SCHED_REORDER before
11595 issuing one insn from list READY which contains *NREADYP entries.
11596 For target z10 it reorders load instructions to avoid early load
11597 conflicts in the floating point pipeline */
11598 static int
11599 s390_sched_reorder (FILE *file, int verbose,
11600 rtx_insn **ready, int *nreadyp, int clock ATTRIBUTE_UNUSED)
11601 {
11602 if (s390_tune == PROCESSOR_2097_Z10)
11603 if (reload_completed && *nreadyp > 1)
11604 s390_z10_prevent_earlyload_conflicts (ready, nreadyp);
11605
11606 if (s390_tune == PROCESSOR_2827_ZEC12
11607 && reload_completed
11608 && *nreadyp > 1)
11609 {
11610 int i;
11611 int last_index = *nreadyp - 1;
11612 int max_index = -1;
11613 int max_score = -1;
11614 rtx_insn *tmp;
11615
11616 /* Just move the insn with the highest score to the top (the
11617 end) of the list. A full sort is not needed since a conflict
11618 in the hazard recognition cannot happen. So the top insn in
11619 the ready list will always be taken. */
11620 for (i = last_index; i >= 0; i--)
11621 {
11622 int score;
11623
11624 if (recog_memoized (ready[i]) < 0)
11625 continue;
11626
11627 score = s390_sched_score (ready[i]);
11628 if (score > max_score)
11629 {
11630 max_score = score;
11631 max_index = i;
11632 }
11633 }
11634
11635 if (max_index != -1)
11636 {
11637 if (max_index != last_index)
11638 {
11639 tmp = ready[max_index];
11640 ready[max_index] = ready[last_index];
11641 ready[last_index] = tmp;
11642
11643 if (verbose > 5)
11644 fprintf (file,
11645 "move insn %d to the top of list\n",
11646 INSN_UID (ready[last_index]));
11647 }
11648 else if (verbose > 5)
11649 fprintf (file,
11650 "best insn %d already on top\n",
11651 INSN_UID (ready[last_index]));
11652 }
11653
11654 if (verbose > 5)
11655 {
11656 fprintf (file, "ready list ooo attributes - sched state: %d\n",
11657 s390_sched_state);
11658
11659 for (i = last_index; i >= 0; i--)
11660 {
11661 if (recog_memoized (ready[i]) < 0)
11662 continue;
11663 fprintf (file, "insn %d score: %d: ", INSN_UID (ready[i]),
11664 s390_sched_score (ready[i]));
11665 #define PRINT_OOO_ATTR(ATTR) fprintf (file, "%s ", get_attr_##ATTR (ready[i]) ? #ATTR : "!" #ATTR);
11666 PRINT_OOO_ATTR (ooo_cracked);
11667 PRINT_OOO_ATTR (ooo_expanded);
11668 PRINT_OOO_ATTR (ooo_endgroup);
11669 PRINT_OOO_ATTR (ooo_groupalone);
11670 #undef PRINT_OOO_ATTR
11671 fprintf (file, "\n");
11672 }
11673 }
11674 }
11675
11676 return s390_issue_rate ();
11677 }
11678
11679
11680 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
11681 the scheduler has issued INSN. It stores the last issued insn into
11682 last_scheduled_insn in order to make it available for
11683 s390_sched_reorder. */
11684 static int
11685 s390_sched_variable_issue (FILE *file, int verbose, rtx_insn *insn, int more)
11686 {
11687 last_scheduled_insn = insn;
11688
11689 if (s390_tune == PROCESSOR_2827_ZEC12
11690 && reload_completed
11691 && recog_memoized (insn) >= 0)
11692 {
11693 unsigned int mask = s390_get_sched_attrmask (insn);
11694
11695 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) != 0
11696 || (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) != 0)
11697 s390_sched_state = S390_OOO_SCHED_STATE_CRACKED;
11698 else if ((mask & S390_OOO_SCHED_ATTR_MASK_ENDGROUP) != 0
11699 || (mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) != 0)
11700 s390_sched_state = S390_OOO_SCHED_STATE_NORMAL;
11701 else
11702 {
11703 /* Only normal insns are left (mask == 0). */
11704 switch (s390_sched_state)
11705 {
11706 case 0:
11707 case 1:
11708 case 2:
11709 case S390_OOO_SCHED_STATE_NORMAL:
11710 if (s390_sched_state == S390_OOO_SCHED_STATE_NORMAL)
11711 s390_sched_state = 1;
11712 else
11713 s390_sched_state++;
11714
11715 break;
11716 case S390_OOO_SCHED_STATE_CRACKED:
11717 s390_sched_state = S390_OOO_SCHED_STATE_NORMAL;
11718 break;
11719 }
11720 }
11721 if (verbose > 5)
11722 {
11723 fprintf (file, "insn %d: ", INSN_UID (insn));
11724 #define PRINT_OOO_ATTR(ATTR) \
11725 fprintf (file, "%s ", get_attr_##ATTR (insn) ? #ATTR : "");
11726 PRINT_OOO_ATTR (ooo_cracked);
11727 PRINT_OOO_ATTR (ooo_expanded);
11728 PRINT_OOO_ATTR (ooo_endgroup);
11729 PRINT_OOO_ATTR (ooo_groupalone);
11730 #undef PRINT_OOO_ATTR
11731 fprintf (file, "\n");
11732 fprintf (file, "sched state: %d\n", s390_sched_state);
11733 }
11734 }
11735
11736 if (GET_CODE (PATTERN (insn)) != USE
11737 && GET_CODE (PATTERN (insn)) != CLOBBER)
11738 return more - 1;
11739 else
11740 return more;
11741 }
11742
11743 static void
11744 s390_sched_init (FILE *file ATTRIBUTE_UNUSED,
11745 int verbose ATTRIBUTE_UNUSED,
11746 int max_ready ATTRIBUTE_UNUSED)
11747 {
11748 last_scheduled_insn = NULL;
11749 s390_sched_state = 0;
11750 }
11751
11752 /* This function checks the whole of insn X for memory references. The
11753 function always returns zero because the framework it is called
11754 from would stop recursively analyzing the insn upon a return value
11755 other than zero. The real result of this function is updating
11756 counter variable MEM_COUNT. */
11757 static int
11758 check_dpu (rtx *x, unsigned *mem_count)
11759 {
11760 if (*x != NULL_RTX && MEM_P (*x))
11761 (*mem_count)++;
11762 return 0;
11763 }
11764
11765 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
11766 a new number struct loop *loop should be unrolled if tuned for cpus with
11767 a built-in stride prefetcher.
11768 The loop is analyzed for memory accesses by calling check_dpu for
11769 each rtx of the loop. Depending on the loop_depth and the amount of
11770 memory accesses a new number <=nunroll is returned to improve the
11771 behaviour of the hardware prefetch unit. */
11772 static unsigned
11773 s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop)
11774 {
11775 basic_block *bbs;
11776 rtx_insn *insn;
11777 unsigned i;
11778 unsigned mem_count = 0;
11779
11780 if (s390_tune != PROCESSOR_2097_Z10
11781 && s390_tune != PROCESSOR_2817_Z196
11782 && s390_tune != PROCESSOR_2827_ZEC12)
11783 return nunroll;
11784
11785 /* Count the number of memory references within the loop body. */
11786 bbs = get_loop_body (loop);
11787 for (i = 0; i < loop->num_nodes; i++)
11788 {
11789 for (insn = BB_HEAD (bbs[i]); insn != BB_END (bbs[i]); insn = NEXT_INSN (insn))
11790 if (INSN_P (insn) && INSN_CODE (insn) != -1)
11791 for_each_rtx_in_insn (&insn, (rtx_function) check_dpu, &mem_count);
11792 }
11793 free (bbs);
11794
11795 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
11796 if (mem_count == 0)
11797 return nunroll;
11798
11799 switch (loop_depth(loop))
11800 {
11801 case 1:
11802 return MIN (nunroll, 28 / mem_count);
11803 case 2:
11804 return MIN (nunroll, 22 / mem_count);
11805 default:
11806 return MIN (nunroll, 16 / mem_count);
11807 }
11808 }
11809
11810 static void
11811 s390_option_override (void)
11812 {
11813 unsigned int i;
11814 cl_deferred_option *opt;
11815 vec<cl_deferred_option> *v =
11816 (vec<cl_deferred_option> *) s390_deferred_options;
11817
11818 if (v)
11819 FOR_EACH_VEC_ELT (*v, i, opt)
11820 {
11821 switch (opt->opt_index)
11822 {
11823 case OPT_mhotpatch:
11824 s390_hotpatch_trampoline_halfwords = (opt->value) ?
11825 s390_hotpatch_trampoline_halfwords_default : -1;
11826 break;
11827 case OPT_mhotpatch_:
11828 {
11829 int val;
11830
11831 val = integral_argument (opt->arg);
11832 if (val == -1)
11833 {
11834 /* argument is not a plain number */
11835 error ("argument to %qs should be a non-negative integer",
11836 "-mhotpatch=");
11837 break;
11838 }
11839 else if (val > s390_hotpatch_trampoline_halfwords_max)
11840 {
11841 error ("argument to %qs is too large (max. %d)",
11842 "-mhotpatch=", s390_hotpatch_trampoline_halfwords_max);
11843 break;
11844 }
11845 s390_hotpatch_trampoline_halfwords = val;
11846 break;
11847 }
11848 default:
11849 gcc_unreachable ();
11850 }
11851 }
11852
11853 /* Set up function hooks. */
11854 init_machine_status = s390_init_machine_status;
11855
11856 /* Architecture mode defaults according to ABI. */
11857 if (!(target_flags_explicit & MASK_ZARCH))
11858 {
11859 if (TARGET_64BIT)
11860 target_flags |= MASK_ZARCH;
11861 else
11862 target_flags &= ~MASK_ZARCH;
11863 }
11864
11865 /* Set the march default in case it hasn't been specified on
11866 cmdline. */
11867 if (s390_arch == PROCESSOR_max)
11868 {
11869 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
11870 s390_arch = TARGET_ZARCH ? PROCESSOR_2064_Z900 : PROCESSOR_9672_G5;
11871 s390_arch_flags = processor_flags_table[(int)s390_arch];
11872 }
11873
11874 /* Determine processor to tune for. */
11875 if (s390_tune == PROCESSOR_max)
11876 {
11877 s390_tune = s390_arch;
11878 s390_tune_flags = s390_arch_flags;
11879 }
11880
11881 /* Sanity checks. */
11882 if (TARGET_ZARCH && !TARGET_CPU_ZARCH)
11883 error ("z/Architecture mode not supported on %s", s390_arch_string);
11884 if (TARGET_64BIT && !TARGET_ZARCH)
11885 error ("64-bit ABI not supported in ESA/390 mode");
11886
11887 /* Use hardware DFP if available and not explicitly disabled by
11888 user. E.g. with -m31 -march=z10 -mzarch */
11889 if (!(target_flags_explicit & MASK_HARD_DFP) && TARGET_DFP)
11890 target_flags |= MASK_HARD_DFP;
11891
11892 /* Enable hardware transactions if available and not explicitly
11893 disabled by user. E.g. with -m31 -march=zEC12 -mzarch */
11894 if (!(target_flags_explicit & MASK_OPT_HTM) && TARGET_CPU_HTM && TARGET_ZARCH)
11895 target_flags |= MASK_OPT_HTM;
11896
11897 if (TARGET_HARD_DFP && !TARGET_DFP)
11898 {
11899 if (target_flags_explicit & MASK_HARD_DFP)
11900 {
11901 if (!TARGET_CPU_DFP)
11902 error ("hardware decimal floating point instructions"
11903 " not available on %s", s390_arch_string);
11904 if (!TARGET_ZARCH)
11905 error ("hardware decimal floating point instructions"
11906 " not available in ESA/390 mode");
11907 }
11908 else
11909 target_flags &= ~MASK_HARD_DFP;
11910 }
11911
11912 if ((target_flags_explicit & MASK_SOFT_FLOAT) && TARGET_SOFT_FLOAT)
11913 {
11914 if ((target_flags_explicit & MASK_HARD_DFP) && TARGET_HARD_DFP)
11915 error ("-mhard-dfp can%'t be used in conjunction with -msoft-float");
11916
11917 target_flags &= ~MASK_HARD_DFP;
11918 }
11919
11920 /* Set processor cost function. */
11921 switch (s390_tune)
11922 {
11923 case PROCESSOR_2084_Z990:
11924 s390_cost = &z990_cost;
11925 break;
11926 case PROCESSOR_2094_Z9_109:
11927 s390_cost = &z9_109_cost;
11928 break;
11929 case PROCESSOR_2097_Z10:
11930 s390_cost = &z10_cost;
11931 break;
11932 case PROCESSOR_2817_Z196:
11933 s390_cost = &z196_cost;
11934 break;
11935 case PROCESSOR_2827_ZEC12:
11936 s390_cost = &zEC12_cost;
11937 break;
11938 default:
11939 s390_cost = &z900_cost;
11940 }
11941
11942 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
11943 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
11944 "in combination");
11945
11946 if (s390_stack_size)
11947 {
11948 if (s390_stack_guard >= s390_stack_size)
11949 error ("stack size must be greater than the stack guard value");
11950 else if (s390_stack_size > 1 << 16)
11951 error ("stack size must not be greater than 64k");
11952 }
11953 else if (s390_stack_guard)
11954 error ("-mstack-guard implies use of -mstack-size");
11955
11956 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
11957 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
11958 target_flags |= MASK_LONG_DOUBLE_128;
11959 #endif
11960
11961 if (s390_tune == PROCESSOR_2097_Z10
11962 || s390_tune == PROCESSOR_2817_Z196
11963 || s390_tune == PROCESSOR_2827_ZEC12)
11964 {
11965 maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS, 100,
11966 global_options.x_param_values,
11967 global_options_set.x_param_values);
11968 maybe_set_param_value (PARAM_MAX_UNROLL_TIMES, 32,
11969 global_options.x_param_values,
11970 global_options_set.x_param_values);
11971 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 2000,
11972 global_options.x_param_values,
11973 global_options_set.x_param_values);
11974 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES, 64,
11975 global_options.x_param_values,
11976 global_options_set.x_param_values);
11977 }
11978
11979 maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH, 256,
11980 global_options.x_param_values,
11981 global_options_set.x_param_values);
11982 /* values for loop prefetching */
11983 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE, 256,
11984 global_options.x_param_values,
11985 global_options_set.x_param_values);
11986 maybe_set_param_value (PARAM_L1_CACHE_SIZE, 128,
11987 global_options.x_param_values,
11988 global_options_set.x_param_values);
11989 /* s390 has more than 2 levels and the size is much larger. Since
11990 we are always running virtualized assume that we only get a small
11991 part of the caches above l1. */
11992 maybe_set_param_value (PARAM_L2_CACHE_SIZE, 1500,
11993 global_options.x_param_values,
11994 global_options_set.x_param_values);
11995 maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO, 2,
11996 global_options.x_param_values,
11997 global_options_set.x_param_values);
11998 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES, 6,
11999 global_options.x_param_values,
12000 global_options_set.x_param_values);
12001
12002 /* This cannot reside in s390_option_optimization_table since HAVE_prefetch
12003 requires the arch flags to be evaluated already. Since prefetching
12004 is beneficial on s390, we enable it if available. */
12005 if (flag_prefetch_loop_arrays < 0 && HAVE_prefetch && optimize >= 3)
12006 flag_prefetch_loop_arrays = 1;
12007
12008 /* Use the alternative scheduling-pressure algorithm by default. */
12009 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM, 2,
12010 global_options.x_param_values,
12011 global_options_set.x_param_values);
12012
12013 if (TARGET_TPF)
12014 {
12015 /* Don't emit DWARF3/4 unless specifically selected. The TPF
12016 debuggers do not yet support DWARF 3/4. */
12017 if (!global_options_set.x_dwarf_strict)
12018 dwarf_strict = 1;
12019 if (!global_options_set.x_dwarf_version)
12020 dwarf_version = 2;
12021 }
12022
12023 /* Register a target-specific optimization-and-lowering pass
12024 to run immediately before prologue and epilogue generation.
12025
12026 Registering the pass must be done at start up. It's
12027 convenient to do it here. */
12028 opt_pass *new_pass = new pass_s390_early_mach (g);
12029 struct register_pass_info insert_pass_s390_early_mach =
12030 {
12031 new_pass, /* pass */
12032 "pro_and_epilogue", /* reference_pass_name */
12033 1, /* ref_pass_instance_number */
12034 PASS_POS_INSERT_BEFORE /* po_op */
12035 };
12036 register_pass (&insert_pass_s390_early_mach);
12037 }
12038
12039 /* Initialize GCC target structure. */
12040
12041 #undef TARGET_ASM_ALIGNED_HI_OP
12042 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
12043 #undef TARGET_ASM_ALIGNED_DI_OP
12044 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
12045 #undef TARGET_ASM_INTEGER
12046 #define TARGET_ASM_INTEGER s390_assemble_integer
12047
12048 #undef TARGET_ASM_OPEN_PAREN
12049 #define TARGET_ASM_OPEN_PAREN ""
12050
12051 #undef TARGET_ASM_CLOSE_PAREN
12052 #define TARGET_ASM_CLOSE_PAREN ""
12053
12054 #undef TARGET_OPTION_OVERRIDE
12055 #define TARGET_OPTION_OVERRIDE s390_option_override
12056
12057 #undef TARGET_ENCODE_SECTION_INFO
12058 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
12059
12060 #undef TARGET_SCALAR_MODE_SUPPORTED_P
12061 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
12062
12063 #ifdef HAVE_AS_TLS
12064 #undef TARGET_HAVE_TLS
12065 #define TARGET_HAVE_TLS true
12066 #endif
12067 #undef TARGET_CANNOT_FORCE_CONST_MEM
12068 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
12069
12070 #undef TARGET_DELEGITIMIZE_ADDRESS
12071 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
12072
12073 #undef TARGET_LEGITIMIZE_ADDRESS
12074 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
12075
12076 #undef TARGET_RETURN_IN_MEMORY
12077 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
12078
12079 #undef TARGET_INIT_BUILTINS
12080 #define TARGET_INIT_BUILTINS s390_init_builtins
12081 #undef TARGET_EXPAND_BUILTIN
12082 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
12083
12084 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
12085 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA s390_output_addr_const_extra
12086
12087 #undef TARGET_ASM_OUTPUT_MI_THUNK
12088 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
12089 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
12090 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
12091
12092 #undef TARGET_SCHED_ADJUST_PRIORITY
12093 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
12094 #undef TARGET_SCHED_ISSUE_RATE
12095 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
12096 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
12097 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
12098
12099 #undef TARGET_SCHED_VARIABLE_ISSUE
12100 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
12101 #undef TARGET_SCHED_REORDER
12102 #define TARGET_SCHED_REORDER s390_sched_reorder
12103 #undef TARGET_SCHED_INIT
12104 #define TARGET_SCHED_INIT s390_sched_init
12105
12106 #undef TARGET_CANNOT_COPY_INSN_P
12107 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
12108 #undef TARGET_RTX_COSTS
12109 #define TARGET_RTX_COSTS s390_rtx_costs
12110 #undef TARGET_ADDRESS_COST
12111 #define TARGET_ADDRESS_COST s390_address_cost
12112 #undef TARGET_REGISTER_MOVE_COST
12113 #define TARGET_REGISTER_MOVE_COST s390_register_move_cost
12114 #undef TARGET_MEMORY_MOVE_COST
12115 #define TARGET_MEMORY_MOVE_COST s390_memory_move_cost
12116
12117 #undef TARGET_MACHINE_DEPENDENT_REORG
12118 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
12119
12120 #undef TARGET_VALID_POINTER_MODE
12121 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
12122
12123 #undef TARGET_BUILD_BUILTIN_VA_LIST
12124 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
12125 #undef TARGET_EXPAND_BUILTIN_VA_START
12126 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
12127 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
12128 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
12129
12130 #undef TARGET_PROMOTE_FUNCTION_MODE
12131 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
12132 #undef TARGET_PASS_BY_REFERENCE
12133 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
12134
12135 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
12136 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
12137 #undef TARGET_FUNCTION_ARG
12138 #define TARGET_FUNCTION_ARG s390_function_arg
12139 #undef TARGET_FUNCTION_ARG_ADVANCE
12140 #define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance
12141 #undef TARGET_FUNCTION_VALUE
12142 #define TARGET_FUNCTION_VALUE s390_function_value
12143 #undef TARGET_LIBCALL_VALUE
12144 #define TARGET_LIBCALL_VALUE s390_libcall_value
12145
12146 #undef TARGET_KEEP_LEAF_WHEN_PROFILED
12147 #define TARGET_KEEP_LEAF_WHEN_PROFILED s390_keep_leaf_when_profiled
12148
12149 #undef TARGET_FIXED_CONDITION_CODE_REGS
12150 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
12151
12152 #undef TARGET_CC_MODES_COMPATIBLE
12153 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
12154
12155 #undef TARGET_INVALID_WITHIN_DOLOOP
12156 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_insn_null
12157
12158 #ifdef HAVE_AS_TLS
12159 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
12160 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
12161 #endif
12162
12163 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
12164 #undef TARGET_MANGLE_TYPE
12165 #define TARGET_MANGLE_TYPE s390_mangle_type
12166 #endif
12167
12168 #undef TARGET_SCALAR_MODE_SUPPORTED_P
12169 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
12170
12171 #undef TARGET_PREFERRED_RELOAD_CLASS
12172 #define TARGET_PREFERRED_RELOAD_CLASS s390_preferred_reload_class
12173
12174 #undef TARGET_SECONDARY_RELOAD
12175 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
12176
12177 #undef TARGET_LIBGCC_CMP_RETURN_MODE
12178 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
12179
12180 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
12181 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
12182
12183 #undef TARGET_LEGITIMATE_ADDRESS_P
12184 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
12185
12186 #undef TARGET_LEGITIMATE_CONSTANT_P
12187 #define TARGET_LEGITIMATE_CONSTANT_P s390_legitimate_constant_p
12188
12189 #undef TARGET_LRA_P
12190 #define TARGET_LRA_P s390_lra_p
12191
12192 #undef TARGET_CAN_ELIMINATE
12193 #define TARGET_CAN_ELIMINATE s390_can_eliminate
12194
12195 #undef TARGET_CONDITIONAL_REGISTER_USAGE
12196 #define TARGET_CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage
12197
12198 #undef TARGET_LOOP_UNROLL_ADJUST
12199 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
12200
12201 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
12202 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
12203 #undef TARGET_TRAMPOLINE_INIT
12204 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
12205
12206 #undef TARGET_UNWIND_WORD_MODE
12207 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
12208
12209 #undef TARGET_CANONICALIZE_COMPARISON
12210 #define TARGET_CANONICALIZE_COMPARISON s390_canonicalize_comparison
12211
12212 #undef TARGET_HARD_REGNO_SCRATCH_OK
12213 #define TARGET_HARD_REGNO_SCRATCH_OK s390_hard_regno_scratch_ok
12214
12215 #undef TARGET_ATTRIBUTE_TABLE
12216 #define TARGET_ATTRIBUTE_TABLE s390_attribute_table
12217
12218 #undef TARGET_CAN_INLINE_P
12219 #define TARGET_CAN_INLINE_P s390_can_inline_p
12220
12221 #undef TARGET_SET_UP_BY_PROLOGUE
12222 #define TARGET_SET_UP_BY_PROLOGUE s300_set_up_by_prologue
12223
12224 struct gcc_target targetm = TARGET_INITIALIZER;
12225
12226 #include "gt-s390.h"
Mirror of https://gcc.gnu.org/git/gcc.git