1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com) and
6 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
32 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
43 #include "diagnostic-core.h"
44 #include "basic-block.h"
45 #include "integrate.h"
48 #include "target-def.h"
50 #include "langhooks.h"
58 static const int processor_flags_table
[] =
60 /* g5 */ PF_IEEE_FLOAT
,
61 /* g6 */ PF_IEEE_FLOAT
,
62 /* z900 */ PF_IEEE_FLOAT
| PF_ZARCH
,
63 /* z990 */ PF_IEEE_FLOAT
| PF_ZARCH
| PF_LONG_DISPLACEMENT
,
64 /* z9-109 */ PF_IEEE_FLOAT
| PF_ZARCH
| PF_LONG_DISPLACEMENT
66 /* z9-ec */ PF_IEEE_FLOAT
| PF_ZARCH
| PF_LONG_DISPLACEMENT
68 /* z10 */ PF_IEEE_FLOAT
| PF_ZARCH
| PF_LONG_DISPLACEMENT
69 | PF_EXTIMM
| PF_DFP
| PF_Z10
,
70 /* z196 */ PF_IEEE_FLOAT
| PF_ZARCH
| PF_LONG_DISPLACEMENT
71 | PF_EXTIMM
| PF_DFP
| PF_Z10
| PF_Z196
74 /* Define the specific costs for a given cpu. */
76 struct processor_costs
79 const int m
; /* cost of an M instruction. */
80 const int mghi
; /* cost of an MGHI instruction. */
81 const int mh
; /* cost of an MH instruction. */
82 const int mhi
; /* cost of an MHI instruction. */
83 const int ml
; /* cost of an ML instruction. */
84 const int mr
; /* cost of an MR instruction. */
85 const int ms
; /* cost of an MS instruction. */
86 const int msg
; /* cost of an MSG instruction. */
87 const int msgf
; /* cost of an MSGF instruction. */
88 const int msgfr
; /* cost of an MSGFR instruction. */
89 const int msgr
; /* cost of an MSGR instruction. */
90 const int msr
; /* cost of an MSR instruction. */
91 const int mult_df
; /* cost of multiplication in DFmode. */
94 const int sqxbr
; /* cost of square root in TFmode. */
95 const int sqdbr
; /* cost of square root in DFmode. */
96 const int sqebr
; /* cost of square root in SFmode. */
97 /* multiply and add */
98 const int madbr
; /* cost of multiply and add in DFmode. */
99 const int maebr
; /* cost of multiply and add in SFmode. */
111 const struct processor_costs
*s390_cost
;
114 struct processor_costs z900_cost
=
116 COSTS_N_INSNS (5), /* M */
117 COSTS_N_INSNS (10), /* MGHI */
118 COSTS_N_INSNS (5), /* MH */
119 COSTS_N_INSNS (4), /* MHI */
120 COSTS_N_INSNS (5), /* ML */
121 COSTS_N_INSNS (5), /* MR */
122 COSTS_N_INSNS (4), /* MS */
123 COSTS_N_INSNS (15), /* MSG */
124 COSTS_N_INSNS (7), /* MSGF */
125 COSTS_N_INSNS (7), /* MSGFR */
126 COSTS_N_INSNS (10), /* MSGR */
127 COSTS_N_INSNS (4), /* MSR */
128 COSTS_N_INSNS (7), /* multiplication in DFmode */
129 COSTS_N_INSNS (13), /* MXBR */
130 COSTS_N_INSNS (136), /* SQXBR */
131 COSTS_N_INSNS (44), /* SQDBR */
132 COSTS_N_INSNS (35), /* SQEBR */
133 COSTS_N_INSNS (18), /* MADBR */
134 COSTS_N_INSNS (13), /* MAEBR */
135 COSTS_N_INSNS (134), /* DXBR */
136 COSTS_N_INSNS (30), /* DDBR */
137 COSTS_N_INSNS (27), /* DEBR */
138 COSTS_N_INSNS (220), /* DLGR */
139 COSTS_N_INSNS (34), /* DLR */
140 COSTS_N_INSNS (34), /* DR */
141 COSTS_N_INSNS (32), /* DSGFR */
142 COSTS_N_INSNS (32), /* DSGR */
146 struct processor_costs z990_cost
=
148 COSTS_N_INSNS (4), /* M */
149 COSTS_N_INSNS (2), /* MGHI */
150 COSTS_N_INSNS (2), /* MH */
151 COSTS_N_INSNS (2), /* MHI */
152 COSTS_N_INSNS (4), /* ML */
153 COSTS_N_INSNS (4), /* MR */
154 COSTS_N_INSNS (5), /* MS */
155 COSTS_N_INSNS (6), /* MSG */
156 COSTS_N_INSNS (4), /* MSGF */
157 COSTS_N_INSNS (4), /* MSGFR */
158 COSTS_N_INSNS (4), /* MSGR */
159 COSTS_N_INSNS (4), /* MSR */
160 COSTS_N_INSNS (1), /* multiplication in DFmode */
161 COSTS_N_INSNS (28), /* MXBR */
162 COSTS_N_INSNS (130), /* SQXBR */
163 COSTS_N_INSNS (66), /* SQDBR */
164 COSTS_N_INSNS (38), /* SQEBR */
165 COSTS_N_INSNS (1), /* MADBR */
166 COSTS_N_INSNS (1), /* MAEBR */
167 COSTS_N_INSNS (60), /* DXBR */
168 COSTS_N_INSNS (40), /* DDBR */
169 COSTS_N_INSNS (26), /* DEBR */
170 COSTS_N_INSNS (176), /* DLGR */
171 COSTS_N_INSNS (31), /* DLR */
172 COSTS_N_INSNS (31), /* DR */
173 COSTS_N_INSNS (31), /* DSGFR */
174 COSTS_N_INSNS (31), /* DSGR */
178 struct processor_costs z9_109_cost
=
180 COSTS_N_INSNS (4), /* M */
181 COSTS_N_INSNS (2), /* MGHI */
182 COSTS_N_INSNS (2), /* MH */
183 COSTS_N_INSNS (2), /* MHI */
184 COSTS_N_INSNS (4), /* ML */
185 COSTS_N_INSNS (4), /* MR */
186 COSTS_N_INSNS (5), /* MS */
187 COSTS_N_INSNS (6), /* MSG */
188 COSTS_N_INSNS (4), /* MSGF */
189 COSTS_N_INSNS (4), /* MSGFR */
190 COSTS_N_INSNS (4), /* MSGR */
191 COSTS_N_INSNS (4), /* MSR */
192 COSTS_N_INSNS (1), /* multiplication in DFmode */
193 COSTS_N_INSNS (28), /* MXBR */
194 COSTS_N_INSNS (130), /* SQXBR */
195 COSTS_N_INSNS (66), /* SQDBR */
196 COSTS_N_INSNS (38), /* SQEBR */
197 COSTS_N_INSNS (1), /* MADBR */
198 COSTS_N_INSNS (1), /* MAEBR */
199 COSTS_N_INSNS (60), /* DXBR */
200 COSTS_N_INSNS (40), /* DDBR */
201 COSTS_N_INSNS (26), /* DEBR */
202 COSTS_N_INSNS (30), /* DLGR */
203 COSTS_N_INSNS (23), /* DLR */
204 COSTS_N_INSNS (23), /* DR */
205 COSTS_N_INSNS (24), /* DSGFR */
206 COSTS_N_INSNS (24), /* DSGR */
210 struct processor_costs z10_cost
=
212 COSTS_N_INSNS (10), /* M */
213 COSTS_N_INSNS (10), /* MGHI */
214 COSTS_N_INSNS (10), /* MH */
215 COSTS_N_INSNS (10), /* MHI */
216 COSTS_N_INSNS (10), /* ML */
217 COSTS_N_INSNS (10), /* MR */
218 COSTS_N_INSNS (10), /* MS */
219 COSTS_N_INSNS (10), /* MSG */
220 COSTS_N_INSNS (10), /* MSGF */
221 COSTS_N_INSNS (10), /* MSGFR */
222 COSTS_N_INSNS (10), /* MSGR */
223 COSTS_N_INSNS (10), /* MSR */
224 COSTS_N_INSNS (1) , /* multiplication in DFmode */
225 COSTS_N_INSNS (50), /* MXBR */
226 COSTS_N_INSNS (120), /* SQXBR */
227 COSTS_N_INSNS (52), /* SQDBR */
228 COSTS_N_INSNS (38), /* SQEBR */
229 COSTS_N_INSNS (1), /* MADBR */
230 COSTS_N_INSNS (1), /* MAEBR */
231 COSTS_N_INSNS (111), /* DXBR */
232 COSTS_N_INSNS (39), /* DDBR */
233 COSTS_N_INSNS (32), /* DEBR */
234 COSTS_N_INSNS (160), /* DLGR */
235 COSTS_N_INSNS (71), /* DLR */
236 COSTS_N_INSNS (71), /* DR */
237 COSTS_N_INSNS (71), /* DSGFR */
238 COSTS_N_INSNS (71), /* DSGR */
242 struct processor_costs z196_cost
=
244 COSTS_N_INSNS (7), /* M */
245 COSTS_N_INSNS (5), /* MGHI */
246 COSTS_N_INSNS (5), /* MH */
247 COSTS_N_INSNS (5), /* MHI */
248 COSTS_N_INSNS (7), /* ML */
249 COSTS_N_INSNS (7), /* MR */
250 COSTS_N_INSNS (6), /* MS */
251 COSTS_N_INSNS (8), /* MSG */
252 COSTS_N_INSNS (6), /* MSGF */
253 COSTS_N_INSNS (6), /* MSGFR */
254 COSTS_N_INSNS (8), /* MSGR */
255 COSTS_N_INSNS (6), /* MSR */
256 COSTS_N_INSNS (1) , /* multiplication in DFmode */
257 COSTS_N_INSNS (40), /* MXBR B+40 */
258 COSTS_N_INSNS (100), /* SQXBR B+100 */
259 COSTS_N_INSNS (42), /* SQDBR B+42 */
260 COSTS_N_INSNS (28), /* SQEBR B+28 */
261 COSTS_N_INSNS (1), /* MADBR B */
262 COSTS_N_INSNS (1), /* MAEBR B */
263 COSTS_N_INSNS (101), /* DXBR B+101 */
264 COSTS_N_INSNS (29), /* DDBR */
265 COSTS_N_INSNS (22), /* DEBR */
266 COSTS_N_INSNS (160), /* DLGR cracked */
267 COSTS_N_INSNS (160), /* DLR cracked */
268 COSTS_N_INSNS (160), /* DR expanded */
269 COSTS_N_INSNS (160), /* DSGFR cracked */
270 COSTS_N_INSNS (160), /* DSGR cracked */
273 extern int reload_completed
;
275 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
276 static rtx last_scheduled_insn
;
278 /* Structure used to hold the components of a S/390 memory
279 address. A legitimate address on S/390 is of the general
281 base + index + displacement
282 where any of the components is optional.
284 base and index are registers of the class ADDR_REGS,
285 displacement is an unsigned 12-bit immediate constant. */
296 /* The following structure is embedded in the machine
297 specific part of struct function. */
299 struct GTY (()) s390_frame_layout
301 /* Offset within stack frame. */
302 HOST_WIDE_INT gprs_offset
;
303 HOST_WIDE_INT f0_offset
;
304 HOST_WIDE_INT f4_offset
;
305 HOST_WIDE_INT f8_offset
;
306 HOST_WIDE_INT backchain_offset
;
308 /* Number of first and last gpr where slots in the register
309 save area are reserved for. */
310 int first_save_gpr_slot
;
311 int last_save_gpr_slot
;
313 /* Number of first and last gpr to be saved, restored. */
315 int first_restore_gpr
;
317 int last_restore_gpr
;
319 /* Bits standing for floating point registers. Set, if the
320 respective register has to be saved. Starting with reg 16 (f0)
321 at the rightmost bit.
322 Bit 15 - 8 7 6 5 4 3 2 1 0
323 fpr 15 - 8 7 5 3 1 6 4 2 0
324 reg 31 - 24 23 22 21 20 19 18 17 16 */
325 unsigned int fpr_bitmap
;
327 /* Number of floating point registers f8-f15 which must be saved. */
330 /* Set if return address needs to be saved.
331 This flag is set by s390_return_addr_rtx if it could not use
332 the initial value of r14 and therefore depends on r14 saved
334 bool save_return_addr_p
;
336 /* Size of stack frame. */
337 HOST_WIDE_INT frame_size
;
340 /* Define the structure for the machine field in struct function. */
342 struct GTY(()) machine_function
344 struct s390_frame_layout frame_layout
;
346 /* Literal pool base register. */
349 /* True if we may need to perform branch splitting. */
350 bool split_branches_pending_p
;
352 /* Some local-dynamic TLS symbol name. */
353 const char *some_ld_name
;
355 bool has_landing_pad_p
;
358 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
360 #define cfun_frame_layout (cfun->machine->frame_layout)
361 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
362 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
363 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
364 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
366 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
369 /* Number of GPRs and FPRs used for argument passing. */
370 #define GP_ARG_NUM_REG 5
371 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
373 /* A couple of shortcuts. */
374 #define CONST_OK_FOR_J(x) \
375 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
376 #define CONST_OK_FOR_K(x) \
377 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
378 #define CONST_OK_FOR_Os(x) \
379 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
380 #define CONST_OK_FOR_Op(x) \
381 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
382 #define CONST_OK_FOR_On(x) \
383 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
385 #define REGNO_PAIR_OK(REGNO, MODE) \
386 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
388 /* That's the read ahead of the dynamic branch prediction unit in
389 bytes on a z10 (or higher) CPU. */
390 #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
392 /* Return the alignment for LABEL. We default to the -falign-labels
393 value except for the literal pool base label. */
395 s390_label_align (rtx label
)
397 rtx prev_insn
= prev_active_insn (label
);
399 if (prev_insn
== NULL_RTX
)
402 prev_insn
= single_set (prev_insn
);
404 if (prev_insn
== NULL_RTX
)
407 prev_insn
= SET_SRC (prev_insn
);
409 /* Don't align literal pool base labels. */
410 if (GET_CODE (prev_insn
) == UNSPEC
411 && XINT (prev_insn
, 1) == UNSPEC_MAIN_BASE
)
415 return align_labels_log
;
418 static enum machine_mode
419 s390_libgcc_cmp_return_mode (void)
421 return TARGET_64BIT
? DImode
: SImode
;
424 static enum machine_mode
425 s390_libgcc_shift_count_mode (void)
427 return TARGET_64BIT
? DImode
: SImode
;
430 static enum machine_mode
431 s390_unwind_word_mode (void)
433 return TARGET_64BIT
? DImode
: SImode
;
436 /* Return true if the back end supports mode MODE. */
438 s390_scalar_mode_supported_p (enum machine_mode mode
)
440 /* In contrast to the default implementation reject TImode constants on 31bit
441 TARGET_ZARCH for ABI compliance. */
442 if (!TARGET_64BIT
&& TARGET_ZARCH
&& mode
== TImode
)
445 if (DECIMAL_FLOAT_MODE_P (mode
))
446 return default_decimal_float_supported_p ();
448 return default_scalar_mode_supported_p (mode
);
451 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
454 s390_set_has_landing_pad_p (bool value
)
456 cfun
->machine
->has_landing_pad_p
= value
;
459 /* If two condition code modes are compatible, return a condition code
460 mode which is compatible with both. Otherwise, return
463 static enum machine_mode
464 s390_cc_modes_compatible (enum machine_mode m1
, enum machine_mode m2
)
472 if (m2
== CCUmode
|| m2
== CCTmode
|| m2
== CCZ1mode
473 || m2
== CCSmode
|| m2
== CCSRmode
|| m2
== CCURmode
)
494 /* Return true if SET either doesn't set the CC register, or else
495 the source and destination have matching CC modes and that
496 CC mode is at least as constrained as REQ_MODE. */
499 s390_match_ccmode_set (rtx set
, enum machine_mode req_mode
)
501 enum machine_mode set_mode
;
503 gcc_assert (GET_CODE (set
) == SET
);
505 if (GET_CODE (SET_DEST (set
)) != REG
|| !CC_REGNO_P (REGNO (SET_DEST (set
))))
508 set_mode
= GET_MODE (SET_DEST (set
));
522 if (req_mode
!= set_mode
)
527 if (req_mode
!= CCSmode
&& req_mode
!= CCUmode
&& req_mode
!= CCTmode
528 && req_mode
!= CCSRmode
&& req_mode
!= CCURmode
)
534 if (req_mode
!= CCAmode
)
542 return (GET_MODE (SET_SRC (set
)) == set_mode
);
545 /* Return true if every SET in INSN that sets the CC register
546 has source and destination with matching CC modes and that
547 CC mode is at least as constrained as REQ_MODE.
548 If REQ_MODE is VOIDmode, always return false. */
551 s390_match_ccmode (rtx insn
, enum machine_mode req_mode
)
555 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
556 if (req_mode
== VOIDmode
)
559 if (GET_CODE (PATTERN (insn
)) == SET
)
560 return s390_match_ccmode_set (PATTERN (insn
), req_mode
);
562 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
563 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
565 rtx set
= XVECEXP (PATTERN (insn
), 0, i
);
566 if (GET_CODE (set
) == SET
)
567 if (!s390_match_ccmode_set (set
, req_mode
))
574 /* If a test-under-mask instruction can be used to implement
575 (compare (and ... OP1) OP2), return the CC mode required
576 to do that. Otherwise, return VOIDmode.
577 MIXED is true if the instruction can distinguish between
578 CC1 and CC2 for mixed selected bits (TMxx), it is false
579 if the instruction cannot (TM). */
582 s390_tm_ccmode (rtx op1
, rtx op2
, bool mixed
)
586 /* ??? Fixme: should work on CONST_DOUBLE as well. */
587 if (GET_CODE (op1
) != CONST_INT
|| GET_CODE (op2
) != CONST_INT
)
590 /* Selected bits all zero: CC0.
591 e.g.: int a; if ((a & (16 + 128)) == 0) */
592 if (INTVAL (op2
) == 0)
595 /* Selected bits all one: CC3.
596 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
597 if (INTVAL (op2
) == INTVAL (op1
))
600 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
602 if ((a & (16 + 128)) == 16) -> CCT1
603 if ((a & (16 + 128)) == 128) -> CCT2 */
606 bit1
= exact_log2 (INTVAL (op2
));
607 bit0
= exact_log2 (INTVAL (op1
) ^ INTVAL (op2
));
608 if (bit0
!= -1 && bit1
!= -1)
609 return bit0
> bit1
? CCT1mode
: CCT2mode
;
615 /* Given a comparison code OP (EQ, NE, etc.) and the operands
616 OP0 and OP1 of a COMPARE, return the mode to be used for the
620 s390_select_ccmode (enum rtx_code code
, rtx op0
, rtx op1
)
626 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
627 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
629 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
630 && CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1))))
632 if ((GET_CODE (op0
) == PLUS
|| GET_CODE (op0
) == MINUS
633 || GET_CODE (op1
) == NEG
)
634 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
637 if (GET_CODE (op0
) == AND
)
639 /* Check whether we can potentially do it via TM. */
640 enum machine_mode ccmode
;
641 ccmode
= s390_tm_ccmode (XEXP (op0
, 1), op1
, 1);
642 if (ccmode
!= VOIDmode
)
644 /* Relax CCTmode to CCZmode to allow fall-back to AND
645 if that turns out to be beneficial. */
646 return ccmode
== CCTmode
? CCZmode
: ccmode
;
650 if (register_operand (op0
, HImode
)
651 && GET_CODE (op1
) == CONST_INT
652 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 65535))
654 if (register_operand (op0
, QImode
)
655 && GET_CODE (op1
) == CONST_INT
656 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 255))
665 /* The only overflow condition of NEG and ABS happens when
666 -INT_MAX is used as parameter, which stays negative. So
667 we have an overflow from a positive value to a negative.
668 Using CCAP mode the resulting cc can be used for comparisons. */
669 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
670 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
673 /* If constants are involved in an add instruction it is possible to use
674 the resulting cc for comparisons with zero. Knowing the sign of the
675 constant the overflow behavior gets predictable. e.g.:
676 int a, b; if ((b = a + c) > 0)
677 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
678 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
679 && CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1))))
681 if (INTVAL (XEXP((op0
), 1)) < 0)
695 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
696 && GET_CODE (op1
) != CONST_INT
)
702 if (GET_CODE (op0
) == PLUS
703 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
706 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
707 && GET_CODE (op1
) != CONST_INT
)
713 if (GET_CODE (op0
) == MINUS
714 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
717 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
718 && GET_CODE (op1
) != CONST_INT
)
727 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
728 that we can implement more efficiently. */
731 s390_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
)
733 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
734 if ((*code
== EQ
|| *code
== NE
)
735 && *op1
== const0_rtx
736 && GET_CODE (*op0
) == ZERO_EXTRACT
737 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
738 && GET_CODE (XEXP (*op0
, 2)) == CONST_INT
739 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
741 rtx inner
= XEXP (*op0
, 0);
742 HOST_WIDE_INT modesize
= GET_MODE_BITSIZE (GET_MODE (inner
));
743 HOST_WIDE_INT len
= INTVAL (XEXP (*op0
, 1));
744 HOST_WIDE_INT pos
= INTVAL (XEXP (*op0
, 2));
746 if (len
> 0 && len
< modesize
747 && pos
>= 0 && pos
+ len
<= modesize
748 && modesize
<= HOST_BITS_PER_WIDE_INT
)
750 unsigned HOST_WIDE_INT block
;
751 block
= ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
752 block
<<= modesize
- pos
- len
;
754 *op0
= gen_rtx_AND (GET_MODE (inner
), inner
,
755 gen_int_mode (block
, GET_MODE (inner
)));
759 /* Narrow AND of memory against immediate to enable TM. */
760 if ((*code
== EQ
|| *code
== NE
)
761 && *op1
== const0_rtx
762 && GET_CODE (*op0
) == AND
763 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
764 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
766 rtx inner
= XEXP (*op0
, 0);
767 rtx mask
= XEXP (*op0
, 1);
769 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
770 if (GET_CODE (inner
) == SUBREG
771 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner
)))
772 && (GET_MODE_SIZE (GET_MODE (inner
))
773 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner
))))
775 & GET_MODE_MASK (GET_MODE (inner
))
776 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner
))))
778 inner
= SUBREG_REG (inner
);
780 /* Do not change volatile MEMs. */
781 if (MEM_P (inner
) && !MEM_VOLATILE_P (inner
))
783 int part
= s390_single_part (XEXP (*op0
, 1),
784 GET_MODE (inner
), QImode
, 0);
787 mask
= gen_int_mode (s390_extract_part (mask
, QImode
, 0), QImode
);
788 inner
= adjust_address_nv (inner
, QImode
, part
);
789 *op0
= gen_rtx_AND (QImode
, inner
, mask
);
794 /* Narrow comparisons against 0xffff to HImode if possible. */
795 if ((*code
== EQ
|| *code
== NE
)
796 && GET_CODE (*op1
) == CONST_INT
797 && INTVAL (*op1
) == 0xffff
798 && SCALAR_INT_MODE_P (GET_MODE (*op0
))
799 && (nonzero_bits (*op0
, GET_MODE (*op0
))
800 & ~(unsigned HOST_WIDE_INT
) 0xffff) == 0)
802 *op0
= gen_lowpart (HImode
, *op0
);
806 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
807 if (GET_CODE (*op0
) == UNSPEC
808 && XINT (*op0
, 1) == UNSPEC_CCU_TO_INT
809 && XVECLEN (*op0
, 0) == 1
810 && GET_MODE (XVECEXP (*op0
, 0, 0)) == CCUmode
811 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
812 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
813 && *op1
== const0_rtx
)
815 enum rtx_code new_code
= UNKNOWN
;
818 case EQ
: new_code
= EQ
; break;
819 case NE
: new_code
= NE
; break;
820 case LT
: new_code
= GTU
; break;
821 case GT
: new_code
= LTU
; break;
822 case LE
: new_code
= GEU
; break;
823 case GE
: new_code
= LEU
; break;
827 if (new_code
!= UNKNOWN
)
829 *op0
= XVECEXP (*op0
, 0, 0);
834 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
835 if (GET_CODE (*op0
) == UNSPEC
836 && XINT (*op0
, 1) == UNSPEC_CCZ_TO_INT
837 && XVECLEN (*op0
, 0) == 1
838 && GET_MODE (XVECEXP (*op0
, 0, 0)) == CCZmode
839 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
840 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
841 && *op1
== const0_rtx
)
843 enum rtx_code new_code
= UNKNOWN
;
846 case EQ
: new_code
= EQ
; break;
847 case NE
: new_code
= NE
; break;
851 if (new_code
!= UNKNOWN
)
853 *op0
= XVECEXP (*op0
, 0, 0);
858 /* Simplify cascaded EQ, NE with const0_rtx. */
859 if ((*code
== NE
|| *code
== EQ
)
860 && (GET_CODE (*op0
) == EQ
|| GET_CODE (*op0
) == NE
)
861 && GET_MODE (*op0
) == SImode
862 && GET_MODE (XEXP (*op0
, 0)) == CCZ1mode
863 && REG_P (XEXP (*op0
, 0))
864 && XEXP (*op0
, 1) == const0_rtx
865 && *op1
== const0_rtx
)
867 if ((*code
== EQ
&& GET_CODE (*op0
) == NE
)
868 || (*code
== NE
&& GET_CODE (*op0
) == EQ
))
872 *op0
= XEXP (*op0
, 0);
875 /* Prefer register over memory as first operand. */
876 if (MEM_P (*op0
) && REG_P (*op1
))
878 rtx tem
= *op0
; *op0
= *op1
; *op1
= tem
;
879 *code
= swap_condition (*code
);
883 /* Emit a compare instruction suitable to implement the comparison
884 OP0 CODE OP1. Return the correct condition RTL to be placed in
885 the IF_THEN_ELSE of the conditional branch testing the result. */
888 s390_emit_compare (enum rtx_code code
, rtx op0
, rtx op1
)
890 enum machine_mode mode
= s390_select_ccmode (code
, op0
, op1
);
893 /* Do not output a redundant compare instruction if a compare_and_swap
894 pattern already computed the result and the machine modes are compatible. */
895 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
897 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0
), mode
)
903 cc
= gen_rtx_REG (mode
, CC_REGNUM
);
904 emit_insn (gen_rtx_SET (VOIDmode
, cc
, gen_rtx_COMPARE (mode
, op0
, op1
)));
907 return gen_rtx_fmt_ee (code
, VOIDmode
, cc
, const0_rtx
);
910 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
912 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
913 conditional branch testing the result. */
916 s390_emit_compare_and_swap (enum rtx_code code
, rtx old
, rtx mem
, rtx cmp
, rtx new_rtx
)
918 emit_insn (gen_sync_compare_and_swapsi (old
, mem
, cmp
, new_rtx
));
919 return s390_emit_compare (code
, gen_rtx_REG (CCZ1mode
, CC_REGNUM
), const0_rtx
);
922 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
923 unconditional jump, else a conditional jump under condition COND. */
926 s390_emit_jump (rtx target
, rtx cond
)
930 target
= gen_rtx_LABEL_REF (VOIDmode
, target
);
932 target
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, target
, pc_rtx
);
934 insn
= gen_rtx_SET (VOIDmode
, pc_rtx
, target
);
935 emit_jump_insn (insn
);
938 /* Return branch condition mask to implement a branch
939 specified by CODE. Return -1 for invalid comparisons. */
942 s390_branch_condition_mask (rtx code
)
944 const int CC0
= 1 << 3;
945 const int CC1
= 1 << 2;
946 const int CC2
= 1 << 1;
947 const int CC3
= 1 << 0;
949 gcc_assert (GET_CODE (XEXP (code
, 0)) == REG
);
950 gcc_assert (REGNO (XEXP (code
, 0)) == CC_REGNUM
);
951 gcc_assert (XEXP (code
, 1) == const0_rtx
);
953 switch (GET_MODE (XEXP (code
, 0)))
957 switch (GET_CODE (code
))
960 case NE
: return CC1
| CC2
| CC3
;
966 switch (GET_CODE (code
))
969 case NE
: return CC0
| CC2
| CC3
;
975 switch (GET_CODE (code
))
978 case NE
: return CC0
| CC1
| CC3
;
984 switch (GET_CODE (code
))
987 case NE
: return CC0
| CC1
| CC2
;
993 switch (GET_CODE (code
))
995 case EQ
: return CC0
| CC2
;
996 case NE
: return CC1
| CC3
;
1002 switch (GET_CODE (code
))
1004 case LTU
: return CC2
| CC3
; /* carry */
1005 case GEU
: return CC0
| CC1
; /* no carry */
1011 switch (GET_CODE (code
))
1013 case GTU
: return CC0
| CC1
; /* borrow */
1014 case LEU
: return CC2
| CC3
; /* no borrow */
1020 switch (GET_CODE (code
))
1022 case EQ
: return CC0
| CC2
;
1023 case NE
: return CC1
| CC3
;
1024 case LTU
: return CC1
;
1025 case GTU
: return CC3
;
1026 case LEU
: return CC1
| CC2
;
1027 case GEU
: return CC2
| CC3
;
1032 switch (GET_CODE (code
))
1034 case EQ
: return CC0
;
1035 case NE
: return CC1
| CC2
| CC3
;
1036 case LTU
: return CC1
;
1037 case GTU
: return CC2
;
1038 case LEU
: return CC0
| CC1
;
1039 case GEU
: return CC0
| CC2
;
1045 switch (GET_CODE (code
))
1047 case EQ
: return CC0
;
1048 case NE
: return CC2
| CC1
| CC3
;
1049 case LTU
: return CC2
;
1050 case GTU
: return CC1
;
1051 case LEU
: return CC0
| CC2
;
1052 case GEU
: return CC0
| CC1
;
1058 switch (GET_CODE (code
))
1060 case EQ
: return CC0
;
1061 case NE
: return CC1
| CC2
| CC3
;
1062 case LT
: return CC1
| CC3
;
1063 case GT
: return CC2
;
1064 case LE
: return CC0
| CC1
| CC3
;
1065 case GE
: return CC0
| CC2
;
1071 switch (GET_CODE (code
))
1073 case EQ
: return CC0
;
1074 case NE
: return CC1
| CC2
| CC3
;
1075 case LT
: return CC1
;
1076 case GT
: return CC2
| CC3
;
1077 case LE
: return CC0
| CC1
;
1078 case GE
: return CC0
| CC2
| CC3
;
1084 switch (GET_CODE (code
))
1086 case EQ
: return CC0
;
1087 case NE
: return CC1
| CC2
| CC3
;
1088 case LT
: return CC1
;
1089 case GT
: return CC2
;
1090 case LE
: return CC0
| CC1
;
1091 case GE
: return CC0
| CC2
;
1092 case UNORDERED
: return CC3
;
1093 case ORDERED
: return CC0
| CC1
| CC2
;
1094 case UNEQ
: return CC0
| CC3
;
1095 case UNLT
: return CC1
| CC3
;
1096 case UNGT
: return CC2
| CC3
;
1097 case UNLE
: return CC0
| CC1
| CC3
;
1098 case UNGE
: return CC0
| CC2
| CC3
;
1099 case LTGT
: return CC1
| CC2
;
1105 switch (GET_CODE (code
))
1107 case EQ
: return CC0
;
1108 case NE
: return CC2
| CC1
| CC3
;
1109 case LT
: return CC2
;
1110 case GT
: return CC1
;
1111 case LE
: return CC0
| CC2
;
1112 case GE
: return CC0
| CC1
;
1113 case UNORDERED
: return CC3
;
1114 case ORDERED
: return CC0
| CC2
| CC1
;
1115 case UNEQ
: return CC0
| CC3
;
1116 case UNLT
: return CC2
| CC3
;
1117 case UNGT
: return CC1
| CC3
;
1118 case UNLE
: return CC0
| CC2
| CC3
;
1119 case UNGE
: return CC0
| CC1
| CC3
;
1120 case LTGT
: return CC2
| CC1
;
1131 /* Return branch condition mask to implement a compare and branch
1132 specified by CODE. Return -1 for invalid comparisons. */
1135 s390_compare_and_branch_condition_mask (rtx code
)
1137 const int CC0
= 1 << 3;
1138 const int CC1
= 1 << 2;
1139 const int CC2
= 1 << 1;
1141 switch (GET_CODE (code
))
1165 /* If INV is false, return assembler mnemonic string to implement
1166 a branch specified by CODE. If INV is true, return mnemonic
1167 for the corresponding inverted branch. */
1170 s390_branch_condition_mnemonic (rtx code
, int inv
)
1174 static const char *const mnemonic
[16] =
1176 NULL
, "o", "h", "nle",
1177 "l", "nhe", "lh", "ne",
1178 "e", "nlh", "he", "nl",
1179 "le", "nh", "no", NULL
1182 if (GET_CODE (XEXP (code
, 0)) == REG
1183 && REGNO (XEXP (code
, 0)) == CC_REGNUM
1184 && XEXP (code
, 1) == const0_rtx
)
1185 mask
= s390_branch_condition_mask (code
);
1187 mask
= s390_compare_and_branch_condition_mask (code
);
1189 gcc_assert (mask
>= 0);
1194 gcc_assert (mask
>= 1 && mask
<= 14);
1196 return mnemonic
[mask
];
1199 /* Return the part of op which has a value different from def.
1200 The size of the part is determined by mode.
1201 Use this function only if you already know that op really
1202 contains such a part. */
1204 unsigned HOST_WIDE_INT
1205 s390_extract_part (rtx op
, enum machine_mode mode
, int def
)
1207 unsigned HOST_WIDE_INT value
= 0;
1208 int max_parts
= HOST_BITS_PER_WIDE_INT
/ GET_MODE_BITSIZE (mode
);
1209 int part_bits
= GET_MODE_BITSIZE (mode
);
1210 unsigned HOST_WIDE_INT part_mask
1211 = ((unsigned HOST_WIDE_INT
)1 << part_bits
) - 1;
1214 for (i
= 0; i
< max_parts
; i
++)
1217 value
= (unsigned HOST_WIDE_INT
) INTVAL (op
);
1219 value
>>= part_bits
;
1221 if ((value
& part_mask
) != (def
& part_mask
))
1222 return value
& part_mask
;
1228 /* If OP is an integer constant of mode MODE with exactly one
1229 part of mode PART_MODE unequal to DEF, return the number of that
1230 part. Otherwise, return -1. */
1233 s390_single_part (rtx op
,
1234 enum machine_mode mode
,
1235 enum machine_mode part_mode
,
1238 unsigned HOST_WIDE_INT value
= 0;
1239 int n_parts
= GET_MODE_SIZE (mode
) / GET_MODE_SIZE (part_mode
);
1240 unsigned HOST_WIDE_INT part_mask
1241 = ((unsigned HOST_WIDE_INT
)1 << GET_MODE_BITSIZE (part_mode
)) - 1;
1244 if (GET_CODE (op
) != CONST_INT
)
1247 for (i
= 0; i
< n_parts
; i
++)
1250 value
= (unsigned HOST_WIDE_INT
) INTVAL (op
);
1252 value
>>= GET_MODE_BITSIZE (part_mode
);
1254 if ((value
& part_mask
) != (def
& part_mask
))
1262 return part
== -1 ? -1 : n_parts
- 1 - part
;
1265 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1266 bits and no other bits are set in IN. POS and LENGTH can be used
1267 to obtain the start position and the length of the bitfield.
1269 POS gives the position of the first bit of the bitfield counting
1270 from the lowest order bit starting with zero. In order to use this
1271 value for S/390 instructions this has to be converted to "bits big
1275 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in
, int size
,
1276 int *pos
, int *length
)
1281 unsigned HOST_WIDE_INT mask
= 1ULL;
1282 bool contiguous
= false;
1284 for (i
= 0; i
< size
; mask
<<= 1, i
++)
1308 /* Calculate a mask for all bits beyond the contiguous bits. */
1309 mask
= (-1LL & ~(((1ULL << (tmp_length
+ tmp_pos
- 1)) << 1) - 1));
1314 if (tmp_length
+ tmp_pos
- 1 > size
)
1318 *length
= tmp_length
;
1326 /* Check whether we can (and want to) split a double-word
1327 move in mode MODE from SRC to DST into two single-word
1328 moves, moving the subword FIRST_SUBWORD first. */
1331 s390_split_ok_p (rtx dst
, rtx src
, enum machine_mode mode
, int first_subword
)
1333 /* Floating point registers cannot be split. */
1334 if (FP_REG_P (src
) || FP_REG_P (dst
))
1337 /* We don't need to split if operands are directly accessible. */
1338 if (s_operand (src
, mode
) || s_operand (dst
, mode
))
1341 /* Non-offsettable memory references cannot be split. */
1342 if ((GET_CODE (src
) == MEM
&& !offsettable_memref_p (src
))
1343 || (GET_CODE (dst
) == MEM
&& !offsettable_memref_p (dst
)))
1346 /* Moving the first subword must not clobber a register
1347 needed to move the second subword. */
1348 if (register_operand (dst
, mode
))
1350 rtx subreg
= operand_subword (dst
, first_subword
, 0, mode
);
1351 if (reg_overlap_mentioned_p (subreg
, src
))
1358 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1359 and [MEM2, MEM2 + SIZE] do overlap and false
1363 s390_overlap_p (rtx mem1
, rtx mem2
, HOST_WIDE_INT size
)
1365 rtx addr1
, addr2
, addr_delta
;
1366 HOST_WIDE_INT delta
;
1368 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
1374 addr1
= XEXP (mem1
, 0);
1375 addr2
= XEXP (mem2
, 0);
1377 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
1379 /* This overlapping check is used by peepholes merging memory block operations.
1380 Overlapping operations would otherwise be recognized by the S/390 hardware
1381 and would fall back to a slower implementation. Allowing overlapping
1382 operations would lead to slow code but not to wrong code. Therefore we are
1383 somewhat optimistic if we cannot prove that the memory blocks are
1385 That's why we return false here although this may accept operations on
1386 overlapping memory areas. */
1387 if (!addr_delta
|| GET_CODE (addr_delta
) != CONST_INT
)
1390 delta
= INTVAL (addr_delta
);
1393 || (delta
> 0 && delta
< size
)
1394 || (delta
< 0 && -delta
< size
))
1400 /* Check whether the address of memory reference MEM2 equals exactly
1401 the address of memory reference MEM1 plus DELTA. Return true if
1402 we can prove this to be the case, false otherwise. */
1405 s390_offset_p (rtx mem1
, rtx mem2
, rtx delta
)
1407 rtx addr1
, addr2
, addr_delta
;
1409 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
1412 addr1
= XEXP (mem1
, 0);
1413 addr2
= XEXP (mem2
, 0);
1415 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
1416 if (!addr_delta
|| !rtx_equal_p (addr_delta
, delta
))
1422 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1425 s390_expand_logical_operator (enum rtx_code code
, enum machine_mode mode
,
1428 enum machine_mode wmode
= mode
;
1429 rtx dst
= operands
[0];
1430 rtx src1
= operands
[1];
1431 rtx src2
= operands
[2];
1434 /* If we cannot handle the operation directly, use a temp register. */
1435 if (!s390_logical_operator_ok_p (operands
))
1436 dst
= gen_reg_rtx (mode
);
1438 /* QImode and HImode patterns make sense only if we have a destination
1439 in memory. Otherwise perform the operation in SImode. */
1440 if ((mode
== QImode
|| mode
== HImode
) && GET_CODE (dst
) != MEM
)
1443 /* Widen operands if required. */
1446 if (GET_CODE (dst
) == SUBREG
1447 && (tem
= simplify_subreg (wmode
, dst
, mode
, 0)) != 0)
1449 else if (REG_P (dst
))
1450 dst
= gen_rtx_SUBREG (wmode
, dst
, 0);
1452 dst
= gen_reg_rtx (wmode
);
1454 if (GET_CODE (src1
) == SUBREG
1455 && (tem
= simplify_subreg (wmode
, src1
, mode
, 0)) != 0)
1457 else if (GET_MODE (src1
) != VOIDmode
)
1458 src1
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src1
), 0);
1460 if (GET_CODE (src2
) == SUBREG
1461 && (tem
= simplify_subreg (wmode
, src2
, mode
, 0)) != 0)
1463 else if (GET_MODE (src2
) != VOIDmode
)
1464 src2
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src2
), 0);
1467 /* Emit the instruction. */
1468 op
= gen_rtx_SET (VOIDmode
, dst
, gen_rtx_fmt_ee (code
, wmode
, src1
, src2
));
1469 clob
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
1470 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clob
)));
1472 /* Fix up the destination if needed. */
1473 if (dst
!= operands
[0])
1474 emit_move_insn (operands
[0], gen_lowpart (mode
, dst
));
1477 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1480 s390_logical_operator_ok_p (rtx
*operands
)
1482 /* If the destination operand is in memory, it needs to coincide
1483 with one of the source operands. After reload, it has to be
1484 the first source operand. */
1485 if (GET_CODE (operands
[0]) == MEM
)
1486 return rtx_equal_p (operands
[0], operands
[1])
1487 || (!reload_completed
&& rtx_equal_p (operands
[0], operands
[2]));
1492 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1493 operand IMMOP to switch from SS to SI type instructions. */
1496 s390_narrow_logical_operator (enum rtx_code code
, rtx
*memop
, rtx
*immop
)
1498 int def
= code
== AND
? -1 : 0;
1502 gcc_assert (GET_CODE (*memop
) == MEM
);
1503 gcc_assert (!MEM_VOLATILE_P (*memop
));
1505 mask
= s390_extract_part (*immop
, QImode
, def
);
1506 part
= s390_single_part (*immop
, GET_MODE (*memop
), QImode
, def
);
1507 gcc_assert (part
>= 0);
1509 *memop
= adjust_address (*memop
, QImode
, part
);
1510 *immop
= gen_int_mode (mask
, QImode
);
1514 /* How to allocate a 'struct machine_function'. */
1516 static struct machine_function
*
1517 s390_init_machine_status (void)
1519 return ggc_alloc_cleared_machine_function ();
1522 /* Change optimizations to be performed, depending on the
1523 optimization level. */
1525 static const struct default_options s390_option_optimization_table
[] =
1527 { OPT_LEVELS_1_PLUS
, OPT_fomit_frame_pointer
, NULL
, 1 },
1529 /* ??? There are apparently still problems with -fcaller-saves. */
1530 { OPT_LEVELS_ALL
, OPT_fcaller_saves
, NULL
, 0 },
1532 /* Use MVCLE instructions to decrease code size if requested. */
1533 { OPT_LEVELS_SIZE
, OPT_mmvcle
, NULL
, 1 },
1535 { OPT_LEVELS_NONE
, 0, NULL
, 0 }
1538 /* Implement TARGET_OPTION_INIT_STRUCT. */
1541 s390_option_init_struct (struct gcc_options
*opts
)
1543 /* By default, always emit DWARF-2 unwind info. This allows debugging
1544 without maintaining a stack frame back-chain. */
1545 opts
->x_flag_asynchronous_unwind_tables
= 1;
1548 /* Implement TARGET_HANDLE_OPTION. */
1551 s390_handle_option (struct gcc_options
*opts
,
1552 struct gcc_options
*opts_set ATTRIBUTE_UNUSED
,
1553 const struct cl_decoded_option
*decoded
,
1556 size_t code
= decoded
->opt_index
;
1557 const char *arg
= decoded
->arg
;
1558 int value
= decoded
->value
;
1563 opts
->x_s390_arch_flags
= processor_flags_table
[value
];
1564 opts
->x_s390_arch_string
= arg
;
1567 case OPT_mstack_guard_
:
1568 if (exact_log2 (value
) == -1)
1569 error_at (loc
, "stack guard value must be an exact power of 2");
1572 case OPT_mstack_size_
:
1573 if (exact_log2 (value
) == -1)
1574 error_at (loc
, "stack size must be an exact power of 2");
1578 opts
->x_s390_tune_flags
= processor_flags_table
[value
];
1581 case OPT_mwarn_framesize_
:
1582 return sscanf (arg
, HOST_WIDE_INT_PRINT_DEC
,
1583 &opts
->x_s390_warn_framesize
) == 1;
1591 s390_option_override (void)
1593 /* Set up function hooks. */
1594 init_machine_status
= s390_init_machine_status
;
1596 /* Architecture mode defaults according to ABI. */
1597 if (!(target_flags_explicit
& MASK_ZARCH
))
1600 target_flags
|= MASK_ZARCH
;
1602 target_flags
&= ~MASK_ZARCH
;
1605 /* Set the march default in case it hasn't been specified on
1607 if (s390_arch
== PROCESSOR_max
)
1609 s390_arch_string
= TARGET_ZARCH
? "z900" : "g5";
1610 s390_arch
= TARGET_ZARCH
? PROCESSOR_2064_Z900
: PROCESSOR_9672_G5
;
1611 s390_arch_flags
= processor_flags_table
[(int)s390_arch
];
1614 /* Determine processor to tune for. */
1615 if (s390_tune
== PROCESSOR_max
)
1617 s390_tune
= s390_arch
;
1618 s390_tune_flags
= s390_arch_flags
;
1621 /* Sanity checks. */
1622 if (TARGET_ZARCH
&& !TARGET_CPU_ZARCH
)
1623 error ("z/Architecture mode not supported on %s", s390_arch_string
);
1624 if (TARGET_64BIT
&& !TARGET_ZARCH
)
1625 error ("64-bit ABI not supported in ESA/390 mode");
1627 if (TARGET_HARD_DFP
&& !TARGET_DFP
)
1629 if (target_flags_explicit
& MASK_HARD_DFP
)
1631 if (!TARGET_CPU_DFP
)
1632 error ("hardware decimal floating point instructions"
1633 " not available on %s", s390_arch_string
);
1635 error ("hardware decimal floating point instructions"
1636 " not available in ESA/390 mode");
1639 target_flags
&= ~MASK_HARD_DFP
;
1642 if ((target_flags_explicit
& MASK_SOFT_FLOAT
) && TARGET_SOFT_FLOAT
)
1644 if ((target_flags_explicit
& MASK_HARD_DFP
) && TARGET_HARD_DFP
)
1645 error ("-mhard-dfp can%'t be used in conjunction with -msoft-float");
1647 target_flags
&= ~MASK_HARD_DFP
;
1650 /* Set processor cost function. */
1653 case PROCESSOR_2084_Z990
:
1654 s390_cost
= &z990_cost
;
1656 case PROCESSOR_2094_Z9_109
:
1657 s390_cost
= &z9_109_cost
;
1659 case PROCESSOR_2097_Z10
:
1660 s390_cost
= &z10_cost
;
1661 case PROCESSOR_2817_Z196
:
1662 s390_cost
= &z196_cost
;
1665 s390_cost
= &z900_cost
;
1668 if (TARGET_BACKCHAIN
&& TARGET_PACKED_STACK
&& TARGET_HARD_FLOAT
)
1669 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1672 if (s390_stack_size
)
1674 if (s390_stack_guard
>= s390_stack_size
)
1675 error ("stack size must be greater than the stack guard value");
1676 else if (s390_stack_size
> 1 << 16)
1677 error ("stack size must not be greater than 64k");
1679 else if (s390_stack_guard
)
1680 error ("-mstack-guard implies use of -mstack-size");
1682 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1683 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
1684 target_flags
|= MASK_LONG_DOUBLE_128
;
1687 if (s390_tune
== PROCESSOR_2097_Z10
1688 || s390_tune
== PROCESSOR_2817_Z196
)
1690 maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS
, 100,
1691 global_options
.x_param_values
,
1692 global_options_set
.x_param_values
);
1693 maybe_set_param_value (PARAM_MAX_UNROLL_TIMES
, 32,
1694 global_options
.x_param_values
,
1695 global_options_set
.x_param_values
);
1696 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS
, 2000,
1697 global_options
.x_param_values
,
1698 global_options_set
.x_param_values
);
1699 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES
, 64,
1700 global_options
.x_param_values
,
1701 global_options_set
.x_param_values
);
1704 maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH
, 256,
1705 global_options
.x_param_values
,
1706 global_options_set
.x_param_values
);
1707 /* values for loop prefetching */
1708 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
, 256,
1709 global_options
.x_param_values
,
1710 global_options_set
.x_param_values
);
1711 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, 128,
1712 global_options
.x_param_values
,
1713 global_options_set
.x_param_values
);
1714 /* s390 has more than 2 levels and the size is much larger. Since
1715 we are always running virtualized assume that we only get a small
1716 part of the caches above l1. */
1717 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, 1500,
1718 global_options
.x_param_values
,
1719 global_options_set
.x_param_values
);
1720 maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO
, 2,
1721 global_options
.x_param_values
,
1722 global_options_set
.x_param_values
);
1723 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
, 6,
1724 global_options
.x_param_values
,
1725 global_options_set
.x_param_values
);
1727 /* This cannot reside in s390_option_optimization_table since HAVE_prefetch
1728 requires the arch flags to be evaluated already. Since prefetching
1729 is beneficial on s390, we enable it if available. */
1730 if (flag_prefetch_loop_arrays
< 0 && HAVE_prefetch
&& optimize
>= 3)
1731 flag_prefetch_loop_arrays
= 1;
1734 /* Map for smallest class containing reg regno. */
1736 const enum reg_class regclass_map
[FIRST_PSEUDO_REGISTER
] =
1737 { GENERAL_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1738 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1739 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1740 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1741 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1742 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1743 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1744 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1745 ADDR_REGS
, CC_REGS
, ADDR_REGS
, ADDR_REGS
,
1746 ACCESS_REGS
, ACCESS_REGS
1749 /* Return attribute type of insn. */
1751 static enum attr_type
1752 s390_safe_attr_type (rtx insn
)
1754 if (recog_memoized (insn
) >= 0)
1755 return get_attr_type (insn
);
1760 /* Return true if DISP is a valid short displacement. */
1763 s390_short_displacement (rtx disp
)
1765 /* No displacement is OK. */
1769 /* Without the long displacement facility we don't need to
1770 distingiush between long and short displacement. */
1771 if (!TARGET_LONG_DISPLACEMENT
)
1774 /* Integer displacement in range. */
1775 if (GET_CODE (disp
) == CONST_INT
)
1776 return INTVAL (disp
) >= 0 && INTVAL (disp
) < 4096;
1778 /* GOT offset is not OK, the GOT can be large. */
1779 if (GET_CODE (disp
) == CONST
1780 && GET_CODE (XEXP (disp
, 0)) == UNSPEC
1781 && (XINT (XEXP (disp
, 0), 1) == UNSPEC_GOT
1782 || XINT (XEXP (disp
, 0), 1) == UNSPEC_GOTNTPOFF
))
1785 /* All other symbolic constants are literal pool references,
1786 which are OK as the literal pool must be small. */
1787 if (GET_CODE (disp
) == CONST
)
1793 /* Decompose a RTL expression ADDR for a memory address into
1794 its components, returned in OUT.
1796 Returns false if ADDR is not a valid memory address, true
1797 otherwise. If OUT is NULL, don't return the components,
1798 but check for validity only.
1800 Note: Only addresses in canonical form are recognized.
1801 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1802 canonical form so that they will be recognized. */
1805 s390_decompose_address (rtx addr
, struct s390_address
*out
)
1807 HOST_WIDE_INT offset
= 0;
1808 rtx base
= NULL_RTX
;
1809 rtx indx
= NULL_RTX
;
1810 rtx disp
= NULL_RTX
;
1812 bool pointer
= false;
1813 bool base_ptr
= false;
1814 bool indx_ptr
= false;
1815 bool literal_pool
= false;
1817 /* We may need to substitute the literal pool base register into the address
1818 below. However, at this point we do not know which register is going to
1819 be used as base, so we substitute the arg pointer register. This is going
1820 to be treated as holding a pointer below -- it shouldn't be used for any
1822 rtx fake_pool_base
= gen_rtx_REG (Pmode
, ARG_POINTER_REGNUM
);
1824 /* Decompose address into base + index + displacement. */
1826 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == UNSPEC
)
1829 else if (GET_CODE (addr
) == PLUS
)
1831 rtx op0
= XEXP (addr
, 0);
1832 rtx op1
= XEXP (addr
, 1);
1833 enum rtx_code code0
= GET_CODE (op0
);
1834 enum rtx_code code1
= GET_CODE (op1
);
1836 if (code0
== REG
|| code0
== UNSPEC
)
1838 if (code1
== REG
|| code1
== UNSPEC
)
1840 indx
= op0
; /* index + base */
1846 base
= op0
; /* base + displacement */
1851 else if (code0
== PLUS
)
1853 indx
= XEXP (op0
, 0); /* index + base + disp */
1854 base
= XEXP (op0
, 1);
1865 disp
= addr
; /* displacement */
1867 /* Extract integer part of displacement. */
1871 if (GET_CODE (disp
) == CONST_INT
)
1873 offset
= INTVAL (disp
);
1876 else if (GET_CODE (disp
) == CONST
1877 && GET_CODE (XEXP (disp
, 0)) == PLUS
1878 && GET_CODE (XEXP (XEXP (disp
, 0), 1)) == CONST_INT
)
1880 offset
= INTVAL (XEXP (XEXP (disp
, 0), 1));
1881 disp
= XEXP (XEXP (disp
, 0), 0);
1885 /* Strip off CONST here to avoid special case tests later. */
1886 if (disp
&& GET_CODE (disp
) == CONST
)
1887 disp
= XEXP (disp
, 0);
1889 /* We can convert literal pool addresses to
1890 displacements by basing them off the base register. */
1891 if (disp
&& GET_CODE (disp
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (disp
))
1893 /* Either base or index must be free to hold the base register. */
1895 base
= fake_pool_base
, literal_pool
= true;
1897 indx
= fake_pool_base
, literal_pool
= true;
1901 /* Mark up the displacement. */
1902 disp
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, disp
),
1903 UNSPEC_LTREL_OFFSET
);
1906 /* Validate base register. */
1909 if (GET_CODE (base
) == UNSPEC
)
1910 switch (XINT (base
, 1))
1914 disp
= gen_rtx_UNSPEC (Pmode
,
1915 gen_rtvec (1, XVECEXP (base
, 0, 0)),
1916 UNSPEC_LTREL_OFFSET
);
1920 base
= XVECEXP (base
, 0, 1);
1923 case UNSPEC_LTREL_BASE
:
1924 if (XVECLEN (base
, 0) == 1)
1925 base
= fake_pool_base
, literal_pool
= true;
1927 base
= XVECEXP (base
, 0, 1);
1935 || (GET_MODE (base
) != SImode
1936 && GET_MODE (base
) != Pmode
))
1939 if (REGNO (base
) == STACK_POINTER_REGNUM
1940 || REGNO (base
) == FRAME_POINTER_REGNUM
1941 || ((reload_completed
|| reload_in_progress
)
1942 && frame_pointer_needed
1943 && REGNO (base
) == HARD_FRAME_POINTER_REGNUM
)
1944 || REGNO (base
) == ARG_POINTER_REGNUM
1946 && REGNO (base
) == PIC_OFFSET_TABLE_REGNUM
))
1947 pointer
= base_ptr
= true;
1949 if ((reload_completed
|| reload_in_progress
)
1950 && base
== cfun
->machine
->base_reg
)
1951 pointer
= base_ptr
= literal_pool
= true;
1954 /* Validate index register. */
1957 if (GET_CODE (indx
) == UNSPEC
)
1958 switch (XINT (indx
, 1))
1962 disp
= gen_rtx_UNSPEC (Pmode
,
1963 gen_rtvec (1, XVECEXP (indx
, 0, 0)),
1964 UNSPEC_LTREL_OFFSET
);
1968 indx
= XVECEXP (indx
, 0, 1);
1971 case UNSPEC_LTREL_BASE
:
1972 if (XVECLEN (indx
, 0) == 1)
1973 indx
= fake_pool_base
, literal_pool
= true;
1975 indx
= XVECEXP (indx
, 0, 1);
1983 || (GET_MODE (indx
) != SImode
1984 && GET_MODE (indx
) != Pmode
))
1987 if (REGNO (indx
) == STACK_POINTER_REGNUM
1988 || REGNO (indx
) == FRAME_POINTER_REGNUM
1989 || ((reload_completed
|| reload_in_progress
)
1990 && frame_pointer_needed
1991 && REGNO (indx
) == HARD_FRAME_POINTER_REGNUM
)
1992 || REGNO (indx
) == ARG_POINTER_REGNUM
1994 && REGNO (indx
) == PIC_OFFSET_TABLE_REGNUM
))
1995 pointer
= indx_ptr
= true;
1997 if ((reload_completed
|| reload_in_progress
)
1998 && indx
== cfun
->machine
->base_reg
)
1999 pointer
= indx_ptr
= literal_pool
= true;
2002 /* Prefer to use pointer as base, not index. */
2003 if (base
&& indx
&& !base_ptr
2004 && (indx_ptr
|| (!REG_POINTER (base
) && REG_POINTER (indx
))))
2011 /* Validate displacement. */
2014 /* If virtual registers are involved, the displacement will change later
2015 anyway as the virtual registers get eliminated. This could make a
2016 valid displacement invalid, but it is more likely to make an invalid
2017 displacement valid, because we sometimes access the register save area
2018 via negative offsets to one of those registers.
2019 Thus we don't check the displacement for validity here. If after
2020 elimination the displacement turns out to be invalid after all,
2021 this is fixed up by reload in any case. */
2022 if (base
!= arg_pointer_rtx
2023 && indx
!= arg_pointer_rtx
2024 && base
!= return_address_pointer_rtx
2025 && indx
!= return_address_pointer_rtx
2026 && base
!= frame_pointer_rtx
2027 && indx
!= frame_pointer_rtx
2028 && base
!= virtual_stack_vars_rtx
2029 && indx
!= virtual_stack_vars_rtx
)
2030 if (!DISP_IN_RANGE (offset
))
2035 /* All the special cases are pointers. */
2038 /* In the small-PIC case, the linker converts @GOT
2039 and @GOTNTPOFF offsets to possible displacements. */
2040 if (GET_CODE (disp
) == UNSPEC
2041 && (XINT (disp
, 1) == UNSPEC_GOT
2042 || XINT (disp
, 1) == UNSPEC_GOTNTPOFF
)
2048 /* Accept pool label offsets. */
2049 else if (GET_CODE (disp
) == UNSPEC
2050 && XINT (disp
, 1) == UNSPEC_POOL_OFFSET
)
2053 /* Accept literal pool references. */
2054 else if (GET_CODE (disp
) == UNSPEC
2055 && XINT (disp
, 1) == UNSPEC_LTREL_OFFSET
)
2057 /* In case CSE pulled a non literal pool reference out of
2058 the pool we have to reject the address. This is
2059 especially important when loading the GOT pointer on non
2060 zarch CPUs. In this case the literal pool contains an lt
2061 relative offset to the _GLOBAL_OFFSET_TABLE_ label which
2062 will most likely exceed the displacement. */
2063 if (GET_CODE (XVECEXP (disp
, 0, 0)) != SYMBOL_REF
2064 || !CONSTANT_POOL_ADDRESS_P (XVECEXP (disp
, 0, 0)))
2067 orig_disp
= gen_rtx_CONST (Pmode
, disp
);
2070 /* If we have an offset, make sure it does not
2071 exceed the size of the constant pool entry. */
2072 rtx sym
= XVECEXP (disp
, 0, 0);
2073 if (offset
>= GET_MODE_SIZE (get_pool_mode (sym
)))
2076 orig_disp
= plus_constant (orig_disp
, offset
);
2091 out
->disp
= orig_disp
;
2092 out
->pointer
= pointer
;
2093 out
->literal_pool
= literal_pool
;
2099 /* Decompose a RTL expression OP for a shift count into its components,
2100 and return the base register in BASE and the offset in OFFSET.
2102 Return true if OP is a valid shift count, false if not. */
2105 s390_decompose_shift_count (rtx op
, rtx
*base
, HOST_WIDE_INT
*offset
)
2107 HOST_WIDE_INT off
= 0;
2109 /* We can have an integer constant, an address register,
2110 or a sum of the two. */
2111 if (GET_CODE (op
) == CONST_INT
)
2116 if (op
&& GET_CODE (op
) == PLUS
&& GET_CODE (XEXP (op
, 1)) == CONST_INT
)
2118 off
= INTVAL (XEXP (op
, 1));
2121 while (op
&& GET_CODE (op
) == SUBREG
)
2122 op
= SUBREG_REG (op
);
2124 if (op
&& GET_CODE (op
) != REG
)
2136 /* Return true if CODE is a valid address without index. */
2139 s390_legitimate_address_without_index_p (rtx op
)
2141 struct s390_address addr
;
2143 if (!s390_decompose_address (XEXP (op
, 0), &addr
))
2152 /* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int
2153 and return these parts in SYMREF and ADDEND. You can pass NULL in
2154 SYMREF and/or ADDEND if you are not interested in these values.
2155 Literal pool references are *not* considered symbol references. */
2158 s390_symref_operand_p (rtx addr
, rtx
*symref
, HOST_WIDE_INT
*addend
)
2160 HOST_WIDE_INT tmpaddend
= 0;
2162 if (GET_CODE (addr
) == CONST
)
2163 addr
= XEXP (addr
, 0);
2165 if (GET_CODE (addr
) == PLUS
)
2167 if (GET_CODE (XEXP (addr
, 0)) == SYMBOL_REF
2168 && !CONSTANT_POOL_ADDRESS_P (XEXP (addr
, 0))
2169 && CONST_INT_P (XEXP (addr
, 1)))
2171 tmpaddend
= INTVAL (XEXP (addr
, 1));
2172 addr
= XEXP (addr
, 0);
2178 if (GET_CODE (addr
) != SYMBOL_REF
|| CONSTANT_POOL_ADDRESS_P (addr
))
2184 *addend
= tmpaddend
;
2190 /* Return true if the address in OP is valid for constraint letter C
2191 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2192 pool MEMs should be accepted. Only the Q, R, S, T constraint
2193 letters are allowed for C. */
2196 s390_check_qrst_address (char c
, rtx op
, bool lit_pool_ok
)
2198 struct s390_address addr
;
2199 bool decomposed
= false;
2201 /* This check makes sure that no symbolic address (except literal
2202 pool references) are accepted by the R or T constraints. */
2203 if (s390_symref_operand_p (op
, NULL
, NULL
))
2206 /* Ensure literal pool references are only accepted if LIT_POOL_OK. */
2209 if (!s390_decompose_address (op
, &addr
))
2211 if (addr
.literal_pool
)
2218 case 'Q': /* no index short displacement */
2219 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
2223 if (!s390_short_displacement (addr
.disp
))
2227 case 'R': /* with index short displacement */
2228 if (TARGET_LONG_DISPLACEMENT
)
2230 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
2232 if (!s390_short_displacement (addr
.disp
))
2235 /* Any invalid address here will be fixed up by reload,
2236 so accept it for the most generic constraint. */
2239 case 'S': /* no index long displacement */
2240 if (!TARGET_LONG_DISPLACEMENT
)
2242 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
2246 if (s390_short_displacement (addr
.disp
))
2250 case 'T': /* with index long displacement */
2251 if (!TARGET_LONG_DISPLACEMENT
)
2253 /* Any invalid address here will be fixed up by reload,
2254 so accept it for the most generic constraint. */
2255 if ((decomposed
|| s390_decompose_address (op
, &addr
))
2256 && s390_short_displacement (addr
.disp
))
2266 /* Evaluates constraint strings described by the regular expression
2267 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2268 the constraint given in STR, or 0 else. */
2271 s390_mem_constraint (const char *str
, rtx op
)
2278 /* Check for offsettable variants of memory constraints. */
2279 if (!MEM_P (op
) || MEM_VOLATILE_P (op
))
2281 if ((reload_completed
|| reload_in_progress
)
2282 ? !offsettable_memref_p (op
) : !offsettable_nonstrict_memref_p (op
))
2284 return s390_check_qrst_address (str
[1], XEXP (op
, 0), true);
2286 /* Check for non-literal-pool variants of memory constraints. */
2289 return s390_check_qrst_address (str
[1], XEXP (op
, 0), false);
2294 if (GET_CODE (op
) != MEM
)
2296 return s390_check_qrst_address (c
, XEXP (op
, 0), true);
2298 return (s390_check_qrst_address ('Q', op
, true)
2299 || s390_check_qrst_address ('R', op
, true));
2301 return (s390_check_qrst_address ('S', op
, true)
2302 || s390_check_qrst_address ('T', op
, true));
2304 /* Simply check for the basic form of a shift count. Reload will
2305 take care of making sure we have a proper base register. */
2306 if (!s390_decompose_shift_count (op
, NULL
, NULL
))
2310 return s390_check_qrst_address (str
[1], op
, true);
2318 /* Evaluates constraint strings starting with letter O. Input
2319 parameter C is the second letter following the "O" in the constraint
2320 string. Returns 1 if VALUE meets the respective constraint and 0
2324 s390_O_constraint_str (const char c
, HOST_WIDE_INT value
)
2332 return trunc_int_for_mode (value
, SImode
) == value
;
2336 || s390_single_part (GEN_INT (value
), DImode
, SImode
, 0) == 1;
2339 return s390_single_part (GEN_INT (value
- 1), DImode
, SImode
, -1) == 1;
2347 /* Evaluates constraint strings starting with letter N. Parameter STR
2348 contains the letters following letter "N" in the constraint string.
2349 Returns true if VALUE matches the constraint. */
2352 s390_N_constraint_str (const char *str
, HOST_WIDE_INT value
)
2354 enum machine_mode mode
, part_mode
;
2356 int part
, part_goal
;
2362 part_goal
= str
[0] - '0';
2406 if (GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (part_mode
))
2409 part
= s390_single_part (GEN_INT (value
), mode
, part_mode
, def
);
2412 if (part_goal
!= -1 && part_goal
!= part
)
2419 /* Returns true if the input parameter VALUE is a float zero. */
2422 s390_float_const_zero_p (rtx value
)
2424 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
2425 && value
== CONST0_RTX (GET_MODE (value
)));
2428 /* Implement TARGET_REGISTER_MOVE_COST. */
2431 s390_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
2432 reg_class_t from
, reg_class_t to
)
2434 /* On s390, copy between fprs and gprs is expensive. */
2435 if ((reg_classes_intersect_p (from
, GENERAL_REGS
)
2436 && reg_classes_intersect_p (to
, FP_REGS
))
2437 || (reg_classes_intersect_p (from
, FP_REGS
)
2438 && reg_classes_intersect_p (to
, GENERAL_REGS
)))
2444 /* Implement TARGET_MEMORY_MOVE_COST. */
2447 s390_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
2448 reg_class_t rclass ATTRIBUTE_UNUSED
,
2449 bool in ATTRIBUTE_UNUSED
)
2454 /* Compute a (partial) cost for rtx X. Return true if the complete
2455 cost has been computed, and false if subexpressions should be
2456 scanned. In either case, *TOTAL contains the cost result.
2457 CODE contains GET_CODE (x), OUTER_CODE contains the code
2458 of the superexpression of x. */
2461 s390_rtx_costs (rtx x
, int code
, int outer_code
, int *total
,
2462 bool speed ATTRIBUTE_UNUSED
)
2485 *total
= COSTS_N_INSNS (1);
2490 *total
= COSTS_N_INSNS (1);
2494 switch (GET_MODE (x
))
2498 rtx left
= XEXP (x
, 0);
2499 rtx right
= XEXP (x
, 1);
2500 if (GET_CODE (right
) == CONST_INT
2501 && CONST_OK_FOR_K (INTVAL (right
)))
2502 *total
= s390_cost
->mhi
;
2503 else if (GET_CODE (left
) == SIGN_EXTEND
)
2504 *total
= s390_cost
->mh
;
2506 *total
= s390_cost
->ms
; /* msr, ms, msy */
2511 rtx left
= XEXP (x
, 0);
2512 rtx right
= XEXP (x
, 1);
2515 if (GET_CODE (right
) == CONST_INT
2516 && CONST_OK_FOR_K (INTVAL (right
)))
2517 *total
= s390_cost
->mghi
;
2518 else if (GET_CODE (left
) == SIGN_EXTEND
)
2519 *total
= s390_cost
->msgf
;
2521 *total
= s390_cost
->msg
; /* msgr, msg */
2523 else /* TARGET_31BIT */
2525 if (GET_CODE (left
) == SIGN_EXTEND
2526 && GET_CODE (right
) == SIGN_EXTEND
)
2527 /* mulsidi case: mr, m */
2528 *total
= s390_cost
->m
;
2529 else if (GET_CODE (left
) == ZERO_EXTEND
2530 && GET_CODE (right
) == ZERO_EXTEND
2531 && TARGET_CPU_ZARCH
)
2532 /* umulsidi case: ml, mlr */
2533 *total
= s390_cost
->ml
;
2535 /* Complex calculation is required. */
2536 *total
= COSTS_N_INSNS (40);
2542 *total
= s390_cost
->mult_df
;
2545 *total
= s390_cost
->mxbr
;
2553 switch (GET_MODE (x
))
2556 *total
= s390_cost
->madbr
;
2559 *total
= s390_cost
->maebr
;
2564 /* Negate in the third argument is free: FMSUB. */
2565 if (GET_CODE (XEXP (x
, 2)) == NEG
)
2567 *total
+= (rtx_cost (XEXP (x
, 0), FMA
, speed
)
2568 + rtx_cost (XEXP (x
, 1), FMA
, speed
)
2569 + rtx_cost (XEXP (XEXP (x
, 2), 0), FMA
, speed
));
2576 if (GET_MODE (x
) == TImode
) /* 128 bit division */
2577 *total
= s390_cost
->dlgr
;
2578 else if (GET_MODE (x
) == DImode
)
2580 rtx right
= XEXP (x
, 1);
2581 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
2582 *total
= s390_cost
->dlr
;
2583 else /* 64 by 64 bit division */
2584 *total
= s390_cost
->dlgr
;
2586 else if (GET_MODE (x
) == SImode
) /* 32 bit division */
2587 *total
= s390_cost
->dlr
;
2592 if (GET_MODE (x
) == DImode
)
2594 rtx right
= XEXP (x
, 1);
2595 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
2597 *total
= s390_cost
->dsgfr
;
2599 *total
= s390_cost
->dr
;
2600 else /* 64 by 64 bit division */
2601 *total
= s390_cost
->dsgr
;
2603 else if (GET_MODE (x
) == SImode
) /* 32 bit division */
2604 *total
= s390_cost
->dlr
;
2605 else if (GET_MODE (x
) == SFmode
)
2607 *total
= s390_cost
->debr
;
2609 else if (GET_MODE (x
) == DFmode
)
2611 *total
= s390_cost
->ddbr
;
2613 else if (GET_MODE (x
) == TFmode
)
2615 *total
= s390_cost
->dxbr
;
2620 if (GET_MODE (x
) == SFmode
)
2621 *total
= s390_cost
->sqebr
;
2622 else if (GET_MODE (x
) == DFmode
)
2623 *total
= s390_cost
->sqdbr
;
2625 *total
= s390_cost
->sqxbr
;
2630 if (outer_code
== MULT
|| outer_code
== DIV
|| outer_code
== MOD
2631 || outer_code
== PLUS
|| outer_code
== MINUS
2632 || outer_code
== COMPARE
)
2637 *total
= COSTS_N_INSNS (1);
2638 if (GET_CODE (XEXP (x
, 0)) == AND
2639 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2640 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
2642 rtx op0
= XEXP (XEXP (x
, 0), 0);
2643 rtx op1
= XEXP (XEXP (x
, 0), 1);
2644 rtx op2
= XEXP (x
, 1);
2646 if (memory_operand (op0
, GET_MODE (op0
))
2647 && s390_tm_ccmode (op1
, op2
, 0) != VOIDmode
)
2649 if (register_operand (op0
, GET_MODE (op0
))
2650 && s390_tm_ccmode (op1
, op2
, 1) != VOIDmode
)
2660 /* Return the cost of an address rtx ADDR. */
2663 s390_address_cost (rtx addr
, bool speed ATTRIBUTE_UNUSED
)
2665 struct s390_address ad
;
2666 if (!s390_decompose_address (addr
, &ad
))
2669 return ad
.indx
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2672 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2673 otherwise return 0. */
2676 tls_symbolic_operand (rtx op
)
2678 if (GET_CODE (op
) != SYMBOL_REF
)
2680 return SYMBOL_REF_TLS_MODEL (op
);
2683 /* Split DImode access register reference REG (on 64-bit) into its constituent
2684 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2685 gen_highpart cannot be used as they assume all registers are word-sized,
2686 while our access registers have only half that size. */
2689 s390_split_access_reg (rtx reg
, rtx
*lo
, rtx
*hi
)
2691 gcc_assert (TARGET_64BIT
);
2692 gcc_assert (ACCESS_REG_P (reg
));
2693 gcc_assert (GET_MODE (reg
) == DImode
);
2694 gcc_assert (!(REGNO (reg
) & 1));
2696 *lo
= gen_rtx_REG (SImode
, REGNO (reg
) + 1);
2697 *hi
= gen_rtx_REG (SImode
, REGNO (reg
));
2700 /* Return true if OP contains a symbol reference */
2703 symbolic_reference_mentioned_p (rtx op
)
2708 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
2711 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
2712 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
2718 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
2719 if (symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
2723 else if (fmt
[i
] == 'e' && symbolic_reference_mentioned_p (XEXP (op
, i
)))
2730 /* Return true if OP contains a reference to a thread-local symbol. */
2733 tls_symbolic_reference_mentioned_p (rtx op
)
2738 if (GET_CODE (op
) == SYMBOL_REF
)
2739 return tls_symbolic_operand (op
);
2741 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
2742 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
2748 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
2749 if (tls_symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
2753 else if (fmt
[i
] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op
, i
)))
2761 /* Return true if OP is a legitimate general operand when
2762 generating PIC code. It is given that flag_pic is on
2763 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2766 legitimate_pic_operand_p (rtx op
)
2768 /* Accept all non-symbolic constants. */
2769 if (!SYMBOLIC_CONST (op
))
2772 /* Reject everything else; must be handled
2773 via emit_symbolic_move. */
2777 /* Returns true if the constant value OP is a legitimate general operand.
2778 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2781 legitimate_constant_p (rtx op
)
2783 /* Accept all non-symbolic constants. */
2784 if (!SYMBOLIC_CONST (op
))
2787 /* Accept immediate LARL operands. */
2788 if (TARGET_CPU_ZARCH
&& larl_operand (op
, VOIDmode
))
2791 /* Thread-local symbols are never legal constants. This is
2792 so that emit_call knows that computing such addresses
2793 might require a function call. */
2794 if (TLS_SYMBOLIC_CONST (op
))
2797 /* In the PIC case, symbolic constants must *not* be
2798 forced into the literal pool. We accept them here,
2799 so that they will be handled by emit_symbolic_move. */
2803 /* All remaining non-PIC symbolic constants are
2804 forced into the literal pool. */
2808 /* Determine if it's legal to put X into the constant pool. This
2809 is not possible if X contains the address of a symbol that is
2810 not constant (TLS) or not known at final link time (PIC). */
2813 s390_cannot_force_const_mem (enum machine_mode mode
, rtx x
)
2815 switch (GET_CODE (x
))
2819 /* Accept all non-symbolic constants. */
2823 /* Labels are OK iff we are non-PIC. */
2824 return flag_pic
!= 0;
2827 /* 'Naked' TLS symbol references are never OK,
2828 non-TLS symbols are OK iff we are non-PIC. */
2829 if (tls_symbolic_operand (x
))
2832 return flag_pic
!= 0;
2835 return s390_cannot_force_const_mem (mode
, XEXP (x
, 0));
2838 return s390_cannot_force_const_mem (mode
, XEXP (x
, 0))
2839 || s390_cannot_force_const_mem (mode
, XEXP (x
, 1));
2842 switch (XINT (x
, 1))
2844 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2845 case UNSPEC_LTREL_OFFSET
:
2853 case UNSPEC_GOTNTPOFF
:
2854 case UNSPEC_INDNTPOFF
:
2857 /* If the literal pool shares the code section, be put
2858 execute template placeholders into the pool as well. */
2860 return TARGET_CPU_ZARCH
;
2872 /* Returns true if the constant value OP is a legitimate general
2873 operand during and after reload. The difference to
2874 legitimate_constant_p is that this function will not accept
2875 a constant that would need to be forced to the literal pool
2876 before it can be used as operand.
2877 This function accepts all constants which can be loaded directly
2881 legitimate_reload_constant_p (rtx op
)
2883 /* Accept la(y) operands. */
2884 if (GET_CODE (op
) == CONST_INT
2885 && DISP_IN_RANGE (INTVAL (op
)))
2888 /* Accept l(g)hi/l(g)fi operands. */
2889 if (GET_CODE (op
) == CONST_INT
2890 && (CONST_OK_FOR_K (INTVAL (op
)) || CONST_OK_FOR_Os (INTVAL (op
))))
2893 /* Accept lliXX operands. */
2895 && GET_CODE (op
) == CONST_INT
2896 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
2897 && s390_single_part (op
, word_mode
, HImode
, 0) >= 0)
2901 && GET_CODE (op
) == CONST_INT
2902 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
2903 && s390_single_part (op
, word_mode
, SImode
, 0) >= 0)
2906 /* Accept larl operands. */
2907 if (TARGET_CPU_ZARCH
2908 && larl_operand (op
, VOIDmode
))
2911 /* Accept floating-point zero operands that fit into a single GPR. */
2912 if (GET_CODE (op
) == CONST_DOUBLE
2913 && s390_float_const_zero_p (op
)
2914 && GET_MODE_SIZE (GET_MODE (op
)) <= UNITS_PER_WORD
)
2917 /* Accept double-word operands that can be split. */
2918 if (GET_CODE (op
) == CONST_INT
2919 && trunc_int_for_mode (INTVAL (op
), word_mode
) != INTVAL (op
))
2921 enum machine_mode dword_mode
= word_mode
== SImode
? DImode
: TImode
;
2922 rtx hi
= operand_subword (op
, 0, 0, dword_mode
);
2923 rtx lo
= operand_subword (op
, 1, 0, dword_mode
);
2924 return legitimate_reload_constant_p (hi
)
2925 && legitimate_reload_constant_p (lo
);
2928 /* Everything else cannot be handled without reload. */
2932 /* Returns true if the constant value OP is a legitimate fp operand
2933 during and after reload.
2934 This function accepts all constants which can be loaded directly
2938 legitimate_reload_fp_constant_p (rtx op
)
2940 /* Accept floating-point zero operands if the load zero instruction
2943 && GET_CODE (op
) == CONST_DOUBLE
2944 && s390_float_const_zero_p (op
))
2950 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2951 return the class of reg to actually use. */
2954 s390_preferred_reload_class (rtx op
, reg_class_t rclass
)
2956 switch (GET_CODE (op
))
2958 /* Constants we cannot reload into general registers
2959 must be forced into the literal pool. */
2962 if (reg_class_subset_p (GENERAL_REGS
, rclass
)
2963 && legitimate_reload_constant_p (op
))
2964 return GENERAL_REGS
;
2965 else if (reg_class_subset_p (ADDR_REGS
, rclass
)
2966 && legitimate_reload_constant_p (op
))
2968 else if (reg_class_subset_p (FP_REGS
, rclass
)
2969 && legitimate_reload_fp_constant_p (op
))
2973 /* If a symbolic constant or a PLUS is reloaded,
2974 it is most likely being used as an address, so
2975 prefer ADDR_REGS. If 'class' is not a superset
2976 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2980 if (!legitimate_reload_constant_p (op
))
2984 /* load address will be used. */
2985 if (reg_class_subset_p (ADDR_REGS
, rclass
))
2997 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2998 multiple of ALIGNMENT and the SYMBOL_REF being naturally
3002 s390_check_symref_alignment (rtx addr
, HOST_WIDE_INT alignment
)
3004 HOST_WIDE_INT addend
;
3007 if (!s390_symref_operand_p (addr
, &symref
, &addend
))
3010 return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref
)
3011 && !(addend
& (alignment
- 1)));
3014 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
3015 operand SCRATCH is used to reload the even part of the address and
3019 s390_reload_larl_operand (rtx reg
, rtx addr
, rtx scratch
)
3021 HOST_WIDE_INT addend
;
3024 if (!s390_symref_operand_p (addr
, &symref
, &addend
))
3028 /* Easy case. The addend is even so larl will do fine. */
3029 emit_move_insn (reg
, addr
);
3032 /* We can leave the scratch register untouched if the target
3033 register is a valid base register. */
3034 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
3035 && REGNO_REG_CLASS (REGNO (reg
)) == ADDR_REGS
)
3038 gcc_assert (REGNO (scratch
) < FIRST_PSEUDO_REGISTER
);
3039 gcc_assert (REGNO_REG_CLASS (REGNO (scratch
)) == ADDR_REGS
);
3042 emit_move_insn (scratch
,
3043 gen_rtx_CONST (Pmode
,
3044 gen_rtx_PLUS (Pmode
, symref
,
3045 GEN_INT (addend
- 1))));
3047 emit_move_insn (scratch
, symref
);
3049 /* Increment the address using la in order to avoid clobbering cc. */
3050 emit_move_insn (reg
, gen_rtx_PLUS (Pmode
, scratch
, const1_rtx
));
3054 /* Generate what is necessary to move between REG and MEM using
3055 SCRATCH. The direction is given by TOMEM. */
3058 s390_reload_symref_address (rtx reg
, rtx mem
, rtx scratch
, bool tomem
)
3060 /* Reload might have pulled a constant out of the literal pool.
3061 Force it back in. */
3062 if (CONST_INT_P (mem
) || GET_CODE (mem
) == CONST_DOUBLE
3063 || GET_CODE (mem
) == CONST
)
3064 mem
= force_const_mem (GET_MODE (reg
), mem
);
3066 gcc_assert (MEM_P (mem
));
3068 /* For a load from memory we can leave the scratch register
3069 untouched if the target register is a valid base register. */
3071 && REGNO (reg
) < FIRST_PSEUDO_REGISTER
3072 && REGNO_REG_CLASS (REGNO (reg
)) == ADDR_REGS
3073 && GET_MODE (reg
) == GET_MODE (scratch
))
3076 /* Load address into scratch register. Since we can't have a
3077 secondary reload for a secondary reload we have to cover the case
3078 where larl would need a secondary reload here as well. */
3079 s390_reload_larl_operand (scratch
, XEXP (mem
, 0), scratch
);
3081 /* Now we can use a standard load/store to do the move. */
3083 emit_move_insn (replace_equiv_address (mem
, scratch
), reg
);
3085 emit_move_insn (reg
, replace_equiv_address (mem
, scratch
));
3088 /* Inform reload about cases where moving X with a mode MODE to a register in
3089 RCLASS requires an extra scratch or immediate register. Return the class
3090 needed for the immediate register. */
3093 s390_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
3094 enum machine_mode mode
, secondary_reload_info
*sri
)
3096 enum reg_class rclass
= (enum reg_class
) rclass_i
;
3098 /* Intermediate register needed. */
3099 if (reg_classes_intersect_p (CC_REGS
, rclass
))
3100 return GENERAL_REGS
;
3104 HOST_WIDE_INT offset
;
3107 /* On z10 several optimizer steps may generate larl operands with
3110 && s390_symref_operand_p (x
, &symref
, &offset
)
3112 && !SYMBOL_REF_ALIGN1_P (symref
)
3113 && (offset
& 1) == 1)
3114 sri
->icode
= ((mode
== DImode
) ? CODE_FOR_reloaddi_larl_odd_addend_z10
3115 : CODE_FOR_reloadsi_larl_odd_addend_z10
);
3117 /* On z10 we need a scratch register when moving QI, TI or floating
3118 point mode values from or to a memory location with a SYMBOL_REF
3119 or if the symref addend of a SI or DI move is not aligned to the
3120 width of the access. */
3122 && s390_symref_operand_p (XEXP (x
, 0), NULL
, NULL
)
3123 && (mode
== QImode
|| mode
== TImode
|| FLOAT_MODE_P (mode
)
3124 || (!TARGET_ZARCH
&& mode
== DImode
)
3125 || ((mode
== HImode
|| mode
== SImode
|| mode
== DImode
)
3126 && (!s390_check_symref_alignment (XEXP (x
, 0),
3127 GET_MODE_SIZE (mode
))))))
3129 #define __SECONDARY_RELOAD_CASE(M,m) \
3132 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
3133 CODE_FOR_reload##m##di_tomem_z10; \
3135 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
3136 CODE_FOR_reload##m##si_tomem_z10; \
3139 switch (GET_MODE (x
))
3141 __SECONDARY_RELOAD_CASE (QI
, qi
);
3142 __SECONDARY_RELOAD_CASE (HI
, hi
);
3143 __SECONDARY_RELOAD_CASE (SI
, si
);
3144 __SECONDARY_RELOAD_CASE (DI
, di
);
3145 __SECONDARY_RELOAD_CASE (TI
, ti
);
3146 __SECONDARY_RELOAD_CASE (SF
, sf
);
3147 __SECONDARY_RELOAD_CASE (DF
, df
);
3148 __SECONDARY_RELOAD_CASE (TF
, tf
);
3149 __SECONDARY_RELOAD_CASE (SD
, sd
);
3150 __SECONDARY_RELOAD_CASE (DD
, dd
);
3151 __SECONDARY_RELOAD_CASE (TD
, td
);
3156 #undef __SECONDARY_RELOAD_CASE
3160 /* We need a scratch register when loading a PLUS expression which
3161 is not a legitimate operand of the LOAD ADDRESS instruction. */
3162 if (in_p
&& s390_plus_operand (x
, mode
))
3163 sri
->icode
= (TARGET_64BIT
?
3164 CODE_FOR_reloaddi_plus
: CODE_FOR_reloadsi_plus
);
3166 /* Performing a multiword move from or to memory we have to make sure the
3167 second chunk in memory is addressable without causing a displacement
3168 overflow. If that would be the case we calculate the address in
3169 a scratch register. */
3171 && GET_CODE (XEXP (x
, 0)) == PLUS
3172 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3173 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x
, 0), 1))
3174 + GET_MODE_SIZE (mode
) - 1))
3176 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3177 in a s_operand address since we may fallback to lm/stm. So we only
3178 have to care about overflows in the b+i+d case. */
3179 if ((reg_classes_intersect_p (GENERAL_REGS
, rclass
)
3180 && s390_class_max_nregs (GENERAL_REGS
, mode
) > 1
3181 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
3182 /* For FP_REGS no lm/stm is available so this check is triggered
3183 for displacement overflows in b+i+d and b+d like addresses. */
3184 || (reg_classes_intersect_p (FP_REGS
, rclass
)
3185 && s390_class_max_nregs (FP_REGS
, mode
) > 1))
3188 sri
->icode
= (TARGET_64BIT
?
3189 CODE_FOR_reloaddi_nonoffmem_in
:
3190 CODE_FOR_reloadsi_nonoffmem_in
);
3192 sri
->icode
= (TARGET_64BIT
?
3193 CODE_FOR_reloaddi_nonoffmem_out
:
3194 CODE_FOR_reloadsi_nonoffmem_out
);
3198 /* A scratch address register is needed when a symbolic constant is
3199 copied to r0 compiling with -fPIC. In other cases the target
3200 register might be used as temporary (see legitimize_pic_address). */
3201 if (in_p
&& SYMBOLIC_CONST (x
) && flag_pic
== 2 && rclass
!= ADDR_REGS
)
3202 sri
->icode
= (TARGET_64BIT
?
3203 CODE_FOR_reloaddi_PIC_addr
:
3204 CODE_FOR_reloadsi_PIC_addr
);
3206 /* Either scratch or no register needed. */
3210 /* Generate code to load SRC, which is PLUS that is not a
3211 legitimate operand for the LA instruction, into TARGET.
3212 SCRATCH may be used as scratch register. */
3215 s390_expand_plus_operand (rtx target
, rtx src
,
3219 struct s390_address ad
;
3221 /* src must be a PLUS; get its two operands. */
3222 gcc_assert (GET_CODE (src
) == PLUS
);
3223 gcc_assert (GET_MODE (src
) == Pmode
);
3225 /* Check if any of the two operands is already scheduled
3226 for replacement by reload. This can happen e.g. when
3227 float registers occur in an address. */
3228 sum1
= find_replacement (&XEXP (src
, 0));
3229 sum2
= find_replacement (&XEXP (src
, 1));
3230 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
3232 /* If the address is already strictly valid, there's nothing to do. */
3233 if (!s390_decompose_address (src
, &ad
)
3234 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
3235 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
3237 /* Otherwise, one of the operands cannot be an address register;
3238 we reload its value into the scratch register. */
3239 if (true_regnum (sum1
) < 1 || true_regnum (sum1
) > 15)
3241 emit_move_insn (scratch
, sum1
);
3244 if (true_regnum (sum2
) < 1 || true_regnum (sum2
) > 15)
3246 emit_move_insn (scratch
, sum2
);
3250 /* According to the way these invalid addresses are generated
3251 in reload.c, it should never happen (at least on s390) that
3252 *neither* of the PLUS components, after find_replacements
3253 was applied, is an address register. */
3254 if (sum1
== scratch
&& sum2
== scratch
)
3260 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
3263 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3264 is only ever performed on addresses, so we can mark the
3265 sum as legitimate for LA in any case. */
3266 s390_load_address (target
, src
);
3270 /* Return true if ADDR is a valid memory address.
3271 STRICT specifies whether strict register checking applies. */
3274 s390_legitimate_address_p (enum machine_mode mode
, rtx addr
, bool strict
)
3276 struct s390_address ad
;
3279 && larl_operand (addr
, VOIDmode
)
3280 && (mode
== VOIDmode
3281 || s390_check_symref_alignment (addr
, GET_MODE_SIZE (mode
))))
3284 if (!s390_decompose_address (addr
, &ad
))
3289 if (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
3292 if (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
)))
3298 && !(REGNO (ad
.base
) >= FIRST_PSEUDO_REGISTER
3299 || REGNO_REG_CLASS (REGNO (ad
.base
)) == ADDR_REGS
))
3303 && !(REGNO (ad
.indx
) >= FIRST_PSEUDO_REGISTER
3304 || REGNO_REG_CLASS (REGNO (ad
.indx
)) == ADDR_REGS
))
3310 /* Return true if OP is a valid operand for the LA instruction.
3311 In 31-bit, we need to prove that the result is used as an
3312 address, as LA performs only a 31-bit addition. */
3315 legitimate_la_operand_p (rtx op
)
3317 struct s390_address addr
;
3318 if (!s390_decompose_address (op
, &addr
))
3321 return (TARGET_64BIT
|| addr
.pointer
);
3324 /* Return true if it is valid *and* preferable to use LA to
3325 compute the sum of OP1 and OP2. */
3328 preferred_la_operand_p (rtx op1
, rtx op2
)
3330 struct s390_address addr
;
3332 if (op2
!= const0_rtx
)
3333 op1
= gen_rtx_PLUS (Pmode
, op1
, op2
);
3335 if (!s390_decompose_address (op1
, &addr
))
3337 if (addr
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (addr
.base
)))
3339 if (addr
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (addr
.indx
)))
3342 /* Avoid LA instructions with index register on z196; it is
3343 preferable to use regular add instructions when possible. */
3344 if (addr
.indx
&& s390_tune
== PROCESSOR_2817_Z196
)
3347 if (!TARGET_64BIT
&& !addr
.pointer
)
3353 if ((addr
.base
&& REG_P (addr
.base
) && REG_POINTER (addr
.base
))
3354 || (addr
.indx
&& REG_P (addr
.indx
) && REG_POINTER (addr
.indx
)))
3360 /* Emit a forced load-address operation to load SRC into DST.
3361 This will use the LOAD ADDRESS instruction even in situations
3362 where legitimate_la_operand_p (SRC) returns false. */
3365 s390_load_address (rtx dst
, rtx src
)
3368 emit_move_insn (dst
, src
);
3370 emit_insn (gen_force_la_31 (dst
, src
));
3373 /* Return a legitimate reference for ORIG (an address) using the
3374 register REG. If REG is 0, a new pseudo is generated.
3376 There are two types of references that must be handled:
3378 1. Global data references must load the address from the GOT, via
3379 the PIC reg. An insn is emitted to do this load, and the reg is
3382 2. Static data references, constant pool addresses, and code labels
3383 compute the address as an offset from the GOT, whose base is in
3384 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3385 differentiate them from global data objects. The returned
3386 address is the PIC reg + an unspec constant.
3388 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3389 reg also appears in the address. */
3392 legitimize_pic_address (rtx orig
, rtx reg
)
3398 gcc_assert (!TLS_SYMBOLIC_CONST (addr
));
3400 if (GET_CODE (addr
) == LABEL_REF
3401 || (GET_CODE (addr
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (addr
)))
3403 /* This is a local symbol. */
3404 if (TARGET_CPU_ZARCH
&& larl_operand (addr
, VOIDmode
))
3406 /* Access local symbols PC-relative via LARL.
3407 This is the same as in the non-PIC case, so it is
3408 handled automatically ... */
3412 /* Access local symbols relative to the GOT. */
3414 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3416 if (reload_in_progress
|| reload_completed
)
3417 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3419 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTOFF
);
3420 addr
= gen_rtx_CONST (Pmode
, addr
);
3421 addr
= force_const_mem (Pmode
, addr
);
3422 emit_move_insn (temp
, addr
);
3424 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3427 s390_load_address (reg
, new_rtx
);
3432 else if (GET_CODE (addr
) == SYMBOL_REF
)
3435 reg
= gen_reg_rtx (Pmode
);
3439 /* Assume GOT offset < 4k. This is handled the same way
3440 in both 31- and 64-bit code (@GOT). */
3442 if (reload_in_progress
|| reload_completed
)
3443 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3445 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
3446 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3447 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new_rtx
);
3448 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3449 emit_move_insn (reg
, new_rtx
);
3452 else if (TARGET_CPU_ZARCH
)
3454 /* If the GOT offset might be >= 4k, we determine the position
3455 of the GOT entry via a PC-relative LARL (@GOTENT). */
3457 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3459 gcc_assert (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
3460 || REGNO_REG_CLASS (REGNO (temp
)) == ADDR_REGS
);
3462 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTENT
);
3463 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3464 emit_move_insn (temp
, new_rtx
);
3466 new_rtx
= gen_const_mem (Pmode
, temp
);
3467 emit_move_insn (reg
, new_rtx
);
3472 /* If the GOT offset might be >= 4k, we have to load it
3473 from the literal pool (@GOT). */
3475 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3477 gcc_assert (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
3478 || REGNO_REG_CLASS (REGNO (temp
)) == ADDR_REGS
);
3480 if (reload_in_progress
|| reload_completed
)
3481 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3483 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
3484 addr
= gen_rtx_CONST (Pmode
, addr
);
3485 addr
= force_const_mem (Pmode
, addr
);
3486 emit_move_insn (temp
, addr
);
3488 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3489 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3490 emit_move_insn (reg
, new_rtx
);
3496 if (GET_CODE (addr
) == CONST
)
3498 addr
= XEXP (addr
, 0);
3499 if (GET_CODE (addr
) == UNSPEC
)
3501 gcc_assert (XVECLEN (addr
, 0) == 1);
3502 switch (XINT (addr
, 1))
3504 /* If someone moved a GOT-relative UNSPEC
3505 out of the literal pool, force them back in. */
3508 new_rtx
= force_const_mem (Pmode
, orig
);
3511 /* @GOT is OK as is if small. */
3514 new_rtx
= force_const_mem (Pmode
, orig
);
3517 /* @GOTENT is OK as is. */
3521 /* @PLT is OK as is on 64-bit, must be converted to
3522 GOT-relative @PLTOFF on 31-bit. */
3524 if (!TARGET_CPU_ZARCH
)
3526 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3528 if (reload_in_progress
|| reload_completed
)
3529 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3531 addr
= XVECEXP (addr
, 0, 0);
3532 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
),
3534 addr
= gen_rtx_CONST (Pmode
, addr
);
3535 addr
= force_const_mem (Pmode
, addr
);
3536 emit_move_insn (temp
, addr
);
3538 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3541 s390_load_address (reg
, new_rtx
);
3547 /* Everything else cannot happen. */
3553 gcc_assert (GET_CODE (addr
) == PLUS
);
3555 if (GET_CODE (addr
) == PLUS
)
3557 rtx op0
= XEXP (addr
, 0), op1
= XEXP (addr
, 1);
3559 gcc_assert (!TLS_SYMBOLIC_CONST (op0
));
3560 gcc_assert (!TLS_SYMBOLIC_CONST (op1
));
3562 /* Check first to see if this is a constant offset
3563 from a local symbol reference. */
3564 if ((GET_CODE (op0
) == LABEL_REF
3565 || (GET_CODE (op0
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op0
)))
3566 && GET_CODE (op1
) == CONST_INT
)
3568 if (TARGET_CPU_ZARCH
3569 && larl_operand (op0
, VOIDmode
)
3570 && INTVAL (op1
) < (HOST_WIDE_INT
)1 << 31
3571 && INTVAL (op1
) >= -((HOST_WIDE_INT
)1 << 31))
3573 if (INTVAL (op1
) & 1)
3575 /* LARL can't handle odd offsets, so emit a
3576 pair of LARL and LA. */
3577 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3579 if (!DISP_IN_RANGE (INTVAL (op1
)))
3581 HOST_WIDE_INT even
= INTVAL (op1
) - 1;
3582 op0
= gen_rtx_PLUS (Pmode
, op0
, GEN_INT (even
));
3583 op0
= gen_rtx_CONST (Pmode
, op0
);
3587 emit_move_insn (temp
, op0
);
3588 new_rtx
= gen_rtx_PLUS (Pmode
, temp
, op1
);
3592 s390_load_address (reg
, new_rtx
);
3598 /* If the offset is even, we can just use LARL.
3599 This will happen automatically. */
3604 /* Access local symbols relative to the GOT. */
3606 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3608 if (reload_in_progress
|| reload_completed
)
3609 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3611 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op0
),
3613 addr
= gen_rtx_PLUS (Pmode
, addr
, op1
);
3614 addr
= gen_rtx_CONST (Pmode
, addr
);
3615 addr
= force_const_mem (Pmode
, addr
);
3616 emit_move_insn (temp
, addr
);
3618 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3621 s390_load_address (reg
, new_rtx
);
3627 /* Now, check whether it is a GOT relative symbol plus offset
3628 that was pulled out of the literal pool. Force it back in. */
3630 else if (GET_CODE (op0
) == UNSPEC
3631 && GET_CODE (op1
) == CONST_INT
3632 && XINT (op0
, 1) == UNSPEC_GOTOFF
)
3634 gcc_assert (XVECLEN (op0
, 0) == 1);
3636 new_rtx
= force_const_mem (Pmode
, orig
);
3639 /* Otherwise, compute the sum. */
3642 base
= legitimize_pic_address (XEXP (addr
, 0), reg
);
3643 new_rtx
= legitimize_pic_address (XEXP (addr
, 1),
3644 base
== reg
? NULL_RTX
: reg
);
3645 if (GET_CODE (new_rtx
) == CONST_INT
)
3646 new_rtx
= plus_constant (base
, INTVAL (new_rtx
));
3649 if (GET_CODE (new_rtx
) == PLUS
&& CONSTANT_P (XEXP (new_rtx
, 1)))
3651 base
= gen_rtx_PLUS (Pmode
, base
, XEXP (new_rtx
, 0));
3652 new_rtx
= XEXP (new_rtx
, 1);
3654 new_rtx
= gen_rtx_PLUS (Pmode
, base
, new_rtx
);
3657 if (GET_CODE (new_rtx
) == CONST
)
3658 new_rtx
= XEXP (new_rtx
, 0);
3659 new_rtx
= force_operand (new_rtx
, 0);
3666 /* Load the thread pointer into a register. */
3669 s390_get_thread_pointer (void)
3671 rtx tp
= gen_reg_rtx (Pmode
);
3673 emit_move_insn (tp
, gen_rtx_REG (Pmode
, TP_REGNUM
));
3674 mark_reg_pointer (tp
, BITS_PER_WORD
);
3679 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3680 in s390_tls_symbol which always refers to __tls_get_offset.
3681 The returned offset is written to RESULT_REG and an USE rtx is
3682 generated for TLS_CALL. */
3684 static GTY(()) rtx s390_tls_symbol
;
3687 s390_emit_tls_call_insn (rtx result_reg
, rtx tls_call
)
3691 gcc_assert (flag_pic
);
3693 if (!s390_tls_symbol
)
3694 s390_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_offset");
3696 insn
= s390_emit_call (s390_tls_symbol
, tls_call
, result_reg
,
3697 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
3699 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), result_reg
);
3700 RTL_CONST_CALL_P (insn
) = 1;
3703 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3704 this (thread-local) address. REG may be used as temporary. */
3707 legitimize_tls_address (rtx addr
, rtx reg
)
3709 rtx new_rtx
, tls_call
, temp
, base
, r2
, insn
;
3711 if (GET_CODE (addr
) == SYMBOL_REF
)
3712 switch (tls_symbolic_operand (addr
))
3714 case TLS_MODEL_GLOBAL_DYNAMIC
:
3716 r2
= gen_rtx_REG (Pmode
, 2);
3717 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_TLSGD
);
3718 new_rtx
= gen_rtx_CONST (Pmode
, tls_call
);
3719 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3720 emit_move_insn (r2
, new_rtx
);
3721 s390_emit_tls_call_insn (r2
, tls_call
);
3722 insn
= get_insns ();
3725 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
3726 temp
= gen_reg_rtx (Pmode
);
3727 emit_libcall_block (insn
, temp
, r2
, new_rtx
);
3729 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3732 s390_load_address (reg
, new_rtx
);
3737 case TLS_MODEL_LOCAL_DYNAMIC
:
3739 r2
= gen_rtx_REG (Pmode
, 2);
3740 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM
);
3741 new_rtx
= gen_rtx_CONST (Pmode
, tls_call
);
3742 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3743 emit_move_insn (r2
, new_rtx
);
3744 s390_emit_tls_call_insn (r2
, tls_call
);
3745 insn
= get_insns ();
3748 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM_NTPOFF
);
3749 temp
= gen_reg_rtx (Pmode
);
3750 emit_libcall_block (insn
, temp
, r2
, new_rtx
);
3752 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3753 base
= gen_reg_rtx (Pmode
);
3754 s390_load_address (base
, new_rtx
);
3756 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_DTPOFF
);
3757 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3758 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3759 temp
= gen_reg_rtx (Pmode
);
3760 emit_move_insn (temp
, new_rtx
);
3762 new_rtx
= gen_rtx_PLUS (Pmode
, base
, temp
);
3765 s390_load_address (reg
, new_rtx
);
3770 case TLS_MODEL_INITIAL_EXEC
:
3773 /* Assume GOT offset < 4k. This is handled the same way
3774 in both 31- and 64-bit code. */
3776 if (reload_in_progress
|| reload_completed
)
3777 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3779 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
3780 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3781 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new_rtx
);
3782 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3783 temp
= gen_reg_rtx (Pmode
);
3784 emit_move_insn (temp
, new_rtx
);
3786 else if (TARGET_CPU_ZARCH
)
3788 /* If the GOT offset might be >= 4k, we determine the position
3789 of the GOT entry via a PC-relative LARL. */
3791 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
3792 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3793 temp
= gen_reg_rtx (Pmode
);
3794 emit_move_insn (temp
, new_rtx
);
3796 new_rtx
= gen_const_mem (Pmode
, temp
);
3797 temp
= gen_reg_rtx (Pmode
);
3798 emit_move_insn (temp
, new_rtx
);
3802 /* If the GOT offset might be >= 4k, we have to load it
3803 from the literal pool. */
3805 if (reload_in_progress
|| reload_completed
)
3806 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3808 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
3809 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3810 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3811 temp
= gen_reg_rtx (Pmode
);
3812 emit_move_insn (temp
, new_rtx
);
3814 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3815 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3817 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new_rtx
, addr
), UNSPEC_TLS_LOAD
);
3818 temp
= gen_reg_rtx (Pmode
);
3819 emit_insn (gen_rtx_SET (Pmode
, temp
, new_rtx
));
3823 /* In position-dependent code, load the absolute address of
3824 the GOT entry from the literal pool. */
3826 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
3827 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3828 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3829 temp
= gen_reg_rtx (Pmode
);
3830 emit_move_insn (temp
, new_rtx
);
3833 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
3834 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new_rtx
, addr
), UNSPEC_TLS_LOAD
);
3835 temp
= gen_reg_rtx (Pmode
);
3836 emit_insn (gen_rtx_SET (Pmode
, temp
, new_rtx
));
3839 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3842 s390_load_address (reg
, new_rtx
);
3847 case TLS_MODEL_LOCAL_EXEC
:
3848 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
3849 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3850 new_rtx
= force_const_mem (Pmode
, new_rtx
);
3851 temp
= gen_reg_rtx (Pmode
);
3852 emit_move_insn (temp
, new_rtx
);
3854 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3857 s390_load_address (reg
, new_rtx
);
3866 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == UNSPEC
)
3868 switch (XINT (XEXP (addr
, 0), 1))
3870 case UNSPEC_INDNTPOFF
:
3871 gcc_assert (TARGET_CPU_ZARCH
);
3880 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == PLUS
3881 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST_INT
)
3883 new_rtx
= XEXP (XEXP (addr
, 0), 0);
3884 if (GET_CODE (new_rtx
) != SYMBOL_REF
)
3885 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
3887 new_rtx
= legitimize_tls_address (new_rtx
, reg
);
3888 new_rtx
= plus_constant (new_rtx
, INTVAL (XEXP (XEXP (addr
, 0), 1)));
3889 new_rtx
= force_operand (new_rtx
, 0);
3893 gcc_unreachable (); /* for now ... */
3898 /* Emit insns making the address in operands[1] valid for a standard
3899 move to operands[0]. operands[1] is replaced by an address which
3900 should be used instead of the former RTX to emit the move
3904 emit_symbolic_move (rtx
*operands
)
3906 rtx temp
= !can_create_pseudo_p () ? operands
[0] : gen_reg_rtx (Pmode
);
3908 if (GET_CODE (operands
[0]) == MEM
)
3909 operands
[1] = force_reg (Pmode
, operands
[1]);
3910 else if (TLS_SYMBOLIC_CONST (operands
[1]))
3911 operands
[1] = legitimize_tls_address (operands
[1], temp
);
3913 operands
[1] = legitimize_pic_address (operands
[1], temp
);
3916 /* Try machine-dependent ways of modifying an illegitimate address X
3917 to be legitimate. If we find one, return the new, valid address.
3919 OLDX is the address as it was before break_out_memory_refs was called.
3920 In some cases it is useful to look at this to decide what needs to be done.
3922 MODE is the mode of the operand pointed to by X.
3924 When -fpic is used, special handling is needed for symbolic references.
3925 See comments by legitimize_pic_address for details. */
3928 s390_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3929 enum machine_mode mode ATTRIBUTE_UNUSED
)
3931 rtx constant_term
= const0_rtx
;
3933 if (TLS_SYMBOLIC_CONST (x
))
3935 x
= legitimize_tls_address (x
, 0);
3937 if (s390_legitimate_address_p (mode
, x
, FALSE
))
3940 else if (GET_CODE (x
) == PLUS
3941 && (TLS_SYMBOLIC_CONST (XEXP (x
, 0))
3942 || TLS_SYMBOLIC_CONST (XEXP (x
, 1))))
3948 if (SYMBOLIC_CONST (x
)
3949 || (GET_CODE (x
) == PLUS
3950 && (SYMBOLIC_CONST (XEXP (x
, 0))
3951 || SYMBOLIC_CONST (XEXP (x
, 1)))))
3952 x
= legitimize_pic_address (x
, 0);
3954 if (s390_legitimate_address_p (mode
, x
, FALSE
))
3958 x
= eliminate_constant_term (x
, &constant_term
);
3960 /* Optimize loading of large displacements by splitting them
3961 into the multiple of 4K and the rest; this allows the
3962 former to be CSE'd if possible.
3964 Don't do this if the displacement is added to a register
3965 pointing into the stack frame, as the offsets will
3966 change later anyway. */
3968 if (GET_CODE (constant_term
) == CONST_INT
3969 && !TARGET_LONG_DISPLACEMENT
3970 && !DISP_IN_RANGE (INTVAL (constant_term
))
3971 && !(REG_P (x
) && REGNO_PTR_FRAME_P (REGNO (x
))))
3973 HOST_WIDE_INT lower
= INTVAL (constant_term
) & 0xfff;
3974 HOST_WIDE_INT upper
= INTVAL (constant_term
) ^ lower
;
3976 rtx temp
= gen_reg_rtx (Pmode
);
3977 rtx val
= force_operand (GEN_INT (upper
), temp
);
3979 emit_move_insn (temp
, val
);
3981 x
= gen_rtx_PLUS (Pmode
, x
, temp
);
3982 constant_term
= GEN_INT (lower
);
3985 if (GET_CODE (x
) == PLUS
)
3987 if (GET_CODE (XEXP (x
, 0)) == REG
)
3989 rtx temp
= gen_reg_rtx (Pmode
);
3990 rtx val
= force_operand (XEXP (x
, 1), temp
);
3992 emit_move_insn (temp
, val
);
3994 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0), temp
);
3997 else if (GET_CODE (XEXP (x
, 1)) == REG
)
3999 rtx temp
= gen_reg_rtx (Pmode
);
4000 rtx val
= force_operand (XEXP (x
, 0), temp
);
4002 emit_move_insn (temp
, val
);
4004 x
= gen_rtx_PLUS (Pmode
, temp
, XEXP (x
, 1));
4008 if (constant_term
!= const0_rtx
)
4009 x
= gen_rtx_PLUS (Pmode
, x
, constant_term
);
4014 /* Try a machine-dependent way of reloading an illegitimate address AD
4015 operand. If we find one, push the reload and return the new address.
4017 MODE is the mode of the enclosing MEM. OPNUM is the operand number
4018 and TYPE is the reload type of the current reload. */
4021 legitimize_reload_address (rtx ad
, enum machine_mode mode ATTRIBUTE_UNUSED
,
4022 int opnum
, int type
)
4024 if (!optimize
|| TARGET_LONG_DISPLACEMENT
)
4027 if (GET_CODE (ad
) == PLUS
)
4029 rtx tem
= simplify_binary_operation (PLUS
, Pmode
,
4030 XEXP (ad
, 0), XEXP (ad
, 1));
4035 if (GET_CODE (ad
) == PLUS
4036 && GET_CODE (XEXP (ad
, 0)) == REG
4037 && GET_CODE (XEXP (ad
, 1)) == CONST_INT
4038 && !DISP_IN_RANGE (INTVAL (XEXP (ad
, 1))))
4040 HOST_WIDE_INT lower
= INTVAL (XEXP (ad
, 1)) & 0xfff;
4041 HOST_WIDE_INT upper
= INTVAL (XEXP (ad
, 1)) ^ lower
;
4042 rtx cst
, tem
, new_rtx
;
4044 cst
= GEN_INT (upper
);
4045 if (!legitimate_reload_constant_p (cst
))
4046 cst
= force_const_mem (Pmode
, cst
);
4048 tem
= gen_rtx_PLUS (Pmode
, XEXP (ad
, 0), cst
);
4049 new_rtx
= gen_rtx_PLUS (Pmode
, tem
, GEN_INT (lower
));
4051 push_reload (XEXP (tem
, 1), 0, &XEXP (tem
, 1), 0,
4052 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
4053 opnum
, (enum reload_type
) type
);
4060 /* Emit code to move LEN bytes from DST to SRC. */
4063 s390_expand_movmem (rtx dst
, rtx src
, rtx len
)
4065 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
4067 if (INTVAL (len
) > 0)
4068 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (INTVAL (len
) - 1)));
4071 else if (TARGET_MVCLE
)
4073 emit_insn (gen_movmem_long (dst
, src
, convert_to_mode (Pmode
, len
, 1)));
4078 rtx dst_addr
, src_addr
, count
, blocks
, temp
;
4079 rtx loop_start_label
= gen_label_rtx ();
4080 rtx loop_end_label
= gen_label_rtx ();
4081 rtx end_label
= gen_label_rtx ();
4082 enum machine_mode mode
;
4084 mode
= GET_MODE (len
);
4085 if (mode
== VOIDmode
)
4088 dst_addr
= gen_reg_rtx (Pmode
);
4089 src_addr
= gen_reg_rtx (Pmode
);
4090 count
= gen_reg_rtx (mode
);
4091 blocks
= gen_reg_rtx (mode
);
4093 convert_move (count
, len
, 1);
4094 emit_cmp_and_jump_insns (count
, const0_rtx
,
4095 EQ
, NULL_RTX
, mode
, 1, end_label
);
4097 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
4098 emit_move_insn (src_addr
, force_operand (XEXP (src
, 0), NULL_RTX
));
4099 dst
= change_address (dst
, VOIDmode
, dst_addr
);
4100 src
= change_address (src
, VOIDmode
, src_addr
);
4102 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4105 emit_move_insn (count
, temp
);
4107 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4110 emit_move_insn (blocks
, temp
);
4112 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4113 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4115 emit_label (loop_start_label
);
4118 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 768))
4122 /* Issue a read prefetch for the +3 cache line. */
4123 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, src_addr
, GEN_INT (768)),
4124 const0_rtx
, const0_rtx
);
4125 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4126 emit_insn (prefetch
);
4128 /* Issue a write prefetch for the +3 cache line. */
4129 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (768)),
4130 const1_rtx
, const0_rtx
);
4131 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4132 emit_insn (prefetch
);
4135 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (255)));
4136 s390_load_address (dst_addr
,
4137 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
4138 s390_load_address (src_addr
,
4139 gen_rtx_PLUS (Pmode
, src_addr
, GEN_INT (256)));
4141 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4144 emit_move_insn (blocks
, temp
);
4146 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4147 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4149 emit_jump (loop_start_label
);
4150 emit_label (loop_end_label
);
4152 emit_insn (gen_movmem_short (dst
, src
,
4153 convert_to_mode (Pmode
, count
, 1)));
4154 emit_label (end_label
);
4158 /* Emit code to set LEN bytes at DST to VAL.
4159 Make use of clrmem if VAL is zero. */
4162 s390_expand_setmem (rtx dst
, rtx len
, rtx val
)
4164 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) == 0)
4167 gcc_assert (GET_CODE (val
) == CONST_INT
|| GET_MODE (val
) == QImode
);
4169 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) > 0 && INTVAL (len
) <= 257)
4171 if (val
== const0_rtx
&& INTVAL (len
) <= 256)
4172 emit_insn (gen_clrmem_short (dst
, GEN_INT (INTVAL (len
) - 1)));
4175 /* Initialize memory by storing the first byte. */
4176 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
4178 if (INTVAL (len
) > 1)
4180 /* Initiate 1 byte overlap move.
4181 The first byte of DST is propagated through DSTP1.
4182 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
4183 DST is set to size 1 so the rest of the memory location
4184 does not count as source operand. */
4185 rtx dstp1
= adjust_address (dst
, VOIDmode
, 1);
4186 set_mem_size (dst
, const1_rtx
);
4188 emit_insn (gen_movmem_short (dstp1
, dst
,
4189 GEN_INT (INTVAL (len
) - 2)));
4194 else if (TARGET_MVCLE
)
4196 val
= force_not_mem (convert_modes (Pmode
, QImode
, val
, 1));
4197 emit_insn (gen_setmem_long (dst
, convert_to_mode (Pmode
, len
, 1), val
));
4202 rtx dst_addr
, count
, blocks
, temp
, dstp1
= NULL_RTX
;
4203 rtx loop_start_label
= gen_label_rtx ();
4204 rtx loop_end_label
= gen_label_rtx ();
4205 rtx end_label
= gen_label_rtx ();
4206 enum machine_mode mode
;
4208 mode
= GET_MODE (len
);
4209 if (mode
== VOIDmode
)
4212 dst_addr
= gen_reg_rtx (Pmode
);
4213 count
= gen_reg_rtx (mode
);
4214 blocks
= gen_reg_rtx (mode
);
4216 convert_move (count
, len
, 1);
4217 emit_cmp_and_jump_insns (count
, const0_rtx
,
4218 EQ
, NULL_RTX
, mode
, 1, end_label
);
4220 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
4221 dst
= change_address (dst
, VOIDmode
, dst_addr
);
4223 if (val
== const0_rtx
)
4224 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4228 dstp1
= adjust_address (dst
, VOIDmode
, 1);
4229 set_mem_size (dst
, const1_rtx
);
4231 /* Initialize memory by storing the first byte. */
4232 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
4234 /* If count is 1 we are done. */
4235 emit_cmp_and_jump_insns (count
, const1_rtx
,
4236 EQ
, NULL_RTX
, mode
, 1, end_label
);
4238 temp
= expand_binop (mode
, add_optab
, count
, GEN_INT (-2), count
, 1,
4242 emit_move_insn (count
, temp
);
4244 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4247 emit_move_insn (blocks
, temp
);
4249 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4250 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4252 emit_label (loop_start_label
);
4255 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 1024))
4257 /* Issue a write prefetch for the +4 cache line. */
4258 rtx prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, dst_addr
,
4260 const1_rtx
, const0_rtx
);
4261 emit_insn (prefetch
);
4262 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4265 if (val
== const0_rtx
)
4266 emit_insn (gen_clrmem_short (dst
, GEN_INT (255)));
4268 emit_insn (gen_movmem_short (dstp1
, dst
, GEN_INT (255)));
4269 s390_load_address (dst_addr
,
4270 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
4272 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4275 emit_move_insn (blocks
, temp
);
4277 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4278 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4280 emit_jump (loop_start_label
);
4281 emit_label (loop_end_label
);
4283 if (val
== const0_rtx
)
4284 emit_insn (gen_clrmem_short (dst
, convert_to_mode (Pmode
, count
, 1)));
4286 emit_insn (gen_movmem_short (dstp1
, dst
, convert_to_mode (Pmode
, count
, 1)));
4287 emit_label (end_label
);
4291 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4292 and return the result in TARGET. */
4295 s390_expand_cmpmem (rtx target
, rtx op0
, rtx op1
, rtx len
)
4297 rtx ccreg
= gen_rtx_REG (CCUmode
, CC_REGNUM
);
4300 /* As the result of CMPINT is inverted compared to what we need,
4301 we have to swap the operands. */
4302 tmp
= op0
; op0
= op1
; op1
= tmp
;
4304 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
4306 if (INTVAL (len
) > 0)
4308 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (INTVAL (len
) - 1)));
4309 emit_insn (gen_cmpint (target
, ccreg
));
4312 emit_move_insn (target
, const0_rtx
);
4314 else if (TARGET_MVCLE
)
4316 emit_insn (gen_cmpmem_long (op0
, op1
, convert_to_mode (Pmode
, len
, 1)));
4317 emit_insn (gen_cmpint (target
, ccreg
));
4321 rtx addr0
, addr1
, count
, blocks
, temp
;
4322 rtx loop_start_label
= gen_label_rtx ();
4323 rtx loop_end_label
= gen_label_rtx ();
4324 rtx end_label
= gen_label_rtx ();
4325 enum machine_mode mode
;
4327 mode
= GET_MODE (len
);
4328 if (mode
== VOIDmode
)
4331 addr0
= gen_reg_rtx (Pmode
);
4332 addr1
= gen_reg_rtx (Pmode
);
4333 count
= gen_reg_rtx (mode
);
4334 blocks
= gen_reg_rtx (mode
);
4336 convert_move (count
, len
, 1);
4337 emit_cmp_and_jump_insns (count
, const0_rtx
,
4338 EQ
, NULL_RTX
, mode
, 1, end_label
);
4340 emit_move_insn (addr0
, force_operand (XEXP (op0
, 0), NULL_RTX
));
4341 emit_move_insn (addr1
, force_operand (XEXP (op1
, 0), NULL_RTX
));
4342 op0
= change_address (op0
, VOIDmode
, addr0
);
4343 op1
= change_address (op1
, VOIDmode
, addr1
);
4345 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
4348 emit_move_insn (count
, temp
);
4350 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
4353 emit_move_insn (blocks
, temp
);
4355 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4356 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4358 emit_label (loop_start_label
);
4361 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 512))
4365 /* Issue a read prefetch for the +2 cache line of operand 1. */
4366 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, addr0
, GEN_INT (512)),
4367 const0_rtx
, const0_rtx
);
4368 emit_insn (prefetch
);
4369 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4371 /* Issue a read prefetch for the +2 cache line of operand 2. */
4372 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, addr1
, GEN_INT (512)),
4373 const0_rtx
, const0_rtx
);
4374 emit_insn (prefetch
);
4375 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
4378 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (255)));
4379 temp
= gen_rtx_NE (VOIDmode
, ccreg
, const0_rtx
);
4380 temp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, temp
,
4381 gen_rtx_LABEL_REF (VOIDmode
, end_label
), pc_rtx
);
4382 temp
= gen_rtx_SET (VOIDmode
, pc_rtx
, temp
);
4383 emit_jump_insn (temp
);
4385 s390_load_address (addr0
,
4386 gen_rtx_PLUS (Pmode
, addr0
, GEN_INT (256)));
4387 s390_load_address (addr1
,
4388 gen_rtx_PLUS (Pmode
, addr1
, GEN_INT (256)));
4390 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
4393 emit_move_insn (blocks
, temp
);
4395 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
4396 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
4398 emit_jump (loop_start_label
);
4399 emit_label (loop_end_label
);
4401 emit_insn (gen_cmpmem_short (op0
, op1
,
4402 convert_to_mode (Pmode
, count
, 1)));
4403 emit_label (end_label
);
4405 emit_insn (gen_cmpint (target
, ccreg
));
4410 /* Expand conditional increment or decrement using alc/slb instructions.
4411 Should generate code setting DST to either SRC or SRC + INCREMENT,
4412 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4413 Returns true if successful, false otherwise.
4415 That makes it possible to implement some if-constructs without jumps e.g.:
4416 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4417 unsigned int a, b, c;
4418 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4419 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4420 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4421 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4423 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4424 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4425 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4426 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4427 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4430 s390_expand_addcc (enum rtx_code cmp_code
, rtx cmp_op0
, rtx cmp_op1
,
4431 rtx dst
, rtx src
, rtx increment
)
4433 enum machine_mode cmp_mode
;
4434 enum machine_mode cc_mode
;
4440 if ((GET_MODE (cmp_op0
) == SImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
4441 && (GET_MODE (cmp_op1
) == SImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
4443 else if ((GET_MODE (cmp_op0
) == DImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
4444 && (GET_MODE (cmp_op1
) == DImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
4449 /* Try ADD LOGICAL WITH CARRY. */
4450 if (increment
== const1_rtx
)
4452 /* Determine CC mode to use. */
4453 if (cmp_code
== EQ
|| cmp_code
== NE
)
4455 if (cmp_op1
!= const0_rtx
)
4457 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
4458 NULL_RTX
, 0, OPTAB_WIDEN
);
4459 cmp_op1
= const0_rtx
;
4462 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
4465 if (cmp_code
== LTU
|| cmp_code
== LEU
)
4470 cmp_code
= swap_condition (cmp_code
);
4487 /* Emit comparison instruction pattern. */
4488 if (!register_operand (cmp_op0
, cmp_mode
))
4489 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
4491 insn
= gen_rtx_SET (VOIDmode
, gen_rtx_REG (cc_mode
, CC_REGNUM
),
4492 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
4493 /* We use insn_invalid_p here to add clobbers if required. */
4494 ret
= insn_invalid_p (emit_insn (insn
));
4497 /* Emit ALC instruction pattern. */
4498 op_res
= gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
4499 gen_rtx_REG (cc_mode
, CC_REGNUM
),
4502 if (src
!= const0_rtx
)
4504 if (!register_operand (src
, GET_MODE (dst
)))
4505 src
= force_reg (GET_MODE (dst
), src
);
4507 op_res
= gen_rtx_PLUS (GET_MODE (dst
), op_res
, src
);
4508 op_res
= gen_rtx_PLUS (GET_MODE (dst
), op_res
, const0_rtx
);
4511 p
= rtvec_alloc (2);
4513 gen_rtx_SET (VOIDmode
, dst
, op_res
);
4515 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4516 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
4521 /* Try SUBTRACT LOGICAL WITH BORROW. */
4522 if (increment
== constm1_rtx
)
4524 /* Determine CC mode to use. */
4525 if (cmp_code
== EQ
|| cmp_code
== NE
)
4527 if (cmp_op1
!= const0_rtx
)
4529 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
4530 NULL_RTX
, 0, OPTAB_WIDEN
);
4531 cmp_op1
= const0_rtx
;
4534 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
4537 if (cmp_code
== GTU
|| cmp_code
== GEU
)
4542 cmp_code
= swap_condition (cmp_code
);
4559 /* Emit comparison instruction pattern. */
4560 if (!register_operand (cmp_op0
, cmp_mode
))
4561 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
4563 insn
= gen_rtx_SET (VOIDmode
, gen_rtx_REG (cc_mode
, CC_REGNUM
),
4564 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
4565 /* We use insn_invalid_p here to add clobbers if required. */
4566 ret
= insn_invalid_p (emit_insn (insn
));
4569 /* Emit SLB instruction pattern. */
4570 if (!register_operand (src
, GET_MODE (dst
)))
4571 src
= force_reg (GET_MODE (dst
), src
);
4573 op_res
= gen_rtx_MINUS (GET_MODE (dst
),
4574 gen_rtx_MINUS (GET_MODE (dst
), src
, const0_rtx
),
4575 gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
4576 gen_rtx_REG (cc_mode
, CC_REGNUM
),
4578 p
= rtvec_alloc (2);
4580 gen_rtx_SET (VOIDmode
, dst
, op_res
);
4582 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4583 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
4591 /* Expand code for the insv template. Return true if successful. */
4594 s390_expand_insv (rtx dest
, rtx op1
, rtx op2
, rtx src
)
4596 int bitsize
= INTVAL (op1
);
4597 int bitpos
= INTVAL (op2
);
4599 /* On z10 we can use the risbg instruction to implement insv. */
4601 && ((GET_MODE (dest
) == DImode
&& GET_MODE (src
) == DImode
)
4602 || (GET_MODE (dest
) == SImode
&& GET_MODE (src
) == SImode
)))
4607 op
= gen_rtx_SET (GET_MODE(src
),
4608 gen_rtx_ZERO_EXTRACT (GET_MODE (dest
), dest
, op1
, op2
),
4610 clobber
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4611 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clobber
)));
4616 /* We need byte alignment. */
4617 if (bitsize
% BITS_PER_UNIT
)
4621 && memory_operand (dest
, VOIDmode
)
4622 && (register_operand (src
, word_mode
)
4623 || const_int_operand (src
, VOIDmode
)))
4625 /* Emit standard pattern if possible. */
4626 enum machine_mode mode
= smallest_mode_for_size (bitsize
, MODE_INT
);
4627 if (GET_MODE_BITSIZE (mode
) == bitsize
)
4628 emit_move_insn (adjust_address (dest
, mode
, 0), gen_lowpart (mode
, src
));
4630 /* (set (ze (mem)) (const_int)). */
4631 else if (const_int_operand (src
, VOIDmode
))
4633 int size
= bitsize
/ BITS_PER_UNIT
;
4634 rtx src_mem
= adjust_address (force_const_mem (word_mode
, src
), BLKmode
,
4635 GET_MODE_SIZE (word_mode
) - size
);
4637 dest
= adjust_address (dest
, BLKmode
, 0);
4638 set_mem_size (dest
, GEN_INT (size
));
4639 s390_expand_movmem (dest
, src_mem
, GEN_INT (size
));
4642 /* (set (ze (mem)) (reg)). */
4643 else if (register_operand (src
, word_mode
))
4645 if (bitsize
<= GET_MODE_BITSIZE (SImode
))
4646 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
, op1
,
4650 /* Emit st,stcmh sequence. */
4651 int stcmh_width
= bitsize
- GET_MODE_BITSIZE (SImode
);
4652 int size
= stcmh_width
/ BITS_PER_UNIT
;
4654 emit_move_insn (adjust_address (dest
, SImode
, size
),
4655 gen_lowpart (SImode
, src
));
4656 set_mem_size (dest
, GEN_INT (size
));
4657 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
, GEN_INT
4658 (stcmh_width
), const0_rtx
),
4659 gen_rtx_LSHIFTRT (word_mode
, src
, GEN_INT
4660 (GET_MODE_BITSIZE (SImode
))));
4669 /* (set (ze (reg)) (const_int)). */
4671 && register_operand (dest
, word_mode
)
4672 && (bitpos
% 16) == 0
4673 && (bitsize
% 16) == 0
4674 && const_int_operand (src
, VOIDmode
))
4676 HOST_WIDE_INT val
= INTVAL (src
);
4677 int regpos
= bitpos
+ bitsize
;
4679 while (regpos
> bitpos
)
4681 enum machine_mode putmode
;
4684 if (TARGET_EXTIMM
&& (regpos
% 32 == 0) && (regpos
>= bitpos
+ 32))
4689 putsize
= GET_MODE_BITSIZE (putmode
);
4691 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
,
4694 gen_int_mode (val
, putmode
));
4697 gcc_assert (regpos
== bitpos
);
4704 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4705 register that holds VAL of mode MODE shifted by COUNT bits. */
4708 s390_expand_mask_and_shift (rtx val
, enum machine_mode mode
, rtx count
)
4710 val
= expand_simple_binop (SImode
, AND
, val
, GEN_INT (GET_MODE_MASK (mode
)),
4711 NULL_RTX
, 1, OPTAB_DIRECT
);
4712 return expand_simple_binop (SImode
, ASHIFT
, val
, count
,
4713 NULL_RTX
, 1, OPTAB_DIRECT
);
4716 /* Structure to hold the initial parameters for a compare_and_swap operation
4717 in HImode and QImode. */
4719 struct alignment_context
4721 rtx memsi
; /* SI aligned memory location. */
4722 rtx shift
; /* Bit offset with regard to lsb. */
4723 rtx modemask
; /* Mask of the HQImode shifted by SHIFT bits. */
4724 rtx modemaski
; /* ~modemask */
4725 bool aligned
; /* True if memory is aligned, false else. */
4728 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4729 structure AC for transparent simplifying, if the memory alignment is known
4730 to be at least 32bit. MEM is the memory location for the actual operation
4731 and MODE its mode. */
4734 init_alignment_context (struct alignment_context
*ac
, rtx mem
,
4735 enum machine_mode mode
)
4737 ac
->shift
= GEN_INT (GET_MODE_SIZE (SImode
) - GET_MODE_SIZE (mode
));
4738 ac
->aligned
= (MEM_ALIGN (mem
) >= GET_MODE_BITSIZE (SImode
));
4741 ac
->memsi
= adjust_address (mem
, SImode
, 0); /* Memory is aligned. */
4744 /* Alignment is unknown. */
4745 rtx byteoffset
, addr
, align
;
4747 /* Force the address into a register. */
4748 addr
= force_reg (Pmode
, XEXP (mem
, 0));
4750 /* Align it to SImode. */
4751 align
= expand_simple_binop (Pmode
, AND
, addr
,
4752 GEN_INT (-GET_MODE_SIZE (SImode
)),
4753 NULL_RTX
, 1, OPTAB_DIRECT
);
4755 ac
->memsi
= gen_rtx_MEM (SImode
, align
);
4756 MEM_VOLATILE_P (ac
->memsi
) = MEM_VOLATILE_P (mem
);
4757 set_mem_alias_set (ac
->memsi
, ALIAS_SET_MEMORY_BARRIER
);
4758 set_mem_align (ac
->memsi
, GET_MODE_BITSIZE (SImode
));
4760 /* Calculate shiftcount. */
4761 byteoffset
= expand_simple_binop (Pmode
, AND
, addr
,
4762 GEN_INT (GET_MODE_SIZE (SImode
) - 1),
4763 NULL_RTX
, 1, OPTAB_DIRECT
);
4764 /* As we already have some offset, evaluate the remaining distance. */
4765 ac
->shift
= expand_simple_binop (SImode
, MINUS
, ac
->shift
, byteoffset
,
4766 NULL_RTX
, 1, OPTAB_DIRECT
);
4769 /* Shift is the byte count, but we need the bitcount. */
4770 ac
->shift
= expand_simple_binop (SImode
, MULT
, ac
->shift
, GEN_INT (BITS_PER_UNIT
),
4771 NULL_RTX
, 1, OPTAB_DIRECT
);
4772 /* Calculate masks. */
4773 ac
->modemask
= expand_simple_binop (SImode
, ASHIFT
,
4774 GEN_INT (GET_MODE_MASK (mode
)), ac
->shift
,
4775 NULL_RTX
, 1, OPTAB_DIRECT
);
4776 ac
->modemaski
= expand_simple_unop (SImode
, NOT
, ac
->modemask
, NULL_RTX
, 1);
4779 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4780 the memory location, CMP the old value to compare MEM with and NEW_RTX the value
4781 to set if CMP == MEM.
4782 CMP is never in memory for compare_and_swap_cc because
4783 expand_bool_compare_and_swap puts it into a register for later compare. */
4786 s390_expand_cs_hqi (enum machine_mode mode
, rtx target
, rtx mem
, rtx cmp
, rtx new_rtx
)
4788 struct alignment_context ac
;
4789 rtx cmpv
, newv
, val
, resv
, cc
;
4790 rtx res
= gen_reg_rtx (SImode
);
4791 rtx csloop
= gen_label_rtx ();
4792 rtx csend
= gen_label_rtx ();
4794 gcc_assert (register_operand (target
, VOIDmode
));
4795 gcc_assert (MEM_P (mem
));
4797 init_alignment_context (&ac
, mem
, mode
);
4799 /* Shift the values to the correct bit positions. */
4800 if (!(ac
.aligned
&& MEM_P (cmp
)))
4801 cmp
= s390_expand_mask_and_shift (cmp
, mode
, ac
.shift
);
4802 if (!(ac
.aligned
&& MEM_P (new_rtx
)))
4803 new_rtx
= s390_expand_mask_and_shift (new_rtx
, mode
, ac
.shift
);
4805 /* Load full word. Subsequent loads are performed by CS. */
4806 val
= expand_simple_binop (SImode
, AND
, ac
.memsi
, ac
.modemaski
,
4807 NULL_RTX
, 1, OPTAB_DIRECT
);
4809 /* Start CS loop. */
4810 emit_label (csloop
);
4811 /* val = "<mem>00..0<mem>"
4812 * cmp = "00..0<cmp>00..0"
4813 * new = "00..0<new>00..0"
4816 /* Patch cmp and new with val at correct position. */
4817 if (ac
.aligned
&& MEM_P (cmp
))
4819 cmpv
= force_reg (SImode
, val
);
4820 store_bit_field (cmpv
, GET_MODE_BITSIZE (mode
), 0, SImode
, cmp
);
4823 cmpv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, cmp
, val
,
4824 NULL_RTX
, 1, OPTAB_DIRECT
));
4825 if (ac
.aligned
&& MEM_P (new_rtx
))
4827 newv
= force_reg (SImode
, val
);
4828 store_bit_field (newv
, GET_MODE_BITSIZE (mode
), 0, SImode
, new_rtx
);
4831 newv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, new_rtx
, val
,
4832 NULL_RTX
, 1, OPTAB_DIRECT
));
4834 /* Jump to end if we're done (likely?). */
4835 s390_emit_jump (csend
, s390_emit_compare_and_swap (EQ
, res
, ac
.memsi
,
4838 /* Check for changes outside mode. */
4839 resv
= expand_simple_binop (SImode
, AND
, res
, ac
.modemaski
,
4840 NULL_RTX
, 1, OPTAB_DIRECT
);
4841 cc
= s390_emit_compare (NE
, resv
, val
);
4842 emit_move_insn (val
, resv
);
4843 /* Loop internal if so. */
4844 s390_emit_jump (csloop
, cc
);
4848 /* Return the correct part of the bitfield. */
4849 convert_move (target
, expand_simple_binop (SImode
, LSHIFTRT
, res
, ac
.shift
,
4850 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
4853 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4854 and VAL the value to play with. If AFTER is true then store the value
4855 MEM holds after the operation, if AFTER is false then store the value MEM
4856 holds before the operation. If TARGET is zero then discard that value, else
4857 store it to TARGET. */
4860 s390_expand_atomic (enum machine_mode mode
, enum rtx_code code
,
4861 rtx target
, rtx mem
, rtx val
, bool after
)
4863 struct alignment_context ac
;
4865 rtx new_rtx
= gen_reg_rtx (SImode
);
4866 rtx orig
= gen_reg_rtx (SImode
);
4867 rtx csloop
= gen_label_rtx ();
4869 gcc_assert (!target
|| register_operand (target
, VOIDmode
));
4870 gcc_assert (MEM_P (mem
));
4872 init_alignment_context (&ac
, mem
, mode
);
4874 /* Shift val to the correct bit positions.
4875 Preserve "icm", but prevent "ex icm". */
4876 if (!(ac
.aligned
&& code
== SET
&& MEM_P (val
)))
4877 val
= s390_expand_mask_and_shift (val
, mode
, ac
.shift
);
4879 /* Further preparation insns. */
4880 if (code
== PLUS
|| code
== MINUS
)
4881 emit_move_insn (orig
, val
);
4882 else if (code
== MULT
|| code
== AND
) /* val = "11..1<val>11..1" */
4883 val
= expand_simple_binop (SImode
, XOR
, val
, ac
.modemaski
,
4884 NULL_RTX
, 1, OPTAB_DIRECT
);
4886 /* Load full word. Subsequent loads are performed by CS. */
4887 cmp
= force_reg (SImode
, ac
.memsi
);
4889 /* Start CS loop. */
4890 emit_label (csloop
);
4891 emit_move_insn (new_rtx
, cmp
);
4893 /* Patch new with val at correct position. */
4898 val
= expand_simple_binop (SImode
, code
, new_rtx
, orig
,
4899 NULL_RTX
, 1, OPTAB_DIRECT
);
4900 val
= expand_simple_binop (SImode
, AND
, val
, ac
.modemask
,
4901 NULL_RTX
, 1, OPTAB_DIRECT
);
4904 if (ac
.aligned
&& MEM_P (val
))
4905 store_bit_field (new_rtx
, GET_MODE_BITSIZE (mode
), 0, SImode
, val
);
4908 new_rtx
= expand_simple_binop (SImode
, AND
, new_rtx
, ac
.modemaski
,
4909 NULL_RTX
, 1, OPTAB_DIRECT
);
4910 new_rtx
= expand_simple_binop (SImode
, IOR
, new_rtx
, val
,
4911 NULL_RTX
, 1, OPTAB_DIRECT
);
4917 new_rtx
= expand_simple_binop (SImode
, code
, new_rtx
, val
,
4918 NULL_RTX
, 1, OPTAB_DIRECT
);
4920 case MULT
: /* NAND */
4921 new_rtx
= expand_simple_binop (SImode
, AND
, new_rtx
, val
,
4922 NULL_RTX
, 1, OPTAB_DIRECT
);
4923 new_rtx
= expand_simple_binop (SImode
, XOR
, new_rtx
, ac
.modemask
,
4924 NULL_RTX
, 1, OPTAB_DIRECT
);
4930 s390_emit_jump (csloop
, s390_emit_compare_and_swap (NE
, cmp
,
4931 ac
.memsi
, cmp
, new_rtx
));
4933 /* Return the correct part of the bitfield. */
4935 convert_move (target
, expand_simple_binop (SImode
, LSHIFTRT
,
4936 after
? new_rtx
: cmp
, ac
.shift
,
4937 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
4940 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4941 We need to emit DTP-relative relocations. */
4943 static void s390_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
4946 s390_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4951 fputs ("\t.long\t", file
);
4954 fputs ("\t.quad\t", file
);
4959 output_addr_const (file
, x
);
4960 fputs ("@DTPOFF", file
);
4963 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4964 /* Implement TARGET_MANGLE_TYPE. */
4967 s390_mangle_type (const_tree type
)
4969 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
4970 && TARGET_LONG_DOUBLE_128
)
4973 /* For all other types, use normal C++ mangling. */
4978 /* In the name of slightly smaller debug output, and to cater to
4979 general assembler lossage, recognize various UNSPEC sequences
4980 and turn them back into a direct symbol reference. */
4983 s390_delegitimize_address (rtx orig_x
)
4987 orig_x
= delegitimize_mem_from_attrs (orig_x
);
4990 /* Extract the symbol ref from:
4991 (plus:SI (reg:SI 12 %r12)
4992 (const:SI (unspec:SI [(symbol_ref/f:SI ("*.LC0"))]
4993 UNSPEC_GOTOFF/PLTOFF)))
4995 (plus:SI (reg:SI 12 %r12)
4996 (const:SI (plus:SI (unspec:SI [(symbol_ref:SI ("L"))]
4997 UNSPEC_GOTOFF/PLTOFF)
4998 (const_int 4 [0x4])))) */
4999 if (GET_CODE (x
) == PLUS
5000 && REG_P (XEXP (x
, 0))
5001 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
5002 && GET_CODE (XEXP (x
, 1)) == CONST
)
5004 HOST_WIDE_INT offset
= 0;
5006 /* The const operand. */
5007 y
= XEXP (XEXP (x
, 1), 0);
5009 if (GET_CODE (y
) == PLUS
5010 && GET_CODE (XEXP (y
, 1)) == CONST_INT
)
5012 offset
= INTVAL (XEXP (y
, 1));
5016 if (GET_CODE (y
) == UNSPEC
5017 && (XINT (y
, 1) == UNSPEC_GOTOFF
5018 || XINT (y
, 1) == UNSPEC_PLTOFF
))
5019 return plus_constant (XVECEXP (y
, 0, 0), offset
);
5022 if (GET_CODE (x
) != MEM
)
5026 if (GET_CODE (x
) == PLUS
5027 && GET_CODE (XEXP (x
, 1)) == CONST
5028 && GET_CODE (XEXP (x
, 0)) == REG
5029 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
)
5031 y
= XEXP (XEXP (x
, 1), 0);
5032 if (GET_CODE (y
) == UNSPEC
5033 && XINT (y
, 1) == UNSPEC_GOT
)
5034 y
= XVECEXP (y
, 0, 0);
5038 else if (GET_CODE (x
) == CONST
)
5040 /* Extract the symbol ref from:
5041 (mem:QI (const:DI (unspec:DI [(symbol_ref:DI ("foo"))]
5042 UNSPEC_PLT/GOTENT))) */
5045 if (GET_CODE (y
) == UNSPEC
5046 && (XINT (y
, 1) == UNSPEC_GOTENT
5047 || XINT (y
, 1) == UNSPEC_PLT
))
5048 y
= XVECEXP (y
, 0, 0);
5055 if (GET_MODE (orig_x
) != Pmode
)
5057 if (GET_MODE (orig_x
) == BLKmode
)
5059 y
= lowpart_subreg (GET_MODE (orig_x
), y
, Pmode
);
5066 /* Output operand OP to stdio stream FILE.
5067 OP is an address (register + offset) which is not used to address data;
5068 instead the rightmost bits are interpreted as the value. */
5071 print_shift_count_operand (FILE *file
, rtx op
)
5073 HOST_WIDE_INT offset
;
5076 /* Extract base register and offset. */
5077 if (!s390_decompose_shift_count (op
, &base
, &offset
))
5083 gcc_assert (GET_CODE (base
) == REG
);
5084 gcc_assert (REGNO (base
) < FIRST_PSEUDO_REGISTER
);
5085 gcc_assert (REGNO_REG_CLASS (REGNO (base
)) == ADDR_REGS
);
5088 /* Offsets are constricted to twelve bits. */
5089 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
& ((1 << 12) - 1));
5091 fprintf (file
, "(%s)", reg_names
[REGNO (base
)]);
5094 /* See 'get_some_local_dynamic_name'. */
5097 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
5101 if (GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
5103 x
= get_pool_constant (x
);
5104 return for_each_rtx (&x
, get_some_local_dynamic_name_1
, 0);
5107 if (GET_CODE (x
) == SYMBOL_REF
5108 && tls_symbolic_operand (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
5110 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
5117 /* Locate some local-dynamic symbol still in use by this function
5118 so that we can print its name in local-dynamic base patterns. */
5121 get_some_local_dynamic_name (void)
5125 if (cfun
->machine
->some_ld_name
)
5126 return cfun
->machine
->some_ld_name
;
5128 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5130 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
5131 return cfun
->machine
->some_ld_name
;
5136 /* Output machine-dependent UNSPECs occurring in address constant X
5137 in assembler syntax to stdio stream FILE. Returns true if the
5138 constant X could be recognized, false otherwise. */
5141 s390_output_addr_const_extra (FILE *file
, rtx x
)
5143 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 1)
5144 switch (XINT (x
, 1))
5147 output_addr_const (file
, XVECEXP (x
, 0, 0));
5148 fprintf (file
, "@GOTENT");
5151 output_addr_const (file
, XVECEXP (x
, 0, 0));
5152 fprintf (file
, "@GOT");
5155 output_addr_const (file
, XVECEXP (x
, 0, 0));
5156 fprintf (file
, "@GOTOFF");
5159 output_addr_const (file
, XVECEXP (x
, 0, 0));
5160 fprintf (file
, "@PLT");
5163 output_addr_const (file
, XVECEXP (x
, 0, 0));
5164 fprintf (file
, "@PLTOFF");
5167 output_addr_const (file
, XVECEXP (x
, 0, 0));
5168 fprintf (file
, "@TLSGD");
5171 assemble_name (file
, get_some_local_dynamic_name ());
5172 fprintf (file
, "@TLSLDM");
5175 output_addr_const (file
, XVECEXP (x
, 0, 0));
5176 fprintf (file
, "@DTPOFF");
5179 output_addr_const (file
, XVECEXP (x
, 0, 0));
5180 fprintf (file
, "@NTPOFF");
5182 case UNSPEC_GOTNTPOFF
:
5183 output_addr_const (file
, XVECEXP (x
, 0, 0));
5184 fprintf (file
, "@GOTNTPOFF");
5186 case UNSPEC_INDNTPOFF
:
5187 output_addr_const (file
, XVECEXP (x
, 0, 0));
5188 fprintf (file
, "@INDNTPOFF");
5192 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 2)
5193 switch (XINT (x
, 1))
5195 case UNSPEC_POOL_OFFSET
:
5196 x
= gen_rtx_MINUS (GET_MODE (x
), XVECEXP (x
, 0, 0), XVECEXP (x
, 0, 1));
5197 output_addr_const (file
, x
);
5203 /* Output address operand ADDR in assembler syntax to
5204 stdio stream FILE. */
5207 print_operand_address (FILE *file
, rtx addr
)
5209 struct s390_address ad
;
5211 if (s390_symref_operand_p (addr
, NULL
, NULL
))
5215 output_operand_lossage ("symbolic memory references are "
5216 "only supported on z10 or later");
5219 output_addr_const (file
, addr
);
5223 if (!s390_decompose_address (addr
, &ad
)
5224 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
5225 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
5226 output_operand_lossage ("cannot decompose address");
5229 output_addr_const (file
, ad
.disp
);
5231 fprintf (file
, "0");
5233 if (ad
.base
&& ad
.indx
)
5234 fprintf (file
, "(%s,%s)", reg_names
[REGNO (ad
.indx
)],
5235 reg_names
[REGNO (ad
.base
)]);
5237 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
5240 /* Output operand X in assembler syntax to stdio stream FILE.
5241 CODE specified the format flag. The following format flags
5244 'C': print opcode suffix for branch condition.
5245 'D': print opcode suffix for inverse branch condition.
5246 'E': print opcode suffix for branch on index instruction.
5247 'J': print tls_load/tls_gdcall/tls_ldcall suffix
5248 'G': print the size of the operand in bytes.
5249 'O': print only the displacement of a memory reference.
5250 'R': print only the base register of a memory reference.
5251 'S': print S-type memory reference (base+displacement).
5252 'N': print the second word of a DImode operand.
5253 'M': print the second word of a TImode operand.
5254 'Y': print shift count operand.
5256 'b': print integer X as if it's an unsigned byte.
5257 'c': print integer X as if it's an signed byte.
5258 'x': print integer X as if it's an unsigned halfword.
5259 'h': print integer X as if it's a signed halfword.
5260 'i': print the first nonzero HImode part of X.
5261 'j': print the first HImode part unequal to -1 of X.
5262 'k': print the first nonzero SImode part of X.
5263 'm': print the first SImode part unequal to -1 of X.
5264 'o': print integer X as if it's an unsigned 32bit word. */
5267 print_operand (FILE *file
, rtx x
, int code
)
5272 fprintf (file
, s390_branch_condition_mnemonic (x
, FALSE
));
5276 fprintf (file
, s390_branch_condition_mnemonic (x
, TRUE
));
5280 if (GET_CODE (x
) == LE
)
5281 fprintf (file
, "l");
5282 else if (GET_CODE (x
) == GT
)
5283 fprintf (file
, "h");
5285 output_operand_lossage ("invalid comparison operator "
5286 "for 'E' output modifier");
5290 if (GET_CODE (x
) == SYMBOL_REF
)
5292 fprintf (file
, "%s", ":tls_load:");
5293 output_addr_const (file
, x
);
5295 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD
)
5297 fprintf (file
, "%s", ":tls_gdcall:");
5298 output_addr_const (file
, XVECEXP (x
, 0, 0));
5300 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM
)
5302 fprintf (file
, "%s", ":tls_ldcall:");
5303 assemble_name (file
, get_some_local_dynamic_name ());
5306 output_operand_lossage ("invalid reference for 'J' output modifier");
5310 fprintf (file
, "%u", GET_MODE_SIZE (GET_MODE (x
)));
5315 struct s390_address ad
;
5320 output_operand_lossage ("memory reference expected for "
5321 "'O' output modifier");
5325 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5328 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
5331 output_operand_lossage ("invalid address for 'O' output modifier");
5336 output_addr_const (file
, ad
.disp
);
5338 fprintf (file
, "0");
5344 struct s390_address ad
;
5349 output_operand_lossage ("memory reference expected for "
5350 "'R' output modifier");
5354 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5357 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
5360 output_operand_lossage ("invalid address for 'R' output modifier");
5365 fprintf (file
, "%s", reg_names
[REGNO (ad
.base
)]);
5367 fprintf (file
, "0");
5373 struct s390_address ad
;
5378 output_operand_lossage ("memory reference expected for "
5379 "'S' output modifier");
5382 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
5385 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
5388 output_operand_lossage ("invalid address for 'S' output modifier");
5393 output_addr_const (file
, ad
.disp
);
5395 fprintf (file
, "0");
5398 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
5403 if (GET_CODE (x
) == REG
)
5404 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
5405 else if (GET_CODE (x
) == MEM
)
5406 x
= change_address (x
, VOIDmode
, plus_constant (XEXP (x
, 0), 4));
5408 output_operand_lossage ("register or memory expression expected "
5409 "for 'N' output modifier");
5413 if (GET_CODE (x
) == REG
)
5414 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
5415 else if (GET_CODE (x
) == MEM
)
5416 x
= change_address (x
, VOIDmode
, plus_constant (XEXP (x
, 0), 8));
5418 output_operand_lossage ("register or memory expression expected "
5419 "for 'M' output modifier");
5423 print_shift_count_operand (file
, x
);
5427 switch (GET_CODE (x
))
5430 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
5434 output_address (XEXP (x
, 0));
5441 output_addr_const (file
, x
);
5446 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xff);
5447 else if (code
== 'c')
5448 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ((INTVAL (x
) & 0xff) ^ 0x80) - 0x80);
5449 else if (code
== 'x')
5450 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffff);
5451 else if (code
== 'h')
5452 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ((INTVAL (x
) & 0xffff) ^ 0x8000) - 0x8000);
5453 else if (code
== 'i')
5454 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5455 s390_extract_part (x
, HImode
, 0));
5456 else if (code
== 'j')
5457 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5458 s390_extract_part (x
, HImode
, -1));
5459 else if (code
== 'k')
5460 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5461 s390_extract_part (x
, SImode
, 0));
5462 else if (code
== 'm')
5463 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5464 s390_extract_part (x
, SImode
, -1));
5465 else if (code
== 'o')
5466 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffffffff);
5468 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
5472 gcc_assert (GET_MODE (x
) == VOIDmode
);
5474 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
) & 0xff);
5475 else if (code
== 'x')
5476 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
) & 0xffff);
5477 else if (code
== 'h')
5478 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
5479 ((CONST_DOUBLE_LOW (x
) & 0xffff) ^ 0x8000) - 0x8000);
5483 output_operand_lossage ("invalid constant - try using "
5484 "an output modifier");
5486 output_operand_lossage ("invalid constant for output modifier '%c'",
5493 output_operand_lossage ("invalid expression - try using "
5494 "an output modifier");
5496 output_operand_lossage ("invalid expression for output "
5497 "modifier '%c'", code
);
5502 /* Target hook for assembling integer objects. We need to define it
5503 here to work a round a bug in some versions of GAS, which couldn't
5504 handle values smaller than INT_MIN when printed in decimal. */
5507 s390_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
5509 if (size
== 8 && aligned_p
5510 && GET_CODE (x
) == CONST_INT
&& INTVAL (x
) < INT_MIN
)
5512 fprintf (asm_out_file
, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX
"\n",
5516 return default_assemble_integer (x
, size
, aligned_p
);
5519 /* Returns true if register REGNO is used for forming
5520 a memory address in expression X. */
5523 reg_used_in_mem_p (int regno
, rtx x
)
5525 enum rtx_code code
= GET_CODE (x
);
5531 if (refers_to_regno_p (regno
, regno
+1,
5535 else if (code
== SET
5536 && GET_CODE (SET_DEST (x
)) == PC
)
5538 if (refers_to_regno_p (regno
, regno
+1,
5543 fmt
= GET_RTX_FORMAT (code
);
5544 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5547 && reg_used_in_mem_p (regno
, XEXP (x
, i
)))
5550 else if (fmt
[i
] == 'E')
5551 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
5552 if (reg_used_in_mem_p (regno
, XVECEXP (x
, i
, j
)))
5558 /* Returns true if expression DEP_RTX sets an address register
5559 used by instruction INSN to address memory. */
5562 addr_generation_dependency_p (rtx dep_rtx
, rtx insn
)
5566 if (GET_CODE (dep_rtx
) == INSN
)
5567 dep_rtx
= PATTERN (dep_rtx
);
5569 if (GET_CODE (dep_rtx
) == SET
)
5571 target
= SET_DEST (dep_rtx
);
5572 if (GET_CODE (target
) == STRICT_LOW_PART
)
5573 target
= XEXP (target
, 0);
5574 while (GET_CODE (target
) == SUBREG
)
5575 target
= SUBREG_REG (target
);
5577 if (GET_CODE (target
) == REG
)
5579 int regno
= REGNO (target
);
5581 if (s390_safe_attr_type (insn
) == TYPE_LA
)
5583 pat
= PATTERN (insn
);
5584 if (GET_CODE (pat
) == PARALLEL
)
5586 gcc_assert (XVECLEN (pat
, 0) == 2);
5587 pat
= XVECEXP (pat
, 0, 0);
5589 gcc_assert (GET_CODE (pat
) == SET
);
5590 return refers_to_regno_p (regno
, regno
+1, SET_SRC (pat
), 0);
5592 else if (get_attr_atype (insn
) == ATYPE_AGEN
)
5593 return reg_used_in_mem_p (regno
, PATTERN (insn
));
5599 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5602 s390_agen_dep_p (rtx dep_insn
, rtx insn
)
5604 rtx dep_rtx
= PATTERN (dep_insn
);
5607 if (GET_CODE (dep_rtx
) == SET
5608 && addr_generation_dependency_p (dep_rtx
, insn
))
5610 else if (GET_CODE (dep_rtx
) == PARALLEL
)
5612 for (i
= 0; i
< XVECLEN (dep_rtx
, 0); i
++)
5614 if (addr_generation_dependency_p (XVECEXP (dep_rtx
, 0, i
), insn
))
5622 /* A C statement (sans semicolon) to update the integer scheduling priority
5623 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5624 reduce the priority to execute INSN later. Do not define this macro if
5625 you do not need to adjust the scheduling priorities of insns.
5627 A STD instruction should be scheduled earlier,
5628 in order to use the bypass. */
5630 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
5632 if (! INSN_P (insn
))
5635 if (s390_tune
!= PROCESSOR_2084_Z990
5636 && s390_tune
!= PROCESSOR_2094_Z9_109
5637 && s390_tune
!= PROCESSOR_2097_Z10
5638 && s390_tune
!= PROCESSOR_2817_Z196
)
5641 switch (s390_safe_attr_type (insn
))
5645 priority
= priority
<< 3;
5649 priority
= priority
<< 1;
5658 /* The number of instructions that can be issued per cycle. */
5661 s390_issue_rate (void)
5665 case PROCESSOR_2084_Z990
:
5666 case PROCESSOR_2094_Z9_109
:
5667 case PROCESSOR_2817_Z196
:
5669 case PROCESSOR_2097_Z10
:
5677 s390_first_cycle_multipass_dfa_lookahead (void)
5682 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5683 Fix up MEMs as required. */
5686 annotate_constant_pool_refs (rtx
*x
)
5691 gcc_assert (GET_CODE (*x
) != SYMBOL_REF
5692 || !CONSTANT_POOL_ADDRESS_P (*x
));
5694 /* Literal pool references can only occur inside a MEM ... */
5695 if (GET_CODE (*x
) == MEM
)
5697 rtx memref
= XEXP (*x
, 0);
5699 if (GET_CODE (memref
) == SYMBOL_REF
5700 && CONSTANT_POOL_ADDRESS_P (memref
))
5702 rtx base
= cfun
->machine
->base_reg
;
5703 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, memref
, base
),
5706 *x
= replace_equiv_address (*x
, addr
);
5710 if (GET_CODE (memref
) == CONST
5711 && GET_CODE (XEXP (memref
, 0)) == PLUS
5712 && GET_CODE (XEXP (XEXP (memref
, 0), 1)) == CONST_INT
5713 && GET_CODE (XEXP (XEXP (memref
, 0), 0)) == SYMBOL_REF
5714 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref
, 0), 0)))
5716 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (memref
, 0), 1));
5717 rtx sym
= XEXP (XEXP (memref
, 0), 0);
5718 rtx base
= cfun
->machine
->base_reg
;
5719 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
5722 *x
= replace_equiv_address (*x
, plus_constant (addr
, off
));
5727 /* ... or a load-address type pattern. */
5728 if (GET_CODE (*x
) == SET
)
5730 rtx addrref
= SET_SRC (*x
);
5732 if (GET_CODE (addrref
) == SYMBOL_REF
5733 && CONSTANT_POOL_ADDRESS_P (addrref
))
5735 rtx base
= cfun
->machine
->base_reg
;
5736 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, addrref
, base
),
5739 SET_SRC (*x
) = addr
;
5743 if (GET_CODE (addrref
) == CONST
5744 && GET_CODE (XEXP (addrref
, 0)) == PLUS
5745 && GET_CODE (XEXP (XEXP (addrref
, 0), 1)) == CONST_INT
5746 && GET_CODE (XEXP (XEXP (addrref
, 0), 0)) == SYMBOL_REF
5747 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref
, 0), 0)))
5749 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (addrref
, 0), 1));
5750 rtx sym
= XEXP (XEXP (addrref
, 0), 0);
5751 rtx base
= cfun
->machine
->base_reg
;
5752 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
5755 SET_SRC (*x
) = plus_constant (addr
, off
);
5760 /* Annotate LTREL_BASE as well. */
5761 if (GET_CODE (*x
) == UNSPEC
5762 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
5764 rtx base
= cfun
->machine
->base_reg
;
5765 *x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XVECEXP (*x
, 0, 0), base
),
5770 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5771 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5775 annotate_constant_pool_refs (&XEXP (*x
, i
));
5777 else if (fmt
[i
] == 'E')
5779 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
5780 annotate_constant_pool_refs (&XVECEXP (*x
, i
, j
));
5785 /* Split all branches that exceed the maximum distance.
5786 Returns true if this created a new literal pool entry. */
5789 s390_split_branches (void)
5791 rtx temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
5792 int new_literal
= 0, ret
;
5793 rtx insn
, pat
, tmp
, target
;
5796 /* We need correct insn addresses. */
5798 shorten_branches (get_insns ());
5800 /* Find all branches that exceed 64KB, and split them. */
5802 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5804 if (GET_CODE (insn
) != JUMP_INSN
)
5807 pat
= PATTERN (insn
);
5808 if (GET_CODE (pat
) == PARALLEL
&& XVECLEN (pat
, 0) > 2)
5809 pat
= XVECEXP (pat
, 0, 0);
5810 if (GET_CODE (pat
) != SET
|| SET_DEST (pat
) != pc_rtx
)
5813 if (GET_CODE (SET_SRC (pat
)) == LABEL_REF
)
5815 label
= &SET_SRC (pat
);
5817 else if (GET_CODE (SET_SRC (pat
)) == IF_THEN_ELSE
)
5819 if (GET_CODE (XEXP (SET_SRC (pat
), 1)) == LABEL_REF
)
5820 label
= &XEXP (SET_SRC (pat
), 1);
5821 else if (GET_CODE (XEXP (SET_SRC (pat
), 2)) == LABEL_REF
)
5822 label
= &XEXP (SET_SRC (pat
), 2);
5829 if (get_attr_length (insn
) <= 4)
5832 /* We are going to use the return register as scratch register,
5833 make sure it will be saved/restored by the prologue/epilogue. */
5834 cfun_frame_layout
.save_return_addr_p
= 1;
5839 tmp
= force_const_mem (Pmode
, *label
);
5840 tmp
= emit_insn_before (gen_rtx_SET (Pmode
, temp_reg
, tmp
), insn
);
5841 INSN_ADDRESSES_NEW (tmp
, -1);
5842 annotate_constant_pool_refs (&PATTERN (tmp
));
5849 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, *label
),
5850 UNSPEC_LTREL_OFFSET
);
5851 target
= gen_rtx_CONST (Pmode
, target
);
5852 target
= force_const_mem (Pmode
, target
);
5853 tmp
= emit_insn_before (gen_rtx_SET (Pmode
, temp_reg
, target
), insn
);
5854 INSN_ADDRESSES_NEW (tmp
, -1);
5855 annotate_constant_pool_refs (&PATTERN (tmp
));
5857 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XEXP (target
, 0),
5858 cfun
->machine
->base_reg
),
5860 target
= gen_rtx_PLUS (Pmode
, temp_reg
, target
);
5863 ret
= validate_change (insn
, label
, target
, 0);
5871 /* Find an annotated literal pool symbol referenced in RTX X,
5872 and store it at REF. Will abort if X contains references to
5873 more than one such pool symbol; multiple references to the same
5874 symbol are allowed, however.
5876 The rtx pointed to by REF must be initialized to NULL_RTX
5877 by the caller before calling this routine. */
5880 find_constant_pool_ref (rtx x
, rtx
*ref
)
5885 /* Ignore LTREL_BASE references. */
5886 if (GET_CODE (x
) == UNSPEC
5887 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
5889 /* Likewise POOL_ENTRY insns. */
5890 if (GET_CODE (x
) == UNSPEC_VOLATILE
5891 && XINT (x
, 1) == UNSPECV_POOL_ENTRY
)
5894 gcc_assert (GET_CODE (x
) != SYMBOL_REF
5895 || !CONSTANT_POOL_ADDRESS_P (x
));
5897 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_LTREF
)
5899 rtx sym
= XVECEXP (x
, 0, 0);
5900 gcc_assert (GET_CODE (sym
) == SYMBOL_REF
5901 && CONSTANT_POOL_ADDRESS_P (sym
));
5903 if (*ref
== NULL_RTX
)
5906 gcc_assert (*ref
== sym
);
5911 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5912 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5916 find_constant_pool_ref (XEXP (x
, i
), ref
);
5918 else if (fmt
[i
] == 'E')
5920 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
5921 find_constant_pool_ref (XVECEXP (x
, i
, j
), ref
);
5926 /* Replace every reference to the annotated literal pool
5927 symbol REF in X by its base plus OFFSET. */
5930 replace_constant_pool_ref (rtx
*x
, rtx ref
, rtx offset
)
5935 gcc_assert (*x
!= ref
);
5937 if (GET_CODE (*x
) == UNSPEC
5938 && XINT (*x
, 1) == UNSPEC_LTREF
5939 && XVECEXP (*x
, 0, 0) == ref
)
5941 *x
= gen_rtx_PLUS (Pmode
, XVECEXP (*x
, 0, 1), offset
);
5945 if (GET_CODE (*x
) == PLUS
5946 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
5947 && GET_CODE (XEXP (*x
, 0)) == UNSPEC
5948 && XINT (XEXP (*x
, 0), 1) == UNSPEC_LTREF
5949 && XVECEXP (XEXP (*x
, 0), 0, 0) == ref
)
5951 rtx addr
= gen_rtx_PLUS (Pmode
, XVECEXP (XEXP (*x
, 0), 0, 1), offset
);
5952 *x
= plus_constant (addr
, INTVAL (XEXP (*x
, 1)));
5956 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5957 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5961 replace_constant_pool_ref (&XEXP (*x
, i
), ref
, offset
);
5963 else if (fmt
[i
] == 'E')
5965 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
5966 replace_constant_pool_ref (&XVECEXP (*x
, i
, j
), ref
, offset
);
5971 /* Check whether X contains an UNSPEC_LTREL_BASE.
5972 Return its constant pool symbol if found, NULL_RTX otherwise. */
5975 find_ltrel_base (rtx x
)
5980 if (GET_CODE (x
) == UNSPEC
5981 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
5982 return XVECEXP (x
, 0, 0);
5984 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5985 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5989 rtx fnd
= find_ltrel_base (XEXP (x
, i
));
5993 else if (fmt
[i
] == 'E')
5995 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
5997 rtx fnd
= find_ltrel_base (XVECEXP (x
, i
, j
));
6007 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
6010 replace_ltrel_base (rtx
*x
)
6015 if (GET_CODE (*x
) == UNSPEC
6016 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
6018 *x
= XVECEXP (*x
, 0, 1);
6022 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
6023 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
6027 replace_ltrel_base (&XEXP (*x
, i
));
6029 else if (fmt
[i
] == 'E')
6031 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
6032 replace_ltrel_base (&XVECEXP (*x
, i
, j
));
6038 /* We keep a list of constants which we have to add to internal
6039 constant tables in the middle of large functions. */
6041 #define NR_C_MODES 11
6042 enum machine_mode constant_modes
[NR_C_MODES
] =
6044 TFmode
, TImode
, TDmode
,
6045 DFmode
, DImode
, DDmode
,
6046 SFmode
, SImode
, SDmode
,
6053 struct constant
*next
;
6058 struct constant_pool
6060 struct constant_pool
*next
;
6064 rtx emit_pool_after
;
6066 struct constant
*constants
[NR_C_MODES
];
6067 struct constant
*execute
;
6072 /* Allocate new constant_pool structure. */
6074 static struct constant_pool
*
6075 s390_alloc_pool (void)
6077 struct constant_pool
*pool
;
6080 pool
= (struct constant_pool
*) xmalloc (sizeof *pool
);
6082 for (i
= 0; i
< NR_C_MODES
; i
++)
6083 pool
->constants
[i
] = NULL
;
6085 pool
->execute
= NULL
;
6086 pool
->label
= gen_label_rtx ();
6087 pool
->first_insn
= NULL_RTX
;
6088 pool
->pool_insn
= NULL_RTX
;
6089 pool
->insns
= BITMAP_ALLOC (NULL
);
6091 pool
->emit_pool_after
= NULL_RTX
;
6096 /* Create new constant pool covering instructions starting at INSN
6097 and chain it to the end of POOL_LIST. */
6099 static struct constant_pool
*
6100 s390_start_pool (struct constant_pool
**pool_list
, rtx insn
)
6102 struct constant_pool
*pool
, **prev
;
6104 pool
= s390_alloc_pool ();
6105 pool
->first_insn
= insn
;
6107 for (prev
= pool_list
; *prev
; prev
= &(*prev
)->next
)
6114 /* End range of instructions covered by POOL at INSN and emit
6115 placeholder insn representing the pool. */
6118 s390_end_pool (struct constant_pool
*pool
, rtx insn
)
6120 rtx pool_size
= GEN_INT (pool
->size
+ 8 /* alignment slop */);
6123 insn
= get_last_insn ();
6125 pool
->pool_insn
= emit_insn_after (gen_pool (pool_size
), insn
);
6126 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6129 /* Add INSN to the list of insns covered by POOL. */
6132 s390_add_pool_insn (struct constant_pool
*pool
, rtx insn
)
6134 bitmap_set_bit (pool
->insns
, INSN_UID (insn
));
6137 /* Return pool out of POOL_LIST that covers INSN. */
6139 static struct constant_pool
*
6140 s390_find_pool (struct constant_pool
*pool_list
, rtx insn
)
6142 struct constant_pool
*pool
;
6144 for (pool
= pool_list
; pool
; pool
= pool
->next
)
6145 if (bitmap_bit_p (pool
->insns
, INSN_UID (insn
)))
6151 /* Add constant VAL of mode MODE to the constant pool POOL. */
6154 s390_add_constant (struct constant_pool
*pool
, rtx val
, enum machine_mode mode
)
6159 for (i
= 0; i
< NR_C_MODES
; i
++)
6160 if (constant_modes
[i
] == mode
)
6162 gcc_assert (i
!= NR_C_MODES
);
6164 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
6165 if (rtx_equal_p (val
, c
->value
))
6170 c
= (struct constant
*) xmalloc (sizeof *c
);
6172 c
->label
= gen_label_rtx ();
6173 c
->next
= pool
->constants
[i
];
6174 pool
->constants
[i
] = c
;
6175 pool
->size
+= GET_MODE_SIZE (mode
);
6179 /* Return an rtx that represents the offset of X from the start of
6183 s390_pool_offset (struct constant_pool
*pool
, rtx x
)
6187 label
= gen_rtx_LABEL_REF (GET_MODE (x
), pool
->label
);
6188 x
= gen_rtx_UNSPEC (GET_MODE (x
), gen_rtvec (2, x
, label
),
6189 UNSPEC_POOL_OFFSET
);
6190 return gen_rtx_CONST (GET_MODE (x
), x
);
6193 /* Find constant VAL of mode MODE in the constant pool POOL.
6194 Return an RTX describing the distance from the start of
6195 the pool to the location of the new constant. */
6198 s390_find_constant (struct constant_pool
*pool
, rtx val
,
6199 enum machine_mode mode
)
6204 for (i
= 0; i
< NR_C_MODES
; i
++)
6205 if (constant_modes
[i
] == mode
)
6207 gcc_assert (i
!= NR_C_MODES
);
6209 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
6210 if (rtx_equal_p (val
, c
->value
))
6215 return s390_pool_offset (pool
, gen_rtx_LABEL_REF (Pmode
, c
->label
));
6218 /* Check whether INSN is an execute. Return the label_ref to its
6219 execute target template if so, NULL_RTX otherwise. */
6222 s390_execute_label (rtx insn
)
6224 if (GET_CODE (insn
) == INSN
6225 && GET_CODE (PATTERN (insn
)) == PARALLEL
6226 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == UNSPEC
6227 && XINT (XVECEXP (PATTERN (insn
), 0, 0), 1) == UNSPEC_EXECUTE
)
6228 return XVECEXP (XVECEXP (PATTERN (insn
), 0, 0), 0, 2);
6233 /* Add execute target for INSN to the constant pool POOL. */
6236 s390_add_execute (struct constant_pool
*pool
, rtx insn
)
6240 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
6241 if (INSN_UID (insn
) == INSN_UID (c
->value
))
6246 c
= (struct constant
*) xmalloc (sizeof *c
);
6248 c
->label
= gen_label_rtx ();
6249 c
->next
= pool
->execute
;
6255 /* Find execute target for INSN in the constant pool POOL.
6256 Return an RTX describing the distance from the start of
6257 the pool to the location of the execute target. */
6260 s390_find_execute (struct constant_pool
*pool
, rtx insn
)
6264 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
6265 if (INSN_UID (insn
) == INSN_UID (c
->value
))
6270 return s390_pool_offset (pool
, gen_rtx_LABEL_REF (Pmode
, c
->label
));
6273 /* For an execute INSN, extract the execute target template. */
6276 s390_execute_target (rtx insn
)
6278 rtx pattern
= PATTERN (insn
);
6279 gcc_assert (s390_execute_label (insn
));
6281 if (XVECLEN (pattern
, 0) == 2)
6283 pattern
= copy_rtx (XVECEXP (pattern
, 0, 1));
6287 rtvec vec
= rtvec_alloc (XVECLEN (pattern
, 0) - 1);
6290 for (i
= 0; i
< XVECLEN (pattern
, 0) - 1; i
++)
6291 RTVEC_ELT (vec
, i
) = copy_rtx (XVECEXP (pattern
, 0, i
+ 1));
6293 pattern
= gen_rtx_PARALLEL (VOIDmode
, vec
);
6299 /* Indicate that INSN cannot be duplicated. This is the case for
6300 execute insns that carry a unique label. */
6303 s390_cannot_copy_insn_p (rtx insn
)
6305 rtx label
= s390_execute_label (insn
);
6306 return label
&& label
!= const0_rtx
;
6309 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
6310 do not emit the pool base label. */
6313 s390_dump_pool (struct constant_pool
*pool
, bool remote_label
)
6316 rtx insn
= pool
->pool_insn
;
6319 /* Switch to rodata section. */
6320 if (TARGET_CPU_ZARCH
)
6322 insn
= emit_insn_after (gen_pool_section_start (), insn
);
6323 INSN_ADDRESSES_NEW (insn
, -1);
6326 /* Ensure minimum pool alignment. */
6327 if (TARGET_CPU_ZARCH
)
6328 insn
= emit_insn_after (gen_pool_align (GEN_INT (8)), insn
);
6330 insn
= emit_insn_after (gen_pool_align (GEN_INT (4)), insn
);
6331 INSN_ADDRESSES_NEW (insn
, -1);
6333 /* Emit pool base label. */
6336 insn
= emit_label_after (pool
->label
, insn
);
6337 INSN_ADDRESSES_NEW (insn
, -1);
6340 /* Dump constants in descending alignment requirement order,
6341 ensuring proper alignment for every constant. */
6342 for (i
= 0; i
< NR_C_MODES
; i
++)
6343 for (c
= pool
->constants
[i
]; c
; c
= c
->next
)
6345 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6346 rtx value
= copy_rtx (c
->value
);
6347 if (GET_CODE (value
) == CONST
6348 && GET_CODE (XEXP (value
, 0)) == UNSPEC
6349 && XINT (XEXP (value
, 0), 1) == UNSPEC_LTREL_OFFSET
6350 && XVECLEN (XEXP (value
, 0), 0) == 1)
6351 value
= s390_pool_offset (pool
, XVECEXP (XEXP (value
, 0), 0, 0));
6353 insn
= emit_label_after (c
->label
, insn
);
6354 INSN_ADDRESSES_NEW (insn
, -1);
6356 value
= gen_rtx_UNSPEC_VOLATILE (constant_modes
[i
],
6357 gen_rtvec (1, value
),
6358 UNSPECV_POOL_ENTRY
);
6359 insn
= emit_insn_after (value
, insn
);
6360 INSN_ADDRESSES_NEW (insn
, -1);
6363 /* Ensure minimum alignment for instructions. */
6364 insn
= emit_insn_after (gen_pool_align (GEN_INT (2)), insn
);
6365 INSN_ADDRESSES_NEW (insn
, -1);
6367 /* Output in-pool execute template insns. */
6368 for (c
= pool
->execute
; c
; c
= c
->next
)
6370 insn
= emit_label_after (c
->label
, insn
);
6371 INSN_ADDRESSES_NEW (insn
, -1);
6373 insn
= emit_insn_after (s390_execute_target (c
->value
), insn
);
6374 INSN_ADDRESSES_NEW (insn
, -1);
6377 /* Switch back to previous section. */
6378 if (TARGET_CPU_ZARCH
)
6380 insn
= emit_insn_after (gen_pool_section_end (), insn
);
6381 INSN_ADDRESSES_NEW (insn
, -1);
6384 insn
= emit_barrier_after (insn
);
6385 INSN_ADDRESSES_NEW (insn
, -1);
6387 /* Remove placeholder insn. */
6388 remove_insn (pool
->pool_insn
);
6391 /* Free all memory used by POOL. */
6394 s390_free_pool (struct constant_pool
*pool
)
6396 struct constant
*c
, *next
;
6399 for (i
= 0; i
< NR_C_MODES
; i
++)
6400 for (c
= pool
->constants
[i
]; c
; c
= next
)
6406 for (c
= pool
->execute
; c
; c
= next
)
6412 BITMAP_FREE (pool
->insns
);
6417 /* Collect main literal pool. Return NULL on overflow. */
6419 static struct constant_pool
*
6420 s390_mainpool_start (void)
6422 struct constant_pool
*pool
;
6425 pool
= s390_alloc_pool ();
6427 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6429 if (GET_CODE (insn
) == INSN
6430 && GET_CODE (PATTERN (insn
)) == SET
6431 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC_VOLATILE
6432 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPECV_MAIN_POOL
)
6434 gcc_assert (!pool
->pool_insn
);
6435 pool
->pool_insn
= insn
;
6438 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
6440 s390_add_execute (pool
, insn
);
6442 else if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6444 rtx pool_ref
= NULL_RTX
;
6445 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6448 rtx constant
= get_pool_constant (pool_ref
);
6449 enum machine_mode mode
= get_pool_mode (pool_ref
);
6450 s390_add_constant (pool
, constant
, mode
);
6454 /* If hot/cold partitioning is enabled we have to make sure that
6455 the literal pool is emitted in the same section where the
6456 initialization of the literal pool base pointer takes place.
6457 emit_pool_after is only used in the non-overflow case on non
6458 Z cpus where we can emit the literal pool at the end of the
6459 function body within the text section. */
6461 && NOTE_KIND (insn
) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6462 && !pool
->emit_pool_after
)
6463 pool
->emit_pool_after
= PREV_INSN (insn
);
6466 gcc_assert (pool
->pool_insn
|| pool
->size
== 0);
6468 if (pool
->size
>= 4096)
6470 /* We're going to chunkify the pool, so remove the main
6471 pool placeholder insn. */
6472 remove_insn (pool
->pool_insn
);
6474 s390_free_pool (pool
);
6478 /* If the functions ends with the section where the literal pool
6479 should be emitted set the marker to its end. */
6480 if (pool
&& !pool
->emit_pool_after
)
6481 pool
->emit_pool_after
= get_last_insn ();
6486 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6487 Modify the current function to output the pool constants as well as
6488 the pool register setup instruction. */
6491 s390_mainpool_finish (struct constant_pool
*pool
)
6493 rtx base_reg
= cfun
->machine
->base_reg
;
6496 /* If the pool is empty, we're done. */
6497 if (pool
->size
== 0)
6499 /* We don't actually need a base register after all. */
6500 cfun
->machine
->base_reg
= NULL_RTX
;
6502 if (pool
->pool_insn
)
6503 remove_insn (pool
->pool_insn
);
6504 s390_free_pool (pool
);
6508 /* We need correct insn addresses. */
6509 shorten_branches (get_insns ());
6511 /* On zSeries, we use a LARL to load the pool register. The pool is
6512 located in the .rodata section, so we emit it after the function. */
6513 if (TARGET_CPU_ZARCH
)
6515 insn
= gen_main_base_64 (base_reg
, pool
->label
);
6516 insn
= emit_insn_after (insn
, pool
->pool_insn
);
6517 INSN_ADDRESSES_NEW (insn
, -1);
6518 remove_insn (pool
->pool_insn
);
6520 insn
= get_last_insn ();
6521 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6522 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6524 s390_dump_pool (pool
, 0);
6527 /* On S/390, if the total size of the function's code plus literal pool
6528 does not exceed 4096 bytes, we use BASR to set up a function base
6529 pointer, and emit the literal pool at the end of the function. */
6530 else if (INSN_ADDRESSES (INSN_UID (pool
->emit_pool_after
))
6531 + pool
->size
+ 8 /* alignment slop */ < 4096)
6533 insn
= gen_main_base_31_small (base_reg
, pool
->label
);
6534 insn
= emit_insn_after (insn
, pool
->pool_insn
);
6535 INSN_ADDRESSES_NEW (insn
, -1);
6536 remove_insn (pool
->pool_insn
);
6538 insn
= emit_label_after (pool
->label
, insn
);
6539 INSN_ADDRESSES_NEW (insn
, -1);
6541 /* emit_pool_after will be set by s390_mainpool_start to the
6542 last insn of the section where the literal pool should be
6544 insn
= pool
->emit_pool_after
;
6546 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6547 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6549 s390_dump_pool (pool
, 1);
6552 /* Otherwise, we emit an inline literal pool and use BASR to branch
6553 over it, setting up the pool register at the same time. */
6556 rtx pool_end
= gen_label_rtx ();
6558 insn
= gen_main_base_31_large (base_reg
, pool
->label
, pool_end
);
6559 insn
= emit_insn_after (insn
, pool
->pool_insn
);
6560 INSN_ADDRESSES_NEW (insn
, -1);
6561 remove_insn (pool
->pool_insn
);
6563 insn
= emit_label_after (pool
->label
, insn
);
6564 INSN_ADDRESSES_NEW (insn
, -1);
6566 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
6567 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
6569 insn
= emit_label_after (pool_end
, pool
->pool_insn
);
6570 INSN_ADDRESSES_NEW (insn
, -1);
6572 s390_dump_pool (pool
, 1);
6576 /* Replace all literal pool references. */
6578 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6581 replace_ltrel_base (&PATTERN (insn
));
6583 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6585 rtx addr
, pool_ref
= NULL_RTX
;
6586 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6589 if (s390_execute_label (insn
))
6590 addr
= s390_find_execute (pool
, insn
);
6592 addr
= s390_find_constant (pool
, get_pool_constant (pool_ref
),
6593 get_pool_mode (pool_ref
));
6595 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
6596 INSN_CODE (insn
) = -1;
6602 /* Free the pool. */
6603 s390_free_pool (pool
);
6606 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6607 We have decided we cannot use this pool, so revert all changes
6608 to the current function that were done by s390_mainpool_start. */
6610 s390_mainpool_cancel (struct constant_pool
*pool
)
6612 /* We didn't actually change the instruction stream, so simply
6613 free the pool memory. */
6614 s390_free_pool (pool
);
6618 /* Chunkify the literal pool. */
6620 #define S390_POOL_CHUNK_MIN 0xc00
6621 #define S390_POOL_CHUNK_MAX 0xe00
6623 static struct constant_pool
*
6624 s390_chunkify_start (void)
6626 struct constant_pool
*curr_pool
= NULL
, *pool_list
= NULL
;
6629 rtx pending_ltrel
= NULL_RTX
;
6632 rtx (*gen_reload_base
) (rtx
, rtx
) =
6633 TARGET_CPU_ZARCH
? gen_reload_base_64
: gen_reload_base_31
;
6636 /* We need correct insn addresses. */
6638 shorten_branches (get_insns ());
6640 /* Scan all insns and move literals to pool chunks. */
6642 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6644 bool section_switch_p
= false;
6646 /* Check for pending LTREL_BASE. */
6649 rtx ltrel_base
= find_ltrel_base (PATTERN (insn
));
6652 gcc_assert (ltrel_base
== pending_ltrel
);
6653 pending_ltrel
= NULL_RTX
;
6657 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
6660 curr_pool
= s390_start_pool (&pool_list
, insn
);
6662 s390_add_execute (curr_pool
, insn
);
6663 s390_add_pool_insn (curr_pool
, insn
);
6665 else if (GET_CODE (insn
) == INSN
|| CALL_P (insn
))
6667 rtx pool_ref
= NULL_RTX
;
6668 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6671 rtx constant
= get_pool_constant (pool_ref
);
6672 enum machine_mode mode
= get_pool_mode (pool_ref
);
6675 curr_pool
= s390_start_pool (&pool_list
, insn
);
6677 s390_add_constant (curr_pool
, constant
, mode
);
6678 s390_add_pool_insn (curr_pool
, insn
);
6680 /* Don't split the pool chunk between a LTREL_OFFSET load
6681 and the corresponding LTREL_BASE. */
6682 if (GET_CODE (constant
) == CONST
6683 && GET_CODE (XEXP (constant
, 0)) == UNSPEC
6684 && XINT (XEXP (constant
, 0), 1) == UNSPEC_LTREL_OFFSET
)
6686 gcc_assert (!pending_ltrel
);
6687 pending_ltrel
= pool_ref
;
6690 /* Make sure we do not split between a call and its
6691 corresponding CALL_ARG_LOCATION note. */
6694 rtx next
= NEXT_INSN (insn
);
6695 if (next
&& NOTE_P (next
)
6696 && NOTE_KIND (next
) == NOTE_INSN_CALL_ARG_LOCATION
)
6701 if (GET_CODE (insn
) == JUMP_INSN
|| GET_CODE (insn
) == CODE_LABEL
)
6704 s390_add_pool_insn (curr_pool
, insn
);
6705 /* An LTREL_BASE must follow within the same basic block. */
6706 gcc_assert (!pending_ltrel
);
6709 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_SWITCH_TEXT_SECTIONS
)
6710 section_switch_p
= true;
6713 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn
)
6714 || INSN_ADDRESSES (INSN_UID (insn
)) == -1)
6717 if (TARGET_CPU_ZARCH
)
6719 if (curr_pool
->size
< S390_POOL_CHUNK_MAX
)
6722 s390_end_pool (curr_pool
, NULL_RTX
);
6727 int chunk_size
= INSN_ADDRESSES (INSN_UID (insn
))
6728 - INSN_ADDRESSES (INSN_UID (curr_pool
->first_insn
))
6731 /* We will later have to insert base register reload insns.
6732 Those will have an effect on code size, which we need to
6733 consider here. This calculation makes rather pessimistic
6734 worst-case assumptions. */
6735 if (GET_CODE (insn
) == CODE_LABEL
)
6738 if (chunk_size
< S390_POOL_CHUNK_MIN
6739 && curr_pool
->size
< S390_POOL_CHUNK_MIN
6740 && !section_switch_p
)
6743 /* Pool chunks can only be inserted after BARRIERs ... */
6744 if (GET_CODE (insn
) == BARRIER
)
6746 s390_end_pool (curr_pool
, insn
);
6751 /* ... so if we don't find one in time, create one. */
6752 else if (chunk_size
> S390_POOL_CHUNK_MAX
6753 || curr_pool
->size
> S390_POOL_CHUNK_MAX
6754 || section_switch_p
)
6756 rtx label
, jump
, barrier
;
6758 if (!section_switch_p
)
6760 /* We can insert the barrier only after a 'real' insn. */
6761 if (GET_CODE (insn
) != INSN
&& GET_CODE (insn
) != CALL_INSN
)
6763 if (get_attr_length (insn
) == 0)
6765 /* Don't separate LTREL_BASE from the corresponding
6766 LTREL_OFFSET load. */
6772 gcc_assert (!pending_ltrel
);
6774 /* The old pool has to end before the section switch
6775 note in order to make it part of the current
6777 insn
= PREV_INSN (insn
);
6780 label
= gen_label_rtx ();
6781 jump
= emit_jump_insn_after (gen_jump (label
), insn
);
6782 barrier
= emit_barrier_after (jump
);
6783 insn
= emit_label_after (label
, barrier
);
6784 JUMP_LABEL (jump
) = label
;
6785 LABEL_NUSES (label
) = 1;
6787 INSN_ADDRESSES_NEW (jump
, -1);
6788 INSN_ADDRESSES_NEW (barrier
, -1);
6789 INSN_ADDRESSES_NEW (insn
, -1);
6791 s390_end_pool (curr_pool
, barrier
);
6799 s390_end_pool (curr_pool
, NULL_RTX
);
6800 gcc_assert (!pending_ltrel
);
6802 /* Find all labels that are branched into
6803 from an insn belonging to a different chunk. */
6805 far_labels
= BITMAP_ALLOC (NULL
);
6807 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6809 /* Labels marked with LABEL_PRESERVE_P can be target
6810 of non-local jumps, so we have to mark them.
6811 The same holds for named labels.
6813 Don't do that, however, if it is the label before
6816 if (GET_CODE (insn
) == CODE_LABEL
6817 && (LABEL_PRESERVE_P (insn
) || LABEL_NAME (insn
)))
6819 rtx vec_insn
= next_real_insn (insn
);
6820 rtx vec_pat
= vec_insn
&& GET_CODE (vec_insn
) == JUMP_INSN
?
6821 PATTERN (vec_insn
) : NULL_RTX
;
6823 || !(GET_CODE (vec_pat
) == ADDR_VEC
6824 || GET_CODE (vec_pat
) == ADDR_DIFF_VEC
))
6825 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (insn
));
6828 /* If we have a direct jump (conditional or unconditional)
6829 or a casesi jump, check all potential targets. */
6830 else if (GET_CODE (insn
) == JUMP_INSN
)
6832 rtx pat
= PATTERN (insn
);
6833 if (GET_CODE (pat
) == PARALLEL
&& XVECLEN (pat
, 0) > 2)
6834 pat
= XVECEXP (pat
, 0, 0);
6836 if (GET_CODE (pat
) == SET
)
6838 rtx label
= JUMP_LABEL (insn
);
6841 if (s390_find_pool (pool_list
, label
)
6842 != s390_find_pool (pool_list
, insn
))
6843 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
6846 else if (GET_CODE (pat
) == PARALLEL
6847 && XVECLEN (pat
, 0) == 2
6848 && GET_CODE (XVECEXP (pat
, 0, 0)) == SET
6849 && GET_CODE (XVECEXP (pat
, 0, 1)) == USE
6850 && GET_CODE (XEXP (XVECEXP (pat
, 0, 1), 0)) == LABEL_REF
)
6852 /* Find the jump table used by this casesi jump. */
6853 rtx vec_label
= XEXP (XEXP (XVECEXP (pat
, 0, 1), 0), 0);
6854 rtx vec_insn
= next_real_insn (vec_label
);
6855 rtx vec_pat
= vec_insn
&& GET_CODE (vec_insn
) == JUMP_INSN
?
6856 PATTERN (vec_insn
) : NULL_RTX
;
6858 && (GET_CODE (vec_pat
) == ADDR_VEC
6859 || GET_CODE (vec_pat
) == ADDR_DIFF_VEC
))
6861 int i
, diff_p
= GET_CODE (vec_pat
) == ADDR_DIFF_VEC
;
6863 for (i
= 0; i
< XVECLEN (vec_pat
, diff_p
); i
++)
6865 rtx label
= XEXP (XVECEXP (vec_pat
, diff_p
, i
), 0);
6867 if (s390_find_pool (pool_list
, label
)
6868 != s390_find_pool (pool_list
, insn
))
6869 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
6876 /* Insert base register reload insns before every pool. */
6878 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
6880 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
6882 rtx insn
= curr_pool
->first_insn
;
6883 INSN_ADDRESSES_NEW (emit_insn_before (new_insn
, insn
), -1);
6886 /* Insert base register reload insns at every far label. */
6888 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6889 if (GET_CODE (insn
) == CODE_LABEL
6890 && bitmap_bit_p (far_labels
, CODE_LABEL_NUMBER (insn
)))
6892 struct constant_pool
*pool
= s390_find_pool (pool_list
, insn
);
6895 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
6897 INSN_ADDRESSES_NEW (emit_insn_after (new_insn
, insn
), -1);
6902 BITMAP_FREE (far_labels
);
6905 /* Recompute insn addresses. */
6907 init_insn_lengths ();
6908 shorten_branches (get_insns ());
6913 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6914 After we have decided to use this list, finish implementing
6915 all changes to the current function as required. */
6918 s390_chunkify_finish (struct constant_pool
*pool_list
)
6920 struct constant_pool
*curr_pool
= NULL
;
6924 /* Replace all literal pool references. */
6926 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6929 replace_ltrel_base (&PATTERN (insn
));
6931 curr_pool
= s390_find_pool (pool_list
, insn
);
6935 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6937 rtx addr
, pool_ref
= NULL_RTX
;
6938 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6941 if (s390_execute_label (insn
))
6942 addr
= s390_find_execute (curr_pool
, insn
);
6944 addr
= s390_find_constant (curr_pool
,
6945 get_pool_constant (pool_ref
),
6946 get_pool_mode (pool_ref
));
6948 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
6949 INSN_CODE (insn
) = -1;
6954 /* Dump out all literal pools. */
6956 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
6957 s390_dump_pool (curr_pool
, 0);
6959 /* Free pool list. */
6963 struct constant_pool
*next
= pool_list
->next
;
6964 s390_free_pool (pool_list
);
6969 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6970 We have decided we cannot use this list, so revert all changes
6971 to the current function that were done by s390_chunkify_start. */
6974 s390_chunkify_cancel (struct constant_pool
*pool_list
)
6976 struct constant_pool
*curr_pool
= NULL
;
6979 /* Remove all pool placeholder insns. */
6981 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
6983 /* Did we insert an extra barrier? Remove it. */
6984 rtx barrier
= PREV_INSN (curr_pool
->pool_insn
);
6985 rtx jump
= barrier
? PREV_INSN (barrier
) : NULL_RTX
;
6986 rtx label
= NEXT_INSN (curr_pool
->pool_insn
);
6988 if (jump
&& GET_CODE (jump
) == JUMP_INSN
6989 && barrier
&& GET_CODE (barrier
) == BARRIER
6990 && label
&& GET_CODE (label
) == CODE_LABEL
6991 && GET_CODE (PATTERN (jump
)) == SET
6992 && SET_DEST (PATTERN (jump
)) == pc_rtx
6993 && GET_CODE (SET_SRC (PATTERN (jump
))) == LABEL_REF
6994 && XEXP (SET_SRC (PATTERN (jump
)), 0) == label
)
6997 remove_insn (barrier
);
6998 remove_insn (label
);
7001 remove_insn (curr_pool
->pool_insn
);
7004 /* Remove all base register reload insns. */
7006 for (insn
= get_insns (); insn
; )
7008 rtx next_insn
= NEXT_INSN (insn
);
7010 if (GET_CODE (insn
) == INSN
7011 && GET_CODE (PATTERN (insn
)) == SET
7012 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC
7013 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPEC_RELOAD_BASE
)
7019 /* Free pool list. */
7023 struct constant_pool
*next
= pool_list
->next
;
7024 s390_free_pool (pool_list
);
7029 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
7032 s390_output_pool_entry (rtx exp
, enum machine_mode mode
, unsigned int align
)
7036 switch (GET_MODE_CLASS (mode
))
7039 case MODE_DECIMAL_FLOAT
:
7040 gcc_assert (GET_CODE (exp
) == CONST_DOUBLE
);
7042 REAL_VALUE_FROM_CONST_DOUBLE (r
, exp
);
7043 assemble_real (r
, mode
, align
);
7047 assemble_integer (exp
, GET_MODE_SIZE (mode
), align
, 1);
7048 mark_symbol_refs_as_used (exp
);
7057 /* Return an RTL expression representing the value of the return address
7058 for the frame COUNT steps up from the current frame. FRAME is the
7059 frame pointer of that frame. */
7062 s390_return_addr_rtx (int count
, rtx frame ATTRIBUTE_UNUSED
)
7067 /* Without backchain, we fail for all but the current frame. */
7069 if (!TARGET_BACKCHAIN
&& count
> 0)
7072 /* For the current frame, we need to make sure the initial
7073 value of RETURN_REGNUM is actually saved. */
7077 /* On non-z architectures branch splitting could overwrite r14. */
7078 if (TARGET_CPU_ZARCH
)
7079 return get_hard_reg_initial_val (Pmode
, RETURN_REGNUM
);
7082 cfun_frame_layout
.save_return_addr_p
= true;
7083 return gen_rtx_MEM (Pmode
, return_address_pointer_rtx
);
7087 if (TARGET_PACKED_STACK
)
7088 offset
= -2 * UNITS_PER_LONG
;
7090 offset
= RETURN_REGNUM
* UNITS_PER_LONG
;
7092 addr
= plus_constant (frame
, offset
);
7093 addr
= memory_address (Pmode
, addr
);
7094 return gen_rtx_MEM (Pmode
, addr
);
7097 /* Return an RTL expression representing the back chain stored in
7098 the current stack frame. */
7101 s390_back_chain_rtx (void)
7105 gcc_assert (TARGET_BACKCHAIN
);
7107 if (TARGET_PACKED_STACK
)
7108 chain
= plus_constant (stack_pointer_rtx
,
7109 STACK_POINTER_OFFSET
- UNITS_PER_LONG
);
7111 chain
= stack_pointer_rtx
;
7113 chain
= gen_rtx_MEM (Pmode
, chain
);
7117 /* Find first call clobbered register unused in a function.
7118 This could be used as base register in a leaf function
7119 or for holding the return address before epilogue. */
7122 find_unused_clobbered_reg (void)
7125 for (i
= 0; i
< 6; i
++)
7126 if (!df_regs_ever_live_p (i
))
7132 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
7133 clobbered hard regs in SETREG. */
7136 s390_reg_clobbered_rtx (rtx setreg
, const_rtx set_insn ATTRIBUTE_UNUSED
, void *data
)
7138 int *regs_ever_clobbered
= (int *)data
;
7139 unsigned int i
, regno
;
7140 enum machine_mode mode
= GET_MODE (setreg
);
7142 if (GET_CODE (setreg
) == SUBREG
)
7144 rtx inner
= SUBREG_REG (setreg
);
7145 if (!GENERAL_REG_P (inner
))
7147 regno
= subreg_regno (setreg
);
7149 else if (GENERAL_REG_P (setreg
))
7150 regno
= REGNO (setreg
);
7155 i
< regno
+ HARD_REGNO_NREGS (regno
, mode
);
7157 regs_ever_clobbered
[i
] = 1;
7160 /* Walks through all basic blocks of the current function looking
7161 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
7162 of the passed integer array REGS_EVER_CLOBBERED are set to one for
7163 each of those regs. */
7166 s390_regs_ever_clobbered (int *regs_ever_clobbered
)
7172 memset (regs_ever_clobbered
, 0, 16 * sizeof (int));
7174 /* For non-leaf functions we have to consider all call clobbered regs to be
7176 if (!current_function_is_leaf
)
7178 for (i
= 0; i
< 16; i
++)
7179 regs_ever_clobbered
[i
] = call_really_used_regs
[i
];
7182 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
7183 this work is done by liveness analysis (mark_regs_live_at_end).
7184 Special care is needed for functions containing landing pads. Landing pads
7185 may use the eh registers, but the code which sets these registers is not
7186 contained in that function. Hence s390_regs_ever_clobbered is not able to
7187 deal with this automatically. */
7188 if (crtl
->calls_eh_return
|| cfun
->machine
->has_landing_pad_p
)
7189 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
7190 if (crtl
->calls_eh_return
7191 || (cfun
->machine
->has_landing_pad_p
7192 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i
))))
7193 regs_ever_clobbered
[EH_RETURN_DATA_REGNO (i
)] = 1;
7195 /* For nonlocal gotos all call-saved registers have to be saved.
7196 This flag is also set for the unwinding code in libgcc.
7197 See expand_builtin_unwind_init. For regs_ever_live this is done by
7199 if (cfun
->has_nonlocal_label
)
7200 for (i
= 0; i
< 16; i
++)
7201 if (!call_really_used_regs
[i
])
7202 regs_ever_clobbered
[i
] = 1;
7204 FOR_EACH_BB (cur_bb
)
7206 FOR_BB_INSNS (cur_bb
, cur_insn
)
7208 if (INSN_P (cur_insn
))
7209 note_stores (PATTERN (cur_insn
),
7210 s390_reg_clobbered_rtx
,
7211 regs_ever_clobbered
);
7216 /* Determine the frame area which actually has to be accessed
7217 in the function epilogue. The values are stored at the
7218 given pointers AREA_BOTTOM (address of the lowest used stack
7219 address) and AREA_TOP (address of the first item which does
7220 not belong to the stack frame). */
7223 s390_frame_area (int *area_bottom
, int *area_top
)
7231 if (cfun_frame_layout
.first_restore_gpr
!= -1)
7233 b
= (cfun_frame_layout
.gprs_offset
7234 + cfun_frame_layout
.first_restore_gpr
* UNITS_PER_LONG
);
7235 t
= b
+ (cfun_frame_layout
.last_restore_gpr
7236 - cfun_frame_layout
.first_restore_gpr
+ 1) * UNITS_PER_LONG
;
7239 if (TARGET_64BIT
&& cfun_save_high_fprs_p
)
7241 b
= MIN (b
, cfun_frame_layout
.f8_offset
);
7242 t
= MAX (t
, (cfun_frame_layout
.f8_offset
7243 + cfun_frame_layout
.high_fprs
* 8));
7247 for (i
= 2; i
< 4; i
++)
7248 if (cfun_fpr_bit_p (i
))
7250 b
= MIN (b
, cfun_frame_layout
.f4_offset
+ (i
- 2) * 8);
7251 t
= MAX (t
, cfun_frame_layout
.f4_offset
+ (i
- 1) * 8);
7258 /* Fill cfun->machine with info about register usage of current function.
7259 Return in CLOBBERED_REGS which GPRs are currently considered set. */
7262 s390_register_info (int clobbered_regs
[])
7266 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
7267 cfun_frame_layout
.fpr_bitmap
= 0;
7268 cfun_frame_layout
.high_fprs
= 0;
7270 for (i
= 24; i
< 32; i
++)
7271 if (df_regs_ever_live_p (i
) && !global_regs
[i
])
7273 cfun_set_fpr_bit (i
- 16);
7274 cfun_frame_layout
.high_fprs
++;
7277 /* Find first and last gpr to be saved. We trust regs_ever_live
7278 data, except that we don't save and restore global registers.
7280 Also, all registers with special meaning to the compiler need
7281 to be handled extra. */
7283 s390_regs_ever_clobbered (clobbered_regs
);
7285 for (i
= 0; i
< 16; i
++)
7286 clobbered_regs
[i
] = clobbered_regs
[i
] && !global_regs
[i
] && !fixed_regs
[i
];
7288 if (frame_pointer_needed
)
7289 clobbered_regs
[HARD_FRAME_POINTER_REGNUM
] = 1;
7292 clobbered_regs
[PIC_OFFSET_TABLE_REGNUM
]
7293 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
);
7295 clobbered_regs
[BASE_REGNUM
]
7296 |= (cfun
->machine
->base_reg
7297 && REGNO (cfun
->machine
->base_reg
) == BASE_REGNUM
);
7299 clobbered_regs
[RETURN_REGNUM
]
7300 |= (!current_function_is_leaf
7301 || TARGET_TPF_PROFILING
7302 || cfun
->machine
->split_branches_pending_p
7303 || cfun_frame_layout
.save_return_addr_p
7304 || crtl
->calls_eh_return
7307 clobbered_regs
[STACK_POINTER_REGNUM
]
7308 |= (!current_function_is_leaf
7309 || TARGET_TPF_PROFILING
7310 || cfun_save_high_fprs_p
7311 || get_frame_size () > 0
7312 || cfun
->calls_alloca
7315 for (i
= 6; i
< 16; i
++)
7316 if (df_regs_ever_live_p (i
) || clobbered_regs
[i
])
7318 for (j
= 15; j
> i
; j
--)
7319 if (df_regs_ever_live_p (j
) || clobbered_regs
[j
])
7324 /* Nothing to save/restore. */
7325 cfun_frame_layout
.first_save_gpr_slot
= -1;
7326 cfun_frame_layout
.last_save_gpr_slot
= -1;
7327 cfun_frame_layout
.first_save_gpr
= -1;
7328 cfun_frame_layout
.first_restore_gpr
= -1;
7329 cfun_frame_layout
.last_save_gpr
= -1;
7330 cfun_frame_layout
.last_restore_gpr
= -1;
7334 /* Save slots for gprs from i to j. */
7335 cfun_frame_layout
.first_save_gpr_slot
= i
;
7336 cfun_frame_layout
.last_save_gpr_slot
= j
;
7338 for (i
= cfun_frame_layout
.first_save_gpr_slot
;
7339 i
< cfun_frame_layout
.last_save_gpr_slot
+ 1;
7341 if (clobbered_regs
[i
])
7344 for (j
= cfun_frame_layout
.last_save_gpr_slot
; j
> i
; j
--)
7345 if (clobbered_regs
[j
])
7348 if (i
== cfun_frame_layout
.last_save_gpr_slot
+ 1)
7350 /* Nothing to save/restore. */
7351 cfun_frame_layout
.first_save_gpr
= -1;
7352 cfun_frame_layout
.first_restore_gpr
= -1;
7353 cfun_frame_layout
.last_save_gpr
= -1;
7354 cfun_frame_layout
.last_restore_gpr
= -1;
7358 /* Save / Restore from gpr i to j. */
7359 cfun_frame_layout
.first_save_gpr
= i
;
7360 cfun_frame_layout
.first_restore_gpr
= i
;
7361 cfun_frame_layout
.last_save_gpr
= j
;
7362 cfun_frame_layout
.last_restore_gpr
= j
;
7368 /* Varargs functions need to save gprs 2 to 6. */
7369 if (cfun
->va_list_gpr_size
7370 && crtl
->args
.info
.gprs
< GP_ARG_NUM_REG
)
7372 int min_gpr
= crtl
->args
.info
.gprs
;
7373 int max_gpr
= min_gpr
+ cfun
->va_list_gpr_size
;
7374 if (max_gpr
> GP_ARG_NUM_REG
)
7375 max_gpr
= GP_ARG_NUM_REG
;
7377 if (cfun_frame_layout
.first_save_gpr
== -1
7378 || cfun_frame_layout
.first_save_gpr
> 2 + min_gpr
)
7380 cfun_frame_layout
.first_save_gpr
= 2 + min_gpr
;
7381 cfun_frame_layout
.first_save_gpr_slot
= 2 + min_gpr
;
7384 if (cfun_frame_layout
.last_save_gpr
== -1
7385 || cfun_frame_layout
.last_save_gpr
< 2 + max_gpr
- 1)
7387 cfun_frame_layout
.last_save_gpr
= 2 + max_gpr
- 1;
7388 cfun_frame_layout
.last_save_gpr_slot
= 2 + max_gpr
- 1;
7392 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
7393 if (TARGET_HARD_FLOAT
&& cfun
->va_list_fpr_size
7394 && crtl
->args
.info
.fprs
< FP_ARG_NUM_REG
)
7396 int min_fpr
= crtl
->args
.info
.fprs
;
7397 int max_fpr
= min_fpr
+ cfun
->va_list_fpr_size
;
7398 if (max_fpr
> FP_ARG_NUM_REG
)
7399 max_fpr
= FP_ARG_NUM_REG
;
7401 /* ??? This is currently required to ensure proper location
7402 of the fpr save slots within the va_list save area. */
7403 if (TARGET_PACKED_STACK
)
7406 for (i
= min_fpr
; i
< max_fpr
; i
++)
7407 cfun_set_fpr_bit (i
);
7412 for (i
= 2; i
< 4; i
++)
7413 if (df_regs_ever_live_p (i
+ 16) && !global_regs
[i
+ 16])
7414 cfun_set_fpr_bit (i
);
7417 /* Fill cfun->machine with info about frame of current function. */
7420 s390_frame_info (void)
7424 cfun_frame_layout
.frame_size
= get_frame_size ();
7425 if (!TARGET_64BIT
&& cfun_frame_layout
.frame_size
> 0x7fff0000)
7426 fatal_error ("total size of local variables exceeds architecture limit");
7428 if (!TARGET_PACKED_STACK
)
7430 cfun_frame_layout
.backchain_offset
= 0;
7431 cfun_frame_layout
.f0_offset
= 16 * UNITS_PER_LONG
;
7432 cfun_frame_layout
.f4_offset
= cfun_frame_layout
.f0_offset
+ 2 * 8;
7433 cfun_frame_layout
.f8_offset
= -cfun_frame_layout
.high_fprs
* 8;
7434 cfun_frame_layout
.gprs_offset
= (cfun_frame_layout
.first_save_gpr_slot
7437 else if (TARGET_BACKCHAIN
) /* kernel stack layout */
7439 cfun_frame_layout
.backchain_offset
= (STACK_POINTER_OFFSET
7441 cfun_frame_layout
.gprs_offset
7442 = (cfun_frame_layout
.backchain_offset
7443 - (STACK_POINTER_REGNUM
- cfun_frame_layout
.first_save_gpr_slot
+ 1)
7448 cfun_frame_layout
.f4_offset
7449 = (cfun_frame_layout
.gprs_offset
7450 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7452 cfun_frame_layout
.f0_offset
7453 = (cfun_frame_layout
.f4_offset
7454 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7458 /* On 31 bit we have to care about alignment of the
7459 floating point regs to provide fastest access. */
7460 cfun_frame_layout
.f0_offset
7461 = ((cfun_frame_layout
.gprs_offset
7462 & ~(STACK_BOUNDARY
/ BITS_PER_UNIT
- 1))
7463 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7465 cfun_frame_layout
.f4_offset
7466 = (cfun_frame_layout
.f0_offset
7467 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7470 else /* no backchain */
7472 cfun_frame_layout
.f4_offset
7473 = (STACK_POINTER_OFFSET
7474 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
7476 cfun_frame_layout
.f0_offset
7477 = (cfun_frame_layout
.f4_offset
7478 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
7480 cfun_frame_layout
.gprs_offset
7481 = cfun_frame_layout
.f0_offset
- cfun_gprs_save_area_size
;
7484 if (current_function_is_leaf
7485 && !TARGET_TPF_PROFILING
7486 && cfun_frame_layout
.frame_size
== 0
7487 && !cfun_save_high_fprs_p
7488 && !cfun
->calls_alloca
7492 if (!TARGET_PACKED_STACK
)
7493 cfun_frame_layout
.frame_size
+= (STACK_POINTER_OFFSET
7494 + crtl
->outgoing_args_size
7495 + cfun_frame_layout
.high_fprs
* 8);
7498 if (TARGET_BACKCHAIN
)
7499 cfun_frame_layout
.frame_size
+= UNITS_PER_LONG
;
7501 /* No alignment trouble here because f8-f15 are only saved under
7503 cfun_frame_layout
.f8_offset
= (MIN (MIN (cfun_frame_layout
.f0_offset
,
7504 cfun_frame_layout
.f4_offset
),
7505 cfun_frame_layout
.gprs_offset
)
7506 - cfun_frame_layout
.high_fprs
* 8);
7508 cfun_frame_layout
.frame_size
+= cfun_frame_layout
.high_fprs
* 8;
7510 for (i
= 0; i
< 8; i
++)
7511 if (cfun_fpr_bit_p (i
))
7512 cfun_frame_layout
.frame_size
+= 8;
7514 cfun_frame_layout
.frame_size
+= cfun_gprs_save_area_size
;
7516 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
7517 the frame size to sustain 8 byte alignment of stack frames. */
7518 cfun_frame_layout
.frame_size
= ((cfun_frame_layout
.frame_size
+
7519 STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
7520 & ~(STACK_BOUNDARY
/ BITS_PER_UNIT
- 1));
7522 cfun_frame_layout
.frame_size
+= crtl
->outgoing_args_size
;
7526 /* Generate frame layout. Fills in register and frame data for the current
7527 function in cfun->machine. This routine can be called multiple times;
7528 it will re-do the complete frame layout every time. */
7531 s390_init_frame_layout (void)
7533 HOST_WIDE_INT frame_size
;
7535 int clobbered_regs
[16];
7537 /* On S/390 machines, we may need to perform branch splitting, which
7538 will require both base and return address register. We have no
7539 choice but to assume we're going to need them until right at the
7540 end of the machine dependent reorg phase. */
7541 if (!TARGET_CPU_ZARCH
)
7542 cfun
->machine
->split_branches_pending_p
= true;
7546 frame_size
= cfun_frame_layout
.frame_size
;
7548 /* Try to predict whether we'll need the base register. */
7549 base_used
= cfun
->machine
->split_branches_pending_p
7550 || crtl
->uses_const_pool
7551 || (!DISP_IN_RANGE (frame_size
)
7552 && !CONST_OK_FOR_K (frame_size
));
7554 /* Decide which register to use as literal pool base. In small
7555 leaf functions, try to use an unused call-clobbered register
7556 as base register to avoid save/restore overhead. */
7558 cfun
->machine
->base_reg
= NULL_RTX
;
7559 else if (current_function_is_leaf
&& !df_regs_ever_live_p (5))
7560 cfun
->machine
->base_reg
= gen_rtx_REG (Pmode
, 5);
7562 cfun
->machine
->base_reg
= gen_rtx_REG (Pmode
, BASE_REGNUM
);
7564 s390_register_info (clobbered_regs
);
7567 while (frame_size
!= cfun_frame_layout
.frame_size
);
7570 /* Update frame layout. Recompute actual register save data based on
7571 current info and update regs_ever_live for the special registers.
7572 May be called multiple times, but may never cause *more* registers
7573 to be saved than s390_init_frame_layout allocated room for. */
7576 s390_update_frame_layout (void)
7578 int clobbered_regs
[16];
7580 s390_register_info (clobbered_regs
);
7582 df_set_regs_ever_live (BASE_REGNUM
,
7583 clobbered_regs
[BASE_REGNUM
] ? true : false);
7584 df_set_regs_ever_live (RETURN_REGNUM
,
7585 clobbered_regs
[RETURN_REGNUM
] ? true : false);
7586 df_set_regs_ever_live (STACK_POINTER_REGNUM
,
7587 clobbered_regs
[STACK_POINTER_REGNUM
] ? true : false);
7589 if (cfun
->machine
->base_reg
)
7590 df_set_regs_ever_live (REGNO (cfun
->machine
->base_reg
), true);
7593 /* Return true if it is legal to put a value with MODE into REGNO. */
7596 s390_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
7598 switch (REGNO_REG_CLASS (regno
))
7601 if (REGNO_PAIR_OK (regno
, mode
))
7603 if (mode
== SImode
|| mode
== DImode
)
7606 if (FLOAT_MODE_P (mode
) && GET_MODE_CLASS (mode
) != MODE_VECTOR_FLOAT
)
7611 if (FRAME_REGNO_P (regno
) && mode
== Pmode
)
7616 if (REGNO_PAIR_OK (regno
, mode
))
7619 || (mode
!= TFmode
&& mode
!= TCmode
&& mode
!= TDmode
))
7624 if (GET_MODE_CLASS (mode
) == MODE_CC
)
7628 if (REGNO_PAIR_OK (regno
, mode
))
7630 if (mode
== SImode
|| mode
== Pmode
)
7641 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
7644 s390_hard_regno_rename_ok (unsigned int old_reg
, unsigned int new_reg
)
7646 /* Once we've decided upon a register to use as base register, it must
7647 no longer be used for any other purpose. */
7648 if (cfun
->machine
->base_reg
)
7649 if (REGNO (cfun
->machine
->base_reg
) == old_reg
7650 || REGNO (cfun
->machine
->base_reg
) == new_reg
)
7656 /* Maximum number of registers to represent a value of mode MODE
7657 in a register of class RCLASS. */
7660 s390_class_max_nregs (enum reg_class rclass
, enum machine_mode mode
)
7665 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
7666 return 2 * ((GET_MODE_SIZE (mode
) / 2 + 8 - 1) / 8);
7668 return (GET_MODE_SIZE (mode
) + 8 - 1) / 8;
7670 return (GET_MODE_SIZE (mode
) + 4 - 1) / 4;
7674 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
7677 /* Return true if register FROM can be eliminated via register TO. */
7680 s390_can_eliminate (const int from
, const int to
)
7682 /* On zSeries machines, we have not marked the base register as fixed.
7683 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
7684 If a function requires the base register, we say here that this
7685 elimination cannot be performed. This will cause reload to free
7686 up the base register (as if it were fixed). On the other hand,
7687 if the current function does *not* require the base register, we
7688 say here the elimination succeeds, which in turn allows reload
7689 to allocate the base register for any other purpose. */
7690 if (from
== BASE_REGNUM
&& to
== BASE_REGNUM
)
7692 if (TARGET_CPU_ZARCH
)
7694 s390_init_frame_layout ();
7695 return cfun
->machine
->base_reg
== NULL_RTX
;
7701 /* Everything else must point into the stack frame. */
7702 gcc_assert (to
== STACK_POINTER_REGNUM
7703 || to
== HARD_FRAME_POINTER_REGNUM
);
7705 gcc_assert (from
== FRAME_POINTER_REGNUM
7706 || from
== ARG_POINTER_REGNUM
7707 || from
== RETURN_ADDRESS_POINTER_REGNUM
);
7709 /* Make sure we actually saved the return address. */
7710 if (from
== RETURN_ADDRESS_POINTER_REGNUM
)
7711 if (!crtl
->calls_eh_return
7713 && !cfun_frame_layout
.save_return_addr_p
)
7719 /* Return offset between register FROM and TO initially after prolog. */
7722 s390_initial_elimination_offset (int from
, int to
)
7724 HOST_WIDE_INT offset
;
7727 /* ??? Why are we called for non-eliminable pairs? */
7728 if (!s390_can_eliminate (from
, to
))
7733 case FRAME_POINTER_REGNUM
:
7734 offset
= (get_frame_size()
7735 + STACK_POINTER_OFFSET
7736 + crtl
->outgoing_args_size
);
7739 case ARG_POINTER_REGNUM
:
7740 s390_init_frame_layout ();
7741 offset
= cfun_frame_layout
.frame_size
+ STACK_POINTER_OFFSET
;
7744 case RETURN_ADDRESS_POINTER_REGNUM
:
7745 s390_init_frame_layout ();
7746 index
= RETURN_REGNUM
- cfun_frame_layout
.first_save_gpr_slot
;
7747 gcc_assert (index
>= 0);
7748 offset
= cfun_frame_layout
.frame_size
+ cfun_frame_layout
.gprs_offset
;
7749 offset
+= index
* UNITS_PER_LONG
;
7763 /* Emit insn to save fpr REGNUM at offset OFFSET relative
7764 to register BASE. Return generated insn. */
7767 save_fpr (rtx base
, int offset
, int regnum
)
7770 addr
= gen_rtx_MEM (DFmode
, plus_constant (base
, offset
));
7772 if (regnum
>= 16 && regnum
<= (16 + FP_ARG_NUM_REG
))
7773 set_mem_alias_set (addr
, get_varargs_alias_set ());
7775 set_mem_alias_set (addr
, get_frame_alias_set ());
7777 return emit_move_insn (addr
, gen_rtx_REG (DFmode
, regnum
));
7780 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
7781 to register BASE. Return generated insn. */
7784 restore_fpr (rtx base
, int offset
, int regnum
)
7787 addr
= gen_rtx_MEM (DFmode
, plus_constant (base
, offset
));
7788 set_mem_alias_set (addr
, get_frame_alias_set ());
7790 return emit_move_insn (gen_rtx_REG (DFmode
, regnum
), addr
);
7793 /* Return true if REGNO is a global register, but not one
7794 of the special ones that need to be saved/restored in anyway. */
7797 global_not_special_regno_p (int regno
)
7799 return (global_regs
[regno
]
7800 /* These registers are special and need to be
7801 restored in any case. */
7802 && !(regno
== STACK_POINTER_REGNUM
7803 || regno
== RETURN_REGNUM
7804 || regno
== BASE_REGNUM
7805 || (flag_pic
&& regno
== (int)PIC_OFFSET_TABLE_REGNUM
)));
7808 /* Generate insn to save registers FIRST to LAST into
7809 the register save area located at offset OFFSET
7810 relative to register BASE. */
7813 save_gprs (rtx base
, int offset
, int first
, int last
)
7815 rtx addr
, insn
, note
;
7818 addr
= plus_constant (base
, offset
);
7819 addr
= gen_rtx_MEM (Pmode
, addr
);
7821 set_mem_alias_set (addr
, get_frame_alias_set ());
7823 /* Special-case single register. */
7827 insn
= gen_movdi (addr
, gen_rtx_REG (Pmode
, first
));
7829 insn
= gen_movsi (addr
, gen_rtx_REG (Pmode
, first
));
7831 if (!global_not_special_regno_p (first
))
7832 RTX_FRAME_RELATED_P (insn
) = 1;
7837 insn
= gen_store_multiple (addr
,
7838 gen_rtx_REG (Pmode
, first
),
7839 GEN_INT (last
- first
+ 1));
7841 if (first
<= 6 && cfun
->stdarg
)
7842 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
7844 rtx mem
= XEXP (XVECEXP (PATTERN (insn
), 0, i
), 0);
7847 set_mem_alias_set (mem
, get_varargs_alias_set ());
7850 /* We need to set the FRAME_RELATED flag on all SETs
7851 inside the store-multiple pattern.
7853 However, we must not emit DWARF records for registers 2..5
7854 if they are stored for use by variable arguments ...
7856 ??? Unfortunately, it is not enough to simply not the
7857 FRAME_RELATED flags for those SETs, because the first SET
7858 of the PARALLEL is always treated as if it had the flag
7859 set, even if it does not. Therefore we emit a new pattern
7860 without those registers as REG_FRAME_RELATED_EXPR note. */
7862 if (first
>= 6 && !global_not_special_regno_p (first
))
7864 rtx pat
= PATTERN (insn
);
7866 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
7867 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
7868 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat
,
7870 RTX_FRAME_RELATED_P (XVECEXP (pat
, 0, i
)) = 1;
7872 RTX_FRAME_RELATED_P (insn
) = 1;
7878 for (start
= first
>= 6 ? first
: 6; start
<= last
; start
++)
7879 if (!global_not_special_regno_p (start
))
7885 addr
= plus_constant (base
, offset
+ (start
- first
) * UNITS_PER_LONG
);
7886 note
= gen_store_multiple (gen_rtx_MEM (Pmode
, addr
),
7887 gen_rtx_REG (Pmode
, start
),
7888 GEN_INT (last
- start
+ 1));
7889 note
= PATTERN (note
);
7891 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note
);
7893 for (i
= 0; i
< XVECLEN (note
, 0); i
++)
7894 if (GET_CODE (XVECEXP (note
, 0, i
)) == SET
7895 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note
,
7897 RTX_FRAME_RELATED_P (XVECEXP (note
, 0, i
)) = 1;
7899 RTX_FRAME_RELATED_P (insn
) = 1;
7905 /* Generate insn to restore registers FIRST to LAST from
7906 the register save area located at offset OFFSET
7907 relative to register BASE. */
7910 restore_gprs (rtx base
, int offset
, int first
, int last
)
7914 addr
= plus_constant (base
, offset
);
7915 addr
= gen_rtx_MEM (Pmode
, addr
);
7916 set_mem_alias_set (addr
, get_frame_alias_set ());
7918 /* Special-case single register. */
7922 insn
= gen_movdi (gen_rtx_REG (Pmode
, first
), addr
);
7924 insn
= gen_movsi (gen_rtx_REG (Pmode
, first
), addr
);
7929 insn
= gen_load_multiple (gen_rtx_REG (Pmode
, first
),
7931 GEN_INT (last
- first
+ 1));
7935 /* Return insn sequence to load the GOT register. */
7937 static GTY(()) rtx got_symbol
;
7939 s390_load_got (void)
7945 got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
7946 SYMBOL_REF_FLAGS (got_symbol
) = SYMBOL_FLAG_LOCAL
;
7951 if (TARGET_CPU_ZARCH
)
7953 emit_move_insn (pic_offset_table_rtx
, got_symbol
);
7959 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, got_symbol
),
7960 UNSPEC_LTREL_OFFSET
);
7961 offset
= gen_rtx_CONST (Pmode
, offset
);
7962 offset
= force_const_mem (Pmode
, offset
);
7964 emit_move_insn (pic_offset_table_rtx
, offset
);
7966 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, XEXP (offset
, 0)),
7968 offset
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, offset
);
7970 emit_move_insn (pic_offset_table_rtx
, offset
);
7973 insns
= get_insns ();
7978 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
7979 and the change to the stack pointer. */
7982 s390_emit_stack_tie (void)
7984 rtx mem
= gen_frame_mem (BLKmode
,
7985 gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
));
7987 emit_insn (gen_stack_tie (mem
));
7990 /* Expand the prologue into a bunch of separate insns. */
7993 s390_emit_prologue (void)
8001 /* Complete frame layout. */
8003 s390_update_frame_layout ();
8005 /* Annotate all constant pool references to let the scheduler know
8006 they implicitly use the base register. */
8008 push_topmost_sequence ();
8010 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8013 annotate_constant_pool_refs (&PATTERN (insn
));
8014 df_insn_rescan (insn
);
8017 pop_topmost_sequence ();
8019 /* Choose best register to use for temp use within prologue.
8020 See below for why TPF must use the register 1. */
8022 if (!has_hard_reg_initial_val (Pmode
, RETURN_REGNUM
)
8023 && !current_function_is_leaf
8024 && !TARGET_TPF_PROFILING
)
8025 temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
8027 temp_reg
= gen_rtx_REG (Pmode
, 1);
8029 /* Save call saved gprs. */
8030 if (cfun_frame_layout
.first_save_gpr
!= -1)
8032 insn
= save_gprs (stack_pointer_rtx
,
8033 cfun_frame_layout
.gprs_offset
+
8034 UNITS_PER_LONG
* (cfun_frame_layout
.first_save_gpr
8035 - cfun_frame_layout
.first_save_gpr_slot
),
8036 cfun_frame_layout
.first_save_gpr
,
8037 cfun_frame_layout
.last_save_gpr
);
8041 /* Dummy insn to mark literal pool slot. */
8043 if (cfun
->machine
->base_reg
)
8044 emit_insn (gen_main_pool (cfun
->machine
->base_reg
));
8046 offset
= cfun_frame_layout
.f0_offset
;
8048 /* Save f0 and f2. */
8049 for (i
= 0; i
< 2; i
++)
8051 if (cfun_fpr_bit_p (i
))
8053 save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
8056 else if (!TARGET_PACKED_STACK
)
8060 /* Save f4 and f6. */
8061 offset
= cfun_frame_layout
.f4_offset
;
8062 for (i
= 2; i
< 4; i
++)
8064 if (cfun_fpr_bit_p (i
))
8066 insn
= save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
8069 /* If f4 and f6 are call clobbered they are saved due to stdargs and
8070 therefore are not frame related. */
8071 if (!call_really_used_regs
[i
+ 16])
8072 RTX_FRAME_RELATED_P (insn
) = 1;
8074 else if (!TARGET_PACKED_STACK
)
8078 if (TARGET_PACKED_STACK
8079 && cfun_save_high_fprs_p
8080 && cfun_frame_layout
.f8_offset
+ cfun_frame_layout
.high_fprs
* 8 > 0)
8082 offset
= (cfun_frame_layout
.f8_offset
8083 + (cfun_frame_layout
.high_fprs
- 1) * 8);
8085 for (i
= 15; i
> 7 && offset
>= 0; i
--)
8086 if (cfun_fpr_bit_p (i
))
8088 insn
= save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
8090 RTX_FRAME_RELATED_P (insn
) = 1;
8093 if (offset
>= cfun_frame_layout
.f8_offset
)
8097 if (!TARGET_PACKED_STACK
)
8098 next_fpr
= cfun_save_high_fprs_p
? 31 : 0;
8100 if (flag_stack_usage
)
8101 current_function_static_stack_size
= cfun_frame_layout
.frame_size
;
8103 /* Decrement stack pointer. */
8105 if (cfun_frame_layout
.frame_size
> 0)
8107 rtx frame_off
= GEN_INT (-cfun_frame_layout
.frame_size
);
8110 if (s390_stack_size
)
8112 HOST_WIDE_INT stack_guard
;
8114 if (s390_stack_guard
)
8115 stack_guard
= s390_stack_guard
;
8118 /* If no value for stack guard is provided the smallest power of 2
8119 larger than the current frame size is chosen. */
8121 while (stack_guard
< cfun_frame_layout
.frame_size
)
8125 if (cfun_frame_layout
.frame_size
>= s390_stack_size
)
8127 warning (0, "frame size of function %qs is %wd"
8128 " bytes exceeding user provided stack limit of "
8130 "An unconditional trap is added.",
8131 current_function_name(), cfun_frame_layout
.frame_size
,
8133 emit_insn (gen_trap ());
8137 /* stack_guard has to be smaller than s390_stack_size.
8138 Otherwise we would emit an AND with zero which would
8139 not match the test under mask pattern. */
8140 if (stack_guard
>= s390_stack_size
)
8142 warning (0, "frame size of function %qs is %wd"
8143 " bytes which is more than half the stack size. "
8144 "The dynamic check would not be reliable. "
8145 "No check emitted for this function.",
8146 current_function_name(),
8147 cfun_frame_layout
.frame_size
);
8151 HOST_WIDE_INT stack_check_mask
= ((s390_stack_size
- 1)
8152 & ~(stack_guard
- 1));
8154 rtx t
= gen_rtx_AND (Pmode
, stack_pointer_rtx
,
8155 GEN_INT (stack_check_mask
));
8157 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode
,
8159 t
, const0_rtx
, const0_rtx
));
8161 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode
,
8163 t
, const0_rtx
, const0_rtx
));
8168 if (s390_warn_framesize
> 0
8169 && cfun_frame_layout
.frame_size
>= s390_warn_framesize
)
8170 warning (0, "frame size of %qs is %wd bytes",
8171 current_function_name (), cfun_frame_layout
.frame_size
);
8173 if (s390_warn_dynamicstack_p
&& cfun
->calls_alloca
)
8174 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
8176 /* Save incoming stack pointer into temp reg. */
8177 if (TARGET_BACKCHAIN
|| next_fpr
)
8178 insn
= emit_insn (gen_move_insn (temp_reg
, stack_pointer_rtx
));
8180 /* Subtract frame size from stack pointer. */
8182 if (DISP_IN_RANGE (INTVAL (frame_off
)))
8184 insn
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8185 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
8187 insn
= emit_insn (insn
);
8191 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
8192 frame_off
= force_const_mem (Pmode
, frame_off
);
8194 insn
= emit_insn (gen_add2_insn (stack_pointer_rtx
, frame_off
));
8195 annotate_constant_pool_refs (&PATTERN (insn
));
8198 RTX_FRAME_RELATED_P (insn
) = 1;
8199 real_frame_off
= GEN_INT (-cfun_frame_layout
.frame_size
);
8200 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
8201 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8202 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
8205 /* Set backchain. */
8207 if (TARGET_BACKCHAIN
)
8209 if (cfun_frame_layout
.backchain_offset
)
8210 addr
= gen_rtx_MEM (Pmode
,
8211 plus_constant (stack_pointer_rtx
,
8212 cfun_frame_layout
.backchain_offset
));
8214 addr
= gen_rtx_MEM (Pmode
, stack_pointer_rtx
);
8215 set_mem_alias_set (addr
, get_frame_alias_set ());
8216 insn
= emit_insn (gen_move_insn (addr
, temp_reg
));
8219 /* If we support non-call exceptions (e.g. for Java),
8220 we need to make sure the backchain pointer is set up
8221 before any possibly trapping memory access. */
8222 if (TARGET_BACKCHAIN
&& cfun
->can_throw_non_call_exceptions
)
8224 addr
= gen_rtx_MEM (BLKmode
, gen_rtx_SCRATCH (VOIDmode
));
8225 emit_clobber (addr
);
8229 /* Save fprs 8 - 15 (64 bit ABI). */
8231 if (cfun_save_high_fprs_p
&& next_fpr
)
8233 /* If the stack might be accessed through a different register
8234 we have to make sure that the stack pointer decrement is not
8235 moved below the use of the stack slots. */
8236 s390_emit_stack_tie ();
8238 insn
= emit_insn (gen_add2_insn (temp_reg
,
8239 GEN_INT (cfun_frame_layout
.f8_offset
)));
8243 for (i
= 24; i
<= next_fpr
; i
++)
8244 if (cfun_fpr_bit_p (i
- 16))
8246 rtx addr
= plus_constant (stack_pointer_rtx
,
8247 cfun_frame_layout
.frame_size
8248 + cfun_frame_layout
.f8_offset
8251 insn
= save_fpr (temp_reg
, offset
, i
);
8253 RTX_FRAME_RELATED_P (insn
) = 1;
8254 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
8255 gen_rtx_SET (VOIDmode
,
8256 gen_rtx_MEM (DFmode
, addr
),
8257 gen_rtx_REG (DFmode
, i
)));
8261 /* Set frame pointer, if needed. */
8263 if (frame_pointer_needed
)
8265 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
8266 RTX_FRAME_RELATED_P (insn
) = 1;
8269 /* Set up got pointer, if needed. */
8271 if (flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
8273 rtx insns
= s390_load_got ();
8275 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
8276 annotate_constant_pool_refs (&PATTERN (insn
));
8281 if (TARGET_TPF_PROFILING
)
8283 /* Generate a BAS instruction to serve as a function
8284 entry intercept to facilitate the use of tracing
8285 algorithms located at the branch target. */
8286 emit_insn (gen_prologue_tpf ());
8288 /* Emit a blockage here so that all code
8289 lies between the profiling mechanisms. */
8290 emit_insn (gen_blockage ());
8294 /* Expand the epilogue into a bunch of separate insns. */
8297 s390_emit_epilogue (bool sibcall
)
8299 rtx frame_pointer
, return_reg
, cfa_restores
= NULL_RTX
;
8300 int area_bottom
, area_top
, offset
= 0;
8305 if (TARGET_TPF_PROFILING
)
8308 /* Generate a BAS instruction to serve as a function
8309 entry intercept to facilitate the use of tracing
8310 algorithms located at the branch target. */
8312 /* Emit a blockage here so that all code
8313 lies between the profiling mechanisms. */
8314 emit_insn (gen_blockage ());
8316 emit_insn (gen_epilogue_tpf ());
8319 /* Check whether to use frame or stack pointer for restore. */
8321 frame_pointer
= (frame_pointer_needed
8322 ? hard_frame_pointer_rtx
: stack_pointer_rtx
);
8324 s390_frame_area (&area_bottom
, &area_top
);
8326 /* Check whether we can access the register save area.
8327 If not, increment the frame pointer as required. */
8329 if (area_top
<= area_bottom
)
8331 /* Nothing to restore. */
8333 else if (DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_bottom
)
8334 && DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_top
- 1))
8336 /* Area is in range. */
8337 offset
= cfun_frame_layout
.frame_size
;
8341 rtx insn
, frame_off
, cfa
;
8343 offset
= area_bottom
< 0 ? -area_bottom
: 0;
8344 frame_off
= GEN_INT (cfun_frame_layout
.frame_size
- offset
);
8346 cfa
= gen_rtx_SET (VOIDmode
, frame_pointer
,
8347 gen_rtx_PLUS (Pmode
, frame_pointer
, frame_off
));
8348 if (DISP_IN_RANGE (INTVAL (frame_off
)))
8350 insn
= gen_rtx_SET (VOIDmode
, frame_pointer
,
8351 gen_rtx_PLUS (Pmode
, frame_pointer
, frame_off
));
8352 insn
= emit_insn (insn
);
8356 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
8357 frame_off
= force_const_mem (Pmode
, frame_off
);
8359 insn
= emit_insn (gen_add2_insn (frame_pointer
, frame_off
));
8360 annotate_constant_pool_refs (&PATTERN (insn
));
8362 add_reg_note (insn
, REG_CFA_ADJUST_CFA
, cfa
);
8363 RTX_FRAME_RELATED_P (insn
) = 1;
8366 /* Restore call saved fprs. */
8370 if (cfun_save_high_fprs_p
)
8372 next_offset
= cfun_frame_layout
.f8_offset
;
8373 for (i
= 24; i
< 32; i
++)
8375 if (cfun_fpr_bit_p (i
- 16))
8377 restore_fpr (frame_pointer
,
8378 offset
+ next_offset
, i
);
8380 = alloc_reg_note (REG_CFA_RESTORE
,
8381 gen_rtx_REG (DFmode
, i
), cfa_restores
);
8390 next_offset
= cfun_frame_layout
.f4_offset
;
8391 for (i
= 18; i
< 20; i
++)
8393 if (cfun_fpr_bit_p (i
- 16))
8395 restore_fpr (frame_pointer
,
8396 offset
+ next_offset
, i
);
8398 = alloc_reg_note (REG_CFA_RESTORE
,
8399 gen_rtx_REG (DFmode
, i
), cfa_restores
);
8402 else if (!TARGET_PACKED_STACK
)
8408 /* Return register. */
8410 return_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
8412 /* Restore call saved gprs. */
8414 if (cfun_frame_layout
.first_restore_gpr
!= -1)
8419 /* Check for global register and save them
8420 to stack location from where they get restored. */
8422 for (i
= cfun_frame_layout
.first_restore_gpr
;
8423 i
<= cfun_frame_layout
.last_restore_gpr
;
8426 if (global_not_special_regno_p (i
))
8428 addr
= plus_constant (frame_pointer
,
8429 offset
+ cfun_frame_layout
.gprs_offset
8430 + (i
- cfun_frame_layout
.first_save_gpr_slot
)
8432 addr
= gen_rtx_MEM (Pmode
, addr
);
8433 set_mem_alias_set (addr
, get_frame_alias_set ());
8434 emit_move_insn (addr
, gen_rtx_REG (Pmode
, i
));
8438 = alloc_reg_note (REG_CFA_RESTORE
,
8439 gen_rtx_REG (Pmode
, i
), cfa_restores
);
8444 /* Fetch return address from stack before load multiple,
8445 this will do good for scheduling. */
8447 if (cfun_frame_layout
.save_return_addr_p
8448 || (cfun_frame_layout
.first_restore_gpr
< BASE_REGNUM
8449 && cfun_frame_layout
.last_restore_gpr
> RETURN_REGNUM
))
8451 int return_regnum
= find_unused_clobbered_reg();
8454 return_reg
= gen_rtx_REG (Pmode
, return_regnum
);
8456 addr
= plus_constant (frame_pointer
,
8457 offset
+ cfun_frame_layout
.gprs_offset
8459 - cfun_frame_layout
.first_save_gpr_slot
)
8461 addr
= gen_rtx_MEM (Pmode
, addr
);
8462 set_mem_alias_set (addr
, get_frame_alias_set ());
8463 emit_move_insn (return_reg
, addr
);
8467 insn
= restore_gprs (frame_pointer
,
8468 offset
+ cfun_frame_layout
.gprs_offset
8469 + (cfun_frame_layout
.first_restore_gpr
8470 - cfun_frame_layout
.first_save_gpr_slot
)
8472 cfun_frame_layout
.first_restore_gpr
,
8473 cfun_frame_layout
.last_restore_gpr
);
8474 insn
= emit_insn (insn
);
8475 REG_NOTES (insn
) = cfa_restores
;
8476 add_reg_note (insn
, REG_CFA_DEF_CFA
,
8477 plus_constant (stack_pointer_rtx
, STACK_POINTER_OFFSET
));
8478 RTX_FRAME_RELATED_P (insn
) = 1;
8484 /* Return to caller. */
8486 p
= rtvec_alloc (2);
8488 RTVEC_ELT (p
, 0) = gen_rtx_RETURN (VOIDmode
);
8489 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
, return_reg
);
8490 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
8495 /* Return the size in bytes of a function argument of
8496 type TYPE and/or mode MODE. At least one of TYPE or
8497 MODE must be specified. */
8500 s390_function_arg_size (enum machine_mode mode
, const_tree type
)
8503 return int_size_in_bytes (type
);
8505 /* No type info available for some library calls ... */
8506 if (mode
!= BLKmode
)
8507 return GET_MODE_SIZE (mode
);
8509 /* If we have neither type nor mode, abort */
8513 /* Return true if a function argument of type TYPE and mode MODE
8514 is to be passed in a floating-point register, if available. */
8517 s390_function_arg_float (enum machine_mode mode
, const_tree type
)
8519 int size
= s390_function_arg_size (mode
, type
);
8523 /* Soft-float changes the ABI: no floating-point registers are used. */
8524 if (TARGET_SOFT_FLOAT
)
8527 /* No type info available for some library calls ... */
8529 return mode
== SFmode
|| mode
== DFmode
|| mode
== SDmode
|| mode
== DDmode
;
8531 /* The ABI says that record types with a single member are treated
8532 just like that member would be. */
8533 while (TREE_CODE (type
) == RECORD_TYPE
)
8535 tree field
, single
= NULL_TREE
;
8537 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
8539 if (TREE_CODE (field
) != FIELD_DECL
)
8542 if (single
== NULL_TREE
)
8543 single
= TREE_TYPE (field
);
8548 if (single
== NULL_TREE
)
8554 return TREE_CODE (type
) == REAL_TYPE
;
8557 /* Return true if a function argument of type TYPE and mode MODE
8558 is to be passed in an integer register, or a pair of integer
8559 registers, if available. */
8562 s390_function_arg_integer (enum machine_mode mode
, const_tree type
)
8564 int size
= s390_function_arg_size (mode
, type
);
8568 /* No type info available for some library calls ... */
8570 return GET_MODE_CLASS (mode
) == MODE_INT
8571 || (TARGET_SOFT_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
));
8573 /* We accept small integral (and similar) types. */
8574 if (INTEGRAL_TYPE_P (type
)
8575 || POINTER_TYPE_P (type
)
8576 || TREE_CODE (type
) == NULLPTR_TYPE
8577 || TREE_CODE (type
) == OFFSET_TYPE
8578 || (TARGET_SOFT_FLOAT
&& TREE_CODE (type
) == REAL_TYPE
))
8581 /* We also accept structs of size 1, 2, 4, 8 that are not
8582 passed in floating-point registers. */
8583 if (AGGREGATE_TYPE_P (type
)
8584 && exact_log2 (size
) >= 0
8585 && !s390_function_arg_float (mode
, type
))
8591 /* Return 1 if a function argument of type TYPE and mode MODE
8592 is to be passed by reference. The ABI specifies that only
8593 structures of size 1, 2, 4, or 8 bytes are passed by value,
8594 all other structures (and complex numbers) are passed by
8598 s390_pass_by_reference (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
,
8599 enum machine_mode mode
, const_tree type
,
8600 bool named ATTRIBUTE_UNUSED
)
8602 int size
= s390_function_arg_size (mode
, type
);
8608 if (AGGREGATE_TYPE_P (type
) && exact_log2 (size
) < 0)
8611 if (TREE_CODE (type
) == COMPLEX_TYPE
8612 || TREE_CODE (type
) == VECTOR_TYPE
)
8619 /* Update the data in CUM to advance over an argument of mode MODE and
8620 data type TYPE. (TYPE is null for libcalls where that information
8621 may not be available.). The boolean NAMED specifies whether the
8622 argument is a named argument (as opposed to an unnamed argument
8623 matching an ellipsis). */
8626 s390_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
8627 const_tree type
, bool named ATTRIBUTE_UNUSED
)
8629 if (s390_function_arg_float (mode
, type
))
8633 else if (s390_function_arg_integer (mode
, type
))
8635 int size
= s390_function_arg_size (mode
, type
);
8636 cum
->gprs
+= ((size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
);
8642 /* Define where to put the arguments to a function.
8643 Value is zero to push the argument on the stack,
8644 or a hard register in which to store the argument.
8646 MODE is the argument's machine mode.
8647 TYPE is the data type of the argument (as a tree).
8648 This is null for libcalls where that information may
8650 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8651 the preceding args and about the function being called.
8652 NAMED is nonzero if this argument is a named parameter
8653 (otherwise it is an extra parameter matching an ellipsis).
8655 On S/390, we use general purpose registers 2 through 6 to
8656 pass integer, pointer, and certain structure arguments, and
8657 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
8658 to pass floating point arguments. All remaining arguments
8659 are pushed to the stack. */
8662 s390_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
8663 const_tree type
, bool named ATTRIBUTE_UNUSED
)
8665 if (s390_function_arg_float (mode
, type
))
8667 if (cum
->fprs
+ 1 > FP_ARG_NUM_REG
)
8670 return gen_rtx_REG (mode
, cum
->fprs
+ 16);
8672 else if (s390_function_arg_integer (mode
, type
))
8674 int size
= s390_function_arg_size (mode
, type
);
8675 int n_gprs
= (size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
;
8677 if (cum
->gprs
+ n_gprs
> GP_ARG_NUM_REG
)
8679 else if (n_gprs
== 1 || UNITS_PER_WORD
== UNITS_PER_LONG
)
8680 return gen_rtx_REG (mode
, cum
->gprs
+ 2);
8681 else if (n_gprs
== 2)
8683 rtvec p
= rtvec_alloc (2);
8686 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, cum
->gprs
+ 2),
8689 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, cum
->gprs
+ 3),
8692 return gen_rtx_PARALLEL (mode
, p
);
8696 /* After the real arguments, expand_call calls us once again
8697 with a void_type_node type. Whatever we return here is
8698 passed as operand 2 to the call expanders.
8700 We don't need this feature ... */
8701 else if (type
== void_type_node
)
8707 /* Return true if return values of type TYPE should be returned
8708 in a memory buffer whose address is passed by the caller as
8709 hidden first argument. */
8712 s390_return_in_memory (const_tree type
, const_tree fundecl ATTRIBUTE_UNUSED
)
8714 /* We accept small integral (and similar) types. */
8715 if (INTEGRAL_TYPE_P (type
)
8716 || POINTER_TYPE_P (type
)
8717 || TREE_CODE (type
) == OFFSET_TYPE
8718 || TREE_CODE (type
) == REAL_TYPE
)
8719 return int_size_in_bytes (type
) > 8;
8721 /* Aggregates and similar constructs are always returned
8723 if (AGGREGATE_TYPE_P (type
)
8724 || TREE_CODE (type
) == COMPLEX_TYPE
8725 || TREE_CODE (type
) == VECTOR_TYPE
)
8728 /* ??? We get called on all sorts of random stuff from
8729 aggregate_value_p. We can't abort, but it's not clear
8730 what's safe to return. Pretend it's a struct I guess. */
8734 /* Function arguments and return values are promoted to word size. */
8736 static enum machine_mode
8737 s390_promote_function_mode (const_tree type
, enum machine_mode mode
,
8739 const_tree fntype ATTRIBUTE_UNUSED
,
8740 int for_return ATTRIBUTE_UNUSED
)
8742 if (INTEGRAL_MODE_P (mode
)
8743 && GET_MODE_SIZE (mode
) < UNITS_PER_LONG
)
8745 if (POINTER_TYPE_P (type
))
8746 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
8753 /* Define where to return a (scalar) value of type RET_TYPE.
8754 If RET_TYPE is null, define where to return a (scalar)
8755 value of mode MODE from a libcall. */
8758 s390_function_and_libcall_value (enum machine_mode mode
,
8759 const_tree ret_type
,
8760 const_tree fntype_or_decl
,
8761 bool outgoing ATTRIBUTE_UNUSED
)
8763 /* For normal functions perform the promotion as
8764 promote_function_mode would do. */
8767 int unsignedp
= TYPE_UNSIGNED (ret_type
);
8768 mode
= promote_function_mode (ret_type
, mode
, &unsignedp
,
8772 gcc_assert (GET_MODE_CLASS (mode
) == MODE_INT
|| SCALAR_FLOAT_MODE_P (mode
));
8773 gcc_assert (GET_MODE_SIZE (mode
) <= 8);
8775 if (TARGET_HARD_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
))
8776 return gen_rtx_REG (mode
, 16);
8777 else if (GET_MODE_SIZE (mode
) <= UNITS_PER_LONG
8778 || UNITS_PER_LONG
== UNITS_PER_WORD
)
8779 return gen_rtx_REG (mode
, 2);
8780 else if (GET_MODE_SIZE (mode
) == 2 * UNITS_PER_LONG
)
8782 /* This case is triggered when returning a 64 bit value with
8783 -m31 -mzarch. Although the value would fit into a single
8784 register it has to be forced into a 32 bit register pair in
8785 order to match the ABI. */
8786 rtvec p
= rtvec_alloc (2);
8789 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, 2), const0_rtx
);
8791 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, 3), GEN_INT (4));
8793 return gen_rtx_PARALLEL (mode
, p
);
8799 /* Define where to return a scalar return value of type RET_TYPE. */
8802 s390_function_value (const_tree ret_type
, const_tree fn_decl_or_type
,
8805 return s390_function_and_libcall_value (TYPE_MODE (ret_type
), ret_type
,
8806 fn_decl_or_type
, outgoing
);
8809 /* Define where to return a scalar libcall return value of mode
8813 s390_libcall_value (enum machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
8815 return s390_function_and_libcall_value (mode
, NULL_TREE
,
8820 /* Create and return the va_list datatype.
8822 On S/390, va_list is an array type equivalent to
8824 typedef struct __va_list_tag
8828 void *__overflow_arg_area;
8829 void *__reg_save_area;
8832 where __gpr and __fpr hold the number of general purpose
8833 or floating point arguments used up to now, respectively,
8834 __overflow_arg_area points to the stack location of the
8835 next argument passed on the stack, and __reg_save_area
8836 always points to the start of the register area in the
8837 call frame of the current function. The function prologue
8838 saves all registers used for argument passing into this
8839 area if the function uses variable arguments. */
8842 s390_build_builtin_va_list (void)
8844 tree f_gpr
, f_fpr
, f_ovf
, f_sav
, record
, type_decl
;
8846 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
8849 build_decl (BUILTINS_LOCATION
,
8850 TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
8852 f_gpr
= build_decl (BUILTINS_LOCATION
,
8853 FIELD_DECL
, get_identifier ("__gpr"),
8854 long_integer_type_node
);
8855 f_fpr
= build_decl (BUILTINS_LOCATION
,
8856 FIELD_DECL
, get_identifier ("__fpr"),
8857 long_integer_type_node
);
8858 f_ovf
= build_decl (BUILTINS_LOCATION
,
8859 FIELD_DECL
, get_identifier ("__overflow_arg_area"),
8861 f_sav
= build_decl (BUILTINS_LOCATION
,
8862 FIELD_DECL
, get_identifier ("__reg_save_area"),
8865 va_list_gpr_counter_field
= f_gpr
;
8866 va_list_fpr_counter_field
= f_fpr
;
8868 DECL_FIELD_CONTEXT (f_gpr
) = record
;
8869 DECL_FIELD_CONTEXT (f_fpr
) = record
;
8870 DECL_FIELD_CONTEXT (f_ovf
) = record
;
8871 DECL_FIELD_CONTEXT (f_sav
) = record
;
8873 TYPE_STUB_DECL (record
) = type_decl
;
8874 TYPE_NAME (record
) = type_decl
;
8875 TYPE_FIELDS (record
) = f_gpr
;
8876 DECL_CHAIN (f_gpr
) = f_fpr
;
8877 DECL_CHAIN (f_fpr
) = f_ovf
;
8878 DECL_CHAIN (f_ovf
) = f_sav
;
8880 layout_type (record
);
8882 /* The correct type is an array type of one element. */
8883 return build_array_type (record
, build_index_type (size_zero_node
));
8886 /* Implement va_start by filling the va_list structure VALIST.
8887 STDARG_P is always true, and ignored.
8888 NEXTARG points to the first anonymous stack argument.
8890 The following global variables are used to initialize
8891 the va_list structure:
8894 holds number of gprs and fprs used for named arguments.
8895 crtl->args.arg_offset_rtx:
8896 holds the offset of the first anonymous stack argument
8897 (relative to the virtual arg pointer). */
8900 s390_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
8902 HOST_WIDE_INT n_gpr
, n_fpr
;
8904 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
8905 tree gpr
, fpr
, ovf
, sav
, t
;
8907 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
8908 f_fpr
= DECL_CHAIN (f_gpr
);
8909 f_ovf
= DECL_CHAIN (f_fpr
);
8910 f_sav
= DECL_CHAIN (f_ovf
);
8912 valist
= build_simple_mem_ref (valist
);
8913 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
8914 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
8915 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
8916 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
8918 /* Count number of gp and fp argument registers used. */
8920 n_gpr
= crtl
->args
.info
.gprs
;
8921 n_fpr
= crtl
->args
.info
.fprs
;
8923 if (cfun
->va_list_gpr_size
)
8925 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
8926 build_int_cst (NULL_TREE
, n_gpr
));
8927 TREE_SIDE_EFFECTS (t
) = 1;
8928 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8931 if (cfun
->va_list_fpr_size
)
8933 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
8934 build_int_cst (NULL_TREE
, n_fpr
));
8935 TREE_SIDE_EFFECTS (t
) = 1;
8936 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8939 /* Find the overflow area. */
8940 if (n_gpr
+ cfun
->va_list_gpr_size
> GP_ARG_NUM_REG
8941 || n_fpr
+ cfun
->va_list_fpr_size
> FP_ARG_NUM_REG
)
8943 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
8945 off
= INTVAL (crtl
->args
.arg_offset_rtx
);
8946 off
= off
< 0 ? 0 : off
;
8947 if (TARGET_DEBUG_ARG
)
8948 fprintf (stderr
, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
8949 (int)n_gpr
, (int)n_fpr
, off
);
8951 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (ovf
), t
, size_int (off
));
8953 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
8954 TREE_SIDE_EFFECTS (t
) = 1;
8955 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8958 /* Find the register save area. */
8959 if ((cfun
->va_list_gpr_size
&& n_gpr
< GP_ARG_NUM_REG
)
8960 || (cfun
->va_list_fpr_size
&& n_fpr
< FP_ARG_NUM_REG
))
8962 t
= make_tree (TREE_TYPE (sav
), return_address_pointer_rtx
);
8963 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (sav
), t
,
8964 size_int (-RETURN_REGNUM
* UNITS_PER_LONG
));
8966 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
8967 TREE_SIDE_EFFECTS (t
) = 1;
8968 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8972 /* Implement va_arg by updating the va_list structure
8973 VALIST as required to retrieve an argument of type
8974 TYPE, and returning that argument.
8976 Generates code equivalent to:
8978 if (integral value) {
8979 if (size <= 4 && args.gpr < 5 ||
8980 size > 4 && args.gpr < 4 )
8981 ret = args.reg_save_area[args.gpr+8]
8983 ret = *args.overflow_arg_area++;
8984 } else if (float value) {
8986 ret = args.reg_save_area[args.fpr+64]
8988 ret = *args.overflow_arg_area++;
8989 } else if (aggregate value) {
8991 ret = *args.reg_save_area[args.gpr]
8993 ret = **args.overflow_arg_area++;
8997 s390_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
8998 gimple_seq
*post_p ATTRIBUTE_UNUSED
)
9000 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
9001 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
9002 int indirect_p
, size
, n_reg
, sav_ofs
, sav_scale
, max_reg
;
9003 tree lab_false
, lab_over
, addr
;
9005 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
9006 f_fpr
= DECL_CHAIN (f_gpr
);
9007 f_ovf
= DECL_CHAIN (f_fpr
);
9008 f_sav
= DECL_CHAIN (f_ovf
);
9010 valist
= build_va_arg_indirect_ref (valist
);
9011 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
9012 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
9013 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
9015 /* The tree for args* cannot be shared between gpr/fpr and ovf since
9016 both appear on a lhs. */
9017 valist
= unshare_expr (valist
);
9018 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
9020 size
= int_size_in_bytes (type
);
9022 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
9024 if (TARGET_DEBUG_ARG
)
9026 fprintf (stderr
, "va_arg: aggregate type");
9030 /* Aggregates are passed by reference. */
9035 /* kernel stack layout on 31 bit: It is assumed here that no padding
9036 will be added by s390_frame_info because for va_args always an even
9037 number of gprs has to be saved r15-r2 = 14 regs. */
9038 sav_ofs
= 2 * UNITS_PER_LONG
;
9039 sav_scale
= UNITS_PER_LONG
;
9040 size
= UNITS_PER_LONG
;
9041 max_reg
= GP_ARG_NUM_REG
- n_reg
;
9043 else if (s390_function_arg_float (TYPE_MODE (type
), type
))
9045 if (TARGET_DEBUG_ARG
)
9047 fprintf (stderr
, "va_arg: float type");
9051 /* FP args go in FP registers, if present. */
9055 sav_ofs
= 16 * UNITS_PER_LONG
;
9057 max_reg
= FP_ARG_NUM_REG
- n_reg
;
9061 if (TARGET_DEBUG_ARG
)
9063 fprintf (stderr
, "va_arg: other type");
9067 /* Otherwise into GP registers. */
9070 n_reg
= (size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
;
9072 /* kernel stack layout on 31 bit: It is assumed here that no padding
9073 will be added by s390_frame_info because for va_args always an even
9074 number of gprs has to be saved r15-r2 = 14 regs. */
9075 sav_ofs
= 2 * UNITS_PER_LONG
;
9077 if (size
< UNITS_PER_LONG
)
9078 sav_ofs
+= UNITS_PER_LONG
- size
;
9080 sav_scale
= UNITS_PER_LONG
;
9081 max_reg
= GP_ARG_NUM_REG
- n_reg
;
9084 /* Pull the value out of the saved registers ... */
9086 lab_false
= create_artificial_label (UNKNOWN_LOCATION
);
9087 lab_over
= create_artificial_label (UNKNOWN_LOCATION
);
9088 addr
= create_tmp_var (ptr_type_node
, "addr");
9090 t
= fold_convert (TREE_TYPE (reg
), size_int (max_reg
));
9091 t
= build2 (GT_EXPR
, boolean_type_node
, reg
, t
);
9092 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
9093 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
9094 gimplify_and_add (t
, pre_p
);
9096 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, sav
,
9097 size_int (sav_ofs
));
9098 u
= build2 (MULT_EXPR
, TREE_TYPE (reg
), reg
,
9099 fold_convert (TREE_TYPE (reg
), size_int (sav_scale
)));
9100 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, t
, fold_convert (sizetype
, u
));
9102 gimplify_assign (addr
, t
, pre_p
);
9104 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
9106 gimple_seq_add_stmt (pre_p
, gimple_build_label (lab_false
));
9109 /* ... Otherwise out of the overflow area. */
9112 if (size
< UNITS_PER_LONG
)
9113 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, t
,
9114 size_int (UNITS_PER_LONG
- size
));
9116 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
9118 gimplify_assign (addr
, t
, pre_p
);
9120 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, t
,
9122 gimplify_assign (ovf
, t
, pre_p
);
9124 gimple_seq_add_stmt (pre_p
, gimple_build_label (lab_over
));
9127 /* Increment register save count. */
9129 u
= build2 (PREINCREMENT_EXPR
, TREE_TYPE (reg
), reg
,
9130 fold_convert (TREE_TYPE (reg
), size_int (n_reg
)));
9131 gimplify_and_add (u
, pre_p
);
9135 t
= build_pointer_type_for_mode (build_pointer_type (type
),
9137 addr
= fold_convert (t
, addr
);
9138 addr
= build_va_arg_indirect_ref (addr
);
9142 t
= build_pointer_type_for_mode (type
, ptr_mode
, true);
9143 addr
= fold_convert (t
, addr
);
9146 return build_va_arg_indirect_ref (addr
);
9154 S390_BUILTIN_THREAD_POINTER
,
9155 S390_BUILTIN_SET_THREAD_POINTER
,
9160 static enum insn_code
const code_for_builtin_64
[S390_BUILTIN_max
] = {
9165 static enum insn_code
const code_for_builtin_31
[S390_BUILTIN_max
] = {
9171 s390_init_builtins (void)
9175 ftype
= build_function_type (ptr_type_node
, void_list_node
);
9176 add_builtin_function ("__builtin_thread_pointer", ftype
,
9177 S390_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
9180 ftype
= build_function_type_list (void_type_node
, ptr_type_node
, NULL_TREE
);
9181 add_builtin_function ("__builtin_set_thread_pointer", ftype
,
9182 S390_BUILTIN_SET_THREAD_POINTER
, BUILT_IN_MD
,
9186 /* Expand an expression EXP that calls a built-in function,
9187 with result going to TARGET if that's convenient
9188 (and in mode MODE if that's convenient).
9189 SUBTARGET may be used as the target for computing one of EXP's operands.
9190 IGNORE is nonzero if the value is to be ignored. */
9193 s390_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
9194 enum machine_mode mode ATTRIBUTE_UNUSED
,
9195 int ignore ATTRIBUTE_UNUSED
)
9199 enum insn_code
const *code_for_builtin
=
9200 TARGET_64BIT
? code_for_builtin_64
: code_for_builtin_31
;
9202 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
9203 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
9204 enum insn_code icode
;
9205 rtx op
[MAX_ARGS
], pat
;
9209 call_expr_arg_iterator iter
;
9211 if (fcode
>= S390_BUILTIN_max
)
9212 internal_error ("bad builtin fcode");
9213 icode
= code_for_builtin
[fcode
];
9215 internal_error ("bad builtin fcode");
9217 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
9220 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
9222 const struct insn_operand_data
*insn_op
;
9224 if (arg
== error_mark_node
)
9226 if (arity
> MAX_ARGS
)
9229 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
9231 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, EXPAND_NORMAL
);
9233 if (!(*insn_op
->predicate
) (op
[arity
], insn_op
->mode
))
9234 op
[arity
] = copy_to_mode_reg (insn_op
->mode
, op
[arity
]);
9240 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
9242 || GET_MODE (target
) != tmode
9243 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
9244 target
= gen_reg_rtx (tmode
);
9250 pat
= GEN_FCN (icode
) (target
);
9254 pat
= GEN_FCN (icode
) (target
, op
[0]);
9256 pat
= GEN_FCN (icode
) (op
[0]);
9259 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
9275 /* Output assembly code for the trampoline template to
9278 On S/390, we use gpr 1 internally in the trampoline code;
9279 gpr 0 is used to hold the static chain. */
9282 s390_asm_trampoline_template (FILE *file
)
9285 op
[0] = gen_rtx_REG (Pmode
, 0);
9286 op
[1] = gen_rtx_REG (Pmode
, 1);
9290 output_asm_insn ("basr\t%1,0", op
);
9291 output_asm_insn ("lmg\t%0,%1,14(%1)", op
);
9292 output_asm_insn ("br\t%1", op
);
9293 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 10));
9297 output_asm_insn ("basr\t%1,0", op
);
9298 output_asm_insn ("lm\t%0,%1,6(%1)", op
);
9299 output_asm_insn ("br\t%1", op
);
9300 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 8));
9304 /* Emit RTL insns to initialize the variable parts of a trampoline.
9305 FNADDR is an RTX for the address of the function's pure code.
9306 CXT is an RTX for the static chain value for the function. */
9309 s390_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
9311 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
9314 emit_block_move (m_tramp
, assemble_trampoline_template (),
9315 GEN_INT (2*UNITS_PER_WORD
), BLOCK_OP_NORMAL
);
9317 mem
= adjust_address (m_tramp
, Pmode
, 2*UNITS_PER_WORD
);
9318 emit_move_insn (mem
, cxt
);
9319 mem
= adjust_address (m_tramp
, Pmode
, 3*UNITS_PER_WORD
);
9320 emit_move_insn (mem
, fnaddr
);
9323 /* Output assembler code to FILE to increment profiler label # LABELNO
9324 for profiling a function entry. */
9327 s390_function_profiler (FILE *file
, int labelno
)
9332 ASM_GENERATE_INTERNAL_LABEL (label
, "LP", labelno
);
9334 fprintf (file
, "# function profiler \n");
9336 op
[0] = gen_rtx_REG (Pmode
, RETURN_REGNUM
);
9337 op
[1] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
9338 op
[1] = gen_rtx_MEM (Pmode
, plus_constant (op
[1], UNITS_PER_LONG
));
9340 op
[2] = gen_rtx_REG (Pmode
, 1);
9341 op
[3] = gen_rtx_SYMBOL_REF (Pmode
, label
);
9342 SYMBOL_REF_FLAGS (op
[3]) = SYMBOL_FLAG_LOCAL
;
9344 op
[4] = gen_rtx_SYMBOL_REF (Pmode
, "_mcount");
9347 op
[4] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[4]), UNSPEC_PLT
);
9348 op
[4] = gen_rtx_CONST (Pmode
, op
[4]);
9353 output_asm_insn ("stg\t%0,%1", op
);
9354 output_asm_insn ("larl\t%2,%3", op
);
9355 output_asm_insn ("brasl\t%0,%4", op
);
9356 output_asm_insn ("lg\t%0,%1", op
);
9360 op
[6] = gen_label_rtx ();
9362 output_asm_insn ("st\t%0,%1", op
);
9363 output_asm_insn ("bras\t%2,%l6", op
);
9364 output_asm_insn (".long\t%4", op
);
9365 output_asm_insn (".long\t%3", op
);
9366 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
9367 output_asm_insn ("l\t%0,0(%2)", op
);
9368 output_asm_insn ("l\t%2,4(%2)", op
);
9369 output_asm_insn ("basr\t%0,%0", op
);
9370 output_asm_insn ("l\t%0,%1", op
);
9374 op
[5] = gen_label_rtx ();
9375 op
[6] = gen_label_rtx ();
9377 output_asm_insn ("st\t%0,%1", op
);
9378 output_asm_insn ("bras\t%2,%l6", op
);
9379 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[5]));
9380 output_asm_insn (".long\t%4-%l5", op
);
9381 output_asm_insn (".long\t%3-%l5", op
);
9382 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
9383 output_asm_insn ("lr\t%0,%2", op
);
9384 output_asm_insn ("a\t%0,0(%2)", op
);
9385 output_asm_insn ("a\t%2,4(%2)", op
);
9386 output_asm_insn ("basr\t%0,%0", op
);
9387 output_asm_insn ("l\t%0,%1", op
);
9391 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
9392 into its SYMBOL_REF_FLAGS. */
9395 s390_encode_section_info (tree decl
, rtx rtl
, int first
)
9397 default_encode_section_info (decl
, rtl
, first
);
9399 if (TREE_CODE (decl
) == VAR_DECL
)
9401 /* If a variable has a forced alignment to < 2 bytes, mark it
9402 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
9404 if (DECL_USER_ALIGN (decl
) && DECL_ALIGN (decl
) < 16)
9405 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_ALIGN1
;
9406 if (!DECL_SIZE (decl
)
9407 || !DECL_ALIGN (decl
)
9408 || !host_integerp (DECL_SIZE (decl
), 0)
9409 || (DECL_ALIGN (decl
) <= 64
9410 && DECL_ALIGN (decl
) != tree_low_cst (DECL_SIZE (decl
), 0)))
9411 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED
;
9414 /* Literal pool references don't have a decl so they are handled
9415 differently here. We rely on the information in the MEM_ALIGN
9416 entry to decide upon natural alignment. */
9418 && GET_CODE (XEXP (rtl
, 0)) == SYMBOL_REF
9419 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl
, 0))
9420 && (MEM_ALIGN (rtl
) == 0
9421 || GET_MODE_BITSIZE (GET_MODE (rtl
)) == 0
9422 || MEM_ALIGN (rtl
) < GET_MODE_BITSIZE (GET_MODE (rtl
))))
9423 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED
;
9426 /* Output thunk to FILE that implements a C++ virtual function call (with
9427 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
9428 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
9429 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
9430 relative to the resulting this pointer. */
9433 s390_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
9434 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
9440 /* Make sure unwind info is emitted for the thunk if needed. */
9441 final_start_function (emit_barrier (), file
, 1);
9443 /* Operand 0 is the target function. */
9444 op
[0] = XEXP (DECL_RTL (function
), 0);
9445 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (op
[0]))
9448 op
[0] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[0]),
9449 TARGET_64BIT
? UNSPEC_PLT
: UNSPEC_GOT
);
9450 op
[0] = gen_rtx_CONST (Pmode
, op
[0]);
9453 /* Operand 1 is the 'this' pointer. */
9454 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
9455 op
[1] = gen_rtx_REG (Pmode
, 3);
9457 op
[1] = gen_rtx_REG (Pmode
, 2);
9459 /* Operand 2 is the delta. */
9460 op
[2] = GEN_INT (delta
);
9462 /* Operand 3 is the vcall_offset. */
9463 op
[3] = GEN_INT (vcall_offset
);
9465 /* Operand 4 is the temporary register. */
9466 op
[4] = gen_rtx_REG (Pmode
, 1);
9468 /* Operands 5 to 8 can be used as labels. */
9474 /* Operand 9 can be used for temporary register. */
9477 /* Generate code. */
9480 /* Setup literal pool pointer if required. */
9481 if ((!DISP_IN_RANGE (delta
)
9482 && !CONST_OK_FOR_K (delta
)
9483 && !CONST_OK_FOR_Os (delta
))
9484 || (!DISP_IN_RANGE (vcall_offset
)
9485 && !CONST_OK_FOR_K (vcall_offset
)
9486 && !CONST_OK_FOR_Os (vcall_offset
)))
9488 op
[5] = gen_label_rtx ();
9489 output_asm_insn ("larl\t%4,%5", op
);
9492 /* Add DELTA to this pointer. */
9495 if (CONST_OK_FOR_J (delta
))
9496 output_asm_insn ("la\t%1,%2(%1)", op
);
9497 else if (DISP_IN_RANGE (delta
))
9498 output_asm_insn ("lay\t%1,%2(%1)", op
);
9499 else if (CONST_OK_FOR_K (delta
))
9500 output_asm_insn ("aghi\t%1,%2", op
);
9501 else if (CONST_OK_FOR_Os (delta
))
9502 output_asm_insn ("agfi\t%1,%2", op
);
9505 op
[6] = gen_label_rtx ();
9506 output_asm_insn ("agf\t%1,%6-%5(%4)", op
);
9510 /* Perform vcall adjustment. */
9513 if (DISP_IN_RANGE (vcall_offset
))
9515 output_asm_insn ("lg\t%4,0(%1)", op
);
9516 output_asm_insn ("ag\t%1,%3(%4)", op
);
9518 else if (CONST_OK_FOR_K (vcall_offset
))
9520 output_asm_insn ("lghi\t%4,%3", op
);
9521 output_asm_insn ("ag\t%4,0(%1)", op
);
9522 output_asm_insn ("ag\t%1,0(%4)", op
);
9524 else if (CONST_OK_FOR_Os (vcall_offset
))
9526 output_asm_insn ("lgfi\t%4,%3", op
);
9527 output_asm_insn ("ag\t%4,0(%1)", op
);
9528 output_asm_insn ("ag\t%1,0(%4)", op
);
9532 op
[7] = gen_label_rtx ();
9533 output_asm_insn ("llgf\t%4,%7-%5(%4)", op
);
9534 output_asm_insn ("ag\t%4,0(%1)", op
);
9535 output_asm_insn ("ag\t%1,0(%4)", op
);
9539 /* Jump to target. */
9540 output_asm_insn ("jg\t%0", op
);
9542 /* Output literal pool if required. */
9545 output_asm_insn (".align\t4", op
);
9546 targetm
.asm_out
.internal_label (file
, "L",
9547 CODE_LABEL_NUMBER (op
[5]));
9551 targetm
.asm_out
.internal_label (file
, "L",
9552 CODE_LABEL_NUMBER (op
[6]));
9553 output_asm_insn (".long\t%2", op
);
9557 targetm
.asm_out
.internal_label (file
, "L",
9558 CODE_LABEL_NUMBER (op
[7]));
9559 output_asm_insn (".long\t%3", op
);
9564 /* Setup base pointer if required. */
9566 || (!DISP_IN_RANGE (delta
)
9567 && !CONST_OK_FOR_K (delta
)
9568 && !CONST_OK_FOR_Os (delta
))
9569 || (!DISP_IN_RANGE (delta
)
9570 && !CONST_OK_FOR_K (vcall_offset
)
9571 && !CONST_OK_FOR_Os (vcall_offset
)))
9573 op
[5] = gen_label_rtx ();
9574 output_asm_insn ("basr\t%4,0", op
);
9575 targetm
.asm_out
.internal_label (file
, "L",
9576 CODE_LABEL_NUMBER (op
[5]));
9579 /* Add DELTA to this pointer. */
9582 if (CONST_OK_FOR_J (delta
))
9583 output_asm_insn ("la\t%1,%2(%1)", op
);
9584 else if (DISP_IN_RANGE (delta
))
9585 output_asm_insn ("lay\t%1,%2(%1)", op
);
9586 else if (CONST_OK_FOR_K (delta
))
9587 output_asm_insn ("ahi\t%1,%2", op
);
9588 else if (CONST_OK_FOR_Os (delta
))
9589 output_asm_insn ("afi\t%1,%2", op
);
9592 op
[6] = gen_label_rtx ();
9593 output_asm_insn ("a\t%1,%6-%5(%4)", op
);
9597 /* Perform vcall adjustment. */
9600 if (CONST_OK_FOR_J (vcall_offset
))
9602 output_asm_insn ("l\t%4,0(%1)", op
);
9603 output_asm_insn ("a\t%1,%3(%4)", op
);
9605 else if (DISP_IN_RANGE (vcall_offset
))
9607 output_asm_insn ("l\t%4,0(%1)", op
);
9608 output_asm_insn ("ay\t%1,%3(%4)", op
);
9610 else if (CONST_OK_FOR_K (vcall_offset
))
9612 output_asm_insn ("lhi\t%4,%3", op
);
9613 output_asm_insn ("a\t%4,0(%1)", op
);
9614 output_asm_insn ("a\t%1,0(%4)", op
);
9616 else if (CONST_OK_FOR_Os (vcall_offset
))
9618 output_asm_insn ("iilf\t%4,%3", op
);
9619 output_asm_insn ("a\t%4,0(%1)", op
);
9620 output_asm_insn ("a\t%1,0(%4)", op
);
9624 op
[7] = gen_label_rtx ();
9625 output_asm_insn ("l\t%4,%7-%5(%4)", op
);
9626 output_asm_insn ("a\t%4,0(%1)", op
);
9627 output_asm_insn ("a\t%1,0(%4)", op
);
9630 /* We had to clobber the base pointer register.
9631 Re-setup the base pointer (with a different base). */
9632 op
[5] = gen_label_rtx ();
9633 output_asm_insn ("basr\t%4,0", op
);
9634 targetm
.asm_out
.internal_label (file
, "L",
9635 CODE_LABEL_NUMBER (op
[5]));
9638 /* Jump to target. */
9639 op
[8] = gen_label_rtx ();
9642 output_asm_insn ("l\t%4,%8-%5(%4)", op
);
9644 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
9645 /* We cannot call through .plt, since .plt requires %r12 loaded. */
9646 else if (flag_pic
== 1)
9648 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
9649 output_asm_insn ("l\t%4,%0(%4)", op
);
9651 else if (flag_pic
== 2)
9653 op
[9] = gen_rtx_REG (Pmode
, 0);
9654 output_asm_insn ("l\t%9,%8-4-%5(%4)", op
);
9655 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
9656 output_asm_insn ("ar\t%4,%9", op
);
9657 output_asm_insn ("l\t%4,0(%4)", op
);
9660 output_asm_insn ("br\t%4", op
);
9662 /* Output literal pool. */
9663 output_asm_insn (".align\t4", op
);
9665 if (nonlocal
&& flag_pic
== 2)
9666 output_asm_insn (".long\t%0", op
);
9669 op
[0] = gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
9670 SYMBOL_REF_FLAGS (op
[0]) = SYMBOL_FLAG_LOCAL
;
9673 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[8]));
9675 output_asm_insn (".long\t%0", op
);
9677 output_asm_insn (".long\t%0-%5", op
);
9681 targetm
.asm_out
.internal_label (file
, "L",
9682 CODE_LABEL_NUMBER (op
[6]));
9683 output_asm_insn (".long\t%2", op
);
9687 targetm
.asm_out
.internal_label (file
, "L",
9688 CODE_LABEL_NUMBER (op
[7]));
9689 output_asm_insn (".long\t%3", op
);
9692 final_end_function ();
9696 s390_valid_pointer_mode (enum machine_mode mode
)
9698 return (mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
));
9701 /* Checks whether the given CALL_EXPR would use a caller
9702 saved register. This is used to decide whether sibling call
9703 optimization could be performed on the respective function
9707 s390_call_saved_register_used (tree call_expr
)
9709 CUMULATIVE_ARGS cum
;
9711 enum machine_mode mode
;
9716 INIT_CUMULATIVE_ARGS (cum
, NULL
, NULL
, 0, 0);
9718 for (i
= 0; i
< call_expr_nargs (call_expr
); i
++)
9720 parameter
= CALL_EXPR_ARG (call_expr
, i
);
9721 gcc_assert (parameter
);
9723 /* For an undeclared variable passed as parameter we will get
9724 an ERROR_MARK node here. */
9725 if (TREE_CODE (parameter
) == ERROR_MARK
)
9728 type
= TREE_TYPE (parameter
);
9731 mode
= TYPE_MODE (type
);
9734 if (pass_by_reference (&cum
, mode
, type
, true))
9737 type
= build_pointer_type (type
);
9740 parm_rtx
= s390_function_arg (&cum
, mode
, type
, 0);
9742 s390_function_arg_advance (&cum
, mode
, type
, 0);
9747 if (REG_P (parm_rtx
))
9750 reg
< HARD_REGNO_NREGS (REGNO (parm_rtx
), GET_MODE (parm_rtx
));
9752 if (!call_used_regs
[reg
+ REGNO (parm_rtx
)])
9756 if (GET_CODE (parm_rtx
) == PARALLEL
)
9760 for (i
= 0; i
< XVECLEN (parm_rtx
, 0); i
++)
9762 rtx r
= XEXP (XVECEXP (parm_rtx
, 0, i
), 0);
9764 gcc_assert (REG_P (r
));
9767 reg
< HARD_REGNO_NREGS (REGNO (r
), GET_MODE (r
));
9769 if (!call_used_regs
[reg
+ REGNO (r
)])
9778 /* Return true if the given call expression can be
9779 turned into a sibling call.
9780 DECL holds the declaration of the function to be called whereas
9781 EXP is the call expression itself. */
9784 s390_function_ok_for_sibcall (tree decl
, tree exp
)
9786 /* The TPF epilogue uses register 1. */
9787 if (TARGET_TPF_PROFILING
)
9790 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
9791 which would have to be restored before the sibcall. */
9792 if (!TARGET_64BIT
&& flag_pic
&& decl
&& !targetm
.binds_local_p (decl
))
9795 /* Register 6 on s390 is available as an argument register but unfortunately
9796 "caller saved". This makes functions needing this register for arguments
9797 not suitable for sibcalls. */
9798 return !s390_call_saved_register_used (exp
);
9801 /* Return the fixed registers used for condition codes. */
9804 s390_fixed_condition_code_regs (unsigned int *p1
, unsigned int *p2
)
9807 *p2
= INVALID_REGNUM
;
9812 /* This function is used by the call expanders of the machine description.
9813 It emits the call insn itself together with the necessary operations
9814 to adjust the target address and returns the emitted insn.
9815 ADDR_LOCATION is the target address rtx
9816 TLS_CALL the location of the thread-local symbol
9817 RESULT_REG the register where the result of the call should be stored
9818 RETADDR_REG the register where the return address should be stored
9819 If this parameter is NULL_RTX the call is considered
9820 to be a sibling call. */
9823 s390_emit_call (rtx addr_location
, rtx tls_call
, rtx result_reg
,
9826 bool plt_call
= false;
9832 /* Direct function calls need special treatment. */
9833 if (GET_CODE (addr_location
) == SYMBOL_REF
)
9835 /* When calling a global routine in PIC mode, we must
9836 replace the symbol itself with the PLT stub. */
9837 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (addr_location
))
9839 if (retaddr_reg
!= NULL_RTX
)
9841 addr_location
= gen_rtx_UNSPEC (Pmode
,
9842 gen_rtvec (1, addr_location
),
9844 addr_location
= gen_rtx_CONST (Pmode
, addr_location
);
9848 /* For -fpic code the PLT entries might use r12 which is
9849 call-saved. Therefore we cannot do a sibcall when
9850 calling directly using a symbol ref. When reaching
9851 this point we decided (in s390_function_ok_for_sibcall)
9852 to do a sibcall for a function pointer but one of the
9853 optimizers was able to get rid of the function pointer
9854 by propagating the symbol ref into the call. This
9855 optimization is illegal for S/390 so we turn the direct
9856 call into a indirect call again. */
9857 addr_location
= force_reg (Pmode
, addr_location
);
9860 /* Unless we can use the bras(l) insn, force the
9861 routine address into a register. */
9862 if (!TARGET_SMALL_EXEC
&& !TARGET_CPU_ZARCH
)
9865 addr_location
= legitimize_pic_address (addr_location
, 0);
9867 addr_location
= force_reg (Pmode
, addr_location
);
9871 /* If it is already an indirect call or the code above moved the
9872 SYMBOL_REF to somewhere else make sure the address can be found in
9874 if (retaddr_reg
== NULL_RTX
9875 && GET_CODE (addr_location
) != SYMBOL_REF
9878 emit_move_insn (gen_rtx_REG (Pmode
, SIBCALL_REGNUM
), addr_location
);
9879 addr_location
= gen_rtx_REG (Pmode
, SIBCALL_REGNUM
);
9882 addr_location
= gen_rtx_MEM (QImode
, addr_location
);
9883 call
= gen_rtx_CALL (VOIDmode
, addr_location
, const0_rtx
);
9885 if (result_reg
!= NULL_RTX
)
9886 call
= gen_rtx_SET (VOIDmode
, result_reg
, call
);
9888 if (retaddr_reg
!= NULL_RTX
)
9890 clobber
= gen_rtx_CLOBBER (VOIDmode
, retaddr_reg
);
9892 if (tls_call
!= NULL_RTX
)
9893 vec
= gen_rtvec (3, call
, clobber
,
9894 gen_rtx_USE (VOIDmode
, tls_call
));
9896 vec
= gen_rtvec (2, call
, clobber
);
9898 call
= gen_rtx_PARALLEL (VOIDmode
, vec
);
9901 insn
= emit_call_insn (call
);
9903 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
9904 if ((!TARGET_64BIT
&& plt_call
) || tls_call
!= NULL_RTX
)
9906 /* s390_function_ok_for_sibcall should
9907 have denied sibcalls in this case. */
9908 gcc_assert (retaddr_reg
!= NULL_RTX
);
9910 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
9915 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
9918 s390_conditional_register_usage (void)
9924 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
9925 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
9927 if (TARGET_CPU_ZARCH
)
9929 fixed_regs
[BASE_REGNUM
] = 0;
9930 call_used_regs
[BASE_REGNUM
] = 0;
9931 fixed_regs
[RETURN_REGNUM
] = 0;
9932 call_used_regs
[RETURN_REGNUM
] = 0;
9936 for (i
= 24; i
< 32; i
++)
9937 call_used_regs
[i
] = call_really_used_regs
[i
] = 0;
9941 for (i
= 18; i
< 20; i
++)
9942 call_used_regs
[i
] = call_really_used_regs
[i
] = 0;
9945 if (TARGET_SOFT_FLOAT
)
9947 for (i
= 16; i
< 32; i
++)
9948 call_used_regs
[i
] = fixed_regs
[i
] = 1;
9952 /* Corresponding function to eh_return expander. */
9954 static GTY(()) rtx s390_tpf_eh_return_symbol
;
9956 s390_emit_tpf_eh_return (rtx target
)
9960 if (!s390_tpf_eh_return_symbol
)
9961 s390_tpf_eh_return_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tpf_eh_return");
9963 reg
= gen_rtx_REG (Pmode
, 2);
9965 emit_move_insn (reg
, target
);
9966 insn
= s390_emit_call (s390_tpf_eh_return_symbol
, NULL_RTX
, reg
,
9967 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
9968 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
9970 emit_move_insn (EH_RETURN_HANDLER_RTX
, reg
);
9973 /* Rework the prologue/epilogue to avoid saving/restoring
9974 registers unnecessarily. */
9977 s390_optimize_prologue (void)
9979 rtx insn
, new_insn
, next_insn
;
9981 /* Do a final recompute of the frame-related data. */
9983 s390_update_frame_layout ();
9985 /* If all special registers are in fact used, there's nothing we
9986 can do, so no point in walking the insn list. */
9988 if (cfun_frame_layout
.first_save_gpr
<= BASE_REGNUM
9989 && cfun_frame_layout
.last_save_gpr
>= BASE_REGNUM
9990 && (TARGET_CPU_ZARCH
9991 || (cfun_frame_layout
.first_save_gpr
<= RETURN_REGNUM
9992 && cfun_frame_layout
.last_save_gpr
>= RETURN_REGNUM
)))
9995 /* Search for prologue/epilogue insns and replace them. */
9997 for (insn
= get_insns (); insn
; insn
= next_insn
)
9999 int first
, last
, off
;
10000 rtx set
, base
, offset
;
10002 next_insn
= NEXT_INSN (insn
);
10004 if (GET_CODE (insn
) != INSN
)
10007 if (GET_CODE (PATTERN (insn
)) == PARALLEL
10008 && store_multiple_operation (PATTERN (insn
), VOIDmode
))
10010 set
= XVECEXP (PATTERN (insn
), 0, 0);
10011 first
= REGNO (SET_SRC (set
));
10012 last
= first
+ XVECLEN (PATTERN (insn
), 0) - 1;
10013 offset
= const0_rtx
;
10014 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
10015 off
= INTVAL (offset
);
10017 if (GET_CODE (base
) != REG
|| off
< 0)
10019 if (cfun_frame_layout
.first_save_gpr
!= -1
10020 && (cfun_frame_layout
.first_save_gpr
< first
10021 || cfun_frame_layout
.last_save_gpr
> last
))
10023 if (REGNO (base
) != STACK_POINTER_REGNUM
10024 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
10026 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
10029 if (cfun_frame_layout
.first_save_gpr
!= -1)
10031 new_insn
= save_gprs (base
,
10032 off
+ (cfun_frame_layout
.first_save_gpr
10033 - first
) * UNITS_PER_LONG
,
10034 cfun_frame_layout
.first_save_gpr
,
10035 cfun_frame_layout
.last_save_gpr
);
10036 new_insn
= emit_insn_before (new_insn
, insn
);
10037 INSN_ADDRESSES_NEW (new_insn
, -1);
10040 remove_insn (insn
);
10044 if (cfun_frame_layout
.first_save_gpr
== -1
10045 && GET_CODE (PATTERN (insn
)) == SET
10046 && GET_CODE (SET_SRC (PATTERN (insn
))) == REG
10047 && (REGNO (SET_SRC (PATTERN (insn
))) == BASE_REGNUM
10048 || (!TARGET_CPU_ZARCH
10049 && REGNO (SET_SRC (PATTERN (insn
))) == RETURN_REGNUM
))
10050 && GET_CODE (SET_DEST (PATTERN (insn
))) == MEM
)
10052 set
= PATTERN (insn
);
10053 first
= REGNO (SET_SRC (set
));
10054 offset
= const0_rtx
;
10055 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
10056 off
= INTVAL (offset
);
10058 if (GET_CODE (base
) != REG
|| off
< 0)
10060 if (REGNO (base
) != STACK_POINTER_REGNUM
10061 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
10064 remove_insn (insn
);
10068 if (GET_CODE (PATTERN (insn
)) == PARALLEL
10069 && load_multiple_operation (PATTERN (insn
), VOIDmode
))
10071 set
= XVECEXP (PATTERN (insn
), 0, 0);
10072 first
= REGNO (SET_DEST (set
));
10073 last
= first
+ XVECLEN (PATTERN (insn
), 0) - 1;
10074 offset
= const0_rtx
;
10075 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
10076 off
= INTVAL (offset
);
10078 if (GET_CODE (base
) != REG
|| off
< 0)
10080 if (cfun_frame_layout
.first_restore_gpr
!= -1
10081 && (cfun_frame_layout
.first_restore_gpr
< first
10082 || cfun_frame_layout
.last_restore_gpr
> last
))
10084 if (REGNO (base
) != STACK_POINTER_REGNUM
10085 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
10087 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
10090 if (cfun_frame_layout
.first_restore_gpr
!= -1)
10092 new_insn
= restore_gprs (base
,
10093 off
+ (cfun_frame_layout
.first_restore_gpr
10094 - first
) * UNITS_PER_LONG
,
10095 cfun_frame_layout
.first_restore_gpr
,
10096 cfun_frame_layout
.last_restore_gpr
);
10097 new_insn
= emit_insn_before (new_insn
, insn
);
10098 INSN_ADDRESSES_NEW (new_insn
, -1);
10101 remove_insn (insn
);
10105 if (cfun_frame_layout
.first_restore_gpr
== -1
10106 && GET_CODE (PATTERN (insn
)) == SET
10107 && GET_CODE (SET_DEST (PATTERN (insn
))) == REG
10108 && (REGNO (SET_DEST (PATTERN (insn
))) == BASE_REGNUM
10109 || (!TARGET_CPU_ZARCH
10110 && REGNO (SET_DEST (PATTERN (insn
))) == RETURN_REGNUM
))
10111 && GET_CODE (SET_SRC (PATTERN (insn
))) == MEM
)
10113 set
= PATTERN (insn
);
10114 first
= REGNO (SET_DEST (set
));
10115 offset
= const0_rtx
;
10116 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
10117 off
= INTVAL (offset
);
10119 if (GET_CODE (base
) != REG
|| off
< 0)
10121 if (REGNO (base
) != STACK_POINTER_REGNUM
10122 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
10125 remove_insn (insn
);
10131 /* On z10 and later the dynamic branch prediction must see the
10132 backward jump within a certain windows. If not it falls back to
10133 the static prediction. This function rearranges the loop backward
10134 branch in a way which makes the static prediction always correct.
10135 The function returns true if it added an instruction. */
10137 s390_fix_long_loop_prediction (rtx insn
)
10139 rtx set
= single_set (insn
);
10140 rtx code_label
, label_ref
, new_label
;
10146 /* This will exclude branch on count and branch on index patterns
10147 since these are correctly statically predicted. */
10149 || SET_DEST (set
) != pc_rtx
10150 || GET_CODE (SET_SRC(set
)) != IF_THEN_ELSE
)
10153 label_ref
= (GET_CODE (XEXP (SET_SRC (set
), 1)) == LABEL_REF
?
10154 XEXP (SET_SRC (set
), 1) : XEXP (SET_SRC (set
), 2));
10156 gcc_assert (GET_CODE (label_ref
) == LABEL_REF
);
10158 code_label
= XEXP (label_ref
, 0);
10160 if (INSN_ADDRESSES (INSN_UID (code_label
)) == -1
10161 || INSN_ADDRESSES (INSN_UID (insn
)) == -1
10162 || (INSN_ADDRESSES (INSN_UID (insn
))
10163 - INSN_ADDRESSES (INSN_UID (code_label
)) < PREDICT_DISTANCE
))
10166 for (distance
= 0, cur_insn
= PREV_INSN (insn
);
10167 distance
< PREDICT_DISTANCE
- 6;
10168 distance
+= get_attr_length (cur_insn
), cur_insn
= PREV_INSN (cur_insn
))
10169 if (!cur_insn
|| JUMP_P (cur_insn
) || LABEL_P (cur_insn
))
10172 new_label
= gen_label_rtx ();
10173 uncond_jump
= emit_jump_insn_after (
10174 gen_rtx_SET (VOIDmode
, pc_rtx
,
10175 gen_rtx_LABEL_REF (VOIDmode
, code_label
)),
10177 emit_label_after (new_label
, uncond_jump
);
10179 tmp
= XEXP (SET_SRC (set
), 1);
10180 XEXP (SET_SRC (set
), 1) = XEXP (SET_SRC (set
), 2);
10181 XEXP (SET_SRC (set
), 2) = tmp
;
10182 INSN_CODE (insn
) = -1;
10184 XEXP (label_ref
, 0) = new_label
;
10185 JUMP_LABEL (insn
) = new_label
;
10186 JUMP_LABEL (uncond_jump
) = code_label
;
10191 /* Returns 1 if INSN reads the value of REG for purposes not related
10192 to addressing of memory, and 0 otherwise. */
10194 s390_non_addr_reg_read_p (rtx reg
, rtx insn
)
10196 return reg_referenced_p (reg
, PATTERN (insn
))
10197 && !reg_used_in_mem_p (REGNO (reg
), PATTERN (insn
));
10200 /* Starting from INSN find_cond_jump looks downwards in the insn
10201 stream for a single jump insn which is the last user of the
10202 condition code set in INSN. */
10204 find_cond_jump (rtx insn
)
10206 for (; insn
; insn
= NEXT_INSN (insn
))
10210 if (LABEL_P (insn
))
10213 if (!JUMP_P (insn
))
10215 if (reg_mentioned_p (gen_rtx_REG (CCmode
, CC_REGNUM
), insn
))
10220 /* This will be triggered by a return. */
10221 if (GET_CODE (PATTERN (insn
)) != SET
)
10224 gcc_assert (SET_DEST (PATTERN (insn
)) == pc_rtx
);
10225 ite
= SET_SRC (PATTERN (insn
));
10227 if (GET_CODE (ite
) != IF_THEN_ELSE
)
10230 cc
= XEXP (XEXP (ite
, 0), 0);
10231 if (!REG_P (cc
) || !CC_REGNO_P (REGNO (cc
)))
10234 if (find_reg_note (insn
, REG_DEAD
, cc
))
10242 /* Swap the condition in COND and the operands in OP0 and OP1 so that
10243 the semantics does not change. If NULL_RTX is passed as COND the
10244 function tries to find the conditional jump starting with INSN. */
10246 s390_swap_cmp (rtx cond
, rtx
*op0
, rtx
*op1
, rtx insn
)
10250 if (cond
== NULL_RTX
)
10252 rtx jump
= find_cond_jump (NEXT_INSN (insn
));
10253 jump
= jump
? single_set (jump
) : NULL_RTX
;
10255 if (jump
== NULL_RTX
)
10258 cond
= XEXP (XEXP (jump
, 1), 0);
10263 PUT_CODE (cond
, swap_condition (GET_CODE (cond
)));
10266 /* On z10, instructions of the compare-and-branch family have the
10267 property to access the register occurring as second operand with
10268 its bits complemented. If such a compare is grouped with a second
10269 instruction that accesses the same register non-complemented, and
10270 if that register's value is delivered via a bypass, then the
10271 pipeline recycles, thereby causing significant performance decline.
10272 This function locates such situations and exchanges the two
10273 operands of the compare. The function return true whenever it
10276 s390_z10_optimize_cmp (rtx insn
)
10278 rtx prev_insn
, next_insn
;
10279 bool insn_added_p
= false;
10280 rtx cond
, *op0
, *op1
;
10282 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
10284 /* Handle compare and branch and branch on count
10286 rtx pattern
= single_set (insn
);
10289 || SET_DEST (pattern
) != pc_rtx
10290 || GET_CODE (SET_SRC (pattern
)) != IF_THEN_ELSE
)
10293 cond
= XEXP (SET_SRC (pattern
), 0);
10294 op0
= &XEXP (cond
, 0);
10295 op1
= &XEXP (cond
, 1);
10297 else if (GET_CODE (PATTERN (insn
)) == SET
)
10301 /* Handle normal compare instructions. */
10302 src
= SET_SRC (PATTERN (insn
));
10303 dest
= SET_DEST (PATTERN (insn
));
10306 || !CC_REGNO_P (REGNO (dest
))
10307 || GET_CODE (src
) != COMPARE
)
10310 /* s390_swap_cmp will try to find the conditional
10311 jump when passing NULL_RTX as condition. */
10313 op0
= &XEXP (src
, 0);
10314 op1
= &XEXP (src
, 1);
10319 if (!REG_P (*op0
) || !REG_P (*op1
))
10322 if (GET_MODE_CLASS (GET_MODE (*op0
)) != MODE_INT
)
10325 /* Swap the COMPARE arguments and its mask if there is a
10326 conflicting access in the previous insn. */
10327 prev_insn
= prev_active_insn (insn
);
10328 if (prev_insn
!= NULL_RTX
&& INSN_P (prev_insn
)
10329 && reg_referenced_p (*op1
, PATTERN (prev_insn
)))
10330 s390_swap_cmp (cond
, op0
, op1
, insn
);
10332 /* Check if there is a conflict with the next insn. If there
10333 was no conflict with the previous insn, then swap the
10334 COMPARE arguments and its mask. If we already swapped
10335 the operands, or if swapping them would cause a conflict
10336 with the previous insn, issue a NOP after the COMPARE in
10337 order to separate the two instuctions. */
10338 next_insn
= next_active_insn (insn
);
10339 if (next_insn
!= NULL_RTX
&& INSN_P (next_insn
)
10340 && s390_non_addr_reg_read_p (*op1
, next_insn
))
10342 if (prev_insn
!= NULL_RTX
&& INSN_P (prev_insn
)
10343 && s390_non_addr_reg_read_p (*op0
, prev_insn
))
10345 if (REGNO (*op1
) == 0)
10346 emit_insn_after (gen_nop1 (), insn
);
10348 emit_insn_after (gen_nop (), insn
);
10349 insn_added_p
= true;
10352 s390_swap_cmp (cond
, op0
, op1
, insn
);
10354 return insn_added_p
;
10357 /* Perform machine-dependent processing. */
10362 bool pool_overflow
= false;
10364 /* Make sure all splits have been performed; splits after
10365 machine_dependent_reorg might confuse insn length counts. */
10366 split_all_insns_noflow ();
10368 /* Install the main literal pool and the associated base
10369 register load insns.
10371 In addition, there are two problematic situations we need
10374 - the literal pool might be > 4096 bytes in size, so that
10375 some of its elements cannot be directly accessed
10377 - a branch target might be > 64K away from the branch, so that
10378 it is not possible to use a PC-relative instruction.
10380 To fix those, we split the single literal pool into multiple
10381 pool chunks, reloading the pool base register at various
10382 points throughout the function to ensure it always points to
10383 the pool chunk the following code expects, and / or replace
10384 PC-relative branches by absolute branches.
10386 However, the two problems are interdependent: splitting the
10387 literal pool can move a branch further away from its target,
10388 causing the 64K limit to overflow, and on the other hand,
10389 replacing a PC-relative branch by an absolute branch means
10390 we need to put the branch target address into the literal
10391 pool, possibly causing it to overflow.
10393 So, we loop trying to fix up both problems until we manage
10394 to satisfy both conditions at the same time. Note that the
10395 loop is guaranteed to terminate as every pass of the loop
10396 strictly decreases the total number of PC-relative branches
10397 in the function. (This is not completely true as there
10398 might be branch-over-pool insns introduced by chunkify_start.
10399 Those never need to be split however.) */
10403 struct constant_pool
*pool
= NULL
;
10405 /* Collect the literal pool. */
10406 if (!pool_overflow
)
10408 pool
= s390_mainpool_start ();
10410 pool_overflow
= true;
10413 /* If literal pool overflowed, start to chunkify it. */
10415 pool
= s390_chunkify_start ();
10417 /* Split out-of-range branches. If this has created new
10418 literal pool entries, cancel current chunk list and
10419 recompute it. zSeries machines have large branch
10420 instructions, so we never need to split a branch. */
10421 if (!TARGET_CPU_ZARCH
&& s390_split_branches ())
10424 s390_chunkify_cancel (pool
);
10426 s390_mainpool_cancel (pool
);
10431 /* If we made it up to here, both conditions are satisfied.
10432 Finish up literal pool related changes. */
10434 s390_chunkify_finish (pool
);
10436 s390_mainpool_finish (pool
);
10438 /* We're done splitting branches. */
10439 cfun
->machine
->split_branches_pending_p
= false;
10443 /* Generate out-of-pool execute target insns. */
10444 if (TARGET_CPU_ZARCH
)
10446 rtx insn
, label
, target
;
10448 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10450 label
= s390_execute_label (insn
);
10454 gcc_assert (label
!= const0_rtx
);
10456 target
= emit_label (XEXP (label
, 0));
10457 INSN_ADDRESSES_NEW (target
, -1);
10459 target
= emit_insn (s390_execute_target (insn
));
10460 INSN_ADDRESSES_NEW (target
, -1);
10464 /* Try to optimize prologue and epilogue further. */
10465 s390_optimize_prologue ();
10467 /* Walk over the insns and do some >=z10 specific changes. */
10468 if (s390_tune
== PROCESSOR_2097_Z10
10469 || s390_tune
== PROCESSOR_2817_Z196
)
10472 bool insn_added_p
= false;
10474 /* The insn lengths and addresses have to be up to date for the
10475 following manipulations. */
10476 shorten_branches (get_insns ());
10478 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10480 if (!INSN_P (insn
) || INSN_CODE (insn
) <= 0)
10484 insn_added_p
|= s390_fix_long_loop_prediction (insn
);
10486 if ((GET_CODE (PATTERN (insn
)) == PARALLEL
10487 || GET_CODE (PATTERN (insn
)) == SET
)
10488 && s390_tune
== PROCESSOR_2097_Z10
)
10489 insn_added_p
|= s390_z10_optimize_cmp (insn
);
10492 /* Adjust branches if we added new instructions. */
10494 shorten_branches (get_insns ());
10498 /* Return true if INSN is a fp load insn writing register REGNO. */
10500 s390_fpload_toreg (rtx insn
, unsigned int regno
)
10503 enum attr_type flag
= s390_safe_attr_type (insn
);
10505 if (flag
!= TYPE_FLOADSF
&& flag
!= TYPE_FLOADDF
)
10508 set
= single_set (insn
);
10510 if (set
== NULL_RTX
)
10513 if (!REG_P (SET_DEST (set
)) || !MEM_P (SET_SRC (set
)))
10516 if (REGNO (SET_DEST (set
)) != regno
)
10522 /* This value describes the distance to be avoided between an
10523 aritmetic fp instruction and an fp load writing the same register.
10524 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
10525 fine but the exact value has to be avoided. Otherwise the FP
10526 pipeline will throw an exception causing a major penalty. */
10527 #define Z10_EARLYLOAD_DISTANCE 7
10529 /* Rearrange the ready list in order to avoid the situation described
10530 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
10531 moved to the very end of the ready list. */
10533 s390_z10_prevent_earlyload_conflicts (rtx
*ready
, int *nready_p
)
10535 unsigned int regno
;
10536 int nready
= *nready_p
;
10541 enum attr_type flag
;
10544 /* Skip DISTANCE - 1 active insns. */
10545 for (insn
= last_scheduled_insn
, distance
= Z10_EARLYLOAD_DISTANCE
- 1;
10546 distance
> 0 && insn
!= NULL_RTX
;
10547 distance
--, insn
= prev_active_insn (insn
))
10548 if (CALL_P (insn
) || JUMP_P (insn
))
10551 if (insn
== NULL_RTX
)
10554 set
= single_set (insn
);
10556 if (set
== NULL_RTX
|| !REG_P (SET_DEST (set
))
10557 || GET_MODE_CLASS (GET_MODE (SET_DEST (set
))) != MODE_FLOAT
)
10560 flag
= s390_safe_attr_type (insn
);
10562 if (flag
== TYPE_FLOADSF
|| flag
== TYPE_FLOADDF
)
10565 regno
= REGNO (SET_DEST (set
));
10568 while (!s390_fpload_toreg (ready
[i
], regno
) && i
> 0)
10575 memmove (&ready
[1], &ready
[0], sizeof (rtx
) * i
);
10579 /* This function is called via hook TARGET_SCHED_REORDER before
10580 issueing one insn from list READY which contains *NREADYP entries.
10581 For target z10 it reorders load instructions to avoid early load
10582 conflicts in the floating point pipeline */
10584 s390_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
10585 rtx
*ready
, int *nreadyp
, int clock ATTRIBUTE_UNUSED
)
10587 if (s390_tune
== PROCESSOR_2097_Z10
)
10588 if (reload_completed
&& *nreadyp
> 1)
10589 s390_z10_prevent_earlyload_conflicts (ready
, nreadyp
);
10591 return s390_issue_rate ();
10594 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
10595 the scheduler has issued INSN. It stores the last issued insn into
10596 last_scheduled_insn in order to make it available for
10597 s390_sched_reorder. */
10599 s390_sched_variable_issue (FILE *file ATTRIBUTE_UNUSED
,
10600 int verbose ATTRIBUTE_UNUSED
,
10601 rtx insn
, int more
)
10603 last_scheduled_insn
= insn
;
10605 if (GET_CODE (PATTERN (insn
)) != USE
10606 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
10613 s390_sched_init (FILE *file ATTRIBUTE_UNUSED
,
10614 int verbose ATTRIBUTE_UNUSED
,
10615 int max_ready ATTRIBUTE_UNUSED
)
10617 last_scheduled_insn
= NULL_RTX
;
10620 /* This function checks the whole of insn X for memory references. The
10621 function always returns zero because the framework it is called
10622 from would stop recursively analyzing the insn upon a return value
10623 other than zero. The real result of this function is updating
10624 counter variable MEM_COUNT. */
10626 check_dpu (rtx
*x
, unsigned *mem_count
)
10628 if (*x
!= NULL_RTX
&& MEM_P (*x
))
10633 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
10634 a new number struct loop *loop should be unrolled if tuned for cpus with
10635 a built-in stride prefetcher.
10636 The loop is analyzed for memory accesses by calling check_dpu for
10637 each rtx of the loop. Depending on the loop_depth and the amount of
10638 memory accesses a new number <=nunroll is returned to improve the
10639 behaviour of the hardware prefetch unit. */
10641 s390_loop_unroll_adjust (unsigned nunroll
, struct loop
*loop
)
10646 unsigned mem_count
= 0;
10648 if (s390_tune
!= PROCESSOR_2097_Z10
&& s390_tune
!= PROCESSOR_2817_Z196
)
10651 /* Count the number of memory references within the loop body. */
10652 bbs
= get_loop_body (loop
);
10653 for (i
= 0; i
< loop
->num_nodes
; i
++)
10655 for (insn
= BB_HEAD (bbs
[i
]); insn
!= BB_END (bbs
[i
]); insn
= NEXT_INSN (insn
))
10656 if (INSN_P (insn
) && INSN_CODE (insn
) != -1)
10657 for_each_rtx (&insn
, (rtx_function
) check_dpu
, &mem_count
);
10661 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
10662 if (mem_count
== 0)
10665 switch (loop_depth(loop
))
10668 return MIN (nunroll
, 28 / mem_count
);
10670 return MIN (nunroll
, 22 / mem_count
);
10672 return MIN (nunroll
, 16 / mem_count
);
10676 /* Initialize GCC target structure. */
10678 #undef TARGET_ASM_ALIGNED_HI_OP
10679 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10680 #undef TARGET_ASM_ALIGNED_DI_OP
10681 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10682 #undef TARGET_ASM_INTEGER
10683 #define TARGET_ASM_INTEGER s390_assemble_integer
10685 #undef TARGET_ASM_OPEN_PAREN
10686 #define TARGET_ASM_OPEN_PAREN ""
10688 #undef TARGET_ASM_CLOSE_PAREN
10689 #define TARGET_ASM_CLOSE_PAREN ""
10691 #undef TARGET_DEFAULT_TARGET_FLAGS
10692 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT)
10694 #undef TARGET_HANDLE_OPTION
10695 #define TARGET_HANDLE_OPTION s390_handle_option
10697 #undef TARGET_OPTION_OVERRIDE
10698 #define TARGET_OPTION_OVERRIDE s390_option_override
10700 #undef TARGET_OPTION_OPTIMIZATION_TABLE
10701 #define TARGET_OPTION_OPTIMIZATION_TABLE s390_option_optimization_table
10703 #undef TARGET_OPTION_INIT_STRUCT
10704 #define TARGET_OPTION_INIT_STRUCT s390_option_init_struct
10706 #undef TARGET_ENCODE_SECTION_INFO
10707 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
10709 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10710 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10713 #undef TARGET_HAVE_TLS
10714 #define TARGET_HAVE_TLS true
10716 #undef TARGET_CANNOT_FORCE_CONST_MEM
10717 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
10719 #undef TARGET_DELEGITIMIZE_ADDRESS
10720 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
10722 #undef TARGET_LEGITIMIZE_ADDRESS
10723 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
10725 #undef TARGET_RETURN_IN_MEMORY
10726 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
10728 #undef TARGET_INIT_BUILTINS
10729 #define TARGET_INIT_BUILTINS s390_init_builtins
10730 #undef TARGET_EXPAND_BUILTIN
10731 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
10733 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
10734 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA s390_output_addr_const_extra
10736 #undef TARGET_ASM_OUTPUT_MI_THUNK
10737 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
10738 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10739 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
10741 #undef TARGET_SCHED_ADJUST_PRIORITY
10742 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
10743 #undef TARGET_SCHED_ISSUE_RATE
10744 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
10745 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10746 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
10748 #undef TARGET_SCHED_VARIABLE_ISSUE
10749 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
10750 #undef TARGET_SCHED_REORDER
10751 #define TARGET_SCHED_REORDER s390_sched_reorder
10752 #undef TARGET_SCHED_INIT
10753 #define TARGET_SCHED_INIT s390_sched_init
10755 #undef TARGET_CANNOT_COPY_INSN_P
10756 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
10757 #undef TARGET_RTX_COSTS
10758 #define TARGET_RTX_COSTS s390_rtx_costs
10759 #undef TARGET_ADDRESS_COST
10760 #define TARGET_ADDRESS_COST s390_address_cost
10761 #undef TARGET_REGISTER_MOVE_COST
10762 #define TARGET_REGISTER_MOVE_COST s390_register_move_cost
10763 #undef TARGET_MEMORY_MOVE_COST
10764 #define TARGET_MEMORY_MOVE_COST s390_memory_move_cost
10766 #undef TARGET_MACHINE_DEPENDENT_REORG
10767 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
10769 #undef TARGET_VALID_POINTER_MODE
10770 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
10772 #undef TARGET_BUILD_BUILTIN_VA_LIST
10773 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
10774 #undef TARGET_EXPAND_BUILTIN_VA_START
10775 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
10776 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
10777 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
10779 #undef TARGET_PROMOTE_FUNCTION_MODE
10780 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
10781 #undef TARGET_PASS_BY_REFERENCE
10782 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
10784 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10785 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
10786 #undef TARGET_FUNCTION_ARG
10787 #define TARGET_FUNCTION_ARG s390_function_arg
10788 #undef TARGET_FUNCTION_ARG_ADVANCE
10789 #define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance
10790 #undef TARGET_FUNCTION_VALUE
10791 #define TARGET_FUNCTION_VALUE s390_function_value
10792 #undef TARGET_LIBCALL_VALUE
10793 #define TARGET_LIBCALL_VALUE s390_libcall_value
10795 #undef TARGET_FIXED_CONDITION_CODE_REGS
10796 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
10798 #undef TARGET_CC_MODES_COMPATIBLE
10799 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
10801 #undef TARGET_INVALID_WITHIN_DOLOOP
10802 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
10805 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
10806 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
10809 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10810 #undef TARGET_MANGLE_TYPE
10811 #define TARGET_MANGLE_TYPE s390_mangle_type
10814 #undef TARGET_SCALAR_MODE_SUPPORTED_P
10815 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
10817 #undef TARGET_PREFERRED_RELOAD_CLASS
10818 #define TARGET_PREFERRED_RELOAD_CLASS s390_preferred_reload_class
10820 #undef TARGET_SECONDARY_RELOAD
10821 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
10823 #undef TARGET_LIBGCC_CMP_RETURN_MODE
10824 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
10826 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
10827 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
10829 #undef TARGET_LEGITIMATE_ADDRESS_P
10830 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
10832 #undef TARGET_CAN_ELIMINATE
10833 #define TARGET_CAN_ELIMINATE s390_can_eliminate
10835 #undef TARGET_CONDITIONAL_REGISTER_USAGE
10836 #define TARGET_CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage
10838 #undef TARGET_LOOP_UNROLL_ADJUST
10839 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
10841 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
10842 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
10843 #undef TARGET_TRAMPOLINE_INIT
10844 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
10846 #undef TARGET_UNWIND_WORD_MODE
10847 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
10849 struct gcc_target targetm
= TARGET_INITIALIZER
;
10851 #include "gt-s390.h"