1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 2, or (at your option) any later
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the Free
21 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
26 #include "coretypes.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
45 #include "basic-block.h"
46 #include "integrate.h"
49 #include "target-def.h"
51 #include "langhooks.h"
53 #include "tree-gimple.h"
57 /* Define the specific costs for a given cpu. */
59 struct processor_costs
62 const int m
; /* cost of an M instruction. */
63 const int mghi
; /* cost of an MGHI instruction. */
64 const int mh
; /* cost of an MH instruction. */
65 const int mhi
; /* cost of an MHI instruction. */
66 const int ml
; /* cost of an ML instruction. */
67 const int mr
; /* cost of an MR instruction. */
68 const int ms
; /* cost of an MS instruction. */
69 const int msg
; /* cost of an MSG instruction. */
70 const int msgf
; /* cost of an MSGF instruction. */
71 const int msgfr
; /* cost of an MSGFR instruction. */
72 const int msgr
; /* cost of an MSGR instruction. */
73 const int msr
; /* cost of an MSR instruction. */
74 const int mult_df
; /* cost of multiplication in DFmode. */
77 const int sqxbr
; /* cost of square root in TFmode. */
78 const int sqdbr
; /* cost of square root in DFmode. */
79 const int sqebr
; /* cost of square root in SFmode. */
80 /* multiply and add */
81 const int madbr
; /* cost of multiply and add in DFmode. */
82 const int maebr
; /* cost of multiply and add in SFmode. */
94 const struct processor_costs
*s390_cost
;
97 struct processor_costs z900_cost
=
99 COSTS_N_INSNS (5), /* M */
100 COSTS_N_INSNS (10), /* MGHI */
101 COSTS_N_INSNS (5), /* MH */
102 COSTS_N_INSNS (4), /* MHI */
103 COSTS_N_INSNS (5), /* ML */
104 COSTS_N_INSNS (5), /* MR */
105 COSTS_N_INSNS (4), /* MS */
106 COSTS_N_INSNS (15), /* MSG */
107 COSTS_N_INSNS (7), /* MSGF */
108 COSTS_N_INSNS (7), /* MSGFR */
109 COSTS_N_INSNS (10), /* MSGR */
110 COSTS_N_INSNS (4), /* MSR */
111 COSTS_N_INSNS (7), /* multiplication in DFmode */
112 COSTS_N_INSNS (13), /* MXBR */
113 COSTS_N_INSNS (136), /* SQXBR */
114 COSTS_N_INSNS (44), /* SQDBR */
115 COSTS_N_INSNS (35), /* SQEBR */
116 COSTS_N_INSNS (18), /* MADBR */
117 COSTS_N_INSNS (13), /* MAEBR */
118 COSTS_N_INSNS (134), /* DXBR */
119 COSTS_N_INSNS (30), /* DDBR */
120 COSTS_N_INSNS (27), /* DEBR */
121 COSTS_N_INSNS (220), /* DLGR */
122 COSTS_N_INSNS (34), /* DLR */
123 COSTS_N_INSNS (34), /* DR */
124 COSTS_N_INSNS (32), /* DSGFR */
125 COSTS_N_INSNS (32), /* DSGR */
129 struct processor_costs z990_cost
=
131 COSTS_N_INSNS (4), /* M */
132 COSTS_N_INSNS (2), /* MGHI */
133 COSTS_N_INSNS (2), /* MH */
134 COSTS_N_INSNS (2), /* MHI */
135 COSTS_N_INSNS (4), /* ML */
136 COSTS_N_INSNS (4), /* MR */
137 COSTS_N_INSNS (5), /* MS */
138 COSTS_N_INSNS (6), /* MSG */
139 COSTS_N_INSNS (4), /* MSGF */
140 COSTS_N_INSNS (4), /* MSGFR */
141 COSTS_N_INSNS (4), /* MSGR */
142 COSTS_N_INSNS (4), /* MSR */
143 COSTS_N_INSNS (1), /* multiplication in DFmode */
144 COSTS_N_INSNS (28), /* MXBR */
145 COSTS_N_INSNS (130), /* SQXBR */
146 COSTS_N_INSNS (66), /* SQDBR */
147 COSTS_N_INSNS (38), /* SQEBR */
148 COSTS_N_INSNS (1), /* MADBR */
149 COSTS_N_INSNS (1), /* MAEBR */
150 COSTS_N_INSNS (60), /* DXBR */
151 COSTS_N_INSNS (40), /* DDBR */
152 COSTS_N_INSNS (26), /* DEBR */
153 COSTS_N_INSNS (176), /* DLGR */
154 COSTS_N_INSNS (31), /* DLR */
155 COSTS_N_INSNS (31), /* DR */
156 COSTS_N_INSNS (31), /* DSGFR */
157 COSTS_N_INSNS (31), /* DSGR */
161 struct processor_costs z9_109_cost
=
163 COSTS_N_INSNS (4), /* M */
164 COSTS_N_INSNS (2), /* MGHI */
165 COSTS_N_INSNS (2), /* MH */
166 COSTS_N_INSNS (2), /* MHI */
167 COSTS_N_INSNS (4), /* ML */
168 COSTS_N_INSNS (4), /* MR */
169 COSTS_N_INSNS (5), /* MS */
170 COSTS_N_INSNS (6), /* MSG */
171 COSTS_N_INSNS (4), /* MSGF */
172 COSTS_N_INSNS (4), /* MSGFR */
173 COSTS_N_INSNS (4), /* MSGR */
174 COSTS_N_INSNS (4), /* MSR */
175 COSTS_N_INSNS (1), /* multiplication in DFmode */
176 COSTS_N_INSNS (28), /* MXBR */
177 COSTS_N_INSNS (130), /* SQXBR */
178 COSTS_N_INSNS (66), /* SQDBR */
179 COSTS_N_INSNS (38), /* SQEBR */
180 COSTS_N_INSNS (1), /* MADBR */
181 COSTS_N_INSNS (1), /* MAEBR */
182 COSTS_N_INSNS (60), /* DXBR */
183 COSTS_N_INSNS (40), /* DDBR */
184 COSTS_N_INSNS (26), /* DEBR */
185 COSTS_N_INSNS (30), /* DLGR */
186 COSTS_N_INSNS (23), /* DLR */
187 COSTS_N_INSNS (23), /* DR */
188 COSTS_N_INSNS (24), /* DSGFR */
189 COSTS_N_INSNS (24), /* DSGR */
192 extern int reload_completed
;
194 /* Save information from a "cmpxx" operation until the branch or scc is
196 rtx s390_compare_op0
, s390_compare_op1
;
198 /* Save the result of a compare_and_swap until the branch or scc is
200 rtx s390_compare_emitted
= NULL_RTX
;
202 /* Structure used to hold the components of a S/390 memory
203 address. A legitimate address on S/390 is of the general
205 base + index + displacement
206 where any of the components is optional.
208 base and index are registers of the class ADDR_REGS,
209 displacement is an unsigned 12-bit immediate constant. */
220 /* Which cpu are we tuning for. */
221 enum processor_type s390_tune
= PROCESSOR_max
;
222 enum processor_flags s390_tune_flags
;
223 /* Which instruction set architecture to use. */
224 enum processor_type s390_arch
;
225 enum processor_flags s390_arch_flags
;
227 HOST_WIDE_INT s390_warn_framesize
= 0;
228 HOST_WIDE_INT s390_stack_size
= 0;
229 HOST_WIDE_INT s390_stack_guard
= 0;
231 /* The following structure is embedded in the machine
232 specific part of struct function. */
234 struct s390_frame_layout
GTY (())
236 /* Offset within stack frame. */
237 HOST_WIDE_INT gprs_offset
;
238 HOST_WIDE_INT f0_offset
;
239 HOST_WIDE_INT f4_offset
;
240 HOST_WIDE_INT f8_offset
;
241 HOST_WIDE_INT backchain_offset
;
243 /* Number of first and last gpr where slots in the register
244 save area are reserved for. */
245 int first_save_gpr_slot
;
246 int last_save_gpr_slot
;
248 /* Number of first and last gpr to be saved, restored. */
250 int first_restore_gpr
;
252 int last_restore_gpr
;
254 /* Bits standing for floating point registers. Set, if the
255 respective register has to be saved. Starting with reg 16 (f0)
256 at the rightmost bit.
257 Bit 15 - 8 7 6 5 4 3 2 1 0
258 fpr 15 - 8 7 5 3 1 6 4 2 0
259 reg 31 - 24 23 22 21 20 19 18 17 16 */
260 unsigned int fpr_bitmap
;
262 /* Number of floating point registers f8-f15 which must be saved. */
265 /* Set if return address needs to be saved.
266 This flag is set by s390_return_addr_rtx if it could not use
267 the initial value of r14 and therefore depends on r14 saved
269 bool save_return_addr_p
;
271 /* Size of stack frame. */
272 HOST_WIDE_INT frame_size
;
275 /* Define the structure for the machine field in struct function. */
277 struct machine_function
GTY(())
279 struct s390_frame_layout frame_layout
;
281 /* Literal pool base register. */
284 /* True if we may need to perform branch splitting. */
285 bool split_branches_pending_p
;
287 /* True during final stage of literal pool processing. */
288 bool decomposed_literal_pool_addresses_ok_p
;
290 /* Some local-dynamic TLS symbol name. */
291 const char *some_ld_name
;
293 bool has_landing_pad_p
;
296 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
298 #define cfun_frame_layout (cfun->machine->frame_layout)
299 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
300 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
301 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_WORD)
302 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
304 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
307 /* Number of GPRs and FPRs used for argument passing. */
308 #define GP_ARG_NUM_REG 5
309 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
311 /* A couple of shortcuts. */
312 #define CONST_OK_FOR_J(x) \
313 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
314 #define CONST_OK_FOR_K(x) \
315 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
316 #define CONST_OK_FOR_Os(x) \
317 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
318 #define CONST_OK_FOR_Op(x) \
319 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
320 #define CONST_OK_FOR_On(x) \
321 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
323 #define REGNO_PAIR_OK(REGNO, MODE) \
324 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
326 /* Return true if the back end supports mode MODE. */
328 s390_scalar_mode_supported_p (enum machine_mode mode
)
330 if (DECIMAL_FLOAT_MODE_P (mode
))
333 return default_scalar_mode_supported_p (mode
);
336 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
339 s390_set_has_landing_pad_p (bool value
)
341 cfun
->machine
->has_landing_pad_p
= value
;
344 /* If two condition code modes are compatible, return a condition code
345 mode which is compatible with both. Otherwise, return
348 static enum machine_mode
349 s390_cc_modes_compatible (enum machine_mode m1
, enum machine_mode m2
)
357 if (m2
== CCUmode
|| m2
== CCTmode
|| m2
== CCZ1mode
358 || m2
== CCSmode
|| m2
== CCSRmode
|| m2
== CCURmode
)
379 /* Return true if SET either doesn't set the CC register, or else
380 the source and destination have matching CC modes and that
381 CC mode is at least as constrained as REQ_MODE. */
384 s390_match_ccmode_set (rtx set
, enum machine_mode req_mode
)
386 enum machine_mode set_mode
;
388 gcc_assert (GET_CODE (set
) == SET
);
390 if (GET_CODE (SET_DEST (set
)) != REG
|| !CC_REGNO_P (REGNO (SET_DEST (set
))))
393 set_mode
= GET_MODE (SET_DEST (set
));
407 if (req_mode
!= set_mode
)
412 if (req_mode
!= CCSmode
&& req_mode
!= CCUmode
&& req_mode
!= CCTmode
413 && req_mode
!= CCSRmode
&& req_mode
!= CCURmode
)
419 if (req_mode
!= CCAmode
)
427 return (GET_MODE (SET_SRC (set
)) == set_mode
);
430 /* Return true if every SET in INSN that sets the CC register
431 has source and destination with matching CC modes and that
432 CC mode is at least as constrained as REQ_MODE.
433 If REQ_MODE is VOIDmode, always return false. */
436 s390_match_ccmode (rtx insn
, enum machine_mode req_mode
)
440 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
441 if (req_mode
== VOIDmode
)
444 if (GET_CODE (PATTERN (insn
)) == SET
)
445 return s390_match_ccmode_set (PATTERN (insn
), req_mode
);
447 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
448 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
450 rtx set
= XVECEXP (PATTERN (insn
), 0, i
);
451 if (GET_CODE (set
) == SET
)
452 if (!s390_match_ccmode_set (set
, req_mode
))
459 /* If a test-under-mask instruction can be used to implement
460 (compare (and ... OP1) OP2), return the CC mode required
461 to do that. Otherwise, return VOIDmode.
462 MIXED is true if the instruction can distinguish between
463 CC1 and CC2 for mixed selected bits (TMxx), it is false
464 if the instruction cannot (TM). */
467 s390_tm_ccmode (rtx op1
, rtx op2
, bool mixed
)
471 /* ??? Fixme: should work on CONST_DOUBLE as well. */
472 if (GET_CODE (op1
) != CONST_INT
|| GET_CODE (op2
) != CONST_INT
)
475 /* Selected bits all zero: CC0.
476 e.g.: int a; if ((a & (16 + 128)) == 0) */
477 if (INTVAL (op2
) == 0)
480 /* Selected bits all one: CC3.
481 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
482 if (INTVAL (op2
) == INTVAL (op1
))
485 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
487 if ((a & (16 + 128)) == 16) -> CCT1
488 if ((a & (16 + 128)) == 128) -> CCT2 */
491 bit1
= exact_log2 (INTVAL (op2
));
492 bit0
= exact_log2 (INTVAL (op1
) ^ INTVAL (op2
));
493 if (bit0
!= -1 && bit1
!= -1)
494 return bit0
> bit1
? CCT1mode
: CCT2mode
;
500 /* Given a comparison code OP (EQ, NE, etc.) and the operands
501 OP0 and OP1 of a COMPARE, return the mode to be used for the
505 s390_select_ccmode (enum rtx_code code
, rtx op0
, rtx op1
)
511 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
512 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
514 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
515 && CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1))))
517 if ((GET_CODE (op0
) == PLUS
|| GET_CODE (op0
) == MINUS
518 || GET_CODE (op1
) == NEG
)
519 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
522 if (GET_CODE (op0
) == AND
)
524 /* Check whether we can potentially do it via TM. */
525 enum machine_mode ccmode
;
526 ccmode
= s390_tm_ccmode (XEXP (op0
, 1), op1
, 1);
527 if (ccmode
!= VOIDmode
)
529 /* Relax CCTmode to CCZmode to allow fall-back to AND
530 if that turns out to be beneficial. */
531 return ccmode
== CCTmode
? CCZmode
: ccmode
;
535 if (register_operand (op0
, HImode
)
536 && GET_CODE (op1
) == CONST_INT
537 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 65535))
539 if (register_operand (op0
, QImode
)
540 && GET_CODE (op1
) == CONST_INT
541 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 255))
550 /* The only overflow condition of NEG and ABS happens when
551 -INT_MAX is used as parameter, which stays negative. So
552 we have an overflow from a positive value to a negative.
553 Using CCAP mode the resulting cc can be used for comparisons. */
554 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
555 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
558 /* If constants are involved in an add instruction it is possible to use
559 the resulting cc for comparisons with zero. Knowing the sign of the
560 constant the overflow behavior gets predictable. e.g.:
561 int a, b; if ((b = a + c) > 0)
562 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
563 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
564 && CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1))))
566 if (INTVAL (XEXP((op0
), 1)) < 0)
580 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
581 && GET_CODE (op1
) != CONST_INT
)
587 if (GET_CODE (op0
) == PLUS
588 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
591 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
592 && GET_CODE (op1
) != CONST_INT
)
598 if (GET_CODE (op0
) == MINUS
599 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
602 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
603 && GET_CODE (op1
) != CONST_INT
)
612 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
613 that we can implement more efficiently. */
616 s390_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
)
618 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
619 if ((*code
== EQ
|| *code
== NE
)
620 && *op1
== const0_rtx
621 && GET_CODE (*op0
) == ZERO_EXTRACT
622 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
623 && GET_CODE (XEXP (*op0
, 2)) == CONST_INT
624 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
626 rtx inner
= XEXP (*op0
, 0);
627 HOST_WIDE_INT modesize
= GET_MODE_BITSIZE (GET_MODE (inner
));
628 HOST_WIDE_INT len
= INTVAL (XEXP (*op0
, 1));
629 HOST_WIDE_INT pos
= INTVAL (XEXP (*op0
, 2));
631 if (len
> 0 && len
< modesize
632 && pos
>= 0 && pos
+ len
<= modesize
633 && modesize
<= HOST_BITS_PER_WIDE_INT
)
635 unsigned HOST_WIDE_INT block
;
636 block
= ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
637 block
<<= modesize
- pos
- len
;
639 *op0
= gen_rtx_AND (GET_MODE (inner
), inner
,
640 gen_int_mode (block
, GET_MODE (inner
)));
644 /* Narrow AND of memory against immediate to enable TM. */
645 if ((*code
== EQ
|| *code
== NE
)
646 && *op1
== const0_rtx
647 && GET_CODE (*op0
) == AND
648 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
649 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
651 rtx inner
= XEXP (*op0
, 0);
652 rtx mask
= XEXP (*op0
, 1);
654 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
655 if (GET_CODE (inner
) == SUBREG
656 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner
)))
657 && (GET_MODE_SIZE (GET_MODE (inner
))
658 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner
))))
660 & GET_MODE_MASK (GET_MODE (inner
))
661 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner
))))
663 inner
= SUBREG_REG (inner
);
665 /* Do not change volatile MEMs. */
666 if (MEM_P (inner
) && !MEM_VOLATILE_P (inner
))
668 int part
= s390_single_part (XEXP (*op0
, 1),
669 GET_MODE (inner
), QImode
, 0);
672 mask
= gen_int_mode (s390_extract_part (mask
, QImode
, 0), QImode
);
673 inner
= adjust_address_nv (inner
, QImode
, part
);
674 *op0
= gen_rtx_AND (QImode
, inner
, mask
);
679 /* Narrow comparisons against 0xffff to HImode if possible. */
680 if ((*code
== EQ
|| *code
== NE
)
681 && GET_CODE (*op1
) == CONST_INT
682 && INTVAL (*op1
) == 0xffff
683 && SCALAR_INT_MODE_P (GET_MODE (*op0
))
684 && (nonzero_bits (*op0
, GET_MODE (*op0
))
685 & ~(unsigned HOST_WIDE_INT
) 0xffff) == 0)
687 *op0
= gen_lowpart (HImode
, *op0
);
691 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
692 if (GET_CODE (*op0
) == UNSPEC
693 && XINT (*op0
, 1) == UNSPEC_CCU_TO_INT
694 && XVECLEN (*op0
, 0) == 1
695 && GET_MODE (XVECEXP (*op0
, 0, 0)) == CCUmode
696 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
697 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
698 && *op1
== const0_rtx
)
700 enum rtx_code new_code
= UNKNOWN
;
703 case EQ
: new_code
= EQ
; break;
704 case NE
: new_code
= NE
; break;
705 case LT
: new_code
= GTU
; break;
706 case GT
: new_code
= LTU
; break;
707 case LE
: new_code
= GEU
; break;
708 case GE
: new_code
= LEU
; break;
712 if (new_code
!= UNKNOWN
)
714 *op0
= XVECEXP (*op0
, 0, 0);
719 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
720 if (GET_CODE (*op0
) == UNSPEC
721 && XINT (*op0
, 1) == UNSPEC_CCZ_TO_INT
722 && XVECLEN (*op0
, 0) == 1
723 && GET_MODE (XVECEXP (*op0
, 0, 0)) == CCZmode
724 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
725 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
726 && *op1
== const0_rtx
)
728 enum rtx_code new_code
= UNKNOWN
;
731 case EQ
: new_code
= EQ
; break;
732 case NE
: new_code
= NE
; break;
736 if (new_code
!= UNKNOWN
)
738 *op0
= XVECEXP (*op0
, 0, 0);
743 /* Simplify cascaded EQ, NE with const0_rtx. */
744 if ((*code
== NE
|| *code
== EQ
)
745 && (GET_CODE (*op0
) == EQ
|| GET_CODE (*op0
) == NE
)
746 && GET_MODE (*op0
) == SImode
747 && GET_MODE (XEXP (*op0
, 0)) == CCZ1mode
748 && REG_P (XEXP (*op0
, 0))
749 && XEXP (*op0
, 1) == const0_rtx
750 && *op1
== const0_rtx
)
752 if ((*code
== EQ
&& GET_CODE (*op0
) == NE
)
753 || (*code
== NE
&& GET_CODE (*op0
) == EQ
))
757 *op0
= XEXP (*op0
, 0);
760 /* Prefer register over memory as first operand. */
761 if (MEM_P (*op0
) && REG_P (*op1
))
763 rtx tem
= *op0
; *op0
= *op1
; *op1
= tem
;
764 *code
= swap_condition (*code
);
768 /* Emit a compare instruction suitable to implement the comparison
769 OP0 CODE OP1. Return the correct condition RTL to be placed in
770 the IF_THEN_ELSE of the conditional branch testing the result. */
773 s390_emit_compare (enum rtx_code code
, rtx op0
, rtx op1
)
775 enum machine_mode mode
= s390_select_ccmode (code
, op0
, op1
);
778 /* Do not output a redundant compare instruction if a compare_and_swap
779 pattern already computed the result and the machine modes are compatible. */
780 if (s390_compare_emitted
781 && (s390_cc_modes_compatible (GET_MODE (s390_compare_emitted
), mode
)
782 == GET_MODE (s390_compare_emitted
)))
783 ret
= gen_rtx_fmt_ee (code
, VOIDmode
, s390_compare_emitted
, const0_rtx
);
786 rtx cc
= gen_rtx_REG (mode
, CC_REGNUM
);
788 emit_insn (gen_rtx_SET (VOIDmode
, cc
, gen_rtx_COMPARE (mode
, op0
, op1
)));
789 ret
= gen_rtx_fmt_ee (code
, VOIDmode
, cc
, const0_rtx
);
791 s390_compare_emitted
= NULL_RTX
;
795 /* Emit a SImode compare and swap instruction setting MEM to NEW if OLD
797 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
798 conditional branch testing the result. */
801 s390_emit_compare_and_swap (enum rtx_code code
, rtx old
, rtx mem
, rtx cmp
, rtx
new)
805 emit_insn (gen_sync_compare_and_swap_ccsi (old
, mem
, cmp
, new));
806 ret
= gen_rtx_fmt_ee (code
, VOIDmode
, s390_compare_emitted
, const0_rtx
);
808 s390_compare_emitted
= NULL_RTX
;
813 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
814 unconditional jump, else a conditional jump under condition COND. */
817 s390_emit_jump (rtx target
, rtx cond
)
821 target
= gen_rtx_LABEL_REF (VOIDmode
, target
);
823 target
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, target
, pc_rtx
);
825 insn
= gen_rtx_SET (VOIDmode
, pc_rtx
, target
);
826 emit_jump_insn (insn
);
829 /* Return branch condition mask to implement a branch
830 specified by CODE. Return -1 for invalid comparisons. */
833 s390_branch_condition_mask (rtx code
)
835 const int CC0
= 1 << 3;
836 const int CC1
= 1 << 2;
837 const int CC2
= 1 << 1;
838 const int CC3
= 1 << 0;
840 gcc_assert (GET_CODE (XEXP (code
, 0)) == REG
);
841 gcc_assert (REGNO (XEXP (code
, 0)) == CC_REGNUM
);
842 gcc_assert (XEXP (code
, 1) == const0_rtx
);
844 switch (GET_MODE (XEXP (code
, 0)))
848 switch (GET_CODE (code
))
851 case NE
: return CC1
| CC2
| CC3
;
857 switch (GET_CODE (code
))
860 case NE
: return CC0
| CC2
| CC3
;
866 switch (GET_CODE (code
))
869 case NE
: return CC0
| CC1
| CC3
;
875 switch (GET_CODE (code
))
878 case NE
: return CC0
| CC1
| CC2
;
884 switch (GET_CODE (code
))
886 case EQ
: return CC0
| CC2
;
887 case NE
: return CC1
| CC3
;
893 switch (GET_CODE (code
))
895 case LTU
: return CC2
| CC3
; /* carry */
896 case GEU
: return CC0
| CC1
; /* no carry */
902 switch (GET_CODE (code
))
904 case GTU
: return CC0
| CC1
; /* borrow */
905 case LEU
: return CC2
| CC3
; /* no borrow */
911 switch (GET_CODE (code
))
913 case EQ
: return CC0
| CC2
;
914 case NE
: return CC1
| CC3
;
915 case LTU
: return CC1
;
916 case GTU
: return CC3
;
917 case LEU
: return CC1
| CC2
;
918 case GEU
: return CC2
| CC3
;
923 switch (GET_CODE (code
))
926 case NE
: return CC1
| CC2
| CC3
;
927 case LTU
: return CC1
;
928 case GTU
: return CC2
;
929 case LEU
: return CC0
| CC1
;
930 case GEU
: return CC0
| CC2
;
936 switch (GET_CODE (code
))
939 case NE
: return CC2
| CC1
| CC3
;
940 case LTU
: return CC2
;
941 case GTU
: return CC1
;
942 case LEU
: return CC0
| CC2
;
943 case GEU
: return CC0
| CC1
;
949 switch (GET_CODE (code
))
952 case NE
: return CC1
| CC2
| CC3
;
953 case LT
: return CC1
| CC3
;
955 case LE
: return CC0
| CC1
| CC3
;
956 case GE
: return CC0
| CC2
;
962 switch (GET_CODE (code
))
965 case NE
: return CC1
| CC2
| CC3
;
967 case GT
: return CC2
| CC3
;
968 case LE
: return CC0
| CC1
;
969 case GE
: return CC0
| CC2
| CC3
;
975 switch (GET_CODE (code
))
978 case NE
: return CC1
| CC2
| CC3
;
981 case LE
: return CC0
| CC1
;
982 case GE
: return CC0
| CC2
;
983 case UNORDERED
: return CC3
;
984 case ORDERED
: return CC0
| CC1
| CC2
;
985 case UNEQ
: return CC0
| CC3
;
986 case UNLT
: return CC1
| CC3
;
987 case UNGT
: return CC2
| CC3
;
988 case UNLE
: return CC0
| CC1
| CC3
;
989 case UNGE
: return CC0
| CC2
| CC3
;
990 case LTGT
: return CC1
| CC2
;
996 switch (GET_CODE (code
))
999 case NE
: return CC2
| CC1
| CC3
;
1000 case LT
: return CC2
;
1001 case GT
: return CC1
;
1002 case LE
: return CC0
| CC2
;
1003 case GE
: return CC0
| CC1
;
1004 case UNORDERED
: return CC3
;
1005 case ORDERED
: return CC0
| CC2
| CC1
;
1006 case UNEQ
: return CC0
| CC3
;
1007 case UNLT
: return CC2
| CC3
;
1008 case UNGT
: return CC1
| CC3
;
1009 case UNLE
: return CC0
| CC2
| CC3
;
1010 case UNGE
: return CC0
| CC1
| CC3
;
1011 case LTGT
: return CC2
| CC1
;
1021 /* If INV is false, return assembler mnemonic string to implement
1022 a branch specified by CODE. If INV is true, return mnemonic
1023 for the corresponding inverted branch. */
1026 s390_branch_condition_mnemonic (rtx code
, int inv
)
1028 static const char *const mnemonic
[16] =
1030 NULL
, "o", "h", "nle",
1031 "l", "nhe", "lh", "ne",
1032 "e", "nlh", "he", "nl",
1033 "le", "nh", "no", NULL
1036 int mask
= s390_branch_condition_mask (code
);
1037 gcc_assert (mask
>= 0);
1042 gcc_assert (mask
>= 1 && mask
<= 14);
1044 return mnemonic
[mask
];
1047 /* Return the part of op which has a value different from def.
1048 The size of the part is determined by mode.
1049 Use this function only if you already know that op really
1050 contains such a part. */
1052 unsigned HOST_WIDE_INT
1053 s390_extract_part (rtx op
, enum machine_mode mode
, int def
)
1055 unsigned HOST_WIDE_INT value
= 0;
1056 int max_parts
= HOST_BITS_PER_WIDE_INT
/ GET_MODE_BITSIZE (mode
);
1057 int part_bits
= GET_MODE_BITSIZE (mode
);
1058 unsigned HOST_WIDE_INT part_mask
1059 = ((unsigned HOST_WIDE_INT
)1 << part_bits
) - 1;
1062 for (i
= 0; i
< max_parts
; i
++)
1065 value
= (unsigned HOST_WIDE_INT
) INTVAL (op
);
1067 value
>>= part_bits
;
1069 if ((value
& part_mask
) != (def
& part_mask
))
1070 return value
& part_mask
;
1076 /* If OP is an integer constant of mode MODE with exactly one
1077 part of mode PART_MODE unequal to DEF, return the number of that
1078 part. Otherwise, return -1. */
1081 s390_single_part (rtx op
,
1082 enum machine_mode mode
,
1083 enum machine_mode part_mode
,
1086 unsigned HOST_WIDE_INT value
= 0;
1087 int n_parts
= GET_MODE_SIZE (mode
) / GET_MODE_SIZE (part_mode
);
1088 unsigned HOST_WIDE_INT part_mask
1089 = ((unsigned HOST_WIDE_INT
)1 << GET_MODE_BITSIZE (part_mode
)) - 1;
1092 if (GET_CODE (op
) != CONST_INT
)
1095 for (i
= 0; i
< n_parts
; i
++)
1098 value
= (unsigned HOST_WIDE_INT
) INTVAL (op
);
1100 value
>>= GET_MODE_BITSIZE (part_mode
);
1102 if ((value
& part_mask
) != (def
& part_mask
))
1110 return part
== -1 ? -1 : n_parts
- 1 - part
;
1113 /* Check whether we can (and want to) split a double-word
1114 move in mode MODE from SRC to DST into two single-word
1115 moves, moving the subword FIRST_SUBWORD first. */
1118 s390_split_ok_p (rtx dst
, rtx src
, enum machine_mode mode
, int first_subword
)
1120 /* Floating point registers cannot be split. */
1121 if (FP_REG_P (src
) || FP_REG_P (dst
))
1124 /* We don't need to split if operands are directly accessible. */
1125 if (s_operand (src
, mode
) || s_operand (dst
, mode
))
1128 /* Non-offsettable memory references cannot be split. */
1129 if ((GET_CODE (src
) == MEM
&& !offsettable_memref_p (src
))
1130 || (GET_CODE (dst
) == MEM
&& !offsettable_memref_p (dst
)))
1133 /* Moving the first subword must not clobber a register
1134 needed to move the second subword. */
1135 if (register_operand (dst
, mode
))
1137 rtx subreg
= operand_subword (dst
, first_subword
, 0, mode
);
1138 if (reg_overlap_mentioned_p (subreg
, src
))
1145 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1146 and [MEM2, MEM2 + SIZE] do overlap and false
1150 s390_overlap_p (rtx mem1
, rtx mem2
, HOST_WIDE_INT size
)
1152 rtx addr1
, addr2
, addr_delta
;
1153 HOST_WIDE_INT delta
;
1155 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
1161 addr1
= XEXP (mem1
, 0);
1162 addr2
= XEXP (mem2
, 0);
1164 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
1166 /* This overlapping check is used by peepholes merging memory block operations.
1167 Overlapping operations would otherwise be recognized by the S/390 hardware
1168 and would fall back to a slower implementation. Allowing overlapping
1169 operations would lead to slow code but not to wrong code. Therefore we are
1170 somewhat optimistic if we cannot prove that the memory blocks are
1172 That's why we return false here although this may accept operations on
1173 overlapping memory areas. */
1174 if (!addr_delta
|| GET_CODE (addr_delta
) != CONST_INT
)
1177 delta
= INTVAL (addr_delta
);
1180 || (delta
> 0 && delta
< size
)
1181 || (delta
< 0 && -delta
< size
))
1187 /* Check whether the address of memory reference MEM2 equals exactly
1188 the address of memory reference MEM1 plus DELTA. Return true if
1189 we can prove this to be the case, false otherwise. */
1192 s390_offset_p (rtx mem1
, rtx mem2
, rtx delta
)
1194 rtx addr1
, addr2
, addr_delta
;
1196 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
1199 addr1
= XEXP (mem1
, 0);
1200 addr2
= XEXP (mem2
, 0);
1202 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
1203 if (!addr_delta
|| !rtx_equal_p (addr_delta
, delta
))
1209 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1212 s390_expand_logical_operator (enum rtx_code code
, enum machine_mode mode
,
1215 enum machine_mode wmode
= mode
;
1216 rtx dst
= operands
[0];
1217 rtx src1
= operands
[1];
1218 rtx src2
= operands
[2];
1221 /* If we cannot handle the operation directly, use a temp register. */
1222 if (!s390_logical_operator_ok_p (operands
))
1223 dst
= gen_reg_rtx (mode
);
1225 /* QImode and HImode patterns make sense only if we have a destination
1226 in memory. Otherwise perform the operation in SImode. */
1227 if ((mode
== QImode
|| mode
== HImode
) && GET_CODE (dst
) != MEM
)
1230 /* Widen operands if required. */
1233 if (GET_CODE (dst
) == SUBREG
1234 && (tem
= simplify_subreg (wmode
, dst
, mode
, 0)) != 0)
1236 else if (REG_P (dst
))
1237 dst
= gen_rtx_SUBREG (wmode
, dst
, 0);
1239 dst
= gen_reg_rtx (wmode
);
1241 if (GET_CODE (src1
) == SUBREG
1242 && (tem
= simplify_subreg (wmode
, src1
, mode
, 0)) != 0)
1244 else if (GET_MODE (src1
) != VOIDmode
)
1245 src1
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src1
), 0);
1247 if (GET_CODE (src2
) == SUBREG
1248 && (tem
= simplify_subreg (wmode
, src2
, mode
, 0)) != 0)
1250 else if (GET_MODE (src2
) != VOIDmode
)
1251 src2
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src2
), 0);
1254 /* Emit the instruction. */
1255 op
= gen_rtx_SET (VOIDmode
, dst
, gen_rtx_fmt_ee (code
, wmode
, src1
, src2
));
1256 clob
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
1257 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clob
)));
1259 /* Fix up the destination if needed. */
1260 if (dst
!= operands
[0])
1261 emit_move_insn (operands
[0], gen_lowpart (mode
, dst
));
1264 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1267 s390_logical_operator_ok_p (rtx
*operands
)
1269 /* If the destination operand is in memory, it needs to coincide
1270 with one of the source operands. After reload, it has to be
1271 the first source operand. */
1272 if (GET_CODE (operands
[0]) == MEM
)
1273 return rtx_equal_p (operands
[0], operands
[1])
1274 || (!reload_completed
&& rtx_equal_p (operands
[0], operands
[2]));
1279 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1280 operand IMMOP to switch from SS to SI type instructions. */
1283 s390_narrow_logical_operator (enum rtx_code code
, rtx
*memop
, rtx
*immop
)
1285 int def
= code
== AND
? -1 : 0;
1289 gcc_assert (GET_CODE (*memop
) == MEM
);
1290 gcc_assert (!MEM_VOLATILE_P (*memop
));
1292 mask
= s390_extract_part (*immop
, QImode
, def
);
1293 part
= s390_single_part (*immop
, GET_MODE (*memop
), QImode
, def
);
1294 gcc_assert (part
>= 0);
1296 *memop
= adjust_address (*memop
, QImode
, part
);
1297 *immop
= gen_int_mode (mask
, QImode
);
1301 /* How to allocate a 'struct machine_function'. */
1303 static struct machine_function
*
1304 s390_init_machine_status (void)
1306 return ggc_alloc_cleared (sizeof (struct machine_function
));
1309 /* Change optimizations to be performed, depending on the
1312 LEVEL is the optimization level specified; 2 if `-O2' is
1313 specified, 1 if `-O' is specified, and 0 if neither is specified.
1315 SIZE is nonzero if `-Os' is specified and zero otherwise. */
1318 optimization_options (int level ATTRIBUTE_UNUSED
, int size ATTRIBUTE_UNUSED
)
1320 /* ??? There are apparently still problems with -fcaller-saves. */
1321 flag_caller_saves
= 0;
1323 /* By default, always emit DWARF-2 unwind info. This allows debugging
1324 without maintaining a stack frame back-chain. */
1325 flag_asynchronous_unwind_tables
= 1;
1327 /* Use MVCLE instructions to decrease code size if requested. */
1329 target_flags
|= MASK_MVCLE
;
1332 /* Return true if ARG is the name of a processor. Set *TYPE and *FLAGS
1333 to the associated processor_type and processor_flags if so. */
1336 s390_handle_arch_option (const char *arg
,
1337 enum processor_type
*type
,
1338 enum processor_flags
*flags
)
1342 const char *const name
; /* processor name or nickname. */
1343 const enum processor_type processor
;
1344 const enum processor_flags flags
;
1346 const processor_alias_table
[] =
1348 {"g5", PROCESSOR_9672_G5
, PF_IEEE_FLOAT
},
1349 {"g6", PROCESSOR_9672_G6
, PF_IEEE_FLOAT
},
1350 {"z900", PROCESSOR_2064_Z900
, PF_IEEE_FLOAT
| PF_ZARCH
},
1351 {"z990", PROCESSOR_2084_Z990
, PF_IEEE_FLOAT
| PF_ZARCH
1352 | PF_LONG_DISPLACEMENT
},
1353 {"z9-109", PROCESSOR_2094_Z9_109
, PF_IEEE_FLOAT
| PF_ZARCH
1354 | PF_LONG_DISPLACEMENT
| PF_EXTIMM
},
1355 {"z9-ec", PROCESSOR_2094_Z9_109
, PF_IEEE_FLOAT
| PF_ZARCH
1356 | PF_LONG_DISPLACEMENT
| PF_EXTIMM
| PF_DFP
},
1360 for (i
= 0; i
< ARRAY_SIZE (processor_alias_table
); i
++)
1361 if (strcmp (arg
, processor_alias_table
[i
].name
) == 0)
1363 *type
= processor_alias_table
[i
].processor
;
1364 *flags
= processor_alias_table
[i
].flags
;
1370 /* Implement TARGET_HANDLE_OPTION. */
1373 s390_handle_option (size_t code
, const char *arg
, int value ATTRIBUTE_UNUSED
)
1378 return s390_handle_arch_option (arg
, &s390_arch
, &s390_arch_flags
);
1380 case OPT_mstack_guard_
:
1381 if (sscanf (arg
, HOST_WIDE_INT_PRINT_DEC
, &s390_stack_guard
) != 1)
1383 if (exact_log2 (s390_stack_guard
) == -1)
1384 error ("stack guard value must be an exact power of 2");
1387 case OPT_mstack_size_
:
1388 if (sscanf (arg
, HOST_WIDE_INT_PRINT_DEC
, &s390_stack_size
) != 1)
1390 if (exact_log2 (s390_stack_size
) == -1)
1391 error ("stack size must be an exact power of 2");
1395 return s390_handle_arch_option (arg
, &s390_tune
, &s390_tune_flags
);
1397 case OPT_mwarn_framesize_
:
1398 return sscanf (arg
, HOST_WIDE_INT_PRINT_DEC
, &s390_warn_framesize
) == 1;
1406 override_options (void)
1408 /* Set up function hooks. */
1409 init_machine_status
= s390_init_machine_status
;
1411 /* Architecture mode defaults according to ABI. */
1412 if (!(target_flags_explicit
& MASK_ZARCH
))
1415 target_flags
|= MASK_ZARCH
;
1417 target_flags
&= ~MASK_ZARCH
;
1420 /* Determine processor architectural level. */
1421 if (!s390_arch_string
)
1423 s390_arch_string
= TARGET_ZARCH
? "z900" : "g5";
1424 s390_handle_arch_option (s390_arch_string
, &s390_arch
, &s390_arch_flags
);
1427 /* Determine processor to tune for. */
1428 if (s390_tune
== PROCESSOR_max
)
1430 s390_tune
= s390_arch
;
1431 s390_tune_flags
= s390_arch_flags
;
1434 /* Sanity checks. */
1435 if (TARGET_ZARCH
&& !TARGET_CPU_ZARCH
)
1436 error ("z/Architecture mode not supported on %s", s390_arch_string
);
1437 if (TARGET_64BIT
&& !TARGET_ZARCH
)
1438 error ("64-bit ABI not supported in ESA/390 mode");
1440 if (TARGET_HARD_DFP
&& (!TARGET_CPU_DFP
|| !TARGET_ZARCH
))
1442 if (target_flags_explicit
& MASK_SOFT_DFP
)
1444 if (!TARGET_CPU_DFP
)
1445 error ("Hardware decimal floating point instructions"
1446 " not available on %s", s390_arch_string
);
1448 error ("Hardware decimal floating point instructions"
1449 " not available in ESA/390 mode");
1452 target_flags
|= MASK_SOFT_DFP
;
1455 if ((target_flags_explicit
& MASK_SOFT_FLOAT
) && TARGET_SOFT_FLOAT
)
1457 if ((target_flags_explicit
& MASK_SOFT_DFP
) && TARGET_HARD_DFP
)
1458 error ("-mhard-dfp can't be used in conjunction with -msoft-float");
1460 target_flags
|= MASK_SOFT_DFP
;
1463 /* Set processor cost function. */
1464 if (s390_tune
== PROCESSOR_2094_Z9_109
)
1465 s390_cost
= &z9_109_cost
;
1466 else if (s390_tune
== PROCESSOR_2084_Z990
)
1467 s390_cost
= &z990_cost
;
1469 s390_cost
= &z900_cost
;
1471 if (TARGET_BACKCHAIN
&& TARGET_PACKED_STACK
&& TARGET_HARD_FLOAT
)
1472 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1475 if (s390_stack_size
)
1477 if (s390_stack_guard
>= s390_stack_size
)
1478 error ("stack size must be greater than the stack guard value");
1479 else if (s390_stack_size
> 1 << 16)
1480 error ("stack size must not be greater than 64k");
1482 else if (s390_stack_guard
)
1483 error ("-mstack-guard implies use of -mstack-size");
1485 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1486 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
1487 target_flags
|= MASK_LONG_DOUBLE_128
;
1491 /* Map for smallest class containing reg regno. */
1493 const enum reg_class regclass_map
[FIRST_PSEUDO_REGISTER
] =
1494 { GENERAL_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1495 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1496 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1497 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1498 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1499 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1500 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1501 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1502 ADDR_REGS
, CC_REGS
, ADDR_REGS
, ADDR_REGS
,
1503 ACCESS_REGS
, ACCESS_REGS
1506 /* Return attribute type of insn. */
1508 static enum attr_type
1509 s390_safe_attr_type (rtx insn
)
1511 if (recog_memoized (insn
) >= 0)
1512 return get_attr_type (insn
);
1517 /* Return true if DISP is a valid short displacement. */
1520 s390_short_displacement (rtx disp
)
1522 /* No displacement is OK. */
1526 /* Integer displacement in range. */
1527 if (GET_CODE (disp
) == CONST_INT
)
1528 return INTVAL (disp
) >= 0 && INTVAL (disp
) < 4096;
1530 /* GOT offset is not OK, the GOT can be large. */
1531 if (GET_CODE (disp
) == CONST
1532 && GET_CODE (XEXP (disp
, 0)) == UNSPEC
1533 && (XINT (XEXP (disp
, 0), 1) == UNSPEC_GOT
1534 || XINT (XEXP (disp
, 0), 1) == UNSPEC_GOTNTPOFF
))
1537 /* All other symbolic constants are literal pool references,
1538 which are OK as the literal pool must be small. */
1539 if (GET_CODE (disp
) == CONST
)
1545 /* Decompose a RTL expression ADDR for a memory address into
1546 its components, returned in OUT.
1548 Returns false if ADDR is not a valid memory address, true
1549 otherwise. If OUT is NULL, don't return the components,
1550 but check for validity only.
1552 Note: Only addresses in canonical form are recognized.
1553 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1554 canonical form so that they will be recognized. */
1557 s390_decompose_address (rtx addr
, struct s390_address
*out
)
1559 HOST_WIDE_INT offset
= 0;
1560 rtx base
= NULL_RTX
;
1561 rtx indx
= NULL_RTX
;
1562 rtx disp
= NULL_RTX
;
1564 bool pointer
= false;
1565 bool base_ptr
= false;
1566 bool indx_ptr
= false;
1567 bool literal_pool
= false;
1569 /* We may need to substitute the literal pool base register into the address
1570 below. However, at this point we do not know which register is going to
1571 be used as base, so we substitute the arg pointer register. This is going
1572 to be treated as holding a pointer below -- it shouldn't be used for any
1574 rtx fake_pool_base
= gen_rtx_REG (Pmode
, ARG_POINTER_REGNUM
);
1576 /* Decompose address into base + index + displacement. */
1578 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == UNSPEC
)
1581 else if (GET_CODE (addr
) == PLUS
)
1583 rtx op0
= XEXP (addr
, 0);
1584 rtx op1
= XEXP (addr
, 1);
1585 enum rtx_code code0
= GET_CODE (op0
);
1586 enum rtx_code code1
= GET_CODE (op1
);
1588 if (code0
== REG
|| code0
== UNSPEC
)
1590 if (code1
== REG
|| code1
== UNSPEC
)
1592 indx
= op0
; /* index + base */
1598 base
= op0
; /* base + displacement */
1603 else if (code0
== PLUS
)
1605 indx
= XEXP (op0
, 0); /* index + base + disp */
1606 base
= XEXP (op0
, 1);
1617 disp
= addr
; /* displacement */
1619 /* Extract integer part of displacement. */
1623 if (GET_CODE (disp
) == CONST_INT
)
1625 offset
= INTVAL (disp
);
1628 else if (GET_CODE (disp
) == CONST
1629 && GET_CODE (XEXP (disp
, 0)) == PLUS
1630 && GET_CODE (XEXP (XEXP (disp
, 0), 1)) == CONST_INT
)
1632 offset
= INTVAL (XEXP (XEXP (disp
, 0), 1));
1633 disp
= XEXP (XEXP (disp
, 0), 0);
1637 /* Strip off CONST here to avoid special case tests later. */
1638 if (disp
&& GET_CODE (disp
) == CONST
)
1639 disp
= XEXP (disp
, 0);
1641 /* We can convert literal pool addresses to
1642 displacements by basing them off the base register. */
1643 if (disp
&& GET_CODE (disp
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (disp
))
1645 /* Either base or index must be free to hold the base register. */
1647 base
= fake_pool_base
, literal_pool
= true;
1649 indx
= fake_pool_base
, literal_pool
= true;
1653 /* Mark up the displacement. */
1654 disp
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, disp
),
1655 UNSPEC_LTREL_OFFSET
);
1658 /* Validate base register. */
1661 if (GET_CODE (base
) == UNSPEC
)
1662 switch (XINT (base
, 1))
1666 disp
= gen_rtx_UNSPEC (Pmode
,
1667 gen_rtvec (1, XVECEXP (base
, 0, 0)),
1668 UNSPEC_LTREL_OFFSET
);
1672 base
= XVECEXP (base
, 0, 1);
1675 case UNSPEC_LTREL_BASE
:
1676 if (XVECLEN (base
, 0) == 1)
1677 base
= fake_pool_base
, literal_pool
= true;
1679 base
= XVECEXP (base
, 0, 1);
1687 || (GET_MODE (base
) != SImode
1688 && GET_MODE (base
) != Pmode
))
1691 if (REGNO (base
) == STACK_POINTER_REGNUM
1692 || REGNO (base
) == FRAME_POINTER_REGNUM
1693 || ((reload_completed
|| reload_in_progress
)
1694 && frame_pointer_needed
1695 && REGNO (base
) == HARD_FRAME_POINTER_REGNUM
)
1696 || REGNO (base
) == ARG_POINTER_REGNUM
1698 && REGNO (base
) == PIC_OFFSET_TABLE_REGNUM
))
1699 pointer
= base_ptr
= true;
1701 if ((reload_completed
|| reload_in_progress
)
1702 && base
== cfun
->machine
->base_reg
)
1703 pointer
= base_ptr
= literal_pool
= true;
1706 /* Validate index register. */
1709 if (GET_CODE (indx
) == UNSPEC
)
1710 switch (XINT (indx
, 1))
1714 disp
= gen_rtx_UNSPEC (Pmode
,
1715 gen_rtvec (1, XVECEXP (indx
, 0, 0)),
1716 UNSPEC_LTREL_OFFSET
);
1720 indx
= XVECEXP (indx
, 0, 1);
1723 case UNSPEC_LTREL_BASE
:
1724 if (XVECLEN (indx
, 0) == 1)
1725 indx
= fake_pool_base
, literal_pool
= true;
1727 indx
= XVECEXP (indx
, 0, 1);
1735 || (GET_MODE (indx
) != SImode
1736 && GET_MODE (indx
) != Pmode
))
1739 if (REGNO (indx
) == STACK_POINTER_REGNUM
1740 || REGNO (indx
) == FRAME_POINTER_REGNUM
1741 || ((reload_completed
|| reload_in_progress
)
1742 && frame_pointer_needed
1743 && REGNO (indx
) == HARD_FRAME_POINTER_REGNUM
)
1744 || REGNO (indx
) == ARG_POINTER_REGNUM
1746 && REGNO (indx
) == PIC_OFFSET_TABLE_REGNUM
))
1747 pointer
= indx_ptr
= true;
1749 if ((reload_completed
|| reload_in_progress
)
1750 && indx
== cfun
->machine
->base_reg
)
1751 pointer
= indx_ptr
= literal_pool
= true;
1754 /* Prefer to use pointer as base, not index. */
1755 if (base
&& indx
&& !base_ptr
1756 && (indx_ptr
|| (!REG_POINTER (base
) && REG_POINTER (indx
))))
1763 /* Validate displacement. */
1766 /* If virtual registers are involved, the displacement will change later
1767 anyway as the virtual registers get eliminated. This could make a
1768 valid displacement invalid, but it is more likely to make an invalid
1769 displacement valid, because we sometimes access the register save area
1770 via negative offsets to one of those registers.
1771 Thus we don't check the displacement for validity here. If after
1772 elimination the displacement turns out to be invalid after all,
1773 this is fixed up by reload in any case. */
1774 if (base
!= arg_pointer_rtx
1775 && indx
!= arg_pointer_rtx
1776 && base
!= return_address_pointer_rtx
1777 && indx
!= return_address_pointer_rtx
1778 && base
!= frame_pointer_rtx
1779 && indx
!= frame_pointer_rtx
1780 && base
!= virtual_stack_vars_rtx
1781 && indx
!= virtual_stack_vars_rtx
)
1782 if (!DISP_IN_RANGE (offset
))
1787 /* All the special cases are pointers. */
1790 /* In the small-PIC case, the linker converts @GOT
1791 and @GOTNTPOFF offsets to possible displacements. */
1792 if (GET_CODE (disp
) == UNSPEC
1793 && (XINT (disp
, 1) == UNSPEC_GOT
1794 || XINT (disp
, 1) == UNSPEC_GOTNTPOFF
)
1800 /* Accept chunkified literal pool symbol references. */
1801 else if (cfun
&& cfun
->machine
1802 && cfun
->machine
->decomposed_literal_pool_addresses_ok_p
1803 && GET_CODE (disp
) == MINUS
1804 && GET_CODE (XEXP (disp
, 0)) == LABEL_REF
1805 && GET_CODE (XEXP (disp
, 1)) == LABEL_REF
)
1810 /* Accept literal pool references. */
1811 else if (GET_CODE (disp
) == UNSPEC
1812 && XINT (disp
, 1) == UNSPEC_LTREL_OFFSET
)
1814 orig_disp
= gen_rtx_CONST (Pmode
, disp
);
1817 /* If we have an offset, make sure it does not
1818 exceed the size of the constant pool entry. */
1819 rtx sym
= XVECEXP (disp
, 0, 0);
1820 if (offset
>= GET_MODE_SIZE (get_pool_mode (sym
)))
1823 orig_disp
= plus_constant (orig_disp
, offset
);
1838 out
->disp
= orig_disp
;
1839 out
->pointer
= pointer
;
1840 out
->literal_pool
= literal_pool
;
1846 /* Decompose a RTL expression OP for a shift count into its components,
1847 and return the base register in BASE and the offset in OFFSET.
1849 Return true if OP is a valid shift count, false if not. */
1852 s390_decompose_shift_count (rtx op
, rtx
*base
, HOST_WIDE_INT
*offset
)
1854 HOST_WIDE_INT off
= 0;
1856 /* We can have an integer constant, an address register,
1857 or a sum of the two. */
1858 if (GET_CODE (op
) == CONST_INT
)
1863 if (op
&& GET_CODE (op
) == PLUS
&& GET_CODE (XEXP (op
, 1)) == CONST_INT
)
1865 off
= INTVAL (XEXP (op
, 1));
1868 while (op
&& GET_CODE (op
) == SUBREG
)
1869 op
= SUBREG_REG (op
);
1871 if (op
&& GET_CODE (op
) != REG
)
1883 /* Return true if CODE is a valid address without index. */
1886 s390_legitimate_address_without_index_p (rtx op
)
1888 struct s390_address addr
;
1890 if (!s390_decompose_address (XEXP (op
, 0), &addr
))
1899 /* Evaluates constraint strings described by the regular expression
1900 ([A|B](Q|R|S|T))|U|W and returns 1 if OP is a valid operand for the
1901 constraint given in STR, or 0 else. */
1904 s390_mem_constraint (const char *str
, rtx op
)
1906 struct s390_address addr
;
1909 /* Check for offsettable variants of memory constraints. */
1912 /* Only accept non-volatile MEMs. */
1913 if (!MEM_P (op
) || MEM_VOLATILE_P (op
))
1916 if ((reload_completed
|| reload_in_progress
)
1917 ? !offsettable_memref_p (op
) : !offsettable_nonstrict_memref_p (op
))
1923 /* Check for non-literal-pool variants of memory constraints. */
1926 if (GET_CODE (op
) != MEM
)
1928 if (!s390_decompose_address (XEXP (op
, 0), &addr
))
1930 if (addr
.literal_pool
)
1939 if (GET_CODE (op
) != MEM
)
1941 if (!s390_decompose_address (XEXP (op
, 0), &addr
))
1946 if (TARGET_LONG_DISPLACEMENT
)
1948 if (!s390_short_displacement (addr
.disp
))
1954 if (GET_CODE (op
) != MEM
)
1957 if (TARGET_LONG_DISPLACEMENT
)
1959 if (!s390_decompose_address (XEXP (op
, 0), &addr
))
1961 if (!s390_short_displacement (addr
.disp
))
1967 if (!TARGET_LONG_DISPLACEMENT
)
1969 if (GET_CODE (op
) != MEM
)
1971 if (!s390_decompose_address (XEXP (op
, 0), &addr
))
1975 if (s390_short_displacement (addr
.disp
))
1980 if (!TARGET_LONG_DISPLACEMENT
)
1982 if (GET_CODE (op
) != MEM
)
1984 /* Any invalid address here will be fixed up by reload,
1985 so accept it for the most generic constraint. */
1986 if (s390_decompose_address (XEXP (op
, 0), &addr
)
1987 && s390_short_displacement (addr
.disp
))
1992 if (TARGET_LONG_DISPLACEMENT
)
1994 if (!s390_decompose_address (op
, &addr
))
1996 if (!s390_short_displacement (addr
.disp
))
2002 if (!TARGET_LONG_DISPLACEMENT
)
2004 /* Any invalid address here will be fixed up by reload,
2005 so accept it for the most generic constraint. */
2006 if (s390_decompose_address (op
, &addr
)
2007 && s390_short_displacement (addr
.disp
))
2012 /* Simply check for the basic form of a shift count. Reload will
2013 take care of making sure we have a proper base register. */
2014 if (!s390_decompose_shift_count (op
, NULL
, NULL
))
2027 /* Evaluates constraint strings starting with letter O. Input
2028 parameter C is the second letter following the "O" in the constraint
2029 string. Returns 1 if VALUE meets the respective constraint and 0
2033 s390_O_constraint_str (const char c
, HOST_WIDE_INT value
)
2041 return trunc_int_for_mode (value
, SImode
) == value
;
2045 || s390_single_part (GEN_INT (value
), DImode
, SImode
, 0) == 1;
2049 || s390_single_part (GEN_INT (value
), DImode
, SImode
, -1) == 1;
2057 /* Evaluates constraint strings starting with letter N. Parameter STR
2058 contains the letters following letter "N" in the constraint string.
2059 Returns true if VALUE matches the constraint. */
2062 s390_N_constraint_str (const char *str
, HOST_WIDE_INT value
)
2064 enum machine_mode mode
, part_mode
;
2066 int part
, part_goal
;
2072 part_goal
= str
[0] - '0';
2116 if (GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (part_mode
))
2119 part
= s390_single_part (GEN_INT (value
), mode
, part_mode
, def
);
2122 if (part_goal
!= -1 && part_goal
!= part
)
2129 /* Returns true if the input parameter VALUE is a float zero. */
2132 s390_float_const_zero_p (rtx value
)
2134 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
2135 && value
== CONST0_RTX (GET_MODE (value
)));
2139 /* Compute a (partial) cost for rtx X. Return true if the complete
2140 cost has been computed, and false if subexpressions should be
2141 scanned. In either case, *TOTAL contains the cost result.
2142 CODE contains GET_CODE (x), OUTER_CODE contains the code
2143 of the superexpression of x. */
2146 s390_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
2169 *total
= COSTS_N_INSNS (1);
2174 /* Check for multiply and add. */
2175 if ((GET_MODE (x
) == DFmode
|| GET_MODE (x
) == SFmode
)
2176 && GET_CODE (XEXP (x
, 0)) == MULT
2177 && TARGET_HARD_FLOAT
&& TARGET_FUSED_MADD
)
2179 /* This is the multiply and add case. */
2180 if (GET_MODE (x
) == DFmode
)
2181 *total
= s390_cost
->madbr
;
2183 *total
= s390_cost
->maebr
;
2184 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 0), MULT
)
2185 + rtx_cost (XEXP (XEXP (x
, 0), 1), MULT
)
2186 + rtx_cost (XEXP (x
, 1), code
);
2187 return true; /* Do not do an additional recursive descent. */
2189 *total
= COSTS_N_INSNS (1);
2193 switch (GET_MODE (x
))
2197 rtx left
= XEXP (x
, 0);
2198 rtx right
= XEXP (x
, 1);
2199 if (GET_CODE (right
) == CONST_INT
2200 && CONST_OK_FOR_K (INTVAL (right
)))
2201 *total
= s390_cost
->mhi
;
2202 else if (GET_CODE (left
) == SIGN_EXTEND
)
2203 *total
= s390_cost
->mh
;
2205 *total
= s390_cost
->ms
; /* msr, ms, msy */
2210 rtx left
= XEXP (x
, 0);
2211 rtx right
= XEXP (x
, 1);
2214 if (GET_CODE (right
) == CONST_INT
2215 && CONST_OK_FOR_K (INTVAL (right
)))
2216 *total
= s390_cost
->mghi
;
2217 else if (GET_CODE (left
) == SIGN_EXTEND
)
2218 *total
= s390_cost
->msgf
;
2220 *total
= s390_cost
->msg
; /* msgr, msg */
2222 else /* TARGET_31BIT */
2224 if (GET_CODE (left
) == SIGN_EXTEND
2225 && GET_CODE (right
) == SIGN_EXTEND
)
2226 /* mulsidi case: mr, m */
2227 *total
= s390_cost
->m
;
2228 else if (GET_CODE (left
) == ZERO_EXTEND
2229 && GET_CODE (right
) == ZERO_EXTEND
2230 && TARGET_CPU_ZARCH
)
2231 /* umulsidi case: ml, mlr */
2232 *total
= s390_cost
->ml
;
2234 /* Complex calculation is required. */
2235 *total
= COSTS_N_INSNS (40);
2241 *total
= s390_cost
->mult_df
;
2244 *total
= s390_cost
->mxbr
;
2253 if (GET_MODE (x
) == TImode
) /* 128 bit division */
2254 *total
= s390_cost
->dlgr
;
2255 else if (GET_MODE (x
) == DImode
)
2257 rtx right
= XEXP (x
, 1);
2258 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
2259 *total
= s390_cost
->dlr
;
2260 else /* 64 by 64 bit division */
2261 *total
= s390_cost
->dlgr
;
2263 else if (GET_MODE (x
) == SImode
) /* 32 bit division */
2264 *total
= s390_cost
->dlr
;
2269 if (GET_MODE (x
) == DImode
)
2271 rtx right
= XEXP (x
, 1);
2272 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
2274 *total
= s390_cost
->dsgfr
;
2276 *total
= s390_cost
->dr
;
2277 else /* 64 by 64 bit division */
2278 *total
= s390_cost
->dsgr
;
2280 else if (GET_MODE (x
) == SImode
) /* 32 bit division */
2281 *total
= s390_cost
->dlr
;
2282 else if (GET_MODE (x
) == SFmode
)
2284 *total
= s390_cost
->debr
;
2286 else if (GET_MODE (x
) == DFmode
)
2288 *total
= s390_cost
->ddbr
;
2290 else if (GET_MODE (x
) == TFmode
)
2292 *total
= s390_cost
->dxbr
;
2297 if (GET_MODE (x
) == SFmode
)
2298 *total
= s390_cost
->sqebr
;
2299 else if (GET_MODE (x
) == DFmode
)
2300 *total
= s390_cost
->sqdbr
;
2302 *total
= s390_cost
->sqxbr
;
2307 if (outer_code
== MULT
|| outer_code
== DIV
|| outer_code
== MOD
2308 || outer_code
== PLUS
|| outer_code
== MINUS
2309 || outer_code
== COMPARE
)
2314 *total
= COSTS_N_INSNS (1);
2315 if (GET_CODE (XEXP (x
, 0)) == AND
2316 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2317 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
2319 rtx op0
= XEXP (XEXP (x
, 0), 0);
2320 rtx op1
= XEXP (XEXP (x
, 0), 1);
2321 rtx op2
= XEXP (x
, 1);
2323 if (memory_operand (op0
, GET_MODE (op0
))
2324 && s390_tm_ccmode (op1
, op2
, 0) != VOIDmode
)
2326 if (register_operand (op0
, GET_MODE (op0
))
2327 && s390_tm_ccmode (op1
, op2
, 1) != VOIDmode
)
2337 /* Return the cost of an address rtx ADDR. */
2340 s390_address_cost (rtx addr
)
2342 struct s390_address ad
;
2343 if (!s390_decompose_address (addr
, &ad
))
2346 return ad
.indx
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2349 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2350 otherwise return 0. */
2353 tls_symbolic_operand (rtx op
)
2355 if (GET_CODE (op
) != SYMBOL_REF
)
2357 return SYMBOL_REF_TLS_MODEL (op
);
2360 /* Split DImode access register reference REG (on 64-bit) into its constituent
2361 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2362 gen_highpart cannot be used as they assume all registers are word-sized,
2363 while our access registers have only half that size. */
2366 s390_split_access_reg (rtx reg
, rtx
*lo
, rtx
*hi
)
2368 gcc_assert (TARGET_64BIT
);
2369 gcc_assert (ACCESS_REG_P (reg
));
2370 gcc_assert (GET_MODE (reg
) == DImode
);
2371 gcc_assert (!(REGNO (reg
) & 1));
2373 *lo
= gen_rtx_REG (SImode
, REGNO (reg
) + 1);
2374 *hi
= gen_rtx_REG (SImode
, REGNO (reg
));
2377 /* Return true if OP contains a symbol reference */
2380 symbolic_reference_mentioned_p (rtx op
)
2385 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
2388 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
2389 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
2395 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
2396 if (symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
2400 else if (fmt
[i
] == 'e' && symbolic_reference_mentioned_p (XEXP (op
, i
)))
2407 /* Return true if OP contains a reference to a thread-local symbol. */
2410 tls_symbolic_reference_mentioned_p (rtx op
)
2415 if (GET_CODE (op
) == SYMBOL_REF
)
2416 return tls_symbolic_operand (op
);
2418 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
2419 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
2425 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
2426 if (tls_symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
2430 else if (fmt
[i
] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op
, i
)))
2438 /* Return true if OP is a legitimate general operand when
2439 generating PIC code. It is given that flag_pic is on
2440 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2443 legitimate_pic_operand_p (rtx op
)
2445 /* Accept all non-symbolic constants. */
2446 if (!SYMBOLIC_CONST (op
))
2449 /* Reject everything else; must be handled
2450 via emit_symbolic_move. */
2454 /* Returns true if the constant value OP is a legitimate general operand.
2455 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2458 legitimate_constant_p (rtx op
)
2460 /* Accept all non-symbolic constants. */
2461 if (!SYMBOLIC_CONST (op
))
2464 /* Accept immediate LARL operands. */
2465 if (TARGET_CPU_ZARCH
&& larl_operand (op
, VOIDmode
))
2468 /* Thread-local symbols are never legal constants. This is
2469 so that emit_call knows that computing such addresses
2470 might require a function call. */
2471 if (TLS_SYMBOLIC_CONST (op
))
2474 /* In the PIC case, symbolic constants must *not* be
2475 forced into the literal pool. We accept them here,
2476 so that they will be handled by emit_symbolic_move. */
2480 /* All remaining non-PIC symbolic constants are
2481 forced into the literal pool. */
2485 /* Determine if it's legal to put X into the constant pool. This
2486 is not possible if X contains the address of a symbol that is
2487 not constant (TLS) or not known at final link time (PIC). */
2490 s390_cannot_force_const_mem (rtx x
)
2492 switch (GET_CODE (x
))
2496 /* Accept all non-symbolic constants. */
2500 /* Labels are OK iff we are non-PIC. */
2501 return flag_pic
!= 0;
2504 /* 'Naked' TLS symbol references are never OK,
2505 non-TLS symbols are OK iff we are non-PIC. */
2506 if (tls_symbolic_operand (x
))
2509 return flag_pic
!= 0;
2512 return s390_cannot_force_const_mem (XEXP (x
, 0));
2515 return s390_cannot_force_const_mem (XEXP (x
, 0))
2516 || s390_cannot_force_const_mem (XEXP (x
, 1));
2519 switch (XINT (x
, 1))
2521 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2522 case UNSPEC_LTREL_OFFSET
:
2530 case UNSPEC_GOTNTPOFF
:
2531 case UNSPEC_INDNTPOFF
:
2534 /* If the literal pool shares the code section, be put
2535 execute template placeholders into the pool as well. */
2537 return TARGET_CPU_ZARCH
;
2549 /* Returns true if the constant value OP is a legitimate general
2550 operand during and after reload. The difference to
2551 legitimate_constant_p is that this function will not accept
2552 a constant that would need to be forced to the literal pool
2553 before it can be used as operand. */
2556 legitimate_reload_constant_p (rtx op
)
2558 /* Accept la(y) operands. */
2559 if (GET_CODE (op
) == CONST_INT
2560 && DISP_IN_RANGE (INTVAL (op
)))
2563 /* Accept l(g)hi/l(g)fi operands. */
2564 if (GET_CODE (op
) == CONST_INT
2565 && (CONST_OK_FOR_K (INTVAL (op
)) || CONST_OK_FOR_Os (INTVAL (op
))))
2568 /* Accept lliXX operands. */
2570 && GET_CODE (op
) == CONST_INT
2571 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
2572 && s390_single_part (op
, word_mode
, HImode
, 0) >= 0)
2576 && GET_CODE (op
) == CONST_INT
2577 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
2578 && s390_single_part (op
, word_mode
, SImode
, 0) >= 0)
2581 /* Accept larl operands. */
2582 if (TARGET_CPU_ZARCH
2583 && larl_operand (op
, VOIDmode
))
2586 /* Accept lzXX operands. */
2587 if (GET_CODE (op
) == CONST_DOUBLE
2588 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, 'G', "G"))
2591 /* Accept double-word operands that can be split. */
2592 if (GET_CODE (op
) == CONST_INT
2593 && trunc_int_for_mode (INTVAL (op
), word_mode
) != INTVAL (op
))
2595 enum machine_mode dword_mode
= word_mode
== SImode
? DImode
: TImode
;
2596 rtx hi
= operand_subword (op
, 0, 0, dword_mode
);
2597 rtx lo
= operand_subword (op
, 1, 0, dword_mode
);
2598 return legitimate_reload_constant_p (hi
)
2599 && legitimate_reload_constant_p (lo
);
2602 /* Everything else cannot be handled without reload. */
2606 /* Given an rtx OP being reloaded into a reg required to be in class CLASS,
2607 return the class of reg to actually use. */
2610 s390_preferred_reload_class (rtx op
, enum reg_class
class)
2612 switch (GET_CODE (op
))
2614 /* Constants we cannot reload must be forced into the
2619 if (legitimate_reload_constant_p (op
))
2624 /* If a symbolic constant or a PLUS is reloaded,
2625 it is most likely being used as an address, so
2626 prefer ADDR_REGS. If 'class' is not a superset
2627 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2632 if (reg_class_subset_p (ADDR_REGS
, class))
2644 /* Inform reload about cases where moving X with a mode MODE to a register in
2645 CLASS requires an extra scratch or immediate register. Return the class
2646 needed for the immediate register. */
2648 static enum reg_class
2649 s390_secondary_reload (bool in_p
, rtx x
, enum reg_class
class,
2650 enum machine_mode mode
, secondary_reload_info
*sri
)
2652 /* Intermediate register needed. */
2653 if (reg_classes_intersect_p (CC_REGS
, class))
2654 return GENERAL_REGS
;
2656 /* We need a scratch register when loading a PLUS expression which
2657 is not a legitimate operand of the LOAD ADDRESS instruction. */
2658 if (in_p
&& s390_plus_operand (x
, mode
))
2659 sri
->icode
= (TARGET_64BIT
?
2660 CODE_FOR_reloaddi_plus
: CODE_FOR_reloadsi_plus
);
2662 /* Performing a multiword move from or to memory we have to make sure the
2663 second chunk in memory is addressable without causing a displacement
2664 overflow. If that would be the case we calculate the address in
2665 a scratch register. */
2667 && GET_CODE (XEXP (x
, 0)) == PLUS
2668 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2669 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x
, 0), 1))
2670 + GET_MODE_SIZE (mode
) - 1))
2672 /* For GENERAL_REGS a displacement overflow is no problem if occurring
2673 in a s_operand address since we may fallback to lm/stm. So we only
2674 have to care about overflows in the b+i+d case. */
2675 if ((reg_classes_intersect_p (GENERAL_REGS
, class)
2676 && s390_class_max_nregs (GENERAL_REGS
, mode
) > 1
2677 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
2678 /* For FP_REGS no lm/stm is available so this check is triggered
2679 for displacement overflows in b+i+d and b+d like addresses. */
2680 || (reg_classes_intersect_p (FP_REGS
, class)
2681 && s390_class_max_nregs (FP_REGS
, mode
) > 1))
2684 sri
->icode
= (TARGET_64BIT
?
2685 CODE_FOR_reloaddi_nonoffmem_in
:
2686 CODE_FOR_reloadsi_nonoffmem_in
);
2688 sri
->icode
= (TARGET_64BIT
?
2689 CODE_FOR_reloaddi_nonoffmem_out
:
2690 CODE_FOR_reloadsi_nonoffmem_out
);
2694 /* Either scratch or no register needed. */
2698 /* Generate code to load SRC, which is PLUS that is not a
2699 legitimate operand for the LA instruction, into TARGET.
2700 SCRATCH may be used as scratch register. */
2703 s390_expand_plus_operand (rtx target
, rtx src
,
2707 struct s390_address ad
;
2709 /* src must be a PLUS; get its two operands. */
2710 gcc_assert (GET_CODE (src
) == PLUS
);
2711 gcc_assert (GET_MODE (src
) == Pmode
);
2713 /* Check if any of the two operands is already scheduled
2714 for replacement by reload. This can happen e.g. when
2715 float registers occur in an address. */
2716 sum1
= find_replacement (&XEXP (src
, 0));
2717 sum2
= find_replacement (&XEXP (src
, 1));
2718 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
2720 /* If the address is already strictly valid, there's nothing to do. */
2721 if (!s390_decompose_address (src
, &ad
)
2722 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
2723 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
2725 /* Otherwise, one of the operands cannot be an address register;
2726 we reload its value into the scratch register. */
2727 if (true_regnum (sum1
) < 1 || true_regnum (sum1
) > 15)
2729 emit_move_insn (scratch
, sum1
);
2732 if (true_regnum (sum2
) < 1 || true_regnum (sum2
) > 15)
2734 emit_move_insn (scratch
, sum2
);
2738 /* According to the way these invalid addresses are generated
2739 in reload.c, it should never happen (at least on s390) that
2740 *neither* of the PLUS components, after find_replacements
2741 was applied, is an address register. */
2742 if (sum1
== scratch
&& sum2
== scratch
)
2748 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
2751 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
2752 is only ever performed on addresses, so we can mark the
2753 sum as legitimate for LA in any case. */
2754 s390_load_address (target
, src
);
2758 /* Return true if ADDR is a valid memory address.
2759 STRICT specifies whether strict register checking applies. */
2762 legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
2763 rtx addr
, int strict
)
2765 struct s390_address ad
;
2766 if (!s390_decompose_address (addr
, &ad
))
2771 if (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
2774 if (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
)))
2780 && !(REGNO (ad
.base
) >= FIRST_PSEUDO_REGISTER
2781 || REGNO_REG_CLASS (REGNO (ad
.base
)) == ADDR_REGS
))
2785 && !(REGNO (ad
.indx
) >= FIRST_PSEUDO_REGISTER
2786 || REGNO_REG_CLASS (REGNO (ad
.indx
)) == ADDR_REGS
))
2792 /* Return true if OP is a valid operand for the LA instruction.
2793 In 31-bit, we need to prove that the result is used as an
2794 address, as LA performs only a 31-bit addition. */
2797 legitimate_la_operand_p (rtx op
)
2799 struct s390_address addr
;
2800 if (!s390_decompose_address (op
, &addr
))
2803 return (TARGET_64BIT
|| addr
.pointer
);
2806 /* Return true if it is valid *and* preferable to use LA to
2807 compute the sum of OP1 and OP2. */
2810 preferred_la_operand_p (rtx op1
, rtx op2
)
2812 struct s390_address addr
;
2814 if (op2
!= const0_rtx
)
2815 op1
= gen_rtx_PLUS (Pmode
, op1
, op2
);
2817 if (!s390_decompose_address (op1
, &addr
))
2819 if (addr
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (addr
.base
)))
2821 if (addr
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (addr
.indx
)))
2824 if (!TARGET_64BIT
&& !addr
.pointer
)
2830 if ((addr
.base
&& REG_P (addr
.base
) && REG_POINTER (addr
.base
))
2831 || (addr
.indx
&& REG_P (addr
.indx
) && REG_POINTER (addr
.indx
)))
2837 /* Emit a forced load-address operation to load SRC into DST.
2838 This will use the LOAD ADDRESS instruction even in situations
2839 where legitimate_la_operand_p (SRC) returns false. */
2842 s390_load_address (rtx dst
, rtx src
)
2845 emit_move_insn (dst
, src
);
2847 emit_insn (gen_force_la_31 (dst
, src
));
2850 /* Return a legitimate reference for ORIG (an address) using the
2851 register REG. If REG is 0, a new pseudo is generated.
2853 There are two types of references that must be handled:
2855 1. Global data references must load the address from the GOT, via
2856 the PIC reg. An insn is emitted to do this load, and the reg is
2859 2. Static data references, constant pool addresses, and code labels
2860 compute the address as an offset from the GOT, whose base is in
2861 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
2862 differentiate them from global data objects. The returned
2863 address is the PIC reg + an unspec constant.
2865 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
2866 reg also appears in the address. */
2869 legitimize_pic_address (rtx orig
, rtx reg
)
2875 gcc_assert (!TLS_SYMBOLIC_CONST (addr
));
2877 if (GET_CODE (addr
) == LABEL_REF
2878 || (GET_CODE (addr
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (addr
)))
2880 /* This is a local symbol. */
2881 if (TARGET_CPU_ZARCH
&& larl_operand (addr
, VOIDmode
))
2883 /* Access local symbols PC-relative via LARL.
2884 This is the same as in the non-PIC case, so it is
2885 handled automatically ... */
2889 /* Access local symbols relative to the GOT. */
2891 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
2893 if (reload_in_progress
|| reload_completed
)
2894 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
2896 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTOFF
);
2897 addr
= gen_rtx_CONST (Pmode
, addr
);
2898 addr
= force_const_mem (Pmode
, addr
);
2899 emit_move_insn (temp
, addr
);
2901 new = gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
2904 s390_load_address (reg
, new);
2909 else if (GET_CODE (addr
) == SYMBOL_REF
)
2912 reg
= gen_reg_rtx (Pmode
);
2916 /* Assume GOT offset < 4k. This is handled the same way
2917 in both 31- and 64-bit code (@GOT). */
2919 if (reload_in_progress
|| reload_completed
)
2920 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
2922 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
2923 new = gen_rtx_CONST (Pmode
, new);
2924 new = gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new);
2925 new = gen_const_mem (Pmode
, new);
2926 emit_move_insn (reg
, new);
2929 else if (TARGET_CPU_ZARCH
)
2931 /* If the GOT offset might be >= 4k, we determine the position
2932 of the GOT entry via a PC-relative LARL (@GOTENT). */
2934 rtx temp
= gen_reg_rtx (Pmode
);
2936 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTENT
);
2937 new = gen_rtx_CONST (Pmode
, new);
2938 emit_move_insn (temp
, new);
2940 new = gen_const_mem (Pmode
, temp
);
2941 emit_move_insn (reg
, new);
2946 /* If the GOT offset might be >= 4k, we have to load it
2947 from the literal pool (@GOT). */
2949 rtx temp
= gen_reg_rtx (Pmode
);
2951 if (reload_in_progress
|| reload_completed
)
2952 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
2954 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
2955 addr
= gen_rtx_CONST (Pmode
, addr
);
2956 addr
= force_const_mem (Pmode
, addr
);
2957 emit_move_insn (temp
, addr
);
2959 new = gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
2960 new = gen_const_mem (Pmode
, new);
2961 emit_move_insn (reg
, new);
2967 if (GET_CODE (addr
) == CONST
)
2969 addr
= XEXP (addr
, 0);
2970 if (GET_CODE (addr
) == UNSPEC
)
2972 gcc_assert (XVECLEN (addr
, 0) == 1);
2973 switch (XINT (addr
, 1))
2975 /* If someone moved a GOT-relative UNSPEC
2976 out of the literal pool, force them back in. */
2979 new = force_const_mem (Pmode
, orig
);
2982 /* @GOT is OK as is if small. */
2985 new = force_const_mem (Pmode
, orig
);
2988 /* @GOTENT is OK as is. */
2992 /* @PLT is OK as is on 64-bit, must be converted to
2993 GOT-relative @PLTOFF on 31-bit. */
2995 if (!TARGET_CPU_ZARCH
)
2997 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
2999 if (reload_in_progress
|| reload_completed
)
3000 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3002 addr
= XVECEXP (addr
, 0, 0);
3003 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
),
3005 addr
= gen_rtx_CONST (Pmode
, addr
);
3006 addr
= force_const_mem (Pmode
, addr
);
3007 emit_move_insn (temp
, addr
);
3009 new = gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3012 s390_load_address (reg
, new);
3018 /* Everything else cannot happen. */
3024 gcc_assert (GET_CODE (addr
) == PLUS
);
3026 if (GET_CODE (addr
) == PLUS
)
3028 rtx op0
= XEXP (addr
, 0), op1
= XEXP (addr
, 1);
3030 gcc_assert (!TLS_SYMBOLIC_CONST (op0
));
3031 gcc_assert (!TLS_SYMBOLIC_CONST (op1
));
3033 /* Check first to see if this is a constant offset
3034 from a local symbol reference. */
3035 if ((GET_CODE (op0
) == LABEL_REF
3036 || (GET_CODE (op0
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op0
)))
3037 && GET_CODE (op1
) == CONST_INT
)
3039 if (TARGET_CPU_ZARCH
3040 && larl_operand (op0
, VOIDmode
)
3041 && INTVAL (op1
) < (HOST_WIDE_INT
)1 << 31
3042 && INTVAL (op1
) >= -((HOST_WIDE_INT
)1 << 31))
3044 if (INTVAL (op1
) & 1)
3046 /* LARL can't handle odd offsets, so emit a
3047 pair of LARL and LA. */
3048 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3050 if (!DISP_IN_RANGE (INTVAL (op1
)))
3052 HOST_WIDE_INT even
= INTVAL (op1
) - 1;
3053 op0
= gen_rtx_PLUS (Pmode
, op0
, GEN_INT (even
));
3054 op0
= gen_rtx_CONST (Pmode
, op0
);
3058 emit_move_insn (temp
, op0
);
3059 new = gen_rtx_PLUS (Pmode
, temp
, op1
);
3063 s390_load_address (reg
, new);
3069 /* If the offset is even, we can just use LARL.
3070 This will happen automatically. */
3075 /* Access local symbols relative to the GOT. */
3077 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3079 if (reload_in_progress
|| reload_completed
)
3080 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3082 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op0
),
3084 addr
= gen_rtx_PLUS (Pmode
, addr
, op1
);
3085 addr
= gen_rtx_CONST (Pmode
, addr
);
3086 addr
= force_const_mem (Pmode
, addr
);
3087 emit_move_insn (temp
, addr
);
3089 new = gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3092 s390_load_address (reg
, new);
3098 /* Now, check whether it is a GOT relative symbol plus offset
3099 that was pulled out of the literal pool. Force it back in. */
3101 else if (GET_CODE (op0
) == UNSPEC
3102 && GET_CODE (op1
) == CONST_INT
3103 && XINT (op0
, 1) == UNSPEC_GOTOFF
)
3105 gcc_assert (XVECLEN (op0
, 0) == 1);
3107 new = force_const_mem (Pmode
, orig
);
3110 /* Otherwise, compute the sum. */
3113 base
= legitimize_pic_address (XEXP (addr
, 0), reg
);
3114 new = legitimize_pic_address (XEXP (addr
, 1),
3115 base
== reg
? NULL_RTX
: reg
);
3116 if (GET_CODE (new) == CONST_INT
)
3117 new = plus_constant (base
, INTVAL (new));
3120 if (GET_CODE (new) == PLUS
&& CONSTANT_P (XEXP (new, 1)))
3122 base
= gen_rtx_PLUS (Pmode
, base
, XEXP (new, 0));
3123 new = XEXP (new, 1);
3125 new = gen_rtx_PLUS (Pmode
, base
, new);
3128 if (GET_CODE (new) == CONST
)
3129 new = XEXP (new, 0);
3130 new = force_operand (new, 0);
3137 /* Load the thread pointer into a register. */
3140 s390_get_thread_pointer (void)
3142 rtx tp
= gen_reg_rtx (Pmode
);
3144 emit_move_insn (tp
, gen_rtx_REG (Pmode
, TP_REGNUM
));
3145 mark_reg_pointer (tp
, BITS_PER_WORD
);
3150 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3151 in s390_tls_symbol which always refers to __tls_get_offset.
3152 The returned offset is written to RESULT_REG and an USE rtx is
3153 generated for TLS_CALL. */
3155 static GTY(()) rtx s390_tls_symbol
;
3158 s390_emit_tls_call_insn (rtx result_reg
, rtx tls_call
)
3162 gcc_assert (flag_pic
);
3164 if (!s390_tls_symbol
)
3165 s390_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_offset");
3167 insn
= s390_emit_call (s390_tls_symbol
, tls_call
, result_reg
,
3168 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
3170 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), result_reg
);
3171 CONST_OR_PURE_CALL_P (insn
) = 1;
3174 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3175 this (thread-local) address. REG may be used as temporary. */
3178 legitimize_tls_address (rtx addr
, rtx reg
)
3180 rtx
new, tls_call
, temp
, base
, r2
, insn
;
3182 if (GET_CODE (addr
) == SYMBOL_REF
)
3183 switch (tls_symbolic_operand (addr
))
3185 case TLS_MODEL_GLOBAL_DYNAMIC
:
3187 r2
= gen_rtx_REG (Pmode
, 2);
3188 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_TLSGD
);
3189 new = gen_rtx_CONST (Pmode
, tls_call
);
3190 new = force_const_mem (Pmode
, new);
3191 emit_move_insn (r2
, new);
3192 s390_emit_tls_call_insn (r2
, tls_call
);
3193 insn
= get_insns ();
3196 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
3197 temp
= gen_reg_rtx (Pmode
);
3198 emit_libcall_block (insn
, temp
, r2
, new);
3200 new = gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3203 s390_load_address (reg
, new);
3208 case TLS_MODEL_LOCAL_DYNAMIC
:
3210 r2
= gen_rtx_REG (Pmode
, 2);
3211 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM
);
3212 new = gen_rtx_CONST (Pmode
, tls_call
);
3213 new = force_const_mem (Pmode
, new);
3214 emit_move_insn (r2
, new);
3215 s390_emit_tls_call_insn (r2
, tls_call
);
3216 insn
= get_insns ();
3219 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM_NTPOFF
);
3220 temp
= gen_reg_rtx (Pmode
);
3221 emit_libcall_block (insn
, temp
, r2
, new);
3223 new = gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3224 base
= gen_reg_rtx (Pmode
);
3225 s390_load_address (base
, new);
3227 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_DTPOFF
);
3228 new = gen_rtx_CONST (Pmode
, new);
3229 new = force_const_mem (Pmode
, new);
3230 temp
= gen_reg_rtx (Pmode
);
3231 emit_move_insn (temp
, new);
3233 new = gen_rtx_PLUS (Pmode
, base
, temp
);
3236 s390_load_address (reg
, new);
3241 case TLS_MODEL_INITIAL_EXEC
:
3244 /* Assume GOT offset < 4k. This is handled the same way
3245 in both 31- and 64-bit code. */
3247 if (reload_in_progress
|| reload_completed
)
3248 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3250 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
3251 new = gen_rtx_CONST (Pmode
, new);
3252 new = gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new);
3253 new = gen_const_mem (Pmode
, new);
3254 temp
= gen_reg_rtx (Pmode
);
3255 emit_move_insn (temp
, new);
3257 else if (TARGET_CPU_ZARCH
)
3259 /* If the GOT offset might be >= 4k, we determine the position
3260 of the GOT entry via a PC-relative LARL. */
3262 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
3263 new = gen_rtx_CONST (Pmode
, new);
3264 temp
= gen_reg_rtx (Pmode
);
3265 emit_move_insn (temp
, new);
3267 new = gen_const_mem (Pmode
, temp
);
3268 temp
= gen_reg_rtx (Pmode
);
3269 emit_move_insn (temp
, new);
3273 /* If the GOT offset might be >= 4k, we have to load it
3274 from the literal pool. */
3276 if (reload_in_progress
|| reload_completed
)
3277 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3279 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
3280 new = gen_rtx_CONST (Pmode
, new);
3281 new = force_const_mem (Pmode
, new);
3282 temp
= gen_reg_rtx (Pmode
);
3283 emit_move_insn (temp
, new);
3285 new = gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3286 new = gen_const_mem (Pmode
, new);
3288 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new, addr
), UNSPEC_TLS_LOAD
);
3289 temp
= gen_reg_rtx (Pmode
);
3290 emit_insn (gen_rtx_SET (Pmode
, temp
, new));
3294 /* In position-dependent code, load the absolute address of
3295 the GOT entry from the literal pool. */
3297 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
3298 new = gen_rtx_CONST (Pmode
, new);
3299 new = force_const_mem (Pmode
, new);
3300 temp
= gen_reg_rtx (Pmode
);
3301 emit_move_insn (temp
, new);
3304 new = gen_const_mem (Pmode
, new);
3305 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new, addr
), UNSPEC_TLS_LOAD
);
3306 temp
= gen_reg_rtx (Pmode
);
3307 emit_insn (gen_rtx_SET (Pmode
, temp
, new));
3310 new = gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3313 s390_load_address (reg
, new);
3318 case TLS_MODEL_LOCAL_EXEC
:
3319 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
3320 new = gen_rtx_CONST (Pmode
, new);
3321 new = force_const_mem (Pmode
, new);
3322 temp
= gen_reg_rtx (Pmode
);
3323 emit_move_insn (temp
, new);
3325 new = gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3328 s390_load_address (reg
, new);
3337 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == UNSPEC
)
3339 switch (XINT (XEXP (addr
, 0), 1))
3341 case UNSPEC_INDNTPOFF
:
3342 gcc_assert (TARGET_CPU_ZARCH
);
3351 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == PLUS
3352 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST_INT
)
3354 new = XEXP (XEXP (addr
, 0), 0);
3355 if (GET_CODE (new) != SYMBOL_REF
)
3356 new = gen_rtx_CONST (Pmode
, new);
3358 new = legitimize_tls_address (new, reg
);
3359 new = plus_constant (new, INTVAL (XEXP (XEXP (addr
, 0), 1)));
3360 new = force_operand (new, 0);
3364 gcc_unreachable (); /* for now ... */
3369 /* Emit insns to move operands[1] into operands[0]. */
3372 emit_symbolic_move (rtx
*operands
)
3374 rtx temp
= no_new_pseudos
? operands
[0] : gen_reg_rtx (Pmode
);
3376 if (GET_CODE (operands
[0]) == MEM
)
3377 operands
[1] = force_reg (Pmode
, operands
[1]);
3378 else if (TLS_SYMBOLIC_CONST (operands
[1]))
3379 operands
[1] = legitimize_tls_address (operands
[1], temp
);
3381 operands
[1] = legitimize_pic_address (operands
[1], temp
);
3384 /* Try machine-dependent ways of modifying an illegitimate address X
3385 to be legitimate. If we find one, return the new, valid address.
3387 OLDX is the address as it was before break_out_memory_refs was called.
3388 In some cases it is useful to look at this to decide what needs to be done.
3390 MODE is the mode of the operand pointed to by X.
3392 When -fpic is used, special handling is needed for symbolic references.
3393 See comments by legitimize_pic_address for details. */
3396 legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3397 enum machine_mode mode ATTRIBUTE_UNUSED
)
3399 rtx constant_term
= const0_rtx
;
3401 if (TLS_SYMBOLIC_CONST (x
))
3403 x
= legitimize_tls_address (x
, 0);
3405 if (legitimate_address_p (mode
, x
, FALSE
))
3408 else if (GET_CODE (x
) == PLUS
3409 && (TLS_SYMBOLIC_CONST (XEXP (x
, 0))
3410 || TLS_SYMBOLIC_CONST (XEXP (x
, 1))))
3416 if (SYMBOLIC_CONST (x
)
3417 || (GET_CODE (x
) == PLUS
3418 && (SYMBOLIC_CONST (XEXP (x
, 0))
3419 || SYMBOLIC_CONST (XEXP (x
, 1)))))
3420 x
= legitimize_pic_address (x
, 0);
3422 if (legitimate_address_p (mode
, x
, FALSE
))
3426 x
= eliminate_constant_term (x
, &constant_term
);
3428 /* Optimize loading of large displacements by splitting them
3429 into the multiple of 4K and the rest; this allows the
3430 former to be CSE'd if possible.
3432 Don't do this if the displacement is added to a register
3433 pointing into the stack frame, as the offsets will
3434 change later anyway. */
3436 if (GET_CODE (constant_term
) == CONST_INT
3437 && !TARGET_LONG_DISPLACEMENT
3438 && !DISP_IN_RANGE (INTVAL (constant_term
))
3439 && !(REG_P (x
) && REGNO_PTR_FRAME_P (REGNO (x
))))
3441 HOST_WIDE_INT lower
= INTVAL (constant_term
) & 0xfff;
3442 HOST_WIDE_INT upper
= INTVAL (constant_term
) ^ lower
;
3444 rtx temp
= gen_reg_rtx (Pmode
);
3445 rtx val
= force_operand (GEN_INT (upper
), temp
);
3447 emit_move_insn (temp
, val
);
3449 x
= gen_rtx_PLUS (Pmode
, x
, temp
);
3450 constant_term
= GEN_INT (lower
);
3453 if (GET_CODE (x
) == PLUS
)
3455 if (GET_CODE (XEXP (x
, 0)) == REG
)
3457 rtx temp
= gen_reg_rtx (Pmode
);
3458 rtx val
= force_operand (XEXP (x
, 1), temp
);
3460 emit_move_insn (temp
, val
);
3462 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0), temp
);
3465 else if (GET_CODE (XEXP (x
, 1)) == REG
)
3467 rtx temp
= gen_reg_rtx (Pmode
);
3468 rtx val
= force_operand (XEXP (x
, 0), temp
);
3470 emit_move_insn (temp
, val
);
3472 x
= gen_rtx_PLUS (Pmode
, temp
, XEXP (x
, 1));
3476 if (constant_term
!= const0_rtx
)
3477 x
= gen_rtx_PLUS (Pmode
, x
, constant_term
);
3482 /* Try a machine-dependent way of reloading an illegitimate address AD
3483 operand. If we find one, push the reload and and return the new address.
3485 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3486 and TYPE is the reload type of the current reload. */
3489 legitimize_reload_address (rtx ad
, enum machine_mode mode ATTRIBUTE_UNUSED
,
3490 int opnum
, int type
)
3492 if (!optimize
|| TARGET_LONG_DISPLACEMENT
)
3495 if (GET_CODE (ad
) == PLUS
)
3497 rtx tem
= simplify_binary_operation (PLUS
, Pmode
,
3498 XEXP (ad
, 0), XEXP (ad
, 1));
3503 if (GET_CODE (ad
) == PLUS
3504 && GET_CODE (XEXP (ad
, 0)) == REG
3505 && GET_CODE (XEXP (ad
, 1)) == CONST_INT
3506 && !DISP_IN_RANGE (INTVAL (XEXP (ad
, 1))))
3508 HOST_WIDE_INT lower
= INTVAL (XEXP (ad
, 1)) & 0xfff;
3509 HOST_WIDE_INT upper
= INTVAL (XEXP (ad
, 1)) ^ lower
;
3512 cst
= GEN_INT (upper
);
3513 if (!legitimate_reload_constant_p (cst
))
3514 cst
= force_const_mem (Pmode
, cst
);
3516 tem
= gen_rtx_PLUS (Pmode
, XEXP (ad
, 0), cst
);
3517 new = gen_rtx_PLUS (Pmode
, tem
, GEN_INT (lower
));
3519 push_reload (XEXP (tem
, 1), 0, &XEXP (tem
, 1), 0,
3520 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
3521 opnum
, (enum reload_type
) type
);
3528 /* Emit code to move LEN bytes from DST to SRC. */
3531 s390_expand_movmem (rtx dst
, rtx src
, rtx len
)
3533 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
3535 if (INTVAL (len
) > 0)
3536 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (INTVAL (len
) - 1)));
3539 else if (TARGET_MVCLE
)
3541 emit_insn (gen_movmem_long (dst
, src
, convert_to_mode (Pmode
, len
, 1)));
3546 rtx dst_addr
, src_addr
, count
, blocks
, temp
;
3547 rtx loop_start_label
= gen_label_rtx ();
3548 rtx loop_end_label
= gen_label_rtx ();
3549 rtx end_label
= gen_label_rtx ();
3550 enum machine_mode mode
;
3552 mode
= GET_MODE (len
);
3553 if (mode
== VOIDmode
)
3556 dst_addr
= gen_reg_rtx (Pmode
);
3557 src_addr
= gen_reg_rtx (Pmode
);
3558 count
= gen_reg_rtx (mode
);
3559 blocks
= gen_reg_rtx (mode
);
3561 convert_move (count
, len
, 1);
3562 emit_cmp_and_jump_insns (count
, const0_rtx
,
3563 EQ
, NULL_RTX
, mode
, 1, end_label
);
3565 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
3566 emit_move_insn (src_addr
, force_operand (XEXP (src
, 0), NULL_RTX
));
3567 dst
= change_address (dst
, VOIDmode
, dst_addr
);
3568 src
= change_address (src
, VOIDmode
, src_addr
);
3570 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1, 0);
3572 emit_move_insn (count
, temp
);
3574 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1, 0);
3576 emit_move_insn (blocks
, temp
);
3578 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
3579 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
3581 emit_label (loop_start_label
);
3583 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (255)));
3584 s390_load_address (dst_addr
,
3585 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
3586 s390_load_address (src_addr
,
3587 gen_rtx_PLUS (Pmode
, src_addr
, GEN_INT (256)));
3589 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1, 0);
3591 emit_move_insn (blocks
, temp
);
3593 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
3594 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
3596 emit_jump (loop_start_label
);
3597 emit_label (loop_end_label
);
3599 emit_insn (gen_movmem_short (dst
, src
,
3600 convert_to_mode (Pmode
, count
, 1)));
3601 emit_label (end_label
);
3605 /* Emit code to set LEN bytes at DST to VAL.
3606 Make use of clrmem if VAL is zero. */
3609 s390_expand_setmem (rtx dst
, rtx len
, rtx val
)
3611 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) == 0)
3614 gcc_assert (GET_CODE (val
) == CONST_INT
|| GET_MODE (val
) == QImode
);
3616 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) > 0 && INTVAL (len
) <= 257)
3618 if (val
== const0_rtx
&& INTVAL (len
) <= 256)
3619 emit_insn (gen_clrmem_short (dst
, GEN_INT (INTVAL (len
) - 1)));
3622 /* Initialize memory by storing the first byte. */
3623 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
3625 if (INTVAL (len
) > 1)
3627 /* Initiate 1 byte overlap move.
3628 The first byte of DST is propagated through DSTP1.
3629 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
3630 DST is set to size 1 so the rest of the memory location
3631 does not count as source operand. */
3632 rtx dstp1
= adjust_address (dst
, VOIDmode
, 1);
3633 set_mem_size (dst
, const1_rtx
);
3635 emit_insn (gen_movmem_short (dstp1
, dst
,
3636 GEN_INT (INTVAL (len
) - 2)));
3641 else if (TARGET_MVCLE
)
3643 val
= force_not_mem (convert_modes (Pmode
, QImode
, val
, 1));
3644 emit_insn (gen_setmem_long (dst
, convert_to_mode (Pmode
, len
, 1), val
));
3649 rtx dst_addr
, src_addr
, count
, blocks
, temp
, dstp1
= NULL_RTX
;
3650 rtx loop_start_label
= gen_label_rtx ();
3651 rtx loop_end_label
= gen_label_rtx ();
3652 rtx end_label
= gen_label_rtx ();
3653 enum machine_mode mode
;
3655 mode
= GET_MODE (len
);
3656 if (mode
== VOIDmode
)
3659 dst_addr
= gen_reg_rtx (Pmode
);
3660 src_addr
= gen_reg_rtx (Pmode
);
3661 count
= gen_reg_rtx (mode
);
3662 blocks
= gen_reg_rtx (mode
);
3664 convert_move (count
, len
, 1);
3665 emit_cmp_and_jump_insns (count
, const0_rtx
,
3666 EQ
, NULL_RTX
, mode
, 1, end_label
);
3668 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
3669 dst
= change_address (dst
, VOIDmode
, dst_addr
);
3671 if (val
== const0_rtx
)
3672 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1, 0);
3675 dstp1
= adjust_address (dst
, VOIDmode
, 1);
3676 set_mem_size (dst
, const1_rtx
);
3678 /* Initialize memory by storing the first byte. */
3679 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
3681 /* If count is 1 we are done. */
3682 emit_cmp_and_jump_insns (count
, const1_rtx
,
3683 EQ
, NULL_RTX
, mode
, 1, end_label
);
3685 temp
= expand_binop (mode
, add_optab
, count
, GEN_INT (-2), count
, 1, 0);
3688 emit_move_insn (count
, temp
);
3690 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1, 0);
3692 emit_move_insn (blocks
, temp
);
3694 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
3695 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
3697 emit_label (loop_start_label
);
3699 if (val
== const0_rtx
)
3700 emit_insn (gen_clrmem_short (dst
, GEN_INT (255)));
3702 emit_insn (gen_movmem_short (dstp1
, dst
, GEN_INT (255)));
3703 s390_load_address (dst_addr
,
3704 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
3706 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1, 0);
3708 emit_move_insn (blocks
, temp
);
3710 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
3711 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
3713 emit_jump (loop_start_label
);
3714 emit_label (loop_end_label
);
3716 if (val
== const0_rtx
)
3717 emit_insn (gen_clrmem_short (dst
, convert_to_mode (Pmode
, count
, 1)));
3719 emit_insn (gen_movmem_short (dstp1
, dst
, convert_to_mode (Pmode
, count
, 1)));
3720 emit_label (end_label
);
3724 /* Emit code to compare LEN bytes at OP0 with those at OP1,
3725 and return the result in TARGET. */
3728 s390_expand_cmpmem (rtx target
, rtx op0
, rtx op1
, rtx len
)
3730 rtx ccreg
= gen_rtx_REG (CCUmode
, CC_REGNUM
);
3733 /* As the result of CMPINT is inverted compared to what we need,
3734 we have to swap the operands. */
3735 tmp
= op0
; op0
= op1
; op1
= tmp
;
3737 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
3739 if (INTVAL (len
) > 0)
3741 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (INTVAL (len
) - 1)));
3742 emit_insn (gen_cmpint (target
, ccreg
));
3745 emit_move_insn (target
, const0_rtx
);
3747 else if (TARGET_MVCLE
)
3749 emit_insn (gen_cmpmem_long (op0
, op1
, convert_to_mode (Pmode
, len
, 1)));
3750 emit_insn (gen_cmpint (target
, ccreg
));
3754 rtx addr0
, addr1
, count
, blocks
, temp
;
3755 rtx loop_start_label
= gen_label_rtx ();
3756 rtx loop_end_label
= gen_label_rtx ();
3757 rtx end_label
= gen_label_rtx ();
3758 enum machine_mode mode
;
3760 mode
= GET_MODE (len
);
3761 if (mode
== VOIDmode
)
3764 addr0
= gen_reg_rtx (Pmode
);
3765 addr1
= gen_reg_rtx (Pmode
);
3766 count
= gen_reg_rtx (mode
);
3767 blocks
= gen_reg_rtx (mode
);
3769 convert_move (count
, len
, 1);
3770 emit_cmp_and_jump_insns (count
, const0_rtx
,
3771 EQ
, NULL_RTX
, mode
, 1, end_label
);
3773 emit_move_insn (addr0
, force_operand (XEXP (op0
, 0), NULL_RTX
));
3774 emit_move_insn (addr1
, force_operand (XEXP (op1
, 0), NULL_RTX
));
3775 op0
= change_address (op0
, VOIDmode
, addr0
);
3776 op1
= change_address (op1
, VOIDmode
, addr1
);
3778 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1, 0);
3780 emit_move_insn (count
, temp
);
3782 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1, 0);
3784 emit_move_insn (blocks
, temp
);
3786 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
3787 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
3789 emit_label (loop_start_label
);
3791 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (255)));
3792 temp
= gen_rtx_NE (VOIDmode
, ccreg
, const0_rtx
);
3793 temp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, temp
,
3794 gen_rtx_LABEL_REF (VOIDmode
, end_label
), pc_rtx
);
3795 temp
= gen_rtx_SET (VOIDmode
, pc_rtx
, temp
);
3796 emit_jump_insn (temp
);
3798 s390_load_address (addr0
,
3799 gen_rtx_PLUS (Pmode
, addr0
, GEN_INT (256)));
3800 s390_load_address (addr1
,
3801 gen_rtx_PLUS (Pmode
, addr1
, GEN_INT (256)));
3803 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1, 0);
3805 emit_move_insn (blocks
, temp
);
3807 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
3808 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
3810 emit_jump (loop_start_label
);
3811 emit_label (loop_end_label
);
3813 emit_insn (gen_cmpmem_short (op0
, op1
,
3814 convert_to_mode (Pmode
, count
, 1)));
3815 emit_label (end_label
);
3817 emit_insn (gen_cmpint (target
, ccreg
));
3822 /* Expand conditional increment or decrement using alc/slb instructions.
3823 Should generate code setting DST to either SRC or SRC + INCREMENT,
3824 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
3825 Returns true if successful, false otherwise.
3827 That makes it possible to implement some if-constructs without jumps e.g.:
3828 (borrow = CC0 | CC1 and carry = CC2 | CC3)
3829 unsigned int a, b, c;
3830 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
3831 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
3832 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
3833 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
3835 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
3836 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
3837 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
3838 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
3839 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
3842 s390_expand_addcc (enum rtx_code cmp_code
, rtx cmp_op0
, rtx cmp_op1
,
3843 rtx dst
, rtx src
, rtx increment
)
3845 enum machine_mode cmp_mode
;
3846 enum machine_mode cc_mode
;
3852 if ((GET_MODE (cmp_op0
) == SImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
3853 && (GET_MODE (cmp_op1
) == SImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
3855 else if ((GET_MODE (cmp_op0
) == DImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
3856 && (GET_MODE (cmp_op1
) == DImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
3861 /* Try ADD LOGICAL WITH CARRY. */
3862 if (increment
== const1_rtx
)
3864 /* Determine CC mode to use. */
3865 if (cmp_code
== EQ
|| cmp_code
== NE
)
3867 if (cmp_op1
!= const0_rtx
)
3869 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
3870 NULL_RTX
, 0, OPTAB_WIDEN
);
3871 cmp_op1
= const0_rtx
;
3874 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
3877 if (cmp_code
== LTU
|| cmp_code
== LEU
)
3882 cmp_code
= swap_condition (cmp_code
);
3899 /* Emit comparison instruction pattern. */
3900 if (!register_operand (cmp_op0
, cmp_mode
))
3901 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
3903 insn
= gen_rtx_SET (VOIDmode
, gen_rtx_REG (cc_mode
, CC_REGNUM
),
3904 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
3905 /* We use insn_invalid_p here to add clobbers if required. */
3906 ret
= insn_invalid_p (emit_insn (insn
));
3909 /* Emit ALC instruction pattern. */
3910 op_res
= gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
3911 gen_rtx_REG (cc_mode
, CC_REGNUM
),
3914 if (src
!= const0_rtx
)
3916 if (!register_operand (src
, GET_MODE (dst
)))
3917 src
= force_reg (GET_MODE (dst
), src
);
3919 src
= gen_rtx_PLUS (GET_MODE (dst
), src
, const0_rtx
);
3920 op_res
= gen_rtx_PLUS (GET_MODE (dst
), src
, op_res
);
3923 p
= rtvec_alloc (2);
3925 gen_rtx_SET (VOIDmode
, dst
, op_res
);
3927 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
3928 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
3933 /* Try SUBTRACT LOGICAL WITH BORROW. */
3934 if (increment
== constm1_rtx
)
3936 /* Determine CC mode to use. */
3937 if (cmp_code
== EQ
|| cmp_code
== NE
)
3939 if (cmp_op1
!= const0_rtx
)
3941 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
3942 NULL_RTX
, 0, OPTAB_WIDEN
);
3943 cmp_op1
= const0_rtx
;
3946 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
3949 if (cmp_code
== GTU
|| cmp_code
== GEU
)
3954 cmp_code
= swap_condition (cmp_code
);
3971 /* Emit comparison instruction pattern. */
3972 if (!register_operand (cmp_op0
, cmp_mode
))
3973 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
3975 insn
= gen_rtx_SET (VOIDmode
, gen_rtx_REG (cc_mode
, CC_REGNUM
),
3976 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
3977 /* We use insn_invalid_p here to add clobbers if required. */
3978 ret
= insn_invalid_p (emit_insn (insn
));
3981 /* Emit SLB instruction pattern. */
3982 if (!register_operand (src
, GET_MODE (dst
)))
3983 src
= force_reg (GET_MODE (dst
), src
);
3985 op_res
= gen_rtx_MINUS (GET_MODE (dst
),
3986 gen_rtx_MINUS (GET_MODE (dst
), src
, const0_rtx
),
3987 gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
3988 gen_rtx_REG (cc_mode
, CC_REGNUM
),
3990 p
= rtvec_alloc (2);
3992 gen_rtx_SET (VOIDmode
, dst
, op_res
);
3994 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
3995 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
4003 /* Expand code for the insv template. Return true if successful, false else. */
4006 s390_expand_insv (rtx dest
, rtx op1
, rtx op2
, rtx src
)
4008 int bitsize
= INTVAL (op1
);
4009 int bitpos
= INTVAL (op2
);
4011 /* We need byte alignment. */
4012 if (bitsize
% BITS_PER_UNIT
)
4016 && memory_operand (dest
, VOIDmode
)
4017 && (register_operand (src
, word_mode
)
4018 || const_int_operand (src
, VOIDmode
)))
4020 /* Emit standard pattern if possible. */
4021 enum machine_mode mode
= smallest_mode_for_size (bitsize
, MODE_INT
);
4022 if (GET_MODE_BITSIZE (mode
) == bitsize
)
4023 emit_move_insn (adjust_address (dest
, mode
, 0), gen_lowpart (mode
, src
));
4025 /* (set (ze (mem)) (const_int)). */
4026 else if (const_int_operand (src
, VOIDmode
))
4028 int size
= bitsize
/ BITS_PER_UNIT
;
4029 rtx src_mem
= adjust_address (force_const_mem (word_mode
, src
), BLKmode
,
4030 GET_MODE_SIZE (word_mode
) - size
);
4032 dest
= adjust_address (dest
, BLKmode
, 0);
4033 set_mem_size (dest
, GEN_INT (size
));
4034 s390_expand_movmem (dest
, src_mem
, GEN_INT (size
));
4037 /* (set (ze (mem)) (reg)). */
4038 else if (register_operand (src
, word_mode
))
4040 if (bitsize
<= GET_MODE_BITSIZE (SImode
))
4041 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
, op1
,
4045 /* Emit st,stcmh sequence. */
4046 int stcmh_width
= bitsize
- GET_MODE_BITSIZE (SImode
);
4047 int size
= stcmh_width
/ BITS_PER_UNIT
;
4049 emit_move_insn (adjust_address (dest
, SImode
, size
),
4050 gen_lowpart (SImode
, src
));
4051 set_mem_size (dest
, GEN_INT (size
));
4052 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
, GEN_INT
4053 (stcmh_width
), const0_rtx
),
4054 gen_rtx_LSHIFTRT (word_mode
, src
, GEN_INT
4055 (GET_MODE_BITSIZE (SImode
))));
4064 /* (set (ze (reg)) (const_int)). */
4066 && register_operand (dest
, word_mode
)
4067 && (bitpos
% 16) == 0
4068 && (bitsize
% 16) == 0
4069 && const_int_operand (src
, VOIDmode
))
4071 HOST_WIDE_INT val
= INTVAL (src
);
4072 int regpos
= bitpos
+ bitsize
;
4074 while (regpos
> bitpos
)
4076 enum machine_mode putmode
;
4079 if (TARGET_EXTIMM
&& (regpos
% 32 == 0) && (regpos
>= bitpos
+ 32))
4084 putsize
= GET_MODE_BITSIZE (putmode
);
4086 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
,
4089 gen_int_mode (val
, putmode
));
4092 gcc_assert (regpos
== bitpos
);
4099 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4100 register that holds VAL of mode MODE shifted by COUNT bits. */
4103 s390_expand_mask_and_shift (rtx val
, enum machine_mode mode
, rtx count
)
4105 val
= expand_simple_binop (SImode
, AND
, val
, GEN_INT (GET_MODE_MASK (mode
)),
4106 NULL_RTX
, 1, OPTAB_DIRECT
);
4107 return expand_simple_binop (SImode
, ASHIFT
, val
, count
,
4108 NULL_RTX
, 1, OPTAB_DIRECT
);
4111 /* Structure to hold the initial parameters for a compare_and_swap operation
4112 in HImode and QImode. */
4114 struct alignment_context
4116 rtx memsi
; /* SI aligned memory location. */
4117 rtx shift
; /* Bit offset with regard to lsb. */
4118 rtx modemask
; /* Mask of the HQImode shifted by SHIFT bits. */
4119 rtx modemaski
; /* ~modemask */
4120 bool aligned
; /* True if memory is aligned, false else. */
4123 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4124 structure AC for transparent simplifying, if the memory alignment is known
4125 to be at least 32bit. MEM is the memory location for the actual operation
4126 and MODE its mode. */
4129 init_alignment_context (struct alignment_context
*ac
, rtx mem
,
4130 enum machine_mode mode
)
4132 ac
->shift
= GEN_INT (GET_MODE_SIZE (SImode
) - GET_MODE_SIZE (mode
));
4133 ac
->aligned
= (MEM_ALIGN (mem
) >= GET_MODE_BITSIZE (SImode
));
4136 ac
->memsi
= adjust_address (mem
, SImode
, 0); /* Memory is aligned. */
4139 /* Alignment is unknown. */
4140 rtx byteoffset
, addr
, align
;
4142 /* Force the address into a register. */
4143 addr
= force_reg (Pmode
, XEXP (mem
, 0));
4145 /* Align it to SImode. */
4146 align
= expand_simple_binop (Pmode
, AND
, addr
,
4147 GEN_INT (-GET_MODE_SIZE (SImode
)),
4148 NULL_RTX
, 1, OPTAB_DIRECT
);
4150 ac
->memsi
= gen_rtx_MEM (SImode
, align
);
4151 MEM_VOLATILE_P (ac
->memsi
) = MEM_VOLATILE_P (mem
);
4152 set_mem_alias_set (ac
->memsi
, ALIAS_SET_MEMORY_BARRIER
);
4153 set_mem_align (ac
->memsi
, GET_MODE_BITSIZE (SImode
));
4155 /* Calculate shiftcount. */
4156 byteoffset
= expand_simple_binop (Pmode
, AND
, addr
,
4157 GEN_INT (GET_MODE_SIZE (SImode
) - 1),
4158 NULL_RTX
, 1, OPTAB_DIRECT
);
4159 /* As we already have some offset, evaluate the remaining distance. */
4160 ac
->shift
= expand_simple_binop (SImode
, MINUS
, ac
->shift
, byteoffset
,
4161 NULL_RTX
, 1, OPTAB_DIRECT
);
4164 /* Shift is the byte count, but we need the bitcount. */
4165 ac
->shift
= expand_simple_binop (SImode
, MULT
, ac
->shift
, GEN_INT (BITS_PER_UNIT
),
4166 NULL_RTX
, 1, OPTAB_DIRECT
);
4167 /* Calculate masks. */
4168 ac
->modemask
= expand_simple_binop (SImode
, ASHIFT
,
4169 GEN_INT (GET_MODE_MASK (mode
)), ac
->shift
,
4170 NULL_RTX
, 1, OPTAB_DIRECT
);
4171 ac
->modemaski
= expand_simple_unop (SImode
, NOT
, ac
->modemask
, NULL_RTX
, 1);
4174 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4175 the memory location, CMP the old value to compare MEM with and NEW the value
4176 to set if CMP == MEM.
4177 CMP is never in memory for compare_and_swap_cc because
4178 expand_bool_compare_and_swap puts it into a register for later compare. */
4181 s390_expand_cs_hqi (enum machine_mode mode
, rtx target
, rtx mem
, rtx cmp
, rtx
new)
4183 struct alignment_context ac
;
4184 rtx cmpv
, newv
, val
, resv
, cc
;
4185 rtx res
= gen_reg_rtx (SImode
);
4186 rtx csloop
= gen_label_rtx ();
4187 rtx csend
= gen_label_rtx ();
4189 gcc_assert (register_operand (target
, VOIDmode
));
4190 gcc_assert (MEM_P (mem
));
4192 init_alignment_context (&ac
, mem
, mode
);
4194 /* Shift the values to the correct bit positions. */
4195 if (!(ac
.aligned
&& MEM_P (cmp
)))
4196 cmp
= s390_expand_mask_and_shift (cmp
, mode
, ac
.shift
);
4197 if (!(ac
.aligned
&& MEM_P (new)))
4198 new = s390_expand_mask_and_shift (new, mode
, ac
.shift
);
4200 /* Load full word. Subsequent loads are performed by CS. */
4201 val
= expand_simple_binop (SImode
, AND
, ac
.memsi
, ac
.modemaski
,
4202 NULL_RTX
, 1, OPTAB_DIRECT
);
4204 /* Start CS loop. */
4205 emit_label (csloop
);
4206 /* val = "<mem>00..0<mem>"
4207 * cmp = "00..0<cmp>00..0"
4208 * new = "00..0<new>00..0"
4211 /* Patch cmp and new with val at correct position. */
4212 if (ac
.aligned
&& MEM_P (cmp
))
4214 cmpv
= force_reg (SImode
, val
);
4215 store_bit_field (cmpv
, GET_MODE_BITSIZE (mode
), 0, SImode
, cmp
);
4218 cmpv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, cmp
, val
,
4219 NULL_RTX
, 1, OPTAB_DIRECT
));
4220 if (ac
.aligned
&& MEM_P (new))
4222 newv
= force_reg (SImode
, val
);
4223 store_bit_field (newv
, GET_MODE_BITSIZE (mode
), 0, SImode
, new);
4226 newv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, new, val
,
4227 NULL_RTX
, 1, OPTAB_DIRECT
));
4229 /* Jump to end if we're done (likely?). */
4230 s390_emit_jump (csend
, s390_emit_compare_and_swap (EQ
, res
, ac
.memsi
,
4233 /* Check for changes outside mode. */
4234 resv
= expand_simple_binop (SImode
, AND
, res
, ac
.modemaski
,
4235 NULL_RTX
, 1, OPTAB_DIRECT
);
4236 cc
= s390_emit_compare (NE
, resv
, val
);
4237 emit_move_insn (val
, resv
);
4238 /* Loop internal if so. */
4239 s390_emit_jump (csloop
, cc
);
4243 /* Return the correct part of the bitfield. */
4244 convert_move (target
, expand_simple_binop (SImode
, LSHIFTRT
, res
, ac
.shift
,
4245 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
4248 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4249 and VAL the value to play with. If AFTER is true then store the value
4250 MEM holds after the operation, if AFTER is false then store the value MEM
4251 holds before the operation. If TARGET is zero then discard that value, else
4252 store it to TARGET. */
4255 s390_expand_atomic (enum machine_mode mode
, enum rtx_code code
,
4256 rtx target
, rtx mem
, rtx val
, bool after
)
4258 struct alignment_context ac
;
4260 rtx
new = gen_reg_rtx (SImode
);
4261 rtx orig
= gen_reg_rtx (SImode
);
4262 rtx csloop
= gen_label_rtx ();
4264 gcc_assert (!target
|| register_operand (target
, VOIDmode
));
4265 gcc_assert (MEM_P (mem
));
4267 init_alignment_context (&ac
, mem
, mode
);
4269 /* Shift val to the correct bit positions.
4270 Preserve "icm", but prevent "ex icm". */
4271 if (!(ac
.aligned
&& code
== SET
&& MEM_P (val
)))
4272 val
= s390_expand_mask_and_shift (val
, mode
, ac
.shift
);
4274 /* Further preparation insns. */
4275 if (code
== PLUS
|| code
== MINUS
)
4276 emit_move_insn (orig
, val
);
4277 else if (code
== MULT
|| code
== AND
) /* val = "11..1<val>11..1" */
4278 val
= expand_simple_binop (SImode
, XOR
, val
, ac
.modemaski
,
4279 NULL_RTX
, 1, OPTAB_DIRECT
);
4281 /* Load full word. Subsequent loads are performed by CS. */
4282 cmp
= force_reg (SImode
, ac
.memsi
);
4284 /* Start CS loop. */
4285 emit_label (csloop
);
4286 emit_move_insn (new, cmp
);
4288 /* Patch new with val at correct position. */
4293 val
= expand_simple_binop (SImode
, code
, new, orig
,
4294 NULL_RTX
, 1, OPTAB_DIRECT
);
4295 val
= expand_simple_binop (SImode
, AND
, val
, ac
.modemask
,
4296 NULL_RTX
, 1, OPTAB_DIRECT
);
4299 if (ac
.aligned
&& MEM_P (val
))
4300 store_bit_field (new, GET_MODE_BITSIZE (mode
), 0, SImode
, val
);
4303 new = expand_simple_binop (SImode
, AND
, new, ac
.modemaski
,
4304 NULL_RTX
, 1, OPTAB_DIRECT
);
4305 new = expand_simple_binop (SImode
, IOR
, new, val
,
4306 NULL_RTX
, 1, OPTAB_DIRECT
);
4312 new = expand_simple_binop (SImode
, code
, new, val
,
4313 NULL_RTX
, 1, OPTAB_DIRECT
);
4315 case MULT
: /* NAND */
4316 new = expand_simple_binop (SImode
, XOR
, new, ac
.modemask
,
4317 NULL_RTX
, 1, OPTAB_DIRECT
);
4318 new = expand_simple_binop (SImode
, AND
, new, val
,
4319 NULL_RTX
, 1, OPTAB_DIRECT
);
4325 s390_emit_jump (csloop
, s390_emit_compare_and_swap (NE
, cmp
,
4326 ac
.memsi
, cmp
, new));
4328 /* Return the correct part of the bitfield. */
4330 convert_move (target
, expand_simple_binop (SImode
, LSHIFTRT
,
4331 after
? new : cmp
, ac
.shift
,
4332 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
4335 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4336 We need to emit DTP-relative relocations. */
4338 static void s390_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
4341 s390_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4346 fputs ("\t.long\t", file
);
4349 fputs ("\t.quad\t", file
);
4354 output_addr_const (file
, x
);
4355 fputs ("@DTPOFF", file
);
4358 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4359 /* Implement TARGET_MANGLE_FUNDAMENTAL_TYPE. */
4362 s390_mangle_fundamental_type (tree type
)
4364 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
4365 && TARGET_LONG_DOUBLE_128
)
4368 /* For all other types, use normal C++ mangling. */
4373 /* In the name of slightly smaller debug output, and to cater to
4374 general assembler lossage, recognize various UNSPEC sequences
4375 and turn them back into a direct symbol reference. */
4378 s390_delegitimize_address (rtx orig_x
)
4382 if (GET_CODE (x
) != MEM
)
4386 if (GET_CODE (x
) == PLUS
4387 && GET_CODE (XEXP (x
, 1)) == CONST
4388 && GET_CODE (XEXP (x
, 0)) == REG
4389 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
)
4391 y
= XEXP (XEXP (x
, 1), 0);
4392 if (GET_CODE (y
) == UNSPEC
4393 && XINT (y
, 1) == UNSPEC_GOT
)
4394 return XVECEXP (y
, 0, 0);
4398 if (GET_CODE (x
) == CONST
)
4401 if (GET_CODE (y
) == UNSPEC
4402 && XINT (y
, 1) == UNSPEC_GOTENT
)
4403 return XVECEXP (y
, 0, 0);
4410 /* Output operand OP to stdio stream FILE.
4411 OP is an address (register + offset) which is not used to address data;
4412 instead the rightmost bits are interpreted as the value. */
4415 print_shift_count_operand (FILE *file
, rtx op
)
4417 HOST_WIDE_INT offset
;
4420 /* Extract base register and offset. */
4421 if (!s390_decompose_shift_count (op
, &base
, &offset
))
4427 gcc_assert (GET_CODE (base
) == REG
);
4428 gcc_assert (REGNO (base
) < FIRST_PSEUDO_REGISTER
);
4429 gcc_assert (REGNO_REG_CLASS (REGNO (base
)) == ADDR_REGS
);
4432 /* Offsets are constricted to twelve bits. */
4433 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
& ((1 << 12) - 1));
4435 fprintf (file
, "(%s)", reg_names
[REGNO (base
)]);
4438 /* See 'get_some_local_dynamic_name'. */
4441 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
4445 if (GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
4447 x
= get_pool_constant (x
);
4448 return for_each_rtx (&x
, get_some_local_dynamic_name_1
, 0);
4451 if (GET_CODE (x
) == SYMBOL_REF
4452 && tls_symbolic_operand (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
4454 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
4461 /* Locate some local-dynamic symbol still in use by this function
4462 so that we can print its name in local-dynamic base patterns. */
4465 get_some_local_dynamic_name (void)
4469 if (cfun
->machine
->some_ld_name
)
4470 return cfun
->machine
->some_ld_name
;
4472 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
4474 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
4475 return cfun
->machine
->some_ld_name
;
4480 /* Output machine-dependent UNSPECs occurring in address constant X
4481 in assembler syntax to stdio stream FILE. Returns true if the
4482 constant X could be recognized, false otherwise. */
4485 s390_output_addr_const_extra (FILE *file
, rtx x
)
4487 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 1)
4488 switch (XINT (x
, 1))
4491 output_addr_const (file
, XVECEXP (x
, 0, 0));
4492 fprintf (file
, "@GOTENT");
4495 output_addr_const (file
, XVECEXP (x
, 0, 0));
4496 fprintf (file
, "@GOT");
4499 output_addr_const (file
, XVECEXP (x
, 0, 0));
4500 fprintf (file
, "@GOTOFF");
4503 output_addr_const (file
, XVECEXP (x
, 0, 0));
4504 fprintf (file
, "@PLT");
4507 output_addr_const (file
, XVECEXP (x
, 0, 0));
4508 fprintf (file
, "@PLTOFF");
4511 output_addr_const (file
, XVECEXP (x
, 0, 0));
4512 fprintf (file
, "@TLSGD");
4515 assemble_name (file
, get_some_local_dynamic_name ());
4516 fprintf (file
, "@TLSLDM");
4519 output_addr_const (file
, XVECEXP (x
, 0, 0));
4520 fprintf (file
, "@DTPOFF");
4523 output_addr_const (file
, XVECEXP (x
, 0, 0));
4524 fprintf (file
, "@NTPOFF");
4526 case UNSPEC_GOTNTPOFF
:
4527 output_addr_const (file
, XVECEXP (x
, 0, 0));
4528 fprintf (file
, "@GOTNTPOFF");
4530 case UNSPEC_INDNTPOFF
:
4531 output_addr_const (file
, XVECEXP (x
, 0, 0));
4532 fprintf (file
, "@INDNTPOFF");
4539 /* Output address operand ADDR in assembler syntax to
4540 stdio stream FILE. */
4543 print_operand_address (FILE *file
, rtx addr
)
4545 struct s390_address ad
;
4547 if (!s390_decompose_address (addr
, &ad
)
4548 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
4549 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
4550 output_operand_lossage ("cannot decompose address");
4553 output_addr_const (file
, ad
.disp
);
4555 fprintf (file
, "0");
4557 if (ad
.base
&& ad
.indx
)
4558 fprintf (file
, "(%s,%s)", reg_names
[REGNO (ad
.indx
)],
4559 reg_names
[REGNO (ad
.base
)]);
4561 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
4564 /* Output operand X in assembler syntax to stdio stream FILE.
4565 CODE specified the format flag. The following format flags
4568 'C': print opcode suffix for branch condition.
4569 'D': print opcode suffix for inverse branch condition.
4570 'J': print tls_load/tls_gdcall/tls_ldcall suffix
4571 'G': print the size of the operand in bytes.
4572 'O': print only the displacement of a memory reference.
4573 'R': print only the base register of a memory reference.
4574 'S': print S-type memory reference (base+displacement).
4575 'N': print the second word of a DImode operand.
4576 'M': print the second word of a TImode operand.
4577 'Y': print shift count operand.
4579 'b': print integer X as if it's an unsigned byte.
4580 'x': print integer X as if it's an unsigned halfword.
4581 'h': print integer X as if it's a signed halfword.
4582 'i': print the first nonzero HImode part of X.
4583 'j': print the first HImode part unequal to -1 of X.
4584 'k': print the first nonzero SImode part of X.
4585 'm': print the first SImode part unequal to -1 of X.
4586 'o': print integer X as if it's an unsigned 32bit word. */
4589 print_operand (FILE *file
, rtx x
, int code
)
4594 fprintf (file
, s390_branch_condition_mnemonic (x
, FALSE
));
4598 fprintf (file
, s390_branch_condition_mnemonic (x
, TRUE
));
4602 if (GET_CODE (x
) == SYMBOL_REF
)
4604 fprintf (file
, "%s", ":tls_load:");
4605 output_addr_const (file
, x
);
4607 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD
)
4609 fprintf (file
, "%s", ":tls_gdcall:");
4610 output_addr_const (file
, XVECEXP (x
, 0, 0));
4612 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM
)
4614 fprintf (file
, "%s", ":tls_ldcall:");
4615 assemble_name (file
, get_some_local_dynamic_name ());
4622 fprintf (file
, "%u", GET_MODE_SIZE (GET_MODE (x
)));
4627 struct s390_address ad
;
4630 gcc_assert (GET_CODE (x
) == MEM
);
4631 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
4633 gcc_assert (!ad
.base
|| REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)));
4634 gcc_assert (!ad
.indx
);
4637 output_addr_const (file
, ad
.disp
);
4639 fprintf (file
, "0");
4645 struct s390_address ad
;
4648 gcc_assert (GET_CODE (x
) == MEM
);
4649 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
4651 gcc_assert (!ad
.base
|| REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)));
4652 gcc_assert (!ad
.indx
);
4655 fprintf (file
, "%s", reg_names
[REGNO (ad
.base
)]);
4657 fprintf (file
, "0");
4663 struct s390_address ad
;
4666 gcc_assert (GET_CODE (x
) == MEM
);
4667 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
4669 gcc_assert (!ad
.base
|| REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)));
4670 gcc_assert (!ad
.indx
);
4673 output_addr_const (file
, ad
.disp
);
4675 fprintf (file
, "0");
4678 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
4683 if (GET_CODE (x
) == REG
)
4684 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
4685 else if (GET_CODE (x
) == MEM
)
4686 x
= change_address (x
, VOIDmode
, plus_constant (XEXP (x
, 0), 4));
4692 if (GET_CODE (x
) == REG
)
4693 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
4694 else if (GET_CODE (x
) == MEM
)
4695 x
= change_address (x
, VOIDmode
, plus_constant (XEXP (x
, 0), 8));
4701 print_shift_count_operand (file
, x
);
4705 switch (GET_CODE (x
))
4708 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
4712 output_address (XEXP (x
, 0));
4719 output_addr_const (file
, x
);
4724 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xff);
4725 else if (code
== 'x')
4726 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffff);
4727 else if (code
== 'h')
4728 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ((INTVAL (x
) & 0xffff) ^ 0x8000) - 0x8000);
4729 else if (code
== 'i')
4730 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
4731 s390_extract_part (x
, HImode
, 0));
4732 else if (code
== 'j')
4733 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
4734 s390_extract_part (x
, HImode
, -1));
4735 else if (code
== 'k')
4736 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
4737 s390_extract_part (x
, SImode
, 0));
4738 else if (code
== 'm')
4739 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
4740 s390_extract_part (x
, SImode
, -1));
4741 else if (code
== 'o')
4742 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffffffff);
4744 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
4748 gcc_assert (GET_MODE (x
) == VOIDmode
);
4750 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
) & 0xff);
4751 else if (code
== 'x')
4752 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
) & 0xffff);
4753 else if (code
== 'h')
4754 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ((CONST_DOUBLE_LOW (x
) & 0xffff) ^ 0x8000) - 0x8000);
4760 fatal_insn ("UNKNOWN in print_operand !?", x
);
4765 /* Target hook for assembling integer objects. We need to define it
4766 here to work a round a bug in some versions of GAS, which couldn't
4767 handle values smaller than INT_MIN when printed in decimal. */
4770 s390_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
4772 if (size
== 8 && aligned_p
4773 && GET_CODE (x
) == CONST_INT
&& INTVAL (x
) < INT_MIN
)
4775 fprintf (asm_out_file
, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX
"\n",
4779 return default_assemble_integer (x
, size
, aligned_p
);
4782 /* Returns true if register REGNO is used for forming
4783 a memory address in expression X. */
4786 reg_used_in_mem_p (int regno
, rtx x
)
4788 enum rtx_code code
= GET_CODE (x
);
4794 if (refers_to_regno_p (regno
, regno
+1,
4798 else if (code
== SET
4799 && GET_CODE (SET_DEST (x
)) == PC
)
4801 if (refers_to_regno_p (regno
, regno
+1,
4806 fmt
= GET_RTX_FORMAT (code
);
4807 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4810 && reg_used_in_mem_p (regno
, XEXP (x
, i
)))
4813 else if (fmt
[i
] == 'E')
4814 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
4815 if (reg_used_in_mem_p (regno
, XVECEXP (x
, i
, j
)))
4821 /* Returns true if expression DEP_RTX sets an address register
4822 used by instruction INSN to address memory. */
4825 addr_generation_dependency_p (rtx dep_rtx
, rtx insn
)
4829 if (GET_CODE (dep_rtx
) == INSN
)
4830 dep_rtx
= PATTERN (dep_rtx
);
4832 if (GET_CODE (dep_rtx
) == SET
)
4834 target
= SET_DEST (dep_rtx
);
4835 if (GET_CODE (target
) == STRICT_LOW_PART
)
4836 target
= XEXP (target
, 0);
4837 while (GET_CODE (target
) == SUBREG
)
4838 target
= SUBREG_REG (target
);
4840 if (GET_CODE (target
) == REG
)
4842 int regno
= REGNO (target
);
4844 if (s390_safe_attr_type (insn
) == TYPE_LA
)
4846 pat
= PATTERN (insn
);
4847 if (GET_CODE (pat
) == PARALLEL
)
4849 gcc_assert (XVECLEN (pat
, 0) == 2);
4850 pat
= XVECEXP (pat
, 0, 0);
4852 gcc_assert (GET_CODE (pat
) == SET
);
4853 return refers_to_regno_p (regno
, regno
+1, SET_SRC (pat
), 0);
4855 else if (get_attr_atype (insn
) == ATYPE_AGEN
)
4856 return reg_used_in_mem_p (regno
, PATTERN (insn
));
4862 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
4865 s390_agen_dep_p (rtx dep_insn
, rtx insn
)
4867 rtx dep_rtx
= PATTERN (dep_insn
);
4870 if (GET_CODE (dep_rtx
) == SET
4871 && addr_generation_dependency_p (dep_rtx
, insn
))
4873 else if (GET_CODE (dep_rtx
) == PARALLEL
)
4875 for (i
= 0; i
< XVECLEN (dep_rtx
, 0); i
++)
4877 if (addr_generation_dependency_p (XVECEXP (dep_rtx
, 0, i
), insn
))
4884 /* A C statement (sans semicolon) to update the integer scheduling priority
4885 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
4886 reduce the priority to execute INSN later. Do not define this macro if
4887 you do not need to adjust the scheduling priorities of insns.
4889 A STD instruction should be scheduled earlier,
4890 in order to use the bypass. */
4893 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
4895 if (! INSN_P (insn
))
4898 if (s390_tune
!= PROCESSOR_2084_Z990
4899 && s390_tune
!= PROCESSOR_2094_Z9_109
)
4902 switch (s390_safe_attr_type (insn
))
4906 priority
= priority
<< 3;
4910 priority
= priority
<< 1;
4918 /* The number of instructions that can be issued per cycle. */
4921 s390_issue_rate (void)
4923 if (s390_tune
== PROCESSOR_2084_Z990
4924 || s390_tune
== PROCESSOR_2094_Z9_109
)
4930 s390_first_cycle_multipass_dfa_lookahead (void)
4936 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
4937 Fix up MEMs as required. */
4940 annotate_constant_pool_refs (rtx
*x
)
4945 gcc_assert (GET_CODE (*x
) != SYMBOL_REF
4946 || !CONSTANT_POOL_ADDRESS_P (*x
));
4948 /* Literal pool references can only occur inside a MEM ... */
4949 if (GET_CODE (*x
) == MEM
)
4951 rtx memref
= XEXP (*x
, 0);
4953 if (GET_CODE (memref
) == SYMBOL_REF
4954 && CONSTANT_POOL_ADDRESS_P (memref
))
4956 rtx base
= cfun
->machine
->base_reg
;
4957 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, memref
, base
),
4960 *x
= replace_equiv_address (*x
, addr
);
4964 if (GET_CODE (memref
) == CONST
4965 && GET_CODE (XEXP (memref
, 0)) == PLUS
4966 && GET_CODE (XEXP (XEXP (memref
, 0), 1)) == CONST_INT
4967 && GET_CODE (XEXP (XEXP (memref
, 0), 0)) == SYMBOL_REF
4968 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref
, 0), 0)))
4970 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (memref
, 0), 1));
4971 rtx sym
= XEXP (XEXP (memref
, 0), 0);
4972 rtx base
= cfun
->machine
->base_reg
;
4973 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
4976 *x
= replace_equiv_address (*x
, plus_constant (addr
, off
));
4981 /* ... or a load-address type pattern. */
4982 if (GET_CODE (*x
) == SET
)
4984 rtx addrref
= SET_SRC (*x
);
4986 if (GET_CODE (addrref
) == SYMBOL_REF
4987 && CONSTANT_POOL_ADDRESS_P (addrref
))
4989 rtx base
= cfun
->machine
->base_reg
;
4990 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, addrref
, base
),
4993 SET_SRC (*x
) = addr
;
4997 if (GET_CODE (addrref
) == CONST
4998 && GET_CODE (XEXP (addrref
, 0)) == PLUS
4999 && GET_CODE (XEXP (XEXP (addrref
, 0), 1)) == CONST_INT
5000 && GET_CODE (XEXP (XEXP (addrref
, 0), 0)) == SYMBOL_REF
5001 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref
, 0), 0)))
5003 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (addrref
, 0), 1));
5004 rtx sym
= XEXP (XEXP (addrref
, 0), 0);
5005 rtx base
= cfun
->machine
->base_reg
;
5006 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
5009 SET_SRC (*x
) = plus_constant (addr
, off
);
5014 /* Annotate LTREL_BASE as well. */
5015 if (GET_CODE (*x
) == UNSPEC
5016 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
5018 rtx base
= cfun
->machine
->base_reg
;
5019 *x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XVECEXP (*x
, 0, 0), base
),
5024 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5025 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5029 annotate_constant_pool_refs (&XEXP (*x
, i
));
5031 else if (fmt
[i
] == 'E')
5033 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
5034 annotate_constant_pool_refs (&XVECEXP (*x
, i
, j
));
5039 /* Split all branches that exceed the maximum distance.
5040 Returns true if this created a new literal pool entry. */
5043 s390_split_branches (void)
5045 rtx temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
5046 int new_literal
= 0, ret
;
5047 rtx insn
, pat
, tmp
, target
;
5050 /* We need correct insn addresses. */
5052 shorten_branches (get_insns ());
5054 /* Find all branches that exceed 64KB, and split them. */
5056 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5058 if (GET_CODE (insn
) != JUMP_INSN
)
5061 pat
= PATTERN (insn
);
5062 if (GET_CODE (pat
) == PARALLEL
&& XVECLEN (pat
, 0) > 2)
5063 pat
= XVECEXP (pat
, 0, 0);
5064 if (GET_CODE (pat
) != SET
|| SET_DEST (pat
) != pc_rtx
)
5067 if (GET_CODE (SET_SRC (pat
)) == LABEL_REF
)
5069 label
= &SET_SRC (pat
);
5071 else if (GET_CODE (SET_SRC (pat
)) == IF_THEN_ELSE
)
5073 if (GET_CODE (XEXP (SET_SRC (pat
), 1)) == LABEL_REF
)
5074 label
= &XEXP (SET_SRC (pat
), 1);
5075 else if (GET_CODE (XEXP (SET_SRC (pat
), 2)) == LABEL_REF
)
5076 label
= &XEXP (SET_SRC (pat
), 2);
5083 if (get_attr_length (insn
) <= 4)
5086 /* We are going to use the return register as scratch register,
5087 make sure it will be saved/restored by the prologue/epilogue. */
5088 cfun_frame_layout
.save_return_addr_p
= 1;
5093 tmp
= force_const_mem (Pmode
, *label
);
5094 tmp
= emit_insn_before (gen_rtx_SET (Pmode
, temp_reg
, tmp
), insn
);
5095 INSN_ADDRESSES_NEW (tmp
, -1);
5096 annotate_constant_pool_refs (&PATTERN (tmp
));
5103 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, *label
),
5104 UNSPEC_LTREL_OFFSET
);
5105 target
= gen_rtx_CONST (Pmode
, target
);
5106 target
= force_const_mem (Pmode
, target
);
5107 tmp
= emit_insn_before (gen_rtx_SET (Pmode
, temp_reg
, target
), insn
);
5108 INSN_ADDRESSES_NEW (tmp
, -1);
5109 annotate_constant_pool_refs (&PATTERN (tmp
));
5111 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XEXP (target
, 0),
5112 cfun
->machine
->base_reg
),
5114 target
= gen_rtx_PLUS (Pmode
, temp_reg
, target
);
5117 ret
= validate_change (insn
, label
, target
, 0);
5125 /* Find an annotated literal pool symbol referenced in RTX X,
5126 and store it at REF. Will abort if X contains references to
5127 more than one such pool symbol; multiple references to the same
5128 symbol are allowed, however.
5130 The rtx pointed to by REF must be initialized to NULL_RTX
5131 by the caller before calling this routine. */
5134 find_constant_pool_ref (rtx x
, rtx
*ref
)
5139 /* Ignore LTREL_BASE references. */
5140 if (GET_CODE (x
) == UNSPEC
5141 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
5143 /* Likewise POOL_ENTRY insns. */
5144 if (GET_CODE (x
) == UNSPEC_VOLATILE
5145 && XINT (x
, 1) == UNSPECV_POOL_ENTRY
)
5148 gcc_assert (GET_CODE (x
) != SYMBOL_REF
5149 || !CONSTANT_POOL_ADDRESS_P (x
));
5151 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_LTREF
)
5153 rtx sym
= XVECEXP (x
, 0, 0);
5154 gcc_assert (GET_CODE (sym
) == SYMBOL_REF
5155 && CONSTANT_POOL_ADDRESS_P (sym
));
5157 if (*ref
== NULL_RTX
)
5160 gcc_assert (*ref
== sym
);
5165 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5166 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5170 find_constant_pool_ref (XEXP (x
, i
), ref
);
5172 else if (fmt
[i
] == 'E')
5174 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
5175 find_constant_pool_ref (XVECEXP (x
, i
, j
), ref
);
5180 /* Replace every reference to the annotated literal pool
5181 symbol REF in X by its base plus OFFSET. */
5184 replace_constant_pool_ref (rtx
*x
, rtx ref
, rtx offset
)
5189 gcc_assert (*x
!= ref
);
5191 if (GET_CODE (*x
) == UNSPEC
5192 && XINT (*x
, 1) == UNSPEC_LTREF
5193 && XVECEXP (*x
, 0, 0) == ref
)
5195 *x
= gen_rtx_PLUS (Pmode
, XVECEXP (*x
, 0, 1), offset
);
5199 if (GET_CODE (*x
) == PLUS
5200 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
5201 && GET_CODE (XEXP (*x
, 0)) == UNSPEC
5202 && XINT (XEXP (*x
, 0), 1) == UNSPEC_LTREF
5203 && XVECEXP (XEXP (*x
, 0), 0, 0) == ref
)
5205 rtx addr
= gen_rtx_PLUS (Pmode
, XVECEXP (XEXP (*x
, 0), 0, 1), offset
);
5206 *x
= plus_constant (addr
, INTVAL (XEXP (*x
, 1)));
5210 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5211 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5215 replace_constant_pool_ref (&XEXP (*x
, i
), ref
, offset
);
5217 else if (fmt
[i
] == 'E')
5219 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
5220 replace_constant_pool_ref (&XVECEXP (*x
, i
, j
), ref
, offset
);
5225 /* Check whether X contains an UNSPEC_LTREL_BASE.
5226 Return its constant pool symbol if found, NULL_RTX otherwise. */
5229 find_ltrel_base (rtx x
)
5234 if (GET_CODE (x
) == UNSPEC
5235 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
5236 return XVECEXP (x
, 0, 0);
5238 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5239 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5243 rtx fnd
= find_ltrel_base (XEXP (x
, i
));
5247 else if (fmt
[i
] == 'E')
5249 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
5251 rtx fnd
= find_ltrel_base (XVECEXP (x
, i
, j
));
5261 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5264 replace_ltrel_base (rtx
*x
)
5269 if (GET_CODE (*x
) == UNSPEC
5270 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
5272 *x
= XVECEXP (*x
, 0, 1);
5276 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5277 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5281 replace_ltrel_base (&XEXP (*x
, i
));
5283 else if (fmt
[i
] == 'E')
5285 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
5286 replace_ltrel_base (&XVECEXP (*x
, i
, j
));
5292 /* We keep a list of constants which we have to add to internal
5293 constant tables in the middle of large functions. */
5295 #define NR_C_MODES 11
5296 enum machine_mode constant_modes
[NR_C_MODES
] =
5298 TFmode
, TImode
, TDmode
,
5299 DFmode
, DImode
, DDmode
,
5300 SFmode
, SImode
, SDmode
,
5307 struct constant
*next
;
5312 struct constant_pool
5314 struct constant_pool
*next
;
5319 struct constant
*constants
[NR_C_MODES
];
5320 struct constant
*execute
;
5325 /* Allocate new constant_pool structure. */
5327 static struct constant_pool
*
5328 s390_alloc_pool (void)
5330 struct constant_pool
*pool
;
5333 pool
= (struct constant_pool
*) xmalloc (sizeof *pool
);
5335 for (i
= 0; i
< NR_C_MODES
; i
++)
5336 pool
->constants
[i
] = NULL
;
5338 pool
->execute
= NULL
;
5339 pool
->label
= gen_label_rtx ();
5340 pool
->first_insn
= NULL_RTX
;
5341 pool
->pool_insn
= NULL_RTX
;
5342 pool
->insns
= BITMAP_ALLOC (NULL
);
5348 /* Create new constant pool covering instructions starting at INSN
5349 and chain it to the end of POOL_LIST. */
5351 static struct constant_pool
*
5352 s390_start_pool (struct constant_pool
**pool_list
, rtx insn
)
5354 struct constant_pool
*pool
, **prev
;
5356 pool
= s390_alloc_pool ();
5357 pool
->first_insn
= insn
;
5359 for (prev
= pool_list
; *prev
; prev
= &(*prev
)->next
)
5366 /* End range of instructions covered by POOL at INSN and emit
5367 placeholder insn representing the pool. */
5370 s390_end_pool (struct constant_pool
*pool
, rtx insn
)
5372 rtx pool_size
= GEN_INT (pool
->size
+ 8 /* alignment slop */);
5375 insn
= get_last_insn ();
5377 pool
->pool_insn
= emit_insn_after (gen_pool (pool_size
), insn
);
5378 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
5381 /* Add INSN to the list of insns covered by POOL. */
5384 s390_add_pool_insn (struct constant_pool
*pool
, rtx insn
)
5386 bitmap_set_bit (pool
->insns
, INSN_UID (insn
));
5389 /* Return pool out of POOL_LIST that covers INSN. */
5391 static struct constant_pool
*
5392 s390_find_pool (struct constant_pool
*pool_list
, rtx insn
)
5394 struct constant_pool
*pool
;
5396 for (pool
= pool_list
; pool
; pool
= pool
->next
)
5397 if (bitmap_bit_p (pool
->insns
, INSN_UID (insn
)))
5403 /* Add constant VAL of mode MODE to the constant pool POOL. */
5406 s390_add_constant (struct constant_pool
*pool
, rtx val
, enum machine_mode mode
)
5411 for (i
= 0; i
< NR_C_MODES
; i
++)
5412 if (constant_modes
[i
] == mode
)
5414 gcc_assert (i
!= NR_C_MODES
);
5416 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
5417 if (rtx_equal_p (val
, c
->value
))
5422 c
= (struct constant
*) xmalloc (sizeof *c
);
5424 c
->label
= gen_label_rtx ();
5425 c
->next
= pool
->constants
[i
];
5426 pool
->constants
[i
] = c
;
5427 pool
->size
+= GET_MODE_SIZE (mode
);
5431 /* Find constant VAL of mode MODE in the constant pool POOL.
5432 Return an RTX describing the distance from the start of
5433 the pool to the location of the new constant. */
5436 s390_find_constant (struct constant_pool
*pool
, rtx val
,
5437 enum machine_mode mode
)
5443 for (i
= 0; i
< NR_C_MODES
; i
++)
5444 if (constant_modes
[i
] == mode
)
5446 gcc_assert (i
!= NR_C_MODES
);
5448 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
5449 if (rtx_equal_p (val
, c
->value
))
5454 offset
= gen_rtx_MINUS (Pmode
, gen_rtx_LABEL_REF (Pmode
, c
->label
),
5455 gen_rtx_LABEL_REF (Pmode
, pool
->label
));
5456 offset
= gen_rtx_CONST (Pmode
, offset
);
5460 /* Check whether INSN is an execute. Return the label_ref to its
5461 execute target template if so, NULL_RTX otherwise. */
5464 s390_execute_label (rtx insn
)
5466 if (GET_CODE (insn
) == INSN
5467 && GET_CODE (PATTERN (insn
)) == PARALLEL
5468 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == UNSPEC
5469 && XINT (XVECEXP (PATTERN (insn
), 0, 0), 1) == UNSPEC_EXECUTE
)
5470 return XVECEXP (XVECEXP (PATTERN (insn
), 0, 0), 0, 2);
5475 /* Add execute target for INSN to the constant pool POOL. */
5478 s390_add_execute (struct constant_pool
*pool
, rtx insn
)
5482 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
5483 if (INSN_UID (insn
) == INSN_UID (c
->value
))
5488 c
= (struct constant
*) xmalloc (sizeof *c
);
5490 c
->label
= gen_label_rtx ();
5491 c
->next
= pool
->execute
;
5497 /* Find execute target for INSN in the constant pool POOL.
5498 Return an RTX describing the distance from the start of
5499 the pool to the location of the execute target. */
5502 s390_find_execute (struct constant_pool
*pool
, rtx insn
)
5507 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
5508 if (INSN_UID (insn
) == INSN_UID (c
->value
))
5513 offset
= gen_rtx_MINUS (Pmode
, gen_rtx_LABEL_REF (Pmode
, c
->label
),
5514 gen_rtx_LABEL_REF (Pmode
, pool
->label
));
5515 offset
= gen_rtx_CONST (Pmode
, offset
);
5519 /* For an execute INSN, extract the execute target template. */
5522 s390_execute_target (rtx insn
)
5524 rtx pattern
= PATTERN (insn
);
5525 gcc_assert (s390_execute_label (insn
));
5527 if (XVECLEN (pattern
, 0) == 2)
5529 pattern
= copy_rtx (XVECEXP (pattern
, 0, 1));
5533 rtvec vec
= rtvec_alloc (XVECLEN (pattern
, 0) - 1);
5536 for (i
= 0; i
< XVECLEN (pattern
, 0) - 1; i
++)
5537 RTVEC_ELT (vec
, i
) = copy_rtx (XVECEXP (pattern
, 0, i
+ 1));
5539 pattern
= gen_rtx_PARALLEL (VOIDmode
, vec
);
5545 /* Indicate that INSN cannot be duplicated. This is the case for
5546 execute insns that carry a unique label. */
5549 s390_cannot_copy_insn_p (rtx insn
)
5551 rtx label
= s390_execute_label (insn
);
5552 return label
&& label
!= const0_rtx
;
5555 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
5556 do not emit the pool base label. */
5559 s390_dump_pool (struct constant_pool
*pool
, bool remote_label
)
5562 rtx insn
= pool
->pool_insn
;
5565 /* Switch to rodata section. */
5566 if (TARGET_CPU_ZARCH
)
5568 insn
= emit_insn_after (gen_pool_section_start (), insn
);
5569 INSN_ADDRESSES_NEW (insn
, -1);
5572 /* Ensure minimum pool alignment. */
5573 if (TARGET_CPU_ZARCH
)
5574 insn
= emit_insn_after (gen_pool_align (GEN_INT (8)), insn
);
5576 insn
= emit_insn_after (gen_pool_align (GEN_INT (4)), insn
);
5577 INSN_ADDRESSES_NEW (insn
, -1);
5579 /* Emit pool base label. */
5582 insn
= emit_label_after (pool
->label
, insn
);
5583 INSN_ADDRESSES_NEW (insn
, -1);
5586 /* Dump constants in descending alignment requirement order,
5587 ensuring proper alignment for every constant. */
5588 for (i
= 0; i
< NR_C_MODES
; i
++)
5589 for (c
= pool
->constants
[i
]; c
; c
= c
->next
)
5591 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
5592 rtx value
= c
->value
;
5593 if (GET_CODE (value
) == CONST
5594 && GET_CODE (XEXP (value
, 0)) == UNSPEC
5595 && XINT (XEXP (value
, 0), 1) == UNSPEC_LTREL_OFFSET
5596 && XVECLEN (XEXP (value
, 0), 0) == 1)
5598 value
= gen_rtx_MINUS (Pmode
, XVECEXP (XEXP (value
, 0), 0, 0),
5599 gen_rtx_LABEL_REF (VOIDmode
, pool
->label
));
5600 value
= gen_rtx_CONST (VOIDmode
, value
);
5603 insn
= emit_label_after (c
->label
, insn
);
5604 INSN_ADDRESSES_NEW (insn
, -1);
5606 value
= gen_rtx_UNSPEC_VOLATILE (constant_modes
[i
],
5607 gen_rtvec (1, value
),
5608 UNSPECV_POOL_ENTRY
);
5609 insn
= emit_insn_after (value
, insn
);
5610 INSN_ADDRESSES_NEW (insn
, -1);
5613 /* Ensure minimum alignment for instructions. */
5614 insn
= emit_insn_after (gen_pool_align (GEN_INT (2)), insn
);
5615 INSN_ADDRESSES_NEW (insn
, -1);
5617 /* Output in-pool execute template insns. */
5618 for (c
= pool
->execute
; c
; c
= c
->next
)
5620 insn
= emit_label_after (c
->label
, insn
);
5621 INSN_ADDRESSES_NEW (insn
, -1);
5623 insn
= emit_insn_after (s390_execute_target (c
->value
), insn
);
5624 INSN_ADDRESSES_NEW (insn
, -1);
5627 /* Switch back to previous section. */
5628 if (TARGET_CPU_ZARCH
)
5630 insn
= emit_insn_after (gen_pool_section_end (), insn
);
5631 INSN_ADDRESSES_NEW (insn
, -1);
5634 insn
= emit_barrier_after (insn
);
5635 INSN_ADDRESSES_NEW (insn
, -1);
5637 /* Remove placeholder insn. */
5638 remove_insn (pool
->pool_insn
);
5641 /* Free all memory used by POOL. */
5644 s390_free_pool (struct constant_pool
*pool
)
5646 struct constant
*c
, *next
;
5649 for (i
= 0; i
< NR_C_MODES
; i
++)
5650 for (c
= pool
->constants
[i
]; c
; c
= next
)
5656 for (c
= pool
->execute
; c
; c
= next
)
5662 BITMAP_FREE (pool
->insns
);
5667 /* Collect main literal pool. Return NULL on overflow. */
5669 static struct constant_pool
*
5670 s390_mainpool_start (void)
5672 struct constant_pool
*pool
;
5675 pool
= s390_alloc_pool ();
5677 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5679 if (GET_CODE (insn
) == INSN
5680 && GET_CODE (PATTERN (insn
)) == SET
5681 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC_VOLATILE
5682 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPECV_MAIN_POOL
)
5684 gcc_assert (!pool
->pool_insn
);
5685 pool
->pool_insn
= insn
;
5688 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
5690 s390_add_execute (pool
, insn
);
5692 else if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
5694 rtx pool_ref
= NULL_RTX
;
5695 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
5698 rtx constant
= get_pool_constant (pool_ref
);
5699 enum machine_mode mode
= get_pool_mode (pool_ref
);
5700 s390_add_constant (pool
, constant
, mode
);
5705 gcc_assert (pool
->pool_insn
|| pool
->size
== 0);
5707 if (pool
->size
>= 4096)
5709 /* We're going to chunkify the pool, so remove the main
5710 pool placeholder insn. */
5711 remove_insn (pool
->pool_insn
);
5713 s390_free_pool (pool
);
5720 /* POOL holds the main literal pool as collected by s390_mainpool_start.
5721 Modify the current function to output the pool constants as well as
5722 the pool register setup instruction. */
5725 s390_mainpool_finish (struct constant_pool
*pool
)
5727 rtx base_reg
= cfun
->machine
->base_reg
;
5730 /* If the pool is empty, we're done. */
5731 if (pool
->size
== 0)
5733 /* We don't actually need a base register after all. */
5734 cfun
->machine
->base_reg
= NULL_RTX
;
5736 if (pool
->pool_insn
)
5737 remove_insn (pool
->pool_insn
);
5738 s390_free_pool (pool
);
5742 /* We need correct insn addresses. */
5743 shorten_branches (get_insns ());
5745 /* On zSeries, we use a LARL to load the pool register. The pool is
5746 located in the .rodata section, so we emit it after the function. */
5747 if (TARGET_CPU_ZARCH
)
5749 insn
= gen_main_base_64 (base_reg
, pool
->label
);
5750 insn
= emit_insn_after (insn
, pool
->pool_insn
);
5751 INSN_ADDRESSES_NEW (insn
, -1);
5752 remove_insn (pool
->pool_insn
);
5754 insn
= get_last_insn ();
5755 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
5756 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
5758 s390_dump_pool (pool
, 0);
5761 /* On S/390, if the total size of the function's code plus literal pool
5762 does not exceed 4096 bytes, we use BASR to set up a function base
5763 pointer, and emit the literal pool at the end of the function. */
5764 else if (INSN_ADDRESSES (INSN_UID (get_last_insn ()))
5765 + pool
->size
+ 8 /* alignment slop */ < 4096)
5767 insn
= gen_main_base_31_small (base_reg
, pool
->label
);
5768 insn
= emit_insn_after (insn
, pool
->pool_insn
);
5769 INSN_ADDRESSES_NEW (insn
, -1);
5770 remove_insn (pool
->pool_insn
);
5772 insn
= emit_label_after (pool
->label
, insn
);
5773 INSN_ADDRESSES_NEW (insn
, -1);
5775 insn
= get_last_insn ();
5776 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
5777 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
5779 s390_dump_pool (pool
, 1);
5782 /* Otherwise, we emit an inline literal pool and use BASR to branch
5783 over it, setting up the pool register at the same time. */
5786 rtx pool_end
= gen_label_rtx ();
5788 insn
= gen_main_base_31_large (base_reg
, pool
->label
, pool_end
);
5789 insn
= emit_insn_after (insn
, pool
->pool_insn
);
5790 INSN_ADDRESSES_NEW (insn
, -1);
5791 remove_insn (pool
->pool_insn
);
5793 insn
= emit_label_after (pool
->label
, insn
);
5794 INSN_ADDRESSES_NEW (insn
, -1);
5796 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
5797 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
5799 insn
= emit_label_after (pool_end
, pool
->pool_insn
);
5800 INSN_ADDRESSES_NEW (insn
, -1);
5802 s390_dump_pool (pool
, 1);
5806 /* Replace all literal pool references. */
5808 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5811 replace_ltrel_base (&PATTERN (insn
));
5813 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
5815 rtx addr
, pool_ref
= NULL_RTX
;
5816 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
5819 if (s390_execute_label (insn
))
5820 addr
= s390_find_execute (pool
, insn
);
5822 addr
= s390_find_constant (pool
, get_pool_constant (pool_ref
),
5823 get_pool_mode (pool_ref
));
5825 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
5826 INSN_CODE (insn
) = -1;
5832 /* Free the pool. */
5833 s390_free_pool (pool
);
5836 /* POOL holds the main literal pool as collected by s390_mainpool_start.
5837 We have decided we cannot use this pool, so revert all changes
5838 to the current function that were done by s390_mainpool_start. */
5840 s390_mainpool_cancel (struct constant_pool
*pool
)
5842 /* We didn't actually change the instruction stream, so simply
5843 free the pool memory. */
5844 s390_free_pool (pool
);
5848 /* Chunkify the literal pool. */
5850 #define S390_POOL_CHUNK_MIN 0xc00
5851 #define S390_POOL_CHUNK_MAX 0xe00
5853 static struct constant_pool
*
5854 s390_chunkify_start (void)
5856 struct constant_pool
*curr_pool
= NULL
, *pool_list
= NULL
;
5859 rtx pending_ltrel
= NULL_RTX
;
5862 rtx (*gen_reload_base
) (rtx
, rtx
) =
5863 TARGET_CPU_ZARCH
? gen_reload_base_64
: gen_reload_base_31
;
5866 /* We need correct insn addresses. */
5868 shorten_branches (get_insns ());
5870 /* Scan all insns and move literals to pool chunks. */
5872 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5874 /* Check for pending LTREL_BASE. */
5877 rtx ltrel_base
= find_ltrel_base (PATTERN (insn
));
5880 gcc_assert (ltrel_base
== pending_ltrel
);
5881 pending_ltrel
= NULL_RTX
;
5885 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
5888 curr_pool
= s390_start_pool (&pool_list
, insn
);
5890 s390_add_execute (curr_pool
, insn
);
5891 s390_add_pool_insn (curr_pool
, insn
);
5893 else if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
5895 rtx pool_ref
= NULL_RTX
;
5896 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
5899 rtx constant
= get_pool_constant (pool_ref
);
5900 enum machine_mode mode
= get_pool_mode (pool_ref
);
5903 curr_pool
= s390_start_pool (&pool_list
, insn
);
5905 s390_add_constant (curr_pool
, constant
, mode
);
5906 s390_add_pool_insn (curr_pool
, insn
);
5908 /* Don't split the pool chunk between a LTREL_OFFSET load
5909 and the corresponding LTREL_BASE. */
5910 if (GET_CODE (constant
) == CONST
5911 && GET_CODE (XEXP (constant
, 0)) == UNSPEC
5912 && XINT (XEXP (constant
, 0), 1) == UNSPEC_LTREL_OFFSET
)
5914 gcc_assert (!pending_ltrel
);
5915 pending_ltrel
= pool_ref
;
5920 if (GET_CODE (insn
) == JUMP_INSN
|| GET_CODE (insn
) == CODE_LABEL
)
5923 s390_add_pool_insn (curr_pool
, insn
);
5924 /* An LTREL_BASE must follow within the same basic block. */
5925 gcc_assert (!pending_ltrel
);
5929 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn
)
5930 || INSN_ADDRESSES (INSN_UID (insn
)) == -1)
5933 if (TARGET_CPU_ZARCH
)
5935 if (curr_pool
->size
< S390_POOL_CHUNK_MAX
)
5938 s390_end_pool (curr_pool
, NULL_RTX
);
5943 int chunk_size
= INSN_ADDRESSES (INSN_UID (insn
))
5944 - INSN_ADDRESSES (INSN_UID (curr_pool
->first_insn
))
5947 /* We will later have to insert base register reload insns.
5948 Those will have an effect on code size, which we need to
5949 consider here. This calculation makes rather pessimistic
5950 worst-case assumptions. */
5951 if (GET_CODE (insn
) == CODE_LABEL
)
5954 if (chunk_size
< S390_POOL_CHUNK_MIN
5955 && curr_pool
->size
< S390_POOL_CHUNK_MIN
)
5958 /* Pool chunks can only be inserted after BARRIERs ... */
5959 if (GET_CODE (insn
) == BARRIER
)
5961 s390_end_pool (curr_pool
, insn
);
5966 /* ... so if we don't find one in time, create one. */
5967 else if ((chunk_size
> S390_POOL_CHUNK_MAX
5968 || curr_pool
->size
> S390_POOL_CHUNK_MAX
))
5970 rtx label
, jump
, barrier
;
5972 /* We can insert the barrier only after a 'real' insn. */
5973 if (GET_CODE (insn
) != INSN
&& GET_CODE (insn
) != CALL_INSN
)
5975 if (get_attr_length (insn
) == 0)
5978 /* Don't separate LTREL_BASE from the corresponding
5979 LTREL_OFFSET load. */
5983 label
= gen_label_rtx ();
5984 jump
= emit_jump_insn_after (gen_jump (label
), insn
);
5985 barrier
= emit_barrier_after (jump
);
5986 insn
= emit_label_after (label
, barrier
);
5987 JUMP_LABEL (jump
) = label
;
5988 LABEL_NUSES (label
) = 1;
5990 INSN_ADDRESSES_NEW (jump
, -1);
5991 INSN_ADDRESSES_NEW (barrier
, -1);
5992 INSN_ADDRESSES_NEW (insn
, -1);
5994 s390_end_pool (curr_pool
, barrier
);
6002 s390_end_pool (curr_pool
, NULL_RTX
);
6003 gcc_assert (!pending_ltrel
);
6005 /* Find all labels that are branched into
6006 from an insn belonging to a different chunk. */
6008 far_labels
= BITMAP_ALLOC (NULL
);
6010 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6012 /* Labels marked with LABEL_PRESERVE_P can be target
6013 of non-local jumps, so we have to mark them.
6014 The same holds for named labels.
6016 Don't do that, however, if it is the label before
6019 if (GET_CODE (insn
) == CODE_LABEL
6020 && (LABEL_PRESERVE_P (insn
) || LABEL_NAME (insn
)))
6022 rtx vec_insn
= next_real_insn (insn
);
6023 rtx vec_pat
= vec_insn
&& GET_CODE (vec_insn
) == JUMP_INSN
?
6024 PATTERN (vec_insn
) : NULL_RTX
;
6026 || !(GET_CODE (vec_pat
) == ADDR_VEC
6027 || GET_CODE (vec_pat
) == ADDR_DIFF_VEC
))
6028 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (insn
));
6031 /* If we have a direct jump (conditional or unconditional)
6032 or a casesi jump, check all potential targets. */
6033 else if (GET_CODE (insn
) == JUMP_INSN
)
6035 rtx pat
= PATTERN (insn
);
6036 if (GET_CODE (pat
) == PARALLEL
&& XVECLEN (pat
, 0) > 2)
6037 pat
= XVECEXP (pat
, 0, 0);
6039 if (GET_CODE (pat
) == SET
)
6041 rtx label
= JUMP_LABEL (insn
);
6044 if (s390_find_pool (pool_list
, label
)
6045 != s390_find_pool (pool_list
, insn
))
6046 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
6049 else if (GET_CODE (pat
) == PARALLEL
6050 && XVECLEN (pat
, 0) == 2
6051 && GET_CODE (XVECEXP (pat
, 0, 0)) == SET
6052 && GET_CODE (XVECEXP (pat
, 0, 1)) == USE
6053 && GET_CODE (XEXP (XVECEXP (pat
, 0, 1), 0)) == LABEL_REF
)
6055 /* Find the jump table used by this casesi jump. */
6056 rtx vec_label
= XEXP (XEXP (XVECEXP (pat
, 0, 1), 0), 0);
6057 rtx vec_insn
= next_real_insn (vec_label
);
6058 rtx vec_pat
= vec_insn
&& GET_CODE (vec_insn
) == JUMP_INSN
?
6059 PATTERN (vec_insn
) : NULL_RTX
;
6061 && (GET_CODE (vec_pat
) == ADDR_VEC
6062 || GET_CODE (vec_pat
) == ADDR_DIFF_VEC
))
6064 int i
, diff_p
= GET_CODE (vec_pat
) == ADDR_DIFF_VEC
;
6066 for (i
= 0; i
< XVECLEN (vec_pat
, diff_p
); i
++)
6068 rtx label
= XEXP (XVECEXP (vec_pat
, diff_p
, i
), 0);
6070 if (s390_find_pool (pool_list
, label
)
6071 != s390_find_pool (pool_list
, insn
))
6072 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
6079 /* Insert base register reload insns before every pool. */
6081 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
6083 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
6085 rtx insn
= curr_pool
->first_insn
;
6086 INSN_ADDRESSES_NEW (emit_insn_before (new_insn
, insn
), -1);
6089 /* Insert base register reload insns at every far label. */
6091 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6092 if (GET_CODE (insn
) == CODE_LABEL
6093 && bitmap_bit_p (far_labels
, CODE_LABEL_NUMBER (insn
)))
6095 struct constant_pool
*pool
= s390_find_pool (pool_list
, insn
);
6098 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
6100 INSN_ADDRESSES_NEW (emit_insn_after (new_insn
, insn
), -1);
6105 BITMAP_FREE (far_labels
);
6108 /* Recompute insn addresses. */
6110 init_insn_lengths ();
6111 shorten_branches (get_insns ());
6116 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6117 After we have decided to use this list, finish implementing
6118 all changes to the current function as required. */
6121 s390_chunkify_finish (struct constant_pool
*pool_list
)
6123 struct constant_pool
*curr_pool
= NULL
;
6127 /* Replace all literal pool references. */
6129 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6132 replace_ltrel_base (&PATTERN (insn
));
6134 curr_pool
= s390_find_pool (pool_list
, insn
);
6138 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6140 rtx addr
, pool_ref
= NULL_RTX
;
6141 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6144 if (s390_execute_label (insn
))
6145 addr
= s390_find_execute (curr_pool
, insn
);
6147 addr
= s390_find_constant (curr_pool
,
6148 get_pool_constant (pool_ref
),
6149 get_pool_mode (pool_ref
));
6151 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
6152 INSN_CODE (insn
) = -1;
6157 /* Dump out all literal pools. */
6159 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
6160 s390_dump_pool (curr_pool
, 0);
6162 /* Free pool list. */
6166 struct constant_pool
*next
= pool_list
->next
;
6167 s390_free_pool (pool_list
);
6172 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6173 We have decided we cannot use this list, so revert all changes
6174 to the current function that were done by s390_chunkify_start. */
6177 s390_chunkify_cancel (struct constant_pool
*pool_list
)
6179 struct constant_pool
*curr_pool
= NULL
;
6182 /* Remove all pool placeholder insns. */
6184 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
6186 /* Did we insert an extra barrier? Remove it. */
6187 rtx barrier
= PREV_INSN (curr_pool
->pool_insn
);
6188 rtx jump
= barrier
? PREV_INSN (barrier
) : NULL_RTX
;
6189 rtx label
= NEXT_INSN (curr_pool
->pool_insn
);
6191 if (jump
&& GET_CODE (jump
) == JUMP_INSN
6192 && barrier
&& GET_CODE (barrier
) == BARRIER
6193 && label
&& GET_CODE (label
) == CODE_LABEL
6194 && GET_CODE (PATTERN (jump
)) == SET
6195 && SET_DEST (PATTERN (jump
)) == pc_rtx
6196 && GET_CODE (SET_SRC (PATTERN (jump
))) == LABEL_REF
6197 && XEXP (SET_SRC (PATTERN (jump
)), 0) == label
)
6200 remove_insn (barrier
);
6201 remove_insn (label
);
6204 remove_insn (curr_pool
->pool_insn
);
6207 /* Remove all base register reload insns. */
6209 for (insn
= get_insns (); insn
; )
6211 rtx next_insn
= NEXT_INSN (insn
);
6213 if (GET_CODE (insn
) == INSN
6214 && GET_CODE (PATTERN (insn
)) == SET
6215 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC
6216 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPEC_RELOAD_BASE
)
6222 /* Free pool list. */
6226 struct constant_pool
*next
= pool_list
->next
;
6227 s390_free_pool (pool_list
);
6233 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
6236 s390_output_pool_entry (rtx exp
, enum machine_mode mode
, unsigned int align
)
6240 switch (GET_MODE_CLASS (mode
))
6243 case MODE_DECIMAL_FLOAT
:
6244 gcc_assert (GET_CODE (exp
) == CONST_DOUBLE
);
6246 REAL_VALUE_FROM_CONST_DOUBLE (r
, exp
);
6247 assemble_real (r
, mode
, align
);
6251 assemble_integer (exp
, GET_MODE_SIZE (mode
), align
, 1);
6260 /* Return an RTL expression representing the value of the return address
6261 for the frame COUNT steps up from the current frame. FRAME is the
6262 frame pointer of that frame. */
6265 s390_return_addr_rtx (int count
, rtx frame ATTRIBUTE_UNUSED
)
6270 /* Without backchain, we fail for all but the current frame. */
6272 if (!TARGET_BACKCHAIN
&& count
> 0)
6275 /* For the current frame, we need to make sure the initial
6276 value of RETURN_REGNUM is actually saved. */
6280 /* On non-z architectures branch splitting could overwrite r14. */
6281 if (TARGET_CPU_ZARCH
)
6282 return get_hard_reg_initial_val (Pmode
, RETURN_REGNUM
);
6285 cfun_frame_layout
.save_return_addr_p
= true;
6286 return gen_rtx_MEM (Pmode
, return_address_pointer_rtx
);
6290 if (TARGET_PACKED_STACK
)
6291 offset
= -2 * UNITS_PER_WORD
;
6293 offset
= RETURN_REGNUM
* UNITS_PER_WORD
;
6295 addr
= plus_constant (frame
, offset
);
6296 addr
= memory_address (Pmode
, addr
);
6297 return gen_rtx_MEM (Pmode
, addr
);
6300 /* Return an RTL expression representing the back chain stored in
6301 the current stack frame. */
6304 s390_back_chain_rtx (void)
6308 gcc_assert (TARGET_BACKCHAIN
);
6310 if (TARGET_PACKED_STACK
)
6311 chain
= plus_constant (stack_pointer_rtx
,
6312 STACK_POINTER_OFFSET
- UNITS_PER_WORD
);
6314 chain
= stack_pointer_rtx
;
6316 chain
= gen_rtx_MEM (Pmode
, chain
);
6320 /* Find first call clobbered register unused in a function.
6321 This could be used as base register in a leaf function
6322 or for holding the return address before epilogue. */
6325 find_unused_clobbered_reg (void)
6328 for (i
= 0; i
< 6; i
++)
6329 if (!df_regs_ever_live_p (i
))
6335 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
6336 clobbered hard regs in SETREG. */
6339 s390_reg_clobbered_rtx (rtx setreg
, rtx set_insn ATTRIBUTE_UNUSED
, void *data
)
6341 int *regs_ever_clobbered
= (int *)data
;
6342 unsigned int i
, regno
;
6343 enum machine_mode mode
= GET_MODE (setreg
);
6345 if (GET_CODE (setreg
) == SUBREG
)
6347 rtx inner
= SUBREG_REG (setreg
);
6348 if (!GENERAL_REG_P (inner
))
6350 regno
= subreg_regno (setreg
);
6352 else if (GENERAL_REG_P (setreg
))
6353 regno
= REGNO (setreg
);
6358 i
< regno
+ HARD_REGNO_NREGS (regno
, mode
);
6360 regs_ever_clobbered
[i
] = 1;
6363 /* Walks through all basic blocks of the current function looking
6364 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
6365 of the passed integer array REGS_EVER_CLOBBERED are set to one for
6366 each of those regs. */
6369 s390_regs_ever_clobbered (int *regs_ever_clobbered
)
6375 memset (regs_ever_clobbered
, 0, 16 * sizeof (int));
6377 /* For non-leaf functions we have to consider all call clobbered regs to be
6379 if (!current_function_is_leaf
)
6381 for (i
= 0; i
< 16; i
++)
6382 regs_ever_clobbered
[i
] = call_really_used_regs
[i
];
6385 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
6386 this work is done by liveness analysis (mark_regs_live_at_end).
6387 Special care is needed for functions containing landing pads. Landing pads
6388 may use the eh registers, but the code which sets these registers is not
6389 contained in that function. Hence s390_regs_ever_clobbered is not able to
6390 deal with this automatically. */
6391 if (current_function_calls_eh_return
|| cfun
->machine
->has_landing_pad_p
)
6392 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
6393 if (current_function_calls_eh_return
6394 || (cfun
->machine
->has_landing_pad_p
6395 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i
))))
6396 regs_ever_clobbered
[EH_RETURN_DATA_REGNO (i
)] = 1;
6398 /* For nonlocal gotos all call-saved registers have to be saved.
6399 This flag is also set for the unwinding code in libgcc.
6400 See expand_builtin_unwind_init. For regs_ever_live this is done by
6402 if (current_function_has_nonlocal_label
)
6403 for (i
= 0; i
< 16; i
++)
6404 if (!call_really_used_regs
[i
])
6405 regs_ever_clobbered
[i
] = 1;
6407 FOR_EACH_BB (cur_bb
)
6409 FOR_BB_INSNS (cur_bb
, cur_insn
)
6411 if (INSN_P (cur_insn
))
6412 note_stores (PATTERN (cur_insn
),
6413 s390_reg_clobbered_rtx
,
6414 regs_ever_clobbered
);
6419 /* Determine the frame area which actually has to be accessed
6420 in the function epilogue. The values are stored at the
6421 given pointers AREA_BOTTOM (address of the lowest used stack
6422 address) and AREA_TOP (address of the first item which does
6423 not belong to the stack frame). */
6426 s390_frame_area (int *area_bottom
, int *area_top
)
6434 if (cfun_frame_layout
.first_restore_gpr
!= -1)
6436 b
= (cfun_frame_layout
.gprs_offset
6437 + cfun_frame_layout
.first_restore_gpr
* UNITS_PER_WORD
);
6438 t
= b
+ (cfun_frame_layout
.last_restore_gpr
6439 - cfun_frame_layout
.first_restore_gpr
+ 1) * UNITS_PER_WORD
;
6442 if (TARGET_64BIT
&& cfun_save_high_fprs_p
)
6444 b
= MIN (b
, cfun_frame_layout
.f8_offset
);
6445 t
= MAX (t
, (cfun_frame_layout
.f8_offset
6446 + cfun_frame_layout
.high_fprs
* 8));
6450 for (i
= 2; i
< 4; i
++)
6451 if (cfun_fpr_bit_p (i
))
6453 b
= MIN (b
, cfun_frame_layout
.f4_offset
+ (i
- 2) * 8);
6454 t
= MAX (t
, cfun_frame_layout
.f4_offset
+ (i
- 1) * 8);
6461 /* Fill cfun->machine with info about register usage of current function.
6462 Return in CLOBBERED_REGS which GPRs are currently considered set. */
6465 s390_register_info (int clobbered_regs
[])
6469 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
6470 cfun_frame_layout
.fpr_bitmap
= 0;
6471 cfun_frame_layout
.high_fprs
= 0;
6473 for (i
= 24; i
< 32; i
++)
6474 if (df_regs_ever_live_p (i
) && !global_regs
[i
])
6476 cfun_set_fpr_bit (i
- 16);
6477 cfun_frame_layout
.high_fprs
++;
6480 /* Find first and last gpr to be saved. We trust regs_ever_live
6481 data, except that we don't save and restore global registers.
6483 Also, all registers with special meaning to the compiler need
6484 to be handled extra. */
6486 s390_regs_ever_clobbered (clobbered_regs
);
6488 for (i
= 0; i
< 16; i
++)
6489 clobbered_regs
[i
] = clobbered_regs
[i
] && !global_regs
[i
] && !fixed_regs
[i
];
6491 if (frame_pointer_needed
)
6492 clobbered_regs
[HARD_FRAME_POINTER_REGNUM
] = 1;
6495 clobbered_regs
[PIC_OFFSET_TABLE_REGNUM
]
6496 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
);
6498 clobbered_regs
[BASE_REGNUM
]
6499 |= (cfun
->machine
->base_reg
6500 && REGNO (cfun
->machine
->base_reg
) == BASE_REGNUM
);
6502 clobbered_regs
[RETURN_REGNUM
]
6503 |= (!current_function_is_leaf
6504 || TARGET_TPF_PROFILING
6505 || cfun
->machine
->split_branches_pending_p
6506 || cfun_frame_layout
.save_return_addr_p
6507 || current_function_calls_eh_return
6508 || current_function_stdarg
);
6510 clobbered_regs
[STACK_POINTER_REGNUM
]
6511 |= (!current_function_is_leaf
6512 || TARGET_TPF_PROFILING
6513 || cfun_save_high_fprs_p
6514 || get_frame_size () > 0
6515 || current_function_calls_alloca
6516 || current_function_stdarg
);
6518 for (i
= 6; i
< 16; i
++)
6519 if (df_regs_ever_live_p (i
) || clobbered_regs
[i
])
6521 for (j
= 15; j
> i
; j
--)
6522 if (df_regs_ever_live_p (j
) || clobbered_regs
[j
])
6527 /* Nothing to save/restore. */
6528 cfun_frame_layout
.first_save_gpr_slot
= -1;
6529 cfun_frame_layout
.last_save_gpr_slot
= -1;
6530 cfun_frame_layout
.first_save_gpr
= -1;
6531 cfun_frame_layout
.first_restore_gpr
= -1;
6532 cfun_frame_layout
.last_save_gpr
= -1;
6533 cfun_frame_layout
.last_restore_gpr
= -1;
6537 /* Save slots for gprs from i to j. */
6538 cfun_frame_layout
.first_save_gpr_slot
= i
;
6539 cfun_frame_layout
.last_save_gpr_slot
= j
;
6541 for (i
= cfun_frame_layout
.first_save_gpr_slot
;
6542 i
< cfun_frame_layout
.last_save_gpr_slot
+ 1;
6544 if (clobbered_regs
[i
])
6547 for (j
= cfun_frame_layout
.last_save_gpr_slot
; j
> i
; j
--)
6548 if (clobbered_regs
[j
])
6551 if (i
== cfun_frame_layout
.last_save_gpr_slot
+ 1)
6553 /* Nothing to save/restore. */
6554 cfun_frame_layout
.first_save_gpr
= -1;
6555 cfun_frame_layout
.first_restore_gpr
= -1;
6556 cfun_frame_layout
.last_save_gpr
= -1;
6557 cfun_frame_layout
.last_restore_gpr
= -1;
6561 /* Save / Restore from gpr i to j. */
6562 cfun_frame_layout
.first_save_gpr
= i
;
6563 cfun_frame_layout
.first_restore_gpr
= i
;
6564 cfun_frame_layout
.last_save_gpr
= j
;
6565 cfun_frame_layout
.last_restore_gpr
= j
;
6569 if (current_function_stdarg
)
6571 /* Varargs functions need to save gprs 2 to 6. */
6572 if (cfun
->va_list_gpr_size
6573 && current_function_args_info
.gprs
< GP_ARG_NUM_REG
)
6575 int min_gpr
= current_function_args_info
.gprs
;
6576 int max_gpr
= min_gpr
+ cfun
->va_list_gpr_size
;
6577 if (max_gpr
> GP_ARG_NUM_REG
)
6578 max_gpr
= GP_ARG_NUM_REG
;
6580 if (cfun_frame_layout
.first_save_gpr
== -1
6581 || cfun_frame_layout
.first_save_gpr
> 2 + min_gpr
)
6583 cfun_frame_layout
.first_save_gpr
= 2 + min_gpr
;
6584 cfun_frame_layout
.first_save_gpr_slot
= 2 + min_gpr
;
6587 if (cfun_frame_layout
.last_save_gpr
== -1
6588 || cfun_frame_layout
.last_save_gpr
< 2 + max_gpr
- 1)
6590 cfun_frame_layout
.last_save_gpr
= 2 + max_gpr
- 1;
6591 cfun_frame_layout
.last_save_gpr_slot
= 2 + max_gpr
- 1;
6595 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
6596 if (TARGET_HARD_FLOAT
&& cfun
->va_list_fpr_size
6597 && current_function_args_info
.fprs
< FP_ARG_NUM_REG
)
6599 int min_fpr
= current_function_args_info
.fprs
;
6600 int max_fpr
= min_fpr
+ cfun
->va_list_fpr_size
;
6601 if (max_fpr
> FP_ARG_NUM_REG
)
6602 max_fpr
= FP_ARG_NUM_REG
;
6604 /* ??? This is currently required to ensure proper location
6605 of the fpr save slots within the va_list save area. */
6606 if (TARGET_PACKED_STACK
)
6609 for (i
= min_fpr
; i
< max_fpr
; i
++)
6610 cfun_set_fpr_bit (i
);
6615 for (i
= 2; i
< 4; i
++)
6616 if (df_regs_ever_live_p (i
+ 16) && !global_regs
[i
+ 16])
6617 cfun_set_fpr_bit (i
);
6620 /* Fill cfun->machine with info about frame of current function. */
6623 s390_frame_info (void)
6627 cfun_frame_layout
.frame_size
= get_frame_size ();
6628 if (!TARGET_64BIT
&& cfun_frame_layout
.frame_size
> 0x7fff0000)
6629 fatal_error ("total size of local variables exceeds architecture limit");
6631 if (!TARGET_PACKED_STACK
)
6633 cfun_frame_layout
.backchain_offset
= 0;
6634 cfun_frame_layout
.f0_offset
= 16 * UNITS_PER_WORD
;
6635 cfun_frame_layout
.f4_offset
= cfun_frame_layout
.f0_offset
+ 2 * 8;
6636 cfun_frame_layout
.f8_offset
= -cfun_frame_layout
.high_fprs
* 8;
6637 cfun_frame_layout
.gprs_offset
= (cfun_frame_layout
.first_save_gpr_slot
6640 else if (TARGET_BACKCHAIN
) /* kernel stack layout */
6642 cfun_frame_layout
.backchain_offset
= (STACK_POINTER_OFFSET
6644 cfun_frame_layout
.gprs_offset
6645 = (cfun_frame_layout
.backchain_offset
6646 - (STACK_POINTER_REGNUM
- cfun_frame_layout
.first_save_gpr_slot
+ 1)
6651 cfun_frame_layout
.f4_offset
6652 = (cfun_frame_layout
.gprs_offset
6653 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6655 cfun_frame_layout
.f0_offset
6656 = (cfun_frame_layout
.f4_offset
6657 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6661 /* On 31 bit we have to care about alignment of the
6662 floating point regs to provide fastest access. */
6663 cfun_frame_layout
.f0_offset
6664 = ((cfun_frame_layout
.gprs_offset
6665 & ~(STACK_BOUNDARY
/ BITS_PER_UNIT
- 1))
6666 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6668 cfun_frame_layout
.f4_offset
6669 = (cfun_frame_layout
.f0_offset
6670 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6673 else /* no backchain */
6675 cfun_frame_layout
.f4_offset
6676 = (STACK_POINTER_OFFSET
6677 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6679 cfun_frame_layout
.f0_offset
6680 = (cfun_frame_layout
.f4_offset
6681 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6683 cfun_frame_layout
.gprs_offset
6684 = cfun_frame_layout
.f0_offset
- cfun_gprs_save_area_size
;
6687 if (current_function_is_leaf
6688 && !TARGET_TPF_PROFILING
6689 && cfun_frame_layout
.frame_size
== 0
6690 && !cfun_save_high_fprs_p
6691 && !current_function_calls_alloca
6692 && !current_function_stdarg
)
6695 if (!TARGET_PACKED_STACK
)
6696 cfun_frame_layout
.frame_size
+= (STACK_POINTER_OFFSET
6697 + current_function_outgoing_args_size
6698 + cfun_frame_layout
.high_fprs
* 8);
6701 if (TARGET_BACKCHAIN
)
6702 cfun_frame_layout
.frame_size
+= UNITS_PER_WORD
;
6704 /* No alignment trouble here because f8-f15 are only saved under
6706 cfun_frame_layout
.f8_offset
= (MIN (MIN (cfun_frame_layout
.f0_offset
,
6707 cfun_frame_layout
.f4_offset
),
6708 cfun_frame_layout
.gprs_offset
)
6709 - cfun_frame_layout
.high_fprs
* 8);
6711 cfun_frame_layout
.frame_size
+= cfun_frame_layout
.high_fprs
* 8;
6713 for (i
= 0; i
< 8; i
++)
6714 if (cfun_fpr_bit_p (i
))
6715 cfun_frame_layout
.frame_size
+= 8;
6717 cfun_frame_layout
.frame_size
+= cfun_gprs_save_area_size
;
6719 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
6720 the frame size to sustain 8 byte alignment of stack frames. */
6721 cfun_frame_layout
.frame_size
= ((cfun_frame_layout
.frame_size
+
6722 STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
6723 & ~(STACK_BOUNDARY
/ BITS_PER_UNIT
- 1));
6725 cfun_frame_layout
.frame_size
+= current_function_outgoing_args_size
;
6729 /* Generate frame layout. Fills in register and frame data for the current
6730 function in cfun->machine. This routine can be called multiple times;
6731 it will re-do the complete frame layout every time. */
6734 s390_init_frame_layout (void)
6736 HOST_WIDE_INT frame_size
;
6738 int clobbered_regs
[16];
6740 /* On S/390 machines, we may need to perform branch splitting, which
6741 will require both base and return address register. We have no
6742 choice but to assume we're going to need them until right at the
6743 end of the machine dependent reorg phase. */
6744 if (!TARGET_CPU_ZARCH
)
6745 cfun
->machine
->split_branches_pending_p
= true;
6749 frame_size
= cfun_frame_layout
.frame_size
;
6751 /* Try to predict whether we'll need the base register. */
6752 base_used
= cfun
->machine
->split_branches_pending_p
6753 || current_function_uses_const_pool
6754 || (!DISP_IN_RANGE (frame_size
)
6755 && !CONST_OK_FOR_K (frame_size
));
6757 /* Decide which register to use as literal pool base. In small
6758 leaf functions, try to use an unused call-clobbered register
6759 as base register to avoid save/restore overhead. */
6761 cfun
->machine
->base_reg
= NULL_RTX
;
6762 else if (current_function_is_leaf
&& !df_regs_ever_live_p (5))
6763 cfun
->machine
->base_reg
= gen_rtx_REG (Pmode
, 5);
6765 cfun
->machine
->base_reg
= gen_rtx_REG (Pmode
, BASE_REGNUM
);
6767 s390_register_info (clobbered_regs
);
6770 while (frame_size
!= cfun_frame_layout
.frame_size
);
6773 /* Update frame layout. Recompute actual register save data based on
6774 current info and update regs_ever_live for the special registers.
6775 May be called multiple times, but may never cause *more* registers
6776 to be saved than s390_init_frame_layout allocated room for. */
6779 s390_update_frame_layout (void)
6781 int clobbered_regs
[16];
6783 s390_register_info (clobbered_regs
);
6785 df_set_regs_ever_live (BASE_REGNUM
,
6786 clobbered_regs
[BASE_REGNUM
] ? true : false);
6787 df_set_regs_ever_live (RETURN_REGNUM
,
6788 clobbered_regs
[RETURN_REGNUM
] ? true : false);
6789 df_set_regs_ever_live (STACK_POINTER_REGNUM
,
6790 clobbered_regs
[STACK_POINTER_REGNUM
] ? true : false);
6792 if (cfun
->machine
->base_reg
)
6793 df_set_regs_ever_live (REGNO (cfun
->machine
->base_reg
), true);
6796 /* Return true if it is legal to put a value with MODE into REGNO. */
6799 s390_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
6801 switch (REGNO_REG_CLASS (regno
))
6804 if (REGNO_PAIR_OK (regno
, mode
))
6806 if (mode
== SImode
|| mode
== DImode
)
6809 if (FLOAT_MODE_P (mode
) && GET_MODE_CLASS (mode
) != MODE_VECTOR_FLOAT
)
6814 if (FRAME_REGNO_P (regno
) && mode
== Pmode
)
6819 if (REGNO_PAIR_OK (regno
, mode
))
6822 || (mode
!= TFmode
&& mode
!= TCmode
&& mode
!= TDmode
))
6827 if (GET_MODE_CLASS (mode
) == MODE_CC
)
6831 if (REGNO_PAIR_OK (regno
, mode
))
6833 if (mode
== SImode
|| mode
== Pmode
)
6844 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
6847 s390_hard_regno_rename_ok (unsigned int old_reg
, unsigned int new_reg
)
6849 /* Once we've decided upon a register to use as base register, it must
6850 no longer be used for any other purpose. */
6851 if (cfun
->machine
->base_reg
)
6852 if (REGNO (cfun
->machine
->base_reg
) == old_reg
6853 || REGNO (cfun
->machine
->base_reg
) == new_reg
)
6859 /* Maximum number of registers to represent a value of mode MODE
6860 in a register of class CLASS. */
6863 s390_class_max_nregs (enum reg_class
class, enum machine_mode mode
)
6868 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
6869 return 2 * ((GET_MODE_SIZE (mode
) / 2 + 8 - 1) / 8);
6871 return (GET_MODE_SIZE (mode
) + 8 - 1) / 8;
6873 return (GET_MODE_SIZE (mode
) + 4 - 1) / 4;
6877 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6880 /* Return true if register FROM can be eliminated via register TO. */
6883 s390_can_eliminate (int from
, int to
)
6885 /* On zSeries machines, we have not marked the base register as fixed.
6886 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
6887 If a function requires the base register, we say here that this
6888 elimination cannot be performed. This will cause reload to free
6889 up the base register (as if it were fixed). On the other hand,
6890 if the current function does *not* require the base register, we
6891 say here the elimination succeeds, which in turn allows reload
6892 to allocate the base register for any other purpose. */
6893 if (from
== BASE_REGNUM
&& to
== BASE_REGNUM
)
6895 if (TARGET_CPU_ZARCH
)
6897 s390_init_frame_layout ();
6898 return cfun
->machine
->base_reg
== NULL_RTX
;
6904 /* Everything else must point into the stack frame. */
6905 gcc_assert (to
== STACK_POINTER_REGNUM
6906 || to
== HARD_FRAME_POINTER_REGNUM
);
6908 gcc_assert (from
== FRAME_POINTER_REGNUM
6909 || from
== ARG_POINTER_REGNUM
6910 || from
== RETURN_ADDRESS_POINTER_REGNUM
);
6912 /* Make sure we actually saved the return address. */
6913 if (from
== RETURN_ADDRESS_POINTER_REGNUM
)
6914 if (!current_function_calls_eh_return
6915 && !current_function_stdarg
6916 && !cfun_frame_layout
.save_return_addr_p
)
6922 /* Return offset between register FROM and TO initially after prolog. */
6925 s390_initial_elimination_offset (int from
, int to
)
6927 HOST_WIDE_INT offset
;
6930 /* ??? Why are we called for non-eliminable pairs? */
6931 if (!s390_can_eliminate (from
, to
))
6936 case FRAME_POINTER_REGNUM
:
6937 offset
= (get_frame_size()
6938 + STACK_POINTER_OFFSET
6939 + current_function_outgoing_args_size
);
6942 case ARG_POINTER_REGNUM
:
6943 s390_init_frame_layout ();
6944 offset
= cfun_frame_layout
.frame_size
+ STACK_POINTER_OFFSET
;
6947 case RETURN_ADDRESS_POINTER_REGNUM
:
6948 s390_init_frame_layout ();
6949 index
= RETURN_REGNUM
- cfun_frame_layout
.first_save_gpr_slot
;
6950 gcc_assert (index
>= 0);
6951 offset
= cfun_frame_layout
.frame_size
+ cfun_frame_layout
.gprs_offset
;
6952 offset
+= index
* UNITS_PER_WORD
;
6966 /* Emit insn to save fpr REGNUM at offset OFFSET relative
6967 to register BASE. Return generated insn. */
6970 save_fpr (rtx base
, int offset
, int regnum
)
6973 addr
= gen_rtx_MEM (DFmode
, plus_constant (base
, offset
));
6975 if (regnum
>= 16 && regnum
<= (16 + FP_ARG_NUM_REG
))
6976 set_mem_alias_set (addr
, get_varargs_alias_set ());
6978 set_mem_alias_set (addr
, get_frame_alias_set ());
6980 return emit_move_insn (addr
, gen_rtx_REG (DFmode
, regnum
));
6983 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
6984 to register BASE. Return generated insn. */
6987 restore_fpr (rtx base
, int offset
, int regnum
)
6990 addr
= gen_rtx_MEM (DFmode
, plus_constant (base
, offset
));
6991 set_mem_alias_set (addr
, get_frame_alias_set ());
6993 return emit_move_insn (gen_rtx_REG (DFmode
, regnum
), addr
);
6996 /* Generate insn to save registers FIRST to LAST into
6997 the register save area located at offset OFFSET
6998 relative to register BASE. */
7001 save_gprs (rtx base
, int offset
, int first
, int last
)
7003 rtx addr
, insn
, note
;
7006 addr
= plus_constant (base
, offset
);
7007 addr
= gen_rtx_MEM (Pmode
, addr
);
7009 set_mem_alias_set (addr
, get_frame_alias_set ());
7011 /* Special-case single register. */
7015 insn
= gen_movdi (addr
, gen_rtx_REG (Pmode
, first
));
7017 insn
= gen_movsi (addr
, gen_rtx_REG (Pmode
, first
));
7019 RTX_FRAME_RELATED_P (insn
) = 1;
7024 insn
= gen_store_multiple (addr
,
7025 gen_rtx_REG (Pmode
, first
),
7026 GEN_INT (last
- first
+ 1));
7028 if (first
<= 6 && current_function_stdarg
)
7029 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
7031 rtx mem
= XEXP (XVECEXP (PATTERN (insn
), 0, i
), 0);
7034 set_mem_alias_set (mem
, get_varargs_alias_set ());
7037 /* We need to set the FRAME_RELATED flag on all SETs
7038 inside the store-multiple pattern.
7040 However, we must not emit DWARF records for registers 2..5
7041 if they are stored for use by variable arguments ...
7043 ??? Unfortunately, it is not enough to simply not the
7044 FRAME_RELATED flags for those SETs, because the first SET
7045 of the PARALLEL is always treated as if it had the flag
7046 set, even if it does not. Therefore we emit a new pattern
7047 without those registers as REG_FRAME_RELATED_EXPR note. */
7051 rtx pat
= PATTERN (insn
);
7053 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
7054 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
)
7055 RTX_FRAME_RELATED_P (XVECEXP (pat
, 0, i
)) = 1;
7057 RTX_FRAME_RELATED_P (insn
) = 1;
7061 addr
= plus_constant (base
, offset
+ (6 - first
) * UNITS_PER_WORD
);
7062 note
= gen_store_multiple (gen_rtx_MEM (Pmode
, addr
),
7063 gen_rtx_REG (Pmode
, 6),
7064 GEN_INT (last
- 6 + 1));
7065 note
= PATTERN (note
);
7068 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
7069 note
, REG_NOTES (insn
));
7071 for (i
= 0; i
< XVECLEN (note
, 0); i
++)
7072 if (GET_CODE (XVECEXP (note
, 0, i
)) == SET
)
7073 RTX_FRAME_RELATED_P (XVECEXP (note
, 0, i
)) = 1;
7075 RTX_FRAME_RELATED_P (insn
) = 1;
7081 /* Generate insn to restore registers FIRST to LAST from
7082 the register save area located at offset OFFSET
7083 relative to register BASE. */
7086 restore_gprs (rtx base
, int offset
, int first
, int last
)
7090 addr
= plus_constant (base
, offset
);
7091 addr
= gen_rtx_MEM (Pmode
, addr
);
7092 set_mem_alias_set (addr
, get_frame_alias_set ());
7094 /* Special-case single register. */
7098 insn
= gen_movdi (gen_rtx_REG (Pmode
, first
), addr
);
7100 insn
= gen_movsi (gen_rtx_REG (Pmode
, first
), addr
);
7105 insn
= gen_load_multiple (gen_rtx_REG (Pmode
, first
),
7107 GEN_INT (last
- first
+ 1));
7111 /* Return insn sequence to load the GOT register. */
7113 static GTY(()) rtx got_symbol
;
7115 s390_load_got (void)
7121 got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
7122 SYMBOL_REF_FLAGS (got_symbol
) = SYMBOL_FLAG_LOCAL
;
7127 if (TARGET_CPU_ZARCH
)
7129 emit_move_insn (pic_offset_table_rtx
, got_symbol
);
7135 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, got_symbol
),
7136 UNSPEC_LTREL_OFFSET
);
7137 offset
= gen_rtx_CONST (Pmode
, offset
);
7138 offset
= force_const_mem (Pmode
, offset
);
7140 emit_move_insn (pic_offset_table_rtx
, offset
);
7142 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, XEXP (offset
, 0)),
7144 offset
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, offset
);
7146 emit_move_insn (pic_offset_table_rtx
, offset
);
7149 insns
= get_insns ();
7154 /* Expand the prologue into a bunch of separate insns. */
7157 s390_emit_prologue (void)
7165 /* Complete frame layout. */
7167 s390_update_frame_layout ();
7169 /* Annotate all constant pool references to let the scheduler know
7170 they implicitly use the base register. */
7172 push_topmost_sequence ();
7174 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
7177 annotate_constant_pool_refs (&PATTERN (insn
));
7178 df_insn_rescan (insn
);
7181 pop_topmost_sequence ();
7183 /* Choose best register to use for temp use within prologue.
7184 See below for why TPF must use the register 1. */
7186 if (!has_hard_reg_initial_val (Pmode
, RETURN_REGNUM
)
7187 && !current_function_is_leaf
7188 && !TARGET_TPF_PROFILING
)
7189 temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
7191 temp_reg
= gen_rtx_REG (Pmode
, 1);
7193 /* Save call saved gprs. */
7194 if (cfun_frame_layout
.first_save_gpr
!= -1)
7196 insn
= save_gprs (stack_pointer_rtx
,
7197 cfun_frame_layout
.gprs_offset
+
7198 UNITS_PER_WORD
* (cfun_frame_layout
.first_save_gpr
7199 - cfun_frame_layout
.first_save_gpr_slot
),
7200 cfun_frame_layout
.first_save_gpr
,
7201 cfun_frame_layout
.last_save_gpr
);
7205 /* Dummy insn to mark literal pool slot. */
7207 if (cfun
->machine
->base_reg
)
7208 emit_insn (gen_main_pool (cfun
->machine
->base_reg
));
7210 offset
= cfun_frame_layout
.f0_offset
;
7212 /* Save f0 and f2. */
7213 for (i
= 0; i
< 2; i
++)
7215 if (cfun_fpr_bit_p (i
))
7217 save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
7220 else if (!TARGET_PACKED_STACK
)
7224 /* Save f4 and f6. */
7225 offset
= cfun_frame_layout
.f4_offset
;
7226 for (i
= 2; i
< 4; i
++)
7228 if (cfun_fpr_bit_p (i
))
7230 insn
= save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
7233 /* If f4 and f6 are call clobbered they are saved due to stdargs and
7234 therefore are not frame related. */
7235 if (!call_really_used_regs
[i
+ 16])
7236 RTX_FRAME_RELATED_P (insn
) = 1;
7238 else if (!TARGET_PACKED_STACK
)
7242 if (TARGET_PACKED_STACK
7243 && cfun_save_high_fprs_p
7244 && cfun_frame_layout
.f8_offset
+ cfun_frame_layout
.high_fprs
* 8 > 0)
7246 offset
= (cfun_frame_layout
.f8_offset
7247 + (cfun_frame_layout
.high_fprs
- 1) * 8);
7249 for (i
= 15; i
> 7 && offset
>= 0; i
--)
7250 if (cfun_fpr_bit_p (i
))
7252 insn
= save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
7254 RTX_FRAME_RELATED_P (insn
) = 1;
7257 if (offset
>= cfun_frame_layout
.f8_offset
)
7261 if (!TARGET_PACKED_STACK
)
7262 next_fpr
= cfun_save_high_fprs_p
? 31 : 0;
7264 /* Decrement stack pointer. */
7266 if (cfun_frame_layout
.frame_size
> 0)
7268 rtx frame_off
= GEN_INT (-cfun_frame_layout
.frame_size
);
7270 if (s390_stack_size
)
7272 HOST_WIDE_INT stack_guard
;
7274 if (s390_stack_guard
)
7275 stack_guard
= s390_stack_guard
;
7278 /* If no value for stack guard is provided the smallest power of 2
7279 larger than the current frame size is chosen. */
7281 while (stack_guard
< cfun_frame_layout
.frame_size
)
7285 if (cfun_frame_layout
.frame_size
>= s390_stack_size
)
7287 warning (0, "frame size of function %qs is "
7288 HOST_WIDE_INT_PRINT_DEC
7289 " bytes exceeding user provided stack limit of "
7290 HOST_WIDE_INT_PRINT_DEC
" bytes. "
7291 "An unconditional trap is added.",
7292 current_function_name(), cfun_frame_layout
.frame_size
,
7294 emit_insn (gen_trap ());
7298 HOST_WIDE_INT stack_check_mask
= ((s390_stack_size
- 1)
7299 & ~(stack_guard
- 1));
7300 rtx t
= gen_rtx_AND (Pmode
, stack_pointer_rtx
,
7301 GEN_INT (stack_check_mask
));
7303 gen_cmpdi (t
, const0_rtx
);
7305 gen_cmpsi (t
, const0_rtx
);
7307 emit_insn (gen_conditional_trap (gen_rtx_EQ (CCmode
,
7308 gen_rtx_REG (CCmode
,
7315 if (s390_warn_framesize
> 0
7316 && cfun_frame_layout
.frame_size
>= s390_warn_framesize
)
7317 warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC
" bytes",
7318 current_function_name (), cfun_frame_layout
.frame_size
);
7320 if (s390_warn_dynamicstack_p
&& cfun
->calls_alloca
)
7321 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
7323 /* Save incoming stack pointer into temp reg. */
7324 if (TARGET_BACKCHAIN
|| next_fpr
)
7325 insn
= emit_insn (gen_move_insn (temp_reg
, stack_pointer_rtx
));
7327 /* Subtract frame size from stack pointer. */
7329 if (DISP_IN_RANGE (INTVAL (frame_off
)))
7331 insn
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
7332 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
7334 insn
= emit_insn (insn
);
7338 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
7339 frame_off
= force_const_mem (Pmode
, frame_off
);
7341 insn
= emit_insn (gen_add2_insn (stack_pointer_rtx
, frame_off
));
7342 annotate_constant_pool_refs (&PATTERN (insn
));
7345 RTX_FRAME_RELATED_P (insn
) = 1;
7347 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
7348 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
7349 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
7350 GEN_INT (-cfun_frame_layout
.frame_size
))),
7353 /* Set backchain. */
7355 if (TARGET_BACKCHAIN
)
7357 if (cfun_frame_layout
.backchain_offset
)
7358 addr
= gen_rtx_MEM (Pmode
,
7359 plus_constant (stack_pointer_rtx
,
7360 cfun_frame_layout
.backchain_offset
));
7362 addr
= gen_rtx_MEM (Pmode
, stack_pointer_rtx
);
7363 set_mem_alias_set (addr
, get_frame_alias_set ());
7364 insn
= emit_insn (gen_move_insn (addr
, temp_reg
));
7367 /* If we support asynchronous exceptions (e.g. for Java),
7368 we need to make sure the backchain pointer is set up
7369 before any possibly trapping memory access. */
7371 if (TARGET_BACKCHAIN
&& flag_non_call_exceptions
)
7373 addr
= gen_rtx_MEM (BLKmode
, gen_rtx_SCRATCH (VOIDmode
));
7374 emit_insn (gen_rtx_CLOBBER (VOIDmode
, addr
));
7378 /* Save fprs 8 - 15 (64 bit ABI). */
7380 if (cfun_save_high_fprs_p
&& next_fpr
)
7382 insn
= emit_insn (gen_add2_insn (temp_reg
,
7383 GEN_INT (cfun_frame_layout
.f8_offset
)));
7387 for (i
= 24; i
<= next_fpr
; i
++)
7388 if (cfun_fpr_bit_p (i
- 16))
7390 rtx addr
= plus_constant (stack_pointer_rtx
,
7391 cfun_frame_layout
.frame_size
7392 + cfun_frame_layout
.f8_offset
7395 insn
= save_fpr (temp_reg
, offset
, i
);
7397 RTX_FRAME_RELATED_P (insn
) = 1;
7399 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
7400 gen_rtx_SET (VOIDmode
,
7401 gen_rtx_MEM (DFmode
, addr
),
7402 gen_rtx_REG (DFmode
, i
)),
7407 /* Set frame pointer, if needed. */
7409 if (frame_pointer_needed
)
7411 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
7412 RTX_FRAME_RELATED_P (insn
) = 1;
7415 /* Set up got pointer, if needed. */
7417 if (flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
7419 rtx insns
= s390_load_got ();
7421 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
7422 annotate_constant_pool_refs (&PATTERN (insn
));
7427 if (TARGET_TPF_PROFILING
)
7429 /* Generate a BAS instruction to serve as a function
7430 entry intercept to facilitate the use of tracing
7431 algorithms located at the branch target. */
7432 emit_insn (gen_prologue_tpf ());
7434 /* Emit a blockage here so that all code
7435 lies between the profiling mechanisms. */
7436 emit_insn (gen_blockage ());
7440 /* Expand the epilogue into a bunch of separate insns. */
7443 s390_emit_epilogue (bool sibcall
)
7445 rtx frame_pointer
, return_reg
;
7446 int area_bottom
, area_top
, offset
= 0;
7451 if (TARGET_TPF_PROFILING
)
7454 /* Generate a BAS instruction to serve as a function
7455 entry intercept to facilitate the use of tracing
7456 algorithms located at the branch target. */
7458 /* Emit a blockage here so that all code
7459 lies between the profiling mechanisms. */
7460 emit_insn (gen_blockage ());
7462 emit_insn (gen_epilogue_tpf ());
7465 /* Check whether to use frame or stack pointer for restore. */
7467 frame_pointer
= (frame_pointer_needed
7468 ? hard_frame_pointer_rtx
: stack_pointer_rtx
);
7470 s390_frame_area (&area_bottom
, &area_top
);
7472 /* Check whether we can access the register save area.
7473 If not, increment the frame pointer as required. */
7475 if (area_top
<= area_bottom
)
7477 /* Nothing to restore. */
7479 else if (DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_bottom
)
7480 && DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_top
- 1))
7482 /* Area is in range. */
7483 offset
= cfun_frame_layout
.frame_size
;
7487 rtx insn
, frame_off
;
7489 offset
= area_bottom
< 0 ? -area_bottom
: 0;
7490 frame_off
= GEN_INT (cfun_frame_layout
.frame_size
- offset
);
7492 if (DISP_IN_RANGE (INTVAL (frame_off
)))
7494 insn
= gen_rtx_SET (VOIDmode
, frame_pointer
,
7495 gen_rtx_PLUS (Pmode
, frame_pointer
, frame_off
));
7496 insn
= emit_insn (insn
);
7500 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
7501 frame_off
= force_const_mem (Pmode
, frame_off
);
7503 insn
= emit_insn (gen_add2_insn (frame_pointer
, frame_off
));
7504 annotate_constant_pool_refs (&PATTERN (insn
));
7508 /* Restore call saved fprs. */
7512 if (cfun_save_high_fprs_p
)
7514 next_offset
= cfun_frame_layout
.f8_offset
;
7515 for (i
= 24; i
< 32; i
++)
7517 if (cfun_fpr_bit_p (i
- 16))
7519 restore_fpr (frame_pointer
,
7520 offset
+ next_offset
, i
);
7529 next_offset
= cfun_frame_layout
.f4_offset
;
7530 for (i
= 18; i
< 20; i
++)
7532 if (cfun_fpr_bit_p (i
- 16))
7534 restore_fpr (frame_pointer
,
7535 offset
+ next_offset
, i
);
7538 else if (!TARGET_PACKED_STACK
)
7544 /* Return register. */
7546 return_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
7548 /* Restore call saved gprs. */
7550 if (cfun_frame_layout
.first_restore_gpr
!= -1)
7555 /* Check for global register and save them
7556 to stack location from where they get restored. */
7558 for (i
= cfun_frame_layout
.first_restore_gpr
;
7559 i
<= cfun_frame_layout
.last_restore_gpr
;
7562 /* These registers are special and need to be
7563 restored in any case. */
7564 if (i
== STACK_POINTER_REGNUM
7565 || i
== RETURN_REGNUM
7567 || (flag_pic
&& i
== (int)PIC_OFFSET_TABLE_REGNUM
))
7572 addr
= plus_constant (frame_pointer
,
7573 offset
+ cfun_frame_layout
.gprs_offset
7574 + (i
- cfun_frame_layout
.first_save_gpr_slot
)
7576 addr
= gen_rtx_MEM (Pmode
, addr
);
7577 set_mem_alias_set (addr
, get_frame_alias_set ());
7578 emit_move_insn (addr
, gen_rtx_REG (Pmode
, i
));
7584 /* Fetch return address from stack before load multiple,
7585 this will do good for scheduling. */
7587 if (cfun_frame_layout
.save_return_addr_p
7588 || (cfun_frame_layout
.first_restore_gpr
< BASE_REGNUM
7589 && cfun_frame_layout
.last_restore_gpr
> RETURN_REGNUM
))
7591 int return_regnum
= find_unused_clobbered_reg();
7594 return_reg
= gen_rtx_REG (Pmode
, return_regnum
);
7596 addr
= plus_constant (frame_pointer
,
7597 offset
+ cfun_frame_layout
.gprs_offset
7599 - cfun_frame_layout
.first_save_gpr_slot
)
7601 addr
= gen_rtx_MEM (Pmode
, addr
);
7602 set_mem_alias_set (addr
, get_frame_alias_set ());
7603 emit_move_insn (return_reg
, addr
);
7607 insn
= restore_gprs (frame_pointer
,
7608 offset
+ cfun_frame_layout
.gprs_offset
7609 + (cfun_frame_layout
.first_restore_gpr
7610 - cfun_frame_layout
.first_save_gpr_slot
)
7612 cfun_frame_layout
.first_restore_gpr
,
7613 cfun_frame_layout
.last_restore_gpr
);
7620 /* Return to caller. */
7622 p
= rtvec_alloc (2);
7624 RTVEC_ELT (p
, 0) = gen_rtx_RETURN (VOIDmode
);
7625 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
, return_reg
);
7626 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
7631 /* Return the size in bytes of a function argument of
7632 type TYPE and/or mode MODE. At least one of TYPE or
7633 MODE must be specified. */
7636 s390_function_arg_size (enum machine_mode mode
, tree type
)
7639 return int_size_in_bytes (type
);
7641 /* No type info available for some library calls ... */
7642 if (mode
!= BLKmode
)
7643 return GET_MODE_SIZE (mode
);
7645 /* If we have neither type nor mode, abort */
7649 /* Return true if a function argument of type TYPE and mode MODE
7650 is to be passed in a floating-point register, if available. */
7653 s390_function_arg_float (enum machine_mode mode
, tree type
)
7655 int size
= s390_function_arg_size (mode
, type
);
7659 /* Soft-float changes the ABI: no floating-point registers are used. */
7660 if (TARGET_SOFT_FLOAT
)
7663 /* No type info available for some library calls ... */
7665 return mode
== SFmode
|| mode
== DFmode
|| mode
== SDmode
|| mode
== DDmode
;
7667 /* The ABI says that record types with a single member are treated
7668 just like that member would be. */
7669 while (TREE_CODE (type
) == RECORD_TYPE
)
7671 tree field
, single
= NULL_TREE
;
7673 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
7675 if (TREE_CODE (field
) != FIELD_DECL
)
7678 if (single
== NULL_TREE
)
7679 single
= TREE_TYPE (field
);
7684 if (single
== NULL_TREE
)
7690 return TREE_CODE (type
) == REAL_TYPE
;
7693 /* Return true if a function argument of type TYPE and mode MODE
7694 is to be passed in an integer register, or a pair of integer
7695 registers, if available. */
7698 s390_function_arg_integer (enum machine_mode mode
, tree type
)
7700 int size
= s390_function_arg_size (mode
, type
);
7704 /* No type info available for some library calls ... */
7706 return GET_MODE_CLASS (mode
) == MODE_INT
7707 || (TARGET_SOFT_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
));
7709 /* We accept small integral (and similar) types. */
7710 if (INTEGRAL_TYPE_P (type
)
7711 || POINTER_TYPE_P (type
)
7712 || TREE_CODE (type
) == OFFSET_TYPE
7713 || (TARGET_SOFT_FLOAT
&& TREE_CODE (type
) == REAL_TYPE
))
7716 /* We also accept structs of size 1, 2, 4, 8 that are not
7717 passed in floating-point registers. */
7718 if (AGGREGATE_TYPE_P (type
)
7719 && exact_log2 (size
) >= 0
7720 && !s390_function_arg_float (mode
, type
))
7726 /* Return 1 if a function argument of type TYPE and mode MODE
7727 is to be passed by reference. The ABI specifies that only
7728 structures of size 1, 2, 4, or 8 bytes are passed by value,
7729 all other structures (and complex numbers) are passed by
7733 s390_pass_by_reference (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
,
7734 enum machine_mode mode
, tree type
,
7735 bool named ATTRIBUTE_UNUSED
)
7737 int size
= s390_function_arg_size (mode
, type
);
7743 if (AGGREGATE_TYPE_P (type
) && exact_log2 (size
) < 0)
7746 if (TREE_CODE (type
) == COMPLEX_TYPE
7747 || TREE_CODE (type
) == VECTOR_TYPE
)
7754 /* Update the data in CUM to advance over an argument of mode MODE and
7755 data type TYPE. (TYPE is null for libcalls where that information
7756 may not be available.). The boolean NAMED specifies whether the
7757 argument is a named argument (as opposed to an unnamed argument
7758 matching an ellipsis). */
7761 s390_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
7762 tree type
, int named ATTRIBUTE_UNUSED
)
7764 if (s390_function_arg_float (mode
, type
))
7768 else if (s390_function_arg_integer (mode
, type
))
7770 int size
= s390_function_arg_size (mode
, type
);
7771 cum
->gprs
+= ((size
+ UNITS_PER_WORD
-1) / UNITS_PER_WORD
);
7777 /* Define where to put the arguments to a function.
7778 Value is zero to push the argument on the stack,
7779 or a hard register in which to store the argument.
7781 MODE is the argument's machine mode.
7782 TYPE is the data type of the argument (as a tree).
7783 This is null for libcalls where that information may
7785 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7786 the preceding args and about the function being called.
7787 NAMED is nonzero if this argument is a named parameter
7788 (otherwise it is an extra parameter matching an ellipsis).
7790 On S/390, we use general purpose registers 2 through 6 to
7791 pass integer, pointer, and certain structure arguments, and
7792 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
7793 to pass floating point arguments. All remaining arguments
7794 are pushed to the stack. */
7797 s390_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
, tree type
,
7798 int named ATTRIBUTE_UNUSED
)
7800 if (s390_function_arg_float (mode
, type
))
7802 if (cum
->fprs
+ 1 > FP_ARG_NUM_REG
)
7805 return gen_rtx_REG (mode
, cum
->fprs
+ 16);
7807 else if (s390_function_arg_integer (mode
, type
))
7809 int size
= s390_function_arg_size (mode
, type
);
7810 int n_gprs
= (size
+ UNITS_PER_WORD
-1) / UNITS_PER_WORD
;
7812 if (cum
->gprs
+ n_gprs
> GP_ARG_NUM_REG
)
7815 return gen_rtx_REG (mode
, cum
->gprs
+ 2);
7818 /* After the real arguments, expand_call calls us once again
7819 with a void_type_node type. Whatever we return here is
7820 passed as operand 2 to the call expanders.
7822 We don't need this feature ... */
7823 else if (type
== void_type_node
)
7829 /* Return true if return values of type TYPE should be returned
7830 in a memory buffer whose address is passed by the caller as
7831 hidden first argument. */
7834 s390_return_in_memory (tree type
, tree fundecl ATTRIBUTE_UNUSED
)
7836 /* We accept small integral (and similar) types. */
7837 if (INTEGRAL_TYPE_P (type
)
7838 || POINTER_TYPE_P (type
)
7839 || TREE_CODE (type
) == OFFSET_TYPE
7840 || TREE_CODE (type
) == REAL_TYPE
)
7841 return int_size_in_bytes (type
) > 8;
7843 /* Aggregates and similar constructs are always returned
7845 if (AGGREGATE_TYPE_P (type
)
7846 || TREE_CODE (type
) == COMPLEX_TYPE
7847 || TREE_CODE (type
) == VECTOR_TYPE
)
7850 /* ??? We get called on all sorts of random stuff from
7851 aggregate_value_p. We can't abort, but it's not clear
7852 what's safe to return. Pretend it's a struct I guess. */
7856 /* Define where to return a (scalar) value of type TYPE.
7857 If TYPE is null, define where to return a (scalar)
7858 value of mode MODE from a libcall. */
7861 s390_function_value (tree type
, enum machine_mode mode
)
7865 int unsignedp
= TYPE_UNSIGNED (type
);
7866 mode
= promote_mode (type
, TYPE_MODE (type
), &unsignedp
, 1);
7869 gcc_assert (GET_MODE_CLASS (mode
) == MODE_INT
|| SCALAR_FLOAT_MODE_P (mode
));
7870 gcc_assert (GET_MODE_SIZE (mode
) <= 8);
7872 if (TARGET_HARD_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
))
7873 return gen_rtx_REG (mode
, 16);
7875 return gen_rtx_REG (mode
, 2);
7879 /* Create and return the va_list datatype.
7881 On S/390, va_list is an array type equivalent to
7883 typedef struct __va_list_tag
7887 void *__overflow_arg_area;
7888 void *__reg_save_area;
7891 where __gpr and __fpr hold the number of general purpose
7892 or floating point arguments used up to now, respectively,
7893 __overflow_arg_area points to the stack location of the
7894 next argument passed on the stack, and __reg_save_area
7895 always points to the start of the register area in the
7896 call frame of the current function. The function prologue
7897 saves all registers used for argument passing into this
7898 area if the function uses variable arguments. */
7901 s390_build_builtin_va_list (void)
7903 tree f_gpr
, f_fpr
, f_ovf
, f_sav
, record
, type_decl
;
7905 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
7908 build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
7910 f_gpr
= build_decl (FIELD_DECL
, get_identifier ("__gpr"),
7911 long_integer_type_node
);
7912 f_fpr
= build_decl (FIELD_DECL
, get_identifier ("__fpr"),
7913 long_integer_type_node
);
7914 f_ovf
= build_decl (FIELD_DECL
, get_identifier ("__overflow_arg_area"),
7916 f_sav
= build_decl (FIELD_DECL
, get_identifier ("__reg_save_area"),
7919 va_list_gpr_counter_field
= f_gpr
;
7920 va_list_fpr_counter_field
= f_fpr
;
7922 DECL_FIELD_CONTEXT (f_gpr
) = record
;
7923 DECL_FIELD_CONTEXT (f_fpr
) = record
;
7924 DECL_FIELD_CONTEXT (f_ovf
) = record
;
7925 DECL_FIELD_CONTEXT (f_sav
) = record
;
7927 TREE_CHAIN (record
) = type_decl
;
7928 TYPE_NAME (record
) = type_decl
;
7929 TYPE_FIELDS (record
) = f_gpr
;
7930 TREE_CHAIN (f_gpr
) = f_fpr
;
7931 TREE_CHAIN (f_fpr
) = f_ovf
;
7932 TREE_CHAIN (f_ovf
) = f_sav
;
7934 layout_type (record
);
7936 /* The correct type is an array type of one element. */
7937 return build_array_type (record
, build_index_type (size_zero_node
));
7940 /* Implement va_start by filling the va_list structure VALIST.
7941 STDARG_P is always true, and ignored.
7942 NEXTARG points to the first anonymous stack argument.
7944 The following global variables are used to initialize
7945 the va_list structure:
7947 current_function_args_info:
7948 holds number of gprs and fprs used for named arguments.
7949 current_function_arg_offset_rtx:
7950 holds the offset of the first anonymous stack argument
7951 (relative to the virtual arg pointer). */
7954 s390_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
7956 HOST_WIDE_INT n_gpr
, n_fpr
;
7958 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
7959 tree gpr
, fpr
, ovf
, sav
, t
;
7961 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
7962 f_fpr
= TREE_CHAIN (f_gpr
);
7963 f_ovf
= TREE_CHAIN (f_fpr
);
7964 f_sav
= TREE_CHAIN (f_ovf
);
7966 valist
= build_va_arg_indirect_ref (valist
);
7967 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
7968 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
7969 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
7970 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
7972 /* Count number of gp and fp argument registers used. */
7974 n_gpr
= current_function_args_info
.gprs
;
7975 n_fpr
= current_function_args_info
.fprs
;
7977 if (cfun
->va_list_gpr_size
)
7979 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (gpr
), gpr
,
7980 build_int_cst (NULL_TREE
, n_gpr
));
7981 TREE_SIDE_EFFECTS (t
) = 1;
7982 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
7985 if (cfun
->va_list_fpr_size
)
7987 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (fpr
), fpr
,
7988 build_int_cst (NULL_TREE
, n_fpr
));
7989 TREE_SIDE_EFFECTS (t
) = 1;
7990 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
7993 /* Find the overflow area. */
7994 if (n_gpr
+ cfun
->va_list_gpr_size
> GP_ARG_NUM_REG
7995 || n_fpr
+ cfun
->va_list_fpr_size
> FP_ARG_NUM_REG
)
7997 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
7999 off
= INTVAL (current_function_arg_offset_rtx
);
8000 off
= off
< 0 ? 0 : off
;
8001 if (TARGET_DEBUG_ARG
)
8002 fprintf (stderr
, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
8003 (int)n_gpr
, (int)n_fpr
, off
);
8005 t
= build2 (PLUS_EXPR
, TREE_TYPE (ovf
), t
, build_int_cst (NULL_TREE
, off
));
8007 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (ovf
), ovf
, t
);
8008 TREE_SIDE_EFFECTS (t
) = 1;
8009 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8012 /* Find the register save area. */
8013 if ((cfun
->va_list_gpr_size
&& n_gpr
< GP_ARG_NUM_REG
)
8014 || (cfun
->va_list_fpr_size
&& n_fpr
< FP_ARG_NUM_REG
))
8016 t
= make_tree (TREE_TYPE (sav
), return_address_pointer_rtx
);
8017 t
= build2 (PLUS_EXPR
, TREE_TYPE (sav
), t
,
8018 build_int_cst (NULL_TREE
, -RETURN_REGNUM
* UNITS_PER_WORD
));
8020 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (sav
), sav
, t
);
8021 TREE_SIDE_EFFECTS (t
) = 1;
8022 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8026 /* Implement va_arg by updating the va_list structure
8027 VALIST as required to retrieve an argument of type
8028 TYPE, and returning that argument.
8030 Generates code equivalent to:
8032 if (integral value) {
8033 if (size <= 4 && args.gpr < 5 ||
8034 size > 4 && args.gpr < 4 )
8035 ret = args.reg_save_area[args.gpr+8]
8037 ret = *args.overflow_arg_area++;
8038 } else if (float value) {
8040 ret = args.reg_save_area[args.fpr+64]
8042 ret = *args.overflow_arg_area++;
8043 } else if (aggregate value) {
8045 ret = *args.reg_save_area[args.gpr]
8047 ret = **args.overflow_arg_area++;
8051 s390_gimplify_va_arg (tree valist
, tree type
, tree
*pre_p
,
8052 tree
*post_p ATTRIBUTE_UNUSED
)
8054 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
8055 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
8056 int indirect_p
, size
, n_reg
, sav_ofs
, sav_scale
, max_reg
;
8057 tree lab_false
, lab_over
, addr
;
8059 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
8060 f_fpr
= TREE_CHAIN (f_gpr
);
8061 f_ovf
= TREE_CHAIN (f_fpr
);
8062 f_sav
= TREE_CHAIN (f_ovf
);
8064 valist
= build_va_arg_indirect_ref (valist
);
8065 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
8066 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
8067 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
8068 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
8070 size
= int_size_in_bytes (type
);
8072 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
8074 if (TARGET_DEBUG_ARG
)
8076 fprintf (stderr
, "va_arg: aggregate type");
8080 /* Aggregates are passed by reference. */
8085 /* kernel stack layout on 31 bit: It is assumed here that no padding
8086 will be added by s390_frame_info because for va_args always an even
8087 number of gprs has to be saved r15-r2 = 14 regs. */
8088 sav_ofs
= 2 * UNITS_PER_WORD
;
8089 sav_scale
= UNITS_PER_WORD
;
8090 size
= UNITS_PER_WORD
;
8091 max_reg
= GP_ARG_NUM_REG
- n_reg
;
8093 else if (s390_function_arg_float (TYPE_MODE (type
), type
))
8095 if (TARGET_DEBUG_ARG
)
8097 fprintf (stderr
, "va_arg: float type");
8101 /* FP args go in FP registers, if present. */
8105 sav_ofs
= 16 * UNITS_PER_WORD
;
8107 max_reg
= FP_ARG_NUM_REG
- n_reg
;
8111 if (TARGET_DEBUG_ARG
)
8113 fprintf (stderr
, "va_arg: other type");
8117 /* Otherwise into GP registers. */
8120 n_reg
= (size
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
8122 /* kernel stack layout on 31 bit: It is assumed here that no padding
8123 will be added by s390_frame_info because for va_args always an even
8124 number of gprs has to be saved r15-r2 = 14 regs. */
8125 sav_ofs
= 2 * UNITS_PER_WORD
;
8127 if (size
< UNITS_PER_WORD
)
8128 sav_ofs
+= UNITS_PER_WORD
- size
;
8130 sav_scale
= UNITS_PER_WORD
;
8131 max_reg
= GP_ARG_NUM_REG
- n_reg
;
8134 /* Pull the value out of the saved registers ... */
8136 lab_false
= create_artificial_label ();
8137 lab_over
= create_artificial_label ();
8138 addr
= create_tmp_var (ptr_type_node
, "addr");
8139 DECL_POINTER_ALIAS_SET (addr
) = get_varargs_alias_set ();
8141 t
= fold_convert (TREE_TYPE (reg
), size_int (max_reg
));
8142 t
= build2 (GT_EXPR
, boolean_type_node
, reg
, t
);
8143 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
8144 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
8145 gimplify_and_add (t
, pre_p
);
8147 t
= build2 (PLUS_EXPR
, ptr_type_node
, sav
,
8148 fold_convert (ptr_type_node
, size_int (sav_ofs
)));
8149 u
= build2 (MULT_EXPR
, TREE_TYPE (reg
), reg
,
8150 fold_convert (TREE_TYPE (reg
), size_int (sav_scale
)));
8151 t
= build2 (PLUS_EXPR
, ptr_type_node
, t
, fold_convert (ptr_type_node
, u
));
8153 t
= build2 (GIMPLE_MODIFY_STMT
, void_type_node
, addr
, t
);
8154 gimplify_and_add (t
, pre_p
);
8156 t
= build1 (GOTO_EXPR
, void_type_node
, lab_over
);
8157 gimplify_and_add (t
, pre_p
);
8159 t
= build1 (LABEL_EXPR
, void_type_node
, lab_false
);
8160 append_to_statement_list (t
, pre_p
);
8163 /* ... Otherwise out of the overflow area. */
8166 if (size
< UNITS_PER_WORD
)
8167 t
= build2 (PLUS_EXPR
, ptr_type_node
, t
,
8168 fold_convert (ptr_type_node
, size_int (UNITS_PER_WORD
- size
)));
8170 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
8172 u
= build2 (GIMPLE_MODIFY_STMT
, void_type_node
, addr
, t
);
8173 gimplify_and_add (u
, pre_p
);
8175 t
= build2 (PLUS_EXPR
, ptr_type_node
, t
,
8176 fold_convert (ptr_type_node
, size_int (size
)));
8177 t
= build2 (GIMPLE_MODIFY_STMT
, ptr_type_node
, ovf
, t
);
8178 gimplify_and_add (t
, pre_p
);
8180 t
= build1 (LABEL_EXPR
, void_type_node
, lab_over
);
8181 append_to_statement_list (t
, pre_p
);
8184 /* Increment register save count. */
8186 u
= build2 (PREINCREMENT_EXPR
, TREE_TYPE (reg
), reg
,
8187 fold_convert (TREE_TYPE (reg
), size_int (n_reg
)));
8188 gimplify_and_add (u
, pre_p
);
8192 t
= build_pointer_type (build_pointer_type (type
));
8193 addr
= fold_convert (t
, addr
);
8194 addr
= build_va_arg_indirect_ref (addr
);
8198 t
= build_pointer_type (type
);
8199 addr
= fold_convert (t
, addr
);
8202 return build_va_arg_indirect_ref (addr
);
8210 S390_BUILTIN_THREAD_POINTER
,
8211 S390_BUILTIN_SET_THREAD_POINTER
,
8216 static unsigned int const code_for_builtin_64
[S390_BUILTIN_max
] = {
8221 static unsigned int const code_for_builtin_31
[S390_BUILTIN_max
] = {
8227 s390_init_builtins (void)
8231 ftype
= build_function_type (ptr_type_node
, void_list_node
);
8232 add_builtin_function ("__builtin_thread_pointer", ftype
,
8233 S390_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
8236 ftype
= build_function_type_list (void_type_node
, ptr_type_node
, NULL_TREE
);
8237 add_builtin_function ("__builtin_set_thread_pointer", ftype
,
8238 S390_BUILTIN_SET_THREAD_POINTER
, BUILT_IN_MD
,
8242 /* Expand an expression EXP that calls a built-in function,
8243 with result going to TARGET if that's convenient
8244 (and in mode MODE if that's convenient).
8245 SUBTARGET may be used as the target for computing one of EXP's operands.
8246 IGNORE is nonzero if the value is to be ignored. */
8249 s390_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
8250 enum machine_mode mode ATTRIBUTE_UNUSED
,
8251 int ignore ATTRIBUTE_UNUSED
)
8255 unsigned int const *code_for_builtin
=
8256 TARGET_64BIT
? code_for_builtin_64
: code_for_builtin_31
;
8258 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8259 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8260 enum insn_code icode
;
8261 rtx op
[MAX_ARGS
], pat
;
8265 call_expr_arg_iterator iter
;
8267 if (fcode
>= S390_BUILTIN_max
)
8268 internal_error ("bad builtin fcode");
8269 icode
= code_for_builtin
[fcode
];
8271 internal_error ("bad builtin fcode");
8273 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
8276 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
8278 const struct insn_operand_data
*insn_op
;
8280 if (arg
== error_mark_node
)
8282 if (arity
> MAX_ARGS
)
8285 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
8287 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, 0);
8289 if (!(*insn_op
->predicate
) (op
[arity
], insn_op
->mode
))
8290 op
[arity
] = copy_to_mode_reg (insn_op
->mode
, op
[arity
]);
8296 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
8298 || GET_MODE (target
) != tmode
8299 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8300 target
= gen_reg_rtx (tmode
);
8306 pat
= GEN_FCN (icode
) (target
);
8310 pat
= GEN_FCN (icode
) (target
, op
[0]);
8312 pat
= GEN_FCN (icode
) (op
[0]);
8315 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
8331 /* Output assembly code for the trampoline template to
8334 On S/390, we use gpr 1 internally in the trampoline code;
8335 gpr 0 is used to hold the static chain. */
8338 s390_trampoline_template (FILE *file
)
8341 op
[0] = gen_rtx_REG (Pmode
, 0);
8342 op
[1] = gen_rtx_REG (Pmode
, 1);
8346 output_asm_insn ("basr\t%1,0", op
);
8347 output_asm_insn ("lmg\t%0,%1,14(%1)", op
);
8348 output_asm_insn ("br\t%1", op
);
8349 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 10));
8353 output_asm_insn ("basr\t%1,0", op
);
8354 output_asm_insn ("lm\t%0,%1,6(%1)", op
);
8355 output_asm_insn ("br\t%1", op
);
8356 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 8));
8360 /* Emit RTL insns to initialize the variable parts of a trampoline.
8361 FNADDR is an RTX for the address of the function's pure code.
8362 CXT is an RTX for the static chain value for the function. */
8365 s390_initialize_trampoline (rtx addr
, rtx fnaddr
, rtx cxt
)
8367 emit_move_insn (gen_rtx_MEM (Pmode
,
8368 memory_address (Pmode
,
8369 plus_constant (addr
, (TARGET_64BIT
? 16 : 8)))), cxt
);
8370 emit_move_insn (gen_rtx_MEM (Pmode
,
8371 memory_address (Pmode
,
8372 plus_constant (addr
, (TARGET_64BIT
? 24 : 12)))), fnaddr
);
8375 /* Output assembler code to FILE to increment profiler label # LABELNO
8376 for profiling a function entry. */
8379 s390_function_profiler (FILE *file
, int labelno
)
8384 ASM_GENERATE_INTERNAL_LABEL (label
, "LP", labelno
);
8386 fprintf (file
, "# function profiler \n");
8388 op
[0] = gen_rtx_REG (Pmode
, RETURN_REGNUM
);
8389 op
[1] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
8390 op
[1] = gen_rtx_MEM (Pmode
, plus_constant (op
[1], UNITS_PER_WORD
));
8392 op
[2] = gen_rtx_REG (Pmode
, 1);
8393 op
[3] = gen_rtx_SYMBOL_REF (Pmode
, label
);
8394 SYMBOL_REF_FLAGS (op
[3]) = SYMBOL_FLAG_LOCAL
;
8396 op
[4] = gen_rtx_SYMBOL_REF (Pmode
, "_mcount");
8399 op
[4] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[4]), UNSPEC_PLT
);
8400 op
[4] = gen_rtx_CONST (Pmode
, op
[4]);
8405 output_asm_insn ("stg\t%0,%1", op
);
8406 output_asm_insn ("larl\t%2,%3", op
);
8407 output_asm_insn ("brasl\t%0,%4", op
);
8408 output_asm_insn ("lg\t%0,%1", op
);
8412 op
[6] = gen_label_rtx ();
8414 output_asm_insn ("st\t%0,%1", op
);
8415 output_asm_insn ("bras\t%2,%l6", op
);
8416 output_asm_insn (".long\t%4", op
);
8417 output_asm_insn (".long\t%3", op
);
8418 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
8419 output_asm_insn ("l\t%0,0(%2)", op
);
8420 output_asm_insn ("l\t%2,4(%2)", op
);
8421 output_asm_insn ("basr\t%0,%0", op
);
8422 output_asm_insn ("l\t%0,%1", op
);
8426 op
[5] = gen_label_rtx ();
8427 op
[6] = gen_label_rtx ();
8429 output_asm_insn ("st\t%0,%1", op
);
8430 output_asm_insn ("bras\t%2,%l6", op
);
8431 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[5]));
8432 output_asm_insn (".long\t%4-%l5", op
);
8433 output_asm_insn (".long\t%3-%l5", op
);
8434 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
8435 output_asm_insn ("lr\t%0,%2", op
);
8436 output_asm_insn ("a\t%0,0(%2)", op
);
8437 output_asm_insn ("a\t%2,4(%2)", op
);
8438 output_asm_insn ("basr\t%0,%0", op
);
8439 output_asm_insn ("l\t%0,%1", op
);
8443 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
8444 into its SYMBOL_REF_FLAGS. */
8447 s390_encode_section_info (tree decl
, rtx rtl
, int first
)
8449 default_encode_section_info (decl
, rtl
, first
);
8451 /* If a variable has a forced alignment to < 2 bytes, mark it with
8452 SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL operand. */
8453 if (TREE_CODE (decl
) == VAR_DECL
8454 && DECL_USER_ALIGN (decl
) && DECL_ALIGN (decl
) < 16)
8455 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_ALIGN1
;
8458 /* Output thunk to FILE that implements a C++ virtual function call (with
8459 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
8460 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
8461 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
8462 relative to the resulting this pointer. */
8465 s390_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
8466 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
8472 /* Operand 0 is the target function. */
8473 op
[0] = XEXP (DECL_RTL (function
), 0);
8474 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (op
[0]))
8477 op
[0] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[0]),
8478 TARGET_64BIT
? UNSPEC_PLT
: UNSPEC_GOT
);
8479 op
[0] = gen_rtx_CONST (Pmode
, op
[0]);
8482 /* Operand 1 is the 'this' pointer. */
8483 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
8484 op
[1] = gen_rtx_REG (Pmode
, 3);
8486 op
[1] = gen_rtx_REG (Pmode
, 2);
8488 /* Operand 2 is the delta. */
8489 op
[2] = GEN_INT (delta
);
8491 /* Operand 3 is the vcall_offset. */
8492 op
[3] = GEN_INT (vcall_offset
);
8494 /* Operand 4 is the temporary register. */
8495 op
[4] = gen_rtx_REG (Pmode
, 1);
8497 /* Operands 5 to 8 can be used as labels. */
8503 /* Operand 9 can be used for temporary register. */
8506 /* Generate code. */
8509 /* Setup literal pool pointer if required. */
8510 if ((!DISP_IN_RANGE (delta
)
8511 && !CONST_OK_FOR_K (delta
)
8512 && !CONST_OK_FOR_Os (delta
))
8513 || (!DISP_IN_RANGE (vcall_offset
)
8514 && !CONST_OK_FOR_K (vcall_offset
)
8515 && !CONST_OK_FOR_Os (vcall_offset
)))
8517 op
[5] = gen_label_rtx ();
8518 output_asm_insn ("larl\t%4,%5", op
);
8521 /* Add DELTA to this pointer. */
8524 if (CONST_OK_FOR_J (delta
))
8525 output_asm_insn ("la\t%1,%2(%1)", op
);
8526 else if (DISP_IN_RANGE (delta
))
8527 output_asm_insn ("lay\t%1,%2(%1)", op
);
8528 else if (CONST_OK_FOR_K (delta
))
8529 output_asm_insn ("aghi\t%1,%2", op
);
8530 else if (CONST_OK_FOR_Os (delta
))
8531 output_asm_insn ("agfi\t%1,%2", op
);
8534 op
[6] = gen_label_rtx ();
8535 output_asm_insn ("agf\t%1,%6-%5(%4)", op
);
8539 /* Perform vcall adjustment. */
8542 if (DISP_IN_RANGE (vcall_offset
))
8544 output_asm_insn ("lg\t%4,0(%1)", op
);
8545 output_asm_insn ("ag\t%1,%3(%4)", op
);
8547 else if (CONST_OK_FOR_K (vcall_offset
))
8549 output_asm_insn ("lghi\t%4,%3", op
);
8550 output_asm_insn ("ag\t%4,0(%1)", op
);
8551 output_asm_insn ("ag\t%1,0(%4)", op
);
8553 else if (CONST_OK_FOR_Os (vcall_offset
))
8555 output_asm_insn ("lgfi\t%4,%3", op
);
8556 output_asm_insn ("ag\t%4,0(%1)", op
);
8557 output_asm_insn ("ag\t%1,0(%4)", op
);
8561 op
[7] = gen_label_rtx ();
8562 output_asm_insn ("llgf\t%4,%7-%5(%4)", op
);
8563 output_asm_insn ("ag\t%4,0(%1)", op
);
8564 output_asm_insn ("ag\t%1,0(%4)", op
);
8568 /* Jump to target. */
8569 output_asm_insn ("jg\t%0", op
);
8571 /* Output literal pool if required. */
8574 output_asm_insn (".align\t4", op
);
8575 targetm
.asm_out
.internal_label (file
, "L",
8576 CODE_LABEL_NUMBER (op
[5]));
8580 targetm
.asm_out
.internal_label (file
, "L",
8581 CODE_LABEL_NUMBER (op
[6]));
8582 output_asm_insn (".long\t%2", op
);
8586 targetm
.asm_out
.internal_label (file
, "L",
8587 CODE_LABEL_NUMBER (op
[7]));
8588 output_asm_insn (".long\t%3", op
);
8593 /* Setup base pointer if required. */
8595 || (!DISP_IN_RANGE (delta
)
8596 && !CONST_OK_FOR_K (delta
)
8597 && !CONST_OK_FOR_Os (delta
))
8598 || (!DISP_IN_RANGE (delta
)
8599 && !CONST_OK_FOR_K (vcall_offset
)
8600 && !CONST_OK_FOR_Os (vcall_offset
)))
8602 op
[5] = gen_label_rtx ();
8603 output_asm_insn ("basr\t%4,0", op
);
8604 targetm
.asm_out
.internal_label (file
, "L",
8605 CODE_LABEL_NUMBER (op
[5]));
8608 /* Add DELTA to this pointer. */
8611 if (CONST_OK_FOR_J (delta
))
8612 output_asm_insn ("la\t%1,%2(%1)", op
);
8613 else if (DISP_IN_RANGE (delta
))
8614 output_asm_insn ("lay\t%1,%2(%1)", op
);
8615 else if (CONST_OK_FOR_K (delta
))
8616 output_asm_insn ("ahi\t%1,%2", op
);
8617 else if (CONST_OK_FOR_Os (delta
))
8618 output_asm_insn ("afi\t%1,%2", op
);
8621 op
[6] = gen_label_rtx ();
8622 output_asm_insn ("a\t%1,%6-%5(%4)", op
);
8626 /* Perform vcall adjustment. */
8629 if (CONST_OK_FOR_J (vcall_offset
))
8631 output_asm_insn ("l\t%4,0(%1)", op
);
8632 output_asm_insn ("a\t%1,%3(%4)", op
);
8634 else if (DISP_IN_RANGE (vcall_offset
))
8636 output_asm_insn ("l\t%4,0(%1)", op
);
8637 output_asm_insn ("ay\t%1,%3(%4)", op
);
8639 else if (CONST_OK_FOR_K (vcall_offset
))
8641 output_asm_insn ("lhi\t%4,%3", op
);
8642 output_asm_insn ("a\t%4,0(%1)", op
);
8643 output_asm_insn ("a\t%1,0(%4)", op
);
8645 else if (CONST_OK_FOR_Os (vcall_offset
))
8647 output_asm_insn ("iilf\t%4,%3", op
);
8648 output_asm_insn ("a\t%4,0(%1)", op
);
8649 output_asm_insn ("a\t%1,0(%4)", op
);
8653 op
[7] = gen_label_rtx ();
8654 output_asm_insn ("l\t%4,%7-%5(%4)", op
);
8655 output_asm_insn ("a\t%4,0(%1)", op
);
8656 output_asm_insn ("a\t%1,0(%4)", op
);
8659 /* We had to clobber the base pointer register.
8660 Re-setup the base pointer (with a different base). */
8661 op
[5] = gen_label_rtx ();
8662 output_asm_insn ("basr\t%4,0", op
);
8663 targetm
.asm_out
.internal_label (file
, "L",
8664 CODE_LABEL_NUMBER (op
[5]));
8667 /* Jump to target. */
8668 op
[8] = gen_label_rtx ();
8671 output_asm_insn ("l\t%4,%8-%5(%4)", op
);
8673 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
8674 /* We cannot call through .plt, since .plt requires %r12 loaded. */
8675 else if (flag_pic
== 1)
8677 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
8678 output_asm_insn ("l\t%4,%0(%4)", op
);
8680 else if (flag_pic
== 2)
8682 op
[9] = gen_rtx_REG (Pmode
, 0);
8683 output_asm_insn ("l\t%9,%8-4-%5(%4)", op
);
8684 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
8685 output_asm_insn ("ar\t%4,%9", op
);
8686 output_asm_insn ("l\t%4,0(%4)", op
);
8689 output_asm_insn ("br\t%4", op
);
8691 /* Output literal pool. */
8692 output_asm_insn (".align\t4", op
);
8694 if (nonlocal
&& flag_pic
== 2)
8695 output_asm_insn (".long\t%0", op
);
8698 op
[0] = gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
8699 SYMBOL_REF_FLAGS (op
[0]) = SYMBOL_FLAG_LOCAL
;
8702 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[8]));
8704 output_asm_insn (".long\t%0", op
);
8706 output_asm_insn (".long\t%0-%5", op
);
8710 targetm
.asm_out
.internal_label (file
, "L",
8711 CODE_LABEL_NUMBER (op
[6]));
8712 output_asm_insn (".long\t%2", op
);
8716 targetm
.asm_out
.internal_label (file
, "L",
8717 CODE_LABEL_NUMBER (op
[7]));
8718 output_asm_insn (".long\t%3", op
);
8724 s390_valid_pointer_mode (enum machine_mode mode
)
8726 return (mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
));
8729 /* Checks whether the given CALL_EXPR would use a caller
8730 saved register. This is used to decide whether sibling call
8731 optimization could be performed on the respective function
8735 s390_call_saved_register_used (tree call_expr
)
8737 CUMULATIVE_ARGS cum
;
8739 enum machine_mode mode
;
8744 INIT_CUMULATIVE_ARGS (cum
, NULL
, NULL
, 0, 0);
8746 for (i
= 0; i
< call_expr_nargs (call_expr
); i
++)
8748 parameter
= CALL_EXPR_ARG (call_expr
, i
);
8749 gcc_assert (parameter
);
8751 /* For an undeclared variable passed as parameter we will get
8752 an ERROR_MARK node here. */
8753 if (TREE_CODE (parameter
) == ERROR_MARK
)
8756 type
= TREE_TYPE (parameter
);
8759 mode
= TYPE_MODE (type
);
8762 if (pass_by_reference (&cum
, mode
, type
, true))
8765 type
= build_pointer_type (type
);
8768 parm_rtx
= s390_function_arg (&cum
, mode
, type
, 0);
8770 s390_function_arg_advance (&cum
, mode
, type
, 0);
8772 if (parm_rtx
&& REG_P (parm_rtx
))
8775 reg
< HARD_REGNO_NREGS (REGNO (parm_rtx
), GET_MODE (parm_rtx
));
8777 if (! call_used_regs
[reg
+ REGNO (parm_rtx
)])
8784 /* Return true if the given call expression can be
8785 turned into a sibling call.
8786 DECL holds the declaration of the function to be called whereas
8787 EXP is the call expression itself. */
8790 s390_function_ok_for_sibcall (tree decl
, tree exp
)
8792 /* The TPF epilogue uses register 1. */
8793 if (TARGET_TPF_PROFILING
)
8796 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
8797 which would have to be restored before the sibcall. */
8798 if (!TARGET_64BIT
&& flag_pic
&& decl
&& !targetm
.binds_local_p (decl
))
8801 /* Register 6 on s390 is available as an argument register but unfortunately
8802 "caller saved". This makes functions needing this register for arguments
8803 not suitable for sibcalls. */
8804 return !s390_call_saved_register_used (exp
);
8807 /* Return the fixed registers used for condition codes. */
8810 s390_fixed_condition_code_regs (unsigned int *p1
, unsigned int *p2
)
8813 *p2
= INVALID_REGNUM
;
8818 /* This function is used by the call expanders of the machine description.
8819 It emits the call insn itself together with the necessary operations
8820 to adjust the target address and returns the emitted insn.
8821 ADDR_LOCATION is the target address rtx
8822 TLS_CALL the location of the thread-local symbol
8823 RESULT_REG the register where the result of the call should be stored
8824 RETADDR_REG the register where the return address should be stored
8825 If this parameter is NULL_RTX the call is considered
8826 to be a sibling call. */
8829 s390_emit_call (rtx addr_location
, rtx tls_call
, rtx result_reg
,
8832 bool plt_call
= false;
8838 /* Direct function calls need special treatment. */
8839 if (GET_CODE (addr_location
) == SYMBOL_REF
)
8841 /* When calling a global routine in PIC mode, we must
8842 replace the symbol itself with the PLT stub. */
8843 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (addr_location
))
8845 addr_location
= gen_rtx_UNSPEC (Pmode
,
8846 gen_rtvec (1, addr_location
),
8848 addr_location
= gen_rtx_CONST (Pmode
, addr_location
);
8852 /* Unless we can use the bras(l) insn, force the
8853 routine address into a register. */
8854 if (!TARGET_SMALL_EXEC
&& !TARGET_CPU_ZARCH
)
8857 addr_location
= legitimize_pic_address (addr_location
, 0);
8859 addr_location
= force_reg (Pmode
, addr_location
);
8863 /* If it is already an indirect call or the code above moved the
8864 SYMBOL_REF to somewhere else make sure the address can be found in
8866 if (retaddr_reg
== NULL_RTX
8867 && GET_CODE (addr_location
) != SYMBOL_REF
8870 emit_move_insn (gen_rtx_REG (Pmode
, SIBCALL_REGNUM
), addr_location
);
8871 addr_location
= gen_rtx_REG (Pmode
, SIBCALL_REGNUM
);
8874 addr_location
= gen_rtx_MEM (QImode
, addr_location
);
8875 call
= gen_rtx_CALL (VOIDmode
, addr_location
, const0_rtx
);
8877 if (result_reg
!= NULL_RTX
)
8878 call
= gen_rtx_SET (VOIDmode
, result_reg
, call
);
8880 if (retaddr_reg
!= NULL_RTX
)
8882 clobber
= gen_rtx_CLOBBER (VOIDmode
, retaddr_reg
);
8884 if (tls_call
!= NULL_RTX
)
8885 vec
= gen_rtvec (3, call
, clobber
,
8886 gen_rtx_USE (VOIDmode
, tls_call
));
8888 vec
= gen_rtvec (2, call
, clobber
);
8890 call
= gen_rtx_PARALLEL (VOIDmode
, vec
);
8893 insn
= emit_call_insn (call
);
8895 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
8896 if ((!TARGET_64BIT
&& plt_call
) || tls_call
!= NULL_RTX
)
8898 /* s390_function_ok_for_sibcall should
8899 have denied sibcalls in this case. */
8900 gcc_assert (retaddr_reg
!= NULL_RTX
);
8902 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
8907 /* Implement CONDITIONAL_REGISTER_USAGE. */
8910 s390_conditional_register_usage (void)
8916 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
8917 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
8919 if (TARGET_CPU_ZARCH
)
8921 fixed_regs
[BASE_REGNUM
] = 0;
8922 call_used_regs
[BASE_REGNUM
] = 0;
8923 fixed_regs
[RETURN_REGNUM
] = 0;
8924 call_used_regs
[RETURN_REGNUM
] = 0;
8928 for (i
= 24; i
< 32; i
++)
8929 call_used_regs
[i
] = call_really_used_regs
[i
] = 0;
8933 for (i
= 18; i
< 20; i
++)
8934 call_used_regs
[i
] = call_really_used_regs
[i
] = 0;
8937 if (TARGET_SOFT_FLOAT
)
8939 for (i
= 16; i
< 32; i
++)
8940 call_used_regs
[i
] = fixed_regs
[i
] = 1;
8944 /* Corresponding function to eh_return expander. */
8946 static GTY(()) rtx s390_tpf_eh_return_symbol
;
8948 s390_emit_tpf_eh_return (rtx target
)
8952 if (!s390_tpf_eh_return_symbol
)
8953 s390_tpf_eh_return_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tpf_eh_return");
8955 reg
= gen_rtx_REG (Pmode
, 2);
8957 emit_move_insn (reg
, target
);
8958 insn
= s390_emit_call (s390_tpf_eh_return_symbol
, NULL_RTX
, reg
,
8959 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
8960 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
8962 emit_move_insn (EH_RETURN_HANDLER_RTX
, reg
);
8965 /* Rework the prologue/epilogue to avoid saving/restoring
8966 registers unnecessarily. */
8969 s390_optimize_prologue (void)
8971 rtx insn
, new_insn
, next_insn
;
8973 /* Do a final recompute of the frame-related data. */
8975 s390_update_frame_layout ();
8977 /* If all special registers are in fact used, there's nothing we
8978 can do, so no point in walking the insn list. */
8980 if (cfun_frame_layout
.first_save_gpr
<= BASE_REGNUM
8981 && cfun_frame_layout
.last_save_gpr
>= BASE_REGNUM
8982 && (TARGET_CPU_ZARCH
8983 || (cfun_frame_layout
.first_save_gpr
<= RETURN_REGNUM
8984 && cfun_frame_layout
.last_save_gpr
>= RETURN_REGNUM
)))
8987 /* Search for prologue/epilogue insns and replace them. */
8989 for (insn
= get_insns (); insn
; insn
= next_insn
)
8991 int first
, last
, off
;
8992 rtx set
, base
, offset
;
8994 next_insn
= NEXT_INSN (insn
);
8996 if (GET_CODE (insn
) != INSN
)
8999 if (GET_CODE (PATTERN (insn
)) == PARALLEL
9000 && store_multiple_operation (PATTERN (insn
), VOIDmode
))
9002 set
= XVECEXP (PATTERN (insn
), 0, 0);
9003 first
= REGNO (SET_SRC (set
));
9004 last
= first
+ XVECLEN (PATTERN (insn
), 0) - 1;
9005 offset
= const0_rtx
;
9006 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
9007 off
= INTVAL (offset
);
9009 if (GET_CODE (base
) != REG
|| off
< 0)
9011 if (cfun_frame_layout
.first_save_gpr
!= -1
9012 && (cfun_frame_layout
.first_save_gpr
< first
9013 || cfun_frame_layout
.last_save_gpr
> last
))
9015 if (REGNO (base
) != STACK_POINTER_REGNUM
9016 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
9018 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
9021 if (cfun_frame_layout
.first_save_gpr
!= -1)
9023 new_insn
= save_gprs (base
,
9024 off
+ (cfun_frame_layout
.first_save_gpr
9025 - first
) * UNITS_PER_WORD
,
9026 cfun_frame_layout
.first_save_gpr
,
9027 cfun_frame_layout
.last_save_gpr
);
9028 new_insn
= emit_insn_before (new_insn
, insn
);
9029 INSN_ADDRESSES_NEW (new_insn
, -1);
9036 if (cfun_frame_layout
.first_save_gpr
== -1
9037 && GET_CODE (PATTERN (insn
)) == SET
9038 && GET_CODE (SET_SRC (PATTERN (insn
))) == REG
9039 && (REGNO (SET_SRC (PATTERN (insn
))) == BASE_REGNUM
9040 || (!TARGET_CPU_ZARCH
9041 && REGNO (SET_SRC (PATTERN (insn
))) == RETURN_REGNUM
))
9042 && GET_CODE (SET_DEST (PATTERN (insn
))) == MEM
)
9044 set
= PATTERN (insn
);
9045 first
= REGNO (SET_SRC (set
));
9046 offset
= const0_rtx
;
9047 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
9048 off
= INTVAL (offset
);
9050 if (GET_CODE (base
) != REG
|| off
< 0)
9052 if (REGNO (base
) != STACK_POINTER_REGNUM
9053 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
9060 if (GET_CODE (PATTERN (insn
)) == PARALLEL
9061 && load_multiple_operation (PATTERN (insn
), VOIDmode
))
9063 set
= XVECEXP (PATTERN (insn
), 0, 0);
9064 first
= REGNO (SET_DEST (set
));
9065 last
= first
+ XVECLEN (PATTERN (insn
), 0) - 1;
9066 offset
= const0_rtx
;
9067 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
9068 off
= INTVAL (offset
);
9070 if (GET_CODE (base
) != REG
|| off
< 0)
9072 if (cfun_frame_layout
.first_restore_gpr
!= -1
9073 && (cfun_frame_layout
.first_restore_gpr
< first
9074 || cfun_frame_layout
.last_restore_gpr
> last
))
9076 if (REGNO (base
) != STACK_POINTER_REGNUM
9077 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
9079 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
9082 if (cfun_frame_layout
.first_restore_gpr
!= -1)
9084 new_insn
= restore_gprs (base
,
9085 off
+ (cfun_frame_layout
.first_restore_gpr
9086 - first
) * UNITS_PER_WORD
,
9087 cfun_frame_layout
.first_restore_gpr
,
9088 cfun_frame_layout
.last_restore_gpr
);
9089 new_insn
= emit_insn_before (new_insn
, insn
);
9090 INSN_ADDRESSES_NEW (new_insn
, -1);
9097 if (cfun_frame_layout
.first_restore_gpr
== -1
9098 && GET_CODE (PATTERN (insn
)) == SET
9099 && GET_CODE (SET_DEST (PATTERN (insn
))) == REG
9100 && (REGNO (SET_DEST (PATTERN (insn
))) == BASE_REGNUM
9101 || (!TARGET_CPU_ZARCH
9102 && REGNO (SET_DEST (PATTERN (insn
))) == RETURN_REGNUM
))
9103 && GET_CODE (SET_SRC (PATTERN (insn
))) == MEM
)
9105 set
= PATTERN (insn
);
9106 first
= REGNO (SET_DEST (set
));
9107 offset
= const0_rtx
;
9108 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
9109 off
= INTVAL (offset
);
9111 if (GET_CODE (base
) != REG
|| off
< 0)
9113 if (REGNO (base
) != STACK_POINTER_REGNUM
9114 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
9123 /* Perform machine-dependent processing. */
9128 bool pool_overflow
= false;
9130 /* Make sure all splits have been performed; splits after
9131 machine_dependent_reorg might confuse insn length counts. */
9132 split_all_insns_noflow ();
9134 /* From here on decomposed literal pool addresses must be accepted. */
9135 cfun
->machine
->decomposed_literal_pool_addresses_ok_p
= true;
9137 /* Install the main literal pool and the associated base
9138 register load insns.
9140 In addition, there are two problematic situations we need
9143 - the literal pool might be > 4096 bytes in size, so that
9144 some of its elements cannot be directly accessed
9146 - a branch target might be > 64K away from the branch, so that
9147 it is not possible to use a PC-relative instruction.
9149 To fix those, we split the single literal pool into multiple
9150 pool chunks, reloading the pool base register at various
9151 points throughout the function to ensure it always points to
9152 the pool chunk the following code expects, and / or replace
9153 PC-relative branches by absolute branches.
9155 However, the two problems are interdependent: splitting the
9156 literal pool can move a branch further away from its target,
9157 causing the 64K limit to overflow, and on the other hand,
9158 replacing a PC-relative branch by an absolute branch means
9159 we need to put the branch target address into the literal
9160 pool, possibly causing it to overflow.
9162 So, we loop trying to fix up both problems until we manage
9163 to satisfy both conditions at the same time. Note that the
9164 loop is guaranteed to terminate as every pass of the loop
9165 strictly decreases the total number of PC-relative branches
9166 in the function. (This is not completely true as there
9167 might be branch-over-pool insns introduced by chunkify_start.
9168 Those never need to be split however.) */
9172 struct constant_pool
*pool
= NULL
;
9174 /* Collect the literal pool. */
9177 pool
= s390_mainpool_start ();
9179 pool_overflow
= true;
9182 /* If literal pool overflowed, start to chunkify it. */
9184 pool
= s390_chunkify_start ();
9186 /* Split out-of-range branches. If this has created new
9187 literal pool entries, cancel current chunk list and
9188 recompute it. zSeries machines have large branch
9189 instructions, so we never need to split a branch. */
9190 if (!TARGET_CPU_ZARCH
&& s390_split_branches ())
9193 s390_chunkify_cancel (pool
);
9195 s390_mainpool_cancel (pool
);
9200 /* If we made it up to here, both conditions are satisfied.
9201 Finish up literal pool related changes. */
9203 s390_chunkify_finish (pool
);
9205 s390_mainpool_finish (pool
);
9207 /* We're done splitting branches. */
9208 cfun
->machine
->split_branches_pending_p
= false;
9212 /* Generate out-of-pool execute target insns. */
9213 if (TARGET_CPU_ZARCH
)
9215 rtx insn
, label
, target
;
9217 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9219 label
= s390_execute_label (insn
);
9223 gcc_assert (label
!= const0_rtx
);
9225 target
= emit_label (XEXP (label
, 0));
9226 INSN_ADDRESSES_NEW (target
, -1);
9228 target
= emit_insn (s390_execute_target (insn
));
9229 INSN_ADDRESSES_NEW (target
, -1);
9233 /* Try to optimize prologue and epilogue further. */
9234 s390_optimize_prologue ();
9238 /* Initialize GCC target structure. */
9240 #undef TARGET_ASM_ALIGNED_HI_OP
9241 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
9242 #undef TARGET_ASM_ALIGNED_DI_OP
9243 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
9244 #undef TARGET_ASM_INTEGER
9245 #define TARGET_ASM_INTEGER s390_assemble_integer
9247 #undef TARGET_ASM_OPEN_PAREN
9248 #define TARGET_ASM_OPEN_PAREN ""
9250 #undef TARGET_ASM_CLOSE_PAREN
9251 #define TARGET_ASM_CLOSE_PAREN ""
9253 #undef TARGET_DEFAULT_TARGET_FLAGS
9254 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
9255 #undef TARGET_HANDLE_OPTION
9256 #define TARGET_HANDLE_OPTION s390_handle_option
9258 #undef TARGET_ENCODE_SECTION_INFO
9259 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
9262 #undef TARGET_HAVE_TLS
9263 #define TARGET_HAVE_TLS true
9265 #undef TARGET_CANNOT_FORCE_CONST_MEM
9266 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
9268 #undef TARGET_DELEGITIMIZE_ADDRESS
9269 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
9271 #undef TARGET_RETURN_IN_MEMORY
9272 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
9274 #undef TARGET_INIT_BUILTINS
9275 #define TARGET_INIT_BUILTINS s390_init_builtins
9276 #undef TARGET_EXPAND_BUILTIN
9277 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
9279 #undef TARGET_ASM_OUTPUT_MI_THUNK
9280 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
9281 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
9282 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
9284 #undef TARGET_SCHED_ADJUST_PRIORITY
9285 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
9286 #undef TARGET_SCHED_ISSUE_RATE
9287 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
9288 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
9289 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
9291 #undef TARGET_CANNOT_COPY_INSN_P
9292 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
9293 #undef TARGET_RTX_COSTS
9294 #define TARGET_RTX_COSTS s390_rtx_costs
9295 #undef TARGET_ADDRESS_COST
9296 #define TARGET_ADDRESS_COST s390_address_cost
9298 #undef TARGET_MACHINE_DEPENDENT_REORG
9299 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
9301 #undef TARGET_VALID_POINTER_MODE
9302 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
9304 #undef TARGET_BUILD_BUILTIN_VA_LIST
9305 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
9306 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
9307 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
9309 #undef TARGET_PROMOTE_FUNCTION_ARGS
9310 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
9311 #undef TARGET_PROMOTE_FUNCTION_RETURN
9312 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
9313 #undef TARGET_PASS_BY_REFERENCE
9314 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
9316 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
9317 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
9319 #undef TARGET_FIXED_CONDITION_CODE_REGS
9320 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
9322 #undef TARGET_CC_MODES_COMPATIBLE
9323 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
9325 #undef TARGET_INVALID_WITHIN_DOLOOP
9326 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_rtx_null
9329 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
9330 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
9333 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
9334 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
9335 #define TARGET_MANGLE_FUNDAMENTAL_TYPE s390_mangle_fundamental_type
9338 #undef TARGET_SCALAR_MODE_SUPPORTED_P
9339 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
9341 #undef TARGET_SECONDARY_RELOAD
9342 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
9344 struct gcc_target targetm
= TARGET_INITIALIZER
;
9346 #include "gt-s390.h"