1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999-2016 Free Software Foundation, Inc.
3 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 Ulrich Weigand (uweigand@de.ibm.com) and
5 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 3, or (at your option) any later
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
28 #include "target-globals.h"
36 #include "stringpool.h"
43 #include "diagnostic-core.h"
44 #include "diagnostic.h"
46 #include "fold-const.h"
47 #include "print-tree.h"
48 #include "stor-layout.h"
51 #include "conditions.h"
53 #include "insn-attr.h"
65 #include "cfgcleanup.h"
67 #include "langhooks.h"
68 #include "internal-fn.h"
69 #include "gimple-fold.h"
74 #include "tree-pass.h"
79 #include "tm-constrs.h"
81 /* This file should be included last. */
82 #include "target-def.h"
84 /* Remember the last target of s390_set_current_function. */
85 static GTY(()) tree s390_previous_fndecl
;
87 /* Define the specific costs for a given cpu. */
89 struct processor_costs
92 const int m
; /* cost of an M instruction. */
93 const int mghi
; /* cost of an MGHI instruction. */
94 const int mh
; /* cost of an MH instruction. */
95 const int mhi
; /* cost of an MHI instruction. */
96 const int ml
; /* cost of an ML instruction. */
97 const int mr
; /* cost of an MR instruction. */
98 const int ms
; /* cost of an MS instruction. */
99 const int msg
; /* cost of an MSG instruction. */
100 const int msgf
; /* cost of an MSGF instruction. */
101 const int msgfr
; /* cost of an MSGFR instruction. */
102 const int msgr
; /* cost of an MSGR instruction. */
103 const int msr
; /* cost of an MSR instruction. */
104 const int mult_df
; /* cost of multiplication in DFmode. */
107 const int sqxbr
; /* cost of square root in TFmode. */
108 const int sqdbr
; /* cost of square root in DFmode. */
109 const int sqebr
; /* cost of square root in SFmode. */
110 /* multiply and add */
111 const int madbr
; /* cost of multiply and add in DFmode. */
112 const int maebr
; /* cost of multiply and add in SFmode. */
124 #define s390_cost ((const struct processor_costs *)(s390_cost_pointer))
127 struct processor_costs z900_cost
=
129 COSTS_N_INSNS (5), /* M */
130 COSTS_N_INSNS (10), /* MGHI */
131 COSTS_N_INSNS (5), /* MH */
132 COSTS_N_INSNS (4), /* MHI */
133 COSTS_N_INSNS (5), /* ML */
134 COSTS_N_INSNS (5), /* MR */
135 COSTS_N_INSNS (4), /* MS */
136 COSTS_N_INSNS (15), /* MSG */
137 COSTS_N_INSNS (7), /* MSGF */
138 COSTS_N_INSNS (7), /* MSGFR */
139 COSTS_N_INSNS (10), /* MSGR */
140 COSTS_N_INSNS (4), /* MSR */
141 COSTS_N_INSNS (7), /* multiplication in DFmode */
142 COSTS_N_INSNS (13), /* MXBR */
143 COSTS_N_INSNS (136), /* SQXBR */
144 COSTS_N_INSNS (44), /* SQDBR */
145 COSTS_N_INSNS (35), /* SQEBR */
146 COSTS_N_INSNS (18), /* MADBR */
147 COSTS_N_INSNS (13), /* MAEBR */
148 COSTS_N_INSNS (134), /* DXBR */
149 COSTS_N_INSNS (30), /* DDBR */
150 COSTS_N_INSNS (27), /* DEBR */
151 COSTS_N_INSNS (220), /* DLGR */
152 COSTS_N_INSNS (34), /* DLR */
153 COSTS_N_INSNS (34), /* DR */
154 COSTS_N_INSNS (32), /* DSGFR */
155 COSTS_N_INSNS (32), /* DSGR */
159 struct processor_costs z990_cost
=
161 COSTS_N_INSNS (4), /* M */
162 COSTS_N_INSNS (2), /* MGHI */
163 COSTS_N_INSNS (2), /* MH */
164 COSTS_N_INSNS (2), /* MHI */
165 COSTS_N_INSNS (4), /* ML */
166 COSTS_N_INSNS (4), /* MR */
167 COSTS_N_INSNS (5), /* MS */
168 COSTS_N_INSNS (6), /* MSG */
169 COSTS_N_INSNS (4), /* MSGF */
170 COSTS_N_INSNS (4), /* MSGFR */
171 COSTS_N_INSNS (4), /* MSGR */
172 COSTS_N_INSNS (4), /* MSR */
173 COSTS_N_INSNS (1), /* multiplication in DFmode */
174 COSTS_N_INSNS (28), /* MXBR */
175 COSTS_N_INSNS (130), /* SQXBR */
176 COSTS_N_INSNS (66), /* SQDBR */
177 COSTS_N_INSNS (38), /* SQEBR */
178 COSTS_N_INSNS (1), /* MADBR */
179 COSTS_N_INSNS (1), /* MAEBR */
180 COSTS_N_INSNS (60), /* DXBR */
181 COSTS_N_INSNS (40), /* DDBR */
182 COSTS_N_INSNS (26), /* DEBR */
183 COSTS_N_INSNS (176), /* DLGR */
184 COSTS_N_INSNS (31), /* DLR */
185 COSTS_N_INSNS (31), /* DR */
186 COSTS_N_INSNS (31), /* DSGFR */
187 COSTS_N_INSNS (31), /* DSGR */
191 struct processor_costs z9_109_cost
=
193 COSTS_N_INSNS (4), /* M */
194 COSTS_N_INSNS (2), /* MGHI */
195 COSTS_N_INSNS (2), /* MH */
196 COSTS_N_INSNS (2), /* MHI */
197 COSTS_N_INSNS (4), /* ML */
198 COSTS_N_INSNS (4), /* MR */
199 COSTS_N_INSNS (5), /* MS */
200 COSTS_N_INSNS (6), /* MSG */
201 COSTS_N_INSNS (4), /* MSGF */
202 COSTS_N_INSNS (4), /* MSGFR */
203 COSTS_N_INSNS (4), /* MSGR */
204 COSTS_N_INSNS (4), /* MSR */
205 COSTS_N_INSNS (1), /* multiplication in DFmode */
206 COSTS_N_INSNS (28), /* MXBR */
207 COSTS_N_INSNS (130), /* SQXBR */
208 COSTS_N_INSNS (66), /* SQDBR */
209 COSTS_N_INSNS (38), /* SQEBR */
210 COSTS_N_INSNS (1), /* MADBR */
211 COSTS_N_INSNS (1), /* MAEBR */
212 COSTS_N_INSNS (60), /* DXBR */
213 COSTS_N_INSNS (40), /* DDBR */
214 COSTS_N_INSNS (26), /* DEBR */
215 COSTS_N_INSNS (30), /* DLGR */
216 COSTS_N_INSNS (23), /* DLR */
217 COSTS_N_INSNS (23), /* DR */
218 COSTS_N_INSNS (24), /* DSGFR */
219 COSTS_N_INSNS (24), /* DSGR */
223 struct processor_costs z10_cost
=
225 COSTS_N_INSNS (10), /* M */
226 COSTS_N_INSNS (10), /* MGHI */
227 COSTS_N_INSNS (10), /* MH */
228 COSTS_N_INSNS (10), /* MHI */
229 COSTS_N_INSNS (10), /* ML */
230 COSTS_N_INSNS (10), /* MR */
231 COSTS_N_INSNS (10), /* MS */
232 COSTS_N_INSNS (10), /* MSG */
233 COSTS_N_INSNS (10), /* MSGF */
234 COSTS_N_INSNS (10), /* MSGFR */
235 COSTS_N_INSNS (10), /* MSGR */
236 COSTS_N_INSNS (10), /* MSR */
237 COSTS_N_INSNS (1) , /* multiplication in DFmode */
238 COSTS_N_INSNS (50), /* MXBR */
239 COSTS_N_INSNS (120), /* SQXBR */
240 COSTS_N_INSNS (52), /* SQDBR */
241 COSTS_N_INSNS (38), /* SQEBR */
242 COSTS_N_INSNS (1), /* MADBR */
243 COSTS_N_INSNS (1), /* MAEBR */
244 COSTS_N_INSNS (111), /* DXBR */
245 COSTS_N_INSNS (39), /* DDBR */
246 COSTS_N_INSNS (32), /* DEBR */
247 COSTS_N_INSNS (160), /* DLGR */
248 COSTS_N_INSNS (71), /* DLR */
249 COSTS_N_INSNS (71), /* DR */
250 COSTS_N_INSNS (71), /* DSGFR */
251 COSTS_N_INSNS (71), /* DSGR */
255 struct processor_costs z196_cost
=
257 COSTS_N_INSNS (7), /* M */
258 COSTS_N_INSNS (5), /* MGHI */
259 COSTS_N_INSNS (5), /* MH */
260 COSTS_N_INSNS (5), /* MHI */
261 COSTS_N_INSNS (7), /* ML */
262 COSTS_N_INSNS (7), /* MR */
263 COSTS_N_INSNS (6), /* MS */
264 COSTS_N_INSNS (8), /* MSG */
265 COSTS_N_INSNS (6), /* MSGF */
266 COSTS_N_INSNS (6), /* MSGFR */
267 COSTS_N_INSNS (8), /* MSGR */
268 COSTS_N_INSNS (6), /* MSR */
269 COSTS_N_INSNS (1) , /* multiplication in DFmode */
270 COSTS_N_INSNS (40), /* MXBR B+40 */
271 COSTS_N_INSNS (100), /* SQXBR B+100 */
272 COSTS_N_INSNS (42), /* SQDBR B+42 */
273 COSTS_N_INSNS (28), /* SQEBR B+28 */
274 COSTS_N_INSNS (1), /* MADBR B */
275 COSTS_N_INSNS (1), /* MAEBR B */
276 COSTS_N_INSNS (101), /* DXBR B+101 */
277 COSTS_N_INSNS (29), /* DDBR */
278 COSTS_N_INSNS (22), /* DEBR */
279 COSTS_N_INSNS (160), /* DLGR cracked */
280 COSTS_N_INSNS (160), /* DLR cracked */
281 COSTS_N_INSNS (160), /* DR expanded */
282 COSTS_N_INSNS (160), /* DSGFR cracked */
283 COSTS_N_INSNS (160), /* DSGR cracked */
287 struct processor_costs zEC12_cost
=
289 COSTS_N_INSNS (7), /* M */
290 COSTS_N_INSNS (5), /* MGHI */
291 COSTS_N_INSNS (5), /* MH */
292 COSTS_N_INSNS (5), /* MHI */
293 COSTS_N_INSNS (7), /* ML */
294 COSTS_N_INSNS (7), /* MR */
295 COSTS_N_INSNS (6), /* MS */
296 COSTS_N_INSNS (8), /* MSG */
297 COSTS_N_INSNS (6), /* MSGF */
298 COSTS_N_INSNS (6), /* MSGFR */
299 COSTS_N_INSNS (8), /* MSGR */
300 COSTS_N_INSNS (6), /* MSR */
301 COSTS_N_INSNS (1) , /* multiplication in DFmode */
302 COSTS_N_INSNS (40), /* MXBR B+40 */
303 COSTS_N_INSNS (100), /* SQXBR B+100 */
304 COSTS_N_INSNS (42), /* SQDBR B+42 */
305 COSTS_N_INSNS (28), /* SQEBR B+28 */
306 COSTS_N_INSNS (1), /* MADBR B */
307 COSTS_N_INSNS (1), /* MAEBR B */
308 COSTS_N_INSNS (131), /* DXBR B+131 */
309 COSTS_N_INSNS (29), /* DDBR */
310 COSTS_N_INSNS (22), /* DEBR */
311 COSTS_N_INSNS (160), /* DLGR cracked */
312 COSTS_N_INSNS (160), /* DLR cracked */
313 COSTS_N_INSNS (160), /* DR expanded */
314 COSTS_N_INSNS (160), /* DSGFR cracked */
315 COSTS_N_INSNS (160), /* DSGR cracked */
320 const char *const name
;
321 const enum processor_type processor
;
322 const struct processor_costs
*cost
;
324 const processor_table
[] =
326 { "g5", PROCESSOR_9672_G5
, &z900_cost
},
327 { "g6", PROCESSOR_9672_G6
, &z900_cost
},
328 { "z900", PROCESSOR_2064_Z900
, &z900_cost
},
329 { "z990", PROCESSOR_2084_Z990
, &z990_cost
},
330 { "z9-109", PROCESSOR_2094_Z9_109
, &z9_109_cost
},
331 { "z9-ec", PROCESSOR_2094_Z9_EC
, &z9_109_cost
},
332 { "z10", PROCESSOR_2097_Z10
, &z10_cost
},
333 { "z196", PROCESSOR_2817_Z196
, &z196_cost
},
334 { "zEC12", PROCESSOR_2827_ZEC12
, &zEC12_cost
},
335 { "z13", PROCESSOR_2964_Z13
, &zEC12_cost
},
336 { "native", PROCESSOR_NATIVE
, NULL
}
339 extern int reload_completed
;
341 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
342 static rtx_insn
*last_scheduled_insn
;
344 /* Structure used to hold the components of a S/390 memory
345 address. A legitimate address on S/390 is of the general
347 base + index + displacement
348 where any of the components is optional.
350 base and index are registers of the class ADDR_REGS,
351 displacement is an unsigned 12-bit immediate constant. */
362 /* The following structure is embedded in the machine
363 specific part of struct function. */
365 struct GTY (()) s390_frame_layout
367 /* Offset within stack frame. */
368 HOST_WIDE_INT gprs_offset
;
369 HOST_WIDE_INT f0_offset
;
370 HOST_WIDE_INT f4_offset
;
371 HOST_WIDE_INT f8_offset
;
372 HOST_WIDE_INT backchain_offset
;
374 /* Number of first and last gpr where slots in the register
375 save area are reserved for. */
376 int first_save_gpr_slot
;
377 int last_save_gpr_slot
;
379 /* Location (FP register number) where GPRs (r0-r15) should
381 0 - does not need to be saved at all
383 #define SAVE_SLOT_NONE 0
384 #define SAVE_SLOT_STACK -1
385 signed char gpr_save_slots
[16];
387 /* Number of first and last gpr to be saved, restored. */
389 int first_restore_gpr
;
391 int last_restore_gpr
;
393 /* Bits standing for floating point registers. Set, if the
394 respective register has to be saved. Starting with reg 16 (f0)
395 at the rightmost bit.
396 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
397 fpr 15 13 11 9 14 12 10 8 7 5 3 1 6 4 2 0
398 reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 */
399 unsigned int fpr_bitmap
;
401 /* Number of floating point registers f8-f15 which must be saved. */
404 /* Set if return address needs to be saved.
405 This flag is set by s390_return_addr_rtx if it could not use
406 the initial value of r14 and therefore depends on r14 saved
408 bool save_return_addr_p
;
410 /* Size of stack frame. */
411 HOST_WIDE_INT frame_size
;
414 /* Define the structure for the machine field in struct function. */
416 struct GTY(()) machine_function
418 struct s390_frame_layout frame_layout
;
420 /* Literal pool base register. */
423 /* True if we may need to perform branch splitting. */
424 bool split_branches_pending_p
;
426 bool has_landing_pad_p
;
428 /* True if the current function may contain a tbegin clobbering
432 /* For -fsplit-stack support: A stack local which holds a pointer to
433 the stack arguments for a function with a variable number of
434 arguments. This is set at the start of the function and is used
435 to initialize the overflow_arg_area field of the va_list
437 rtx split_stack_varargs_pointer
;
440 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
442 #define cfun_frame_layout (cfun->machine->frame_layout)
443 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
444 #define cfun_save_arg_fprs_p (!!(TARGET_64BIT \
445 ? cfun_frame_layout.fpr_bitmap & 0x0f \
446 : cfun_frame_layout.fpr_bitmap & 0x03))
447 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
448 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
449 #define cfun_set_fpr_save(REGNO) (cfun->machine->frame_layout.fpr_bitmap |= \
450 (1 << (REGNO - FPR0_REGNUM)))
451 #define cfun_fpr_save_p(REGNO) (!!(cfun->machine->frame_layout.fpr_bitmap & \
452 (1 << (REGNO - FPR0_REGNUM))))
453 #define cfun_gpr_save_slot(REGNO) \
454 cfun->machine->frame_layout.gpr_save_slots[REGNO]
456 /* Number of GPRs and FPRs used for argument passing. */
457 #define GP_ARG_NUM_REG 5
458 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
459 #define VEC_ARG_NUM_REG 8
461 /* A couple of shortcuts. */
462 #define CONST_OK_FOR_J(x) \
463 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
464 #define CONST_OK_FOR_K(x) \
465 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
466 #define CONST_OK_FOR_Os(x) \
467 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
468 #define CONST_OK_FOR_Op(x) \
469 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
470 #define CONST_OK_FOR_On(x) \
471 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
473 #define REGNO_PAIR_OK(REGNO, MODE) \
474 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
476 /* That's the read ahead of the dynamic branch prediction unit in
477 bytes on a z10 (or higher) CPU. */
478 #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
481 /* Indicate which ABI has been used for passing vector args.
482 0 - no vector type arguments have been passed where the ABI is relevant
483 1 - the old ABI has been used
484 2 - a vector type argument has been passed either in a vector register
485 or on the stack by value */
486 static int s390_vector_abi
= 0;
488 /* Set the vector ABI marker if TYPE is subject to the vector ABI
489 switch. The vector ABI affects only vector data types. There are
490 two aspects of the vector ABI relevant here:
492 1. vectors >= 16 bytes have an alignment of 8 bytes with the new
493 ABI and natural alignment with the old.
495 2. vector <= 16 bytes are passed in VRs or by value on the stack
496 with the new ABI but by reference on the stack with the old.
498 If ARG_P is true TYPE is used for a function argument or return
499 value. The ABI marker then is set for all vector data types. If
500 ARG_P is false only type 1 vectors are being checked. */
503 s390_check_type_for_vector_abi (const_tree type
, bool arg_p
, bool in_struct_p
)
505 static hash_set
<const_tree
> visited_types_hash
;
510 if (type
== NULL_TREE
|| TREE_CODE (type
) == ERROR_MARK
)
513 if (visited_types_hash
.contains (type
))
516 visited_types_hash
.add (type
);
518 if (VECTOR_TYPE_P (type
))
520 int type_size
= int_size_in_bytes (type
);
522 /* Outside arguments only the alignment is changing and this
523 only happens for vector types >= 16 bytes. */
524 if (!arg_p
&& type_size
< 16)
527 /* In arguments vector types > 16 are passed as before (GCC
528 never enforced the bigger alignment for arguments which was
529 required by the old vector ABI). However, it might still be
530 ABI relevant due to the changed alignment if it is a struct
532 if (arg_p
&& type_size
> 16 && !in_struct_p
)
535 s390_vector_abi
= TARGET_VX_ABI
? 2 : 1;
537 else if (POINTER_TYPE_P (type
) || TREE_CODE (type
) == ARRAY_TYPE
)
539 /* ARRAY_TYPE: Since with neither of the ABIs we have more than
540 natural alignment there will never be ABI dependent padding
541 in an array type. That's why we do not set in_struct_p to
543 s390_check_type_for_vector_abi (TREE_TYPE (type
), arg_p
, in_struct_p
);
545 else if (TREE_CODE (type
) == FUNCTION_TYPE
|| TREE_CODE (type
) == METHOD_TYPE
)
549 /* Check the return type. */
550 s390_check_type_for_vector_abi (TREE_TYPE (type
), true, false);
552 for (arg_chain
= TYPE_ARG_TYPES (type
);
554 arg_chain
= TREE_CHAIN (arg_chain
))
555 s390_check_type_for_vector_abi (TREE_VALUE (arg_chain
), true, false);
557 else if (RECORD_OR_UNION_TYPE_P (type
))
561 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
563 if (TREE_CODE (field
) != FIELD_DECL
)
566 s390_check_type_for_vector_abi (TREE_TYPE (field
), arg_p
, true);
572 /* System z builtins. */
574 #include "s390-builtins.h"
576 const unsigned int bflags_builtin
[S390_BUILTIN_MAX
+ 1] =
581 #define B_DEF(NAME, PATTERN, ATTRS, BFLAGS, ...) BFLAGS,
583 #define OB_DEF_VAR(...)
584 #include "s390-builtins.def"
588 const unsigned int opflags_builtin
[S390_BUILTIN_MAX
+ 1] =
593 #define B_DEF(NAME, PATTERN, ATTRS, BFLAGS, OPFLAGS, ...) OPFLAGS,
595 #define OB_DEF_VAR(...)
596 #include "s390-builtins.def"
600 const unsigned int bflags_overloaded_builtin
[S390_OVERLOADED_BUILTIN_MAX
+ 1] =
606 #define OB_DEF(NAME, FIRST_VAR_NAME, LAST_VAR_NAME, BFLAGS, ...) BFLAGS,
607 #define OB_DEF_VAR(...)
608 #include "s390-builtins.def"
613 opflags_overloaded_builtin_var
[S390_OVERLOADED_BUILTIN_VAR_MAX
+ 1] =
620 #define OB_DEF_VAR(NAME, PATTERN, FLAGS, FNTYPE) FLAGS,
621 #include "s390-builtins.def"
625 tree s390_builtin_types
[BT_MAX
];
626 tree s390_builtin_fn_types
[BT_FN_MAX
];
627 tree s390_builtin_decls
[S390_BUILTIN_MAX
+
628 S390_OVERLOADED_BUILTIN_MAX
+
629 S390_OVERLOADED_BUILTIN_VAR_MAX
];
631 static enum insn_code
const code_for_builtin
[S390_BUILTIN_MAX
+ 1] = {
635 #define B_DEF(NAME, PATTERN, ...) CODE_FOR_##PATTERN,
637 #define OB_DEF_VAR(...)
639 #include "s390-builtins.def"
644 s390_init_builtins (void)
646 /* These definitions are being used in s390-builtins.def. */
647 tree returns_twice_attr
= tree_cons (get_identifier ("returns_twice"),
649 tree noreturn_attr
= tree_cons (get_identifier ("noreturn"), NULL
, NULL
);
650 tree c_uint64_type_node
;
652 /* The uint64_type_node from tree.c is not compatible to the C99
653 uint64_t data type. What we want is c_uint64_type_node from
654 c-common.c. But since backend code is not supposed to interface
655 with the frontend we recreate it here. */
657 c_uint64_type_node
= long_unsigned_type_node
;
659 c_uint64_type_node
= long_long_unsigned_type_node
;
662 #define DEF_TYPE(INDEX, BFLAGS, NODE, CONST_P) \
663 if (s390_builtin_types[INDEX] == NULL) \
664 s390_builtin_types[INDEX] = (!CONST_P) ? \
665 (NODE) : build_type_variant ((NODE), 1, 0);
667 #undef DEF_POINTER_TYPE
668 #define DEF_POINTER_TYPE(INDEX, BFLAGS, INDEX_BASE) \
669 if (s390_builtin_types[INDEX] == NULL) \
670 s390_builtin_types[INDEX] = \
671 build_pointer_type (s390_builtin_types[INDEX_BASE]);
673 #undef DEF_DISTINCT_TYPE
674 #define DEF_DISTINCT_TYPE(INDEX, BFLAGS, INDEX_BASE) \
675 if (s390_builtin_types[INDEX] == NULL) \
676 s390_builtin_types[INDEX] = \
677 build_distinct_type_copy (s390_builtin_types[INDEX_BASE]);
679 #undef DEF_VECTOR_TYPE
680 #define DEF_VECTOR_TYPE(INDEX, BFLAGS, INDEX_BASE, ELEMENTS) \
681 if (s390_builtin_types[INDEX] == NULL) \
682 s390_builtin_types[INDEX] = \
683 build_vector_type (s390_builtin_types[INDEX_BASE], ELEMENTS);
685 #undef DEF_OPAQUE_VECTOR_TYPE
686 #define DEF_OPAQUE_VECTOR_TYPE(INDEX, BFLAGS, INDEX_BASE, ELEMENTS) \
687 if (s390_builtin_types[INDEX] == NULL) \
688 s390_builtin_types[INDEX] = \
689 build_opaque_vector_type (s390_builtin_types[INDEX_BASE], ELEMENTS);
692 #define DEF_FN_TYPE(INDEX, BFLAGS, args...) \
693 if (s390_builtin_fn_types[INDEX] == NULL) \
694 s390_builtin_fn_types[INDEX] = \
695 build_function_type_list (args, NULL_TREE);
697 #define DEF_OV_TYPE(...)
698 #include "s390-builtin-types.def"
701 #define B_DEF(NAME, PATTERN, ATTRS, BFLAGS, OPFLAGS, FNTYPE) \
702 if (s390_builtin_decls[S390_BUILTIN_##NAME] == NULL) \
703 s390_builtin_decls[S390_BUILTIN_##NAME] = \
704 add_builtin_function ("__builtin_" #NAME, \
705 s390_builtin_fn_types[FNTYPE], \
706 S390_BUILTIN_##NAME, \
711 #define OB_DEF(NAME, FIRST_VAR_NAME, LAST_VAR_NAME, BFLAGS, FNTYPE) \
712 if (s390_builtin_decls[S390_OVERLOADED_BUILTIN_##NAME + S390_BUILTIN_MAX] \
714 s390_builtin_decls[S390_OVERLOADED_BUILTIN_##NAME + S390_BUILTIN_MAX] = \
715 add_builtin_function ("__builtin_" #NAME, \
716 s390_builtin_fn_types[FNTYPE], \
717 S390_OVERLOADED_BUILTIN_##NAME + S390_BUILTIN_MAX, \
722 #define OB_DEF_VAR(...)
723 #include "s390-builtins.def"
727 /* Return true if ARG is appropriate as argument number ARGNUM of
728 builtin DECL. The operand flags from s390-builtins.def have to
729 passed as OP_FLAGS. */
731 s390_const_operand_ok (tree arg
, int argnum
, int op_flags
, tree decl
)
733 if (O_UIMM_P (op_flags
))
735 int bitwidths
[] = { 1, 2, 3, 4, 5, 8, 12, 16, 32 };
736 int bitwidth
= bitwidths
[op_flags
- O_U1
];
738 if (!tree_fits_uhwi_p (arg
)
739 || tree_to_uhwi (arg
) > ((unsigned HOST_WIDE_INT
)1 << bitwidth
) - 1)
741 error("constant argument %d for builtin %qF is out of range (0.."
742 HOST_WIDE_INT_PRINT_UNSIGNED
")",
744 ((unsigned HOST_WIDE_INT
)1 << bitwidth
) - 1);
749 if (O_SIMM_P (op_flags
))
751 int bitwidths
[] = { 2, 3, 4, 5, 8, 12, 16, 32 };
752 int bitwidth
= bitwidths
[op_flags
- O_S2
];
754 if (!tree_fits_shwi_p (arg
)
755 || tree_to_shwi (arg
) < -((HOST_WIDE_INT
)1 << (bitwidth
- 1))
756 || tree_to_shwi (arg
) > (((HOST_WIDE_INT
)1 << (bitwidth
- 1)) - 1))
758 error("constant argument %d for builtin %qF is out of range ("
759 HOST_WIDE_INT_PRINT_DEC
".."
760 HOST_WIDE_INT_PRINT_DEC
")",
762 -((HOST_WIDE_INT
)1 << (bitwidth
- 1)),
763 ((HOST_WIDE_INT
)1 << (bitwidth
- 1)) - 1);
770 /* Expand an expression EXP that calls a built-in function,
771 with result going to TARGET if that's convenient
772 (and in mode MODE if that's convenient).
773 SUBTARGET may be used as the target for computing one of EXP's operands.
774 IGNORE is nonzero if the value is to be ignored. */
777 s390_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
778 machine_mode mode ATTRIBUTE_UNUSED
,
779 int ignore ATTRIBUTE_UNUSED
)
783 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
784 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
785 enum insn_code icode
;
786 rtx op
[MAX_ARGS
], pat
;
790 call_expr_arg_iterator iter
;
791 unsigned int all_op_flags
= opflags_for_builtin (fcode
);
792 machine_mode last_vec_mode
= VOIDmode
;
794 if (TARGET_DEBUG_ARG
)
797 "s390_expand_builtin, code = %4d, %s, bflags = 0x%x\n",
798 (int)fcode
, IDENTIFIER_POINTER (DECL_NAME (fndecl
)),
799 bflags_for_builtin (fcode
));
802 if (S390_USE_TARGET_ATTRIBUTE
)
806 bflags
= bflags_for_builtin (fcode
);
807 if ((bflags
& B_HTM
) && !TARGET_HTM
)
809 error ("Builtin %qF is not supported without -mhtm "
810 "(default with -march=zEC12 and higher).", fndecl
);
813 if ((bflags
& B_VX
) && !TARGET_VX
)
815 error ("Builtin %qF is not supported without -mvx "
816 "(default with -march=z13 and higher).", fndecl
);
820 if (fcode
>= S390_OVERLOADED_BUILTIN_VAR_OFFSET
821 && fcode
< S390_ALL_BUILTIN_MAX
)
825 else if (fcode
< S390_OVERLOADED_BUILTIN_OFFSET
)
827 icode
= code_for_builtin
[fcode
];
828 /* Set a flag in the machine specific cfun part in order to support
829 saving/restoring of FPRs. */
830 if (fcode
== S390_BUILTIN_tbegin
|| fcode
== S390_BUILTIN_tbegin_retry
)
831 cfun
->machine
->tbegin_p
= true;
833 else if (fcode
< S390_OVERLOADED_BUILTIN_VAR_OFFSET
)
835 error ("Unresolved overloaded builtin");
839 internal_error ("bad builtin fcode");
842 internal_error ("bad builtin icode");
844 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
848 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
850 || GET_MODE (target
) != tmode
851 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
852 target
= gen_reg_rtx (tmode
);
854 /* There are builtins (e.g. vec_promote) with no vector
855 arguments but an element selector. So we have to also look
856 at the vector return type when emitting the modulo
858 if (VECTOR_MODE_P (insn_data
[icode
].operand
[0].mode
))
859 last_vec_mode
= insn_data
[icode
].operand
[0].mode
;
863 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
865 const struct insn_operand_data
*insn_op
;
866 unsigned int op_flags
= all_op_flags
& ((1 << O_SHIFT
) - 1);
868 all_op_flags
= all_op_flags
>> O_SHIFT
;
870 if (arg
== error_mark_node
)
872 if (arity
>= MAX_ARGS
)
875 if (O_IMM_P (op_flags
)
876 && TREE_CODE (arg
) != INTEGER_CST
)
878 error ("constant value required for builtin %qF argument %d",
883 if (!s390_const_operand_ok (arg
, arity
+ 1, op_flags
, fndecl
))
886 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
887 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, EXPAND_NORMAL
);
889 /* expand_expr truncates constants to the target mode only if it
890 is "convenient". However, our checks below rely on this
892 if (CONST_INT_P (op
[arity
])
893 && SCALAR_INT_MODE_P (insn_op
->mode
)
894 && GET_MODE (op
[arity
]) != insn_op
->mode
)
895 op
[arity
] = GEN_INT (trunc_int_for_mode (INTVAL (op
[arity
]),
898 /* Wrap the expanded RTX for pointer types into a MEM expr with
899 the proper mode. This allows us to use e.g. (match_operand
900 "memory_operand"..) in the insn patterns instead of (mem
901 (match_operand "address_operand)). This is helpful for
902 patterns not just accepting MEMs. */
903 if (POINTER_TYPE_P (TREE_TYPE (arg
))
904 && insn_op
->predicate
!= address_operand
)
905 op
[arity
] = gen_rtx_MEM (insn_op
->mode
, op
[arity
]);
907 /* Expand the module operation required on element selectors. */
908 if (op_flags
== O_ELEM
)
910 gcc_assert (last_vec_mode
!= VOIDmode
);
911 op
[arity
] = simplify_expand_binop (SImode
, code_to_optab (AND
),
913 GEN_INT (GET_MODE_NUNITS (last_vec_mode
) - 1),
914 NULL_RTX
, 1, OPTAB_DIRECT
);
917 /* Record the vector mode used for an element selector. This assumes:
918 1. There is no builtin with two different vector modes and an element selector
919 2. The element selector comes after the vector type it is referring to.
920 This currently the true for all the builtins but FIXME we
921 should better check for that. */
922 if (VECTOR_MODE_P (insn_op
->mode
))
923 last_vec_mode
= insn_op
->mode
;
925 if (insn_op
->predicate (op
[arity
], insn_op
->mode
))
931 if (MEM_P (op
[arity
])
932 && insn_op
->predicate
== memory_operand
933 && (GET_MODE (XEXP (op
[arity
], 0)) == Pmode
934 || GET_MODE (XEXP (op
[arity
], 0)) == VOIDmode
))
936 op
[arity
] = replace_equiv_address (op
[arity
],
937 copy_to_mode_reg (Pmode
,
938 XEXP (op
[arity
], 0)));
940 else if (GET_MODE (op
[arity
]) == insn_op
->mode
941 || GET_MODE (op
[arity
]) == VOIDmode
942 || (insn_op
->predicate
== address_operand
943 && GET_MODE (op
[arity
]) == Pmode
))
945 /* An address_operand usually has VOIDmode in the expander
946 so we cannot use this. */
947 machine_mode target_mode
=
948 (insn_op
->predicate
== address_operand
949 ? Pmode
: insn_op
->mode
);
950 op
[arity
] = copy_to_mode_reg (target_mode
, op
[arity
]);
953 if (!insn_op
->predicate (op
[arity
], insn_op
->mode
))
955 error ("Invalid argument %d for builtin %qF", arity
+ 1, fndecl
);
964 pat
= GEN_FCN (icode
) (target
);
968 pat
= GEN_FCN (icode
) (target
, op
[0]);
970 pat
= GEN_FCN (icode
) (op
[0]);
974 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
976 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
980 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1], op
[2]);
982 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
986 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1], op
[2], op
[3]);
988 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
992 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1], op
[2], op
[3], op
[4]);
994 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3], op
[4]);
998 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1], op
[2], op
[3], op
[4], op
[5]);
1000 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3], op
[4], op
[5]);
1016 static const int s390_hotpatch_hw_max
= 1000000;
1017 static int s390_hotpatch_hw_before_label
= 0;
1018 static int s390_hotpatch_hw_after_label
= 0;
1020 /* Check whether the hotpatch attribute is applied to a function and, if it has
1021 an argument, the argument is valid. */
1024 s390_handle_hotpatch_attribute (tree
*node
, tree name
, tree args
,
1025 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
1031 if (TREE_CODE (*node
) != FUNCTION_DECL
)
1033 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
1035 *no_add_attrs
= true;
1037 if (args
!= NULL
&& TREE_CHAIN (args
) != NULL
)
1039 expr
= TREE_VALUE (args
);
1040 expr2
= TREE_VALUE (TREE_CHAIN (args
));
1042 if (args
== NULL
|| TREE_CHAIN (args
) == NULL
)
1044 else if (TREE_CODE (expr
) != INTEGER_CST
1045 || !INTEGRAL_TYPE_P (TREE_TYPE (expr
))
1046 || wi::gtu_p (expr
, s390_hotpatch_hw_max
))
1048 else if (TREE_CODE (expr2
) != INTEGER_CST
1049 || !INTEGRAL_TYPE_P (TREE_TYPE (expr2
))
1050 || wi::gtu_p (expr2
, s390_hotpatch_hw_max
))
1056 error ("requested %qE attribute is not a comma separated pair of"
1057 " non-negative integer constants or too large (max. %d)", name
,
1058 s390_hotpatch_hw_max
);
1059 *no_add_attrs
= true;
1065 /* Expand the s390_vector_bool type attribute. */
1068 s390_handle_vectorbool_attribute (tree
*node
, tree name ATTRIBUTE_UNUSED
,
1069 tree args ATTRIBUTE_UNUSED
,
1070 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
1072 tree type
= *node
, result
= NULL_TREE
;
1075 while (POINTER_TYPE_P (type
)
1076 || TREE_CODE (type
) == FUNCTION_TYPE
1077 || TREE_CODE (type
) == METHOD_TYPE
1078 || TREE_CODE (type
) == ARRAY_TYPE
)
1079 type
= TREE_TYPE (type
);
1081 mode
= TYPE_MODE (type
);
1084 case DImode
: case V2DImode
: result
= s390_builtin_types
[BT_BV2DI
]; break;
1085 case SImode
: case V4SImode
: result
= s390_builtin_types
[BT_BV4SI
]; break;
1086 case HImode
: case V8HImode
: result
= s390_builtin_types
[BT_BV8HI
]; break;
1087 case QImode
: case V16QImode
: result
= s390_builtin_types
[BT_BV16QI
];
1091 *no_add_attrs
= true; /* No need to hang on to the attribute. */
1094 *node
= lang_hooks
.types
.reconstruct_complex_type (*node
, result
);
1099 static const struct attribute_spec s390_attribute_table
[] = {
1100 { "hotpatch", 2, 2, true, false, false, s390_handle_hotpatch_attribute
, false },
1101 { "s390_vector_bool", 0, 0, false, true, false, s390_handle_vectorbool_attribute
, true },
1103 { NULL
, 0, 0, false, false, false, NULL
, false }
1106 /* Return the alignment for LABEL. We default to the -falign-labels
1107 value except for the literal pool base label. */
1109 s390_label_align (rtx label
)
1111 rtx_insn
*prev_insn
= prev_active_insn (label
);
1114 if (prev_insn
== NULL_RTX
)
1117 set
= single_set (prev_insn
);
1119 if (set
== NULL_RTX
)
1122 src
= SET_SRC (set
);
1124 /* Don't align literal pool base labels. */
1125 if (GET_CODE (src
) == UNSPEC
1126 && XINT (src
, 1) == UNSPEC_MAIN_BASE
)
1130 return align_labels_log
;
1134 s390_libgcc_cmp_return_mode (void)
1136 return TARGET_64BIT
? DImode
: SImode
;
1140 s390_libgcc_shift_count_mode (void)
1142 return TARGET_64BIT
? DImode
: SImode
;
1146 s390_unwind_word_mode (void)
1148 return TARGET_64BIT
? DImode
: SImode
;
1151 /* Return true if the back end supports mode MODE. */
1153 s390_scalar_mode_supported_p (machine_mode mode
)
1155 /* In contrast to the default implementation reject TImode constants on 31bit
1156 TARGET_ZARCH for ABI compliance. */
1157 if (!TARGET_64BIT
&& TARGET_ZARCH
&& mode
== TImode
)
1160 if (DECIMAL_FLOAT_MODE_P (mode
))
1161 return default_decimal_float_supported_p ();
1163 return default_scalar_mode_supported_p (mode
);
1166 /* Return true if the back end supports vector mode MODE. */
1168 s390_vector_mode_supported_p (machine_mode mode
)
1172 if (!VECTOR_MODE_P (mode
)
1174 || GET_MODE_SIZE (mode
) > 16)
1177 inner
= GET_MODE_INNER (mode
);
1195 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
1198 s390_set_has_landing_pad_p (bool value
)
1200 cfun
->machine
->has_landing_pad_p
= value
;
1203 /* If two condition code modes are compatible, return a condition code
1204 mode which is compatible with both. Otherwise, return
1208 s390_cc_modes_compatible (machine_mode m1
, machine_mode m2
)
1216 if (m2
== CCUmode
|| m2
== CCTmode
|| m2
== CCZ1mode
1217 || m2
== CCSmode
|| m2
== CCSRmode
|| m2
== CCURmode
)
1238 /* Return true if SET either doesn't set the CC register, or else
1239 the source and destination have matching CC modes and that
1240 CC mode is at least as constrained as REQ_MODE. */
1243 s390_match_ccmode_set (rtx set
, machine_mode req_mode
)
1245 machine_mode set_mode
;
1247 gcc_assert (GET_CODE (set
) == SET
);
1249 if (GET_CODE (SET_DEST (set
)) != REG
|| !CC_REGNO_P (REGNO (SET_DEST (set
))))
1252 set_mode
= GET_MODE (SET_DEST (set
));
1271 if (req_mode
!= set_mode
)
1276 if (req_mode
!= CCSmode
&& req_mode
!= CCUmode
&& req_mode
!= CCTmode
1277 && req_mode
!= CCSRmode
&& req_mode
!= CCURmode
)
1283 if (req_mode
!= CCAmode
)
1291 return (GET_MODE (SET_SRC (set
)) == set_mode
);
1294 /* Return true if every SET in INSN that sets the CC register
1295 has source and destination with matching CC modes and that
1296 CC mode is at least as constrained as REQ_MODE.
1297 If REQ_MODE is VOIDmode, always return false. */
1300 s390_match_ccmode (rtx_insn
*insn
, machine_mode req_mode
)
1304 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
1305 if (req_mode
== VOIDmode
)
1308 if (GET_CODE (PATTERN (insn
)) == SET
)
1309 return s390_match_ccmode_set (PATTERN (insn
), req_mode
);
1311 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
1312 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1314 rtx set
= XVECEXP (PATTERN (insn
), 0, i
);
1315 if (GET_CODE (set
) == SET
)
1316 if (!s390_match_ccmode_set (set
, req_mode
))
1323 /* If a test-under-mask instruction can be used to implement
1324 (compare (and ... OP1) OP2), return the CC mode required
1325 to do that. Otherwise, return VOIDmode.
1326 MIXED is true if the instruction can distinguish between
1327 CC1 and CC2 for mixed selected bits (TMxx), it is false
1328 if the instruction cannot (TM). */
1331 s390_tm_ccmode (rtx op1
, rtx op2
, bool mixed
)
1335 /* ??? Fixme: should work on CONST_WIDE_INT as well. */
1336 if (GET_CODE (op1
) != CONST_INT
|| GET_CODE (op2
) != CONST_INT
)
1339 /* Selected bits all zero: CC0.
1340 e.g.: int a; if ((a & (16 + 128)) == 0) */
1341 if (INTVAL (op2
) == 0)
1344 /* Selected bits all one: CC3.
1345 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
1346 if (INTVAL (op2
) == INTVAL (op1
))
1349 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
1351 if ((a & (16 + 128)) == 16) -> CCT1
1352 if ((a & (16 + 128)) == 128) -> CCT2 */
1355 bit1
= exact_log2 (INTVAL (op2
));
1356 bit0
= exact_log2 (INTVAL (op1
) ^ INTVAL (op2
));
1357 if (bit0
!= -1 && bit1
!= -1)
1358 return bit0
> bit1
? CCT1mode
: CCT2mode
;
1364 /* Given a comparison code OP (EQ, NE, etc.) and the operands
1365 OP0 and OP1 of a COMPARE, return the mode to be used for the
1369 s390_select_ccmode (enum rtx_code code
, rtx op0
, rtx op1
)
1372 && register_operand (op0
, DFmode
)
1373 && register_operand (op1
, DFmode
))
1375 /* LT, LE, UNGT, UNGE require swapping OP0 and OP1. Either
1376 s390_emit_compare or s390_canonicalize_comparison will take
1398 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
1399 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
1401 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
1402 && CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1))))
1404 if ((GET_CODE (op0
) == PLUS
|| GET_CODE (op0
) == MINUS
1405 || GET_CODE (op1
) == NEG
)
1406 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
1409 if (GET_CODE (op0
) == AND
)
1411 /* Check whether we can potentially do it via TM. */
1412 machine_mode ccmode
;
1413 ccmode
= s390_tm_ccmode (XEXP (op0
, 1), op1
, 1);
1414 if (ccmode
!= VOIDmode
)
1416 /* Relax CCTmode to CCZmode to allow fall-back to AND
1417 if that turns out to be beneficial. */
1418 return ccmode
== CCTmode
? CCZmode
: ccmode
;
1422 if (register_operand (op0
, HImode
)
1423 && GET_CODE (op1
) == CONST_INT
1424 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 65535))
1426 if (register_operand (op0
, QImode
)
1427 && GET_CODE (op1
) == CONST_INT
1428 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 255))
1437 /* The only overflow condition of NEG and ABS happens when
1438 -INT_MAX is used as parameter, which stays negative. So
1439 we have an overflow from a positive value to a negative.
1440 Using CCAP mode the resulting cc can be used for comparisons. */
1441 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
1442 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
1445 /* If constants are involved in an add instruction it is possible to use
1446 the resulting cc for comparisons with zero. Knowing the sign of the
1447 constant the overflow behavior gets predictable. e.g.:
1448 int a, b; if ((b = a + c) > 0)
1449 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
1450 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
1451 && (CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1)))
1452 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (XEXP (op0
, 1)), 'O', "Os")
1453 /* Avoid INT32_MIN on 32 bit. */
1454 && (!TARGET_ZARCH
|| INTVAL (XEXP (op0
, 1)) != -0x7fffffff - 1))))
1456 if (INTVAL (XEXP((op0
), 1)) < 0)
1470 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
1471 && GET_CODE (op1
) != CONST_INT
)
1477 if (GET_CODE (op0
) == PLUS
1478 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
1481 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
1482 && GET_CODE (op1
) != CONST_INT
)
1488 if (GET_CODE (op0
) == MINUS
1489 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
1492 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
1493 && GET_CODE (op1
) != CONST_INT
)
1502 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
1503 that we can implement more efficiently. */
1506 s390_canonicalize_comparison (int *code
, rtx
*op0
, rtx
*op1
,
1507 bool op0_preserve_value
)
1509 if (op0_preserve_value
)
1512 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
1513 if ((*code
== EQ
|| *code
== NE
)
1514 && *op1
== const0_rtx
1515 && GET_CODE (*op0
) == ZERO_EXTRACT
1516 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
1517 && GET_CODE (XEXP (*op0
, 2)) == CONST_INT
1518 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
1520 rtx inner
= XEXP (*op0
, 0);
1521 HOST_WIDE_INT modesize
= GET_MODE_BITSIZE (GET_MODE (inner
));
1522 HOST_WIDE_INT len
= INTVAL (XEXP (*op0
, 1));
1523 HOST_WIDE_INT pos
= INTVAL (XEXP (*op0
, 2));
1525 if (len
> 0 && len
< modesize
1526 && pos
>= 0 && pos
+ len
<= modesize
1527 && modesize
<= HOST_BITS_PER_WIDE_INT
)
1529 unsigned HOST_WIDE_INT block
;
1530 block
= ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
1531 block
<<= modesize
- pos
- len
;
1533 *op0
= gen_rtx_AND (GET_MODE (inner
), inner
,
1534 gen_int_mode (block
, GET_MODE (inner
)));
1538 /* Narrow AND of memory against immediate to enable TM. */
1539 if ((*code
== EQ
|| *code
== NE
)
1540 && *op1
== const0_rtx
1541 && GET_CODE (*op0
) == AND
1542 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
1543 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
1545 rtx inner
= XEXP (*op0
, 0);
1546 rtx mask
= XEXP (*op0
, 1);
1548 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
1549 if (GET_CODE (inner
) == SUBREG
1550 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner
)))
1551 && (GET_MODE_SIZE (GET_MODE (inner
))
1552 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner
))))
1554 & GET_MODE_MASK (GET_MODE (inner
))
1555 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner
))))
1557 inner
= SUBREG_REG (inner
);
1559 /* Do not change volatile MEMs. */
1560 if (MEM_P (inner
) && !MEM_VOLATILE_P (inner
))
1562 int part
= s390_single_part (XEXP (*op0
, 1),
1563 GET_MODE (inner
), QImode
, 0);
1566 mask
= gen_int_mode (s390_extract_part (mask
, QImode
, 0), QImode
);
1567 inner
= adjust_address_nv (inner
, QImode
, part
);
1568 *op0
= gen_rtx_AND (QImode
, inner
, mask
);
1573 /* Narrow comparisons against 0xffff to HImode if possible. */
1574 if ((*code
== EQ
|| *code
== NE
)
1575 && GET_CODE (*op1
) == CONST_INT
1576 && INTVAL (*op1
) == 0xffff
1577 && SCALAR_INT_MODE_P (GET_MODE (*op0
))
1578 && (nonzero_bits (*op0
, GET_MODE (*op0
))
1579 & ~(unsigned HOST_WIDE_INT
) 0xffff) == 0)
1581 *op0
= gen_lowpart (HImode
, *op0
);
1585 /* Remove redundant UNSPEC_STRCMPCC_TO_INT conversions if possible. */
1586 if (GET_CODE (*op0
) == UNSPEC
1587 && XINT (*op0
, 1) == UNSPEC_STRCMPCC_TO_INT
1588 && XVECLEN (*op0
, 0) == 1
1589 && GET_MODE (XVECEXP (*op0
, 0, 0)) == CCUmode
1590 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
1591 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
1592 && *op1
== const0_rtx
)
1594 enum rtx_code new_code
= UNKNOWN
;
1597 case EQ
: new_code
= EQ
; break;
1598 case NE
: new_code
= NE
; break;
1599 case LT
: new_code
= GTU
; break;
1600 case GT
: new_code
= LTU
; break;
1601 case LE
: new_code
= GEU
; break;
1602 case GE
: new_code
= LEU
; break;
1606 if (new_code
!= UNKNOWN
)
1608 *op0
= XVECEXP (*op0
, 0, 0);
1613 /* Remove redundant UNSPEC_CC_TO_INT conversions if possible. */
1614 if (GET_CODE (*op0
) == UNSPEC
1615 && XINT (*op0
, 1) == UNSPEC_CC_TO_INT
1616 && XVECLEN (*op0
, 0) == 1
1617 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
1618 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
1619 && CONST_INT_P (*op1
))
1621 enum rtx_code new_code
= UNKNOWN
;
1622 switch (GET_MODE (XVECEXP (*op0
, 0, 0)))
1628 case EQ
: new_code
= EQ
; break;
1629 case NE
: new_code
= NE
; break;
1636 if (new_code
!= UNKNOWN
)
1638 /* For CCRAWmode put the required cc mask into the second
1640 if (GET_MODE (XVECEXP (*op0
, 0, 0)) == CCRAWmode
1641 && INTVAL (*op1
) >= 0 && INTVAL (*op1
) <= 3)
1642 *op1
= gen_rtx_CONST_INT (VOIDmode
, 1 << (3 - INTVAL (*op1
)));
1643 *op0
= XVECEXP (*op0
, 0, 0);
1648 /* Simplify cascaded EQ, NE with const0_rtx. */
1649 if ((*code
== NE
|| *code
== EQ
)
1650 && (GET_CODE (*op0
) == EQ
|| GET_CODE (*op0
) == NE
)
1651 && GET_MODE (*op0
) == SImode
1652 && GET_MODE (XEXP (*op0
, 0)) == CCZ1mode
1653 && REG_P (XEXP (*op0
, 0))
1654 && XEXP (*op0
, 1) == const0_rtx
1655 && *op1
== const0_rtx
)
1657 if ((*code
== EQ
&& GET_CODE (*op0
) == NE
)
1658 || (*code
== NE
&& GET_CODE (*op0
) == EQ
))
1662 *op0
= XEXP (*op0
, 0);
1665 /* Prefer register over memory as first operand. */
1666 if (MEM_P (*op0
) && REG_P (*op1
))
1668 rtx tem
= *op0
; *op0
= *op1
; *op1
= tem
;
1669 *code
= (int)swap_condition ((enum rtx_code
)*code
);
1672 /* Using the scalar variants of vector instructions for 64 bit FP
1673 comparisons might require swapping the operands. */
1675 && register_operand (*op0
, DFmode
)
1676 && register_operand (*op1
, DFmode
)
1677 && (*code
== LT
|| *code
== LE
|| *code
== UNGT
|| *code
== UNGE
))
1683 case LT
: *code
= GT
; break;
1684 case LE
: *code
= GE
; break;
1685 case UNGT
: *code
= UNLE
; break;
1686 case UNGE
: *code
= UNLT
; break;
1689 tmp
= *op0
; *op0
= *op1
; *op1
= tmp
;
1693 /* Helper function for s390_emit_compare. If possible emit a 64 bit
1694 FP compare using the single element variant of vector instructions.
1695 Replace CODE with the comparison code to be used in the CC reg
1696 compare and return the condition code register RTX in CC. */
1699 s390_expand_vec_compare_scalar (enum rtx_code
*code
, rtx cmp1
, rtx cmp2
,
1702 machine_mode cmp_mode
;
1703 bool swap_p
= false;
1707 case EQ
: cmp_mode
= CCVEQmode
; break;
1708 case NE
: cmp_mode
= CCVEQmode
; break;
1709 case GT
: cmp_mode
= CCVFHmode
; break;
1710 case GE
: cmp_mode
= CCVFHEmode
; break;
1711 case UNLE
: cmp_mode
= CCVFHmode
; break;
1712 case UNLT
: cmp_mode
= CCVFHEmode
; break;
1713 case LT
: cmp_mode
= CCVFHmode
; *code
= GT
; swap_p
= true; break;
1714 case LE
: cmp_mode
= CCVFHEmode
; *code
= GE
; swap_p
= true; break;
1715 case UNGE
: cmp_mode
= CCVFHmode
; *code
= UNLE
; swap_p
= true; break;
1716 case UNGT
: cmp_mode
= CCVFHEmode
; *code
= UNLT
; swap_p
= true; break;
1717 default: return false;
1726 *cc
= gen_rtx_REG (cmp_mode
, CC_REGNUM
);
1727 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
1730 gen_rtx_COMPARE (cmp_mode
, cmp1
,
1732 gen_rtx_CLOBBER (VOIDmode
,
1733 gen_rtx_SCRATCH (V2DImode
)))));
1738 /* Emit a compare instruction suitable to implement the comparison
1739 OP0 CODE OP1. Return the correct condition RTL to be placed in
1740 the IF_THEN_ELSE of the conditional branch testing the result. */
1743 s390_emit_compare (enum rtx_code code
, rtx op0
, rtx op1
)
1745 machine_mode mode
= s390_select_ccmode (code
, op0
, op1
);
1749 && register_operand (op0
, DFmode
)
1750 && register_operand (op1
, DFmode
)
1751 && s390_expand_vec_compare_scalar (&code
, op0
, op1
, &cc
))
1753 /* Work has been done by s390_expand_vec_compare_scalar already. */
1755 else if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
1757 /* Do not output a redundant compare instruction if a
1758 compare_and_swap pattern already computed the result and the
1759 machine modes are compatible. */
1760 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0
), mode
)
1766 cc
= gen_rtx_REG (mode
, CC_REGNUM
);
1767 emit_insn (gen_rtx_SET (cc
, gen_rtx_COMPARE (mode
, op0
, op1
)));
1770 return gen_rtx_fmt_ee (code
, VOIDmode
, cc
, const0_rtx
);
1773 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
1775 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
1776 conditional branch testing the result. */
1779 s390_emit_compare_and_swap (enum rtx_code code
, rtx old
, rtx mem
,
1780 rtx cmp
, rtx new_rtx
)
1782 emit_insn (gen_atomic_compare_and_swapsi_internal (old
, mem
, cmp
, new_rtx
));
1783 return s390_emit_compare (code
, gen_rtx_REG (CCZ1mode
, CC_REGNUM
),
1787 /* Emit a jump instruction to TARGET and return it. If COND is
1788 NULL_RTX, emit an unconditional jump, else a conditional jump under
1792 s390_emit_jump (rtx target
, rtx cond
)
1796 target
= gen_rtx_LABEL_REF (VOIDmode
, target
);
1798 target
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, target
, pc_rtx
);
1800 insn
= gen_rtx_SET (pc_rtx
, target
);
1801 return emit_jump_insn (insn
);
1804 /* Return branch condition mask to implement a branch
1805 specified by CODE. Return -1 for invalid comparisons. */
1808 s390_branch_condition_mask (rtx code
)
1810 const int CC0
= 1 << 3;
1811 const int CC1
= 1 << 2;
1812 const int CC2
= 1 << 1;
1813 const int CC3
= 1 << 0;
1815 gcc_assert (GET_CODE (XEXP (code
, 0)) == REG
);
1816 gcc_assert (REGNO (XEXP (code
, 0)) == CC_REGNUM
);
1817 gcc_assert (XEXP (code
, 1) == const0_rtx
1818 || (GET_MODE (XEXP (code
, 0)) == CCRAWmode
1819 && CONST_INT_P (XEXP (code
, 1))));
1822 switch (GET_MODE (XEXP (code
, 0)))
1826 switch (GET_CODE (code
))
1828 case EQ
: return CC0
;
1829 case NE
: return CC1
| CC2
| CC3
;
1835 switch (GET_CODE (code
))
1837 case EQ
: return CC1
;
1838 case NE
: return CC0
| CC2
| CC3
;
1844 switch (GET_CODE (code
))
1846 case EQ
: return CC2
;
1847 case NE
: return CC0
| CC1
| CC3
;
1853 switch (GET_CODE (code
))
1855 case EQ
: return CC3
;
1856 case NE
: return CC0
| CC1
| CC2
;
1862 switch (GET_CODE (code
))
1864 case EQ
: return CC0
| CC2
;
1865 case NE
: return CC1
| CC3
;
1871 switch (GET_CODE (code
))
1873 case LTU
: return CC2
| CC3
; /* carry */
1874 case GEU
: return CC0
| CC1
; /* no carry */
1880 switch (GET_CODE (code
))
1882 case GTU
: return CC0
| CC1
; /* borrow */
1883 case LEU
: return CC2
| CC3
; /* no borrow */
1889 switch (GET_CODE (code
))
1891 case EQ
: return CC0
| CC2
;
1892 case NE
: return CC1
| CC3
;
1893 case LTU
: return CC1
;
1894 case GTU
: return CC3
;
1895 case LEU
: return CC1
| CC2
;
1896 case GEU
: return CC2
| CC3
;
1901 switch (GET_CODE (code
))
1903 case EQ
: return CC0
;
1904 case NE
: return CC1
| CC2
| CC3
;
1905 case LTU
: return CC1
;
1906 case GTU
: return CC2
;
1907 case LEU
: return CC0
| CC1
;
1908 case GEU
: return CC0
| CC2
;
1914 switch (GET_CODE (code
))
1916 case EQ
: return CC0
;
1917 case NE
: return CC2
| CC1
| CC3
;
1918 case LTU
: return CC2
;
1919 case GTU
: return CC1
;
1920 case LEU
: return CC0
| CC2
;
1921 case GEU
: return CC0
| CC1
;
1927 switch (GET_CODE (code
))
1929 case EQ
: return CC0
;
1930 case NE
: return CC1
| CC2
| CC3
;
1931 case LT
: return CC1
| CC3
;
1932 case GT
: return CC2
;
1933 case LE
: return CC0
| CC1
| CC3
;
1934 case GE
: return CC0
| CC2
;
1940 switch (GET_CODE (code
))
1942 case EQ
: return CC0
;
1943 case NE
: return CC1
| CC2
| CC3
;
1944 case LT
: return CC1
;
1945 case GT
: return CC2
| CC3
;
1946 case LE
: return CC0
| CC1
;
1947 case GE
: return CC0
| CC2
| CC3
;
1953 switch (GET_CODE (code
))
1955 case EQ
: return CC0
;
1956 case NE
: return CC1
| CC2
| CC3
;
1957 case LT
: return CC1
;
1958 case GT
: return CC2
;
1959 case LE
: return CC0
| CC1
;
1960 case GE
: return CC0
| CC2
;
1961 case UNORDERED
: return CC3
;
1962 case ORDERED
: return CC0
| CC1
| CC2
;
1963 case UNEQ
: return CC0
| CC3
;
1964 case UNLT
: return CC1
| CC3
;
1965 case UNGT
: return CC2
| CC3
;
1966 case UNLE
: return CC0
| CC1
| CC3
;
1967 case UNGE
: return CC0
| CC2
| CC3
;
1968 case LTGT
: return CC1
| CC2
;
1974 switch (GET_CODE (code
))
1976 case EQ
: return CC0
;
1977 case NE
: return CC2
| CC1
| CC3
;
1978 case LT
: return CC2
;
1979 case GT
: return CC1
;
1980 case LE
: return CC0
| CC2
;
1981 case GE
: return CC0
| CC1
;
1982 case UNORDERED
: return CC3
;
1983 case ORDERED
: return CC0
| CC2
| CC1
;
1984 case UNEQ
: return CC0
| CC3
;
1985 case UNLT
: return CC2
| CC3
;
1986 case UNGT
: return CC1
| CC3
;
1987 case UNLE
: return CC0
| CC2
| CC3
;
1988 case UNGE
: return CC0
| CC1
| CC3
;
1989 case LTGT
: return CC2
| CC1
;
1994 /* Vector comparison modes. */
1997 switch (GET_CODE (code
))
1999 case EQ
: return CC0
;
2000 case NE
: return CC3
;
2005 switch (GET_CODE (code
))
2007 case EQ
: return CC0
| CC1
;
2008 case NE
: return CC3
| CC1
;
2012 /* Integer vector compare modes. */
2015 switch (GET_CODE (code
))
2017 case GT
: return CC0
;
2018 case LE
: return CC3
;
2023 switch (GET_CODE (code
))
2025 case GT
: return CC0
| CC1
;
2026 case LE
: return CC3
| CC1
;
2031 switch (GET_CODE (code
))
2033 case GTU
: return CC0
;
2034 case LEU
: return CC3
;
2039 switch (GET_CODE (code
))
2041 case GTU
: return CC0
| CC1
;
2042 case LEU
: return CC3
| CC1
;
2046 /* FP vector compare modes. */
2049 switch (GET_CODE (code
))
2051 case GT
: return CC0
;
2052 case UNLE
: return CC3
;
2057 switch (GET_CODE (code
))
2059 case GT
: return CC0
| CC1
;
2060 case UNLE
: return CC3
| CC1
;
2065 switch (GET_CODE (code
))
2067 case GE
: return CC0
;
2068 case UNLT
: return CC3
;
2073 switch (GET_CODE (code
))
2075 case GE
: return CC0
| CC1
;
2076 case UNLT
: return CC3
| CC1
;
2082 switch (GET_CODE (code
))
2085 return INTVAL (XEXP (code
, 1));
2087 return (INTVAL (XEXP (code
, 1))) ^ 0xf;
2098 /* Return branch condition mask to implement a compare and branch
2099 specified by CODE. Return -1 for invalid comparisons. */
2102 s390_compare_and_branch_condition_mask (rtx code
)
2104 const int CC0
= 1 << 3;
2105 const int CC1
= 1 << 2;
2106 const int CC2
= 1 << 1;
2108 switch (GET_CODE (code
))
2132 /* If INV is false, return assembler mnemonic string to implement
2133 a branch specified by CODE. If INV is true, return mnemonic
2134 for the corresponding inverted branch. */
2137 s390_branch_condition_mnemonic (rtx code
, int inv
)
2141 static const char *const mnemonic
[16] =
2143 NULL
, "o", "h", "nle",
2144 "l", "nhe", "lh", "ne",
2145 "e", "nlh", "he", "nl",
2146 "le", "nh", "no", NULL
2149 if (GET_CODE (XEXP (code
, 0)) == REG
2150 && REGNO (XEXP (code
, 0)) == CC_REGNUM
2151 && (XEXP (code
, 1) == const0_rtx
2152 || (GET_MODE (XEXP (code
, 0)) == CCRAWmode
2153 && CONST_INT_P (XEXP (code
, 1)))))
2154 mask
= s390_branch_condition_mask (code
);
2156 mask
= s390_compare_and_branch_condition_mask (code
);
2158 gcc_assert (mask
>= 0);
2163 gcc_assert (mask
>= 1 && mask
<= 14);
2165 return mnemonic
[mask
];
2168 /* Return the part of op which has a value different from def.
2169 The size of the part is determined by mode.
2170 Use this function only if you already know that op really
2171 contains such a part. */
2173 unsigned HOST_WIDE_INT
2174 s390_extract_part (rtx op
, machine_mode mode
, int def
)
2176 unsigned HOST_WIDE_INT value
= 0;
2177 int max_parts
= HOST_BITS_PER_WIDE_INT
/ GET_MODE_BITSIZE (mode
);
2178 int part_bits
= GET_MODE_BITSIZE (mode
);
2179 unsigned HOST_WIDE_INT part_mask
2180 = ((unsigned HOST_WIDE_INT
)1 << part_bits
) - 1;
2183 for (i
= 0; i
< max_parts
; i
++)
2186 value
= (unsigned HOST_WIDE_INT
) INTVAL (op
);
2188 value
>>= part_bits
;
2190 if ((value
& part_mask
) != (def
& part_mask
))
2191 return value
& part_mask
;
2197 /* If OP is an integer constant of mode MODE with exactly one
2198 part of mode PART_MODE unequal to DEF, return the number of that
2199 part. Otherwise, return -1. */
2202 s390_single_part (rtx op
,
2204 machine_mode part_mode
,
2207 unsigned HOST_WIDE_INT value
= 0;
2208 int n_parts
= GET_MODE_SIZE (mode
) / GET_MODE_SIZE (part_mode
);
2209 unsigned HOST_WIDE_INT part_mask
2210 = ((unsigned HOST_WIDE_INT
)1 << GET_MODE_BITSIZE (part_mode
)) - 1;
2213 if (GET_CODE (op
) != CONST_INT
)
2216 for (i
= 0; i
< n_parts
; i
++)
2219 value
= (unsigned HOST_WIDE_INT
) INTVAL (op
);
2221 value
>>= GET_MODE_BITSIZE (part_mode
);
2223 if ((value
& part_mask
) != (def
& part_mask
))
2231 return part
== -1 ? -1 : n_parts
- 1 - part
;
2234 /* Return true if IN contains a contiguous bitfield in the lower SIZE
2235 bits and no other bits are set in IN. POS and LENGTH can be used
2236 to obtain the start position and the length of the bitfield.
2238 POS gives the position of the first bit of the bitfield counting
2239 from the lowest order bit starting with zero. In order to use this
2240 value for S/390 instructions this has to be converted to "bits big
2244 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in
, int size
,
2245 int *pos
, int *length
)
2250 unsigned HOST_WIDE_INT mask
= 1ULL;
2251 bool contiguous
= false;
2253 for (i
= 0; i
< size
; mask
<<= 1, i
++)
2277 /* Calculate a mask for all bits beyond the contiguous bits. */
2278 mask
= (-1LL & ~(((1ULL << (tmp_length
+ tmp_pos
- 1)) << 1) - 1));
2280 if ((unsigned)size
< sizeof (HOST_WIDE_INT
) * BITS_PER_UNIT
)
2281 mask
&= (HOST_WIDE_INT_1U
<< size
) - 1;
2286 if (tmp_length
+ tmp_pos
- 1 > size
)
2290 *length
= tmp_length
;
2298 /* Return true if OP contains the same contiguous bitfield in *all*
2299 its elements. START and END can be used to obtain the start and
2300 end position of the bitfield.
2302 START/STOP give the position of the first/last bit of the bitfield
2303 counting from the lowest order bit starting with zero. In order to
2304 use these values for S/390 instructions this has to be converted to
2305 "bits big endian" style. */
2308 s390_contiguous_bitmask_vector_p (rtx op
, int *start
, int *end
)
2310 unsigned HOST_WIDE_INT mask
;
2314 if (!const_vec_duplicate_p (op
, &elt
)
2315 || !CONST_INT_P (elt
))
2318 size
= GET_MODE_UNIT_BITSIZE (GET_MODE (op
));
2320 /* We cannot deal with V1TI/V1TF. This would require a vgmq. */
2324 mask
= UINTVAL (elt
);
2325 if (s390_contiguous_bitmask_p (mask
, size
, start
,
2326 end
!= NULL
? &length
: NULL
))
2329 *end
= *start
+ length
- 1;
2332 /* 0xff00000f style immediates can be covered by swapping start and
2333 end indices in vgm. */
2334 if (s390_contiguous_bitmask_p (~mask
, size
, start
,
2335 end
!= NULL
? &length
: NULL
))
2340 *start
= *start
+ length
;
2346 /* Return true if C consists only of byte chunks being either 0 or
2347 0xff. If MASK is !=NULL a byte mask is generated which is
2348 appropriate for the vector generate byte mask instruction. */
2351 s390_bytemask_vector_p (rtx op
, unsigned *mask
)
2354 unsigned tmp_mask
= 0;
2355 int nunit
, unit_size
;
2357 if (!VECTOR_MODE_P (GET_MODE (op
))
2358 || GET_CODE (op
) != CONST_VECTOR
2359 || !CONST_INT_P (XVECEXP (op
, 0, 0)))
2362 nunit
= GET_MODE_NUNITS (GET_MODE (op
));
2363 unit_size
= GET_MODE_UNIT_SIZE (GET_MODE (op
));
2365 for (i
= 0; i
< nunit
; i
++)
2367 unsigned HOST_WIDE_INT c
;
2370 if (!CONST_INT_P (XVECEXP (op
, 0, i
)))
2373 c
= UINTVAL (XVECEXP (op
, 0, i
));
2374 for (j
= 0; j
< unit_size
; j
++)
2376 if ((c
& 0xff) != 0 && (c
& 0xff) != 0xff)
2378 tmp_mask
|= (c
& 1) << ((nunit
- 1 - i
) * unit_size
+ j
);
2379 c
= c
>> BITS_PER_UNIT
;
2389 /* Check whether a rotate of ROTL followed by an AND of CONTIG is
2390 equivalent to a shift followed by the AND. In particular, CONTIG
2391 should not overlap the (rotated) bit 0/bit 63 gap. Negative values
2392 for ROTL indicate a rotate to the right. */
2395 s390_extzv_shift_ok (int bitsize
, int rotl
, unsigned HOST_WIDE_INT contig
)
2400 ok
= s390_contiguous_bitmask_p (contig
, bitsize
, &pos
, &len
);
2403 return ((rotl
>= 0 && rotl
<= pos
)
2404 || (rotl
< 0 && -rotl
<= bitsize
- len
- pos
));
2407 /* Check whether we can (and want to) split a double-word
2408 move in mode MODE from SRC to DST into two single-word
2409 moves, moving the subword FIRST_SUBWORD first. */
2412 s390_split_ok_p (rtx dst
, rtx src
, machine_mode mode
, int first_subword
)
2414 /* Floating point and vector registers cannot be split. */
2415 if (FP_REG_P (src
) || FP_REG_P (dst
) || VECTOR_REG_P (src
) || VECTOR_REG_P (dst
))
2418 /* We don't need to split if operands are directly accessible. */
2419 if (s_operand (src
, mode
) || s_operand (dst
, mode
))
2422 /* Non-offsettable memory references cannot be split. */
2423 if ((GET_CODE (src
) == MEM
&& !offsettable_memref_p (src
))
2424 || (GET_CODE (dst
) == MEM
&& !offsettable_memref_p (dst
)))
2427 /* Moving the first subword must not clobber a register
2428 needed to move the second subword. */
2429 if (register_operand (dst
, mode
))
2431 rtx subreg
= operand_subword (dst
, first_subword
, 0, mode
);
2432 if (reg_overlap_mentioned_p (subreg
, src
))
2439 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
2440 and [MEM2, MEM2 + SIZE] do overlap and false
2444 s390_overlap_p (rtx mem1
, rtx mem2
, HOST_WIDE_INT size
)
2446 rtx addr1
, addr2
, addr_delta
;
2447 HOST_WIDE_INT delta
;
2449 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
2455 addr1
= XEXP (mem1
, 0);
2456 addr2
= XEXP (mem2
, 0);
2458 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
2460 /* This overlapping check is used by peepholes merging memory block operations.
2461 Overlapping operations would otherwise be recognized by the S/390 hardware
2462 and would fall back to a slower implementation. Allowing overlapping
2463 operations would lead to slow code but not to wrong code. Therefore we are
2464 somewhat optimistic if we cannot prove that the memory blocks are
2466 That's why we return false here although this may accept operations on
2467 overlapping memory areas. */
2468 if (!addr_delta
|| GET_CODE (addr_delta
) != CONST_INT
)
2471 delta
= INTVAL (addr_delta
);
2474 || (delta
> 0 && delta
< size
)
2475 || (delta
< 0 && -delta
< size
))
2481 /* Check whether the address of memory reference MEM2 equals exactly
2482 the address of memory reference MEM1 plus DELTA. Return true if
2483 we can prove this to be the case, false otherwise. */
2486 s390_offset_p (rtx mem1
, rtx mem2
, rtx delta
)
2488 rtx addr1
, addr2
, addr_delta
;
2490 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
2493 addr1
= XEXP (mem1
, 0);
2494 addr2
= XEXP (mem2
, 0);
2496 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
2497 if (!addr_delta
|| !rtx_equal_p (addr_delta
, delta
))
2503 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
2506 s390_expand_logical_operator (enum rtx_code code
, machine_mode mode
,
2509 machine_mode wmode
= mode
;
2510 rtx dst
= operands
[0];
2511 rtx src1
= operands
[1];
2512 rtx src2
= operands
[2];
2515 /* If we cannot handle the operation directly, use a temp register. */
2516 if (!s390_logical_operator_ok_p (operands
))
2517 dst
= gen_reg_rtx (mode
);
2519 /* QImode and HImode patterns make sense only if we have a destination
2520 in memory. Otherwise perform the operation in SImode. */
2521 if ((mode
== QImode
|| mode
== HImode
) && GET_CODE (dst
) != MEM
)
2524 /* Widen operands if required. */
2527 if (GET_CODE (dst
) == SUBREG
2528 && (tem
= simplify_subreg (wmode
, dst
, mode
, 0)) != 0)
2530 else if (REG_P (dst
))
2531 dst
= gen_rtx_SUBREG (wmode
, dst
, 0);
2533 dst
= gen_reg_rtx (wmode
);
2535 if (GET_CODE (src1
) == SUBREG
2536 && (tem
= simplify_subreg (wmode
, src1
, mode
, 0)) != 0)
2538 else if (GET_MODE (src1
) != VOIDmode
)
2539 src1
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src1
), 0);
2541 if (GET_CODE (src2
) == SUBREG
2542 && (tem
= simplify_subreg (wmode
, src2
, mode
, 0)) != 0)
2544 else if (GET_MODE (src2
) != VOIDmode
)
2545 src2
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src2
), 0);
2548 /* Emit the instruction. */
2549 op
= gen_rtx_SET (dst
, gen_rtx_fmt_ee (code
, wmode
, src1
, src2
));
2550 clob
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
2551 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clob
)));
2553 /* Fix up the destination if needed. */
2554 if (dst
!= operands
[0])
2555 emit_move_insn (operands
[0], gen_lowpart (mode
, dst
));
2558 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
2561 s390_logical_operator_ok_p (rtx
*operands
)
2563 /* If the destination operand is in memory, it needs to coincide
2564 with one of the source operands. After reload, it has to be
2565 the first source operand. */
2566 if (GET_CODE (operands
[0]) == MEM
)
2567 return rtx_equal_p (operands
[0], operands
[1])
2568 || (!reload_completed
&& rtx_equal_p (operands
[0], operands
[2]));
2573 /* Narrow logical operation CODE of memory operand MEMOP with immediate
2574 operand IMMOP to switch from SS to SI type instructions. */
2577 s390_narrow_logical_operator (enum rtx_code code
, rtx
*memop
, rtx
*immop
)
2579 int def
= code
== AND
? -1 : 0;
2583 gcc_assert (GET_CODE (*memop
) == MEM
);
2584 gcc_assert (!MEM_VOLATILE_P (*memop
));
2586 mask
= s390_extract_part (*immop
, QImode
, def
);
2587 part
= s390_single_part (*immop
, GET_MODE (*memop
), QImode
, def
);
2588 gcc_assert (part
>= 0);
2590 *memop
= adjust_address (*memop
, QImode
, part
);
2591 *immop
= gen_int_mode (mask
, QImode
);
2595 /* How to allocate a 'struct machine_function'. */
2597 static struct machine_function
*
2598 s390_init_machine_status (void)
2600 return ggc_cleared_alloc
<machine_function
> ();
2603 /* Map for smallest class containing reg regno. */
2605 const enum reg_class regclass_map
[FIRST_PSEUDO_REGISTER
] =
2606 { GENERAL_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, /* 0 */
2607 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, /* 4 */
2608 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, /* 8 */
2609 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, /* 12 */
2610 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
, /* 16 */
2611 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
, /* 20 */
2612 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
, /* 24 */
2613 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
, /* 28 */
2614 ADDR_REGS
, CC_REGS
, ADDR_REGS
, ADDR_REGS
, /* 32 */
2615 ACCESS_REGS
, ACCESS_REGS
, VEC_REGS
, VEC_REGS
, /* 36 */
2616 VEC_REGS
, VEC_REGS
, VEC_REGS
, VEC_REGS
, /* 40 */
2617 VEC_REGS
, VEC_REGS
, VEC_REGS
, VEC_REGS
, /* 44 */
2618 VEC_REGS
, VEC_REGS
, VEC_REGS
, VEC_REGS
, /* 48 */
2619 VEC_REGS
, VEC_REGS
/* 52 */
2622 /* Return attribute type of insn. */
2624 static enum attr_type
2625 s390_safe_attr_type (rtx_insn
*insn
)
2627 if (recog_memoized (insn
) >= 0)
2628 return get_attr_type (insn
);
2633 /* Return true if DISP is a valid short displacement. */
2636 s390_short_displacement (rtx disp
)
2638 /* No displacement is OK. */
2642 /* Without the long displacement facility we don't need to
2643 distingiush between long and short displacement. */
2644 if (!TARGET_LONG_DISPLACEMENT
)
2647 /* Integer displacement in range. */
2648 if (GET_CODE (disp
) == CONST_INT
)
2649 return INTVAL (disp
) >= 0 && INTVAL (disp
) < 4096;
2651 /* GOT offset is not OK, the GOT can be large. */
2652 if (GET_CODE (disp
) == CONST
2653 && GET_CODE (XEXP (disp
, 0)) == UNSPEC
2654 && (XINT (XEXP (disp
, 0), 1) == UNSPEC_GOT
2655 || XINT (XEXP (disp
, 0), 1) == UNSPEC_GOTNTPOFF
))
2658 /* All other symbolic constants are literal pool references,
2659 which are OK as the literal pool must be small. */
2660 if (GET_CODE (disp
) == CONST
)
2666 /* Decompose a RTL expression ADDR for a memory address into
2667 its components, returned in OUT.
2669 Returns false if ADDR is not a valid memory address, true
2670 otherwise. If OUT is NULL, don't return the components,
2671 but check for validity only.
2673 Note: Only addresses in canonical form are recognized.
2674 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
2675 canonical form so that they will be recognized. */
2678 s390_decompose_address (rtx addr
, struct s390_address
*out
)
2680 HOST_WIDE_INT offset
= 0;
2681 rtx base
= NULL_RTX
;
2682 rtx indx
= NULL_RTX
;
2683 rtx disp
= NULL_RTX
;
2685 bool pointer
= false;
2686 bool base_ptr
= false;
2687 bool indx_ptr
= false;
2688 bool literal_pool
= false;
2690 /* We may need to substitute the literal pool base register into the address
2691 below. However, at this point we do not know which register is going to
2692 be used as base, so we substitute the arg pointer register. This is going
2693 to be treated as holding a pointer below -- it shouldn't be used for any
2695 rtx fake_pool_base
= gen_rtx_REG (Pmode
, ARG_POINTER_REGNUM
);
2697 /* Decompose address into base + index + displacement. */
2699 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == UNSPEC
)
2702 else if (GET_CODE (addr
) == PLUS
)
2704 rtx op0
= XEXP (addr
, 0);
2705 rtx op1
= XEXP (addr
, 1);
2706 enum rtx_code code0
= GET_CODE (op0
);
2707 enum rtx_code code1
= GET_CODE (op1
);
2709 if (code0
== REG
|| code0
== UNSPEC
)
2711 if (code1
== REG
|| code1
== UNSPEC
)
2713 indx
= op0
; /* index + base */
2719 base
= op0
; /* base + displacement */
2724 else if (code0
== PLUS
)
2726 indx
= XEXP (op0
, 0); /* index + base + disp */
2727 base
= XEXP (op0
, 1);
2738 disp
= addr
; /* displacement */
2740 /* Extract integer part of displacement. */
2744 if (GET_CODE (disp
) == CONST_INT
)
2746 offset
= INTVAL (disp
);
2749 else if (GET_CODE (disp
) == CONST
2750 && GET_CODE (XEXP (disp
, 0)) == PLUS
2751 && GET_CODE (XEXP (XEXP (disp
, 0), 1)) == CONST_INT
)
2753 offset
= INTVAL (XEXP (XEXP (disp
, 0), 1));
2754 disp
= XEXP (XEXP (disp
, 0), 0);
2758 /* Strip off CONST here to avoid special case tests later. */
2759 if (disp
&& GET_CODE (disp
) == CONST
)
2760 disp
= XEXP (disp
, 0);
2762 /* We can convert literal pool addresses to
2763 displacements by basing them off the base register. */
2764 if (disp
&& GET_CODE (disp
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (disp
))
2766 /* Either base or index must be free to hold the base register. */
2768 base
= fake_pool_base
, literal_pool
= true;
2770 indx
= fake_pool_base
, literal_pool
= true;
2774 /* Mark up the displacement. */
2775 disp
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, disp
),
2776 UNSPEC_LTREL_OFFSET
);
2779 /* Validate base register. */
2782 if (GET_CODE (base
) == UNSPEC
)
2783 switch (XINT (base
, 1))
2787 disp
= gen_rtx_UNSPEC (Pmode
,
2788 gen_rtvec (1, XVECEXP (base
, 0, 0)),
2789 UNSPEC_LTREL_OFFSET
);
2793 base
= XVECEXP (base
, 0, 1);
2796 case UNSPEC_LTREL_BASE
:
2797 if (XVECLEN (base
, 0) == 1)
2798 base
= fake_pool_base
, literal_pool
= true;
2800 base
= XVECEXP (base
, 0, 1);
2808 || (GET_MODE (base
) != SImode
2809 && GET_MODE (base
) != Pmode
))
2812 if (REGNO (base
) == STACK_POINTER_REGNUM
2813 || REGNO (base
) == FRAME_POINTER_REGNUM
2814 || ((reload_completed
|| reload_in_progress
)
2815 && frame_pointer_needed
2816 && REGNO (base
) == HARD_FRAME_POINTER_REGNUM
)
2817 || REGNO (base
) == ARG_POINTER_REGNUM
2819 && REGNO (base
) == PIC_OFFSET_TABLE_REGNUM
))
2820 pointer
= base_ptr
= true;
2822 if ((reload_completed
|| reload_in_progress
)
2823 && base
== cfun
->machine
->base_reg
)
2824 pointer
= base_ptr
= literal_pool
= true;
2827 /* Validate index register. */
2830 if (GET_CODE (indx
) == UNSPEC
)
2831 switch (XINT (indx
, 1))
2835 disp
= gen_rtx_UNSPEC (Pmode
,
2836 gen_rtvec (1, XVECEXP (indx
, 0, 0)),
2837 UNSPEC_LTREL_OFFSET
);
2841 indx
= XVECEXP (indx
, 0, 1);
2844 case UNSPEC_LTREL_BASE
:
2845 if (XVECLEN (indx
, 0) == 1)
2846 indx
= fake_pool_base
, literal_pool
= true;
2848 indx
= XVECEXP (indx
, 0, 1);
2856 || (GET_MODE (indx
) != SImode
2857 && GET_MODE (indx
) != Pmode
))
2860 if (REGNO (indx
) == STACK_POINTER_REGNUM
2861 || REGNO (indx
) == FRAME_POINTER_REGNUM
2862 || ((reload_completed
|| reload_in_progress
)
2863 && frame_pointer_needed
2864 && REGNO (indx
) == HARD_FRAME_POINTER_REGNUM
)
2865 || REGNO (indx
) == ARG_POINTER_REGNUM
2867 && REGNO (indx
) == PIC_OFFSET_TABLE_REGNUM
))
2868 pointer
= indx_ptr
= true;
2870 if ((reload_completed
|| reload_in_progress
)
2871 && indx
== cfun
->machine
->base_reg
)
2872 pointer
= indx_ptr
= literal_pool
= true;
2875 /* Prefer to use pointer as base, not index. */
2876 if (base
&& indx
&& !base_ptr
2877 && (indx_ptr
|| (!REG_POINTER (base
) && REG_POINTER (indx
))))
2884 /* Validate displacement. */
2887 /* If virtual registers are involved, the displacement will change later
2888 anyway as the virtual registers get eliminated. This could make a
2889 valid displacement invalid, but it is more likely to make an invalid
2890 displacement valid, because we sometimes access the register save area
2891 via negative offsets to one of those registers.
2892 Thus we don't check the displacement for validity here. If after
2893 elimination the displacement turns out to be invalid after all,
2894 this is fixed up by reload in any case. */
2895 /* LRA maintains always displacements up to date and we need to
2896 know the displacement is right during all LRA not only at the
2897 final elimination. */
2899 || (base
!= arg_pointer_rtx
2900 && indx
!= arg_pointer_rtx
2901 && base
!= return_address_pointer_rtx
2902 && indx
!= return_address_pointer_rtx
2903 && base
!= frame_pointer_rtx
2904 && indx
!= frame_pointer_rtx
2905 && base
!= virtual_stack_vars_rtx
2906 && indx
!= virtual_stack_vars_rtx
))
2907 if (!DISP_IN_RANGE (offset
))
2912 /* All the special cases are pointers. */
2915 /* In the small-PIC case, the linker converts @GOT
2916 and @GOTNTPOFF offsets to possible displacements. */
2917 if (GET_CODE (disp
) == UNSPEC
2918 && (XINT (disp
, 1) == UNSPEC_GOT
2919 || XINT (disp
, 1) == UNSPEC_GOTNTPOFF
)
2925 /* Accept pool label offsets. */
2926 else if (GET_CODE (disp
) == UNSPEC
2927 && XINT (disp
, 1) == UNSPEC_POOL_OFFSET
)
2930 /* Accept literal pool references. */
2931 else if (GET_CODE (disp
) == UNSPEC
2932 && XINT (disp
, 1) == UNSPEC_LTREL_OFFSET
)
2934 /* In case CSE pulled a non literal pool reference out of
2935 the pool we have to reject the address. This is
2936 especially important when loading the GOT pointer on non
2937 zarch CPUs. In this case the literal pool contains an lt
2938 relative offset to the _GLOBAL_OFFSET_TABLE_ label which
2939 will most likely exceed the displacement. */
2940 if (GET_CODE (XVECEXP (disp
, 0, 0)) != SYMBOL_REF
2941 || !CONSTANT_POOL_ADDRESS_P (XVECEXP (disp
, 0, 0)))
2944 orig_disp
= gen_rtx_CONST (Pmode
, disp
);
2947 /* If we have an offset, make sure it does not
2948 exceed the size of the constant pool entry. */
2949 rtx sym
= XVECEXP (disp
, 0, 0);
2950 if (offset
>= GET_MODE_SIZE (get_pool_mode (sym
)))
2953 orig_disp
= plus_constant (Pmode
, orig_disp
, offset
);
2968 out
->disp
= orig_disp
;
2969 out
->pointer
= pointer
;
2970 out
->literal_pool
= literal_pool
;
2976 /* Decompose a RTL expression OP for a shift count into its components,
2977 and return the base register in BASE and the offset in OFFSET.
2979 Return true if OP is a valid shift count, false if not. */
2982 s390_decompose_shift_count (rtx op
, rtx
*base
, HOST_WIDE_INT
*offset
)
2984 HOST_WIDE_INT off
= 0;
2986 /* We can have an integer constant, an address register,
2987 or a sum of the two. */
2988 if (GET_CODE (op
) == CONST_INT
)
2993 if (op
&& GET_CODE (op
) == PLUS
&& GET_CODE (XEXP (op
, 1)) == CONST_INT
)
2995 off
= INTVAL (XEXP (op
, 1));
2998 while (op
&& GET_CODE (op
) == SUBREG
)
2999 op
= SUBREG_REG (op
);
3001 if (op
&& GET_CODE (op
) != REG
)
3013 /* Return true if CODE is a valid address without index. */
3016 s390_legitimate_address_without_index_p (rtx op
)
3018 struct s390_address addr
;
3020 if (!s390_decompose_address (XEXP (op
, 0), &addr
))
3029 /* Return TRUE if ADDR is an operand valid for a load/store relative
3030 instruction. Be aware that the alignment of the operand needs to
3031 be checked separately.
3032 Valid addresses are single references or a sum of a reference and a
3033 constant integer. Return these parts in SYMREF and ADDEND. You can
3034 pass NULL in REF and/or ADDEND if you are not interested in these
3035 values. Literal pool references are *not* considered symbol
3039 s390_loadrelative_operand_p (rtx addr
, rtx
*symref
, HOST_WIDE_INT
*addend
)
3041 HOST_WIDE_INT tmpaddend
= 0;
3043 if (GET_CODE (addr
) == CONST
)
3044 addr
= XEXP (addr
, 0);
3046 if (GET_CODE (addr
) == PLUS
)
3048 if (!CONST_INT_P (XEXP (addr
, 1)))
3051 tmpaddend
= INTVAL (XEXP (addr
, 1));
3052 addr
= XEXP (addr
, 0);
3055 if ((GET_CODE (addr
) == SYMBOL_REF
&& !CONSTANT_POOL_ADDRESS_P (addr
))
3056 || (GET_CODE (addr
) == UNSPEC
3057 && (XINT (addr
, 1) == UNSPEC_GOTENT
3058 || (TARGET_CPU_ZARCH
&& XINT (addr
, 1) == UNSPEC_PLT
))))
3063 *addend
= tmpaddend
;
3070 /* Return true if the address in OP is valid for constraint letter C
3071 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
3072 pool MEMs should be accepted. Only the Q, R, S, T constraint
3073 letters are allowed for C. */
3076 s390_check_qrst_address (char c
, rtx op
, bool lit_pool_ok
)
3078 struct s390_address addr
;
3079 bool decomposed
= false;
3081 /* This check makes sure that no symbolic address (except literal
3082 pool references) are accepted by the R or T constraints. */
3083 if (s390_loadrelative_operand_p (op
, NULL
, NULL
))
3086 /* Ensure literal pool references are only accepted if LIT_POOL_OK. */
3089 if (!s390_decompose_address (op
, &addr
))
3091 if (addr
.literal_pool
)
3098 case 'Q': /* no index short displacement */
3099 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
3103 if (!s390_short_displacement (addr
.disp
))
3107 case 'R': /* with index short displacement */
3108 if (TARGET_LONG_DISPLACEMENT
)
3110 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
3112 if (!s390_short_displacement (addr
.disp
))
3115 /* Any invalid address here will be fixed up by reload,
3116 so accept it for the most generic constraint. */
3119 case 'S': /* no index long displacement */
3120 if (!TARGET_LONG_DISPLACEMENT
)
3122 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
3126 if (s390_short_displacement (addr
.disp
))
3130 case 'T': /* with index long displacement */
3131 if (!TARGET_LONG_DISPLACEMENT
)
3133 /* Any invalid address here will be fixed up by reload,
3134 so accept it for the most generic constraint. */
3135 if ((decomposed
|| s390_decompose_address (op
, &addr
))
3136 && s390_short_displacement (addr
.disp
))
3146 /* Evaluates constraint strings described by the regular expression
3147 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
3148 the constraint given in STR, or 0 else. */
3151 s390_mem_constraint (const char *str
, rtx op
)
3158 /* Check for offsettable variants of memory constraints. */
3159 if (!MEM_P (op
) || MEM_VOLATILE_P (op
))
3161 if ((reload_completed
|| reload_in_progress
)
3162 ? !offsettable_memref_p (op
) : !offsettable_nonstrict_memref_p (op
))
3164 return s390_check_qrst_address (str
[1], XEXP (op
, 0), true);
3166 /* Check for non-literal-pool variants of memory constraints. */
3169 return s390_check_qrst_address (str
[1], XEXP (op
, 0), false);
3174 if (GET_CODE (op
) != MEM
)
3176 return s390_check_qrst_address (c
, XEXP (op
, 0), true);
3178 return (s390_check_qrst_address ('Q', op
, true)
3179 || s390_check_qrst_address ('R', op
, true));
3181 return (s390_check_qrst_address ('S', op
, true)
3182 || s390_check_qrst_address ('T', op
, true));
3184 /* Simply check for the basic form of a shift count. Reload will
3185 take care of making sure we have a proper base register. */
3186 if (!s390_decompose_shift_count (op
, NULL
, NULL
))
3190 return s390_check_qrst_address (str
[1], op
, true);
3198 /* Evaluates constraint strings starting with letter O. Input
3199 parameter C is the second letter following the "O" in the constraint
3200 string. Returns 1 if VALUE meets the respective constraint and 0
3204 s390_O_constraint_str (const char c
, HOST_WIDE_INT value
)
3212 return trunc_int_for_mode (value
, SImode
) == value
;
3216 || s390_single_part (GEN_INT (value
), DImode
, SImode
, 0) == 1;
3219 return s390_single_part (GEN_INT (value
- 1), DImode
, SImode
, -1) == 1;
3227 /* Evaluates constraint strings starting with letter N. Parameter STR
3228 contains the letters following letter "N" in the constraint string.
3229 Returns true if VALUE matches the constraint. */
3232 s390_N_constraint_str (const char *str
, HOST_WIDE_INT value
)
3234 machine_mode mode
, part_mode
;
3236 int part
, part_goal
;
3242 part_goal
= str
[0] - '0';
3286 if (GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (part_mode
))
3289 part
= s390_single_part (GEN_INT (value
), mode
, part_mode
, def
);
3292 if (part_goal
!= -1 && part_goal
!= part
)
3299 /* Returns true if the input parameter VALUE is a float zero. */
3302 s390_float_const_zero_p (rtx value
)
3304 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
3305 && value
== CONST0_RTX (GET_MODE (value
)));
3308 /* Implement TARGET_REGISTER_MOVE_COST. */
3311 s390_register_move_cost (machine_mode mode
,
3312 reg_class_t from
, reg_class_t to
)
3314 /* On s390, copy between fprs and gprs is expensive. */
3316 /* It becomes somewhat faster having ldgr/lgdr. */
3317 if (TARGET_Z10
&& GET_MODE_SIZE (mode
) == 8)
3319 /* ldgr is single cycle. */
3320 if (reg_classes_intersect_p (from
, GENERAL_REGS
)
3321 && reg_classes_intersect_p (to
, FP_REGS
))
3323 /* lgdr needs 3 cycles. */
3324 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
3325 && reg_classes_intersect_p (from
, FP_REGS
))
3329 /* Otherwise copying is done via memory. */
3330 if ((reg_classes_intersect_p (from
, GENERAL_REGS
)
3331 && reg_classes_intersect_p (to
, FP_REGS
))
3332 || (reg_classes_intersect_p (from
, FP_REGS
)
3333 && reg_classes_intersect_p (to
, GENERAL_REGS
)))
3339 /* Implement TARGET_MEMORY_MOVE_COST. */
3342 s390_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
3343 reg_class_t rclass ATTRIBUTE_UNUSED
,
3344 bool in ATTRIBUTE_UNUSED
)
3349 /* Compute a (partial) cost for rtx X. Return true if the complete
3350 cost has been computed, and false if subexpressions should be
3351 scanned. In either case, *TOTAL contains the cost result.
3352 OUTER_CODE contains the code of the superexpression of x. */
3355 s390_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
3356 int opno ATTRIBUTE_UNUSED
,
3357 int *total
, bool speed ATTRIBUTE_UNUSED
)
3359 int code
= GET_CODE (x
);
3367 case CONST_WIDE_INT
:
3374 if (GET_CODE (XEXP (x
, 0)) == AND
3375 && GET_CODE (XEXP (x
, 1)) == ASHIFT
3376 && REG_P (XEXP (XEXP (x
, 0), 0))
3377 && REG_P (XEXP (XEXP (x
, 1), 0))
3378 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
3379 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
3380 && (UINTVAL (XEXP (XEXP (x
, 0), 1)) ==
3381 (1UL << UINTVAL (XEXP (XEXP (x
, 1), 1))) - 1))
3383 *total
= COSTS_N_INSNS (2);
3395 *total
= COSTS_N_INSNS (1);
3400 *total
= COSTS_N_INSNS (1);
3408 rtx left
= XEXP (x
, 0);
3409 rtx right
= XEXP (x
, 1);
3410 if (GET_CODE (right
) == CONST_INT
3411 && CONST_OK_FOR_K (INTVAL (right
)))
3412 *total
= s390_cost
->mhi
;
3413 else if (GET_CODE (left
) == SIGN_EXTEND
)
3414 *total
= s390_cost
->mh
;
3416 *total
= s390_cost
->ms
; /* msr, ms, msy */
3421 rtx left
= XEXP (x
, 0);
3422 rtx right
= XEXP (x
, 1);
3425 if (GET_CODE (right
) == CONST_INT
3426 && CONST_OK_FOR_K (INTVAL (right
)))
3427 *total
= s390_cost
->mghi
;
3428 else if (GET_CODE (left
) == SIGN_EXTEND
)
3429 *total
= s390_cost
->msgf
;
3431 *total
= s390_cost
->msg
; /* msgr, msg */
3433 else /* TARGET_31BIT */
3435 if (GET_CODE (left
) == SIGN_EXTEND
3436 && GET_CODE (right
) == SIGN_EXTEND
)
3437 /* mulsidi case: mr, m */
3438 *total
= s390_cost
->m
;
3439 else if (GET_CODE (left
) == ZERO_EXTEND
3440 && GET_CODE (right
) == ZERO_EXTEND
3441 && TARGET_CPU_ZARCH
)
3442 /* umulsidi case: ml, mlr */
3443 *total
= s390_cost
->ml
;
3445 /* Complex calculation is required. */
3446 *total
= COSTS_N_INSNS (40);
3452 *total
= s390_cost
->mult_df
;
3455 *total
= s390_cost
->mxbr
;
3466 *total
= s390_cost
->madbr
;
3469 *total
= s390_cost
->maebr
;
3474 /* Negate in the third argument is free: FMSUB. */
3475 if (GET_CODE (XEXP (x
, 2)) == NEG
)
3477 *total
+= (rtx_cost (XEXP (x
, 0), mode
, FMA
, 0, speed
)
3478 + rtx_cost (XEXP (x
, 1), mode
, FMA
, 1, speed
)
3479 + rtx_cost (XEXP (XEXP (x
, 2), 0), mode
, FMA
, 2, speed
));
3486 if (mode
== TImode
) /* 128 bit division */
3487 *total
= s390_cost
->dlgr
;
3488 else if (mode
== DImode
)
3490 rtx right
= XEXP (x
, 1);
3491 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
3492 *total
= s390_cost
->dlr
;
3493 else /* 64 by 64 bit division */
3494 *total
= s390_cost
->dlgr
;
3496 else if (mode
== SImode
) /* 32 bit division */
3497 *total
= s390_cost
->dlr
;
3504 rtx right
= XEXP (x
, 1);
3505 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
3507 *total
= s390_cost
->dsgfr
;
3509 *total
= s390_cost
->dr
;
3510 else /* 64 by 64 bit division */
3511 *total
= s390_cost
->dsgr
;
3513 else if (mode
== SImode
) /* 32 bit division */
3514 *total
= s390_cost
->dlr
;
3515 else if (mode
== SFmode
)
3517 *total
= s390_cost
->debr
;
3519 else if (mode
== DFmode
)
3521 *total
= s390_cost
->ddbr
;
3523 else if (mode
== TFmode
)
3525 *total
= s390_cost
->dxbr
;
3531 *total
= s390_cost
->sqebr
;
3532 else if (mode
== DFmode
)
3533 *total
= s390_cost
->sqdbr
;
3535 *total
= s390_cost
->sqxbr
;
3540 if (outer_code
== MULT
|| outer_code
== DIV
|| outer_code
== MOD
3541 || outer_code
== PLUS
|| outer_code
== MINUS
3542 || outer_code
== COMPARE
)
3547 *total
= COSTS_N_INSNS (1);
3548 if (GET_CODE (XEXP (x
, 0)) == AND
3549 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3550 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
3552 rtx op0
= XEXP (XEXP (x
, 0), 0);
3553 rtx op1
= XEXP (XEXP (x
, 0), 1);
3554 rtx op2
= XEXP (x
, 1);
3556 if (memory_operand (op0
, GET_MODE (op0
))
3557 && s390_tm_ccmode (op1
, op2
, 0) != VOIDmode
)
3559 if (register_operand (op0
, GET_MODE (op0
))
3560 && s390_tm_ccmode (op1
, op2
, 1) != VOIDmode
)
3570 /* Return the cost of an address rtx ADDR. */
3573 s390_address_cost (rtx addr
, machine_mode mode ATTRIBUTE_UNUSED
,
3574 addr_space_t as ATTRIBUTE_UNUSED
,
3575 bool speed ATTRIBUTE_UNUSED
)
3577 struct s390_address ad
;
3578 if (!s390_decompose_address (addr
, &ad
))
3581 return ad
.indx
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
3584 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
3585 otherwise return 0. */
3588 tls_symbolic_operand (rtx op
)
3590 if (GET_CODE (op
) != SYMBOL_REF
)
3592 return SYMBOL_REF_TLS_MODEL (op
);
3595 /* Split DImode access register reference REG (on 64-bit) into its constituent
3596 low and high parts, and store them into LO and HI. Note that gen_lowpart/
3597 gen_highpart cannot be used as they assume all registers are word-sized,
3598 while our access registers have only half that size. */
3601 s390_split_access_reg (rtx reg
, rtx
*lo
, rtx
*hi
)
3603 gcc_assert (TARGET_64BIT
);
3604 gcc_assert (ACCESS_REG_P (reg
));
3605 gcc_assert (GET_MODE (reg
) == DImode
);
3606 gcc_assert (!(REGNO (reg
) & 1));
3608 *lo
= gen_rtx_REG (SImode
, REGNO (reg
) + 1);
3609 *hi
= gen_rtx_REG (SImode
, REGNO (reg
));
3612 /* Return true if OP contains a symbol reference */
3615 symbolic_reference_mentioned_p (rtx op
)
3620 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
3623 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
3624 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
3630 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
3631 if (symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
3635 else if (fmt
[i
] == 'e' && symbolic_reference_mentioned_p (XEXP (op
, i
)))
3642 /* Return true if OP contains a reference to a thread-local symbol. */
3645 tls_symbolic_reference_mentioned_p (rtx op
)
3650 if (GET_CODE (op
) == SYMBOL_REF
)
3651 return tls_symbolic_operand (op
);
3653 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
3654 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
3660 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
3661 if (tls_symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
3665 else if (fmt
[i
] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op
, i
)))
3673 /* Return true if OP is a legitimate general operand when
3674 generating PIC code. It is given that flag_pic is on
3675 and that OP satisfies CONSTANT_P. */
3678 legitimate_pic_operand_p (rtx op
)
3680 /* Accept all non-symbolic constants. */
3681 if (!SYMBOLIC_CONST (op
))
3684 /* Reject everything else; must be handled
3685 via emit_symbolic_move. */
3689 /* Returns true if the constant value OP is a legitimate general operand.
3690 It is given that OP satisfies CONSTANT_P. */
3693 s390_legitimate_constant_p (machine_mode mode
, rtx op
)
3695 if (TARGET_VX
&& VECTOR_MODE_P (mode
) && GET_CODE (op
) == CONST_VECTOR
)
3697 if (GET_MODE_SIZE (mode
) != 16)
3700 if (!satisfies_constraint_j00 (op
)
3701 && !satisfies_constraint_jm1 (op
)
3702 && !satisfies_constraint_jKK (op
)
3703 && !satisfies_constraint_jxx (op
)
3704 && !satisfies_constraint_jyy (op
))
3708 /* Accept all non-symbolic constants. */
3709 if (!SYMBOLIC_CONST (op
))
3712 /* Accept immediate LARL operands. */
3713 if (TARGET_CPU_ZARCH
&& larl_operand (op
, mode
))
3716 /* Thread-local symbols are never legal constants. This is
3717 so that emit_call knows that computing such addresses
3718 might require a function call. */
3719 if (TLS_SYMBOLIC_CONST (op
))
3722 /* In the PIC case, symbolic constants must *not* be
3723 forced into the literal pool. We accept them here,
3724 so that they will be handled by emit_symbolic_move. */
3728 /* All remaining non-PIC symbolic constants are
3729 forced into the literal pool. */
3733 /* Determine if it's legal to put X into the constant pool. This
3734 is not possible if X contains the address of a symbol that is
3735 not constant (TLS) or not known at final link time (PIC). */
3738 s390_cannot_force_const_mem (machine_mode mode
, rtx x
)
3740 switch (GET_CODE (x
))
3744 case CONST_WIDE_INT
:
3746 /* Accept all non-symbolic constants. */
3750 /* Labels are OK iff we are non-PIC. */
3751 return flag_pic
!= 0;
3754 /* 'Naked' TLS symbol references are never OK,
3755 non-TLS symbols are OK iff we are non-PIC. */
3756 if (tls_symbolic_operand (x
))
3759 return flag_pic
!= 0;
3762 return s390_cannot_force_const_mem (mode
, XEXP (x
, 0));
3765 return s390_cannot_force_const_mem (mode
, XEXP (x
, 0))
3766 || s390_cannot_force_const_mem (mode
, XEXP (x
, 1));
3769 switch (XINT (x
, 1))
3771 /* Only lt-relative or GOT-relative UNSPECs are OK. */
3772 case UNSPEC_LTREL_OFFSET
:
3780 case UNSPEC_GOTNTPOFF
:
3781 case UNSPEC_INDNTPOFF
:
3784 /* If the literal pool shares the code section, be put
3785 execute template placeholders into the pool as well. */
3787 return TARGET_CPU_ZARCH
;
3799 /* Returns true if the constant value OP is a legitimate general
3800 operand during and after reload. The difference to
3801 legitimate_constant_p is that this function will not accept
3802 a constant that would need to be forced to the literal pool
3803 before it can be used as operand.
3804 This function accepts all constants which can be loaded directly
3808 legitimate_reload_constant_p (rtx op
)
3810 /* Accept la(y) operands. */
3811 if (GET_CODE (op
) == CONST_INT
3812 && DISP_IN_RANGE (INTVAL (op
)))
3815 /* Accept l(g)hi/l(g)fi operands. */
3816 if (GET_CODE (op
) == CONST_INT
3817 && (CONST_OK_FOR_K (INTVAL (op
)) || CONST_OK_FOR_Os (INTVAL (op
))))
3820 /* Accept lliXX operands. */
3822 && GET_CODE (op
) == CONST_INT
3823 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
3824 && s390_single_part (op
, word_mode
, HImode
, 0) >= 0)
3828 && GET_CODE (op
) == CONST_INT
3829 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
3830 && s390_single_part (op
, word_mode
, SImode
, 0) >= 0)
3833 /* Accept larl operands. */
3834 if (TARGET_CPU_ZARCH
3835 && larl_operand (op
, VOIDmode
))
3838 /* Accept floating-point zero operands that fit into a single GPR. */
3839 if (GET_CODE (op
) == CONST_DOUBLE
3840 && s390_float_const_zero_p (op
)
3841 && GET_MODE_SIZE (GET_MODE (op
)) <= UNITS_PER_WORD
)
3844 /* Accept double-word operands that can be split. */
3845 if (GET_CODE (op
) == CONST_WIDE_INT
3846 || (GET_CODE (op
) == CONST_INT
3847 && trunc_int_for_mode (INTVAL (op
), word_mode
) != INTVAL (op
)))
3849 machine_mode dword_mode
= word_mode
== SImode
? DImode
: TImode
;
3850 rtx hi
= operand_subword (op
, 0, 0, dword_mode
);
3851 rtx lo
= operand_subword (op
, 1, 0, dword_mode
);
3852 return legitimate_reload_constant_p (hi
)
3853 && legitimate_reload_constant_p (lo
);
3856 /* Everything else cannot be handled without reload. */
3860 /* Returns true if the constant value OP is a legitimate fp operand
3861 during and after reload.
3862 This function accepts all constants which can be loaded directly
3866 legitimate_reload_fp_constant_p (rtx op
)
3868 /* Accept floating-point zero operands if the load zero instruction
3869 can be used. Prior to z196 the load fp zero instruction caused a
3870 performance penalty if the result is used as BFP number. */
3872 && GET_CODE (op
) == CONST_DOUBLE
3873 && s390_float_const_zero_p (op
))
3879 /* Returns true if the constant value OP is a legitimate vector operand
3880 during and after reload.
3881 This function accepts all constants which can be loaded directly
3885 legitimate_reload_vector_constant_p (rtx op
)
3887 if (TARGET_VX
&& GET_MODE_SIZE (GET_MODE (op
)) == 16
3888 && (satisfies_constraint_j00 (op
)
3889 || satisfies_constraint_jm1 (op
)
3890 || satisfies_constraint_jKK (op
)
3891 || satisfies_constraint_jxx (op
)
3892 || satisfies_constraint_jyy (op
)))
3898 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
3899 return the class of reg to actually use. */
3902 s390_preferred_reload_class (rtx op
, reg_class_t rclass
)
3904 switch (GET_CODE (op
))
3906 /* Constants we cannot reload into general registers
3907 must be forced into the literal pool. */
3911 case CONST_WIDE_INT
:
3912 if (reg_class_subset_p (GENERAL_REGS
, rclass
)
3913 && legitimate_reload_constant_p (op
))
3914 return GENERAL_REGS
;
3915 else if (reg_class_subset_p (ADDR_REGS
, rclass
)
3916 && legitimate_reload_constant_p (op
))
3918 else if (reg_class_subset_p (FP_REGS
, rclass
)
3919 && legitimate_reload_fp_constant_p (op
))
3921 else if (reg_class_subset_p (VEC_REGS
, rclass
)
3922 && legitimate_reload_vector_constant_p (op
))
3927 /* If a symbolic constant or a PLUS is reloaded,
3928 it is most likely being used as an address, so
3929 prefer ADDR_REGS. If 'class' is not a superset
3930 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
3932 /* Symrefs cannot be pushed into the literal pool with -fPIC
3933 so we *MUST NOT* return NO_REGS for these cases
3934 (s390_cannot_force_const_mem will return true).
3936 On the other hand we MUST return NO_REGS for symrefs with
3937 invalid addend which might have been pushed to the literal
3938 pool (no -fPIC). Usually we would expect them to be
3939 handled via secondary reload but this does not happen if
3940 they are used as literal pool slot replacement in reload
3941 inheritance (see emit_input_reload_insns). */
3942 if (TARGET_CPU_ZARCH
3943 && GET_CODE (XEXP (op
, 0)) == PLUS
3944 && GET_CODE (XEXP (XEXP(op
, 0), 0)) == SYMBOL_REF
3945 && GET_CODE (XEXP (XEXP(op
, 0), 1)) == CONST_INT
)
3947 if (flag_pic
&& reg_class_subset_p (ADDR_REGS
, rclass
))
3955 if (!legitimate_reload_constant_p (op
))
3959 /* load address will be used. */
3960 if (reg_class_subset_p (ADDR_REGS
, rclass
))
3972 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
3973 multiple of ALIGNMENT and the SYMBOL_REF being naturally
3977 s390_check_symref_alignment (rtx addr
, HOST_WIDE_INT alignment
)
3979 HOST_WIDE_INT addend
;
3982 /* The "required alignment" might be 0 (e.g. for certain structs
3983 accessed via BLKmode). Early abort in this case, as well as when
3984 an alignment > 8 is required. */
3985 if (alignment
< 2 || alignment
> 8)
3988 if (!s390_loadrelative_operand_p (addr
, &symref
, &addend
))
3991 if (addend
& (alignment
- 1))
3994 if (GET_CODE (symref
) == SYMBOL_REF
)
3996 /* We have load-relative instructions for 2-byte, 4-byte, and
3997 8-byte alignment so allow only these. */
4000 case 8: return !SYMBOL_FLAG_NOTALIGN8_P (symref
);
4001 case 4: return !SYMBOL_FLAG_NOTALIGN4_P (symref
);
4002 case 2: return !SYMBOL_FLAG_NOTALIGN2_P (symref
);
4003 default: return false;
4007 if (GET_CODE (symref
) == UNSPEC
4008 && alignment
<= UNITS_PER_LONG
)
4014 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
4015 operand SCRATCH is used to reload the even part of the address and
4019 s390_reload_larl_operand (rtx reg
, rtx addr
, rtx scratch
)
4021 HOST_WIDE_INT addend
;
4024 if (!s390_loadrelative_operand_p (addr
, &symref
, &addend
))
4028 /* Easy case. The addend is even so larl will do fine. */
4029 emit_move_insn (reg
, addr
);
4032 /* We can leave the scratch register untouched if the target
4033 register is a valid base register. */
4034 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
4035 && REGNO_REG_CLASS (REGNO (reg
)) == ADDR_REGS
)
4038 gcc_assert (REGNO (scratch
) < FIRST_PSEUDO_REGISTER
);
4039 gcc_assert (REGNO_REG_CLASS (REGNO (scratch
)) == ADDR_REGS
);
4042 emit_move_insn (scratch
,
4043 gen_rtx_CONST (Pmode
,
4044 gen_rtx_PLUS (Pmode
, symref
,
4045 GEN_INT (addend
- 1))));
4047 emit_move_insn (scratch
, symref
);
4049 /* Increment the address using la in order to avoid clobbering cc. */
4050 s390_load_address (reg
, gen_rtx_PLUS (Pmode
, scratch
, const1_rtx
));
4054 /* Generate what is necessary to move between REG and MEM using
4055 SCRATCH. The direction is given by TOMEM. */
4058 s390_reload_symref_address (rtx reg
, rtx mem
, rtx scratch
, bool tomem
)
4060 /* Reload might have pulled a constant out of the literal pool.
4061 Force it back in. */
4062 if (CONST_INT_P (mem
) || GET_CODE (mem
) == CONST_DOUBLE
4063 || GET_CODE (mem
) == CONST_WIDE_INT
4064 || GET_CODE (mem
) == CONST_VECTOR
4065 || GET_CODE (mem
) == CONST
)
4066 mem
= force_const_mem (GET_MODE (reg
), mem
);
4068 gcc_assert (MEM_P (mem
));
4070 /* For a load from memory we can leave the scratch register
4071 untouched if the target register is a valid base register. */
4073 && REGNO (reg
) < FIRST_PSEUDO_REGISTER
4074 && REGNO_REG_CLASS (REGNO (reg
)) == ADDR_REGS
4075 && GET_MODE (reg
) == GET_MODE (scratch
))
4078 /* Load address into scratch register. Since we can't have a
4079 secondary reload for a secondary reload we have to cover the case
4080 where larl would need a secondary reload here as well. */
4081 s390_reload_larl_operand (scratch
, XEXP (mem
, 0), scratch
);
4083 /* Now we can use a standard load/store to do the move. */
4085 emit_move_insn (replace_equiv_address (mem
, scratch
), reg
);
4087 emit_move_insn (reg
, replace_equiv_address (mem
, scratch
));
4090 /* Inform reload about cases where moving X with a mode MODE to a register in
4091 RCLASS requires an extra scratch or immediate register. Return the class
4092 needed for the immediate register. */
4095 s390_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
4096 machine_mode mode
, secondary_reload_info
*sri
)
4098 enum reg_class rclass
= (enum reg_class
) rclass_i
;
4100 /* Intermediate register needed. */
4101 if (reg_classes_intersect_p (CC_REGS
, rclass
))
4102 return GENERAL_REGS
;
4106 /* The vst/vl vector move instructions allow only for short
4109 && GET_CODE (XEXP (x
, 0)) == PLUS
4110 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4111 && !SHORT_DISP_IN_RANGE(INTVAL (XEXP (XEXP (x
, 0), 1)))
4112 && reg_class_subset_p (rclass
, VEC_REGS
)
4113 && (!reg_class_subset_p (rclass
, FP_REGS
)
4114 || (GET_MODE_SIZE (mode
) > 8
4115 && s390_class_max_nregs (FP_REGS
, mode
) == 1)))
4118 sri
->icode
= (TARGET_64BIT
?
4119 CODE_FOR_reloaddi_la_in
:
4120 CODE_FOR_reloadsi_la_in
);
4122 sri
->icode
= (TARGET_64BIT
?
4123 CODE_FOR_reloaddi_la_out
:
4124 CODE_FOR_reloadsi_la_out
);
4130 HOST_WIDE_INT offset
;
4133 /* On z10 several optimizer steps may generate larl operands with
4136 && s390_loadrelative_operand_p (x
, &symref
, &offset
)
4138 && !SYMBOL_FLAG_NOTALIGN2_P (symref
)
4139 && (offset
& 1) == 1)
4140 sri
->icode
= ((mode
== DImode
) ? CODE_FOR_reloaddi_larl_odd_addend_z10
4141 : CODE_FOR_reloadsi_larl_odd_addend_z10
);
4143 /* Handle all the (mem (symref)) accesses we cannot use the z10
4144 instructions for. */
4146 && s390_loadrelative_operand_p (XEXP (x
, 0), NULL
, NULL
)
4148 || !reg_class_subset_p (rclass
, GENERAL_REGS
)
4149 || GET_MODE_SIZE (mode
) > UNITS_PER_WORD
4150 || !s390_check_symref_alignment (XEXP (x
, 0),
4151 GET_MODE_SIZE (mode
))))
4153 #define __SECONDARY_RELOAD_CASE(M,m) \
4156 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
4157 CODE_FOR_reload##m##di_tomem_z10; \
4159 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
4160 CODE_FOR_reload##m##si_tomem_z10; \
4163 switch (GET_MODE (x
))
4165 __SECONDARY_RELOAD_CASE (QI
, qi
);
4166 __SECONDARY_RELOAD_CASE (HI
, hi
);
4167 __SECONDARY_RELOAD_CASE (SI
, si
);
4168 __SECONDARY_RELOAD_CASE (DI
, di
);
4169 __SECONDARY_RELOAD_CASE (TI
, ti
);
4170 __SECONDARY_RELOAD_CASE (SF
, sf
);
4171 __SECONDARY_RELOAD_CASE (DF
, df
);
4172 __SECONDARY_RELOAD_CASE (TF
, tf
);
4173 __SECONDARY_RELOAD_CASE (SD
, sd
);
4174 __SECONDARY_RELOAD_CASE (DD
, dd
);
4175 __SECONDARY_RELOAD_CASE (TD
, td
);
4176 __SECONDARY_RELOAD_CASE (V1QI
, v1qi
);
4177 __SECONDARY_RELOAD_CASE (V2QI
, v2qi
);
4178 __SECONDARY_RELOAD_CASE (V4QI
, v4qi
);
4179 __SECONDARY_RELOAD_CASE (V8QI
, v8qi
);
4180 __SECONDARY_RELOAD_CASE (V16QI
, v16qi
);
4181 __SECONDARY_RELOAD_CASE (V1HI
, v1hi
);
4182 __SECONDARY_RELOAD_CASE (V2HI
, v2hi
);
4183 __SECONDARY_RELOAD_CASE (V4HI
, v4hi
);
4184 __SECONDARY_RELOAD_CASE (V8HI
, v8hi
);
4185 __SECONDARY_RELOAD_CASE (V1SI
, v1si
);
4186 __SECONDARY_RELOAD_CASE (V2SI
, v2si
);
4187 __SECONDARY_RELOAD_CASE (V4SI
, v4si
);
4188 __SECONDARY_RELOAD_CASE (V1DI
, v1di
);
4189 __SECONDARY_RELOAD_CASE (V2DI
, v2di
);
4190 __SECONDARY_RELOAD_CASE (V1TI
, v1ti
);
4191 __SECONDARY_RELOAD_CASE (V1SF
, v1sf
);
4192 __SECONDARY_RELOAD_CASE (V2SF
, v2sf
);
4193 __SECONDARY_RELOAD_CASE (V4SF
, v4sf
);
4194 __SECONDARY_RELOAD_CASE (V1DF
, v1df
);
4195 __SECONDARY_RELOAD_CASE (V2DF
, v2df
);
4196 __SECONDARY_RELOAD_CASE (V1TF
, v1tf
);
4200 #undef __SECONDARY_RELOAD_CASE
4204 /* We need a scratch register when loading a PLUS expression which
4205 is not a legitimate operand of the LOAD ADDRESS instruction. */
4206 /* LRA can deal with transformation of plus op very well -- so we
4207 don't need to prompt LRA in this case. */
4208 if (! lra_in_progress
&& in_p
&& s390_plus_operand (x
, mode
))
4209 sri
->icode
= (TARGET_64BIT
?
4210 CODE_FOR_reloaddi_plus
: CODE_FOR_reloadsi_plus
);
4212 /* Performing a multiword move from or to memory we have to make sure the
4213 second chunk in memory is addressable without causing a displacement
4214 overflow. If that would be the case we calculate the address in
4215 a scratch register. */
4217 && GET_CODE (XEXP (x
, 0)) == PLUS
4218 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4219 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x
, 0), 1))
4220 + GET_MODE_SIZE (mode
) - 1))
4222 /* For GENERAL_REGS a displacement overflow is no problem if occurring
4223 in a s_operand address since we may fallback to lm/stm. So we only
4224 have to care about overflows in the b+i+d case. */
4225 if ((reg_classes_intersect_p (GENERAL_REGS
, rclass
)
4226 && s390_class_max_nregs (GENERAL_REGS
, mode
) > 1
4227 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
4228 /* For FP_REGS no lm/stm is available so this check is triggered
4229 for displacement overflows in b+i+d and b+d like addresses. */
4230 || (reg_classes_intersect_p (FP_REGS
, rclass
)
4231 && s390_class_max_nregs (FP_REGS
, mode
) > 1))
4234 sri
->icode
= (TARGET_64BIT
?
4235 CODE_FOR_reloaddi_la_in
:
4236 CODE_FOR_reloadsi_la_in
);
4238 sri
->icode
= (TARGET_64BIT
?
4239 CODE_FOR_reloaddi_la_out
:
4240 CODE_FOR_reloadsi_la_out
);
4244 /* A scratch address register is needed when a symbolic constant is
4245 copied to r0 compiling with -fPIC. In other cases the target
4246 register might be used as temporary (see legitimize_pic_address). */
4247 if (in_p
&& SYMBOLIC_CONST (x
) && flag_pic
== 2 && rclass
!= ADDR_REGS
)
4248 sri
->icode
= (TARGET_64BIT
?
4249 CODE_FOR_reloaddi_PIC_addr
:
4250 CODE_FOR_reloadsi_PIC_addr
);
4252 /* Either scratch or no register needed. */
4256 /* Generate code to load SRC, which is PLUS that is not a
4257 legitimate operand for the LA instruction, into TARGET.
4258 SCRATCH may be used as scratch register. */
4261 s390_expand_plus_operand (rtx target
, rtx src
,
4265 struct s390_address ad
;
4267 /* src must be a PLUS; get its two operands. */
4268 gcc_assert (GET_CODE (src
) == PLUS
);
4269 gcc_assert (GET_MODE (src
) == Pmode
);
4271 /* Check if any of the two operands is already scheduled
4272 for replacement by reload. This can happen e.g. when
4273 float registers occur in an address. */
4274 sum1
= find_replacement (&XEXP (src
, 0));
4275 sum2
= find_replacement (&XEXP (src
, 1));
4276 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
4278 /* If the address is already strictly valid, there's nothing to do. */
4279 if (!s390_decompose_address (src
, &ad
)
4280 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
4281 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
4283 /* Otherwise, one of the operands cannot be an address register;
4284 we reload its value into the scratch register. */
4285 if (true_regnum (sum1
) < 1 || true_regnum (sum1
) > 15)
4287 emit_move_insn (scratch
, sum1
);
4290 if (true_regnum (sum2
) < 1 || true_regnum (sum2
) > 15)
4292 emit_move_insn (scratch
, sum2
);
4296 /* According to the way these invalid addresses are generated
4297 in reload.c, it should never happen (at least on s390) that
4298 *neither* of the PLUS components, after find_replacements
4299 was applied, is an address register. */
4300 if (sum1
== scratch
&& sum2
== scratch
)
4306 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
4309 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
4310 is only ever performed on addresses, so we can mark the
4311 sum as legitimate for LA in any case. */
4312 s390_load_address (target
, src
);
4316 /* Return true if ADDR is a valid memory address.
4317 STRICT specifies whether strict register checking applies. */
4320 s390_legitimate_address_p (machine_mode mode
, rtx addr
, bool strict
)
4322 struct s390_address ad
;
4325 && larl_operand (addr
, VOIDmode
)
4326 && (mode
== VOIDmode
4327 || s390_check_symref_alignment (addr
, GET_MODE_SIZE (mode
))))
4330 if (!s390_decompose_address (addr
, &ad
))
4335 if (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
4338 if (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
)))
4344 && !(REGNO (ad
.base
) >= FIRST_PSEUDO_REGISTER
4345 || REGNO_REG_CLASS (REGNO (ad
.base
)) == ADDR_REGS
))
4349 && !(REGNO (ad
.indx
) >= FIRST_PSEUDO_REGISTER
4350 || REGNO_REG_CLASS (REGNO (ad
.indx
)) == ADDR_REGS
))
4356 /* Return true if OP is a valid operand for the LA instruction.
4357 In 31-bit, we need to prove that the result is used as an
4358 address, as LA performs only a 31-bit addition. */
4361 legitimate_la_operand_p (rtx op
)
4363 struct s390_address addr
;
4364 if (!s390_decompose_address (op
, &addr
))
4367 return (TARGET_64BIT
|| addr
.pointer
);
4370 /* Return true if it is valid *and* preferable to use LA to
4371 compute the sum of OP1 and OP2. */
4374 preferred_la_operand_p (rtx op1
, rtx op2
)
4376 struct s390_address addr
;
4378 if (op2
!= const0_rtx
)
4379 op1
= gen_rtx_PLUS (Pmode
, op1
, op2
);
4381 if (!s390_decompose_address (op1
, &addr
))
4383 if (addr
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (addr
.base
)))
4385 if (addr
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (addr
.indx
)))
4388 /* Avoid LA instructions with index register on z196; it is
4389 preferable to use regular add instructions when possible.
4390 Starting with zEC12 the la with index register is "uncracked"
4392 if (addr
.indx
&& s390_tune
== PROCESSOR_2817_Z196
)
4395 if (!TARGET_64BIT
&& !addr
.pointer
)
4401 if ((addr
.base
&& REG_P (addr
.base
) && REG_POINTER (addr
.base
))
4402 || (addr
.indx
&& REG_P (addr
.indx
) && REG_POINTER (addr
.indx
)))
4408 /* Emit a forced load-address operation to load SRC into DST.
4409 This will use the LOAD ADDRESS instruction even in situations
4410 where legitimate_la_operand_p (SRC) returns false. */
4413 s390_load_address (rtx dst
, rtx src
)
4416 emit_move_insn (dst
, src
);
4418 emit_insn (gen_force_la_31 (dst
, src
));
4421 /* Return a legitimate reference for ORIG (an address) using the
4422 register REG. If REG is 0, a new pseudo is generated.
4424 There are two types of references that must be handled:
4426 1. Global data references must load the address from the GOT, via
4427 the PIC reg. An insn is emitted to do this load, and the reg is
4430 2. Static data references, constant pool addresses, and code labels
4431 compute the address as an offset from the GOT, whose base is in
4432 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
4433 differentiate them from global data objects. The returned
4434 address is the PIC reg + an unspec constant.
4436 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
4437 reg also appears in the address. */
4440 legitimize_pic_address (rtx orig
, rtx reg
)
4443 rtx addend
= const0_rtx
;
4446 gcc_assert (!TLS_SYMBOLIC_CONST (addr
));
4448 if (GET_CODE (addr
) == CONST
)
4449 addr
= XEXP (addr
, 0);
4451 if (GET_CODE (addr
) == PLUS
)
4453 addend
= XEXP (addr
, 1);
4454 addr
= XEXP (addr
, 0);
4457 if ((GET_CODE (addr
) == LABEL_REF
4458 || (GET_CODE (addr
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (addr
))
4459 || (GET_CODE (addr
) == UNSPEC
&&
4460 (XINT (addr
, 1) == UNSPEC_GOTENT
4461 || (TARGET_CPU_ZARCH
&& XINT (addr
, 1) == UNSPEC_PLT
))))
4462 && GET_CODE (addend
) == CONST_INT
)
4464 /* This can be locally addressed. */
4466 /* larl_operand requires UNSPECs to be wrapped in a const rtx. */
4467 rtx const_addr
= (GET_CODE (addr
) == UNSPEC
?
4468 gen_rtx_CONST (Pmode
, addr
) : addr
);
4470 if (TARGET_CPU_ZARCH
4471 && larl_operand (const_addr
, VOIDmode
)
4472 && INTVAL (addend
) < (HOST_WIDE_INT
)1 << 31
4473 && INTVAL (addend
) >= -((HOST_WIDE_INT
)1 << 31))
4475 if (INTVAL (addend
) & 1)
4477 /* LARL can't handle odd offsets, so emit a pair of LARL
4479 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
4481 if (!DISP_IN_RANGE (INTVAL (addend
)))
4483 HOST_WIDE_INT even
= INTVAL (addend
) - 1;
4484 addr
= gen_rtx_PLUS (Pmode
, addr
, GEN_INT (even
));
4485 addr
= gen_rtx_CONST (Pmode
, addr
);
4486 addend
= const1_rtx
;
4489 emit_move_insn (temp
, addr
);
4490 new_rtx
= gen_rtx_PLUS (Pmode
, temp
, addend
);
4494 s390_load_address (reg
, new_rtx
);
4500 /* If the offset is even, we can just use LARL. This
4501 will happen automatically. */
4506 /* No larl - Access local symbols relative to the GOT. */
4508 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
4510 if (reload_in_progress
|| reload_completed
)
4511 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
4513 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTOFF
);
4514 if (addend
!= const0_rtx
)
4515 addr
= gen_rtx_PLUS (Pmode
, addr
, addend
);
4516 addr
= gen_rtx_CONST (Pmode
, addr
);
4517 addr
= force_const_mem (Pmode
, addr
);
4518 emit_move_insn (temp
, addr
);
4520 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
4523 s390_load_address (reg
, new_rtx
);
4528 else if (GET_CODE (addr
) == SYMBOL_REF
&& addend
== const0_rtx
)
4530 /* A non-local symbol reference without addend.
4532 The symbol ref is wrapped into an UNSPEC to make sure the
4533 proper operand modifier (@GOT or @GOTENT) will be emitted.
4534 This will tell the linker to put the symbol into the GOT.
4536 Additionally the code dereferencing the GOT slot is emitted here.
4538 An addend to the symref needs to be added afterwards.
4539 legitimize_pic_address calls itself recursively to handle
4540 that case. So no need to do it here. */
4543 reg
= gen_reg_rtx (Pmode
);
4547 /* Use load relative if possible.
4548 lgrl <target>, sym@GOTENT */
4549 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTENT
);
4550 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
4551 new_rtx
= gen_const_mem (GET_MODE (reg
), new_rtx
);
4553 emit_move_insn (reg
, new_rtx
);
4556 else if (flag_pic
== 1)
4558 /* Assume GOT offset is a valid displacement operand (< 4k
4559 or < 512k with z990). This is handled the same way in
4560 both 31- and 64-bit code (@GOT).
4561 lg <target>, sym@GOT(r12) */
4563 if (reload_in_progress
|| reload_completed
)
4564 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
4566 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
4567 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
4568 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new_rtx
);
4569 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
4570 emit_move_insn (reg
, new_rtx
);
4573 else if (TARGET_CPU_ZARCH
)
4575 /* If the GOT offset might be >= 4k, we determine the position
4576 of the GOT entry via a PC-relative LARL (@GOTENT).
4577 larl temp, sym@GOTENT
4578 lg <target>, 0(temp) */
4580 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
4582 gcc_assert (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
4583 || REGNO_REG_CLASS (REGNO (temp
)) == ADDR_REGS
);
4585 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTENT
);
4586 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
4587 emit_move_insn (temp
, new_rtx
);
4589 new_rtx
= gen_const_mem (Pmode
, temp
);
4590 emit_move_insn (reg
, new_rtx
);
4596 /* If the GOT offset might be >= 4k, we have to load it
4597 from the literal pool (@GOT).
4599 lg temp, lit-litbase(r13)
4600 lg <target>, 0(temp)
4601 lit: .long sym@GOT */
4603 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
4605 gcc_assert (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
4606 || REGNO_REG_CLASS (REGNO (temp
)) == ADDR_REGS
);
4608 if (reload_in_progress
|| reload_completed
)
4609 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
4611 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
4612 addr
= gen_rtx_CONST (Pmode
, addr
);
4613 addr
= force_const_mem (Pmode
, addr
);
4614 emit_move_insn (temp
, addr
);
4616 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
4617 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
4618 emit_move_insn (reg
, new_rtx
);
4622 else if (GET_CODE (addr
) == UNSPEC
&& GET_CODE (addend
) == CONST_INT
)
4624 gcc_assert (XVECLEN (addr
, 0) == 1);
4625 switch (XINT (addr
, 1))
4627 /* These address symbols (or PLT slots) relative to the GOT
4628 (not GOT slots!). In general this will exceed the
4629 displacement range so these value belong into the literal
4633 new_rtx
= force_const_mem (Pmode
, orig
);
4636 /* For -fPIC the GOT size might exceed the displacement
4637 range so make sure the value is in the literal pool. */
4640 new_rtx
= force_const_mem (Pmode
, orig
);
4643 /* For @GOTENT larl is used. This is handled like local
4649 /* @PLT is OK as is on 64-bit, must be converted to
4650 GOT-relative @PLTOFF on 31-bit. */
4652 if (!TARGET_CPU_ZARCH
)
4654 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
4656 if (reload_in_progress
|| reload_completed
)
4657 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
4659 addr
= XVECEXP (addr
, 0, 0);
4660 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
),
4662 if (addend
!= const0_rtx
)
4663 addr
= gen_rtx_PLUS (Pmode
, addr
, addend
);
4664 addr
= gen_rtx_CONST (Pmode
, addr
);
4665 addr
= force_const_mem (Pmode
, addr
);
4666 emit_move_insn (temp
, addr
);
4668 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
4671 s390_load_address (reg
, new_rtx
);
4676 /* On 64 bit larl can be used. This case is handled like
4677 local symbol refs. */
4681 /* Everything else cannot happen. */
4686 else if (addend
!= const0_rtx
)
4688 /* Otherwise, compute the sum. */
4690 rtx base
= legitimize_pic_address (addr
, reg
);
4691 new_rtx
= legitimize_pic_address (addend
,
4692 base
== reg
? NULL_RTX
: reg
);
4693 if (GET_CODE (new_rtx
) == CONST_INT
)
4694 new_rtx
= plus_constant (Pmode
, base
, INTVAL (new_rtx
));
4697 if (GET_CODE (new_rtx
) == PLUS
&& CONSTANT_P (XEXP (new_rtx
, 1)))
4699 base
= gen_rtx_PLUS (Pmode
, base
, XEXP (new_rtx
, 0));
4700 new_rtx
= XEXP (new_rtx
, 1);
4702 new_rtx
= gen_rtx_PLUS (Pmode
, base
, new_rtx
);
4705 if (GET_CODE (new_rtx
) == CONST
)
4706 new_rtx
= XEXP (new_rtx
, 0);
4707 new_rtx
= force_operand (new_rtx
, 0);
4713 /* Load the thread pointer into a register. */
4716 s390_get_thread_pointer (void)
4718 rtx tp
= gen_reg_rtx (Pmode
);
4720 emit_move_insn (tp
, gen_rtx_REG (Pmode
, TP_REGNUM
));
4721 mark_reg_pointer (tp
, BITS_PER_WORD
);
4726 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
4727 in s390_tls_symbol which always refers to __tls_get_offset.
4728 The returned offset is written to RESULT_REG and an USE rtx is
4729 generated for TLS_CALL. */
4731 static GTY(()) rtx s390_tls_symbol
;
4734 s390_emit_tls_call_insn (rtx result_reg
, rtx tls_call
)
4739 emit_insn (s390_load_got ());
4741 if (!s390_tls_symbol
)
4742 s390_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_offset");
4744 insn
= s390_emit_call (s390_tls_symbol
, tls_call
, result_reg
,
4745 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
4747 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), result_reg
);
4748 RTL_CONST_CALL_P (insn
) = 1;
4751 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
4752 this (thread-local) address. REG may be used as temporary. */
4755 legitimize_tls_address (rtx addr
, rtx reg
)
4757 rtx new_rtx
, tls_call
, temp
, base
, r2
, insn
;
4759 if (GET_CODE (addr
) == SYMBOL_REF
)
4760 switch (tls_symbolic_operand (addr
))
4762 case TLS_MODEL_GLOBAL_DYNAMIC
:
4764 r2
= gen_rtx_REG (Pmode
, 2);
4765 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_TLSGD
);
4766 new_rtx
= gen_rtx_CONST (Pmode
, tls_call
);
4767 new_rtx
= force_const_mem (Pmode
, new_rtx
);
4768 emit_move_insn (r2
, new_rtx
);
4769 s390_emit_tls_call_insn (r2
, tls_call
);
4770 insn
= get_insns ();
4773 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
4774 temp
= gen_reg_rtx (Pmode
);
4775 emit_libcall_block (insn
, temp
, r2
, new_rtx
);
4777 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
4780 s390_load_address (reg
, new_rtx
);
4785 case TLS_MODEL_LOCAL_DYNAMIC
:
4787 r2
= gen_rtx_REG (Pmode
, 2);
4788 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM
);
4789 new_rtx
= gen_rtx_CONST (Pmode
, tls_call
);
4790 new_rtx
= force_const_mem (Pmode
, new_rtx
);
4791 emit_move_insn (r2
, new_rtx
);
4792 s390_emit_tls_call_insn (r2
, tls_call
);
4793 insn
= get_insns ();
4796 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM_NTPOFF
);
4797 temp
= gen_reg_rtx (Pmode
);
4798 emit_libcall_block (insn
, temp
, r2
, new_rtx
);
4800 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
4801 base
= gen_reg_rtx (Pmode
);
4802 s390_load_address (base
, new_rtx
);
4804 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_DTPOFF
);
4805 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
4806 new_rtx
= force_const_mem (Pmode
, new_rtx
);
4807 temp
= gen_reg_rtx (Pmode
);
4808 emit_move_insn (temp
, new_rtx
);
4810 new_rtx
= gen_rtx_PLUS (Pmode
, base
, temp
);
4813 s390_load_address (reg
, new_rtx
);
4818 case TLS_MODEL_INITIAL_EXEC
:
4821 /* Assume GOT offset < 4k. This is handled the same way
4822 in both 31- and 64-bit code. */
4824 if (reload_in_progress
|| reload_completed
)
4825 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
4827 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
4828 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
4829 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new_rtx
);
4830 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
4831 temp
= gen_reg_rtx (Pmode
);
4832 emit_move_insn (temp
, new_rtx
);
4834 else if (TARGET_CPU_ZARCH
)
4836 /* If the GOT offset might be >= 4k, we determine the position
4837 of the GOT entry via a PC-relative LARL. */
4839 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
4840 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
4841 temp
= gen_reg_rtx (Pmode
);
4842 emit_move_insn (temp
, new_rtx
);
4844 new_rtx
= gen_const_mem (Pmode
, temp
);
4845 temp
= gen_reg_rtx (Pmode
);
4846 emit_move_insn (temp
, new_rtx
);
4850 /* If the GOT offset might be >= 4k, we have to load it
4851 from the literal pool. */
4853 if (reload_in_progress
|| reload_completed
)
4854 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
4856 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
4857 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
4858 new_rtx
= force_const_mem (Pmode
, new_rtx
);
4859 temp
= gen_reg_rtx (Pmode
);
4860 emit_move_insn (temp
, new_rtx
);
4862 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
4863 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
4865 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new_rtx
, addr
), UNSPEC_TLS_LOAD
);
4866 temp
= gen_reg_rtx (Pmode
);
4867 emit_insn (gen_rtx_SET (temp
, new_rtx
));
4871 /* In position-dependent code, load the absolute address of
4872 the GOT entry from the literal pool. */
4874 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
4875 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
4876 new_rtx
= force_const_mem (Pmode
, new_rtx
);
4877 temp
= gen_reg_rtx (Pmode
);
4878 emit_move_insn (temp
, new_rtx
);
4881 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
4882 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new_rtx
, addr
), UNSPEC_TLS_LOAD
);
4883 temp
= gen_reg_rtx (Pmode
);
4884 emit_insn (gen_rtx_SET (temp
, new_rtx
));
4887 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
4890 s390_load_address (reg
, new_rtx
);
4895 case TLS_MODEL_LOCAL_EXEC
:
4896 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
4897 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
4898 new_rtx
= force_const_mem (Pmode
, new_rtx
);
4899 temp
= gen_reg_rtx (Pmode
);
4900 emit_move_insn (temp
, new_rtx
);
4902 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
4905 s390_load_address (reg
, new_rtx
);
4914 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == UNSPEC
)
4916 switch (XINT (XEXP (addr
, 0), 1))
4918 case UNSPEC_INDNTPOFF
:
4919 gcc_assert (TARGET_CPU_ZARCH
);
4928 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == PLUS
4929 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST_INT
)
4931 new_rtx
= XEXP (XEXP (addr
, 0), 0);
4932 if (GET_CODE (new_rtx
) != SYMBOL_REF
)
4933 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
4935 new_rtx
= legitimize_tls_address (new_rtx
, reg
);
4936 new_rtx
= plus_constant (Pmode
, new_rtx
,
4937 INTVAL (XEXP (XEXP (addr
, 0), 1)));
4938 new_rtx
= force_operand (new_rtx
, 0);
4942 gcc_unreachable (); /* for now ... */
4947 /* Emit insns making the address in operands[1] valid for a standard
4948 move to operands[0]. operands[1] is replaced by an address which
4949 should be used instead of the former RTX to emit the move
4953 emit_symbolic_move (rtx
*operands
)
4955 rtx temp
= !can_create_pseudo_p () ? operands
[0] : gen_reg_rtx (Pmode
);
4957 if (GET_CODE (operands
[0]) == MEM
)
4958 operands
[1] = force_reg (Pmode
, operands
[1]);
4959 else if (TLS_SYMBOLIC_CONST (operands
[1]))
4960 operands
[1] = legitimize_tls_address (operands
[1], temp
);
4962 operands
[1] = legitimize_pic_address (operands
[1], temp
);
4965 /* Try machine-dependent ways of modifying an illegitimate address X
4966 to be legitimate. If we find one, return the new, valid address.
4968 OLDX is the address as it was before break_out_memory_refs was called.
4969 In some cases it is useful to look at this to decide what needs to be done.
4971 MODE is the mode of the operand pointed to by X.
4973 When -fpic is used, special handling is needed for symbolic references.
4974 See comments by legitimize_pic_address for details. */
4977 s390_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
4978 machine_mode mode ATTRIBUTE_UNUSED
)
4980 rtx constant_term
= const0_rtx
;
4982 if (TLS_SYMBOLIC_CONST (x
))
4984 x
= legitimize_tls_address (x
, 0);
4986 if (s390_legitimate_address_p (mode
, x
, FALSE
))
4989 else if (GET_CODE (x
) == PLUS
4990 && (TLS_SYMBOLIC_CONST (XEXP (x
, 0))
4991 || TLS_SYMBOLIC_CONST (XEXP (x
, 1))))
4997 if (SYMBOLIC_CONST (x
)
4998 || (GET_CODE (x
) == PLUS
4999 && (SYMBOLIC_CONST (XEXP (x
, 0))
5000 || SYMBOLIC_CONST (XEXP (x
, 1)))))
5001 x
= legitimize_pic_address (x
, 0);
5003 if (s390_legitimate_address_p (mode
, x
, FALSE
))
5007 x
= eliminate_constant_term (x
, &constant_term
);
5009 /* Optimize loading of large displacements by splitting them
5010 into the multiple of 4K and the rest; this allows the
5011 former to be CSE'd if possible.
5013 Don't do this if the displacement is added to a register
5014 pointing into the stack frame, as the offsets will
5015 change later anyway. */
5017 if (GET_CODE (constant_term
) == CONST_INT
5018 && !TARGET_LONG_DISPLACEMENT
5019 && !DISP_IN_RANGE (INTVAL (constant_term
))
5020 && !(REG_P (x
) && REGNO_PTR_FRAME_P (REGNO (x
))))
5022 HOST_WIDE_INT lower
= INTVAL (constant_term
) & 0xfff;
5023 HOST_WIDE_INT upper
= INTVAL (constant_term
) ^ lower
;
5025 rtx temp
= gen_reg_rtx (Pmode
);
5026 rtx val
= force_operand (GEN_INT (upper
), temp
);
5028 emit_move_insn (temp
, val
);
5030 x
= gen_rtx_PLUS (Pmode
, x
, temp
);
5031 constant_term
= GEN_INT (lower
);
5034 if (GET_CODE (x
) == PLUS
)
5036 if (GET_CODE (XEXP (x
, 0)) == REG
)
5038 rtx temp
= gen_reg_rtx (Pmode
);
5039 rtx val
= force_operand (XEXP (x
, 1), temp
);
5041 emit_move_insn (temp
, val
);
5043 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0), temp
);
5046 else if (GET_CODE (XEXP (x
, 1)) == REG
)
5048 rtx temp
= gen_reg_rtx (Pmode
);
5049 rtx val
= force_operand (XEXP (x
, 0), temp
);
5051 emit_move_insn (temp
, val
);
5053 x
= gen_rtx_PLUS (Pmode
, temp
, XEXP (x
, 1));
5057 if (constant_term
!= const0_rtx
)
5058 x
= gen_rtx_PLUS (Pmode
, x
, constant_term
);
5063 /* Try a machine-dependent way of reloading an illegitimate address AD
5064 operand. If we find one, push the reload and return the new address.
5066 MODE is the mode of the enclosing MEM. OPNUM is the operand number
5067 and TYPE is the reload type of the current reload. */
5070 legitimize_reload_address (rtx ad
, machine_mode mode ATTRIBUTE_UNUSED
,
5071 int opnum
, int type
)
5073 if (!optimize
|| TARGET_LONG_DISPLACEMENT
)
5076 if (GET_CODE (ad
) == PLUS
)
5078 rtx tem
= simplify_binary_operation (PLUS
, Pmode
,
5079 XEXP (ad
, 0), XEXP (ad
, 1));
5084 if (GET_CODE (ad
) == PLUS
5085 && GET_CODE (XEXP (ad
, 0)) == REG
5086 && GET_CODE (XEXP (ad
, 1)) == CONST_INT
5087 && !DISP_IN_RANGE (INTVAL (XEXP (ad
, 1))))
5089 HOST_WIDE_INT lower
= INTVAL (XEXP (ad
, 1)) & 0xfff;
5090 HOST_WIDE_INT upper
= INTVAL (XEXP (ad
, 1)) ^ lower
;
5091 rtx cst
, tem
, new_rtx
;
5093 cst
= GEN_INT (upper
);
5094 if (!legitimate_reload_constant_p (cst
))
5095 cst
= force_const_mem (Pmode
, cst
);
5097 tem
= gen_rtx_PLUS (Pmode
, XEXP (ad
, 0), cst
);
5098 new_rtx
= gen_rtx_PLUS (Pmode
, tem
, GEN_INT (lower
));
5100 push_reload (XEXP (tem
, 1), 0, &XEXP (tem
, 1), 0,
5101 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
5102 opnum
, (enum reload_type
) type
);
5109 /* Emit code to move LEN bytes from DST to SRC. */
5112 s390_expand_movmem (rtx dst
, rtx src
, rtx len
)
5114 /* When tuning for z10 or higher we rely on the Glibc functions to
5115 do the right thing. Only for constant lengths below 64k we will
5116 generate inline code. */
5117 if (s390_tune
>= PROCESSOR_2097_Z10
5118 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > (1<<16)))
5121 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
5123 if (INTVAL (len
) > 0)
5124 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (INTVAL (len
) - 1)));
5127 else if (TARGET_MVCLE
)
5129 emit_insn (gen_movmem_long (dst
, src
, convert_to_mode (Pmode
, len
, 1)));
5134 rtx dst_addr
, src_addr
, count
, blocks
, temp
;
5135 rtx_code_label
*loop_start_label
= gen_label_rtx ();
5136 rtx_code_label
*loop_end_label
= gen_label_rtx ();
5137 rtx_code_label
*end_label
= gen_label_rtx ();
5140 mode
= GET_MODE (len
);
5141 if (mode
== VOIDmode
)
5144 dst_addr
= gen_reg_rtx (Pmode
);
5145 src_addr
= gen_reg_rtx (Pmode
);
5146 count
= gen_reg_rtx (mode
);
5147 blocks
= gen_reg_rtx (mode
);
5149 convert_move (count
, len
, 1);
5150 emit_cmp_and_jump_insns (count
, const0_rtx
,
5151 EQ
, NULL_RTX
, mode
, 1, end_label
);
5153 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
5154 emit_move_insn (src_addr
, force_operand (XEXP (src
, 0), NULL_RTX
));
5155 dst
= change_address (dst
, VOIDmode
, dst_addr
);
5156 src
= change_address (src
, VOIDmode
, src_addr
);
5158 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
5161 emit_move_insn (count
, temp
);
5163 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
5166 emit_move_insn (blocks
, temp
);
5168 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
5169 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
5171 emit_label (loop_start_label
);
5174 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 768))
5178 /* Issue a read prefetch for the +3 cache line. */
5179 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, src_addr
, GEN_INT (768)),
5180 const0_rtx
, const0_rtx
);
5181 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
5182 emit_insn (prefetch
);
5184 /* Issue a write prefetch for the +3 cache line. */
5185 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (768)),
5186 const1_rtx
, const0_rtx
);
5187 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
5188 emit_insn (prefetch
);
5191 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (255)));
5192 s390_load_address (dst_addr
,
5193 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
5194 s390_load_address (src_addr
,
5195 gen_rtx_PLUS (Pmode
, src_addr
, GEN_INT (256)));
5197 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
5200 emit_move_insn (blocks
, temp
);
5202 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
5203 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
5205 emit_jump (loop_start_label
);
5206 emit_label (loop_end_label
);
5208 emit_insn (gen_movmem_short (dst
, src
,
5209 convert_to_mode (Pmode
, count
, 1)));
5210 emit_label (end_label
);
5215 /* Emit code to set LEN bytes at DST to VAL.
5216 Make use of clrmem if VAL is zero. */
5219 s390_expand_setmem (rtx dst
, rtx len
, rtx val
)
5221 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) == 0)
5224 gcc_assert (GET_CODE (val
) == CONST_INT
|| GET_MODE (val
) == QImode
);
5226 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) > 0 && INTVAL (len
) <= 257)
5228 if (val
== const0_rtx
&& INTVAL (len
) <= 256)
5229 emit_insn (gen_clrmem_short (dst
, GEN_INT (INTVAL (len
) - 1)));
5232 /* Initialize memory by storing the first byte. */
5233 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
5235 if (INTVAL (len
) > 1)
5237 /* Initiate 1 byte overlap move.
5238 The first byte of DST is propagated through DSTP1.
5239 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
5240 DST is set to size 1 so the rest of the memory location
5241 does not count as source operand. */
5242 rtx dstp1
= adjust_address (dst
, VOIDmode
, 1);
5243 set_mem_size (dst
, 1);
5245 emit_insn (gen_movmem_short (dstp1
, dst
,
5246 GEN_INT (INTVAL (len
) - 2)));
5251 else if (TARGET_MVCLE
)
5253 val
= force_not_mem (convert_modes (Pmode
, QImode
, val
, 1));
5255 emit_insn (gen_setmem_long_di (dst
, convert_to_mode (Pmode
, len
, 1),
5258 emit_insn (gen_setmem_long_si (dst
, convert_to_mode (Pmode
, len
, 1),
5264 rtx dst_addr
, count
, blocks
, temp
, dstp1
= NULL_RTX
;
5265 rtx_code_label
*loop_start_label
= gen_label_rtx ();
5266 rtx_code_label
*loop_end_label
= gen_label_rtx ();
5267 rtx_code_label
*end_label
= gen_label_rtx ();
5270 mode
= GET_MODE (len
);
5271 if (mode
== VOIDmode
)
5274 dst_addr
= gen_reg_rtx (Pmode
);
5275 count
= gen_reg_rtx (mode
);
5276 blocks
= gen_reg_rtx (mode
);
5278 convert_move (count
, len
, 1);
5279 emit_cmp_and_jump_insns (count
, const0_rtx
,
5280 EQ
, NULL_RTX
, mode
, 1, end_label
);
5282 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
5283 dst
= change_address (dst
, VOIDmode
, dst_addr
);
5285 if (val
== const0_rtx
)
5286 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
5290 dstp1
= adjust_address (dst
, VOIDmode
, 1);
5291 set_mem_size (dst
, 1);
5293 /* Initialize memory by storing the first byte. */
5294 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
5296 /* If count is 1 we are done. */
5297 emit_cmp_and_jump_insns (count
, const1_rtx
,
5298 EQ
, NULL_RTX
, mode
, 1, end_label
);
5300 temp
= expand_binop (mode
, add_optab
, count
, GEN_INT (-2), count
, 1,
5304 emit_move_insn (count
, temp
);
5306 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
5309 emit_move_insn (blocks
, temp
);
5311 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
5312 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
5314 emit_label (loop_start_label
);
5317 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 1024))
5319 /* Issue a write prefetch for the +4 cache line. */
5320 rtx prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, dst_addr
,
5322 const1_rtx
, const0_rtx
);
5323 emit_insn (prefetch
);
5324 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
5327 if (val
== const0_rtx
)
5328 emit_insn (gen_clrmem_short (dst
, GEN_INT (255)));
5330 emit_insn (gen_movmem_short (dstp1
, dst
, GEN_INT (255)));
5331 s390_load_address (dst_addr
,
5332 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
5334 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
5337 emit_move_insn (blocks
, temp
);
5339 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
5340 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
5342 emit_jump (loop_start_label
);
5343 emit_label (loop_end_label
);
5345 if (val
== const0_rtx
)
5346 emit_insn (gen_clrmem_short (dst
, convert_to_mode (Pmode
, count
, 1)));
5348 emit_insn (gen_movmem_short (dstp1
, dst
, convert_to_mode (Pmode
, count
, 1)));
5349 emit_label (end_label
);
5353 /* Emit code to compare LEN bytes at OP0 with those at OP1,
5354 and return the result in TARGET. */
5357 s390_expand_cmpmem (rtx target
, rtx op0
, rtx op1
, rtx len
)
5359 rtx ccreg
= gen_rtx_REG (CCUmode
, CC_REGNUM
);
5362 /* When tuning for z10 or higher we rely on the Glibc functions to
5363 do the right thing. Only for constant lengths below 64k we will
5364 generate inline code. */
5365 if (s390_tune
>= PROCESSOR_2097_Z10
5366 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > (1<<16)))
5369 /* As the result of CMPINT is inverted compared to what we need,
5370 we have to swap the operands. */
5371 tmp
= op0
; op0
= op1
; op1
= tmp
;
5373 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
5375 if (INTVAL (len
) > 0)
5377 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (INTVAL (len
) - 1)));
5378 emit_insn (gen_cmpint (target
, ccreg
));
5381 emit_move_insn (target
, const0_rtx
);
5383 else if (TARGET_MVCLE
)
5385 emit_insn (gen_cmpmem_long (op0
, op1
, convert_to_mode (Pmode
, len
, 1)));
5386 emit_insn (gen_cmpint (target
, ccreg
));
5390 rtx addr0
, addr1
, count
, blocks
, temp
;
5391 rtx_code_label
*loop_start_label
= gen_label_rtx ();
5392 rtx_code_label
*loop_end_label
= gen_label_rtx ();
5393 rtx_code_label
*end_label
= gen_label_rtx ();
5396 mode
= GET_MODE (len
);
5397 if (mode
== VOIDmode
)
5400 addr0
= gen_reg_rtx (Pmode
);
5401 addr1
= gen_reg_rtx (Pmode
);
5402 count
= gen_reg_rtx (mode
);
5403 blocks
= gen_reg_rtx (mode
);
5405 convert_move (count
, len
, 1);
5406 emit_cmp_and_jump_insns (count
, const0_rtx
,
5407 EQ
, NULL_RTX
, mode
, 1, end_label
);
5409 emit_move_insn (addr0
, force_operand (XEXP (op0
, 0), NULL_RTX
));
5410 emit_move_insn (addr1
, force_operand (XEXP (op1
, 0), NULL_RTX
));
5411 op0
= change_address (op0
, VOIDmode
, addr0
);
5412 op1
= change_address (op1
, VOIDmode
, addr1
);
5414 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
5417 emit_move_insn (count
, temp
);
5419 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
5422 emit_move_insn (blocks
, temp
);
5424 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
5425 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
5427 emit_label (loop_start_label
);
5430 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 512))
5434 /* Issue a read prefetch for the +2 cache line of operand 1. */
5435 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, addr0
, GEN_INT (512)),
5436 const0_rtx
, const0_rtx
);
5437 emit_insn (prefetch
);
5438 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
5440 /* Issue a read prefetch for the +2 cache line of operand 2. */
5441 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, addr1
, GEN_INT (512)),
5442 const0_rtx
, const0_rtx
);
5443 emit_insn (prefetch
);
5444 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
5447 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (255)));
5448 temp
= gen_rtx_NE (VOIDmode
, ccreg
, const0_rtx
);
5449 temp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, temp
,
5450 gen_rtx_LABEL_REF (VOIDmode
, end_label
), pc_rtx
);
5451 temp
= gen_rtx_SET (pc_rtx
, temp
);
5452 emit_jump_insn (temp
);
5454 s390_load_address (addr0
,
5455 gen_rtx_PLUS (Pmode
, addr0
, GEN_INT (256)));
5456 s390_load_address (addr1
,
5457 gen_rtx_PLUS (Pmode
, addr1
, GEN_INT (256)));
5459 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
5462 emit_move_insn (blocks
, temp
);
5464 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
5465 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
5467 emit_jump (loop_start_label
);
5468 emit_label (loop_end_label
);
5470 emit_insn (gen_cmpmem_short (op0
, op1
,
5471 convert_to_mode (Pmode
, count
, 1)));
5472 emit_label (end_label
);
5474 emit_insn (gen_cmpint (target
, ccreg
));
5479 /* Emit a conditional jump to LABEL for condition code mask MASK using
5480 comparsion operator COMPARISON. Return the emitted jump insn. */
5483 s390_emit_ccraw_jump (HOST_WIDE_INT mask
, enum rtx_code comparison
, rtx label
)
5487 gcc_assert (comparison
== EQ
|| comparison
== NE
);
5488 gcc_assert (mask
> 0 && mask
< 15);
5490 temp
= gen_rtx_fmt_ee (comparison
, VOIDmode
,
5491 gen_rtx_REG (CCRAWmode
, CC_REGNUM
), GEN_INT (mask
));
5492 temp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, temp
,
5493 gen_rtx_LABEL_REF (VOIDmode
, label
), pc_rtx
);
5494 temp
= gen_rtx_SET (pc_rtx
, temp
);
5495 return emit_jump_insn (temp
);
5498 /* Emit the instructions to implement strlen of STRING and store the
5499 result in TARGET. The string has the known ALIGNMENT. This
5500 version uses vector instructions and is therefore not appropriate
5501 for targets prior to z13. */
5504 s390_expand_vec_strlen (rtx target
, rtx string
, rtx alignment
)
5506 int very_unlikely
= REG_BR_PROB_BASE
/ 100 - 1;
5507 int very_likely
= REG_BR_PROB_BASE
- 1;
5508 rtx highest_index_to_load_reg
= gen_reg_rtx (Pmode
);
5509 rtx str_reg
= gen_reg_rtx (V16QImode
);
5510 rtx str_addr_base_reg
= gen_reg_rtx (Pmode
);
5511 rtx str_idx_reg
= gen_reg_rtx (Pmode
);
5512 rtx result_reg
= gen_reg_rtx (V16QImode
);
5513 rtx is_aligned_label
= gen_label_rtx ();
5514 rtx into_loop_label
= NULL_RTX
;
5515 rtx loop_start_label
= gen_label_rtx ();
5517 rtx len
= gen_reg_rtx (QImode
);
5520 s390_load_address (str_addr_base_reg
, XEXP (string
, 0));
5521 emit_move_insn (str_idx_reg
, const0_rtx
);
5523 if (INTVAL (alignment
) < 16)
5525 /* Check whether the address happens to be aligned properly so
5526 jump directly to the aligned loop. */
5527 emit_cmp_and_jump_insns (gen_rtx_AND (Pmode
,
5528 str_addr_base_reg
, GEN_INT (15)),
5529 const0_rtx
, EQ
, NULL_RTX
,
5530 Pmode
, 1, is_aligned_label
);
5532 temp
= gen_reg_rtx (Pmode
);
5533 temp
= expand_binop (Pmode
, and_optab
, str_addr_base_reg
,
5534 GEN_INT (15), temp
, 1, OPTAB_DIRECT
);
5535 gcc_assert (REG_P (temp
));
5536 highest_index_to_load_reg
=
5537 expand_binop (Pmode
, sub_optab
, GEN_INT (15), temp
,
5538 highest_index_to_load_reg
, 1, OPTAB_DIRECT
);
5539 gcc_assert (REG_P (highest_index_to_load_reg
));
5540 emit_insn (gen_vllv16qi (str_reg
,
5541 convert_to_mode (SImode
, highest_index_to_load_reg
, 1),
5542 gen_rtx_MEM (BLKmode
, str_addr_base_reg
)));
5544 into_loop_label
= gen_label_rtx ();
5545 s390_emit_jump (into_loop_label
, NULL_RTX
);
5549 emit_label (is_aligned_label
);
5550 LABEL_NUSES (is_aligned_label
) = INTVAL (alignment
) < 16 ? 2 : 1;
5552 /* Reaching this point we are only performing 16 bytes aligned
5554 emit_move_insn (highest_index_to_load_reg
, GEN_INT (15));
5556 emit_label (loop_start_label
);
5557 LABEL_NUSES (loop_start_label
) = 1;
5559 /* Load 16 bytes of the string into VR. */
5560 emit_move_insn (str_reg
,
5561 gen_rtx_MEM (V16QImode
,
5562 gen_rtx_PLUS (Pmode
, str_idx_reg
,
5563 str_addr_base_reg
)));
5564 if (into_loop_label
!= NULL_RTX
)
5566 emit_label (into_loop_label
);
5567 LABEL_NUSES (into_loop_label
) = 1;
5570 /* Increment string index by 16 bytes. */
5571 expand_binop (Pmode
, add_optab
, str_idx_reg
, GEN_INT (16),
5572 str_idx_reg
, 1, OPTAB_DIRECT
);
5574 emit_insn (gen_vec_vfenesv16qi (result_reg
, str_reg
, str_reg
,
5575 GEN_INT (VSTRING_FLAG_ZS
| VSTRING_FLAG_CS
)));
5577 add_int_reg_note (s390_emit_ccraw_jump (8, NE
, loop_start_label
),
5578 REG_BR_PROB
, very_likely
);
5579 emit_insn (gen_vec_extractv16qi (len
, result_reg
, GEN_INT (7)));
5581 /* If the string pointer wasn't aligned we have loaded less then 16
5582 bytes and the remaining bytes got filled with zeros (by vll).
5583 Now we have to check whether the resulting index lies within the
5584 bytes actually part of the string. */
5586 cond
= s390_emit_compare (GT
, convert_to_mode (Pmode
, len
, 1),
5587 highest_index_to_load_reg
);
5588 s390_load_address (highest_index_to_load_reg
,
5589 gen_rtx_PLUS (Pmode
, highest_index_to_load_reg
,
5592 emit_insn (gen_movdicc (str_idx_reg
, cond
,
5593 highest_index_to_load_reg
, str_idx_reg
));
5595 emit_insn (gen_movsicc (str_idx_reg
, cond
,
5596 highest_index_to_load_reg
, str_idx_reg
));
5598 add_int_reg_note (s390_emit_jump (is_aligned_label
, cond
), REG_BR_PROB
,
5601 expand_binop (Pmode
, add_optab
, str_idx_reg
,
5602 GEN_INT (-16), str_idx_reg
, 1, OPTAB_DIRECT
);
5603 /* FIXME: len is already zero extended - so avoid the llgcr emitted
5605 temp
= expand_binop (Pmode
, add_optab
, str_idx_reg
,
5606 convert_to_mode (Pmode
, len
, 1),
5607 target
, 1, OPTAB_DIRECT
);
5609 emit_move_insn (target
, temp
);
5612 /* Expand conditional increment or decrement using alc/slb instructions.
5613 Should generate code setting DST to either SRC or SRC + INCREMENT,
5614 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
5615 Returns true if successful, false otherwise.
5617 That makes it possible to implement some if-constructs without jumps e.g.:
5618 (borrow = CC0 | CC1 and carry = CC2 | CC3)
5619 unsigned int a, b, c;
5620 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
5621 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
5622 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
5623 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
5625 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
5626 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
5627 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
5628 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
5629 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
5632 s390_expand_addcc (enum rtx_code cmp_code
, rtx cmp_op0
, rtx cmp_op1
,
5633 rtx dst
, rtx src
, rtx increment
)
5635 machine_mode cmp_mode
;
5636 machine_mode cc_mode
;
5642 if ((GET_MODE (cmp_op0
) == SImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
5643 && (GET_MODE (cmp_op1
) == SImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
5645 else if ((GET_MODE (cmp_op0
) == DImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
5646 && (GET_MODE (cmp_op1
) == DImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
5651 /* Try ADD LOGICAL WITH CARRY. */
5652 if (increment
== const1_rtx
)
5654 /* Determine CC mode to use. */
5655 if (cmp_code
== EQ
|| cmp_code
== NE
)
5657 if (cmp_op1
!= const0_rtx
)
5659 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
5660 NULL_RTX
, 0, OPTAB_WIDEN
);
5661 cmp_op1
= const0_rtx
;
5664 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
5667 if (cmp_code
== LTU
|| cmp_code
== LEU
)
5672 cmp_code
= swap_condition (cmp_code
);
5689 /* Emit comparison instruction pattern. */
5690 if (!register_operand (cmp_op0
, cmp_mode
))
5691 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
5693 insn
= gen_rtx_SET (gen_rtx_REG (cc_mode
, CC_REGNUM
),
5694 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
5695 /* We use insn_invalid_p here to add clobbers if required. */
5696 ret
= insn_invalid_p (emit_insn (insn
), false);
5699 /* Emit ALC instruction pattern. */
5700 op_res
= gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
5701 gen_rtx_REG (cc_mode
, CC_REGNUM
),
5704 if (src
!= const0_rtx
)
5706 if (!register_operand (src
, GET_MODE (dst
)))
5707 src
= force_reg (GET_MODE (dst
), src
);
5709 op_res
= gen_rtx_PLUS (GET_MODE (dst
), op_res
, src
);
5710 op_res
= gen_rtx_PLUS (GET_MODE (dst
), op_res
, const0_rtx
);
5713 p
= rtvec_alloc (2);
5715 gen_rtx_SET (dst
, op_res
);
5717 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
5718 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
5723 /* Try SUBTRACT LOGICAL WITH BORROW. */
5724 if (increment
== constm1_rtx
)
5726 /* Determine CC mode to use. */
5727 if (cmp_code
== EQ
|| cmp_code
== NE
)
5729 if (cmp_op1
!= const0_rtx
)
5731 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
5732 NULL_RTX
, 0, OPTAB_WIDEN
);
5733 cmp_op1
= const0_rtx
;
5736 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
5739 if (cmp_code
== GTU
|| cmp_code
== GEU
)
5744 cmp_code
= swap_condition (cmp_code
);
5761 /* Emit comparison instruction pattern. */
5762 if (!register_operand (cmp_op0
, cmp_mode
))
5763 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
5765 insn
= gen_rtx_SET (gen_rtx_REG (cc_mode
, CC_REGNUM
),
5766 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
5767 /* We use insn_invalid_p here to add clobbers if required. */
5768 ret
= insn_invalid_p (emit_insn (insn
), false);
5771 /* Emit SLB instruction pattern. */
5772 if (!register_operand (src
, GET_MODE (dst
)))
5773 src
= force_reg (GET_MODE (dst
), src
);
5775 op_res
= gen_rtx_MINUS (GET_MODE (dst
),
5776 gen_rtx_MINUS (GET_MODE (dst
), src
, const0_rtx
),
5777 gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
5778 gen_rtx_REG (cc_mode
, CC_REGNUM
),
5780 p
= rtvec_alloc (2);
5782 gen_rtx_SET (dst
, op_res
);
5784 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
5785 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
5793 /* Expand code for the insv template. Return true if successful. */
5796 s390_expand_insv (rtx dest
, rtx op1
, rtx op2
, rtx src
)
5798 int bitsize
= INTVAL (op1
);
5799 int bitpos
= INTVAL (op2
);
5800 machine_mode mode
= GET_MODE (dest
);
5802 int smode_bsize
, mode_bsize
;
5805 if (bitsize
+ bitpos
> GET_MODE_BITSIZE (mode
))
5808 /* Generate INSERT IMMEDIATE (IILL et al). */
5809 /* (set (ze (reg)) (const_int)). */
5811 && register_operand (dest
, word_mode
)
5812 && (bitpos
% 16) == 0
5813 && (bitsize
% 16) == 0
5814 && const_int_operand (src
, VOIDmode
))
5816 HOST_WIDE_INT val
= INTVAL (src
);
5817 int regpos
= bitpos
+ bitsize
;
5819 while (regpos
> bitpos
)
5821 machine_mode putmode
;
5824 if (TARGET_EXTIMM
&& (regpos
% 32 == 0) && (regpos
>= bitpos
+ 32))
5829 putsize
= GET_MODE_BITSIZE (putmode
);
5831 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
,
5834 gen_int_mode (val
, putmode
));
5837 gcc_assert (regpos
== bitpos
);
5841 smode
= smallest_mode_for_size (bitsize
, MODE_INT
);
5842 smode_bsize
= GET_MODE_BITSIZE (smode
);
5843 mode_bsize
= GET_MODE_BITSIZE (mode
);
5845 /* Generate STORE CHARACTERS UNDER MASK (STCM et al). */
5847 && (bitsize
% BITS_PER_UNIT
) == 0
5849 && (register_operand (src
, word_mode
)
5850 || const_int_operand (src
, VOIDmode
)))
5852 /* Emit standard pattern if possible. */
5853 if (smode_bsize
== bitsize
)
5855 emit_move_insn (adjust_address (dest
, smode
, 0),
5856 gen_lowpart (smode
, src
));
5860 /* (set (ze (mem)) (const_int)). */
5861 else if (const_int_operand (src
, VOIDmode
))
5863 int size
= bitsize
/ BITS_PER_UNIT
;
5864 rtx src_mem
= adjust_address (force_const_mem (word_mode
, src
),
5866 UNITS_PER_WORD
- size
);
5868 dest
= adjust_address (dest
, BLKmode
, 0);
5869 set_mem_size (dest
, size
);
5870 s390_expand_movmem (dest
, src_mem
, GEN_INT (size
));
5874 /* (set (ze (mem)) (reg)). */
5875 else if (register_operand (src
, word_mode
))
5878 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
, op1
,
5882 /* Emit st,stcmh sequence. */
5883 int stcmh_width
= bitsize
- 32;
5884 int size
= stcmh_width
/ BITS_PER_UNIT
;
5886 emit_move_insn (adjust_address (dest
, SImode
, size
),
5887 gen_lowpart (SImode
, src
));
5888 set_mem_size (dest
, size
);
5889 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
,
5890 GEN_INT (stcmh_width
),
5892 gen_rtx_LSHIFTRT (word_mode
, src
, GEN_INT (32)));
5898 /* Generate INSERT CHARACTERS UNDER MASK (IC, ICM et al). */
5899 if ((bitpos
% BITS_PER_UNIT
) == 0
5900 && (bitsize
% BITS_PER_UNIT
) == 0
5901 && (bitpos
& 32) == ((bitpos
+ bitsize
- 1) & 32)
5903 && (mode
== DImode
|| mode
== SImode
)
5904 && register_operand (dest
, mode
))
5906 /* Emit a strict_low_part pattern if possible. */
5907 if (smode_bsize
== bitsize
&& bitpos
== mode_bsize
- smode_bsize
)
5909 op
= gen_rtx_STRICT_LOW_PART (VOIDmode
, gen_lowpart (smode
, dest
));
5910 op
= gen_rtx_SET (op
, gen_lowpart (smode
, src
));
5911 clobber
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
5912 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clobber
)));
5916 /* ??? There are more powerful versions of ICM that are not
5917 completely represented in the md file. */
5920 /* For z10, generate ROTATE THEN INSERT SELECTED BITS (RISBG et al). */
5921 if (TARGET_Z10
&& (mode
== DImode
|| mode
== SImode
))
5923 machine_mode mode_s
= GET_MODE (src
);
5925 if (mode_s
== VOIDmode
)
5927 /* For constant zero values the representation with AND
5928 appears to be folded in more situations than the (set
5929 (zero_extract) ...).
5930 We only do this when the start and end of the bitfield
5931 remain in the same SImode chunk. That way nihf or nilf
5933 The AND patterns might still generate a risbg for this. */
5934 if (src
== const0_rtx
&& bitpos
/ 32 == (bitpos
+ bitsize
- 1) / 32)
5937 src
= force_reg (mode
, src
);
5939 else if (mode_s
!= mode
)
5941 gcc_assert (GET_MODE_BITSIZE (mode_s
) >= bitsize
);
5942 src
= force_reg (mode_s
, src
);
5943 src
= gen_lowpart (mode
, src
);
5946 op
= gen_rtx_ZERO_EXTRACT (mode
, dest
, op1
, op2
),
5947 op
= gen_rtx_SET (op
, src
);
5951 clobber
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
5952 op
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clobber
));
5962 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
5963 register that holds VAL of mode MODE shifted by COUNT bits. */
5966 s390_expand_mask_and_shift (rtx val
, machine_mode mode
, rtx count
)
5968 val
= expand_simple_binop (SImode
, AND
, val
, GEN_INT (GET_MODE_MASK (mode
)),
5969 NULL_RTX
, 1, OPTAB_DIRECT
);
5970 return expand_simple_binop (SImode
, ASHIFT
, val
, count
,
5971 NULL_RTX
, 1, OPTAB_DIRECT
);
5974 /* Generate a vector comparison COND of CMP_OP1 and CMP_OP2 and store
5975 the result in TARGET. */
5978 s390_expand_vec_compare (rtx target
, enum rtx_code cond
,
5979 rtx cmp_op1
, rtx cmp_op2
)
5981 machine_mode mode
= GET_MODE (target
);
5982 bool neg_p
= false, swap_p
= false;
5985 if (GET_MODE (cmp_op1
) == V2DFmode
)
5989 /* NE a != b -> !(a == b) */
5990 case NE
: cond
= EQ
; neg_p
= true; break;
5991 /* UNGT a u> b -> !(b >= a) */
5992 case UNGT
: cond
= GE
; neg_p
= true; swap_p
= true; break;
5993 /* UNGE a u>= b -> !(b > a) */
5994 case UNGE
: cond
= GT
; neg_p
= true; swap_p
= true; break;
5995 /* LE: a <= b -> b >= a */
5996 case LE
: cond
= GE
; swap_p
= true; break;
5997 /* UNLE: a u<= b -> !(a > b) */
5998 case UNLE
: cond
= GT
; neg_p
= true; break;
5999 /* LT: a < b -> b > a */
6000 case LT
: cond
= GT
; swap_p
= true; break;
6001 /* UNLT: a u< b -> !(a >= b) */
6002 case UNLT
: cond
= GE
; neg_p
= true; break;
6004 emit_insn (gen_vec_cmpuneqv2df (target
, cmp_op1
, cmp_op2
));
6007 emit_insn (gen_vec_cmpltgtv2df (target
, cmp_op1
, cmp_op2
));
6010 emit_insn (gen_vec_orderedv2df (target
, cmp_op1
, cmp_op2
));
6013 emit_insn (gen_vec_unorderedv2df (target
, cmp_op1
, cmp_op2
));
6022 /* NE: a != b -> !(a == b) */
6023 case NE
: cond
= EQ
; neg_p
= true; break;
6024 /* GE: a >= b -> !(b > a) */
6025 case GE
: cond
= GT
; neg_p
= true; swap_p
= true; break;
6026 /* GEU: a >= b -> !(b > a) */
6027 case GEU
: cond
= GTU
; neg_p
= true; swap_p
= true; break;
6028 /* LE: a <= b -> !(a > b) */
6029 case LE
: cond
= GT
; neg_p
= true; break;
6030 /* LEU: a <= b -> !(a > b) */
6031 case LEU
: cond
= GTU
; neg_p
= true; break;
6032 /* LT: a < b -> b > a */
6033 case LT
: cond
= GT
; swap_p
= true; break;
6034 /* LTU: a < b -> b > a */
6035 case LTU
: cond
= GTU
; swap_p
= true; break;
6042 tmp
= cmp_op1
; cmp_op1
= cmp_op2
; cmp_op2
= tmp
;
6045 emit_insn (gen_rtx_SET (target
, gen_rtx_fmt_ee (cond
,
6047 cmp_op1
, cmp_op2
)));
6049 emit_insn (gen_rtx_SET (target
, gen_rtx_NOT (mode
, target
)));
6052 /* Expand the comparison CODE of CMP1 and CMP2 and copy 1 or 0 into
6053 TARGET if either all (ALL_P is true) or any (ALL_P is false) of the
6054 elements in CMP1 and CMP2 fulfill the comparison. */
6056 s390_expand_vec_compare_cc (rtx target
, enum rtx_code code
,
6057 rtx cmp1
, rtx cmp2
, bool all_p
)
6059 enum rtx_code new_code
= code
;
6060 machine_mode cmp_mode
, full_cmp_mode
, scratch_mode
;
6061 rtx tmp_reg
= gen_reg_rtx (SImode
);
6062 bool swap_p
= false;
6064 if (GET_MODE_CLASS (GET_MODE (cmp1
)) == MODE_VECTOR_INT
)
6068 case EQ
: cmp_mode
= CCVEQmode
; break;
6069 case NE
: cmp_mode
= CCVEQmode
; break;
6070 case GT
: cmp_mode
= CCVHmode
; break;
6071 case GE
: cmp_mode
= CCVHmode
; new_code
= LE
; swap_p
= true; break;
6072 case LT
: cmp_mode
= CCVHmode
; new_code
= GT
; swap_p
= true; break;
6073 case LE
: cmp_mode
= CCVHmode
; new_code
= LE
; break;
6074 case GTU
: cmp_mode
= CCVHUmode
; break;
6075 case GEU
: cmp_mode
= CCVHUmode
; new_code
= LEU
; swap_p
= true; break;
6076 case LTU
: cmp_mode
= CCVHUmode
; new_code
= GTU
; swap_p
= true; break;
6077 case LEU
: cmp_mode
= CCVHUmode
; new_code
= LEU
; break;
6078 default: gcc_unreachable ();
6080 scratch_mode
= GET_MODE (cmp1
);
6082 else if (GET_MODE (cmp1
) == V2DFmode
)
6086 case EQ
: cmp_mode
= CCVEQmode
; break;
6087 case NE
: cmp_mode
= CCVEQmode
; break;
6088 case GT
: cmp_mode
= CCVFHmode
; break;
6089 case GE
: cmp_mode
= CCVFHEmode
; break;
6090 case UNLE
: cmp_mode
= CCVFHmode
; break;
6091 case UNLT
: cmp_mode
= CCVFHEmode
; break;
6092 case LT
: cmp_mode
= CCVFHmode
; new_code
= GT
; swap_p
= true; break;
6093 case LE
: cmp_mode
= CCVFHEmode
; new_code
= GE
; swap_p
= true; break;
6094 default: gcc_unreachable ();
6096 scratch_mode
= V2DImode
;
6104 case CCVEQmode
: full_cmp_mode
= CCVEQANYmode
; break;
6105 case CCVHmode
: full_cmp_mode
= CCVHANYmode
; break;
6106 case CCVHUmode
: full_cmp_mode
= CCVHUANYmode
; break;
6107 case CCVFHmode
: full_cmp_mode
= CCVFHANYmode
; break;
6108 case CCVFHEmode
: full_cmp_mode
= CCVFHEANYmode
; break;
6109 default: gcc_unreachable ();
6112 /* The modes without ANY match the ALL modes. */
6113 full_cmp_mode
= cmp_mode
;
6122 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
6123 gen_rtvec (2, gen_rtx_SET (
6124 gen_rtx_REG (cmp_mode
, CC_REGNUM
),
6125 gen_rtx_COMPARE (cmp_mode
, cmp1
, cmp2
)),
6126 gen_rtx_CLOBBER (VOIDmode
,
6127 gen_rtx_SCRATCH (scratch_mode
)))));
6128 emit_move_insn (target
, const0_rtx
);
6129 emit_move_insn (tmp_reg
, const1_rtx
);
6131 emit_move_insn (target
,
6132 gen_rtx_IF_THEN_ELSE (SImode
,
6133 gen_rtx_fmt_ee (new_code
, VOIDmode
,
6134 gen_rtx_REG (full_cmp_mode
, CC_REGNUM
),
6139 /* Generate a vector comparison expression loading either elements of
6140 THEN or ELS into TARGET depending on the comparison COND of CMP_OP1
6144 s390_expand_vcond (rtx target
, rtx then
, rtx els
,
6145 enum rtx_code cond
, rtx cmp_op1
, rtx cmp_op2
)
6148 machine_mode result_mode
;
6151 machine_mode target_mode
= GET_MODE (target
);
6152 machine_mode cmp_mode
= GET_MODE (cmp_op1
);
6153 rtx op
= (cond
== LT
) ? els
: then
;
6155 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
6156 and x < 0 ? 1 : 0 into (unsigned) x >> 31. Likewise
6157 for short and byte (x >> 15 and x >> 7 respectively). */
6158 if ((cond
== LT
|| cond
== GE
)
6159 && target_mode
== cmp_mode
6160 && cmp_op2
== CONST0_RTX (cmp_mode
)
6161 && op
== CONST0_RTX (target_mode
)
6162 && s390_vector_mode_supported_p (target_mode
)
6163 && GET_MODE_CLASS (target_mode
) == MODE_VECTOR_INT
)
6165 rtx negop
= (cond
== LT
) ? then
: els
;
6167 int shift
= GET_MODE_BITSIZE (GET_MODE_INNER (target_mode
)) - 1;
6169 /* if x < 0 ? 1 : 0 or if x >= 0 ? 0 : 1 */
6170 if (negop
== CONST1_RTX (target_mode
))
6172 rtx res
= expand_simple_binop (cmp_mode
, LSHIFTRT
, cmp_op1
,
6173 GEN_INT (shift
), target
,
6176 emit_move_insn (target
, res
);
6180 /* if x < 0 ? -1 : 0 or if x >= 0 ? 0 : -1 */
6181 else if (all_ones_operand (negop
, target_mode
))
6183 rtx res
= expand_simple_binop (cmp_mode
, ASHIFTRT
, cmp_op1
,
6184 GEN_INT (shift
), target
,
6187 emit_move_insn (target
, res
);
6192 /* We always use an integral type vector to hold the comparison
6194 result_mode
= cmp_mode
== V2DFmode
? V2DImode
: cmp_mode
;
6195 result_target
= gen_reg_rtx (result_mode
);
6197 /* We allow vector immediates as comparison operands that
6198 can be handled by the optimization above but not by the
6199 following code. Hence, force them into registers here. */
6200 if (!REG_P (cmp_op1
))
6201 cmp_op1
= force_reg (target_mode
, cmp_op1
);
6203 if (!REG_P (cmp_op2
))
6204 cmp_op2
= force_reg (target_mode
, cmp_op2
);
6206 s390_expand_vec_compare (result_target
, cond
,
6209 /* If the results are supposed to be either -1 or 0 we are done
6210 since this is what our compare instructions generate anyway. */
6211 if (all_ones_operand (then
, GET_MODE (then
))
6212 && const0_operand (els
, GET_MODE (els
)))
6214 emit_move_insn (target
, gen_rtx_SUBREG (target_mode
,
6219 /* Otherwise we will do a vsel afterwards. */
6220 /* This gets triggered e.g.
6221 with gcc.c-torture/compile/pr53410-1.c */
6223 then
= force_reg (target_mode
, then
);
6226 els
= force_reg (target_mode
, els
);
6228 tmp
= gen_rtx_fmt_ee (EQ
, VOIDmode
,
6230 CONST0_RTX (result_mode
));
6232 /* We compared the result against zero above so we have to swap then
6234 tmp
= gen_rtx_IF_THEN_ELSE (target_mode
, tmp
, els
, then
);
6236 gcc_assert (target_mode
== GET_MODE (then
));
6237 emit_insn (gen_rtx_SET (target
, tmp
));
6240 /* Emit the RTX necessary to initialize the vector TARGET with values
6243 s390_expand_vec_init (rtx target
, rtx vals
)
6245 machine_mode mode
= GET_MODE (target
);
6246 machine_mode inner_mode
= GET_MODE_INNER (mode
);
6247 int n_elts
= GET_MODE_NUNITS (mode
);
6248 bool all_same
= true, all_regs
= true, all_const_int
= true;
6252 for (i
= 0; i
< n_elts
; ++i
)
6254 x
= XVECEXP (vals
, 0, i
);
6256 if (!CONST_INT_P (x
))
6257 all_const_int
= false;
6259 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
6266 /* Use vector gen mask or vector gen byte mask if possible. */
6267 if (all_same
&& all_const_int
6268 && (XVECEXP (vals
, 0, 0) == const0_rtx
6269 || s390_contiguous_bitmask_vector_p (XVECEXP (vals
, 0, 0),
6271 || s390_bytemask_vector_p (XVECEXP (vals
, 0, 0), NULL
)))
6273 emit_insn (gen_rtx_SET (target
,
6274 gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0))));
6280 emit_insn (gen_rtx_SET (target
,
6281 gen_rtx_VEC_DUPLICATE (mode
,
6282 XVECEXP (vals
, 0, 0))));
6286 if (all_regs
&& REG_P (target
) && n_elts
== 2 && inner_mode
== DImode
)
6288 /* Use vector load pair. */
6289 emit_insn (gen_rtx_SET (target
,
6290 gen_rtx_VEC_CONCAT (mode
,
6291 XVECEXP (vals
, 0, 0),
6292 XVECEXP (vals
, 0, 1))));
6296 /* We are about to set the vector elements one by one. Zero out the
6297 full register first in order to help the data flow framework to
6298 detect it as full VR set. */
6299 emit_insn (gen_rtx_SET (target
, CONST0_RTX (mode
)));
6301 /* Unfortunately the vec_init expander is not allowed to fail. So
6302 we have to implement the fallback ourselves. */
6303 for (i
= 0; i
< n_elts
; i
++)
6304 emit_insn (gen_rtx_SET (target
,
6305 gen_rtx_UNSPEC (mode
,
6306 gen_rtvec (3, XVECEXP (vals
, 0, i
),
6307 GEN_INT (i
), target
),
6311 /* Structure to hold the initial parameters for a compare_and_swap operation
6312 in HImode and QImode. */
6314 struct alignment_context
6316 rtx memsi
; /* SI aligned memory location. */
6317 rtx shift
; /* Bit offset with regard to lsb. */
6318 rtx modemask
; /* Mask of the HQImode shifted by SHIFT bits. */
6319 rtx modemaski
; /* ~modemask */
6320 bool aligned
; /* True if memory is aligned, false else. */
6323 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
6324 structure AC for transparent simplifying, if the memory alignment is known
6325 to be at least 32bit. MEM is the memory location for the actual operation
6326 and MODE its mode. */
6329 init_alignment_context (struct alignment_context
*ac
, rtx mem
,
6332 ac
->shift
= GEN_INT (GET_MODE_SIZE (SImode
) - GET_MODE_SIZE (mode
));
6333 ac
->aligned
= (MEM_ALIGN (mem
) >= GET_MODE_BITSIZE (SImode
));
6336 ac
->memsi
= adjust_address (mem
, SImode
, 0); /* Memory is aligned. */
6339 /* Alignment is unknown. */
6340 rtx byteoffset
, addr
, align
;
6342 /* Force the address into a register. */
6343 addr
= force_reg (Pmode
, XEXP (mem
, 0));
6345 /* Align it to SImode. */
6346 align
= expand_simple_binop (Pmode
, AND
, addr
,
6347 GEN_INT (-GET_MODE_SIZE (SImode
)),
6348 NULL_RTX
, 1, OPTAB_DIRECT
);
6350 ac
->memsi
= gen_rtx_MEM (SImode
, align
);
6351 MEM_VOLATILE_P (ac
->memsi
) = MEM_VOLATILE_P (mem
);
6352 set_mem_alias_set (ac
->memsi
, ALIAS_SET_MEMORY_BARRIER
);
6353 set_mem_align (ac
->memsi
, GET_MODE_BITSIZE (SImode
));
6355 /* Calculate shiftcount. */
6356 byteoffset
= expand_simple_binop (Pmode
, AND
, addr
,
6357 GEN_INT (GET_MODE_SIZE (SImode
) - 1),
6358 NULL_RTX
, 1, OPTAB_DIRECT
);
6359 /* As we already have some offset, evaluate the remaining distance. */
6360 ac
->shift
= expand_simple_binop (SImode
, MINUS
, ac
->shift
, byteoffset
,
6361 NULL_RTX
, 1, OPTAB_DIRECT
);
6364 /* Shift is the byte count, but we need the bitcount. */
6365 ac
->shift
= expand_simple_binop (SImode
, ASHIFT
, ac
->shift
, GEN_INT (3),
6366 NULL_RTX
, 1, OPTAB_DIRECT
);
6368 /* Calculate masks. */
6369 ac
->modemask
= expand_simple_binop (SImode
, ASHIFT
,
6370 GEN_INT (GET_MODE_MASK (mode
)),
6371 ac
->shift
, NULL_RTX
, 1, OPTAB_DIRECT
);
6372 ac
->modemaski
= expand_simple_unop (SImode
, NOT
, ac
->modemask
,
6376 /* A subroutine of s390_expand_cs_hqi. Insert INS into VAL. If possible,
6377 use a single insv insn into SEQ2. Otherwise, put prep insns in SEQ1 and
6378 perform the merge in SEQ2. */
6381 s390_two_part_insv (struct alignment_context
*ac
, rtx
*seq1
, rtx
*seq2
,
6382 machine_mode mode
, rtx val
, rtx ins
)
6389 tmp
= copy_to_mode_reg (SImode
, val
);
6390 if (s390_expand_insv (tmp
, GEN_INT (GET_MODE_BITSIZE (mode
)),
6394 *seq2
= get_insns ();
6401 /* Failed to use insv. Generate a two part shift and mask. */
6403 tmp
= s390_expand_mask_and_shift (ins
, mode
, ac
->shift
);
6404 *seq1
= get_insns ();
6408 tmp
= expand_simple_binop (SImode
, IOR
, tmp
, val
, NULL_RTX
, 1, OPTAB_DIRECT
);
6409 *seq2
= get_insns ();
6415 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
6416 the memory location, CMP the old value to compare MEM with and NEW_RTX the
6417 value to set if CMP == MEM. */
6420 s390_expand_cs_hqi (machine_mode mode
, rtx btarget
, rtx vtarget
, rtx mem
,
6421 rtx cmp
, rtx new_rtx
, bool is_weak
)
6423 struct alignment_context ac
;
6424 rtx cmpv
, newv
, val
, cc
, seq0
, seq1
, seq2
, seq3
;
6425 rtx res
= gen_reg_rtx (SImode
);
6426 rtx_code_label
*csloop
= NULL
, *csend
= NULL
;
6428 gcc_assert (MEM_P (mem
));
6430 init_alignment_context (&ac
, mem
, mode
);
6432 /* Load full word. Subsequent loads are performed by CS. */
6433 val
= expand_simple_binop (SImode
, AND
, ac
.memsi
, ac
.modemaski
,
6434 NULL_RTX
, 1, OPTAB_DIRECT
);
6436 /* Prepare insertions of cmp and new_rtx into the loaded value. When
6437 possible, we try to use insv to make this happen efficiently. If
6438 that fails we'll generate code both inside and outside the loop. */
6439 cmpv
= s390_two_part_insv (&ac
, &seq0
, &seq2
, mode
, val
, cmp
);
6440 newv
= s390_two_part_insv (&ac
, &seq1
, &seq3
, mode
, val
, new_rtx
);
6447 /* Start CS loop. */
6450 /* Begin assuming success. */
6451 emit_move_insn (btarget
, const1_rtx
);
6453 csloop
= gen_label_rtx ();
6454 csend
= gen_label_rtx ();
6455 emit_label (csloop
);
6458 /* val = "<mem>00..0<mem>"
6459 * cmp = "00..0<cmp>00..0"
6460 * new = "00..0<new>00..0"
6466 cc
= s390_emit_compare_and_swap (EQ
, res
, ac
.memsi
, cmpv
, newv
);
6468 emit_insn (gen_cstorecc4 (btarget
, cc
, XEXP (cc
, 0), XEXP (cc
, 1)));
6473 /* Jump to end if we're done (likely?). */
6474 s390_emit_jump (csend
, cc
);
6476 /* Check for changes outside mode, and loop internal if so.
6477 Arrange the moves so that the compare is adjacent to the
6478 branch so that we can generate CRJ. */
6479 tmp
= copy_to_reg (val
);
6480 force_expand_binop (SImode
, and_optab
, res
, ac
.modemaski
, val
,
6482 cc
= s390_emit_compare (NE
, val
, tmp
);
6483 s390_emit_jump (csloop
, cc
);
6486 emit_move_insn (btarget
, const0_rtx
);
6490 /* Return the correct part of the bitfield. */
6491 convert_move (vtarget
, expand_simple_binop (SImode
, LSHIFTRT
, res
, ac
.shift
,
6492 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
6495 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
6496 and VAL the value to play with. If AFTER is true then store the value
6497 MEM holds after the operation, if AFTER is false then store the value MEM
6498 holds before the operation. If TARGET is zero then discard that value, else
6499 store it to TARGET. */
6502 s390_expand_atomic (machine_mode mode
, enum rtx_code code
,
6503 rtx target
, rtx mem
, rtx val
, bool after
)
6505 struct alignment_context ac
;
6507 rtx new_rtx
= gen_reg_rtx (SImode
);
6508 rtx orig
= gen_reg_rtx (SImode
);
6509 rtx_code_label
*csloop
= gen_label_rtx ();
6511 gcc_assert (!target
|| register_operand (target
, VOIDmode
));
6512 gcc_assert (MEM_P (mem
));
6514 init_alignment_context (&ac
, mem
, mode
);
6516 /* Shift val to the correct bit positions.
6517 Preserve "icm", but prevent "ex icm". */
6518 if (!(ac
.aligned
&& code
== SET
&& MEM_P (val
)))
6519 val
= s390_expand_mask_and_shift (val
, mode
, ac
.shift
);
6521 /* Further preparation insns. */
6522 if (code
== PLUS
|| code
== MINUS
)
6523 emit_move_insn (orig
, val
);
6524 else if (code
== MULT
|| code
== AND
) /* val = "11..1<val>11..1" */
6525 val
= expand_simple_binop (SImode
, XOR
, val
, ac
.modemaski
,
6526 NULL_RTX
, 1, OPTAB_DIRECT
);
6528 /* Load full word. Subsequent loads are performed by CS. */
6529 cmp
= force_reg (SImode
, ac
.memsi
);
6531 /* Start CS loop. */
6532 emit_label (csloop
);
6533 emit_move_insn (new_rtx
, cmp
);
6535 /* Patch new with val at correct position. */
6540 val
= expand_simple_binop (SImode
, code
, new_rtx
, orig
,
6541 NULL_RTX
, 1, OPTAB_DIRECT
);
6542 val
= expand_simple_binop (SImode
, AND
, val
, ac
.modemask
,
6543 NULL_RTX
, 1, OPTAB_DIRECT
);
6546 if (ac
.aligned
&& MEM_P (val
))
6547 store_bit_field (new_rtx
, GET_MODE_BITSIZE (mode
), 0,
6548 0, 0, SImode
, val
, false);
6551 new_rtx
= expand_simple_binop (SImode
, AND
, new_rtx
, ac
.modemaski
,
6552 NULL_RTX
, 1, OPTAB_DIRECT
);
6553 new_rtx
= expand_simple_binop (SImode
, IOR
, new_rtx
, val
,
6554 NULL_RTX
, 1, OPTAB_DIRECT
);
6560 new_rtx
= expand_simple_binop (SImode
, code
, new_rtx
, val
,
6561 NULL_RTX
, 1, OPTAB_DIRECT
);
6563 case MULT
: /* NAND */
6564 new_rtx
= expand_simple_binop (SImode
, AND
, new_rtx
, val
,
6565 NULL_RTX
, 1, OPTAB_DIRECT
);
6566 new_rtx
= expand_simple_binop (SImode
, XOR
, new_rtx
, ac
.modemask
,
6567 NULL_RTX
, 1, OPTAB_DIRECT
);
6573 s390_emit_jump (csloop
, s390_emit_compare_and_swap (NE
, cmp
,
6574 ac
.memsi
, cmp
, new_rtx
));
6576 /* Return the correct part of the bitfield. */
6578 convert_move (target
, expand_simple_binop (SImode
, LSHIFTRT
,
6579 after
? new_rtx
: cmp
, ac
.shift
,
6580 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
6583 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
6584 We need to emit DTP-relative relocations. */
6586 static void s390_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
6589 s390_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
6594 fputs ("\t.long\t", file
);
6597 fputs ("\t.quad\t", file
);
6602 output_addr_const (file
, x
);
6603 fputs ("@DTPOFF", file
);
6606 /* Return the proper mode for REGNO being represented in the dwarf
6609 s390_dwarf_frame_reg_mode (int regno
)
6611 machine_mode save_mode
= default_dwarf_frame_reg_mode (regno
);
6613 /* Make sure not to return DImode for any GPR with -m31 -mzarch. */
6614 if (GENERAL_REGNO_P (regno
))
6617 /* The rightmost 64 bits of vector registers are call-clobbered. */
6618 if (GET_MODE_SIZE (save_mode
) > 8)
6624 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
6625 /* Implement TARGET_MANGLE_TYPE. */
6628 s390_mangle_type (const_tree type
)
6630 type
= TYPE_MAIN_VARIANT (type
);
6632 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
6633 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
6636 if (type
== s390_builtin_types
[BT_BV16QI
]) return "U6__boolc";
6637 if (type
== s390_builtin_types
[BT_BV8HI
]) return "U6__bools";
6638 if (type
== s390_builtin_types
[BT_BV4SI
]) return "U6__booli";
6639 if (type
== s390_builtin_types
[BT_BV2DI
]) return "U6__booll";
6641 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
6642 && TARGET_LONG_DOUBLE_128
)
6645 /* For all other types, use normal C++ mangling. */
6650 /* In the name of slightly smaller debug output, and to cater to
6651 general assembler lossage, recognize various UNSPEC sequences
6652 and turn them back into a direct symbol reference. */
6655 s390_delegitimize_address (rtx orig_x
)
6659 orig_x
= delegitimize_mem_from_attrs (orig_x
);
6662 /* Extract the symbol ref from:
6663 (plus:SI (reg:SI 12 %r12)
6664 (const:SI (unspec:SI [(symbol_ref/f:SI ("*.LC0"))]
6665 UNSPEC_GOTOFF/PLTOFF)))
6667 (plus:SI (reg:SI 12 %r12)
6668 (const:SI (plus:SI (unspec:SI [(symbol_ref:SI ("L"))]
6669 UNSPEC_GOTOFF/PLTOFF)
6670 (const_int 4 [0x4])))) */
6671 if (GET_CODE (x
) == PLUS
6672 && REG_P (XEXP (x
, 0))
6673 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
6674 && GET_CODE (XEXP (x
, 1)) == CONST
)
6676 HOST_WIDE_INT offset
= 0;
6678 /* The const operand. */
6679 y
= XEXP (XEXP (x
, 1), 0);
6681 if (GET_CODE (y
) == PLUS
6682 && GET_CODE (XEXP (y
, 1)) == CONST_INT
)
6684 offset
= INTVAL (XEXP (y
, 1));
6688 if (GET_CODE (y
) == UNSPEC
6689 && (XINT (y
, 1) == UNSPEC_GOTOFF
6690 || XINT (y
, 1) == UNSPEC_PLTOFF
))
6691 return plus_constant (Pmode
, XVECEXP (y
, 0, 0), offset
);
6694 if (GET_CODE (x
) != MEM
)
6698 if (GET_CODE (x
) == PLUS
6699 && GET_CODE (XEXP (x
, 1)) == CONST
6700 && GET_CODE (XEXP (x
, 0)) == REG
6701 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
)
6703 y
= XEXP (XEXP (x
, 1), 0);
6704 if (GET_CODE (y
) == UNSPEC
6705 && XINT (y
, 1) == UNSPEC_GOT
)
6706 y
= XVECEXP (y
, 0, 0);
6710 else if (GET_CODE (x
) == CONST
)
6712 /* Extract the symbol ref from:
6713 (mem:QI (const:DI (unspec:DI [(symbol_ref:DI ("foo"))]
6714 UNSPEC_PLT/GOTENT))) */
6717 if (GET_CODE (y
) == UNSPEC
6718 && (XINT (y
, 1) == UNSPEC_GOTENT
6719 || XINT (y
, 1) == UNSPEC_PLT
))
6720 y
= XVECEXP (y
, 0, 0);
6727 if (GET_MODE (orig_x
) != Pmode
)
6729 if (GET_MODE (orig_x
) == BLKmode
)
6731 y
= lowpart_subreg (GET_MODE (orig_x
), y
, Pmode
);
6738 /* Output operand OP to stdio stream FILE.
6739 OP is an address (register + offset) which is not used to address data;
6740 instead the rightmost bits are interpreted as the value. */
6743 print_shift_count_operand (FILE *file
, rtx op
)
6745 HOST_WIDE_INT offset
;
6748 /* Extract base register and offset. */
6749 if (!s390_decompose_shift_count (op
, &base
, &offset
))
6755 gcc_assert (GET_CODE (base
) == REG
);
6756 gcc_assert (REGNO (base
) < FIRST_PSEUDO_REGISTER
);
6757 gcc_assert (REGNO_REG_CLASS (REGNO (base
)) == ADDR_REGS
);
6760 /* Offsets are constricted to twelve bits. */
6761 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
& ((1 << 12) - 1));
6763 fprintf (file
, "(%s)", reg_names
[REGNO (base
)]);
6766 /* Assigns the number of NOP halfwords to be emitted before and after the
6767 function label to *HW_BEFORE and *HW_AFTER. Both pointers must not be NULL.
6768 If hotpatching is disabled for the function, the values are set to zero.
6772 s390_function_num_hotpatch_hw (tree decl
,
6778 attr
= lookup_attribute ("hotpatch", DECL_ATTRIBUTES (decl
));
6780 /* Handle the arguments of the hotpatch attribute. The values
6781 specified via attribute might override the cmdline argument
6785 tree args
= TREE_VALUE (attr
);
6787 *hw_before
= TREE_INT_CST_LOW (TREE_VALUE (args
));
6788 *hw_after
= TREE_INT_CST_LOW (TREE_VALUE (TREE_CHAIN (args
)));
6792 /* Use the values specified by the cmdline arguments. */
6793 *hw_before
= s390_hotpatch_hw_before_label
;
6794 *hw_after
= s390_hotpatch_hw_after_label
;
6798 /* Write the current .machine and .machinemode specification to the assembler
6801 #ifdef HAVE_AS_MACHINE_MACHINEMODE
6803 s390_asm_output_machine_for_arch (FILE *asm_out_file
)
6805 fprintf (asm_out_file
, "\t.machinemode %s\n",
6806 (TARGET_ZARCH
) ? "zarch" : "esa");
6807 fprintf (asm_out_file
, "\t.machine \"%s", processor_table
[s390_arch
].name
);
6808 if (S390_USE_ARCHITECTURE_MODIFIERS
)
6812 cpu_flags
= processor_flags_table
[(int) s390_arch
];
6813 if (TARGET_HTM
&& !(cpu_flags
& PF_TX
))
6814 fprintf (asm_out_file
, "+htm");
6815 else if (!TARGET_HTM
&& (cpu_flags
& PF_TX
))
6816 fprintf (asm_out_file
, "+nohtm");
6817 if (TARGET_VX
&& !(cpu_flags
& PF_VX
))
6818 fprintf (asm_out_file
, "+vx");
6819 else if (!TARGET_VX
&& (cpu_flags
& PF_VX
))
6820 fprintf (asm_out_file
, "+novx");
6822 fprintf (asm_out_file
, "\"\n");
6825 /* Write an extra function header before the very start of the function. */
6828 s390_asm_output_function_prefix (FILE *asm_out_file
,
6829 const char *fnname ATTRIBUTE_UNUSED
)
6831 if (DECL_FUNCTION_SPECIFIC_TARGET (current_function_decl
) == NULL
)
6833 /* Since only the function specific options are saved but not the indications
6834 which options are set, it's too much work here to figure out which options
6835 have actually changed. Thus, generate .machine and .machinemode whenever a
6836 function has the target attribute or pragma. */
6837 fprintf (asm_out_file
, "\t.machinemode push\n");
6838 fprintf (asm_out_file
, "\t.machine push\n");
6839 s390_asm_output_machine_for_arch (asm_out_file
);
6842 /* Write an extra function footer after the very end of the function. */
6845 s390_asm_declare_function_size (FILE *asm_out_file
,
6846 const char *fnname
, tree decl
)
6848 if (!flag_inhibit_size_directive
)
6849 ASM_OUTPUT_MEASURED_SIZE (asm_out_file
, fnname
);
6850 if (DECL_FUNCTION_SPECIFIC_TARGET (decl
) == NULL
)
6852 fprintf (asm_out_file
, "\t.machine pop\n");
6853 fprintf (asm_out_file
, "\t.machinemode pop\n");
6857 /* Write the extra assembler code needed to declare a function properly. */
6860 s390_asm_output_function_label (FILE *asm_out_file
, const char *fname
,
6863 int hw_before
, hw_after
;
6865 s390_function_num_hotpatch_hw (decl
, &hw_before
, &hw_after
);
6868 unsigned int function_alignment
;
6871 /* Add a trampoline code area before the function label and initialize it
6872 with two-byte nop instructions. This area can be overwritten with code
6873 that jumps to a patched version of the function. */
6874 asm_fprintf (asm_out_file
, "\tnopr\t%%r7"
6875 "\t# pre-label NOPs for hotpatch (%d halfwords)\n",
6877 for (i
= 1; i
< hw_before
; i
++)
6878 fputs ("\tnopr\t%r7\n", asm_out_file
);
6880 /* Note: The function label must be aligned so that (a) the bytes of the
6881 following nop do not cross a cacheline boundary, and (b) a jump address
6882 (eight bytes for 64 bit targets, 4 bytes for 32 bit targets) can be
6883 stored directly before the label without crossing a cacheline
6884 boundary. All this is necessary to make sure the trampoline code can
6885 be changed atomically.
6886 This alignment is done automatically using the FOUNCTION_BOUNDARY, but
6887 if there are NOPs before the function label, the alignment is placed
6888 before them. So it is necessary to duplicate the alignment after the
6890 function_alignment
= MAX (8, DECL_ALIGN (decl
) / BITS_PER_UNIT
);
6891 if (! DECL_USER_ALIGN (decl
))
6892 function_alignment
= MAX (function_alignment
,
6893 (unsigned int) align_functions
);
6894 fputs ("\t# alignment for hotpatch\n", asm_out_file
);
6895 ASM_OUTPUT_ALIGN (asm_out_file
, floor_log2 (function_alignment
));
6898 if (S390_USE_TARGET_ATTRIBUTE
&& TARGET_DEBUG_ARG
)
6900 asm_fprintf (asm_out_file
, "\t# fn:%s ar%d\n", fname
, s390_arch
);
6901 asm_fprintf (asm_out_file
, "\t# fn:%s tu%d\n", fname
, s390_tune
);
6902 asm_fprintf (asm_out_file
, "\t# fn:%s sg%d\n", fname
, s390_stack_guard
);
6903 asm_fprintf (asm_out_file
, "\t# fn:%s ss%d\n", fname
, s390_stack_size
);
6904 asm_fprintf (asm_out_file
, "\t# fn:%s bc%d\n", fname
, s390_branch_cost
);
6905 asm_fprintf (asm_out_file
, "\t# fn:%s wf%d\n", fname
,
6906 s390_warn_framesize
);
6907 asm_fprintf (asm_out_file
, "\t# fn:%s ba%d\n", fname
, TARGET_BACKCHAIN
);
6908 asm_fprintf (asm_out_file
, "\t# fn:%s hd%d\n", fname
, TARGET_HARD_DFP
);
6909 asm_fprintf (asm_out_file
, "\t# fn:%s hf%d\n", fname
, !TARGET_SOFT_FLOAT
);
6910 asm_fprintf (asm_out_file
, "\t# fn:%s ht%d\n", fname
, TARGET_OPT_HTM
);
6911 asm_fprintf (asm_out_file
, "\t# fn:%s vx%d\n", fname
, TARGET_OPT_VX
);
6912 asm_fprintf (asm_out_file
, "\t# fn:%s ps%d\n", fname
,
6913 TARGET_PACKED_STACK
);
6914 asm_fprintf (asm_out_file
, "\t# fn:%s se%d\n", fname
, TARGET_SMALL_EXEC
);
6915 asm_fprintf (asm_out_file
, "\t# fn:%s mv%d\n", fname
, TARGET_MVCLE
);
6916 asm_fprintf (asm_out_file
, "\t# fn:%s zv%d\n", fname
, TARGET_ZVECTOR
);
6917 asm_fprintf (asm_out_file
, "\t# fn:%s wd%d\n", fname
,
6918 s390_warn_dynamicstack_p
);
6920 ASM_OUTPUT_LABEL (asm_out_file
, fname
);
6922 asm_fprintf (asm_out_file
,
6923 "\t# post-label NOPs for hotpatch (%d halfwords)\n",
6927 /* Output machine-dependent UNSPECs occurring in address constant X
6928 in assembler syntax to stdio stream FILE. Returns true if the
6929 constant X could be recognized, false otherwise. */
6932 s390_output_addr_const_extra (FILE *file
, rtx x
)
6934 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 1)
6935 switch (XINT (x
, 1))
6938 output_addr_const (file
, XVECEXP (x
, 0, 0));
6939 fprintf (file
, "@GOTENT");
6942 output_addr_const (file
, XVECEXP (x
, 0, 0));
6943 fprintf (file
, "@GOT");
6946 output_addr_const (file
, XVECEXP (x
, 0, 0));
6947 fprintf (file
, "@GOTOFF");
6950 output_addr_const (file
, XVECEXP (x
, 0, 0));
6951 fprintf (file
, "@PLT");
6954 output_addr_const (file
, XVECEXP (x
, 0, 0));
6955 fprintf (file
, "@PLTOFF");
6958 output_addr_const (file
, XVECEXP (x
, 0, 0));
6959 fprintf (file
, "@TLSGD");
6962 assemble_name (file
, get_some_local_dynamic_name ());
6963 fprintf (file
, "@TLSLDM");
6966 output_addr_const (file
, XVECEXP (x
, 0, 0));
6967 fprintf (file
, "@DTPOFF");
6970 output_addr_const (file
, XVECEXP (x
, 0, 0));
6971 fprintf (file
, "@NTPOFF");
6973 case UNSPEC_GOTNTPOFF
:
6974 output_addr_const (file
, XVECEXP (x
, 0, 0));
6975 fprintf (file
, "@GOTNTPOFF");
6977 case UNSPEC_INDNTPOFF
:
6978 output_addr_const (file
, XVECEXP (x
, 0, 0));
6979 fprintf (file
, "@INDNTPOFF");
6983 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 2)
6984 switch (XINT (x
, 1))
6986 case UNSPEC_POOL_OFFSET
:
6987 x
= gen_rtx_MINUS (GET_MODE (x
), XVECEXP (x
, 0, 0), XVECEXP (x
, 0, 1));
6988 output_addr_const (file
, x
);
6994 /* Output address operand ADDR in assembler syntax to
6995 stdio stream FILE. */
6998 print_operand_address (FILE *file
, rtx addr
)
7000 struct s390_address ad
;
7002 if (s390_loadrelative_operand_p (addr
, NULL
, NULL
))
7006 output_operand_lossage ("symbolic memory references are "
7007 "only supported on z10 or later");
7010 output_addr_const (file
, addr
);
7014 if (!s390_decompose_address (addr
, &ad
)
7015 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
7016 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
7017 output_operand_lossage ("cannot decompose address");
7020 output_addr_const (file
, ad
.disp
);
7022 fprintf (file
, "0");
7024 if (ad
.base
&& ad
.indx
)
7025 fprintf (file
, "(%s,%s)", reg_names
[REGNO (ad
.indx
)],
7026 reg_names
[REGNO (ad
.base
)]);
7028 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
7031 /* Output operand X in assembler syntax to stdio stream FILE.
7032 CODE specified the format flag. The following format flags
7035 'C': print opcode suffix for branch condition.
7036 'D': print opcode suffix for inverse branch condition.
7037 'E': print opcode suffix for branch on index instruction.
7038 'G': print the size of the operand in bytes.
7039 'J': print tls_load/tls_gdcall/tls_ldcall suffix
7040 'M': print the second word of a TImode operand.
7041 'N': print the second word of a DImode operand.
7042 'O': print only the displacement of a memory reference or address.
7043 'R': print only the base register of a memory reference or address.
7044 'S': print S-type memory reference (base+displacement).
7045 'Y': print shift count operand.
7047 'b': print integer X as if it's an unsigned byte.
7048 'c': print integer X as if it's an signed byte.
7049 'e': "end" contiguous bitmask X in either DImode or vector inner mode.
7050 'f': "end" contiguous bitmask X in SImode.
7051 'h': print integer X as if it's a signed halfword.
7052 'i': print the first nonzero HImode part of X.
7053 'j': print the first HImode part unequal to -1 of X.
7054 'k': print the first nonzero SImode part of X.
7055 'm': print the first SImode part unequal to -1 of X.
7056 'o': print integer X as if it's an unsigned 32bit word.
7057 's': "start" of contiguous bitmask X in either DImode or vector inner mode.
7058 't': CONST_INT: "start" of contiguous bitmask X in SImode.
7059 CONST_VECTOR: Generate a bitmask for vgbm instruction.
7060 'x': print integer X as if it's an unsigned halfword.
7061 'v': print register number as vector register (v1 instead of f1).
7065 print_operand (FILE *file
, rtx x
, int code
)
7072 fprintf (file
, s390_branch_condition_mnemonic (x
, FALSE
));
7076 fprintf (file
, s390_branch_condition_mnemonic (x
, TRUE
));
7080 if (GET_CODE (x
) == LE
)
7081 fprintf (file
, "l");
7082 else if (GET_CODE (x
) == GT
)
7083 fprintf (file
, "h");
7085 output_operand_lossage ("invalid comparison operator "
7086 "for 'E' output modifier");
7090 if (GET_CODE (x
) == SYMBOL_REF
)
7092 fprintf (file
, "%s", ":tls_load:");
7093 output_addr_const (file
, x
);
7095 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD
)
7097 fprintf (file
, "%s", ":tls_gdcall:");
7098 output_addr_const (file
, XVECEXP (x
, 0, 0));
7100 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM
)
7102 fprintf (file
, "%s", ":tls_ldcall:");
7103 const char *name
= get_some_local_dynamic_name ();
7105 assemble_name (file
, name
);
7108 output_operand_lossage ("invalid reference for 'J' output modifier");
7112 fprintf (file
, "%u", GET_MODE_SIZE (GET_MODE (x
)));
7117 struct s390_address ad
;
7120 ret
= s390_decompose_address (MEM_P (x
) ? XEXP (x
, 0) : x
, &ad
);
7123 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
7126 output_operand_lossage ("invalid address for 'O' output modifier");
7131 output_addr_const (file
, ad
.disp
);
7133 fprintf (file
, "0");
7139 struct s390_address ad
;
7142 ret
= s390_decompose_address (MEM_P (x
) ? XEXP (x
, 0) : x
, &ad
);
7145 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
7148 output_operand_lossage ("invalid address for 'R' output modifier");
7153 fprintf (file
, "%s", reg_names
[REGNO (ad
.base
)]);
7155 fprintf (file
, "0");
7161 struct s390_address ad
;
7166 output_operand_lossage ("memory reference expected for "
7167 "'S' output modifier");
7170 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
7173 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
7176 output_operand_lossage ("invalid address for 'S' output modifier");
7181 output_addr_const (file
, ad
.disp
);
7183 fprintf (file
, "0");
7186 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
7191 if (GET_CODE (x
) == REG
)
7192 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
7193 else if (GET_CODE (x
) == MEM
)
7194 x
= change_address (x
, VOIDmode
,
7195 plus_constant (Pmode
, XEXP (x
, 0), 4));
7197 output_operand_lossage ("register or memory expression expected "
7198 "for 'N' output modifier");
7202 if (GET_CODE (x
) == REG
)
7203 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
7204 else if (GET_CODE (x
) == MEM
)
7205 x
= change_address (x
, VOIDmode
,
7206 plus_constant (Pmode
, XEXP (x
, 0), 8));
7208 output_operand_lossage ("register or memory expression expected "
7209 "for 'M' output modifier");
7213 print_shift_count_operand (file
, x
);
7217 switch (GET_CODE (x
))
7220 /* Print FP regs as fx instead of vx when they are accessed
7221 through non-vector mode. */
7223 || VECTOR_NOFP_REG_P (x
)
7224 || (FP_REG_P (x
) && VECTOR_MODE_P (GET_MODE (x
)))
7225 || (VECTOR_REG_P (x
)
7226 && (GET_MODE_SIZE (GET_MODE (x
)) /
7227 s390_class_max_nregs (FP_REGS
, GET_MODE (x
))) > 8))
7228 fprintf (file
, "%%v%s", reg_names
[REGNO (x
)] + 2);
7230 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
7234 output_address (GET_MODE (x
), XEXP (x
, 0));
7241 output_addr_const (file
, x
);
7254 ival
= ((ival
& 0xff) ^ 0x80) - 0x80;
7260 ival
= ((ival
& 0xffff) ^ 0x8000) - 0x8000;
7263 ival
= s390_extract_part (x
, HImode
, 0);
7266 ival
= s390_extract_part (x
, HImode
, -1);
7269 ival
= s390_extract_part (x
, SImode
, 0);
7272 ival
= s390_extract_part (x
, SImode
, -1);
7283 len
= (code
== 's' || code
== 'e' ? 64 : 32);
7284 ok
= s390_contiguous_bitmask_p (ival
, len
, &pos
, &len
);
7286 if (code
== 's' || code
== 't')
7287 ival
= 64 - pos
- len
;
7289 ival
= 64 - 1 - pos
;
7293 output_operand_lossage ("invalid constant for output modifier '%c'", code
);
7295 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ival
);
7298 case CONST_WIDE_INT
:
7300 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7301 CONST_WIDE_INT_ELT (x
, 0) & 0xff);
7302 else if (code
== 'x')
7303 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7304 CONST_WIDE_INT_ELT (x
, 0) & 0xffff);
7305 else if (code
== 'h')
7306 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7307 ((CONST_WIDE_INT_ELT (x
, 0) & 0xffff) ^ 0x8000) - 0x8000);
7311 output_operand_lossage ("invalid constant - try using "
7312 "an output modifier");
7314 output_operand_lossage ("invalid constant for output modifier '%c'",
7322 gcc_assert (const_vec_duplicate_p (x
));
7323 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7324 ((INTVAL (XVECEXP (x
, 0, 0)) & 0xffff) ^ 0x8000) - 0x8000);
7329 int start
, stop
, inner_len
;
7332 inner_len
= GET_MODE_UNIT_BITSIZE (GET_MODE (x
));
7333 ok
= s390_contiguous_bitmask_vector_p (x
, &start
, &stop
);
7335 if (code
== 's' || code
== 't')
7336 ival
= inner_len
- stop
- 1;
7338 ival
= inner_len
- start
- 1;
7339 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ival
);
7345 bool ok
= s390_bytemask_vector_p (x
, &mask
);
7347 fprintf (file
, "%u", mask
);
7352 output_operand_lossage ("invalid constant vector for output "
7353 "modifier '%c'", code
);
7359 output_operand_lossage ("invalid expression - try using "
7360 "an output modifier");
7362 output_operand_lossage ("invalid expression for output "
7363 "modifier '%c'", code
);
7368 /* Target hook for assembling integer objects. We need to define it
7369 here to work a round a bug in some versions of GAS, which couldn't
7370 handle values smaller than INT_MIN when printed in decimal. */
7373 s390_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
7375 if (size
== 8 && aligned_p
7376 && GET_CODE (x
) == CONST_INT
&& INTVAL (x
) < INT_MIN
)
7378 fprintf (asm_out_file
, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX
"\n",
7382 return default_assemble_integer (x
, size
, aligned_p
);
7385 /* Returns true if register REGNO is used for forming
7386 a memory address in expression X. */
7389 reg_used_in_mem_p (int regno
, rtx x
)
7391 enum rtx_code code
= GET_CODE (x
);
7397 if (refers_to_regno_p (regno
, XEXP (x
, 0)))
7400 else if (code
== SET
7401 && GET_CODE (SET_DEST (x
)) == PC
)
7403 if (refers_to_regno_p (regno
, SET_SRC (x
)))
7407 fmt
= GET_RTX_FORMAT (code
);
7408 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7411 && reg_used_in_mem_p (regno
, XEXP (x
, i
)))
7414 else if (fmt
[i
] == 'E')
7415 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7416 if (reg_used_in_mem_p (regno
, XVECEXP (x
, i
, j
)))
7422 /* Returns true if expression DEP_RTX sets an address register
7423 used by instruction INSN to address memory. */
7426 addr_generation_dependency_p (rtx dep_rtx
, rtx_insn
*insn
)
7430 if (NONJUMP_INSN_P (dep_rtx
))
7431 dep_rtx
= PATTERN (dep_rtx
);
7433 if (GET_CODE (dep_rtx
) == SET
)
7435 target
= SET_DEST (dep_rtx
);
7436 if (GET_CODE (target
) == STRICT_LOW_PART
)
7437 target
= XEXP (target
, 0);
7438 while (GET_CODE (target
) == SUBREG
)
7439 target
= SUBREG_REG (target
);
7441 if (GET_CODE (target
) == REG
)
7443 int regno
= REGNO (target
);
7445 if (s390_safe_attr_type (insn
) == TYPE_LA
)
7447 pat
= PATTERN (insn
);
7448 if (GET_CODE (pat
) == PARALLEL
)
7450 gcc_assert (XVECLEN (pat
, 0) == 2);
7451 pat
= XVECEXP (pat
, 0, 0);
7453 gcc_assert (GET_CODE (pat
) == SET
);
7454 return refers_to_regno_p (regno
, SET_SRC (pat
));
7456 else if (get_attr_atype (insn
) == ATYPE_AGEN
)
7457 return reg_used_in_mem_p (regno
, PATTERN (insn
));
7463 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
7466 s390_agen_dep_p (rtx_insn
*dep_insn
, rtx_insn
*insn
)
7468 rtx dep_rtx
= PATTERN (dep_insn
);
7471 if (GET_CODE (dep_rtx
) == SET
7472 && addr_generation_dependency_p (dep_rtx
, insn
))
7474 else if (GET_CODE (dep_rtx
) == PARALLEL
)
7476 for (i
= 0; i
< XVECLEN (dep_rtx
, 0); i
++)
7478 if (addr_generation_dependency_p (XVECEXP (dep_rtx
, 0, i
), insn
))
7486 /* A C statement (sans semicolon) to update the integer scheduling priority
7487 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
7488 reduce the priority to execute INSN later. Do not define this macro if
7489 you do not need to adjust the scheduling priorities of insns.
7491 A STD instruction should be scheduled earlier,
7492 in order to use the bypass. */
7494 s390_adjust_priority (rtx_insn
*insn
, int priority
)
7496 if (! INSN_P (insn
))
7499 if (s390_tune
<= PROCESSOR_2064_Z900
)
7502 switch (s390_safe_attr_type (insn
))
7506 priority
= priority
<< 3;
7510 priority
= priority
<< 1;
7519 /* The number of instructions that can be issued per cycle. */
7522 s390_issue_rate (void)
7526 case PROCESSOR_2084_Z990
:
7527 case PROCESSOR_2094_Z9_109
:
7528 case PROCESSOR_2094_Z9_EC
:
7529 case PROCESSOR_2817_Z196
:
7531 case PROCESSOR_2097_Z10
:
7533 case PROCESSOR_9672_G5
:
7534 case PROCESSOR_9672_G6
:
7535 case PROCESSOR_2064_Z900
:
7536 /* Starting with EC12 we use the sched_reorder hook to take care
7537 of instruction dispatch constraints. The algorithm only
7538 picks the best instruction and assumes only a single
7539 instruction gets issued per cycle. */
7540 case PROCESSOR_2827_ZEC12
:
7541 case PROCESSOR_2964_Z13
:
7548 s390_first_cycle_multipass_dfa_lookahead (void)
7553 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
7554 Fix up MEMs as required. */
7557 annotate_constant_pool_refs (rtx
*x
)
7562 gcc_assert (GET_CODE (*x
) != SYMBOL_REF
7563 || !CONSTANT_POOL_ADDRESS_P (*x
));
7565 /* Literal pool references can only occur inside a MEM ... */
7566 if (GET_CODE (*x
) == MEM
)
7568 rtx memref
= XEXP (*x
, 0);
7570 if (GET_CODE (memref
) == SYMBOL_REF
7571 && CONSTANT_POOL_ADDRESS_P (memref
))
7573 rtx base
= cfun
->machine
->base_reg
;
7574 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, memref
, base
),
7577 *x
= replace_equiv_address (*x
, addr
);
7581 if (GET_CODE (memref
) == CONST
7582 && GET_CODE (XEXP (memref
, 0)) == PLUS
7583 && GET_CODE (XEXP (XEXP (memref
, 0), 1)) == CONST_INT
7584 && GET_CODE (XEXP (XEXP (memref
, 0), 0)) == SYMBOL_REF
7585 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref
, 0), 0)))
7587 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (memref
, 0), 1));
7588 rtx sym
= XEXP (XEXP (memref
, 0), 0);
7589 rtx base
= cfun
->machine
->base_reg
;
7590 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
7593 *x
= replace_equiv_address (*x
, plus_constant (Pmode
, addr
, off
));
7598 /* ... or a load-address type pattern. */
7599 if (GET_CODE (*x
) == SET
)
7601 rtx addrref
= SET_SRC (*x
);
7603 if (GET_CODE (addrref
) == SYMBOL_REF
7604 && CONSTANT_POOL_ADDRESS_P (addrref
))
7606 rtx base
= cfun
->machine
->base_reg
;
7607 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, addrref
, base
),
7610 SET_SRC (*x
) = addr
;
7614 if (GET_CODE (addrref
) == CONST
7615 && GET_CODE (XEXP (addrref
, 0)) == PLUS
7616 && GET_CODE (XEXP (XEXP (addrref
, 0), 1)) == CONST_INT
7617 && GET_CODE (XEXP (XEXP (addrref
, 0), 0)) == SYMBOL_REF
7618 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref
, 0), 0)))
7620 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (addrref
, 0), 1));
7621 rtx sym
= XEXP (XEXP (addrref
, 0), 0);
7622 rtx base
= cfun
->machine
->base_reg
;
7623 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
7626 SET_SRC (*x
) = plus_constant (Pmode
, addr
, off
);
7631 /* Annotate LTREL_BASE as well. */
7632 if (GET_CODE (*x
) == UNSPEC
7633 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
7635 rtx base
= cfun
->machine
->base_reg
;
7636 *x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XVECEXP (*x
, 0, 0), base
),
7641 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
7642 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
7646 annotate_constant_pool_refs (&XEXP (*x
, i
));
7648 else if (fmt
[i
] == 'E')
7650 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
7651 annotate_constant_pool_refs (&XVECEXP (*x
, i
, j
));
7656 /* Split all branches that exceed the maximum distance.
7657 Returns true if this created a new literal pool entry. */
7660 s390_split_branches (void)
7662 rtx temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
7663 int new_literal
= 0, ret
;
7668 /* We need correct insn addresses. */
7670 shorten_branches (get_insns ());
7672 /* Find all branches that exceed 64KB, and split them. */
7674 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
7676 if (! JUMP_P (insn
) || tablejump_p (insn
, NULL
, NULL
))
7679 pat
= PATTERN (insn
);
7680 if (GET_CODE (pat
) == PARALLEL
)
7681 pat
= XVECEXP (pat
, 0, 0);
7682 if (GET_CODE (pat
) != SET
|| SET_DEST (pat
) != pc_rtx
)
7685 if (GET_CODE (SET_SRC (pat
)) == LABEL_REF
)
7687 label
= &SET_SRC (pat
);
7689 else if (GET_CODE (SET_SRC (pat
)) == IF_THEN_ELSE
)
7691 if (GET_CODE (XEXP (SET_SRC (pat
), 1)) == LABEL_REF
)
7692 label
= &XEXP (SET_SRC (pat
), 1);
7693 else if (GET_CODE (XEXP (SET_SRC (pat
), 2)) == LABEL_REF
)
7694 label
= &XEXP (SET_SRC (pat
), 2);
7701 if (get_attr_length (insn
) <= 4)
7704 /* We are going to use the return register as scratch register,
7705 make sure it will be saved/restored by the prologue/epilogue. */
7706 cfun_frame_layout
.save_return_addr_p
= 1;
7711 rtx mem
= force_const_mem (Pmode
, *label
);
7712 rtx_insn
*set_insn
= emit_insn_before (gen_rtx_SET (temp_reg
, mem
),
7714 INSN_ADDRESSES_NEW (set_insn
, -1);
7715 annotate_constant_pool_refs (&PATTERN (set_insn
));
7722 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, *label
),
7723 UNSPEC_LTREL_OFFSET
);
7724 target
= gen_rtx_CONST (Pmode
, target
);
7725 target
= force_const_mem (Pmode
, target
);
7726 rtx_insn
*set_insn
= emit_insn_before (gen_rtx_SET (temp_reg
, target
),
7728 INSN_ADDRESSES_NEW (set_insn
, -1);
7729 annotate_constant_pool_refs (&PATTERN (set_insn
));
7731 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XEXP (target
, 0),
7732 cfun
->machine
->base_reg
),
7734 target
= gen_rtx_PLUS (Pmode
, temp_reg
, target
);
7737 ret
= validate_change (insn
, label
, target
, 0);
7745 /* Find an annotated literal pool symbol referenced in RTX X,
7746 and store it at REF. Will abort if X contains references to
7747 more than one such pool symbol; multiple references to the same
7748 symbol are allowed, however.
7750 The rtx pointed to by REF must be initialized to NULL_RTX
7751 by the caller before calling this routine. */
7754 find_constant_pool_ref (rtx x
, rtx
*ref
)
7759 /* Ignore LTREL_BASE references. */
7760 if (GET_CODE (x
) == UNSPEC
7761 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
7763 /* Likewise POOL_ENTRY insns. */
7764 if (GET_CODE (x
) == UNSPEC_VOLATILE
7765 && XINT (x
, 1) == UNSPECV_POOL_ENTRY
)
7768 gcc_assert (GET_CODE (x
) != SYMBOL_REF
7769 || !CONSTANT_POOL_ADDRESS_P (x
));
7771 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_LTREF
)
7773 rtx sym
= XVECEXP (x
, 0, 0);
7774 gcc_assert (GET_CODE (sym
) == SYMBOL_REF
7775 && CONSTANT_POOL_ADDRESS_P (sym
));
7777 if (*ref
== NULL_RTX
)
7780 gcc_assert (*ref
== sym
);
7785 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
7786 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
7790 find_constant_pool_ref (XEXP (x
, i
), ref
);
7792 else if (fmt
[i
] == 'E')
7794 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7795 find_constant_pool_ref (XVECEXP (x
, i
, j
), ref
);
7800 /* Replace every reference to the annotated literal pool
7801 symbol REF in X by its base plus OFFSET. */
7804 replace_constant_pool_ref (rtx
*x
, rtx ref
, rtx offset
)
7809 gcc_assert (*x
!= ref
);
7811 if (GET_CODE (*x
) == UNSPEC
7812 && XINT (*x
, 1) == UNSPEC_LTREF
7813 && XVECEXP (*x
, 0, 0) == ref
)
7815 *x
= gen_rtx_PLUS (Pmode
, XVECEXP (*x
, 0, 1), offset
);
7819 if (GET_CODE (*x
) == PLUS
7820 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
7821 && GET_CODE (XEXP (*x
, 0)) == UNSPEC
7822 && XINT (XEXP (*x
, 0), 1) == UNSPEC_LTREF
7823 && XVECEXP (XEXP (*x
, 0), 0, 0) == ref
)
7825 rtx addr
= gen_rtx_PLUS (Pmode
, XVECEXP (XEXP (*x
, 0), 0, 1), offset
);
7826 *x
= plus_constant (Pmode
, addr
, INTVAL (XEXP (*x
, 1)));
7830 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
7831 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
7835 replace_constant_pool_ref (&XEXP (*x
, i
), ref
, offset
);
7837 else if (fmt
[i
] == 'E')
7839 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
7840 replace_constant_pool_ref (&XVECEXP (*x
, i
, j
), ref
, offset
);
7845 /* Check whether X contains an UNSPEC_LTREL_BASE.
7846 Return its constant pool symbol if found, NULL_RTX otherwise. */
7849 find_ltrel_base (rtx x
)
7854 if (GET_CODE (x
) == UNSPEC
7855 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
7856 return XVECEXP (x
, 0, 0);
7858 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
7859 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
7863 rtx fnd
= find_ltrel_base (XEXP (x
, i
));
7867 else if (fmt
[i
] == 'E')
7869 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7871 rtx fnd
= find_ltrel_base (XVECEXP (x
, i
, j
));
7881 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
7884 replace_ltrel_base (rtx
*x
)
7889 if (GET_CODE (*x
) == UNSPEC
7890 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
7892 *x
= XVECEXP (*x
, 0, 1);
7896 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
7897 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
7901 replace_ltrel_base (&XEXP (*x
, i
));
7903 else if (fmt
[i
] == 'E')
7905 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
7906 replace_ltrel_base (&XVECEXP (*x
, i
, j
));
7912 /* We keep a list of constants which we have to add to internal
7913 constant tables in the middle of large functions. */
7915 #define NR_C_MODES 32
7916 machine_mode constant_modes
[NR_C_MODES
] =
7918 TFmode
, TImode
, TDmode
,
7919 V16QImode
, V8HImode
, V4SImode
, V2DImode
, V1TImode
,
7920 V4SFmode
, V2DFmode
, V1TFmode
,
7921 DFmode
, DImode
, DDmode
,
7922 V8QImode
, V4HImode
, V2SImode
, V1DImode
, V2SFmode
, V1DFmode
,
7923 SFmode
, SImode
, SDmode
,
7924 V4QImode
, V2HImode
, V1SImode
, V1SFmode
,
7933 struct constant
*next
;
7935 rtx_code_label
*label
;
7938 struct constant_pool
7940 struct constant_pool
*next
;
7941 rtx_insn
*first_insn
;
7942 rtx_insn
*pool_insn
;
7944 rtx_insn
*emit_pool_after
;
7946 struct constant
*constants
[NR_C_MODES
];
7947 struct constant
*execute
;
7948 rtx_code_label
*label
;
7952 /* Allocate new constant_pool structure. */
7954 static struct constant_pool
*
7955 s390_alloc_pool (void)
7957 struct constant_pool
*pool
;
7960 pool
= (struct constant_pool
*) xmalloc (sizeof *pool
);
7962 for (i
= 0; i
< NR_C_MODES
; i
++)
7963 pool
->constants
[i
] = NULL
;
7965 pool
->execute
= NULL
;
7966 pool
->label
= gen_label_rtx ();
7967 pool
->first_insn
= NULL
;
7968 pool
->pool_insn
= NULL
;
7969 pool
->insns
= BITMAP_ALLOC (NULL
);
7971 pool
->emit_pool_after
= NULL
;
7976 /* Create new constant pool covering instructions starting at INSN
7977 and chain it to the end of POOL_LIST. */
7979 static struct constant_pool
*
7980 s390_start_pool (struct constant_pool
**pool_list
, rtx_insn
*insn
)
7982 struct constant_pool
*pool
, **prev
;
7984 pool
= s390_alloc_pool ();
7985 pool
->first_insn
= insn
;
7987 for (prev
= pool_list
; *prev
; prev
= &(*prev
)->next
)
7994 /* End range of instructions covered by POOL at INSN and emit
7995 placeholder insn representing the pool. */
7998 s390_end_pool (struct constant_pool
*pool
, rtx_insn
*insn
)
8000 rtx pool_size
= GEN_INT (pool
->size
+ 8 /* alignment slop */);
8003 insn
= get_last_insn ();
8005 pool
->pool_insn
= emit_insn_after (gen_pool (pool_size
), insn
);
8006 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
8009 /* Add INSN to the list of insns covered by POOL. */
8012 s390_add_pool_insn (struct constant_pool
*pool
, rtx insn
)
8014 bitmap_set_bit (pool
->insns
, INSN_UID (insn
));
8017 /* Return pool out of POOL_LIST that covers INSN. */
8019 static struct constant_pool
*
8020 s390_find_pool (struct constant_pool
*pool_list
, rtx insn
)
8022 struct constant_pool
*pool
;
8024 for (pool
= pool_list
; pool
; pool
= pool
->next
)
8025 if (bitmap_bit_p (pool
->insns
, INSN_UID (insn
)))
8031 /* Add constant VAL of mode MODE to the constant pool POOL. */
8034 s390_add_constant (struct constant_pool
*pool
, rtx val
, machine_mode mode
)
8039 for (i
= 0; i
< NR_C_MODES
; i
++)
8040 if (constant_modes
[i
] == mode
)
8042 gcc_assert (i
!= NR_C_MODES
);
8044 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
8045 if (rtx_equal_p (val
, c
->value
))
8050 c
= (struct constant
*) xmalloc (sizeof *c
);
8052 c
->label
= gen_label_rtx ();
8053 c
->next
= pool
->constants
[i
];
8054 pool
->constants
[i
] = c
;
8055 pool
->size
+= GET_MODE_SIZE (mode
);
8059 /* Return an rtx that represents the offset of X from the start of
8063 s390_pool_offset (struct constant_pool
*pool
, rtx x
)
8067 label
= gen_rtx_LABEL_REF (GET_MODE (x
), pool
->label
);
8068 x
= gen_rtx_UNSPEC (GET_MODE (x
), gen_rtvec (2, x
, label
),
8069 UNSPEC_POOL_OFFSET
);
8070 return gen_rtx_CONST (GET_MODE (x
), x
);
8073 /* Find constant VAL of mode MODE in the constant pool POOL.
8074 Return an RTX describing the distance from the start of
8075 the pool to the location of the new constant. */
8078 s390_find_constant (struct constant_pool
*pool
, rtx val
,
8084 for (i
= 0; i
< NR_C_MODES
; i
++)
8085 if (constant_modes
[i
] == mode
)
8087 gcc_assert (i
!= NR_C_MODES
);
8089 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
8090 if (rtx_equal_p (val
, c
->value
))
8095 return s390_pool_offset (pool
, gen_rtx_LABEL_REF (Pmode
, c
->label
));
8098 /* Check whether INSN is an execute. Return the label_ref to its
8099 execute target template if so, NULL_RTX otherwise. */
8102 s390_execute_label (rtx insn
)
8104 if (NONJUMP_INSN_P (insn
)
8105 && GET_CODE (PATTERN (insn
)) == PARALLEL
8106 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == UNSPEC
8107 && XINT (XVECEXP (PATTERN (insn
), 0, 0), 1) == UNSPEC_EXECUTE
)
8108 return XVECEXP (XVECEXP (PATTERN (insn
), 0, 0), 0, 2);
8113 /* Add execute target for INSN to the constant pool POOL. */
8116 s390_add_execute (struct constant_pool
*pool
, rtx insn
)
8120 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
8121 if (INSN_UID (insn
) == INSN_UID (c
->value
))
8126 c
= (struct constant
*) xmalloc (sizeof *c
);
8128 c
->label
= gen_label_rtx ();
8129 c
->next
= pool
->execute
;
8135 /* Find execute target for INSN in the constant pool POOL.
8136 Return an RTX describing the distance from the start of
8137 the pool to the location of the execute target. */
8140 s390_find_execute (struct constant_pool
*pool
, rtx insn
)
8144 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
8145 if (INSN_UID (insn
) == INSN_UID (c
->value
))
8150 return s390_pool_offset (pool
, gen_rtx_LABEL_REF (Pmode
, c
->label
));
8153 /* For an execute INSN, extract the execute target template. */
8156 s390_execute_target (rtx insn
)
8158 rtx pattern
= PATTERN (insn
);
8159 gcc_assert (s390_execute_label (insn
));
8161 if (XVECLEN (pattern
, 0) == 2)
8163 pattern
= copy_rtx (XVECEXP (pattern
, 0, 1));
8167 rtvec vec
= rtvec_alloc (XVECLEN (pattern
, 0) - 1);
8170 for (i
= 0; i
< XVECLEN (pattern
, 0) - 1; i
++)
8171 RTVEC_ELT (vec
, i
) = copy_rtx (XVECEXP (pattern
, 0, i
+ 1));
8173 pattern
= gen_rtx_PARALLEL (VOIDmode
, vec
);
8179 /* Indicate that INSN cannot be duplicated. This is the case for
8180 execute insns that carry a unique label. */
8183 s390_cannot_copy_insn_p (rtx_insn
*insn
)
8185 rtx label
= s390_execute_label (insn
);
8186 return label
&& label
!= const0_rtx
;
8189 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
8190 do not emit the pool base label. */
8193 s390_dump_pool (struct constant_pool
*pool
, bool remote_label
)
8196 rtx_insn
*insn
= pool
->pool_insn
;
8199 /* Switch to rodata section. */
8200 if (TARGET_CPU_ZARCH
)
8202 insn
= emit_insn_after (gen_pool_section_start (), insn
);
8203 INSN_ADDRESSES_NEW (insn
, -1);
8206 /* Ensure minimum pool alignment. */
8207 if (TARGET_CPU_ZARCH
)
8208 insn
= emit_insn_after (gen_pool_align (GEN_INT (8)), insn
);
8210 insn
= emit_insn_after (gen_pool_align (GEN_INT (4)), insn
);
8211 INSN_ADDRESSES_NEW (insn
, -1);
8213 /* Emit pool base label. */
8216 insn
= emit_label_after (pool
->label
, insn
);
8217 INSN_ADDRESSES_NEW (insn
, -1);
8220 /* Dump constants in descending alignment requirement order,
8221 ensuring proper alignment for every constant. */
8222 for (i
= 0; i
< NR_C_MODES
; i
++)
8223 for (c
= pool
->constants
[i
]; c
; c
= c
->next
)
8225 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
8226 rtx value
= copy_rtx (c
->value
);
8227 if (GET_CODE (value
) == CONST
8228 && GET_CODE (XEXP (value
, 0)) == UNSPEC
8229 && XINT (XEXP (value
, 0), 1) == UNSPEC_LTREL_OFFSET
8230 && XVECLEN (XEXP (value
, 0), 0) == 1)
8231 value
= s390_pool_offset (pool
, XVECEXP (XEXP (value
, 0), 0, 0));
8233 insn
= emit_label_after (c
->label
, insn
);
8234 INSN_ADDRESSES_NEW (insn
, -1);
8236 value
= gen_rtx_UNSPEC_VOLATILE (constant_modes
[i
],
8237 gen_rtvec (1, value
),
8238 UNSPECV_POOL_ENTRY
);
8239 insn
= emit_insn_after (value
, insn
);
8240 INSN_ADDRESSES_NEW (insn
, -1);
8243 /* Ensure minimum alignment for instructions. */
8244 insn
= emit_insn_after (gen_pool_align (GEN_INT (2)), insn
);
8245 INSN_ADDRESSES_NEW (insn
, -1);
8247 /* Output in-pool execute template insns. */
8248 for (c
= pool
->execute
; c
; c
= c
->next
)
8250 insn
= emit_label_after (c
->label
, insn
);
8251 INSN_ADDRESSES_NEW (insn
, -1);
8253 insn
= emit_insn_after (s390_execute_target (c
->value
), insn
);
8254 INSN_ADDRESSES_NEW (insn
, -1);
8257 /* Switch back to previous section. */
8258 if (TARGET_CPU_ZARCH
)
8260 insn
= emit_insn_after (gen_pool_section_end (), insn
);
8261 INSN_ADDRESSES_NEW (insn
, -1);
8264 insn
= emit_barrier_after (insn
);
8265 INSN_ADDRESSES_NEW (insn
, -1);
8267 /* Remove placeholder insn. */
8268 remove_insn (pool
->pool_insn
);
8271 /* Free all memory used by POOL. */
8274 s390_free_pool (struct constant_pool
*pool
)
8276 struct constant
*c
, *next
;
8279 for (i
= 0; i
< NR_C_MODES
; i
++)
8280 for (c
= pool
->constants
[i
]; c
; c
= next
)
8286 for (c
= pool
->execute
; c
; c
= next
)
8292 BITMAP_FREE (pool
->insns
);
8297 /* Collect main literal pool. Return NULL on overflow. */
8299 static struct constant_pool
*
8300 s390_mainpool_start (void)
8302 struct constant_pool
*pool
;
8305 pool
= s390_alloc_pool ();
8307 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8309 if (NONJUMP_INSN_P (insn
)
8310 && GET_CODE (PATTERN (insn
)) == SET
8311 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC_VOLATILE
8312 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPECV_MAIN_POOL
)
8314 /* There might be two main_pool instructions if base_reg
8315 is call-clobbered; one for shrink-wrapped code and one
8316 for the rest. We want to keep the first. */
8317 if (pool
->pool_insn
)
8319 insn
= PREV_INSN (insn
);
8320 delete_insn (NEXT_INSN (insn
));
8323 pool
->pool_insn
= insn
;
8326 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
8328 s390_add_execute (pool
, insn
);
8330 else if (NONJUMP_INSN_P (insn
) || CALL_P (insn
))
8332 rtx pool_ref
= NULL_RTX
;
8333 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
8336 rtx constant
= get_pool_constant (pool_ref
);
8337 machine_mode mode
= get_pool_mode (pool_ref
);
8338 s390_add_constant (pool
, constant
, mode
);
8342 /* If hot/cold partitioning is enabled we have to make sure that
8343 the literal pool is emitted in the same section where the
8344 initialization of the literal pool base pointer takes place.
8345 emit_pool_after is only used in the non-overflow case on non
8346 Z cpus where we can emit the literal pool at the end of the
8347 function body within the text section. */
8349 && NOTE_KIND (insn
) == NOTE_INSN_SWITCH_TEXT_SECTIONS
8350 && !pool
->emit_pool_after
)
8351 pool
->emit_pool_after
= PREV_INSN (insn
);
8354 gcc_assert (pool
->pool_insn
|| pool
->size
== 0);
8356 if (pool
->size
>= 4096)
8358 /* We're going to chunkify the pool, so remove the main
8359 pool placeholder insn. */
8360 remove_insn (pool
->pool_insn
);
8362 s390_free_pool (pool
);
8366 /* If the functions ends with the section where the literal pool
8367 should be emitted set the marker to its end. */
8368 if (pool
&& !pool
->emit_pool_after
)
8369 pool
->emit_pool_after
= get_last_insn ();
8374 /* POOL holds the main literal pool as collected by s390_mainpool_start.
8375 Modify the current function to output the pool constants as well as
8376 the pool register setup instruction. */
8379 s390_mainpool_finish (struct constant_pool
*pool
)
8381 rtx base_reg
= cfun
->machine
->base_reg
;
8383 /* If the pool is empty, we're done. */
8384 if (pool
->size
== 0)
8386 /* We don't actually need a base register after all. */
8387 cfun
->machine
->base_reg
= NULL_RTX
;
8389 if (pool
->pool_insn
)
8390 remove_insn (pool
->pool_insn
);
8391 s390_free_pool (pool
);
8395 /* We need correct insn addresses. */
8396 shorten_branches (get_insns ());
8398 /* On zSeries, we use a LARL to load the pool register. The pool is
8399 located in the .rodata section, so we emit it after the function. */
8400 if (TARGET_CPU_ZARCH
)
8402 rtx set
= gen_main_base_64 (base_reg
, pool
->label
);
8403 rtx_insn
*insn
= emit_insn_after (set
, pool
->pool_insn
);
8404 INSN_ADDRESSES_NEW (insn
, -1);
8405 remove_insn (pool
->pool_insn
);
8407 insn
= get_last_insn ();
8408 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
8409 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
8411 s390_dump_pool (pool
, 0);
8414 /* On S/390, if the total size of the function's code plus literal pool
8415 does not exceed 4096 bytes, we use BASR to set up a function base
8416 pointer, and emit the literal pool at the end of the function. */
8417 else if (INSN_ADDRESSES (INSN_UID (pool
->emit_pool_after
))
8418 + pool
->size
+ 8 /* alignment slop */ < 4096)
8420 rtx set
= gen_main_base_31_small (base_reg
, pool
->label
);
8421 rtx_insn
*insn
= emit_insn_after (set
, pool
->pool_insn
);
8422 INSN_ADDRESSES_NEW (insn
, -1);
8423 remove_insn (pool
->pool_insn
);
8425 insn
= emit_label_after (pool
->label
, insn
);
8426 INSN_ADDRESSES_NEW (insn
, -1);
8428 /* emit_pool_after will be set by s390_mainpool_start to the
8429 last insn of the section where the literal pool should be
8431 insn
= pool
->emit_pool_after
;
8433 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
8434 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
8436 s390_dump_pool (pool
, 1);
8439 /* Otherwise, we emit an inline literal pool and use BASR to branch
8440 over it, setting up the pool register at the same time. */
8443 rtx_code_label
*pool_end
= gen_label_rtx ();
8445 rtx pat
= gen_main_base_31_large (base_reg
, pool
->label
, pool_end
);
8446 rtx_insn
*insn
= emit_jump_insn_after (pat
, pool
->pool_insn
);
8447 JUMP_LABEL (insn
) = pool_end
;
8448 INSN_ADDRESSES_NEW (insn
, -1);
8449 remove_insn (pool
->pool_insn
);
8451 insn
= emit_label_after (pool
->label
, insn
);
8452 INSN_ADDRESSES_NEW (insn
, -1);
8454 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
8455 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
8457 insn
= emit_label_after (pool_end
, pool
->pool_insn
);
8458 INSN_ADDRESSES_NEW (insn
, -1);
8460 s390_dump_pool (pool
, 1);
8464 /* Replace all literal pool references. */
8466 for (rtx_insn
*insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8469 replace_ltrel_base (&PATTERN (insn
));
8471 if (NONJUMP_INSN_P (insn
) || CALL_P (insn
))
8473 rtx addr
, pool_ref
= NULL_RTX
;
8474 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
8477 if (s390_execute_label (insn
))
8478 addr
= s390_find_execute (pool
, insn
);
8480 addr
= s390_find_constant (pool
, get_pool_constant (pool_ref
),
8481 get_pool_mode (pool_ref
));
8483 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
8484 INSN_CODE (insn
) = -1;
8490 /* Free the pool. */
8491 s390_free_pool (pool
);
8494 /* POOL holds the main literal pool as collected by s390_mainpool_start.
8495 We have decided we cannot use this pool, so revert all changes
8496 to the current function that were done by s390_mainpool_start. */
8498 s390_mainpool_cancel (struct constant_pool
*pool
)
8500 /* We didn't actually change the instruction stream, so simply
8501 free the pool memory. */
8502 s390_free_pool (pool
);
8506 /* Chunkify the literal pool. */
8508 #define S390_POOL_CHUNK_MIN 0xc00
8509 #define S390_POOL_CHUNK_MAX 0xe00
8511 static struct constant_pool
*
8512 s390_chunkify_start (void)
8514 struct constant_pool
*curr_pool
= NULL
, *pool_list
= NULL
;
8517 rtx pending_ltrel
= NULL_RTX
;
8520 rtx (*gen_reload_base
) (rtx
, rtx
) =
8521 TARGET_CPU_ZARCH
? gen_reload_base_64
: gen_reload_base_31
;
8524 /* We need correct insn addresses. */
8526 shorten_branches (get_insns ());
8528 /* Scan all insns and move literals to pool chunks. */
8530 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8532 bool section_switch_p
= false;
8534 /* Check for pending LTREL_BASE. */
8537 rtx ltrel_base
= find_ltrel_base (PATTERN (insn
));
8540 gcc_assert (ltrel_base
== pending_ltrel
);
8541 pending_ltrel
= NULL_RTX
;
8545 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
8548 curr_pool
= s390_start_pool (&pool_list
, insn
);
8550 s390_add_execute (curr_pool
, insn
);
8551 s390_add_pool_insn (curr_pool
, insn
);
8553 else if (NONJUMP_INSN_P (insn
) || CALL_P (insn
))
8555 rtx pool_ref
= NULL_RTX
;
8556 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
8559 rtx constant
= get_pool_constant (pool_ref
);
8560 machine_mode mode
= get_pool_mode (pool_ref
);
8563 curr_pool
= s390_start_pool (&pool_list
, insn
);
8565 s390_add_constant (curr_pool
, constant
, mode
);
8566 s390_add_pool_insn (curr_pool
, insn
);
8568 /* Don't split the pool chunk between a LTREL_OFFSET load
8569 and the corresponding LTREL_BASE. */
8570 if (GET_CODE (constant
) == CONST
8571 && GET_CODE (XEXP (constant
, 0)) == UNSPEC
8572 && XINT (XEXP (constant
, 0), 1) == UNSPEC_LTREL_OFFSET
)
8574 gcc_assert (!pending_ltrel
);
8575 pending_ltrel
= pool_ref
;
8580 if (JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
) || LABEL_P (insn
))
8583 s390_add_pool_insn (curr_pool
, insn
);
8584 /* An LTREL_BASE must follow within the same basic block. */
8585 gcc_assert (!pending_ltrel
);
8589 switch (NOTE_KIND (insn
))
8591 case NOTE_INSN_SWITCH_TEXT_SECTIONS
:
8592 section_switch_p
= true;
8594 case NOTE_INSN_VAR_LOCATION
:
8595 case NOTE_INSN_CALL_ARG_LOCATION
:
8602 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn
)
8603 || INSN_ADDRESSES (INSN_UID (insn
)) == -1)
8606 if (TARGET_CPU_ZARCH
)
8608 if (curr_pool
->size
< S390_POOL_CHUNK_MAX
)
8611 s390_end_pool (curr_pool
, NULL
);
8616 int chunk_size
= INSN_ADDRESSES (INSN_UID (insn
))
8617 - INSN_ADDRESSES (INSN_UID (curr_pool
->first_insn
))
8620 /* We will later have to insert base register reload insns.
8621 Those will have an effect on code size, which we need to
8622 consider here. This calculation makes rather pessimistic
8623 worst-case assumptions. */
8627 if (chunk_size
< S390_POOL_CHUNK_MIN
8628 && curr_pool
->size
< S390_POOL_CHUNK_MIN
8629 && !section_switch_p
)
8632 /* Pool chunks can only be inserted after BARRIERs ... */
8633 if (BARRIER_P (insn
))
8635 s390_end_pool (curr_pool
, insn
);
8640 /* ... so if we don't find one in time, create one. */
8641 else if (chunk_size
> S390_POOL_CHUNK_MAX
8642 || curr_pool
->size
> S390_POOL_CHUNK_MAX
8643 || section_switch_p
)
8645 rtx_insn
*label
, *jump
, *barrier
, *next
, *prev
;
8647 if (!section_switch_p
)
8649 /* We can insert the barrier only after a 'real' insn. */
8650 if (! NONJUMP_INSN_P (insn
) && ! CALL_P (insn
))
8652 if (get_attr_length (insn
) == 0)
8654 /* Don't separate LTREL_BASE from the corresponding
8655 LTREL_OFFSET load. */
8662 next
= NEXT_INSN (insn
);
8666 && (NOTE_KIND (next
) == NOTE_INSN_VAR_LOCATION
8667 || NOTE_KIND (next
) == NOTE_INSN_CALL_ARG_LOCATION
));
8671 gcc_assert (!pending_ltrel
);
8673 /* The old pool has to end before the section switch
8674 note in order to make it part of the current
8676 insn
= PREV_INSN (insn
);
8679 label
= gen_label_rtx ();
8681 if (prev
&& NOTE_P (prev
))
8682 prev
= prev_nonnote_insn (prev
);
8684 jump
= emit_jump_insn_after_setloc (gen_jump (label
), insn
,
8685 INSN_LOCATION (prev
));
8687 jump
= emit_jump_insn_after_noloc (gen_jump (label
), insn
);
8688 barrier
= emit_barrier_after (jump
);
8689 insn
= emit_label_after (label
, barrier
);
8690 JUMP_LABEL (jump
) = label
;
8691 LABEL_NUSES (label
) = 1;
8693 INSN_ADDRESSES_NEW (jump
, -1);
8694 INSN_ADDRESSES_NEW (barrier
, -1);
8695 INSN_ADDRESSES_NEW (insn
, -1);
8697 s390_end_pool (curr_pool
, barrier
);
8705 s390_end_pool (curr_pool
, NULL
);
8706 gcc_assert (!pending_ltrel
);
8708 /* Find all labels that are branched into
8709 from an insn belonging to a different chunk. */
8711 far_labels
= BITMAP_ALLOC (NULL
);
8713 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8715 rtx_jump_table_data
*table
;
8717 /* Labels marked with LABEL_PRESERVE_P can be target
8718 of non-local jumps, so we have to mark them.
8719 The same holds for named labels.
8721 Don't do that, however, if it is the label before
8725 && (LABEL_PRESERVE_P (insn
) || LABEL_NAME (insn
)))
8727 rtx_insn
*vec_insn
= NEXT_INSN (insn
);
8728 if (! vec_insn
|| ! JUMP_TABLE_DATA_P (vec_insn
))
8729 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (insn
));
8731 /* Check potential targets in a table jump (casesi_jump). */
8732 else if (tablejump_p (insn
, NULL
, &table
))
8734 rtx vec_pat
= PATTERN (table
);
8735 int i
, diff_p
= GET_CODE (vec_pat
) == ADDR_DIFF_VEC
;
8737 for (i
= 0; i
< XVECLEN (vec_pat
, diff_p
); i
++)
8739 rtx label
= XEXP (XVECEXP (vec_pat
, diff_p
, i
), 0);
8741 if (s390_find_pool (pool_list
, label
)
8742 != s390_find_pool (pool_list
, insn
))
8743 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
8746 /* If we have a direct jump (conditional or unconditional),
8747 check all potential targets. */
8748 else if (JUMP_P (insn
))
8750 rtx pat
= PATTERN (insn
);
8752 if (GET_CODE (pat
) == PARALLEL
)
8753 pat
= XVECEXP (pat
, 0, 0);
8755 if (GET_CODE (pat
) == SET
)
8757 rtx label
= JUMP_LABEL (insn
);
8758 if (label
&& !ANY_RETURN_P (label
))
8760 if (s390_find_pool (pool_list
, label
)
8761 != s390_find_pool (pool_list
, insn
))
8762 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
8768 /* Insert base register reload insns before every pool. */
8770 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
8772 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
8774 rtx_insn
*insn
= curr_pool
->first_insn
;
8775 INSN_ADDRESSES_NEW (emit_insn_before (new_insn
, insn
), -1);
8778 /* Insert base register reload insns at every far label. */
8780 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8782 && bitmap_bit_p (far_labels
, CODE_LABEL_NUMBER (insn
)))
8784 struct constant_pool
*pool
= s390_find_pool (pool_list
, insn
);
8787 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
8789 INSN_ADDRESSES_NEW (emit_insn_after (new_insn
, insn
), -1);
8794 BITMAP_FREE (far_labels
);
8797 /* Recompute insn addresses. */
8799 init_insn_lengths ();
8800 shorten_branches (get_insns ());
8805 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
8806 After we have decided to use this list, finish implementing
8807 all changes to the current function as required. */
8810 s390_chunkify_finish (struct constant_pool
*pool_list
)
8812 struct constant_pool
*curr_pool
= NULL
;
8816 /* Replace all literal pool references. */
8818 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8821 replace_ltrel_base (&PATTERN (insn
));
8823 curr_pool
= s390_find_pool (pool_list
, insn
);
8827 if (NONJUMP_INSN_P (insn
) || CALL_P (insn
))
8829 rtx addr
, pool_ref
= NULL_RTX
;
8830 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
8833 if (s390_execute_label (insn
))
8834 addr
= s390_find_execute (curr_pool
, insn
);
8836 addr
= s390_find_constant (curr_pool
,
8837 get_pool_constant (pool_ref
),
8838 get_pool_mode (pool_ref
));
8840 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
8841 INSN_CODE (insn
) = -1;
8846 /* Dump out all literal pools. */
8848 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
8849 s390_dump_pool (curr_pool
, 0);
8851 /* Free pool list. */
8855 struct constant_pool
*next
= pool_list
->next
;
8856 s390_free_pool (pool_list
);
8861 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
8862 We have decided we cannot use this list, so revert all changes
8863 to the current function that were done by s390_chunkify_start. */
8866 s390_chunkify_cancel (struct constant_pool
*pool_list
)
8868 struct constant_pool
*curr_pool
= NULL
;
8871 /* Remove all pool placeholder insns. */
8873 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
8875 /* Did we insert an extra barrier? Remove it. */
8876 rtx_insn
*barrier
= PREV_INSN (curr_pool
->pool_insn
);
8877 rtx_insn
*jump
= barrier
? PREV_INSN (barrier
) : NULL
;
8878 rtx_insn
*label
= NEXT_INSN (curr_pool
->pool_insn
);
8880 if (jump
&& JUMP_P (jump
)
8881 && barrier
&& BARRIER_P (barrier
)
8882 && label
&& LABEL_P (label
)
8883 && GET_CODE (PATTERN (jump
)) == SET
8884 && SET_DEST (PATTERN (jump
)) == pc_rtx
8885 && GET_CODE (SET_SRC (PATTERN (jump
))) == LABEL_REF
8886 && XEXP (SET_SRC (PATTERN (jump
)), 0) == label
)
8889 remove_insn (barrier
);
8890 remove_insn (label
);
8893 remove_insn (curr_pool
->pool_insn
);
8896 /* Remove all base register reload insns. */
8898 for (insn
= get_insns (); insn
; )
8900 rtx_insn
*next_insn
= NEXT_INSN (insn
);
8902 if (NONJUMP_INSN_P (insn
)
8903 && GET_CODE (PATTERN (insn
)) == SET
8904 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC
8905 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPEC_RELOAD_BASE
)
8911 /* Free pool list. */
8915 struct constant_pool
*next
= pool_list
->next
;
8916 s390_free_pool (pool_list
);
8921 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
8924 s390_output_pool_entry (rtx exp
, machine_mode mode
, unsigned int align
)
8926 switch (GET_MODE_CLASS (mode
))
8929 case MODE_DECIMAL_FLOAT
:
8930 gcc_assert (GET_CODE (exp
) == CONST_DOUBLE
);
8932 assemble_real (*CONST_DOUBLE_REAL_VALUE (exp
), mode
, align
);
8936 assemble_integer (exp
, GET_MODE_SIZE (mode
), align
, 1);
8937 mark_symbol_refs_as_used (exp
);
8940 case MODE_VECTOR_INT
:
8941 case MODE_VECTOR_FLOAT
:
8944 machine_mode inner_mode
;
8945 gcc_assert (GET_CODE (exp
) == CONST_VECTOR
);
8947 inner_mode
= GET_MODE_INNER (GET_MODE (exp
));
8948 for (i
= 0; i
< XVECLEN (exp
, 0); i
++)
8949 s390_output_pool_entry (XVECEXP (exp
, 0, i
),
8953 : GET_MODE_BITSIZE (inner_mode
));
8963 /* Return an RTL expression representing the value of the return address
8964 for the frame COUNT steps up from the current frame. FRAME is the
8965 frame pointer of that frame. */
8968 s390_return_addr_rtx (int count
, rtx frame ATTRIBUTE_UNUSED
)
8973 /* Without backchain, we fail for all but the current frame. */
8975 if (!TARGET_BACKCHAIN
&& count
> 0)
8978 /* For the current frame, we need to make sure the initial
8979 value of RETURN_REGNUM is actually saved. */
8983 /* On non-z architectures branch splitting could overwrite r14. */
8984 if (TARGET_CPU_ZARCH
)
8985 return get_hard_reg_initial_val (Pmode
, RETURN_REGNUM
);
8988 cfun_frame_layout
.save_return_addr_p
= true;
8989 return gen_rtx_MEM (Pmode
, return_address_pointer_rtx
);
8993 if (TARGET_PACKED_STACK
)
8994 offset
= -2 * UNITS_PER_LONG
;
8996 offset
= RETURN_REGNUM
* UNITS_PER_LONG
;
8998 addr
= plus_constant (Pmode
, frame
, offset
);
8999 addr
= memory_address (Pmode
, addr
);
9000 return gen_rtx_MEM (Pmode
, addr
);
9003 /* Return an RTL expression representing the back chain stored in
9004 the current stack frame. */
9007 s390_back_chain_rtx (void)
9011 gcc_assert (TARGET_BACKCHAIN
);
9013 if (TARGET_PACKED_STACK
)
9014 chain
= plus_constant (Pmode
, stack_pointer_rtx
,
9015 STACK_POINTER_OFFSET
- UNITS_PER_LONG
);
9017 chain
= stack_pointer_rtx
;
9019 chain
= gen_rtx_MEM (Pmode
, chain
);
9023 /* Find first call clobbered register unused in a function.
9024 This could be used as base register in a leaf function
9025 or for holding the return address before epilogue. */
9028 find_unused_clobbered_reg (void)
9031 for (i
= 0; i
< 6; i
++)
9032 if (!df_regs_ever_live_p (i
))
9038 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
9039 clobbered hard regs in SETREG. */
9042 s390_reg_clobbered_rtx (rtx setreg
, const_rtx set_insn ATTRIBUTE_UNUSED
, void *data
)
9044 char *regs_ever_clobbered
= (char *)data
;
9045 unsigned int i
, regno
;
9046 machine_mode mode
= GET_MODE (setreg
);
9048 if (GET_CODE (setreg
) == SUBREG
)
9050 rtx inner
= SUBREG_REG (setreg
);
9051 if (!GENERAL_REG_P (inner
) && !FP_REG_P (inner
))
9053 regno
= subreg_regno (setreg
);
9055 else if (GENERAL_REG_P (setreg
) || FP_REG_P (setreg
))
9056 regno
= REGNO (setreg
);
9061 i
< regno
+ HARD_REGNO_NREGS (regno
, mode
);
9063 regs_ever_clobbered
[i
] = 1;
9066 /* Walks through all basic blocks of the current function looking
9067 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
9068 of the passed integer array REGS_EVER_CLOBBERED are set to one for
9069 each of those regs. */
9072 s390_regs_ever_clobbered (char regs_ever_clobbered
[])
9078 memset (regs_ever_clobbered
, 0, 32);
9080 /* For non-leaf functions we have to consider all call clobbered regs to be
9084 for (i
= 0; i
< 32; i
++)
9085 regs_ever_clobbered
[i
] = call_really_used_regs
[i
];
9088 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
9089 this work is done by liveness analysis (mark_regs_live_at_end).
9090 Special care is needed for functions containing landing pads. Landing pads
9091 may use the eh registers, but the code which sets these registers is not
9092 contained in that function. Hence s390_regs_ever_clobbered is not able to
9093 deal with this automatically. */
9094 if (crtl
->calls_eh_return
|| cfun
->machine
->has_landing_pad_p
)
9095 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
9096 if (crtl
->calls_eh_return
9097 || (cfun
->machine
->has_landing_pad_p
9098 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i
))))
9099 regs_ever_clobbered
[EH_RETURN_DATA_REGNO (i
)] = 1;
9101 /* For nonlocal gotos all call-saved registers have to be saved.
9102 This flag is also set for the unwinding code in libgcc.
9103 See expand_builtin_unwind_init. For regs_ever_live this is done by
9105 if (crtl
->saves_all_registers
)
9106 for (i
= 0; i
< 32; i
++)
9107 if (!call_really_used_regs
[i
])
9108 regs_ever_clobbered
[i
] = 1;
9110 FOR_EACH_BB_FN (cur_bb
, cfun
)
9112 FOR_BB_INSNS (cur_bb
, cur_insn
)
9116 if (!INSN_P (cur_insn
))
9119 pat
= PATTERN (cur_insn
);
9121 /* Ignore GPR restore insns. */
9122 if (epilogue_completed
&& RTX_FRAME_RELATED_P (cur_insn
))
9124 if (GET_CODE (pat
) == SET
9125 && GENERAL_REG_P (SET_DEST (pat
)))
9128 if (GET_MODE (SET_SRC (pat
)) == DImode
9129 && FP_REG_P (SET_SRC (pat
)))
9133 if (GET_CODE (SET_SRC (pat
)) == MEM
)
9138 if (GET_CODE (pat
) == PARALLEL
9139 && load_multiple_operation (pat
, VOIDmode
))
9144 s390_reg_clobbered_rtx
,
9145 regs_ever_clobbered
);
9150 /* Determine the frame area which actually has to be accessed
9151 in the function epilogue. The values are stored at the
9152 given pointers AREA_BOTTOM (address of the lowest used stack
9153 address) and AREA_TOP (address of the first item which does
9154 not belong to the stack frame). */
9157 s390_frame_area (int *area_bottom
, int *area_top
)
9164 if (cfun_frame_layout
.first_restore_gpr
!= -1)
9166 b
= (cfun_frame_layout
.gprs_offset
9167 + cfun_frame_layout
.first_restore_gpr
* UNITS_PER_LONG
);
9168 t
= b
+ (cfun_frame_layout
.last_restore_gpr
9169 - cfun_frame_layout
.first_restore_gpr
+ 1) * UNITS_PER_LONG
;
9172 if (TARGET_64BIT
&& cfun_save_high_fprs_p
)
9174 b
= MIN (b
, cfun_frame_layout
.f8_offset
);
9175 t
= MAX (t
, (cfun_frame_layout
.f8_offset
9176 + cfun_frame_layout
.high_fprs
* 8));
9181 if (cfun_fpr_save_p (FPR4_REGNUM
))
9183 b
= MIN (b
, cfun_frame_layout
.f4_offset
);
9184 t
= MAX (t
, cfun_frame_layout
.f4_offset
+ 8);
9186 if (cfun_fpr_save_p (FPR6_REGNUM
))
9188 b
= MIN (b
, cfun_frame_layout
.f4_offset
+ 8);
9189 t
= MAX (t
, cfun_frame_layout
.f4_offset
+ 16);
9195 /* Update gpr_save_slots in the frame layout trying to make use of
9196 FPRs as GPR save slots.
9197 This is a helper routine of s390_register_info. */
9200 s390_register_info_gprtofpr ()
9202 int save_reg_slot
= FPR0_REGNUM
;
9205 if (!TARGET_Z10
|| !TARGET_HARD_FLOAT
|| !crtl
->is_leaf
)
9208 for (i
= 15; i
>= 6; i
--)
9210 if (cfun_gpr_save_slot (i
) == SAVE_SLOT_NONE
)
9213 /* Advance to the next FP register which can be used as a
9215 while ((!call_really_used_regs
[save_reg_slot
]
9216 || df_regs_ever_live_p (save_reg_slot
)
9217 || cfun_fpr_save_p (save_reg_slot
))
9218 && FP_REGNO_P (save_reg_slot
))
9220 if (!FP_REGNO_P (save_reg_slot
))
9222 /* We only want to use ldgr/lgdr if we can get rid of
9223 stm/lm entirely. So undo the gpr slot allocation in
9224 case we ran out of FPR save slots. */
9225 for (j
= 6; j
<= 15; j
++)
9226 if (FP_REGNO_P (cfun_gpr_save_slot (j
)))
9227 cfun_gpr_save_slot (j
) = SAVE_SLOT_STACK
;
9230 cfun_gpr_save_slot (i
) = save_reg_slot
++;
9234 /* Set the bits in fpr_bitmap for FPRs which need to be saved due to
9236 This is a helper routine for s390_register_info. */
9239 s390_register_info_stdarg_fpr ()
9245 /* Save the FP argument regs for stdarg. f0, f2 for 31 bit and
9246 f0-f4 for 64 bit. */
9248 || !TARGET_HARD_FLOAT
9249 || !cfun
->va_list_fpr_size
9250 || crtl
->args
.info
.fprs
>= FP_ARG_NUM_REG
)
9253 min_fpr
= crtl
->args
.info
.fprs
;
9254 max_fpr
= min_fpr
+ cfun
->va_list_fpr_size
- 1;
9255 if (max_fpr
>= FP_ARG_NUM_REG
)
9256 max_fpr
= FP_ARG_NUM_REG
- 1;
9258 /* FPR argument regs start at f0. */
9259 min_fpr
+= FPR0_REGNUM
;
9260 max_fpr
+= FPR0_REGNUM
;
9262 for (i
= min_fpr
; i
<= max_fpr
; i
++)
9263 cfun_set_fpr_save (i
);
9266 /* Reserve the GPR save slots for GPRs which need to be saved due to
9268 This is a helper routine for s390_register_info. */
9271 s390_register_info_stdarg_gpr ()
9278 || !cfun
->va_list_gpr_size
9279 || crtl
->args
.info
.gprs
>= GP_ARG_NUM_REG
)
9282 min_gpr
= crtl
->args
.info
.gprs
;
9283 max_gpr
= min_gpr
+ cfun
->va_list_gpr_size
- 1;
9284 if (max_gpr
>= GP_ARG_NUM_REG
)
9285 max_gpr
= GP_ARG_NUM_REG
- 1;
9287 /* GPR argument regs start at r2. */
9288 min_gpr
+= GPR2_REGNUM
;
9289 max_gpr
+= GPR2_REGNUM
;
9291 /* If r6 was supposed to be saved into an FPR and now needs to go to
9292 the stack for vararg we have to adjust the restore range to make
9293 sure that the restore is done from stack as well. */
9294 if (FP_REGNO_P (cfun_gpr_save_slot (GPR6_REGNUM
))
9295 && min_gpr
<= GPR6_REGNUM
9296 && max_gpr
>= GPR6_REGNUM
)
9298 if (cfun_frame_layout
.first_restore_gpr
== -1
9299 || cfun_frame_layout
.first_restore_gpr
> GPR6_REGNUM
)
9300 cfun_frame_layout
.first_restore_gpr
= GPR6_REGNUM
;
9301 if (cfun_frame_layout
.last_restore_gpr
== -1
9302 || cfun_frame_layout
.last_restore_gpr
< GPR6_REGNUM
)
9303 cfun_frame_layout
.last_restore_gpr
= GPR6_REGNUM
;
9306 if (cfun_frame_layout
.first_save_gpr
== -1
9307 || cfun_frame_layout
.first_save_gpr
> min_gpr
)
9308 cfun_frame_layout
.first_save_gpr
= min_gpr
;
9310 if (cfun_frame_layout
.last_save_gpr
== -1
9311 || cfun_frame_layout
.last_save_gpr
< max_gpr
)
9312 cfun_frame_layout
.last_save_gpr
= max_gpr
;
9314 for (i
= min_gpr
; i
<= max_gpr
; i
++)
9315 cfun_gpr_save_slot (i
) = SAVE_SLOT_STACK
;
9318 /* Calculate the save and restore ranges for stm(g) and lm(g) in the
9319 prologue and epilogue. */
9322 s390_register_info_set_ranges ()
9326 /* Find the first and the last save slot supposed to use the stack
9327 to set the restore range.
9328 Vararg regs might be marked as save to stack but only the
9329 call-saved regs really need restoring (i.e. r6). This code
9330 assumes that the vararg regs have not yet been recorded in
9331 cfun_gpr_save_slot. */
9332 for (i
= 0; i
< 16 && cfun_gpr_save_slot (i
) != SAVE_SLOT_STACK
; i
++);
9333 for (j
= 15; j
> i
&& cfun_gpr_save_slot (j
) != SAVE_SLOT_STACK
; j
--);
9334 cfun_frame_layout
.first_restore_gpr
= (i
== 16) ? -1 : i
;
9335 cfun_frame_layout
.last_restore_gpr
= (i
== 16) ? -1 : j
;
9336 cfun_frame_layout
.first_save_gpr
= (i
== 16) ? -1 : i
;
9337 cfun_frame_layout
.last_save_gpr
= (i
== 16) ? -1 : j
;
9340 /* The GPR and FPR save slots in cfun->machine->frame_layout are set
9341 for registers which need to be saved in function prologue.
9342 This function can be used until the insns emitted for save/restore
9343 of the regs are visible in the RTL stream. */
9346 s390_register_info ()
9349 char clobbered_regs
[32];
9351 gcc_assert (!epilogue_completed
);
9353 if (reload_completed
)
9354 /* After reload we rely on our own routine to determine which
9355 registers need saving. */
9356 s390_regs_ever_clobbered (clobbered_regs
);
9358 /* During reload we use regs_ever_live as a base since reload
9359 does changes in there which we otherwise would not be aware
9361 for (i
= 0; i
< 32; i
++)
9362 clobbered_regs
[i
] = df_regs_ever_live_p (i
);
9364 for (i
= 0; i
< 32; i
++)
9365 clobbered_regs
[i
] = clobbered_regs
[i
] && !global_regs
[i
];
9367 /* Mark the call-saved FPRs which need to be saved.
9368 This needs to be done before checking the special GPRs since the
9369 stack pointer usage depends on whether high FPRs have to be saved
9371 cfun_frame_layout
.fpr_bitmap
= 0;
9372 cfun_frame_layout
.high_fprs
= 0;
9373 for (i
= FPR0_REGNUM
; i
<= FPR15_REGNUM
; i
++)
9374 if (clobbered_regs
[i
] && !call_really_used_regs
[i
])
9376 cfun_set_fpr_save (i
);
9377 if (i
>= FPR8_REGNUM
)
9378 cfun_frame_layout
.high_fprs
++;
9381 /* Register 12 is used for GOT address, but also as temp in prologue
9382 for split-stack stdarg functions (unless r14 is available). */
9384 |= ((flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
9385 || (flag_split_stack
&& cfun
->stdarg
9386 && (crtl
->is_leaf
|| TARGET_TPF_PROFILING
9387 || has_hard_reg_initial_val (Pmode
, RETURN_REGNUM
))));
9389 clobbered_regs
[BASE_REGNUM
]
9390 |= (cfun
->machine
->base_reg
9391 && REGNO (cfun
->machine
->base_reg
) == BASE_REGNUM
);
9393 clobbered_regs
[HARD_FRAME_POINTER_REGNUM
]
9394 |= !!frame_pointer_needed
;
9396 /* On pre z900 machines this might take until machine dependent
9398 save_return_addr_p will only be set on non-zarch machines so
9399 there is no risk that r14 goes into an FPR instead of a stack
9401 clobbered_regs
[RETURN_REGNUM
]
9403 || TARGET_TPF_PROFILING
9404 || cfun
->machine
->split_branches_pending_p
9405 || cfun_frame_layout
.save_return_addr_p
9406 || crtl
->calls_eh_return
);
9408 clobbered_regs
[STACK_POINTER_REGNUM
]
9410 || TARGET_TPF_PROFILING
9411 || cfun_save_high_fprs_p
9412 || get_frame_size () > 0
9413 || (reload_completed
&& cfun_frame_layout
.frame_size
> 0)
9414 || cfun
->calls_alloca
);
9416 memset (cfun_frame_layout
.gpr_save_slots
, SAVE_SLOT_NONE
, 16);
9418 for (i
= 6; i
< 16; i
++)
9419 if (clobbered_regs
[i
])
9420 cfun_gpr_save_slot (i
) = SAVE_SLOT_STACK
;
9422 s390_register_info_stdarg_fpr ();
9423 s390_register_info_gprtofpr ();
9424 s390_register_info_set_ranges ();
9425 /* stdarg functions might need to save GPRs 2 to 6. This might
9426 override the GPR->FPR save decision made by
9427 s390_register_info_gprtofpr for r6 since vararg regs must go to
9429 s390_register_info_stdarg_gpr ();
9432 /* This function is called by s390_optimize_prologue in order to get
9433 rid of unnecessary GPR save/restore instructions. The register info
9434 for the GPRs is re-computed and the ranges are re-calculated. */
9437 s390_optimize_register_info ()
9439 char clobbered_regs
[32];
9442 gcc_assert (epilogue_completed
);
9443 gcc_assert (!cfun
->machine
->split_branches_pending_p
);
9445 s390_regs_ever_clobbered (clobbered_regs
);
9447 for (i
= 0; i
< 32; i
++)
9448 clobbered_regs
[i
] = clobbered_regs
[i
] && !global_regs
[i
];
9450 /* There is still special treatment needed for cases invisible to
9451 s390_regs_ever_clobbered. */
9452 clobbered_regs
[RETURN_REGNUM
]
9453 |= (TARGET_TPF_PROFILING
9454 /* When expanding builtin_return_addr in ESA mode we do not
9455 know whether r14 will later be needed as scratch reg when
9456 doing branch splitting. So the builtin always accesses the
9457 r14 save slot and we need to stick to the save/restore
9458 decision for r14 even if it turns out that it didn't get
9460 || cfun_frame_layout
.save_return_addr_p
9461 || crtl
->calls_eh_return
);
9463 memset (cfun_frame_layout
.gpr_save_slots
, SAVE_SLOT_NONE
, 6);
9465 for (i
= 6; i
< 16; i
++)
9466 if (!clobbered_regs
[i
])
9467 cfun_gpr_save_slot (i
) = SAVE_SLOT_NONE
;
9469 s390_register_info_set_ranges ();
9470 s390_register_info_stdarg_gpr ();
9473 /* Fill cfun->machine with info about frame of current function. */
9476 s390_frame_info (void)
9478 HOST_WIDE_INT lowest_offset
;
9480 cfun_frame_layout
.first_save_gpr_slot
= cfun_frame_layout
.first_save_gpr
;
9481 cfun_frame_layout
.last_save_gpr_slot
= cfun_frame_layout
.last_save_gpr
;
9483 /* The va_arg builtin uses a constant distance of 16 *
9484 UNITS_PER_LONG (r0-r15) to reach the FPRs from the reg_save_area
9485 pointer. So even if we are going to save the stack pointer in an
9486 FPR we need the stack space in order to keep the offsets
9488 if (cfun
->stdarg
&& cfun_save_arg_fprs_p
)
9490 cfun_frame_layout
.last_save_gpr_slot
= STACK_POINTER_REGNUM
;
9492 if (cfun_frame_layout
.first_save_gpr_slot
== -1)
9493 cfun_frame_layout
.first_save_gpr_slot
= STACK_POINTER_REGNUM
;
9496 cfun_frame_layout
.frame_size
= get_frame_size ();
9497 if (!TARGET_64BIT
&& cfun_frame_layout
.frame_size
> 0x7fff0000)
9498 fatal_error (input_location
,
9499 "total size of local variables exceeds architecture limit");
9501 if (!TARGET_PACKED_STACK
)
9503 /* Fixed stack layout. */
9504 cfun_frame_layout
.backchain_offset
= 0;
9505 cfun_frame_layout
.f0_offset
= 16 * UNITS_PER_LONG
;
9506 cfun_frame_layout
.f4_offset
= cfun_frame_layout
.f0_offset
+ 2 * 8;
9507 cfun_frame_layout
.f8_offset
= -cfun_frame_layout
.high_fprs
* 8;
9508 cfun_frame_layout
.gprs_offset
= (cfun_frame_layout
.first_save_gpr_slot
9511 else if (TARGET_BACKCHAIN
)
9513 /* Kernel stack layout - packed stack, backchain, no float */
9514 gcc_assert (TARGET_SOFT_FLOAT
);
9515 cfun_frame_layout
.backchain_offset
= (STACK_POINTER_OFFSET
9518 /* The distance between the backchain and the return address
9519 save slot must not change. So we always need a slot for the
9520 stack pointer which resides in between. */
9521 cfun_frame_layout
.last_save_gpr_slot
= STACK_POINTER_REGNUM
;
9523 cfun_frame_layout
.gprs_offset
9524 = cfun_frame_layout
.backchain_offset
- cfun_gprs_save_area_size
;
9526 /* FPRs will not be saved. Nevertheless pick sane values to
9527 keep area calculations valid. */
9528 cfun_frame_layout
.f0_offset
=
9529 cfun_frame_layout
.f4_offset
=
9530 cfun_frame_layout
.f8_offset
= cfun_frame_layout
.gprs_offset
;
9536 /* Packed stack layout without backchain. */
9538 /* With stdarg FPRs need their dedicated slots. */
9539 num_fprs
= (TARGET_64BIT
&& cfun
->stdarg
? 2
9540 : (cfun_fpr_save_p (FPR4_REGNUM
) +
9541 cfun_fpr_save_p (FPR6_REGNUM
)));
9542 cfun_frame_layout
.f4_offset
= STACK_POINTER_OFFSET
- 8 * num_fprs
;
9544 num_fprs
= (cfun
->stdarg
? 2
9545 : (cfun_fpr_save_p (FPR0_REGNUM
)
9546 + cfun_fpr_save_p (FPR2_REGNUM
)));
9547 cfun_frame_layout
.f0_offset
= cfun_frame_layout
.f4_offset
- 8 * num_fprs
;
9549 cfun_frame_layout
.gprs_offset
9550 = cfun_frame_layout
.f0_offset
- cfun_gprs_save_area_size
;
9552 cfun_frame_layout
.f8_offset
= (cfun_frame_layout
.gprs_offset
9553 - cfun_frame_layout
.high_fprs
* 8);
9556 if (cfun_save_high_fprs_p
)
9557 cfun_frame_layout
.frame_size
+= cfun_frame_layout
.high_fprs
* 8;
9560 cfun_frame_layout
.frame_size
+= crtl
->outgoing_args_size
;
9562 /* In the following cases we have to allocate a STACK_POINTER_OFFSET
9563 sized area at the bottom of the stack. This is required also for
9564 leaf functions. When GCC generates a local stack reference it
9565 will always add STACK_POINTER_OFFSET to all these references. */
9567 && !TARGET_TPF_PROFILING
9568 && cfun_frame_layout
.frame_size
== 0
9569 && !cfun
->calls_alloca
)
9572 /* Calculate the number of bytes we have used in our own register
9573 save area. With the packed stack layout we can re-use the
9574 remaining bytes for normal stack elements. */
9576 if (TARGET_PACKED_STACK
)
9577 lowest_offset
= MIN (MIN (cfun_frame_layout
.f0_offset
,
9578 cfun_frame_layout
.f4_offset
),
9579 cfun_frame_layout
.gprs_offset
);
9583 if (TARGET_BACKCHAIN
)
9584 lowest_offset
= MIN (lowest_offset
, cfun_frame_layout
.backchain_offset
);
9586 cfun_frame_layout
.frame_size
+= STACK_POINTER_OFFSET
- lowest_offset
;
9588 /* If under 31 bit an odd number of gprs has to be saved we have to
9589 adjust the frame size to sustain 8 byte alignment of stack
9591 cfun_frame_layout
.frame_size
= ((cfun_frame_layout
.frame_size
+
9592 STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
9593 & ~(STACK_BOUNDARY
/ BITS_PER_UNIT
- 1));
9596 /* Generate frame layout. Fills in register and frame data for the current
9597 function in cfun->machine. This routine can be called multiple times;
9598 it will re-do the complete frame layout every time. */
9601 s390_init_frame_layout (void)
9603 HOST_WIDE_INT frame_size
;
9606 /* After LRA the frame layout is supposed to be read-only and should
9607 not be re-computed. */
9608 if (reload_completed
)
9611 /* On S/390 machines, we may need to perform branch splitting, which
9612 will require both base and return address register. We have no
9613 choice but to assume we're going to need them until right at the
9614 end of the machine dependent reorg phase. */
9615 if (!TARGET_CPU_ZARCH
)
9616 cfun
->machine
->split_branches_pending_p
= true;
9620 frame_size
= cfun_frame_layout
.frame_size
;
9622 /* Try to predict whether we'll need the base register. */
9623 base_used
= cfun
->machine
->split_branches_pending_p
9624 || crtl
->uses_const_pool
9625 || (!DISP_IN_RANGE (frame_size
)
9626 && !CONST_OK_FOR_K (frame_size
));
9628 /* Decide which register to use as literal pool base. In small
9629 leaf functions, try to use an unused call-clobbered register
9630 as base register to avoid save/restore overhead. */
9632 cfun
->machine
->base_reg
= NULL_RTX
;
9638 /* Prefer r5 (most likely to be free). */
9639 for (br
= 5; br
>= 2 && df_regs_ever_live_p (br
); br
--)
9641 cfun
->machine
->base_reg
=
9642 gen_rtx_REG (Pmode
, (br
>= 2) ? br
: BASE_REGNUM
);
9645 s390_register_info ();
9648 while (frame_size
!= cfun_frame_layout
.frame_size
);
9651 /* Remove the FPR clobbers from a tbegin insn if it can be proven that
9652 the TX is nonescaping. A transaction is considered escaping if
9653 there is at least one path from tbegin returning CC0 to the
9654 function exit block without an tend.
9656 The check so far has some limitations:
9657 - only single tbegin/tend BBs are supported
9658 - the first cond jump after tbegin must separate the CC0 path from ~CC0
9659 - when CC is copied to a GPR and the CC0 check is done with the GPR
9660 this is not supported
9664 s390_optimize_nonescaping_tx (void)
9666 const unsigned int CC0
= 1 << 3;
9667 basic_block tbegin_bb
= NULL
;
9668 basic_block tend_bb
= NULL
;
9673 rtx_insn
*tbegin_insn
= NULL
;
9675 if (!cfun
->machine
->tbegin_p
)
9678 for (bb_index
= 0; bb_index
< n_basic_blocks_for_fn (cfun
); bb_index
++)
9680 bb
= BASIC_BLOCK_FOR_FN (cfun
, bb_index
);
9685 FOR_BB_INSNS (bb
, insn
)
9687 rtx ite
, cc
, pat
, target
;
9688 unsigned HOST_WIDE_INT mask
;
9690 if (!INSN_P (insn
) || INSN_CODE (insn
) <= 0)
9693 pat
= PATTERN (insn
);
9695 if (GET_CODE (pat
) == PARALLEL
)
9696 pat
= XVECEXP (pat
, 0, 0);
9698 if (GET_CODE (pat
) != SET
9699 || GET_CODE (SET_SRC (pat
)) != UNSPEC_VOLATILE
)
9702 if (XINT (SET_SRC (pat
), 1) == UNSPECV_TBEGIN
)
9708 /* Just return if the tbegin doesn't have clobbers. */
9709 if (GET_CODE (PATTERN (insn
)) != PARALLEL
)
9712 if (tbegin_bb
!= NULL
)
9715 /* Find the next conditional jump. */
9716 for (tmp
= NEXT_INSN (insn
);
9718 tmp
= NEXT_INSN (tmp
))
9720 if (reg_set_p (gen_rtx_REG (CCmode
, CC_REGNUM
), tmp
))
9725 ite
= SET_SRC (PATTERN (tmp
));
9726 if (GET_CODE (ite
) != IF_THEN_ELSE
)
9729 cc
= XEXP (XEXP (ite
, 0), 0);
9730 if (!REG_P (cc
) || !CC_REGNO_P (REGNO (cc
))
9731 || GET_MODE (cc
) != CCRAWmode
9732 || GET_CODE (XEXP (XEXP (ite
, 0), 1)) != CONST_INT
)
9735 if (bb
->succs
->length () != 2)
9738 mask
= INTVAL (XEXP (XEXP (ite
, 0), 1));
9739 if (GET_CODE (XEXP (ite
, 0)) == NE
)
9743 target
= XEXP (ite
, 1);
9744 else if (mask
== (CC0
^ 0xf))
9745 target
= XEXP (ite
, 2);
9753 ei
= ei_start (bb
->succs
);
9754 e1
= ei_safe_edge (ei
);
9756 e2
= ei_safe_edge (ei
);
9758 if (e2
->flags
& EDGE_FALLTHRU
)
9761 e1
= ei_safe_edge (ei
);
9764 if (!(e1
->flags
& EDGE_FALLTHRU
))
9767 tbegin_bb
= (target
== pc_rtx
) ? e1
->dest
: e2
->dest
;
9769 if (tmp
== BB_END (bb
))
9774 if (XINT (SET_SRC (pat
), 1) == UNSPECV_TEND
)
9776 if (tend_bb
!= NULL
)
9783 /* Either we successfully remove the FPR clobbers here or we are not
9784 able to do anything for this TX. Both cases don't qualify for
9786 cfun
->machine
->tbegin_p
= false;
9788 if (tbegin_bb
== NULL
|| tend_bb
== NULL
)
9791 calculate_dominance_info (CDI_POST_DOMINATORS
);
9792 result
= dominated_by_p (CDI_POST_DOMINATORS
, tbegin_bb
, tend_bb
);
9793 free_dominance_info (CDI_POST_DOMINATORS
);
9798 PATTERN (tbegin_insn
) = gen_rtx_PARALLEL (VOIDmode
,
9800 XVECEXP (PATTERN (tbegin_insn
), 0, 0),
9801 XVECEXP (PATTERN (tbegin_insn
), 0, 1)));
9802 INSN_CODE (tbegin_insn
) = -1;
9803 df_insn_rescan (tbegin_insn
);
9808 /* Return true if it is legal to put a value with MODE into REGNO. */
9811 s390_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
9813 if (!TARGET_VX
&& VECTOR_NOFP_REGNO_P (regno
))
9816 switch (REGNO_REG_CLASS (regno
))
9819 return ((GET_MODE_CLASS (mode
) == MODE_INT
9820 && s390_class_max_nregs (VEC_REGS
, mode
) == 1)
9822 || s390_vector_mode_supported_p (mode
));
9826 && ((GET_MODE_CLASS (mode
) == MODE_INT
9827 && s390_class_max_nregs (FP_REGS
, mode
) == 1)
9829 || s390_vector_mode_supported_p (mode
)))
9832 if (REGNO_PAIR_OK (regno
, mode
))
9834 if (mode
== SImode
|| mode
== DImode
)
9837 if (FLOAT_MODE_P (mode
) && GET_MODE_CLASS (mode
) != MODE_VECTOR_FLOAT
)
9842 if (FRAME_REGNO_P (regno
) && mode
== Pmode
)
9847 if (REGNO_PAIR_OK (regno
, mode
))
9850 || (mode
!= TFmode
&& mode
!= TCmode
&& mode
!= TDmode
))
9855 if (GET_MODE_CLASS (mode
) == MODE_CC
)
9859 if (REGNO_PAIR_OK (regno
, mode
))
9861 if (mode
== SImode
|| mode
== Pmode
)
9872 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
9875 s390_hard_regno_rename_ok (unsigned int old_reg
, unsigned int new_reg
)
9877 /* Once we've decided upon a register to use as base register, it must
9878 no longer be used for any other purpose. */
9879 if (cfun
->machine
->base_reg
)
9880 if (REGNO (cfun
->machine
->base_reg
) == old_reg
9881 || REGNO (cfun
->machine
->base_reg
) == new_reg
)
9884 /* Prevent regrename from using call-saved regs which haven't
9885 actually been saved. This is necessary since regrename assumes
9886 the backend save/restore decisions are based on
9887 df_regs_ever_live. Since we have our own routine we have to tell
9888 regrename manually about it. */
9889 if (GENERAL_REGNO_P (new_reg
)
9890 && !call_really_used_regs
[new_reg
]
9891 && cfun_gpr_save_slot (new_reg
) == SAVE_SLOT_NONE
)
9897 /* Return nonzero if register REGNO can be used as a scratch register
9901 s390_hard_regno_scratch_ok (unsigned int regno
)
9903 /* See s390_hard_regno_rename_ok. */
9904 if (GENERAL_REGNO_P (regno
)
9905 && !call_really_used_regs
[regno
]
9906 && cfun_gpr_save_slot (regno
) == SAVE_SLOT_NONE
)
9912 /* Maximum number of registers to represent a value of mode MODE
9913 in a register of class RCLASS. */
9916 s390_class_max_nregs (enum reg_class rclass
, machine_mode mode
)
9919 bool reg_pair_required_p
= false;
9925 reg_size
= TARGET_VX
? 16 : 8;
9927 /* TF and TD modes would fit into a VR but we put them into a
9928 register pair since we do not have 128bit FP instructions on
9931 && SCALAR_FLOAT_MODE_P (mode
)
9932 && GET_MODE_SIZE (mode
) >= 16)
9933 reg_pair_required_p
= true;
9935 /* Even if complex types would fit into a single FPR/VR we force
9936 them into a register pair to deal with the parts more easily.
9937 (FIXME: What about complex ints?) */
9938 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
9939 reg_pair_required_p
= true;
9945 reg_size
= UNITS_PER_WORD
;
9949 if (reg_pair_required_p
)
9950 return 2 * ((GET_MODE_SIZE (mode
) / 2 + reg_size
- 1) / reg_size
);
9952 return (GET_MODE_SIZE (mode
) + reg_size
- 1) / reg_size
;
9955 /* Return TRUE if changing mode from FROM to TO should not be allowed
9956 for register class CLASS. */
9959 s390_cannot_change_mode_class (machine_mode from_mode
,
9960 machine_mode to_mode
,
9961 enum reg_class rclass
)
9963 machine_mode small_mode
;
9964 machine_mode big_mode
;
9966 if (GET_MODE_SIZE (from_mode
) == GET_MODE_SIZE (to_mode
))
9969 if (GET_MODE_SIZE (from_mode
) < GET_MODE_SIZE (to_mode
))
9971 small_mode
= from_mode
;
9976 small_mode
= to_mode
;
9977 big_mode
= from_mode
;
9980 /* Values residing in VRs are little-endian style. All modes are
9981 placed left-aligned in an VR. This means that we cannot allow
9982 switching between modes with differing sizes. Also if the vector
9983 facility is available we still place TFmode values in VR register
9984 pairs, since the only instructions we have operating on TFmodes
9985 only deal with register pairs. Therefore we have to allow DFmode
9986 subregs of TFmodes to enable the TFmode splitters. */
9987 if (reg_classes_intersect_p (VEC_REGS
, rclass
)
9988 && (GET_MODE_SIZE (small_mode
) < 8
9989 || s390_class_max_nregs (VEC_REGS
, big_mode
) == 1))
9992 /* Likewise for access registers, since they have only half the
9993 word size on 64-bit. */
9994 if (reg_classes_intersect_p (ACCESS_REGS
, rclass
))
10000 /* Return true if we use LRA instead of reload pass. */
10004 return s390_lra_flag
;
10007 /* Return true if register FROM can be eliminated via register TO. */
10010 s390_can_eliminate (const int from
, const int to
)
10012 /* On zSeries machines, we have not marked the base register as fixed.
10013 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
10014 If a function requires the base register, we say here that this
10015 elimination cannot be performed. This will cause reload to free
10016 up the base register (as if it were fixed). On the other hand,
10017 if the current function does *not* require the base register, we
10018 say here the elimination succeeds, which in turn allows reload
10019 to allocate the base register for any other purpose. */
10020 if (from
== BASE_REGNUM
&& to
== BASE_REGNUM
)
10022 if (TARGET_CPU_ZARCH
)
10024 s390_init_frame_layout ();
10025 return cfun
->machine
->base_reg
== NULL_RTX
;
10031 /* Everything else must point into the stack frame. */
10032 gcc_assert (to
== STACK_POINTER_REGNUM
10033 || to
== HARD_FRAME_POINTER_REGNUM
);
10035 gcc_assert (from
== FRAME_POINTER_REGNUM
10036 || from
== ARG_POINTER_REGNUM
10037 || from
== RETURN_ADDRESS_POINTER_REGNUM
);
10039 /* Make sure we actually saved the return address. */
10040 if (from
== RETURN_ADDRESS_POINTER_REGNUM
)
10041 if (!crtl
->calls_eh_return
10043 && !cfun_frame_layout
.save_return_addr_p
)
10049 /* Return offset between register FROM and TO initially after prolog. */
10052 s390_initial_elimination_offset (int from
, int to
)
10054 HOST_WIDE_INT offset
;
10056 /* ??? Why are we called for non-eliminable pairs? */
10057 if (!s390_can_eliminate (from
, to
))
10062 case FRAME_POINTER_REGNUM
:
10063 offset
= (get_frame_size()
10064 + STACK_POINTER_OFFSET
10065 + crtl
->outgoing_args_size
);
10068 case ARG_POINTER_REGNUM
:
10069 s390_init_frame_layout ();
10070 offset
= cfun_frame_layout
.frame_size
+ STACK_POINTER_OFFSET
;
10073 case RETURN_ADDRESS_POINTER_REGNUM
:
10074 s390_init_frame_layout ();
10076 if (cfun_frame_layout
.first_save_gpr_slot
== -1)
10078 /* If it turns out that for stdarg nothing went into the reg
10079 save area we also do not need the return address
10081 if (cfun
->stdarg
&& !cfun_save_arg_fprs_p
)
10084 gcc_unreachable ();
10087 /* In order to make the following work it is not necessary for
10088 r14 to have a save slot. It is sufficient if one other GPR
10089 got one. Since the GPRs are always stored without gaps we
10090 are able to calculate where the r14 save slot would
10092 offset
= (cfun_frame_layout
.frame_size
+ cfun_frame_layout
.gprs_offset
+
10093 (RETURN_REGNUM
- cfun_frame_layout
.first_save_gpr_slot
) *
10102 gcc_unreachable ();
10108 /* Emit insn to save fpr REGNUM at offset OFFSET relative
10109 to register BASE. Return generated insn. */
10112 save_fpr (rtx base
, int offset
, int regnum
)
10115 addr
= gen_rtx_MEM (DFmode
, plus_constant (Pmode
, base
, offset
));
10117 if (regnum
>= 16 && regnum
<= (16 + FP_ARG_NUM_REG
))
10118 set_mem_alias_set (addr
, get_varargs_alias_set ());
10120 set_mem_alias_set (addr
, get_frame_alias_set ());
10122 return emit_move_insn (addr
, gen_rtx_REG (DFmode
, regnum
));
10125 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
10126 to register BASE. Return generated insn. */
10129 restore_fpr (rtx base
, int offset
, int regnum
)
10132 addr
= gen_rtx_MEM (DFmode
, plus_constant (Pmode
, base
, offset
));
10133 set_mem_alias_set (addr
, get_frame_alias_set ());
10135 return emit_move_insn (gen_rtx_REG (DFmode
, regnum
), addr
);
10138 /* Return true if REGNO is a global register, but not one
10139 of the special ones that need to be saved/restored in anyway. */
10142 global_not_special_regno_p (int regno
)
10144 return (global_regs
[regno
]
10145 /* These registers are special and need to be
10146 restored in any case. */
10147 && !(regno
== STACK_POINTER_REGNUM
10148 || regno
== RETURN_REGNUM
10149 || regno
== BASE_REGNUM
10150 || (flag_pic
&& regno
== (int)PIC_OFFSET_TABLE_REGNUM
)));
10153 /* Generate insn to save registers FIRST to LAST into
10154 the register save area located at offset OFFSET
10155 relative to register BASE. */
10158 save_gprs (rtx base
, int offset
, int first
, int last
)
10160 rtx addr
, insn
, note
;
10163 addr
= plus_constant (Pmode
, base
, offset
);
10164 addr
= gen_rtx_MEM (Pmode
, addr
);
10166 set_mem_alias_set (addr
, get_frame_alias_set ());
10168 /* Special-case single register. */
10172 insn
= gen_movdi (addr
, gen_rtx_REG (Pmode
, first
));
10174 insn
= gen_movsi (addr
, gen_rtx_REG (Pmode
, first
));
10176 if (!global_not_special_regno_p (first
))
10177 RTX_FRAME_RELATED_P (insn
) = 1;
10182 insn
= gen_store_multiple (addr
,
10183 gen_rtx_REG (Pmode
, first
),
10184 GEN_INT (last
- first
+ 1));
10186 if (first
<= 6 && cfun
->stdarg
)
10187 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
10189 rtx mem
= XEXP (XVECEXP (PATTERN (insn
), 0, i
), 0);
10191 if (first
+ i
<= 6)
10192 set_mem_alias_set (mem
, get_varargs_alias_set ());
10195 /* We need to set the FRAME_RELATED flag on all SETs
10196 inside the store-multiple pattern.
10198 However, we must not emit DWARF records for registers 2..5
10199 if they are stored for use by variable arguments ...
10201 ??? Unfortunately, it is not enough to simply not the
10202 FRAME_RELATED flags for those SETs, because the first SET
10203 of the PARALLEL is always treated as if it had the flag
10204 set, even if it does not. Therefore we emit a new pattern
10205 without those registers as REG_FRAME_RELATED_EXPR note. */
10207 if (first
>= 6 && !global_not_special_regno_p (first
))
10209 rtx pat
= PATTERN (insn
);
10211 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
10212 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
10213 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat
,
10215 RTX_FRAME_RELATED_P (XVECEXP (pat
, 0, i
)) = 1;
10217 RTX_FRAME_RELATED_P (insn
) = 1;
10219 else if (last
>= 6)
10223 for (start
= first
>= 6 ? first
: 6; start
<= last
; start
++)
10224 if (!global_not_special_regno_p (start
))
10230 addr
= plus_constant (Pmode
, base
,
10231 offset
+ (start
- first
) * UNITS_PER_LONG
);
10236 note
= gen_movdi (gen_rtx_MEM (Pmode
, addr
),
10237 gen_rtx_REG (Pmode
, start
));
10239 note
= gen_movsi (gen_rtx_MEM (Pmode
, addr
),
10240 gen_rtx_REG (Pmode
, start
));
10241 note
= PATTERN (note
);
10243 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note
);
10244 RTX_FRAME_RELATED_P (insn
) = 1;
10249 note
= gen_store_multiple (gen_rtx_MEM (Pmode
, addr
),
10250 gen_rtx_REG (Pmode
, start
),
10251 GEN_INT (last
- start
+ 1));
10252 note
= PATTERN (note
);
10254 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note
);
10256 for (i
= 0; i
< XVECLEN (note
, 0); i
++)
10257 if (GET_CODE (XVECEXP (note
, 0, i
)) == SET
10258 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note
,
10260 RTX_FRAME_RELATED_P (XVECEXP (note
, 0, i
)) = 1;
10262 RTX_FRAME_RELATED_P (insn
) = 1;
10268 /* Generate insn to restore registers FIRST to LAST from
10269 the register save area located at offset OFFSET
10270 relative to register BASE. */
10273 restore_gprs (rtx base
, int offset
, int first
, int last
)
10277 addr
= plus_constant (Pmode
, base
, offset
);
10278 addr
= gen_rtx_MEM (Pmode
, addr
);
10279 set_mem_alias_set (addr
, get_frame_alias_set ());
10281 /* Special-case single register. */
10285 insn
= gen_movdi (gen_rtx_REG (Pmode
, first
), addr
);
10287 insn
= gen_movsi (gen_rtx_REG (Pmode
, first
), addr
);
10289 RTX_FRAME_RELATED_P (insn
) = 1;
10293 insn
= gen_load_multiple (gen_rtx_REG (Pmode
, first
),
10295 GEN_INT (last
- first
+ 1));
10296 RTX_FRAME_RELATED_P (insn
) = 1;
10300 /* Return insn sequence to load the GOT register. */
10302 static GTY(()) rtx got_symbol
;
10304 s390_load_got (void)
10308 /* We cannot use pic_offset_table_rtx here since we use this
10309 function also for non-pic if __tls_get_offset is called and in
10310 that case PIC_OFFSET_TABLE_REGNUM as well as pic_offset_table_rtx
10312 rtx got_rtx
= gen_rtx_REG (Pmode
, 12);
10316 got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
10317 SYMBOL_REF_FLAGS (got_symbol
) = SYMBOL_FLAG_LOCAL
;
10322 if (TARGET_CPU_ZARCH
)
10324 emit_move_insn (got_rtx
, got_symbol
);
10330 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, got_symbol
),
10331 UNSPEC_LTREL_OFFSET
);
10332 offset
= gen_rtx_CONST (Pmode
, offset
);
10333 offset
= force_const_mem (Pmode
, offset
);
10335 emit_move_insn (got_rtx
, offset
);
10337 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, XEXP (offset
, 0)),
10338 UNSPEC_LTREL_BASE
);
10339 offset
= gen_rtx_PLUS (Pmode
, got_rtx
, offset
);
10341 emit_move_insn (got_rtx
, offset
);
10344 insns
= get_insns ();
10349 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
10350 and the change to the stack pointer. */
10353 s390_emit_stack_tie (void)
10355 rtx mem
= gen_frame_mem (BLKmode
,
10356 gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
));
10358 emit_insn (gen_stack_tie (mem
));
10361 /* Copy GPRS into FPR save slots. */
10364 s390_save_gprs_to_fprs (void)
10368 if (!TARGET_Z10
|| !TARGET_HARD_FLOAT
|| !crtl
->is_leaf
)
10371 for (i
= 6; i
< 16; i
++)
10373 if (FP_REGNO_P (cfun_gpr_save_slot (i
)))
10376 emit_move_insn (gen_rtx_REG (DImode
, cfun_gpr_save_slot (i
)),
10377 gen_rtx_REG (DImode
, i
));
10378 RTX_FRAME_RELATED_P (insn
) = 1;
10379 /* This prevents dwarf2cfi from interpreting the set. Doing
10380 so it might emit def_cfa_register infos setting an FPR as
10382 add_reg_note (insn
, REG_CFA_REGISTER
, PATTERN (insn
));
10387 /* Restore GPRs from FPR save slots. */
10390 s390_restore_gprs_from_fprs (void)
10394 if (!TARGET_Z10
|| !TARGET_HARD_FLOAT
|| !crtl
->is_leaf
)
10397 for (i
= 6; i
< 16; i
++)
10399 if (FP_REGNO_P (cfun_gpr_save_slot (i
)))
10402 emit_move_insn (gen_rtx_REG (DImode
, i
),
10403 gen_rtx_REG (DImode
, cfun_gpr_save_slot (i
)));
10404 df_set_regs_ever_live (i
, true);
10405 add_reg_note (insn
, REG_CFA_RESTORE
, gen_rtx_REG (DImode
, i
));
10406 if (i
== STACK_POINTER_REGNUM
)
10407 add_reg_note (insn
, REG_CFA_DEF_CFA
,
10408 plus_constant (Pmode
, stack_pointer_rtx
,
10409 STACK_POINTER_OFFSET
));
10410 RTX_FRAME_RELATED_P (insn
) = 1;
10416 /* A pass run immediately before shrink-wrapping and prologue and epilogue
10421 const pass_data pass_data_s390_early_mach
=
10423 RTL_PASS
, /* type */
10424 "early_mach", /* name */
10425 OPTGROUP_NONE
, /* optinfo_flags */
10426 TV_MACH_DEP
, /* tv_id */
10427 0, /* properties_required */
10428 0, /* properties_provided */
10429 0, /* properties_destroyed */
10430 0, /* todo_flags_start */
10431 ( TODO_df_verify
| TODO_df_finish
), /* todo_flags_finish */
10434 class pass_s390_early_mach
: public rtl_opt_pass
10437 pass_s390_early_mach (gcc::context
*ctxt
)
10438 : rtl_opt_pass (pass_data_s390_early_mach
, ctxt
)
10441 /* opt_pass methods: */
10442 virtual unsigned int execute (function
*);
10444 }; // class pass_s390_early_mach
10447 pass_s390_early_mach::execute (function
*fun
)
10451 /* Try to get rid of the FPR clobbers. */
10452 s390_optimize_nonescaping_tx ();
10454 /* Re-compute register info. */
10455 s390_register_info ();
10457 /* If we're using a base register, ensure that it is always valid for
10458 the first non-prologue instruction. */
10459 if (fun
->machine
->base_reg
)
10460 emit_insn_at_entry (gen_main_pool (fun
->machine
->base_reg
));
10462 /* Annotate all constant pool references to let the scheduler know
10463 they implicitly use the base register. */
10464 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10467 annotate_constant_pool_refs (&PATTERN (insn
));
10468 df_insn_rescan (insn
);
10473 } // anon namespace
10475 /* Expand the prologue into a bunch of separate insns. */
10478 s390_emit_prologue (void)
10486 /* Choose best register to use for temp use within prologue.
10487 TPF with profiling must avoid the register 14 - the tracing function
10488 needs the original contents of r14 to be preserved. */
10490 if (!has_hard_reg_initial_val (Pmode
, RETURN_REGNUM
)
10492 && !TARGET_TPF_PROFILING
)
10493 temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
10494 else if (flag_split_stack
&& cfun
->stdarg
)
10495 temp_reg
= gen_rtx_REG (Pmode
, 12);
10497 temp_reg
= gen_rtx_REG (Pmode
, 1);
10499 s390_save_gprs_to_fprs ();
10501 /* Save call saved gprs. */
10502 if (cfun_frame_layout
.first_save_gpr
!= -1)
10504 insn
= save_gprs (stack_pointer_rtx
,
10505 cfun_frame_layout
.gprs_offset
+
10506 UNITS_PER_LONG
* (cfun_frame_layout
.first_save_gpr
10507 - cfun_frame_layout
.first_save_gpr_slot
),
10508 cfun_frame_layout
.first_save_gpr
,
10509 cfun_frame_layout
.last_save_gpr
);
10513 /* Dummy insn to mark literal pool slot. */
10515 if (cfun
->machine
->base_reg
)
10516 emit_insn (gen_main_pool (cfun
->machine
->base_reg
));
10518 offset
= cfun_frame_layout
.f0_offset
;
10520 /* Save f0 and f2. */
10521 for (i
= FPR0_REGNUM
; i
<= FPR0_REGNUM
+ 1; i
++)
10523 if (cfun_fpr_save_p (i
))
10525 save_fpr (stack_pointer_rtx
, offset
, i
);
10528 else if (!TARGET_PACKED_STACK
|| cfun
->stdarg
)
10532 /* Save f4 and f6. */
10533 offset
= cfun_frame_layout
.f4_offset
;
10534 for (i
= FPR4_REGNUM
; i
<= FPR4_REGNUM
+ 1; i
++)
10536 if (cfun_fpr_save_p (i
))
10538 insn
= save_fpr (stack_pointer_rtx
, offset
, i
);
10541 /* If f4 and f6 are call clobbered they are saved due to
10542 stdargs and therefore are not frame related. */
10543 if (!call_really_used_regs
[i
])
10544 RTX_FRAME_RELATED_P (insn
) = 1;
10546 else if (!TARGET_PACKED_STACK
|| call_really_used_regs
[i
])
10550 if (TARGET_PACKED_STACK
10551 && cfun_save_high_fprs_p
10552 && cfun_frame_layout
.f8_offset
+ cfun_frame_layout
.high_fprs
* 8 > 0)
10554 offset
= (cfun_frame_layout
.f8_offset
10555 + (cfun_frame_layout
.high_fprs
- 1) * 8);
10557 for (i
= FPR15_REGNUM
; i
>= FPR8_REGNUM
&& offset
>= 0; i
--)
10558 if (cfun_fpr_save_p (i
))
10560 insn
= save_fpr (stack_pointer_rtx
, offset
, i
);
10562 RTX_FRAME_RELATED_P (insn
) = 1;
10565 if (offset
>= cfun_frame_layout
.f8_offset
)
10569 if (!TARGET_PACKED_STACK
)
10570 next_fpr
= cfun_save_high_fprs_p
? FPR15_REGNUM
: 0;
10572 if (flag_stack_usage_info
)
10573 current_function_static_stack_size
= cfun_frame_layout
.frame_size
;
10575 /* Decrement stack pointer. */
10577 if (cfun_frame_layout
.frame_size
> 0)
10579 rtx frame_off
= GEN_INT (-cfun_frame_layout
.frame_size
);
10580 rtx real_frame_off
;
10582 if (s390_stack_size
)
10584 HOST_WIDE_INT stack_guard
;
10586 if (s390_stack_guard
)
10587 stack_guard
= s390_stack_guard
;
10590 /* If no value for stack guard is provided the smallest power of 2
10591 larger than the current frame size is chosen. */
10593 while (stack_guard
< cfun_frame_layout
.frame_size
)
10597 if (cfun_frame_layout
.frame_size
>= s390_stack_size
)
10599 warning (0, "frame size of function %qs is %wd"
10600 " bytes exceeding user provided stack limit of "
10602 "An unconditional trap is added.",
10603 current_function_name(), cfun_frame_layout
.frame_size
,
10605 emit_insn (gen_trap ());
10610 /* stack_guard has to be smaller than s390_stack_size.
10611 Otherwise we would emit an AND with zero which would
10612 not match the test under mask pattern. */
10613 if (stack_guard
>= s390_stack_size
)
10615 warning (0, "frame size of function %qs is %wd"
10616 " bytes which is more than half the stack size. "
10617 "The dynamic check would not be reliable. "
10618 "No check emitted for this function.",
10619 current_function_name(),
10620 cfun_frame_layout
.frame_size
);
10624 HOST_WIDE_INT stack_check_mask
= ((s390_stack_size
- 1)
10625 & ~(stack_guard
- 1));
10627 rtx t
= gen_rtx_AND (Pmode
, stack_pointer_rtx
,
10628 GEN_INT (stack_check_mask
));
10630 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode
,
10632 t
, const0_rtx
, const0_rtx
));
10634 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode
,
10636 t
, const0_rtx
, const0_rtx
));
10641 if (s390_warn_framesize
> 0
10642 && cfun_frame_layout
.frame_size
>= s390_warn_framesize
)
10643 warning (0, "frame size of %qs is %wd bytes",
10644 current_function_name (), cfun_frame_layout
.frame_size
);
10646 if (s390_warn_dynamicstack_p
&& cfun
->calls_alloca
)
10647 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
10649 /* Save incoming stack pointer into temp reg. */
10650 if (TARGET_BACKCHAIN
|| next_fpr
)
10651 insn
= emit_insn (gen_move_insn (temp_reg
, stack_pointer_rtx
));
10653 /* Subtract frame size from stack pointer. */
10655 if (DISP_IN_RANGE (INTVAL (frame_off
)))
10657 insn
= gen_rtx_SET (stack_pointer_rtx
,
10658 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
10660 insn
= emit_insn (insn
);
10664 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
10665 frame_off
= force_const_mem (Pmode
, frame_off
);
10667 insn
= emit_insn (gen_add2_insn (stack_pointer_rtx
, frame_off
));
10668 annotate_constant_pool_refs (&PATTERN (insn
));
10671 RTX_FRAME_RELATED_P (insn
) = 1;
10672 real_frame_off
= GEN_INT (-cfun_frame_layout
.frame_size
);
10673 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
10674 gen_rtx_SET (stack_pointer_rtx
,
10675 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
10678 /* Set backchain. */
10680 if (TARGET_BACKCHAIN
)
10682 if (cfun_frame_layout
.backchain_offset
)
10683 addr
= gen_rtx_MEM (Pmode
,
10684 plus_constant (Pmode
, stack_pointer_rtx
,
10685 cfun_frame_layout
.backchain_offset
));
10687 addr
= gen_rtx_MEM (Pmode
, stack_pointer_rtx
);
10688 set_mem_alias_set (addr
, get_frame_alias_set ());
10689 insn
= emit_insn (gen_move_insn (addr
, temp_reg
));
10692 /* If we support non-call exceptions (e.g. for Java),
10693 we need to make sure the backchain pointer is set up
10694 before any possibly trapping memory access. */
10695 if (TARGET_BACKCHAIN
&& cfun
->can_throw_non_call_exceptions
)
10697 addr
= gen_rtx_MEM (BLKmode
, gen_rtx_SCRATCH (VOIDmode
));
10698 emit_clobber (addr
);
10702 /* Save fprs 8 - 15 (64 bit ABI). */
10704 if (cfun_save_high_fprs_p
&& next_fpr
)
10706 /* If the stack might be accessed through a different register
10707 we have to make sure that the stack pointer decrement is not
10708 moved below the use of the stack slots. */
10709 s390_emit_stack_tie ();
10711 insn
= emit_insn (gen_add2_insn (temp_reg
,
10712 GEN_INT (cfun_frame_layout
.f8_offset
)));
10716 for (i
= FPR8_REGNUM
; i
<= next_fpr
; i
++)
10717 if (cfun_fpr_save_p (i
))
10719 rtx addr
= plus_constant (Pmode
, stack_pointer_rtx
,
10720 cfun_frame_layout
.frame_size
10721 + cfun_frame_layout
.f8_offset
10724 insn
= save_fpr (temp_reg
, offset
, i
);
10726 RTX_FRAME_RELATED_P (insn
) = 1;
10727 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
10728 gen_rtx_SET (gen_rtx_MEM (DFmode
, addr
),
10729 gen_rtx_REG (DFmode
, i
)));
10733 /* Set frame pointer, if needed. */
10735 if (frame_pointer_needed
)
10737 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
10738 RTX_FRAME_RELATED_P (insn
) = 1;
10741 /* Set up got pointer, if needed. */
10743 if (flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
10745 rtx_insn
*insns
= s390_load_got ();
10747 for (rtx_insn
*insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
10748 annotate_constant_pool_refs (&PATTERN (insn
));
10753 if (TARGET_TPF_PROFILING
)
10755 /* Generate a BAS instruction to serve as a function
10756 entry intercept to facilitate the use of tracing
10757 algorithms located at the branch target. */
10758 emit_insn (gen_prologue_tpf ());
10760 /* Emit a blockage here so that all code
10761 lies between the profiling mechanisms. */
10762 emit_insn (gen_blockage ());
10766 /* Expand the epilogue into a bunch of separate insns. */
10769 s390_emit_epilogue (bool sibcall
)
10771 rtx frame_pointer
, return_reg
, cfa_restores
= NULL_RTX
;
10772 int area_bottom
, area_top
, offset
= 0;
10777 if (TARGET_TPF_PROFILING
)
10780 /* Generate a BAS instruction to serve as a function
10781 entry intercept to facilitate the use of tracing
10782 algorithms located at the branch target. */
10784 /* Emit a blockage here so that all code
10785 lies between the profiling mechanisms. */
10786 emit_insn (gen_blockage ());
10788 emit_insn (gen_epilogue_tpf ());
10791 /* Check whether to use frame or stack pointer for restore. */
10793 frame_pointer
= (frame_pointer_needed
10794 ? hard_frame_pointer_rtx
: stack_pointer_rtx
);
10796 s390_frame_area (&area_bottom
, &area_top
);
10798 /* Check whether we can access the register save area.
10799 If not, increment the frame pointer as required. */
10801 if (area_top
<= area_bottom
)
10803 /* Nothing to restore. */
10805 else if (DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_bottom
)
10806 && DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_top
- 1))
10808 /* Area is in range. */
10809 offset
= cfun_frame_layout
.frame_size
;
10813 rtx insn
, frame_off
, cfa
;
10815 offset
= area_bottom
< 0 ? -area_bottom
: 0;
10816 frame_off
= GEN_INT (cfun_frame_layout
.frame_size
- offset
);
10818 cfa
= gen_rtx_SET (frame_pointer
,
10819 gen_rtx_PLUS (Pmode
, frame_pointer
, frame_off
));
10820 if (DISP_IN_RANGE (INTVAL (frame_off
)))
10822 insn
= gen_rtx_SET (frame_pointer
,
10823 gen_rtx_PLUS (Pmode
, frame_pointer
, frame_off
));
10824 insn
= emit_insn (insn
);
10828 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
10829 frame_off
= force_const_mem (Pmode
, frame_off
);
10831 insn
= emit_insn (gen_add2_insn (frame_pointer
, frame_off
));
10832 annotate_constant_pool_refs (&PATTERN (insn
));
10834 add_reg_note (insn
, REG_CFA_ADJUST_CFA
, cfa
);
10835 RTX_FRAME_RELATED_P (insn
) = 1;
10838 /* Restore call saved fprs. */
10842 if (cfun_save_high_fprs_p
)
10844 next_offset
= cfun_frame_layout
.f8_offset
;
10845 for (i
= FPR8_REGNUM
; i
<= FPR15_REGNUM
; i
++)
10847 if (cfun_fpr_save_p (i
))
10849 restore_fpr (frame_pointer
,
10850 offset
+ next_offset
, i
);
10852 = alloc_reg_note (REG_CFA_RESTORE
,
10853 gen_rtx_REG (DFmode
, i
), cfa_restores
);
10862 next_offset
= cfun_frame_layout
.f4_offset
;
10864 for (i
= FPR4_REGNUM
; i
<= FPR4_REGNUM
+ 1; i
++)
10866 if (cfun_fpr_save_p (i
))
10868 restore_fpr (frame_pointer
,
10869 offset
+ next_offset
, i
);
10871 = alloc_reg_note (REG_CFA_RESTORE
,
10872 gen_rtx_REG (DFmode
, i
), cfa_restores
);
10875 else if (!TARGET_PACKED_STACK
)
10881 /* Return register. */
10883 return_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
10885 /* Restore call saved gprs. */
10887 if (cfun_frame_layout
.first_restore_gpr
!= -1)
10892 /* Check for global register and save them
10893 to stack location from where they get restored. */
10895 for (i
= cfun_frame_layout
.first_restore_gpr
;
10896 i
<= cfun_frame_layout
.last_restore_gpr
;
10899 if (global_not_special_regno_p (i
))
10901 addr
= plus_constant (Pmode
, frame_pointer
,
10902 offset
+ cfun_frame_layout
.gprs_offset
10903 + (i
- cfun_frame_layout
.first_save_gpr_slot
)
10905 addr
= gen_rtx_MEM (Pmode
, addr
);
10906 set_mem_alias_set (addr
, get_frame_alias_set ());
10907 emit_move_insn (addr
, gen_rtx_REG (Pmode
, i
));
10911 = alloc_reg_note (REG_CFA_RESTORE
,
10912 gen_rtx_REG (Pmode
, i
), cfa_restores
);
10917 /* Fetch return address from stack before load multiple,
10918 this will do good for scheduling.
10920 Only do this if we already decided that r14 needs to be
10921 saved to a stack slot. (And not just because r14 happens to
10922 be in between two GPRs which need saving.) Otherwise it
10923 would be difficult to take that decision back in
10924 s390_optimize_prologue. */
10925 if (cfun_gpr_save_slot (RETURN_REGNUM
) == SAVE_SLOT_STACK
)
10927 int return_regnum
= find_unused_clobbered_reg();
10928 if (!return_regnum
)
10930 return_reg
= gen_rtx_REG (Pmode
, return_regnum
);
10932 addr
= plus_constant (Pmode
, frame_pointer
,
10933 offset
+ cfun_frame_layout
.gprs_offset
10935 - cfun_frame_layout
.first_save_gpr_slot
)
10937 addr
= gen_rtx_MEM (Pmode
, addr
);
10938 set_mem_alias_set (addr
, get_frame_alias_set ());
10939 emit_move_insn (return_reg
, addr
);
10941 /* Once we did that optimization we have to make sure
10942 s390_optimize_prologue does not try to remove the
10943 store of r14 since we will not be able to find the
10944 load issued here. */
10945 cfun_frame_layout
.save_return_addr_p
= true;
10949 insn
= restore_gprs (frame_pointer
,
10950 offset
+ cfun_frame_layout
.gprs_offset
10951 + (cfun_frame_layout
.first_restore_gpr
10952 - cfun_frame_layout
.first_save_gpr_slot
)
10954 cfun_frame_layout
.first_restore_gpr
,
10955 cfun_frame_layout
.last_restore_gpr
);
10956 insn
= emit_insn (insn
);
10957 REG_NOTES (insn
) = cfa_restores
;
10958 add_reg_note (insn
, REG_CFA_DEF_CFA
,
10959 plus_constant (Pmode
, stack_pointer_rtx
,
10960 STACK_POINTER_OFFSET
));
10961 RTX_FRAME_RELATED_P (insn
) = 1;
10964 s390_restore_gprs_from_fprs ();
10969 /* Return to caller. */
10971 p
= rtvec_alloc (2);
10973 RTVEC_ELT (p
, 0) = ret_rtx
;
10974 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
, return_reg
);
10975 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
10979 /* Implement TARGET_SET_UP_BY_PROLOGUE. */
10982 s300_set_up_by_prologue (hard_reg_set_container
*regs
)
10984 if (cfun
->machine
->base_reg
10985 && !call_really_used_regs
[REGNO (cfun
->machine
->base_reg
)])
10986 SET_HARD_REG_BIT (regs
->set
, REGNO (cfun
->machine
->base_reg
));
10989 /* -fsplit-stack support. */
10991 /* A SYMBOL_REF for __morestack. */
10992 static GTY(()) rtx morestack_ref
;
10994 /* When using -fsplit-stack, the allocation routines set a field in
10995 the TCB to the bottom of the stack plus this much space, measured
10998 #define SPLIT_STACK_AVAILABLE 1024
11000 /* Emit -fsplit-stack prologue, which goes before the regular function
11004 s390_expand_split_stack_prologue (void)
11006 rtx r1
, guard
, cc
= NULL
;
11008 /* Offset from thread pointer to __private_ss. */
11009 int psso
= TARGET_64BIT
? 0x38 : 0x20;
11010 /* Pointer size in bytes. */
11011 /* Frame size and argument size - the two parameters to __morestack. */
11012 HOST_WIDE_INT frame_size
= cfun_frame_layout
.frame_size
;
11013 /* Align argument size to 8 bytes - simplifies __morestack code. */
11014 HOST_WIDE_INT args_size
= crtl
->args
.size
>= 0
11015 ? ((crtl
->args
.size
+ 7) & ~7)
11017 /* Label to be called by __morestack. */
11018 rtx_code_label
*call_done
= NULL
;
11019 rtx_code_label
*parm_base
= NULL
;
11022 gcc_assert (flag_split_stack
&& reload_completed
);
11023 if (!TARGET_CPU_ZARCH
)
11025 sorry ("CPUs older than z900 are not supported for -fsplit-stack");
11029 r1
= gen_rtx_REG (Pmode
, 1);
11031 /* If no stack frame will be allocated, don't do anything. */
11034 if (cfun
->machine
->split_stack_varargs_pointer
!= NULL_RTX
)
11036 /* If va_start is used, just use r15. */
11037 emit_move_insn (r1
,
11038 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
11039 GEN_INT (STACK_POINTER_OFFSET
)));
11045 if (morestack_ref
== NULL_RTX
)
11047 morestack_ref
= gen_rtx_SYMBOL_REF (Pmode
, "__morestack");
11048 SYMBOL_REF_FLAGS (morestack_ref
) |= (SYMBOL_FLAG_LOCAL
11049 | SYMBOL_FLAG_FUNCTION
);
11052 if (CONST_OK_FOR_K (frame_size
) || CONST_OK_FOR_Op (frame_size
))
11054 /* If frame_size will fit in an add instruction, do a stack space
11055 check, and only call __morestack if there's not enough space. */
11057 /* Get thread pointer. r1 is the only register we can always destroy - r0
11058 could contain a static chain (and cannot be used to address memory
11059 anyway), r2-r6 can contain parameters, and r6-r15 are callee-saved. */
11060 emit_move_insn (r1
, gen_rtx_REG (Pmode
, TP_REGNUM
));
11061 /* Aim at __private_ss. */
11062 guard
= gen_rtx_MEM (Pmode
, plus_constant (Pmode
, r1
, psso
));
11064 /* If less that 1kiB used, skip addition and compare directly with
11066 if (frame_size
> SPLIT_STACK_AVAILABLE
)
11068 emit_move_insn (r1
, guard
);
11070 emit_insn (gen_adddi3 (r1
, r1
, GEN_INT (frame_size
)));
11072 emit_insn (gen_addsi3 (r1
, r1
, GEN_INT (frame_size
)));
11076 /* Compare the (maybe adjusted) guard with the stack pointer. */
11077 cc
= s390_emit_compare (LT
, stack_pointer_rtx
, guard
);
11080 call_done
= gen_label_rtx ();
11081 parm_base
= gen_label_rtx ();
11083 /* Emit the parameter block. */
11084 tmp
= gen_split_stack_data (parm_base
, call_done
,
11085 GEN_INT (frame_size
),
11086 GEN_INT (args_size
));
11087 insn
= emit_insn (tmp
);
11088 add_reg_note (insn
, REG_LABEL_OPERAND
, call_done
);
11089 LABEL_NUSES (call_done
)++;
11090 add_reg_note (insn
, REG_LABEL_OPERAND
, parm_base
);
11091 LABEL_NUSES (parm_base
)++;
11093 /* %r1 = litbase. */
11094 insn
= emit_move_insn (r1
, gen_rtx_LABEL_REF (VOIDmode
, parm_base
));
11095 add_reg_note (insn
, REG_LABEL_OPERAND
, parm_base
);
11096 LABEL_NUSES (parm_base
)++;
11098 /* Now, we need to call __morestack. It has very special calling
11099 conventions: it preserves param/return/static chain registers for
11100 calling main function body, and looks for its own parameters at %r1. */
11104 tmp
= gen_split_stack_cond_call (morestack_ref
, cc
, call_done
);
11106 insn
= emit_jump_insn (tmp
);
11107 JUMP_LABEL (insn
) = call_done
;
11108 LABEL_NUSES (call_done
)++;
11110 /* Mark the jump as very unlikely to be taken. */
11111 add_int_reg_note (insn
, REG_BR_PROB
, REG_BR_PROB_BASE
/ 100);
11113 if (cfun
->machine
->split_stack_varargs_pointer
!= NULL_RTX
)
11115 /* If va_start is used, and __morestack was not called, just use
11117 emit_move_insn (r1
,
11118 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
11119 GEN_INT (STACK_POINTER_OFFSET
)));
11124 tmp
= gen_split_stack_call (morestack_ref
, call_done
);
11125 insn
= emit_jump_insn (tmp
);
11126 JUMP_LABEL (insn
) = call_done
;
11127 LABEL_NUSES (call_done
)++;
11131 /* __morestack will call us here. */
11133 emit_label (call_done
);
11136 /* We may have to tell the dataflow pass that the split stack prologue
11137 is initializing a register. */
11140 s390_live_on_entry (bitmap regs
)
11142 if (cfun
->machine
->split_stack_varargs_pointer
!= NULL_RTX
)
11144 gcc_assert (flag_split_stack
);
11145 bitmap_set_bit (regs
, 1);
11149 /* Return true if the function can use simple_return to return outside
11150 of a shrink-wrapped region. At present shrink-wrapping is supported
11154 s390_can_use_simple_return_insn (void)
11159 /* Return true if the epilogue is guaranteed to contain only a return
11160 instruction and if a direct return can therefore be used instead.
11161 One of the main advantages of using direct return instructions
11162 is that we can then use conditional returns. */
11165 s390_can_use_return_insn (void)
11169 if (!reload_completed
)
11175 if (TARGET_TPF_PROFILING
)
11178 for (i
= 0; i
< 16; i
++)
11179 if (cfun_gpr_save_slot (i
) != SAVE_SLOT_NONE
)
11182 /* For 31 bit this is not covered by the frame_size check below
11183 since f4, f6 are saved in the register save area without needing
11184 additional stack space. */
11186 && (cfun_fpr_save_p (FPR4_REGNUM
) || cfun_fpr_save_p (FPR6_REGNUM
)))
11189 if (cfun
->machine
->base_reg
11190 && !call_really_used_regs
[REGNO (cfun
->machine
->base_reg
)])
11193 return cfun_frame_layout
.frame_size
== 0;
11196 /* The VX ABI differs for vararg functions. Therefore we need the
11197 prototype of the callee to be available when passing vector type
11199 static const char *
11200 s390_invalid_arg_for_unprototyped_fn (const_tree typelist
, const_tree funcdecl
, const_tree val
)
11202 return ((TARGET_VX_ABI
11204 && VECTOR_TYPE_P (TREE_TYPE (val
))
11205 && (funcdecl
== NULL_TREE
11206 || (TREE_CODE (funcdecl
) == FUNCTION_DECL
11207 && DECL_BUILT_IN_CLASS (funcdecl
) != BUILT_IN_MD
)))
11208 ? N_("Vector argument passed to unprototyped function")
11213 /* Return the size in bytes of a function argument of
11214 type TYPE and/or mode MODE. At least one of TYPE or
11215 MODE must be specified. */
11218 s390_function_arg_size (machine_mode mode
, const_tree type
)
11221 return int_size_in_bytes (type
);
11223 /* No type info available for some library calls ... */
11224 if (mode
!= BLKmode
)
11225 return GET_MODE_SIZE (mode
);
11227 /* If we have neither type nor mode, abort */
11228 gcc_unreachable ();
11231 /* Return true if a function argument of type TYPE and mode MODE
11232 is to be passed in a vector register, if available. */
11235 s390_function_arg_vector (machine_mode mode
, const_tree type
)
11237 if (!TARGET_VX_ABI
)
11240 if (s390_function_arg_size (mode
, type
) > 16)
11243 /* No type info available for some library calls ... */
11245 return VECTOR_MODE_P (mode
);
11247 /* The ABI says that record types with a single member are treated
11248 just like that member would be. */
11249 while (TREE_CODE (type
) == RECORD_TYPE
)
11251 tree field
, single
= NULL_TREE
;
11253 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
11255 if (TREE_CODE (field
) != FIELD_DECL
)
11258 if (single
== NULL_TREE
)
11259 single
= TREE_TYPE (field
);
11264 if (single
== NULL_TREE
)
11268 /* If the field declaration adds extra byte due to
11269 e.g. padding this is not accepted as vector type. */
11270 if (int_size_in_bytes (single
) <= 0
11271 || int_size_in_bytes (single
) != int_size_in_bytes (type
))
11277 return VECTOR_TYPE_P (type
);
11280 /* Return true if a function argument of type TYPE and mode MODE
11281 is to be passed in a floating-point register, if available. */
11284 s390_function_arg_float (machine_mode mode
, const_tree type
)
11286 if (s390_function_arg_size (mode
, type
) > 8)
11289 /* Soft-float changes the ABI: no floating-point registers are used. */
11290 if (TARGET_SOFT_FLOAT
)
11293 /* No type info available for some library calls ... */
11295 return mode
== SFmode
|| mode
== DFmode
|| mode
== SDmode
|| mode
== DDmode
;
11297 /* The ABI says that record types with a single member are treated
11298 just like that member would be. */
11299 while (TREE_CODE (type
) == RECORD_TYPE
)
11301 tree field
, single
= NULL_TREE
;
11303 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
11305 if (TREE_CODE (field
) != FIELD_DECL
)
11308 if (single
== NULL_TREE
)
11309 single
= TREE_TYPE (field
);
11314 if (single
== NULL_TREE
)
11320 return TREE_CODE (type
) == REAL_TYPE
;
11323 /* Return true if a function argument of type TYPE and mode MODE
11324 is to be passed in an integer register, or a pair of integer
11325 registers, if available. */
11328 s390_function_arg_integer (machine_mode mode
, const_tree type
)
11330 int size
= s390_function_arg_size (mode
, type
);
11334 /* No type info available for some library calls ... */
11336 return GET_MODE_CLASS (mode
) == MODE_INT
11337 || (TARGET_SOFT_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
));
11339 /* We accept small integral (and similar) types. */
11340 if (INTEGRAL_TYPE_P (type
)
11341 || POINTER_TYPE_P (type
)
11342 || TREE_CODE (type
) == NULLPTR_TYPE
11343 || TREE_CODE (type
) == OFFSET_TYPE
11344 || (TARGET_SOFT_FLOAT
&& TREE_CODE (type
) == REAL_TYPE
))
11347 /* We also accept structs of size 1, 2, 4, 8 that are not
11348 passed in floating-point registers. */
11349 if (AGGREGATE_TYPE_P (type
)
11350 && exact_log2 (size
) >= 0
11351 && !s390_function_arg_float (mode
, type
))
11357 /* Return 1 if a function argument of type TYPE and mode MODE
11358 is to be passed by reference. The ABI specifies that only
11359 structures of size 1, 2, 4, or 8 bytes are passed by value,
11360 all other structures (and complex numbers) are passed by
11364 s390_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED
,
11365 machine_mode mode
, const_tree type
,
11366 bool named ATTRIBUTE_UNUSED
)
11368 int size
= s390_function_arg_size (mode
, type
);
11370 if (s390_function_arg_vector (mode
, type
))
11378 if (AGGREGATE_TYPE_P (type
) && exact_log2 (size
) < 0)
11381 if (TREE_CODE (type
) == COMPLEX_TYPE
11382 || TREE_CODE (type
) == VECTOR_TYPE
)
11389 /* Update the data in CUM to advance over an argument of mode MODE and
11390 data type TYPE. (TYPE is null for libcalls where that information
11391 may not be available.). The boolean NAMED specifies whether the
11392 argument is a named argument (as opposed to an unnamed argument
11393 matching an ellipsis). */
11396 s390_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
11397 const_tree type
, bool named
)
11399 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
11401 if (s390_function_arg_vector (mode
, type
))
11403 /* We are called for unnamed vector stdarg arguments which are
11404 passed on the stack. In this case this hook does not have to
11405 do anything since stack arguments are tracked by common
11411 else if (s390_function_arg_float (mode
, type
))
11415 else if (s390_function_arg_integer (mode
, type
))
11417 int size
= s390_function_arg_size (mode
, type
);
11418 cum
->gprs
+= ((size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
);
11421 gcc_unreachable ();
11424 /* Define where to put the arguments to a function.
11425 Value is zero to push the argument on the stack,
11426 or a hard register in which to store the argument.
11428 MODE is the argument's machine mode.
11429 TYPE is the data type of the argument (as a tree).
11430 This is null for libcalls where that information may
11432 CUM is a variable of type CUMULATIVE_ARGS which gives info about
11433 the preceding args and about the function being called.
11434 NAMED is nonzero if this argument is a named parameter
11435 (otherwise it is an extra parameter matching an ellipsis).
11437 On S/390, we use general purpose registers 2 through 6 to
11438 pass integer, pointer, and certain structure arguments, and
11439 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
11440 to pass floating point arguments. All remaining arguments
11441 are pushed to the stack. */
11444 s390_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
11445 const_tree type
, bool named
)
11447 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
11450 s390_check_type_for_vector_abi (type
, true, false);
11452 if (s390_function_arg_vector (mode
, type
))
11454 /* Vector arguments being part of the ellipsis are passed on the
11456 if (!named
|| (cum
->vrs
+ 1 > VEC_ARG_NUM_REG
))
11459 return gen_rtx_REG (mode
, cum
->vrs
+ FIRST_VEC_ARG_REGNO
);
11461 else if (s390_function_arg_float (mode
, type
))
11463 if (cum
->fprs
+ 1 > FP_ARG_NUM_REG
)
11466 return gen_rtx_REG (mode
, cum
->fprs
+ 16);
11468 else if (s390_function_arg_integer (mode
, type
))
11470 int size
= s390_function_arg_size (mode
, type
);
11471 int n_gprs
= (size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
;
11473 if (cum
->gprs
+ n_gprs
> GP_ARG_NUM_REG
)
11475 else if (n_gprs
== 1 || UNITS_PER_WORD
== UNITS_PER_LONG
)
11476 return gen_rtx_REG (mode
, cum
->gprs
+ 2);
11477 else if (n_gprs
== 2)
11479 rtvec p
= rtvec_alloc (2);
11482 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, cum
->gprs
+ 2),
11485 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, cum
->gprs
+ 3),
11488 return gen_rtx_PARALLEL (mode
, p
);
11492 /* After the real arguments, expand_call calls us once again
11493 with a void_type_node type. Whatever we return here is
11494 passed as operand 2 to the call expanders.
11496 We don't need this feature ... */
11497 else if (type
== void_type_node
)
11500 gcc_unreachable ();
11503 /* Return true if return values of type TYPE should be returned
11504 in a memory buffer whose address is passed by the caller as
11505 hidden first argument. */
11508 s390_return_in_memory (const_tree type
, const_tree fundecl ATTRIBUTE_UNUSED
)
11510 /* We accept small integral (and similar) types. */
11511 if (INTEGRAL_TYPE_P (type
)
11512 || POINTER_TYPE_P (type
)
11513 || TREE_CODE (type
) == OFFSET_TYPE
11514 || TREE_CODE (type
) == REAL_TYPE
)
11515 return int_size_in_bytes (type
) > 8;
11517 /* vector types which fit into a VR. */
11519 && VECTOR_TYPE_P (type
)
11520 && int_size_in_bytes (type
) <= 16)
11523 /* Aggregates and similar constructs are always returned
11525 if (AGGREGATE_TYPE_P (type
)
11526 || TREE_CODE (type
) == COMPLEX_TYPE
11527 || VECTOR_TYPE_P (type
))
11530 /* ??? We get called on all sorts of random stuff from
11531 aggregate_value_p. We can't abort, but it's not clear
11532 what's safe to return. Pretend it's a struct I guess. */
11536 /* Function arguments and return values are promoted to word size. */
11538 static machine_mode
11539 s390_promote_function_mode (const_tree type
, machine_mode mode
,
11541 const_tree fntype ATTRIBUTE_UNUSED
,
11542 int for_return ATTRIBUTE_UNUSED
)
11544 if (INTEGRAL_MODE_P (mode
)
11545 && GET_MODE_SIZE (mode
) < UNITS_PER_LONG
)
11547 if (type
!= NULL_TREE
&& POINTER_TYPE_P (type
))
11548 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
11555 /* Define where to return a (scalar) value of type RET_TYPE.
11556 If RET_TYPE is null, define where to return a (scalar)
11557 value of mode MODE from a libcall. */
11560 s390_function_and_libcall_value (machine_mode mode
,
11561 const_tree ret_type
,
11562 const_tree fntype_or_decl
,
11563 bool outgoing ATTRIBUTE_UNUSED
)
11565 /* For vector return types it is important to use the RET_TYPE
11566 argument whenever available since the middle-end might have
11567 changed the mode to a scalar mode. */
11568 bool vector_ret_type_p
= ((ret_type
&& VECTOR_TYPE_P (ret_type
))
11569 || (!ret_type
&& VECTOR_MODE_P (mode
)));
11571 /* For normal functions perform the promotion as
11572 promote_function_mode would do. */
11575 int unsignedp
= TYPE_UNSIGNED (ret_type
);
11576 mode
= promote_function_mode (ret_type
, mode
, &unsignedp
,
11577 fntype_or_decl
, 1);
11580 gcc_assert (GET_MODE_CLASS (mode
) == MODE_INT
11581 || SCALAR_FLOAT_MODE_P (mode
)
11582 || (TARGET_VX_ABI
&& vector_ret_type_p
));
11583 gcc_assert (GET_MODE_SIZE (mode
) <= (TARGET_VX_ABI
? 16 : 8));
11585 if (TARGET_VX_ABI
&& vector_ret_type_p
)
11586 return gen_rtx_REG (mode
, FIRST_VEC_ARG_REGNO
);
11587 else if (TARGET_HARD_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
))
11588 return gen_rtx_REG (mode
, 16);
11589 else if (GET_MODE_SIZE (mode
) <= UNITS_PER_LONG
11590 || UNITS_PER_LONG
== UNITS_PER_WORD
)
11591 return gen_rtx_REG (mode
, 2);
11592 else if (GET_MODE_SIZE (mode
) == 2 * UNITS_PER_LONG
)
11594 /* This case is triggered when returning a 64 bit value with
11595 -m31 -mzarch. Although the value would fit into a single
11596 register it has to be forced into a 32 bit register pair in
11597 order to match the ABI. */
11598 rtvec p
= rtvec_alloc (2);
11601 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, 2), const0_rtx
);
11603 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, 3), GEN_INT (4));
11605 return gen_rtx_PARALLEL (mode
, p
);
11608 gcc_unreachable ();
11611 /* Define where to return a scalar return value of type RET_TYPE. */
11614 s390_function_value (const_tree ret_type
, const_tree fn_decl_or_type
,
11617 return s390_function_and_libcall_value (TYPE_MODE (ret_type
), ret_type
,
11618 fn_decl_or_type
, outgoing
);
11621 /* Define where to return a scalar libcall return value of mode
11625 s390_libcall_value (machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
11627 return s390_function_and_libcall_value (mode
, NULL_TREE
,
11632 /* Create and return the va_list datatype.
11634 On S/390, va_list is an array type equivalent to
11636 typedef struct __va_list_tag
11640 void *__overflow_arg_area;
11641 void *__reg_save_area;
11644 where __gpr and __fpr hold the number of general purpose
11645 or floating point arguments used up to now, respectively,
11646 __overflow_arg_area points to the stack location of the
11647 next argument passed on the stack, and __reg_save_area
11648 always points to the start of the register area in the
11649 call frame of the current function. The function prologue
11650 saves all registers used for argument passing into this
11651 area if the function uses variable arguments. */
11654 s390_build_builtin_va_list (void)
11656 tree f_gpr
, f_fpr
, f_ovf
, f_sav
, record
, type_decl
;
11658 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
11661 build_decl (BUILTINS_LOCATION
,
11662 TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
11664 f_gpr
= build_decl (BUILTINS_LOCATION
,
11665 FIELD_DECL
, get_identifier ("__gpr"),
11666 long_integer_type_node
);
11667 f_fpr
= build_decl (BUILTINS_LOCATION
,
11668 FIELD_DECL
, get_identifier ("__fpr"),
11669 long_integer_type_node
);
11670 f_ovf
= build_decl (BUILTINS_LOCATION
,
11671 FIELD_DECL
, get_identifier ("__overflow_arg_area"),
11673 f_sav
= build_decl (BUILTINS_LOCATION
,
11674 FIELD_DECL
, get_identifier ("__reg_save_area"),
11677 va_list_gpr_counter_field
= f_gpr
;
11678 va_list_fpr_counter_field
= f_fpr
;
11680 DECL_FIELD_CONTEXT (f_gpr
) = record
;
11681 DECL_FIELD_CONTEXT (f_fpr
) = record
;
11682 DECL_FIELD_CONTEXT (f_ovf
) = record
;
11683 DECL_FIELD_CONTEXT (f_sav
) = record
;
11685 TYPE_STUB_DECL (record
) = type_decl
;
11686 TYPE_NAME (record
) = type_decl
;
11687 TYPE_FIELDS (record
) = f_gpr
;
11688 DECL_CHAIN (f_gpr
) = f_fpr
;
11689 DECL_CHAIN (f_fpr
) = f_ovf
;
11690 DECL_CHAIN (f_ovf
) = f_sav
;
11692 layout_type (record
);
11694 /* The correct type is an array type of one element. */
11695 return build_array_type (record
, build_index_type (size_zero_node
));
11698 /* Implement va_start by filling the va_list structure VALIST.
11699 STDARG_P is always true, and ignored.
11700 NEXTARG points to the first anonymous stack argument.
11702 The following global variables are used to initialize
11703 the va_list structure:
11706 holds number of gprs and fprs used for named arguments.
11707 crtl->args.arg_offset_rtx:
11708 holds the offset of the first anonymous stack argument
11709 (relative to the virtual arg pointer). */
11712 s390_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
11714 HOST_WIDE_INT n_gpr
, n_fpr
;
11716 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
11717 tree gpr
, fpr
, ovf
, sav
, t
;
11719 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
11720 f_fpr
= DECL_CHAIN (f_gpr
);
11721 f_ovf
= DECL_CHAIN (f_fpr
);
11722 f_sav
= DECL_CHAIN (f_ovf
);
11724 valist
= build_simple_mem_ref (valist
);
11725 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
11726 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
11727 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
11728 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
11730 /* Count number of gp and fp argument registers used. */
11732 n_gpr
= crtl
->args
.info
.gprs
;
11733 n_fpr
= crtl
->args
.info
.fprs
;
11735 if (cfun
->va_list_gpr_size
)
11737 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
11738 build_int_cst (NULL_TREE
, n_gpr
));
11739 TREE_SIDE_EFFECTS (t
) = 1;
11740 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
11743 if (cfun
->va_list_fpr_size
)
11745 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
11746 build_int_cst (NULL_TREE
, n_fpr
));
11747 TREE_SIDE_EFFECTS (t
) = 1;
11748 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
11751 if (flag_split_stack
11752 && (lookup_attribute ("no_split_stack", DECL_ATTRIBUTES (cfun
->decl
))
11754 && cfun
->machine
->split_stack_varargs_pointer
== NULL_RTX
)
11759 reg
= gen_reg_rtx (Pmode
);
11760 cfun
->machine
->split_stack_varargs_pointer
= reg
;
11763 emit_move_insn (reg
, gen_rtx_REG (Pmode
, 1));
11764 seq
= get_insns ();
11767 push_topmost_sequence ();
11768 emit_insn_after (seq
, entry_of_function ());
11769 pop_topmost_sequence ();
11772 /* Find the overflow area.
11773 FIXME: This currently is too pessimistic when the vector ABI is
11774 enabled. In that case we *always* set up the overflow area
11776 if (n_gpr
+ cfun
->va_list_gpr_size
> GP_ARG_NUM_REG
11777 || n_fpr
+ cfun
->va_list_fpr_size
> FP_ARG_NUM_REG
11780 if (cfun
->machine
->split_stack_varargs_pointer
== NULL_RTX
)
11781 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
11783 t
= make_tree (TREE_TYPE (ovf
), cfun
->machine
->split_stack_varargs_pointer
);
11785 off
= INTVAL (crtl
->args
.arg_offset_rtx
);
11786 off
= off
< 0 ? 0 : off
;
11787 if (TARGET_DEBUG_ARG
)
11788 fprintf (stderr
, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
11789 (int)n_gpr
, (int)n_fpr
, off
);
11791 t
= fold_build_pointer_plus_hwi (t
, off
);
11793 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
11794 TREE_SIDE_EFFECTS (t
) = 1;
11795 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
11798 /* Find the register save area. */
11799 if ((cfun
->va_list_gpr_size
&& n_gpr
< GP_ARG_NUM_REG
)
11800 || (cfun
->va_list_fpr_size
&& n_fpr
< FP_ARG_NUM_REG
))
11802 t
= make_tree (TREE_TYPE (sav
), return_address_pointer_rtx
);
11803 t
= fold_build_pointer_plus_hwi (t
, -RETURN_REGNUM
* UNITS_PER_LONG
);
11805 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
11806 TREE_SIDE_EFFECTS (t
) = 1;
11807 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
11811 /* Implement va_arg by updating the va_list structure
11812 VALIST as required to retrieve an argument of type
11813 TYPE, and returning that argument.
11815 Generates code equivalent to:
11817 if (integral value) {
11818 if (size <= 4 && args.gpr < 5 ||
11819 size > 4 && args.gpr < 4 )
11820 ret = args.reg_save_area[args.gpr+8]
11822 ret = *args.overflow_arg_area++;
11823 } else if (vector value) {
11824 ret = *args.overflow_arg_area;
11825 args.overflow_arg_area += size / 8;
11826 } else if (float value) {
11828 ret = args.reg_save_area[args.fpr+64]
11830 ret = *args.overflow_arg_area++;
11831 } else if (aggregate value) {
11833 ret = *args.reg_save_area[args.gpr]
11835 ret = **args.overflow_arg_area++;
11839 s390_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
11840 gimple_seq
*post_p ATTRIBUTE_UNUSED
)
11842 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
11843 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
11844 int indirect_p
, size
, n_reg
, sav_ofs
, sav_scale
, max_reg
;
11845 tree lab_false
, lab_over
;
11846 tree addr
= create_tmp_var (ptr_type_node
, "addr");
11847 bool left_align_p
; /* How a value < UNITS_PER_LONG is aligned within
11850 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
11851 f_fpr
= DECL_CHAIN (f_gpr
);
11852 f_ovf
= DECL_CHAIN (f_fpr
);
11853 f_sav
= DECL_CHAIN (f_ovf
);
11855 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
11856 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
11857 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
11859 /* The tree for args* cannot be shared between gpr/fpr and ovf since
11860 both appear on a lhs. */
11861 valist
= unshare_expr (valist
);
11862 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
11864 size
= int_size_in_bytes (type
);
11866 s390_check_type_for_vector_abi (type
, true, false);
11868 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
11870 if (TARGET_DEBUG_ARG
)
11872 fprintf (stderr
, "va_arg: aggregate type");
11876 /* Aggregates are passed by reference. */
11881 /* kernel stack layout on 31 bit: It is assumed here that no padding
11882 will be added by s390_frame_info because for va_args always an even
11883 number of gprs has to be saved r15-r2 = 14 regs. */
11884 sav_ofs
= 2 * UNITS_PER_LONG
;
11885 sav_scale
= UNITS_PER_LONG
;
11886 size
= UNITS_PER_LONG
;
11887 max_reg
= GP_ARG_NUM_REG
- n_reg
;
11888 left_align_p
= false;
11890 else if (s390_function_arg_vector (TYPE_MODE (type
), type
))
11892 if (TARGET_DEBUG_ARG
)
11894 fprintf (stderr
, "va_arg: vector type");
11904 left_align_p
= true;
11906 else if (s390_function_arg_float (TYPE_MODE (type
), type
))
11908 if (TARGET_DEBUG_ARG
)
11910 fprintf (stderr
, "va_arg: float type");
11914 /* FP args go in FP registers, if present. */
11918 sav_ofs
= 16 * UNITS_PER_LONG
;
11920 max_reg
= FP_ARG_NUM_REG
- n_reg
;
11921 left_align_p
= false;
11925 if (TARGET_DEBUG_ARG
)
11927 fprintf (stderr
, "va_arg: other type");
11931 /* Otherwise into GP registers. */
11934 n_reg
= (size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
;
11936 /* kernel stack layout on 31 bit: It is assumed here that no padding
11937 will be added by s390_frame_info because for va_args always an even
11938 number of gprs has to be saved r15-r2 = 14 regs. */
11939 sav_ofs
= 2 * UNITS_PER_LONG
;
11941 if (size
< UNITS_PER_LONG
)
11942 sav_ofs
+= UNITS_PER_LONG
- size
;
11944 sav_scale
= UNITS_PER_LONG
;
11945 max_reg
= GP_ARG_NUM_REG
- n_reg
;
11946 left_align_p
= false;
11949 /* Pull the value out of the saved registers ... */
11951 if (reg
!= NULL_TREE
)
11954 if (reg > ((typeof (reg))max_reg))
11957 addr = sav + sav_ofs + reg * save_scale;
11964 lab_false
= create_artificial_label (UNKNOWN_LOCATION
);
11965 lab_over
= create_artificial_label (UNKNOWN_LOCATION
);
11967 t
= fold_convert (TREE_TYPE (reg
), size_int (max_reg
));
11968 t
= build2 (GT_EXPR
, boolean_type_node
, reg
, t
);
11969 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
11970 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
11971 gimplify_and_add (t
, pre_p
);
11973 t
= fold_build_pointer_plus_hwi (sav
, sav_ofs
);
11974 u
= build2 (MULT_EXPR
, TREE_TYPE (reg
), reg
,
11975 fold_convert (TREE_TYPE (reg
), size_int (sav_scale
)));
11976 t
= fold_build_pointer_plus (t
, u
);
11978 gimplify_assign (addr
, t
, pre_p
);
11980 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
11982 gimple_seq_add_stmt (pre_p
, gimple_build_label (lab_false
));
11985 /* ... Otherwise out of the overflow area. */
11988 if (size
< UNITS_PER_LONG
&& !left_align_p
)
11989 t
= fold_build_pointer_plus_hwi (t
, UNITS_PER_LONG
- size
);
11991 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
11993 gimplify_assign (addr
, t
, pre_p
);
11995 if (size
< UNITS_PER_LONG
&& left_align_p
)
11996 t
= fold_build_pointer_plus_hwi (t
, UNITS_PER_LONG
);
11998 t
= fold_build_pointer_plus_hwi (t
, size
);
12000 gimplify_assign (ovf
, t
, pre_p
);
12002 if (reg
!= NULL_TREE
)
12003 gimple_seq_add_stmt (pre_p
, gimple_build_label (lab_over
));
12006 /* Increment register save count. */
12010 u
= build2 (PREINCREMENT_EXPR
, TREE_TYPE (reg
), reg
,
12011 fold_convert (TREE_TYPE (reg
), size_int (n_reg
)));
12012 gimplify_and_add (u
, pre_p
);
12017 t
= build_pointer_type_for_mode (build_pointer_type (type
),
12019 addr
= fold_convert (t
, addr
);
12020 addr
= build_va_arg_indirect_ref (addr
);
12024 t
= build_pointer_type_for_mode (type
, ptr_mode
, true);
12025 addr
= fold_convert (t
, addr
);
12028 return build_va_arg_indirect_ref (addr
);
12031 /* Emit rtl for the tbegin or tbegin_retry (RETRY != NULL_RTX)
12033 DEST - Register location where CC will be stored.
12034 TDB - Pointer to a 256 byte area where to store the transaction.
12035 diagnostic block. NULL if TDB is not needed.
12036 RETRY - Retry count value. If non-NULL a retry loop for CC2
12038 CLOBBER_FPRS_P - If true clobbers for all FPRs are emitted as part
12039 of the tbegin instruction pattern. */
12042 s390_expand_tbegin (rtx dest
, rtx tdb
, rtx retry
, bool clobber_fprs_p
)
12044 rtx retry_plus_two
= gen_reg_rtx (SImode
);
12045 rtx retry_reg
= gen_reg_rtx (SImode
);
12046 rtx_code_label
*retry_label
= NULL
;
12048 if (retry
!= NULL_RTX
)
12050 emit_move_insn (retry_reg
, retry
);
12051 emit_insn (gen_addsi3 (retry_plus_two
, retry_reg
, const2_rtx
));
12052 emit_insn (gen_addsi3 (retry_reg
, retry_reg
, const1_rtx
));
12053 retry_label
= gen_label_rtx ();
12054 emit_label (retry_label
);
12057 if (clobber_fprs_p
)
12060 emit_insn (gen_tbegin_1_z13 (gen_rtx_CONST_INT (VOIDmode
, TBEGIN_MASK
),
12063 emit_insn (gen_tbegin_1 (gen_rtx_CONST_INT (VOIDmode
, TBEGIN_MASK
),
12067 emit_insn (gen_tbegin_nofloat_1 (gen_rtx_CONST_INT (VOIDmode
, TBEGIN_MASK
),
12070 emit_move_insn (dest
, gen_rtx_UNSPEC (SImode
,
12071 gen_rtvec (1, gen_rtx_REG (CCRAWmode
,
12073 UNSPEC_CC_TO_INT
));
12074 if (retry
!= NULL_RTX
)
12076 const int CC0
= 1 << 3;
12077 const int CC1
= 1 << 2;
12078 const int CC3
= 1 << 0;
12080 rtx count
= gen_reg_rtx (SImode
);
12081 rtx_code_label
*leave_label
= gen_label_rtx ();
12083 /* Exit for success and permanent failures. */
12084 jump
= s390_emit_jump (leave_label
,
12085 gen_rtx_EQ (VOIDmode
,
12086 gen_rtx_REG (CCRAWmode
, CC_REGNUM
),
12087 gen_rtx_CONST_INT (VOIDmode
, CC0
| CC1
| CC3
)));
12088 LABEL_NUSES (leave_label
) = 1;
12090 /* CC2 - transient failure. Perform retry with ppa. */
12091 emit_move_insn (count
, retry_plus_two
);
12092 emit_insn (gen_subsi3 (count
, count
, retry_reg
));
12093 emit_insn (gen_tx_assist (count
));
12094 jump
= emit_jump_insn (gen_doloop_si64 (retry_label
,
12097 JUMP_LABEL (jump
) = retry_label
;
12098 LABEL_NUSES (retry_label
) = 1;
12099 emit_label (leave_label
);
12104 /* Return the decl for the target specific builtin with the function
12108 s390_builtin_decl (unsigned fcode
, bool initialized_p ATTRIBUTE_UNUSED
)
12110 if (fcode
>= S390_BUILTIN_MAX
)
12111 return error_mark_node
;
12113 return s390_builtin_decls
[fcode
];
12116 /* We call mcount before the function prologue. So a profiled leaf
12117 function should stay a leaf function. */
12120 s390_keep_leaf_when_profiled ()
12125 /* Output assembly code for the trampoline template to
12128 On S/390, we use gpr 1 internally in the trampoline code;
12129 gpr 0 is used to hold the static chain. */
12132 s390_asm_trampoline_template (FILE *file
)
12135 op
[0] = gen_rtx_REG (Pmode
, 0);
12136 op
[1] = gen_rtx_REG (Pmode
, 1);
12140 output_asm_insn ("basr\t%1,0", op
); /* 2 byte */
12141 output_asm_insn ("lmg\t%0,%1,14(%1)", op
); /* 6 byte */
12142 output_asm_insn ("br\t%1", op
); /* 2 byte */
12143 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 10));
12147 output_asm_insn ("basr\t%1,0", op
); /* 2 byte */
12148 output_asm_insn ("lm\t%0,%1,6(%1)", op
); /* 4 byte */
12149 output_asm_insn ("br\t%1", op
); /* 2 byte */
12150 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 8));
12154 /* Emit RTL insns to initialize the variable parts of a trampoline.
12155 FNADDR is an RTX for the address of the function's pure code.
12156 CXT is an RTX for the static chain value for the function. */
12159 s390_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
12161 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
12164 emit_block_move (m_tramp
, assemble_trampoline_template (),
12165 GEN_INT (2 * UNITS_PER_LONG
), BLOCK_OP_NORMAL
);
12167 mem
= adjust_address (m_tramp
, Pmode
, 2 * UNITS_PER_LONG
);
12168 emit_move_insn (mem
, cxt
);
12169 mem
= adjust_address (m_tramp
, Pmode
, 3 * UNITS_PER_LONG
);
12170 emit_move_insn (mem
, fnaddr
);
12173 /* Output assembler code to FILE to increment profiler label # LABELNO
12174 for profiling a function entry. */
12177 s390_function_profiler (FILE *file
, int labelno
)
12182 ASM_GENERATE_INTERNAL_LABEL (label
, "LP", labelno
);
12184 fprintf (file
, "# function profiler \n");
12186 op
[0] = gen_rtx_REG (Pmode
, RETURN_REGNUM
);
12187 op
[1] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
12188 op
[1] = gen_rtx_MEM (Pmode
, plus_constant (Pmode
, op
[1], UNITS_PER_LONG
));
12190 op
[2] = gen_rtx_REG (Pmode
, 1);
12191 op
[3] = gen_rtx_SYMBOL_REF (Pmode
, label
);
12192 SYMBOL_REF_FLAGS (op
[3]) = SYMBOL_FLAG_LOCAL
;
12194 op
[4] = gen_rtx_SYMBOL_REF (Pmode
, "_mcount");
12197 op
[4] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[4]), UNSPEC_PLT
);
12198 op
[4] = gen_rtx_CONST (Pmode
, op
[4]);
12203 output_asm_insn ("stg\t%0,%1", op
);
12204 output_asm_insn ("larl\t%2,%3", op
);
12205 output_asm_insn ("brasl\t%0,%4", op
);
12206 output_asm_insn ("lg\t%0,%1", op
);
12208 else if (!flag_pic
)
12210 op
[6] = gen_label_rtx ();
12212 output_asm_insn ("st\t%0,%1", op
);
12213 output_asm_insn ("bras\t%2,%l6", op
);
12214 output_asm_insn (".long\t%4", op
);
12215 output_asm_insn (".long\t%3", op
);
12216 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
12217 output_asm_insn ("l\t%0,0(%2)", op
);
12218 output_asm_insn ("l\t%2,4(%2)", op
);
12219 output_asm_insn ("basr\t%0,%0", op
);
12220 output_asm_insn ("l\t%0,%1", op
);
12224 op
[5] = gen_label_rtx ();
12225 op
[6] = gen_label_rtx ();
12227 output_asm_insn ("st\t%0,%1", op
);
12228 output_asm_insn ("bras\t%2,%l6", op
);
12229 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[5]));
12230 output_asm_insn (".long\t%4-%l5", op
);
12231 output_asm_insn (".long\t%3-%l5", op
);
12232 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
12233 output_asm_insn ("lr\t%0,%2", op
);
12234 output_asm_insn ("a\t%0,0(%2)", op
);
12235 output_asm_insn ("a\t%2,4(%2)", op
);
12236 output_asm_insn ("basr\t%0,%0", op
);
12237 output_asm_insn ("l\t%0,%1", op
);
12241 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
12242 into its SYMBOL_REF_FLAGS. */
12245 s390_encode_section_info (tree decl
, rtx rtl
, int first
)
12247 default_encode_section_info (decl
, rtl
, first
);
12249 if (TREE_CODE (decl
) == VAR_DECL
)
12251 /* Store the alignment to be able to check if we can use
12252 a larl/load-relative instruction. We only handle the cases
12253 that can go wrong (i.e. no FUNC_DECLs). If a symref does
12254 not have any flag we assume it to be correctly aligned. */
12256 if (DECL_ALIGN (decl
) % 64)
12257 SYMBOL_FLAG_SET_NOTALIGN8 (XEXP (rtl
, 0));
12259 if (DECL_ALIGN (decl
) % 32)
12260 SYMBOL_FLAG_SET_NOTALIGN4 (XEXP (rtl
, 0));
12262 if (DECL_ALIGN (decl
) == 0 || DECL_ALIGN (decl
) % 16)
12263 SYMBOL_FLAG_SET_NOTALIGN2 (XEXP (rtl
, 0));
12266 /* Literal pool references don't have a decl so they are handled
12267 differently here. We rely on the information in the MEM_ALIGN
12268 entry to decide upon the alignment. */
12270 && GET_CODE (XEXP (rtl
, 0)) == SYMBOL_REF
12271 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl
, 0))
12272 && MEM_ALIGN (rtl
) != 0
12273 && GET_MODE_BITSIZE (GET_MODE (rtl
)) != 0)
12275 if (MEM_ALIGN (rtl
) % 64)
12276 SYMBOL_FLAG_SET_NOTALIGN8 (XEXP (rtl
, 0));
12278 if (MEM_ALIGN (rtl
) % 32)
12279 SYMBOL_FLAG_SET_NOTALIGN4 (XEXP (rtl
, 0));
12281 if (MEM_ALIGN (rtl
) == 0 || MEM_ALIGN (rtl
) % 16)
12282 SYMBOL_FLAG_SET_NOTALIGN2 (XEXP (rtl
, 0));
12286 /* Output thunk to FILE that implements a C++ virtual function call (with
12287 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
12288 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
12289 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
12290 relative to the resulting this pointer. */
12293 s390_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
12294 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
12300 /* Make sure unwind info is emitted for the thunk if needed. */
12301 final_start_function (emit_barrier (), file
, 1);
12303 /* Operand 0 is the target function. */
12304 op
[0] = XEXP (DECL_RTL (function
), 0);
12305 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (op
[0]))
12308 op
[0] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[0]),
12309 TARGET_64BIT
? UNSPEC_PLT
: UNSPEC_GOT
);
12310 op
[0] = gen_rtx_CONST (Pmode
, op
[0]);
12313 /* Operand 1 is the 'this' pointer. */
12314 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
12315 op
[1] = gen_rtx_REG (Pmode
, 3);
12317 op
[1] = gen_rtx_REG (Pmode
, 2);
12319 /* Operand 2 is the delta. */
12320 op
[2] = GEN_INT (delta
);
12322 /* Operand 3 is the vcall_offset. */
12323 op
[3] = GEN_INT (vcall_offset
);
12325 /* Operand 4 is the temporary register. */
12326 op
[4] = gen_rtx_REG (Pmode
, 1);
12328 /* Operands 5 to 8 can be used as labels. */
12334 /* Operand 9 can be used for temporary register. */
12337 /* Generate code. */
12340 /* Setup literal pool pointer if required. */
12341 if ((!DISP_IN_RANGE (delta
)
12342 && !CONST_OK_FOR_K (delta
)
12343 && !CONST_OK_FOR_Os (delta
))
12344 || (!DISP_IN_RANGE (vcall_offset
)
12345 && !CONST_OK_FOR_K (vcall_offset
)
12346 && !CONST_OK_FOR_Os (vcall_offset
)))
12348 op
[5] = gen_label_rtx ();
12349 output_asm_insn ("larl\t%4,%5", op
);
12352 /* Add DELTA to this pointer. */
12355 if (CONST_OK_FOR_J (delta
))
12356 output_asm_insn ("la\t%1,%2(%1)", op
);
12357 else if (DISP_IN_RANGE (delta
))
12358 output_asm_insn ("lay\t%1,%2(%1)", op
);
12359 else if (CONST_OK_FOR_K (delta
))
12360 output_asm_insn ("aghi\t%1,%2", op
);
12361 else if (CONST_OK_FOR_Os (delta
))
12362 output_asm_insn ("agfi\t%1,%2", op
);
12365 op
[6] = gen_label_rtx ();
12366 output_asm_insn ("agf\t%1,%6-%5(%4)", op
);
12370 /* Perform vcall adjustment. */
12373 if (DISP_IN_RANGE (vcall_offset
))
12375 output_asm_insn ("lg\t%4,0(%1)", op
);
12376 output_asm_insn ("ag\t%1,%3(%4)", op
);
12378 else if (CONST_OK_FOR_K (vcall_offset
))
12380 output_asm_insn ("lghi\t%4,%3", op
);
12381 output_asm_insn ("ag\t%4,0(%1)", op
);
12382 output_asm_insn ("ag\t%1,0(%4)", op
);
12384 else if (CONST_OK_FOR_Os (vcall_offset
))
12386 output_asm_insn ("lgfi\t%4,%3", op
);
12387 output_asm_insn ("ag\t%4,0(%1)", op
);
12388 output_asm_insn ("ag\t%1,0(%4)", op
);
12392 op
[7] = gen_label_rtx ();
12393 output_asm_insn ("llgf\t%4,%7-%5(%4)", op
);
12394 output_asm_insn ("ag\t%4,0(%1)", op
);
12395 output_asm_insn ("ag\t%1,0(%4)", op
);
12399 /* Jump to target. */
12400 output_asm_insn ("jg\t%0", op
);
12402 /* Output literal pool if required. */
12405 output_asm_insn (".align\t4", op
);
12406 targetm
.asm_out
.internal_label (file
, "L",
12407 CODE_LABEL_NUMBER (op
[5]));
12411 targetm
.asm_out
.internal_label (file
, "L",
12412 CODE_LABEL_NUMBER (op
[6]));
12413 output_asm_insn (".long\t%2", op
);
12417 targetm
.asm_out
.internal_label (file
, "L",
12418 CODE_LABEL_NUMBER (op
[7]));
12419 output_asm_insn (".long\t%3", op
);
12424 /* Setup base pointer if required. */
12426 || (!DISP_IN_RANGE (delta
)
12427 && !CONST_OK_FOR_K (delta
)
12428 && !CONST_OK_FOR_Os (delta
))
12429 || (!DISP_IN_RANGE (delta
)
12430 && !CONST_OK_FOR_K (vcall_offset
)
12431 && !CONST_OK_FOR_Os (vcall_offset
)))
12433 op
[5] = gen_label_rtx ();
12434 output_asm_insn ("basr\t%4,0", op
);
12435 targetm
.asm_out
.internal_label (file
, "L",
12436 CODE_LABEL_NUMBER (op
[5]));
12439 /* Add DELTA to this pointer. */
12442 if (CONST_OK_FOR_J (delta
))
12443 output_asm_insn ("la\t%1,%2(%1)", op
);
12444 else if (DISP_IN_RANGE (delta
))
12445 output_asm_insn ("lay\t%1,%2(%1)", op
);
12446 else if (CONST_OK_FOR_K (delta
))
12447 output_asm_insn ("ahi\t%1,%2", op
);
12448 else if (CONST_OK_FOR_Os (delta
))
12449 output_asm_insn ("afi\t%1,%2", op
);
12452 op
[6] = gen_label_rtx ();
12453 output_asm_insn ("a\t%1,%6-%5(%4)", op
);
12457 /* Perform vcall adjustment. */
12460 if (CONST_OK_FOR_J (vcall_offset
))
12462 output_asm_insn ("l\t%4,0(%1)", op
);
12463 output_asm_insn ("a\t%1,%3(%4)", op
);
12465 else if (DISP_IN_RANGE (vcall_offset
))
12467 output_asm_insn ("l\t%4,0(%1)", op
);
12468 output_asm_insn ("ay\t%1,%3(%4)", op
);
12470 else if (CONST_OK_FOR_K (vcall_offset
))
12472 output_asm_insn ("lhi\t%4,%3", op
);
12473 output_asm_insn ("a\t%4,0(%1)", op
);
12474 output_asm_insn ("a\t%1,0(%4)", op
);
12476 else if (CONST_OK_FOR_Os (vcall_offset
))
12478 output_asm_insn ("iilf\t%4,%3", op
);
12479 output_asm_insn ("a\t%4,0(%1)", op
);
12480 output_asm_insn ("a\t%1,0(%4)", op
);
12484 op
[7] = gen_label_rtx ();
12485 output_asm_insn ("l\t%4,%7-%5(%4)", op
);
12486 output_asm_insn ("a\t%4,0(%1)", op
);
12487 output_asm_insn ("a\t%1,0(%4)", op
);
12490 /* We had to clobber the base pointer register.
12491 Re-setup the base pointer (with a different base). */
12492 op
[5] = gen_label_rtx ();
12493 output_asm_insn ("basr\t%4,0", op
);
12494 targetm
.asm_out
.internal_label (file
, "L",
12495 CODE_LABEL_NUMBER (op
[5]));
12498 /* Jump to target. */
12499 op
[8] = gen_label_rtx ();
12502 output_asm_insn ("l\t%4,%8-%5(%4)", op
);
12503 else if (!nonlocal
)
12504 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
12505 /* We cannot call through .plt, since .plt requires %r12 loaded. */
12506 else if (flag_pic
== 1)
12508 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
12509 output_asm_insn ("l\t%4,%0(%4)", op
);
12511 else if (flag_pic
== 2)
12513 op
[9] = gen_rtx_REG (Pmode
, 0);
12514 output_asm_insn ("l\t%9,%8-4-%5(%4)", op
);
12515 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
12516 output_asm_insn ("ar\t%4,%9", op
);
12517 output_asm_insn ("l\t%4,0(%4)", op
);
12520 output_asm_insn ("br\t%4", op
);
12522 /* Output literal pool. */
12523 output_asm_insn (".align\t4", op
);
12525 if (nonlocal
&& flag_pic
== 2)
12526 output_asm_insn (".long\t%0", op
);
12529 op
[0] = gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
12530 SYMBOL_REF_FLAGS (op
[0]) = SYMBOL_FLAG_LOCAL
;
12533 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[8]));
12535 output_asm_insn (".long\t%0", op
);
12537 output_asm_insn (".long\t%0-%5", op
);
12541 targetm
.asm_out
.internal_label (file
, "L",
12542 CODE_LABEL_NUMBER (op
[6]));
12543 output_asm_insn (".long\t%2", op
);
12547 targetm
.asm_out
.internal_label (file
, "L",
12548 CODE_LABEL_NUMBER (op
[7]));
12549 output_asm_insn (".long\t%3", op
);
12552 final_end_function ();
12556 s390_valid_pointer_mode (machine_mode mode
)
12558 return (mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
));
12561 /* Checks whether the given CALL_EXPR would use a caller
12562 saved register. This is used to decide whether sibling call
12563 optimization could be performed on the respective function
12567 s390_call_saved_register_used (tree call_expr
)
12569 CUMULATIVE_ARGS cum_v
;
12570 cumulative_args_t cum
;
12577 INIT_CUMULATIVE_ARGS (cum_v
, NULL
, NULL
, 0, 0);
12578 cum
= pack_cumulative_args (&cum_v
);
12580 for (i
= 0; i
< call_expr_nargs (call_expr
); i
++)
12582 parameter
= CALL_EXPR_ARG (call_expr
, i
);
12583 gcc_assert (parameter
);
12585 /* For an undeclared variable passed as parameter we will get
12586 an ERROR_MARK node here. */
12587 if (TREE_CODE (parameter
) == ERROR_MARK
)
12590 type
= TREE_TYPE (parameter
);
12593 mode
= TYPE_MODE (type
);
12596 /* We assume that in the target function all parameters are
12597 named. This only has an impact on vector argument register
12598 usage none of which is call-saved. */
12599 if (pass_by_reference (&cum_v
, mode
, type
, true))
12602 type
= build_pointer_type (type
);
12605 parm_rtx
= s390_function_arg (cum
, mode
, type
, true);
12607 s390_function_arg_advance (cum
, mode
, type
, true);
12612 if (REG_P (parm_rtx
))
12615 reg
< HARD_REGNO_NREGS (REGNO (parm_rtx
), GET_MODE (parm_rtx
));
12617 if (!call_used_regs
[reg
+ REGNO (parm_rtx
)])
12621 if (GET_CODE (parm_rtx
) == PARALLEL
)
12625 for (i
= 0; i
< XVECLEN (parm_rtx
, 0); i
++)
12627 rtx r
= XEXP (XVECEXP (parm_rtx
, 0, i
), 0);
12629 gcc_assert (REG_P (r
));
12632 reg
< HARD_REGNO_NREGS (REGNO (r
), GET_MODE (r
));
12634 if (!call_used_regs
[reg
+ REGNO (r
)])
12643 /* Return true if the given call expression can be
12644 turned into a sibling call.
12645 DECL holds the declaration of the function to be called whereas
12646 EXP is the call expression itself. */
12649 s390_function_ok_for_sibcall (tree decl
, tree exp
)
12651 /* The TPF epilogue uses register 1. */
12652 if (TARGET_TPF_PROFILING
)
12655 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
12656 which would have to be restored before the sibcall. */
12657 if (!TARGET_64BIT
&& flag_pic
&& decl
&& !targetm
.binds_local_p (decl
))
12660 /* Register 6 on s390 is available as an argument register but unfortunately
12661 "caller saved". This makes functions needing this register for arguments
12662 not suitable for sibcalls. */
12663 return !s390_call_saved_register_used (exp
);
12666 /* Return the fixed registers used for condition codes. */
12669 s390_fixed_condition_code_regs (unsigned int *p1
, unsigned int *p2
)
12672 *p2
= INVALID_REGNUM
;
12677 /* This function is used by the call expanders of the machine description.
12678 It emits the call insn itself together with the necessary operations
12679 to adjust the target address and returns the emitted insn.
12680 ADDR_LOCATION is the target address rtx
12681 TLS_CALL the location of the thread-local symbol
12682 RESULT_REG the register where the result of the call should be stored
12683 RETADDR_REG the register where the return address should be stored
12684 If this parameter is NULL_RTX the call is considered
12685 to be a sibling call. */
12688 s390_emit_call (rtx addr_location
, rtx tls_call
, rtx result_reg
,
12691 bool plt_call
= false;
12697 /* Direct function calls need special treatment. */
12698 if (GET_CODE (addr_location
) == SYMBOL_REF
)
12700 /* When calling a global routine in PIC mode, we must
12701 replace the symbol itself with the PLT stub. */
12702 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (addr_location
))
12704 if (TARGET_64BIT
|| retaddr_reg
!= NULL_RTX
)
12706 addr_location
= gen_rtx_UNSPEC (Pmode
,
12707 gen_rtvec (1, addr_location
),
12709 addr_location
= gen_rtx_CONST (Pmode
, addr_location
);
12713 /* For -fpic code the PLT entries might use r12 which is
12714 call-saved. Therefore we cannot do a sibcall when
12715 calling directly using a symbol ref. When reaching
12716 this point we decided (in s390_function_ok_for_sibcall)
12717 to do a sibcall for a function pointer but one of the
12718 optimizers was able to get rid of the function pointer
12719 by propagating the symbol ref into the call. This
12720 optimization is illegal for S/390 so we turn the direct
12721 call into a indirect call again. */
12722 addr_location
= force_reg (Pmode
, addr_location
);
12725 /* Unless we can use the bras(l) insn, force the
12726 routine address into a register. */
12727 if (!TARGET_SMALL_EXEC
&& !TARGET_CPU_ZARCH
)
12730 addr_location
= legitimize_pic_address (addr_location
, 0);
12732 addr_location
= force_reg (Pmode
, addr_location
);
12736 /* If it is already an indirect call or the code above moved the
12737 SYMBOL_REF to somewhere else make sure the address can be found in
12739 if (retaddr_reg
== NULL_RTX
12740 && GET_CODE (addr_location
) != SYMBOL_REF
12743 emit_move_insn (gen_rtx_REG (Pmode
, SIBCALL_REGNUM
), addr_location
);
12744 addr_location
= gen_rtx_REG (Pmode
, SIBCALL_REGNUM
);
12747 addr_location
= gen_rtx_MEM (QImode
, addr_location
);
12748 call
= gen_rtx_CALL (VOIDmode
, addr_location
, const0_rtx
);
12750 if (result_reg
!= NULL_RTX
)
12751 call
= gen_rtx_SET (result_reg
, call
);
12753 if (retaddr_reg
!= NULL_RTX
)
12755 clobber
= gen_rtx_CLOBBER (VOIDmode
, retaddr_reg
);
12757 if (tls_call
!= NULL_RTX
)
12758 vec
= gen_rtvec (3, call
, clobber
,
12759 gen_rtx_USE (VOIDmode
, tls_call
));
12761 vec
= gen_rtvec (2, call
, clobber
);
12763 call
= gen_rtx_PARALLEL (VOIDmode
, vec
);
12766 insn
= emit_call_insn (call
);
12768 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
12769 if ((!TARGET_64BIT
&& plt_call
) || tls_call
!= NULL_RTX
)
12771 /* s390_function_ok_for_sibcall should
12772 have denied sibcalls in this case. */
12773 gcc_assert (retaddr_reg
!= NULL_RTX
);
12774 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), gen_rtx_REG (Pmode
, 12));
12779 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
12782 s390_conditional_register_usage (void)
12788 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
12789 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
12791 if (TARGET_CPU_ZARCH
)
12793 fixed_regs
[BASE_REGNUM
] = 0;
12794 call_used_regs
[BASE_REGNUM
] = 0;
12795 fixed_regs
[RETURN_REGNUM
] = 0;
12796 call_used_regs
[RETURN_REGNUM
] = 0;
12800 for (i
= FPR8_REGNUM
; i
<= FPR15_REGNUM
; i
++)
12801 call_used_regs
[i
] = call_really_used_regs
[i
] = 0;
12805 call_used_regs
[FPR4_REGNUM
] = call_really_used_regs
[FPR4_REGNUM
] = 0;
12806 call_used_regs
[FPR6_REGNUM
] = call_really_used_regs
[FPR6_REGNUM
] = 0;
12809 if (TARGET_SOFT_FLOAT
)
12811 for (i
= FPR0_REGNUM
; i
<= FPR15_REGNUM
; i
++)
12812 call_used_regs
[i
] = fixed_regs
[i
] = 1;
12815 /* Disable v16 - v31 for non-vector target. */
12818 for (i
= VR16_REGNUM
; i
<= VR31_REGNUM
; i
++)
12819 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
12823 /* Corresponding function to eh_return expander. */
12825 static GTY(()) rtx s390_tpf_eh_return_symbol
;
12827 s390_emit_tpf_eh_return (rtx target
)
12832 if (!s390_tpf_eh_return_symbol
)
12833 s390_tpf_eh_return_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tpf_eh_return");
12835 reg
= gen_rtx_REG (Pmode
, 2);
12836 orig_ra
= gen_rtx_REG (Pmode
, 3);
12838 emit_move_insn (reg
, target
);
12839 emit_move_insn (orig_ra
, get_hard_reg_initial_val (Pmode
, RETURN_REGNUM
));
12840 insn
= s390_emit_call (s390_tpf_eh_return_symbol
, NULL_RTX
, reg
,
12841 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
12842 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
12843 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), orig_ra
);
12845 emit_move_insn (EH_RETURN_HANDLER_RTX
, reg
);
12848 /* Rework the prologue/epilogue to avoid saving/restoring
12849 registers unnecessarily. */
12852 s390_optimize_prologue (void)
12854 rtx_insn
*insn
, *new_insn
, *next_insn
;
12856 /* Do a final recompute of the frame-related data. */
12857 s390_optimize_register_info ();
12859 /* If all special registers are in fact used, there's nothing we
12860 can do, so no point in walking the insn list. */
12862 if (cfun_frame_layout
.first_save_gpr
<= BASE_REGNUM
12863 && cfun_frame_layout
.last_save_gpr
>= BASE_REGNUM
12864 && (TARGET_CPU_ZARCH
12865 || (cfun_frame_layout
.first_save_gpr
<= RETURN_REGNUM
12866 && cfun_frame_layout
.last_save_gpr
>= RETURN_REGNUM
)))
12869 /* Search for prologue/epilogue insns and replace them. */
12871 for (insn
= get_insns (); insn
; insn
= next_insn
)
12873 int first
, last
, off
;
12874 rtx set
, base
, offset
;
12877 next_insn
= NEXT_INSN (insn
);
12879 if (! NONJUMP_INSN_P (insn
) || ! RTX_FRAME_RELATED_P (insn
))
12882 pat
= PATTERN (insn
);
12884 /* Remove ldgr/lgdr instructions used for saving and restore
12885 GPRs if possible. */
12887 && GET_CODE (pat
) == SET
12888 && GET_MODE (SET_SRC (pat
)) == DImode
12889 && REG_P (SET_SRC (pat
))
12890 && REG_P (SET_DEST (pat
)))
12892 int src_regno
= REGNO (SET_SRC (pat
));
12893 int dest_regno
= REGNO (SET_DEST (pat
));
12897 if (!((GENERAL_REGNO_P (src_regno
) && FP_REGNO_P (dest_regno
))
12898 || (FP_REGNO_P (src_regno
) && GENERAL_REGNO_P (dest_regno
))))
12901 gpr_regno
= GENERAL_REGNO_P (src_regno
) ? src_regno
: dest_regno
;
12902 fpr_regno
= FP_REGNO_P (src_regno
) ? src_regno
: dest_regno
;
12904 /* GPR must be call-saved, FPR must be call-clobbered. */
12905 if (!call_really_used_regs
[fpr_regno
]
12906 || call_really_used_regs
[gpr_regno
])
12909 /* It must not happen that what we once saved in an FPR now
12910 needs a stack slot. */
12911 gcc_assert (cfun_gpr_save_slot (gpr_regno
) != SAVE_SLOT_STACK
);
12913 if (cfun_gpr_save_slot (gpr_regno
) == SAVE_SLOT_NONE
)
12915 remove_insn (insn
);
12920 if (GET_CODE (pat
) == PARALLEL
12921 && store_multiple_operation (pat
, VOIDmode
))
12923 set
= XVECEXP (pat
, 0, 0);
12924 first
= REGNO (SET_SRC (set
));
12925 last
= first
+ XVECLEN (pat
, 0) - 1;
12926 offset
= const0_rtx
;
12927 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
12928 off
= INTVAL (offset
);
12930 if (GET_CODE (base
) != REG
|| off
< 0)
12932 if (cfun_frame_layout
.first_save_gpr
!= -1
12933 && (cfun_frame_layout
.first_save_gpr
< first
12934 || cfun_frame_layout
.last_save_gpr
> last
))
12936 if (REGNO (base
) != STACK_POINTER_REGNUM
12937 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
12939 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
12942 if (cfun_frame_layout
.first_save_gpr
!= -1)
12944 rtx s_pat
= save_gprs (base
,
12945 off
+ (cfun_frame_layout
.first_save_gpr
12946 - first
) * UNITS_PER_LONG
,
12947 cfun_frame_layout
.first_save_gpr
,
12948 cfun_frame_layout
.last_save_gpr
);
12949 new_insn
= emit_insn_before (s_pat
, insn
);
12950 INSN_ADDRESSES_NEW (new_insn
, -1);
12953 remove_insn (insn
);
12957 if (cfun_frame_layout
.first_save_gpr
== -1
12958 && GET_CODE (pat
) == SET
12959 && GENERAL_REG_P (SET_SRC (pat
))
12960 && GET_CODE (SET_DEST (pat
)) == MEM
)
12963 first
= REGNO (SET_SRC (set
));
12964 offset
= const0_rtx
;
12965 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
12966 off
= INTVAL (offset
);
12968 if (GET_CODE (base
) != REG
|| off
< 0)
12970 if (REGNO (base
) != STACK_POINTER_REGNUM
12971 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
12974 remove_insn (insn
);
12978 if (GET_CODE (pat
) == PARALLEL
12979 && load_multiple_operation (pat
, VOIDmode
))
12981 set
= XVECEXP (pat
, 0, 0);
12982 first
= REGNO (SET_DEST (set
));
12983 last
= first
+ XVECLEN (pat
, 0) - 1;
12984 offset
= const0_rtx
;
12985 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
12986 off
= INTVAL (offset
);
12988 if (GET_CODE (base
) != REG
|| off
< 0)
12991 if (cfun_frame_layout
.first_restore_gpr
!= -1
12992 && (cfun_frame_layout
.first_restore_gpr
< first
12993 || cfun_frame_layout
.last_restore_gpr
> last
))
12995 if (REGNO (base
) != STACK_POINTER_REGNUM
12996 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
12998 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
13001 if (cfun_frame_layout
.first_restore_gpr
!= -1)
13003 rtx rpat
= restore_gprs (base
,
13004 off
+ (cfun_frame_layout
.first_restore_gpr
13005 - first
) * UNITS_PER_LONG
,
13006 cfun_frame_layout
.first_restore_gpr
,
13007 cfun_frame_layout
.last_restore_gpr
);
13009 /* Remove REG_CFA_RESTOREs for registers that we no
13010 longer need to save. */
13011 REG_NOTES (rpat
) = REG_NOTES (insn
);
13012 for (rtx
*ptr
= ®_NOTES (rpat
); *ptr
; )
13013 if (REG_NOTE_KIND (*ptr
) == REG_CFA_RESTORE
13014 && ((int) REGNO (XEXP (*ptr
, 0))
13015 < cfun_frame_layout
.first_restore_gpr
))
13016 *ptr
= XEXP (*ptr
, 1);
13018 ptr
= &XEXP (*ptr
, 1);
13019 new_insn
= emit_insn_before (rpat
, insn
);
13020 RTX_FRAME_RELATED_P (new_insn
) = 1;
13021 INSN_ADDRESSES_NEW (new_insn
, -1);
13024 remove_insn (insn
);
13028 if (cfun_frame_layout
.first_restore_gpr
== -1
13029 && GET_CODE (pat
) == SET
13030 && GENERAL_REG_P (SET_DEST (pat
))
13031 && GET_CODE (SET_SRC (pat
)) == MEM
)
13034 first
= REGNO (SET_DEST (set
));
13035 offset
= const0_rtx
;
13036 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
13037 off
= INTVAL (offset
);
13039 if (GET_CODE (base
) != REG
|| off
< 0)
13042 if (REGNO (base
) != STACK_POINTER_REGNUM
13043 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
13046 remove_insn (insn
);
13052 /* On z10 and later the dynamic branch prediction must see the
13053 backward jump within a certain windows. If not it falls back to
13054 the static prediction. This function rearranges the loop backward
13055 branch in a way which makes the static prediction always correct.
13056 The function returns true if it added an instruction. */
13058 s390_fix_long_loop_prediction (rtx_insn
*insn
)
13060 rtx set
= single_set (insn
);
13061 rtx code_label
, label_ref
, new_label
;
13062 rtx_insn
*uncond_jump
;
13063 rtx_insn
*cur_insn
;
13067 /* This will exclude branch on count and branch on index patterns
13068 since these are correctly statically predicted. */
13070 || SET_DEST (set
) != pc_rtx
13071 || GET_CODE (SET_SRC(set
)) != IF_THEN_ELSE
)
13074 /* Skip conditional returns. */
13075 if (ANY_RETURN_P (XEXP (SET_SRC (set
), 1))
13076 && XEXP (SET_SRC (set
), 2) == pc_rtx
)
13079 label_ref
= (GET_CODE (XEXP (SET_SRC (set
), 1)) == LABEL_REF
?
13080 XEXP (SET_SRC (set
), 1) : XEXP (SET_SRC (set
), 2));
13082 gcc_assert (GET_CODE (label_ref
) == LABEL_REF
);
13084 code_label
= XEXP (label_ref
, 0);
13086 if (INSN_ADDRESSES (INSN_UID (code_label
)) == -1
13087 || INSN_ADDRESSES (INSN_UID (insn
)) == -1
13088 || (INSN_ADDRESSES (INSN_UID (insn
))
13089 - INSN_ADDRESSES (INSN_UID (code_label
)) < PREDICT_DISTANCE
))
13092 for (distance
= 0, cur_insn
= PREV_INSN (insn
);
13093 distance
< PREDICT_DISTANCE
- 6;
13094 distance
+= get_attr_length (cur_insn
), cur_insn
= PREV_INSN (cur_insn
))
13095 if (!cur_insn
|| JUMP_P (cur_insn
) || LABEL_P (cur_insn
))
13098 new_label
= gen_label_rtx ();
13099 uncond_jump
= emit_jump_insn_after (
13100 gen_rtx_SET (pc_rtx
,
13101 gen_rtx_LABEL_REF (VOIDmode
, code_label
)),
13103 emit_label_after (new_label
, uncond_jump
);
13105 tmp
= XEXP (SET_SRC (set
), 1);
13106 XEXP (SET_SRC (set
), 1) = XEXP (SET_SRC (set
), 2);
13107 XEXP (SET_SRC (set
), 2) = tmp
;
13108 INSN_CODE (insn
) = -1;
13110 XEXP (label_ref
, 0) = new_label
;
13111 JUMP_LABEL (insn
) = new_label
;
13112 JUMP_LABEL (uncond_jump
) = code_label
;
13117 /* Returns 1 if INSN reads the value of REG for purposes not related
13118 to addressing of memory, and 0 otherwise. */
13120 s390_non_addr_reg_read_p (rtx reg
, rtx_insn
*insn
)
13122 return reg_referenced_p (reg
, PATTERN (insn
))
13123 && !reg_used_in_mem_p (REGNO (reg
), PATTERN (insn
));
13126 /* Starting from INSN find_cond_jump looks downwards in the insn
13127 stream for a single jump insn which is the last user of the
13128 condition code set in INSN. */
13130 find_cond_jump (rtx_insn
*insn
)
13132 for (; insn
; insn
= NEXT_INSN (insn
))
13136 if (LABEL_P (insn
))
13139 if (!JUMP_P (insn
))
13141 if (reg_mentioned_p (gen_rtx_REG (CCmode
, CC_REGNUM
), insn
))
13146 /* This will be triggered by a return. */
13147 if (GET_CODE (PATTERN (insn
)) != SET
)
13150 gcc_assert (SET_DEST (PATTERN (insn
)) == pc_rtx
);
13151 ite
= SET_SRC (PATTERN (insn
));
13153 if (GET_CODE (ite
) != IF_THEN_ELSE
)
13156 cc
= XEXP (XEXP (ite
, 0), 0);
13157 if (!REG_P (cc
) || !CC_REGNO_P (REGNO (cc
)))
13160 if (find_reg_note (insn
, REG_DEAD
, cc
))
13168 /* Swap the condition in COND and the operands in OP0 and OP1 so that
13169 the semantics does not change. If NULL_RTX is passed as COND the
13170 function tries to find the conditional jump starting with INSN. */
13172 s390_swap_cmp (rtx cond
, rtx
*op0
, rtx
*op1
, rtx_insn
*insn
)
13176 if (cond
== NULL_RTX
)
13178 rtx_insn
*jump
= find_cond_jump (NEXT_INSN (insn
));
13179 rtx set
= jump
? single_set (jump
) : NULL_RTX
;
13181 if (set
== NULL_RTX
)
13184 cond
= XEXP (SET_SRC (set
), 0);
13189 PUT_CODE (cond
, swap_condition (GET_CODE (cond
)));
13192 /* On z10, instructions of the compare-and-branch family have the
13193 property to access the register occurring as second operand with
13194 its bits complemented. If such a compare is grouped with a second
13195 instruction that accesses the same register non-complemented, and
13196 if that register's value is delivered via a bypass, then the
13197 pipeline recycles, thereby causing significant performance decline.
13198 This function locates such situations and exchanges the two
13199 operands of the compare. The function return true whenever it
13202 s390_z10_optimize_cmp (rtx_insn
*insn
)
13204 rtx_insn
*prev_insn
, *next_insn
;
13205 bool insn_added_p
= false;
13206 rtx cond
, *op0
, *op1
;
13208 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
13210 /* Handle compare and branch and branch on count
13212 rtx pattern
= single_set (insn
);
13215 || SET_DEST (pattern
) != pc_rtx
13216 || GET_CODE (SET_SRC (pattern
)) != IF_THEN_ELSE
)
13219 cond
= XEXP (SET_SRC (pattern
), 0);
13220 op0
= &XEXP (cond
, 0);
13221 op1
= &XEXP (cond
, 1);
13223 else if (GET_CODE (PATTERN (insn
)) == SET
)
13227 /* Handle normal compare instructions. */
13228 src
= SET_SRC (PATTERN (insn
));
13229 dest
= SET_DEST (PATTERN (insn
));
13232 || !CC_REGNO_P (REGNO (dest
))
13233 || GET_CODE (src
) != COMPARE
)
13236 /* s390_swap_cmp will try to find the conditional
13237 jump when passing NULL_RTX as condition. */
13239 op0
= &XEXP (src
, 0);
13240 op1
= &XEXP (src
, 1);
13245 if (!REG_P (*op0
) || !REG_P (*op1
))
13248 if (GET_MODE_CLASS (GET_MODE (*op0
)) != MODE_INT
)
13251 /* Swap the COMPARE arguments and its mask if there is a
13252 conflicting access in the previous insn. */
13253 prev_insn
= prev_active_insn (insn
);
13254 if (prev_insn
!= NULL_RTX
&& INSN_P (prev_insn
)
13255 && reg_referenced_p (*op1
, PATTERN (prev_insn
)))
13256 s390_swap_cmp (cond
, op0
, op1
, insn
);
13258 /* Check if there is a conflict with the next insn. If there
13259 was no conflict with the previous insn, then swap the
13260 COMPARE arguments and its mask. If we already swapped
13261 the operands, or if swapping them would cause a conflict
13262 with the previous insn, issue a NOP after the COMPARE in
13263 order to separate the two instuctions. */
13264 next_insn
= next_active_insn (insn
);
13265 if (next_insn
!= NULL_RTX
&& INSN_P (next_insn
)
13266 && s390_non_addr_reg_read_p (*op1
, next_insn
))
13268 if (prev_insn
!= NULL_RTX
&& INSN_P (prev_insn
)
13269 && s390_non_addr_reg_read_p (*op0
, prev_insn
))
13271 if (REGNO (*op1
) == 0)
13272 emit_insn_after (gen_nop1 (), insn
);
13274 emit_insn_after (gen_nop (), insn
);
13275 insn_added_p
= true;
13278 s390_swap_cmp (cond
, op0
, op1
, insn
);
13280 return insn_added_p
;
13283 /* Perform machine-dependent processing. */
13288 bool pool_overflow
= false;
13289 int hw_before
, hw_after
;
13291 /* Make sure all splits have been performed; splits after
13292 machine_dependent_reorg might confuse insn length counts. */
13293 split_all_insns_noflow ();
13295 /* Install the main literal pool and the associated base
13296 register load insns.
13298 In addition, there are two problematic situations we need
13301 - the literal pool might be > 4096 bytes in size, so that
13302 some of its elements cannot be directly accessed
13304 - a branch target might be > 64K away from the branch, so that
13305 it is not possible to use a PC-relative instruction.
13307 To fix those, we split the single literal pool into multiple
13308 pool chunks, reloading the pool base register at various
13309 points throughout the function to ensure it always points to
13310 the pool chunk the following code expects, and / or replace
13311 PC-relative branches by absolute branches.
13313 However, the two problems are interdependent: splitting the
13314 literal pool can move a branch further away from its target,
13315 causing the 64K limit to overflow, and on the other hand,
13316 replacing a PC-relative branch by an absolute branch means
13317 we need to put the branch target address into the literal
13318 pool, possibly causing it to overflow.
13320 So, we loop trying to fix up both problems until we manage
13321 to satisfy both conditions at the same time. Note that the
13322 loop is guaranteed to terminate as every pass of the loop
13323 strictly decreases the total number of PC-relative branches
13324 in the function. (This is not completely true as there
13325 might be branch-over-pool insns introduced by chunkify_start.
13326 Those never need to be split however.) */
13330 struct constant_pool
*pool
= NULL
;
13332 /* Collect the literal pool. */
13333 if (!pool_overflow
)
13335 pool
= s390_mainpool_start ();
13337 pool_overflow
= true;
13340 /* If literal pool overflowed, start to chunkify it. */
13342 pool
= s390_chunkify_start ();
13344 /* Split out-of-range branches. If this has created new
13345 literal pool entries, cancel current chunk list and
13346 recompute it. zSeries machines have large branch
13347 instructions, so we never need to split a branch. */
13348 if (!TARGET_CPU_ZARCH
&& s390_split_branches ())
13351 s390_chunkify_cancel (pool
);
13353 s390_mainpool_cancel (pool
);
13358 /* If we made it up to here, both conditions are satisfied.
13359 Finish up literal pool related changes. */
13361 s390_chunkify_finish (pool
);
13363 s390_mainpool_finish (pool
);
13365 /* We're done splitting branches. */
13366 cfun
->machine
->split_branches_pending_p
= false;
13370 /* Generate out-of-pool execute target insns. */
13371 if (TARGET_CPU_ZARCH
)
13373 rtx_insn
*insn
, *target
;
13376 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
13378 label
= s390_execute_label (insn
);
13382 gcc_assert (label
!= const0_rtx
);
13384 target
= emit_label (XEXP (label
, 0));
13385 INSN_ADDRESSES_NEW (target
, -1);
13387 target
= emit_insn (s390_execute_target (insn
));
13388 INSN_ADDRESSES_NEW (target
, -1);
13392 /* Try to optimize prologue and epilogue further. */
13393 s390_optimize_prologue ();
13395 /* Walk over the insns and do some >=z10 specific changes. */
13396 if (s390_tune
>= PROCESSOR_2097_Z10
)
13399 bool insn_added_p
= false;
13401 /* The insn lengths and addresses have to be up to date for the
13402 following manipulations. */
13403 shorten_branches (get_insns ());
13405 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
13407 if (!INSN_P (insn
) || INSN_CODE (insn
) <= 0)
13411 insn_added_p
|= s390_fix_long_loop_prediction (insn
);
13413 if ((GET_CODE (PATTERN (insn
)) == PARALLEL
13414 || GET_CODE (PATTERN (insn
)) == SET
)
13415 && s390_tune
== PROCESSOR_2097_Z10
)
13416 insn_added_p
|= s390_z10_optimize_cmp (insn
);
13419 /* Adjust branches if we added new instructions. */
13421 shorten_branches (get_insns ());
13424 s390_function_num_hotpatch_hw (current_function_decl
, &hw_before
, &hw_after
);
13429 /* Insert NOPs for hotpatching. */
13430 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
13432 1. inside the area covered by debug information to allow setting
13433 breakpoints at the NOPs,
13434 2. before any insn which results in an asm instruction,
13435 3. before in-function labels to avoid jumping to the NOPs, for
13436 example as part of a loop,
13437 4. before any barrier in case the function is completely empty
13438 (__builtin_unreachable ()) and has neither internal labels nor
13441 if (active_insn_p (insn
) || BARRIER_P (insn
) || LABEL_P (insn
))
13443 /* Output a series of NOPs before the first active insn. */
13444 while (insn
&& hw_after
> 0)
13446 if (hw_after
>= 3 && TARGET_CPU_ZARCH
)
13448 emit_insn_before (gen_nop_6_byte (), insn
);
13451 else if (hw_after
>= 2)
13453 emit_insn_before (gen_nop_4_byte (), insn
);
13458 emit_insn_before (gen_nop_2_byte (), insn
);
13465 /* Return true if INSN is a fp load insn writing register REGNO. */
13467 s390_fpload_toreg (rtx_insn
*insn
, unsigned int regno
)
13470 enum attr_type flag
= s390_safe_attr_type (insn
);
13472 if (flag
!= TYPE_FLOADSF
&& flag
!= TYPE_FLOADDF
)
13475 set
= single_set (insn
);
13477 if (set
== NULL_RTX
)
13480 if (!REG_P (SET_DEST (set
)) || !MEM_P (SET_SRC (set
)))
13483 if (REGNO (SET_DEST (set
)) != regno
)
13489 /* This value describes the distance to be avoided between an
13490 aritmetic fp instruction and an fp load writing the same register.
13491 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
13492 fine but the exact value has to be avoided. Otherwise the FP
13493 pipeline will throw an exception causing a major penalty. */
13494 #define Z10_EARLYLOAD_DISTANCE 7
13496 /* Rearrange the ready list in order to avoid the situation described
13497 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
13498 moved to the very end of the ready list. */
13500 s390_z10_prevent_earlyload_conflicts (rtx_insn
**ready
, int *nready_p
)
13502 unsigned int regno
;
13503 int nready
= *nready_p
;
13508 enum attr_type flag
;
13511 /* Skip DISTANCE - 1 active insns. */
13512 for (insn
= last_scheduled_insn
, distance
= Z10_EARLYLOAD_DISTANCE
- 1;
13513 distance
> 0 && insn
!= NULL_RTX
;
13514 distance
--, insn
= prev_active_insn (insn
))
13515 if (CALL_P (insn
) || JUMP_P (insn
))
13518 if (insn
== NULL_RTX
)
13521 set
= single_set (insn
);
13523 if (set
== NULL_RTX
|| !REG_P (SET_DEST (set
))
13524 || GET_MODE_CLASS (GET_MODE (SET_DEST (set
))) != MODE_FLOAT
)
13527 flag
= s390_safe_attr_type (insn
);
13529 if (flag
== TYPE_FLOADSF
|| flag
== TYPE_FLOADDF
)
13532 regno
= REGNO (SET_DEST (set
));
13535 while (!s390_fpload_toreg (ready
[i
], regno
) && i
> 0)
13542 memmove (&ready
[1], &ready
[0], sizeof (rtx_insn
*) * i
);
13547 /* The s390_sched_state variable tracks the state of the current or
13548 the last instruction group.
13550 0,1,2 number of instructions scheduled in the current group
13551 3 the last group is complete - normal insns
13552 4 the last group was a cracked/expanded insn */
13554 static int s390_sched_state
;
13556 #define S390_OOO_SCHED_STATE_NORMAL 3
13557 #define S390_OOO_SCHED_STATE_CRACKED 4
13559 #define S390_OOO_SCHED_ATTR_MASK_CRACKED 0x1
13560 #define S390_OOO_SCHED_ATTR_MASK_EXPANDED 0x2
13561 #define S390_OOO_SCHED_ATTR_MASK_ENDGROUP 0x4
13562 #define S390_OOO_SCHED_ATTR_MASK_GROUPALONE 0x8
13564 static unsigned int
13565 s390_get_sched_attrmask (rtx_insn
*insn
)
13567 unsigned int mask
= 0;
13569 if (get_attr_ooo_cracked (insn
))
13570 mask
|= S390_OOO_SCHED_ATTR_MASK_CRACKED
;
13571 if (get_attr_ooo_expanded (insn
))
13572 mask
|= S390_OOO_SCHED_ATTR_MASK_EXPANDED
;
13573 if (get_attr_ooo_endgroup (insn
))
13574 mask
|= S390_OOO_SCHED_ATTR_MASK_ENDGROUP
;
13575 if (get_attr_ooo_groupalone (insn
))
13576 mask
|= S390_OOO_SCHED_ATTR_MASK_GROUPALONE
;
13580 /* Return the scheduling score for INSN. The higher the score the
13581 better. The score is calculated from the OOO scheduling attributes
13582 of INSN and the scheduling state s390_sched_state. */
13584 s390_sched_score (rtx_insn
*insn
)
13586 unsigned int mask
= s390_get_sched_attrmask (insn
);
13589 switch (s390_sched_state
)
13592 /* Try to put insns into the first slot which would otherwise
13594 if ((mask
& S390_OOO_SCHED_ATTR_MASK_CRACKED
) != 0
13595 || (mask
& S390_OOO_SCHED_ATTR_MASK_EXPANDED
) != 0)
13597 if ((mask
& S390_OOO_SCHED_ATTR_MASK_GROUPALONE
) != 0)
13600 /* Prefer not cracked insns while trying to put together a
13602 if ((mask
& S390_OOO_SCHED_ATTR_MASK_CRACKED
) == 0
13603 && (mask
& S390_OOO_SCHED_ATTR_MASK_EXPANDED
) == 0
13604 && (mask
& S390_OOO_SCHED_ATTR_MASK_GROUPALONE
) == 0)
13606 if ((mask
& S390_OOO_SCHED_ATTR_MASK_ENDGROUP
) == 0)
13610 /* Prefer not cracked insns while trying to put together a
13612 if ((mask
& S390_OOO_SCHED_ATTR_MASK_CRACKED
) == 0
13613 && (mask
& S390_OOO_SCHED_ATTR_MASK_EXPANDED
) == 0
13614 && (mask
& S390_OOO_SCHED_ATTR_MASK_GROUPALONE
) == 0)
13616 /* Prefer endgroup insns in the last slot. */
13617 if ((mask
& S390_OOO_SCHED_ATTR_MASK_ENDGROUP
) != 0)
13620 case S390_OOO_SCHED_STATE_NORMAL
:
13621 /* Prefer not cracked insns if the last was not cracked. */
13622 if ((mask
& S390_OOO_SCHED_ATTR_MASK_CRACKED
) == 0
13623 && (mask
& S390_OOO_SCHED_ATTR_MASK_EXPANDED
) == 0)
13625 if ((mask
& S390_OOO_SCHED_ATTR_MASK_GROUPALONE
) != 0)
13628 case S390_OOO_SCHED_STATE_CRACKED
:
13629 /* Try to keep cracked insns together to prevent them from
13630 interrupting groups. */
13631 if ((mask
& S390_OOO_SCHED_ATTR_MASK_CRACKED
) != 0
13632 || (mask
& S390_OOO_SCHED_ATTR_MASK_EXPANDED
) != 0)
13639 /* This function is called via hook TARGET_SCHED_REORDER before
13640 issuing one insn from list READY which contains *NREADYP entries.
13641 For target z10 it reorders load instructions to avoid early load
13642 conflicts in the floating point pipeline */
13644 s390_sched_reorder (FILE *file
, int verbose
,
13645 rtx_insn
**ready
, int *nreadyp
, int clock ATTRIBUTE_UNUSED
)
13647 if (s390_tune
== PROCESSOR_2097_Z10
13648 && reload_completed
13650 s390_z10_prevent_earlyload_conflicts (ready
, nreadyp
);
13652 if (s390_tune
>= PROCESSOR_2827_ZEC12
13653 && reload_completed
13657 int last_index
= *nreadyp
- 1;
13658 int max_index
= -1;
13659 int max_score
= -1;
13662 /* Just move the insn with the highest score to the top (the
13663 end) of the list. A full sort is not needed since a conflict
13664 in the hazard recognition cannot happen. So the top insn in
13665 the ready list will always be taken. */
13666 for (i
= last_index
; i
>= 0; i
--)
13670 if (recog_memoized (ready
[i
]) < 0)
13673 score
= s390_sched_score (ready
[i
]);
13674 if (score
> max_score
)
13681 if (max_index
!= -1)
13683 if (max_index
!= last_index
)
13685 tmp
= ready
[max_index
];
13686 ready
[max_index
] = ready
[last_index
];
13687 ready
[last_index
] = tmp
;
13691 "move insn %d to the top of list\n",
13692 INSN_UID (ready
[last_index
]));
13694 else if (verbose
> 5)
13696 "best insn %d already on top\n",
13697 INSN_UID (ready
[last_index
]));
13702 fprintf (file
, "ready list ooo attributes - sched state: %d\n",
13705 for (i
= last_index
; i
>= 0; i
--)
13707 if (recog_memoized (ready
[i
]) < 0)
13709 fprintf (file
, "insn %d score: %d: ", INSN_UID (ready
[i
]),
13710 s390_sched_score (ready
[i
]));
13711 #define PRINT_OOO_ATTR(ATTR) fprintf (file, "%s ", get_attr_##ATTR (ready[i]) ? #ATTR : "!" #ATTR);
13712 PRINT_OOO_ATTR (ooo_cracked
);
13713 PRINT_OOO_ATTR (ooo_expanded
);
13714 PRINT_OOO_ATTR (ooo_endgroup
);
13715 PRINT_OOO_ATTR (ooo_groupalone
);
13716 #undef PRINT_OOO_ATTR
13717 fprintf (file
, "\n");
13722 return s390_issue_rate ();
13726 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
13727 the scheduler has issued INSN. It stores the last issued insn into
13728 last_scheduled_insn in order to make it available for
13729 s390_sched_reorder. */
13731 s390_sched_variable_issue (FILE *file
, int verbose
, rtx_insn
*insn
, int more
)
13733 last_scheduled_insn
= insn
;
13735 if (s390_tune
>= PROCESSOR_2827_ZEC12
13736 && reload_completed
13737 && recog_memoized (insn
) >= 0)
13739 unsigned int mask
= s390_get_sched_attrmask (insn
);
13741 if ((mask
& S390_OOO_SCHED_ATTR_MASK_CRACKED
) != 0
13742 || (mask
& S390_OOO_SCHED_ATTR_MASK_EXPANDED
) != 0)
13743 s390_sched_state
= S390_OOO_SCHED_STATE_CRACKED
;
13744 else if ((mask
& S390_OOO_SCHED_ATTR_MASK_ENDGROUP
) != 0
13745 || (mask
& S390_OOO_SCHED_ATTR_MASK_GROUPALONE
) != 0)
13746 s390_sched_state
= S390_OOO_SCHED_STATE_NORMAL
;
13749 /* Only normal insns are left (mask == 0). */
13750 switch (s390_sched_state
)
13755 case S390_OOO_SCHED_STATE_NORMAL
:
13756 if (s390_sched_state
== S390_OOO_SCHED_STATE_NORMAL
)
13757 s390_sched_state
= 1;
13759 s390_sched_state
++;
13762 case S390_OOO_SCHED_STATE_CRACKED
:
13763 s390_sched_state
= S390_OOO_SCHED_STATE_NORMAL
;
13769 fprintf (file
, "insn %d: ", INSN_UID (insn
));
13770 #define PRINT_OOO_ATTR(ATTR) \
13771 fprintf (file, "%s ", get_attr_##ATTR (insn) ? #ATTR : "");
13772 PRINT_OOO_ATTR (ooo_cracked
);
13773 PRINT_OOO_ATTR (ooo_expanded
);
13774 PRINT_OOO_ATTR (ooo_endgroup
);
13775 PRINT_OOO_ATTR (ooo_groupalone
);
13776 #undef PRINT_OOO_ATTR
13777 fprintf (file
, "\n");
13778 fprintf (file
, "sched state: %d\n", s390_sched_state
);
13782 if (GET_CODE (PATTERN (insn
)) != USE
13783 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
13790 s390_sched_init (FILE *file ATTRIBUTE_UNUSED
,
13791 int verbose ATTRIBUTE_UNUSED
,
13792 int max_ready ATTRIBUTE_UNUSED
)
13794 last_scheduled_insn
= NULL
;
13795 s390_sched_state
= 0;
13798 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
13799 a new number struct loop *loop should be unrolled if tuned for cpus with
13800 a built-in stride prefetcher.
13801 The loop is analyzed for memory accesses by calling check_dpu for
13802 each rtx of the loop. Depending on the loop_depth and the amount of
13803 memory accesses a new number <=nunroll is returned to improve the
13804 behavior of the hardware prefetch unit. */
13806 s390_loop_unroll_adjust (unsigned nunroll
, struct loop
*loop
)
13811 unsigned mem_count
= 0;
13813 if (s390_tune
< PROCESSOR_2097_Z10
)
13816 /* Count the number of memory references within the loop body. */
13817 bbs
= get_loop_body (loop
);
13818 subrtx_iterator::array_type array
;
13819 for (i
= 0; i
< loop
->num_nodes
; i
++)
13820 FOR_BB_INSNS (bbs
[i
], insn
)
13821 if (INSN_P (insn
) && INSN_CODE (insn
) != -1)
13822 FOR_EACH_SUBRTX (iter
, array
, PATTERN (insn
), NONCONST
)
13827 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
13828 if (mem_count
== 0)
13831 switch (loop_depth(loop
))
13834 return MIN (nunroll
, 28 / mem_count
);
13836 return MIN (nunroll
, 22 / mem_count
);
13838 return MIN (nunroll
, 16 / mem_count
);
13842 /* Restore the current options. This is a hook function and also called
13846 s390_function_specific_restore (struct gcc_options
*opts
,
13847 struct cl_target_option
*ptr ATTRIBUTE_UNUSED
)
13849 opts
->x_s390_cost_pointer
= (long)processor_table
[opts
->x_s390_tune
].cost
;
13853 s390_option_override_internal (bool main_args_p
,
13854 struct gcc_options
*opts
,
13855 const struct gcc_options
*opts_set
)
13857 const char *prefix
;
13858 const char *suffix
;
13860 /* Set up prefix/suffix so the error messages refer to either the command
13861 line argument, or the attribute(target). */
13869 prefix
= "option(\"";
13874 /* Architecture mode defaults according to ABI. */
13875 if (!(opts_set
->x_target_flags
& MASK_ZARCH
))
13878 opts
->x_target_flags
|= MASK_ZARCH
;
13880 opts
->x_target_flags
&= ~MASK_ZARCH
;
13883 /* Set the march default in case it hasn't been specified on cmdline. */
13884 if (!opts_set
->x_s390_arch
)
13885 opts
->x_s390_arch
= PROCESSOR_2064_Z900
;
13886 else if (opts
->x_s390_arch
== PROCESSOR_9672_G5
13887 || opts
->x_s390_arch
== PROCESSOR_9672_G6
)
13888 warning (OPT_Wdeprecated
, "%sarch=%s%s is deprecated and will be removed "
13889 "in future releases; use at least %sarch=z900%s",
13890 prefix
, opts
->x_s390_arch
== PROCESSOR_9672_G5
? "g5" : "g6",
13891 suffix
, prefix
, suffix
);
13893 opts
->x_s390_arch_flags
= processor_flags_table
[(int) opts
->x_s390_arch
];
13895 /* Determine processor to tune for. */
13896 if (!opts_set
->x_s390_tune
)
13897 opts
->x_s390_tune
= opts
->x_s390_arch
;
13898 else if (opts
->x_s390_tune
== PROCESSOR_9672_G5
13899 || opts
->x_s390_tune
== PROCESSOR_9672_G6
)
13900 warning (OPT_Wdeprecated
, "%stune=%s%s is deprecated and will be removed "
13901 "in future releases; use at least %stune=z900%s",
13902 prefix
, opts
->x_s390_tune
== PROCESSOR_9672_G5
? "g5" : "g6",
13903 suffix
, prefix
, suffix
);
13905 opts
->x_s390_tune_flags
= processor_flags_table
[opts
->x_s390_tune
];
13907 /* Sanity checks. */
13908 if (opts
->x_s390_arch
== PROCESSOR_NATIVE
13909 || opts
->x_s390_tune
== PROCESSOR_NATIVE
)
13910 gcc_unreachable ();
13911 if (TARGET_ZARCH_P (opts
->x_target_flags
) && !TARGET_CPU_ZARCH_P (opts
))
13912 error ("z/Architecture mode not supported on %s",
13913 processor_table
[(int)opts
->x_s390_arch
].name
);
13914 if (TARGET_64BIT
&& !TARGET_ZARCH_P (opts
->x_target_flags
))
13915 error ("64-bit ABI not supported in ESA/390 mode");
13917 /* Enable hardware transactions if available and not explicitly
13918 disabled by user. E.g. with -m31 -march=zEC12 -mzarch */
13919 if (!TARGET_OPT_HTM_P (opts_set
->x_target_flags
))
13921 if (TARGET_CPU_HTM_P (opts
) && TARGET_ZARCH_P (opts
->x_target_flags
))
13922 opts
->x_target_flags
|= MASK_OPT_HTM
;
13924 opts
->x_target_flags
&= ~MASK_OPT_HTM
;
13927 if (TARGET_OPT_VX_P (opts_set
->x_target_flags
))
13929 if (TARGET_OPT_VX_P (opts
->x_target_flags
))
13931 if (!TARGET_CPU_VX_P (opts
))
13932 error ("hardware vector support not available on %s",
13933 processor_table
[(int)opts
->x_s390_arch
].name
);
13934 if (TARGET_SOFT_FLOAT_P (opts
->x_target_flags
))
13935 error ("hardware vector support not available with -msoft-float");
13940 if (TARGET_CPU_VX_P (opts
))
13941 /* Enable vector support if available and not explicitly disabled
13942 by user. E.g. with -m31 -march=z13 -mzarch */
13943 opts
->x_target_flags
|= MASK_OPT_VX
;
13945 opts
->x_target_flags
&= ~MASK_OPT_VX
;
13948 /* Use hardware DFP if available and not explicitly disabled by
13949 user. E.g. with -m31 -march=z10 -mzarch */
13950 if (!TARGET_HARD_DFP_P (opts_set
->x_target_flags
))
13952 if (TARGET_DFP_P (opts
))
13953 opts
->x_target_flags
|= MASK_HARD_DFP
;
13955 opts
->x_target_flags
&= ~MASK_HARD_DFP
;
13958 if (TARGET_HARD_DFP_P (opts
->x_target_flags
) && !TARGET_DFP_P (opts
))
13960 if (TARGET_HARD_DFP_P (opts_set
->x_target_flags
))
13962 if (!TARGET_CPU_DFP_P (opts
))
13963 error ("hardware decimal floating point instructions"
13964 " not available on %s",
13965 processor_table
[(int)opts
->x_s390_arch
].name
);
13966 if (!TARGET_ZARCH_P (opts
->x_target_flags
))
13967 error ("hardware decimal floating point instructions"
13968 " not available in ESA/390 mode");
13971 opts
->x_target_flags
&= ~MASK_HARD_DFP
;
13974 if (TARGET_SOFT_FLOAT_P (opts_set
->x_target_flags
)
13975 && TARGET_SOFT_FLOAT_P (opts
->x_target_flags
))
13977 if (TARGET_HARD_DFP_P (opts_set
->x_target_flags
)
13978 && TARGET_HARD_DFP_P (opts
->x_target_flags
))
13979 error ("-mhard-dfp can%'t be used in conjunction with -msoft-float");
13981 opts
->x_target_flags
&= ~MASK_HARD_DFP
;
13984 if (TARGET_BACKCHAIN_P (opts
->x_target_flags
)
13985 && TARGET_PACKED_STACK_P (opts
->x_target_flags
)
13986 && TARGET_HARD_FLOAT_P (opts
->x_target_flags
))
13987 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
13990 if (opts
->x_s390_stack_size
)
13992 if (opts
->x_s390_stack_guard
>= opts
->x_s390_stack_size
)
13993 error ("stack size must be greater than the stack guard value");
13994 else if (opts
->x_s390_stack_size
> 1 << 16)
13995 error ("stack size must not be greater than 64k");
13997 else if (opts
->x_s390_stack_guard
)
13998 error ("-mstack-guard implies use of -mstack-size");
14000 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
14001 if (!TARGET_LONG_DOUBLE_128_P (opts_set
->x_target_flags
))
14002 opts
->x_target_flags
|= MASK_LONG_DOUBLE_128
;
14005 if (opts
->x_s390_tune
>= PROCESSOR_2097_Z10
)
14007 maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS
, 100,
14008 opts
->x_param_values
,
14009 opts_set
->x_param_values
);
14010 maybe_set_param_value (PARAM_MAX_UNROLL_TIMES
, 32,
14011 opts
->x_param_values
,
14012 opts_set
->x_param_values
);
14013 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS
, 2000,
14014 opts
->x_param_values
,
14015 opts_set
->x_param_values
);
14016 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES
, 64,
14017 opts
->x_param_values
,
14018 opts_set
->x_param_values
);
14021 maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH
, 256,
14022 opts
->x_param_values
,
14023 opts_set
->x_param_values
);
14024 /* values for loop prefetching */
14025 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
, 256,
14026 opts
->x_param_values
,
14027 opts_set
->x_param_values
);
14028 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, 128,
14029 opts
->x_param_values
,
14030 opts_set
->x_param_values
);
14031 /* s390 has more than 2 levels and the size is much larger. Since
14032 we are always running virtualized assume that we only get a small
14033 part of the caches above l1. */
14034 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, 1500,
14035 opts
->x_param_values
,
14036 opts_set
->x_param_values
);
14037 maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO
, 2,
14038 opts
->x_param_values
,
14039 opts_set
->x_param_values
);
14040 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
, 6,
14041 opts
->x_param_values
,
14042 opts_set
->x_param_values
);
14044 /* Use the alternative scheduling-pressure algorithm by default. */
14045 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM
, 2,
14046 opts
->x_param_values
,
14047 opts_set
->x_param_values
);
14049 /* Call target specific restore function to do post-init work. At the moment,
14050 this just sets opts->x_s390_cost_pointer. */
14051 s390_function_specific_restore (opts
, NULL
);
14055 s390_option_override (void)
14058 cl_deferred_option
*opt
;
14059 vec
<cl_deferred_option
> *v
=
14060 (vec
<cl_deferred_option
> *) s390_deferred_options
;
14063 FOR_EACH_VEC_ELT (*v
, i
, opt
)
14065 switch (opt
->opt_index
)
14067 case OPT_mhotpatch_
:
14074 strncpy (s
, opt
->arg
, 256);
14076 t
= strchr (s
, ',');
14081 val1
= integral_argument (s
);
14082 val2
= integral_argument (t
);
14089 if (val1
== -1 || val2
== -1)
14091 /* argument is not a plain number */
14092 error ("arguments to %qs should be non-negative integers",
14096 else if (val1
> s390_hotpatch_hw_max
14097 || val2
> s390_hotpatch_hw_max
)
14099 error ("argument to %qs is too large (max. %d)",
14100 "-mhotpatch=n,m", s390_hotpatch_hw_max
);
14103 s390_hotpatch_hw_before_label
= val1
;
14104 s390_hotpatch_hw_after_label
= val2
;
14108 gcc_unreachable ();
14112 /* Set up function hooks. */
14113 init_machine_status
= s390_init_machine_status
;
14115 s390_option_override_internal (true, &global_options
, &global_options_set
);
14117 /* Save the initial options in case the user does function specific
14119 target_option_default_node
= build_target_option_node (&global_options
);
14120 target_option_current_node
= target_option_default_node
;
14122 /* This cannot reside in s390_option_optimization_table since HAVE_prefetch
14123 requires the arch flags to be evaluated already. Since prefetching
14124 is beneficial on s390, we enable it if available. */
14125 if (flag_prefetch_loop_arrays
< 0 && HAVE_prefetch
&& optimize
>= 3)
14126 flag_prefetch_loop_arrays
= 1;
14130 /* Don't emit DWARF3/4 unless specifically selected. The TPF
14131 debuggers do not yet support DWARF 3/4. */
14132 if (!global_options_set
.x_dwarf_strict
)
14134 if (!global_options_set
.x_dwarf_version
)
14138 /* Register a target-specific optimization-and-lowering pass
14139 to run immediately before prologue and epilogue generation.
14141 Registering the pass must be done at start up. It's
14142 convenient to do it here. */
14143 opt_pass
*new_pass
= new pass_s390_early_mach (g
);
14144 struct register_pass_info insert_pass_s390_early_mach
=
14146 new_pass
, /* pass */
14147 "pro_and_epilogue", /* reference_pass_name */
14148 1, /* ref_pass_instance_number */
14149 PASS_POS_INSERT_BEFORE
/* po_op */
14151 register_pass (&insert_pass_s390_early_mach
);
14154 #if S390_USE_TARGET_ATTRIBUTE
14155 /* Inner function to process the attribute((target(...))), take an argument and
14156 set the current options from the argument. If we have a list, recursively go
14160 s390_valid_target_attribute_inner_p (tree args
,
14161 struct gcc_options
*opts
,
14162 struct gcc_options
*new_opts_set
,
14168 #define S390_ATTRIB(S,O,A) { S, sizeof (S)-1, O, A, 0 }
14169 #define S390_PRAGMA(S,O,A) { S, sizeof (S)-1, O, A, 1 }
14170 static const struct
14172 const char *string
;
14176 int only_as_pragma
;
14179 S390_ATTRIB ("arch=", OPT_march_
, 1),
14180 S390_ATTRIB ("tune=", OPT_mtune_
, 1),
14181 /* uinteger options */
14182 S390_ATTRIB ("stack-guard=", OPT_mstack_guard_
, 1),
14183 S390_ATTRIB ("stack-size=", OPT_mstack_size_
, 1),
14184 S390_ATTRIB ("branch-cost=", OPT_mbranch_cost_
, 1),
14185 S390_ATTRIB ("warn-framesize=", OPT_mwarn_framesize_
, 1),
14187 S390_ATTRIB ("backchain", OPT_mbackchain
, 0),
14188 S390_ATTRIB ("hard-dfp", OPT_mhard_dfp
, 0),
14189 S390_ATTRIB ("hard-float", OPT_mhard_float
, 0),
14190 S390_ATTRIB ("htm", OPT_mhtm
, 0),
14191 S390_ATTRIB ("vx", OPT_mvx
, 0),
14192 S390_ATTRIB ("packed-stack", OPT_mpacked_stack
, 0),
14193 S390_ATTRIB ("small-exec", OPT_msmall_exec
, 0),
14194 S390_ATTRIB ("soft-float", OPT_msoft_float
, 0),
14195 S390_ATTRIB ("mvcle", OPT_mmvcle
, 0),
14196 S390_PRAGMA ("zvector", OPT_mzvector
, 0),
14197 /* boolean options */
14198 S390_ATTRIB ("warn-dynamicstack", OPT_mwarn_dynamicstack
, 0),
14203 /* If this is a list, recurse to get the options. */
14204 if (TREE_CODE (args
) == TREE_LIST
)
14207 int num_pragma_values
;
14210 /* Note: attribs.c:decl_attributes prepends the values from
14211 current_target_pragma to the list of target attributes. To determine
14212 whether we're looking at a value of the attribute or the pragma we
14213 assume that the first [list_length (current_target_pragma)] values in
14214 the list are the values from the pragma. */
14215 num_pragma_values
= (!force_pragma
&& current_target_pragma
!= NULL
)
14216 ? list_length (current_target_pragma
) : 0;
14217 for (i
= 0; args
; args
= TREE_CHAIN (args
), i
++)
14221 is_pragma
= (force_pragma
|| i
< num_pragma_values
);
14222 if (TREE_VALUE (args
)
14223 && !s390_valid_target_attribute_inner_p (TREE_VALUE (args
),
14224 opts
, new_opts_set
,
14233 else if (TREE_CODE (args
) != STRING_CST
)
14235 error ("attribute %<target%> argument not a string");
14239 /* Handle multiple arguments separated by commas. */
14240 next_optstr
= ASTRDUP (TREE_STRING_POINTER (args
));
14242 while (next_optstr
&& *next_optstr
!= '\0')
14244 char *p
= next_optstr
;
14246 char *comma
= strchr (next_optstr
, ',');
14247 size_t len
, opt_len
;
14253 enum cl_var_type var_type
;
14259 len
= comma
- next_optstr
;
14260 next_optstr
= comma
+ 1;
14265 next_optstr
= NULL
;
14268 /* Recognize no-xxx. */
14269 if (len
> 3 && p
[0] == 'n' && p
[1] == 'o' && p
[2] == '-')
14278 /* Find the option. */
14281 for (i
= 0; i
< ARRAY_SIZE (attrs
); i
++)
14283 opt_len
= attrs
[i
].len
;
14284 if (ch
== attrs
[i
].string
[0]
14285 && ((attrs
[i
].has_arg
) ? len
> opt_len
: len
== opt_len
)
14286 && memcmp (p
, attrs
[i
].string
, opt_len
) == 0)
14288 opt
= attrs
[i
].opt
;
14289 if (!opt_set_p
&& cl_options
[opt
].cl_reject_negative
)
14291 mask
= cl_options
[opt
].var_value
;
14292 var_type
= cl_options
[opt
].var_type
;
14298 /* Process the option. */
14301 error ("attribute(target(\"%s\")) is unknown", orig_p
);
14304 else if (attrs
[i
].only_as_pragma
&& !force_pragma
)
14306 /* Value is not allowed for the target attribute. */
14307 error ("Value %qs is not supported by attribute %<target%>",
14312 else if (var_type
== CLVC_BIT_SET
|| var_type
== CLVC_BIT_CLEAR
)
14314 if (var_type
== CLVC_BIT_CLEAR
)
14315 opt_set_p
= !opt_set_p
;
14318 opts
->x_target_flags
|= mask
;
14320 opts
->x_target_flags
&= ~mask
;
14321 new_opts_set
->x_target_flags
|= mask
;
14324 else if (cl_options
[opt
].var_type
== CLVC_BOOLEAN
)
14328 if (cl_options
[opt
].cl_uinteger
)
14330 /* Unsigned integer argument. Code based on the function
14331 decode_cmdline_option () in opts-common.c. */
14332 value
= integral_argument (p
+ opt_len
);
14335 value
= (opt_set_p
) ? 1 : 0;
14339 struct cl_decoded_option decoded
;
14341 /* Value range check; only implemented for numeric and boolean
14342 options at the moment. */
14343 generate_option (opt
, NULL
, value
, CL_TARGET
, &decoded
);
14344 s390_handle_option (opts
, new_opts_set
, &decoded
, input_location
);
14345 set_option (opts
, new_opts_set
, opt
, value
,
14346 p
+ opt_len
, DK_UNSPECIFIED
, input_location
,
14351 error ("attribute(target(\"%s\")) is unknown", orig_p
);
14356 else if (cl_options
[opt
].var_type
== CLVC_ENUM
)
14361 arg_ok
= opt_enum_arg_to_value (opt
, p
+ opt_len
, &value
, CL_TARGET
);
14363 set_option (opts
, new_opts_set
, opt
, value
,
14364 p
+ opt_len
, DK_UNSPECIFIED
, input_location
,
14368 error ("attribute(target(\"%s\")) is unknown", orig_p
);
14374 gcc_unreachable ();
14379 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
14382 s390_valid_target_attribute_tree (tree args
,
14383 struct gcc_options
*opts
,
14384 const struct gcc_options
*opts_set
,
14387 tree t
= NULL_TREE
;
14388 struct gcc_options new_opts_set
;
14390 memset (&new_opts_set
, 0, sizeof (new_opts_set
));
14392 /* Process each of the options on the chain. */
14393 if (! s390_valid_target_attribute_inner_p (args
, opts
, &new_opts_set
,
14395 return error_mark_node
;
14397 /* If some option was set (even if it has not changed), rerun
14398 s390_option_override_internal, and then save the options away. */
14399 if (new_opts_set
.x_target_flags
14400 || new_opts_set
.x_s390_arch
14401 || new_opts_set
.x_s390_tune
14402 || new_opts_set
.x_s390_stack_guard
14403 || new_opts_set
.x_s390_stack_size
14404 || new_opts_set
.x_s390_branch_cost
14405 || new_opts_set
.x_s390_warn_framesize
14406 || new_opts_set
.x_s390_warn_dynamicstack_p
)
14408 const unsigned char *src
= (const unsigned char *)opts_set
;
14409 unsigned char *dest
= (unsigned char *)&new_opts_set
;
14412 /* Merge the original option flags into the new ones. */
14413 for (i
= 0; i
< sizeof(*opts_set
); i
++)
14416 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
14417 s390_option_override_internal (false, opts
, &new_opts_set
);
14418 /* Save the current options unless we are validating options for
14420 t
= build_target_option_node (opts
);
14425 /* Hook to validate attribute((target("string"))). */
14428 s390_valid_target_attribute_p (tree fndecl
,
14429 tree
ARG_UNUSED (name
),
14431 int ARG_UNUSED (flags
))
14433 struct gcc_options func_options
;
14434 tree new_target
, new_optimize
;
14437 /* attribute((target("default"))) does nothing, beyond
14438 affecting multi-versioning. */
14439 if (TREE_VALUE (args
)
14440 && TREE_CODE (TREE_VALUE (args
)) == STRING_CST
14441 && TREE_CHAIN (args
) == NULL_TREE
14442 && strcmp (TREE_STRING_POINTER (TREE_VALUE (args
)), "default") == 0)
14445 tree old_optimize
= build_optimization_node (&global_options
);
14447 /* Get the optimization options of the current function. */
14448 tree func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
14450 if (!func_optimize
)
14451 func_optimize
= old_optimize
;
14453 /* Init func_options. */
14454 memset (&func_options
, 0, sizeof (func_options
));
14455 init_options_struct (&func_options
, NULL
);
14456 lang_hooks
.init_options_struct (&func_options
);
14458 cl_optimization_restore (&func_options
, TREE_OPTIMIZATION (func_optimize
));
14460 /* Initialize func_options to the default before its target options can
14462 cl_target_option_restore (&func_options
,
14463 TREE_TARGET_OPTION (target_option_default_node
));
14465 new_target
= s390_valid_target_attribute_tree (args
, &func_options
,
14466 &global_options_set
,
14468 current_target_pragma
));
14469 new_optimize
= build_optimization_node (&func_options
);
14470 if (new_target
== error_mark_node
)
14472 else if (fndecl
&& new_target
)
14474 DECL_FUNCTION_SPECIFIC_TARGET (fndecl
) = new_target
;
14475 if (old_optimize
!= new_optimize
)
14476 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
) = new_optimize
;
14481 /* Restore targets globals from NEW_TREE and invalidate s390_previous_fndecl
14485 s390_activate_target_options (tree new_tree
)
14487 cl_target_option_restore (&global_options
, TREE_TARGET_OPTION (new_tree
));
14488 if (TREE_TARGET_GLOBALS (new_tree
))
14489 restore_target_globals (TREE_TARGET_GLOBALS (new_tree
));
14490 else if (new_tree
== target_option_default_node
)
14491 restore_target_globals (&default_target_globals
);
14493 TREE_TARGET_GLOBALS (new_tree
) = save_target_globals_default_opts ();
14494 s390_previous_fndecl
= NULL_TREE
;
14497 /* Establish appropriate back-end context for processing the function
14498 FNDECL. The argument might be NULL to indicate processing at top
14499 level, outside of any function scope. */
14501 s390_set_current_function (tree fndecl
)
14503 /* Only change the context if the function changes. This hook is called
14504 several times in the course of compiling a function, and we don't want to
14505 slow things down too much or call target_reinit when it isn't safe. */
14506 if (fndecl
== s390_previous_fndecl
)
14510 if (s390_previous_fndecl
== NULL_TREE
)
14511 old_tree
= target_option_current_node
;
14512 else if (DECL_FUNCTION_SPECIFIC_TARGET (s390_previous_fndecl
))
14513 old_tree
= DECL_FUNCTION_SPECIFIC_TARGET (s390_previous_fndecl
);
14515 old_tree
= target_option_default_node
;
14517 if (fndecl
== NULL_TREE
)
14519 if (old_tree
!= target_option_current_node
)
14520 s390_activate_target_options (target_option_current_node
);
14524 tree new_tree
= DECL_FUNCTION_SPECIFIC_TARGET (fndecl
);
14525 if (new_tree
== NULL_TREE
)
14526 new_tree
= target_option_default_node
;
14528 if (old_tree
!= new_tree
)
14529 s390_activate_target_options (new_tree
);
14530 s390_previous_fndecl
= fndecl
;
14534 /* Implement TARGET_USE_BY_PIECES_INFRASTRUCTURE_P. */
14537 s390_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size
,
14538 unsigned int align ATTRIBUTE_UNUSED
,
14539 enum by_pieces_operation op ATTRIBUTE_UNUSED
,
14540 bool speed_p ATTRIBUTE_UNUSED
)
14542 return (size
== 1 || size
== 2
14543 || size
== 4 || (TARGET_ZARCH
&& size
== 8));
14546 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
14549 s390_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
14551 tree sfpc
= s390_builtin_decls
[S390_BUILTIN_s390_sfpc
];
14552 tree efpc
= s390_builtin_decls
[S390_BUILTIN_s390_efpc
];
14553 tree call_efpc
= build_call_expr (efpc
, 0);
14554 tree fenv_var
= create_tmp_var_raw (unsigned_type_node
);
14556 #define FPC_EXCEPTION_MASK HOST_WIDE_INT_UC (0xf8000000)
14557 #define FPC_FLAGS_MASK HOST_WIDE_INT_UC (0x00f80000)
14558 #define FPC_DXC_MASK HOST_WIDE_INT_UC (0x0000ff00)
14559 #define FPC_EXCEPTION_MASK_SHIFT HOST_WIDE_INT_UC (24)
14560 #define FPC_FLAGS_SHIFT HOST_WIDE_INT_UC (16)
14561 #define FPC_DXC_SHIFT HOST_WIDE_INT_UC (8)
14563 /* Generates the equivalent of feholdexcept (&fenv_var)
14565 fenv_var = __builtin_s390_efpc ();
14566 __builtin_s390_sfpc (fenv_var & mask) */
14567 tree old_fpc
= build2 (MODIFY_EXPR
, unsigned_type_node
, fenv_var
, call_efpc
);
14569 build2 (BIT_AND_EXPR
, unsigned_type_node
, fenv_var
,
14570 build_int_cst (unsigned_type_node
,
14571 ~(FPC_DXC_MASK
| FPC_FLAGS_MASK
|
14572 FPC_EXCEPTION_MASK
)));
14573 tree set_new_fpc
= build_call_expr (sfpc
, 1, new_fpc
);
14574 *hold
= build2 (COMPOUND_EXPR
, void_type_node
, old_fpc
, set_new_fpc
);
14576 /* Generates the equivalent of feclearexcept (FE_ALL_EXCEPT)
14578 __builtin_s390_sfpc (__builtin_s390_efpc () & mask) */
14579 new_fpc
= build2 (BIT_AND_EXPR
, unsigned_type_node
, call_efpc
,
14580 build_int_cst (unsigned_type_node
,
14581 ~(FPC_DXC_MASK
| FPC_FLAGS_MASK
)));
14582 *clear
= build_call_expr (sfpc
, 1, new_fpc
);
14584 /* Generates the equivalent of feupdateenv (fenv_var)
14586 old_fpc = __builtin_s390_efpc ();
14587 __builtin_s390_sfpc (fenv_var);
14588 __atomic_feraiseexcept ((old_fpc & FPC_FLAGS_MASK) >> FPC_FLAGS_SHIFT); */
14590 old_fpc
= create_tmp_var_raw (unsigned_type_node
);
14591 tree store_old_fpc
= build2 (MODIFY_EXPR
, void_type_node
,
14592 old_fpc
, call_efpc
);
14594 set_new_fpc
= build_call_expr (sfpc
, 1, fenv_var
);
14596 tree raise_old_except
= build2 (BIT_AND_EXPR
, unsigned_type_node
, old_fpc
,
14597 build_int_cst (unsigned_type_node
,
14599 raise_old_except
= build2 (RSHIFT_EXPR
, unsigned_type_node
, raise_old_except
,
14600 build_int_cst (unsigned_type_node
,
14602 tree atomic_feraiseexcept
14603 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT
);
14604 raise_old_except
= build_call_expr (atomic_feraiseexcept
,
14605 1, raise_old_except
);
14607 *update
= build2 (COMPOUND_EXPR
, void_type_node
,
14608 build2 (COMPOUND_EXPR
, void_type_node
,
14609 store_old_fpc
, set_new_fpc
),
14612 #undef FPC_EXCEPTION_MASK
14613 #undef FPC_FLAGS_MASK
14614 #undef FPC_DXC_MASK
14615 #undef FPC_EXCEPTION_MASK_SHIFT
14616 #undef FPC_FLAGS_SHIFT
14617 #undef FPC_DXC_SHIFT
14620 /* Return the vector mode to be used for inner mode MODE when doing
14622 static machine_mode
14623 s390_preferred_simd_mode (machine_mode mode
)
14643 /* Our hardware does not require vectors to be strictly aligned. */
14645 s390_support_vector_misalignment (machine_mode mode ATTRIBUTE_UNUSED
,
14646 const_tree type ATTRIBUTE_UNUSED
,
14647 int misalignment ATTRIBUTE_UNUSED
,
14648 bool is_packed ATTRIBUTE_UNUSED
)
14653 return default_builtin_support_vector_misalignment (mode
, type
, misalignment
,
14657 /* The vector ABI requires vector types to be aligned on an 8 byte
14658 boundary (our stack alignment). However, we allow this to be
14659 overriden by the user, while this definitely breaks the ABI. */
14660 static HOST_WIDE_INT
14661 s390_vector_alignment (const_tree type
)
14663 if (!TARGET_VX_ABI
)
14664 return default_vector_alignment (type
);
14666 if (TYPE_USER_ALIGN (type
))
14667 return TYPE_ALIGN (type
);
14669 return MIN (64, tree_to_shwi (TYPE_SIZE (type
)));
14672 #ifdef HAVE_AS_MACHINE_MACHINEMODE
14673 /* Implement TARGET_ASM_FILE_START. */
14675 s390_asm_file_start (void)
14677 s390_asm_output_machine_for_arch (asm_out_file
);
14681 /* Implement TARGET_ASM_FILE_END. */
14683 s390_asm_file_end (void)
14685 #ifdef HAVE_AS_GNU_ATTRIBUTE
14686 varpool_node
*vnode
;
14687 cgraph_node
*cnode
;
14689 FOR_EACH_VARIABLE (vnode
)
14690 if (TREE_PUBLIC (vnode
->decl
))
14691 s390_check_type_for_vector_abi (TREE_TYPE (vnode
->decl
), false, false);
14693 FOR_EACH_FUNCTION (cnode
)
14694 if (TREE_PUBLIC (cnode
->decl
))
14695 s390_check_type_for_vector_abi (TREE_TYPE (cnode
->decl
), false, false);
14698 if (s390_vector_abi
!= 0)
14699 fprintf (asm_out_file
, "\t.gnu_attribute 8, %d\n",
14702 file_end_indicate_exec_stack ();
14704 if (flag_split_stack
)
14705 file_end_indicate_split_stack ();
14708 /* Return true if TYPE is a vector bool type. */
14710 s390_vector_bool_type_p (const_tree type
)
14712 return TYPE_VECTOR_OPAQUE (type
);
14715 /* Return the diagnostic message string if the binary operation OP is
14716 not permitted on TYPE1 and TYPE2, NULL otherwise. */
14718 s390_invalid_binary_op (int op ATTRIBUTE_UNUSED
, const_tree type1
, const_tree type2
)
14720 bool bool1_p
, bool2_p
;
14724 machine_mode mode1
, mode2
;
14726 if (!TARGET_ZVECTOR
)
14729 if (!VECTOR_TYPE_P (type1
) || !VECTOR_TYPE_P (type2
))
14732 bool1_p
= s390_vector_bool_type_p (type1
);
14733 bool2_p
= s390_vector_bool_type_p (type2
);
14735 /* Mixing signed and unsigned types is forbidden for all
14737 if (!bool1_p
&& !bool2_p
14738 && TYPE_UNSIGNED (type1
) != TYPE_UNSIGNED (type2
))
14739 return N_("types differ in signess");
14741 plusminus_p
= (op
== PLUS_EXPR
|| op
== MINUS_EXPR
);
14742 muldiv_p
= (op
== MULT_EXPR
|| op
== RDIV_EXPR
|| op
== TRUNC_DIV_EXPR
14743 || op
== CEIL_DIV_EXPR
|| op
== FLOOR_DIV_EXPR
14744 || op
== ROUND_DIV_EXPR
);
14745 compare_p
= (op
== LT_EXPR
|| op
== LE_EXPR
|| op
== GT_EXPR
|| op
== GE_EXPR
14746 || op
== EQ_EXPR
|| op
== NE_EXPR
);
14748 if (bool1_p
&& bool2_p
&& (plusminus_p
|| muldiv_p
))
14749 return N_("binary operator does not support two vector bool operands");
14751 if (bool1_p
!= bool2_p
&& (muldiv_p
|| compare_p
))
14752 return N_("binary operator does not support vector bool operand");
14754 mode1
= TYPE_MODE (type1
);
14755 mode2
= TYPE_MODE (type2
);
14757 if (bool1_p
!= bool2_p
&& plusminus_p
14758 && (GET_MODE_CLASS (mode1
) == MODE_VECTOR_FLOAT
14759 || GET_MODE_CLASS (mode2
) == MODE_VECTOR_FLOAT
))
14760 return N_("binary operator does not support mixing vector "
14761 "bool with floating point vector operands");
14766 /* Initialize GCC target structure. */
14768 #undef TARGET_ASM_ALIGNED_HI_OP
14769 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
14770 #undef TARGET_ASM_ALIGNED_DI_OP
14771 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
14772 #undef TARGET_ASM_INTEGER
14773 #define TARGET_ASM_INTEGER s390_assemble_integer
14775 #undef TARGET_ASM_OPEN_PAREN
14776 #define TARGET_ASM_OPEN_PAREN ""
14778 #undef TARGET_ASM_CLOSE_PAREN
14779 #define TARGET_ASM_CLOSE_PAREN ""
14781 #undef TARGET_OPTION_OVERRIDE
14782 #define TARGET_OPTION_OVERRIDE s390_option_override
14784 #undef TARGET_ENCODE_SECTION_INFO
14785 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
14787 #undef TARGET_SCALAR_MODE_SUPPORTED_P
14788 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
14791 #undef TARGET_HAVE_TLS
14792 #define TARGET_HAVE_TLS true
14794 #undef TARGET_CANNOT_FORCE_CONST_MEM
14795 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
14797 #undef TARGET_DELEGITIMIZE_ADDRESS
14798 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
14800 #undef TARGET_LEGITIMIZE_ADDRESS
14801 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
14803 #undef TARGET_RETURN_IN_MEMORY
14804 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
14806 #undef TARGET_INIT_BUILTINS
14807 #define TARGET_INIT_BUILTINS s390_init_builtins
14808 #undef TARGET_EXPAND_BUILTIN
14809 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
14810 #undef TARGET_BUILTIN_DECL
14811 #define TARGET_BUILTIN_DECL s390_builtin_decl
14813 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
14814 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA s390_output_addr_const_extra
14816 #undef TARGET_ASM_OUTPUT_MI_THUNK
14817 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
14818 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
14819 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
14821 #undef TARGET_SCHED_ADJUST_PRIORITY
14822 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
14823 #undef TARGET_SCHED_ISSUE_RATE
14824 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
14825 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
14826 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
14828 #undef TARGET_SCHED_VARIABLE_ISSUE
14829 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
14830 #undef TARGET_SCHED_REORDER
14831 #define TARGET_SCHED_REORDER s390_sched_reorder
14832 #undef TARGET_SCHED_INIT
14833 #define TARGET_SCHED_INIT s390_sched_init
14835 #undef TARGET_CANNOT_COPY_INSN_P
14836 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
14837 #undef TARGET_RTX_COSTS
14838 #define TARGET_RTX_COSTS s390_rtx_costs
14839 #undef TARGET_ADDRESS_COST
14840 #define TARGET_ADDRESS_COST s390_address_cost
14841 #undef TARGET_REGISTER_MOVE_COST
14842 #define TARGET_REGISTER_MOVE_COST s390_register_move_cost
14843 #undef TARGET_MEMORY_MOVE_COST
14844 #define TARGET_MEMORY_MOVE_COST s390_memory_move_cost
14846 #undef TARGET_MACHINE_DEPENDENT_REORG
14847 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
14849 #undef TARGET_VALID_POINTER_MODE
14850 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
14852 #undef TARGET_BUILD_BUILTIN_VA_LIST
14853 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
14854 #undef TARGET_EXPAND_BUILTIN_VA_START
14855 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
14856 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
14857 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
14859 #undef TARGET_PROMOTE_FUNCTION_MODE
14860 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
14861 #undef TARGET_PASS_BY_REFERENCE
14862 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
14864 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
14865 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
14866 #undef TARGET_FUNCTION_ARG
14867 #define TARGET_FUNCTION_ARG s390_function_arg
14868 #undef TARGET_FUNCTION_ARG_ADVANCE
14869 #define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance
14870 #undef TARGET_FUNCTION_VALUE
14871 #define TARGET_FUNCTION_VALUE s390_function_value
14872 #undef TARGET_LIBCALL_VALUE
14873 #define TARGET_LIBCALL_VALUE s390_libcall_value
14874 #undef TARGET_STRICT_ARGUMENT_NAMING
14875 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
14877 #undef TARGET_KEEP_LEAF_WHEN_PROFILED
14878 #define TARGET_KEEP_LEAF_WHEN_PROFILED s390_keep_leaf_when_profiled
14880 #undef TARGET_FIXED_CONDITION_CODE_REGS
14881 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
14883 #undef TARGET_CC_MODES_COMPATIBLE
14884 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
14886 #undef TARGET_INVALID_WITHIN_DOLOOP
14887 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_insn_null
14890 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
14891 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
14894 #undef TARGET_DWARF_FRAME_REG_MODE
14895 #define TARGET_DWARF_FRAME_REG_MODE s390_dwarf_frame_reg_mode
14897 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
14898 #undef TARGET_MANGLE_TYPE
14899 #define TARGET_MANGLE_TYPE s390_mangle_type
14902 #undef TARGET_SCALAR_MODE_SUPPORTED_P
14903 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
14905 #undef TARGET_VECTOR_MODE_SUPPORTED_P
14906 #define TARGET_VECTOR_MODE_SUPPORTED_P s390_vector_mode_supported_p
14908 #undef TARGET_PREFERRED_RELOAD_CLASS
14909 #define TARGET_PREFERRED_RELOAD_CLASS s390_preferred_reload_class
14911 #undef TARGET_SECONDARY_RELOAD
14912 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
14914 #undef TARGET_LIBGCC_CMP_RETURN_MODE
14915 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
14917 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
14918 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
14920 #undef TARGET_LEGITIMATE_ADDRESS_P
14921 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
14923 #undef TARGET_LEGITIMATE_CONSTANT_P
14924 #define TARGET_LEGITIMATE_CONSTANT_P s390_legitimate_constant_p
14926 #undef TARGET_LRA_P
14927 #define TARGET_LRA_P s390_lra_p
14929 #undef TARGET_CAN_ELIMINATE
14930 #define TARGET_CAN_ELIMINATE s390_can_eliminate
14932 #undef TARGET_CONDITIONAL_REGISTER_USAGE
14933 #define TARGET_CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage
14935 #undef TARGET_LOOP_UNROLL_ADJUST
14936 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
14938 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
14939 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
14940 #undef TARGET_TRAMPOLINE_INIT
14941 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
14943 #undef TARGET_UNWIND_WORD_MODE
14944 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
14946 #undef TARGET_CANONICALIZE_COMPARISON
14947 #define TARGET_CANONICALIZE_COMPARISON s390_canonicalize_comparison
14949 #undef TARGET_HARD_REGNO_SCRATCH_OK
14950 #define TARGET_HARD_REGNO_SCRATCH_OK s390_hard_regno_scratch_ok
14952 #undef TARGET_ATTRIBUTE_TABLE
14953 #define TARGET_ATTRIBUTE_TABLE s390_attribute_table
14955 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
14956 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
14958 #undef TARGET_SET_UP_BY_PROLOGUE
14959 #define TARGET_SET_UP_BY_PROLOGUE s300_set_up_by_prologue
14961 #undef TARGET_EXTRA_LIVE_ON_ENTRY
14962 #define TARGET_EXTRA_LIVE_ON_ENTRY s390_live_on_entry
14964 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
14965 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
14966 s390_use_by_pieces_infrastructure_p
14968 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
14969 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV s390_atomic_assign_expand_fenv
14971 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
14972 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN s390_invalid_arg_for_unprototyped_fn
14974 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
14975 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE s390_preferred_simd_mode
14977 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
14978 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT s390_support_vector_misalignment
14980 #undef TARGET_VECTOR_ALIGNMENT
14981 #define TARGET_VECTOR_ALIGNMENT s390_vector_alignment
14983 #undef TARGET_INVALID_BINARY_OP
14984 #define TARGET_INVALID_BINARY_OP s390_invalid_binary_op
14986 #ifdef HAVE_AS_MACHINE_MACHINEMODE
14987 #undef TARGET_ASM_FILE_START
14988 #define TARGET_ASM_FILE_START s390_asm_file_start
14991 #undef TARGET_ASM_FILE_END
14992 #define TARGET_ASM_FILE_END s390_asm_file_end
14994 #if S390_USE_TARGET_ATTRIBUTE
14995 #undef TARGET_SET_CURRENT_FUNCTION
14996 #define TARGET_SET_CURRENT_FUNCTION s390_set_current_function
14998 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
14999 #define TARGET_OPTION_VALID_ATTRIBUTE_P s390_valid_target_attribute_p
15002 #undef TARGET_OPTION_RESTORE
15003 #define TARGET_OPTION_RESTORE s390_function_specific_restore
15005 struct gcc_target targetm
= TARGET_INITIALIZER
;
15007 #include "gt-s390.h"