1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999-2017 Free Software Foundation, Inc.
3 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 Ulrich Weigand (uweigand@de.ibm.com) and
5 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 3, or (at your option) any later
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
28 #include "target-globals.h"
37 #include "stringpool.h"
45 #include "diagnostic-core.h"
46 #include "diagnostic.h"
48 #include "fold-const.h"
49 #include "print-tree.h"
50 #include "stor-layout.h"
53 #include "conditions.h"
55 #include "insn-attr.h"
67 #include "cfgcleanup.h"
69 #include "langhooks.h"
70 #include "internal-fn.h"
71 #include "gimple-fold.h"
76 #include "tree-pass.h"
81 #include "tm-constrs.h"
83 #include "symbol-summary.h"
85 #include "ipa-fnsummary.h"
86 #include "sched-int.h"
88 /* This file should be included last. */
89 #include "target-def.h"
91 static bool s390_hard_regno_mode_ok (unsigned int, machine_mode
);
93 /* Remember the last target of s390_set_current_function. */
94 static GTY(()) tree s390_previous_fndecl
;
96 /* Define the specific costs for a given cpu. */
98 struct processor_costs
101 const int m
; /* cost of an M instruction. */
102 const int mghi
; /* cost of an MGHI instruction. */
103 const int mh
; /* cost of an MH instruction. */
104 const int mhi
; /* cost of an MHI instruction. */
105 const int ml
; /* cost of an ML instruction. */
106 const int mr
; /* cost of an MR instruction. */
107 const int ms
; /* cost of an MS instruction. */
108 const int msg
; /* cost of an MSG instruction. */
109 const int msgf
; /* cost of an MSGF instruction. */
110 const int msgfr
; /* cost of an MSGFR instruction. */
111 const int msgr
; /* cost of an MSGR instruction. */
112 const int msr
; /* cost of an MSR instruction. */
113 const int mult_df
; /* cost of multiplication in DFmode. */
116 const int sqxbr
; /* cost of square root in TFmode. */
117 const int sqdbr
; /* cost of square root in DFmode. */
118 const int sqebr
; /* cost of square root in SFmode. */
119 /* multiply and add */
120 const int madbr
; /* cost of multiply and add in DFmode. */
121 const int maebr
; /* cost of multiply and add in SFmode. */
133 #define s390_cost ((const struct processor_costs *)(s390_cost_pointer))
136 struct processor_costs z900_cost
=
138 COSTS_N_INSNS (5), /* M */
139 COSTS_N_INSNS (10), /* MGHI */
140 COSTS_N_INSNS (5), /* MH */
141 COSTS_N_INSNS (4), /* MHI */
142 COSTS_N_INSNS (5), /* ML */
143 COSTS_N_INSNS (5), /* MR */
144 COSTS_N_INSNS (4), /* MS */
145 COSTS_N_INSNS (15), /* MSG */
146 COSTS_N_INSNS (7), /* MSGF */
147 COSTS_N_INSNS (7), /* MSGFR */
148 COSTS_N_INSNS (10), /* MSGR */
149 COSTS_N_INSNS (4), /* MSR */
150 COSTS_N_INSNS (7), /* multiplication in DFmode */
151 COSTS_N_INSNS (13), /* MXBR */
152 COSTS_N_INSNS (136), /* SQXBR */
153 COSTS_N_INSNS (44), /* SQDBR */
154 COSTS_N_INSNS (35), /* SQEBR */
155 COSTS_N_INSNS (18), /* MADBR */
156 COSTS_N_INSNS (13), /* MAEBR */
157 COSTS_N_INSNS (134), /* DXBR */
158 COSTS_N_INSNS (30), /* DDBR */
159 COSTS_N_INSNS (27), /* DEBR */
160 COSTS_N_INSNS (220), /* DLGR */
161 COSTS_N_INSNS (34), /* DLR */
162 COSTS_N_INSNS (34), /* DR */
163 COSTS_N_INSNS (32), /* DSGFR */
164 COSTS_N_INSNS (32), /* DSGR */
168 struct processor_costs z990_cost
=
170 COSTS_N_INSNS (4), /* M */
171 COSTS_N_INSNS (2), /* MGHI */
172 COSTS_N_INSNS (2), /* MH */
173 COSTS_N_INSNS (2), /* MHI */
174 COSTS_N_INSNS (4), /* ML */
175 COSTS_N_INSNS (4), /* MR */
176 COSTS_N_INSNS (5), /* MS */
177 COSTS_N_INSNS (6), /* MSG */
178 COSTS_N_INSNS (4), /* MSGF */
179 COSTS_N_INSNS (4), /* MSGFR */
180 COSTS_N_INSNS (4), /* MSGR */
181 COSTS_N_INSNS (4), /* MSR */
182 COSTS_N_INSNS (1), /* multiplication in DFmode */
183 COSTS_N_INSNS (28), /* MXBR */
184 COSTS_N_INSNS (130), /* SQXBR */
185 COSTS_N_INSNS (66), /* SQDBR */
186 COSTS_N_INSNS (38), /* SQEBR */
187 COSTS_N_INSNS (1), /* MADBR */
188 COSTS_N_INSNS (1), /* MAEBR */
189 COSTS_N_INSNS (60), /* DXBR */
190 COSTS_N_INSNS (40), /* DDBR */
191 COSTS_N_INSNS (26), /* DEBR */
192 COSTS_N_INSNS (176), /* DLGR */
193 COSTS_N_INSNS (31), /* DLR */
194 COSTS_N_INSNS (31), /* DR */
195 COSTS_N_INSNS (31), /* DSGFR */
196 COSTS_N_INSNS (31), /* DSGR */
200 struct processor_costs z9_109_cost
=
202 COSTS_N_INSNS (4), /* M */
203 COSTS_N_INSNS (2), /* MGHI */
204 COSTS_N_INSNS (2), /* MH */
205 COSTS_N_INSNS (2), /* MHI */
206 COSTS_N_INSNS (4), /* ML */
207 COSTS_N_INSNS (4), /* MR */
208 COSTS_N_INSNS (5), /* MS */
209 COSTS_N_INSNS (6), /* MSG */
210 COSTS_N_INSNS (4), /* MSGF */
211 COSTS_N_INSNS (4), /* MSGFR */
212 COSTS_N_INSNS (4), /* MSGR */
213 COSTS_N_INSNS (4), /* MSR */
214 COSTS_N_INSNS (1), /* multiplication in DFmode */
215 COSTS_N_INSNS (28), /* MXBR */
216 COSTS_N_INSNS (130), /* SQXBR */
217 COSTS_N_INSNS (66), /* SQDBR */
218 COSTS_N_INSNS (38), /* SQEBR */
219 COSTS_N_INSNS (1), /* MADBR */
220 COSTS_N_INSNS (1), /* MAEBR */
221 COSTS_N_INSNS (60), /* DXBR */
222 COSTS_N_INSNS (40), /* DDBR */
223 COSTS_N_INSNS (26), /* DEBR */
224 COSTS_N_INSNS (30), /* DLGR */
225 COSTS_N_INSNS (23), /* DLR */
226 COSTS_N_INSNS (23), /* DR */
227 COSTS_N_INSNS (24), /* DSGFR */
228 COSTS_N_INSNS (24), /* DSGR */
232 struct processor_costs z10_cost
=
234 COSTS_N_INSNS (10), /* M */
235 COSTS_N_INSNS (10), /* MGHI */
236 COSTS_N_INSNS (10), /* MH */
237 COSTS_N_INSNS (10), /* MHI */
238 COSTS_N_INSNS (10), /* ML */
239 COSTS_N_INSNS (10), /* MR */
240 COSTS_N_INSNS (10), /* MS */
241 COSTS_N_INSNS (10), /* MSG */
242 COSTS_N_INSNS (10), /* MSGF */
243 COSTS_N_INSNS (10), /* MSGFR */
244 COSTS_N_INSNS (10), /* MSGR */
245 COSTS_N_INSNS (10), /* MSR */
246 COSTS_N_INSNS (1) , /* multiplication in DFmode */
247 COSTS_N_INSNS (50), /* MXBR */
248 COSTS_N_INSNS (120), /* SQXBR */
249 COSTS_N_INSNS (52), /* SQDBR */
250 COSTS_N_INSNS (38), /* SQEBR */
251 COSTS_N_INSNS (1), /* MADBR */
252 COSTS_N_INSNS (1), /* MAEBR */
253 COSTS_N_INSNS (111), /* DXBR */
254 COSTS_N_INSNS (39), /* DDBR */
255 COSTS_N_INSNS (32), /* DEBR */
256 COSTS_N_INSNS (160), /* DLGR */
257 COSTS_N_INSNS (71), /* DLR */
258 COSTS_N_INSNS (71), /* DR */
259 COSTS_N_INSNS (71), /* DSGFR */
260 COSTS_N_INSNS (71), /* DSGR */
264 struct processor_costs z196_cost
=
266 COSTS_N_INSNS (7), /* M */
267 COSTS_N_INSNS (5), /* MGHI */
268 COSTS_N_INSNS (5), /* MH */
269 COSTS_N_INSNS (5), /* MHI */
270 COSTS_N_INSNS (7), /* ML */
271 COSTS_N_INSNS (7), /* MR */
272 COSTS_N_INSNS (6), /* MS */
273 COSTS_N_INSNS (8), /* MSG */
274 COSTS_N_INSNS (6), /* MSGF */
275 COSTS_N_INSNS (6), /* MSGFR */
276 COSTS_N_INSNS (8), /* MSGR */
277 COSTS_N_INSNS (6), /* MSR */
278 COSTS_N_INSNS (1) , /* multiplication in DFmode */
279 COSTS_N_INSNS (40), /* MXBR B+40 */
280 COSTS_N_INSNS (100), /* SQXBR B+100 */
281 COSTS_N_INSNS (42), /* SQDBR B+42 */
282 COSTS_N_INSNS (28), /* SQEBR B+28 */
283 COSTS_N_INSNS (1), /* MADBR B */
284 COSTS_N_INSNS (1), /* MAEBR B */
285 COSTS_N_INSNS (101), /* DXBR B+101 */
286 COSTS_N_INSNS (29), /* DDBR */
287 COSTS_N_INSNS (22), /* DEBR */
288 COSTS_N_INSNS (160), /* DLGR cracked */
289 COSTS_N_INSNS (160), /* DLR cracked */
290 COSTS_N_INSNS (160), /* DR expanded */
291 COSTS_N_INSNS (160), /* DSGFR cracked */
292 COSTS_N_INSNS (160), /* DSGR cracked */
296 struct processor_costs zEC12_cost
=
298 COSTS_N_INSNS (7), /* M */
299 COSTS_N_INSNS (5), /* MGHI */
300 COSTS_N_INSNS (5), /* MH */
301 COSTS_N_INSNS (5), /* MHI */
302 COSTS_N_INSNS (7), /* ML */
303 COSTS_N_INSNS (7), /* MR */
304 COSTS_N_INSNS (6), /* MS */
305 COSTS_N_INSNS (8), /* MSG */
306 COSTS_N_INSNS (6), /* MSGF */
307 COSTS_N_INSNS (6), /* MSGFR */
308 COSTS_N_INSNS (8), /* MSGR */
309 COSTS_N_INSNS (6), /* MSR */
310 COSTS_N_INSNS (1) , /* multiplication in DFmode */
311 COSTS_N_INSNS (40), /* MXBR B+40 */
312 COSTS_N_INSNS (100), /* SQXBR B+100 */
313 COSTS_N_INSNS (42), /* SQDBR B+42 */
314 COSTS_N_INSNS (28), /* SQEBR B+28 */
315 COSTS_N_INSNS (1), /* MADBR B */
316 COSTS_N_INSNS (1), /* MAEBR B */
317 COSTS_N_INSNS (131), /* DXBR B+131 */
318 COSTS_N_INSNS (29), /* DDBR */
319 COSTS_N_INSNS (22), /* DEBR */
320 COSTS_N_INSNS (160), /* DLGR cracked */
321 COSTS_N_INSNS (160), /* DLR cracked */
322 COSTS_N_INSNS (160), /* DR expanded */
323 COSTS_N_INSNS (160), /* DSGFR cracked */
324 COSTS_N_INSNS (160), /* DSGR cracked */
329 /* The preferred name to be used in user visible output. */
330 const char *const name
;
331 /* CPU name as it should be passed to Binutils via .machine */
332 const char *const binutils_name
;
333 const enum processor_type processor
;
334 const struct processor_costs
*cost
;
336 const processor_table
[] =
338 { "g5", "g5", PROCESSOR_9672_G5
, &z900_cost
},
339 { "g6", "g6", PROCESSOR_9672_G6
, &z900_cost
},
340 { "z900", "z900", PROCESSOR_2064_Z900
, &z900_cost
},
341 { "z990", "z990", PROCESSOR_2084_Z990
, &z990_cost
},
342 { "z9-109", "z9-109", PROCESSOR_2094_Z9_109
, &z9_109_cost
},
343 { "z9-ec", "z9-ec", PROCESSOR_2094_Z9_EC
, &z9_109_cost
},
344 { "z10", "z10", PROCESSOR_2097_Z10
, &z10_cost
},
345 { "z196", "z196", PROCESSOR_2817_Z196
, &z196_cost
},
346 { "zEC12", "zEC12", PROCESSOR_2827_ZEC12
, &zEC12_cost
},
347 { "z13", "z13", PROCESSOR_2964_Z13
, &zEC12_cost
},
348 { "z14", "arch12", PROCESSOR_3906_Z14
, &zEC12_cost
},
349 { "native", "", PROCESSOR_NATIVE
, NULL
}
352 extern int reload_completed
;
354 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
355 static rtx_insn
*last_scheduled_insn
;
356 #define MAX_SCHED_UNITS 3
357 static int last_scheduled_unit_distance
[MAX_SCHED_UNITS
];
360 static int current_side
= 1;
361 #define LONGRUNNING_THRESHOLD 5
363 /* Estimate of number of cycles a long-running insn occupies an
365 static unsigned fxu_longrunning
[NUM_SIDES
];
366 static unsigned vfu_longrunning
[NUM_SIDES
];
368 /* Factor to scale latencies by, determined by measurements. */
369 #define LATENCY_FACTOR 4
371 /* The maximum score added for an instruction whose unit hasn't been
372 in use for MAX_SCHED_MIX_DISTANCE steps. Increase this value to
373 give instruction mix scheduling more priority over instruction
375 #define MAX_SCHED_MIX_SCORE 8
377 /* The maximum distance up to which individual scores will be
378 calculated. Everything beyond this gives MAX_SCHED_MIX_SCORE.
379 Increase this with the OOO windows size of the machine. */
380 #define MAX_SCHED_MIX_DISTANCE 100
382 /* Structure used to hold the components of a S/390 memory
383 address. A legitimate address on S/390 is of the general
385 base + index + displacement
386 where any of the components is optional.
388 base and index are registers of the class ADDR_REGS,
389 displacement is an unsigned 12-bit immediate constant. */
400 /* The following structure is embedded in the machine
401 specific part of struct function. */
403 struct GTY (()) s390_frame_layout
405 /* Offset within stack frame. */
406 HOST_WIDE_INT gprs_offset
;
407 HOST_WIDE_INT f0_offset
;
408 HOST_WIDE_INT f4_offset
;
409 HOST_WIDE_INT f8_offset
;
410 HOST_WIDE_INT backchain_offset
;
412 /* Number of first and last gpr where slots in the register
413 save area are reserved for. */
414 int first_save_gpr_slot
;
415 int last_save_gpr_slot
;
417 /* Location (FP register number) where GPRs (r0-r15) should
419 0 - does not need to be saved at all
421 #define SAVE_SLOT_NONE 0
422 #define SAVE_SLOT_STACK -1
423 signed char gpr_save_slots
[16];
425 /* Number of first and last gpr to be saved, restored. */
427 int first_restore_gpr
;
429 int last_restore_gpr
;
431 /* Bits standing for floating point registers. Set, if the
432 respective register has to be saved. Starting with reg 16 (f0)
433 at the rightmost bit.
434 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
435 fpr 15 13 11 9 14 12 10 8 7 5 3 1 6 4 2 0
436 reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 */
437 unsigned int fpr_bitmap
;
439 /* Number of floating point registers f8-f15 which must be saved. */
442 /* Set if return address needs to be saved.
443 This flag is set by s390_return_addr_rtx if it could not use
444 the initial value of r14 and therefore depends on r14 saved
446 bool save_return_addr_p
;
448 /* Size of stack frame. */
449 HOST_WIDE_INT frame_size
;
452 /* Define the structure for the machine field in struct function. */
454 struct GTY(()) machine_function
456 struct s390_frame_layout frame_layout
;
458 /* Literal pool base register. */
461 /* True if we may need to perform branch splitting. */
462 bool split_branches_pending_p
;
464 bool has_landing_pad_p
;
466 /* True if the current function may contain a tbegin clobbering
470 /* For -fsplit-stack support: A stack local which holds a pointer to
471 the stack arguments for a function with a variable number of
472 arguments. This is set at the start of the function and is used
473 to initialize the overflow_arg_area field of the va_list
475 rtx split_stack_varargs_pointer
;
478 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
480 #define cfun_frame_layout (cfun->machine->frame_layout)
481 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
482 #define cfun_save_arg_fprs_p (!!(TARGET_64BIT \
483 ? cfun_frame_layout.fpr_bitmap & 0x0f \
484 : cfun_frame_layout.fpr_bitmap & 0x03))
485 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
486 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
487 #define cfun_set_fpr_save(REGNO) (cfun->machine->frame_layout.fpr_bitmap |= \
488 (1 << (REGNO - FPR0_REGNUM)))
489 #define cfun_fpr_save_p(REGNO) (!!(cfun->machine->frame_layout.fpr_bitmap & \
490 (1 << (REGNO - FPR0_REGNUM))))
491 #define cfun_gpr_save_slot(REGNO) \
492 cfun->machine->frame_layout.gpr_save_slots[REGNO]
494 /* Number of GPRs and FPRs used for argument passing. */
495 #define GP_ARG_NUM_REG 5
496 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
497 #define VEC_ARG_NUM_REG 8
499 /* A couple of shortcuts. */
500 #define CONST_OK_FOR_J(x) \
501 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
502 #define CONST_OK_FOR_K(x) \
503 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
504 #define CONST_OK_FOR_Os(x) \
505 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
506 #define CONST_OK_FOR_Op(x) \
507 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
508 #define CONST_OK_FOR_On(x) \
509 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
511 #define REGNO_PAIR_OK(REGNO, MODE) \
512 (s390_hard_regno_nregs ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
514 /* That's the read ahead of the dynamic branch prediction unit in
515 bytes on a z10 (or higher) CPU. */
516 #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
519 /* Indicate which ABI has been used for passing vector args.
520 0 - no vector type arguments have been passed where the ABI is relevant
521 1 - the old ABI has been used
522 2 - a vector type argument has been passed either in a vector register
523 or on the stack by value */
524 static int s390_vector_abi
= 0;
526 /* Set the vector ABI marker if TYPE is subject to the vector ABI
527 switch. The vector ABI affects only vector data types. There are
528 two aspects of the vector ABI relevant here:
530 1. vectors >= 16 bytes have an alignment of 8 bytes with the new
531 ABI and natural alignment with the old.
533 2. vector <= 16 bytes are passed in VRs or by value on the stack
534 with the new ABI but by reference on the stack with the old.
536 If ARG_P is true TYPE is used for a function argument or return
537 value. The ABI marker then is set for all vector data types. If
538 ARG_P is false only type 1 vectors are being checked. */
541 s390_check_type_for_vector_abi (const_tree type
, bool arg_p
, bool in_struct_p
)
543 static hash_set
<const_tree
> visited_types_hash
;
548 if (type
== NULL_TREE
|| TREE_CODE (type
) == ERROR_MARK
)
551 if (visited_types_hash
.contains (type
))
554 visited_types_hash
.add (type
);
556 if (VECTOR_TYPE_P (type
))
558 int type_size
= int_size_in_bytes (type
);
560 /* Outside arguments only the alignment is changing and this
561 only happens for vector types >= 16 bytes. */
562 if (!arg_p
&& type_size
< 16)
565 /* In arguments vector types > 16 are passed as before (GCC
566 never enforced the bigger alignment for arguments which was
567 required by the old vector ABI). However, it might still be
568 ABI relevant due to the changed alignment if it is a struct
570 if (arg_p
&& type_size
> 16 && !in_struct_p
)
573 s390_vector_abi
= TARGET_VX_ABI
? 2 : 1;
575 else if (POINTER_TYPE_P (type
) || TREE_CODE (type
) == ARRAY_TYPE
)
577 /* ARRAY_TYPE: Since with neither of the ABIs we have more than
578 natural alignment there will never be ABI dependent padding
579 in an array type. That's why we do not set in_struct_p to
581 s390_check_type_for_vector_abi (TREE_TYPE (type
), arg_p
, in_struct_p
);
583 else if (TREE_CODE (type
) == FUNCTION_TYPE
|| TREE_CODE (type
) == METHOD_TYPE
)
587 /* Check the return type. */
588 s390_check_type_for_vector_abi (TREE_TYPE (type
), true, false);
590 for (arg_chain
= TYPE_ARG_TYPES (type
);
592 arg_chain
= TREE_CHAIN (arg_chain
))
593 s390_check_type_for_vector_abi (TREE_VALUE (arg_chain
), true, false);
595 else if (RECORD_OR_UNION_TYPE_P (type
))
599 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
601 if (TREE_CODE (field
) != FIELD_DECL
)
604 s390_check_type_for_vector_abi (TREE_TYPE (field
), arg_p
, true);
610 /* System z builtins. */
612 #include "s390-builtins.h"
614 const unsigned int bflags_builtin
[S390_BUILTIN_MAX
+ 1] =
619 #define B_DEF(NAME, PATTERN, ATTRS, BFLAGS, ...) BFLAGS,
621 #define OB_DEF_VAR(...)
622 #include "s390-builtins.def"
626 const unsigned int opflags_builtin
[S390_BUILTIN_MAX
+ 1] =
631 #define B_DEF(NAME, PATTERN, ATTRS, BFLAGS, OPFLAGS, ...) OPFLAGS,
633 #define OB_DEF_VAR(...)
634 #include "s390-builtins.def"
638 const unsigned int bflags_overloaded_builtin
[S390_OVERLOADED_BUILTIN_MAX
+ 1] =
644 #define OB_DEF(NAME, FIRST_VAR_NAME, LAST_VAR_NAME, BFLAGS, ...) BFLAGS,
645 #define OB_DEF_VAR(...)
646 #include "s390-builtins.def"
651 bflags_overloaded_builtin_var
[S390_OVERLOADED_BUILTIN_VAR_MAX
+ 1] =
658 #define OB_DEF_VAR(NAME, PATTERN, FLAGS, OPFLAGS, FNTYPE) FLAGS,
659 #include "s390-builtins.def"
664 opflags_overloaded_builtin_var
[S390_OVERLOADED_BUILTIN_VAR_MAX
+ 1] =
671 #define OB_DEF_VAR(NAME, PATTERN, FLAGS, OPFLAGS, FNTYPE) OPFLAGS,
672 #include "s390-builtins.def"
676 tree s390_builtin_types
[BT_MAX
];
677 tree s390_builtin_fn_types
[BT_FN_MAX
];
678 tree s390_builtin_decls
[S390_BUILTIN_MAX
+
679 S390_OVERLOADED_BUILTIN_MAX
+
680 S390_OVERLOADED_BUILTIN_VAR_MAX
];
682 static enum insn_code
const code_for_builtin
[S390_BUILTIN_MAX
+ 1] = {
686 #define B_DEF(NAME, PATTERN, ...) CODE_FOR_##PATTERN,
688 #define OB_DEF_VAR(...)
690 #include "s390-builtins.def"
695 s390_init_builtins (void)
697 /* These definitions are being used in s390-builtins.def. */
698 tree returns_twice_attr
= tree_cons (get_identifier ("returns_twice"),
700 tree noreturn_attr
= tree_cons (get_identifier ("noreturn"), NULL
, NULL
);
701 tree c_uint64_type_node
;
703 /* The uint64_type_node from tree.c is not compatible to the C99
704 uint64_t data type. What we want is c_uint64_type_node from
705 c-common.c. But since backend code is not supposed to interface
706 with the frontend we recreate it here. */
708 c_uint64_type_node
= long_unsigned_type_node
;
710 c_uint64_type_node
= long_long_unsigned_type_node
;
713 #define DEF_TYPE(INDEX, NODE, CONST_P) \
714 if (s390_builtin_types[INDEX] == NULL) \
715 s390_builtin_types[INDEX] = (!CONST_P) ? \
716 (NODE) : build_type_variant ((NODE), 1, 0);
718 #undef DEF_POINTER_TYPE
719 #define DEF_POINTER_TYPE(INDEX, INDEX_BASE) \
720 if (s390_builtin_types[INDEX] == NULL) \
721 s390_builtin_types[INDEX] = \
722 build_pointer_type (s390_builtin_types[INDEX_BASE]);
724 #undef DEF_DISTINCT_TYPE
725 #define DEF_DISTINCT_TYPE(INDEX, INDEX_BASE) \
726 if (s390_builtin_types[INDEX] == NULL) \
727 s390_builtin_types[INDEX] = \
728 build_distinct_type_copy (s390_builtin_types[INDEX_BASE]);
730 #undef DEF_VECTOR_TYPE
731 #define DEF_VECTOR_TYPE(INDEX, INDEX_BASE, ELEMENTS) \
732 if (s390_builtin_types[INDEX] == NULL) \
733 s390_builtin_types[INDEX] = \
734 build_vector_type (s390_builtin_types[INDEX_BASE], ELEMENTS);
736 #undef DEF_OPAQUE_VECTOR_TYPE
737 #define DEF_OPAQUE_VECTOR_TYPE(INDEX, INDEX_BASE, ELEMENTS) \
738 if (s390_builtin_types[INDEX] == NULL) \
739 s390_builtin_types[INDEX] = \
740 build_opaque_vector_type (s390_builtin_types[INDEX_BASE], ELEMENTS);
743 #define DEF_FN_TYPE(INDEX, args...) \
744 if (s390_builtin_fn_types[INDEX] == NULL) \
745 s390_builtin_fn_types[INDEX] = \
746 build_function_type_list (args, NULL_TREE);
748 #define DEF_OV_TYPE(...)
749 #include "s390-builtin-types.def"
752 #define B_DEF(NAME, PATTERN, ATTRS, BFLAGS, OPFLAGS, FNTYPE) \
753 if (s390_builtin_decls[S390_BUILTIN_##NAME] == NULL) \
754 s390_builtin_decls[S390_BUILTIN_##NAME] = \
755 add_builtin_function ("__builtin_" #NAME, \
756 s390_builtin_fn_types[FNTYPE], \
757 S390_BUILTIN_##NAME, \
762 #define OB_DEF(NAME, FIRST_VAR_NAME, LAST_VAR_NAME, BFLAGS, FNTYPE) \
763 if (s390_builtin_decls[S390_OVERLOADED_BUILTIN_##NAME + S390_BUILTIN_MAX] \
765 s390_builtin_decls[S390_OVERLOADED_BUILTIN_##NAME + S390_BUILTIN_MAX] = \
766 add_builtin_function ("__builtin_" #NAME, \
767 s390_builtin_fn_types[FNTYPE], \
768 S390_OVERLOADED_BUILTIN_##NAME + S390_BUILTIN_MAX, \
773 #define OB_DEF_VAR(...)
774 #include "s390-builtins.def"
778 /* Return true if ARG is appropriate as argument number ARGNUM of
779 builtin DECL. The operand flags from s390-builtins.def have to
780 passed as OP_FLAGS. */
782 s390_const_operand_ok (tree arg
, int argnum
, int op_flags
, tree decl
)
784 if (O_UIMM_P (op_flags
))
786 int bitwidths
[] = { 1, 2, 3, 4, 5, 8, 12, 16, 32 };
787 int bitwidth
= bitwidths
[op_flags
- O_U1
];
789 if (!tree_fits_uhwi_p (arg
)
790 || tree_to_uhwi (arg
) > (HOST_WIDE_INT_1U
<< bitwidth
) - 1)
792 error("constant argument %d for builtin %qF is out of range (0.."
793 HOST_WIDE_INT_PRINT_UNSIGNED
")",
795 (HOST_WIDE_INT_1U
<< bitwidth
) - 1);
800 if (O_SIMM_P (op_flags
))
802 int bitwidths
[] = { 2, 3, 4, 5, 8, 12, 16, 32 };
803 int bitwidth
= bitwidths
[op_flags
- O_S2
];
805 if (!tree_fits_shwi_p (arg
)
806 || tree_to_shwi (arg
) < -(HOST_WIDE_INT_1
<< (bitwidth
- 1))
807 || tree_to_shwi (arg
) > ((HOST_WIDE_INT_1
<< (bitwidth
- 1)) - 1))
809 error("constant argument %d for builtin %qF is out of range ("
810 HOST_WIDE_INT_PRINT_DEC
".."
811 HOST_WIDE_INT_PRINT_DEC
")",
813 -(HOST_WIDE_INT_1
<< (bitwidth
- 1)),
814 (HOST_WIDE_INT_1
<< (bitwidth
- 1)) - 1);
821 /* Expand an expression EXP that calls a built-in function,
822 with result going to TARGET if that's convenient
823 (and in mode MODE if that's convenient).
824 SUBTARGET may be used as the target for computing one of EXP's operands.
825 IGNORE is nonzero if the value is to be ignored. */
828 s390_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
829 machine_mode mode ATTRIBUTE_UNUSED
,
830 int ignore ATTRIBUTE_UNUSED
)
834 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
835 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
836 enum insn_code icode
;
837 rtx op
[MAX_ARGS
], pat
;
841 call_expr_arg_iterator iter
;
842 unsigned int all_op_flags
= opflags_for_builtin (fcode
);
843 machine_mode last_vec_mode
= VOIDmode
;
845 if (TARGET_DEBUG_ARG
)
848 "s390_expand_builtin, code = %4d, %s, bflags = 0x%x\n",
849 (int)fcode
, IDENTIFIER_POINTER (DECL_NAME (fndecl
)),
850 bflags_for_builtin (fcode
));
853 if (S390_USE_TARGET_ATTRIBUTE
)
857 bflags
= bflags_for_builtin (fcode
);
858 if ((bflags
& B_HTM
) && !TARGET_HTM
)
860 error ("builtin %qF is not supported without -mhtm "
861 "(default with -march=zEC12 and higher).", fndecl
);
864 if (((bflags
& B_VX
) || (bflags
& B_VXE
)) && !TARGET_VX
)
866 error ("builtin %qF requires -mvx "
867 "(default with -march=z13 and higher).", fndecl
);
871 if ((bflags
& B_VXE
) && !TARGET_VXE
)
873 error ("Builtin %qF requires z14 or higher.", fndecl
);
877 if (fcode
>= S390_OVERLOADED_BUILTIN_VAR_OFFSET
878 && fcode
< S390_ALL_BUILTIN_MAX
)
882 else if (fcode
< S390_OVERLOADED_BUILTIN_OFFSET
)
884 icode
= code_for_builtin
[fcode
];
885 /* Set a flag in the machine specific cfun part in order to support
886 saving/restoring of FPRs. */
887 if (fcode
== S390_BUILTIN_tbegin
|| fcode
== S390_BUILTIN_tbegin_retry
)
888 cfun
->machine
->tbegin_p
= true;
890 else if (fcode
< S390_OVERLOADED_BUILTIN_VAR_OFFSET
)
892 error ("unresolved overloaded builtin");
896 internal_error ("bad builtin fcode");
899 internal_error ("bad builtin icode");
901 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
905 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
907 || GET_MODE (target
) != tmode
908 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
909 target
= gen_reg_rtx (tmode
);
911 /* There are builtins (e.g. vec_promote) with no vector
912 arguments but an element selector. So we have to also look
913 at the vector return type when emitting the modulo
915 if (VECTOR_MODE_P (insn_data
[icode
].operand
[0].mode
))
916 last_vec_mode
= insn_data
[icode
].operand
[0].mode
;
920 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
923 const struct insn_operand_data
*insn_op
;
924 unsigned int op_flags
= all_op_flags
& ((1 << O_SHIFT
) - 1);
926 all_op_flags
= all_op_flags
>> O_SHIFT
;
928 if (arg
== error_mark_node
)
930 if (arity
>= MAX_ARGS
)
933 if (O_IMM_P (op_flags
)
934 && TREE_CODE (arg
) != INTEGER_CST
)
936 error ("constant value required for builtin %qF argument %d",
941 if (!s390_const_operand_ok (arg
, arity
+ 1, op_flags
, fndecl
))
944 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
945 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, EXPAND_NORMAL
);
947 /* expand_expr truncates constants to the target mode only if it
948 is "convenient". However, our checks below rely on this
950 if (CONST_INT_P (op
[arity
])
951 && SCALAR_INT_MODE_P (insn_op
->mode
)
952 && GET_MODE (op
[arity
]) != insn_op
->mode
)
953 op
[arity
] = GEN_INT (trunc_int_for_mode (INTVAL (op
[arity
]),
956 /* Wrap the expanded RTX for pointer types into a MEM expr with
957 the proper mode. This allows us to use e.g. (match_operand
958 "memory_operand"..) in the insn patterns instead of (mem
959 (match_operand "address_operand)). This is helpful for
960 patterns not just accepting MEMs. */
961 if (POINTER_TYPE_P (TREE_TYPE (arg
))
962 && insn_op
->predicate
!= address_operand
)
963 op
[arity
] = gen_rtx_MEM (insn_op
->mode
, op
[arity
]);
965 /* Expand the module operation required on element selectors. */
966 if (op_flags
== O_ELEM
)
968 gcc_assert (last_vec_mode
!= VOIDmode
);
969 op
[arity
] = simplify_expand_binop (SImode
, code_to_optab (AND
),
971 GEN_INT (GET_MODE_NUNITS (last_vec_mode
) - 1),
972 NULL_RTX
, 1, OPTAB_DIRECT
);
975 /* Record the vector mode used for an element selector. This assumes:
976 1. There is no builtin with two different vector modes and an element selector
977 2. The element selector comes after the vector type it is referring to.
978 This currently the true for all the builtins but FIXME we
979 should better check for that. */
980 if (VECTOR_MODE_P (insn_op
->mode
))
981 last_vec_mode
= insn_op
->mode
;
983 if (insn_op
->predicate (op
[arity
], insn_op
->mode
))
989 if (MEM_P (op
[arity
])
990 && insn_op
->predicate
== memory_operand
991 && (GET_MODE (XEXP (op
[arity
], 0)) == Pmode
992 || GET_MODE (XEXP (op
[arity
], 0)) == VOIDmode
))
994 op
[arity
] = replace_equiv_address (op
[arity
],
995 copy_to_mode_reg (Pmode
,
996 XEXP (op
[arity
], 0)));
998 /* Some of the builtins require different modes/types than the
999 pattern in order to implement a specific API. Instead of
1000 adding many expanders which do the mode change we do it here.
1001 E.g. s390_vec_add_u128 required to have vector unsigned char
1002 arguments is mapped to addti3. */
1003 else if (insn_op
->mode
!= VOIDmode
1004 && GET_MODE (op
[arity
]) != VOIDmode
1005 && GET_MODE (op
[arity
]) != insn_op
->mode
1006 && ((tmp_rtx
= simplify_gen_subreg (insn_op
->mode
, op
[arity
],
1007 GET_MODE (op
[arity
]), 0))
1010 op
[arity
] = tmp_rtx
;
1012 else if (GET_MODE (op
[arity
]) == insn_op
->mode
1013 || GET_MODE (op
[arity
]) == VOIDmode
1014 || (insn_op
->predicate
== address_operand
1015 && GET_MODE (op
[arity
]) == Pmode
))
1017 /* An address_operand usually has VOIDmode in the expander
1018 so we cannot use this. */
1019 machine_mode target_mode
=
1020 (insn_op
->predicate
== address_operand
1021 ? (machine_mode
) Pmode
: insn_op
->mode
);
1022 op
[arity
] = copy_to_mode_reg (target_mode
, op
[arity
]);
1025 if (!insn_op
->predicate (op
[arity
], insn_op
->mode
))
1027 error ("invalid argument %d for builtin %qF", arity
+ 1, fndecl
);
1036 pat
= GEN_FCN (icode
) (target
);
1040 pat
= GEN_FCN (icode
) (target
, op
[0]);
1042 pat
= GEN_FCN (icode
) (op
[0]);
1046 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
1048 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
1052 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1], op
[2]);
1054 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
1058 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1], op
[2], op
[3]);
1060 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
1064 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1], op
[2], op
[3], op
[4]);
1066 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3], op
[4]);
1070 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1], op
[2], op
[3], op
[4], op
[5]);
1072 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3], op
[4], op
[5]);
1088 static const int s390_hotpatch_hw_max
= 1000000;
1089 static int s390_hotpatch_hw_before_label
= 0;
1090 static int s390_hotpatch_hw_after_label
= 0;
1092 /* Check whether the hotpatch attribute is applied to a function and, if it has
1093 an argument, the argument is valid. */
1096 s390_handle_hotpatch_attribute (tree
*node
, tree name
, tree args
,
1097 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
1103 if (TREE_CODE (*node
) != FUNCTION_DECL
)
1105 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
1107 *no_add_attrs
= true;
1109 if (args
!= NULL
&& TREE_CHAIN (args
) != NULL
)
1111 expr
= TREE_VALUE (args
);
1112 expr2
= TREE_VALUE (TREE_CHAIN (args
));
1114 if (args
== NULL
|| TREE_CHAIN (args
) == NULL
)
1116 else if (TREE_CODE (expr
) != INTEGER_CST
1117 || !INTEGRAL_TYPE_P (TREE_TYPE (expr
))
1118 || wi::gtu_p (wi::to_wide (expr
), s390_hotpatch_hw_max
))
1120 else if (TREE_CODE (expr2
) != INTEGER_CST
1121 || !INTEGRAL_TYPE_P (TREE_TYPE (expr2
))
1122 || wi::gtu_p (wi::to_wide (expr2
), s390_hotpatch_hw_max
))
1128 error ("requested %qE attribute is not a comma separated pair of"
1129 " non-negative integer constants or too large (max. %d)", name
,
1130 s390_hotpatch_hw_max
);
1131 *no_add_attrs
= true;
1137 /* Expand the s390_vector_bool type attribute. */
1140 s390_handle_vectorbool_attribute (tree
*node
, tree name ATTRIBUTE_UNUSED
,
1141 tree args ATTRIBUTE_UNUSED
,
1142 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
1144 tree type
= *node
, result
= NULL_TREE
;
1147 while (POINTER_TYPE_P (type
)
1148 || TREE_CODE (type
) == FUNCTION_TYPE
1149 || TREE_CODE (type
) == METHOD_TYPE
1150 || TREE_CODE (type
) == ARRAY_TYPE
)
1151 type
= TREE_TYPE (type
);
1153 mode
= TYPE_MODE (type
);
1156 case E_DImode
: case E_V2DImode
:
1157 result
= s390_builtin_types
[BT_BV2DI
];
1159 case E_SImode
: case E_V4SImode
:
1160 result
= s390_builtin_types
[BT_BV4SI
];
1162 case E_HImode
: case E_V8HImode
:
1163 result
= s390_builtin_types
[BT_BV8HI
];
1165 case E_QImode
: case E_V16QImode
:
1166 result
= s390_builtin_types
[BT_BV16QI
];
1172 *no_add_attrs
= true; /* No need to hang on to the attribute. */
1175 *node
= lang_hooks
.types
.reconstruct_complex_type (*node
, result
);
1180 static const struct attribute_spec s390_attribute_table
[] = {
1181 { "hotpatch", 2, 2, true, false, false, false,
1182 s390_handle_hotpatch_attribute
, NULL
},
1183 { "s390_vector_bool", 0, 0, false, true, false, true,
1184 s390_handle_vectorbool_attribute
, NULL
},
1186 { NULL
, 0, 0, false, false, false, false, NULL
, NULL
}
1189 /* Return the alignment for LABEL. We default to the -falign-labels
1190 value except for the literal pool base label. */
1192 s390_label_align (rtx_insn
*label
)
1194 rtx_insn
*prev_insn
= prev_active_insn (label
);
1197 if (prev_insn
== NULL_RTX
)
1200 set
= single_set (prev_insn
);
1202 if (set
== NULL_RTX
)
1205 src
= SET_SRC (set
);
1207 /* Don't align literal pool base labels. */
1208 if (GET_CODE (src
) == UNSPEC
1209 && XINT (src
, 1) == UNSPEC_MAIN_BASE
)
1213 return align_labels_log
;
1216 static GTY(()) rtx got_symbol
;
1218 /* Return the GOT table symbol. The symbol will be created when the
1219 function is invoked for the first time. */
1222 s390_got_symbol (void)
1226 got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
1227 SYMBOL_REF_FLAGS (got_symbol
) = SYMBOL_FLAG_LOCAL
;
1233 static scalar_int_mode
1234 s390_libgcc_cmp_return_mode (void)
1236 return TARGET_64BIT
? DImode
: SImode
;
1239 static scalar_int_mode
1240 s390_libgcc_shift_count_mode (void)
1242 return TARGET_64BIT
? DImode
: SImode
;
1245 static scalar_int_mode
1246 s390_unwind_word_mode (void)
1248 return TARGET_64BIT
? DImode
: SImode
;
1251 /* Return true if the back end supports mode MODE. */
1253 s390_scalar_mode_supported_p (scalar_mode mode
)
1255 /* In contrast to the default implementation reject TImode constants on 31bit
1256 TARGET_ZARCH for ABI compliance. */
1257 if (!TARGET_64BIT
&& TARGET_ZARCH
&& mode
== TImode
)
1260 if (DECIMAL_FLOAT_MODE_P (mode
))
1261 return default_decimal_float_supported_p ();
1263 return default_scalar_mode_supported_p (mode
);
1266 /* Return true if the back end supports vector mode MODE. */
1268 s390_vector_mode_supported_p (machine_mode mode
)
1272 if (!VECTOR_MODE_P (mode
)
1274 || GET_MODE_SIZE (mode
) > 16)
1277 inner
= GET_MODE_INNER (mode
);
1295 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
1298 s390_set_has_landing_pad_p (bool value
)
1300 cfun
->machine
->has_landing_pad_p
= value
;
1303 /* If two condition code modes are compatible, return a condition code
1304 mode which is compatible with both. Otherwise, return
1308 s390_cc_modes_compatible (machine_mode m1
, machine_mode m2
)
1316 if (m2
== CCUmode
|| m2
== CCTmode
|| m2
== CCZ1mode
1317 || m2
== CCSmode
|| m2
== CCSRmode
|| m2
== CCURmode
)
1338 /* Return true if SET either doesn't set the CC register, or else
1339 the source and destination have matching CC modes and that
1340 CC mode is at least as constrained as REQ_MODE. */
1343 s390_match_ccmode_set (rtx set
, machine_mode req_mode
)
1345 machine_mode set_mode
;
1347 gcc_assert (GET_CODE (set
) == SET
);
1349 /* These modes are supposed to be used only in CC consumer
1351 gcc_assert (req_mode
!= CCVIALLmode
&& req_mode
!= CCVIANYmode
1352 && req_mode
!= CCVFALLmode
&& req_mode
!= CCVFANYmode
);
1354 if (GET_CODE (SET_DEST (set
)) != REG
|| !CC_REGNO_P (REGNO (SET_DEST (set
))))
1357 set_mode
= GET_MODE (SET_DEST (set
));
1377 if (req_mode
!= set_mode
)
1382 if (req_mode
!= CCSmode
&& req_mode
!= CCUmode
&& req_mode
!= CCTmode
1383 && req_mode
!= CCSRmode
&& req_mode
!= CCURmode
1384 && req_mode
!= CCZ1mode
)
1390 if (req_mode
!= CCAmode
)
1398 return (GET_MODE (SET_SRC (set
)) == set_mode
);
1401 /* Return true if every SET in INSN that sets the CC register
1402 has source and destination with matching CC modes and that
1403 CC mode is at least as constrained as REQ_MODE.
1404 If REQ_MODE is VOIDmode, always return false. */
1407 s390_match_ccmode (rtx_insn
*insn
, machine_mode req_mode
)
1411 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
1412 if (req_mode
== VOIDmode
)
1415 if (GET_CODE (PATTERN (insn
)) == SET
)
1416 return s390_match_ccmode_set (PATTERN (insn
), req_mode
);
1418 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
1419 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1421 rtx set
= XVECEXP (PATTERN (insn
), 0, i
);
1422 if (GET_CODE (set
) == SET
)
1423 if (!s390_match_ccmode_set (set
, req_mode
))
1430 /* If a test-under-mask instruction can be used to implement
1431 (compare (and ... OP1) OP2), return the CC mode required
1432 to do that. Otherwise, return VOIDmode.
1433 MIXED is true if the instruction can distinguish between
1434 CC1 and CC2 for mixed selected bits (TMxx), it is false
1435 if the instruction cannot (TM). */
1438 s390_tm_ccmode (rtx op1
, rtx op2
, bool mixed
)
1442 /* ??? Fixme: should work on CONST_WIDE_INT as well. */
1443 if (GET_CODE (op1
) != CONST_INT
|| GET_CODE (op2
) != CONST_INT
)
1446 /* Selected bits all zero: CC0.
1447 e.g.: int a; if ((a & (16 + 128)) == 0) */
1448 if (INTVAL (op2
) == 0)
1451 /* Selected bits all one: CC3.
1452 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
1453 if (INTVAL (op2
) == INTVAL (op1
))
1456 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
1458 if ((a & (16 + 128)) == 16) -> CCT1
1459 if ((a & (16 + 128)) == 128) -> CCT2 */
1462 bit1
= exact_log2 (INTVAL (op2
));
1463 bit0
= exact_log2 (INTVAL (op1
) ^ INTVAL (op2
));
1464 if (bit0
!= -1 && bit1
!= -1)
1465 return bit0
> bit1
? CCT1mode
: CCT2mode
;
1471 /* Given a comparison code OP (EQ, NE, etc.) and the operands
1472 OP0 and OP1 of a COMPARE, return the mode to be used for the
1476 s390_select_ccmode (enum rtx_code code
, rtx op0
, rtx op1
)
1482 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
1483 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
1485 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
1486 && CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1))))
1488 if ((GET_CODE (op0
) == PLUS
|| GET_CODE (op0
) == MINUS
1489 || GET_CODE (op1
) == NEG
)
1490 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
1493 if (GET_CODE (op0
) == AND
)
1495 /* Check whether we can potentially do it via TM. */
1496 machine_mode ccmode
;
1497 ccmode
= s390_tm_ccmode (XEXP (op0
, 1), op1
, 1);
1498 if (ccmode
!= VOIDmode
)
1500 /* Relax CCTmode to CCZmode to allow fall-back to AND
1501 if that turns out to be beneficial. */
1502 return ccmode
== CCTmode
? CCZmode
: ccmode
;
1506 if (register_operand (op0
, HImode
)
1507 && GET_CODE (op1
) == CONST_INT
1508 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 65535))
1510 if (register_operand (op0
, QImode
)
1511 && GET_CODE (op1
) == CONST_INT
1512 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 255))
1521 /* The only overflow condition of NEG and ABS happens when
1522 -INT_MAX is used as parameter, which stays negative. So
1523 we have an overflow from a positive value to a negative.
1524 Using CCAP mode the resulting cc can be used for comparisons. */
1525 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
1526 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
1529 /* If constants are involved in an add instruction it is possible to use
1530 the resulting cc for comparisons with zero. Knowing the sign of the
1531 constant the overflow behavior gets predictable. e.g.:
1532 int a, b; if ((b = a + c) > 0)
1533 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
1534 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
1535 && (CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1)))
1536 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (XEXP (op0
, 1)), 'O', "Os")
1537 /* Avoid INT32_MIN on 32 bit. */
1538 && (!TARGET_ZARCH
|| INTVAL (XEXP (op0
, 1)) != -0x7fffffff - 1))))
1540 if (INTVAL (XEXP((op0
), 1)) < 0)
1554 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
1555 && GET_CODE (op1
) != CONST_INT
)
1561 if (GET_CODE (op0
) == PLUS
1562 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
1565 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
1566 && GET_CODE (op1
) != CONST_INT
)
1572 if (GET_CODE (op0
) == MINUS
1573 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
1576 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
1577 && GET_CODE (op1
) != CONST_INT
)
1586 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
1587 that we can implement more efficiently. */
1590 s390_canonicalize_comparison (int *code
, rtx
*op0
, rtx
*op1
,
1591 bool op0_preserve_value
)
1593 if (op0_preserve_value
)
1596 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
1597 if ((*code
== EQ
|| *code
== NE
)
1598 && *op1
== const0_rtx
1599 && GET_CODE (*op0
) == ZERO_EXTRACT
1600 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
1601 && GET_CODE (XEXP (*op0
, 2)) == CONST_INT
1602 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
1604 rtx inner
= XEXP (*op0
, 0);
1605 HOST_WIDE_INT modesize
= GET_MODE_BITSIZE (GET_MODE (inner
));
1606 HOST_WIDE_INT len
= INTVAL (XEXP (*op0
, 1));
1607 HOST_WIDE_INT pos
= INTVAL (XEXP (*op0
, 2));
1609 if (len
> 0 && len
< modesize
1610 && pos
>= 0 && pos
+ len
<= modesize
1611 && modesize
<= HOST_BITS_PER_WIDE_INT
)
1613 unsigned HOST_WIDE_INT block
;
1614 block
= (HOST_WIDE_INT_1U
<< len
) - 1;
1615 block
<<= modesize
- pos
- len
;
1617 *op0
= gen_rtx_AND (GET_MODE (inner
), inner
,
1618 gen_int_mode (block
, GET_MODE (inner
)));
1622 /* Narrow AND of memory against immediate to enable TM. */
1623 if ((*code
== EQ
|| *code
== NE
)
1624 && *op1
== const0_rtx
1625 && GET_CODE (*op0
) == AND
1626 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
1627 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
1629 rtx inner
= XEXP (*op0
, 0);
1630 rtx mask
= XEXP (*op0
, 1);
1632 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
1633 if (GET_CODE (inner
) == SUBREG
1634 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner
)))
1635 && (GET_MODE_SIZE (GET_MODE (inner
))
1636 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner
))))
1638 & GET_MODE_MASK (GET_MODE (inner
))
1639 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner
))))
1641 inner
= SUBREG_REG (inner
);
1643 /* Do not change volatile MEMs. */
1644 if (MEM_P (inner
) && !MEM_VOLATILE_P (inner
))
1646 int part
= s390_single_part (XEXP (*op0
, 1),
1647 GET_MODE (inner
), QImode
, 0);
1650 mask
= gen_int_mode (s390_extract_part (mask
, QImode
, 0), QImode
);
1651 inner
= adjust_address_nv (inner
, QImode
, part
);
1652 *op0
= gen_rtx_AND (QImode
, inner
, mask
);
1657 /* Narrow comparisons against 0xffff to HImode if possible. */
1658 if ((*code
== EQ
|| *code
== NE
)
1659 && GET_CODE (*op1
) == CONST_INT
1660 && INTVAL (*op1
) == 0xffff
1661 && SCALAR_INT_MODE_P (GET_MODE (*op0
))
1662 && (nonzero_bits (*op0
, GET_MODE (*op0
))
1663 & ~HOST_WIDE_INT_UC (0xffff)) == 0)
1665 *op0
= gen_lowpart (HImode
, *op0
);
1669 /* Remove redundant UNSPEC_STRCMPCC_TO_INT conversions if possible. */
1670 if (GET_CODE (*op0
) == UNSPEC
1671 && XINT (*op0
, 1) == UNSPEC_STRCMPCC_TO_INT
1672 && XVECLEN (*op0
, 0) == 1
1673 && GET_MODE (XVECEXP (*op0
, 0, 0)) == CCUmode
1674 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
1675 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
1676 && *op1
== const0_rtx
)
1678 enum rtx_code new_code
= UNKNOWN
;
1681 case EQ
: new_code
= EQ
; break;
1682 case NE
: new_code
= NE
; break;
1683 case LT
: new_code
= GTU
; break;
1684 case GT
: new_code
= LTU
; break;
1685 case LE
: new_code
= GEU
; break;
1686 case GE
: new_code
= LEU
; break;
1690 if (new_code
!= UNKNOWN
)
1692 *op0
= XVECEXP (*op0
, 0, 0);
1697 /* Remove redundant UNSPEC_CC_TO_INT conversions if possible. */
1698 if (GET_CODE (*op0
) == UNSPEC
1699 && XINT (*op0
, 1) == UNSPEC_CC_TO_INT
1700 && XVECLEN (*op0
, 0) == 1
1701 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
1702 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
1703 && CONST_INT_P (*op1
))
1705 enum rtx_code new_code
= UNKNOWN
;
1706 switch (GET_MODE (XVECEXP (*op0
, 0, 0)))
1712 case EQ
: new_code
= EQ
; break;
1713 case NE
: new_code
= NE
; break;
1720 if (new_code
!= UNKNOWN
)
1722 /* For CCRAWmode put the required cc mask into the second
1724 if (GET_MODE (XVECEXP (*op0
, 0, 0)) == CCRAWmode
1725 && INTVAL (*op1
) >= 0 && INTVAL (*op1
) <= 3)
1726 *op1
= gen_rtx_CONST_INT (VOIDmode
, 1 << (3 - INTVAL (*op1
)));
1727 *op0
= XVECEXP (*op0
, 0, 0);
1732 /* Simplify cascaded EQ, NE with const0_rtx. */
1733 if ((*code
== NE
|| *code
== EQ
)
1734 && (GET_CODE (*op0
) == EQ
|| GET_CODE (*op0
) == NE
)
1735 && GET_MODE (*op0
) == SImode
1736 && GET_MODE (XEXP (*op0
, 0)) == CCZ1mode
1737 && REG_P (XEXP (*op0
, 0))
1738 && XEXP (*op0
, 1) == const0_rtx
1739 && *op1
== const0_rtx
)
1741 if ((*code
== EQ
&& GET_CODE (*op0
) == NE
)
1742 || (*code
== NE
&& GET_CODE (*op0
) == EQ
))
1746 *op0
= XEXP (*op0
, 0);
1749 /* Prefer register over memory as first operand. */
1750 if (MEM_P (*op0
) && REG_P (*op1
))
1752 rtx tem
= *op0
; *op0
= *op1
; *op1
= tem
;
1753 *code
= (int)swap_condition ((enum rtx_code
)*code
);
1756 /* A comparison result is compared against zero. Replace it with
1757 the (perhaps inverted) original comparison.
1758 This probably should be done by simplify_relational_operation. */
1759 if ((*code
== EQ
|| *code
== NE
)
1760 && *op1
== const0_rtx
1761 && COMPARISON_P (*op0
)
1762 && CC_REG_P (XEXP (*op0
, 0)))
1764 enum rtx_code new_code
;
1767 new_code
= reversed_comparison_code_parts (GET_CODE (*op0
),
1769 XEXP (*op1
, 0), NULL
);
1771 new_code
= GET_CODE (*op0
);
1773 if (new_code
!= UNKNOWN
)
1776 *op1
= XEXP (*op0
, 1);
1777 *op0
= XEXP (*op0
, 0);
1783 /* Emit a compare instruction suitable to implement the comparison
1784 OP0 CODE OP1. Return the correct condition RTL to be placed in
1785 the IF_THEN_ELSE of the conditional branch testing the result. */
1788 s390_emit_compare (enum rtx_code code
, rtx op0
, rtx op1
)
1790 machine_mode mode
= s390_select_ccmode (code
, op0
, op1
);
1793 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
1795 /* Do not output a redundant compare instruction if a
1796 compare_and_swap pattern already computed the result and the
1797 machine modes are compatible. */
1798 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0
), mode
)
1804 cc
= gen_rtx_REG (mode
, CC_REGNUM
);
1805 emit_insn (gen_rtx_SET (cc
, gen_rtx_COMPARE (mode
, op0
, op1
)));
1808 return gen_rtx_fmt_ee (code
, VOIDmode
, cc
, const0_rtx
);
1811 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
1813 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
1814 conditional branch testing the result. */
1817 s390_emit_compare_and_swap (enum rtx_code code
, rtx old
, rtx mem
,
1818 rtx cmp
, rtx new_rtx
, machine_mode ccmode
)
1822 cc
= gen_rtx_REG (ccmode
, CC_REGNUM
);
1823 switch (GET_MODE (mem
))
1826 emit_insn (gen_atomic_compare_and_swapsi_internal (old
, mem
, cmp
,
1830 emit_insn (gen_atomic_compare_and_swapdi_internal (old
, mem
, cmp
,
1834 emit_insn (gen_atomic_compare_and_swapti_internal (old
, mem
, cmp
,
1842 return s390_emit_compare (code
, cc
, const0_rtx
);
1845 /* Emit a jump instruction to TARGET and return it. If COND is
1846 NULL_RTX, emit an unconditional jump, else a conditional jump under
1850 s390_emit_jump (rtx target
, rtx cond
)
1854 target
= gen_rtx_LABEL_REF (VOIDmode
, target
);
1856 target
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, target
, pc_rtx
);
1858 insn
= gen_rtx_SET (pc_rtx
, target
);
1859 return emit_jump_insn (insn
);
1862 /* Return branch condition mask to implement a branch
1863 specified by CODE. Return -1 for invalid comparisons. */
1866 s390_branch_condition_mask (rtx code
)
1868 const int CC0
= 1 << 3;
1869 const int CC1
= 1 << 2;
1870 const int CC2
= 1 << 1;
1871 const int CC3
= 1 << 0;
1873 gcc_assert (GET_CODE (XEXP (code
, 0)) == REG
);
1874 gcc_assert (REGNO (XEXP (code
, 0)) == CC_REGNUM
);
1875 gcc_assert (XEXP (code
, 1) == const0_rtx
1876 || (GET_MODE (XEXP (code
, 0)) == CCRAWmode
1877 && CONST_INT_P (XEXP (code
, 1))));
1880 switch (GET_MODE (XEXP (code
, 0)))
1884 switch (GET_CODE (code
))
1886 case EQ
: return CC0
;
1887 case NE
: return CC1
| CC2
| CC3
;
1893 switch (GET_CODE (code
))
1895 case EQ
: return CC1
;
1896 case NE
: return CC0
| CC2
| CC3
;
1902 switch (GET_CODE (code
))
1904 case EQ
: return CC2
;
1905 case NE
: return CC0
| CC1
| CC3
;
1911 switch (GET_CODE (code
))
1913 case EQ
: return CC3
;
1914 case NE
: return CC0
| CC1
| CC2
;
1920 switch (GET_CODE (code
))
1922 case EQ
: return CC0
| CC2
;
1923 case NE
: return CC1
| CC3
;
1929 switch (GET_CODE (code
))
1931 case LTU
: return CC2
| CC3
; /* carry */
1932 case GEU
: return CC0
| CC1
; /* no carry */
1938 switch (GET_CODE (code
))
1940 case GTU
: return CC0
| CC1
; /* borrow */
1941 case LEU
: return CC2
| CC3
; /* no borrow */
1947 switch (GET_CODE (code
))
1949 case EQ
: return CC0
| CC2
;
1950 case NE
: return CC1
| CC3
;
1951 case LTU
: return CC1
;
1952 case GTU
: return CC3
;
1953 case LEU
: return CC1
| CC2
;
1954 case GEU
: return CC2
| CC3
;
1959 switch (GET_CODE (code
))
1961 case EQ
: return CC0
;
1962 case NE
: return CC1
| CC2
| CC3
;
1963 case LTU
: return CC1
;
1964 case GTU
: return CC2
;
1965 case LEU
: return CC0
| CC1
;
1966 case GEU
: return CC0
| CC2
;
1972 switch (GET_CODE (code
))
1974 case EQ
: return CC0
;
1975 case NE
: return CC2
| CC1
| CC3
;
1976 case LTU
: return CC2
;
1977 case GTU
: return CC1
;
1978 case LEU
: return CC0
| CC2
;
1979 case GEU
: return CC0
| CC1
;
1985 switch (GET_CODE (code
))
1987 case EQ
: return CC0
;
1988 case NE
: return CC1
| CC2
| CC3
;
1989 case LT
: return CC1
| CC3
;
1990 case GT
: return CC2
;
1991 case LE
: return CC0
| CC1
| CC3
;
1992 case GE
: return CC0
| CC2
;
1998 switch (GET_CODE (code
))
2000 case EQ
: return CC0
;
2001 case NE
: return CC1
| CC2
| CC3
;
2002 case LT
: return CC1
;
2003 case GT
: return CC2
| CC3
;
2004 case LE
: return CC0
| CC1
;
2005 case GE
: return CC0
| CC2
| CC3
;
2011 switch (GET_CODE (code
))
2013 case EQ
: return CC0
;
2014 case NE
: return CC1
| CC2
| CC3
;
2015 case LT
: return CC1
;
2016 case GT
: return CC2
;
2017 case LE
: return CC0
| CC1
;
2018 case GE
: return CC0
| CC2
;
2019 case UNORDERED
: return CC3
;
2020 case ORDERED
: return CC0
| CC1
| CC2
;
2021 case UNEQ
: return CC0
| CC3
;
2022 case UNLT
: return CC1
| CC3
;
2023 case UNGT
: return CC2
| CC3
;
2024 case UNLE
: return CC0
| CC1
| CC3
;
2025 case UNGE
: return CC0
| CC2
| CC3
;
2026 case LTGT
: return CC1
| CC2
;
2032 switch (GET_CODE (code
))
2034 case EQ
: return CC0
;
2035 case NE
: return CC2
| CC1
| CC3
;
2036 case LT
: return CC2
;
2037 case GT
: return CC1
;
2038 case LE
: return CC0
| CC2
;
2039 case GE
: return CC0
| CC1
;
2040 case UNORDERED
: return CC3
;
2041 case ORDERED
: return CC0
| CC2
| CC1
;
2042 case UNEQ
: return CC0
| CC3
;
2043 case UNLT
: return CC2
| CC3
;
2044 case UNGT
: return CC1
| CC3
;
2045 case UNLE
: return CC0
| CC2
| CC3
;
2046 case UNGE
: return CC0
| CC1
| CC3
;
2047 case LTGT
: return CC2
| CC1
;
2052 /* Vector comparison modes. */
2053 /* CC2 will never be set. It however is part of the negated
2056 switch (GET_CODE (code
))
2061 case GE
: return CC0
;
2062 /* The inverted modes are in fact *any* modes. */
2066 case LT
: return CC3
| CC1
| CC2
;
2071 switch (GET_CODE (code
))
2076 case GE
: return CC0
| CC1
;
2077 /* The inverted modes are in fact *all* modes. */
2081 case LT
: return CC3
| CC2
;
2085 switch (GET_CODE (code
))
2089 case GE
: return CC0
;
2090 /* The inverted modes are in fact *any* modes. */
2093 case UNLT
: return CC3
| CC1
| CC2
;
2098 switch (GET_CODE (code
))
2102 case GE
: return CC0
| CC1
;
2103 /* The inverted modes are in fact *all* modes. */
2106 case UNLT
: return CC3
| CC2
;
2111 switch (GET_CODE (code
))
2114 return INTVAL (XEXP (code
, 1));
2116 return (INTVAL (XEXP (code
, 1))) ^ 0xf;
2127 /* Return branch condition mask to implement a compare and branch
2128 specified by CODE. Return -1 for invalid comparisons. */
2131 s390_compare_and_branch_condition_mask (rtx code
)
2133 const int CC0
= 1 << 3;
2134 const int CC1
= 1 << 2;
2135 const int CC2
= 1 << 1;
2137 switch (GET_CODE (code
))
2161 /* If INV is false, return assembler mnemonic string to implement
2162 a branch specified by CODE. If INV is true, return mnemonic
2163 for the corresponding inverted branch. */
2166 s390_branch_condition_mnemonic (rtx code
, int inv
)
2170 static const char *const mnemonic
[16] =
2172 NULL
, "o", "h", "nle",
2173 "l", "nhe", "lh", "ne",
2174 "e", "nlh", "he", "nl",
2175 "le", "nh", "no", NULL
2178 if (GET_CODE (XEXP (code
, 0)) == REG
2179 && REGNO (XEXP (code
, 0)) == CC_REGNUM
2180 && (XEXP (code
, 1) == const0_rtx
2181 || (GET_MODE (XEXP (code
, 0)) == CCRAWmode
2182 && CONST_INT_P (XEXP (code
, 1)))))
2183 mask
= s390_branch_condition_mask (code
);
2185 mask
= s390_compare_and_branch_condition_mask (code
);
2187 gcc_assert (mask
>= 0);
2192 gcc_assert (mask
>= 1 && mask
<= 14);
2194 return mnemonic
[mask
];
2197 /* Return the part of op which has a value different from def.
2198 The size of the part is determined by mode.
2199 Use this function only if you already know that op really
2200 contains such a part. */
2202 unsigned HOST_WIDE_INT
2203 s390_extract_part (rtx op
, machine_mode mode
, int def
)
2205 unsigned HOST_WIDE_INT value
= 0;
2206 int max_parts
= HOST_BITS_PER_WIDE_INT
/ GET_MODE_BITSIZE (mode
);
2207 int part_bits
= GET_MODE_BITSIZE (mode
);
2208 unsigned HOST_WIDE_INT part_mask
= (HOST_WIDE_INT_1U
<< part_bits
) - 1;
2211 for (i
= 0; i
< max_parts
; i
++)
2214 value
= UINTVAL (op
);
2216 value
>>= part_bits
;
2218 if ((value
& part_mask
) != (def
& part_mask
))
2219 return value
& part_mask
;
2225 /* If OP is an integer constant of mode MODE with exactly one
2226 part of mode PART_MODE unequal to DEF, return the number of that
2227 part. Otherwise, return -1. */
2230 s390_single_part (rtx op
,
2232 machine_mode part_mode
,
2235 unsigned HOST_WIDE_INT value
= 0;
2236 int n_parts
= GET_MODE_SIZE (mode
) / GET_MODE_SIZE (part_mode
);
2237 unsigned HOST_WIDE_INT part_mask
2238 = (HOST_WIDE_INT_1U
<< GET_MODE_BITSIZE (part_mode
)) - 1;
2241 if (GET_CODE (op
) != CONST_INT
)
2244 for (i
= 0; i
< n_parts
; i
++)
2247 value
= UINTVAL (op
);
2249 value
>>= GET_MODE_BITSIZE (part_mode
);
2251 if ((value
& part_mask
) != (def
& part_mask
))
2259 return part
== -1 ? -1 : n_parts
- 1 - part
;
2262 /* Return true if IN contains a contiguous bitfield in the lower SIZE
2263 bits and no other bits are set in (the lower SIZE bits of) IN.
2265 PSTART and PEND can be used to obtain the start and end
2266 position (inclusive) of the bitfield relative to 64
2267 bits. *PSTART / *PEND gives the position of the first/last bit
2268 of the bitfield counting from the highest order bit starting
2272 s390_contiguous_bitmask_nowrap_p (unsigned HOST_WIDE_INT in
, int size
,
2273 int *pstart
, int *pend
)
2277 int lowbit
= HOST_BITS_PER_WIDE_INT
- 1;
2278 int highbit
= HOST_BITS_PER_WIDE_INT
- size
;
2279 unsigned HOST_WIDE_INT bitmask
= HOST_WIDE_INT_1U
;
2281 gcc_assert (!!pstart
== !!pend
);
2282 for (start
= lowbit
; start
>= highbit
; bitmask
<<= 1, start
--)
2285 /* Look for the rightmost bit of a contiguous range of ones. */
2292 /* Look for the firt zero bit after the range of ones. */
2293 if (! (bitmask
& in
))
2297 /* We're one past the last one-bit. */
2301 /* No one bits found. */
2304 if (start
> highbit
)
2306 unsigned HOST_WIDE_INT mask
;
2308 /* Calculate a mask for all bits beyond the contiguous bits. */
2309 mask
= ((~HOST_WIDE_INT_0U
>> highbit
)
2310 & (~HOST_WIDE_INT_0U
<< (lowbit
- start
+ 1)));
2312 /* There are more bits set beyond the first range of one bits. */
2325 /* Same as s390_contiguous_bitmask_nowrap_p but also returns true
2326 if ~IN contains a contiguous bitfield. In that case, *END is <
2329 If WRAP_P is true, a bitmask that wraps around is also tested.
2330 When a wraparoud occurs *START is greater than *END (in
2331 non-null pointers), and the uppermost (64 - SIZE) bits are thus
2332 part of the range. If WRAP_P is false, no wraparound is
2336 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in
, bool wrap_p
,
2337 int size
, int *start
, int *end
)
2339 int bs
= HOST_BITS_PER_WIDE_INT
;
2342 gcc_assert (!!start
== !!end
);
2343 if ((in
& ((~HOST_WIDE_INT_0U
) >> (bs
- size
))) == 0)
2344 /* This cannot be expressed as a contiguous bitmask. Exit early because
2345 the second call of s390_contiguous_bitmask_nowrap_p would accept this as
2348 b
= s390_contiguous_bitmask_nowrap_p (in
, size
, start
, end
);
2353 b
= s390_contiguous_bitmask_nowrap_p (~in
, size
, start
, end
);
2359 gcc_assert (s
>= 1);
2360 *start
= ((e
+ 1) & (bs
- 1));
2361 *end
= ((s
- 1 + bs
) & (bs
- 1));
2367 /* Return true if OP contains the same contiguous bitfield in *all*
2368 its elements. START and END can be used to obtain the start and
2369 end position of the bitfield.
2371 START/STOP give the position of the first/last bit of the bitfield
2372 counting from the lowest order bit starting with zero. In order to
2373 use these values for S/390 instructions this has to be converted to
2374 "bits big endian" style. */
2377 s390_contiguous_bitmask_vector_p (rtx op
, int *start
, int *end
)
2379 unsigned HOST_WIDE_INT mask
;
2384 gcc_assert (!!start
== !!end
);
2385 if (!const_vec_duplicate_p (op
, &elt
)
2386 || !CONST_INT_P (elt
))
2389 size
= GET_MODE_UNIT_BITSIZE (GET_MODE (op
));
2391 /* We cannot deal with V1TI/V1TF. This would require a vgmq. */
2395 mask
= UINTVAL (elt
);
2397 b
= s390_contiguous_bitmask_p (mask
, true, size
, start
, end
);
2402 *start
-= (HOST_BITS_PER_WIDE_INT
- size
);
2403 *end
-= (HOST_BITS_PER_WIDE_INT
- size
);
2411 /* Return true if C consists only of byte chunks being either 0 or
2412 0xff. If MASK is !=NULL a byte mask is generated which is
2413 appropriate for the vector generate byte mask instruction. */
2416 s390_bytemask_vector_p (rtx op
, unsigned *mask
)
2419 unsigned tmp_mask
= 0;
2420 int nunit
, unit_size
;
2422 if (!VECTOR_MODE_P (GET_MODE (op
))
2423 || GET_CODE (op
) != CONST_VECTOR
2424 || !CONST_INT_P (XVECEXP (op
, 0, 0)))
2427 nunit
= GET_MODE_NUNITS (GET_MODE (op
));
2428 unit_size
= GET_MODE_UNIT_SIZE (GET_MODE (op
));
2430 for (i
= 0; i
< nunit
; i
++)
2432 unsigned HOST_WIDE_INT c
;
2435 if (!CONST_INT_P (XVECEXP (op
, 0, i
)))
2438 c
= UINTVAL (XVECEXP (op
, 0, i
));
2439 for (j
= 0; j
< unit_size
; j
++)
2441 if ((c
& 0xff) != 0 && (c
& 0xff) != 0xff)
2443 tmp_mask
|= (c
& 1) << ((nunit
- 1 - i
) * unit_size
+ j
);
2444 c
= c
>> BITS_PER_UNIT
;
2454 /* Check whether a rotate of ROTL followed by an AND of CONTIG is
2455 equivalent to a shift followed by the AND. In particular, CONTIG
2456 should not overlap the (rotated) bit 0/bit 63 gap. Negative values
2457 for ROTL indicate a rotate to the right. */
2460 s390_extzv_shift_ok (int bitsize
, int rotl
, unsigned HOST_WIDE_INT contig
)
2465 ok
= s390_contiguous_bitmask_nowrap_p (contig
, bitsize
, &start
, &end
);
2469 return (64 - end
>= rotl
);
2472 /* Translate "- rotate right" in BITSIZE mode to "rotate left" in
2474 rotl
= -rotl
+ (64 - bitsize
);
2475 return (start
>= rotl
);
2479 /* Check whether we can (and want to) split a double-word
2480 move in mode MODE from SRC to DST into two single-word
2481 moves, moving the subword FIRST_SUBWORD first. */
2484 s390_split_ok_p (rtx dst
, rtx src
, machine_mode mode
, int first_subword
)
2486 /* Floating point and vector registers cannot be split. */
2487 if (FP_REG_P (src
) || FP_REG_P (dst
) || VECTOR_REG_P (src
) || VECTOR_REG_P (dst
))
2490 /* Non-offsettable memory references cannot be split. */
2491 if ((GET_CODE (src
) == MEM
&& !offsettable_memref_p (src
))
2492 || (GET_CODE (dst
) == MEM
&& !offsettable_memref_p (dst
)))
2495 /* Moving the first subword must not clobber a register
2496 needed to move the second subword. */
2497 if (register_operand (dst
, mode
))
2499 rtx subreg
= operand_subword (dst
, first_subword
, 0, mode
);
2500 if (reg_overlap_mentioned_p (subreg
, src
))
2507 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
2508 and [MEM2, MEM2 + SIZE] do overlap and false
2512 s390_overlap_p (rtx mem1
, rtx mem2
, HOST_WIDE_INT size
)
2514 rtx addr1
, addr2
, addr_delta
;
2515 HOST_WIDE_INT delta
;
2517 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
2523 addr1
= XEXP (mem1
, 0);
2524 addr2
= XEXP (mem2
, 0);
2526 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
2528 /* This overlapping check is used by peepholes merging memory block operations.
2529 Overlapping operations would otherwise be recognized by the S/390 hardware
2530 and would fall back to a slower implementation. Allowing overlapping
2531 operations would lead to slow code but not to wrong code. Therefore we are
2532 somewhat optimistic if we cannot prove that the memory blocks are
2534 That's why we return false here although this may accept operations on
2535 overlapping memory areas. */
2536 if (!addr_delta
|| GET_CODE (addr_delta
) != CONST_INT
)
2539 delta
= INTVAL (addr_delta
);
2542 || (delta
> 0 && delta
< size
)
2543 || (delta
< 0 && -delta
< size
))
2549 /* Check whether the address of memory reference MEM2 equals exactly
2550 the address of memory reference MEM1 plus DELTA. Return true if
2551 we can prove this to be the case, false otherwise. */
2554 s390_offset_p (rtx mem1
, rtx mem2
, rtx delta
)
2556 rtx addr1
, addr2
, addr_delta
;
2558 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
2561 addr1
= XEXP (mem1
, 0);
2562 addr2
= XEXP (mem2
, 0);
2564 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
2565 if (!addr_delta
|| !rtx_equal_p (addr_delta
, delta
))
2571 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
2574 s390_expand_logical_operator (enum rtx_code code
, machine_mode mode
,
2577 machine_mode wmode
= mode
;
2578 rtx dst
= operands
[0];
2579 rtx src1
= operands
[1];
2580 rtx src2
= operands
[2];
2583 /* If we cannot handle the operation directly, use a temp register. */
2584 if (!s390_logical_operator_ok_p (operands
))
2585 dst
= gen_reg_rtx (mode
);
2587 /* QImode and HImode patterns make sense only if we have a destination
2588 in memory. Otherwise perform the operation in SImode. */
2589 if ((mode
== QImode
|| mode
== HImode
) && GET_CODE (dst
) != MEM
)
2592 /* Widen operands if required. */
2595 if (GET_CODE (dst
) == SUBREG
2596 && (tem
= simplify_subreg (wmode
, dst
, mode
, 0)) != 0)
2598 else if (REG_P (dst
))
2599 dst
= gen_rtx_SUBREG (wmode
, dst
, 0);
2601 dst
= gen_reg_rtx (wmode
);
2603 if (GET_CODE (src1
) == SUBREG
2604 && (tem
= simplify_subreg (wmode
, src1
, mode
, 0)) != 0)
2606 else if (GET_MODE (src1
) != VOIDmode
)
2607 src1
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src1
), 0);
2609 if (GET_CODE (src2
) == SUBREG
2610 && (tem
= simplify_subreg (wmode
, src2
, mode
, 0)) != 0)
2612 else if (GET_MODE (src2
) != VOIDmode
)
2613 src2
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src2
), 0);
2616 /* Emit the instruction. */
2617 op
= gen_rtx_SET (dst
, gen_rtx_fmt_ee (code
, wmode
, src1
, src2
));
2618 clob
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
2619 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clob
)));
2621 /* Fix up the destination if needed. */
2622 if (dst
!= operands
[0])
2623 emit_move_insn (operands
[0], gen_lowpart (mode
, dst
));
2626 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
2629 s390_logical_operator_ok_p (rtx
*operands
)
2631 /* If the destination operand is in memory, it needs to coincide
2632 with one of the source operands. After reload, it has to be
2633 the first source operand. */
2634 if (GET_CODE (operands
[0]) == MEM
)
2635 return rtx_equal_p (operands
[0], operands
[1])
2636 || (!reload_completed
&& rtx_equal_p (operands
[0], operands
[2]));
2641 /* Narrow logical operation CODE of memory operand MEMOP with immediate
2642 operand IMMOP to switch from SS to SI type instructions. */
2645 s390_narrow_logical_operator (enum rtx_code code
, rtx
*memop
, rtx
*immop
)
2647 int def
= code
== AND
? -1 : 0;
2651 gcc_assert (GET_CODE (*memop
) == MEM
);
2652 gcc_assert (!MEM_VOLATILE_P (*memop
));
2654 mask
= s390_extract_part (*immop
, QImode
, def
);
2655 part
= s390_single_part (*immop
, GET_MODE (*memop
), QImode
, def
);
2656 gcc_assert (part
>= 0);
2658 *memop
= adjust_address (*memop
, QImode
, part
);
2659 *immop
= gen_int_mode (mask
, QImode
);
2663 /* How to allocate a 'struct machine_function'. */
2665 static struct machine_function
*
2666 s390_init_machine_status (void)
2668 return ggc_cleared_alloc
<machine_function
> ();
2671 /* Map for smallest class containing reg regno. */
2673 const enum reg_class regclass_map
[FIRST_PSEUDO_REGISTER
] =
2674 { GENERAL_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, /* 0 */
2675 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, /* 4 */
2676 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, /* 8 */
2677 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, /* 12 */
2678 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
, /* 16 */
2679 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
, /* 20 */
2680 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
, /* 24 */
2681 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
, /* 28 */
2682 ADDR_REGS
, CC_REGS
, ADDR_REGS
, ADDR_REGS
, /* 32 */
2683 ACCESS_REGS
, ACCESS_REGS
, VEC_REGS
, VEC_REGS
, /* 36 */
2684 VEC_REGS
, VEC_REGS
, VEC_REGS
, VEC_REGS
, /* 40 */
2685 VEC_REGS
, VEC_REGS
, VEC_REGS
, VEC_REGS
, /* 44 */
2686 VEC_REGS
, VEC_REGS
, VEC_REGS
, VEC_REGS
, /* 48 */
2687 VEC_REGS
, VEC_REGS
/* 52 */
2690 /* Return attribute type of insn. */
2692 static enum attr_type
2693 s390_safe_attr_type (rtx_insn
*insn
)
2695 if (recog_memoized (insn
) >= 0)
2696 return get_attr_type (insn
);
2701 /* Return true if DISP is a valid short displacement. */
2704 s390_short_displacement (rtx disp
)
2706 /* No displacement is OK. */
2710 /* Without the long displacement facility we don't need to
2711 distingiush between long and short displacement. */
2712 if (!TARGET_LONG_DISPLACEMENT
)
2715 /* Integer displacement in range. */
2716 if (GET_CODE (disp
) == CONST_INT
)
2717 return INTVAL (disp
) >= 0 && INTVAL (disp
) < 4096;
2719 /* GOT offset is not OK, the GOT can be large. */
2720 if (GET_CODE (disp
) == CONST
2721 && GET_CODE (XEXP (disp
, 0)) == UNSPEC
2722 && (XINT (XEXP (disp
, 0), 1) == UNSPEC_GOT
2723 || XINT (XEXP (disp
, 0), 1) == UNSPEC_GOTNTPOFF
))
2726 /* All other symbolic constants are literal pool references,
2727 which are OK as the literal pool must be small. */
2728 if (GET_CODE (disp
) == CONST
)
2734 /* Decompose a RTL expression ADDR for a memory address into
2735 its components, returned in OUT.
2737 Returns false if ADDR is not a valid memory address, true
2738 otherwise. If OUT is NULL, don't return the components,
2739 but check for validity only.
2741 Note: Only addresses in canonical form are recognized.
2742 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
2743 canonical form so that they will be recognized. */
2746 s390_decompose_address (rtx addr
, struct s390_address
*out
)
2748 HOST_WIDE_INT offset
= 0;
2749 rtx base
= NULL_RTX
;
2750 rtx indx
= NULL_RTX
;
2751 rtx disp
= NULL_RTX
;
2753 bool pointer
= false;
2754 bool base_ptr
= false;
2755 bool indx_ptr
= false;
2756 bool literal_pool
= false;
2758 /* We may need to substitute the literal pool base register into the address
2759 below. However, at this point we do not know which register is going to
2760 be used as base, so we substitute the arg pointer register. This is going
2761 to be treated as holding a pointer below -- it shouldn't be used for any
2763 rtx fake_pool_base
= gen_rtx_REG (Pmode
, ARG_POINTER_REGNUM
);
2765 /* Decompose address into base + index + displacement. */
2767 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == UNSPEC
)
2770 else if (GET_CODE (addr
) == PLUS
)
2772 rtx op0
= XEXP (addr
, 0);
2773 rtx op1
= XEXP (addr
, 1);
2774 enum rtx_code code0
= GET_CODE (op0
);
2775 enum rtx_code code1
= GET_CODE (op1
);
2777 if (code0
== REG
|| code0
== UNSPEC
)
2779 if (code1
== REG
|| code1
== UNSPEC
)
2781 indx
= op0
; /* index + base */
2787 base
= op0
; /* base + displacement */
2792 else if (code0
== PLUS
)
2794 indx
= XEXP (op0
, 0); /* index + base + disp */
2795 base
= XEXP (op0
, 1);
2806 disp
= addr
; /* displacement */
2808 /* Extract integer part of displacement. */
2812 if (GET_CODE (disp
) == CONST_INT
)
2814 offset
= INTVAL (disp
);
2817 else if (GET_CODE (disp
) == CONST
2818 && GET_CODE (XEXP (disp
, 0)) == PLUS
2819 && GET_CODE (XEXP (XEXP (disp
, 0), 1)) == CONST_INT
)
2821 offset
= INTVAL (XEXP (XEXP (disp
, 0), 1));
2822 disp
= XEXP (XEXP (disp
, 0), 0);
2826 /* Strip off CONST here to avoid special case tests later. */
2827 if (disp
&& GET_CODE (disp
) == CONST
)
2828 disp
= XEXP (disp
, 0);
2830 /* We can convert literal pool addresses to
2831 displacements by basing them off the base register. */
2832 if (disp
&& GET_CODE (disp
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (disp
))
2837 base
= fake_pool_base
, literal_pool
= true;
2839 /* Mark up the displacement. */
2840 disp
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, disp
),
2841 UNSPEC_LTREL_OFFSET
);
2844 /* Validate base register. */
2847 if (GET_CODE (base
) == UNSPEC
)
2848 switch (XINT (base
, 1))
2852 disp
= gen_rtx_UNSPEC (Pmode
,
2853 gen_rtvec (1, XVECEXP (base
, 0, 0)),
2854 UNSPEC_LTREL_OFFSET
);
2858 base
= XVECEXP (base
, 0, 1);
2861 case UNSPEC_LTREL_BASE
:
2862 if (XVECLEN (base
, 0) == 1)
2863 base
= fake_pool_base
, literal_pool
= true;
2865 base
= XVECEXP (base
, 0, 1);
2872 if (!REG_P (base
) || GET_MODE (base
) != Pmode
)
2875 if (REGNO (base
) == STACK_POINTER_REGNUM
2876 || REGNO (base
) == FRAME_POINTER_REGNUM
2877 || ((reload_completed
|| reload_in_progress
)
2878 && frame_pointer_needed
2879 && REGNO (base
) == HARD_FRAME_POINTER_REGNUM
)
2880 || REGNO (base
) == ARG_POINTER_REGNUM
2882 && REGNO (base
) == PIC_OFFSET_TABLE_REGNUM
))
2883 pointer
= base_ptr
= true;
2885 if ((reload_completed
|| reload_in_progress
)
2886 && base
== cfun
->machine
->base_reg
)
2887 pointer
= base_ptr
= literal_pool
= true;
2890 /* Validate index register. */
2893 if (GET_CODE (indx
) == UNSPEC
)
2894 switch (XINT (indx
, 1))
2898 disp
= gen_rtx_UNSPEC (Pmode
,
2899 gen_rtvec (1, XVECEXP (indx
, 0, 0)),
2900 UNSPEC_LTREL_OFFSET
);
2904 indx
= XVECEXP (indx
, 0, 1);
2907 case UNSPEC_LTREL_BASE
:
2908 if (XVECLEN (indx
, 0) == 1)
2909 indx
= fake_pool_base
, literal_pool
= true;
2911 indx
= XVECEXP (indx
, 0, 1);
2918 if (!REG_P (indx
) || GET_MODE (indx
) != Pmode
)
2921 if (REGNO (indx
) == STACK_POINTER_REGNUM
2922 || REGNO (indx
) == FRAME_POINTER_REGNUM
2923 || ((reload_completed
|| reload_in_progress
)
2924 && frame_pointer_needed
2925 && REGNO (indx
) == HARD_FRAME_POINTER_REGNUM
)
2926 || REGNO (indx
) == ARG_POINTER_REGNUM
2928 && REGNO (indx
) == PIC_OFFSET_TABLE_REGNUM
))
2929 pointer
= indx_ptr
= true;
2931 if ((reload_completed
|| reload_in_progress
)
2932 && indx
== cfun
->machine
->base_reg
)
2933 pointer
= indx_ptr
= literal_pool
= true;
2936 /* Prefer to use pointer as base, not index. */
2937 if (base
&& indx
&& !base_ptr
2938 && (indx_ptr
|| (!REG_POINTER (base
) && REG_POINTER (indx
))))
2945 /* Validate displacement. */
2948 /* If virtual registers are involved, the displacement will change later
2949 anyway as the virtual registers get eliminated. This could make a
2950 valid displacement invalid, but it is more likely to make an invalid
2951 displacement valid, because we sometimes access the register save area
2952 via negative offsets to one of those registers.
2953 Thus we don't check the displacement for validity here. If after
2954 elimination the displacement turns out to be invalid after all,
2955 this is fixed up by reload in any case. */
2956 /* LRA maintains always displacements up to date and we need to
2957 know the displacement is right during all LRA not only at the
2958 final elimination. */
2960 || (base
!= arg_pointer_rtx
2961 && indx
!= arg_pointer_rtx
2962 && base
!= return_address_pointer_rtx
2963 && indx
!= return_address_pointer_rtx
2964 && base
!= frame_pointer_rtx
2965 && indx
!= frame_pointer_rtx
2966 && base
!= virtual_stack_vars_rtx
2967 && indx
!= virtual_stack_vars_rtx
))
2968 if (!DISP_IN_RANGE (offset
))
2973 /* All the special cases are pointers. */
2976 /* In the small-PIC case, the linker converts @GOT
2977 and @GOTNTPOFF offsets to possible displacements. */
2978 if (GET_CODE (disp
) == UNSPEC
2979 && (XINT (disp
, 1) == UNSPEC_GOT
2980 || XINT (disp
, 1) == UNSPEC_GOTNTPOFF
)
2986 /* Accept pool label offsets. */
2987 else if (GET_CODE (disp
) == UNSPEC
2988 && XINT (disp
, 1) == UNSPEC_POOL_OFFSET
)
2991 /* Accept literal pool references. */
2992 else if (GET_CODE (disp
) == UNSPEC
2993 && XINT (disp
, 1) == UNSPEC_LTREL_OFFSET
)
2995 /* In case CSE pulled a non literal pool reference out of
2996 the pool we have to reject the address. This is
2997 especially important when loading the GOT pointer on non
2998 zarch CPUs. In this case the literal pool contains an lt
2999 relative offset to the _GLOBAL_OFFSET_TABLE_ label which
3000 will most likely exceed the displacement. */
3001 if (GET_CODE (XVECEXP (disp
, 0, 0)) != SYMBOL_REF
3002 || !CONSTANT_POOL_ADDRESS_P (XVECEXP (disp
, 0, 0)))
3005 orig_disp
= gen_rtx_CONST (Pmode
, disp
);
3008 /* If we have an offset, make sure it does not
3009 exceed the size of the constant pool entry. */
3010 rtx sym
= XVECEXP (disp
, 0, 0);
3011 if (offset
>= GET_MODE_SIZE (get_pool_mode (sym
)))
3014 orig_disp
= plus_constant (Pmode
, orig_disp
, offset
);
3029 out
->disp
= orig_disp
;
3030 out
->pointer
= pointer
;
3031 out
->literal_pool
= literal_pool
;
3037 /* Decompose a RTL expression OP for an address style operand into its
3038 components, and return the base register in BASE and the offset in
3039 OFFSET. While OP looks like an address it is never supposed to be
3042 Return true if OP is a valid address operand, false if not. */
3045 s390_decompose_addrstyle_without_index (rtx op
, rtx
*base
,
3046 HOST_WIDE_INT
*offset
)
3050 /* We can have an integer constant, an address register,
3051 or a sum of the two. */
3052 if (CONST_SCALAR_INT_P (op
))
3057 if (op
&& GET_CODE (op
) == PLUS
&& CONST_SCALAR_INT_P (XEXP (op
, 1)))
3062 while (op
&& GET_CODE (op
) == SUBREG
)
3063 op
= SUBREG_REG (op
);
3065 if (op
&& GET_CODE (op
) != REG
)
3070 if (off
== NULL_RTX
)
3072 else if (CONST_INT_P (off
))
3073 *offset
= INTVAL (off
);
3074 else if (CONST_WIDE_INT_P (off
))
3075 /* The offset will anyway be cut down to 12 bits so take just
3076 the lowest order chunk of the wide int. */
3077 *offset
= CONST_WIDE_INT_ELT (off
, 0);
3088 /* Return true if CODE is a valid address without index. */
3091 s390_legitimate_address_without_index_p (rtx op
)
3093 struct s390_address addr
;
3095 if (!s390_decompose_address (XEXP (op
, 0), &addr
))
3104 /* Return TRUE if ADDR is an operand valid for a load/store relative
3105 instruction. Be aware that the alignment of the operand needs to
3106 be checked separately.
3107 Valid addresses are single references or a sum of a reference and a
3108 constant integer. Return these parts in SYMREF and ADDEND. You can
3109 pass NULL in REF and/or ADDEND if you are not interested in these
3110 values. Literal pool references are *not* considered symbol
3114 s390_loadrelative_operand_p (rtx addr
, rtx
*symref
, HOST_WIDE_INT
*addend
)
3116 HOST_WIDE_INT tmpaddend
= 0;
3118 if (GET_CODE (addr
) == CONST
)
3119 addr
= XEXP (addr
, 0);
3121 if (GET_CODE (addr
) == PLUS
)
3123 if (!CONST_INT_P (XEXP (addr
, 1)))
3126 tmpaddend
= INTVAL (XEXP (addr
, 1));
3127 addr
= XEXP (addr
, 0);
3130 if ((GET_CODE (addr
) == SYMBOL_REF
&& !CONSTANT_POOL_ADDRESS_P (addr
))
3131 || (GET_CODE (addr
) == UNSPEC
3132 && (XINT (addr
, 1) == UNSPEC_GOTENT
3133 || (TARGET_CPU_ZARCH
&& XINT (addr
, 1) == UNSPEC_PLT
))))
3138 *addend
= tmpaddend
;
3145 /* Return true if the address in OP is valid for constraint letter C
3146 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
3147 pool MEMs should be accepted. Only the Q, R, S, T constraint
3148 letters are allowed for C. */
3151 s390_check_qrst_address (char c
, rtx op
, bool lit_pool_ok
)
3153 struct s390_address addr
;
3154 bool decomposed
= false;
3156 if (!address_operand (op
, GET_MODE (op
)))
3159 /* This check makes sure that no symbolic address (except literal
3160 pool references) are accepted by the R or T constraints. */
3161 if (s390_loadrelative_operand_p (op
, NULL
, NULL
))
3164 /* Ensure literal pool references are only accepted if LIT_POOL_OK. */
3167 if (!s390_decompose_address (op
, &addr
))
3169 if (addr
.literal_pool
)
3174 /* With reload, we sometimes get intermediate address forms that are
3175 actually invalid as-is, but we need to accept them in the most
3176 generic cases below ('R' or 'T'), since reload will in fact fix
3177 them up. LRA behaves differently here; we never see such forms,
3178 but on the other hand, we need to strictly reject every invalid
3179 address form. Perform this check right up front. */
3180 if (lra_in_progress
)
3182 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
3189 case 'Q': /* no index short displacement */
3190 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
3194 if (!s390_short_displacement (addr
.disp
))
3198 case 'R': /* with index short displacement */
3199 if (TARGET_LONG_DISPLACEMENT
)
3201 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
3203 if (!s390_short_displacement (addr
.disp
))
3206 /* Any invalid address here will be fixed up by reload,
3207 so accept it for the most generic constraint. */
3210 case 'S': /* no index long displacement */
3211 if (!decomposed
&& !s390_decompose_address (op
, &addr
))
3217 case 'T': /* with index long displacement */
3218 /* Any invalid address here will be fixed up by reload,
3219 so accept it for the most generic constraint. */
3229 /* Evaluates constraint strings described by the regular expression
3230 ([A|B|Z](Q|R|S|T))|Y and returns 1 if OP is a valid operand for
3231 the constraint given in STR, or 0 else. */
3234 s390_mem_constraint (const char *str
, rtx op
)
3241 /* Check for offsettable variants of memory constraints. */
3242 if (!MEM_P (op
) || MEM_VOLATILE_P (op
))
3244 if ((reload_completed
|| reload_in_progress
)
3245 ? !offsettable_memref_p (op
) : !offsettable_nonstrict_memref_p (op
))
3247 return s390_check_qrst_address (str
[1], XEXP (op
, 0), true);
3249 /* Check for non-literal-pool variants of memory constraints. */
3252 return s390_check_qrst_address (str
[1], XEXP (op
, 0), false);
3257 if (GET_CODE (op
) != MEM
)
3259 return s390_check_qrst_address (c
, XEXP (op
, 0), true);
3261 /* Simply check for the basic form of a shift count. Reload will
3262 take care of making sure we have a proper base register. */
3263 if (!s390_decompose_addrstyle_without_index (op
, NULL
, NULL
))
3267 return s390_check_qrst_address (str
[1], op
, true);
3275 /* Evaluates constraint strings starting with letter O. Input
3276 parameter C is the second letter following the "O" in the constraint
3277 string. Returns 1 if VALUE meets the respective constraint and 0
3281 s390_O_constraint_str (const char c
, HOST_WIDE_INT value
)
3289 return trunc_int_for_mode (value
, SImode
) == value
;
3293 || s390_single_part (GEN_INT (value
), DImode
, SImode
, 0) == 1;
3296 return s390_single_part (GEN_INT (value
- 1), DImode
, SImode
, -1) == 1;
3304 /* Evaluates constraint strings starting with letter N. Parameter STR
3305 contains the letters following letter "N" in the constraint string.
3306 Returns true if VALUE matches the constraint. */
3309 s390_N_constraint_str (const char *str
, HOST_WIDE_INT value
)
3311 machine_mode mode
, part_mode
;
3313 int part
, part_goal
;
3319 part_goal
= str
[0] - '0';
3363 if (GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (part_mode
))
3366 part
= s390_single_part (GEN_INT (value
), mode
, part_mode
, def
);
3369 if (part_goal
!= -1 && part_goal
!= part
)
3376 /* Returns true if the input parameter VALUE is a float zero. */
3379 s390_float_const_zero_p (rtx value
)
3381 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
3382 && value
== CONST0_RTX (GET_MODE (value
)));
3385 /* Implement TARGET_REGISTER_MOVE_COST. */
3388 s390_register_move_cost (machine_mode mode
,
3389 reg_class_t from
, reg_class_t to
)
3391 /* On s390, copy between fprs and gprs is expensive. */
3393 /* It becomes somewhat faster having ldgr/lgdr. */
3394 if (TARGET_Z10
&& GET_MODE_SIZE (mode
) == 8)
3396 /* ldgr is single cycle. */
3397 if (reg_classes_intersect_p (from
, GENERAL_REGS
)
3398 && reg_classes_intersect_p (to
, FP_REGS
))
3400 /* lgdr needs 3 cycles. */
3401 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
3402 && reg_classes_intersect_p (from
, FP_REGS
))
3406 /* Otherwise copying is done via memory. */
3407 if ((reg_classes_intersect_p (from
, GENERAL_REGS
)
3408 && reg_classes_intersect_p (to
, FP_REGS
))
3409 || (reg_classes_intersect_p (from
, FP_REGS
)
3410 && reg_classes_intersect_p (to
, GENERAL_REGS
)))
3416 /* Implement TARGET_MEMORY_MOVE_COST. */
3419 s390_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
3420 reg_class_t rclass ATTRIBUTE_UNUSED
,
3421 bool in ATTRIBUTE_UNUSED
)
3426 /* Compute a (partial) cost for rtx X. Return true if the complete
3427 cost has been computed, and false if subexpressions should be
3428 scanned. In either case, *TOTAL contains the cost result. The
3429 initial value of *TOTAL is the default value computed by
3430 rtx_cost. It may be left unmodified. OUTER_CODE contains the
3431 code of the superexpression of x. */
3434 s390_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
3435 int opno ATTRIBUTE_UNUSED
,
3436 int *total
, bool speed ATTRIBUTE_UNUSED
)
3438 int code
= GET_CODE (x
);
3446 case CONST_WIDE_INT
:
3453 /* Without this a conditional move instruction would be
3454 accounted as 3 * COSTS_N_INSNS (set, if_then_else,
3455 comparison operator). That's a bit pessimistic. */
3457 if (!TARGET_Z196
|| GET_CODE (SET_SRC (x
)) != IF_THEN_ELSE
)
3460 rtx cond
= XEXP (SET_SRC (x
), 0);
3462 if (!CC_REG_P (XEXP (cond
, 0)) || !CONST_INT_P (XEXP (cond
, 1)))
3465 /* It is going to be a load/store on condition. Make it
3466 slightly more expensive than a normal load. */
3467 *total
= COSTS_N_INSNS (1) + 1;
3469 rtx dst
= SET_DEST (x
);
3470 rtx then
= XEXP (SET_SRC (x
), 1);
3471 rtx els
= XEXP (SET_SRC (x
), 2);
3473 /* It is a real IF-THEN-ELSE. An additional move will be
3474 needed to implement that. */
3475 if (reload_completed
3476 && !rtx_equal_p (dst
, then
)
3477 && !rtx_equal_p (dst
, els
))
3478 *total
+= COSTS_N_INSNS (1) / 2;
3480 /* A minor penalty for constants we cannot directly handle. */
3481 if ((CONST_INT_P (then
) || CONST_INT_P (els
))
3482 && (!TARGET_Z13
|| MEM_P (dst
)
3483 || (CONST_INT_P (then
) && !satisfies_constraint_K (then
))
3484 || (CONST_INT_P (els
) && !satisfies_constraint_K (els
))))
3485 *total
+= COSTS_N_INSNS (1) / 2;
3487 /* A store on condition can only handle register src operands. */
3488 if (MEM_P (dst
) && (!REG_P (then
) || !REG_P (els
)))
3489 *total
+= COSTS_N_INSNS (1) / 2;
3495 if (GET_CODE (XEXP (x
, 0)) == AND
3496 && GET_CODE (XEXP (x
, 1)) == ASHIFT
3497 && REG_P (XEXP (XEXP (x
, 0), 0))
3498 && REG_P (XEXP (XEXP (x
, 1), 0))
3499 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
3500 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
3501 && (UINTVAL (XEXP (XEXP (x
, 0), 1)) ==
3502 (HOST_WIDE_INT_1U
<< UINTVAL (XEXP (XEXP (x
, 1), 1))) - 1))
3504 *total
= COSTS_N_INSNS (2);
3508 /* ~AND on a 128 bit mode. This can be done using a vector
3511 && GET_CODE (XEXP (x
, 0)) == NOT
3512 && GET_CODE (XEXP (x
, 1)) == NOT
3513 && REG_P (XEXP (XEXP (x
, 0), 0))
3514 && REG_P (XEXP (XEXP (x
, 1), 0))
3515 && GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x
, 0), 0))) == 16
3516 && s390_hard_regno_mode_ok (VR0_REGNUM
,
3517 GET_MODE (XEXP (XEXP (x
, 0), 0))))
3519 *total
= COSTS_N_INSNS (1);
3532 *total
= COSTS_N_INSNS (1);
3537 *total
= COSTS_N_INSNS (1);
3545 rtx left
= XEXP (x
, 0);
3546 rtx right
= XEXP (x
, 1);
3547 if (GET_CODE (right
) == CONST_INT
3548 && CONST_OK_FOR_K (INTVAL (right
)))
3549 *total
= s390_cost
->mhi
;
3550 else if (GET_CODE (left
) == SIGN_EXTEND
)
3551 *total
= s390_cost
->mh
;
3553 *total
= s390_cost
->ms
; /* msr, ms, msy */
3558 rtx left
= XEXP (x
, 0);
3559 rtx right
= XEXP (x
, 1);
3562 if (GET_CODE (right
) == CONST_INT
3563 && CONST_OK_FOR_K (INTVAL (right
)))
3564 *total
= s390_cost
->mghi
;
3565 else if (GET_CODE (left
) == SIGN_EXTEND
)
3566 *total
= s390_cost
->msgf
;
3568 *total
= s390_cost
->msg
; /* msgr, msg */
3570 else /* TARGET_31BIT */
3572 if (GET_CODE (left
) == SIGN_EXTEND
3573 && GET_CODE (right
) == SIGN_EXTEND
)
3574 /* mulsidi case: mr, m */
3575 *total
= s390_cost
->m
;
3576 else if (GET_CODE (left
) == ZERO_EXTEND
3577 && GET_CODE (right
) == ZERO_EXTEND
3578 && TARGET_CPU_ZARCH
)
3579 /* umulsidi case: ml, mlr */
3580 *total
= s390_cost
->ml
;
3582 /* Complex calculation is required. */
3583 *total
= COSTS_N_INSNS (40);
3589 *total
= s390_cost
->mult_df
;
3592 *total
= s390_cost
->mxbr
;
3603 *total
= s390_cost
->madbr
;
3606 *total
= s390_cost
->maebr
;
3611 /* Negate in the third argument is free: FMSUB. */
3612 if (GET_CODE (XEXP (x
, 2)) == NEG
)
3614 *total
+= (rtx_cost (XEXP (x
, 0), mode
, FMA
, 0, speed
)
3615 + rtx_cost (XEXP (x
, 1), mode
, FMA
, 1, speed
)
3616 + rtx_cost (XEXP (XEXP (x
, 2), 0), mode
, FMA
, 2, speed
));
3623 if (mode
== TImode
) /* 128 bit division */
3624 *total
= s390_cost
->dlgr
;
3625 else if (mode
== DImode
)
3627 rtx right
= XEXP (x
, 1);
3628 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
3629 *total
= s390_cost
->dlr
;
3630 else /* 64 by 64 bit division */
3631 *total
= s390_cost
->dlgr
;
3633 else if (mode
== SImode
) /* 32 bit division */
3634 *total
= s390_cost
->dlr
;
3641 rtx right
= XEXP (x
, 1);
3642 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
3644 *total
= s390_cost
->dsgfr
;
3646 *total
= s390_cost
->dr
;
3647 else /* 64 by 64 bit division */
3648 *total
= s390_cost
->dsgr
;
3650 else if (mode
== SImode
) /* 32 bit division */
3651 *total
= s390_cost
->dlr
;
3652 else if (mode
== SFmode
)
3654 *total
= s390_cost
->debr
;
3656 else if (mode
== DFmode
)
3658 *total
= s390_cost
->ddbr
;
3660 else if (mode
== TFmode
)
3662 *total
= s390_cost
->dxbr
;
3668 *total
= s390_cost
->sqebr
;
3669 else if (mode
== DFmode
)
3670 *total
= s390_cost
->sqdbr
;
3672 *total
= s390_cost
->sqxbr
;
3677 if (outer_code
== MULT
|| outer_code
== DIV
|| outer_code
== MOD
3678 || outer_code
== PLUS
|| outer_code
== MINUS
3679 || outer_code
== COMPARE
)
3684 *total
= COSTS_N_INSNS (1);
3685 if (GET_CODE (XEXP (x
, 0)) == AND
3686 && GET_CODE (XEXP (x
, 1)) == CONST_INT
3687 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
3689 rtx op0
= XEXP (XEXP (x
, 0), 0);
3690 rtx op1
= XEXP (XEXP (x
, 0), 1);
3691 rtx op2
= XEXP (x
, 1);
3693 if (memory_operand (op0
, GET_MODE (op0
))
3694 && s390_tm_ccmode (op1
, op2
, 0) != VOIDmode
)
3696 if (register_operand (op0
, GET_MODE (op0
))
3697 && s390_tm_ccmode (op1
, op2
, 1) != VOIDmode
)
3707 /* Return the cost of an address rtx ADDR. */
3710 s390_address_cost (rtx addr
, machine_mode mode ATTRIBUTE_UNUSED
,
3711 addr_space_t as ATTRIBUTE_UNUSED
,
3712 bool speed ATTRIBUTE_UNUSED
)
3714 struct s390_address ad
;
3715 if (!s390_decompose_address (addr
, &ad
))
3718 return ad
.indx
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
3721 /* Implement targetm.vectorize.builtin_vectorization_cost. */
3723 s390_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost
,
3725 int misalign ATTRIBUTE_UNUSED
)
3727 switch (type_of_cost
)
3735 case vector_gather_load
:
3736 case vector_scatter_store
:
3739 case cond_branch_not_taken
:
3741 case vec_promote_demote
:
3742 case unaligned_load
:
3743 case unaligned_store
:
3746 case cond_branch_taken
:
3750 return TYPE_VECTOR_SUBPARTS (vectype
) - 1;
3757 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
3758 otherwise return 0. */
3761 tls_symbolic_operand (rtx op
)
3763 if (GET_CODE (op
) != SYMBOL_REF
)
3765 return SYMBOL_REF_TLS_MODEL (op
);
3768 /* Split DImode access register reference REG (on 64-bit) into its constituent
3769 low and high parts, and store them into LO and HI. Note that gen_lowpart/
3770 gen_highpart cannot be used as they assume all registers are word-sized,
3771 while our access registers have only half that size. */
3774 s390_split_access_reg (rtx reg
, rtx
*lo
, rtx
*hi
)
3776 gcc_assert (TARGET_64BIT
);
3777 gcc_assert (ACCESS_REG_P (reg
));
3778 gcc_assert (GET_MODE (reg
) == DImode
);
3779 gcc_assert (!(REGNO (reg
) & 1));
3781 *lo
= gen_rtx_REG (SImode
, REGNO (reg
) + 1);
3782 *hi
= gen_rtx_REG (SImode
, REGNO (reg
));
3785 /* Return true if OP contains a symbol reference */
3788 symbolic_reference_mentioned_p (rtx op
)
3793 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
3796 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
3797 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
3803 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
3804 if (symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
3808 else if (fmt
[i
] == 'e' && symbolic_reference_mentioned_p (XEXP (op
, i
)))
3815 /* Return true if OP contains a reference to a thread-local symbol. */
3818 tls_symbolic_reference_mentioned_p (rtx op
)
3823 if (GET_CODE (op
) == SYMBOL_REF
)
3824 return tls_symbolic_operand (op
);
3826 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
3827 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
3833 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
3834 if (tls_symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
3838 else if (fmt
[i
] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op
, i
)))
3846 /* Return true if OP is a legitimate general operand when
3847 generating PIC code. It is given that flag_pic is on
3848 and that OP satisfies CONSTANT_P. */
3851 legitimate_pic_operand_p (rtx op
)
3853 /* Accept all non-symbolic constants. */
3854 if (!SYMBOLIC_CONST (op
))
3857 /* Reject everything else; must be handled
3858 via emit_symbolic_move. */
3862 /* Returns true if the constant value OP is a legitimate general operand.
3863 It is given that OP satisfies CONSTANT_P. */
3866 s390_legitimate_constant_p (machine_mode mode
, rtx op
)
3868 if (TARGET_VX
&& VECTOR_MODE_P (mode
) && GET_CODE (op
) == CONST_VECTOR
)
3870 if (GET_MODE_SIZE (mode
) != 16)
3873 if (!satisfies_constraint_j00 (op
)
3874 && !satisfies_constraint_jm1 (op
)
3875 && !satisfies_constraint_jKK (op
)
3876 && !satisfies_constraint_jxx (op
)
3877 && !satisfies_constraint_jyy (op
))
3881 /* Accept all non-symbolic constants. */
3882 if (!SYMBOLIC_CONST (op
))
3885 /* Accept immediate LARL operands. */
3886 if (TARGET_CPU_ZARCH
&& larl_operand (op
, mode
))
3889 /* Thread-local symbols are never legal constants. This is
3890 so that emit_call knows that computing such addresses
3891 might require a function call. */
3892 if (TLS_SYMBOLIC_CONST (op
))
3895 /* In the PIC case, symbolic constants must *not* be
3896 forced into the literal pool. We accept them here,
3897 so that they will be handled by emit_symbolic_move. */
3901 /* All remaining non-PIC symbolic constants are
3902 forced into the literal pool. */
3906 /* Determine if it's legal to put X into the constant pool. This
3907 is not possible if X contains the address of a symbol that is
3908 not constant (TLS) or not known at final link time (PIC). */
3911 s390_cannot_force_const_mem (machine_mode mode
, rtx x
)
3913 switch (GET_CODE (x
))
3917 case CONST_WIDE_INT
:
3919 /* Accept all non-symbolic constants. */
3923 /* Labels are OK iff we are non-PIC. */
3924 return flag_pic
!= 0;
3927 /* 'Naked' TLS symbol references are never OK,
3928 non-TLS symbols are OK iff we are non-PIC. */
3929 if (tls_symbolic_operand (x
))
3932 return flag_pic
!= 0;
3935 return s390_cannot_force_const_mem (mode
, XEXP (x
, 0));
3938 return s390_cannot_force_const_mem (mode
, XEXP (x
, 0))
3939 || s390_cannot_force_const_mem (mode
, XEXP (x
, 1));
3942 switch (XINT (x
, 1))
3944 /* Only lt-relative or GOT-relative UNSPECs are OK. */
3945 case UNSPEC_LTREL_OFFSET
:
3953 case UNSPEC_GOTNTPOFF
:
3954 case UNSPEC_INDNTPOFF
:
3957 /* If the literal pool shares the code section, be put
3958 execute template placeholders into the pool as well. */
3960 return TARGET_CPU_ZARCH
;
3972 /* Returns true if the constant value OP is a legitimate general
3973 operand during and after reload. The difference to
3974 legitimate_constant_p is that this function will not accept
3975 a constant that would need to be forced to the literal pool
3976 before it can be used as operand.
3977 This function accepts all constants which can be loaded directly
3981 legitimate_reload_constant_p (rtx op
)
3983 /* Accept la(y) operands. */
3984 if (GET_CODE (op
) == CONST_INT
3985 && DISP_IN_RANGE (INTVAL (op
)))
3988 /* Accept l(g)hi/l(g)fi operands. */
3989 if (GET_CODE (op
) == CONST_INT
3990 && (CONST_OK_FOR_K (INTVAL (op
)) || CONST_OK_FOR_Os (INTVAL (op
))))
3993 /* Accept lliXX operands. */
3995 && GET_CODE (op
) == CONST_INT
3996 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
3997 && s390_single_part (op
, word_mode
, HImode
, 0) >= 0)
4001 && GET_CODE (op
) == CONST_INT
4002 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
4003 && s390_single_part (op
, word_mode
, SImode
, 0) >= 0)
4006 /* Accept larl operands. */
4007 if (TARGET_CPU_ZARCH
4008 && larl_operand (op
, VOIDmode
))
4011 /* Accept floating-point zero operands that fit into a single GPR. */
4012 if (GET_CODE (op
) == CONST_DOUBLE
4013 && s390_float_const_zero_p (op
)
4014 && GET_MODE_SIZE (GET_MODE (op
)) <= UNITS_PER_WORD
)
4017 /* Accept double-word operands that can be split. */
4018 if (GET_CODE (op
) == CONST_WIDE_INT
4019 || (GET_CODE (op
) == CONST_INT
4020 && trunc_int_for_mode (INTVAL (op
), word_mode
) != INTVAL (op
)))
4022 machine_mode dword_mode
= word_mode
== SImode
? DImode
: TImode
;
4023 rtx hi
= operand_subword (op
, 0, 0, dword_mode
);
4024 rtx lo
= operand_subword (op
, 1, 0, dword_mode
);
4025 return legitimate_reload_constant_p (hi
)
4026 && legitimate_reload_constant_p (lo
);
4029 /* Everything else cannot be handled without reload. */
4033 /* Returns true if the constant value OP is a legitimate fp operand
4034 during and after reload.
4035 This function accepts all constants which can be loaded directly
4039 legitimate_reload_fp_constant_p (rtx op
)
4041 /* Accept floating-point zero operands if the load zero instruction
4042 can be used. Prior to z196 the load fp zero instruction caused a
4043 performance penalty if the result is used as BFP number. */
4045 && GET_CODE (op
) == CONST_DOUBLE
4046 && s390_float_const_zero_p (op
))
4052 /* Returns true if the constant value OP is a legitimate vector operand
4053 during and after reload.
4054 This function accepts all constants which can be loaded directly
4058 legitimate_reload_vector_constant_p (rtx op
)
4060 if (TARGET_VX
&& GET_MODE_SIZE (GET_MODE (op
)) == 16
4061 && (satisfies_constraint_j00 (op
)
4062 || satisfies_constraint_jm1 (op
)
4063 || satisfies_constraint_jKK (op
)
4064 || satisfies_constraint_jxx (op
)
4065 || satisfies_constraint_jyy (op
)))
4071 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
4072 return the class of reg to actually use. */
4075 s390_preferred_reload_class (rtx op
, reg_class_t rclass
)
4077 switch (GET_CODE (op
))
4079 /* Constants we cannot reload into general registers
4080 must be forced into the literal pool. */
4084 case CONST_WIDE_INT
:
4085 if (reg_class_subset_p (GENERAL_REGS
, rclass
)
4086 && legitimate_reload_constant_p (op
))
4087 return GENERAL_REGS
;
4088 else if (reg_class_subset_p (ADDR_REGS
, rclass
)
4089 && legitimate_reload_constant_p (op
))
4091 else if (reg_class_subset_p (FP_REGS
, rclass
)
4092 && legitimate_reload_fp_constant_p (op
))
4094 else if (reg_class_subset_p (VEC_REGS
, rclass
)
4095 && legitimate_reload_vector_constant_p (op
))
4100 /* If a symbolic constant or a PLUS is reloaded,
4101 it is most likely being used as an address, so
4102 prefer ADDR_REGS. If 'class' is not a superset
4103 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
4105 /* Symrefs cannot be pushed into the literal pool with -fPIC
4106 so we *MUST NOT* return NO_REGS for these cases
4107 (s390_cannot_force_const_mem will return true).
4109 On the other hand we MUST return NO_REGS for symrefs with
4110 invalid addend which might have been pushed to the literal
4111 pool (no -fPIC). Usually we would expect them to be
4112 handled via secondary reload but this does not happen if
4113 they are used as literal pool slot replacement in reload
4114 inheritance (see emit_input_reload_insns). */
4115 if (TARGET_CPU_ZARCH
4116 && GET_CODE (XEXP (op
, 0)) == PLUS
4117 && GET_CODE (XEXP (XEXP(op
, 0), 0)) == SYMBOL_REF
4118 && GET_CODE (XEXP (XEXP(op
, 0), 1)) == CONST_INT
)
4120 if (flag_pic
&& reg_class_subset_p (ADDR_REGS
, rclass
))
4128 if (!legitimate_reload_constant_p (op
))
4132 /* load address will be used. */
4133 if (reg_class_subset_p (ADDR_REGS
, rclass
))
4145 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
4146 multiple of ALIGNMENT and the SYMBOL_REF being naturally
4150 s390_check_symref_alignment (rtx addr
, HOST_WIDE_INT alignment
)
4152 HOST_WIDE_INT addend
;
4155 /* The "required alignment" might be 0 (e.g. for certain structs
4156 accessed via BLKmode). Early abort in this case, as well as when
4157 an alignment > 8 is required. */
4158 if (alignment
< 2 || alignment
> 8)
4161 if (!s390_loadrelative_operand_p (addr
, &symref
, &addend
))
4164 if (addend
& (alignment
- 1))
4167 if (GET_CODE (symref
) == SYMBOL_REF
)
4169 /* We have load-relative instructions for 2-byte, 4-byte, and
4170 8-byte alignment so allow only these. */
4173 case 8: return !SYMBOL_FLAG_NOTALIGN8_P (symref
);
4174 case 4: return !SYMBOL_FLAG_NOTALIGN4_P (symref
);
4175 case 2: return !SYMBOL_FLAG_NOTALIGN2_P (symref
);
4176 default: return false;
4180 if (GET_CODE (symref
) == UNSPEC
4181 && alignment
<= UNITS_PER_LONG
)
4187 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
4188 operand SCRATCH is used to reload the even part of the address and
4192 s390_reload_larl_operand (rtx reg
, rtx addr
, rtx scratch
)
4194 HOST_WIDE_INT addend
;
4197 if (!s390_loadrelative_operand_p (addr
, &symref
, &addend
))
4201 /* Easy case. The addend is even so larl will do fine. */
4202 emit_move_insn (reg
, addr
);
4205 /* We can leave the scratch register untouched if the target
4206 register is a valid base register. */
4207 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
4208 && REGNO_REG_CLASS (REGNO (reg
)) == ADDR_REGS
)
4211 gcc_assert (REGNO (scratch
) < FIRST_PSEUDO_REGISTER
);
4212 gcc_assert (REGNO_REG_CLASS (REGNO (scratch
)) == ADDR_REGS
);
4215 emit_move_insn (scratch
,
4216 gen_rtx_CONST (Pmode
,
4217 gen_rtx_PLUS (Pmode
, symref
,
4218 GEN_INT (addend
- 1))));
4220 emit_move_insn (scratch
, symref
);
4222 /* Increment the address using la in order to avoid clobbering cc. */
4223 s390_load_address (reg
, gen_rtx_PLUS (Pmode
, scratch
, const1_rtx
));
4227 /* Generate what is necessary to move between REG and MEM using
4228 SCRATCH. The direction is given by TOMEM. */
4231 s390_reload_symref_address (rtx reg
, rtx mem
, rtx scratch
, bool tomem
)
4233 /* Reload might have pulled a constant out of the literal pool.
4234 Force it back in. */
4235 if (CONST_INT_P (mem
) || GET_CODE (mem
) == CONST_DOUBLE
4236 || GET_CODE (mem
) == CONST_WIDE_INT
4237 || GET_CODE (mem
) == CONST_VECTOR
4238 || GET_CODE (mem
) == CONST
)
4239 mem
= force_const_mem (GET_MODE (reg
), mem
);
4241 gcc_assert (MEM_P (mem
));
4243 /* For a load from memory we can leave the scratch register
4244 untouched if the target register is a valid base register. */
4246 && REGNO (reg
) < FIRST_PSEUDO_REGISTER
4247 && REGNO_REG_CLASS (REGNO (reg
)) == ADDR_REGS
4248 && GET_MODE (reg
) == GET_MODE (scratch
))
4251 /* Load address into scratch register. Since we can't have a
4252 secondary reload for a secondary reload we have to cover the case
4253 where larl would need a secondary reload here as well. */
4254 s390_reload_larl_operand (scratch
, XEXP (mem
, 0), scratch
);
4256 /* Now we can use a standard load/store to do the move. */
4258 emit_move_insn (replace_equiv_address (mem
, scratch
), reg
);
4260 emit_move_insn (reg
, replace_equiv_address (mem
, scratch
));
4263 /* Inform reload about cases where moving X with a mode MODE to a register in
4264 RCLASS requires an extra scratch or immediate register. Return the class
4265 needed for the immediate register. */
4268 s390_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
4269 machine_mode mode
, secondary_reload_info
*sri
)
4271 enum reg_class rclass
= (enum reg_class
) rclass_i
;
4273 /* Intermediate register needed. */
4274 if (reg_classes_intersect_p (CC_REGS
, rclass
))
4275 return GENERAL_REGS
;
4279 /* The vst/vl vector move instructions allow only for short
4282 && GET_CODE (XEXP (x
, 0)) == PLUS
4283 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4284 && !SHORT_DISP_IN_RANGE(INTVAL (XEXP (XEXP (x
, 0), 1)))
4285 && reg_class_subset_p (rclass
, VEC_REGS
)
4286 && (!reg_class_subset_p (rclass
, FP_REGS
)
4287 || (GET_MODE_SIZE (mode
) > 8
4288 && s390_class_max_nregs (FP_REGS
, mode
) == 1)))
4291 sri
->icode
= (TARGET_64BIT
?
4292 CODE_FOR_reloaddi_la_in
:
4293 CODE_FOR_reloadsi_la_in
);
4295 sri
->icode
= (TARGET_64BIT
?
4296 CODE_FOR_reloaddi_la_out
:
4297 CODE_FOR_reloadsi_la_out
);
4303 HOST_WIDE_INT offset
;
4306 /* On z10 several optimizer steps may generate larl operands with
4309 && s390_loadrelative_operand_p (x
, &symref
, &offset
)
4311 && !SYMBOL_FLAG_NOTALIGN2_P (symref
)
4312 && (offset
& 1) == 1)
4313 sri
->icode
= ((mode
== DImode
) ? CODE_FOR_reloaddi_larl_odd_addend_z10
4314 : CODE_FOR_reloadsi_larl_odd_addend_z10
);
4316 /* Handle all the (mem (symref)) accesses we cannot use the z10
4317 instructions for. */
4319 && s390_loadrelative_operand_p (XEXP (x
, 0), NULL
, NULL
)
4321 || !reg_class_subset_p (rclass
, GENERAL_REGS
)
4322 || GET_MODE_SIZE (mode
) > UNITS_PER_WORD
4323 || !s390_check_symref_alignment (XEXP (x
, 0),
4324 GET_MODE_SIZE (mode
))))
4326 #define __SECONDARY_RELOAD_CASE(M,m) \
4329 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
4330 CODE_FOR_reload##m##di_tomem_z10; \
4332 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
4333 CODE_FOR_reload##m##si_tomem_z10; \
4336 switch (GET_MODE (x
))
4338 __SECONDARY_RELOAD_CASE (QI
, qi
);
4339 __SECONDARY_RELOAD_CASE (HI
, hi
);
4340 __SECONDARY_RELOAD_CASE (SI
, si
);
4341 __SECONDARY_RELOAD_CASE (DI
, di
);
4342 __SECONDARY_RELOAD_CASE (TI
, ti
);
4343 __SECONDARY_RELOAD_CASE (SF
, sf
);
4344 __SECONDARY_RELOAD_CASE (DF
, df
);
4345 __SECONDARY_RELOAD_CASE (TF
, tf
);
4346 __SECONDARY_RELOAD_CASE (SD
, sd
);
4347 __SECONDARY_RELOAD_CASE (DD
, dd
);
4348 __SECONDARY_RELOAD_CASE (TD
, td
);
4349 __SECONDARY_RELOAD_CASE (V1QI
, v1qi
);
4350 __SECONDARY_RELOAD_CASE (V2QI
, v2qi
);
4351 __SECONDARY_RELOAD_CASE (V4QI
, v4qi
);
4352 __SECONDARY_RELOAD_CASE (V8QI
, v8qi
);
4353 __SECONDARY_RELOAD_CASE (V16QI
, v16qi
);
4354 __SECONDARY_RELOAD_CASE (V1HI
, v1hi
);
4355 __SECONDARY_RELOAD_CASE (V2HI
, v2hi
);
4356 __SECONDARY_RELOAD_CASE (V4HI
, v4hi
);
4357 __SECONDARY_RELOAD_CASE (V8HI
, v8hi
);
4358 __SECONDARY_RELOAD_CASE (V1SI
, v1si
);
4359 __SECONDARY_RELOAD_CASE (V2SI
, v2si
);
4360 __SECONDARY_RELOAD_CASE (V4SI
, v4si
);
4361 __SECONDARY_RELOAD_CASE (V1DI
, v1di
);
4362 __SECONDARY_RELOAD_CASE (V2DI
, v2di
);
4363 __SECONDARY_RELOAD_CASE (V1TI
, v1ti
);
4364 __SECONDARY_RELOAD_CASE (V1SF
, v1sf
);
4365 __SECONDARY_RELOAD_CASE (V2SF
, v2sf
);
4366 __SECONDARY_RELOAD_CASE (V4SF
, v4sf
);
4367 __SECONDARY_RELOAD_CASE (V1DF
, v1df
);
4368 __SECONDARY_RELOAD_CASE (V2DF
, v2df
);
4369 __SECONDARY_RELOAD_CASE (V1TF
, v1tf
);
4373 #undef __SECONDARY_RELOAD_CASE
4377 /* We need a scratch register when loading a PLUS expression which
4378 is not a legitimate operand of the LOAD ADDRESS instruction. */
4379 /* LRA can deal with transformation of plus op very well -- so we
4380 don't need to prompt LRA in this case. */
4381 if (! lra_in_progress
&& in_p
&& s390_plus_operand (x
, mode
))
4382 sri
->icode
= (TARGET_64BIT
?
4383 CODE_FOR_reloaddi_plus
: CODE_FOR_reloadsi_plus
);
4385 /* Performing a multiword move from or to memory we have to make sure the
4386 second chunk in memory is addressable without causing a displacement
4387 overflow. If that would be the case we calculate the address in
4388 a scratch register. */
4390 && GET_CODE (XEXP (x
, 0)) == PLUS
4391 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4392 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x
, 0), 1))
4393 + GET_MODE_SIZE (mode
) - 1))
4395 /* For GENERAL_REGS a displacement overflow is no problem if occurring
4396 in a s_operand address since we may fallback to lm/stm. So we only
4397 have to care about overflows in the b+i+d case. */
4398 if ((reg_classes_intersect_p (GENERAL_REGS
, rclass
)
4399 && s390_class_max_nregs (GENERAL_REGS
, mode
) > 1
4400 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
4401 /* For FP_REGS no lm/stm is available so this check is triggered
4402 for displacement overflows in b+i+d and b+d like addresses. */
4403 || (reg_classes_intersect_p (FP_REGS
, rclass
)
4404 && s390_class_max_nregs (FP_REGS
, mode
) > 1))
4407 sri
->icode
= (TARGET_64BIT
?
4408 CODE_FOR_reloaddi_la_in
:
4409 CODE_FOR_reloadsi_la_in
);
4411 sri
->icode
= (TARGET_64BIT
?
4412 CODE_FOR_reloaddi_la_out
:
4413 CODE_FOR_reloadsi_la_out
);
4417 /* A scratch address register is needed when a symbolic constant is
4418 copied to r0 compiling with -fPIC. In other cases the target
4419 register might be used as temporary (see legitimize_pic_address). */
4420 if (in_p
&& SYMBOLIC_CONST (x
) && flag_pic
== 2 && rclass
!= ADDR_REGS
)
4421 sri
->icode
= (TARGET_64BIT
?
4422 CODE_FOR_reloaddi_PIC_addr
:
4423 CODE_FOR_reloadsi_PIC_addr
);
4425 /* Either scratch or no register needed. */
4429 /* Implement TARGET_SECONDARY_MEMORY_NEEDED.
4431 We need secondary memory to move data between GPRs and FPRs.
4433 - With DFP the ldgr lgdr instructions are available. Due to the
4434 different alignment we cannot use them for SFmode. For 31 bit a
4435 64 bit value in GPR would be a register pair so here we still
4436 need to go via memory.
4438 - With z13 we can do the SF/SImode moves with vlgvf. Due to the
4439 overlapping of FPRs and VRs we still disallow TF/TD modes to be
4440 in full VRs so as before also on z13 we do these moves via
4443 FIXME: Should we try splitting it into two vlgvg's/vlvg's instead? */
4446 s390_secondary_memory_needed (machine_mode mode
,
4447 reg_class_t class1
, reg_class_t class2
)
4449 return (((reg_classes_intersect_p (class1
, VEC_REGS
)
4450 && reg_classes_intersect_p (class2
, GENERAL_REGS
))
4451 || (reg_classes_intersect_p (class1
, GENERAL_REGS
)
4452 && reg_classes_intersect_p (class2
, VEC_REGS
)))
4453 && (!TARGET_DFP
|| !TARGET_64BIT
|| GET_MODE_SIZE (mode
) != 8)
4454 && (!TARGET_VX
|| (SCALAR_FLOAT_MODE_P (mode
)
4455 && GET_MODE_SIZE (mode
) > 8)));
4458 /* Implement TARGET_SECONDARY_MEMORY_NEEDED_MODE.
4460 get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit
4461 because the movsi and movsf patterns don't handle r/f moves. */
4464 s390_secondary_memory_needed_mode (machine_mode mode
)
4466 if (GET_MODE_BITSIZE (mode
) < 32)
4467 return mode_for_size (32, GET_MODE_CLASS (mode
), 0).require ();
4471 /* Generate code to load SRC, which is PLUS that is not a
4472 legitimate operand for the LA instruction, into TARGET.
4473 SCRATCH may be used as scratch register. */
4476 s390_expand_plus_operand (rtx target
, rtx src
,
4480 struct s390_address ad
;
4482 /* src must be a PLUS; get its two operands. */
4483 gcc_assert (GET_CODE (src
) == PLUS
);
4484 gcc_assert (GET_MODE (src
) == Pmode
);
4486 /* Check if any of the two operands is already scheduled
4487 for replacement by reload. This can happen e.g. when
4488 float registers occur in an address. */
4489 sum1
= find_replacement (&XEXP (src
, 0));
4490 sum2
= find_replacement (&XEXP (src
, 1));
4491 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
4493 /* If the address is already strictly valid, there's nothing to do. */
4494 if (!s390_decompose_address (src
, &ad
)
4495 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
4496 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
4498 /* Otherwise, one of the operands cannot be an address register;
4499 we reload its value into the scratch register. */
4500 if (true_regnum (sum1
) < 1 || true_regnum (sum1
) > 15)
4502 emit_move_insn (scratch
, sum1
);
4505 if (true_regnum (sum2
) < 1 || true_regnum (sum2
) > 15)
4507 emit_move_insn (scratch
, sum2
);
4511 /* According to the way these invalid addresses are generated
4512 in reload.c, it should never happen (at least on s390) that
4513 *neither* of the PLUS components, after find_replacements
4514 was applied, is an address register. */
4515 if (sum1
== scratch
&& sum2
== scratch
)
4521 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
4524 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
4525 is only ever performed on addresses, so we can mark the
4526 sum as legitimate for LA in any case. */
4527 s390_load_address (target
, src
);
4531 /* Return true if ADDR is a valid memory address.
4532 STRICT specifies whether strict register checking applies. */
4535 s390_legitimate_address_p (machine_mode mode
, rtx addr
, bool strict
)
4537 struct s390_address ad
;
4540 && larl_operand (addr
, VOIDmode
)
4541 && (mode
== VOIDmode
4542 || s390_check_symref_alignment (addr
, GET_MODE_SIZE (mode
))))
4545 if (!s390_decompose_address (addr
, &ad
))
4550 if (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
4553 if (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
)))
4559 && !(REGNO (ad
.base
) >= FIRST_PSEUDO_REGISTER
4560 || REGNO_REG_CLASS (REGNO (ad
.base
)) == ADDR_REGS
))
4564 && !(REGNO (ad
.indx
) >= FIRST_PSEUDO_REGISTER
4565 || REGNO_REG_CLASS (REGNO (ad
.indx
)) == ADDR_REGS
))
4571 /* Return true if OP is a valid operand for the LA instruction.
4572 In 31-bit, we need to prove that the result is used as an
4573 address, as LA performs only a 31-bit addition. */
4576 legitimate_la_operand_p (rtx op
)
4578 struct s390_address addr
;
4579 if (!s390_decompose_address (op
, &addr
))
4582 return (TARGET_64BIT
|| addr
.pointer
);
4585 /* Return true if it is valid *and* preferable to use LA to
4586 compute the sum of OP1 and OP2. */
4589 preferred_la_operand_p (rtx op1
, rtx op2
)
4591 struct s390_address addr
;
4593 if (op2
!= const0_rtx
)
4594 op1
= gen_rtx_PLUS (Pmode
, op1
, op2
);
4596 if (!s390_decompose_address (op1
, &addr
))
4598 if (addr
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (addr
.base
)))
4600 if (addr
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (addr
.indx
)))
4603 /* Avoid LA instructions with index register on z196; it is
4604 preferable to use regular add instructions when possible.
4605 Starting with zEC12 the la with index register is "uncracked"
4607 if (addr
.indx
&& s390_tune
== PROCESSOR_2817_Z196
)
4610 if (!TARGET_64BIT
&& !addr
.pointer
)
4616 if ((addr
.base
&& REG_P (addr
.base
) && REG_POINTER (addr
.base
))
4617 || (addr
.indx
&& REG_P (addr
.indx
) && REG_POINTER (addr
.indx
)))
4623 /* Emit a forced load-address operation to load SRC into DST.
4624 This will use the LOAD ADDRESS instruction even in situations
4625 where legitimate_la_operand_p (SRC) returns false. */
4628 s390_load_address (rtx dst
, rtx src
)
4631 emit_move_insn (dst
, src
);
4633 emit_insn (gen_force_la_31 (dst
, src
));
4636 /* Return true if it ok to use SYMBOL_REF in a relative address. */
4639 s390_rel_address_ok_p (rtx symbol_ref
)
4643 if (symbol_ref
== s390_got_symbol () || CONSTANT_POOL_ADDRESS_P (symbol_ref
))
4646 decl
= SYMBOL_REF_DECL (symbol_ref
);
4648 if (!flag_pic
|| SYMBOL_REF_LOCAL_P (symbol_ref
))
4649 return (s390_pic_data_is_text_relative
4651 && TREE_CODE (decl
) == FUNCTION_DECL
));
4656 /* Return a legitimate reference for ORIG (an address) using the
4657 register REG. If REG is 0, a new pseudo is generated.
4659 There are two types of references that must be handled:
4661 1. Global data references must load the address from the GOT, via
4662 the PIC reg. An insn is emitted to do this load, and the reg is
4665 2. Static data references, constant pool addresses, and code labels
4666 compute the address as an offset from the GOT, whose base is in
4667 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
4668 differentiate them from global data objects. The returned
4669 address is the PIC reg + an unspec constant.
4671 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
4672 reg also appears in the address. */
4675 legitimize_pic_address (rtx orig
, rtx reg
)
4678 rtx addend
= const0_rtx
;
4681 gcc_assert (!TLS_SYMBOLIC_CONST (addr
));
4683 if (GET_CODE (addr
) == CONST
)
4684 addr
= XEXP (addr
, 0);
4686 if (GET_CODE (addr
) == PLUS
)
4688 addend
= XEXP (addr
, 1);
4689 addr
= XEXP (addr
, 0);
4692 if ((GET_CODE (addr
) == LABEL_REF
4693 || (SYMBOL_REF_P (addr
) && s390_rel_address_ok_p (addr
))
4694 || (GET_CODE (addr
) == UNSPEC
&&
4695 (XINT (addr
, 1) == UNSPEC_GOTENT
4696 || (TARGET_CPU_ZARCH
&& XINT (addr
, 1) == UNSPEC_PLT
))))
4697 && GET_CODE (addend
) == CONST_INT
)
4699 /* This can be locally addressed. */
4701 /* larl_operand requires UNSPECs to be wrapped in a const rtx. */
4702 rtx const_addr
= (GET_CODE (addr
) == UNSPEC
?
4703 gen_rtx_CONST (Pmode
, addr
) : addr
);
4705 if (TARGET_CPU_ZARCH
4706 && larl_operand (const_addr
, VOIDmode
)
4707 && INTVAL (addend
) < HOST_WIDE_INT_1
<< 31
4708 && INTVAL (addend
) >= -(HOST_WIDE_INT_1
<< 31))
4710 if (INTVAL (addend
) & 1)
4712 /* LARL can't handle odd offsets, so emit a pair of LARL
4714 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
4716 if (!DISP_IN_RANGE (INTVAL (addend
)))
4718 HOST_WIDE_INT even
= INTVAL (addend
) - 1;
4719 addr
= gen_rtx_PLUS (Pmode
, addr
, GEN_INT (even
));
4720 addr
= gen_rtx_CONST (Pmode
, addr
);
4721 addend
= const1_rtx
;
4724 emit_move_insn (temp
, addr
);
4725 new_rtx
= gen_rtx_PLUS (Pmode
, temp
, addend
);
4729 s390_load_address (reg
, new_rtx
);
4735 /* If the offset is even, we can just use LARL. This
4736 will happen automatically. */
4741 /* No larl - Access local symbols relative to the GOT. */
4743 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
4745 if (reload_in_progress
|| reload_completed
)
4746 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
4748 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTOFF
);
4749 if (addend
!= const0_rtx
)
4750 addr
= gen_rtx_PLUS (Pmode
, addr
, addend
);
4751 addr
= gen_rtx_CONST (Pmode
, addr
);
4752 addr
= force_const_mem (Pmode
, addr
);
4753 emit_move_insn (temp
, addr
);
4755 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
4758 s390_load_address (reg
, new_rtx
);
4763 else if (GET_CODE (addr
) == SYMBOL_REF
&& addend
== const0_rtx
)
4765 /* A non-local symbol reference without addend.
4767 The symbol ref is wrapped into an UNSPEC to make sure the
4768 proper operand modifier (@GOT or @GOTENT) will be emitted.
4769 This will tell the linker to put the symbol into the GOT.
4771 Additionally the code dereferencing the GOT slot is emitted here.
4773 An addend to the symref needs to be added afterwards.
4774 legitimize_pic_address calls itself recursively to handle
4775 that case. So no need to do it here. */
4778 reg
= gen_reg_rtx (Pmode
);
4782 /* Use load relative if possible.
4783 lgrl <target>, sym@GOTENT */
4784 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTENT
);
4785 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
4786 new_rtx
= gen_const_mem (GET_MODE (reg
), new_rtx
);
4788 emit_move_insn (reg
, new_rtx
);
4791 else if (flag_pic
== 1)
4793 /* Assume GOT offset is a valid displacement operand (< 4k
4794 or < 512k with z990). This is handled the same way in
4795 both 31- and 64-bit code (@GOT).
4796 lg <target>, sym@GOT(r12) */
4798 if (reload_in_progress
|| reload_completed
)
4799 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
4801 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
4802 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
4803 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new_rtx
);
4804 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
4805 emit_move_insn (reg
, new_rtx
);
4808 else if (TARGET_CPU_ZARCH
)
4810 /* If the GOT offset might be >= 4k, we determine the position
4811 of the GOT entry via a PC-relative LARL (@GOTENT).
4812 larl temp, sym@GOTENT
4813 lg <target>, 0(temp) */
4815 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
4817 gcc_assert (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
4818 || REGNO_REG_CLASS (REGNO (temp
)) == ADDR_REGS
);
4820 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTENT
);
4821 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
4822 emit_move_insn (temp
, new_rtx
);
4824 new_rtx
= gen_const_mem (Pmode
, temp
);
4825 emit_move_insn (reg
, new_rtx
);
4831 /* If the GOT offset might be >= 4k, we have to load it
4832 from the literal pool (@GOT).
4834 lg temp, lit-litbase(r13)
4835 lg <target>, 0(temp)
4836 lit: .long sym@GOT */
4838 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
4840 gcc_assert (REGNO (temp
) >= FIRST_PSEUDO_REGISTER
4841 || REGNO_REG_CLASS (REGNO (temp
)) == ADDR_REGS
);
4843 if (reload_in_progress
|| reload_completed
)
4844 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
4846 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
4847 addr
= gen_rtx_CONST (Pmode
, addr
);
4848 addr
= force_const_mem (Pmode
, addr
);
4849 emit_move_insn (temp
, addr
);
4851 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
4852 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
4853 emit_move_insn (reg
, new_rtx
);
4857 else if (GET_CODE (addr
) == UNSPEC
&& GET_CODE (addend
) == CONST_INT
)
4859 gcc_assert (XVECLEN (addr
, 0) == 1);
4860 switch (XINT (addr
, 1))
4862 /* These address symbols (or PLT slots) relative to the GOT
4863 (not GOT slots!). In general this will exceed the
4864 displacement range so these value belong into the literal
4868 new_rtx
= force_const_mem (Pmode
, orig
);
4871 /* For -fPIC the GOT size might exceed the displacement
4872 range so make sure the value is in the literal pool. */
4875 new_rtx
= force_const_mem (Pmode
, orig
);
4878 /* For @GOTENT larl is used. This is handled like local
4884 /* @PLT is OK as is on 64-bit, must be converted to
4885 GOT-relative @PLTOFF on 31-bit. */
4887 if (!TARGET_CPU_ZARCH
)
4889 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
4891 if (reload_in_progress
|| reload_completed
)
4892 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
4894 addr
= XVECEXP (addr
, 0, 0);
4895 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
),
4897 if (addend
!= const0_rtx
)
4898 addr
= gen_rtx_PLUS (Pmode
, addr
, addend
);
4899 addr
= gen_rtx_CONST (Pmode
, addr
);
4900 addr
= force_const_mem (Pmode
, addr
);
4901 emit_move_insn (temp
, addr
);
4903 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
4906 s390_load_address (reg
, new_rtx
);
4911 /* On 64 bit larl can be used. This case is handled like
4912 local symbol refs. */
4916 /* Everything else cannot happen. */
4921 else if (addend
!= const0_rtx
)
4923 /* Otherwise, compute the sum. */
4925 rtx base
= legitimize_pic_address (addr
, reg
);
4926 new_rtx
= legitimize_pic_address (addend
,
4927 base
== reg
? NULL_RTX
: reg
);
4928 if (GET_CODE (new_rtx
) == CONST_INT
)
4929 new_rtx
= plus_constant (Pmode
, base
, INTVAL (new_rtx
));
4932 if (GET_CODE (new_rtx
) == PLUS
&& CONSTANT_P (XEXP (new_rtx
, 1)))
4934 base
= gen_rtx_PLUS (Pmode
, base
, XEXP (new_rtx
, 0));
4935 new_rtx
= XEXP (new_rtx
, 1);
4937 new_rtx
= gen_rtx_PLUS (Pmode
, base
, new_rtx
);
4940 if (GET_CODE (new_rtx
) == CONST
)
4941 new_rtx
= XEXP (new_rtx
, 0);
4942 new_rtx
= force_operand (new_rtx
, 0);
4948 /* Load the thread pointer into a register. */
4951 s390_get_thread_pointer (void)
4953 rtx tp
= gen_reg_rtx (Pmode
);
4955 emit_move_insn (tp
, gen_rtx_REG (Pmode
, TP_REGNUM
));
4956 mark_reg_pointer (tp
, BITS_PER_WORD
);
4961 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
4962 in s390_tls_symbol which always refers to __tls_get_offset.
4963 The returned offset is written to RESULT_REG and an USE rtx is
4964 generated for TLS_CALL. */
4966 static GTY(()) rtx s390_tls_symbol
;
4969 s390_emit_tls_call_insn (rtx result_reg
, rtx tls_call
)
4974 emit_insn (s390_load_got ());
4976 if (!s390_tls_symbol
)
4977 s390_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_offset");
4979 insn
= s390_emit_call (s390_tls_symbol
, tls_call
, result_reg
,
4980 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
4982 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), result_reg
);
4983 RTL_CONST_CALL_P (insn
) = 1;
4986 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
4987 this (thread-local) address. REG may be used as temporary. */
4990 legitimize_tls_address (rtx addr
, rtx reg
)
4992 rtx new_rtx
, tls_call
, temp
, base
, r2
;
4995 if (GET_CODE (addr
) == SYMBOL_REF
)
4996 switch (tls_symbolic_operand (addr
))
4998 case TLS_MODEL_GLOBAL_DYNAMIC
:
5000 r2
= gen_rtx_REG (Pmode
, 2);
5001 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_TLSGD
);
5002 new_rtx
= gen_rtx_CONST (Pmode
, tls_call
);
5003 new_rtx
= force_const_mem (Pmode
, new_rtx
);
5004 emit_move_insn (r2
, new_rtx
);
5005 s390_emit_tls_call_insn (r2
, tls_call
);
5006 insn
= get_insns ();
5009 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
5010 temp
= gen_reg_rtx (Pmode
);
5011 emit_libcall_block (insn
, temp
, r2
, new_rtx
);
5013 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
5016 s390_load_address (reg
, new_rtx
);
5021 case TLS_MODEL_LOCAL_DYNAMIC
:
5023 r2
= gen_rtx_REG (Pmode
, 2);
5024 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM
);
5025 new_rtx
= gen_rtx_CONST (Pmode
, tls_call
);
5026 new_rtx
= force_const_mem (Pmode
, new_rtx
);
5027 emit_move_insn (r2
, new_rtx
);
5028 s390_emit_tls_call_insn (r2
, tls_call
);
5029 insn
= get_insns ();
5032 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM_NTPOFF
);
5033 temp
= gen_reg_rtx (Pmode
);
5034 emit_libcall_block (insn
, temp
, r2
, new_rtx
);
5036 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
5037 base
= gen_reg_rtx (Pmode
);
5038 s390_load_address (base
, new_rtx
);
5040 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_DTPOFF
);
5041 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
5042 new_rtx
= force_const_mem (Pmode
, new_rtx
);
5043 temp
= gen_reg_rtx (Pmode
);
5044 emit_move_insn (temp
, new_rtx
);
5046 new_rtx
= gen_rtx_PLUS (Pmode
, base
, temp
);
5049 s390_load_address (reg
, new_rtx
);
5054 case TLS_MODEL_INITIAL_EXEC
:
5057 /* Assume GOT offset < 4k. This is handled the same way
5058 in both 31- and 64-bit code. */
5060 if (reload_in_progress
|| reload_completed
)
5061 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
5063 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
5064 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
5065 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new_rtx
);
5066 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
5067 temp
= gen_reg_rtx (Pmode
);
5068 emit_move_insn (temp
, new_rtx
);
5070 else if (TARGET_CPU_ZARCH
)
5072 /* If the GOT offset might be >= 4k, we determine the position
5073 of the GOT entry via a PC-relative LARL. */
5075 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
5076 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
5077 temp
= gen_reg_rtx (Pmode
);
5078 emit_move_insn (temp
, new_rtx
);
5080 new_rtx
= gen_const_mem (Pmode
, temp
);
5081 temp
= gen_reg_rtx (Pmode
);
5082 emit_move_insn (temp
, new_rtx
);
5086 /* If the GOT offset might be >= 4k, we have to load it
5087 from the literal pool. */
5089 if (reload_in_progress
|| reload_completed
)
5090 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
5092 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
5093 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
5094 new_rtx
= force_const_mem (Pmode
, new_rtx
);
5095 temp
= gen_reg_rtx (Pmode
);
5096 emit_move_insn (temp
, new_rtx
);
5098 new_rtx
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
5099 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
5101 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new_rtx
, addr
), UNSPEC_TLS_LOAD
);
5102 temp
= gen_reg_rtx (Pmode
);
5103 emit_insn (gen_rtx_SET (temp
, new_rtx
));
5107 /* In position-dependent code, load the absolute address of
5108 the GOT entry from the literal pool. */
5110 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
5111 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
5112 new_rtx
= force_const_mem (Pmode
, new_rtx
);
5113 temp
= gen_reg_rtx (Pmode
);
5114 emit_move_insn (temp
, new_rtx
);
5117 new_rtx
= gen_const_mem (Pmode
, new_rtx
);
5118 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new_rtx
, addr
), UNSPEC_TLS_LOAD
);
5119 temp
= gen_reg_rtx (Pmode
);
5120 emit_insn (gen_rtx_SET (temp
, new_rtx
));
5123 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
5126 s390_load_address (reg
, new_rtx
);
5131 case TLS_MODEL_LOCAL_EXEC
:
5132 new_rtx
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
5133 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
5134 new_rtx
= force_const_mem (Pmode
, new_rtx
);
5135 temp
= gen_reg_rtx (Pmode
);
5136 emit_move_insn (temp
, new_rtx
);
5138 new_rtx
= gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
5141 s390_load_address (reg
, new_rtx
);
5150 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == UNSPEC
)
5152 switch (XINT (XEXP (addr
, 0), 1))
5154 case UNSPEC_INDNTPOFF
:
5155 gcc_assert (TARGET_CPU_ZARCH
);
5164 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == PLUS
5165 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST_INT
)
5167 new_rtx
= XEXP (XEXP (addr
, 0), 0);
5168 if (GET_CODE (new_rtx
) != SYMBOL_REF
)
5169 new_rtx
= gen_rtx_CONST (Pmode
, new_rtx
);
5171 new_rtx
= legitimize_tls_address (new_rtx
, reg
);
5172 new_rtx
= plus_constant (Pmode
, new_rtx
,
5173 INTVAL (XEXP (XEXP (addr
, 0), 1)));
5174 new_rtx
= force_operand (new_rtx
, 0);
5178 gcc_unreachable (); /* for now ... */
5183 /* Emit insns making the address in operands[1] valid for a standard
5184 move to operands[0]. operands[1] is replaced by an address which
5185 should be used instead of the former RTX to emit the move
5189 emit_symbolic_move (rtx
*operands
)
5191 rtx temp
= !can_create_pseudo_p () ? operands
[0] : gen_reg_rtx (Pmode
);
5193 if (GET_CODE (operands
[0]) == MEM
)
5194 operands
[1] = force_reg (Pmode
, operands
[1]);
5195 else if (TLS_SYMBOLIC_CONST (operands
[1]))
5196 operands
[1] = legitimize_tls_address (operands
[1], temp
);
5198 operands
[1] = legitimize_pic_address (operands
[1], temp
);
5201 /* Try machine-dependent ways of modifying an illegitimate address X
5202 to be legitimate. If we find one, return the new, valid address.
5204 OLDX is the address as it was before break_out_memory_refs was called.
5205 In some cases it is useful to look at this to decide what needs to be done.
5207 MODE is the mode of the operand pointed to by X.
5209 When -fpic is used, special handling is needed for symbolic references.
5210 See comments by legitimize_pic_address for details. */
5213 s390_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
5214 machine_mode mode ATTRIBUTE_UNUSED
)
5216 rtx constant_term
= const0_rtx
;
5218 if (TLS_SYMBOLIC_CONST (x
))
5220 x
= legitimize_tls_address (x
, 0);
5222 if (s390_legitimate_address_p (mode
, x
, FALSE
))
5225 else if (GET_CODE (x
) == PLUS
5226 && (TLS_SYMBOLIC_CONST (XEXP (x
, 0))
5227 || TLS_SYMBOLIC_CONST (XEXP (x
, 1))))
5233 if (SYMBOLIC_CONST (x
)
5234 || (GET_CODE (x
) == PLUS
5235 && (SYMBOLIC_CONST (XEXP (x
, 0))
5236 || SYMBOLIC_CONST (XEXP (x
, 1)))))
5237 x
= legitimize_pic_address (x
, 0);
5239 if (s390_legitimate_address_p (mode
, x
, FALSE
))
5243 x
= eliminate_constant_term (x
, &constant_term
);
5245 /* Optimize loading of large displacements by splitting them
5246 into the multiple of 4K and the rest; this allows the
5247 former to be CSE'd if possible.
5249 Don't do this if the displacement is added to a register
5250 pointing into the stack frame, as the offsets will
5251 change later anyway. */
5253 if (GET_CODE (constant_term
) == CONST_INT
5254 && !TARGET_LONG_DISPLACEMENT
5255 && !DISP_IN_RANGE (INTVAL (constant_term
))
5256 && !(REG_P (x
) && REGNO_PTR_FRAME_P (REGNO (x
))))
5258 HOST_WIDE_INT lower
= INTVAL (constant_term
) & 0xfff;
5259 HOST_WIDE_INT upper
= INTVAL (constant_term
) ^ lower
;
5261 rtx temp
= gen_reg_rtx (Pmode
);
5262 rtx val
= force_operand (GEN_INT (upper
), temp
);
5264 emit_move_insn (temp
, val
);
5266 x
= gen_rtx_PLUS (Pmode
, x
, temp
);
5267 constant_term
= GEN_INT (lower
);
5270 if (GET_CODE (x
) == PLUS
)
5272 if (GET_CODE (XEXP (x
, 0)) == REG
)
5274 rtx temp
= gen_reg_rtx (Pmode
);
5275 rtx val
= force_operand (XEXP (x
, 1), temp
);
5277 emit_move_insn (temp
, val
);
5279 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0), temp
);
5282 else if (GET_CODE (XEXP (x
, 1)) == REG
)
5284 rtx temp
= gen_reg_rtx (Pmode
);
5285 rtx val
= force_operand (XEXP (x
, 0), temp
);
5287 emit_move_insn (temp
, val
);
5289 x
= gen_rtx_PLUS (Pmode
, temp
, XEXP (x
, 1));
5293 if (constant_term
!= const0_rtx
)
5294 x
= gen_rtx_PLUS (Pmode
, x
, constant_term
);
5299 /* Try a machine-dependent way of reloading an illegitimate address AD
5300 operand. If we find one, push the reload and return the new address.
5302 MODE is the mode of the enclosing MEM. OPNUM is the operand number
5303 and TYPE is the reload type of the current reload. */
5306 legitimize_reload_address (rtx ad
, machine_mode mode ATTRIBUTE_UNUSED
,
5307 int opnum
, int type
)
5309 if (!optimize
|| TARGET_LONG_DISPLACEMENT
)
5312 if (GET_CODE (ad
) == PLUS
)
5314 rtx tem
= simplify_binary_operation (PLUS
, Pmode
,
5315 XEXP (ad
, 0), XEXP (ad
, 1));
5320 if (GET_CODE (ad
) == PLUS
5321 && GET_CODE (XEXP (ad
, 0)) == REG
5322 && GET_CODE (XEXP (ad
, 1)) == CONST_INT
5323 && !DISP_IN_RANGE (INTVAL (XEXP (ad
, 1))))
5325 HOST_WIDE_INT lower
= INTVAL (XEXP (ad
, 1)) & 0xfff;
5326 HOST_WIDE_INT upper
= INTVAL (XEXP (ad
, 1)) ^ lower
;
5327 rtx cst
, tem
, new_rtx
;
5329 cst
= GEN_INT (upper
);
5330 if (!legitimate_reload_constant_p (cst
))
5331 cst
= force_const_mem (Pmode
, cst
);
5333 tem
= gen_rtx_PLUS (Pmode
, XEXP (ad
, 0), cst
);
5334 new_rtx
= gen_rtx_PLUS (Pmode
, tem
, GEN_INT (lower
));
5336 push_reload (XEXP (tem
, 1), 0, &XEXP (tem
, 1), 0,
5337 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
5338 opnum
, (enum reload_type
) type
);
5345 /* Emit code to move LEN bytes from DST to SRC. */
5348 s390_expand_movmem (rtx dst
, rtx src
, rtx len
)
5350 /* When tuning for z10 or higher we rely on the Glibc functions to
5351 do the right thing. Only for constant lengths below 64k we will
5352 generate inline code. */
5353 if (s390_tune
>= PROCESSOR_2097_Z10
5354 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > (1<<16)))
5357 /* Expand memcpy for constant length operands without a loop if it
5358 is shorter that way.
5360 With a constant length argument a
5361 memcpy loop (without pfd) is 36 bytes -> 6 * mvc */
5362 if (GET_CODE (len
) == CONST_INT
5363 && INTVAL (len
) >= 0
5364 && INTVAL (len
) <= 256 * 6
5365 && (!TARGET_MVCLE
|| INTVAL (len
) <= 256))
5369 for (l
= INTVAL (len
), o
= 0; l
> 0; l
-= 256, o
+= 256)
5371 rtx newdst
= adjust_address (dst
, BLKmode
, o
);
5372 rtx newsrc
= adjust_address (src
, BLKmode
, o
);
5373 emit_insn (gen_movmem_short (newdst
, newsrc
,
5374 GEN_INT (l
> 256 ? 255 : l
- 1)));
5378 else if (TARGET_MVCLE
)
5380 emit_insn (gen_movmem_long (dst
, src
, convert_to_mode (Pmode
, len
, 1)));
5385 rtx dst_addr
, src_addr
, count
, blocks
, temp
;
5386 rtx_code_label
*loop_start_label
= gen_label_rtx ();
5387 rtx_code_label
*loop_end_label
= gen_label_rtx ();
5388 rtx_code_label
*end_label
= gen_label_rtx ();
5391 mode
= GET_MODE (len
);
5392 if (mode
== VOIDmode
)
5395 dst_addr
= gen_reg_rtx (Pmode
);
5396 src_addr
= gen_reg_rtx (Pmode
);
5397 count
= gen_reg_rtx (mode
);
5398 blocks
= gen_reg_rtx (mode
);
5400 convert_move (count
, len
, 1);
5401 emit_cmp_and_jump_insns (count
, const0_rtx
,
5402 EQ
, NULL_RTX
, mode
, 1, end_label
);
5404 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
5405 emit_move_insn (src_addr
, force_operand (XEXP (src
, 0), NULL_RTX
));
5406 dst
= change_address (dst
, VOIDmode
, dst_addr
);
5407 src
= change_address (src
, VOIDmode
, src_addr
);
5409 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
5412 emit_move_insn (count
, temp
);
5414 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
5417 emit_move_insn (blocks
, temp
);
5419 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
5420 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
5422 emit_label (loop_start_label
);
5425 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 768))
5429 /* Issue a read prefetch for the +3 cache line. */
5430 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, src_addr
, GEN_INT (768)),
5431 const0_rtx
, const0_rtx
);
5432 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
5433 emit_insn (prefetch
);
5435 /* Issue a write prefetch for the +3 cache line. */
5436 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (768)),
5437 const1_rtx
, const0_rtx
);
5438 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
5439 emit_insn (prefetch
);
5442 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (255)));
5443 s390_load_address (dst_addr
,
5444 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
5445 s390_load_address (src_addr
,
5446 gen_rtx_PLUS (Pmode
, src_addr
, GEN_INT (256)));
5448 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
5451 emit_move_insn (blocks
, temp
);
5453 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
5454 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
5456 emit_jump (loop_start_label
);
5457 emit_label (loop_end_label
);
5459 emit_insn (gen_movmem_short (dst
, src
,
5460 convert_to_mode (Pmode
, count
, 1)));
5461 emit_label (end_label
);
5466 /* Emit code to set LEN bytes at DST to VAL.
5467 Make use of clrmem if VAL is zero. */
5470 s390_expand_setmem (rtx dst
, rtx len
, rtx val
)
5472 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) <= 0)
5475 gcc_assert (GET_CODE (val
) == CONST_INT
|| GET_MODE (val
) == QImode
);
5477 /* Expand setmem/clrmem for a constant length operand without a
5478 loop if it will be shorter that way.
5479 With a constant length and without pfd argument a
5480 clrmem loop is 32 bytes -> 5.3 * xc
5481 setmem loop is 36 bytes -> 3.6 * (mvi/stc + mvc) */
5482 if (GET_CODE (len
) == CONST_INT
5483 && ((INTVAL (len
) <= 256 * 5 && val
== const0_rtx
)
5484 || INTVAL (len
) <= 257 * 3)
5485 && (!TARGET_MVCLE
|| INTVAL (len
) <= 256))
5489 if (val
== const0_rtx
)
5490 /* clrmem: emit 256 byte blockwise XCs. */
5491 for (l
= INTVAL (len
), o
= 0; l
> 0; l
-= 256, o
+= 256)
5493 rtx newdst
= adjust_address (dst
, BLKmode
, o
);
5494 emit_insn (gen_clrmem_short (newdst
,
5495 GEN_INT (l
> 256 ? 255 : l
- 1)));
5498 /* setmem: emit 1(mvi) + 256(mvc) byte blockwise memsets by
5499 setting first byte to val and using a 256 byte mvc with one
5500 byte overlap to propagate the byte. */
5501 for (l
= INTVAL (len
), o
= 0; l
> 0; l
-= 257, o
+= 257)
5503 rtx newdst
= adjust_address (dst
, BLKmode
, o
);
5504 emit_move_insn (adjust_address (dst
, QImode
, o
), val
);
5507 rtx newdstp1
= adjust_address (dst
, BLKmode
, o
+ 1);
5508 emit_insn (gen_movmem_short (newdstp1
, newdst
,
5509 GEN_INT (l
> 257 ? 255 : l
- 2)));
5514 else if (TARGET_MVCLE
)
5516 val
= force_not_mem (convert_modes (Pmode
, QImode
, val
, 1));
5518 emit_insn (gen_setmem_long_di (dst
, convert_to_mode (Pmode
, len
, 1),
5521 emit_insn (gen_setmem_long_si (dst
, convert_to_mode (Pmode
, len
, 1),
5527 rtx dst_addr
, count
, blocks
, temp
, dstp1
= NULL_RTX
;
5528 rtx_code_label
*loop_start_label
= gen_label_rtx ();
5529 rtx_code_label
*onebyte_end_label
= gen_label_rtx ();
5530 rtx_code_label
*zerobyte_end_label
= gen_label_rtx ();
5531 rtx_code_label
*restbyte_end_label
= gen_label_rtx ();
5534 mode
= GET_MODE (len
);
5535 if (mode
== VOIDmode
)
5538 dst_addr
= gen_reg_rtx (Pmode
);
5539 count
= gen_reg_rtx (mode
);
5540 blocks
= gen_reg_rtx (mode
);
5542 convert_move (count
, len
, 1);
5543 emit_cmp_and_jump_insns (count
, const0_rtx
,
5544 EQ
, NULL_RTX
, mode
, 1, zerobyte_end_label
,
5545 profile_probability::very_unlikely ());
5547 /* We need to make a copy of the target address since memset is
5548 supposed to return it unmodified. We have to make it here
5549 already since the new reg is used at onebyte_end_label. */
5550 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
5551 dst
= change_address (dst
, VOIDmode
, dst_addr
);
5553 if (val
!= const0_rtx
)
5555 /* When using the overlapping mvc the original target
5556 address is only accessed as single byte entity (even by
5557 the mvc reading this value). */
5558 set_mem_size (dst
, 1);
5559 dstp1
= adjust_address (dst
, VOIDmode
, 1);
5560 emit_cmp_and_jump_insns (count
,
5561 const1_rtx
, EQ
, NULL_RTX
, mode
, 1,
5563 profile_probability::very_unlikely ());
5566 /* There is one unconditional (mvi+mvc)/xc after the loop
5567 dealing with the rest of the bytes, subtracting two (mvi+mvc)
5568 or one (xc) here leaves this number of bytes to be handled by
5570 temp
= expand_binop (mode
, add_optab
, count
,
5571 val
== const0_rtx
? constm1_rtx
: GEN_INT (-2),
5572 count
, 1, OPTAB_DIRECT
);
5574 emit_move_insn (count
, temp
);
5576 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
5579 emit_move_insn (blocks
, temp
);
5581 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
5582 EQ
, NULL_RTX
, mode
, 1, restbyte_end_label
);
5584 emit_jump (loop_start_label
);
5586 if (val
!= const0_rtx
)
5588 /* The 1 byte != 0 special case. Not handled efficiently
5589 since we require two jumps for that. However, this
5590 should be very rare. */
5591 emit_label (onebyte_end_label
);
5592 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
5593 emit_jump (zerobyte_end_label
);
5596 emit_label (loop_start_label
);
5599 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 1024))
5601 /* Issue a write prefetch for the +4 cache line. */
5602 rtx prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, dst_addr
,
5604 const1_rtx
, const0_rtx
);
5605 emit_insn (prefetch
);
5606 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
5609 if (val
== const0_rtx
)
5610 emit_insn (gen_clrmem_short (dst
, GEN_INT (255)));
5613 /* Set the first byte in the block to the value and use an
5614 overlapping mvc for the block. */
5615 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
5616 emit_insn (gen_movmem_short (dstp1
, dst
, GEN_INT (254)));
5618 s390_load_address (dst_addr
,
5619 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
5621 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
5624 emit_move_insn (blocks
, temp
);
5626 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
5627 NE
, NULL_RTX
, mode
, 1, loop_start_label
);
5629 emit_label (restbyte_end_label
);
5631 if (val
== const0_rtx
)
5632 emit_insn (gen_clrmem_short (dst
, convert_to_mode (Pmode
, count
, 1)));
5635 /* Set the first byte in the block to the value and use an
5636 overlapping mvc for the block. */
5637 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
5638 /* execute only uses the lowest 8 bits of count that's
5639 exactly what we need here. */
5640 emit_insn (gen_movmem_short (dstp1
, dst
,
5641 convert_to_mode (Pmode
, count
, 1)));
5644 emit_label (zerobyte_end_label
);
5648 /* Emit code to compare LEN bytes at OP0 with those at OP1,
5649 and return the result in TARGET. */
5652 s390_expand_cmpmem (rtx target
, rtx op0
, rtx op1
, rtx len
)
5654 rtx ccreg
= gen_rtx_REG (CCUmode
, CC_REGNUM
);
5657 /* When tuning for z10 or higher we rely on the Glibc functions to
5658 do the right thing. Only for constant lengths below 64k we will
5659 generate inline code. */
5660 if (s390_tune
>= PROCESSOR_2097_Z10
5661 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > (1<<16)))
5664 /* As the result of CMPINT is inverted compared to what we need,
5665 we have to swap the operands. */
5666 tmp
= op0
; op0
= op1
; op1
= tmp
;
5668 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
5670 if (INTVAL (len
) > 0)
5672 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (INTVAL (len
) - 1)));
5673 emit_insn (gen_cmpint (target
, ccreg
));
5676 emit_move_insn (target
, const0_rtx
);
5678 else if (TARGET_MVCLE
)
5680 emit_insn (gen_cmpmem_long (op0
, op1
, convert_to_mode (Pmode
, len
, 1)));
5681 emit_insn (gen_cmpint (target
, ccreg
));
5685 rtx addr0
, addr1
, count
, blocks
, temp
;
5686 rtx_code_label
*loop_start_label
= gen_label_rtx ();
5687 rtx_code_label
*loop_end_label
= gen_label_rtx ();
5688 rtx_code_label
*end_label
= gen_label_rtx ();
5691 mode
= GET_MODE (len
);
5692 if (mode
== VOIDmode
)
5695 addr0
= gen_reg_rtx (Pmode
);
5696 addr1
= gen_reg_rtx (Pmode
);
5697 count
= gen_reg_rtx (mode
);
5698 blocks
= gen_reg_rtx (mode
);
5700 convert_move (count
, len
, 1);
5701 emit_cmp_and_jump_insns (count
, const0_rtx
,
5702 EQ
, NULL_RTX
, mode
, 1, end_label
);
5704 emit_move_insn (addr0
, force_operand (XEXP (op0
, 0), NULL_RTX
));
5705 emit_move_insn (addr1
, force_operand (XEXP (op1
, 0), NULL_RTX
));
5706 op0
= change_address (op0
, VOIDmode
, addr0
);
5707 op1
= change_address (op1
, VOIDmode
, addr1
);
5709 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1,
5712 emit_move_insn (count
, temp
);
5714 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1,
5717 emit_move_insn (blocks
, temp
);
5719 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
5720 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
5722 emit_label (loop_start_label
);
5725 && (GET_CODE (len
) != CONST_INT
|| INTVAL (len
) > 512))
5729 /* Issue a read prefetch for the +2 cache line of operand 1. */
5730 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, addr0
, GEN_INT (512)),
5731 const0_rtx
, const0_rtx
);
5732 emit_insn (prefetch
);
5733 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
5735 /* Issue a read prefetch for the +2 cache line of operand 2. */
5736 prefetch
= gen_prefetch (gen_rtx_PLUS (Pmode
, addr1
, GEN_INT (512)),
5737 const0_rtx
, const0_rtx
);
5738 emit_insn (prefetch
);
5739 PREFETCH_SCHEDULE_BARRIER_P (prefetch
) = true;
5742 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (255)));
5743 temp
= gen_rtx_NE (VOIDmode
, ccreg
, const0_rtx
);
5744 temp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, temp
,
5745 gen_rtx_LABEL_REF (VOIDmode
, end_label
), pc_rtx
);
5746 temp
= gen_rtx_SET (pc_rtx
, temp
);
5747 emit_jump_insn (temp
);
5749 s390_load_address (addr0
,
5750 gen_rtx_PLUS (Pmode
, addr0
, GEN_INT (256)));
5751 s390_load_address (addr1
,
5752 gen_rtx_PLUS (Pmode
, addr1
, GEN_INT (256)));
5754 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1,
5757 emit_move_insn (blocks
, temp
);
5759 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
5760 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
5762 emit_jump (loop_start_label
);
5763 emit_label (loop_end_label
);
5765 emit_insn (gen_cmpmem_short (op0
, op1
,
5766 convert_to_mode (Pmode
, count
, 1)));
5767 emit_label (end_label
);
5769 emit_insn (gen_cmpint (target
, ccreg
));
5774 /* Emit a conditional jump to LABEL for condition code mask MASK using
5775 comparsion operator COMPARISON. Return the emitted jump insn. */
5778 s390_emit_ccraw_jump (HOST_WIDE_INT mask
, enum rtx_code comparison
, rtx label
)
5782 gcc_assert (comparison
== EQ
|| comparison
== NE
);
5783 gcc_assert (mask
> 0 && mask
< 15);
5785 temp
= gen_rtx_fmt_ee (comparison
, VOIDmode
,
5786 gen_rtx_REG (CCRAWmode
, CC_REGNUM
), GEN_INT (mask
));
5787 temp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, temp
,
5788 gen_rtx_LABEL_REF (VOIDmode
, label
), pc_rtx
);
5789 temp
= gen_rtx_SET (pc_rtx
, temp
);
5790 return emit_jump_insn (temp
);
5793 /* Emit the instructions to implement strlen of STRING and store the
5794 result in TARGET. The string has the known ALIGNMENT. This
5795 version uses vector instructions and is therefore not appropriate
5796 for targets prior to z13. */
5799 s390_expand_vec_strlen (rtx target
, rtx string
, rtx alignment
)
5801 rtx highest_index_to_load_reg
= gen_reg_rtx (Pmode
);
5802 rtx str_reg
= gen_reg_rtx (V16QImode
);
5803 rtx str_addr_base_reg
= gen_reg_rtx (Pmode
);
5804 rtx str_idx_reg
= gen_reg_rtx (Pmode
);
5805 rtx result_reg
= gen_reg_rtx (V16QImode
);
5806 rtx is_aligned_label
= gen_label_rtx ();
5807 rtx into_loop_label
= NULL_RTX
;
5808 rtx loop_start_label
= gen_label_rtx ();
5810 rtx len
= gen_reg_rtx (QImode
);
5813 s390_load_address (str_addr_base_reg
, XEXP (string
, 0));
5814 emit_move_insn (str_idx_reg
, const0_rtx
);
5816 if (INTVAL (alignment
) < 16)
5818 /* Check whether the address happens to be aligned properly so
5819 jump directly to the aligned loop. */
5820 emit_cmp_and_jump_insns (gen_rtx_AND (Pmode
,
5821 str_addr_base_reg
, GEN_INT (15)),
5822 const0_rtx
, EQ
, NULL_RTX
,
5823 Pmode
, 1, is_aligned_label
);
5825 temp
= gen_reg_rtx (Pmode
);
5826 temp
= expand_binop (Pmode
, and_optab
, str_addr_base_reg
,
5827 GEN_INT (15), temp
, 1, OPTAB_DIRECT
);
5828 gcc_assert (REG_P (temp
));
5829 highest_index_to_load_reg
=
5830 expand_binop (Pmode
, sub_optab
, GEN_INT (15), temp
,
5831 highest_index_to_load_reg
, 1, OPTAB_DIRECT
);
5832 gcc_assert (REG_P (highest_index_to_load_reg
));
5833 emit_insn (gen_vllv16qi (str_reg
,
5834 convert_to_mode (SImode
, highest_index_to_load_reg
, 1),
5835 gen_rtx_MEM (BLKmode
, str_addr_base_reg
)));
5837 into_loop_label
= gen_label_rtx ();
5838 s390_emit_jump (into_loop_label
, NULL_RTX
);
5842 emit_label (is_aligned_label
);
5843 LABEL_NUSES (is_aligned_label
) = INTVAL (alignment
) < 16 ? 2 : 1;
5845 /* Reaching this point we are only performing 16 bytes aligned
5847 emit_move_insn (highest_index_to_load_reg
, GEN_INT (15));
5849 emit_label (loop_start_label
);
5850 LABEL_NUSES (loop_start_label
) = 1;
5852 /* Load 16 bytes of the string into VR. */
5853 emit_move_insn (str_reg
,
5854 gen_rtx_MEM (V16QImode
,
5855 gen_rtx_PLUS (Pmode
, str_idx_reg
,
5856 str_addr_base_reg
)));
5857 if (into_loop_label
!= NULL_RTX
)
5859 emit_label (into_loop_label
);
5860 LABEL_NUSES (into_loop_label
) = 1;
5863 /* Increment string index by 16 bytes. */
5864 expand_binop (Pmode
, add_optab
, str_idx_reg
, GEN_INT (16),
5865 str_idx_reg
, 1, OPTAB_DIRECT
);
5867 emit_insn (gen_vec_vfenesv16qi (result_reg
, str_reg
, str_reg
,
5868 GEN_INT (VSTRING_FLAG_ZS
| VSTRING_FLAG_CS
)));
5870 add_int_reg_note (s390_emit_ccraw_jump (8, NE
, loop_start_label
),
5872 profile_probability::very_likely ().to_reg_br_prob_note ());
5873 emit_insn (gen_vec_extractv16qiqi (len
, result_reg
, GEN_INT (7)));
5875 /* If the string pointer wasn't aligned we have loaded less then 16
5876 bytes and the remaining bytes got filled with zeros (by vll).
5877 Now we have to check whether the resulting index lies within the
5878 bytes actually part of the string. */
5880 cond
= s390_emit_compare (GT
, convert_to_mode (Pmode
, len
, 1),
5881 highest_index_to_load_reg
);
5882 s390_load_address (highest_index_to_load_reg
,
5883 gen_rtx_PLUS (Pmode
, highest_index_to_load_reg
,
5886 emit_insn (gen_movdicc (str_idx_reg
, cond
,
5887 highest_index_to_load_reg
, str_idx_reg
));
5889 emit_insn (gen_movsicc (str_idx_reg
, cond
,
5890 highest_index_to_load_reg
, str_idx_reg
));
5892 add_reg_br_prob_note (s390_emit_jump (is_aligned_label
, cond
),
5893 profile_probability::very_unlikely ());
5895 expand_binop (Pmode
, add_optab
, str_idx_reg
,
5896 GEN_INT (-16), str_idx_reg
, 1, OPTAB_DIRECT
);
5897 /* FIXME: len is already zero extended - so avoid the llgcr emitted
5899 temp
= expand_binop (Pmode
, add_optab
, str_idx_reg
,
5900 convert_to_mode (Pmode
, len
, 1),
5901 target
, 1, OPTAB_DIRECT
);
5903 emit_move_insn (target
, temp
);
5907 s390_expand_vec_movstr (rtx result
, rtx dst
, rtx src
)
5909 rtx temp
= gen_reg_rtx (Pmode
);
5910 rtx src_addr
= XEXP (src
, 0);
5911 rtx dst_addr
= XEXP (dst
, 0);
5912 rtx src_addr_reg
= gen_reg_rtx (Pmode
);
5913 rtx dst_addr_reg
= gen_reg_rtx (Pmode
);
5914 rtx offset
= gen_reg_rtx (Pmode
);
5915 rtx vsrc
= gen_reg_rtx (V16QImode
);
5916 rtx vpos
= gen_reg_rtx (V16QImode
);
5917 rtx loadlen
= gen_reg_rtx (SImode
);
5918 rtx gpos_qi
= gen_reg_rtx(QImode
);
5919 rtx gpos
= gen_reg_rtx (SImode
);
5920 rtx done_label
= gen_label_rtx ();
5921 rtx loop_label
= gen_label_rtx ();
5922 rtx exit_label
= gen_label_rtx ();
5923 rtx full_label
= gen_label_rtx ();
5925 /* Perform a quick check for string ending on the first up to 16
5926 bytes and exit early if successful. */
5928 emit_insn (gen_vlbb (vsrc
, src
, GEN_INT (6)));
5929 emit_insn (gen_lcbb (loadlen
, src_addr
, GEN_INT (6)));
5930 emit_insn (gen_vfenezv16qi (vpos
, vsrc
, vsrc
));
5931 emit_insn (gen_vec_extractv16qiqi (gpos_qi
, vpos
, GEN_INT (7)));
5932 emit_move_insn (gpos
, gen_rtx_SUBREG (SImode
, gpos_qi
, 0));
5933 /* gpos is the byte index if a zero was found and 16 otherwise.
5934 So if it is lower than the loaded bytes we have a hit. */
5935 emit_cmp_and_jump_insns (gpos
, loadlen
, GE
, NULL_RTX
, SImode
, 1,
5937 emit_insn (gen_vstlv16qi (vsrc
, gpos
, dst
));
5939 force_expand_binop (Pmode
, add_optab
, dst_addr
, gpos
, result
,
5941 emit_jump (exit_label
);
5944 emit_label (full_label
);
5945 LABEL_NUSES (full_label
) = 1;
5947 /* Calculate `offset' so that src + offset points to the last byte
5948 before 16 byte alignment. */
5950 /* temp = src_addr & 0xf */
5951 force_expand_binop (Pmode
, and_optab
, src_addr
, GEN_INT (15), temp
,
5954 /* offset = 0xf - temp */
5955 emit_move_insn (offset
, GEN_INT (15));
5956 force_expand_binop (Pmode
, sub_optab
, offset
, temp
, offset
,
5959 /* Store `offset' bytes in the dstination string. The quick check
5960 has loaded at least `offset' bytes into vsrc. */
5962 emit_insn (gen_vstlv16qi (vsrc
, gen_lowpart (SImode
, offset
), dst
));
5964 /* Advance to the next byte to be loaded. */
5965 force_expand_binop (Pmode
, add_optab
, offset
, const1_rtx
, offset
,
5968 /* Make sure the addresses are single regs which can be used as a
5970 emit_move_insn (src_addr_reg
, src_addr
);
5971 emit_move_insn (dst_addr_reg
, dst_addr
);
5975 emit_label (loop_label
);
5976 LABEL_NUSES (loop_label
) = 1;
5978 emit_move_insn (vsrc
,
5979 gen_rtx_MEM (V16QImode
,
5980 gen_rtx_PLUS (Pmode
, src_addr_reg
, offset
)));
5982 emit_insn (gen_vec_vfenesv16qi (vpos
, vsrc
, vsrc
,
5983 GEN_INT (VSTRING_FLAG_ZS
| VSTRING_FLAG_CS
)));
5984 add_int_reg_note (s390_emit_ccraw_jump (8, EQ
, done_label
),
5985 REG_BR_PROB
, profile_probability::very_unlikely ()
5986 .to_reg_br_prob_note ());
5988 emit_move_insn (gen_rtx_MEM (V16QImode
,
5989 gen_rtx_PLUS (Pmode
, dst_addr_reg
, offset
)),
5992 force_expand_binop (Pmode
, add_optab
, offset
, GEN_INT (16),
5993 offset
, 1, OPTAB_DIRECT
);
5995 emit_jump (loop_label
);
6000 /* We are done. Add the offset of the zero character to the dst_addr
6001 pointer to get the result. */
6003 emit_label (done_label
);
6004 LABEL_NUSES (done_label
) = 1;
6006 force_expand_binop (Pmode
, add_optab
, dst_addr_reg
, offset
, dst_addr_reg
,
6009 emit_insn (gen_vec_extractv16qiqi (gpos_qi
, vpos
, GEN_INT (7)));
6010 emit_move_insn (gpos
, gen_rtx_SUBREG (SImode
, gpos_qi
, 0));
6012 emit_insn (gen_vstlv16qi (vsrc
, gpos
, gen_rtx_MEM (BLKmode
, dst_addr_reg
)));
6014 force_expand_binop (Pmode
, add_optab
, dst_addr_reg
, gpos
, result
,
6019 emit_label (exit_label
);
6020 LABEL_NUSES (exit_label
) = 1;
6024 /* Expand conditional increment or decrement using alc/slb instructions.
6025 Should generate code setting DST to either SRC or SRC + INCREMENT,
6026 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
6027 Returns true if successful, false otherwise.
6029 That makes it possible to implement some if-constructs without jumps e.g.:
6030 (borrow = CC0 | CC1 and carry = CC2 | CC3)
6031 unsigned int a, b, c;
6032 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
6033 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
6034 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
6035 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
6037 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
6038 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
6039 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
6040 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
6041 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
6044 s390_expand_addcc (enum rtx_code cmp_code
, rtx cmp_op0
, rtx cmp_op1
,
6045 rtx dst
, rtx src
, rtx increment
)
6047 machine_mode cmp_mode
;
6048 machine_mode cc_mode
;
6054 if ((GET_MODE (cmp_op0
) == SImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
6055 && (GET_MODE (cmp_op1
) == SImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
6057 else if ((GET_MODE (cmp_op0
) == DImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
6058 && (GET_MODE (cmp_op1
) == DImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
6063 /* Try ADD LOGICAL WITH CARRY. */
6064 if (increment
== const1_rtx
)
6066 /* Determine CC mode to use. */
6067 if (cmp_code
== EQ
|| cmp_code
== NE
)
6069 if (cmp_op1
!= const0_rtx
)
6071 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
6072 NULL_RTX
, 0, OPTAB_WIDEN
);
6073 cmp_op1
= const0_rtx
;
6076 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
6079 if (cmp_code
== LTU
|| cmp_code
== LEU
)
6084 cmp_code
= swap_condition (cmp_code
);
6101 /* Emit comparison instruction pattern. */
6102 if (!register_operand (cmp_op0
, cmp_mode
))
6103 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
6105 insn
= gen_rtx_SET (gen_rtx_REG (cc_mode
, CC_REGNUM
),
6106 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
6107 /* We use insn_invalid_p here to add clobbers if required. */
6108 ret
= insn_invalid_p (emit_insn (insn
), false);
6111 /* Emit ALC instruction pattern. */
6112 op_res
= gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
6113 gen_rtx_REG (cc_mode
, CC_REGNUM
),
6116 if (src
!= const0_rtx
)
6118 if (!register_operand (src
, GET_MODE (dst
)))
6119 src
= force_reg (GET_MODE (dst
), src
);
6121 op_res
= gen_rtx_PLUS (GET_MODE (dst
), op_res
, src
);
6122 op_res
= gen_rtx_PLUS (GET_MODE (dst
), op_res
, const0_rtx
);
6125 p
= rtvec_alloc (2);
6127 gen_rtx_SET (dst
, op_res
);
6129 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
6130 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
6135 /* Try SUBTRACT LOGICAL WITH BORROW. */
6136 if (increment
== constm1_rtx
)
6138 /* Determine CC mode to use. */
6139 if (cmp_code
== EQ
|| cmp_code
== NE
)
6141 if (cmp_op1
!= const0_rtx
)
6143 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
6144 NULL_RTX
, 0, OPTAB_WIDEN
);
6145 cmp_op1
= const0_rtx
;
6148 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
6151 if (cmp_code
== GTU
|| cmp_code
== GEU
)
6156 cmp_code
= swap_condition (cmp_code
);
6173 /* Emit comparison instruction pattern. */
6174 if (!register_operand (cmp_op0
, cmp_mode
))
6175 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
6177 insn
= gen_rtx_SET (gen_rtx_REG (cc_mode
, CC_REGNUM
),
6178 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
6179 /* We use insn_invalid_p here to add clobbers if required. */
6180 ret
= insn_invalid_p (emit_insn (insn
), false);
6183 /* Emit SLB instruction pattern. */
6184 if (!register_operand (src
, GET_MODE (dst
)))
6185 src
= force_reg (GET_MODE (dst
), src
);
6187 op_res
= gen_rtx_MINUS (GET_MODE (dst
),
6188 gen_rtx_MINUS (GET_MODE (dst
), src
, const0_rtx
),
6189 gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
6190 gen_rtx_REG (cc_mode
, CC_REGNUM
),
6192 p
= rtvec_alloc (2);
6194 gen_rtx_SET (dst
, op_res
);
6196 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
6197 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
6205 /* Expand code for the insv template. Return true if successful. */
6208 s390_expand_insv (rtx dest
, rtx op1
, rtx op2
, rtx src
)
6210 int bitsize
= INTVAL (op1
);
6211 int bitpos
= INTVAL (op2
);
6212 machine_mode mode
= GET_MODE (dest
);
6214 int smode_bsize
, mode_bsize
;
6217 if (bitsize
+ bitpos
> GET_MODE_BITSIZE (mode
))
6220 /* Generate INSERT IMMEDIATE (IILL et al). */
6221 /* (set (ze (reg)) (const_int)). */
6223 && register_operand (dest
, word_mode
)
6224 && (bitpos
% 16) == 0
6225 && (bitsize
% 16) == 0
6226 && const_int_operand (src
, VOIDmode
))
6228 HOST_WIDE_INT val
= INTVAL (src
);
6229 int regpos
= bitpos
+ bitsize
;
6231 while (regpos
> bitpos
)
6233 machine_mode putmode
;
6236 if (TARGET_EXTIMM
&& (regpos
% 32 == 0) && (regpos
>= bitpos
+ 32))
6241 putsize
= GET_MODE_BITSIZE (putmode
);
6243 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
,
6246 gen_int_mode (val
, putmode
));
6249 gcc_assert (regpos
== bitpos
);
6253 smode
= smallest_int_mode_for_size (bitsize
);
6254 smode_bsize
= GET_MODE_BITSIZE (smode
);
6255 mode_bsize
= GET_MODE_BITSIZE (mode
);
6257 /* Generate STORE CHARACTERS UNDER MASK (STCM et al). */
6259 && (bitsize
% BITS_PER_UNIT
) == 0
6261 && (register_operand (src
, word_mode
)
6262 || const_int_operand (src
, VOIDmode
)))
6264 /* Emit standard pattern if possible. */
6265 if (smode_bsize
== bitsize
)
6267 emit_move_insn (adjust_address (dest
, smode
, 0),
6268 gen_lowpart (smode
, src
));
6272 /* (set (ze (mem)) (const_int)). */
6273 else if (const_int_operand (src
, VOIDmode
))
6275 int size
= bitsize
/ BITS_PER_UNIT
;
6276 rtx src_mem
= adjust_address (force_const_mem (word_mode
, src
),
6278 UNITS_PER_WORD
- size
);
6280 dest
= adjust_address (dest
, BLKmode
, 0);
6281 set_mem_size (dest
, size
);
6282 s390_expand_movmem (dest
, src_mem
, GEN_INT (size
));
6286 /* (set (ze (mem)) (reg)). */
6287 else if (register_operand (src
, word_mode
))
6290 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
, op1
,
6294 /* Emit st,stcmh sequence. */
6295 int stcmh_width
= bitsize
- 32;
6296 int size
= stcmh_width
/ BITS_PER_UNIT
;
6298 emit_move_insn (adjust_address (dest
, SImode
, size
),
6299 gen_lowpart (SImode
, src
));
6300 set_mem_size (dest
, size
);
6301 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
,
6302 GEN_INT (stcmh_width
),
6304 gen_rtx_LSHIFTRT (word_mode
, src
, GEN_INT (32)));
6310 /* Generate INSERT CHARACTERS UNDER MASK (IC, ICM et al). */
6311 if ((bitpos
% BITS_PER_UNIT
) == 0
6312 && (bitsize
% BITS_PER_UNIT
) == 0
6313 && (bitpos
& 32) == ((bitpos
+ bitsize
- 1) & 32)
6315 && (mode
== DImode
|| mode
== SImode
)
6316 && register_operand (dest
, mode
))
6318 /* Emit a strict_low_part pattern if possible. */
6319 if (smode_bsize
== bitsize
&& bitpos
== mode_bsize
- smode_bsize
)
6321 op
= gen_rtx_STRICT_LOW_PART (VOIDmode
, gen_lowpart (smode
, dest
));
6322 op
= gen_rtx_SET (op
, gen_lowpart (smode
, src
));
6323 clobber
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
6324 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clobber
)));
6328 /* ??? There are more powerful versions of ICM that are not
6329 completely represented in the md file. */
6332 /* For z10, generate ROTATE THEN INSERT SELECTED BITS (RISBG et al). */
6333 if (TARGET_Z10
&& (mode
== DImode
|| mode
== SImode
))
6335 machine_mode mode_s
= GET_MODE (src
);
6337 if (CONSTANT_P (src
))
6339 /* For constant zero values the representation with AND
6340 appears to be folded in more situations than the (set
6341 (zero_extract) ...).
6342 We only do this when the start and end of the bitfield
6343 remain in the same SImode chunk. That way nihf or nilf
6345 The AND patterns might still generate a risbg for this. */
6346 if (src
== const0_rtx
&& bitpos
/ 32 == (bitpos
+ bitsize
- 1) / 32)
6349 src
= force_reg (mode
, src
);
6351 else if (mode_s
!= mode
)
6353 gcc_assert (GET_MODE_BITSIZE (mode_s
) >= bitsize
);
6354 src
= force_reg (mode_s
, src
);
6355 src
= gen_lowpart (mode
, src
);
6358 op
= gen_rtx_ZERO_EXTRACT (mode
, dest
, op1
, op2
),
6359 op
= gen_rtx_SET (op
, src
);
6363 clobber
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
6364 op
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clobber
));
6374 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
6375 register that holds VAL of mode MODE shifted by COUNT bits. */
6378 s390_expand_mask_and_shift (rtx val
, machine_mode mode
, rtx count
)
6380 val
= expand_simple_binop (SImode
, AND
, val
, GEN_INT (GET_MODE_MASK (mode
)),
6381 NULL_RTX
, 1, OPTAB_DIRECT
);
6382 return expand_simple_binop (SImode
, ASHIFT
, val
, count
,
6383 NULL_RTX
, 1, OPTAB_DIRECT
);
6386 /* Generate a vector comparison COND of CMP_OP1 and CMP_OP2 and store
6387 the result in TARGET. */
6390 s390_expand_vec_compare (rtx target
, enum rtx_code cond
,
6391 rtx cmp_op1
, rtx cmp_op2
)
6393 machine_mode mode
= GET_MODE (target
);
6394 bool neg_p
= false, swap_p
= false;
6397 if (GET_MODE_CLASS (GET_MODE (cmp_op1
)) == MODE_VECTOR_FLOAT
)
6401 /* NE a != b -> !(a == b) */
6402 case NE
: cond
= EQ
; neg_p
= true; break;
6403 /* UNGT a u> b -> !(b >= a) */
6404 case UNGT
: cond
= GE
; neg_p
= true; swap_p
= true; break;
6405 /* UNGE a u>= b -> !(b > a) */
6406 case UNGE
: cond
= GT
; neg_p
= true; swap_p
= true; break;
6407 /* LE: a <= b -> b >= a */
6408 case LE
: cond
= GE
; swap_p
= true; break;
6409 /* UNLE: a u<= b -> !(a > b) */
6410 case UNLE
: cond
= GT
; neg_p
= true; break;
6411 /* LT: a < b -> b > a */
6412 case LT
: cond
= GT
; swap_p
= true; break;
6413 /* UNLT: a u< b -> !(a >= b) */
6414 case UNLT
: cond
= GE
; neg_p
= true; break;
6416 emit_insn (gen_vec_cmpuneq (target
, cmp_op1
, cmp_op2
));
6419 emit_insn (gen_vec_cmpltgt (target
, cmp_op1
, cmp_op2
));
6422 emit_insn (gen_vec_ordered (target
, cmp_op1
, cmp_op2
));
6425 emit_insn (gen_vec_unordered (target
, cmp_op1
, cmp_op2
));
6434 /* NE: a != b -> !(a == b) */
6435 case NE
: cond
= EQ
; neg_p
= true; break;
6436 /* GE: a >= b -> !(b > a) */
6437 case GE
: cond
= GT
; neg_p
= true; swap_p
= true; break;
6438 /* GEU: a >= b -> !(b > a) */
6439 case GEU
: cond
= GTU
; neg_p
= true; swap_p
= true; break;
6440 /* LE: a <= b -> !(a > b) */
6441 case LE
: cond
= GT
; neg_p
= true; break;
6442 /* LEU: a <= b -> !(a > b) */
6443 case LEU
: cond
= GTU
; neg_p
= true; break;
6444 /* LT: a < b -> b > a */
6445 case LT
: cond
= GT
; swap_p
= true; break;
6446 /* LTU: a < b -> b > a */
6447 case LTU
: cond
= GTU
; swap_p
= true; break;
6454 tmp
= cmp_op1
; cmp_op1
= cmp_op2
; cmp_op2
= tmp
;
6457 emit_insn (gen_rtx_SET (target
, gen_rtx_fmt_ee (cond
,
6459 cmp_op1
, cmp_op2
)));
6461 emit_insn (gen_rtx_SET (target
, gen_rtx_NOT (mode
, target
)));
6464 /* Expand the comparison CODE of CMP1 and CMP2 and copy 1 or 0 into
6465 TARGET if either all (ALL_P is true) or any (ALL_P is false) of the
6466 elements in CMP1 and CMP2 fulfill the comparison.
6467 This function is only used to emit patterns for the vx builtins and
6468 therefore only handles comparison codes required by the
6471 s390_expand_vec_compare_cc (rtx target
, enum rtx_code code
,
6472 rtx cmp1
, rtx cmp2
, bool all_p
)
6474 machine_mode cc_producer_mode
, cc_consumer_mode
, scratch_mode
;
6475 rtx tmp_reg
= gen_reg_rtx (SImode
);
6476 bool swap_p
= false;
6478 if (GET_MODE_CLASS (GET_MODE (cmp1
)) == MODE_VECTOR_INT
)
6484 cc_producer_mode
= CCVEQmode
;
6488 code
= swap_condition (code
);
6493 cc_producer_mode
= CCVIHmode
;
6497 code
= swap_condition (code
);
6502 cc_producer_mode
= CCVIHUmode
;
6508 scratch_mode
= GET_MODE (cmp1
);
6509 /* These codes represent inverted CC interpretations. Inverting
6510 an ALL CC mode results in an ANY CC mode and the other way
6511 around. Invert the all_p flag here to compensate for
6513 if (code
== NE
|| code
== LE
|| code
== LEU
)
6516 cc_consumer_mode
= all_p
? CCVIALLmode
: CCVIANYmode
;
6518 else if (GET_MODE_CLASS (GET_MODE (cmp1
)) == MODE_VECTOR_FLOAT
)
6524 case EQ
: cc_producer_mode
= CCVEQmode
; break;
6525 case NE
: cc_producer_mode
= CCVEQmode
; inv_p
= true; break;
6526 case GT
: cc_producer_mode
= CCVFHmode
; break;
6527 case GE
: cc_producer_mode
= CCVFHEmode
; break;
6528 case UNLE
: cc_producer_mode
= CCVFHmode
; inv_p
= true; break;
6529 case UNLT
: cc_producer_mode
= CCVFHEmode
; inv_p
= true; break;
6530 case LT
: cc_producer_mode
= CCVFHmode
; code
= GT
; swap_p
= true; break;
6531 case LE
: cc_producer_mode
= CCVFHEmode
; code
= GE
; swap_p
= true; break;
6532 default: gcc_unreachable ();
6534 scratch_mode
= mode_for_int_vector (GET_MODE (cmp1
)).require ();
6539 cc_consumer_mode
= all_p
? CCVFALLmode
: CCVFANYmode
;
6551 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
6552 gen_rtvec (2, gen_rtx_SET (
6553 gen_rtx_REG (cc_producer_mode
, CC_REGNUM
),
6554 gen_rtx_COMPARE (cc_producer_mode
, cmp1
, cmp2
)),
6555 gen_rtx_CLOBBER (VOIDmode
,
6556 gen_rtx_SCRATCH (scratch_mode
)))));
6557 emit_move_insn (target
, const0_rtx
);
6558 emit_move_insn (tmp_reg
, const1_rtx
);
6560 emit_move_insn (target
,
6561 gen_rtx_IF_THEN_ELSE (SImode
,
6562 gen_rtx_fmt_ee (code
, VOIDmode
,
6563 gen_rtx_REG (cc_consumer_mode
, CC_REGNUM
),
6568 /* Invert the comparison CODE applied to a CC mode. This is only safe
6569 if we know whether there result was created by a floating point
6570 compare or not. For the CCV modes this is encoded as part of the
6573 s390_reverse_condition (machine_mode mode
, enum rtx_code code
)
6575 /* Reversal of FP compares takes care -- an ordered compare
6576 becomes an unordered compare and vice versa. */
6577 if (mode
== CCVFALLmode
|| mode
== CCVFANYmode
)
6578 return reverse_condition_maybe_unordered (code
);
6579 else if (mode
== CCVIALLmode
|| mode
== CCVIANYmode
)
6580 return reverse_condition (code
);
6585 /* Generate a vector comparison expression loading either elements of
6586 THEN or ELS into TARGET depending on the comparison COND of CMP_OP1
6590 s390_expand_vcond (rtx target
, rtx then
, rtx els
,
6591 enum rtx_code cond
, rtx cmp_op1
, rtx cmp_op2
)
6594 machine_mode result_mode
;
6597 machine_mode target_mode
= GET_MODE (target
);
6598 machine_mode cmp_mode
= GET_MODE (cmp_op1
);
6599 rtx op
= (cond
== LT
) ? els
: then
;
6601 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
6602 and x < 0 ? 1 : 0 into (unsigned) x >> 31. Likewise
6603 for short and byte (x >> 15 and x >> 7 respectively). */
6604 if ((cond
== LT
|| cond
== GE
)
6605 && target_mode
== cmp_mode
6606 && cmp_op2
== CONST0_RTX (cmp_mode
)
6607 && op
== CONST0_RTX (target_mode
)
6608 && s390_vector_mode_supported_p (target_mode
)
6609 && GET_MODE_CLASS (target_mode
) == MODE_VECTOR_INT
)
6611 rtx negop
= (cond
== LT
) ? then
: els
;
6613 int shift
= GET_MODE_BITSIZE (GET_MODE_INNER (target_mode
)) - 1;
6615 /* if x < 0 ? 1 : 0 or if x >= 0 ? 0 : 1 */
6616 if (negop
== CONST1_RTX (target_mode
))
6618 rtx res
= expand_simple_binop (cmp_mode
, LSHIFTRT
, cmp_op1
,
6619 GEN_INT (shift
), target
,
6622 emit_move_insn (target
, res
);
6626 /* if x < 0 ? -1 : 0 or if x >= 0 ? 0 : -1 */
6627 else if (all_ones_operand (negop
, target_mode
))
6629 rtx res
= expand_simple_binop (cmp_mode
, ASHIFTRT
, cmp_op1
,
6630 GEN_INT (shift
), target
,
6633 emit_move_insn (target
, res
);
6638 /* We always use an integral type vector to hold the comparison
6640 result_mode
= mode_for_int_vector (cmp_mode
).require ();
6641 result_target
= gen_reg_rtx (result_mode
);
6643 /* We allow vector immediates as comparison operands that
6644 can be handled by the optimization above but not by the
6645 following code. Hence, force them into registers here. */
6646 if (!REG_P (cmp_op1
))
6647 cmp_op1
= force_reg (GET_MODE (cmp_op1
), cmp_op1
);
6649 if (!REG_P (cmp_op2
))
6650 cmp_op2
= force_reg (GET_MODE (cmp_op2
), cmp_op2
);
6652 s390_expand_vec_compare (result_target
, cond
,
6655 /* If the results are supposed to be either -1 or 0 we are done
6656 since this is what our compare instructions generate anyway. */
6657 if (all_ones_operand (then
, GET_MODE (then
))
6658 && const0_operand (els
, GET_MODE (els
)))
6660 emit_move_insn (target
, gen_rtx_SUBREG (target_mode
,
6665 /* Otherwise we will do a vsel afterwards. */
6666 /* This gets triggered e.g.
6667 with gcc.c-torture/compile/pr53410-1.c */
6669 then
= force_reg (target_mode
, then
);
6672 els
= force_reg (target_mode
, els
);
6674 tmp
= gen_rtx_fmt_ee (EQ
, VOIDmode
,
6676 CONST0_RTX (result_mode
));
6678 /* We compared the result against zero above so we have to swap then
6680 tmp
= gen_rtx_IF_THEN_ELSE (target_mode
, tmp
, els
, then
);
6682 gcc_assert (target_mode
== GET_MODE (then
));
6683 emit_insn (gen_rtx_SET (target
, tmp
));
6686 /* Emit the RTX necessary to initialize the vector TARGET with values
6689 s390_expand_vec_init (rtx target
, rtx vals
)
6691 machine_mode mode
= GET_MODE (target
);
6692 machine_mode inner_mode
= GET_MODE_INNER (mode
);
6693 int n_elts
= GET_MODE_NUNITS (mode
);
6694 bool all_same
= true, all_regs
= true, all_const_int
= true;
6698 for (i
= 0; i
< n_elts
; ++i
)
6700 x
= XVECEXP (vals
, 0, i
);
6702 if (!CONST_INT_P (x
))
6703 all_const_int
= false;
6705 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
6712 /* Use vector gen mask or vector gen byte mask if possible. */
6713 if (all_same
&& all_const_int
6714 && (XVECEXP (vals
, 0, 0) == const0_rtx
6715 || s390_contiguous_bitmask_vector_p (XVECEXP (vals
, 0, 0),
6717 || s390_bytemask_vector_p (XVECEXP (vals
, 0, 0), NULL
)))
6719 emit_insn (gen_rtx_SET (target
,
6720 gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0))));
6726 emit_insn (gen_rtx_SET (target
,
6727 gen_rtx_VEC_DUPLICATE (mode
,
6728 XVECEXP (vals
, 0, 0))));
6735 && GET_MODE_SIZE (inner_mode
) == 8)
6737 /* Use vector load pair. */
6738 emit_insn (gen_rtx_SET (target
,
6739 gen_rtx_VEC_CONCAT (mode
,
6740 XVECEXP (vals
, 0, 0),
6741 XVECEXP (vals
, 0, 1))));
6745 /* Use vector load logical element and zero. */
6746 if (TARGET_VXE
&& (mode
== V4SImode
|| mode
== V4SFmode
))
6750 x
= XVECEXP (vals
, 0, 0);
6751 if (memory_operand (x
, inner_mode
))
6753 for (i
= 1; i
< n_elts
; ++i
)
6754 found
= found
&& XVECEXP (vals
, 0, i
) == const0_rtx
;
6758 machine_mode half_mode
= (inner_mode
== SFmode
6759 ? V2SFmode
: V2SImode
);
6760 emit_insn (gen_rtx_SET (target
,
6761 gen_rtx_VEC_CONCAT (mode
,
6762 gen_rtx_VEC_CONCAT (half_mode
,
6765 gen_rtx_VEC_CONCAT (half_mode
,
6773 /* We are about to set the vector elements one by one. Zero out the
6774 full register first in order to help the data flow framework to
6775 detect it as full VR set. */
6776 emit_insn (gen_rtx_SET (target
, CONST0_RTX (mode
)));
6778 /* Unfortunately the vec_init expander is not allowed to fail. So
6779 we have to implement the fallback ourselves. */
6780 for (i
= 0; i
< n_elts
; i
++)
6782 rtx elem
= XVECEXP (vals
, 0, i
);
6783 if (!general_operand (elem
, GET_MODE (elem
)))
6784 elem
= force_reg (inner_mode
, elem
);
6786 emit_insn (gen_rtx_SET (target
,
6787 gen_rtx_UNSPEC (mode
,
6789 GEN_INT (i
), target
),
6794 /* Structure to hold the initial parameters for a compare_and_swap operation
6795 in HImode and QImode. */
6797 struct alignment_context
6799 rtx memsi
; /* SI aligned memory location. */
6800 rtx shift
; /* Bit offset with regard to lsb. */
6801 rtx modemask
; /* Mask of the HQImode shifted by SHIFT bits. */
6802 rtx modemaski
; /* ~modemask */
6803 bool aligned
; /* True if memory is aligned, false else. */
6806 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
6807 structure AC for transparent simplifying, if the memory alignment is known
6808 to be at least 32bit. MEM is the memory location for the actual operation
6809 and MODE its mode. */
6812 init_alignment_context (struct alignment_context
*ac
, rtx mem
,
6815 ac
->shift
= GEN_INT (GET_MODE_SIZE (SImode
) - GET_MODE_SIZE (mode
));
6816 ac
->aligned
= (MEM_ALIGN (mem
) >= GET_MODE_BITSIZE (SImode
));
6819 ac
->memsi
= adjust_address (mem
, SImode
, 0); /* Memory is aligned. */
6822 /* Alignment is unknown. */
6823 rtx byteoffset
, addr
, align
;
6825 /* Force the address into a register. */
6826 addr
= force_reg (Pmode
, XEXP (mem
, 0));
6828 /* Align it to SImode. */
6829 align
= expand_simple_binop (Pmode
, AND
, addr
,
6830 GEN_INT (-GET_MODE_SIZE (SImode
)),
6831 NULL_RTX
, 1, OPTAB_DIRECT
);
6833 ac
->memsi
= gen_rtx_MEM (SImode
, align
);
6834 MEM_VOLATILE_P (ac
->memsi
) = MEM_VOLATILE_P (mem
);
6835 set_mem_alias_set (ac
->memsi
, ALIAS_SET_MEMORY_BARRIER
);
6836 set_mem_align (ac
->memsi
, GET_MODE_BITSIZE (SImode
));
6838 /* Calculate shiftcount. */
6839 byteoffset
= expand_simple_binop (Pmode
, AND
, addr
,
6840 GEN_INT (GET_MODE_SIZE (SImode
) - 1),
6841 NULL_RTX
, 1, OPTAB_DIRECT
);
6842 /* As we already have some offset, evaluate the remaining distance. */
6843 ac
->shift
= expand_simple_binop (SImode
, MINUS
, ac
->shift
, byteoffset
,
6844 NULL_RTX
, 1, OPTAB_DIRECT
);
6847 /* Shift is the byte count, but we need the bitcount. */
6848 ac
->shift
= expand_simple_binop (SImode
, ASHIFT
, ac
->shift
, GEN_INT (3),
6849 NULL_RTX
, 1, OPTAB_DIRECT
);
6851 /* Calculate masks. */
6852 ac
->modemask
= expand_simple_binop (SImode
, ASHIFT
,
6853 GEN_INT (GET_MODE_MASK (mode
)),
6854 ac
->shift
, NULL_RTX
, 1, OPTAB_DIRECT
);
6855 ac
->modemaski
= expand_simple_unop (SImode
, NOT
, ac
->modemask
,
6859 /* A subroutine of s390_expand_cs_hqi. Insert INS into VAL. If possible,
6860 use a single insv insn into SEQ2. Otherwise, put prep insns in SEQ1 and
6861 perform the merge in SEQ2. */
6864 s390_two_part_insv (struct alignment_context
*ac
, rtx
*seq1
, rtx
*seq2
,
6865 machine_mode mode
, rtx val
, rtx ins
)
6872 tmp
= copy_to_mode_reg (SImode
, val
);
6873 if (s390_expand_insv (tmp
, GEN_INT (GET_MODE_BITSIZE (mode
)),
6877 *seq2
= get_insns ();
6884 /* Failed to use insv. Generate a two part shift and mask. */
6886 tmp
= s390_expand_mask_and_shift (ins
, mode
, ac
->shift
);
6887 *seq1
= get_insns ();
6891 tmp
= expand_simple_binop (SImode
, IOR
, tmp
, val
, NULL_RTX
, 1, OPTAB_DIRECT
);
6892 *seq2
= get_insns ();
6898 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
6899 the memory location, CMP the old value to compare MEM with and NEW_RTX the
6900 value to set if CMP == MEM. */
6903 s390_expand_cs_hqi (machine_mode mode
, rtx btarget
, rtx vtarget
, rtx mem
,
6904 rtx cmp
, rtx new_rtx
, bool is_weak
)
6906 struct alignment_context ac
;
6907 rtx cmpv
, newv
, val
, cc
, seq0
, seq1
, seq2
, seq3
;
6908 rtx res
= gen_reg_rtx (SImode
);
6909 rtx_code_label
*csloop
= NULL
, *csend
= NULL
;
6911 gcc_assert (MEM_P (mem
));
6913 init_alignment_context (&ac
, mem
, mode
);
6915 /* Load full word. Subsequent loads are performed by CS. */
6916 val
= expand_simple_binop (SImode
, AND
, ac
.memsi
, ac
.modemaski
,
6917 NULL_RTX
, 1, OPTAB_DIRECT
);
6919 /* Prepare insertions of cmp and new_rtx into the loaded value. When
6920 possible, we try to use insv to make this happen efficiently. If
6921 that fails we'll generate code both inside and outside the loop. */
6922 cmpv
= s390_two_part_insv (&ac
, &seq0
, &seq2
, mode
, val
, cmp
);
6923 newv
= s390_two_part_insv (&ac
, &seq1
, &seq3
, mode
, val
, new_rtx
);
6930 /* Start CS loop. */
6933 /* Begin assuming success. */
6934 emit_move_insn (btarget
, const1_rtx
);
6936 csloop
= gen_label_rtx ();
6937 csend
= gen_label_rtx ();
6938 emit_label (csloop
);
6941 /* val = "<mem>00..0<mem>"
6942 * cmp = "00..0<cmp>00..0"
6943 * new = "00..0<new>00..0"
6949 cc
= s390_emit_compare_and_swap (EQ
, res
, ac
.memsi
, cmpv
, newv
, CCZ1mode
);
6951 emit_insn (gen_cstorecc4 (btarget
, cc
, XEXP (cc
, 0), XEXP (cc
, 1)));
6956 /* Jump to end if we're done (likely?). */
6957 s390_emit_jump (csend
, cc
);
6959 /* Check for changes outside mode, and loop internal if so.
6960 Arrange the moves so that the compare is adjacent to the
6961 branch so that we can generate CRJ. */
6962 tmp
= copy_to_reg (val
);
6963 force_expand_binop (SImode
, and_optab
, res
, ac
.modemaski
, val
,
6965 cc
= s390_emit_compare (NE
, val
, tmp
);
6966 s390_emit_jump (csloop
, cc
);
6969 emit_move_insn (btarget
, const0_rtx
);
6973 /* Return the correct part of the bitfield. */
6974 convert_move (vtarget
, expand_simple_binop (SImode
, LSHIFTRT
, res
, ac
.shift
,
6975 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
6978 /* Variant of s390_expand_cs for SI, DI and TI modes. */
6980 s390_expand_cs_tdsi (machine_mode mode
, rtx btarget
, rtx vtarget
, rtx mem
,
6981 rtx cmp
, rtx new_rtx
, bool is_weak
)
6983 rtx output
= vtarget
;
6984 rtx_code_label
*skip_cs_label
= NULL
;
6985 bool do_const_opt
= false;
6987 if (!register_operand (output
, mode
))
6988 output
= gen_reg_rtx (mode
);
6990 /* If IS_WEAK is true and the INPUT value is a constant, compare the memory
6991 with the constant first and skip the compare_and_swap because its very
6992 expensive and likely to fail anyway.
6993 Note 1: This is done only for IS_WEAK. C11 allows optimizations that may
6994 cause spurious in that case.
6995 Note 2: It may be useful to do this also for non-constant INPUT.
6996 Note 3: Currently only targets with "load on condition" are supported
6997 (z196 and newer). */
7000 && (mode
== SImode
|| mode
== DImode
))
7001 do_const_opt
= (is_weak
&& CONST_INT_P (cmp
));
7005 rtx cc
= gen_rtx_REG (CCZmode
, CC_REGNUM
);
7007 skip_cs_label
= gen_label_rtx ();
7008 emit_move_insn (btarget
, const0_rtx
);
7009 if (CONST_INT_P (cmp
) && INTVAL (cmp
) == 0)
7011 rtvec lt
= rtvec_alloc (2);
7013 /* Load-and-test + conditional jump. */
7015 = gen_rtx_SET (cc
, gen_rtx_COMPARE (CCZmode
, mem
, cmp
));
7016 RTVEC_ELT (lt
, 1) = gen_rtx_SET (output
, mem
);
7017 emit_insn (gen_rtx_PARALLEL (VOIDmode
, lt
));
7021 emit_move_insn (output
, mem
);
7022 emit_insn (gen_rtx_SET (cc
, gen_rtx_COMPARE (CCZmode
, output
, cmp
)));
7024 s390_emit_jump (skip_cs_label
, gen_rtx_NE (VOIDmode
, cc
, const0_rtx
));
7025 add_reg_br_prob_note (get_last_insn (),
7026 profile_probability::very_unlikely ());
7027 /* If the jump is not taken, OUTPUT is the expected value. */
7029 /* Reload newval to a register manually, *after* the compare and jump
7030 above. Otherwise Reload might place it before the jump. */
7033 cmp
= force_reg (mode
, cmp
);
7034 new_rtx
= force_reg (mode
, new_rtx
);
7035 s390_emit_compare_and_swap (EQ
, output
, mem
, cmp
, new_rtx
,
7036 (do_const_opt
) ? CCZmode
: CCZ1mode
);
7037 if (skip_cs_label
!= NULL
)
7038 emit_label (skip_cs_label
);
7040 /* We deliberately accept non-register operands in the predicate
7041 to ensure the write back to the output operand happens *before*
7042 the store-flags code below. This makes it easier for combine
7043 to merge the store-flags code with a potential test-and-branch
7044 pattern following (immediately!) afterwards. */
7045 if (output
!= vtarget
)
7046 emit_move_insn (vtarget
, output
);
7052 /* Do not use gen_cstorecc4 here because it writes either 1 or 0, but
7053 btarget has already been initialized with 0 above. */
7054 cc
= gen_rtx_REG (CCZmode
, CC_REGNUM
);
7055 cond
= gen_rtx_EQ (VOIDmode
, cc
, const0_rtx
);
7056 ite
= gen_rtx_IF_THEN_ELSE (SImode
, cond
, const1_rtx
, btarget
);
7057 emit_insn (gen_rtx_SET (btarget
, ite
));
7063 cc
= gen_rtx_REG (CCZ1mode
, CC_REGNUM
);
7064 cond
= gen_rtx_EQ (SImode
, cc
, const0_rtx
);
7065 emit_insn (gen_cstorecc4 (btarget
, cond
, cc
, const0_rtx
));
7069 /* Expand an atomic compare and swap operation. MEM is the memory location,
7070 CMP the old value to compare MEM with and NEW_RTX the value to set if
7074 s390_expand_cs (machine_mode mode
, rtx btarget
, rtx vtarget
, rtx mem
,
7075 rtx cmp
, rtx new_rtx
, bool is_weak
)
7082 s390_expand_cs_tdsi (mode
, btarget
, vtarget
, mem
, cmp
, new_rtx
, is_weak
);
7086 s390_expand_cs_hqi (mode
, btarget
, vtarget
, mem
, cmp
, new_rtx
, is_weak
);
7093 /* Expand an atomic_exchange operation simulated with a compare-and-swap loop.
7094 The memory location MEM is set to INPUT. OUTPUT is set to the previous value
7098 s390_expand_atomic_exchange_tdsi (rtx output
, rtx mem
, rtx input
)
7100 machine_mode mode
= GET_MODE (mem
);
7101 rtx_code_label
*csloop
;
7104 && (mode
== DImode
|| mode
== SImode
)
7105 && CONST_INT_P (input
) && INTVAL (input
) == 0)
7107 emit_move_insn (output
, const0_rtx
);
7109 emit_insn (gen_atomic_fetch_anddi (output
, mem
, const0_rtx
, input
));
7111 emit_insn (gen_atomic_fetch_andsi (output
, mem
, const0_rtx
, input
));
7115 input
= force_reg (mode
, input
);
7116 emit_move_insn (output
, mem
);
7117 csloop
= gen_label_rtx ();
7118 emit_label (csloop
);
7119 s390_emit_jump (csloop
, s390_emit_compare_and_swap (NE
, output
, mem
, output
,
7123 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
7124 and VAL the value to play with. If AFTER is true then store the value
7125 MEM holds after the operation, if AFTER is false then store the value MEM
7126 holds before the operation. If TARGET is zero then discard that value, else
7127 store it to TARGET. */
7130 s390_expand_atomic (machine_mode mode
, enum rtx_code code
,
7131 rtx target
, rtx mem
, rtx val
, bool after
)
7133 struct alignment_context ac
;
7135 rtx new_rtx
= gen_reg_rtx (SImode
);
7136 rtx orig
= gen_reg_rtx (SImode
);
7137 rtx_code_label
*csloop
= gen_label_rtx ();
7139 gcc_assert (!target
|| register_operand (target
, VOIDmode
));
7140 gcc_assert (MEM_P (mem
));
7142 init_alignment_context (&ac
, mem
, mode
);
7144 /* Shift val to the correct bit positions.
7145 Preserve "icm", but prevent "ex icm". */
7146 if (!(ac
.aligned
&& code
== SET
&& MEM_P (val
)))
7147 val
= s390_expand_mask_and_shift (val
, mode
, ac
.shift
);
7149 /* Further preparation insns. */
7150 if (code
== PLUS
|| code
== MINUS
)
7151 emit_move_insn (orig
, val
);
7152 else if (code
== MULT
|| code
== AND
) /* val = "11..1<val>11..1" */
7153 val
= expand_simple_binop (SImode
, XOR
, val
, ac
.modemaski
,
7154 NULL_RTX
, 1, OPTAB_DIRECT
);
7156 /* Load full word. Subsequent loads are performed by CS. */
7157 cmp
= force_reg (SImode
, ac
.memsi
);
7159 /* Start CS loop. */
7160 emit_label (csloop
);
7161 emit_move_insn (new_rtx
, cmp
);
7163 /* Patch new with val at correct position. */
7168 val
= expand_simple_binop (SImode
, code
, new_rtx
, orig
,
7169 NULL_RTX
, 1, OPTAB_DIRECT
);
7170 val
= expand_simple_binop (SImode
, AND
, val
, ac
.modemask
,
7171 NULL_RTX
, 1, OPTAB_DIRECT
);
7174 if (ac
.aligned
&& MEM_P (val
))
7175 store_bit_field (new_rtx
, GET_MODE_BITSIZE (mode
), 0,
7176 0, 0, SImode
, val
, false);
7179 new_rtx
= expand_simple_binop (SImode
, AND
, new_rtx
, ac
.modemaski
,
7180 NULL_RTX
, 1, OPTAB_DIRECT
);
7181 new_rtx
= expand_simple_binop (SImode
, IOR
, new_rtx
, val
,
7182 NULL_RTX
, 1, OPTAB_DIRECT
);
7188 new_rtx
= expand_simple_binop (SImode
, code
, new_rtx
, val
,
7189 NULL_RTX
, 1, OPTAB_DIRECT
);
7191 case MULT
: /* NAND */
7192 new_rtx
= expand_simple_binop (SImode
, AND
, new_rtx
, val
,
7193 NULL_RTX
, 1, OPTAB_DIRECT
);
7194 new_rtx
= expand_simple_binop (SImode
, XOR
, new_rtx
, ac
.modemask
,
7195 NULL_RTX
, 1, OPTAB_DIRECT
);
7201 s390_emit_jump (csloop
, s390_emit_compare_and_swap (NE
, cmp
,
7202 ac
.memsi
, cmp
, new_rtx
,
7205 /* Return the correct part of the bitfield. */
7207 convert_move (target
, expand_simple_binop (SImode
, LSHIFTRT
,
7208 after
? new_rtx
: cmp
, ac
.shift
,
7209 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
7212 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
7213 We need to emit DTP-relative relocations. */
7215 static void s390_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
7218 s390_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
7223 fputs ("\t.long\t", file
);
7226 fputs ("\t.quad\t", file
);
7231 output_addr_const (file
, x
);
7232 fputs ("@DTPOFF", file
);
7235 /* Return the proper mode for REGNO being represented in the dwarf
7238 s390_dwarf_frame_reg_mode (int regno
)
7240 machine_mode save_mode
= default_dwarf_frame_reg_mode (regno
);
7242 /* Make sure not to return DImode for any GPR with -m31 -mzarch. */
7243 if (GENERAL_REGNO_P (regno
))
7246 /* The rightmost 64 bits of vector registers are call-clobbered. */
7247 if (GET_MODE_SIZE (save_mode
) > 8)
7253 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
7254 /* Implement TARGET_MANGLE_TYPE. */
7257 s390_mangle_type (const_tree type
)
7259 type
= TYPE_MAIN_VARIANT (type
);
7261 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
7262 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
7265 if (type
== s390_builtin_types
[BT_BV16QI
]) return "U6__boolc";
7266 if (type
== s390_builtin_types
[BT_BV8HI
]) return "U6__bools";
7267 if (type
== s390_builtin_types
[BT_BV4SI
]) return "U6__booli";
7268 if (type
== s390_builtin_types
[BT_BV2DI
]) return "U6__booll";
7270 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
7271 && TARGET_LONG_DOUBLE_128
)
7274 /* For all other types, use normal C++ mangling. */
7279 /* In the name of slightly smaller debug output, and to cater to
7280 general assembler lossage, recognize various UNSPEC sequences
7281 and turn them back into a direct symbol reference. */
7284 s390_delegitimize_address (rtx orig_x
)
7288 orig_x
= delegitimize_mem_from_attrs (orig_x
);
7291 /* Extract the symbol ref from:
7292 (plus:SI (reg:SI 12 %r12)
7293 (const:SI (unspec:SI [(symbol_ref/f:SI ("*.LC0"))]
7294 UNSPEC_GOTOFF/PLTOFF)))
7296 (plus:SI (reg:SI 12 %r12)
7297 (const:SI (plus:SI (unspec:SI [(symbol_ref:SI ("L"))]
7298 UNSPEC_GOTOFF/PLTOFF)
7299 (const_int 4 [0x4])))) */
7300 if (GET_CODE (x
) == PLUS
7301 && REG_P (XEXP (x
, 0))
7302 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
7303 && GET_CODE (XEXP (x
, 1)) == CONST
)
7305 HOST_WIDE_INT offset
= 0;
7307 /* The const operand. */
7308 y
= XEXP (XEXP (x
, 1), 0);
7310 if (GET_CODE (y
) == PLUS
7311 && GET_CODE (XEXP (y
, 1)) == CONST_INT
)
7313 offset
= INTVAL (XEXP (y
, 1));
7317 if (GET_CODE (y
) == UNSPEC
7318 && (XINT (y
, 1) == UNSPEC_GOTOFF
7319 || XINT (y
, 1) == UNSPEC_PLTOFF
))
7320 return plus_constant (Pmode
, XVECEXP (y
, 0, 0), offset
);
7323 if (GET_CODE (x
) != MEM
)
7327 if (GET_CODE (x
) == PLUS
7328 && GET_CODE (XEXP (x
, 1)) == CONST
7329 && GET_CODE (XEXP (x
, 0)) == REG
7330 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
)
7332 y
= XEXP (XEXP (x
, 1), 0);
7333 if (GET_CODE (y
) == UNSPEC
7334 && XINT (y
, 1) == UNSPEC_GOT
)
7335 y
= XVECEXP (y
, 0, 0);
7339 else if (GET_CODE (x
) == CONST
)
7341 /* Extract the symbol ref from:
7342 (mem:QI (const:DI (unspec:DI [(symbol_ref:DI ("foo"))]
7343 UNSPEC_PLT/GOTENT))) */
7346 if (GET_CODE (y
) == UNSPEC
7347 && (XINT (y
, 1) == UNSPEC_GOTENT
7348 || XINT (y
, 1) == UNSPEC_PLT
))
7349 y
= XVECEXP (y
, 0, 0);
7356 if (GET_MODE (orig_x
) != Pmode
)
7358 if (GET_MODE (orig_x
) == BLKmode
)
7360 y
= lowpart_subreg (GET_MODE (orig_x
), y
, Pmode
);
7367 /* Output operand OP to stdio stream FILE.
7368 OP is an address (register + offset) which is not used to address data;
7369 instead the rightmost bits are interpreted as the value. */
7372 print_addrstyle_operand (FILE *file
, rtx op
)
7374 HOST_WIDE_INT offset
;
7377 /* Extract base register and offset. */
7378 if (!s390_decompose_addrstyle_without_index (op
, &base
, &offset
))
7384 gcc_assert (GET_CODE (base
) == REG
);
7385 gcc_assert (REGNO (base
) < FIRST_PSEUDO_REGISTER
);
7386 gcc_assert (REGNO_REG_CLASS (REGNO (base
)) == ADDR_REGS
);
7389 /* Offsets are constricted to twelve bits. */
7390 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
& ((1 << 12) - 1));
7392 fprintf (file
, "(%s)", reg_names
[REGNO (base
)]);
7395 /* Assigns the number of NOP halfwords to be emitted before and after the
7396 function label to *HW_BEFORE and *HW_AFTER. Both pointers must not be NULL.
7397 If hotpatching is disabled for the function, the values are set to zero.
7401 s390_function_num_hotpatch_hw (tree decl
,
7407 attr
= lookup_attribute ("hotpatch", DECL_ATTRIBUTES (decl
));
7409 /* Handle the arguments of the hotpatch attribute. The values
7410 specified via attribute might override the cmdline argument
7414 tree args
= TREE_VALUE (attr
);
7416 *hw_before
= TREE_INT_CST_LOW (TREE_VALUE (args
));
7417 *hw_after
= TREE_INT_CST_LOW (TREE_VALUE (TREE_CHAIN (args
)));
7421 /* Use the values specified by the cmdline arguments. */
7422 *hw_before
= s390_hotpatch_hw_before_label
;
7423 *hw_after
= s390_hotpatch_hw_after_label
;
7427 /* Write the current .machine and .machinemode specification to the assembler
7430 #ifdef HAVE_AS_MACHINE_MACHINEMODE
7432 s390_asm_output_machine_for_arch (FILE *asm_out_file
)
7434 fprintf (asm_out_file
, "\t.machinemode %s\n",
7435 (TARGET_ZARCH
) ? "zarch" : "esa");
7436 fprintf (asm_out_file
, "\t.machine \"%s",
7437 processor_table
[s390_arch
].binutils_name
);
7438 if (S390_USE_ARCHITECTURE_MODIFIERS
)
7442 cpu_flags
= processor_flags_table
[(int) s390_arch
];
7443 if (TARGET_HTM
&& !(cpu_flags
& PF_TX
))
7444 fprintf (asm_out_file
, "+htm");
7445 else if (!TARGET_HTM
&& (cpu_flags
& PF_TX
))
7446 fprintf (asm_out_file
, "+nohtm");
7447 if (TARGET_VX
&& !(cpu_flags
& PF_VX
))
7448 fprintf (asm_out_file
, "+vx");
7449 else if (!TARGET_VX
&& (cpu_flags
& PF_VX
))
7450 fprintf (asm_out_file
, "+novx");
7452 fprintf (asm_out_file
, "\"\n");
7455 /* Write an extra function header before the very start of the function. */
7458 s390_asm_output_function_prefix (FILE *asm_out_file
,
7459 const char *fnname ATTRIBUTE_UNUSED
)
7461 if (DECL_FUNCTION_SPECIFIC_TARGET (current_function_decl
) == NULL
)
7463 /* Since only the function specific options are saved but not the indications
7464 which options are set, it's too much work here to figure out which options
7465 have actually changed. Thus, generate .machine and .machinemode whenever a
7466 function has the target attribute or pragma. */
7467 fprintf (asm_out_file
, "\t.machinemode push\n");
7468 fprintf (asm_out_file
, "\t.machine push\n");
7469 s390_asm_output_machine_for_arch (asm_out_file
);
7472 /* Write an extra function footer after the very end of the function. */
7475 s390_asm_declare_function_size (FILE *asm_out_file
,
7476 const char *fnname
, tree decl
)
7478 if (!flag_inhibit_size_directive
)
7479 ASM_OUTPUT_MEASURED_SIZE (asm_out_file
, fnname
);
7480 if (DECL_FUNCTION_SPECIFIC_TARGET (decl
) == NULL
)
7482 fprintf (asm_out_file
, "\t.machine pop\n");
7483 fprintf (asm_out_file
, "\t.machinemode pop\n");
7487 /* Write the extra assembler code needed to declare a function properly. */
7490 s390_asm_output_function_label (FILE *asm_out_file
, const char *fname
,
7493 int hw_before
, hw_after
;
7495 s390_function_num_hotpatch_hw (decl
, &hw_before
, &hw_after
);
7498 unsigned int function_alignment
;
7501 /* Add a trampoline code area before the function label and initialize it
7502 with two-byte nop instructions. This area can be overwritten with code
7503 that jumps to a patched version of the function. */
7504 asm_fprintf (asm_out_file
, "\tnopr\t%%r0"
7505 "\t# pre-label NOPs for hotpatch (%d halfwords)\n",
7507 for (i
= 1; i
< hw_before
; i
++)
7508 fputs ("\tnopr\t%r0\n", asm_out_file
);
7510 /* Note: The function label must be aligned so that (a) the bytes of the
7511 following nop do not cross a cacheline boundary, and (b) a jump address
7512 (eight bytes for 64 bit targets, 4 bytes for 32 bit targets) can be
7513 stored directly before the label without crossing a cacheline
7514 boundary. All this is necessary to make sure the trampoline code can
7515 be changed atomically.
7516 This alignment is done automatically using the FOUNCTION_BOUNDARY, but
7517 if there are NOPs before the function label, the alignment is placed
7518 before them. So it is necessary to duplicate the alignment after the
7520 function_alignment
= MAX (8, DECL_ALIGN (decl
) / BITS_PER_UNIT
);
7521 if (! DECL_USER_ALIGN (decl
))
7522 function_alignment
= MAX (function_alignment
,
7523 (unsigned int) align_functions
);
7524 fputs ("\t# alignment for hotpatch\n", asm_out_file
);
7525 ASM_OUTPUT_ALIGN (asm_out_file
, floor_log2 (function_alignment
));
7528 if (S390_USE_TARGET_ATTRIBUTE
&& TARGET_DEBUG_ARG
)
7530 asm_fprintf (asm_out_file
, "\t# fn:%s ar%d\n", fname
, s390_arch
);
7531 asm_fprintf (asm_out_file
, "\t# fn:%s tu%d\n", fname
, s390_tune
);
7532 asm_fprintf (asm_out_file
, "\t# fn:%s sg%d\n", fname
, s390_stack_guard
);
7533 asm_fprintf (asm_out_file
, "\t# fn:%s ss%d\n", fname
, s390_stack_size
);
7534 asm_fprintf (asm_out_file
, "\t# fn:%s bc%d\n", fname
, s390_branch_cost
);
7535 asm_fprintf (asm_out_file
, "\t# fn:%s wf%d\n", fname
,
7536 s390_warn_framesize
);
7537 asm_fprintf (asm_out_file
, "\t# fn:%s ba%d\n", fname
, TARGET_BACKCHAIN
);
7538 asm_fprintf (asm_out_file
, "\t# fn:%s hd%d\n", fname
, TARGET_HARD_DFP
);
7539 asm_fprintf (asm_out_file
, "\t# fn:%s hf%d\n", fname
, !TARGET_SOFT_FLOAT
);
7540 asm_fprintf (asm_out_file
, "\t# fn:%s ht%d\n", fname
, TARGET_OPT_HTM
);
7541 asm_fprintf (asm_out_file
, "\t# fn:%s vx%d\n", fname
, TARGET_OPT_VX
);
7542 asm_fprintf (asm_out_file
, "\t# fn:%s ps%d\n", fname
,
7543 TARGET_PACKED_STACK
);
7544 asm_fprintf (asm_out_file
, "\t# fn:%s se%d\n", fname
, TARGET_SMALL_EXEC
);
7545 asm_fprintf (asm_out_file
, "\t# fn:%s mv%d\n", fname
, TARGET_MVCLE
);
7546 asm_fprintf (asm_out_file
, "\t# fn:%s zv%d\n", fname
, TARGET_ZVECTOR
);
7547 asm_fprintf (asm_out_file
, "\t# fn:%s wd%d\n", fname
,
7548 s390_warn_dynamicstack_p
);
7550 ASM_OUTPUT_LABEL (asm_out_file
, fname
);
7552 asm_fprintf (asm_out_file
,
7553 "\t# post-label NOPs for hotpatch (%d halfwords)\n",
7557 /* Output machine-dependent UNSPECs occurring in address constant X
7558 in assembler syntax to stdio stream FILE. Returns true if the
7559 constant X could be recognized, false otherwise. */
7562 s390_output_addr_const_extra (FILE *file
, rtx x
)
7564 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 1)
7565 switch (XINT (x
, 1))
7568 output_addr_const (file
, XVECEXP (x
, 0, 0));
7569 fprintf (file
, "@GOTENT");
7572 output_addr_const (file
, XVECEXP (x
, 0, 0));
7573 fprintf (file
, "@GOT");
7576 output_addr_const (file
, XVECEXP (x
, 0, 0));
7577 fprintf (file
, "@GOTOFF");
7580 output_addr_const (file
, XVECEXP (x
, 0, 0));
7581 fprintf (file
, "@PLT");
7584 output_addr_const (file
, XVECEXP (x
, 0, 0));
7585 fprintf (file
, "@PLTOFF");
7588 output_addr_const (file
, XVECEXP (x
, 0, 0));
7589 fprintf (file
, "@TLSGD");
7592 assemble_name (file
, get_some_local_dynamic_name ());
7593 fprintf (file
, "@TLSLDM");
7596 output_addr_const (file
, XVECEXP (x
, 0, 0));
7597 fprintf (file
, "@DTPOFF");
7600 output_addr_const (file
, XVECEXP (x
, 0, 0));
7601 fprintf (file
, "@NTPOFF");
7603 case UNSPEC_GOTNTPOFF
:
7604 output_addr_const (file
, XVECEXP (x
, 0, 0));
7605 fprintf (file
, "@GOTNTPOFF");
7607 case UNSPEC_INDNTPOFF
:
7608 output_addr_const (file
, XVECEXP (x
, 0, 0));
7609 fprintf (file
, "@INDNTPOFF");
7613 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 2)
7614 switch (XINT (x
, 1))
7616 case UNSPEC_POOL_OFFSET
:
7617 x
= gen_rtx_MINUS (GET_MODE (x
), XVECEXP (x
, 0, 0), XVECEXP (x
, 0, 1));
7618 output_addr_const (file
, x
);
7624 /* Output address operand ADDR in assembler syntax to
7625 stdio stream FILE. */
7628 print_operand_address (FILE *file
, rtx addr
)
7630 struct s390_address ad
;
7631 memset (&ad
, 0, sizeof (s390_address
));
7633 if (s390_loadrelative_operand_p (addr
, NULL
, NULL
))
7637 output_operand_lossage ("symbolic memory references are "
7638 "only supported on z10 or later");
7641 output_addr_const (file
, addr
);
7645 if (!s390_decompose_address (addr
, &ad
)
7646 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
7647 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
7648 output_operand_lossage ("cannot decompose address");
7651 output_addr_const (file
, ad
.disp
);
7653 fprintf (file
, "0");
7655 if (ad
.base
&& ad
.indx
)
7656 fprintf (file
, "(%s,%s)", reg_names
[REGNO (ad
.indx
)],
7657 reg_names
[REGNO (ad
.base
)]);
7659 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
7662 /* Output operand X in assembler syntax to stdio stream FILE.
7663 CODE specified the format flag. The following format flags
7666 'C': print opcode suffix for branch condition.
7667 'D': print opcode suffix for inverse branch condition.
7668 'E': print opcode suffix for branch on index instruction.
7669 'G': print the size of the operand in bytes.
7670 'J': print tls_load/tls_gdcall/tls_ldcall suffix
7671 'M': print the second word of a TImode operand.
7672 'N': print the second word of a DImode operand.
7673 'O': print only the displacement of a memory reference or address.
7674 'R': print only the base register of a memory reference or address.
7675 'S': print S-type memory reference (base+displacement).
7676 'Y': print address style operand without index (e.g. shift count or setmem
7679 'b': print integer X as if it's an unsigned byte.
7680 'c': print integer X as if it's an signed byte.
7681 'e': "end" contiguous bitmask X in either DImode or vector inner mode.
7682 'f': "end" contiguous bitmask X in SImode.
7683 'h': print integer X as if it's a signed halfword.
7684 'i': print the first nonzero HImode part of X.
7685 'j': print the first HImode part unequal to -1 of X.
7686 'k': print the first nonzero SImode part of X.
7687 'm': print the first SImode part unequal to -1 of X.
7688 'o': print integer X as if it's an unsigned 32bit word.
7689 's': "start" of contiguous bitmask X in either DImode or vector inner mode.
7690 't': CONST_INT: "start" of contiguous bitmask X in SImode.
7691 CONST_VECTOR: Generate a bitmask for vgbm instruction.
7692 'x': print integer X as if it's an unsigned halfword.
7693 'v': print register number as vector register (v1 instead of f1).
7697 print_operand (FILE *file
, rtx x
, int code
)
7704 fprintf (file
, s390_branch_condition_mnemonic (x
, FALSE
));
7708 fprintf (file
, s390_branch_condition_mnemonic (x
, TRUE
));
7712 if (GET_CODE (x
) == LE
)
7713 fprintf (file
, "l");
7714 else if (GET_CODE (x
) == GT
)
7715 fprintf (file
, "h");
7717 output_operand_lossage ("invalid comparison operator "
7718 "for 'E' output modifier");
7722 if (GET_CODE (x
) == SYMBOL_REF
)
7724 fprintf (file
, "%s", ":tls_load:");
7725 output_addr_const (file
, x
);
7727 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD
)
7729 fprintf (file
, "%s", ":tls_gdcall:");
7730 output_addr_const (file
, XVECEXP (x
, 0, 0));
7732 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM
)
7734 fprintf (file
, "%s", ":tls_ldcall:");
7735 const char *name
= get_some_local_dynamic_name ();
7737 assemble_name (file
, name
);
7740 output_operand_lossage ("invalid reference for 'J' output modifier");
7744 fprintf (file
, "%u", GET_MODE_SIZE (GET_MODE (x
)));
7749 struct s390_address ad
;
7752 ret
= s390_decompose_address (MEM_P (x
) ? XEXP (x
, 0) : x
, &ad
);
7755 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
7758 output_operand_lossage ("invalid address for 'O' output modifier");
7763 output_addr_const (file
, ad
.disp
);
7765 fprintf (file
, "0");
7771 struct s390_address ad
;
7774 ret
= s390_decompose_address (MEM_P (x
) ? XEXP (x
, 0) : x
, &ad
);
7777 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
7780 output_operand_lossage ("invalid address for 'R' output modifier");
7785 fprintf (file
, "%s", reg_names
[REGNO (ad
.base
)]);
7787 fprintf (file
, "0");
7793 struct s390_address ad
;
7798 output_operand_lossage ("memory reference expected for "
7799 "'S' output modifier");
7802 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
7805 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
7808 output_operand_lossage ("invalid address for 'S' output modifier");
7813 output_addr_const (file
, ad
.disp
);
7815 fprintf (file
, "0");
7818 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
7823 if (GET_CODE (x
) == REG
)
7824 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
7825 else if (GET_CODE (x
) == MEM
)
7826 x
= change_address (x
, VOIDmode
,
7827 plus_constant (Pmode
, XEXP (x
, 0), 4));
7829 output_operand_lossage ("register or memory expression expected "
7830 "for 'N' output modifier");
7834 if (GET_CODE (x
) == REG
)
7835 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
7836 else if (GET_CODE (x
) == MEM
)
7837 x
= change_address (x
, VOIDmode
,
7838 plus_constant (Pmode
, XEXP (x
, 0), 8));
7840 output_operand_lossage ("register or memory expression expected "
7841 "for 'M' output modifier");
7845 print_addrstyle_operand (file
, x
);
7849 switch (GET_CODE (x
))
7852 /* Print FP regs as fx instead of vx when they are accessed
7853 through non-vector mode. */
7855 || VECTOR_NOFP_REG_P (x
)
7856 || (FP_REG_P (x
) && VECTOR_MODE_P (GET_MODE (x
)))
7857 || (VECTOR_REG_P (x
)
7858 && (GET_MODE_SIZE (GET_MODE (x
)) /
7859 s390_class_max_nregs (FP_REGS
, GET_MODE (x
))) > 8))
7860 fprintf (file
, "%%v%s", reg_names
[REGNO (x
)] + 2);
7862 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
7866 output_address (GET_MODE (x
), XEXP (x
, 0));
7873 output_addr_const (file
, x
);
7886 ival
= ((ival
& 0xff) ^ 0x80) - 0x80;
7892 ival
= ((ival
& 0xffff) ^ 0x8000) - 0x8000;
7895 ival
= s390_extract_part (x
, HImode
, 0);
7898 ival
= s390_extract_part (x
, HImode
, -1);
7901 ival
= s390_extract_part (x
, SImode
, 0);
7904 ival
= s390_extract_part (x
, SImode
, -1);
7916 len
= (code
== 's' || code
== 'e' ? 64 : 32);
7917 ok
= s390_contiguous_bitmask_p (ival
, true, len
, &start
, &end
);
7919 if (code
== 's' || code
== 't')
7926 output_operand_lossage ("invalid constant for output modifier '%c'", code
);
7928 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ival
);
7931 case CONST_WIDE_INT
:
7933 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7934 CONST_WIDE_INT_ELT (x
, 0) & 0xff);
7935 else if (code
== 'x')
7936 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7937 CONST_WIDE_INT_ELT (x
, 0) & 0xffff);
7938 else if (code
== 'h')
7939 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7940 ((CONST_WIDE_INT_ELT (x
, 0) & 0xffff) ^ 0x8000) - 0x8000);
7944 output_operand_lossage ("invalid constant - try using "
7945 "an output modifier");
7947 output_operand_lossage ("invalid constant for output modifier '%c'",
7955 gcc_assert (const_vec_duplicate_p (x
));
7956 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
7957 ((INTVAL (XVECEXP (x
, 0, 0)) & 0xffff) ^ 0x8000) - 0x8000);
7965 ok
= s390_contiguous_bitmask_vector_p (x
, &start
, &end
);
7967 ival
= (code
== 's') ? start
: end
;
7968 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ival
);
7974 bool ok
= s390_bytemask_vector_p (x
, &mask
);
7976 fprintf (file
, "%u", mask
);
7981 output_operand_lossage ("invalid constant vector for output "
7982 "modifier '%c'", code
);
7988 output_operand_lossage ("invalid expression - try using "
7989 "an output modifier");
7991 output_operand_lossage ("invalid expression for output "
7992 "modifier '%c'", code
);
7997 /* Target hook for assembling integer objects. We need to define it
7998 here to work a round a bug in some versions of GAS, which couldn't
7999 handle values smaller than INT_MIN when printed in decimal. */
8002 s390_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
8004 if (size
== 8 && aligned_p
8005 && GET_CODE (x
) == CONST_INT
&& INTVAL (x
) < INT_MIN
)
8007 fprintf (asm_out_file
, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX
"\n",
8011 return default_assemble_integer (x
, size
, aligned_p
);
8014 /* Returns true if register REGNO is used for forming
8015 a memory address in expression X. */
8018 reg_used_in_mem_p (int regno
, rtx x
)
8020 enum rtx_code code
= GET_CODE (x
);
8026 if (refers_to_regno_p (regno
, XEXP (x
, 0)))
8029 else if (code
== SET
8030 && GET_CODE (SET_DEST (x
)) == PC
)
8032 if (refers_to_regno_p (regno
, SET_SRC (x
)))
8036 fmt
= GET_RTX_FORMAT (code
);
8037 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8040 && reg_used_in_mem_p (regno
, XEXP (x
, i
)))
8043 else if (fmt
[i
] == 'E')
8044 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8045 if (reg_used_in_mem_p (regno
, XVECEXP (x
, i
, j
)))
8051 /* Returns true if expression DEP_RTX sets an address register
8052 used by instruction INSN to address memory. */
8055 addr_generation_dependency_p (rtx dep_rtx
, rtx_insn
*insn
)
8059 if (NONJUMP_INSN_P (dep_rtx
))
8060 dep_rtx
= PATTERN (dep_rtx
);
8062 if (GET_CODE (dep_rtx
) == SET
)
8064 target
= SET_DEST (dep_rtx
);
8065 if (GET_CODE (target
) == STRICT_LOW_PART
)
8066 target
= XEXP (target
, 0);
8067 while (GET_CODE (target
) == SUBREG
)
8068 target
= SUBREG_REG (target
);
8070 if (GET_CODE (target
) == REG
)
8072 int regno
= REGNO (target
);
8074 if (s390_safe_attr_type (insn
) == TYPE_LA
)
8076 pat
= PATTERN (insn
);
8077 if (GET_CODE (pat
) == PARALLEL
)
8079 gcc_assert (XVECLEN (pat
, 0) == 2);
8080 pat
= XVECEXP (pat
, 0, 0);
8082 gcc_assert (GET_CODE (pat
) == SET
);
8083 return refers_to_regno_p (regno
, SET_SRC (pat
));
8085 else if (get_attr_atype (insn
) == ATYPE_AGEN
)
8086 return reg_used_in_mem_p (regno
, PATTERN (insn
));
8092 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
8095 s390_agen_dep_p (rtx_insn
*dep_insn
, rtx_insn
*insn
)
8097 rtx dep_rtx
= PATTERN (dep_insn
);
8100 if (GET_CODE (dep_rtx
) == SET
8101 && addr_generation_dependency_p (dep_rtx
, insn
))
8103 else if (GET_CODE (dep_rtx
) == PARALLEL
)
8105 for (i
= 0; i
< XVECLEN (dep_rtx
, 0); i
++)
8107 if (addr_generation_dependency_p (XVECEXP (dep_rtx
, 0, i
), insn
))
8115 /* A C statement (sans semicolon) to update the integer scheduling priority
8116 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
8117 reduce the priority to execute INSN later. Do not define this macro if
8118 you do not need to adjust the scheduling priorities of insns.
8120 A STD instruction should be scheduled earlier,
8121 in order to use the bypass. */
8123 s390_adjust_priority (rtx_insn
*insn
, int priority
)
8125 if (! INSN_P (insn
))
8128 if (s390_tune
<= PROCESSOR_2064_Z900
)
8131 switch (s390_safe_attr_type (insn
))
8135 priority
= priority
<< 3;
8139 priority
= priority
<< 1;
8148 /* The number of instructions that can be issued per cycle. */
8151 s390_issue_rate (void)
8155 case PROCESSOR_2084_Z990
:
8156 case PROCESSOR_2094_Z9_109
:
8157 case PROCESSOR_2094_Z9_EC
:
8158 case PROCESSOR_2817_Z196
:
8160 case PROCESSOR_2097_Z10
:
8162 case PROCESSOR_9672_G5
:
8163 case PROCESSOR_9672_G6
:
8164 case PROCESSOR_2064_Z900
:
8165 /* Starting with EC12 we use the sched_reorder hook to take care
8166 of instruction dispatch constraints. The algorithm only
8167 picks the best instruction and assumes only a single
8168 instruction gets issued per cycle. */
8169 case PROCESSOR_2827_ZEC12
:
8170 case PROCESSOR_2964_Z13
:
8171 case PROCESSOR_3906_Z14
:
8178 s390_first_cycle_multipass_dfa_lookahead (void)
8183 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
8184 Fix up MEMs as required. */
8187 annotate_constant_pool_refs (rtx
*x
)
8192 gcc_assert (GET_CODE (*x
) != SYMBOL_REF
8193 || !CONSTANT_POOL_ADDRESS_P (*x
));
8195 /* Literal pool references can only occur inside a MEM ... */
8196 if (GET_CODE (*x
) == MEM
)
8198 rtx memref
= XEXP (*x
, 0);
8200 if (GET_CODE (memref
) == SYMBOL_REF
8201 && CONSTANT_POOL_ADDRESS_P (memref
))
8203 rtx base
= cfun
->machine
->base_reg
;
8204 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, memref
, base
),
8207 *x
= replace_equiv_address (*x
, addr
);
8211 if (GET_CODE (memref
) == CONST
8212 && GET_CODE (XEXP (memref
, 0)) == PLUS
8213 && GET_CODE (XEXP (XEXP (memref
, 0), 1)) == CONST_INT
8214 && GET_CODE (XEXP (XEXP (memref
, 0), 0)) == SYMBOL_REF
8215 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref
, 0), 0)))
8217 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (memref
, 0), 1));
8218 rtx sym
= XEXP (XEXP (memref
, 0), 0);
8219 rtx base
= cfun
->machine
->base_reg
;
8220 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
8223 *x
= replace_equiv_address (*x
, plus_constant (Pmode
, addr
, off
));
8228 /* ... or a load-address type pattern. */
8229 if (GET_CODE (*x
) == SET
)
8231 rtx addrref
= SET_SRC (*x
);
8233 if (GET_CODE (addrref
) == SYMBOL_REF
8234 && CONSTANT_POOL_ADDRESS_P (addrref
))
8236 rtx base
= cfun
->machine
->base_reg
;
8237 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, addrref
, base
),
8240 SET_SRC (*x
) = addr
;
8244 if (GET_CODE (addrref
) == CONST
8245 && GET_CODE (XEXP (addrref
, 0)) == PLUS
8246 && GET_CODE (XEXP (XEXP (addrref
, 0), 1)) == CONST_INT
8247 && GET_CODE (XEXP (XEXP (addrref
, 0), 0)) == SYMBOL_REF
8248 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref
, 0), 0)))
8250 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (addrref
, 0), 1));
8251 rtx sym
= XEXP (XEXP (addrref
, 0), 0);
8252 rtx base
= cfun
->machine
->base_reg
;
8253 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
8256 SET_SRC (*x
) = plus_constant (Pmode
, addr
, off
);
8261 /* Annotate LTREL_BASE as well. */
8262 if (GET_CODE (*x
) == UNSPEC
8263 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
8265 rtx base
= cfun
->machine
->base_reg
;
8266 *x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XVECEXP (*x
, 0, 0), base
),
8271 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
8272 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
8276 annotate_constant_pool_refs (&XEXP (*x
, i
));
8278 else if (fmt
[i
] == 'E')
8280 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
8281 annotate_constant_pool_refs (&XVECEXP (*x
, i
, j
));
8286 /* Split all branches that exceed the maximum distance.
8287 Returns true if this created a new literal pool entry. */
8290 s390_split_branches (void)
8292 rtx temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
8293 int new_literal
= 0, ret
;
8298 /* We need correct insn addresses. */
8300 shorten_branches (get_insns ());
8302 /* Find all branches that exceed 64KB, and split them. */
8304 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8306 if (! JUMP_P (insn
) || tablejump_p (insn
, NULL
, NULL
))
8309 pat
= PATTERN (insn
);
8310 if (GET_CODE (pat
) == PARALLEL
)
8311 pat
= XVECEXP (pat
, 0, 0);
8312 if (GET_CODE (pat
) != SET
|| SET_DEST (pat
) != pc_rtx
)
8315 if (GET_CODE (SET_SRC (pat
)) == LABEL_REF
)
8317 label
= &SET_SRC (pat
);
8319 else if (GET_CODE (SET_SRC (pat
)) == IF_THEN_ELSE
)
8321 if (GET_CODE (XEXP (SET_SRC (pat
), 1)) == LABEL_REF
)
8322 label
= &XEXP (SET_SRC (pat
), 1);
8323 else if (GET_CODE (XEXP (SET_SRC (pat
), 2)) == LABEL_REF
)
8324 label
= &XEXP (SET_SRC (pat
), 2);
8331 if (get_attr_length (insn
) <= 4)
8334 /* We are going to use the return register as scratch register,
8335 make sure it will be saved/restored by the prologue/epilogue. */
8336 cfun_frame_layout
.save_return_addr_p
= 1;
8341 rtx mem
= force_const_mem (Pmode
, *label
);
8342 rtx_insn
*set_insn
= emit_insn_before (gen_rtx_SET (temp_reg
, mem
),
8344 INSN_ADDRESSES_NEW (set_insn
, -1);
8345 annotate_constant_pool_refs (&PATTERN (set_insn
));
8352 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, *label
),
8353 UNSPEC_LTREL_OFFSET
);
8354 target
= gen_rtx_CONST (Pmode
, target
);
8355 target
= force_const_mem (Pmode
, target
);
8356 rtx_insn
*set_insn
= emit_insn_before (gen_rtx_SET (temp_reg
, target
),
8358 INSN_ADDRESSES_NEW (set_insn
, -1);
8359 annotate_constant_pool_refs (&PATTERN (set_insn
));
8361 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XEXP (target
, 0),
8362 cfun
->machine
->base_reg
),
8364 target
= gen_rtx_PLUS (Pmode
, temp_reg
, target
);
8367 ret
= validate_change (insn
, label
, target
, 0);
8375 /* Find an annotated literal pool symbol referenced in RTX X,
8376 and store it at REF. Will abort if X contains references to
8377 more than one such pool symbol; multiple references to the same
8378 symbol are allowed, however.
8380 The rtx pointed to by REF must be initialized to NULL_RTX
8381 by the caller before calling this routine. */
8384 find_constant_pool_ref (rtx x
, rtx
*ref
)
8389 /* Ignore LTREL_BASE references. */
8390 if (GET_CODE (x
) == UNSPEC
8391 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
8393 /* Likewise POOL_ENTRY insns. */
8394 if (GET_CODE (x
) == UNSPEC_VOLATILE
8395 && XINT (x
, 1) == UNSPECV_POOL_ENTRY
)
8398 gcc_assert (GET_CODE (x
) != SYMBOL_REF
8399 || !CONSTANT_POOL_ADDRESS_P (x
));
8401 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_LTREF
)
8403 rtx sym
= XVECEXP (x
, 0, 0);
8404 gcc_assert (GET_CODE (sym
) == SYMBOL_REF
8405 && CONSTANT_POOL_ADDRESS_P (sym
));
8407 if (*ref
== NULL_RTX
)
8410 gcc_assert (*ref
== sym
);
8415 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
8416 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
8420 find_constant_pool_ref (XEXP (x
, i
), ref
);
8422 else if (fmt
[i
] == 'E')
8424 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8425 find_constant_pool_ref (XVECEXP (x
, i
, j
), ref
);
8430 /* Replace every reference to the annotated literal pool
8431 symbol REF in X by its base plus OFFSET. */
8434 replace_constant_pool_ref (rtx
*x
, rtx ref
, rtx offset
)
8439 gcc_assert (*x
!= ref
);
8441 if (GET_CODE (*x
) == UNSPEC
8442 && XINT (*x
, 1) == UNSPEC_LTREF
8443 && XVECEXP (*x
, 0, 0) == ref
)
8445 *x
= gen_rtx_PLUS (Pmode
, XVECEXP (*x
, 0, 1), offset
);
8449 if (GET_CODE (*x
) == PLUS
8450 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
8451 && GET_CODE (XEXP (*x
, 0)) == UNSPEC
8452 && XINT (XEXP (*x
, 0), 1) == UNSPEC_LTREF
8453 && XVECEXP (XEXP (*x
, 0), 0, 0) == ref
)
8455 rtx addr
= gen_rtx_PLUS (Pmode
, XVECEXP (XEXP (*x
, 0), 0, 1), offset
);
8456 *x
= plus_constant (Pmode
, addr
, INTVAL (XEXP (*x
, 1)));
8460 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
8461 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
8465 replace_constant_pool_ref (&XEXP (*x
, i
), ref
, offset
);
8467 else if (fmt
[i
] == 'E')
8469 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
8470 replace_constant_pool_ref (&XVECEXP (*x
, i
, j
), ref
, offset
);
8475 /* Check whether X contains an UNSPEC_LTREL_BASE.
8476 Return its constant pool symbol if found, NULL_RTX otherwise. */
8479 find_ltrel_base (rtx x
)
8484 if (GET_CODE (x
) == UNSPEC
8485 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
8486 return XVECEXP (x
, 0, 0);
8488 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
8489 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
8493 rtx fnd
= find_ltrel_base (XEXP (x
, i
));
8497 else if (fmt
[i
] == 'E')
8499 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8501 rtx fnd
= find_ltrel_base (XVECEXP (x
, i
, j
));
8511 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
8514 replace_ltrel_base (rtx
*x
)
8519 if (GET_CODE (*x
) == UNSPEC
8520 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
8522 *x
= XVECEXP (*x
, 0, 1);
8526 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
8527 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
8531 replace_ltrel_base (&XEXP (*x
, i
));
8533 else if (fmt
[i
] == 'E')
8535 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
8536 replace_ltrel_base (&XVECEXP (*x
, i
, j
));
8542 /* We keep a list of constants which we have to add to internal
8543 constant tables in the middle of large functions. */
8545 #define NR_C_MODES 32
8546 machine_mode constant_modes
[NR_C_MODES
] =
8548 TFmode
, TImode
, TDmode
,
8549 V16QImode
, V8HImode
, V4SImode
, V2DImode
, V1TImode
,
8550 V4SFmode
, V2DFmode
, V1TFmode
,
8551 DFmode
, DImode
, DDmode
,
8552 V8QImode
, V4HImode
, V2SImode
, V1DImode
, V2SFmode
, V1DFmode
,
8553 SFmode
, SImode
, SDmode
,
8554 V4QImode
, V2HImode
, V1SImode
, V1SFmode
,
8563 struct constant
*next
;
8565 rtx_code_label
*label
;
8568 struct constant_pool
8570 struct constant_pool
*next
;
8571 rtx_insn
*first_insn
;
8572 rtx_insn
*pool_insn
;
8574 rtx_insn
*emit_pool_after
;
8576 struct constant
*constants
[NR_C_MODES
];
8577 struct constant
*execute
;
8578 rtx_code_label
*label
;
8582 /* Allocate new constant_pool structure. */
8584 static struct constant_pool
*
8585 s390_alloc_pool (void)
8587 struct constant_pool
*pool
;
8590 pool
= (struct constant_pool
*) xmalloc (sizeof *pool
);
8592 for (i
= 0; i
< NR_C_MODES
; i
++)
8593 pool
->constants
[i
] = NULL
;
8595 pool
->execute
= NULL
;
8596 pool
->label
= gen_label_rtx ();
8597 pool
->first_insn
= NULL
;
8598 pool
->pool_insn
= NULL
;
8599 pool
->insns
= BITMAP_ALLOC (NULL
);
8601 pool
->emit_pool_after
= NULL
;
8606 /* Create new constant pool covering instructions starting at INSN
8607 and chain it to the end of POOL_LIST. */
8609 static struct constant_pool
*
8610 s390_start_pool (struct constant_pool
**pool_list
, rtx_insn
*insn
)
8612 struct constant_pool
*pool
, **prev
;
8614 pool
= s390_alloc_pool ();
8615 pool
->first_insn
= insn
;
8617 for (prev
= pool_list
; *prev
; prev
= &(*prev
)->next
)
8624 /* End range of instructions covered by POOL at INSN and emit
8625 placeholder insn representing the pool. */
8628 s390_end_pool (struct constant_pool
*pool
, rtx_insn
*insn
)
8630 rtx pool_size
= GEN_INT (pool
->size
+ 8 /* alignment slop */);
8633 insn
= get_last_insn ();
8635 pool
->pool_insn
= emit_insn_after (gen_pool (pool_size
), insn
);
8636 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
8639 /* Add INSN to the list of insns covered by POOL. */
8642 s390_add_pool_insn (struct constant_pool
*pool
, rtx insn
)
8644 bitmap_set_bit (pool
->insns
, INSN_UID (insn
));
8647 /* Return pool out of POOL_LIST that covers INSN. */
8649 static struct constant_pool
*
8650 s390_find_pool (struct constant_pool
*pool_list
, rtx insn
)
8652 struct constant_pool
*pool
;
8654 for (pool
= pool_list
; pool
; pool
= pool
->next
)
8655 if (bitmap_bit_p (pool
->insns
, INSN_UID (insn
)))
8661 /* Add constant VAL of mode MODE to the constant pool POOL. */
8664 s390_add_constant (struct constant_pool
*pool
, rtx val
, machine_mode mode
)
8669 for (i
= 0; i
< NR_C_MODES
; i
++)
8670 if (constant_modes
[i
] == mode
)
8672 gcc_assert (i
!= NR_C_MODES
);
8674 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
8675 if (rtx_equal_p (val
, c
->value
))
8680 c
= (struct constant
*) xmalloc (sizeof *c
);
8682 c
->label
= gen_label_rtx ();
8683 c
->next
= pool
->constants
[i
];
8684 pool
->constants
[i
] = c
;
8685 pool
->size
+= GET_MODE_SIZE (mode
);
8689 /* Return an rtx that represents the offset of X from the start of
8693 s390_pool_offset (struct constant_pool
*pool
, rtx x
)
8697 label
= gen_rtx_LABEL_REF (GET_MODE (x
), pool
->label
);
8698 x
= gen_rtx_UNSPEC (GET_MODE (x
), gen_rtvec (2, x
, label
),
8699 UNSPEC_POOL_OFFSET
);
8700 return gen_rtx_CONST (GET_MODE (x
), x
);
8703 /* Find constant VAL of mode MODE in the constant pool POOL.
8704 Return an RTX describing the distance from the start of
8705 the pool to the location of the new constant. */
8708 s390_find_constant (struct constant_pool
*pool
, rtx val
,
8714 for (i
= 0; i
< NR_C_MODES
; i
++)
8715 if (constant_modes
[i
] == mode
)
8717 gcc_assert (i
!= NR_C_MODES
);
8719 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
8720 if (rtx_equal_p (val
, c
->value
))
8725 return s390_pool_offset (pool
, gen_rtx_LABEL_REF (Pmode
, c
->label
));
8728 /* Check whether INSN is an execute. Return the label_ref to its
8729 execute target template if so, NULL_RTX otherwise. */
8732 s390_execute_label (rtx insn
)
8734 if (NONJUMP_INSN_P (insn
)
8735 && GET_CODE (PATTERN (insn
)) == PARALLEL
8736 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == UNSPEC
8737 && XINT (XVECEXP (PATTERN (insn
), 0, 0), 1) == UNSPEC_EXECUTE
)
8738 return XVECEXP (XVECEXP (PATTERN (insn
), 0, 0), 0, 2);
8743 /* Add execute target for INSN to the constant pool POOL. */
8746 s390_add_execute (struct constant_pool
*pool
, rtx insn
)
8750 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
8751 if (INSN_UID (insn
) == INSN_UID (c
->value
))
8756 c
= (struct constant
*) xmalloc (sizeof *c
);
8758 c
->label
= gen_label_rtx ();
8759 c
->next
= pool
->execute
;
8765 /* Find execute target for INSN in the constant pool POOL.
8766 Return an RTX describing the distance from the start of
8767 the pool to the location of the execute target. */
8770 s390_find_execute (struct constant_pool
*pool
, rtx insn
)
8774 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
8775 if (INSN_UID (insn
) == INSN_UID (c
->value
))
8780 return s390_pool_offset (pool
, gen_rtx_LABEL_REF (Pmode
, c
->label
));
8783 /* For an execute INSN, extract the execute target template. */
8786 s390_execute_target (rtx insn
)
8788 rtx pattern
= PATTERN (insn
);
8789 gcc_assert (s390_execute_label (insn
));
8791 if (XVECLEN (pattern
, 0) == 2)
8793 pattern
= copy_rtx (XVECEXP (pattern
, 0, 1));
8797 rtvec vec
= rtvec_alloc (XVECLEN (pattern
, 0) - 1);
8800 for (i
= 0; i
< XVECLEN (pattern
, 0) - 1; i
++)
8801 RTVEC_ELT (vec
, i
) = copy_rtx (XVECEXP (pattern
, 0, i
+ 1));
8803 pattern
= gen_rtx_PARALLEL (VOIDmode
, vec
);
8809 /* Indicate that INSN cannot be duplicated. This is the case for
8810 execute insns that carry a unique label. */
8813 s390_cannot_copy_insn_p (rtx_insn
*insn
)
8815 rtx label
= s390_execute_label (insn
);
8816 return label
&& label
!= const0_rtx
;
8819 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
8820 do not emit the pool base label. */
8823 s390_dump_pool (struct constant_pool
*pool
, bool remote_label
)
8826 rtx_insn
*insn
= pool
->pool_insn
;
8829 /* Switch to rodata section. */
8830 if (TARGET_CPU_ZARCH
)
8832 insn
= emit_insn_after (gen_pool_section_start (), insn
);
8833 INSN_ADDRESSES_NEW (insn
, -1);
8836 /* Ensure minimum pool alignment. */
8837 if (TARGET_CPU_ZARCH
)
8838 insn
= emit_insn_after (gen_pool_align (GEN_INT (8)), insn
);
8840 insn
= emit_insn_after (gen_pool_align (GEN_INT (4)), insn
);
8841 INSN_ADDRESSES_NEW (insn
, -1);
8843 /* Emit pool base label. */
8846 insn
= emit_label_after (pool
->label
, insn
);
8847 INSN_ADDRESSES_NEW (insn
, -1);
8850 /* Dump constants in descending alignment requirement order,
8851 ensuring proper alignment for every constant. */
8852 for (i
= 0; i
< NR_C_MODES
; i
++)
8853 for (c
= pool
->constants
[i
]; c
; c
= c
->next
)
8855 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
8856 rtx value
= copy_rtx (c
->value
);
8857 if (GET_CODE (value
) == CONST
8858 && GET_CODE (XEXP (value
, 0)) == UNSPEC
8859 && XINT (XEXP (value
, 0), 1) == UNSPEC_LTREL_OFFSET
8860 && XVECLEN (XEXP (value
, 0), 0) == 1)
8861 value
= s390_pool_offset (pool
, XVECEXP (XEXP (value
, 0), 0, 0));
8863 insn
= emit_label_after (c
->label
, insn
);
8864 INSN_ADDRESSES_NEW (insn
, -1);
8866 value
= gen_rtx_UNSPEC_VOLATILE (constant_modes
[i
],
8867 gen_rtvec (1, value
),
8868 UNSPECV_POOL_ENTRY
);
8869 insn
= emit_insn_after (value
, insn
);
8870 INSN_ADDRESSES_NEW (insn
, -1);
8873 /* Ensure minimum alignment for instructions. */
8874 insn
= emit_insn_after (gen_pool_align (GEN_INT (2)), insn
);
8875 INSN_ADDRESSES_NEW (insn
, -1);
8877 /* Output in-pool execute template insns. */
8878 for (c
= pool
->execute
; c
; c
= c
->next
)
8880 insn
= emit_label_after (c
->label
, insn
);
8881 INSN_ADDRESSES_NEW (insn
, -1);
8883 insn
= emit_insn_after (s390_execute_target (c
->value
), insn
);
8884 INSN_ADDRESSES_NEW (insn
, -1);
8887 /* Switch back to previous section. */
8888 if (TARGET_CPU_ZARCH
)
8890 insn
= emit_insn_after (gen_pool_section_end (), insn
);
8891 INSN_ADDRESSES_NEW (insn
, -1);
8894 insn
= emit_barrier_after (insn
);
8895 INSN_ADDRESSES_NEW (insn
, -1);
8897 /* Remove placeholder insn. */
8898 remove_insn (pool
->pool_insn
);
8901 /* Free all memory used by POOL. */
8904 s390_free_pool (struct constant_pool
*pool
)
8906 struct constant
*c
, *next
;
8909 for (i
= 0; i
< NR_C_MODES
; i
++)
8910 for (c
= pool
->constants
[i
]; c
; c
= next
)
8916 for (c
= pool
->execute
; c
; c
= next
)
8922 BITMAP_FREE (pool
->insns
);
8927 /* Collect main literal pool. Return NULL on overflow. */
8929 static struct constant_pool
*
8930 s390_mainpool_start (void)
8932 struct constant_pool
*pool
;
8935 pool
= s390_alloc_pool ();
8937 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8939 if (NONJUMP_INSN_P (insn
)
8940 && GET_CODE (PATTERN (insn
)) == SET
8941 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC_VOLATILE
8942 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPECV_MAIN_POOL
)
8944 /* There might be two main_pool instructions if base_reg
8945 is call-clobbered; one for shrink-wrapped code and one
8946 for the rest. We want to keep the first. */
8947 if (pool
->pool_insn
)
8949 insn
= PREV_INSN (insn
);
8950 delete_insn (NEXT_INSN (insn
));
8953 pool
->pool_insn
= insn
;
8956 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
8958 s390_add_execute (pool
, insn
);
8960 else if (NONJUMP_INSN_P (insn
) || CALL_P (insn
))
8962 rtx pool_ref
= NULL_RTX
;
8963 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
8966 rtx constant
= get_pool_constant (pool_ref
);
8967 machine_mode mode
= get_pool_mode (pool_ref
);
8968 s390_add_constant (pool
, constant
, mode
);
8972 /* If hot/cold partitioning is enabled we have to make sure that
8973 the literal pool is emitted in the same section where the
8974 initialization of the literal pool base pointer takes place.
8975 emit_pool_after is only used in the non-overflow case on non
8976 Z cpus where we can emit the literal pool at the end of the
8977 function body within the text section. */
8979 && NOTE_KIND (insn
) == NOTE_INSN_SWITCH_TEXT_SECTIONS
8980 && !pool
->emit_pool_after
)
8981 pool
->emit_pool_after
= PREV_INSN (insn
);
8984 gcc_assert (pool
->pool_insn
|| pool
->size
== 0);
8986 if (pool
->size
>= 4096)
8988 /* We're going to chunkify the pool, so remove the main
8989 pool placeholder insn. */
8990 remove_insn (pool
->pool_insn
);
8992 s390_free_pool (pool
);
8996 /* If the functions ends with the section where the literal pool
8997 should be emitted set the marker to its end. */
8998 if (pool
&& !pool
->emit_pool_after
)
8999 pool
->emit_pool_after
= get_last_insn ();
9004 /* POOL holds the main literal pool as collected by s390_mainpool_start.
9005 Modify the current function to output the pool constants as well as
9006 the pool register setup instruction. */
9009 s390_mainpool_finish (struct constant_pool
*pool
)
9011 rtx base_reg
= cfun
->machine
->base_reg
;
9013 /* If the pool is empty, we're done. */
9014 if (pool
->size
== 0)
9016 /* We don't actually need a base register after all. */
9017 cfun
->machine
->base_reg
= NULL_RTX
;
9019 if (pool
->pool_insn
)
9020 remove_insn (pool
->pool_insn
);
9021 s390_free_pool (pool
);
9025 /* We need correct insn addresses. */
9026 shorten_branches (get_insns ());
9028 /* On zSeries, we use a LARL to load the pool register. The pool is
9029 located in the .rodata section, so we emit it after the function. */
9030 if (TARGET_CPU_ZARCH
)
9032 rtx set
= gen_main_base_64 (base_reg
, pool
->label
);
9033 rtx_insn
*insn
= emit_insn_after (set
, pool
->pool_insn
);
9034 INSN_ADDRESSES_NEW (insn
, -1);
9035 remove_insn (pool
->pool_insn
);
9037 insn
= get_last_insn ();
9038 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
9039 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
9041 s390_dump_pool (pool
, 0);
9044 /* On S/390, if the total size of the function's code plus literal pool
9045 does not exceed 4096 bytes, we use BASR to set up a function base
9046 pointer, and emit the literal pool at the end of the function. */
9047 else if (INSN_ADDRESSES (INSN_UID (pool
->emit_pool_after
))
9048 + pool
->size
+ 8 /* alignment slop */ < 4096)
9050 rtx set
= gen_main_base_31_small (base_reg
, pool
->label
);
9051 rtx_insn
*insn
= emit_insn_after (set
, pool
->pool_insn
);
9052 INSN_ADDRESSES_NEW (insn
, -1);
9053 remove_insn (pool
->pool_insn
);
9055 insn
= emit_label_after (pool
->label
, insn
);
9056 INSN_ADDRESSES_NEW (insn
, -1);
9058 /* emit_pool_after will be set by s390_mainpool_start to the
9059 last insn of the section where the literal pool should be
9061 insn
= pool
->emit_pool_after
;
9063 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
9064 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
9066 s390_dump_pool (pool
, 1);
9069 /* Otherwise, we emit an inline literal pool and use BASR to branch
9070 over it, setting up the pool register at the same time. */
9073 rtx_code_label
*pool_end
= gen_label_rtx ();
9075 rtx pat
= gen_main_base_31_large (base_reg
, pool
->label
, pool_end
);
9076 rtx_insn
*insn
= emit_jump_insn_after (pat
, pool
->pool_insn
);
9077 JUMP_LABEL (insn
) = pool_end
;
9078 INSN_ADDRESSES_NEW (insn
, -1);
9079 remove_insn (pool
->pool_insn
);
9081 insn
= emit_label_after (pool
->label
, insn
);
9082 INSN_ADDRESSES_NEW (insn
, -1);
9084 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
9085 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
9087 insn
= emit_label_after (pool_end
, pool
->pool_insn
);
9088 INSN_ADDRESSES_NEW (insn
, -1);
9090 s390_dump_pool (pool
, 1);
9094 /* Replace all literal pool references. */
9096 for (rtx_insn
*insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9099 replace_ltrel_base (&PATTERN (insn
));
9101 if (NONJUMP_INSN_P (insn
) || CALL_P (insn
))
9103 rtx addr
, pool_ref
= NULL_RTX
;
9104 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
9107 if (s390_execute_label (insn
))
9108 addr
= s390_find_execute (pool
, insn
);
9110 addr
= s390_find_constant (pool
, get_pool_constant (pool_ref
),
9111 get_pool_mode (pool_ref
));
9113 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
9114 INSN_CODE (insn
) = -1;
9120 /* Free the pool. */
9121 s390_free_pool (pool
);
9124 /* POOL holds the main literal pool as collected by s390_mainpool_start.
9125 We have decided we cannot use this pool, so revert all changes
9126 to the current function that were done by s390_mainpool_start. */
9128 s390_mainpool_cancel (struct constant_pool
*pool
)
9130 /* We didn't actually change the instruction stream, so simply
9131 free the pool memory. */
9132 s390_free_pool (pool
);
9136 /* Chunkify the literal pool. */
9138 #define S390_POOL_CHUNK_MIN 0xc00
9139 #define S390_POOL_CHUNK_MAX 0xe00
9141 static struct constant_pool
*
9142 s390_chunkify_start (void)
9144 struct constant_pool
*curr_pool
= NULL
, *pool_list
= NULL
;
9147 rtx pending_ltrel
= NULL_RTX
;
9150 rtx (*gen_reload_base
) (rtx
, rtx
) =
9151 TARGET_CPU_ZARCH
? gen_reload_base_64
: gen_reload_base_31
;
9154 /* We need correct insn addresses. */
9156 shorten_branches (get_insns ());
9158 /* Scan all insns and move literals to pool chunks. */
9160 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9162 bool section_switch_p
= false;
9164 /* Check for pending LTREL_BASE. */
9167 rtx ltrel_base
= find_ltrel_base (PATTERN (insn
));
9170 gcc_assert (ltrel_base
== pending_ltrel
);
9171 pending_ltrel
= NULL_RTX
;
9175 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
9178 curr_pool
= s390_start_pool (&pool_list
, insn
);
9180 s390_add_execute (curr_pool
, insn
);
9181 s390_add_pool_insn (curr_pool
, insn
);
9183 else if (NONJUMP_INSN_P (insn
) || CALL_P (insn
))
9185 rtx pool_ref
= NULL_RTX
;
9186 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
9189 rtx constant
= get_pool_constant (pool_ref
);
9190 machine_mode mode
= get_pool_mode (pool_ref
);
9193 curr_pool
= s390_start_pool (&pool_list
, insn
);
9195 s390_add_constant (curr_pool
, constant
, mode
);
9196 s390_add_pool_insn (curr_pool
, insn
);
9198 /* Don't split the pool chunk between a LTREL_OFFSET load
9199 and the corresponding LTREL_BASE. */
9200 if (GET_CODE (constant
) == CONST
9201 && GET_CODE (XEXP (constant
, 0)) == UNSPEC
9202 && XINT (XEXP (constant
, 0), 1) == UNSPEC_LTREL_OFFSET
)
9204 gcc_assert (!pending_ltrel
);
9205 pending_ltrel
= pool_ref
;
9210 if (JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
) || LABEL_P (insn
))
9213 s390_add_pool_insn (curr_pool
, insn
);
9214 /* An LTREL_BASE must follow within the same basic block. */
9215 gcc_assert (!pending_ltrel
);
9219 switch (NOTE_KIND (insn
))
9221 case NOTE_INSN_SWITCH_TEXT_SECTIONS
:
9222 section_switch_p
= true;
9224 case NOTE_INSN_VAR_LOCATION
:
9225 case NOTE_INSN_CALL_ARG_LOCATION
:
9232 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn
)
9233 || INSN_ADDRESSES (INSN_UID (insn
)) == -1)
9236 if (TARGET_CPU_ZARCH
)
9238 if (curr_pool
->size
< S390_POOL_CHUNK_MAX
)
9241 s390_end_pool (curr_pool
, NULL
);
9246 int chunk_size
= INSN_ADDRESSES (INSN_UID (insn
))
9247 - INSN_ADDRESSES (INSN_UID (curr_pool
->first_insn
))
9250 /* We will later have to insert base register reload insns.
9251 Those will have an effect on code size, which we need to
9252 consider here. This calculation makes rather pessimistic
9253 worst-case assumptions. */
9257 if (chunk_size
< S390_POOL_CHUNK_MIN
9258 && curr_pool
->size
< S390_POOL_CHUNK_MIN
9259 && !section_switch_p
)
9262 /* Pool chunks can only be inserted after BARRIERs ... */
9263 if (BARRIER_P (insn
))
9265 s390_end_pool (curr_pool
, insn
);
9270 /* ... so if we don't find one in time, create one. */
9271 else if (chunk_size
> S390_POOL_CHUNK_MAX
9272 || curr_pool
->size
> S390_POOL_CHUNK_MAX
9273 || section_switch_p
)
9275 rtx_insn
*label
, *jump
, *barrier
, *next
, *prev
;
9277 if (!section_switch_p
)
9279 /* We can insert the barrier only after a 'real' insn. */
9280 if (! NONJUMP_INSN_P (insn
) && ! CALL_P (insn
))
9282 if (get_attr_length (insn
) == 0)
9284 /* Don't separate LTREL_BASE from the corresponding
9285 LTREL_OFFSET load. */
9292 next
= NEXT_INSN (insn
);
9296 && (NOTE_KIND (next
) == NOTE_INSN_VAR_LOCATION
9297 || NOTE_KIND (next
) == NOTE_INSN_CALL_ARG_LOCATION
));
9301 gcc_assert (!pending_ltrel
);
9303 /* The old pool has to end before the section switch
9304 note in order to make it part of the current
9306 insn
= PREV_INSN (insn
);
9309 label
= gen_label_rtx ();
9311 if (prev
&& NOTE_P (prev
))
9312 prev
= prev_nonnote_insn (prev
);
9314 jump
= emit_jump_insn_after_setloc (gen_jump (label
), insn
,
9315 INSN_LOCATION (prev
));
9317 jump
= emit_jump_insn_after_noloc (gen_jump (label
), insn
);
9318 barrier
= emit_barrier_after (jump
);
9319 insn
= emit_label_after (label
, barrier
);
9320 JUMP_LABEL (jump
) = label
;
9321 LABEL_NUSES (label
) = 1;
9323 INSN_ADDRESSES_NEW (jump
, -1);
9324 INSN_ADDRESSES_NEW (barrier
, -1);
9325 INSN_ADDRESSES_NEW (insn
, -1);
9327 s390_end_pool (curr_pool
, barrier
);
9335 s390_end_pool (curr_pool
, NULL
);
9336 gcc_assert (!pending_ltrel
);
9338 /* Find all labels that are branched into
9339 from an insn belonging to a different chunk. */
9341 far_labels
= BITMAP_ALLOC (NULL
);
9343 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9345 rtx_jump_table_data
*table
;
9347 /* Labels marked with LABEL_PRESERVE_P can be target
9348 of non-local jumps, so we have to mark them.
9349 The same holds for named labels.
9351 Don't do that, however, if it is the label before
9355 && (LABEL_PRESERVE_P (insn
) || LABEL_NAME (insn
)))
9357 rtx_insn
*vec_insn
= NEXT_INSN (insn
);
9358 if (! vec_insn
|| ! JUMP_TABLE_DATA_P (vec_insn
))
9359 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (insn
));
9361 /* Check potential targets in a table jump (casesi_jump). */
9362 else if (tablejump_p (insn
, NULL
, &table
))
9364 rtx vec_pat
= PATTERN (table
);
9365 int i
, diff_p
= GET_CODE (vec_pat
) == ADDR_DIFF_VEC
;
9367 for (i
= 0; i
< XVECLEN (vec_pat
, diff_p
); i
++)
9369 rtx label
= XEXP (XVECEXP (vec_pat
, diff_p
, i
), 0);
9371 if (s390_find_pool (pool_list
, label
)
9372 != s390_find_pool (pool_list
, insn
))
9373 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
9376 /* If we have a direct jump (conditional or unconditional),
9377 check all potential targets. */
9378 else if (JUMP_P (insn
))
9380 rtx pat
= PATTERN (insn
);
9382 if (GET_CODE (pat
) == PARALLEL
)
9383 pat
= XVECEXP (pat
, 0, 0);
9385 if (GET_CODE (pat
) == SET
)
9387 rtx label
= JUMP_LABEL (insn
);
9388 if (label
&& !ANY_RETURN_P (label
))
9390 if (s390_find_pool (pool_list
, label
)
9391 != s390_find_pool (pool_list
, insn
))
9392 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
9398 /* Insert base register reload insns before every pool. */
9400 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
9402 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
9404 rtx_insn
*insn
= curr_pool
->first_insn
;
9405 INSN_ADDRESSES_NEW (emit_insn_before (new_insn
, insn
), -1);
9408 /* Insert base register reload insns at every far label. */
9410 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9412 && bitmap_bit_p (far_labels
, CODE_LABEL_NUMBER (insn
)))
9414 struct constant_pool
*pool
= s390_find_pool (pool_list
, insn
);
9417 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
9419 INSN_ADDRESSES_NEW (emit_insn_after (new_insn
, insn
), -1);
9424 BITMAP_FREE (far_labels
);
9427 /* Recompute insn addresses. */
9429 init_insn_lengths ();
9430 shorten_branches (get_insns ());
9435 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
9436 After we have decided to use this list, finish implementing
9437 all changes to the current function as required. */
9440 s390_chunkify_finish (struct constant_pool
*pool_list
)
9442 struct constant_pool
*curr_pool
= NULL
;
9446 /* Replace all literal pool references. */
9448 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9451 replace_ltrel_base (&PATTERN (insn
));
9453 curr_pool
= s390_find_pool (pool_list
, insn
);
9457 if (NONJUMP_INSN_P (insn
) || CALL_P (insn
))
9459 rtx addr
, pool_ref
= NULL_RTX
;
9460 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
9463 if (s390_execute_label (insn
))
9464 addr
= s390_find_execute (curr_pool
, insn
);
9466 addr
= s390_find_constant (curr_pool
,
9467 get_pool_constant (pool_ref
),
9468 get_pool_mode (pool_ref
));
9470 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
9471 INSN_CODE (insn
) = -1;
9476 /* Dump out all literal pools. */
9478 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
9479 s390_dump_pool (curr_pool
, 0);
9481 /* Free pool list. */
9485 struct constant_pool
*next
= pool_list
->next
;
9486 s390_free_pool (pool_list
);
9491 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
9492 We have decided we cannot use this list, so revert all changes
9493 to the current function that were done by s390_chunkify_start. */
9496 s390_chunkify_cancel (struct constant_pool
*pool_list
)
9498 struct constant_pool
*curr_pool
= NULL
;
9501 /* Remove all pool placeholder insns. */
9503 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
9505 /* Did we insert an extra barrier? Remove it. */
9506 rtx_insn
*barrier
= PREV_INSN (curr_pool
->pool_insn
);
9507 rtx_insn
*jump
= barrier
? PREV_INSN (barrier
) : NULL
;
9508 rtx_insn
*label
= NEXT_INSN (curr_pool
->pool_insn
);
9510 if (jump
&& JUMP_P (jump
)
9511 && barrier
&& BARRIER_P (barrier
)
9512 && label
&& LABEL_P (label
)
9513 && GET_CODE (PATTERN (jump
)) == SET
9514 && SET_DEST (PATTERN (jump
)) == pc_rtx
9515 && GET_CODE (SET_SRC (PATTERN (jump
))) == LABEL_REF
9516 && XEXP (SET_SRC (PATTERN (jump
)), 0) == label
)
9519 remove_insn (barrier
);
9520 remove_insn (label
);
9523 remove_insn (curr_pool
->pool_insn
);
9526 /* Remove all base register reload insns. */
9528 for (insn
= get_insns (); insn
; )
9530 rtx_insn
*next_insn
= NEXT_INSN (insn
);
9532 if (NONJUMP_INSN_P (insn
)
9533 && GET_CODE (PATTERN (insn
)) == SET
9534 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC
9535 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPEC_RELOAD_BASE
)
9541 /* Free pool list. */
9545 struct constant_pool
*next
= pool_list
->next
;
9546 s390_free_pool (pool_list
);
9551 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
9554 s390_output_pool_entry (rtx exp
, machine_mode mode
, unsigned int align
)
9556 switch (GET_MODE_CLASS (mode
))
9559 case MODE_DECIMAL_FLOAT
:
9560 gcc_assert (GET_CODE (exp
) == CONST_DOUBLE
);
9562 assemble_real (*CONST_DOUBLE_REAL_VALUE (exp
),
9563 as_a
<scalar_float_mode
> (mode
), align
);
9567 assemble_integer (exp
, GET_MODE_SIZE (mode
), align
, 1);
9568 mark_symbol_refs_as_used (exp
);
9571 case MODE_VECTOR_INT
:
9572 case MODE_VECTOR_FLOAT
:
9575 machine_mode inner_mode
;
9576 gcc_assert (GET_CODE (exp
) == CONST_VECTOR
);
9578 inner_mode
= GET_MODE_INNER (GET_MODE (exp
));
9579 for (i
= 0; i
< XVECLEN (exp
, 0); i
++)
9580 s390_output_pool_entry (XVECEXP (exp
, 0, i
),
9584 : GET_MODE_BITSIZE (inner_mode
));
9594 /* Return an RTL expression representing the value of the return address
9595 for the frame COUNT steps up from the current frame. FRAME is the
9596 frame pointer of that frame. */
9599 s390_return_addr_rtx (int count
, rtx frame ATTRIBUTE_UNUSED
)
9604 /* Without backchain, we fail for all but the current frame. */
9606 if (!TARGET_BACKCHAIN
&& count
> 0)
9609 /* For the current frame, we need to make sure the initial
9610 value of RETURN_REGNUM is actually saved. */
9614 /* On non-z architectures branch splitting could overwrite r14. */
9615 if (TARGET_CPU_ZARCH
)
9616 return get_hard_reg_initial_val (Pmode
, RETURN_REGNUM
);
9619 cfun_frame_layout
.save_return_addr_p
= true;
9620 return gen_rtx_MEM (Pmode
, return_address_pointer_rtx
);
9624 if (TARGET_PACKED_STACK
)
9625 offset
= -2 * UNITS_PER_LONG
;
9627 offset
= RETURN_REGNUM
* UNITS_PER_LONG
;
9629 addr
= plus_constant (Pmode
, frame
, offset
);
9630 addr
= memory_address (Pmode
, addr
);
9631 return gen_rtx_MEM (Pmode
, addr
);
9634 /* Return an RTL expression representing the back chain stored in
9635 the current stack frame. */
9638 s390_back_chain_rtx (void)
9642 gcc_assert (TARGET_BACKCHAIN
);
9644 if (TARGET_PACKED_STACK
)
9645 chain
= plus_constant (Pmode
, stack_pointer_rtx
,
9646 STACK_POINTER_OFFSET
- UNITS_PER_LONG
);
9648 chain
= stack_pointer_rtx
;
9650 chain
= gen_rtx_MEM (Pmode
, chain
);
9654 /* Find first call clobbered register unused in a function.
9655 This could be used as base register in a leaf function
9656 or for holding the return address before epilogue. */
9659 find_unused_clobbered_reg (void)
9662 for (i
= 0; i
< 6; i
++)
9663 if (!df_regs_ever_live_p (i
))
9669 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
9670 clobbered hard regs in SETREG. */
9673 s390_reg_clobbered_rtx (rtx setreg
, const_rtx set_insn ATTRIBUTE_UNUSED
, void *data
)
9675 char *regs_ever_clobbered
= (char *)data
;
9676 unsigned int i
, regno
;
9677 machine_mode mode
= GET_MODE (setreg
);
9679 if (GET_CODE (setreg
) == SUBREG
)
9681 rtx inner
= SUBREG_REG (setreg
);
9682 if (!GENERAL_REG_P (inner
) && !FP_REG_P (inner
))
9684 regno
= subreg_regno (setreg
);
9686 else if (GENERAL_REG_P (setreg
) || FP_REG_P (setreg
))
9687 regno
= REGNO (setreg
);
9692 i
< end_hard_regno (mode
, regno
);
9694 regs_ever_clobbered
[i
] = 1;
9697 /* Walks through all basic blocks of the current function looking
9698 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
9699 of the passed integer array REGS_EVER_CLOBBERED are set to one for
9700 each of those regs. */
9703 s390_regs_ever_clobbered (char regs_ever_clobbered
[])
9709 memset (regs_ever_clobbered
, 0, 32);
9711 /* For non-leaf functions we have to consider all call clobbered regs to be
9715 for (i
= 0; i
< 32; i
++)
9716 regs_ever_clobbered
[i
] = call_really_used_regs
[i
];
9719 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
9720 this work is done by liveness analysis (mark_regs_live_at_end).
9721 Special care is needed for functions containing landing pads. Landing pads
9722 may use the eh registers, but the code which sets these registers is not
9723 contained in that function. Hence s390_regs_ever_clobbered is not able to
9724 deal with this automatically. */
9725 if (crtl
->calls_eh_return
|| cfun
->machine
->has_landing_pad_p
)
9726 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
9727 if (crtl
->calls_eh_return
9728 || (cfun
->machine
->has_landing_pad_p
9729 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i
))))
9730 regs_ever_clobbered
[EH_RETURN_DATA_REGNO (i
)] = 1;
9732 /* For nonlocal gotos all call-saved registers have to be saved.
9733 This flag is also set for the unwinding code in libgcc.
9734 See expand_builtin_unwind_init. For regs_ever_live this is done by
9736 if (crtl
->saves_all_registers
)
9737 for (i
= 0; i
< 32; i
++)
9738 if (!call_really_used_regs
[i
])
9739 regs_ever_clobbered
[i
] = 1;
9741 FOR_EACH_BB_FN (cur_bb
, cfun
)
9743 FOR_BB_INSNS (cur_bb
, cur_insn
)
9747 if (!INSN_P (cur_insn
))
9750 pat
= PATTERN (cur_insn
);
9752 /* Ignore GPR restore insns. */
9753 if (epilogue_completed
&& RTX_FRAME_RELATED_P (cur_insn
))
9755 if (GET_CODE (pat
) == SET
9756 && GENERAL_REG_P (SET_DEST (pat
)))
9759 if (GET_MODE (SET_SRC (pat
)) == DImode
9760 && FP_REG_P (SET_SRC (pat
)))
9764 if (GET_CODE (SET_SRC (pat
)) == MEM
)
9769 if (GET_CODE (pat
) == PARALLEL
9770 && load_multiple_operation (pat
, VOIDmode
))
9775 s390_reg_clobbered_rtx
,
9776 regs_ever_clobbered
);
9781 /* Determine the frame area which actually has to be accessed
9782 in the function epilogue. The values are stored at the
9783 given pointers AREA_BOTTOM (address of the lowest used stack
9784 address) and AREA_TOP (address of the first item which does
9785 not belong to the stack frame). */
9788 s390_frame_area (int *area_bottom
, int *area_top
)
9795 if (cfun_frame_layout
.first_restore_gpr
!= -1)
9797 b
= (cfun_frame_layout
.gprs_offset
9798 + cfun_frame_layout
.first_restore_gpr
* UNITS_PER_LONG
);
9799 t
= b
+ (cfun_frame_layout
.last_restore_gpr
9800 - cfun_frame_layout
.first_restore_gpr
+ 1) * UNITS_PER_LONG
;
9803 if (TARGET_64BIT
&& cfun_save_high_fprs_p
)
9805 b
= MIN (b
, cfun_frame_layout
.f8_offset
);
9806 t
= MAX (t
, (cfun_frame_layout
.f8_offset
9807 + cfun_frame_layout
.high_fprs
* 8));
9812 if (cfun_fpr_save_p (FPR4_REGNUM
))
9814 b
= MIN (b
, cfun_frame_layout
.f4_offset
);
9815 t
= MAX (t
, cfun_frame_layout
.f4_offset
+ 8);
9817 if (cfun_fpr_save_p (FPR6_REGNUM
))
9819 b
= MIN (b
, cfun_frame_layout
.f4_offset
+ 8);
9820 t
= MAX (t
, cfun_frame_layout
.f4_offset
+ 16);
9826 /* Update gpr_save_slots in the frame layout trying to make use of
9827 FPRs as GPR save slots.
9828 This is a helper routine of s390_register_info. */
9831 s390_register_info_gprtofpr ()
9833 int save_reg_slot
= FPR0_REGNUM
;
9836 if (!TARGET_Z10
|| !TARGET_HARD_FLOAT
|| !crtl
->is_leaf
)
9839 /* builtin_eh_return needs to be able to modify the return address
9840 on the stack. It could also adjust the FPR save slot instead but
9841 is it worth the trouble?! */
9842 if (crtl
->calls_eh_return
)
9845 for (i
= 15; i
>= 6; i
--)
9847 if (cfun_gpr_save_slot (i
) == SAVE_SLOT_NONE
)
9850 /* Advance to the next FP register which can be used as a
9852 while ((!call_really_used_regs
[save_reg_slot
]
9853 || df_regs_ever_live_p (save_reg_slot
)
9854 || cfun_fpr_save_p (save_reg_slot
))
9855 && FP_REGNO_P (save_reg_slot
))
9857 if (!FP_REGNO_P (save_reg_slot
))
9859 /* We only want to use ldgr/lgdr if we can get rid of
9860 stm/lm entirely. So undo the gpr slot allocation in
9861 case we ran out of FPR save slots. */
9862 for (j
= 6; j
<= 15; j
++)
9863 if (FP_REGNO_P (cfun_gpr_save_slot (j
)))
9864 cfun_gpr_save_slot (j
) = SAVE_SLOT_STACK
;
9867 cfun_gpr_save_slot (i
) = save_reg_slot
++;
9871 /* Set the bits in fpr_bitmap for FPRs which need to be saved due to
9873 This is a helper routine for s390_register_info. */
9876 s390_register_info_stdarg_fpr ()
9882 /* Save the FP argument regs for stdarg. f0, f2 for 31 bit and
9883 f0-f4 for 64 bit. */
9885 || !TARGET_HARD_FLOAT
9886 || !cfun
->va_list_fpr_size
9887 || crtl
->args
.info
.fprs
>= FP_ARG_NUM_REG
)
9890 min_fpr
= crtl
->args
.info
.fprs
;
9891 max_fpr
= min_fpr
+ cfun
->va_list_fpr_size
- 1;
9892 if (max_fpr
>= FP_ARG_NUM_REG
)
9893 max_fpr
= FP_ARG_NUM_REG
- 1;
9895 /* FPR argument regs start at f0. */
9896 min_fpr
+= FPR0_REGNUM
;
9897 max_fpr
+= FPR0_REGNUM
;
9899 for (i
= min_fpr
; i
<= max_fpr
; i
++)
9900 cfun_set_fpr_save (i
);
9903 /* Reserve the GPR save slots for GPRs which need to be saved due to
9905 This is a helper routine for s390_register_info. */
9908 s390_register_info_stdarg_gpr ()
9915 || !cfun
->va_list_gpr_size
9916 || crtl
->args
.info
.gprs
>= GP_ARG_NUM_REG
)
9919 min_gpr
= crtl
->args
.info
.gprs
;
9920 max_gpr
= min_gpr
+ cfun
->va_list_gpr_size
- 1;
9921 if (max_gpr
>= GP_ARG_NUM_REG
)
9922 max_gpr
= GP_ARG_NUM_REG
- 1;
9924 /* GPR argument regs start at r2. */
9925 min_gpr
+= GPR2_REGNUM
;
9926 max_gpr
+= GPR2_REGNUM
;
9928 /* If r6 was supposed to be saved into an FPR and now needs to go to
9929 the stack for vararg we have to adjust the restore range to make
9930 sure that the restore is done from stack as well. */
9931 if (FP_REGNO_P (cfun_gpr_save_slot (GPR6_REGNUM
))
9932 && min_gpr
<= GPR6_REGNUM
9933 && max_gpr
>= GPR6_REGNUM
)
9935 if (cfun_frame_layout
.first_restore_gpr
== -1
9936 || cfun_frame_layout
.first_restore_gpr
> GPR6_REGNUM
)
9937 cfun_frame_layout
.first_restore_gpr
= GPR6_REGNUM
;
9938 if (cfun_frame_layout
.last_restore_gpr
== -1
9939 || cfun_frame_layout
.last_restore_gpr
< GPR6_REGNUM
)
9940 cfun_frame_layout
.last_restore_gpr
= GPR6_REGNUM
;
9943 if (cfun_frame_layout
.first_save_gpr
== -1
9944 || cfun_frame_layout
.first_save_gpr
> min_gpr
)
9945 cfun_frame_layout
.first_save_gpr
= min_gpr
;
9947 if (cfun_frame_layout
.last_save_gpr
== -1
9948 || cfun_frame_layout
.last_save_gpr
< max_gpr
)
9949 cfun_frame_layout
.last_save_gpr
= max_gpr
;
9951 for (i
= min_gpr
; i
<= max_gpr
; i
++)
9952 cfun_gpr_save_slot (i
) = SAVE_SLOT_STACK
;
9955 /* Calculate the save and restore ranges for stm(g) and lm(g) in the
9956 prologue and epilogue. */
9959 s390_register_info_set_ranges ()
9963 /* Find the first and the last save slot supposed to use the stack
9964 to set the restore range.
9965 Vararg regs might be marked as save to stack but only the
9966 call-saved regs really need restoring (i.e. r6). This code
9967 assumes that the vararg regs have not yet been recorded in
9968 cfun_gpr_save_slot. */
9969 for (i
= 0; i
< 16 && cfun_gpr_save_slot (i
) != SAVE_SLOT_STACK
; i
++);
9970 for (j
= 15; j
> i
&& cfun_gpr_save_slot (j
) != SAVE_SLOT_STACK
; j
--);
9971 cfun_frame_layout
.first_restore_gpr
= (i
== 16) ? -1 : i
;
9972 cfun_frame_layout
.last_restore_gpr
= (i
== 16) ? -1 : j
;
9973 cfun_frame_layout
.first_save_gpr
= (i
== 16) ? -1 : i
;
9974 cfun_frame_layout
.last_save_gpr
= (i
== 16) ? -1 : j
;
9977 /* The GPR and FPR save slots in cfun->machine->frame_layout are set
9978 for registers which need to be saved in function prologue.
9979 This function can be used until the insns emitted for save/restore
9980 of the regs are visible in the RTL stream. */
9983 s390_register_info ()
9986 char clobbered_regs
[32];
9988 gcc_assert (!epilogue_completed
);
9990 if (reload_completed
)
9991 /* After reload we rely on our own routine to determine which
9992 registers need saving. */
9993 s390_regs_ever_clobbered (clobbered_regs
);
9995 /* During reload we use regs_ever_live as a base since reload
9996 does changes in there which we otherwise would not be aware
9998 for (i
= 0; i
< 32; i
++)
9999 clobbered_regs
[i
] = df_regs_ever_live_p (i
);
10001 for (i
= 0; i
< 32; i
++)
10002 clobbered_regs
[i
] = clobbered_regs
[i
] && !global_regs
[i
];
10004 /* Mark the call-saved FPRs which need to be saved.
10005 This needs to be done before checking the special GPRs since the
10006 stack pointer usage depends on whether high FPRs have to be saved
10008 cfun_frame_layout
.fpr_bitmap
= 0;
10009 cfun_frame_layout
.high_fprs
= 0;
10010 for (i
= FPR0_REGNUM
; i
<= FPR15_REGNUM
; i
++)
10011 if (clobbered_regs
[i
] && !call_really_used_regs
[i
])
10013 cfun_set_fpr_save (i
);
10014 if (i
>= FPR8_REGNUM
)
10015 cfun_frame_layout
.high_fprs
++;
10018 /* Register 12 is used for GOT address, but also as temp in prologue
10019 for split-stack stdarg functions (unless r14 is available). */
10021 |= ((flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
10022 || (flag_split_stack
&& cfun
->stdarg
10023 && (crtl
->is_leaf
|| TARGET_TPF_PROFILING
10024 || has_hard_reg_initial_val (Pmode
, RETURN_REGNUM
))));
10026 clobbered_regs
[BASE_REGNUM
]
10027 |= (cfun
->machine
->base_reg
10028 && REGNO (cfun
->machine
->base_reg
) == BASE_REGNUM
);
10030 clobbered_regs
[HARD_FRAME_POINTER_REGNUM
]
10031 |= !!frame_pointer_needed
;
10033 /* On pre z900 machines this might take until machine dependent
10035 save_return_addr_p will only be set on non-zarch machines so
10036 there is no risk that r14 goes into an FPR instead of a stack
10038 clobbered_regs
[RETURN_REGNUM
]
10040 || TARGET_TPF_PROFILING
10041 || cfun
->machine
->split_branches_pending_p
10042 || cfun_frame_layout
.save_return_addr_p
10043 || crtl
->calls_eh_return
);
10045 clobbered_regs
[STACK_POINTER_REGNUM
]
10047 || TARGET_TPF_PROFILING
10048 || cfun_save_high_fprs_p
10049 || get_frame_size () > 0
10050 || (reload_completed
&& cfun_frame_layout
.frame_size
> 0)
10051 || cfun
->calls_alloca
);
10053 memset (cfun_frame_layout
.gpr_save_slots
, SAVE_SLOT_NONE
, 16);
10055 for (i
= 6; i
< 16; i
++)
10056 if (clobbered_regs
[i
])
10057 cfun_gpr_save_slot (i
) = SAVE_SLOT_STACK
;
10059 s390_register_info_stdarg_fpr ();
10060 s390_register_info_gprtofpr ();
10061 s390_register_info_set_ranges ();
10062 /* stdarg functions might need to save GPRs 2 to 6. This might
10063 override the GPR->FPR save decision made by
10064 s390_register_info_gprtofpr for r6 since vararg regs must go to
10066 s390_register_info_stdarg_gpr ();
10069 /* This function is called by s390_optimize_prologue in order to get
10070 rid of unnecessary GPR save/restore instructions. The register info
10071 for the GPRs is re-computed and the ranges are re-calculated. */
10074 s390_optimize_register_info ()
10076 char clobbered_regs
[32];
10079 gcc_assert (epilogue_completed
);
10080 gcc_assert (!cfun
->machine
->split_branches_pending_p
);
10082 s390_regs_ever_clobbered (clobbered_regs
);
10084 for (i
= 0; i
< 32; i
++)
10085 clobbered_regs
[i
] = clobbered_regs
[i
] && !global_regs
[i
];
10087 /* There is still special treatment needed for cases invisible to
10088 s390_regs_ever_clobbered. */
10089 clobbered_regs
[RETURN_REGNUM
]
10090 |= (TARGET_TPF_PROFILING
10091 /* When expanding builtin_return_addr in ESA mode we do not
10092 know whether r14 will later be needed as scratch reg when
10093 doing branch splitting. So the builtin always accesses the
10094 r14 save slot and we need to stick to the save/restore
10095 decision for r14 even if it turns out that it didn't get
10097 || cfun_frame_layout
.save_return_addr_p
10098 || crtl
->calls_eh_return
);
10100 memset (cfun_frame_layout
.gpr_save_slots
, SAVE_SLOT_NONE
, 6);
10102 for (i
= 6; i
< 16; i
++)
10103 if (!clobbered_regs
[i
])
10104 cfun_gpr_save_slot (i
) = SAVE_SLOT_NONE
;
10106 s390_register_info_set_ranges ();
10107 s390_register_info_stdarg_gpr ();
10110 /* Fill cfun->machine with info about frame of current function. */
10113 s390_frame_info (void)
10115 HOST_WIDE_INT lowest_offset
;
10117 cfun_frame_layout
.first_save_gpr_slot
= cfun_frame_layout
.first_save_gpr
;
10118 cfun_frame_layout
.last_save_gpr_slot
= cfun_frame_layout
.last_save_gpr
;
10120 /* The va_arg builtin uses a constant distance of 16 *
10121 UNITS_PER_LONG (r0-r15) to reach the FPRs from the reg_save_area
10122 pointer. So even if we are going to save the stack pointer in an
10123 FPR we need the stack space in order to keep the offsets
10125 if (cfun
->stdarg
&& cfun_save_arg_fprs_p
)
10127 cfun_frame_layout
.last_save_gpr_slot
= STACK_POINTER_REGNUM
;
10129 if (cfun_frame_layout
.first_save_gpr_slot
== -1)
10130 cfun_frame_layout
.first_save_gpr_slot
= STACK_POINTER_REGNUM
;
10133 cfun_frame_layout
.frame_size
= get_frame_size ();
10134 if (!TARGET_64BIT
&& cfun_frame_layout
.frame_size
> 0x7fff0000)
10135 fatal_error (input_location
,
10136 "total size of local variables exceeds architecture limit");
10138 if (!TARGET_PACKED_STACK
)
10140 /* Fixed stack layout. */
10141 cfun_frame_layout
.backchain_offset
= 0;
10142 cfun_frame_layout
.f0_offset
= 16 * UNITS_PER_LONG
;
10143 cfun_frame_layout
.f4_offset
= cfun_frame_layout
.f0_offset
+ 2 * 8;
10144 cfun_frame_layout
.f8_offset
= -cfun_frame_layout
.high_fprs
* 8;
10145 cfun_frame_layout
.gprs_offset
= (cfun_frame_layout
.first_save_gpr_slot
10148 else if (TARGET_BACKCHAIN
)
10150 /* Kernel stack layout - packed stack, backchain, no float */
10151 gcc_assert (TARGET_SOFT_FLOAT
);
10152 cfun_frame_layout
.backchain_offset
= (STACK_POINTER_OFFSET
10155 /* The distance between the backchain and the return address
10156 save slot must not change. So we always need a slot for the
10157 stack pointer which resides in between. */
10158 cfun_frame_layout
.last_save_gpr_slot
= STACK_POINTER_REGNUM
;
10160 cfun_frame_layout
.gprs_offset
10161 = cfun_frame_layout
.backchain_offset
- cfun_gprs_save_area_size
;
10163 /* FPRs will not be saved. Nevertheless pick sane values to
10164 keep area calculations valid. */
10165 cfun_frame_layout
.f0_offset
=
10166 cfun_frame_layout
.f4_offset
=
10167 cfun_frame_layout
.f8_offset
= cfun_frame_layout
.gprs_offset
;
10173 /* Packed stack layout without backchain. */
10175 /* With stdarg FPRs need their dedicated slots. */
10176 num_fprs
= (TARGET_64BIT
&& cfun
->stdarg
? 2
10177 : (cfun_fpr_save_p (FPR4_REGNUM
) +
10178 cfun_fpr_save_p (FPR6_REGNUM
)));
10179 cfun_frame_layout
.f4_offset
= STACK_POINTER_OFFSET
- 8 * num_fprs
;
10181 num_fprs
= (cfun
->stdarg
? 2
10182 : (cfun_fpr_save_p (FPR0_REGNUM
)
10183 + cfun_fpr_save_p (FPR2_REGNUM
)));
10184 cfun_frame_layout
.f0_offset
= cfun_frame_layout
.f4_offset
- 8 * num_fprs
;
10186 cfun_frame_layout
.gprs_offset
10187 = cfun_frame_layout
.f0_offset
- cfun_gprs_save_area_size
;
10189 cfun_frame_layout
.f8_offset
= (cfun_frame_layout
.gprs_offset
10190 - cfun_frame_layout
.high_fprs
* 8);
10193 if (cfun_save_high_fprs_p
)
10194 cfun_frame_layout
.frame_size
+= cfun_frame_layout
.high_fprs
* 8;
10196 if (!crtl
->is_leaf
)
10197 cfun_frame_layout
.frame_size
+= crtl
->outgoing_args_size
;
10199 /* In the following cases we have to allocate a STACK_POINTER_OFFSET
10200 sized area at the bottom of the stack. This is required also for
10201 leaf functions. When GCC generates a local stack reference it
10202 will always add STACK_POINTER_OFFSET to all these references. */
10204 && !TARGET_TPF_PROFILING
10205 && cfun_frame_layout
.frame_size
== 0
10206 && !cfun
->calls_alloca
)
10209 /* Calculate the number of bytes we have used in our own register
10210 save area. With the packed stack layout we can re-use the
10211 remaining bytes for normal stack elements. */
10213 if (TARGET_PACKED_STACK
)
10214 lowest_offset
= MIN (MIN (cfun_frame_layout
.f0_offset
,
10215 cfun_frame_layout
.f4_offset
),
10216 cfun_frame_layout
.gprs_offset
);
10220 if (TARGET_BACKCHAIN
)
10221 lowest_offset
= MIN (lowest_offset
, cfun_frame_layout
.backchain_offset
);
10223 cfun_frame_layout
.frame_size
+= STACK_POINTER_OFFSET
- lowest_offset
;
10225 /* If under 31 bit an odd number of gprs has to be saved we have to
10226 adjust the frame size to sustain 8 byte alignment of stack
10228 cfun_frame_layout
.frame_size
= ((cfun_frame_layout
.frame_size
+
10229 STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
10230 & ~(STACK_BOUNDARY
/ BITS_PER_UNIT
- 1));
10233 /* Generate frame layout. Fills in register and frame data for the current
10234 function in cfun->machine. This routine can be called multiple times;
10235 it will re-do the complete frame layout every time. */
10238 s390_init_frame_layout (void)
10240 HOST_WIDE_INT frame_size
;
10243 /* After LRA the frame layout is supposed to be read-only and should
10244 not be re-computed. */
10245 if (reload_completed
)
10248 /* On S/390 machines, we may need to perform branch splitting, which
10249 will require both base and return address register. We have no
10250 choice but to assume we're going to need them until right at the
10251 end of the machine dependent reorg phase. */
10252 if (!TARGET_CPU_ZARCH
)
10253 cfun
->machine
->split_branches_pending_p
= true;
10257 frame_size
= cfun_frame_layout
.frame_size
;
10259 /* Try to predict whether we'll need the base register. */
10260 base_used
= cfun
->machine
->split_branches_pending_p
10261 || crtl
->uses_const_pool
10262 || (!DISP_IN_RANGE (frame_size
)
10263 && !CONST_OK_FOR_K (frame_size
));
10265 /* Decide which register to use as literal pool base. In small
10266 leaf functions, try to use an unused call-clobbered register
10267 as base register to avoid save/restore overhead. */
10269 cfun
->machine
->base_reg
= NULL_RTX
;
10275 /* Prefer r5 (most likely to be free). */
10276 for (br
= 5; br
>= 2 && df_regs_ever_live_p (br
); br
--)
10278 cfun
->machine
->base_reg
=
10279 gen_rtx_REG (Pmode
, (br
>= 2) ? br
: BASE_REGNUM
);
10282 s390_register_info ();
10283 s390_frame_info ();
10285 while (frame_size
!= cfun_frame_layout
.frame_size
);
10288 /* Remove the FPR clobbers from a tbegin insn if it can be proven that
10289 the TX is nonescaping. A transaction is considered escaping if
10290 there is at least one path from tbegin returning CC0 to the
10291 function exit block without an tend.
10293 The check so far has some limitations:
10294 - only single tbegin/tend BBs are supported
10295 - the first cond jump after tbegin must separate the CC0 path from ~CC0
10296 - when CC is copied to a GPR and the CC0 check is done with the GPR
10297 this is not supported
10301 s390_optimize_nonescaping_tx (void)
10303 const unsigned int CC0
= 1 << 3;
10304 basic_block tbegin_bb
= NULL
;
10305 basic_block tend_bb
= NULL
;
10308 bool result
= true;
10310 rtx_insn
*tbegin_insn
= NULL
;
10312 if (!cfun
->machine
->tbegin_p
)
10315 for (bb_index
= 0; bb_index
< n_basic_blocks_for_fn (cfun
); bb_index
++)
10317 bb
= BASIC_BLOCK_FOR_FN (cfun
, bb_index
);
10322 FOR_BB_INSNS (bb
, insn
)
10324 rtx ite
, cc
, pat
, target
;
10325 unsigned HOST_WIDE_INT mask
;
10327 if (!INSN_P (insn
) || INSN_CODE (insn
) <= 0)
10330 pat
= PATTERN (insn
);
10332 if (GET_CODE (pat
) == PARALLEL
)
10333 pat
= XVECEXP (pat
, 0, 0);
10335 if (GET_CODE (pat
) != SET
10336 || GET_CODE (SET_SRC (pat
)) != UNSPEC_VOLATILE
)
10339 if (XINT (SET_SRC (pat
), 1) == UNSPECV_TBEGIN
)
10343 tbegin_insn
= insn
;
10345 /* Just return if the tbegin doesn't have clobbers. */
10346 if (GET_CODE (PATTERN (insn
)) != PARALLEL
)
10349 if (tbegin_bb
!= NULL
)
10352 /* Find the next conditional jump. */
10353 for (tmp
= NEXT_INSN (insn
);
10355 tmp
= NEXT_INSN (tmp
))
10357 if (reg_set_p (gen_rtx_REG (CCmode
, CC_REGNUM
), tmp
))
10362 ite
= SET_SRC (PATTERN (tmp
));
10363 if (GET_CODE (ite
) != IF_THEN_ELSE
)
10366 cc
= XEXP (XEXP (ite
, 0), 0);
10367 if (!REG_P (cc
) || !CC_REGNO_P (REGNO (cc
))
10368 || GET_MODE (cc
) != CCRAWmode
10369 || GET_CODE (XEXP (XEXP (ite
, 0), 1)) != CONST_INT
)
10372 if (bb
->succs
->length () != 2)
10375 mask
= INTVAL (XEXP (XEXP (ite
, 0), 1));
10376 if (GET_CODE (XEXP (ite
, 0)) == NE
)
10380 target
= XEXP (ite
, 1);
10381 else if (mask
== (CC0
^ 0xf))
10382 target
= XEXP (ite
, 2);
10390 ei
= ei_start (bb
->succs
);
10391 e1
= ei_safe_edge (ei
);
10393 e2
= ei_safe_edge (ei
);
10395 if (e2
->flags
& EDGE_FALLTHRU
)
10398 e1
= ei_safe_edge (ei
);
10401 if (!(e1
->flags
& EDGE_FALLTHRU
))
10404 tbegin_bb
= (target
== pc_rtx
) ? e1
->dest
: e2
->dest
;
10406 if (tmp
== BB_END (bb
))
10411 if (XINT (SET_SRC (pat
), 1) == UNSPECV_TEND
)
10413 if (tend_bb
!= NULL
)
10420 /* Either we successfully remove the FPR clobbers here or we are not
10421 able to do anything for this TX. Both cases don't qualify for
10423 cfun
->machine
->tbegin_p
= false;
10425 if (tbegin_bb
== NULL
|| tend_bb
== NULL
)
10428 calculate_dominance_info (CDI_POST_DOMINATORS
);
10429 result
= dominated_by_p (CDI_POST_DOMINATORS
, tbegin_bb
, tend_bb
);
10430 free_dominance_info (CDI_POST_DOMINATORS
);
10435 PATTERN (tbegin_insn
) = gen_rtx_PARALLEL (VOIDmode
,
10437 XVECEXP (PATTERN (tbegin_insn
), 0, 0),
10438 XVECEXP (PATTERN (tbegin_insn
), 0, 1)));
10439 INSN_CODE (tbegin_insn
) = -1;
10440 df_insn_rescan (tbegin_insn
);
10445 /* Implement TARGET_HARD_REGNO_NREGS. Because all registers in a class
10446 have the same size, this is equivalent to CLASS_MAX_NREGS. */
10448 static unsigned int
10449 s390_hard_regno_nregs (unsigned int regno
, machine_mode mode
)
10451 return s390_class_max_nregs (REGNO_REG_CLASS (regno
), mode
);
10454 /* Implement TARGET_HARD_REGNO_MODE_OK.
10456 Integer modes <= word size fit into any GPR.
10457 Integer modes > word size fit into successive GPRs, starting with
10458 an even-numbered register.
10459 SImode and DImode fit into FPRs as well.
10461 Floating point modes <= word size fit into any FPR or GPR.
10462 Floating point modes > word size (i.e. DFmode on 32-bit) fit
10463 into any FPR, or an even-odd GPR pair.
10464 TFmode fits only into an even-odd FPR pair.
10466 Complex floating point modes fit either into two FPRs, or into
10467 successive GPRs (again starting with an even number).
10468 TCmode fits only into two successive even-odd FPR pairs.
10470 Condition code modes fit only into the CC register. */
10473 s390_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
10475 if (!TARGET_VX
&& VECTOR_NOFP_REGNO_P (regno
))
10478 switch (REGNO_REG_CLASS (regno
))
10481 return ((GET_MODE_CLASS (mode
) == MODE_INT
10482 && s390_class_max_nregs (VEC_REGS
, mode
) == 1)
10484 || (TARGET_VXE
&& mode
== SFmode
)
10485 || s390_vector_mode_supported_p (mode
));
10489 && ((GET_MODE_CLASS (mode
) == MODE_INT
10490 && s390_class_max_nregs (FP_REGS
, mode
) == 1)
10492 || s390_vector_mode_supported_p (mode
)))
10495 if (REGNO_PAIR_OK (regno
, mode
))
10497 if (mode
== SImode
|| mode
== DImode
)
10500 if (FLOAT_MODE_P (mode
) && GET_MODE_CLASS (mode
) != MODE_VECTOR_FLOAT
)
10505 if (FRAME_REGNO_P (regno
) && mode
== Pmode
)
10510 if (REGNO_PAIR_OK (regno
, mode
))
10513 || (mode
!= TFmode
&& mode
!= TCmode
&& mode
!= TDmode
))
10518 if (GET_MODE_CLASS (mode
) == MODE_CC
)
10522 if (REGNO_PAIR_OK (regno
, mode
))
10524 if (mode
== SImode
|| mode
== Pmode
)
10535 /* Implement TARGET_MODES_TIEABLE_P. */
10538 s390_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
10540 return ((mode1
== SFmode
|| mode1
== DFmode
)
10541 == (mode2
== SFmode
|| mode2
== DFmode
));
10544 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
10547 s390_hard_regno_rename_ok (unsigned int old_reg
, unsigned int new_reg
)
10549 /* Once we've decided upon a register to use as base register, it must
10550 no longer be used for any other purpose. */
10551 if (cfun
->machine
->base_reg
)
10552 if (REGNO (cfun
->machine
->base_reg
) == old_reg
10553 || REGNO (cfun
->machine
->base_reg
) == new_reg
)
10556 /* Prevent regrename from using call-saved regs which haven't
10557 actually been saved. This is necessary since regrename assumes
10558 the backend save/restore decisions are based on
10559 df_regs_ever_live. Since we have our own routine we have to tell
10560 regrename manually about it. */
10561 if (GENERAL_REGNO_P (new_reg
)
10562 && !call_really_used_regs
[new_reg
]
10563 && cfun_gpr_save_slot (new_reg
) == SAVE_SLOT_NONE
)
10569 /* Return nonzero if register REGNO can be used as a scratch register
10573 s390_hard_regno_scratch_ok (unsigned int regno
)
10575 /* See s390_hard_regno_rename_ok. */
10576 if (GENERAL_REGNO_P (regno
)
10577 && !call_really_used_regs
[regno
]
10578 && cfun_gpr_save_slot (regno
) == SAVE_SLOT_NONE
)
10584 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. When generating
10585 code that runs in z/Architecture mode, but conforms to the 31-bit
10586 ABI, GPRs can hold 8 bytes; the ABI guarantees only that the lower 4
10587 bytes are saved across calls, however. */
10590 s390_hard_regno_call_part_clobbered (unsigned int regno
, machine_mode mode
)
10594 && GET_MODE_SIZE (mode
) > 4
10595 && ((regno
>= 6 && regno
<= 15) || regno
== 32))
10599 && GET_MODE_SIZE (mode
) > 8
10600 && (((TARGET_64BIT
&& regno
>= 24 && regno
<= 31))
10601 || (!TARGET_64BIT
&& (regno
== 18 || regno
== 19))))
10607 /* Maximum number of registers to represent a value of mode MODE
10608 in a register of class RCLASS. */
10611 s390_class_max_nregs (enum reg_class rclass
, machine_mode mode
)
10614 bool reg_pair_required_p
= false;
10620 reg_size
= TARGET_VX
? 16 : 8;
10622 /* TF and TD modes would fit into a VR but we put them into a
10623 register pair since we do not have 128bit FP instructions on
10626 && SCALAR_FLOAT_MODE_P (mode
)
10627 && GET_MODE_SIZE (mode
) >= 16)
10628 reg_pair_required_p
= true;
10630 /* Even if complex types would fit into a single FPR/VR we force
10631 them into a register pair to deal with the parts more easily.
10632 (FIXME: What about complex ints?) */
10633 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
10634 reg_pair_required_p
= true;
10640 reg_size
= UNITS_PER_WORD
;
10644 if (reg_pair_required_p
)
10645 return 2 * ((GET_MODE_SIZE (mode
) / 2 + reg_size
- 1) / reg_size
);
10647 return (GET_MODE_SIZE (mode
) + reg_size
- 1) / reg_size
;
10650 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
10653 s390_can_change_mode_class (machine_mode from_mode
,
10654 machine_mode to_mode
,
10655 reg_class_t rclass
)
10657 machine_mode small_mode
;
10658 machine_mode big_mode
;
10660 /* V1TF and TF have different representations in vector
10662 if (reg_classes_intersect_p (VEC_REGS
, rclass
)
10663 && ((from_mode
== V1TFmode
&& to_mode
== TFmode
)
10664 || (from_mode
== TFmode
&& to_mode
== V1TFmode
)))
10667 if (GET_MODE_SIZE (from_mode
) == GET_MODE_SIZE (to_mode
))
10670 if (GET_MODE_SIZE (from_mode
) < GET_MODE_SIZE (to_mode
))
10672 small_mode
= from_mode
;
10673 big_mode
= to_mode
;
10677 small_mode
= to_mode
;
10678 big_mode
= from_mode
;
10681 /* Values residing in VRs are little-endian style. All modes are
10682 placed left-aligned in an VR. This means that we cannot allow
10683 switching between modes with differing sizes. Also if the vector
10684 facility is available we still place TFmode values in VR register
10685 pairs, since the only instructions we have operating on TFmodes
10686 only deal with register pairs. Therefore we have to allow DFmode
10687 subregs of TFmodes to enable the TFmode splitters. */
10688 if (reg_classes_intersect_p (VEC_REGS
, rclass
)
10689 && (GET_MODE_SIZE (small_mode
) < 8
10690 || s390_class_max_nregs (VEC_REGS
, big_mode
) == 1))
10693 /* Likewise for access registers, since they have only half the
10694 word size on 64-bit. */
10695 if (reg_classes_intersect_p (ACCESS_REGS
, rclass
))
10701 /* Return true if we use LRA instead of reload pass. */
10705 return s390_lra_flag
;
10708 /* Return true if register FROM can be eliminated via register TO. */
10711 s390_can_eliminate (const int from
, const int to
)
10713 /* On zSeries machines, we have not marked the base register as fixed.
10714 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
10715 If a function requires the base register, we say here that this
10716 elimination cannot be performed. This will cause reload to free
10717 up the base register (as if it were fixed). On the other hand,
10718 if the current function does *not* require the base register, we
10719 say here the elimination succeeds, which in turn allows reload
10720 to allocate the base register for any other purpose. */
10721 if (from
== BASE_REGNUM
&& to
== BASE_REGNUM
)
10723 if (TARGET_CPU_ZARCH
)
10725 s390_init_frame_layout ();
10726 return cfun
->machine
->base_reg
== NULL_RTX
;
10732 /* Everything else must point into the stack frame. */
10733 gcc_assert (to
== STACK_POINTER_REGNUM
10734 || to
== HARD_FRAME_POINTER_REGNUM
);
10736 gcc_assert (from
== FRAME_POINTER_REGNUM
10737 || from
== ARG_POINTER_REGNUM
10738 || from
== RETURN_ADDRESS_POINTER_REGNUM
);
10740 /* Make sure we actually saved the return address. */
10741 if (from
== RETURN_ADDRESS_POINTER_REGNUM
)
10742 if (!crtl
->calls_eh_return
10744 && !cfun_frame_layout
.save_return_addr_p
)
10750 /* Return offset between register FROM and TO initially after prolog. */
10753 s390_initial_elimination_offset (int from
, int to
)
10755 HOST_WIDE_INT offset
;
10757 /* ??? Why are we called for non-eliminable pairs? */
10758 if (!s390_can_eliminate (from
, to
))
10763 case FRAME_POINTER_REGNUM
:
10764 offset
= (get_frame_size()
10765 + STACK_POINTER_OFFSET
10766 + crtl
->outgoing_args_size
);
10769 case ARG_POINTER_REGNUM
:
10770 s390_init_frame_layout ();
10771 offset
= cfun_frame_layout
.frame_size
+ STACK_POINTER_OFFSET
;
10774 case RETURN_ADDRESS_POINTER_REGNUM
:
10775 s390_init_frame_layout ();
10777 if (cfun_frame_layout
.first_save_gpr_slot
== -1)
10779 /* If it turns out that for stdarg nothing went into the reg
10780 save area we also do not need the return address
10782 if (cfun
->stdarg
&& !cfun_save_arg_fprs_p
)
10785 gcc_unreachable ();
10788 /* In order to make the following work it is not necessary for
10789 r14 to have a save slot. It is sufficient if one other GPR
10790 got one. Since the GPRs are always stored without gaps we
10791 are able to calculate where the r14 save slot would
10793 offset
= (cfun_frame_layout
.frame_size
+ cfun_frame_layout
.gprs_offset
+
10794 (RETURN_REGNUM
- cfun_frame_layout
.first_save_gpr_slot
) *
10803 gcc_unreachable ();
10809 /* Emit insn to save fpr REGNUM at offset OFFSET relative
10810 to register BASE. Return generated insn. */
10813 save_fpr (rtx base
, int offset
, int regnum
)
10816 addr
= gen_rtx_MEM (DFmode
, plus_constant (Pmode
, base
, offset
));
10818 if (regnum
>= 16 && regnum
<= (16 + FP_ARG_NUM_REG
))
10819 set_mem_alias_set (addr
, get_varargs_alias_set ());
10821 set_mem_alias_set (addr
, get_frame_alias_set ());
10823 return emit_move_insn (addr
, gen_rtx_REG (DFmode
, regnum
));
10826 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
10827 to register BASE. Return generated insn. */
10830 restore_fpr (rtx base
, int offset
, int regnum
)
10833 addr
= gen_rtx_MEM (DFmode
, plus_constant (Pmode
, base
, offset
));
10834 set_mem_alias_set (addr
, get_frame_alias_set ());
10836 return emit_move_insn (gen_rtx_REG (DFmode
, regnum
), addr
);
10839 /* Return true if REGNO is a global register, but not one
10840 of the special ones that need to be saved/restored in anyway. */
10843 global_not_special_regno_p (int regno
)
10845 return (global_regs
[regno
]
10846 /* These registers are special and need to be
10847 restored in any case. */
10848 && !(regno
== STACK_POINTER_REGNUM
10849 || regno
== RETURN_REGNUM
10850 || regno
== BASE_REGNUM
10851 || (flag_pic
&& regno
== (int)PIC_OFFSET_TABLE_REGNUM
)));
10854 /* Generate insn to save registers FIRST to LAST into
10855 the register save area located at offset OFFSET
10856 relative to register BASE. */
10859 save_gprs (rtx base
, int offset
, int first
, int last
)
10861 rtx addr
, insn
, note
;
10864 addr
= plus_constant (Pmode
, base
, offset
);
10865 addr
= gen_rtx_MEM (Pmode
, addr
);
10867 set_mem_alias_set (addr
, get_frame_alias_set ());
10869 /* Special-case single register. */
10873 insn
= gen_movdi (addr
, gen_rtx_REG (Pmode
, first
));
10875 insn
= gen_movsi (addr
, gen_rtx_REG (Pmode
, first
));
10877 if (!global_not_special_regno_p (first
))
10878 RTX_FRAME_RELATED_P (insn
) = 1;
10883 insn
= gen_store_multiple (addr
,
10884 gen_rtx_REG (Pmode
, first
),
10885 GEN_INT (last
- first
+ 1));
10887 if (first
<= 6 && cfun
->stdarg
)
10888 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
10890 rtx mem
= XEXP (XVECEXP (PATTERN (insn
), 0, i
), 0);
10892 if (first
+ i
<= 6)
10893 set_mem_alias_set (mem
, get_varargs_alias_set ());
10896 /* We need to set the FRAME_RELATED flag on all SETs
10897 inside the store-multiple pattern.
10899 However, we must not emit DWARF records for registers 2..5
10900 if they are stored for use by variable arguments ...
10902 ??? Unfortunately, it is not enough to simply not the
10903 FRAME_RELATED flags for those SETs, because the first SET
10904 of the PARALLEL is always treated as if it had the flag
10905 set, even if it does not. Therefore we emit a new pattern
10906 without those registers as REG_FRAME_RELATED_EXPR note. */
10908 if (first
>= 6 && !global_not_special_regno_p (first
))
10910 rtx pat
= PATTERN (insn
);
10912 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
10913 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
10914 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat
,
10916 RTX_FRAME_RELATED_P (XVECEXP (pat
, 0, i
)) = 1;
10918 RTX_FRAME_RELATED_P (insn
) = 1;
10920 else if (last
>= 6)
10924 for (start
= first
>= 6 ? first
: 6; start
<= last
; start
++)
10925 if (!global_not_special_regno_p (start
))
10931 addr
= plus_constant (Pmode
, base
,
10932 offset
+ (start
- first
) * UNITS_PER_LONG
);
10937 note
= gen_movdi (gen_rtx_MEM (Pmode
, addr
),
10938 gen_rtx_REG (Pmode
, start
));
10940 note
= gen_movsi (gen_rtx_MEM (Pmode
, addr
),
10941 gen_rtx_REG (Pmode
, start
));
10942 note
= PATTERN (note
);
10944 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note
);
10945 RTX_FRAME_RELATED_P (insn
) = 1;
10950 note
= gen_store_multiple (gen_rtx_MEM (Pmode
, addr
),
10951 gen_rtx_REG (Pmode
, start
),
10952 GEN_INT (last
- start
+ 1));
10953 note
= PATTERN (note
);
10955 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, note
);
10957 for (i
= 0; i
< XVECLEN (note
, 0); i
++)
10958 if (GET_CODE (XVECEXP (note
, 0, i
)) == SET
10959 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note
,
10961 RTX_FRAME_RELATED_P (XVECEXP (note
, 0, i
)) = 1;
10963 RTX_FRAME_RELATED_P (insn
) = 1;
10969 /* Generate insn to restore registers FIRST to LAST from
10970 the register save area located at offset OFFSET
10971 relative to register BASE. */
10974 restore_gprs (rtx base
, int offset
, int first
, int last
)
10978 addr
= plus_constant (Pmode
, base
, offset
);
10979 addr
= gen_rtx_MEM (Pmode
, addr
);
10980 set_mem_alias_set (addr
, get_frame_alias_set ());
10982 /* Special-case single register. */
10986 insn
= gen_movdi (gen_rtx_REG (Pmode
, first
), addr
);
10988 insn
= gen_movsi (gen_rtx_REG (Pmode
, first
), addr
);
10990 RTX_FRAME_RELATED_P (insn
) = 1;
10994 insn
= gen_load_multiple (gen_rtx_REG (Pmode
, first
),
10996 GEN_INT (last
- first
+ 1));
10997 RTX_FRAME_RELATED_P (insn
) = 1;
11001 /* Return insn sequence to load the GOT register. */
11004 s390_load_got (void)
11008 /* We cannot use pic_offset_table_rtx here since we use this
11009 function also for non-pic if __tls_get_offset is called and in
11010 that case PIC_OFFSET_TABLE_REGNUM as well as pic_offset_table_rtx
11012 rtx got_rtx
= gen_rtx_REG (Pmode
, 12);
11016 if (TARGET_CPU_ZARCH
)
11018 emit_move_insn (got_rtx
, s390_got_symbol ());
11024 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, s390_got_symbol ()),
11025 UNSPEC_LTREL_OFFSET
);
11026 offset
= gen_rtx_CONST (Pmode
, offset
);
11027 offset
= force_const_mem (Pmode
, offset
);
11029 emit_move_insn (got_rtx
, offset
);
11031 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, XEXP (offset
, 0)),
11032 UNSPEC_LTREL_BASE
);
11033 offset
= gen_rtx_PLUS (Pmode
, got_rtx
, offset
);
11035 emit_move_insn (got_rtx
, offset
);
11038 insns
= get_insns ();
11043 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
11044 and the change to the stack pointer. */
11047 s390_emit_stack_tie (void)
11049 rtx mem
= gen_frame_mem (BLKmode
,
11050 gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
));
11052 emit_insn (gen_stack_tie (mem
));
11055 /* Copy GPRS into FPR save slots. */
11058 s390_save_gprs_to_fprs (void)
11062 if (!TARGET_Z10
|| !TARGET_HARD_FLOAT
|| !crtl
->is_leaf
)
11065 for (i
= 6; i
< 16; i
++)
11067 if (FP_REGNO_P (cfun_gpr_save_slot (i
)))
11070 emit_move_insn (gen_rtx_REG (DImode
, cfun_gpr_save_slot (i
)),
11071 gen_rtx_REG (DImode
, i
));
11072 RTX_FRAME_RELATED_P (insn
) = 1;
11073 /* This prevents dwarf2cfi from interpreting the set. Doing
11074 so it might emit def_cfa_register infos setting an FPR as
11076 add_reg_note (insn
, REG_CFA_REGISTER
, copy_rtx (PATTERN (insn
)));
11081 /* Restore GPRs from FPR save slots. */
11084 s390_restore_gprs_from_fprs (void)
11088 if (!TARGET_Z10
|| !TARGET_HARD_FLOAT
|| !crtl
->is_leaf
)
11091 for (i
= 6; i
< 16; i
++)
11095 if (!FP_REGNO_P (cfun_gpr_save_slot (i
)))
11098 rtx fpr
= gen_rtx_REG (DImode
, cfun_gpr_save_slot (i
));
11100 if (i
== STACK_POINTER_REGNUM
)
11101 insn
= emit_insn (gen_stack_restore_from_fpr (fpr
));
11103 insn
= emit_move_insn (gen_rtx_REG (DImode
, i
), fpr
);
11105 df_set_regs_ever_live (i
, true);
11106 add_reg_note (insn
, REG_CFA_RESTORE
, gen_rtx_REG (DImode
, i
));
11107 if (i
== STACK_POINTER_REGNUM
)
11108 add_reg_note (insn
, REG_CFA_DEF_CFA
,
11109 plus_constant (Pmode
, stack_pointer_rtx
,
11110 STACK_POINTER_OFFSET
));
11111 RTX_FRAME_RELATED_P (insn
) = 1;
11116 /* A pass run immediately before shrink-wrapping and prologue and epilogue
11121 const pass_data pass_data_s390_early_mach
=
11123 RTL_PASS
, /* type */
11124 "early_mach", /* name */
11125 OPTGROUP_NONE
, /* optinfo_flags */
11126 TV_MACH_DEP
, /* tv_id */
11127 0, /* properties_required */
11128 0, /* properties_provided */
11129 0, /* properties_destroyed */
11130 0, /* todo_flags_start */
11131 ( TODO_df_verify
| TODO_df_finish
), /* todo_flags_finish */
11134 class pass_s390_early_mach
: public rtl_opt_pass
11137 pass_s390_early_mach (gcc::context
*ctxt
)
11138 : rtl_opt_pass (pass_data_s390_early_mach
, ctxt
)
11141 /* opt_pass methods: */
11142 virtual unsigned int execute (function
*);
11144 }; // class pass_s390_early_mach
11147 pass_s390_early_mach::execute (function
*fun
)
11151 /* Try to get rid of the FPR clobbers. */
11152 s390_optimize_nonescaping_tx ();
11154 /* Re-compute register info. */
11155 s390_register_info ();
11157 /* If we're using a base register, ensure that it is always valid for
11158 the first non-prologue instruction. */
11159 if (fun
->machine
->base_reg
)
11160 emit_insn_at_entry (gen_main_pool (fun
->machine
->base_reg
));
11162 /* Annotate all constant pool references to let the scheduler know
11163 they implicitly use the base register. */
11164 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
11167 annotate_constant_pool_refs (&PATTERN (insn
));
11168 df_insn_rescan (insn
);
11173 } // anon namespace
11175 /* Calculate TARGET = REG + OFFSET as s390_emit_prologue would do it.
11176 - push too big immediates to the literal pool and annotate the refs
11177 - emit frame related notes for stack pointer changes. */
11180 s390_prologue_plus_offset (rtx target
, rtx reg
, rtx offset
, bool frame_related_p
)
11183 rtx orig_offset
= offset
;
11185 gcc_assert (REG_P (target
));
11186 gcc_assert (REG_P (reg
));
11187 gcc_assert (CONST_INT_P (offset
));
11189 if (offset
== const0_rtx
) /* lr/lgr */
11191 insn
= emit_move_insn (target
, reg
);
11193 else if (DISP_IN_RANGE (INTVAL (offset
))) /* la */
11195 insn
= emit_move_insn (target
, gen_rtx_PLUS (Pmode
, reg
,
11200 if (!satisfies_constraint_K (offset
) /* ahi/aghi */
11202 || (!satisfies_constraint_Op (offset
) /* alfi/algfi */
11203 && !satisfies_constraint_On (offset
)))) /* slfi/slgfi */
11204 offset
= force_const_mem (Pmode
, offset
);
11208 insn
= emit_move_insn (target
, reg
);
11209 RTX_FRAME_RELATED_P (insn
) = frame_related_p
? 1 : 0;
11212 insn
= emit_insn (gen_add2_insn (target
, offset
));
11214 if (!CONST_INT_P (offset
))
11216 annotate_constant_pool_refs (&PATTERN (insn
));
11218 if (frame_related_p
)
11219 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
11220 gen_rtx_SET (target
,
11221 gen_rtx_PLUS (Pmode
, target
,
11226 RTX_FRAME_RELATED_P (insn
) = frame_related_p
? 1 : 0;
11228 /* If this is a stack adjustment and we are generating a stack clash
11229 prologue, then add a REG_STACK_CHECK note to signal that this insn
11230 should be left alone. */
11231 if (flag_stack_clash_protection
&& target
== stack_pointer_rtx
)
11232 add_reg_note (insn
, REG_STACK_CHECK
, const0_rtx
);
11237 /* Emit a compare instruction with a volatile memory access as stack
11238 probe. It does not waste store tags and does not clobber any
11239 registers apart from the condition code. */
11241 s390_emit_stack_probe (rtx addr
)
11243 rtx tmp
= gen_rtx_MEM (Pmode
, addr
);
11244 MEM_VOLATILE_P (tmp
) = 1;
11245 s390_emit_compare (EQ
, gen_rtx_REG (Pmode
, 0), tmp
);
11246 emit_insn (gen_blockage ());
11249 /* Use a runtime loop if we have to emit more probes than this. */
11250 #define MIN_UNROLL_PROBES 3
11252 /* Allocate SIZE bytes of stack space, using TEMP_REG as a temporary
11253 if necessary. LAST_PROBE_OFFSET contains the offset of the closest
11254 probe relative to the stack pointer.
11256 Note that SIZE is negative.
11258 The return value is true if TEMP_REG has been clobbered. */
11260 allocate_stack_space (rtx size
, HOST_WIDE_INT last_probe_offset
,
11263 bool temp_reg_clobbered_p
= false;
11264 HOST_WIDE_INT probe_interval
11265 = 1 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_PROBE_INTERVAL
);
11266 HOST_WIDE_INT guard_size
11267 = 1 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE
);
11269 if (flag_stack_clash_protection
)
11271 if (last_probe_offset
+ -INTVAL (size
) < guard_size
)
11272 dump_stack_clash_frame_info (NO_PROBE_SMALL_FRAME
, true);
11275 rtx offset
= GEN_INT (probe_interval
- UNITS_PER_LONG
);
11276 HOST_WIDE_INT rounded_size
= -INTVAL (size
) & -probe_interval
;
11277 HOST_WIDE_INT num_probes
= rounded_size
/ probe_interval
;
11278 HOST_WIDE_INT residual
= -INTVAL (size
) - rounded_size
;
11280 if (num_probes
< MIN_UNROLL_PROBES
)
11282 /* Emit unrolled probe statements. */
11284 for (unsigned int i
= 0; i
< num_probes
; i
++)
11286 s390_prologue_plus_offset (stack_pointer_rtx
,
11288 GEN_INT (-probe_interval
), true);
11289 s390_emit_stack_probe (gen_rtx_PLUS (Pmode
,
11293 dump_stack_clash_frame_info (PROBE_INLINE
, residual
!= 0);
11297 /* Emit a loop probing the pages. */
11299 rtx_code_label
*loop_start_label
= gen_label_rtx ();
11301 /* From now on temp_reg will be the CFA register. */
11302 s390_prologue_plus_offset (temp_reg
, stack_pointer_rtx
,
11303 GEN_INT (-rounded_size
), true);
11304 emit_label (loop_start_label
);
11306 s390_prologue_plus_offset (stack_pointer_rtx
,
11308 GEN_INT (-probe_interval
), false);
11309 s390_emit_stack_probe (gen_rtx_PLUS (Pmode
,
11312 emit_cmp_and_jump_insns (stack_pointer_rtx
, temp_reg
,
11314 Pmode
, 1, loop_start_label
);
11316 /* Without this make_edges ICEes. */
11317 JUMP_LABEL (get_last_insn ()) = loop_start_label
;
11318 LABEL_NUSES (loop_start_label
) = 1;
11320 /* That's going to be a NOP since stack pointer and
11321 temp_reg are supposed to be the same here. We just
11322 emit it to set the CFA reg back to r15. */
11323 s390_prologue_plus_offset (stack_pointer_rtx
, temp_reg
,
11325 temp_reg_clobbered_p
= true;
11326 dump_stack_clash_frame_info (PROBE_LOOP
, residual
!= 0);
11329 /* Handle any residual allocation request. */
11330 s390_prologue_plus_offset (stack_pointer_rtx
,
11332 GEN_INT (-residual
), true);
11333 last_probe_offset
+= residual
;
11334 if (last_probe_offset
>= probe_interval
)
11335 s390_emit_stack_probe (gen_rtx_PLUS (Pmode
,
11338 - UNITS_PER_LONG
)));
11340 return temp_reg_clobbered_p
;
11344 /* Subtract frame size from stack pointer. */
11345 s390_prologue_plus_offset (stack_pointer_rtx
,
11349 return temp_reg_clobbered_p
;
11352 /* Expand the prologue into a bunch of separate insns. */
11355 s390_emit_prologue (void)
11363 /* Choose best register to use for temp use within prologue.
11364 TPF with profiling must avoid the register 14 - the tracing function
11365 needs the original contents of r14 to be preserved. */
11367 if (!has_hard_reg_initial_val (Pmode
, RETURN_REGNUM
)
11369 && !TARGET_TPF_PROFILING
)
11370 temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
11371 else if (flag_split_stack
&& cfun
->stdarg
)
11372 temp_reg
= gen_rtx_REG (Pmode
, 12);
11374 temp_reg
= gen_rtx_REG (Pmode
, 1);
11376 /* When probing for stack-clash mitigation, we have to track the distance
11377 between the stack pointer and closest known reference.
11379 Most of the time we have to make a worst case assumption. The
11380 only exception is when TARGET_BACKCHAIN is active, in which case
11381 we know *sp (offset 0) was written. */
11382 HOST_WIDE_INT probe_interval
11383 = 1 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_PROBE_INTERVAL
);
11384 HOST_WIDE_INT last_probe_offset
11385 = (TARGET_BACKCHAIN
11386 ? (TARGET_PACKED_STACK
? STACK_POINTER_OFFSET
- UNITS_PER_LONG
: 0)
11387 : probe_interval
- (STACK_BOUNDARY
/ UNITS_PER_WORD
));
11389 s390_save_gprs_to_fprs ();
11391 /* Save call saved gprs. */
11392 if (cfun_frame_layout
.first_save_gpr
!= -1)
11394 insn
= save_gprs (stack_pointer_rtx
,
11395 cfun_frame_layout
.gprs_offset
+
11396 UNITS_PER_LONG
* (cfun_frame_layout
.first_save_gpr
11397 - cfun_frame_layout
.first_save_gpr_slot
),
11398 cfun_frame_layout
.first_save_gpr
,
11399 cfun_frame_layout
.last_save_gpr
);
11401 /* This is not 100% correct. If we have more than one register saved,
11402 then LAST_PROBE_OFFSET can move even closer to sp. */
11404 = (cfun_frame_layout
.gprs_offset
+
11405 UNITS_PER_LONG
* (cfun_frame_layout
.first_save_gpr
11406 - cfun_frame_layout
.first_save_gpr_slot
));
11411 /* Dummy insn to mark literal pool slot. */
11413 if (cfun
->machine
->base_reg
)
11414 emit_insn (gen_main_pool (cfun
->machine
->base_reg
));
11416 offset
= cfun_frame_layout
.f0_offset
;
11418 /* Save f0 and f2. */
11419 for (i
= FPR0_REGNUM
; i
<= FPR0_REGNUM
+ 1; i
++)
11421 if (cfun_fpr_save_p (i
))
11423 save_fpr (stack_pointer_rtx
, offset
, i
);
11424 if (offset
< last_probe_offset
)
11425 last_probe_offset
= offset
;
11428 else if (!TARGET_PACKED_STACK
|| cfun
->stdarg
)
11432 /* Save f4 and f6. */
11433 offset
= cfun_frame_layout
.f4_offset
;
11434 for (i
= FPR4_REGNUM
; i
<= FPR4_REGNUM
+ 1; i
++)
11436 if (cfun_fpr_save_p (i
))
11438 insn
= save_fpr (stack_pointer_rtx
, offset
, i
);
11439 if (offset
< last_probe_offset
)
11440 last_probe_offset
= offset
;
11443 /* If f4 and f6 are call clobbered they are saved due to
11444 stdargs and therefore are not frame related. */
11445 if (!call_really_used_regs
[i
])
11446 RTX_FRAME_RELATED_P (insn
) = 1;
11448 else if (!TARGET_PACKED_STACK
|| call_really_used_regs
[i
])
11452 if (TARGET_PACKED_STACK
11453 && cfun_save_high_fprs_p
11454 && cfun_frame_layout
.f8_offset
+ cfun_frame_layout
.high_fprs
* 8 > 0)
11456 offset
= (cfun_frame_layout
.f8_offset
11457 + (cfun_frame_layout
.high_fprs
- 1) * 8);
11459 for (i
= FPR15_REGNUM
; i
>= FPR8_REGNUM
&& offset
>= 0; i
--)
11460 if (cfun_fpr_save_p (i
))
11462 insn
= save_fpr (stack_pointer_rtx
, offset
, i
);
11463 if (offset
< last_probe_offset
)
11464 last_probe_offset
= offset
;
11466 RTX_FRAME_RELATED_P (insn
) = 1;
11469 if (offset
>= cfun_frame_layout
.f8_offset
)
11473 if (!TARGET_PACKED_STACK
)
11474 next_fpr
= cfun_save_high_fprs_p
? FPR15_REGNUM
: 0;
11476 if (flag_stack_usage_info
)
11477 current_function_static_stack_size
= cfun_frame_layout
.frame_size
;
11479 /* Decrement stack pointer. */
11481 if (cfun_frame_layout
.frame_size
> 0)
11483 rtx frame_off
= GEN_INT (-cfun_frame_layout
.frame_size
);
11484 rtx_insn
*stack_pointer_backup_loc
;
11485 bool temp_reg_clobbered_p
;
11487 if (s390_stack_size
)
11489 HOST_WIDE_INT stack_guard
;
11491 if (s390_stack_guard
)
11492 stack_guard
= s390_stack_guard
;
11495 /* If no value for stack guard is provided the smallest power of 2
11496 larger than the current frame size is chosen. */
11498 while (stack_guard
< cfun_frame_layout
.frame_size
)
11502 if (cfun_frame_layout
.frame_size
>= s390_stack_size
)
11504 warning (0, "frame size of function %qs is %wd"
11505 " bytes exceeding user provided stack limit of "
11507 "An unconditional trap is added.",
11508 current_function_name(), cfun_frame_layout
.frame_size
,
11510 emit_insn (gen_trap ());
11515 /* stack_guard has to be smaller than s390_stack_size.
11516 Otherwise we would emit an AND with zero which would
11517 not match the test under mask pattern. */
11518 if (stack_guard
>= s390_stack_size
)
11520 warning (0, "frame size of function %qs is %wd"
11521 " bytes which is more than half the stack size. "
11522 "The dynamic check would not be reliable. "
11523 "No check emitted for this function.",
11524 current_function_name(),
11525 cfun_frame_layout
.frame_size
);
11529 HOST_WIDE_INT stack_check_mask
= ((s390_stack_size
- 1)
11530 & ~(stack_guard
- 1));
11532 rtx t
= gen_rtx_AND (Pmode
, stack_pointer_rtx
,
11533 GEN_INT (stack_check_mask
));
11535 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode
,
11537 t
, const0_rtx
, const0_rtx
));
11539 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode
,
11541 t
, const0_rtx
, const0_rtx
));
11546 if (s390_warn_framesize
> 0
11547 && cfun_frame_layout
.frame_size
>= s390_warn_framesize
)
11548 warning (0, "frame size of %qs is %wd bytes",
11549 current_function_name (), cfun_frame_layout
.frame_size
);
11551 if (s390_warn_dynamicstack_p
&& cfun
->calls_alloca
)
11552 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
11554 /* Save the location where we could backup the incoming stack
11556 stack_pointer_backup_loc
= get_last_insn ();
11558 temp_reg_clobbered_p
= allocate_stack_space (frame_off
, last_probe_offset
,
11561 if (TARGET_BACKCHAIN
|| next_fpr
)
11563 if (temp_reg_clobbered_p
)
11565 /* allocate_stack_space had to make use of temp_reg and
11566 we need it to hold a backup of the incoming stack
11567 pointer. Calculate back that value from the current
11569 s390_prologue_plus_offset (temp_reg
, stack_pointer_rtx
,
11570 GEN_INT (cfun_frame_layout
.frame_size
),
11575 /* allocate_stack_space didn't actually required
11576 temp_reg. Insert the stack pointer backup insn
11577 before the stack pointer decrement code - knowing now
11578 that the value will survive. */
11579 emit_insn_after (gen_move_insn (temp_reg
, stack_pointer_rtx
),
11580 stack_pointer_backup_loc
);
11584 /* Set backchain. */
11586 if (TARGET_BACKCHAIN
)
11588 if (cfun_frame_layout
.backchain_offset
)
11589 addr
= gen_rtx_MEM (Pmode
,
11590 plus_constant (Pmode
, stack_pointer_rtx
,
11591 cfun_frame_layout
.backchain_offset
));
11593 addr
= gen_rtx_MEM (Pmode
, stack_pointer_rtx
);
11594 set_mem_alias_set (addr
, get_frame_alias_set ());
11595 insn
= emit_insn (gen_move_insn (addr
, temp_reg
));
11598 /* If we support non-call exceptions (e.g. for Java),
11599 we need to make sure the backchain pointer is set up
11600 before any possibly trapping memory access. */
11601 if (TARGET_BACKCHAIN
&& cfun
->can_throw_non_call_exceptions
)
11603 addr
= gen_rtx_MEM (BLKmode
, gen_rtx_SCRATCH (VOIDmode
));
11604 emit_clobber (addr
);
11607 else if (flag_stack_clash_protection
)
11608 dump_stack_clash_frame_info (NO_PROBE_NO_FRAME
, false);
11610 /* Save fprs 8 - 15 (64 bit ABI). */
11612 if (cfun_save_high_fprs_p
&& next_fpr
)
11614 /* If the stack might be accessed through a different register
11615 we have to make sure that the stack pointer decrement is not
11616 moved below the use of the stack slots. */
11617 s390_emit_stack_tie ();
11619 insn
= emit_insn (gen_add2_insn (temp_reg
,
11620 GEN_INT (cfun_frame_layout
.f8_offset
)));
11624 for (i
= FPR8_REGNUM
; i
<= next_fpr
; i
++)
11625 if (cfun_fpr_save_p (i
))
11627 rtx addr
= plus_constant (Pmode
, stack_pointer_rtx
,
11628 cfun_frame_layout
.frame_size
11629 + cfun_frame_layout
.f8_offset
11632 insn
= save_fpr (temp_reg
, offset
, i
);
11634 RTX_FRAME_RELATED_P (insn
) = 1;
11635 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
11636 gen_rtx_SET (gen_rtx_MEM (DFmode
, addr
),
11637 gen_rtx_REG (DFmode
, i
)));
11641 /* Set frame pointer, if needed. */
11643 if (frame_pointer_needed
)
11645 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11646 RTX_FRAME_RELATED_P (insn
) = 1;
11649 /* Set up got pointer, if needed. */
11651 if (flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
11653 rtx_insn
*insns
= s390_load_got ();
11655 for (rtx_insn
*insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
11656 annotate_constant_pool_refs (&PATTERN (insn
));
11661 if (TARGET_TPF_PROFILING
)
11663 /* Generate a BAS instruction to serve as a function
11664 entry intercept to facilitate the use of tracing
11665 algorithms located at the branch target. */
11666 emit_insn (gen_prologue_tpf ());
11668 /* Emit a blockage here so that all code
11669 lies between the profiling mechanisms. */
11670 emit_insn (gen_blockage ());
11674 /* Expand the epilogue into a bunch of separate insns. */
11677 s390_emit_epilogue (bool sibcall
)
11679 rtx frame_pointer
, return_reg
, cfa_restores
= NULL_RTX
;
11680 int area_bottom
, area_top
, offset
= 0;
11685 if (TARGET_TPF_PROFILING
)
11688 /* Generate a BAS instruction to serve as a function
11689 entry intercept to facilitate the use of tracing
11690 algorithms located at the branch target. */
11692 /* Emit a blockage here so that all code
11693 lies between the profiling mechanisms. */
11694 emit_insn (gen_blockage ());
11696 emit_insn (gen_epilogue_tpf ());
11699 /* Check whether to use frame or stack pointer for restore. */
11701 frame_pointer
= (frame_pointer_needed
11702 ? hard_frame_pointer_rtx
: stack_pointer_rtx
);
11704 s390_frame_area (&area_bottom
, &area_top
);
11706 /* Check whether we can access the register save area.
11707 If not, increment the frame pointer as required. */
11709 if (area_top
<= area_bottom
)
11711 /* Nothing to restore. */
11713 else if (DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_bottom
)
11714 && DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_top
- 1))
11716 /* Area is in range. */
11717 offset
= cfun_frame_layout
.frame_size
;
11721 rtx insn
, frame_off
, cfa
;
11723 offset
= area_bottom
< 0 ? -area_bottom
: 0;
11724 frame_off
= GEN_INT (cfun_frame_layout
.frame_size
- offset
);
11726 cfa
= gen_rtx_SET (frame_pointer
,
11727 gen_rtx_PLUS (Pmode
, frame_pointer
, frame_off
));
11728 if (DISP_IN_RANGE (INTVAL (frame_off
)))
11730 insn
= gen_rtx_SET (frame_pointer
,
11731 gen_rtx_PLUS (Pmode
, frame_pointer
, frame_off
));
11732 insn
= emit_insn (insn
);
11736 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
11737 frame_off
= force_const_mem (Pmode
, frame_off
);
11739 insn
= emit_insn (gen_add2_insn (frame_pointer
, frame_off
));
11740 annotate_constant_pool_refs (&PATTERN (insn
));
11742 add_reg_note (insn
, REG_CFA_ADJUST_CFA
, cfa
);
11743 RTX_FRAME_RELATED_P (insn
) = 1;
11746 /* Restore call saved fprs. */
11750 if (cfun_save_high_fprs_p
)
11752 next_offset
= cfun_frame_layout
.f8_offset
;
11753 for (i
= FPR8_REGNUM
; i
<= FPR15_REGNUM
; i
++)
11755 if (cfun_fpr_save_p (i
))
11757 restore_fpr (frame_pointer
,
11758 offset
+ next_offset
, i
);
11760 = alloc_reg_note (REG_CFA_RESTORE
,
11761 gen_rtx_REG (DFmode
, i
), cfa_restores
);
11770 next_offset
= cfun_frame_layout
.f4_offset
;
11772 for (i
= FPR4_REGNUM
; i
<= FPR4_REGNUM
+ 1; i
++)
11774 if (cfun_fpr_save_p (i
))
11776 restore_fpr (frame_pointer
,
11777 offset
+ next_offset
, i
);
11779 = alloc_reg_note (REG_CFA_RESTORE
,
11780 gen_rtx_REG (DFmode
, i
), cfa_restores
);
11783 else if (!TARGET_PACKED_STACK
)
11789 /* Return register. */
11791 return_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
11793 /* Restore call saved gprs. */
11795 if (cfun_frame_layout
.first_restore_gpr
!= -1)
11800 /* Check for global register and save them
11801 to stack location from where they get restored. */
11803 for (i
= cfun_frame_layout
.first_restore_gpr
;
11804 i
<= cfun_frame_layout
.last_restore_gpr
;
11807 if (global_not_special_regno_p (i
))
11809 addr
= plus_constant (Pmode
, frame_pointer
,
11810 offset
+ cfun_frame_layout
.gprs_offset
11811 + (i
- cfun_frame_layout
.first_save_gpr_slot
)
11813 addr
= gen_rtx_MEM (Pmode
, addr
);
11814 set_mem_alias_set (addr
, get_frame_alias_set ());
11815 emit_move_insn (addr
, gen_rtx_REG (Pmode
, i
));
11819 = alloc_reg_note (REG_CFA_RESTORE
,
11820 gen_rtx_REG (Pmode
, i
), cfa_restores
);
11823 /* Fetch return address from stack before load multiple,
11824 this will do good for scheduling.
11826 Only do this if we already decided that r14 needs to be
11827 saved to a stack slot. (And not just because r14 happens to
11828 be in between two GPRs which need saving.) Otherwise it
11829 would be difficult to take that decision back in
11830 s390_optimize_prologue.
11832 This optimization is only helpful on in-order machines. */
11834 && cfun_gpr_save_slot (RETURN_REGNUM
) == SAVE_SLOT_STACK
11835 && s390_tune
<= PROCESSOR_2097_Z10
)
11837 int return_regnum
= find_unused_clobbered_reg();
11838 if (!return_regnum
)
11840 return_reg
= gen_rtx_REG (Pmode
, return_regnum
);
11842 addr
= plus_constant (Pmode
, frame_pointer
,
11843 offset
+ cfun_frame_layout
.gprs_offset
11845 - cfun_frame_layout
.first_save_gpr_slot
)
11847 addr
= gen_rtx_MEM (Pmode
, addr
);
11848 set_mem_alias_set (addr
, get_frame_alias_set ());
11849 emit_move_insn (return_reg
, addr
);
11851 /* Once we did that optimization we have to make sure
11852 s390_optimize_prologue does not try to remove the store
11853 of r14 since we will not be able to find the load issued
11855 cfun_frame_layout
.save_return_addr_p
= true;
11858 insn
= restore_gprs (frame_pointer
,
11859 offset
+ cfun_frame_layout
.gprs_offset
11860 + (cfun_frame_layout
.first_restore_gpr
11861 - cfun_frame_layout
.first_save_gpr_slot
)
11863 cfun_frame_layout
.first_restore_gpr
,
11864 cfun_frame_layout
.last_restore_gpr
);
11865 insn
= emit_insn (insn
);
11866 REG_NOTES (insn
) = cfa_restores
;
11867 add_reg_note (insn
, REG_CFA_DEF_CFA
,
11868 plus_constant (Pmode
, stack_pointer_rtx
,
11869 STACK_POINTER_OFFSET
));
11870 RTX_FRAME_RELATED_P (insn
) = 1;
11873 s390_restore_gprs_from_fprs ();
11878 /* Return to caller. */
11880 p
= rtvec_alloc (2);
11882 RTVEC_ELT (p
, 0) = ret_rtx
;
11883 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
, return_reg
);
11884 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
11888 /* Implement TARGET_SET_UP_BY_PROLOGUE. */
11891 s300_set_up_by_prologue (hard_reg_set_container
*regs
)
11893 if (cfun
->machine
->base_reg
11894 && !call_really_used_regs
[REGNO (cfun
->machine
->base_reg
)])
11895 SET_HARD_REG_BIT (regs
->set
, REGNO (cfun
->machine
->base_reg
));
11898 /* -fsplit-stack support. */
11900 /* A SYMBOL_REF for __morestack. */
11901 static GTY(()) rtx morestack_ref
;
11903 /* When using -fsplit-stack, the allocation routines set a field in
11904 the TCB to the bottom of the stack plus this much space, measured
11907 #define SPLIT_STACK_AVAILABLE 1024
11909 /* Emit -fsplit-stack prologue, which goes before the regular function
11913 s390_expand_split_stack_prologue (void)
11915 rtx r1
, guard
, cc
= NULL
;
11917 /* Offset from thread pointer to __private_ss. */
11918 int psso
= TARGET_64BIT
? 0x38 : 0x20;
11919 /* Pointer size in bytes. */
11920 /* Frame size and argument size - the two parameters to __morestack. */
11921 HOST_WIDE_INT frame_size
= cfun_frame_layout
.frame_size
;
11922 /* Align argument size to 8 bytes - simplifies __morestack code. */
11923 HOST_WIDE_INT args_size
= crtl
->args
.size
>= 0
11924 ? ((crtl
->args
.size
+ 7) & ~7)
11926 /* Label to be called by __morestack. */
11927 rtx_code_label
*call_done
= NULL
;
11928 rtx_code_label
*parm_base
= NULL
;
11931 gcc_assert (flag_split_stack
&& reload_completed
);
11932 if (!TARGET_CPU_ZARCH
)
11934 sorry ("CPUs older than z900 are not supported for -fsplit-stack");
11938 r1
= gen_rtx_REG (Pmode
, 1);
11940 /* If no stack frame will be allocated, don't do anything. */
11943 if (cfun
->machine
->split_stack_varargs_pointer
!= NULL_RTX
)
11945 /* If va_start is used, just use r15. */
11946 emit_move_insn (r1
,
11947 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
11948 GEN_INT (STACK_POINTER_OFFSET
)));
11954 if (morestack_ref
== NULL_RTX
)
11956 morestack_ref
= gen_rtx_SYMBOL_REF (Pmode
, "__morestack");
11957 SYMBOL_REF_FLAGS (morestack_ref
) |= (SYMBOL_FLAG_LOCAL
11958 | SYMBOL_FLAG_FUNCTION
);
11961 if (CONST_OK_FOR_K (frame_size
) || CONST_OK_FOR_Op (frame_size
))
11963 /* If frame_size will fit in an add instruction, do a stack space
11964 check, and only call __morestack if there's not enough space. */
11966 /* Get thread pointer. r1 is the only register we can always destroy - r0
11967 could contain a static chain (and cannot be used to address memory
11968 anyway), r2-r6 can contain parameters, and r6-r15 are callee-saved. */
11969 emit_move_insn (r1
, gen_rtx_REG (Pmode
, TP_REGNUM
));
11970 /* Aim at __private_ss. */
11971 guard
= gen_rtx_MEM (Pmode
, plus_constant (Pmode
, r1
, psso
));
11973 /* If less that 1kiB used, skip addition and compare directly with
11975 if (frame_size
> SPLIT_STACK_AVAILABLE
)
11977 emit_move_insn (r1
, guard
);
11979 emit_insn (gen_adddi3 (r1
, r1
, GEN_INT (frame_size
)));
11981 emit_insn (gen_addsi3 (r1
, r1
, GEN_INT (frame_size
)));
11985 /* Compare the (maybe adjusted) guard with the stack pointer. */
11986 cc
= s390_emit_compare (LT
, stack_pointer_rtx
, guard
);
11989 call_done
= gen_label_rtx ();
11990 parm_base
= gen_label_rtx ();
11992 /* Emit the parameter block. */
11993 tmp
= gen_split_stack_data (parm_base
, call_done
,
11994 GEN_INT (frame_size
),
11995 GEN_INT (args_size
));
11996 insn
= emit_insn (tmp
);
11997 add_reg_note (insn
, REG_LABEL_OPERAND
, call_done
);
11998 LABEL_NUSES (call_done
)++;
11999 add_reg_note (insn
, REG_LABEL_OPERAND
, parm_base
);
12000 LABEL_NUSES (parm_base
)++;
12002 /* %r1 = litbase. */
12003 insn
= emit_move_insn (r1
, gen_rtx_LABEL_REF (VOIDmode
, parm_base
));
12004 add_reg_note (insn
, REG_LABEL_OPERAND
, parm_base
);
12005 LABEL_NUSES (parm_base
)++;
12007 /* Now, we need to call __morestack. It has very special calling
12008 conventions: it preserves param/return/static chain registers for
12009 calling main function body, and looks for its own parameters at %r1. */
12013 tmp
= gen_split_stack_cond_call (morestack_ref
, cc
, call_done
);
12015 insn
= emit_jump_insn (tmp
);
12016 JUMP_LABEL (insn
) = call_done
;
12017 LABEL_NUSES (call_done
)++;
12019 /* Mark the jump as very unlikely to be taken. */
12020 add_reg_br_prob_note (insn
,
12021 profile_probability::very_unlikely ());
12023 if (cfun
->machine
->split_stack_varargs_pointer
!= NULL_RTX
)
12025 /* If va_start is used, and __morestack was not called, just use
12027 emit_move_insn (r1
,
12028 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
12029 GEN_INT (STACK_POINTER_OFFSET
)));
12034 tmp
= gen_split_stack_call (morestack_ref
, call_done
);
12035 insn
= emit_jump_insn (tmp
);
12036 JUMP_LABEL (insn
) = call_done
;
12037 LABEL_NUSES (call_done
)++;
12041 /* __morestack will call us here. */
12043 emit_label (call_done
);
12046 /* We may have to tell the dataflow pass that the split stack prologue
12047 is initializing a register. */
12050 s390_live_on_entry (bitmap regs
)
12052 if (cfun
->machine
->split_stack_varargs_pointer
!= NULL_RTX
)
12054 gcc_assert (flag_split_stack
);
12055 bitmap_set_bit (regs
, 1);
12059 /* Return true if the function can use simple_return to return outside
12060 of a shrink-wrapped region. At present shrink-wrapping is supported
12064 s390_can_use_simple_return_insn (void)
12069 /* Return true if the epilogue is guaranteed to contain only a return
12070 instruction and if a direct return can therefore be used instead.
12071 One of the main advantages of using direct return instructions
12072 is that we can then use conditional returns. */
12075 s390_can_use_return_insn (void)
12079 if (!reload_completed
)
12085 if (TARGET_TPF_PROFILING
)
12088 for (i
= 0; i
< 16; i
++)
12089 if (cfun_gpr_save_slot (i
) != SAVE_SLOT_NONE
)
12092 /* For 31 bit this is not covered by the frame_size check below
12093 since f4, f6 are saved in the register save area without needing
12094 additional stack space. */
12096 && (cfun_fpr_save_p (FPR4_REGNUM
) || cfun_fpr_save_p (FPR6_REGNUM
)))
12099 if (cfun
->machine
->base_reg
12100 && !call_really_used_regs
[REGNO (cfun
->machine
->base_reg
)])
12103 return cfun_frame_layout
.frame_size
== 0;
12106 /* The VX ABI differs for vararg functions. Therefore we need the
12107 prototype of the callee to be available when passing vector type
12109 static const char *
12110 s390_invalid_arg_for_unprototyped_fn (const_tree typelist
, const_tree funcdecl
, const_tree val
)
12112 return ((TARGET_VX_ABI
12114 && VECTOR_TYPE_P (TREE_TYPE (val
))
12115 && (funcdecl
== NULL_TREE
12116 || (TREE_CODE (funcdecl
) == FUNCTION_DECL
12117 && DECL_BUILT_IN_CLASS (funcdecl
) != BUILT_IN_MD
)))
12118 ? N_("vector argument passed to unprototyped function")
12123 /* Return the size in bytes of a function argument of
12124 type TYPE and/or mode MODE. At least one of TYPE or
12125 MODE must be specified. */
12128 s390_function_arg_size (machine_mode mode
, const_tree type
)
12131 return int_size_in_bytes (type
);
12133 /* No type info available for some library calls ... */
12134 if (mode
!= BLKmode
)
12135 return GET_MODE_SIZE (mode
);
12137 /* If we have neither type nor mode, abort */
12138 gcc_unreachable ();
12141 /* Return true if a function argument of type TYPE and mode MODE
12142 is to be passed in a vector register, if available. */
12145 s390_function_arg_vector (machine_mode mode
, const_tree type
)
12147 if (!TARGET_VX_ABI
)
12150 if (s390_function_arg_size (mode
, type
) > 16)
12153 /* No type info available for some library calls ... */
12155 return VECTOR_MODE_P (mode
);
12157 /* The ABI says that record types with a single member are treated
12158 just like that member would be. */
12159 while (TREE_CODE (type
) == RECORD_TYPE
)
12161 tree field
, single
= NULL_TREE
;
12163 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
12165 if (TREE_CODE (field
) != FIELD_DECL
)
12168 if (single
== NULL_TREE
)
12169 single
= TREE_TYPE (field
);
12174 if (single
== NULL_TREE
)
12178 /* If the field declaration adds extra byte due to
12179 e.g. padding this is not accepted as vector type. */
12180 if (int_size_in_bytes (single
) <= 0
12181 || int_size_in_bytes (single
) != int_size_in_bytes (type
))
12187 return VECTOR_TYPE_P (type
);
12190 /* Return true if a function argument of type TYPE and mode MODE
12191 is to be passed in a floating-point register, if available. */
12194 s390_function_arg_float (machine_mode mode
, const_tree type
)
12196 if (s390_function_arg_size (mode
, type
) > 8)
12199 /* Soft-float changes the ABI: no floating-point registers are used. */
12200 if (TARGET_SOFT_FLOAT
)
12203 /* No type info available for some library calls ... */
12205 return mode
== SFmode
|| mode
== DFmode
|| mode
== SDmode
|| mode
== DDmode
;
12207 /* The ABI says that record types with a single member are treated
12208 just like that member would be. */
12209 while (TREE_CODE (type
) == RECORD_TYPE
)
12211 tree field
, single
= NULL_TREE
;
12213 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
12215 if (TREE_CODE (field
) != FIELD_DECL
)
12218 if (single
== NULL_TREE
)
12219 single
= TREE_TYPE (field
);
12224 if (single
== NULL_TREE
)
12230 return TREE_CODE (type
) == REAL_TYPE
;
12233 /* Return true if a function argument of type TYPE and mode MODE
12234 is to be passed in an integer register, or a pair of integer
12235 registers, if available. */
12238 s390_function_arg_integer (machine_mode mode
, const_tree type
)
12240 int size
= s390_function_arg_size (mode
, type
);
12244 /* No type info available for some library calls ... */
12246 return GET_MODE_CLASS (mode
) == MODE_INT
12247 || (TARGET_SOFT_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
));
12249 /* We accept small integral (and similar) types. */
12250 if (INTEGRAL_TYPE_P (type
)
12251 || POINTER_TYPE_P (type
)
12252 || TREE_CODE (type
) == NULLPTR_TYPE
12253 || TREE_CODE (type
) == OFFSET_TYPE
12254 || (TARGET_SOFT_FLOAT
&& TREE_CODE (type
) == REAL_TYPE
))
12257 /* We also accept structs of size 1, 2, 4, 8 that are not
12258 passed in floating-point registers. */
12259 if (AGGREGATE_TYPE_P (type
)
12260 && exact_log2 (size
) >= 0
12261 && !s390_function_arg_float (mode
, type
))
12267 /* Return 1 if a function argument of type TYPE and mode MODE
12268 is to be passed by reference. The ABI specifies that only
12269 structures of size 1, 2, 4, or 8 bytes are passed by value,
12270 all other structures (and complex numbers) are passed by
12274 s390_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED
,
12275 machine_mode mode
, const_tree type
,
12276 bool named ATTRIBUTE_UNUSED
)
12278 int size
= s390_function_arg_size (mode
, type
);
12280 if (s390_function_arg_vector (mode
, type
))
12288 if (AGGREGATE_TYPE_P (type
) && exact_log2 (size
) < 0)
12291 if (TREE_CODE (type
) == COMPLEX_TYPE
12292 || TREE_CODE (type
) == VECTOR_TYPE
)
12299 /* Update the data in CUM to advance over an argument of mode MODE and
12300 data type TYPE. (TYPE is null for libcalls where that information
12301 may not be available.). The boolean NAMED specifies whether the
12302 argument is a named argument (as opposed to an unnamed argument
12303 matching an ellipsis). */
12306 s390_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
12307 const_tree type
, bool named
)
12309 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
12311 if (s390_function_arg_vector (mode
, type
))
12313 /* We are called for unnamed vector stdarg arguments which are
12314 passed on the stack. In this case this hook does not have to
12315 do anything since stack arguments are tracked by common
12321 else if (s390_function_arg_float (mode
, type
))
12325 else if (s390_function_arg_integer (mode
, type
))
12327 int size
= s390_function_arg_size (mode
, type
);
12328 cum
->gprs
+= ((size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
);
12331 gcc_unreachable ();
12334 /* Define where to put the arguments to a function.
12335 Value is zero to push the argument on the stack,
12336 or a hard register in which to store the argument.
12338 MODE is the argument's machine mode.
12339 TYPE is the data type of the argument (as a tree).
12340 This is null for libcalls where that information may
12342 CUM is a variable of type CUMULATIVE_ARGS which gives info about
12343 the preceding args and about the function being called.
12344 NAMED is nonzero if this argument is a named parameter
12345 (otherwise it is an extra parameter matching an ellipsis).
12347 On S/390, we use general purpose registers 2 through 6 to
12348 pass integer, pointer, and certain structure arguments, and
12349 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
12350 to pass floating point arguments. All remaining arguments
12351 are pushed to the stack. */
12354 s390_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
12355 const_tree type
, bool named
)
12357 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
12360 s390_check_type_for_vector_abi (type
, true, false);
12362 if (s390_function_arg_vector (mode
, type
))
12364 /* Vector arguments being part of the ellipsis are passed on the
12366 if (!named
|| (cum
->vrs
+ 1 > VEC_ARG_NUM_REG
))
12369 return gen_rtx_REG (mode
, cum
->vrs
+ FIRST_VEC_ARG_REGNO
);
12371 else if (s390_function_arg_float (mode
, type
))
12373 if (cum
->fprs
+ 1 > FP_ARG_NUM_REG
)
12376 return gen_rtx_REG (mode
, cum
->fprs
+ 16);
12378 else if (s390_function_arg_integer (mode
, type
))
12380 int size
= s390_function_arg_size (mode
, type
);
12381 int n_gprs
= (size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
;
12383 if (cum
->gprs
+ n_gprs
> GP_ARG_NUM_REG
)
12385 else if (n_gprs
== 1 || UNITS_PER_WORD
== UNITS_PER_LONG
)
12386 return gen_rtx_REG (mode
, cum
->gprs
+ 2);
12387 else if (n_gprs
== 2)
12389 rtvec p
= rtvec_alloc (2);
12392 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, cum
->gprs
+ 2),
12395 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, cum
->gprs
+ 3),
12398 return gen_rtx_PARALLEL (mode
, p
);
12402 /* After the real arguments, expand_call calls us once again
12403 with a void_type_node type. Whatever we return here is
12404 passed as operand 2 to the call expanders.
12406 We don't need this feature ... */
12407 else if (type
== void_type_node
)
12410 gcc_unreachable ();
12413 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Vector arguments are
12414 left-justified when placed on the stack during parameter passing. */
12416 static pad_direction
12417 s390_function_arg_padding (machine_mode mode
, const_tree type
)
12419 if (s390_function_arg_vector (mode
, type
))
12422 return default_function_arg_padding (mode
, type
);
12425 /* Return true if return values of type TYPE should be returned
12426 in a memory buffer whose address is passed by the caller as
12427 hidden first argument. */
12430 s390_return_in_memory (const_tree type
, const_tree fundecl ATTRIBUTE_UNUSED
)
12432 /* We accept small integral (and similar) types. */
12433 if (INTEGRAL_TYPE_P (type
)
12434 || POINTER_TYPE_P (type
)
12435 || TREE_CODE (type
) == OFFSET_TYPE
12436 || TREE_CODE (type
) == REAL_TYPE
)
12437 return int_size_in_bytes (type
) > 8;
12439 /* vector types which fit into a VR. */
12441 && VECTOR_TYPE_P (type
)
12442 && int_size_in_bytes (type
) <= 16)
12445 /* Aggregates and similar constructs are always returned
12447 if (AGGREGATE_TYPE_P (type
)
12448 || TREE_CODE (type
) == COMPLEX_TYPE
12449 || VECTOR_TYPE_P (type
))
12452 /* ??? We get called on all sorts of random stuff from
12453 aggregate_value_p. We can't abort, but it's not clear
12454 what's safe to return. Pretend it's a struct I guess. */
12458 /* Function arguments and return values are promoted to word size. */
12460 static machine_mode
12461 s390_promote_function_mode (const_tree type
, machine_mode mode
,
12463 const_tree fntype ATTRIBUTE_UNUSED
,
12464 int for_return ATTRIBUTE_UNUSED
)
12466 if (INTEGRAL_MODE_P (mode
)
12467 && GET_MODE_SIZE (mode
) < UNITS_PER_LONG
)
12469 if (type
!= NULL_TREE
&& POINTER_TYPE_P (type
))
12470 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
12477 /* Define where to return a (scalar) value of type RET_TYPE.
12478 If RET_TYPE is null, define where to return a (scalar)
12479 value of mode MODE from a libcall. */
12482 s390_function_and_libcall_value (machine_mode mode
,
12483 const_tree ret_type
,
12484 const_tree fntype_or_decl
,
12485 bool outgoing ATTRIBUTE_UNUSED
)
12487 /* For vector return types it is important to use the RET_TYPE
12488 argument whenever available since the middle-end might have
12489 changed the mode to a scalar mode. */
12490 bool vector_ret_type_p
= ((ret_type
&& VECTOR_TYPE_P (ret_type
))
12491 || (!ret_type
&& VECTOR_MODE_P (mode
)));
12493 /* For normal functions perform the promotion as
12494 promote_function_mode would do. */
12497 int unsignedp
= TYPE_UNSIGNED (ret_type
);
12498 mode
= promote_function_mode (ret_type
, mode
, &unsignedp
,
12499 fntype_or_decl
, 1);
12502 gcc_assert (GET_MODE_CLASS (mode
) == MODE_INT
12503 || SCALAR_FLOAT_MODE_P (mode
)
12504 || (TARGET_VX_ABI
&& vector_ret_type_p
));
12505 gcc_assert (GET_MODE_SIZE (mode
) <= (TARGET_VX_ABI
? 16 : 8));
12507 if (TARGET_VX_ABI
&& vector_ret_type_p
)
12508 return gen_rtx_REG (mode
, FIRST_VEC_ARG_REGNO
);
12509 else if (TARGET_HARD_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
))
12510 return gen_rtx_REG (mode
, 16);
12511 else if (GET_MODE_SIZE (mode
) <= UNITS_PER_LONG
12512 || UNITS_PER_LONG
== UNITS_PER_WORD
)
12513 return gen_rtx_REG (mode
, 2);
12514 else if (GET_MODE_SIZE (mode
) == 2 * UNITS_PER_LONG
)
12516 /* This case is triggered when returning a 64 bit value with
12517 -m31 -mzarch. Although the value would fit into a single
12518 register it has to be forced into a 32 bit register pair in
12519 order to match the ABI. */
12520 rtvec p
= rtvec_alloc (2);
12523 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, 2), const0_rtx
);
12525 = gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, 3), GEN_INT (4));
12527 return gen_rtx_PARALLEL (mode
, p
);
12530 gcc_unreachable ();
12533 /* Define where to return a scalar return value of type RET_TYPE. */
12536 s390_function_value (const_tree ret_type
, const_tree fn_decl_or_type
,
12539 return s390_function_and_libcall_value (TYPE_MODE (ret_type
), ret_type
,
12540 fn_decl_or_type
, outgoing
);
12543 /* Define where to return a scalar libcall return value of mode
12547 s390_libcall_value (machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
12549 return s390_function_and_libcall_value (mode
, NULL_TREE
,
12554 /* Create and return the va_list datatype.
12556 On S/390, va_list is an array type equivalent to
12558 typedef struct __va_list_tag
12562 void *__overflow_arg_area;
12563 void *__reg_save_area;
12566 where __gpr and __fpr hold the number of general purpose
12567 or floating point arguments used up to now, respectively,
12568 __overflow_arg_area points to the stack location of the
12569 next argument passed on the stack, and __reg_save_area
12570 always points to the start of the register area in the
12571 call frame of the current function. The function prologue
12572 saves all registers used for argument passing into this
12573 area if the function uses variable arguments. */
12576 s390_build_builtin_va_list (void)
12578 tree f_gpr
, f_fpr
, f_ovf
, f_sav
, record
, type_decl
;
12580 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
12583 build_decl (BUILTINS_LOCATION
,
12584 TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
12586 f_gpr
= build_decl (BUILTINS_LOCATION
,
12587 FIELD_DECL
, get_identifier ("__gpr"),
12588 long_integer_type_node
);
12589 f_fpr
= build_decl (BUILTINS_LOCATION
,
12590 FIELD_DECL
, get_identifier ("__fpr"),
12591 long_integer_type_node
);
12592 f_ovf
= build_decl (BUILTINS_LOCATION
,
12593 FIELD_DECL
, get_identifier ("__overflow_arg_area"),
12595 f_sav
= build_decl (BUILTINS_LOCATION
,
12596 FIELD_DECL
, get_identifier ("__reg_save_area"),
12599 va_list_gpr_counter_field
= f_gpr
;
12600 va_list_fpr_counter_field
= f_fpr
;
12602 DECL_FIELD_CONTEXT (f_gpr
) = record
;
12603 DECL_FIELD_CONTEXT (f_fpr
) = record
;
12604 DECL_FIELD_CONTEXT (f_ovf
) = record
;
12605 DECL_FIELD_CONTEXT (f_sav
) = record
;
12607 TYPE_STUB_DECL (record
) = type_decl
;
12608 TYPE_NAME (record
) = type_decl
;
12609 TYPE_FIELDS (record
) = f_gpr
;
12610 DECL_CHAIN (f_gpr
) = f_fpr
;
12611 DECL_CHAIN (f_fpr
) = f_ovf
;
12612 DECL_CHAIN (f_ovf
) = f_sav
;
12614 layout_type (record
);
12616 /* The correct type is an array type of one element. */
12617 return build_array_type (record
, build_index_type (size_zero_node
));
12620 /* Implement va_start by filling the va_list structure VALIST.
12621 STDARG_P is always true, and ignored.
12622 NEXTARG points to the first anonymous stack argument.
12624 The following global variables are used to initialize
12625 the va_list structure:
12628 holds number of gprs and fprs used for named arguments.
12629 crtl->args.arg_offset_rtx:
12630 holds the offset of the first anonymous stack argument
12631 (relative to the virtual arg pointer). */
12634 s390_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
12636 HOST_WIDE_INT n_gpr
, n_fpr
;
12638 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
12639 tree gpr
, fpr
, ovf
, sav
, t
;
12641 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
12642 f_fpr
= DECL_CHAIN (f_gpr
);
12643 f_ovf
= DECL_CHAIN (f_fpr
);
12644 f_sav
= DECL_CHAIN (f_ovf
);
12646 valist
= build_simple_mem_ref (valist
);
12647 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
12648 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
12649 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
12650 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
12652 /* Count number of gp and fp argument registers used. */
12654 n_gpr
= crtl
->args
.info
.gprs
;
12655 n_fpr
= crtl
->args
.info
.fprs
;
12657 if (cfun
->va_list_gpr_size
)
12659 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
12660 build_int_cst (NULL_TREE
, n_gpr
));
12661 TREE_SIDE_EFFECTS (t
) = 1;
12662 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
12665 if (cfun
->va_list_fpr_size
)
12667 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
12668 build_int_cst (NULL_TREE
, n_fpr
));
12669 TREE_SIDE_EFFECTS (t
) = 1;
12670 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
12673 if (flag_split_stack
12674 && (lookup_attribute ("no_split_stack", DECL_ATTRIBUTES (cfun
->decl
))
12676 && cfun
->machine
->split_stack_varargs_pointer
== NULL_RTX
)
12681 reg
= gen_reg_rtx (Pmode
);
12682 cfun
->machine
->split_stack_varargs_pointer
= reg
;
12685 emit_move_insn (reg
, gen_rtx_REG (Pmode
, 1));
12686 seq
= get_insns ();
12689 push_topmost_sequence ();
12690 emit_insn_after (seq
, entry_of_function ());
12691 pop_topmost_sequence ();
12694 /* Find the overflow area.
12695 FIXME: This currently is too pessimistic when the vector ABI is
12696 enabled. In that case we *always* set up the overflow area
12698 if (n_gpr
+ cfun
->va_list_gpr_size
> GP_ARG_NUM_REG
12699 || n_fpr
+ cfun
->va_list_fpr_size
> FP_ARG_NUM_REG
12702 if (cfun
->machine
->split_stack_varargs_pointer
== NULL_RTX
)
12703 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
12705 t
= make_tree (TREE_TYPE (ovf
), cfun
->machine
->split_stack_varargs_pointer
);
12707 off
= INTVAL (crtl
->args
.arg_offset_rtx
);
12708 off
= off
< 0 ? 0 : off
;
12709 if (TARGET_DEBUG_ARG
)
12710 fprintf (stderr
, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
12711 (int)n_gpr
, (int)n_fpr
, off
);
12713 t
= fold_build_pointer_plus_hwi (t
, off
);
12715 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
12716 TREE_SIDE_EFFECTS (t
) = 1;
12717 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
12720 /* Find the register save area. */
12721 if ((cfun
->va_list_gpr_size
&& n_gpr
< GP_ARG_NUM_REG
)
12722 || (cfun
->va_list_fpr_size
&& n_fpr
< FP_ARG_NUM_REG
))
12724 t
= make_tree (TREE_TYPE (sav
), return_address_pointer_rtx
);
12725 t
= fold_build_pointer_plus_hwi (t
, -RETURN_REGNUM
* UNITS_PER_LONG
);
12727 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
12728 TREE_SIDE_EFFECTS (t
) = 1;
12729 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
12733 /* Implement va_arg by updating the va_list structure
12734 VALIST as required to retrieve an argument of type
12735 TYPE, and returning that argument.
12737 Generates code equivalent to:
12739 if (integral value) {
12740 if (size <= 4 && args.gpr < 5 ||
12741 size > 4 && args.gpr < 4 )
12742 ret = args.reg_save_area[args.gpr+8]
12744 ret = *args.overflow_arg_area++;
12745 } else if (vector value) {
12746 ret = *args.overflow_arg_area;
12747 args.overflow_arg_area += size / 8;
12748 } else if (float value) {
12750 ret = args.reg_save_area[args.fpr+64]
12752 ret = *args.overflow_arg_area++;
12753 } else if (aggregate value) {
12755 ret = *args.reg_save_area[args.gpr]
12757 ret = **args.overflow_arg_area++;
12761 s390_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
12762 gimple_seq
*post_p ATTRIBUTE_UNUSED
)
12764 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
12765 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
12766 int indirect_p
, size
, n_reg
, sav_ofs
, sav_scale
, max_reg
;
12767 tree lab_false
, lab_over
= NULL_TREE
;
12768 tree addr
= create_tmp_var (ptr_type_node
, "addr");
12769 bool left_align_p
; /* How a value < UNITS_PER_LONG is aligned within
12772 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
12773 f_fpr
= DECL_CHAIN (f_gpr
);
12774 f_ovf
= DECL_CHAIN (f_fpr
);
12775 f_sav
= DECL_CHAIN (f_ovf
);
12777 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
12778 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
12779 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
12781 /* The tree for args* cannot be shared between gpr/fpr and ovf since
12782 both appear on a lhs. */
12783 valist
= unshare_expr (valist
);
12784 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
12786 size
= int_size_in_bytes (type
);
12788 s390_check_type_for_vector_abi (type
, true, false);
12790 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
12792 if (TARGET_DEBUG_ARG
)
12794 fprintf (stderr
, "va_arg: aggregate type");
12798 /* Aggregates are passed by reference. */
12803 /* kernel stack layout on 31 bit: It is assumed here that no padding
12804 will be added by s390_frame_info because for va_args always an even
12805 number of gprs has to be saved r15-r2 = 14 regs. */
12806 sav_ofs
= 2 * UNITS_PER_LONG
;
12807 sav_scale
= UNITS_PER_LONG
;
12808 size
= UNITS_PER_LONG
;
12809 max_reg
= GP_ARG_NUM_REG
- n_reg
;
12810 left_align_p
= false;
12812 else if (s390_function_arg_vector (TYPE_MODE (type
), type
))
12814 if (TARGET_DEBUG_ARG
)
12816 fprintf (stderr
, "va_arg: vector type");
12826 left_align_p
= true;
12828 else if (s390_function_arg_float (TYPE_MODE (type
), type
))
12830 if (TARGET_DEBUG_ARG
)
12832 fprintf (stderr
, "va_arg: float type");
12836 /* FP args go in FP registers, if present. */
12840 sav_ofs
= 16 * UNITS_PER_LONG
;
12842 max_reg
= FP_ARG_NUM_REG
- n_reg
;
12843 left_align_p
= false;
12847 if (TARGET_DEBUG_ARG
)
12849 fprintf (stderr
, "va_arg: other type");
12853 /* Otherwise into GP registers. */
12856 n_reg
= (size
+ UNITS_PER_LONG
- 1) / UNITS_PER_LONG
;
12858 /* kernel stack layout on 31 bit: It is assumed here that no padding
12859 will be added by s390_frame_info because for va_args always an even
12860 number of gprs has to be saved r15-r2 = 14 regs. */
12861 sav_ofs
= 2 * UNITS_PER_LONG
;
12863 if (size
< UNITS_PER_LONG
)
12864 sav_ofs
+= UNITS_PER_LONG
- size
;
12866 sav_scale
= UNITS_PER_LONG
;
12867 max_reg
= GP_ARG_NUM_REG
- n_reg
;
12868 left_align_p
= false;
12871 /* Pull the value out of the saved registers ... */
12873 if (reg
!= NULL_TREE
)
12876 if (reg > ((typeof (reg))max_reg))
12879 addr = sav + sav_ofs + reg * save_scale;
12886 lab_false
= create_artificial_label (UNKNOWN_LOCATION
);
12887 lab_over
= create_artificial_label (UNKNOWN_LOCATION
);
12889 t
= fold_convert (TREE_TYPE (reg
), size_int (max_reg
));
12890 t
= build2 (GT_EXPR
, boolean_type_node
, reg
, t
);
12891 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
12892 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
12893 gimplify_and_add (t
, pre_p
);
12895 t
= fold_build_pointer_plus_hwi (sav
, sav_ofs
);
12896 u
= build2 (MULT_EXPR
, TREE_TYPE (reg
), reg
,
12897 fold_convert (TREE_TYPE (reg
), size_int (sav_scale
)));
12898 t
= fold_build_pointer_plus (t
, u
);
12900 gimplify_assign (addr
, t
, pre_p
);
12902 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
12904 gimple_seq_add_stmt (pre_p
, gimple_build_label (lab_false
));
12907 /* ... Otherwise out of the overflow area. */
12910 if (size
< UNITS_PER_LONG
&& !left_align_p
)
12911 t
= fold_build_pointer_plus_hwi (t
, UNITS_PER_LONG
- size
);
12913 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
12915 gimplify_assign (addr
, t
, pre_p
);
12917 if (size
< UNITS_PER_LONG
&& left_align_p
)
12918 t
= fold_build_pointer_plus_hwi (t
, UNITS_PER_LONG
);
12920 t
= fold_build_pointer_plus_hwi (t
, size
);
12922 gimplify_assign (ovf
, t
, pre_p
);
12924 if (reg
!= NULL_TREE
)
12925 gimple_seq_add_stmt (pre_p
, gimple_build_label (lab_over
));
12928 /* Increment register save count. */
12932 u
= build2 (PREINCREMENT_EXPR
, TREE_TYPE (reg
), reg
,
12933 fold_convert (TREE_TYPE (reg
), size_int (n_reg
)));
12934 gimplify_and_add (u
, pre_p
);
12939 t
= build_pointer_type_for_mode (build_pointer_type (type
),
12941 addr
= fold_convert (t
, addr
);
12942 addr
= build_va_arg_indirect_ref (addr
);
12946 t
= build_pointer_type_for_mode (type
, ptr_mode
, true);
12947 addr
= fold_convert (t
, addr
);
12950 return build_va_arg_indirect_ref (addr
);
12953 /* Emit rtl for the tbegin or tbegin_retry (RETRY != NULL_RTX)
12955 DEST - Register location where CC will be stored.
12956 TDB - Pointer to a 256 byte area where to store the transaction.
12957 diagnostic block. NULL if TDB is not needed.
12958 RETRY - Retry count value. If non-NULL a retry loop for CC2
12960 CLOBBER_FPRS_P - If true clobbers for all FPRs are emitted as part
12961 of the tbegin instruction pattern. */
12964 s390_expand_tbegin (rtx dest
, rtx tdb
, rtx retry
, bool clobber_fprs_p
)
12966 rtx retry_plus_two
= gen_reg_rtx (SImode
);
12967 rtx retry_reg
= gen_reg_rtx (SImode
);
12968 rtx_code_label
*retry_label
= NULL
;
12970 if (retry
!= NULL_RTX
)
12972 emit_move_insn (retry_reg
, retry
);
12973 emit_insn (gen_addsi3 (retry_plus_two
, retry_reg
, const2_rtx
));
12974 emit_insn (gen_addsi3 (retry_reg
, retry_reg
, const1_rtx
));
12975 retry_label
= gen_label_rtx ();
12976 emit_label (retry_label
);
12979 if (clobber_fprs_p
)
12982 emit_insn (gen_tbegin_1_z13 (gen_rtx_CONST_INT (VOIDmode
, TBEGIN_MASK
),
12985 emit_insn (gen_tbegin_1 (gen_rtx_CONST_INT (VOIDmode
, TBEGIN_MASK
),
12989 emit_insn (gen_tbegin_nofloat_1 (gen_rtx_CONST_INT (VOIDmode
, TBEGIN_MASK
),
12992 emit_move_insn (dest
, gen_rtx_UNSPEC (SImode
,
12993 gen_rtvec (1, gen_rtx_REG (CCRAWmode
,
12995 UNSPEC_CC_TO_INT
));
12996 if (retry
!= NULL_RTX
)
12998 const int CC0
= 1 << 3;
12999 const int CC1
= 1 << 2;
13000 const int CC3
= 1 << 0;
13002 rtx count
= gen_reg_rtx (SImode
);
13003 rtx_code_label
*leave_label
= gen_label_rtx ();
13005 /* Exit for success and permanent failures. */
13006 jump
= s390_emit_jump (leave_label
,
13007 gen_rtx_EQ (VOIDmode
,
13008 gen_rtx_REG (CCRAWmode
, CC_REGNUM
),
13009 gen_rtx_CONST_INT (VOIDmode
, CC0
| CC1
| CC3
)));
13010 LABEL_NUSES (leave_label
) = 1;
13012 /* CC2 - transient failure. Perform retry with ppa. */
13013 emit_move_insn (count
, retry_plus_two
);
13014 emit_insn (gen_subsi3 (count
, count
, retry_reg
));
13015 emit_insn (gen_tx_assist (count
));
13016 jump
= emit_jump_insn (gen_doloop_si64 (retry_label
,
13019 JUMP_LABEL (jump
) = retry_label
;
13020 LABEL_NUSES (retry_label
) = 1;
13021 emit_label (leave_label
);
13026 /* Return the decl for the target specific builtin with the function
13030 s390_builtin_decl (unsigned fcode
, bool initialized_p ATTRIBUTE_UNUSED
)
13032 if (fcode
>= S390_BUILTIN_MAX
)
13033 return error_mark_node
;
13035 return s390_builtin_decls
[fcode
];
13038 /* We call mcount before the function prologue. So a profiled leaf
13039 function should stay a leaf function. */
13042 s390_keep_leaf_when_profiled ()
13047 /* Output assembly code for the trampoline template to
13050 On S/390, we use gpr 1 internally in the trampoline code;
13051 gpr 0 is used to hold the static chain. */
13054 s390_asm_trampoline_template (FILE *file
)
13057 op
[0] = gen_rtx_REG (Pmode
, 0);
13058 op
[1] = gen_rtx_REG (Pmode
, 1);
13062 output_asm_insn ("basr\t%1,0", op
); /* 2 byte */
13063 output_asm_insn ("lmg\t%0,%1,14(%1)", op
); /* 6 byte */
13064 output_asm_insn ("br\t%1", op
); /* 2 byte */
13065 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 10));
13069 output_asm_insn ("basr\t%1,0", op
); /* 2 byte */
13070 output_asm_insn ("lm\t%0,%1,6(%1)", op
); /* 4 byte */
13071 output_asm_insn ("br\t%1", op
); /* 2 byte */
13072 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 8));
13076 /* Emit RTL insns to initialize the variable parts of a trampoline.
13077 FNADDR is an RTX for the address of the function's pure code.
13078 CXT is an RTX for the static chain value for the function. */
13081 s390_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
13083 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
13086 emit_block_move (m_tramp
, assemble_trampoline_template (),
13087 GEN_INT (2 * UNITS_PER_LONG
), BLOCK_OP_NORMAL
);
13089 mem
= adjust_address (m_tramp
, Pmode
, 2 * UNITS_PER_LONG
);
13090 emit_move_insn (mem
, cxt
);
13091 mem
= adjust_address (m_tramp
, Pmode
, 3 * UNITS_PER_LONG
);
13092 emit_move_insn (mem
, fnaddr
);
13095 /* Output assembler code to FILE to increment profiler label # LABELNO
13096 for profiling a function entry. */
13099 s390_function_profiler (FILE *file
, int labelno
)
13104 ASM_GENERATE_INTERNAL_LABEL (label
, "LP", labelno
);
13106 fprintf (file
, "# function profiler \n");
13108 op
[0] = gen_rtx_REG (Pmode
, RETURN_REGNUM
);
13109 op
[1] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
13110 op
[1] = gen_rtx_MEM (Pmode
, plus_constant (Pmode
, op
[1], UNITS_PER_LONG
));
13112 op
[2] = gen_rtx_REG (Pmode
, 1);
13113 op
[3] = gen_rtx_SYMBOL_REF (Pmode
, label
);
13114 SYMBOL_REF_FLAGS (op
[3]) = SYMBOL_FLAG_LOCAL
;
13116 op
[4] = gen_rtx_SYMBOL_REF (Pmode
, "_mcount");
13119 op
[4] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[4]), UNSPEC_PLT
);
13120 op
[4] = gen_rtx_CONST (Pmode
, op
[4]);
13125 output_asm_insn ("stg\t%0,%1", op
);
13126 output_asm_insn ("larl\t%2,%3", op
);
13127 output_asm_insn ("brasl\t%0,%4", op
);
13128 output_asm_insn ("lg\t%0,%1", op
);
13130 else if (TARGET_CPU_ZARCH
)
13132 output_asm_insn ("st\t%0,%1", op
);
13133 output_asm_insn ("larl\t%2,%3", op
);
13134 output_asm_insn ("brasl\t%0,%4", op
);
13135 output_asm_insn ("l\t%0,%1", op
);
13137 else if (!flag_pic
)
13139 op
[6] = gen_label_rtx ();
13141 output_asm_insn ("st\t%0,%1", op
);
13142 output_asm_insn ("bras\t%2,%l6", op
);
13143 output_asm_insn (".long\t%4", op
);
13144 output_asm_insn (".long\t%3", op
);
13145 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
13146 output_asm_insn ("l\t%0,0(%2)", op
);
13147 output_asm_insn ("l\t%2,4(%2)", op
);
13148 output_asm_insn ("basr\t%0,%0", op
);
13149 output_asm_insn ("l\t%0,%1", op
);
13153 op
[5] = gen_label_rtx ();
13154 op
[6] = gen_label_rtx ();
13156 output_asm_insn ("st\t%0,%1", op
);
13157 output_asm_insn ("bras\t%2,%l6", op
);
13158 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[5]));
13159 output_asm_insn (".long\t%4-%l5", op
);
13160 output_asm_insn (".long\t%3-%l5", op
);
13161 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
13162 output_asm_insn ("lr\t%0,%2", op
);
13163 output_asm_insn ("a\t%0,0(%2)", op
);
13164 output_asm_insn ("a\t%2,4(%2)", op
);
13165 output_asm_insn ("basr\t%0,%0", op
);
13166 output_asm_insn ("l\t%0,%1", op
);
13170 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
13171 into its SYMBOL_REF_FLAGS. */
13174 s390_encode_section_info (tree decl
, rtx rtl
, int first
)
13176 default_encode_section_info (decl
, rtl
, first
);
13178 if (TREE_CODE (decl
) == VAR_DECL
)
13180 /* Store the alignment to be able to check if we can use
13181 a larl/load-relative instruction. We only handle the cases
13182 that can go wrong (i.e. no FUNC_DECLs). */
13183 if (DECL_ALIGN (decl
) == 0 || DECL_ALIGN (decl
) % 16)
13184 SYMBOL_FLAG_SET_NOTALIGN2 (XEXP (rtl
, 0));
13185 else if (DECL_ALIGN (decl
) % 32)
13186 SYMBOL_FLAG_SET_NOTALIGN4 (XEXP (rtl
, 0));
13187 else if (DECL_ALIGN (decl
) % 64)
13188 SYMBOL_FLAG_SET_NOTALIGN8 (XEXP (rtl
, 0));
13191 /* Literal pool references don't have a decl so they are handled
13192 differently here. We rely on the information in the MEM_ALIGN
13193 entry to decide upon the alignment. */
13195 && GET_CODE (XEXP (rtl
, 0)) == SYMBOL_REF
13196 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl
, 0)))
13198 if (MEM_ALIGN (rtl
) == 0 || MEM_ALIGN (rtl
) % 16)
13199 SYMBOL_FLAG_SET_NOTALIGN2 (XEXP (rtl
, 0));
13200 else if (MEM_ALIGN (rtl
) % 32)
13201 SYMBOL_FLAG_SET_NOTALIGN4 (XEXP (rtl
, 0));
13202 else if (MEM_ALIGN (rtl
) % 64)
13203 SYMBOL_FLAG_SET_NOTALIGN8 (XEXP (rtl
, 0));
13207 /* Output thunk to FILE that implements a C++ virtual function call (with
13208 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
13209 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
13210 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
13211 relative to the resulting this pointer. */
13214 s390_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
13215 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
13221 /* Make sure unwind info is emitted for the thunk if needed. */
13222 final_start_function (emit_barrier (), file
, 1);
13224 /* Operand 0 is the target function. */
13225 op
[0] = XEXP (DECL_RTL (function
), 0);
13226 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (op
[0]))
13229 op
[0] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[0]),
13230 TARGET_64BIT
? UNSPEC_PLT
: UNSPEC_GOT
);
13231 op
[0] = gen_rtx_CONST (Pmode
, op
[0]);
13234 /* Operand 1 is the 'this' pointer. */
13235 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
13236 op
[1] = gen_rtx_REG (Pmode
, 3);
13238 op
[1] = gen_rtx_REG (Pmode
, 2);
13240 /* Operand 2 is the delta. */
13241 op
[2] = GEN_INT (delta
);
13243 /* Operand 3 is the vcall_offset. */
13244 op
[3] = GEN_INT (vcall_offset
);
13246 /* Operand 4 is the temporary register. */
13247 op
[4] = gen_rtx_REG (Pmode
, 1);
13249 /* Operands 5 to 8 can be used as labels. */
13255 /* Operand 9 can be used for temporary register. */
13258 /* Generate code. */
13261 /* Setup literal pool pointer if required. */
13262 if ((!DISP_IN_RANGE (delta
)
13263 && !CONST_OK_FOR_K (delta
)
13264 && !CONST_OK_FOR_Os (delta
))
13265 || (!DISP_IN_RANGE (vcall_offset
)
13266 && !CONST_OK_FOR_K (vcall_offset
)
13267 && !CONST_OK_FOR_Os (vcall_offset
)))
13269 op
[5] = gen_label_rtx ();
13270 output_asm_insn ("larl\t%4,%5", op
);
13273 /* Add DELTA to this pointer. */
13276 if (CONST_OK_FOR_J (delta
))
13277 output_asm_insn ("la\t%1,%2(%1)", op
);
13278 else if (DISP_IN_RANGE (delta
))
13279 output_asm_insn ("lay\t%1,%2(%1)", op
);
13280 else if (CONST_OK_FOR_K (delta
))
13281 output_asm_insn ("aghi\t%1,%2", op
);
13282 else if (CONST_OK_FOR_Os (delta
))
13283 output_asm_insn ("agfi\t%1,%2", op
);
13286 op
[6] = gen_label_rtx ();
13287 output_asm_insn ("agf\t%1,%6-%5(%4)", op
);
13291 /* Perform vcall adjustment. */
13294 if (DISP_IN_RANGE (vcall_offset
))
13296 output_asm_insn ("lg\t%4,0(%1)", op
);
13297 output_asm_insn ("ag\t%1,%3(%4)", op
);
13299 else if (CONST_OK_FOR_K (vcall_offset
))
13301 output_asm_insn ("lghi\t%4,%3", op
);
13302 output_asm_insn ("ag\t%4,0(%1)", op
);
13303 output_asm_insn ("ag\t%1,0(%4)", op
);
13305 else if (CONST_OK_FOR_Os (vcall_offset
))
13307 output_asm_insn ("lgfi\t%4,%3", op
);
13308 output_asm_insn ("ag\t%4,0(%1)", op
);
13309 output_asm_insn ("ag\t%1,0(%4)", op
);
13313 op
[7] = gen_label_rtx ();
13314 output_asm_insn ("llgf\t%4,%7-%5(%4)", op
);
13315 output_asm_insn ("ag\t%4,0(%1)", op
);
13316 output_asm_insn ("ag\t%1,0(%4)", op
);
13320 /* Jump to target. */
13321 output_asm_insn ("jg\t%0", op
);
13323 /* Output literal pool if required. */
13326 output_asm_insn (".align\t4", op
);
13327 targetm
.asm_out
.internal_label (file
, "L",
13328 CODE_LABEL_NUMBER (op
[5]));
13332 targetm
.asm_out
.internal_label (file
, "L",
13333 CODE_LABEL_NUMBER (op
[6]));
13334 output_asm_insn (".long\t%2", op
);
13338 targetm
.asm_out
.internal_label (file
, "L",
13339 CODE_LABEL_NUMBER (op
[7]));
13340 output_asm_insn (".long\t%3", op
);
13345 /* Setup base pointer if required. */
13347 || (!DISP_IN_RANGE (delta
)
13348 && !CONST_OK_FOR_K (delta
)
13349 && !CONST_OK_FOR_Os (delta
))
13350 || (!DISP_IN_RANGE (delta
)
13351 && !CONST_OK_FOR_K (vcall_offset
)
13352 && !CONST_OK_FOR_Os (vcall_offset
)))
13354 op
[5] = gen_label_rtx ();
13355 output_asm_insn ("basr\t%4,0", op
);
13356 targetm
.asm_out
.internal_label (file
, "L",
13357 CODE_LABEL_NUMBER (op
[5]));
13360 /* Add DELTA to this pointer. */
13363 if (CONST_OK_FOR_J (delta
))
13364 output_asm_insn ("la\t%1,%2(%1)", op
);
13365 else if (DISP_IN_RANGE (delta
))
13366 output_asm_insn ("lay\t%1,%2(%1)", op
);
13367 else if (CONST_OK_FOR_K (delta
))
13368 output_asm_insn ("ahi\t%1,%2", op
);
13369 else if (CONST_OK_FOR_Os (delta
))
13370 output_asm_insn ("afi\t%1,%2", op
);
13373 op
[6] = gen_label_rtx ();
13374 output_asm_insn ("a\t%1,%6-%5(%4)", op
);
13378 /* Perform vcall adjustment. */
13381 if (CONST_OK_FOR_J (vcall_offset
))
13383 output_asm_insn ("l\t%4,0(%1)", op
);
13384 output_asm_insn ("a\t%1,%3(%4)", op
);
13386 else if (DISP_IN_RANGE (vcall_offset
))
13388 output_asm_insn ("l\t%4,0(%1)", op
);
13389 output_asm_insn ("ay\t%1,%3(%4)", op
);
13391 else if (CONST_OK_FOR_K (vcall_offset
))
13393 output_asm_insn ("lhi\t%4,%3", op
);
13394 output_asm_insn ("a\t%4,0(%1)", op
);
13395 output_asm_insn ("a\t%1,0(%4)", op
);
13397 else if (CONST_OK_FOR_Os (vcall_offset
))
13399 output_asm_insn ("iilf\t%4,%3", op
);
13400 output_asm_insn ("a\t%4,0(%1)", op
);
13401 output_asm_insn ("a\t%1,0(%4)", op
);
13405 op
[7] = gen_label_rtx ();
13406 output_asm_insn ("l\t%4,%7-%5(%4)", op
);
13407 output_asm_insn ("a\t%4,0(%1)", op
);
13408 output_asm_insn ("a\t%1,0(%4)", op
);
13411 /* We had to clobber the base pointer register.
13412 Re-setup the base pointer (with a different base). */
13413 op
[5] = gen_label_rtx ();
13414 output_asm_insn ("basr\t%4,0", op
);
13415 targetm
.asm_out
.internal_label (file
, "L",
13416 CODE_LABEL_NUMBER (op
[5]));
13419 /* Jump to target. */
13420 op
[8] = gen_label_rtx ();
13423 output_asm_insn ("l\t%4,%8-%5(%4)", op
);
13424 else if (!nonlocal
)
13425 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
13426 /* We cannot call through .plt, since .plt requires %r12 loaded. */
13427 else if (flag_pic
== 1)
13429 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
13430 output_asm_insn ("l\t%4,%0(%4)", op
);
13432 else if (flag_pic
== 2)
13434 op
[9] = gen_rtx_REG (Pmode
, 0);
13435 output_asm_insn ("l\t%9,%8-4-%5(%4)", op
);
13436 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
13437 output_asm_insn ("ar\t%4,%9", op
);
13438 output_asm_insn ("l\t%4,0(%4)", op
);
13441 output_asm_insn ("br\t%4", op
);
13443 /* Output literal pool. */
13444 output_asm_insn (".align\t4", op
);
13446 if (nonlocal
&& flag_pic
== 2)
13447 output_asm_insn (".long\t%0", op
);
13450 op
[0] = gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
13451 SYMBOL_REF_FLAGS (op
[0]) = SYMBOL_FLAG_LOCAL
;
13454 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[8]));
13456 output_asm_insn (".long\t%0", op
);
13458 output_asm_insn (".long\t%0-%5", op
);
13462 targetm
.asm_out
.internal_label (file
, "L",
13463 CODE_LABEL_NUMBER (op
[6]));
13464 output_asm_insn (".long\t%2", op
);
13468 targetm
.asm_out
.internal_label (file
, "L",
13469 CODE_LABEL_NUMBER (op
[7]));
13470 output_asm_insn (".long\t%3", op
);
13473 final_end_function ();
13477 s390_valid_pointer_mode (scalar_int_mode mode
)
13479 return (mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
));
13482 /* Checks whether the given CALL_EXPR would use a caller
13483 saved register. This is used to decide whether sibling call
13484 optimization could be performed on the respective function
13488 s390_call_saved_register_used (tree call_expr
)
13490 CUMULATIVE_ARGS cum_v
;
13491 cumulative_args_t cum
;
13498 INIT_CUMULATIVE_ARGS (cum_v
, NULL
, NULL
, 0, 0);
13499 cum
= pack_cumulative_args (&cum_v
);
13501 for (i
= 0; i
< call_expr_nargs (call_expr
); i
++)
13503 parameter
= CALL_EXPR_ARG (call_expr
, i
);
13504 gcc_assert (parameter
);
13506 /* For an undeclared variable passed as parameter we will get
13507 an ERROR_MARK node here. */
13508 if (TREE_CODE (parameter
) == ERROR_MARK
)
13511 type
= TREE_TYPE (parameter
);
13514 mode
= TYPE_MODE (type
);
13517 /* We assume that in the target function all parameters are
13518 named. This only has an impact on vector argument register
13519 usage none of which is call-saved. */
13520 if (pass_by_reference (&cum_v
, mode
, type
, true))
13523 type
= build_pointer_type (type
);
13526 parm_rtx
= s390_function_arg (cum
, mode
, type
, true);
13528 s390_function_arg_advance (cum
, mode
, type
, true);
13533 if (REG_P (parm_rtx
))
13535 for (reg
= 0; reg
< REG_NREGS (parm_rtx
); reg
++)
13536 if (!call_used_regs
[reg
+ REGNO (parm_rtx
)])
13540 if (GET_CODE (parm_rtx
) == PARALLEL
)
13544 for (i
= 0; i
< XVECLEN (parm_rtx
, 0); i
++)
13546 rtx r
= XEXP (XVECEXP (parm_rtx
, 0, i
), 0);
13548 gcc_assert (REG_P (r
));
13550 for (reg
= 0; reg
< REG_NREGS (r
); reg
++)
13551 if (!call_used_regs
[reg
+ REGNO (r
)])
13560 /* Return true if the given call expression can be
13561 turned into a sibling call.
13562 DECL holds the declaration of the function to be called whereas
13563 EXP is the call expression itself. */
13566 s390_function_ok_for_sibcall (tree decl
, tree exp
)
13568 /* The TPF epilogue uses register 1. */
13569 if (TARGET_TPF_PROFILING
)
13572 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
13573 which would have to be restored before the sibcall. */
13574 if (!TARGET_64BIT
&& flag_pic
&& decl
&& !targetm
.binds_local_p (decl
))
13577 /* Register 6 on s390 is available as an argument register but unfortunately
13578 "caller saved". This makes functions needing this register for arguments
13579 not suitable for sibcalls. */
13580 return !s390_call_saved_register_used (exp
);
13583 /* Return the fixed registers used for condition codes. */
13586 s390_fixed_condition_code_regs (unsigned int *p1
, unsigned int *p2
)
13589 *p2
= INVALID_REGNUM
;
13594 /* This function is used by the call expanders of the machine description.
13595 It emits the call insn itself together with the necessary operations
13596 to adjust the target address and returns the emitted insn.
13597 ADDR_LOCATION is the target address rtx
13598 TLS_CALL the location of the thread-local symbol
13599 RESULT_REG the register where the result of the call should be stored
13600 RETADDR_REG the register where the return address should be stored
13601 If this parameter is NULL_RTX the call is considered
13602 to be a sibling call. */
13605 s390_emit_call (rtx addr_location
, rtx tls_call
, rtx result_reg
,
13608 bool plt_call
= false;
13614 /* Direct function calls need special treatment. */
13615 if (GET_CODE (addr_location
) == SYMBOL_REF
)
13617 /* When calling a global routine in PIC mode, we must
13618 replace the symbol itself with the PLT stub. */
13619 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (addr_location
))
13621 if (TARGET_64BIT
|| retaddr_reg
!= NULL_RTX
)
13623 addr_location
= gen_rtx_UNSPEC (Pmode
,
13624 gen_rtvec (1, addr_location
),
13626 addr_location
= gen_rtx_CONST (Pmode
, addr_location
);
13630 /* For -fpic code the PLT entries might use r12 which is
13631 call-saved. Therefore we cannot do a sibcall when
13632 calling directly using a symbol ref. When reaching
13633 this point we decided (in s390_function_ok_for_sibcall)
13634 to do a sibcall for a function pointer but one of the
13635 optimizers was able to get rid of the function pointer
13636 by propagating the symbol ref into the call. This
13637 optimization is illegal for S/390 so we turn the direct
13638 call into a indirect call again. */
13639 addr_location
= force_reg (Pmode
, addr_location
);
13642 /* Unless we can use the bras(l) insn, force the
13643 routine address into a register. */
13644 if (!TARGET_SMALL_EXEC
&& !TARGET_CPU_ZARCH
)
13647 addr_location
= legitimize_pic_address (addr_location
, 0);
13649 addr_location
= force_reg (Pmode
, addr_location
);
13653 /* If it is already an indirect call or the code above moved the
13654 SYMBOL_REF to somewhere else make sure the address can be found in
13656 if (retaddr_reg
== NULL_RTX
13657 && GET_CODE (addr_location
) != SYMBOL_REF
13660 emit_move_insn (gen_rtx_REG (Pmode
, SIBCALL_REGNUM
), addr_location
);
13661 addr_location
= gen_rtx_REG (Pmode
, SIBCALL_REGNUM
);
13664 addr_location
= gen_rtx_MEM (QImode
, addr_location
);
13665 call
= gen_rtx_CALL (VOIDmode
, addr_location
, const0_rtx
);
13667 if (result_reg
!= NULL_RTX
)
13668 call
= gen_rtx_SET (result_reg
, call
);
13670 if (retaddr_reg
!= NULL_RTX
)
13672 clobber
= gen_rtx_CLOBBER (VOIDmode
, retaddr_reg
);
13674 if (tls_call
!= NULL_RTX
)
13675 vec
= gen_rtvec (3, call
, clobber
,
13676 gen_rtx_USE (VOIDmode
, tls_call
));
13678 vec
= gen_rtvec (2, call
, clobber
);
13680 call
= gen_rtx_PARALLEL (VOIDmode
, vec
);
13683 insn
= emit_call_insn (call
);
13685 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
13686 if ((!TARGET_64BIT
&& plt_call
) || tls_call
!= NULL_RTX
)
13688 /* s390_function_ok_for_sibcall should
13689 have denied sibcalls in this case. */
13690 gcc_assert (retaddr_reg
!= NULL_RTX
);
13691 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), gen_rtx_REG (Pmode
, 12));
13696 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
13699 s390_conditional_register_usage (void)
13705 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
13706 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
13708 if (TARGET_CPU_ZARCH
)
13710 fixed_regs
[BASE_REGNUM
] = 0;
13711 call_used_regs
[BASE_REGNUM
] = 0;
13712 fixed_regs
[RETURN_REGNUM
] = 0;
13713 call_used_regs
[RETURN_REGNUM
] = 0;
13717 for (i
= FPR8_REGNUM
; i
<= FPR15_REGNUM
; i
++)
13718 call_used_regs
[i
] = call_really_used_regs
[i
] = 0;
13722 call_used_regs
[FPR4_REGNUM
] = call_really_used_regs
[FPR4_REGNUM
] = 0;
13723 call_used_regs
[FPR6_REGNUM
] = call_really_used_regs
[FPR6_REGNUM
] = 0;
13726 if (TARGET_SOFT_FLOAT
)
13728 for (i
= FPR0_REGNUM
; i
<= FPR15_REGNUM
; i
++)
13729 call_used_regs
[i
] = fixed_regs
[i
] = 1;
13732 /* Disable v16 - v31 for non-vector target. */
13735 for (i
= VR16_REGNUM
; i
<= VR31_REGNUM
; i
++)
13736 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
13740 /* Corresponding function to eh_return expander. */
13742 static GTY(()) rtx s390_tpf_eh_return_symbol
;
13744 s390_emit_tpf_eh_return (rtx target
)
13749 if (!s390_tpf_eh_return_symbol
)
13750 s390_tpf_eh_return_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tpf_eh_return");
13752 reg
= gen_rtx_REG (Pmode
, 2);
13753 orig_ra
= gen_rtx_REG (Pmode
, 3);
13755 emit_move_insn (reg
, target
);
13756 emit_move_insn (orig_ra
, get_hard_reg_initial_val (Pmode
, RETURN_REGNUM
));
13757 insn
= s390_emit_call (s390_tpf_eh_return_symbol
, NULL_RTX
, reg
,
13758 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
13759 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
13760 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), orig_ra
);
13762 emit_move_insn (EH_RETURN_HANDLER_RTX
, reg
);
13765 /* Rework the prologue/epilogue to avoid saving/restoring
13766 registers unnecessarily. */
13769 s390_optimize_prologue (void)
13771 rtx_insn
*insn
, *new_insn
, *next_insn
;
13773 /* Do a final recompute of the frame-related data. */
13774 s390_optimize_register_info ();
13776 /* If all special registers are in fact used, there's nothing we
13777 can do, so no point in walking the insn list. */
13779 if (cfun_frame_layout
.first_save_gpr
<= BASE_REGNUM
13780 && cfun_frame_layout
.last_save_gpr
>= BASE_REGNUM
13781 && (TARGET_CPU_ZARCH
13782 || (cfun_frame_layout
.first_save_gpr
<= RETURN_REGNUM
13783 && cfun_frame_layout
.last_save_gpr
>= RETURN_REGNUM
)))
13786 /* Search for prologue/epilogue insns and replace them. */
13788 for (insn
= get_insns (); insn
; insn
= next_insn
)
13790 int first
, last
, off
;
13791 rtx set
, base
, offset
;
13794 next_insn
= NEXT_INSN (insn
);
13796 if (! NONJUMP_INSN_P (insn
) || ! RTX_FRAME_RELATED_P (insn
))
13799 pat
= PATTERN (insn
);
13801 /* Remove ldgr/lgdr instructions used for saving and restore
13802 GPRs if possible. */
13807 if (INSN_CODE (insn
) == CODE_FOR_stack_restore_from_fpr
)
13808 tmp_pat
= XVECEXP (pat
, 0, 0);
13810 if (GET_CODE (tmp_pat
) == SET
13811 && GET_MODE (SET_SRC (tmp_pat
)) == DImode
13812 && REG_P (SET_SRC (tmp_pat
))
13813 && REG_P (SET_DEST (tmp_pat
)))
13815 int src_regno
= REGNO (SET_SRC (tmp_pat
));
13816 int dest_regno
= REGNO (SET_DEST (tmp_pat
));
13820 if (!((GENERAL_REGNO_P (src_regno
)
13821 && FP_REGNO_P (dest_regno
))
13822 || (FP_REGNO_P (src_regno
)
13823 && GENERAL_REGNO_P (dest_regno
))))
13826 gpr_regno
= GENERAL_REGNO_P (src_regno
) ? src_regno
: dest_regno
;
13827 fpr_regno
= FP_REGNO_P (src_regno
) ? src_regno
: dest_regno
;
13829 /* GPR must be call-saved, FPR must be call-clobbered. */
13830 if (!call_really_used_regs
[fpr_regno
]
13831 || call_really_used_regs
[gpr_regno
])
13834 /* It must not happen that what we once saved in an FPR now
13835 needs a stack slot. */
13836 gcc_assert (cfun_gpr_save_slot (gpr_regno
) != SAVE_SLOT_STACK
);
13838 if (cfun_gpr_save_slot (gpr_regno
) == SAVE_SLOT_NONE
)
13840 remove_insn (insn
);
13846 if (GET_CODE (pat
) == PARALLEL
13847 && store_multiple_operation (pat
, VOIDmode
))
13849 set
= XVECEXP (pat
, 0, 0);
13850 first
= REGNO (SET_SRC (set
));
13851 last
= first
+ XVECLEN (pat
, 0) - 1;
13852 offset
= const0_rtx
;
13853 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
13854 off
= INTVAL (offset
);
13856 if (GET_CODE (base
) != REG
|| off
< 0)
13858 if (cfun_frame_layout
.first_save_gpr
!= -1
13859 && (cfun_frame_layout
.first_save_gpr
< first
13860 || cfun_frame_layout
.last_save_gpr
> last
))
13862 if (REGNO (base
) != STACK_POINTER_REGNUM
13863 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
13865 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
13868 if (cfun_frame_layout
.first_save_gpr
!= -1)
13870 rtx s_pat
= save_gprs (base
,
13871 off
+ (cfun_frame_layout
.first_save_gpr
13872 - first
) * UNITS_PER_LONG
,
13873 cfun_frame_layout
.first_save_gpr
,
13874 cfun_frame_layout
.last_save_gpr
);
13875 new_insn
= emit_insn_before (s_pat
, insn
);
13876 INSN_ADDRESSES_NEW (new_insn
, -1);
13879 remove_insn (insn
);
13883 if (cfun_frame_layout
.first_save_gpr
== -1
13884 && GET_CODE (pat
) == SET
13885 && GENERAL_REG_P (SET_SRC (pat
))
13886 && GET_CODE (SET_DEST (pat
)) == MEM
)
13889 first
= REGNO (SET_SRC (set
));
13890 offset
= const0_rtx
;
13891 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
13892 off
= INTVAL (offset
);
13894 if (GET_CODE (base
) != REG
|| off
< 0)
13896 if (REGNO (base
) != STACK_POINTER_REGNUM
13897 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
13900 remove_insn (insn
);
13904 if (GET_CODE (pat
) == PARALLEL
13905 && load_multiple_operation (pat
, VOIDmode
))
13907 set
= XVECEXP (pat
, 0, 0);
13908 first
= REGNO (SET_DEST (set
));
13909 last
= first
+ XVECLEN (pat
, 0) - 1;
13910 offset
= const0_rtx
;
13911 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
13912 off
= INTVAL (offset
);
13914 if (GET_CODE (base
) != REG
|| off
< 0)
13917 if (cfun_frame_layout
.first_restore_gpr
!= -1
13918 && (cfun_frame_layout
.first_restore_gpr
< first
13919 || cfun_frame_layout
.last_restore_gpr
> last
))
13921 if (REGNO (base
) != STACK_POINTER_REGNUM
13922 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
13924 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
13927 if (cfun_frame_layout
.first_restore_gpr
!= -1)
13929 rtx rpat
= restore_gprs (base
,
13930 off
+ (cfun_frame_layout
.first_restore_gpr
13931 - first
) * UNITS_PER_LONG
,
13932 cfun_frame_layout
.first_restore_gpr
,
13933 cfun_frame_layout
.last_restore_gpr
);
13935 /* Remove REG_CFA_RESTOREs for registers that we no
13936 longer need to save. */
13937 REG_NOTES (rpat
) = REG_NOTES (insn
);
13938 for (rtx
*ptr
= ®_NOTES (rpat
); *ptr
; )
13939 if (REG_NOTE_KIND (*ptr
) == REG_CFA_RESTORE
13940 && ((int) REGNO (XEXP (*ptr
, 0))
13941 < cfun_frame_layout
.first_restore_gpr
))
13942 *ptr
= XEXP (*ptr
, 1);
13944 ptr
= &XEXP (*ptr
, 1);
13945 new_insn
= emit_insn_before (rpat
, insn
);
13946 RTX_FRAME_RELATED_P (new_insn
) = 1;
13947 INSN_ADDRESSES_NEW (new_insn
, -1);
13950 remove_insn (insn
);
13954 if (cfun_frame_layout
.first_restore_gpr
== -1
13955 && GET_CODE (pat
) == SET
13956 && GENERAL_REG_P (SET_DEST (pat
))
13957 && GET_CODE (SET_SRC (pat
)) == MEM
)
13960 first
= REGNO (SET_DEST (set
));
13961 offset
= const0_rtx
;
13962 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
13963 off
= INTVAL (offset
);
13965 if (GET_CODE (base
) != REG
|| off
< 0)
13968 if (REGNO (base
) != STACK_POINTER_REGNUM
13969 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
13972 remove_insn (insn
);
13978 /* On z10 and later the dynamic branch prediction must see the
13979 backward jump within a certain windows. If not it falls back to
13980 the static prediction. This function rearranges the loop backward
13981 branch in a way which makes the static prediction always correct.
13982 The function returns true if it added an instruction. */
13984 s390_fix_long_loop_prediction (rtx_insn
*insn
)
13986 rtx set
= single_set (insn
);
13987 rtx code_label
, label_ref
;
13988 rtx_insn
*uncond_jump
;
13989 rtx_insn
*cur_insn
;
13993 /* This will exclude branch on count and branch on index patterns
13994 since these are correctly statically predicted. */
13996 || SET_DEST (set
) != pc_rtx
13997 || GET_CODE (SET_SRC(set
)) != IF_THEN_ELSE
)
14000 /* Skip conditional returns. */
14001 if (ANY_RETURN_P (XEXP (SET_SRC (set
), 1))
14002 && XEXP (SET_SRC (set
), 2) == pc_rtx
)
14005 label_ref
= (GET_CODE (XEXP (SET_SRC (set
), 1)) == LABEL_REF
?
14006 XEXP (SET_SRC (set
), 1) : XEXP (SET_SRC (set
), 2));
14008 gcc_assert (GET_CODE (label_ref
) == LABEL_REF
);
14010 code_label
= XEXP (label_ref
, 0);
14012 if (INSN_ADDRESSES (INSN_UID (code_label
)) == -1
14013 || INSN_ADDRESSES (INSN_UID (insn
)) == -1
14014 || (INSN_ADDRESSES (INSN_UID (insn
))
14015 - INSN_ADDRESSES (INSN_UID (code_label
)) < PREDICT_DISTANCE
))
14018 for (distance
= 0, cur_insn
= PREV_INSN (insn
);
14019 distance
< PREDICT_DISTANCE
- 6;
14020 distance
+= get_attr_length (cur_insn
), cur_insn
= PREV_INSN (cur_insn
))
14021 if (!cur_insn
|| JUMP_P (cur_insn
) || LABEL_P (cur_insn
))
14024 rtx_code_label
*new_label
= gen_label_rtx ();
14025 uncond_jump
= emit_jump_insn_after (
14026 gen_rtx_SET (pc_rtx
,
14027 gen_rtx_LABEL_REF (VOIDmode
, code_label
)),
14029 emit_label_after (new_label
, uncond_jump
);
14031 tmp
= XEXP (SET_SRC (set
), 1);
14032 XEXP (SET_SRC (set
), 1) = XEXP (SET_SRC (set
), 2);
14033 XEXP (SET_SRC (set
), 2) = tmp
;
14034 INSN_CODE (insn
) = -1;
14036 XEXP (label_ref
, 0) = new_label
;
14037 JUMP_LABEL (insn
) = new_label
;
14038 JUMP_LABEL (uncond_jump
) = code_label
;
14043 /* Returns 1 if INSN reads the value of REG for purposes not related
14044 to addressing of memory, and 0 otherwise. */
14046 s390_non_addr_reg_read_p (rtx reg
, rtx_insn
*insn
)
14048 return reg_referenced_p (reg
, PATTERN (insn
))
14049 && !reg_used_in_mem_p (REGNO (reg
), PATTERN (insn
));
14052 /* Starting from INSN find_cond_jump looks downwards in the insn
14053 stream for a single jump insn which is the last user of the
14054 condition code set in INSN. */
14056 find_cond_jump (rtx_insn
*insn
)
14058 for (; insn
; insn
= NEXT_INSN (insn
))
14062 if (LABEL_P (insn
))
14065 if (!JUMP_P (insn
))
14067 if (reg_mentioned_p (gen_rtx_REG (CCmode
, CC_REGNUM
), insn
))
14072 /* This will be triggered by a return. */
14073 if (GET_CODE (PATTERN (insn
)) != SET
)
14076 gcc_assert (SET_DEST (PATTERN (insn
)) == pc_rtx
);
14077 ite
= SET_SRC (PATTERN (insn
));
14079 if (GET_CODE (ite
) != IF_THEN_ELSE
)
14082 cc
= XEXP (XEXP (ite
, 0), 0);
14083 if (!REG_P (cc
) || !CC_REGNO_P (REGNO (cc
)))
14086 if (find_reg_note (insn
, REG_DEAD
, cc
))
14094 /* Swap the condition in COND and the operands in OP0 and OP1 so that
14095 the semantics does not change. If NULL_RTX is passed as COND the
14096 function tries to find the conditional jump starting with INSN. */
14098 s390_swap_cmp (rtx cond
, rtx
*op0
, rtx
*op1
, rtx_insn
*insn
)
14102 if (cond
== NULL_RTX
)
14104 rtx_insn
*jump
= find_cond_jump (NEXT_INSN (insn
));
14105 rtx set
= jump
? single_set (jump
) : NULL_RTX
;
14107 if (set
== NULL_RTX
)
14110 cond
= XEXP (SET_SRC (set
), 0);
14115 PUT_CODE (cond
, swap_condition (GET_CODE (cond
)));
14118 /* On z10, instructions of the compare-and-branch family have the
14119 property to access the register occurring as second operand with
14120 its bits complemented. If such a compare is grouped with a second
14121 instruction that accesses the same register non-complemented, and
14122 if that register's value is delivered via a bypass, then the
14123 pipeline recycles, thereby causing significant performance decline.
14124 This function locates such situations and exchanges the two
14125 operands of the compare. The function return true whenever it
14128 s390_z10_optimize_cmp (rtx_insn
*insn
)
14130 rtx_insn
*prev_insn
, *next_insn
;
14131 bool insn_added_p
= false;
14132 rtx cond
, *op0
, *op1
;
14134 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
14136 /* Handle compare and branch and branch on count
14138 rtx pattern
= single_set (insn
);
14141 || SET_DEST (pattern
) != pc_rtx
14142 || GET_CODE (SET_SRC (pattern
)) != IF_THEN_ELSE
)
14145 cond
= XEXP (SET_SRC (pattern
), 0);
14146 op0
= &XEXP (cond
, 0);
14147 op1
= &XEXP (cond
, 1);
14149 else if (GET_CODE (PATTERN (insn
)) == SET
)
14153 /* Handle normal compare instructions. */
14154 src
= SET_SRC (PATTERN (insn
));
14155 dest
= SET_DEST (PATTERN (insn
));
14158 || !CC_REGNO_P (REGNO (dest
))
14159 || GET_CODE (src
) != COMPARE
)
14162 /* s390_swap_cmp will try to find the conditional
14163 jump when passing NULL_RTX as condition. */
14165 op0
= &XEXP (src
, 0);
14166 op1
= &XEXP (src
, 1);
14171 if (!REG_P (*op0
) || !REG_P (*op1
))
14174 if (GET_MODE_CLASS (GET_MODE (*op0
)) != MODE_INT
)
14177 /* Swap the COMPARE arguments and its mask if there is a
14178 conflicting access in the previous insn. */
14179 prev_insn
= prev_active_insn (insn
);
14180 if (prev_insn
!= NULL_RTX
&& INSN_P (prev_insn
)
14181 && reg_referenced_p (*op1
, PATTERN (prev_insn
)))
14182 s390_swap_cmp (cond
, op0
, op1
, insn
);
14184 /* Check if there is a conflict with the next insn. If there
14185 was no conflict with the previous insn, then swap the
14186 COMPARE arguments and its mask. If we already swapped
14187 the operands, or if swapping them would cause a conflict
14188 with the previous insn, issue a NOP after the COMPARE in
14189 order to separate the two instuctions. */
14190 next_insn
= next_active_insn (insn
);
14191 if (next_insn
!= NULL_RTX
&& INSN_P (next_insn
)
14192 && s390_non_addr_reg_read_p (*op1
, next_insn
))
14194 if (prev_insn
!= NULL_RTX
&& INSN_P (prev_insn
)
14195 && s390_non_addr_reg_read_p (*op0
, prev_insn
))
14197 if (REGNO (*op1
) == 0)
14198 emit_insn_after (gen_nop1 (), insn
);
14200 emit_insn_after (gen_nop (), insn
);
14201 insn_added_p
= true;
14204 s390_swap_cmp (cond
, op0
, op1
, insn
);
14206 return insn_added_p
;
14209 /* Number of INSNs to be scanned backward in the last BB of the loop
14210 and forward in the first BB of the loop. This usually should be a
14211 bit more than the number of INSNs which could go into one
14213 #define S390_OSC_SCAN_INSN_NUM 5
14215 /* Scan LOOP for static OSC collisions and return true if a osc_break
14216 should be issued for this loop. */
14218 s390_adjust_loop_scan_osc (struct loop
* loop
)
14221 HARD_REG_SET modregs
, newregs
;
14222 rtx_insn
*insn
, *store_insn
= NULL
;
14224 struct s390_address addr_store
, addr_load
;
14225 subrtx_iterator::array_type array
;
14228 CLEAR_HARD_REG_SET (modregs
);
14231 FOR_BB_INSNS_REVERSE (loop
->latch
, insn
)
14233 if (!INSN_P (insn
) || INSN_CODE (insn
) <= 0)
14237 if (insn_count
> S390_OSC_SCAN_INSN_NUM
)
14240 find_all_hard_reg_sets (insn
, &newregs
, true);
14241 IOR_HARD_REG_SET (modregs
, newregs
);
14243 set
= single_set (insn
);
14247 if (MEM_P (SET_DEST (set
))
14248 && s390_decompose_address (XEXP (SET_DEST (set
), 0), &addr_store
))
14255 if (store_insn
== NULL_RTX
)
14259 FOR_BB_INSNS (loop
->header
, insn
)
14261 if (!INSN_P (insn
) || INSN_CODE (insn
) <= 0)
14264 if (insn
== store_insn
)
14268 if (insn_count
> S390_OSC_SCAN_INSN_NUM
)
14271 find_all_hard_reg_sets (insn
, &newregs
, true);
14272 IOR_HARD_REG_SET (modregs
, newregs
);
14274 set
= single_set (insn
);
14278 /* An intermediate store disrupts static OSC checking
14280 if (MEM_P (SET_DEST (set
))
14281 && s390_decompose_address (XEXP (SET_DEST (set
), 0), NULL
))
14284 FOR_EACH_SUBRTX (iter
, array
, SET_SRC (set
), NONCONST
)
14286 && s390_decompose_address (XEXP (*iter
, 0), &addr_load
)
14287 && rtx_equal_p (addr_load
.base
, addr_store
.base
)
14288 && rtx_equal_p (addr_load
.indx
, addr_store
.indx
)
14289 && rtx_equal_p (addr_load
.disp
, addr_store
.disp
))
14291 if ((addr_load
.base
!= NULL_RTX
14292 && TEST_HARD_REG_BIT (modregs
, REGNO (addr_load
.base
)))
14293 || (addr_load
.indx
!= NULL_RTX
14294 && TEST_HARD_REG_BIT (modregs
, REGNO (addr_load
.indx
))))
14301 /* Look for adjustments which can be done on simple innermost
14304 s390_adjust_loops ()
14306 struct loop
*loop
= NULL
;
14309 compute_bb_for_insn ();
14311 /* Find the loops. */
14312 loop_optimizer_init (AVOID_CFG_MODIFICATIONS
);
14314 FOR_EACH_LOOP (loop
, LI_ONLY_INNERMOST
)
14318 flow_loop_dump (loop
, dump_file
, NULL
, 0);
14319 fprintf (dump_file
, ";; OSC loop scan Loop: ");
14321 if (loop
->latch
== NULL
14322 || pc_set (BB_END (loop
->latch
)) == NULL_RTX
14323 || !s390_adjust_loop_scan_osc (loop
))
14327 if (loop
->latch
== NULL
)
14328 fprintf (dump_file
, " muliple backward jumps\n");
14331 fprintf (dump_file
, " header insn: %d latch insn: %d ",
14332 INSN_UID (BB_HEAD (loop
->header
)),
14333 INSN_UID (BB_END (loop
->latch
)));
14334 if (pc_set (BB_END (loop
->latch
)) == NULL_RTX
)
14335 fprintf (dump_file
, " loop does not end with jump\n");
14337 fprintf (dump_file
, " not instrumented\n");
14343 rtx_insn
*new_insn
;
14346 fprintf (dump_file
, " adding OSC break insn: ");
14347 new_insn
= emit_insn_before (gen_osc_break (),
14348 BB_END (loop
->latch
));
14349 INSN_ADDRESSES_NEW (new_insn
, -1);
14353 loop_optimizer_finalize ();
14355 df_finish_pass (false);
14358 /* Perform machine-dependent processing. */
14363 bool pool_overflow
= false;
14364 int hw_before
, hw_after
;
14366 if (s390_tune
== PROCESSOR_2964_Z13
)
14367 s390_adjust_loops ();
14369 /* Make sure all splits have been performed; splits after
14370 machine_dependent_reorg might confuse insn length counts. */
14371 split_all_insns_noflow ();
14373 /* Install the main literal pool and the associated base
14374 register load insns.
14376 In addition, there are two problematic situations we need
14379 - the literal pool might be > 4096 bytes in size, so that
14380 some of its elements cannot be directly accessed
14382 - a branch target might be > 64K away from the branch, so that
14383 it is not possible to use a PC-relative instruction.
14385 To fix those, we split the single literal pool into multiple
14386 pool chunks, reloading the pool base register at various
14387 points throughout the function to ensure it always points to
14388 the pool chunk the following code expects, and / or replace
14389 PC-relative branches by absolute branches.
14391 However, the two problems are interdependent: splitting the
14392 literal pool can move a branch further away from its target,
14393 causing the 64K limit to overflow, and on the other hand,
14394 replacing a PC-relative branch by an absolute branch means
14395 we need to put the branch target address into the literal
14396 pool, possibly causing it to overflow.
14398 So, we loop trying to fix up both problems until we manage
14399 to satisfy both conditions at the same time. Note that the
14400 loop is guaranteed to terminate as every pass of the loop
14401 strictly decreases the total number of PC-relative branches
14402 in the function. (This is not completely true as there
14403 might be branch-over-pool insns introduced by chunkify_start.
14404 Those never need to be split however.) */
14408 struct constant_pool
*pool
= NULL
;
14410 /* Collect the literal pool. */
14411 if (!pool_overflow
)
14413 pool
= s390_mainpool_start ();
14415 pool_overflow
= true;
14418 /* If literal pool overflowed, start to chunkify it. */
14420 pool
= s390_chunkify_start ();
14422 /* Split out-of-range branches. If this has created new
14423 literal pool entries, cancel current chunk list and
14424 recompute it. zSeries machines have large branch
14425 instructions, so we never need to split a branch. */
14426 if (!TARGET_CPU_ZARCH
&& s390_split_branches ())
14429 s390_chunkify_cancel (pool
);
14431 s390_mainpool_cancel (pool
);
14436 /* If we made it up to here, both conditions are satisfied.
14437 Finish up literal pool related changes. */
14439 s390_chunkify_finish (pool
);
14441 s390_mainpool_finish (pool
);
14443 /* We're done splitting branches. */
14444 cfun
->machine
->split_branches_pending_p
= false;
14448 /* Generate out-of-pool execute target insns. */
14449 if (TARGET_CPU_ZARCH
)
14451 rtx_insn
*insn
, *target
;
14454 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
14456 label
= s390_execute_label (insn
);
14460 gcc_assert (label
!= const0_rtx
);
14462 target
= emit_label (XEXP (label
, 0));
14463 INSN_ADDRESSES_NEW (target
, -1);
14465 target
= emit_insn (s390_execute_target (insn
));
14466 INSN_ADDRESSES_NEW (target
, -1);
14470 /* Try to optimize prologue and epilogue further. */
14471 s390_optimize_prologue ();
14473 /* Walk over the insns and do some >=z10 specific changes. */
14474 if (s390_tune
>= PROCESSOR_2097_Z10
)
14477 bool insn_added_p
= false;
14479 /* The insn lengths and addresses have to be up to date for the
14480 following manipulations. */
14481 shorten_branches (get_insns ());
14483 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
14485 if (!INSN_P (insn
) || INSN_CODE (insn
) <= 0)
14489 insn_added_p
|= s390_fix_long_loop_prediction (insn
);
14491 if ((GET_CODE (PATTERN (insn
)) == PARALLEL
14492 || GET_CODE (PATTERN (insn
)) == SET
)
14493 && s390_tune
== PROCESSOR_2097_Z10
)
14494 insn_added_p
|= s390_z10_optimize_cmp (insn
);
14497 /* Adjust branches if we added new instructions. */
14499 shorten_branches (get_insns ());
14502 s390_function_num_hotpatch_hw (current_function_decl
, &hw_before
, &hw_after
);
14507 /* Insert NOPs for hotpatching. */
14508 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
14510 1. inside the area covered by debug information to allow setting
14511 breakpoints at the NOPs,
14512 2. before any insn which results in an asm instruction,
14513 3. before in-function labels to avoid jumping to the NOPs, for
14514 example as part of a loop,
14515 4. before any barrier in case the function is completely empty
14516 (__builtin_unreachable ()) and has neither internal labels nor
14519 if (active_insn_p (insn
) || BARRIER_P (insn
) || LABEL_P (insn
))
14521 /* Output a series of NOPs before the first active insn. */
14522 while (insn
&& hw_after
> 0)
14524 if (hw_after
>= 3 && TARGET_CPU_ZARCH
)
14526 emit_insn_before (gen_nop_6_byte (), insn
);
14529 else if (hw_after
>= 2)
14531 emit_insn_before (gen_nop_4_byte (), insn
);
14536 emit_insn_before (gen_nop_2_byte (), insn
);
14543 /* Return true if INSN is a fp load insn writing register REGNO. */
14545 s390_fpload_toreg (rtx_insn
*insn
, unsigned int regno
)
14548 enum attr_type flag
= s390_safe_attr_type (insn
);
14550 if (flag
!= TYPE_FLOADSF
&& flag
!= TYPE_FLOADDF
)
14553 set
= single_set (insn
);
14555 if (set
== NULL_RTX
)
14558 if (!REG_P (SET_DEST (set
)) || !MEM_P (SET_SRC (set
)))
14561 if (REGNO (SET_DEST (set
)) != regno
)
14567 /* This value describes the distance to be avoided between an
14568 arithmetic fp instruction and an fp load writing the same register.
14569 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
14570 fine but the exact value has to be avoided. Otherwise the FP
14571 pipeline will throw an exception causing a major penalty. */
14572 #define Z10_EARLYLOAD_DISTANCE 7
14574 /* Rearrange the ready list in order to avoid the situation described
14575 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
14576 moved to the very end of the ready list. */
14578 s390_z10_prevent_earlyload_conflicts (rtx_insn
**ready
, int *nready_p
)
14580 unsigned int regno
;
14581 int nready
= *nready_p
;
14586 enum attr_type flag
;
14589 /* Skip DISTANCE - 1 active insns. */
14590 for (insn
= last_scheduled_insn
, distance
= Z10_EARLYLOAD_DISTANCE
- 1;
14591 distance
> 0 && insn
!= NULL_RTX
;
14592 distance
--, insn
= prev_active_insn (insn
))
14593 if (CALL_P (insn
) || JUMP_P (insn
))
14596 if (insn
== NULL_RTX
)
14599 set
= single_set (insn
);
14601 if (set
== NULL_RTX
|| !REG_P (SET_DEST (set
))
14602 || GET_MODE_CLASS (GET_MODE (SET_DEST (set
))) != MODE_FLOAT
)
14605 flag
= s390_safe_attr_type (insn
);
14607 if (flag
== TYPE_FLOADSF
|| flag
== TYPE_FLOADDF
)
14610 regno
= REGNO (SET_DEST (set
));
14613 while (!s390_fpload_toreg (ready
[i
], regno
) && i
> 0)
14620 memmove (&ready
[1], &ready
[0], sizeof (rtx_insn
*) * i
);
14624 /* Returns TRUE if BB is entered via a fallthru edge and all other
14625 incoming edges are less than unlikely. */
14627 s390_bb_fallthru_entry_likely (basic_block bb
)
14629 edge e
, fallthru_edge
;
14635 fallthru_edge
= find_fallthru_edge (bb
->preds
);
14636 if (!fallthru_edge
)
14639 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
14640 if (e
!= fallthru_edge
14641 && e
->probability
>= profile_probability::unlikely ())
14647 /* The s390_sched_state variable tracks the state of the current or
14648 the last instruction group.
14650 0,1,2 number of instructions scheduled in the current group
14651 3 the last group is complete - normal insns
14652 4 the last group was a cracked/expanded insn */
14654 static int s390_sched_state
= 0;
14656 #define S390_SCHED_STATE_NORMAL 3
14657 #define S390_SCHED_STATE_CRACKED 4
14659 #define S390_SCHED_ATTR_MASK_CRACKED 0x1
14660 #define S390_SCHED_ATTR_MASK_EXPANDED 0x2
14661 #define S390_SCHED_ATTR_MASK_ENDGROUP 0x4
14662 #define S390_SCHED_ATTR_MASK_GROUPALONE 0x8
14664 static unsigned int
14665 s390_get_sched_attrmask (rtx_insn
*insn
)
14667 unsigned int mask
= 0;
14671 case PROCESSOR_2827_ZEC12
:
14672 if (get_attr_zEC12_cracked (insn
))
14673 mask
|= S390_SCHED_ATTR_MASK_CRACKED
;
14674 if (get_attr_zEC12_expanded (insn
))
14675 mask
|= S390_SCHED_ATTR_MASK_EXPANDED
;
14676 if (get_attr_zEC12_endgroup (insn
))
14677 mask
|= S390_SCHED_ATTR_MASK_ENDGROUP
;
14678 if (get_attr_zEC12_groupalone (insn
))
14679 mask
|= S390_SCHED_ATTR_MASK_GROUPALONE
;
14681 case PROCESSOR_2964_Z13
:
14682 case PROCESSOR_3906_Z14
:
14683 if (get_attr_z13_cracked (insn
))
14684 mask
|= S390_SCHED_ATTR_MASK_CRACKED
;
14685 if (get_attr_z13_expanded (insn
))
14686 mask
|= S390_SCHED_ATTR_MASK_EXPANDED
;
14687 if (get_attr_z13_endgroup (insn
))
14688 mask
|= S390_SCHED_ATTR_MASK_ENDGROUP
;
14689 if (get_attr_z13_groupalone (insn
))
14690 mask
|= S390_SCHED_ATTR_MASK_GROUPALONE
;
14693 gcc_unreachable ();
14698 static unsigned int
14699 s390_get_unit_mask (rtx_insn
*insn
, int *units
)
14701 unsigned int mask
= 0;
14705 case PROCESSOR_2964_Z13
:
14706 case PROCESSOR_3906_Z14
:
14708 if (get_attr_z13_unit_lsu (insn
))
14710 if (get_attr_z13_unit_fxu (insn
))
14712 if (get_attr_z13_unit_vfu (insn
))
14716 gcc_unreachable ();
14721 /* Return the scheduling score for INSN. The higher the score the
14722 better. The score is calculated from the OOO scheduling attributes
14723 of INSN and the scheduling state s390_sched_state. */
14725 s390_sched_score (rtx_insn
*insn
)
14727 unsigned int mask
= s390_get_sched_attrmask (insn
);
14730 switch (s390_sched_state
)
14733 /* Try to put insns into the first slot which would otherwise
14735 if ((mask
& S390_SCHED_ATTR_MASK_CRACKED
) != 0
14736 || (mask
& S390_SCHED_ATTR_MASK_EXPANDED
) != 0)
14738 if ((mask
& S390_SCHED_ATTR_MASK_GROUPALONE
) != 0)
14742 /* Prefer not cracked insns while trying to put together a
14744 if ((mask
& S390_SCHED_ATTR_MASK_CRACKED
) == 0
14745 && (mask
& S390_SCHED_ATTR_MASK_EXPANDED
) == 0
14746 && (mask
& S390_SCHED_ATTR_MASK_GROUPALONE
) == 0)
14748 if ((mask
& S390_SCHED_ATTR_MASK_ENDGROUP
) == 0)
14752 /* Prefer not cracked insns while trying to put together a
14754 if ((mask
& S390_SCHED_ATTR_MASK_CRACKED
) == 0
14755 && (mask
& S390_SCHED_ATTR_MASK_EXPANDED
) == 0
14756 && (mask
& S390_SCHED_ATTR_MASK_GROUPALONE
) == 0)
14758 /* Prefer endgroup insns in the last slot. */
14759 if ((mask
& S390_SCHED_ATTR_MASK_ENDGROUP
) != 0)
14762 case S390_SCHED_STATE_NORMAL
:
14763 /* Prefer not cracked insns if the last was not cracked. */
14764 if ((mask
& S390_SCHED_ATTR_MASK_CRACKED
) == 0
14765 && (mask
& S390_SCHED_ATTR_MASK_EXPANDED
) == 0)
14767 if ((mask
& S390_SCHED_ATTR_MASK_GROUPALONE
) != 0)
14770 case S390_SCHED_STATE_CRACKED
:
14771 /* Try to keep cracked insns together to prevent them from
14772 interrupting groups. */
14773 if ((mask
& S390_SCHED_ATTR_MASK_CRACKED
) != 0
14774 || (mask
& S390_SCHED_ATTR_MASK_EXPANDED
) != 0)
14779 if (s390_tune
>= PROCESSOR_2964_Z13
)
14782 unsigned unit_mask
, m
= 1;
14784 unit_mask
= s390_get_unit_mask (insn
, &units
);
14785 gcc_assert (units
<= MAX_SCHED_UNITS
);
14787 /* Add a score in range 0..MAX_SCHED_MIX_SCORE depending on how long
14788 ago the last insn of this unit type got scheduled. This is
14789 supposed to help providing a proper instruction mix to the
14791 for (i
= 0; i
< units
; i
++, m
<<= 1)
14793 score
+= (last_scheduled_unit_distance
[i
] * MAX_SCHED_MIX_SCORE
/
14794 MAX_SCHED_MIX_DISTANCE
);
14796 unsigned latency
= insn_default_latency (insn
);
14798 int other_side
= 1 - current_side
;
14800 /* Try to delay long-running insns when side is busy. */
14801 if (latency
> LONGRUNNING_THRESHOLD
)
14803 if (get_attr_z13_unit_fxu (insn
) && fxu_longrunning
[current_side
]
14804 && fxu_longrunning
[other_side
] <= fxu_longrunning
[current_side
])
14805 score
= MAX (0, score
- 10);
14807 if (get_attr_z13_unit_vfu (insn
) && vfu_longrunning
[current_side
]
14808 && vfu_longrunning
[other_side
] <= vfu_longrunning
[current_side
])
14809 score
= MAX (0, score
- 10);
14816 /* This function is called via hook TARGET_SCHED_REORDER before
14817 issuing one insn from list READY which contains *NREADYP entries.
14818 For target z10 it reorders load instructions to avoid early load
14819 conflicts in the floating point pipeline */
14821 s390_sched_reorder (FILE *file
, int verbose
,
14822 rtx_insn
**ready
, int *nreadyp
, int clock ATTRIBUTE_UNUSED
)
14824 if (s390_tune
== PROCESSOR_2097_Z10
14825 && reload_completed
14827 s390_z10_prevent_earlyload_conflicts (ready
, nreadyp
);
14829 if (s390_tune
>= PROCESSOR_2827_ZEC12
14830 && reload_completed
14834 int last_index
= *nreadyp
- 1;
14835 int max_index
= -1;
14836 int max_score
= -1;
14839 /* Just move the insn with the highest score to the top (the
14840 end) of the list. A full sort is not needed since a conflict
14841 in the hazard recognition cannot happen. So the top insn in
14842 the ready list will always be taken. */
14843 for (i
= last_index
; i
>= 0; i
--)
14847 if (recog_memoized (ready
[i
]) < 0)
14850 score
= s390_sched_score (ready
[i
]);
14851 if (score
> max_score
)
14858 if (max_index
!= -1)
14860 if (max_index
!= last_index
)
14862 tmp
= ready
[max_index
];
14863 ready
[max_index
] = ready
[last_index
];
14864 ready
[last_index
] = tmp
;
14868 ";;\t\tBACKEND: move insn %d to the top of list\n",
14869 INSN_UID (ready
[last_index
]));
14871 else if (verbose
> 5)
14873 ";;\t\tBACKEND: best insn %d already on top\n",
14874 INSN_UID (ready
[last_index
]));
14879 fprintf (file
, "ready list ooo attributes - sched state: %d\n",
14882 for (i
= last_index
; i
>= 0; i
--)
14884 unsigned int sched_mask
;
14885 rtx_insn
*insn
= ready
[i
];
14887 if (recog_memoized (insn
) < 0)
14890 sched_mask
= s390_get_sched_attrmask (insn
);
14891 fprintf (file
, ";;\t\tBACKEND: insn %d score: %d: ",
14893 s390_sched_score (insn
));
14894 #define PRINT_SCHED_ATTR(M, ATTR) fprintf (file, "%s ",\
14895 ((M) & sched_mask) ? #ATTR : "");
14896 PRINT_SCHED_ATTR (S390_SCHED_ATTR_MASK_CRACKED
, cracked
);
14897 PRINT_SCHED_ATTR (S390_SCHED_ATTR_MASK_EXPANDED
, expanded
);
14898 PRINT_SCHED_ATTR (S390_SCHED_ATTR_MASK_ENDGROUP
, endgroup
);
14899 PRINT_SCHED_ATTR (S390_SCHED_ATTR_MASK_GROUPALONE
, groupalone
);
14900 #undef PRINT_SCHED_ATTR
14901 if (s390_tune
>= PROCESSOR_2964_Z13
)
14903 unsigned int unit_mask
, m
= 1;
14906 unit_mask
= s390_get_unit_mask (insn
, &units
);
14907 fprintf (file
, "(units:");
14908 for (j
= 0; j
< units
; j
++, m
<<= 1)
14910 fprintf (file
, " u%d", j
);
14911 fprintf (file
, ")");
14913 fprintf (file
, "\n");
14918 return s390_issue_rate ();
14922 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
14923 the scheduler has issued INSN. It stores the last issued insn into
14924 last_scheduled_insn in order to make it available for
14925 s390_sched_reorder. */
14927 s390_sched_variable_issue (FILE *file
, int verbose
, rtx_insn
*insn
, int more
)
14929 last_scheduled_insn
= insn
;
14931 bool starts_group
= false;
14933 if (s390_tune
>= PROCESSOR_2827_ZEC12
14934 && reload_completed
14935 && recog_memoized (insn
) >= 0)
14937 unsigned int mask
= s390_get_sched_attrmask (insn
);
14939 if ((mask
& S390_SCHED_ATTR_MASK_CRACKED
) != 0
14940 || (mask
& S390_SCHED_ATTR_MASK_EXPANDED
) != 0
14941 || (mask
& S390_SCHED_ATTR_MASK_GROUPALONE
) != 0)
14942 starts_group
= true;
14944 if ((mask
& S390_SCHED_ATTR_MASK_CRACKED
) != 0
14945 || (mask
& S390_SCHED_ATTR_MASK_EXPANDED
) != 0)
14946 s390_sched_state
= S390_SCHED_STATE_CRACKED
;
14947 else if ((mask
& S390_SCHED_ATTR_MASK_ENDGROUP
) != 0
14948 || (mask
& S390_SCHED_ATTR_MASK_GROUPALONE
) != 0)
14949 s390_sched_state
= S390_SCHED_STATE_NORMAL
;
14952 /* Only normal insns are left (mask == 0). */
14953 switch (s390_sched_state
)
14956 starts_group
= true;
14960 s390_sched_state
++;
14962 case S390_SCHED_STATE_NORMAL
:
14963 starts_group
= true;
14964 s390_sched_state
= 1;
14966 case S390_SCHED_STATE_CRACKED
:
14967 s390_sched_state
= S390_SCHED_STATE_NORMAL
;
14972 if (s390_tune
>= PROCESSOR_2964_Z13
)
14975 unsigned unit_mask
, m
= 1;
14977 unit_mask
= s390_get_unit_mask (insn
, &units
);
14978 gcc_assert (units
<= MAX_SCHED_UNITS
);
14980 for (i
= 0; i
< units
; i
++, m
<<= 1)
14982 last_scheduled_unit_distance
[i
] = 0;
14983 else if (last_scheduled_unit_distance
[i
] < MAX_SCHED_MIX_DISTANCE
)
14984 last_scheduled_unit_distance
[i
]++;
14987 /* If this insn started a new group, the side flipped. */
14989 current_side
= current_side
? 0 : 1;
14991 for (int i
= 0; i
< 2; i
++)
14993 if (fxu_longrunning
[i
] >= 1)
14994 fxu_longrunning
[i
] -= 1;
14995 if (vfu_longrunning
[i
] >= 1)
14996 vfu_longrunning
[i
] -= 1;
14999 unsigned latency
= insn_default_latency (insn
);
15000 if (latency
> LONGRUNNING_THRESHOLD
)
15002 if (get_attr_z13_unit_fxu (insn
))
15003 fxu_longrunning
[current_side
] = latency
* LATENCY_FACTOR
;
15005 vfu_longrunning
[current_side
] = latency
* LATENCY_FACTOR
;
15010 unsigned int sched_mask
;
15012 sched_mask
= s390_get_sched_attrmask (insn
);
15014 fprintf (file
, ";;\t\tBACKEND: insn %d: ", INSN_UID (insn
));
15015 #define PRINT_SCHED_ATTR(M, ATTR) fprintf (file, "%s ", ((M) & sched_mask) ? #ATTR : "");
15016 PRINT_SCHED_ATTR (S390_SCHED_ATTR_MASK_CRACKED
, cracked
);
15017 PRINT_SCHED_ATTR (S390_SCHED_ATTR_MASK_EXPANDED
, expanded
);
15018 PRINT_SCHED_ATTR (S390_SCHED_ATTR_MASK_ENDGROUP
, endgroup
);
15019 PRINT_SCHED_ATTR (S390_SCHED_ATTR_MASK_GROUPALONE
, groupalone
);
15020 #undef PRINT_SCHED_ATTR
15022 if (s390_tune
>= PROCESSOR_2964_Z13
)
15024 unsigned int unit_mask
, m
= 1;
15027 unit_mask
= s390_get_unit_mask (insn
, &units
);
15028 fprintf (file
, "(units:");
15029 for (j
= 0; j
< units
; j
++, m
<<= 1)
15031 fprintf (file
, " %d", j
);
15032 fprintf (file
, ")");
15034 fprintf (file
, " sched state: %d\n", s390_sched_state
);
15036 if (s390_tune
>= PROCESSOR_2964_Z13
)
15040 s390_get_unit_mask (insn
, &units
);
15042 fprintf (file
, ";;\t\tBACKEND: units unused for: ");
15043 for (j
= 0; j
< units
; j
++)
15044 fprintf (file
, "%d:%d ", j
, last_scheduled_unit_distance
[j
]);
15045 fprintf (file
, "\n");
15050 if (GET_CODE (PATTERN (insn
)) != USE
15051 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
15058 s390_sched_init (FILE *file ATTRIBUTE_UNUSED
,
15059 int verbose ATTRIBUTE_UNUSED
,
15060 int max_ready ATTRIBUTE_UNUSED
)
15062 last_scheduled_insn
= NULL
;
15063 memset (last_scheduled_unit_distance
, 0, MAX_SCHED_UNITS
* sizeof (int));
15065 /* If the next basic block is most likely entered via a fallthru edge
15066 we keep the last sched state. Otherwise we start a new group.
15067 The scheduler traverses basic blocks in "instruction stream" ordering
15068 so if we see a fallthru edge here, s390_sched_state will be of its
15071 current_sched_info->prev_head is the insn before the first insn of the
15072 block of insns to be scheduled.
15074 rtx_insn
*insn
= current_sched_info
->prev_head
15075 ? NEXT_INSN (current_sched_info
->prev_head
) : NULL
;
15076 basic_block bb
= insn
? BLOCK_FOR_INSN (insn
) : NULL
;
15077 if (s390_tune
< PROCESSOR_2964_Z13
|| !s390_bb_fallthru_entry_likely (bb
))
15078 s390_sched_state
= 0;
15081 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
15082 a new number struct loop *loop should be unrolled if tuned for cpus with
15083 a built-in stride prefetcher.
15084 The loop is analyzed for memory accesses by calling check_dpu for
15085 each rtx of the loop. Depending on the loop_depth and the amount of
15086 memory accesses a new number <=nunroll is returned to improve the
15087 behavior of the hardware prefetch unit. */
15089 s390_loop_unroll_adjust (unsigned nunroll
, struct loop
*loop
)
15094 unsigned mem_count
= 0;
15096 if (s390_tune
< PROCESSOR_2097_Z10
)
15099 /* Count the number of memory references within the loop body. */
15100 bbs
= get_loop_body (loop
);
15101 subrtx_iterator::array_type array
;
15102 for (i
= 0; i
< loop
->num_nodes
; i
++)
15103 FOR_BB_INSNS (bbs
[i
], insn
)
15104 if (INSN_P (insn
) && INSN_CODE (insn
) != -1)
15105 FOR_EACH_SUBRTX (iter
, array
, PATTERN (insn
), NONCONST
)
15110 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
15111 if (mem_count
== 0)
15114 switch (loop_depth(loop
))
15117 return MIN (nunroll
, 28 / mem_count
);
15119 return MIN (nunroll
, 22 / mem_count
);
15121 return MIN (nunroll
, 16 / mem_count
);
15125 /* Restore the current options. This is a hook function and also called
15129 s390_function_specific_restore (struct gcc_options
*opts
,
15130 struct cl_target_option
*ptr ATTRIBUTE_UNUSED
)
15132 opts
->x_s390_cost_pointer
= (long)processor_table
[opts
->x_s390_tune
].cost
;
15136 s390_option_override_internal (bool main_args_p
,
15137 struct gcc_options
*opts
,
15138 const struct gcc_options
*opts_set
)
15140 const char *prefix
;
15141 const char *suffix
;
15143 /* Set up prefix/suffix so the error messages refer to either the command
15144 line argument, or the attribute(target). */
15152 prefix
= "option(\"";
15157 /* Architecture mode defaults according to ABI. */
15158 if (!(opts_set
->x_target_flags
& MASK_ZARCH
))
15161 opts
->x_target_flags
|= MASK_ZARCH
;
15163 opts
->x_target_flags
&= ~MASK_ZARCH
;
15166 /* Set the march default in case it hasn't been specified on cmdline. */
15167 if (!opts_set
->x_s390_arch
)
15168 opts
->x_s390_arch
= PROCESSOR_2064_Z900
;
15169 else if (opts
->x_s390_arch
== PROCESSOR_9672_G5
15170 || opts
->x_s390_arch
== PROCESSOR_9672_G6
)
15171 warning (OPT_Wdeprecated
, "%sarch=%s%s is deprecated and will be removed "
15172 "in future releases; use at least %sarch=z900%s",
15173 prefix
, opts
->x_s390_arch
== PROCESSOR_9672_G5
? "g5" : "g6",
15174 suffix
, prefix
, suffix
);
15176 opts
->x_s390_arch_flags
= processor_flags_table
[(int) opts
->x_s390_arch
];
15178 /* Determine processor to tune for. */
15179 if (!opts_set
->x_s390_tune
)
15180 opts
->x_s390_tune
= opts
->x_s390_arch
;
15181 else if (opts
->x_s390_tune
== PROCESSOR_9672_G5
15182 || opts
->x_s390_tune
== PROCESSOR_9672_G6
)
15183 warning (OPT_Wdeprecated
, "%stune=%s%s is deprecated and will be removed "
15184 "in future releases; use at least %stune=z900%s",
15185 prefix
, opts
->x_s390_tune
== PROCESSOR_9672_G5
? "g5" : "g6",
15186 suffix
, prefix
, suffix
);
15188 opts
->x_s390_tune_flags
= processor_flags_table
[opts
->x_s390_tune
];
15190 /* Sanity checks. */
15191 if (opts
->x_s390_arch
== PROCESSOR_NATIVE
15192 || opts
->x_s390_tune
== PROCESSOR_NATIVE
)
15193 gcc_unreachable ();
15194 if (TARGET_ZARCH_P (opts
->x_target_flags
) && !TARGET_CPU_ZARCH_P (opts
))
15195 error ("z/Architecture mode not supported on %s",
15196 processor_table
[(int)opts
->x_s390_arch
].name
);
15197 if (TARGET_64BIT
&& !TARGET_ZARCH_P (opts
->x_target_flags
))
15198 error ("64-bit ABI not supported in ESA/390 mode");
15200 /* Enable hardware transactions if available and not explicitly
15201 disabled by user. E.g. with -m31 -march=zEC12 -mzarch */
15202 if (!TARGET_OPT_HTM_P (opts_set
->x_target_flags
))
15204 if (TARGET_CPU_HTM_P (opts
) && TARGET_ZARCH_P (opts
->x_target_flags
))
15205 opts
->x_target_flags
|= MASK_OPT_HTM
;
15207 opts
->x_target_flags
&= ~MASK_OPT_HTM
;
15210 if (TARGET_OPT_VX_P (opts_set
->x_target_flags
))
15212 if (TARGET_OPT_VX_P (opts
->x_target_flags
))
15214 if (!TARGET_CPU_VX_P (opts
))
15215 error ("hardware vector support not available on %s",
15216 processor_table
[(int)opts
->x_s390_arch
].name
);
15217 if (TARGET_SOFT_FLOAT_P (opts
->x_target_flags
))
15218 error ("hardware vector support not available with -msoft-float");
15223 if (TARGET_CPU_VX_P (opts
))
15224 /* Enable vector support if available and not explicitly disabled
15225 by user. E.g. with -m31 -march=z13 -mzarch */
15226 opts
->x_target_flags
|= MASK_OPT_VX
;
15228 opts
->x_target_flags
&= ~MASK_OPT_VX
;
15231 /* Use hardware DFP if available and not explicitly disabled by
15232 user. E.g. with -m31 -march=z10 -mzarch */
15233 if (!TARGET_HARD_DFP_P (opts_set
->x_target_flags
))
15235 if (TARGET_DFP_P (opts
))
15236 opts
->x_target_flags
|= MASK_HARD_DFP
;
15238 opts
->x_target_flags
&= ~MASK_HARD_DFP
;
15241 if (TARGET_HARD_DFP_P (opts
->x_target_flags
) && !TARGET_DFP_P (opts
))
15243 if (TARGET_HARD_DFP_P (opts_set
->x_target_flags
))
15245 if (!TARGET_CPU_DFP_P (opts
))
15246 error ("hardware decimal floating point instructions"
15247 " not available on %s",
15248 processor_table
[(int)opts
->x_s390_arch
].name
);
15249 if (!TARGET_ZARCH_P (opts
->x_target_flags
))
15250 error ("hardware decimal floating point instructions"
15251 " not available in ESA/390 mode");
15254 opts
->x_target_flags
&= ~MASK_HARD_DFP
;
15257 if (TARGET_SOFT_FLOAT_P (opts_set
->x_target_flags
)
15258 && TARGET_SOFT_FLOAT_P (opts
->x_target_flags
))
15260 if (TARGET_HARD_DFP_P (opts_set
->x_target_flags
)
15261 && TARGET_HARD_DFP_P (opts
->x_target_flags
))
15262 error ("-mhard-dfp can%'t be used in conjunction with -msoft-float");
15264 opts
->x_target_flags
&= ~MASK_HARD_DFP
;
15267 if (TARGET_BACKCHAIN_P (opts
->x_target_flags
)
15268 && TARGET_PACKED_STACK_P (opts
->x_target_flags
)
15269 && TARGET_HARD_FLOAT_P (opts
->x_target_flags
))
15270 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
15273 if (opts
->x_s390_stack_size
)
15275 if (opts
->x_s390_stack_guard
>= opts
->x_s390_stack_size
)
15276 error ("stack size must be greater than the stack guard value");
15277 else if (opts
->x_s390_stack_size
> 1 << 16)
15278 error ("stack size must not be greater than 64k");
15280 else if (opts
->x_s390_stack_guard
)
15281 error ("-mstack-guard implies use of -mstack-size");
15283 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
15284 if (!TARGET_LONG_DOUBLE_128_P (opts_set
->x_target_flags
))
15285 opts
->x_target_flags
|= MASK_LONG_DOUBLE_128
;
15288 if (opts
->x_s390_tune
>= PROCESSOR_2097_Z10
)
15290 maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS
, 100,
15291 opts
->x_param_values
,
15292 opts_set
->x_param_values
);
15293 maybe_set_param_value (PARAM_MAX_UNROLL_TIMES
, 32,
15294 opts
->x_param_values
,
15295 opts_set
->x_param_values
);
15296 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS
, 2000,
15297 opts
->x_param_values
,
15298 opts_set
->x_param_values
);
15299 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES
, 64,
15300 opts
->x_param_values
,
15301 opts_set
->x_param_values
);
15304 maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH
, 256,
15305 opts
->x_param_values
,
15306 opts_set
->x_param_values
);
15307 /* values for loop prefetching */
15308 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
, 256,
15309 opts
->x_param_values
,
15310 opts_set
->x_param_values
);
15311 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, 128,
15312 opts
->x_param_values
,
15313 opts_set
->x_param_values
);
15314 /* s390 has more than 2 levels and the size is much larger. Since
15315 we are always running virtualized assume that we only get a small
15316 part of the caches above l1. */
15317 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, 1500,
15318 opts
->x_param_values
,
15319 opts_set
->x_param_values
);
15320 maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO
, 2,
15321 opts
->x_param_values
,
15322 opts_set
->x_param_values
);
15323 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
, 6,
15324 opts
->x_param_values
,
15325 opts_set
->x_param_values
);
15327 /* Use the alternative scheduling-pressure algorithm by default. */
15328 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM
, 2,
15329 opts
->x_param_values
,
15330 opts_set
->x_param_values
);
15332 maybe_set_param_value (PARAM_MIN_VECT_LOOP_BOUND
, 2,
15333 opts
->x_param_values
,
15334 opts_set
->x_param_values
);
15336 /* Call target specific restore function to do post-init work. At the moment,
15337 this just sets opts->x_s390_cost_pointer. */
15338 s390_function_specific_restore (opts
, NULL
);
15342 s390_option_override (void)
15345 cl_deferred_option
*opt
;
15346 vec
<cl_deferred_option
> *v
=
15347 (vec
<cl_deferred_option
> *) s390_deferred_options
;
15350 FOR_EACH_VEC_ELT (*v
, i
, opt
)
15352 switch (opt
->opt_index
)
15354 case OPT_mhotpatch_
:
15361 strncpy (s
, opt
->arg
, 256);
15363 t
= strchr (s
, ',');
15368 val1
= integral_argument (s
);
15369 val2
= integral_argument (t
);
15376 if (val1
== -1 || val2
== -1)
15378 /* argument is not a plain number */
15379 error ("arguments to %qs should be non-negative integers",
15383 else if (val1
> s390_hotpatch_hw_max
15384 || val2
> s390_hotpatch_hw_max
)
15386 error ("argument to %qs is too large (max. %d)",
15387 "-mhotpatch=n,m", s390_hotpatch_hw_max
);
15390 s390_hotpatch_hw_before_label
= val1
;
15391 s390_hotpatch_hw_after_label
= val2
;
15395 gcc_unreachable ();
15399 /* Set up function hooks. */
15400 init_machine_status
= s390_init_machine_status
;
15402 s390_option_override_internal (true, &global_options
, &global_options_set
);
15404 /* Save the initial options in case the user does function specific
15406 target_option_default_node
= build_target_option_node (&global_options
);
15407 target_option_current_node
= target_option_default_node
;
15409 /* This cannot reside in s390_option_optimization_table since HAVE_prefetch
15410 requires the arch flags to be evaluated already. Since prefetching
15411 is beneficial on s390, we enable it if available. */
15412 if (flag_prefetch_loop_arrays
< 0 && HAVE_prefetch
&& optimize
>= 3)
15413 flag_prefetch_loop_arrays
= 1;
15415 if (!s390_pic_data_is_text_relative
&& !flag_pic
)
15416 error ("-mno-pic-data-is-text-relative cannot be used without -fpic/-fPIC");
15420 /* Don't emit DWARF3/4 unless specifically selected. The TPF
15421 debuggers do not yet support DWARF 3/4. */
15422 if (!global_options_set
.x_dwarf_strict
)
15424 if (!global_options_set
.x_dwarf_version
)
15428 /* Register a target-specific optimization-and-lowering pass
15429 to run immediately before prologue and epilogue generation.
15431 Registering the pass must be done at start up. It's
15432 convenient to do it here. */
15433 opt_pass
*new_pass
= new pass_s390_early_mach (g
);
15434 struct register_pass_info insert_pass_s390_early_mach
=
15436 new_pass
, /* pass */
15437 "pro_and_epilogue", /* reference_pass_name */
15438 1, /* ref_pass_instance_number */
15439 PASS_POS_INSERT_BEFORE
/* po_op */
15441 register_pass (&insert_pass_s390_early_mach
);
15444 #if S390_USE_TARGET_ATTRIBUTE
15445 /* Inner function to process the attribute((target(...))), take an argument and
15446 set the current options from the argument. If we have a list, recursively go
15450 s390_valid_target_attribute_inner_p (tree args
,
15451 struct gcc_options
*opts
,
15452 struct gcc_options
*new_opts_set
,
15458 #define S390_ATTRIB(S,O,A) { S, sizeof (S)-1, O, A, 0 }
15459 #define S390_PRAGMA(S,O,A) { S, sizeof (S)-1, O, A, 1 }
15460 static const struct
15462 const char *string
;
15466 int only_as_pragma
;
15469 S390_ATTRIB ("arch=", OPT_march_
, 1),
15470 S390_ATTRIB ("tune=", OPT_mtune_
, 1),
15471 /* uinteger options */
15472 S390_ATTRIB ("stack-guard=", OPT_mstack_guard_
, 1),
15473 S390_ATTRIB ("stack-size=", OPT_mstack_size_
, 1),
15474 S390_ATTRIB ("branch-cost=", OPT_mbranch_cost_
, 1),
15475 S390_ATTRIB ("warn-framesize=", OPT_mwarn_framesize_
, 1),
15477 S390_ATTRIB ("backchain", OPT_mbackchain
, 0),
15478 S390_ATTRIB ("hard-dfp", OPT_mhard_dfp
, 0),
15479 S390_ATTRIB ("hard-float", OPT_mhard_float
, 0),
15480 S390_ATTRIB ("htm", OPT_mhtm
, 0),
15481 S390_ATTRIB ("vx", OPT_mvx
, 0),
15482 S390_ATTRIB ("packed-stack", OPT_mpacked_stack
, 0),
15483 S390_ATTRIB ("small-exec", OPT_msmall_exec
, 0),
15484 S390_ATTRIB ("soft-float", OPT_msoft_float
, 0),
15485 S390_ATTRIB ("mvcle", OPT_mmvcle
, 0),
15486 S390_PRAGMA ("zvector", OPT_mzvector
, 0),
15487 /* boolean options */
15488 S390_ATTRIB ("warn-dynamicstack", OPT_mwarn_dynamicstack
, 0),
15493 /* If this is a list, recurse to get the options. */
15494 if (TREE_CODE (args
) == TREE_LIST
)
15497 int num_pragma_values
;
15500 /* Note: attribs.c:decl_attributes prepends the values from
15501 current_target_pragma to the list of target attributes. To determine
15502 whether we're looking at a value of the attribute or the pragma we
15503 assume that the first [list_length (current_target_pragma)] values in
15504 the list are the values from the pragma. */
15505 num_pragma_values
= (!force_pragma
&& current_target_pragma
!= NULL
)
15506 ? list_length (current_target_pragma
) : 0;
15507 for (i
= 0; args
; args
= TREE_CHAIN (args
), i
++)
15511 is_pragma
= (force_pragma
|| i
< num_pragma_values
);
15512 if (TREE_VALUE (args
)
15513 && !s390_valid_target_attribute_inner_p (TREE_VALUE (args
),
15514 opts
, new_opts_set
,
15523 else if (TREE_CODE (args
) != STRING_CST
)
15525 error ("attribute %<target%> argument not a string");
15529 /* Handle multiple arguments separated by commas. */
15530 next_optstr
= ASTRDUP (TREE_STRING_POINTER (args
));
15532 while (next_optstr
&& *next_optstr
!= '\0')
15534 char *p
= next_optstr
;
15536 char *comma
= strchr (next_optstr
, ',');
15537 size_t len
, opt_len
;
15543 enum cl_var_type var_type
;
15549 len
= comma
- next_optstr
;
15550 next_optstr
= comma
+ 1;
15555 next_optstr
= NULL
;
15558 /* Recognize no-xxx. */
15559 if (len
> 3 && p
[0] == 'n' && p
[1] == 'o' && p
[2] == '-')
15568 /* Find the option. */
15571 for (i
= 0; i
< ARRAY_SIZE (attrs
); i
++)
15573 opt_len
= attrs
[i
].len
;
15574 if (ch
== attrs
[i
].string
[0]
15575 && ((attrs
[i
].has_arg
) ? len
> opt_len
: len
== opt_len
)
15576 && memcmp (p
, attrs
[i
].string
, opt_len
) == 0)
15578 opt
= attrs
[i
].opt
;
15579 if (!opt_set_p
&& cl_options
[opt
].cl_reject_negative
)
15581 mask
= cl_options
[opt
].var_value
;
15582 var_type
= cl_options
[opt
].var_type
;
15588 /* Process the option. */
15591 error ("attribute(target(\"%s\")) is unknown", orig_p
);
15594 else if (attrs
[i
].only_as_pragma
&& !force_pragma
)
15596 /* Value is not allowed for the target attribute. */
15597 error ("value %qs is not supported by attribute %<target%>",
15602 else if (var_type
== CLVC_BIT_SET
|| var_type
== CLVC_BIT_CLEAR
)
15604 if (var_type
== CLVC_BIT_CLEAR
)
15605 opt_set_p
= !opt_set_p
;
15608 opts
->x_target_flags
|= mask
;
15610 opts
->x_target_flags
&= ~mask
;
15611 new_opts_set
->x_target_flags
|= mask
;
15614 else if (cl_options
[opt
].var_type
== CLVC_BOOLEAN
)
15618 if (cl_options
[opt
].cl_uinteger
)
15620 /* Unsigned integer argument. Code based on the function
15621 decode_cmdline_option () in opts-common.c. */
15622 value
= integral_argument (p
+ opt_len
);
15625 value
= (opt_set_p
) ? 1 : 0;
15629 struct cl_decoded_option decoded
;
15631 /* Value range check; only implemented for numeric and boolean
15632 options at the moment. */
15633 generate_option (opt
, NULL
, value
, CL_TARGET
, &decoded
);
15634 s390_handle_option (opts
, new_opts_set
, &decoded
, input_location
);
15635 set_option (opts
, new_opts_set
, opt
, value
,
15636 p
+ opt_len
, DK_UNSPECIFIED
, input_location
,
15641 error ("attribute(target(\"%s\")) is unknown", orig_p
);
15646 else if (cl_options
[opt
].var_type
== CLVC_ENUM
)
15651 arg_ok
= opt_enum_arg_to_value (opt
, p
+ opt_len
, &value
, CL_TARGET
);
15653 set_option (opts
, new_opts_set
, opt
, value
,
15654 p
+ opt_len
, DK_UNSPECIFIED
, input_location
,
15658 error ("attribute(target(\"%s\")) is unknown", orig_p
);
15664 gcc_unreachable ();
15669 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
15672 s390_valid_target_attribute_tree (tree args
,
15673 struct gcc_options
*opts
,
15674 const struct gcc_options
*opts_set
,
15677 tree t
= NULL_TREE
;
15678 struct gcc_options new_opts_set
;
15680 memset (&new_opts_set
, 0, sizeof (new_opts_set
));
15682 /* Process each of the options on the chain. */
15683 if (! s390_valid_target_attribute_inner_p (args
, opts
, &new_opts_set
,
15685 return error_mark_node
;
15687 /* If some option was set (even if it has not changed), rerun
15688 s390_option_override_internal, and then save the options away. */
15689 if (new_opts_set
.x_target_flags
15690 || new_opts_set
.x_s390_arch
15691 || new_opts_set
.x_s390_tune
15692 || new_opts_set
.x_s390_stack_guard
15693 || new_opts_set
.x_s390_stack_size
15694 || new_opts_set
.x_s390_branch_cost
15695 || new_opts_set
.x_s390_warn_framesize
15696 || new_opts_set
.x_s390_warn_dynamicstack_p
)
15698 const unsigned char *src
= (const unsigned char *)opts_set
;
15699 unsigned char *dest
= (unsigned char *)&new_opts_set
;
15702 /* Merge the original option flags into the new ones. */
15703 for (i
= 0; i
< sizeof(*opts_set
); i
++)
15706 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
15707 s390_option_override_internal (false, opts
, &new_opts_set
);
15708 /* Save the current options unless we are validating options for
15710 t
= build_target_option_node (opts
);
15715 /* Hook to validate attribute((target("string"))). */
15718 s390_valid_target_attribute_p (tree fndecl
,
15719 tree
ARG_UNUSED (name
),
15721 int ARG_UNUSED (flags
))
15723 struct gcc_options func_options
;
15724 tree new_target
, new_optimize
;
15727 /* attribute((target("default"))) does nothing, beyond
15728 affecting multi-versioning. */
15729 if (TREE_VALUE (args
)
15730 && TREE_CODE (TREE_VALUE (args
)) == STRING_CST
15731 && TREE_CHAIN (args
) == NULL_TREE
15732 && strcmp (TREE_STRING_POINTER (TREE_VALUE (args
)), "default") == 0)
15735 tree old_optimize
= build_optimization_node (&global_options
);
15737 /* Get the optimization options of the current function. */
15738 tree func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
15740 if (!func_optimize
)
15741 func_optimize
= old_optimize
;
15743 /* Init func_options. */
15744 memset (&func_options
, 0, sizeof (func_options
));
15745 init_options_struct (&func_options
, NULL
);
15746 lang_hooks
.init_options_struct (&func_options
);
15748 cl_optimization_restore (&func_options
, TREE_OPTIMIZATION (func_optimize
));
15750 /* Initialize func_options to the default before its target options can
15752 cl_target_option_restore (&func_options
,
15753 TREE_TARGET_OPTION (target_option_default_node
));
15755 new_target
= s390_valid_target_attribute_tree (args
, &func_options
,
15756 &global_options_set
,
15758 current_target_pragma
));
15759 new_optimize
= build_optimization_node (&func_options
);
15760 if (new_target
== error_mark_node
)
15762 else if (fndecl
&& new_target
)
15764 DECL_FUNCTION_SPECIFIC_TARGET (fndecl
) = new_target
;
15765 if (old_optimize
!= new_optimize
)
15766 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
) = new_optimize
;
15771 /* Hook to determine if one function can safely inline another. */
15774 s390_can_inline_p (tree caller
, tree callee
)
15776 tree caller_tree
= DECL_FUNCTION_SPECIFIC_TARGET (caller
);
15777 tree callee_tree
= DECL_FUNCTION_SPECIFIC_TARGET (callee
);
15780 callee_tree
= target_option_default_node
;
15782 caller_tree
= target_option_default_node
;
15783 if (callee_tree
== caller_tree
)
15786 struct cl_target_option
*caller_opts
= TREE_TARGET_OPTION (caller_tree
);
15787 struct cl_target_option
*callee_opts
= TREE_TARGET_OPTION (callee_tree
);
15790 if ((caller_opts
->x_target_flags
& ~(MASK_SOFT_FLOAT
| MASK_HARD_DFP
))
15791 != (callee_opts
->x_target_flags
& ~(MASK_SOFT_FLOAT
| MASK_HARD_DFP
)))
15794 /* Don't inline functions to be compiled for a more recent arch into a
15795 function for an older arch. */
15796 else if (caller_opts
->x_s390_arch
< callee_opts
->x_s390_arch
)
15799 /* Inlining a hard float function into a soft float function is only
15800 allowed if the hard float function doesn't actually make use of
15803 We are called from FEs for multi-versioning call optimization, so
15804 beware of ipa_fn_summaries not available. */
15805 else if (((TARGET_SOFT_FLOAT_P (caller_opts
->x_target_flags
)
15806 && !TARGET_SOFT_FLOAT_P (callee_opts
->x_target_flags
))
15807 || (!TARGET_HARD_DFP_P (caller_opts
->x_target_flags
)
15808 && TARGET_HARD_DFP_P (callee_opts
->x_target_flags
)))
15809 && (! ipa_fn_summaries
15810 || ipa_fn_summaries
->get
15811 (cgraph_node::get (callee
))->fp_expressions
))
15817 /* Restore targets globals from NEW_TREE and invalidate s390_previous_fndecl
15821 s390_activate_target_options (tree new_tree
)
15823 cl_target_option_restore (&global_options
, TREE_TARGET_OPTION (new_tree
));
15824 if (TREE_TARGET_GLOBALS (new_tree
))
15825 restore_target_globals (TREE_TARGET_GLOBALS (new_tree
));
15826 else if (new_tree
== target_option_default_node
)
15827 restore_target_globals (&default_target_globals
);
15829 TREE_TARGET_GLOBALS (new_tree
) = save_target_globals_default_opts ();
15830 s390_previous_fndecl
= NULL_TREE
;
15833 /* Establish appropriate back-end context for processing the function
15834 FNDECL. The argument might be NULL to indicate processing at top
15835 level, outside of any function scope. */
15837 s390_set_current_function (tree fndecl
)
15839 /* Only change the context if the function changes. This hook is called
15840 several times in the course of compiling a function, and we don't want to
15841 slow things down too much or call target_reinit when it isn't safe. */
15842 if (fndecl
== s390_previous_fndecl
)
15846 if (s390_previous_fndecl
== NULL_TREE
)
15847 old_tree
= target_option_current_node
;
15848 else if (DECL_FUNCTION_SPECIFIC_TARGET (s390_previous_fndecl
))
15849 old_tree
= DECL_FUNCTION_SPECIFIC_TARGET (s390_previous_fndecl
);
15851 old_tree
= target_option_default_node
;
15853 if (fndecl
== NULL_TREE
)
15855 if (old_tree
!= target_option_current_node
)
15856 s390_activate_target_options (target_option_current_node
);
15860 tree new_tree
= DECL_FUNCTION_SPECIFIC_TARGET (fndecl
);
15861 if (new_tree
== NULL_TREE
)
15862 new_tree
= target_option_default_node
;
15864 if (old_tree
!= new_tree
)
15865 s390_activate_target_options (new_tree
);
15866 s390_previous_fndecl
= fndecl
;
15870 /* Implement TARGET_USE_BY_PIECES_INFRASTRUCTURE_P. */
15873 s390_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size
,
15874 unsigned int align ATTRIBUTE_UNUSED
,
15875 enum by_pieces_operation op ATTRIBUTE_UNUSED
,
15876 bool speed_p ATTRIBUTE_UNUSED
)
15878 return (size
== 1 || size
== 2
15879 || size
== 4 || (TARGET_ZARCH
&& size
== 8));
15882 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
15885 s390_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
15887 tree sfpc
= s390_builtin_decls
[S390_BUILTIN_s390_sfpc
];
15888 tree efpc
= s390_builtin_decls
[S390_BUILTIN_s390_efpc
];
15889 tree call_efpc
= build_call_expr (efpc
, 0);
15890 tree fenv_var
= create_tmp_var_raw (unsigned_type_node
);
15892 #define FPC_EXCEPTION_MASK HOST_WIDE_INT_UC (0xf8000000)
15893 #define FPC_FLAGS_MASK HOST_WIDE_INT_UC (0x00f80000)
15894 #define FPC_DXC_MASK HOST_WIDE_INT_UC (0x0000ff00)
15895 #define FPC_EXCEPTION_MASK_SHIFT HOST_WIDE_INT_UC (24)
15896 #define FPC_FLAGS_SHIFT HOST_WIDE_INT_UC (16)
15897 #define FPC_DXC_SHIFT HOST_WIDE_INT_UC (8)
15899 /* Generates the equivalent of feholdexcept (&fenv_var)
15901 fenv_var = __builtin_s390_efpc ();
15902 __builtin_s390_sfpc (fenv_var & mask) */
15903 tree old_fpc
= build2 (MODIFY_EXPR
, unsigned_type_node
, fenv_var
, call_efpc
);
15905 build2 (BIT_AND_EXPR
, unsigned_type_node
, fenv_var
,
15906 build_int_cst (unsigned_type_node
,
15907 ~(FPC_DXC_MASK
| FPC_FLAGS_MASK
|
15908 FPC_EXCEPTION_MASK
)));
15909 tree set_new_fpc
= build_call_expr (sfpc
, 1, new_fpc
);
15910 *hold
= build2 (COMPOUND_EXPR
, void_type_node
, old_fpc
, set_new_fpc
);
15912 /* Generates the equivalent of feclearexcept (FE_ALL_EXCEPT)
15914 __builtin_s390_sfpc (__builtin_s390_efpc () & mask) */
15915 new_fpc
= build2 (BIT_AND_EXPR
, unsigned_type_node
, call_efpc
,
15916 build_int_cst (unsigned_type_node
,
15917 ~(FPC_DXC_MASK
| FPC_FLAGS_MASK
)));
15918 *clear
= build_call_expr (sfpc
, 1, new_fpc
);
15920 /* Generates the equivalent of feupdateenv (fenv_var)
15922 old_fpc = __builtin_s390_efpc ();
15923 __builtin_s390_sfpc (fenv_var);
15924 __atomic_feraiseexcept ((old_fpc & FPC_FLAGS_MASK) >> FPC_FLAGS_SHIFT); */
15926 old_fpc
= create_tmp_var_raw (unsigned_type_node
);
15927 tree store_old_fpc
= build2 (MODIFY_EXPR
, void_type_node
,
15928 old_fpc
, call_efpc
);
15930 set_new_fpc
= build_call_expr (sfpc
, 1, fenv_var
);
15932 tree raise_old_except
= build2 (BIT_AND_EXPR
, unsigned_type_node
, old_fpc
,
15933 build_int_cst (unsigned_type_node
,
15935 raise_old_except
= build2 (RSHIFT_EXPR
, unsigned_type_node
, raise_old_except
,
15936 build_int_cst (unsigned_type_node
,
15938 tree atomic_feraiseexcept
15939 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT
);
15940 raise_old_except
= build_call_expr (atomic_feraiseexcept
,
15941 1, raise_old_except
);
15943 *update
= build2 (COMPOUND_EXPR
, void_type_node
,
15944 build2 (COMPOUND_EXPR
, void_type_node
,
15945 store_old_fpc
, set_new_fpc
),
15948 #undef FPC_EXCEPTION_MASK
15949 #undef FPC_FLAGS_MASK
15950 #undef FPC_DXC_MASK
15951 #undef FPC_EXCEPTION_MASK_SHIFT
15952 #undef FPC_FLAGS_SHIFT
15953 #undef FPC_DXC_SHIFT
15956 /* Return the vector mode to be used for inner mode MODE when doing
15958 static machine_mode
15959 s390_preferred_simd_mode (scalar_mode mode
)
15987 /* Our hardware does not require vectors to be strictly aligned. */
15989 s390_support_vector_misalignment (machine_mode mode ATTRIBUTE_UNUSED
,
15990 const_tree type ATTRIBUTE_UNUSED
,
15991 int misalignment ATTRIBUTE_UNUSED
,
15992 bool is_packed ATTRIBUTE_UNUSED
)
15997 return default_builtin_support_vector_misalignment (mode
, type
, misalignment
,
16001 /* The vector ABI requires vector types to be aligned on an 8 byte
16002 boundary (our stack alignment). However, we allow this to be
16003 overriden by the user, while this definitely breaks the ABI. */
16004 static HOST_WIDE_INT
16005 s390_vector_alignment (const_tree type
)
16007 if (!TARGET_VX_ABI
)
16008 return default_vector_alignment (type
);
16010 if (TYPE_USER_ALIGN (type
))
16011 return TYPE_ALIGN (type
);
16013 return MIN (64, tree_to_shwi (TYPE_SIZE (type
)));
16016 /* Implement TARGET_CONSTANT_ALIGNMENT. Alignment on even addresses for
16017 LARL instruction. */
16019 static HOST_WIDE_INT
16020 s390_constant_alignment (const_tree
, HOST_WIDE_INT align
)
16022 return MAX (align
, 16);
16025 #ifdef HAVE_AS_MACHINE_MACHINEMODE
16026 /* Implement TARGET_ASM_FILE_START. */
16028 s390_asm_file_start (void)
16030 default_file_start ();
16031 s390_asm_output_machine_for_arch (asm_out_file
);
16035 /* Implement TARGET_ASM_FILE_END. */
16037 s390_asm_file_end (void)
16039 #ifdef HAVE_AS_GNU_ATTRIBUTE
16040 varpool_node
*vnode
;
16041 cgraph_node
*cnode
;
16043 FOR_EACH_VARIABLE (vnode
)
16044 if (TREE_PUBLIC (vnode
->decl
))
16045 s390_check_type_for_vector_abi (TREE_TYPE (vnode
->decl
), false, false);
16047 FOR_EACH_FUNCTION (cnode
)
16048 if (TREE_PUBLIC (cnode
->decl
))
16049 s390_check_type_for_vector_abi (TREE_TYPE (cnode
->decl
), false, false);
16052 if (s390_vector_abi
!= 0)
16053 fprintf (asm_out_file
, "\t.gnu_attribute 8, %d\n",
16056 file_end_indicate_exec_stack ();
16058 if (flag_split_stack
)
16059 file_end_indicate_split_stack ();
16062 /* Return true if TYPE is a vector bool type. */
16064 s390_vector_bool_type_p (const_tree type
)
16066 return TYPE_VECTOR_OPAQUE (type
);
16069 /* Return the diagnostic message string if the binary operation OP is
16070 not permitted on TYPE1 and TYPE2, NULL otherwise. */
16072 s390_invalid_binary_op (int op ATTRIBUTE_UNUSED
, const_tree type1
, const_tree type2
)
16074 bool bool1_p
, bool2_p
;
16078 machine_mode mode1
, mode2
;
16080 if (!TARGET_ZVECTOR
)
16083 if (!VECTOR_TYPE_P (type1
) || !VECTOR_TYPE_P (type2
))
16086 bool1_p
= s390_vector_bool_type_p (type1
);
16087 bool2_p
= s390_vector_bool_type_p (type2
);
16089 /* Mixing signed and unsigned types is forbidden for all
16091 if (!bool1_p
&& !bool2_p
16092 && TYPE_UNSIGNED (type1
) != TYPE_UNSIGNED (type2
))
16093 return N_("types differ in signedness");
16095 plusminus_p
= (op
== PLUS_EXPR
|| op
== MINUS_EXPR
);
16096 muldiv_p
= (op
== MULT_EXPR
|| op
== RDIV_EXPR
|| op
== TRUNC_DIV_EXPR
16097 || op
== CEIL_DIV_EXPR
|| op
== FLOOR_DIV_EXPR
16098 || op
== ROUND_DIV_EXPR
);
16099 compare_p
= (op
== LT_EXPR
|| op
== LE_EXPR
|| op
== GT_EXPR
|| op
== GE_EXPR
16100 || op
== EQ_EXPR
|| op
== NE_EXPR
);
16102 if (bool1_p
&& bool2_p
&& (plusminus_p
|| muldiv_p
))
16103 return N_("binary operator does not support two vector bool operands");
16105 if (bool1_p
!= bool2_p
&& (muldiv_p
|| compare_p
))
16106 return N_("binary operator does not support vector bool operand");
16108 mode1
= TYPE_MODE (type1
);
16109 mode2
= TYPE_MODE (type2
);
16111 if (bool1_p
!= bool2_p
&& plusminus_p
16112 && (GET_MODE_CLASS (mode1
) == MODE_VECTOR_FLOAT
16113 || GET_MODE_CLASS (mode2
) == MODE_VECTOR_FLOAT
))
16114 return N_("binary operator does not support mixing vector "
16115 "bool with floating point vector operands");
16120 /* Implement TARGET_C_EXCESS_PRECISION.
16122 FIXME: For historical reasons, float_t and double_t are typedef'ed to
16123 double on s390, causing operations on float_t to operate in a higher
16124 precision than is necessary. However, it is not the case that SFmode
16125 operations have implicit excess precision, and we generate more optimal
16126 code if we let the compiler know no implicit extra precision is added.
16128 That means when we are compiling with -fexcess-precision=fast, the value
16129 we set for FLT_EVAL_METHOD will be out of line with the actual precision of
16130 float_t (though they would be correct for -fexcess-precision=standard).
16132 A complete fix would modify glibc to remove the unnecessary typedef
16133 of float_t to double. */
16135 static enum flt_eval_method
16136 s390_excess_precision (enum excess_precision_type type
)
16140 case EXCESS_PRECISION_TYPE_IMPLICIT
:
16141 case EXCESS_PRECISION_TYPE_FAST
:
16142 /* The fastest type to promote to will always be the native type,
16143 whether that occurs with implicit excess precision or
16145 return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT
;
16146 case EXCESS_PRECISION_TYPE_STANDARD
:
16147 /* Otherwise, when we are in a standards compliant mode, to
16148 ensure consistency with the implementation in glibc, report that
16149 float is evaluated to the range and precision of double. */
16150 return FLT_EVAL_METHOD_PROMOTE_TO_DOUBLE
;
16152 gcc_unreachable ();
16154 return FLT_EVAL_METHOD_UNPREDICTABLE
;
16157 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
16159 static unsigned HOST_WIDE_INT
16160 s390_asan_shadow_offset (void)
16162 return TARGET_64BIT
? HOST_WIDE_INT_1U
<< 52 : HOST_WIDE_INT_UC (0x20000000);
16165 /* Initialize GCC target structure. */
16167 #undef TARGET_ASM_ALIGNED_HI_OP
16168 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
16169 #undef TARGET_ASM_ALIGNED_DI_OP
16170 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
16171 #undef TARGET_ASM_INTEGER
16172 #define TARGET_ASM_INTEGER s390_assemble_integer
16174 #undef TARGET_ASM_OPEN_PAREN
16175 #define TARGET_ASM_OPEN_PAREN ""
16177 #undef TARGET_ASM_CLOSE_PAREN
16178 #define TARGET_ASM_CLOSE_PAREN ""
16180 #undef TARGET_OPTION_OVERRIDE
16181 #define TARGET_OPTION_OVERRIDE s390_option_override
16183 #ifdef TARGET_THREAD_SSP_OFFSET
16184 #undef TARGET_STACK_PROTECT_GUARD
16185 #define TARGET_STACK_PROTECT_GUARD hook_tree_void_null
16188 #undef TARGET_ENCODE_SECTION_INFO
16189 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
16191 #undef TARGET_SCALAR_MODE_SUPPORTED_P
16192 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
16195 #undef TARGET_HAVE_TLS
16196 #define TARGET_HAVE_TLS true
16198 #undef TARGET_CANNOT_FORCE_CONST_MEM
16199 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
16201 #undef TARGET_DELEGITIMIZE_ADDRESS
16202 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
16204 #undef TARGET_LEGITIMIZE_ADDRESS
16205 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
16207 #undef TARGET_RETURN_IN_MEMORY
16208 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
16210 #undef TARGET_INIT_BUILTINS
16211 #define TARGET_INIT_BUILTINS s390_init_builtins
16212 #undef TARGET_EXPAND_BUILTIN
16213 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
16214 #undef TARGET_BUILTIN_DECL
16215 #define TARGET_BUILTIN_DECL s390_builtin_decl
16217 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
16218 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA s390_output_addr_const_extra
16220 #undef TARGET_ASM_OUTPUT_MI_THUNK
16221 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
16222 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
16223 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
16225 #undef TARGET_C_EXCESS_PRECISION
16226 #define TARGET_C_EXCESS_PRECISION s390_excess_precision
16228 #undef TARGET_SCHED_ADJUST_PRIORITY
16229 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
16230 #undef TARGET_SCHED_ISSUE_RATE
16231 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
16232 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
16233 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
16235 #undef TARGET_SCHED_VARIABLE_ISSUE
16236 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
16237 #undef TARGET_SCHED_REORDER
16238 #define TARGET_SCHED_REORDER s390_sched_reorder
16239 #undef TARGET_SCHED_INIT
16240 #define TARGET_SCHED_INIT s390_sched_init
16242 #undef TARGET_CANNOT_COPY_INSN_P
16243 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
16244 #undef TARGET_RTX_COSTS
16245 #define TARGET_RTX_COSTS s390_rtx_costs
16246 #undef TARGET_ADDRESS_COST
16247 #define TARGET_ADDRESS_COST s390_address_cost
16248 #undef TARGET_REGISTER_MOVE_COST
16249 #define TARGET_REGISTER_MOVE_COST s390_register_move_cost
16250 #undef TARGET_MEMORY_MOVE_COST
16251 #define TARGET_MEMORY_MOVE_COST s390_memory_move_cost
16252 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
16253 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
16254 s390_builtin_vectorization_cost
16256 #undef TARGET_MACHINE_DEPENDENT_REORG
16257 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
16259 #undef TARGET_VALID_POINTER_MODE
16260 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
16262 #undef TARGET_BUILD_BUILTIN_VA_LIST
16263 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
16264 #undef TARGET_EXPAND_BUILTIN_VA_START
16265 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
16266 #undef TARGET_ASAN_SHADOW_OFFSET
16267 #define TARGET_ASAN_SHADOW_OFFSET s390_asan_shadow_offset
16268 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
16269 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
16271 #undef TARGET_PROMOTE_FUNCTION_MODE
16272 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
16273 #undef TARGET_PASS_BY_REFERENCE
16274 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
16276 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
16277 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
16278 #undef TARGET_FUNCTION_ARG
16279 #define TARGET_FUNCTION_ARG s390_function_arg
16280 #undef TARGET_FUNCTION_ARG_ADVANCE
16281 #define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance
16282 #undef TARGET_FUNCTION_ARG_PADDING
16283 #define TARGET_FUNCTION_ARG_PADDING s390_function_arg_padding
16284 #undef TARGET_FUNCTION_VALUE
16285 #define TARGET_FUNCTION_VALUE s390_function_value
16286 #undef TARGET_LIBCALL_VALUE
16287 #define TARGET_LIBCALL_VALUE s390_libcall_value
16288 #undef TARGET_STRICT_ARGUMENT_NAMING
16289 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
16291 #undef TARGET_KEEP_LEAF_WHEN_PROFILED
16292 #define TARGET_KEEP_LEAF_WHEN_PROFILED s390_keep_leaf_when_profiled
16294 #undef TARGET_FIXED_CONDITION_CODE_REGS
16295 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
16297 #undef TARGET_CC_MODES_COMPATIBLE
16298 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
16300 #undef TARGET_INVALID_WITHIN_DOLOOP
16301 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_insn_null
16304 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
16305 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
16308 #undef TARGET_DWARF_FRAME_REG_MODE
16309 #define TARGET_DWARF_FRAME_REG_MODE s390_dwarf_frame_reg_mode
16311 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
16312 #undef TARGET_MANGLE_TYPE
16313 #define TARGET_MANGLE_TYPE s390_mangle_type
16316 #undef TARGET_SCALAR_MODE_SUPPORTED_P
16317 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
16319 #undef TARGET_VECTOR_MODE_SUPPORTED_P
16320 #define TARGET_VECTOR_MODE_SUPPORTED_P s390_vector_mode_supported_p
16322 #undef TARGET_PREFERRED_RELOAD_CLASS
16323 #define TARGET_PREFERRED_RELOAD_CLASS s390_preferred_reload_class
16325 #undef TARGET_SECONDARY_RELOAD
16326 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
16327 #undef TARGET_SECONDARY_MEMORY_NEEDED
16328 #define TARGET_SECONDARY_MEMORY_NEEDED s390_secondary_memory_needed
16329 #undef TARGET_SECONDARY_MEMORY_NEEDED_MODE
16330 #define TARGET_SECONDARY_MEMORY_NEEDED_MODE s390_secondary_memory_needed_mode
16332 #undef TARGET_LIBGCC_CMP_RETURN_MODE
16333 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
16335 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
16336 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
16338 #undef TARGET_LEGITIMATE_ADDRESS_P
16339 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
16341 #undef TARGET_LEGITIMATE_CONSTANT_P
16342 #define TARGET_LEGITIMATE_CONSTANT_P s390_legitimate_constant_p
16344 #undef TARGET_LRA_P
16345 #define TARGET_LRA_P s390_lra_p
16347 #undef TARGET_CAN_ELIMINATE
16348 #define TARGET_CAN_ELIMINATE s390_can_eliminate
16350 #undef TARGET_CONDITIONAL_REGISTER_USAGE
16351 #define TARGET_CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage
16353 #undef TARGET_LOOP_UNROLL_ADJUST
16354 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
16356 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
16357 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
16358 #undef TARGET_TRAMPOLINE_INIT
16359 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
16362 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
16363 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
16365 #undef TARGET_UNWIND_WORD_MODE
16366 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
16368 #undef TARGET_CANONICALIZE_COMPARISON
16369 #define TARGET_CANONICALIZE_COMPARISON s390_canonicalize_comparison
16371 #undef TARGET_HARD_REGNO_SCRATCH_OK
16372 #define TARGET_HARD_REGNO_SCRATCH_OK s390_hard_regno_scratch_ok
16374 #undef TARGET_HARD_REGNO_NREGS
16375 #define TARGET_HARD_REGNO_NREGS s390_hard_regno_nregs
16376 #undef TARGET_HARD_REGNO_MODE_OK
16377 #define TARGET_HARD_REGNO_MODE_OK s390_hard_regno_mode_ok
16378 #undef TARGET_MODES_TIEABLE_P
16379 #define TARGET_MODES_TIEABLE_P s390_modes_tieable_p
16381 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
16382 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
16383 s390_hard_regno_call_part_clobbered
16385 #undef TARGET_ATTRIBUTE_TABLE
16386 #define TARGET_ATTRIBUTE_TABLE s390_attribute_table
16388 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
16389 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
16391 #undef TARGET_SET_UP_BY_PROLOGUE
16392 #define TARGET_SET_UP_BY_PROLOGUE s300_set_up_by_prologue
16394 #undef TARGET_EXTRA_LIVE_ON_ENTRY
16395 #define TARGET_EXTRA_LIVE_ON_ENTRY s390_live_on_entry
16397 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
16398 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
16399 s390_use_by_pieces_infrastructure_p
16401 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
16402 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV s390_atomic_assign_expand_fenv
16404 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
16405 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN s390_invalid_arg_for_unprototyped_fn
16407 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
16408 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE s390_preferred_simd_mode
16410 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
16411 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT s390_support_vector_misalignment
16413 #undef TARGET_VECTOR_ALIGNMENT
16414 #define TARGET_VECTOR_ALIGNMENT s390_vector_alignment
16416 #undef TARGET_INVALID_BINARY_OP
16417 #define TARGET_INVALID_BINARY_OP s390_invalid_binary_op
16419 #ifdef HAVE_AS_MACHINE_MACHINEMODE
16420 #undef TARGET_ASM_FILE_START
16421 #define TARGET_ASM_FILE_START s390_asm_file_start
16424 #undef TARGET_ASM_FILE_END
16425 #define TARGET_ASM_FILE_END s390_asm_file_end
16427 #if S390_USE_TARGET_ATTRIBUTE
16428 #undef TARGET_SET_CURRENT_FUNCTION
16429 #define TARGET_SET_CURRENT_FUNCTION s390_set_current_function
16431 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
16432 #define TARGET_OPTION_VALID_ATTRIBUTE_P s390_valid_target_attribute_p
16434 #undef TARGET_CAN_INLINE_P
16435 #define TARGET_CAN_INLINE_P s390_can_inline_p
16438 #undef TARGET_OPTION_RESTORE
16439 #define TARGET_OPTION_RESTORE s390_function_specific_restore
16441 #undef TARGET_CAN_CHANGE_MODE_CLASS
16442 #define TARGET_CAN_CHANGE_MODE_CLASS s390_can_change_mode_class
16444 #undef TARGET_CONSTANT_ALIGNMENT
16445 #define TARGET_CONSTANT_ALIGNMENT s390_constant_alignment
16447 struct gcc_target targetm
= TARGET_INITIALIZER
;
16449 #include "gt-s390.h"