gcc/config/score/score.md

   1 ;;  Machine description for Sunplus S+CORE
   2 ;;  Copyright (C) 2005, 2007
   3 ;;  Free Software Foundation, Inc.
   4 ;;  Contributed by Sunnorth.
   5
   6 ;; This file is part of GCC.
   7
   8 ;; GCC is free software; you can redistribute it and/or modify
   9 ;; it under the terms of the GNU General Public License as published by
  10 ;; the Free Software Foundation; either version 3, or (at your option)
  11 ;; any later version.
  12
  13 ;; GCC is distributed in the hope that it will be useful,
  14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 ;; GNU General Public License for more details.
  17
  18 ;; You should have received a copy of the GNU General Public License
  19 ;; along with GCC; see the file COPYING3.  If not see
  20 ;; <http://www.gnu.org/licenses/>.
  21
  22 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
  23
  24 ; branch        conditional branch
  25 ; jump          unconditional jump
  26 ; call          unconditional call
  27 ; load          load instruction(s)
  28 ; store         store instruction(s)
  29 ; cmp           integer compare
  30 ; arith         integer arithmetic instruction
  31 ; move          data movement within same register set
  32 ; const         load constant
  33 ; nop           no operation
  34 ; mul           integer multiply
  35 ; div           integer divide
  36 ; cndmv         conditional moves
  37 ; fce           transfer from hi/lo registers
  38 ; tce           transfer to   hi/lo registers
  39 ; fsr           transfer from special registers
  40 ; tsr           transfer to   special registers
  41 ; pseudo        pseudo instruction
  42
  43 (define_constants
  44   [(CC_REGNUM       33)
  45    (T_REGNUM        34)
  46    (RA_REGNUM       3)
  47    (SP_REGNUM       0)
  48    (AT_REGNUM       1)
  49    (FP_REGNUM       2)
  50    (RT_REGNUM       4)
  51    (GP_REGNUM       28)
  52    (EH_REGNUM       29)
  53    (HI_REGNUM       48)
  54    (LO_REGNUM       49)
  55    (CN_REGNUM       50)
  56    (LC_REGNUM       51)
  57    (SC_REGNUM       52)])
  58
  59 (define_constants
  60    [(BITTST         0)
  61     (CPLOAD         1)
  62     (CPRESTORE      2)
  63
  64     (SCB            3)
  65     (SCW            4)
  66     (SCE            5)
  67     (SCLC           6)
  68
  69     (LCB            7)
  70     (LCW            8)
  71     (LCE            9)
  72
  73     (SFFS           10)])
  74
  75 (define_attr "type"
  76   "unknown,branch,jump,call,load,store,cmp,arith,move,const,nop,mul,div,cndmv,fce,tce,fsr,tsr,fcr,tcr,pseudo"
  77   (const_string "unknown"))
  78
  79 (define_attr "mode" "unknown,none,QI,HI,SI,DI"
  80   (const_string "unknown"))
  81
  82 (define_attr "up_c" "yes,no"
  83   (const_string "no"))
  84
  85 (include "score7.md")
  86 (include "predicates.md")
  87 (include "misc.md")
  88 (include "mac.md")
  89
  90 (define_expand "movqi"
  91   [(set (match_operand:QI 0 "nonimmediate_operand")
  92         (match_operand:QI 1 "general_operand"))]
  93   ""
  94 {
  95   if (MEM_P (operands[0])
  96       && !register_operand (operands[1], QImode))
  97     {
  98       operands[1] = force_reg (QImode, operands[1]);
  99     }
 100 })
 101
 102 (define_insn "*movqi_insns"
 103   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a")
 104         (match_operand:QI 1 "general_operand" "i,d,m,d,*x,d,*a,d"))]
 105   "!MEM_P (operands[0]) || register_operand (operands[1], QImode)"
 106 {
 107   switch (which_alternative)
 108     {
 109     case 0: return mdp_limm (operands);
 110     case 1: return mdp_move (operands);
 111     case 2: return mdp_linsn (operands, MDA_BYTE, false);
 112     case 3: return mdp_sinsn (operands, MDA_BYTE);
 113     case 4: return TARGET_MAC ? \"mf%1%S0 %0\" : \"mf%1    %0\";
 114     case 5: return TARGET_MAC ? \"mt%0%S1 %1\" : \"mt%0    %1\";
 115     case 6: return \"mfsr    %0, %1\";
 116     case 7: return \"mtsr    %1, %0\";
 117     default: gcc_unreachable ();
 118     }
 119 }
 120   [(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr")
 121    (set_attr "mode" "QI")])
 122
 123 (define_expand "movhi"
 124   [(set (match_operand:HI 0 "nonimmediate_operand")
 125         (match_operand:HI 1 "general_operand"))]
 126   ""
 127 {
 128   if (MEM_P (operands[0])
 129       && !register_operand (operands[1], HImode))
 130     {
 131       operands[1] = force_reg (HImode, operands[1]);
 132     }
 133 })
 134
 135 (define_insn "*movhi_insns"
 136   [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a")
 137         (match_operand:HI 1 "general_operand" "i,d,m,d,*x,d,*a,d"))]
 138   "!MEM_P (operands[0]) || register_operand (operands[1], HImode)"
 139 {
 140   switch (which_alternative)
 141     {
 142     case 0: return mdp_limm (operands);
 143     case 1: return mdp_move (operands);
 144     case 2: return mdp_linsn (operands, MDA_HWORD, false);
 145     case 3: return mdp_sinsn (operands, MDA_HWORD);
 146     case 4: return TARGET_MAC ? \"mf%1%S0 %0\" : \"mf%1    %0\";
 147     case 5: return TARGET_MAC ? \"mt%0%S1 %1\" : \"mt%0    %1\";
 148     case 6: return \"mfsr    %0, %1\";
 149     case 7: return \"mtsr    %1, %0\";
 150     default: gcc_unreachable ();
 151     }
 152 }
 153   [(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr")
 154    (set_attr "mode" "HI")])
 155
 156 (define_expand "movsi"
 157   [(set (match_operand:SI 0 "nonimmediate_operand")
 158         (match_operand:SI 1 "general_operand"))]
 159   ""
 160 {
 161   if (MEM_P (operands[0])
 162       && !register_operand (operands[1], SImode))
 163     {
 164       operands[1] = force_reg (SImode, operands[1]);
 165     }
 166 })
 167
 168 (define_insn "*movsi_insns"
 169   [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a,d,*c")
 170         (match_operand:SI 1 "general_operand" "i,d,m,d,*x,d,*a,d,*c,d"))]
 171   "!MEM_P (operands[0]) || register_operand (operands[1], SImode)"
 172 {
 173   switch (which_alternative)
 174     {
 175     case 0:
 176       if (GET_CODE (operands[1]) != CONST_INT)
 177         return \"la      %0, %1\";
 178       else
 179         return mdp_limm (operands);
 180     case 1: return mdp_move (operands);
 181     case 2: return mdp_linsn (operands, MDA_WORD, false);
 182     case 3: return mdp_sinsn (operands, MDA_WORD);
 183     case 4: return TARGET_MAC ? \"mf%1%S0 %0\" : \"mf%1    %0\";
 184     case 5: return TARGET_MAC ? \"mt%0%S1 %1\" : \"mt%0    %1\";
 185     case 6: return \"mfsr    %0, %1\";
 186     case 7: return \"mtsr    %1, %0\";
 187     case 8: return \"mfcr    %0, %1\";
 188     case 9: return \"mtcr    %1, %0\";
 189     default: gcc_unreachable ();
 190     }
 191 }
 192   [(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr,fcr,tcr")
 193    (set_attr "mode" "SI")])
 194
 195 (define_insn_and_split "movdi"
 196   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,d,*x")
 197         (match_operand:DI 1 "general_operand" "i,d,m,d,*x,d"))]
 198   ""
 199   "#"
 200   "reload_completed"
 201   [(const_int 0)]
 202 {
 203   mds_movdi (operands);
 204   DONE;
 205 })
 206
 207 (define_expand "movsf"
 208   [(set (match_operand:SF 0 "nonimmediate_operand")
 209         (match_operand:SF 1 "general_operand"))]
 210   ""
 211 {
 212   if (MEM_P (operands[0])
 213       && !register_operand (operands[1], SFmode))
 214     {
 215       operands[1] = force_reg (SFmode, operands[1]);
 216     }
 217 })
 218
 219 (define_insn "*movsf_insns"
 220   [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,d,m")
 221         (match_operand:SF 1 "general_operand" "i,d,m,d"))]
 222   "!MEM_P (operands[0]) || register_operand (operands[1], SFmode)"
 223 {
 224   switch (which_alternative)
 225     {
 226     case 0: return \"li      %0, %D1\";;
 227     case 1: return mdp_move (operands);
 228     case 2: return mdp_linsn (operands, MDA_WORD, false);
 229     case 3: return mdp_sinsn (operands, MDA_WORD);
 230     default: gcc_unreachable ();
 231     }
 232 }
 233   [(set_attr "type" "arith,move,load,store")
 234    (set_attr "mode" "SI")])
 235
 236 (define_insn_and_split "movdf"
 237   [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,m")
 238         (match_operand:DF 1 "general_operand" "i,d,m,d"))]
 239   ""
 240   "#"
 241   "reload_completed"
 242   [(const_int 0)]
 243 {
 244   mds_movdi (operands);
 245   DONE;
 246 })
 247
 248 (define_insn "addsi3"
 249   [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
 250         (plus:SI (match_operand:SI 1 "register_operand" "0,0,d,d")
 251                  (match_operand:SI 2 "arith_operand" "I,L,N,d")))]
 252   ""
 253 {
 254   switch (which_alternative)
 255     {
 256     case 0: return \"addis %0, %U2\";
 257     case 1: return mdp_select_add_imm (operands, false);
 258     case 2: return \"addri %0, %1, %c2\";
 259     case 3: return mdp_select (operands, "add", true, "", false);
 260     default: gcc_unreachable ();
 261     }
 262 }
 263   [(set_attr "type" "arith")
 264    (set_attr "mode" "SI")])
 265
 266 (define_insn "*addsi3_cmp"
 267   [(set (reg:CC_NZ CC_REGNUM)
 268         (compare:CC_NZ (plus:SI
 269                         (match_operand:SI 1 "register_operand" "0,0,d,d")
 270                         (match_operand:SI 2 "arith_operand" "I,L,N,d"))
 271                        (const_int 0)))
 272    (clobber (match_scratch:SI 0 "=d,d,d,d"))]
 273   ""
 274 {
 275   switch (which_alternative)
 276     {
 277     case 0: return \"addis.c %0, %U2\";
 278     case 1: return mdp_select_add_imm (operands, true);
 279     case 2: return \"addri.c %0, %1, %c2\";
 280     case 3: return mdp_select (operands, "add", true, "", true);
 281     default: gcc_unreachable ();
 282     }
 283 }
 284   [(set_attr "type" "arith")
 285    (set_attr "up_c" "yes")
 286    (set_attr "mode" "SI")])
 287
 288 (define_insn "*addsi3_ucc"
 289   [(set (reg:CC_NZ CC_REGNUM)
 290         (compare:CC_NZ (plus:SI
 291                         (match_operand:SI 1 "register_operand" "0,0,d,d")
 292                         (match_operand:SI 2 "arith_operand" "I,L,N,d"))
 293                        (const_int 0)))
 294    (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
 295         (plus:SI (match_dup 1) (match_dup 2)))]
 296   ""
 297 {
 298   switch (which_alternative)
 299     {
 300     case 0: return \"addis.c %0, %U2\";
 301     case 1: return mdp_select_add_imm (operands, true);
 302     case 2: return \"addri.c %0, %1, %c2\";
 303     case 3: return mdp_select (operands, "add", true, "", true);
 304     default: gcc_unreachable ();
 305     }
 306 }
 307   [(set_attr "type" "arith")
 308    (set_attr "up_c" "yes")
 309    (set_attr "mode" "SI")])
 310
 311 (define_insn "adddi3"
 312   [(set (match_operand:DI 0 "register_operand" "=e,d")
 313         (plus:DI (match_operand:DI 1 "register_operand" "0,d")
 314                  (match_operand:DI 2 "register_operand" "e,d")))
 315   (clobber (reg:CC CC_REGNUM))]
 316   ""
 317   "@
 318    add!    %L0, %L2\;addc!   %H0, %H2
 319    add.c   %L0, %L1, %L2\;addc    %H0, %H1, %H2"
 320   [(set_attr "type" "arith")
 321    (set_attr "mode" "DI")])
 322
 323 (define_insn "subsi3"
 324   [(set (match_operand:SI 0 "register_operand" "=d")
 325         (minus:SI (match_operand:SI 1 "register_operand" "d")
 326                   (match_operand:SI 2 "register_operand" "d")))]
 327   ""
 328 {
 329   return mdp_select (operands, "sub", false, "", false);
 330 }
 331   [(set_attr "type" "arith")
 332    (set_attr "mode" "SI")])
 333
 334 (define_insn "*subsi3_cmp"
 335   [(set (reg:CC_NZ CC_REGNUM)
 336         (compare:CC_NZ (minus:SI (match_operand:SI 1 "register_operand" "d")
 337                                  (match_operand:SI 2 "register_operand" "d"))
 338                        (const_int 0)))
 339    (clobber (match_scratch:SI 0 "=d"))]
 340   ""
 341 {
 342   return mdp_select (operands, "sub", false, "", true);
 343 }
 344   [(set_attr "type" "arith")
 345    (set_attr "up_c" "yes")
 346    (set_attr "mode" "SI")])
 347
 348 (define_peephole2
 349   [(set (match_operand:SI 0 "g32reg_operand" "")
 350         (minus:SI (match_operand:SI 1 "g32reg_operand" "")
 351                   (match_operand:SI 2 "g32reg_operand" "")))
 352    (set (reg:CC CC_REGNUM)
 353         (compare:CC (match_dup 1) (match_dup 2)))]
 354   ""
 355   [(set (reg:CC CC_REGNUM)
 356         (compare:CC (match_dup 1) (match_dup 2)))
 357    (set (match_dup 0)
 358         (minus:SI (match_dup 1) (match_dup 2)))])
 359
 360 (define_insn "subsi3_ucc_pcmp"
 361   [(parallel
 362        [(set (reg:CC CC_REGNUM)
 363              (compare:CC (match_operand:SI 1 "register_operand" "d")
 364                          (match_operand:SI 2 "register_operand" "d")))
 365         (set (match_operand:SI 0 "register_operand" "=d")
 366              (minus:SI (match_dup 1) (match_dup 2)))])]
 367   ""
 368 {
 369   return mdp_select (operands, "sub", false, "", true);
 370 }
 371   [(set_attr "type" "arith")
 372    (set_attr "up_c" "yes")
 373    (set_attr "mode" "SI")])
 374
 375 (define_insn "subsi3_ucc"
 376   [(set (reg:CC_NZ CC_REGNUM)
 377         (compare:CC_NZ (minus:SI (match_operand:SI 1 "register_operand" "d")
 378                                  (match_operand:SI 2 "register_operand" "d"))
 379                        (const_int 0)))
 380    (set (match_operand:SI 0 "register_operand" "=d")
 381         (minus:SI (match_dup 1) (match_dup 2)))]
 382   ""
 383 {
 384   return mdp_select (operands, "sub", false, "", true);
 385 }
 386   [(set_attr "type" "arith")
 387    (set_attr "up_c" "yes")
 388    (set_attr "mode" "SI")])
 389
 390 (define_insn "subdi3"
 391   [(set (match_operand:DI 0 "register_operand" "=e,d")
 392         (minus:DI (match_operand:DI 1 "register_operand" "0,d")
 393                   (match_operand:DI 2 "register_operand" "e,d")))
 394    (clobber (reg:CC CC_REGNUM))]
 395   ""
 396   "@
 397    sub!    %L0, %L2\;subc    %H0, %H1, %H2
 398    sub.c   %L0, %L1, %L2\;subc    %H0, %H1, %H2"
 399   [(set_attr "type" "arith")
 400    (set_attr "mode" "DI")])
 401
 402 (define_insn "andsi3"
 403   [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
 404         (and:SI (match_operand:SI 1 "register_operand" "0,0,d,d")
 405                 (match_operand:SI 2 "arith_operand" "I,K,M,d")))]
 406   ""
 407 {
 408   switch (which_alternative)
 409     {
 410     case 0: return \"andis %0, %U2\";
 411     case 1: return \"andi  %0, %c2";
 412     case 2: return \"andri %0, %1, %c2\";
 413     case 3: return mdp_select (operands, "and", true, "", false);
 414     default: gcc_unreachable ();
 415     }
 416 }
 417   [(set_attr "type" "arith")
 418    (set_attr "mode" "SI")])
 419
 420 (define_insn "andsi3_cmp"
 421   [(set (reg:CC_NZ CC_REGNUM)
 422         (compare:CC_NZ (and:SI (match_operand:SI 1 "register_operand" "0,0,0,d")
 423                                (match_operand:SI 2 "arith_operand" "I,K,M,d"))
 424                        (const_int 0)))
 425    (clobber (match_scratch:SI 0 "=d,d,d,d"))]
 426   ""
 427 {
 428   switch (which_alternative)
 429     {
 430     case 0: return \"andis.c %0, %U2\";
 431     case 1: return \"andi.c  %0, %c2";
 432     case 2: return \"andri.c %0, %1, %c2\";
 433     case 3: return mdp_select (operands, "and", true, "", true);
 434     default: gcc_unreachable ();
 435     }
 436 }
 437   [(set_attr "type" "arith")
 438    (set_attr "up_c" "yes")
 439    (set_attr "mode" "SI")])
 440
 441 (define_insn "*andsi3_ucc"
 442   [(set (reg:CC_NZ CC_REGNUM)
 443         (compare:CC_NZ (and:SI
 444                         (match_operand:SI 1 "register_operand" "0,0,d,d")
 445                         (match_operand:SI 2 "arith_operand" "I,K,M,d"))
 446                        (const_int 0)))
 447    (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
 448         (and:SI (match_dup 1) (match_dup 2)))]
 449   ""
 450 {
 451   switch (which_alternative)
 452     {
 453     case 0: return \"andis.c %0, %U2\";
 454     case 1: return \"andi.c  %0, %c2";
 455     case 2: return \"andri.c %0, %1, %c2\";
 456     case 3: return mdp_select (operands, "and", true, "", true);
 457     default: gcc_unreachable ();
 458     }
 459 }
 460   [(set_attr "type" "arith")
 461    (set_attr "up_c" "yes")
 462    (set_attr "mode" "SI")])
 463
 464 (define_insn_and_split "*zero_extract_andi"
 465   [(set (reg:CC CC_REGNUM)
 466         (compare:CC (zero_extract:SI
 467                      (match_operand:SI 0 "register_operand" "d")
 468                      (match_operand:SI 1 "const_uimm5" "")
 469                      (match_operand:SI 2 "const_uimm5" ""))
 470                     (const_int 0)))]
 471   ""
 472   "#"
 473   ""
 474   [(const_int 1)]
 475 {
 476   mds_zero_extract_andi (operands);
 477   DONE;
 478 })
 479
 480 (define_insn "iorsi3"
 481   [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
 482         (ior:SI (match_operand:SI 1 "register_operand" "0,0,d,d")
 483                 (match_operand:SI 2 "arith_operand" "I,K,M,d")))]
 484   ""
 485 {
 486   switch (which_alternative)
 487     {
 488     case 0: return \"oris %0, %U2\";
 489     case 1: return \"ori  %0, %c2\";
 490     case 2: return \"orri %0, %1, %c2\";
 491     case 3: return mdp_select (operands, "or", true, "", false);
 492     default: gcc_unreachable ();
 493     }
 494 }
 495   [(set_attr "type" "arith")
 496    (set_attr "mode" "SI")])
 497
 498 (define_insn "iorsi3_ucc"
 499   [(set (reg:CC_NZ CC_REGNUM)
 500         (compare:CC_NZ (ior:SI
 501                         (match_operand:SI 1 "register_operand" "0,0,d,d")
 502                         (match_operand:SI 2 "arith_operand" "I,K,M,d"))
 503                        (const_int 0)))
 504    (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
 505         (ior:SI (match_dup 1) (match_dup 2)))]
 506   ""
 507 {
 508   switch (which_alternative)
 509     {
 510     case 0: return \"oris.c %0, %U2\";
 511     case 1: return \"ori.c  %0, %c2\";
 512     case 2: return \"orri.c %0, %1, %c2\";
 513     case 3: return mdp_select (operands, "or", true, "", true);
 514     default: gcc_unreachable ();
 515     }
 516 }
 517   [(set_attr "type" "arith")
 518    (set_attr "up_c" "yes")
 519    (set_attr "mode" "SI")])
 520
 521 (define_insn "iorsi3_cmp"
 522   [(set (reg:CC_NZ CC_REGNUM)
 523         (compare:CC_NZ (ior:SI
 524                         (match_operand:SI 1 "register_operand" "0,0,d,d")
 525                         (match_operand:SI 2 "arith_operand" "I,K,M,d"))
 526                        (const_int 0)))
 527    (clobber (match_scratch:SI 0 "=d,d,d,d"))]
 528   ""
 529 {
 530   switch (which_alternative)
 531     {
 532     case 0: return \"oris.c %0, %U2\";
 533     case 1: return \"ori.c  %0, %c2\";
 534     case 2: return \"orri.c %0, %1, %c2\";
 535     case 3: return mdp_select (operands, "or", true, "", true);
 536     default: gcc_unreachable ();
 537     }
 538 }
 539   [(set_attr "type" "arith")
 540    (set_attr "up_c" "yes")
 541    (set_attr "mode" "SI")])
 542
 543 (define_insn "xorsi3"
 544   [(set (match_operand:SI 0 "register_operand" "=d")
 545         (xor:SI (match_operand:SI 1 "register_operand" "d")
 546                 (match_operand:SI 2 "register_operand" "d")))]
 547   ""
 548 {
 549   return mdp_select (operands, "xor", true, "", false);
 550 }
 551   [(set_attr "type" "arith")
 552    (set_attr "mode" "SI")])
 553
 554 (define_insn "xorsi3_ucc"
 555   [(set (reg:CC_NZ CC_REGNUM)
 556         (compare:CC_NZ (xor:SI (match_operand:SI 1 "register_operand" "d")
 557                                (match_operand:SI 2 "register_operand" "d"))
 558                        (const_int 0)))
 559    (set (match_operand:SI 0 "register_operand" "=d")
 560         (xor:SI (match_dup 1) (match_dup 2)))]
 561   ""
 562 {
 563   return mdp_select (operands, "xor", true, "", true);
 564 }
 565   [(set_attr "type" "arith")
 566    (set_attr "up_c" "yes")
 567    (set_attr "mode" "SI")])
 568
 569 (define_insn "xorsi3_cmp"
 570   [(set (reg:CC_NZ CC_REGNUM)
 571         (compare:CC_NZ (xor:SI (match_operand:SI 1 "register_operand" "d")
 572                                (match_operand:SI 2 "register_operand" "d"))
 573                        (const_int 0)))
 574    (clobber (match_scratch:SI 0 "=d"))]
 575   ""
 576 {
 577   return mdp_select (operands, "xor", true, "", true);
 578 }
 579   [(set_attr "type" "arith")
 580    (set_attr "up_c" "yes")
 581    (set_attr "mode" "SI")])
 582
 583 (define_insn "extendqisi2"
 584   [(set (match_operand:SI 0 "register_operand" "=d,d")
 585         (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
 586   ""
 587 {
 588   switch (which_alternative)
 589     {
 590     case 0: return \"extsb   %0, %1\";
 591     case 1: return mdp_linsn (operands, MDA_BYTE, true);
 592     default: gcc_unreachable ();
 593     }
 594 }
 595   [(set_attr "type" "arith,load")
 596    (set_attr "mode" "SI")])
 597
 598 (define_insn "*extendqisi2_ucc"
 599   [(set (reg:CC_N CC_REGNUM)
 600         (compare:CC_N (ashiftrt:SI
 601                        (ashift:SI (match_operand:SI 1 "register_operand" "d")
 602                                   (const_int 24))
 603                        (const_int 24))
 604                       (const_int 0)))
 605    (set (match_operand:SI 0 "register_operand" "=d")
 606         (sign_extend:SI (match_operand:QI 2 "register_operand" "0")))]
 607   ""
 608   "extsb.c %0, %1"
 609   [(set_attr "type" "arith")
 610    (set_attr "up_c" "yes")
 611    (set_attr "mode" "SI")])
 612
 613 (define_insn "*extendqisi2_cmp"
 614   [(set (reg:CC_N CC_REGNUM)
 615         (compare:CC_N (ashiftrt:SI
 616                        (ashift:SI (match_operand:SI 1 "register_operand" "d")
 617                                   (const_int 24))
 618                        (const_int 24))
 619                       (const_int 0)))
 620    (clobber (match_scratch:SI 0 "=d"))]
 621   ""
 622   "extsb.c %0, %1"
 623   [(set_attr "type" "arith")
 624    (set_attr "up_c" "yes")
 625    (set_attr "mode" "SI")])
 626
 627 (define_insn "extendhisi2"
 628   [(set (match_operand:SI 0 "register_operand" "=d,d")
 629         (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
 630   ""
 631 {
 632   switch (which_alternative)
 633     {
 634     case 0: return \"extsh   %0, %1\";
 635     case 1: return mdp_linsn (operands, MDA_HWORD, true);
 636     default: gcc_unreachable ();
 637     }
 638 }
 639   [(set_attr "type" "arith, load")
 640    (set_attr "mode" "SI")])
 641
 642 (define_insn "*extendhisi2_ucc"
 643   [(set (reg:CC_N CC_REGNUM)
 644         (compare:CC_N (ashiftrt:SI
 645                        (ashift:SI (match_operand:SI 1 "register_operand" "d")
 646                                   (const_int 16))
 647                        (const_int 16))
 648                       (const_int 0)))
 649   (set (match_operand:SI 0 "register_operand" "=d")
 650        (sign_extend:SI (match_operand:HI 2 "register_operand" "0")))]
 651   ""
 652   "extsh.c %0, %1"
 653   [(set_attr "type" "arith")
 654    (set_attr "up_c" "yes")
 655    (set_attr "mode" "SI")])
 656
 657 (define_insn "*extendhisi2_cmp"
 658   [(set (reg:CC_N CC_REGNUM)
 659         (compare:CC_N (ashiftrt:SI
 660                        (ashift:SI (match_operand:SI 1 "register_operand" "d")
 661                                   (const_int 16))
 662                        (const_int 16))
 663                       (const_int 0)))
 664    (clobber (match_scratch:SI 0 "=d"))]
 665   ""
 666   "extsh.c %0, %1"
 667   [(set_attr "type" "arith")
 668    (set_attr "up_c" "yes")
 669    (set_attr "mode" "SI")])
 670
 671 (define_insn "zero_extendqisi2"
 672   [(set (match_operand:SI 0 "register_operand" "=d,d")
 673         (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
 674   ""
 675 {
 676   switch (which_alternative)
 677     {
 678     case 0: return \"extzb   %0, %1\";
 679     case 1: return mdp_linsn (operands, MDA_BYTE, false);
 680     default: gcc_unreachable ();
 681     }
 682   }
 683   [(set_attr "type" "arith, load")
 684    (set_attr "mode" "SI")])
 685
 686 (define_insn "*zero_extendqisi2_ucc"
 687   [(set (reg:CC_N CC_REGNUM)
 688         (compare:CC_N (lshiftrt:SI
 689                        (ashift:SI (match_operand:SI 1 "register_operand" "d")
 690                                   (const_int 24))
 691                        (const_int 24))
 692                       (const_int 0)))
 693    (set (match_operand:SI 0 "register_operand" "=d")
 694         (zero_extend:SI (match_operand:QI 2 "register_operand" "0")))]
 695   ""
 696   "extzb.c %0, %1"
 697   [(set_attr "type" "arith")
 698    (set_attr "up_c" "yes")
 699    (set_attr "mode" "SI")])
 700
 701 (define_insn "*zero_extendqisi2_cmp"
 702   [(set (reg:CC_N CC_REGNUM)
 703         (compare:CC_N (lshiftrt:SI
 704                        (ashift:SI (match_operand:SI 1 "register_operand" "d")
 705                                   (const_int 24))
 706                        (const_int 24))
 707                       (const_int 0)))
 708    (clobber (match_scratch:SI 0 "=d"))]
 709   ""
 710   "extzb.c %0, %1"
 711   [(set_attr "type" "arith")
 712    (set_attr "up_c" "yes")
 713    (set_attr "mode" "SI")])
 714
 715 (define_insn "zero_extendhisi2"
 716   [(set (match_operand:SI 0 "register_operand" "=d,d")
 717         (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
 718   ""
 719 {
 720   switch (which_alternative)
 721     {
 722     case 0: return \"extzh   %0, %1\";
 723     case 1: return mdp_linsn (operands, MDA_HWORD, false);
 724     default: gcc_unreachable ();
 725     }
 726   }
 727   [(set_attr "type" "arith, load")
 728    (set_attr "mode" "SI")])
 729
 730 (define_insn "*zero_extendhisi2_ucc"
 731   [(set (reg:CC_N CC_REGNUM)
 732         (compare:CC_N (lshiftrt:SI
 733                        (ashift:SI (match_operand:SI 1 "register_operand" "d")
 734                                   (const_int 16))
 735                        (const_int 16))
 736                       (const_int 0)))
 737   (set (match_operand:SI 0 "register_operand" "=d")
 738        (zero_extend:SI (match_operand:HI 2 "register_operand" "0")))]
 739   ""
 740   "extzh.c %0, %1"
 741   [(set_attr "type" "arith")
 742    (set_attr "up_c" "yes")
 743    (set_attr "mode" "SI")])
 744
 745 (define_insn "*zero_extendhisi2_cmp"
 746   [(set (reg:CC_N CC_REGNUM)
 747         (compare:CC_N (lshiftrt:SI
 748                        (ashift:SI (match_operand:SI 1 "register_operand" "d")
 749                                   (const_int 16))
 750                        (const_int 16))
 751                       (const_int 0)))
 752    (clobber (match_scratch:SI 0 "=d"))]
 753   ""
 754   "extzh.c %0, %1"
 755   [(set_attr "type" "arith")
 756    (set_attr "up_c" "yes")
 757    (set_attr "mode" "SI")])
 758
 759 (define_insn "mulsi3"
 760   [(set (match_operand:SI 0 "register_operand" "=l")
 761         (mult:SI (match_operand:SI 1 "register_operand" "d")
 762                  (match_operand:SI 2 "register_operand" "d")))
 763   (clobber (reg:SI HI_REGNUM))]
 764   "!TARGET_SCORE5U"
 765   "mul     %1, %2"
 766   [(set_attr "type" "mul")
 767    (set_attr "mode" "SI")])
 768
 769 (define_insn "mulsidi3"
 770   [(set (match_operand:DI 0 "register_operand" "=x")
 771         (mult:DI (sign_extend:DI
 772                   (match_operand:SI 1 "register_operand" "d"))
 773                  (sign_extend:DI
 774                   (match_operand:SI 2 "register_operand" "d"))))]
 775   "!TARGET_SCORE5U"
 776   "mul     %1, %2"
 777   [(set_attr "type" "mul")
 778    (set_attr "mode" "DI")])
 779
 780 (define_insn "umulsidi3"
 781   [(set (match_operand:DI 0 "register_operand" "=x")
 782         (mult:DI (zero_extend:DI
 783                   (match_operand:SI 1 "register_operand" "d"))
 784                  (zero_extend:DI
 785                   (match_operand:SI 2 "register_operand" "d"))))]
 786   "!TARGET_SCORE5U"
 787   "mulu    %1, %2"
 788   [(set_attr "type" "mul")
 789    (set_attr "mode" "DI")])
 790
 791 (define_insn "divmodsi4"
 792   [(set (match_operand:SI 0 "register_operand" "=l")
 793         (div:SI (match_operand:SI 1 "register_operand" "d")
 794                 (match_operand:SI 2 "register_operand" "d")))
 795    (set (match_operand:SI 3 "register_operand" "=h")
 796         (mod:SI (match_dup 1) (match_dup 2)))]
 797   "!TARGET_SCORE5U"
 798   "div     %1, %2"
 799   [(set_attr "type" "div")
 800    (set_attr "mode" "SI")])
 801
 802 (define_insn "udivmodsi4"
 803   [(set (match_operand:SI 0 "register_operand" "=l")
 804         (udiv:SI (match_operand:SI 1 "register_operand" "d")
 805                  (match_operand:SI 2 "register_operand" "d")))
 806    (set (match_operand:SI 3 "register_operand" "=h")
 807         (umod:SI (match_dup 1) (match_dup 2)))]
 808   "!TARGET_SCORE5U"
 809   "divu    %1, %2"
 810   [(set_attr "type" "div")
 811    (set_attr "mode" "SI")])
 812
 813 (define_insn "ashlsi3"
 814   [(set (match_operand:SI 0 "register_operand" "=d,d")
 815         (ashift:SI (match_operand:SI 1 "register_operand" "d,d")
 816                    (match_operand:SI 2 "arith_operand" "J,d")))]
 817   ""
 818   "@
 819    slli    %0, %1, %c2
 820    sll     %0, %1, %2"
 821   [(set_attr "type" "arith")
 822    (set_attr "mode" "SI")])
 823
 824 (define_insn "ashlsi3_ucc"
 825   [(set (reg:CC_NZ CC_REGNUM)
 826         (compare:CC_NZ (ashift:SI
 827                         (match_operand:SI 1 "register_operand" "d,d")
 828                         (match_operand:SI 2 "arith_operand" "J,d"))
 829                        (const_int 0)))
 830    (set (match_operand:SI 0 "register_operand" "=d,d")
 831         (ashift:SI (match_dup 1) (match_dup 2)))]
 832   ""
 833 {
 834   switch (which_alternative)
 835     {
 836     case 0: return mdp_select (operands, "slli", false, "c", true);
 837     case 1: return mdp_select (operands, "sll", false, "", true);
 838     default: gcc_unreachable ();
 839     }
 840 }
 841   [(set_attr "type" "arith")
 842    (set_attr "up_c" "yes")
 843    (set_attr "mode" "SI")])
 844
 845 (define_insn "ashlsi3_cmp"
 846   [(set (reg:CC_NZ CC_REGNUM)
 847         (compare:CC_NZ (ashift:SI
 848                         (match_operand:SI 1 "register_operand" "d,d")
 849                         (match_operand:SI 2 "arith_operand" "J,d"))
 850                        (const_int 0)))
 851    (clobber (match_scratch:SI 0 "=d,d"))]
 852   ""
 853 {
 854   switch (which_alternative)
 855     {
 856     case 0: return mdp_select (operands, "slli", false, "c", true);
 857     case 1: return mdp_select (operands, "sll", false, "", true);
 858     default: gcc_unreachable ();
 859     }
 860 }
 861   [(set_attr "type" "arith")
 862    (set_attr "up_c" "yes")
 863    (set_attr "mode" "SI")])
 864
 865 (define_insn "ashrsi3"
 866   [(set (match_operand:SI 0 "register_operand" "=d,d")
 867         (ashiftrt:SI (match_operand:SI 1 "register_operand" "d,d")
 868                      (match_operand:SI 2 "arith_operand" "J,d")))]
 869   ""
 870   "@
 871    srai    %0, %1, %c2
 872    sra     %0, %1, %2"
 873   [(set_attr "type" "arith")
 874    (set_attr "mode" "SI")])
 875
 876 (define_insn "ashrsi3_ucc"
 877   [(set (reg:CC_NZ CC_REGNUM)
 878         (compare:CC_NZ (ashiftrt:SI
 879                         (match_operand:SI 1 "register_operand" "d,d")
 880                         (match_operand:SI 2 "arith_operand" "J,d"))
 881                        (const_int 0)))
 882    (set (match_operand:SI 0 "register_operand" "=d,d")
 883         (ashiftrt:SI (match_dup 1) (match_dup 2)))]
 884   ""
 885 {
 886   switch (which_alternative)
 887     {
 888     case 0: return \"srai.c  %0, %1, %c2\";
 889     case 1: return mdp_select (operands, "sra", false, "", true);
 890     default: gcc_unreachable ();
 891     }
 892 }
 893   [(set_attr "type" "arith")
 894    (set_attr "up_c" "yes")
 895    (set_attr "mode" "SI")])
 896
 897 (define_insn "ashrsi3_cmp"
 898   [(set (reg:CC_NZ CC_REGNUM)
 899         (compare:CC_NZ (ashiftrt:SI
 900                         (match_operand:SI 1 "register_operand" "d,d")
 901                         (match_operand:SI 2 "arith_operand" "J,d"))
 902                        (const_int 0)))
 903    (clobber (match_scratch:SI 0 "=d,d"))]
 904   ""
 905 {
 906   switch (which_alternative)
 907     {
 908     case 0: return \"srai.c  %0, %1, %c2\";
 909     case 1: return mdp_select (operands, "sra", false, "", true);
 910     default: gcc_unreachable ();
 911     }
 912 }
 913   [(set_attr "type" "arith")
 914    (set_attr "up_c" "yes")
 915    (set_attr "mode" "SI")])
 916
 917 (define_insn "lshrsi3"
 918   [(set (match_operand:SI 0 "register_operand" "=d,d")
 919         (lshiftrt:SI (match_operand:SI 1 "register_operand" "d,d")
 920                      (match_operand:SI 2 "arith_operand" "J,d")))]
 921   ""
 922   "@
 923    srli    %0, %1, %c2
 924    srl     %0, %1, %2"
 925   [(set_attr "type" "arith")
 926    (set_attr "mode" "SI")])
 927
 928 (define_insn "lshrsi3_ucc"
 929   [(set (reg:CC_NZ CC_REGNUM)
 930         (compare:CC_NZ (lshiftrt:SI
 931                         (match_operand:SI 1 "register_operand" "d,d")
 932                         (match_operand:SI 2 "arith_operand" "J,d"))
 933                        (const_int 0)))
 934    (set (match_operand:SI 0 "register_operand" "=d,d")
 935         (lshiftrt:SI (match_dup 1) (match_dup 2)))]
 936   ""
 937 {
 938   switch (which_alternative)
 939     {
 940     case 0: return mdp_select (operands, "srli", false, "c", true);
 941     case 1: return mdp_select (operands, "srl", false, "", true);
 942     default: gcc_unreachable ();
 943     }
 944 }
 945   [(set_attr "type" "arith")
 946    (set_attr "up_c" "yes")
 947    (set_attr "mode" "SI")])
 948
 949 (define_insn "lshrsi3_cmp"
 950   [(set (reg:CC_NZ CC_REGNUM)
 951         (compare:CC_NZ (lshiftrt:SI
 952                         (match_operand:SI 1 "register_operand" "d,d")
 953                         (match_operand:SI 2 "arith_operand" "J,d"))
 954                        (const_int 0)))
 955    (clobber (match_scratch:SI 0 "=d,d"))]
 956   ""
 957 {
 958   switch (which_alternative)
 959     {
 960     case 0: return mdp_select (operands, "srli", false, "c", true);
 961     case 1: return mdp_select (operands, "srl", false, "", true);
 962     default: gcc_unreachable ();
 963     }
 964 }
 965   [(set_attr "type" "arith")
 966    (set_attr "up_c" "yes")
 967    (set_attr "mode" "SI")])
 968
 969 (define_insn "negsi2"
 970   [(set (match_operand:SI 0 "register_operand" "=d")
 971         (neg:SI (match_operand:SI 1 "register_operand" "d")))]
 972   ""
 973   "neg     %0, %1"
 974   [(set_attr "type" "arith")
 975    (set_attr "mode" "SI")])
 976
 977 (define_insn "*negsi2_cmp"
 978   [(set (reg:CC_NZ CC_REGNUM)
 979         (compare:CC_NZ (neg:SI (match_operand:SI 1 "register_operand" "e,d"))
 980                        (const_int 0)))
 981    (clobber (match_scratch:SI 0 "=e,d"))]
 982   ""
 983   "@
 984    neg!    %0, %1
 985    neg.c   %0, %1"
 986   [(set_attr "type" "arith")
 987    (set_attr "up_c" "yes")
 988    (set_attr "mode" "SI")])
 989
 990 (define_insn "negsi2_ucc"
 991   [(set (reg:CC_NZ CC_REGNUM)
 992         (compare:CC_NZ (neg:SI (match_operand:SI 1 "register_operand" "e,d"))
 993                        (const_int 0)))
 994    (set (match_operand:SI 0 "register_operand" "=e,d")
 995         (neg:SI (match_dup 1)))]
 996   ""
 997   "@
 998    neg!    %0, %1
 999    neg.c   %0, %1"
1000   [(set_attr "type" "arith")
1001    (set_attr "up_c" "yes")
1002    (set_attr "mode" "SI")])
1003
1004 (define_insn "one_cmplsi2"
1005   [(set (match_operand:SI 0 "register_operand" "=d")
1006         (not:SI (match_operand:SI 1 "register_operand" "d")))]
1007   ""
1008   "not     %0, %1"
1009   [(set_attr "type" "arith")
1010    (set_attr "mode" "SI")])
1011
1012 (define_insn "one_cmplsi2_ucc"
1013   [(set (reg:CC_NZ CC_REGNUM)
1014         (compare:CC_NZ (not:SI (match_operand:SI 1 "register_operand" "e,d"))
1015                        (const_int 0)))
1016    (set (match_operand:SI 0 "register_operand" "=e,d")
1017         (not:SI (match_dup 1)))]
1018   ""
1019   "@
1020    not!    %0, %1
1021    not.c   %0, %1"
1022   [(set_attr "type" "arith")
1023    (set_attr "up_c" "yes")
1024    (set_attr "mode" "SI")])
1025
1026 (define_insn "one_cmplsi2_cmp"
1027   [(set (reg:CC_NZ CC_REGNUM)
1028         (compare:CC_NZ (not:SI (match_operand:SI 1 "register_operand" "e,d"))
1029                        (const_int 0)))
1030    (clobber (match_scratch:SI 0 "=e,d"))]
1031   ""
1032   "@
1033    not!    %0, %1
1034    not.c   %0, %1"
1035   [(set_attr "type" "arith")
1036    (set_attr "up_c" "yes")
1037    (set_attr "mode" "SI")])
1038
1039 (define_insn "rotlsi3"
1040   [(set (match_operand:SI 0 "register_operand" "=d,d")
1041         (rotate:SI (match_operand:SI 1 "register_operand" "d,d")
1042                    (match_operand:SI 2 "arith_operand" "J,d")))
1043    (clobber (reg:CC CC_REGNUM))]
1044   ""
1045   "@
1046    roli.c  %0, %1, %c2
1047    rol.c   %0, %1, %2"
1048   [(set_attr "type" "arith")
1049    (set_attr "mode" "SI")])
1050
1051 (define_insn "rotrsi3"
1052   [(set (match_operand:SI 0 "register_operand" "=d,d")
1053         (rotatert:SI (match_operand:SI 1 "register_operand" "d,d")
1054                      (match_operand:SI 2 "arith_operand" "J,d")))
1055    (clobber (reg:CC CC_REGNUM))]
1056   ""
1057   "@
1058    rori.c  %0, %1, %c2
1059    ror.c   %0, %1, %2"
1060   [(set_attr "type" "arith")
1061    (set_attr "mode" "SI")])
1062
1063 (define_expand "cmpsi"
1064   [(match_operand:SI 0 "register_operand" "")
1065    (match_operand:SI 1 "arith_operand" "")]
1066   ""
1067 {
1068   cmp_op0 = operands[0];
1069   cmp_op1 = operands[1];
1070   DONE;
1071 })
1072
1073 (define_insn "cmpsi_nz"
1074   [(set (reg:CC_NZ CC_REGNUM)
1075         (compare:CC_NZ (match_operand:SI 0 "register_operand" "d,e,d")
1076                        (match_operand:SI 1 "arith_operand" "L,e,d")))]
1077   ""
1078   "@
1079    cmpi.c  %0, %c1
1080    cmp!    %0, %1
1081    cmp.c   %0, %1"
1082    [(set_attr "type" "cmp")
1083     (set_attr "up_c" "yes")
1084     (set_attr "mode" "SI")])
1085
1086 (define_insn "cmpsi_n"
1087   [(set (reg:CC_N CC_REGNUM)
1088         (compare:CC_N (match_operand:SI 0 "register_operand" "d,e,d")
1089                       (match_operand:SI 1 "arith_operand" "L,e,d")))]
1090   ""
1091   "@
1092    cmpi.c  %0, %c1
1093    cmp!    %0, %1
1094    cmp.c   %0, %1"
1095    [(set_attr "type" "cmp")
1096     (set_attr "up_c" "yes")
1097     (set_attr "mode" "SI")])
1098
1099 (define_insn "*cmpsi_to_addsi"
1100   [(set (reg:CC_NZ CC_REGNUM)
1101         (compare:CC_NZ (match_operand:SI 1 "register_operand" "0,d")
1102                        (neg:SI (match_operand:SI 2 "register_operand" "e,d"))))
1103    (clobber (match_scratch:SI 0 "=e,d"))]
1104   ""
1105   "@
1106    add!    %0, %2
1107    add.c   %0, %1, %2"
1108    [(set_attr "type" "cmp")
1109     (set_attr "up_c" "yes")
1110     (set_attr "mode" "SI")])
1111
1112 (define_insn "cmpsi_cc"
1113   [(set (reg:CC CC_REGNUM)
1114         (compare:CC (match_operand:SI 0 "register_operand" "d,e,d")
1115                     (match_operand:SI 1 "arith_operand" "L,e,d")))]
1116   ""
1117   "@
1118    cmpi.c  %0, %c1
1119    cmp!    %0, %1
1120    cmp.c   %0, %1"
1121   [(set_attr "type" "cmp")
1122    (set_attr "up_c" "yes")
1123    (set_attr "mode" "SI")])
1124
1125 (define_expand "beq"
1126   [(set (pc)
1127         (if_then_else (eq (reg:CC CC_REGNUM) (const_int 0))
1128                       (label_ref (match_operand 0 "" ""))
1129                       (pc)))]
1130   ""
1131 {
1132   mda_gen_cmp (CCmode);
1133 })
1134
1135 (define_expand "bne"
1136   [(set (pc)
1137         (if_then_else (ne (reg:CC CC_REGNUM) (const_int 0))
1138                       (label_ref (match_operand 0 "" ""))
1139                       (pc)))]
1140   ""
1141 {
1142   mda_gen_cmp (CCmode);
1143 })
1144
1145 (define_expand "bgt"
1146   [(set (pc)
1147         (if_then_else (gt (reg:CC CC_REGNUM) (const_int 0))
1148                       (label_ref (match_operand 0 "" ""))
1149                       (pc)))]
1150   ""
1151 {
1152   mda_gen_cmp (CCmode);
1153 })
1154
1155 (define_expand "ble"
1156   [(set (pc)
1157         (if_then_else (le (reg:CC CC_REGNUM) (const_int 0))
1158                       (label_ref (match_operand 0 "" ""))
1159                       (pc)))]
1160   ""
1161 {
1162   mda_gen_cmp (CCmode);
1163 })
1164
1165 (define_expand "bge"
1166   [(set (pc)
1167         (if_then_else (ge (reg:CC CC_REGNUM) (const_int 0))
1168                       (label_ref (match_operand 0 "" ""))
1169                       (pc)))]
1170   ""
1171 {
1172   mda_gen_cmp (CCmode);
1173 })
1174
1175 (define_expand "blt"
1176   [(set (pc)
1177         (if_then_else (lt (reg:CC CC_REGNUM) (const_int 0))
1178                       (label_ref (match_operand 0 "" ""))
1179                       (pc)))]
1180   ""
1181 {
1182   mda_gen_cmp (CCmode);
1183 })
1184
1185 (define_expand "bgtu"
1186   [(set (pc)
1187         (if_then_else (gtu (reg:CC CC_REGNUM) (const_int 0))
1188                       (label_ref (match_operand 0 "" ""))
1189                       (pc)))]
1190   ""
1191 {
1192   mda_gen_cmp (CCmode);
1193 })
1194
1195 (define_expand "bleu"
1196   [(set (pc)
1197         (if_then_else (leu (reg:CC CC_REGNUM) (const_int 0))
1198                       (label_ref (match_operand 0 "" ""))
1199                       (pc)))]
1200   ""
1201 {
1202   mda_gen_cmp (CCmode);
1203 })
1204
1205 (define_expand "bgeu"
1206   [(set (pc)
1207         (if_then_else (geu (reg:CC CC_REGNUM) (const_int 0))
1208                       (label_ref (match_operand 0 "" ""))
1209                       (pc)))]
1210   ""
1211 {
1212   mda_gen_cmp (CCmode);
1213 })
1214
1215 (define_expand "bltu"
1216   [(set (pc)
1217         (if_then_else (ltu (reg:CC CC_REGNUM) (const_int 0))
1218                       (label_ref (match_operand 0 "" ""))
1219                       (pc)))]
1220   ""
1221 {
1222   mda_gen_cmp (CCmode);
1223 })
1224
1225 (define_insn "branch_n"
1226   [(set (pc)
1227         (if_then_else
1228          (match_operator 0 "branch_n_operator"
1229                          [(reg:CC_N CC_REGNUM)
1230                           (const_int 0)])
1231          (label_ref (match_operand 1 "" ""))
1232          (pc)))]
1233   ""
1234   "b%C0    %1"
1235   [(set_attr "type" "branch")])
1236
1237 (define_insn "branch_nz"
1238   [(set (pc)
1239         (if_then_else
1240          (match_operator 0 "branch_nz_operator"
1241                          [(reg:CC_NZ CC_REGNUM)
1242                           (const_int 0)])
1243          (label_ref (match_operand 1 "" ""))
1244          (pc)))]
1245   ""
1246   "b%C0    %1"
1247   [(set_attr "type" "branch")])
1248
1249 (define_insn "branch_cc"
1250   [(set (pc)
1251         (if_then_else
1252          (match_operator 0 "comparison_operator"
1253                          [(reg:CC CC_REGNUM)
1254                           (const_int 0)])
1255          (label_ref (match_operand 1 "" ""))
1256          (pc)))]
1257   ""
1258   "b%C0    %1"
1259   [(set_attr "type" "branch")])
1260
1261 (define_insn "jump"
1262   [(set (pc)
1263         (label_ref (match_operand 0 "" "")))]
1264   ""
1265 {
1266   if (!flag_pic)
1267     return \"j      %0\";
1268   else
1269     return \"b      %0\";
1270 }
1271   [(set_attr "type" "jump")])
1272
1273 (define_expand "sibcall"
1274   [(parallel [(call (match_operand 0 "" "")
1275                     (match_operand 1 "" ""))
1276               (use (match_operand 2 "" ""))])]
1277   ""
1278 {
1279   mdx_call (operands, true);
1280   DONE;
1281 })
1282
1283 (define_insn "sibcall_internal"
1284   [(call (mem:SI (match_operand:SI 0 "call_insn_operand" "t,Z"))
1285          (match_operand 1 "" ""))
1286    (clobber (reg:SI RT_REGNUM))]
1287   "SIBLING_CALL_P (insn)"
1288 {
1289   if (!flag_pic)
1290     switch (which_alternative)
1291       {
1292       case 0: return \"br%S0   %0\";
1293       case 1: return \"j       %0\";
1294       default: gcc_unreachable ();
1295       }
1296   else
1297     switch (which_alternative)
1298       {
1299       case 0: return \"mv      r29, %0\;br      r29\";
1300       case 1: return \"la      r29, %0\;br      r29\";
1301       default: gcc_unreachable ();
1302       }
1303 }
1304   [(set_attr "type" "call")])
1305
1306 (define_expand "sibcall_value"
1307   [(parallel [(set (match_operand 0 "" "")
1308               (call (match_operand 1 "" "") (match_operand 2 "" "")))
1309               (use (match_operand 3 "" ""))])]
1310   ""
1311 {
1312   mdx_call_value (operands, true);
1313   DONE;
1314 })
1315
1316 (define_insn "sibcall_value_internal"
1317   [(set (match_operand 0 "register_operand" "=d,d")
1318         (call (mem:SI (match_operand:SI 1 "call_insn_operand" "t,Z"))
1319               (match_operand 2 "" "")))
1320    (clobber (reg:SI RT_REGNUM))]
1321   "SIBLING_CALL_P (insn)"
1322 {
1323   if (!flag_pic)
1324     switch (which_alternative)
1325       {
1326       case 0: return \"br%S1   %1\";
1327       case 1: return \"j       %1\";
1328       default: gcc_unreachable ();
1329       }
1330   else
1331     switch (which_alternative)
1332       {
1333       case 0: return \"mv      r29, %1\;br      r29\";
1334       case 1: return \"la      r29, %1\;br      r29\";
1335       default: gcc_unreachable ();
1336       }
1337 }
1338   [(set_attr "type" "call")])
1339
1340 (define_expand "call"
1341   [(parallel [(call (match_operand 0 "" "") (match_operand 1 "" ""))
1342               (use (match_operand 2 "" ""))])]
1343   ""
1344 {
1345   mdx_call (operands, false);
1346   DONE;
1347 })
1348
1349 (define_insn "call_internal"
1350   [(call (mem:SI (match_operand:SI 0 "call_insn_operand" "d,Z"))
1351          (match_operand 1 "" ""))
1352    (clobber (reg:SI RA_REGNUM))]
1353   ""
1354 {
1355   if (!flag_pic)
1356     switch (which_alternative)
1357       {
1358       case 0: return \"brl%S0  %0\";
1359       case 1: return \"jl      %0\";
1360       default: gcc_unreachable ();
1361       }
1362   else
1363      switch (which_alternative)
1364       {
1365       case 0: return \"mv      r29, %0\;brl     r29\";
1366       case 1: return \"la      r29, %0\;brl     r29\";
1367       default: gcc_unreachable ();
1368       }
1369 }
1370   [(set_attr "type" "call")])
1371
1372 (define_expand "call_value"
1373   [(parallel [(set (match_operand 0 "" "")
1374                    (call (match_operand 1 "" "") (match_operand 2 "" "")))
1375               (use (match_operand 3 "" ""))])]
1376   ""
1377 {
1378   mdx_call_value (operands, false);
1379   DONE;
1380 })
1381
1382 (define_insn "call_value_internal"
1383   [(set (match_operand 0 "register_operand" "=d,d")
1384         (call (mem:SI (match_operand:SI 1 "call_insn_operand" "d,Z"))
1385               (match_operand 2 "" "")))
1386    (clobber (reg:SI RA_REGNUM))]
1387   ""
1388 {
1389   if (!flag_pic)
1390     switch (which_alternative)
1391       {
1392       case 0: return \"brl%S1  %1\";
1393       case 1: return \"jl      %1\";
1394       default: gcc_unreachable ();
1395       }
1396   else
1397     switch (which_alternative)
1398       {
1399       case 0: return \"mv      r29, %1\;brl     r29\";
1400       case 1: return \"la      r29, %1\;brl     r29\";
1401       default: gcc_unreachable ();
1402       }
1403 }
1404   [(set_attr "type" "call")])
1405
1406 (define_expand "indirect_jump"
1407   [(set (pc) (match_operand 0 "register_operand" "d"))]
1408   ""
1409 {
1410   rtx dest;
1411   dest = operands[0];
1412   if (GET_CODE (dest) != REG
1413       || GET_MODE (dest) != Pmode)
1414     operands[0] = copy_to_mode_reg (Pmode, dest);
1415
1416   emit_jump_insn (gen_indirect_jump_internal1 (operands[0]));
1417   DONE;
1418 })
1419
1420 (define_insn "indirect_jump_internal1"
1421   [(set (pc) (match_operand:SI 0 "register_operand" "d"))]
1422   ""
1423   "br%S0   %0"
1424   [(set_attr "type" "jump")])
1425
1426 (define_expand "tablejump"
1427   [(set (pc)
1428         (match_operand 0 "register_operand" "d"))
1429    (use (label_ref (match_operand 1 "" "")))]
1430   ""
1431 {
1432   if (GET_MODE (operands[0]) != ptr_mode)
1433     gcc_unreachable ();
1434   emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
1435   DONE;
1436 })
1437
1438 (define_insn "tablejump_internal1"
1439   [(set (pc)
1440         (match_operand:SI 0 "register_operand" "d"))
1441    (use (label_ref (match_operand 1 "" "")))]
1442   ""
1443   "*
1444    if (flag_pic)
1445      return \"mv      r29, %0\;.cpadd  r29\;br      r29\";
1446    else
1447      return \"br%S0   %0\";
1448   "
1449   [(set_attr "type" "jump")])
1450
1451 (define_expand "prologue"
1452   [(const_int 1)]
1453   ""
1454 {
1455   mdx_prologue ();
1456   DONE;
1457 })
1458
1459 (define_expand "epilogue"
1460   [(const_int 2)]
1461   ""
1462 {
1463   mdx_epilogue (false);
1464   DONE;
1465 })
1466
1467 (define_expand "sibcall_epilogue"
1468   [(const_int 2)]
1469   ""
1470 {
1471   mdx_epilogue (true);
1472   DONE;
1473 })
1474
1475 (define_insn "return_internal"
1476   [(return)
1477    (use (match_operand 0 "pmode_register_operand" "d"))]
1478   ""
1479   "br%S0   %0")
1480
1481 (define_insn "nop"
1482   [(const_int 0)]
1483   ""
1484   "#nop!"
1485 )
1486
1487 (define_insn "cpload"
1488   [(unspec_volatile:SI [(const_int 1)] CPLOAD)]
1489   "flag_pic"
1490   ".cpload r29"
1491 )
1492
1493 (define_insn "cprestore_use_fp"
1494   [(unspec_volatile:SI [(match_operand:SI 0 "" "")] CPRESTORE)
1495    (use (reg:SI FP_REGNUM))]
1496   "flag_pic"
1497   ".cprestore r2, %0"
1498 )
1499
1500 (define_insn "cprestore_use_sp"
1501   [(unspec_volatile:SI [(match_operand:SI 0 "" "")] CPRESTORE)
1502    (use (reg:SI SP_REGNUM))]
1503   "flag_pic"
1504   ".cprestore r0, %0"
1505 )
1506
1507 (define_expand "doloop_end"
1508   [(use (match_operand 0 "" ""))    ; loop pseudo
1509    (use (match_operand 1 "" ""))    ; iterations; zero if unknown
1510    (use (match_operand 2 "" ""))    ; max iterations
1511    (use (match_operand 3 "" ""))    ; loop level
1512    (use (match_operand 4 "" ""))]   ; label
1513   "!TARGET_NHWLOOP"
1514   {
1515     if (INTVAL (operands[3]) > 1)
1516       FAIL;
1517
1518     if (GET_MODE (operands[0]) == SImode)
1519       {
1520         rtx sr0 = gen_rtx_REG (SImode, CN_REGNUM);
1521         emit_jump_insn (gen_doloop_end_si (sr0, operands[4]));
1522       }
1523     else
1524       FAIL;
1525
1526     DONE;
1527   })
1528
1529 (define_insn "doloop_end_si"
1530   [(set (pc)
1531         (if_then_else
1532          (ne (match_operand:SI 0 "sr0_operand" "")
1533              (const_int 0))
1534          (label_ref (match_operand 1 "" ""))
1535          (pc)))
1536    (set (match_dup 0)
1537         (plus:SI (match_dup 0)
1538                  (const_int -1)))
1539    (clobber (reg:CC CC_REGNUM))
1540 ]
1541   "!TARGET_NHWLOOP"
1542   "bcnz %1"
1543   [(set_attr "type" "branch")])