1 /* Output routines for GCC for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1997, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
28 #include "insn-config.h"
36 #include "hard-reg-set.h"
38 #include "insn-attr.h"
42 #include "integrate.h"
45 #include "target-def.h"
47 #include "langhooks.h"
48 #include "basic-block.h"
50 #include "cfglayout.h"
52 int code_for_indirect_jump_scratch
= CODE_FOR_indirect_jump_scratch
;
54 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
55 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
57 /* These are some macros to abstract register modes. */
58 #define CONST_OK_FOR_ADD(size) \
59 (TARGET_SHMEDIA ? CONST_OK_FOR_I10 (size) : CONST_OK_FOR_I08 (size))
60 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
61 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
62 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
64 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
65 int current_function_interrupt
;
67 /* ??? The pragma interrupt support will not work for SH3. */
68 /* This is set by #pragma interrupt and #pragma trapa, and causes gcc to
69 output code for the next function appropriate for an interrupt handler. */
72 /* This is set by the trap_exit attribute for functions. It specifies
73 a trap number to be used in a trapa instruction at function exit
74 (instead of an rte instruction). */
77 /* This is used by the sp_switch attribute for functions. It specifies
78 a variable holding the address of the stack the interrupt function
79 should switch to/from at entry/exit. */
82 /* This is set by #pragma trapa, and is similar to the above, except that
83 the compiler doesn't emit code to preserve all registers. */
84 static int pragma_trapa
;
86 /* This is set by #pragma nosave_low_regs. This is useful on the SH3,
87 which has a separate set of low regs for User and Supervisor modes.
88 This should only be used for the lowest level of interrupts. Higher levels
89 of interrupts must save the registers in case they themselves are
91 int pragma_nosave_low_regs
;
93 /* This is used for communication between SETUP_INCOMING_VARARGS and
94 sh_expand_prologue. */
95 int current_function_anonymous_args
;
97 /* Global variables for machine-dependent things. */
99 /* Which cpu are we scheduling for. */
100 enum processor_type sh_cpu
;
102 /* Saved operands from the last compare to use when we generate an scc
108 /* Provides the class number of the smallest class containing
111 enum reg_class regno_reg_class
[FIRST_PSEUDO_REGISTER
] =
113 R0_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
114 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
115 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
116 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
117 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
118 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
119 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
120 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
121 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
122 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
123 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
124 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
125 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
126 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
127 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
128 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
129 FP0_REGS
,FP_REGS
, FP_REGS
, FP_REGS
,
130 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
131 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
132 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
133 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
134 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
135 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
136 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
137 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
138 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
139 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
140 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
141 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
142 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
143 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
144 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
145 TARGET_REGS
, TARGET_REGS
, TARGET_REGS
, TARGET_REGS
,
146 TARGET_REGS
, TARGET_REGS
, TARGET_REGS
, TARGET_REGS
,
147 DF_REGS
, DF_REGS
, DF_REGS
, DF_REGS
,
148 DF_REGS
, DF_REGS
, DF_REGS
, DF_REGS
,
149 NO_REGS
, GENERAL_REGS
, PR_REGS
, T_REGS
,
150 MAC_REGS
, MAC_REGS
, FPUL_REGS
, FPSCR_REGS
,
154 char sh_register_names
[FIRST_PSEUDO_REGISTER
] \
155 [MAX_REGISTER_NAME_LENGTH
+ 1] = SH_REGISTER_NAMES_INITIALIZER
;
157 char sh_additional_register_names
[ADDREGNAMES_SIZE
] \
158 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH
+ 1]
159 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER
;
161 /* Provide reg_class from a letter such as appears in the machine
162 description. *: target independently reserved letter.
163 reg_class_from_letter['e' - 'a'] is set to NO_REGS for TARGET_FMOVD. */
165 enum reg_class reg_class_from_letter
[] =
167 /* a */ ALL_REGS
, /* b */ TARGET_REGS
, /* c */ FPSCR_REGS
, /* d */ DF_REGS
,
168 /* e */ FP_REGS
, /* f */ FP_REGS
, /* g **/ NO_REGS
, /* h */ NO_REGS
,
169 /* i **/ NO_REGS
, /* j */ NO_REGS
, /* k */ SIBCALL_REGS
, /* l */ PR_REGS
,
170 /* m **/ NO_REGS
, /* n **/ NO_REGS
, /* o **/ NO_REGS
, /* p **/ NO_REGS
,
171 /* q */ NO_REGS
, /* r **/ NO_REGS
, /* s **/ NO_REGS
, /* t */ T_REGS
,
172 /* u */ NO_REGS
, /* v */ NO_REGS
, /* w */ FP0_REGS
, /* x */ MAC_REGS
,
173 /* y */ FPUL_REGS
, /* z */ R0_REGS
176 int assembler_dialect
;
178 static bool shmedia_space_reserved_for_target_registers
;
180 static void split_branches
PARAMS ((rtx
));
181 static int branch_dest
PARAMS ((rtx
));
182 static void force_into
PARAMS ((rtx
, rtx
));
183 static void print_slot
PARAMS ((rtx
));
184 static rtx add_constant
PARAMS ((rtx
, enum machine_mode
, rtx
));
185 static void dump_table
PARAMS ((rtx
));
186 static int hi_const
PARAMS ((rtx
));
187 static int broken_move
PARAMS ((rtx
));
188 static int mova_p
PARAMS ((rtx
));
189 static rtx find_barrier
PARAMS ((int, rtx
, rtx
));
190 static int noncall_uses_reg
PARAMS ((rtx
, rtx
, rtx
*));
191 static rtx gen_block_redirect
PARAMS ((rtx
, int, int));
192 static void sh_reorg
PARAMS ((void));
193 static void output_stack_adjust (int, rtx
, int, HARD_REG_SET
*);
194 static rtx frame_insn
PARAMS ((rtx
));
195 static rtx push
PARAMS ((int));
196 static void pop
PARAMS ((int));
197 static void push_regs
PARAMS ((HARD_REG_SET
*, int));
198 static int calc_live_regs
PARAMS ((HARD_REG_SET
*));
199 static void mark_use
PARAMS ((rtx
, rtx
*));
200 static HOST_WIDE_INT rounded_frame_size
PARAMS ((int));
201 static rtx mark_constant_pool_use
PARAMS ((rtx
));
202 const struct attribute_spec sh_attribute_table
[];
203 static tree sh_handle_interrupt_handler_attribute
PARAMS ((tree
*, tree
, tree
, int, bool *));
204 static tree sh_handle_sp_switch_attribute
PARAMS ((tree
*, tree
, tree
, int, bool *));
205 static tree sh_handle_trap_exit_attribute
PARAMS ((tree
*, tree
, tree
, int, bool *));
206 static tree sh_handle_renesas_attribute
PARAMS ((tree
*, tree
, tree
, int, bool *));
207 static void sh_output_function_epilogue
PARAMS ((FILE *, HOST_WIDE_INT
));
208 static void sh_insert_attributes
PARAMS ((tree
, tree
*));
209 static int sh_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
210 static int sh_use_dfa_interface
PARAMS ((void));
211 static int sh_issue_rate
PARAMS ((void));
212 static bool sh_function_ok_for_sibcall
PARAMS ((tree
, tree
));
214 static bool sh_cannot_modify_jumps_p
PARAMS ((void));
215 static int sh_target_reg_class (void);
216 static bool sh_optimize_target_register_callee_saved (bool);
217 static bool sh_ms_bitfield_layout_p
PARAMS ((tree
));
219 static void sh_init_builtins
PARAMS ((void));
220 static void sh_media_init_builtins
PARAMS ((void));
221 static rtx sh_expand_builtin
PARAMS ((tree
, rtx
, rtx
, enum machine_mode
, int));
222 static void sh_output_mi_thunk
PARAMS ((FILE *, tree
, HOST_WIDE_INT
,
223 HOST_WIDE_INT
, tree
));
224 static void sh_file_start
PARAMS ((void));
225 static int flow_dependent_p
PARAMS ((rtx
, rtx
));
226 static void flow_dependent_p_1
PARAMS ((rtx
, rtx
, void *));
227 static int shiftcosts
PARAMS ((rtx
));
228 static int andcosts
PARAMS ((rtx
));
229 static int addsubcosts
PARAMS ((rtx
));
230 static int multcosts
PARAMS ((rtx
));
231 static bool unspec_caller_rtx_p
PARAMS ((rtx
));
232 static bool sh_cannot_copy_insn_p
PARAMS ((rtx
));
233 static bool sh_rtx_costs
PARAMS ((rtx
, int, int, int *));
234 static int sh_address_cost
PARAMS ((rtx
));
235 static int shmedia_target_regs_stack_space (HARD_REG_SET
*);
236 static int shmedia_reserve_space_for_target_registers_p (int, HARD_REG_SET
*);
237 static int shmedia_target_regs_stack_adjust (HARD_REG_SET
*);
238 static int scavenge_reg (HARD_REG_SET
*s
);
239 struct save_schedule_s
;
240 static struct save_entry_s
*sh5_schedule_saves (HARD_REG_SET
*,
241 struct save_schedule_s
*, int);
243 static bool sh_promote_prototypes
PARAMS ((tree
));
244 static rtx sh_struct_value_rtx
PARAMS ((tree
, int));
245 static bool sh_return_in_memory
PARAMS ((tree
, tree
));
246 static rtx sh_builtin_saveregs
PARAMS ((void));
247 static void sh_setup_incoming_varargs
PARAMS ((CUMULATIVE_ARGS
*, enum machine_mode
, tree
, int *, int));
248 static bool sh_strict_argument_naming
PARAMS ((CUMULATIVE_ARGS
*));
249 static bool sh_pretend_outgoing_varargs_named
PARAMS ((CUMULATIVE_ARGS
*));
252 /* Initialize the GCC target structure. */
253 #undef TARGET_ATTRIBUTE_TABLE
254 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
256 /* The next two are used for debug info when compiling with -gdwarf. */
257 #undef TARGET_ASM_UNALIGNED_HI_OP
258 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
259 #undef TARGET_ASM_UNALIGNED_SI_OP
260 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
262 /* These are NULLed out on non-SH5 in OVERRIDE_OPTIONS. */
263 #undef TARGET_ASM_UNALIGNED_DI_OP
264 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
265 #undef TARGET_ASM_ALIGNED_DI_OP
266 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
268 #undef TARGET_ASM_FUNCTION_EPILOGUE
269 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
271 #undef TARGET_ASM_OUTPUT_MI_THUNK
272 #define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
274 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
275 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
277 #undef TARGET_ASM_FILE_START
278 #define TARGET_ASM_FILE_START sh_file_start
279 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
280 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
282 #undef TARGET_INSERT_ATTRIBUTES
283 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
285 #undef TARGET_SCHED_ADJUST_COST
286 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
288 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
289 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
291 #undef TARGET_SCHED_ISSUE_RATE
292 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
294 #undef TARGET_CANNOT_MODIFY_JUMPS_P
295 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
296 #undef TARGET_BRANCH_TARGET_REGISTER_CLASS
297 #define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class
298 #undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
299 #define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \
300 sh_optimize_target_register_callee_saved
302 #undef TARGET_MS_BITFIELD_LAYOUT_P
303 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
305 #undef TARGET_INIT_BUILTINS
306 #define TARGET_INIT_BUILTINS sh_init_builtins
307 #undef TARGET_EXPAND_BUILTIN
308 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
310 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
311 #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
313 #undef TARGET_CANNOT_COPY_INSN_P
314 #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
315 #undef TARGET_RTX_COSTS
316 #define TARGET_RTX_COSTS sh_rtx_costs
317 #undef TARGET_ADDRESS_COST
318 #define TARGET_ADDRESS_COST sh_address_cost
320 #undef TARGET_MACHINE_DEPENDENT_REORG
321 #define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
324 #undef TARGET_HAVE_TLS
325 #define TARGET_HAVE_TLS true
328 #undef TARGET_PROMOTE_PROTOTYPES
329 #define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes
330 #undef TARGET_PROMOTE_FUNCTION_ARGS
331 #define TARGET_PROMOTE_FUNCTION_ARGS sh_promote_prototypes
332 #undef TARGET_PROMOTE_FUNCTION_RETURN
333 #define TARGET_PROMOTE_FUNCTION_RETURN sh_promote_prototypes
335 #undef TARGET_STRUCT_VALUE_RTX
336 #define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx
337 #undef TARGET_RETURN_IN_MEMORY
338 #define TARGET_RETURN_IN_MEMORY sh_return_in_memory
340 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
341 #define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs
342 #undef TARGET_SETUP_INCOMING_VARARGS
343 #define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs
344 #undef TARGET_STRICT_ARGUMENT_NAMING
345 #define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming
346 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
347 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named
349 struct gcc_target targetm
= TARGET_INITIALIZER
;
351 /* Print the operand address in x to the stream. */
354 print_operand_address (stream
, x
)
358 switch (GET_CODE (x
))
362 fprintf (stream
, "@%s", reg_names
[true_regnum (x
)]);
367 rtx base
= XEXP (x
, 0);
368 rtx index
= XEXP (x
, 1);
370 switch (GET_CODE (index
))
373 fprintf (stream
, "@(%d,%s)", (int) INTVAL (index
),
374 reg_names
[true_regnum (base
)]);
380 int base_num
= true_regnum (base
);
381 int index_num
= true_regnum (index
);
383 fprintf (stream
, "@(r0,%s)",
384 reg_names
[MAX (base_num
, index_num
)]);
396 fprintf (stream
, "@-%s", reg_names
[true_regnum (XEXP (x
, 0))]);
400 fprintf (stream
, "@%s+", reg_names
[true_regnum (XEXP (x
, 0))]);
404 x
= mark_constant_pool_use (x
);
405 output_addr_const (stream
, x
);
410 /* Print operand x (an rtx) in assembler syntax to file stream
411 according to modifier code.
413 '.' print a .s if insn needs delay slot
414 ',' print LOCAL_LABEL_PREFIX
415 '@' print trap, rte or rts depending upon pragma interruptness
416 '#' output a nop if there is nothing to put in the delay slot
417 ''' print likelihood suffix (/u for unlikely).
418 'O' print a constant without the #
419 'R' print the LSW of a dp value - changes if in little endian
420 'S' print the MSW of a dp value - changes if in little endian
421 'T' print the next word of a dp value - same as 'R' in big endian mode.
422 'M' print an `x' if `m' will print `base,index'.
423 'N' print 'r63' if the operand is (const_int 0).
424 'm' print a pair `base,offset' or `base,index', for LD and ST.
425 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
426 'o' output an operator. */
429 print_operand (stream
, x
, code
)
438 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence
, 0, 0))
439 && get_attr_length (XVECEXP (final_sequence
, 0, 1)))
440 fprintf (stream
, ASSEMBLER_DIALECT
? "/s" : ".s");
443 fprintf (stream
, "%s", LOCAL_LABEL_PREFIX
);
447 fprintf (stream
, "trapa #%d", trap_exit
);
448 else if (sh_cfun_interrupt_handler_p ())
449 fprintf (stream
, "rte");
451 fprintf (stream
, "rts");
454 /* Output a nop if there's nothing in the delay slot. */
455 if (dbr_sequence_length () == 0)
456 fprintf (stream
, "\n\tnop");
460 rtx note
= find_reg_note (current_output_insn
, REG_BR_PROB
, 0);
462 if (note
&& INTVAL (XEXP (note
, 0)) * 2 < REG_BR_PROB_BASE
)
463 fputs ("/u", stream
);
467 x
= mark_constant_pool_use (x
);
468 output_addr_const (stream
, x
);
471 fputs (reg_names
[REGNO (x
) + LSW
], (stream
));
474 fputs (reg_names
[REGNO (x
) + MSW
], (stream
));
477 /* Next word of a double. */
478 switch (GET_CODE (x
))
481 fputs (reg_names
[REGNO (x
) + 1], (stream
));
484 if (GET_CODE (XEXP (x
, 0)) != PRE_DEC
485 && GET_CODE (XEXP (x
, 0)) != POST_INC
)
486 x
= adjust_address (x
, SImode
, 4);
487 print_operand_address (stream
, XEXP (x
, 0));
494 switch (GET_CODE (x
))
496 case PLUS
: fputs ("add", stream
); break;
497 case MINUS
: fputs ("sub", stream
); break;
498 case MULT
: fputs ("mul", stream
); break;
499 case DIV
: fputs ("div", stream
); break;
500 case EQ
: fputs ("eq", stream
); break;
501 case NE
: fputs ("ne", stream
); break;
502 case GT
: case LT
: fputs ("gt", stream
); break;
503 case GE
: case LE
: fputs ("ge", stream
); break;
504 case GTU
: case LTU
: fputs ("gtu", stream
); break;
505 case GEU
: case LEU
: fputs ("geu", stream
); break;
511 if (GET_CODE (x
) == MEM
512 && GET_CODE (XEXP (x
, 0)) == PLUS
513 && (GET_CODE (XEXP (XEXP (x
, 0), 1)) == REG
514 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == SUBREG
))
519 if (GET_CODE (x
) != MEM
)
522 switch (GET_CODE (x
))
526 print_operand (stream
, x
, 0);
527 fputs (", 0", stream
);
531 print_operand (stream
, XEXP (x
, 0), 0);
532 fputs (", ", stream
);
533 print_operand (stream
, XEXP (x
, 1), 0);
542 if (x
== CONST0_RTX (GET_MODE (x
)))
544 fprintf ((stream
), "r63");
549 if (GET_CODE (x
) == CONST_INT
)
551 fprintf ((stream
), "%u", (unsigned) INTVAL (x
) & (0x10000 - 1));
558 switch (GET_CODE (x
))
560 /* FIXME: We need this on SHmedia32 because reload generates
561 some sign-extended HI or QI loads into DImode registers
562 but, because Pmode is SImode, the address ends up with a
563 subreg:SI of the DImode register. Maybe reload should be
564 fixed so as to apply alter_subreg to such loads? */
566 if (SUBREG_BYTE (x
) != 0
567 || GET_CODE (SUBREG_REG (x
)) != REG
)
574 if (FP_REGISTER_P (REGNO (x
))
575 && GET_MODE (x
) == V16SFmode
)
576 fprintf ((stream
), "mtrx%s", reg_names
[REGNO (x
)] + 2);
577 else if (FP_REGISTER_P (REGNO (x
))
578 && GET_MODE (x
) == V4SFmode
)
579 fprintf ((stream
), "fv%s", reg_names
[REGNO (x
)] + 2);
580 else if (GET_CODE (x
) == REG
581 && GET_MODE (x
) == V2SFmode
)
582 fprintf ((stream
), "fp%s", reg_names
[REGNO (x
)] + 2);
583 else if (FP_REGISTER_P (REGNO (x
))
584 && GET_MODE_SIZE (GET_MODE (x
)) > 4)
585 fprintf ((stream
), "d%s", reg_names
[REGNO (x
)] + 1);
587 fputs (reg_names
[REGNO (x
)], (stream
));
591 output_address (XEXP (x
, 0));
596 && GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
597 && GET_MODE (XEXP (x
, 0)) == DImode
598 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == TRUNCATE
599 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == HImode
)
601 rtx val
= XEXP (XEXP (XEXP (x
, 0), 0), 0);
604 if (GET_CODE (val
) == ASHIFTRT
)
607 if (GET_CODE (XEXP (val
, 0)) == CONST
)
609 output_addr_const (stream
, XEXP (val
, 0));
610 if (GET_CODE (XEXP (val
, 0)) == CONST
)
612 fputs (" >> ", stream
);
613 output_addr_const (stream
, XEXP (val
, 1));
618 if (GET_CODE (val
) == CONST
)
620 output_addr_const (stream
, val
);
621 if (GET_CODE (val
) == CONST
)
624 fputs (" & 65535)", stream
);
632 output_addr_const (stream
, x
);
639 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
641 force_into (value
, target
)
644 value
= force_operand (value
, target
);
645 if (! rtx_equal_p (value
, target
))
646 emit_insn (gen_move_insn (target
, value
));
649 /* Emit code to perform a block move. Choose the best method.
651 OPERANDS[0] is the destination.
652 OPERANDS[1] is the source.
653 OPERANDS[2] is the size.
654 OPERANDS[3] is the alignment safe to use. */
657 expand_block_move (operands
)
660 int align
= INTVAL (operands
[3]);
661 int constp
= (GET_CODE (operands
[2]) == CONST_INT
);
662 int bytes
= (constp
? INTVAL (operands
[2]) : 0);
664 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
665 alignment, or if it isn't a multiple of 4 bytes, then fail. */
666 if (! constp
|| align
< 4 || (bytes
% 4 != 0))
673 else if (bytes
== 12)
678 rtx r4
= gen_rtx (REG
, SImode
, 4);
679 rtx r5
= gen_rtx (REG
, SImode
, 5);
681 entry_name
= get_identifier ("__movstrSI12_i4");
683 sym
= function_symbol (IDENTIFIER_POINTER (entry_name
));
684 func_addr_rtx
= copy_to_mode_reg (Pmode
, sym
);
685 force_into (XEXP (operands
[0], 0), r4
);
686 force_into (XEXP (operands
[1], 0), r5
);
687 emit_insn (gen_block_move_real_i4 (func_addr_rtx
));
690 else if (! TARGET_SMALLCODE
)
696 rtx r4
= gen_rtx (REG
, SImode
, 4);
697 rtx r5
= gen_rtx (REG
, SImode
, 5);
698 rtx r6
= gen_rtx (REG
, SImode
, 6);
700 entry_name
= get_identifier (bytes
& 4
702 : "__movstr_i4_even");
703 sym
= function_symbol (IDENTIFIER_POINTER (entry_name
));
704 func_addr_rtx
= copy_to_mode_reg (Pmode
, sym
);
705 force_into (XEXP (operands
[0], 0), r4
);
706 force_into (XEXP (operands
[1], 0), r5
);
709 emit_insn (gen_move_insn (r6
, GEN_INT (dwords
- 1)));
710 emit_insn (gen_block_lump_real_i4 (func_addr_rtx
));
722 rtx r4
= gen_rtx_REG (SImode
, 4);
723 rtx r5
= gen_rtx_REG (SImode
, 5);
725 sprintf (entry
, "__movstrSI%d", bytes
);
726 entry_name
= get_identifier (entry
);
727 sym
= function_symbol (IDENTIFIER_POINTER (entry_name
));
728 func_addr_rtx
= copy_to_mode_reg (Pmode
, sym
);
729 force_into (XEXP (operands
[0], 0), r4
);
730 force_into (XEXP (operands
[1], 0), r5
);
731 emit_insn (gen_block_move_real (func_addr_rtx
));
735 /* This is the same number of bytes as a memcpy call, but to a different
736 less common function name, so this will occasionally use more space. */
737 if (! TARGET_SMALLCODE
)
742 int final_switch
, while_loop
;
743 rtx r4
= gen_rtx_REG (SImode
, 4);
744 rtx r5
= gen_rtx_REG (SImode
, 5);
745 rtx r6
= gen_rtx_REG (SImode
, 6);
747 entry_name
= get_identifier ("__movstr");
748 sym
= function_symbol (IDENTIFIER_POINTER (entry_name
));
749 func_addr_rtx
= copy_to_mode_reg (Pmode
, sym
);
750 force_into (XEXP (operands
[0], 0), r4
);
751 force_into (XEXP (operands
[1], 0), r5
);
753 /* r6 controls the size of the move. 16 is decremented from it
754 for each 64 bytes moved. Then the negative bit left over is used
755 as an index into a list of move instructions. e.g., a 72 byte move
756 would be set up with size(r6) = 14, for one iteration through the
757 big while loop, and a switch of -2 for the last part. */
759 final_switch
= 16 - ((bytes
/ 4) % 16);
760 while_loop
= ((bytes
/ 4) / 16 - 1) * 16;
761 emit_insn (gen_move_insn (r6
, GEN_INT (while_loop
+ final_switch
)));
762 emit_insn (gen_block_lump_real (func_addr_rtx
));
769 /* Prepare operands for a move define_expand; specifically, one of the
770 operands must be in a register. */
773 prepare_move_operands (operands
, mode
)
775 enum machine_mode mode
;
777 if ((mode
== SImode
|| mode
== DImode
)
779 && ! ((mode
== Pmode
|| mode
== ptr_mode
)
780 && tls_symbolic_operand (operands
[1], Pmode
) != 0))
783 if (SYMBOLIC_CONST_P (operands
[1]))
785 if (GET_CODE (operands
[0]) == MEM
)
786 operands
[1] = force_reg (Pmode
, operands
[1]);
787 else if (TARGET_SHMEDIA
788 && GET_CODE (operands
[1]) == LABEL_REF
789 && target_reg_operand (operands
[0], mode
))
793 temp
= no_new_pseudos
? operands
[0] : gen_reg_rtx (Pmode
);
794 operands
[1] = legitimize_pic_address (operands
[1], mode
, temp
);
797 else if (GET_CODE (operands
[1]) == CONST
798 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
799 && SYMBOLIC_CONST_P (XEXP (XEXP (operands
[1], 0), 0)))
801 temp
= no_new_pseudos
? operands
[0] : gen_reg_rtx (Pmode
);
802 temp
= legitimize_pic_address (XEXP (XEXP (operands
[1], 0), 0),
804 operands
[1] = expand_binop (mode
, add_optab
, temp
,
805 XEXP (XEXP (operands
[1], 0), 1),
806 no_new_pseudos
? temp
807 : gen_reg_rtx (Pmode
),
812 if (! reload_in_progress
&& ! reload_completed
)
814 /* Copy the source to a register if both operands aren't registers. */
815 if (! register_operand (operands
[0], mode
)
816 && ! sh_register_operand (operands
[1], mode
))
817 operands
[1] = copy_to_mode_reg (mode
, operands
[1]);
819 if (GET_CODE (operands
[0]) == MEM
&& ! memory_operand (operands
[0], mode
))
821 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
822 except that we can't use that function because it is static. */
823 rtx
new = change_address (operands
[0], mode
, 0);
824 MEM_COPY_ATTRIBUTES (new, operands
[0]);
828 /* This case can happen while generating code to move the result
829 of a library call to the target. Reject `st r0,@(rX,rY)' because
830 reload will fail to find a spill register for rX, since r0 is already
831 being used for the source. */
832 else if (refers_to_regno_p (R0_REG
, R0_REG
+ 1, operands
[1], (rtx
*)0)
833 && GET_CODE (operands
[0]) == MEM
834 && GET_CODE (XEXP (operands
[0], 0)) == PLUS
835 && GET_CODE (XEXP (XEXP (operands
[0], 0), 1)) == REG
)
836 operands
[1] = copy_to_mode_reg (mode
, operands
[1]);
839 if (mode
== Pmode
|| mode
== ptr_mode
)
842 enum tls_model tls_kind
;
846 if ((tls_kind
= tls_symbolic_operand (op1
, Pmode
)))
848 rtx tga_op1
, tga_ret
, tmp
, tmp2
;
853 case TLS_MODEL_GLOBAL_DYNAMIC
:
854 tga_ret
= gen_rtx_REG (Pmode
, R0_REG
);
855 emit_insn (gen_tls_global_dynamic (tga_ret
, op1
));
859 case TLS_MODEL_LOCAL_DYNAMIC
:
860 tga_ret
= gen_rtx_REG (Pmode
, R0_REG
);
861 emit_insn (gen_tls_local_dynamic (tga_ret
, op1
));
863 tmp
= gen_reg_rtx (Pmode
);
864 emit_move_insn (tmp
, tga_ret
);
866 if (register_operand (op0
, Pmode
))
869 tmp2
= gen_reg_rtx (Pmode
);
871 emit_insn (gen_symDTPOFF2reg (tmp2
, op1
, tmp
));
875 case TLS_MODEL_INITIAL_EXEC
:
877 emit_insn (gen_GOTaddr2picreg ());
878 tga_op1
= gen_reg_rtx (Pmode
);
879 tmp
= gen_sym2GOTTPOFF (op1
);
880 emit_insn (gen_tls_initial_exec (tga_op1
, tmp
));
884 case TLS_MODEL_LOCAL_EXEC
:
885 tmp2
= gen_reg_rtx (Pmode
);
886 emit_insn (gen_load_gbr (tmp2
));
887 tmp
= gen_reg_rtx (Pmode
);
888 emit_insn (gen_symTPOFF2reg (tmp
, op1
));
889 RTX_UNCHANGING_P (tmp
) = 1;
891 if (register_operand (op0
, Pmode
))
894 op1
= gen_reg_rtx (Pmode
);
896 emit_insn (gen_addsi3 (op1
, tmp
, tmp2
));
909 /* Prepare the operands for an scc instruction; make sure that the
910 compare has been done. */
912 prepare_scc_operands (code
)
915 rtx t_reg
= gen_rtx_REG (SImode
, T_REG
);
916 enum rtx_code oldcode
= code
;
917 enum machine_mode mode
;
919 /* First need a compare insn. */
923 /* It isn't possible to handle this case. */
942 rtx tmp
= sh_compare_op0
;
943 sh_compare_op0
= sh_compare_op1
;
944 sh_compare_op1
= tmp
;
947 mode
= GET_MODE (sh_compare_op0
);
948 if (mode
== VOIDmode
)
949 mode
= GET_MODE (sh_compare_op1
);
951 sh_compare_op0
= force_reg (mode
, sh_compare_op0
);
952 if ((code
!= EQ
&& code
!= NE
953 && (sh_compare_op1
!= const0_rtx
954 || code
== GTU
|| code
== GEU
|| code
== LTU
|| code
== LEU
))
955 || (mode
== DImode
&& sh_compare_op1
!= const0_rtx
)
956 || (TARGET_SH2E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
))
957 sh_compare_op1
= force_reg (mode
, sh_compare_op1
);
959 if (TARGET_SH4
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
960 (mode
== SFmode
? emit_sf_insn
: emit_df_insn
)
961 (gen_rtx (PARALLEL
, VOIDmode
, gen_rtvec (2,
962 gen_rtx (SET
, VOIDmode
, t_reg
,
963 gen_rtx (code
, SImode
,
964 sh_compare_op0
, sh_compare_op1
)),
965 gen_rtx (USE
, VOIDmode
, get_fpscr_rtx ()))));
967 emit_insn (gen_rtx (SET
, VOIDmode
, t_reg
,
968 gen_rtx (code
, SImode
, sh_compare_op0
,
974 /* Called from the md file, set up the operands of a compare instruction. */
977 from_compare (operands
, code
)
981 enum machine_mode mode
= GET_MODE (sh_compare_op0
);
983 if (mode
== VOIDmode
)
984 mode
= GET_MODE (sh_compare_op1
);
987 || (TARGET_SH2E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
))
989 /* Force args into regs, since we can't use constants here. */
990 sh_compare_op0
= force_reg (mode
, sh_compare_op0
);
991 if (sh_compare_op1
!= const0_rtx
992 || code
== GTU
|| code
== GEU
993 || (TARGET_SH2E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
))
994 sh_compare_op1
= force_reg (mode
, sh_compare_op1
);
996 if (TARGET_SH2E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
&& code
== GE
)
998 from_compare (operands
, GT
);
999 insn
= gen_ieee_ccmpeqsf_t (sh_compare_op0
, sh_compare_op1
);
1002 insn
= gen_rtx_SET (VOIDmode
,
1003 gen_rtx_REG (SImode
, T_REG
),
1004 gen_rtx (code
, SImode
, sh_compare_op0
,
1006 if (TARGET_SH4
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1008 insn
= gen_rtx (PARALLEL
, VOIDmode
,
1010 gen_rtx (USE
, VOIDmode
, get_fpscr_rtx ())));
1011 (mode
== SFmode
? emit_sf_insn
: emit_df_insn
) (insn
);
1017 /* Functions to output assembly code. */
1019 /* Return a sequence of instructions to perform DI or DF move.
1021 Since the SH cannot move a DI or DF in one instruction, we have
1022 to take care when we see overlapping source and dest registers. */
1025 output_movedouble (insn
, operands
, mode
)
1026 rtx insn ATTRIBUTE_UNUSED
;
1028 enum machine_mode mode
;
1030 rtx dst
= operands
[0];
1031 rtx src
= operands
[1];
1033 if (GET_CODE (dst
) == MEM
1034 && GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
1035 return "mov.l %T1,%0\n\tmov.l %1,%0";
1037 if (register_operand (dst
, mode
)
1038 && register_operand (src
, mode
))
1040 if (REGNO (src
) == MACH_REG
)
1041 return "sts mach,%S0\n\tsts macl,%R0";
1043 /* When mov.d r1,r2 do r2->r3 then r1->r2;
1044 when mov.d r1,r0 do r1->r0 then r2->r1. */
1046 if (REGNO (src
) + 1 == REGNO (dst
))
1047 return "mov %T1,%T0\n\tmov %1,%0";
1049 return "mov %1,%0\n\tmov %T1,%T0";
1051 else if (GET_CODE (src
) == CONST_INT
)
1053 if (INTVAL (src
) < 0)
1054 output_asm_insn ("mov #-1,%S0", operands
);
1056 output_asm_insn ("mov #0,%S0", operands
);
1058 return "mov %1,%R0";
1060 else if (GET_CODE (src
) == MEM
)
1063 int dreg
= REGNO (dst
);
1064 rtx inside
= XEXP (src
, 0);
1066 if (GET_CODE (inside
) == REG
)
1067 ptrreg
= REGNO (inside
);
1068 else if (GET_CODE (inside
) == SUBREG
)
1069 ptrreg
= subreg_regno (inside
);
1070 else if (GET_CODE (inside
) == PLUS
)
1072 ptrreg
= REGNO (XEXP (inside
, 0));
1073 /* ??? A r0+REG address shouldn't be possible here, because it isn't
1074 an offsettable address. Unfortunately, offsettable addresses use
1075 QImode to check the offset, and a QImode offsettable address
1076 requires r0 for the other operand, which is not currently
1077 supported, so we can't use the 'o' constraint.
1078 Thus we must check for and handle r0+REG addresses here.
1079 We punt for now, since this is likely very rare. */
1080 if (GET_CODE (XEXP (inside
, 1)) == REG
)
1083 else if (GET_CODE (inside
) == LABEL_REF
)
1084 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
1085 else if (GET_CODE (inside
) == POST_INC
)
1086 return "mov.l %1,%0\n\tmov.l %1,%T0";
1090 /* Work out the safe way to copy. Copy into the second half first. */
1092 return "mov.l %T1,%T0\n\tmov.l %1,%0";
1095 return "mov.l %1,%0\n\tmov.l %T1,%T0";
1098 /* Print an instruction which would have gone into a delay slot after
1099 another instruction, but couldn't because the other instruction expanded
1100 into a sequence where putting the slot insn at the end wouldn't work. */
1106 final_scan_insn (XVECEXP (insn
, 0, 1), asm_out_file
, optimize
, 0, 1);
1108 INSN_DELETED_P (XVECEXP (insn
, 0, 1)) = 1;
1112 output_far_jump (insn
, op
)
1116 struct { rtx lab
, reg
, op
; } this;
1117 rtx braf_base_lab
= NULL_RTX
;
1120 int offset
= branch_dest (insn
) - INSN_ADDRESSES (INSN_UID (insn
));
1123 this.lab
= gen_label_rtx ();
1127 && offset
- get_attr_length (insn
) <= 32766)
1130 jump
= "mov.w %O0,%1; braf %1";
1138 jump
= "mov.l %O0,%1; braf %1";
1140 jump
= "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
1143 jump
= "mov.l %O0,%1; jmp @%1";
1145 /* If we have a scratch register available, use it. */
1146 if (GET_CODE ((prev
= prev_nonnote_insn (insn
))) == INSN
1147 && INSN_CODE (prev
) == CODE_FOR_indirect_jump_scratch
)
1149 this.reg
= SET_DEST (XVECEXP (PATTERN (prev
), 0, 0));
1150 if (REGNO (this.reg
) == R0_REG
&& flag_pic
&& ! TARGET_SH2
)
1151 jump
= "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
1152 output_asm_insn (jump
, &this.lab
);
1153 if (dbr_sequence_length ())
1154 print_slot (final_sequence
);
1156 output_asm_insn ("nop", 0);
1160 /* Output the delay slot insn first if any. */
1161 if (dbr_sequence_length ())
1162 print_slot (final_sequence
);
1164 this.reg
= gen_rtx_REG (SImode
, 13);
1165 /* We must keep the stack aligned to 8-byte boundaries on SH5.
1166 Fortunately, MACL is fixed and call-clobbered, and we never
1167 need its value across jumps, so save r13 in it instead of in
1170 output_asm_insn ("lds r13, macl", 0);
1172 output_asm_insn ("mov.l r13,@-r15", 0);
1173 output_asm_insn (jump
, &this.lab
);
1175 output_asm_insn ("sts macl, r13", 0);
1177 output_asm_insn ("mov.l @r15+,r13", 0);
1179 if (far
&& flag_pic
&& TARGET_SH2
)
1181 braf_base_lab
= gen_label_rtx ();
1182 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1183 CODE_LABEL_NUMBER (braf_base_lab
));
1186 output_asm_insn (".align 2", 0);
1187 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (this.lab
));
1189 if (far
&& flag_pic
)
1192 this.lab
= braf_base_lab
;
1193 output_asm_insn (".long %O2-%O0", &this.lab
);
1196 output_asm_insn (far
? ".long %O2" : ".word %O2-%O0", &this.lab
);
1200 /* Local label counter, used for constants in the pool and inside
1201 pattern branches. */
1203 static int lf
= 100;
1205 /* Output code for ordinary branches. */
1208 output_branch (logic
, insn
, operands
)
1213 switch (get_attr_length (insn
))
1216 /* This can happen if filling the delay slot has caused a forward
1217 branch to exceed its range (we could reverse it, but only
1218 when we know we won't overextend other branches; this should
1219 best be handled by relaxation).
1220 It can also happen when other condbranches hoist delay slot insn
1221 from their destination, thus leading to code size increase.
1222 But the branch will still be in the range -4092..+4098 bytes. */
1227 /* The call to print_slot will clobber the operands. */
1228 rtx op0
= operands
[0];
1230 /* If the instruction in the delay slot is annulled (true), then
1231 there is no delay slot where we can put it now. The only safe
1232 place for it is after the label. final will do that by default. */
1235 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence
, 0, 0)))
1237 asm_fprintf (asm_out_file
, "\tb%s%ss\t%LLF%d\n", logic
? "f" : "t",
1238 ASSEMBLER_DIALECT
? "/" : ".", label
);
1239 print_slot (final_sequence
);
1242 asm_fprintf (asm_out_file
, "\tb%s\t%LLF%d\n", logic
? "f" : "t", label
);
1244 output_asm_insn ("bra\t%l0", &op0
);
1245 fprintf (asm_out_file
, "\tnop\n");
1246 (*targetm
.asm_out
.internal_label
)(asm_out_file
, "LF", label
);
1250 /* When relaxing, handle this like a short branch. The linker
1251 will fix it up if it still doesn't fit after relaxation. */
1253 return logic
? "bt%.\t%l0" : "bf%.\t%l0";
1255 /* These are for SH2e, in which we have to account for the
1256 extra nop because of the hardware bug in annulled branches. */
1263 && INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence
, 0, 0)))
1265 asm_fprintf (asm_out_file
, "b%s%ss\t%LLF%d\n",
1267 ASSEMBLER_DIALECT
? "/" : ".", label
);
1268 fprintf (asm_out_file
, "\tnop\n");
1269 output_asm_insn ("bra\t%l0", operands
);
1270 fprintf (asm_out_file
, "\tnop\n");
1271 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LF", label
);
1275 /* When relaxing, fall through. */
1280 sprintf (buffer
, "b%s%ss\t%%l0",
1282 ASSEMBLER_DIALECT
? "/" : ".");
1283 output_asm_insn (buffer
, &operands
[0]);
1288 /* There should be no longer branches now - that would
1289 indicate that something has destroyed the branches set
1290 up in machine_dependent_reorg. */
1296 output_branchy_insn (code
, template, insn
, operands
)
1298 const char *template;
1302 rtx next_insn
= NEXT_INSN (insn
);
1304 if (next_insn
&& GET_CODE (next_insn
) == JUMP_INSN
&& condjump_p (next_insn
))
1306 rtx src
= SET_SRC (PATTERN (next_insn
));
1307 if (GET_CODE (src
) == IF_THEN_ELSE
&& GET_CODE (XEXP (src
, 0)) != code
)
1309 /* Following branch not taken */
1310 operands
[9] = gen_label_rtx ();
1311 emit_label_after (operands
[9], next_insn
);
1312 INSN_ADDRESSES_NEW (operands
[9],
1313 INSN_ADDRESSES (INSN_UID (next_insn
))
1314 + get_attr_length (next_insn
));
1319 int offset
= (branch_dest (next_insn
)
1320 - INSN_ADDRESSES (INSN_UID (next_insn
)) + 4);
1321 if (offset
>= -252 && offset
<= 258)
1323 if (GET_CODE (src
) == IF_THEN_ELSE
)
1325 src
= XEXP (src
, 1);
1331 operands
[9] = gen_label_rtx ();
1332 emit_label_after (operands
[9], insn
);
1333 INSN_ADDRESSES_NEW (operands
[9],
1334 INSN_ADDRESSES (INSN_UID (insn
))
1335 + get_attr_length (insn
));
1340 output_ieee_ccmpeq (insn
, operands
)
1341 rtx insn
, *operands
;
1343 return output_branchy_insn (NE
, "bt\t%l9\\;fcmp/eq\t%1,%0", insn
, operands
);
1346 /* Output the start of the assembler file. */
1351 default_file_start ();
1354 /* We need to show the text section with the proper
1355 attributes as in TEXT_SECTION_ASM_OP, before dwarf2out
1356 emits it without attributes in TEXT_SECTION, else GAS
1357 will complain. We can teach GAS specifically about the
1358 default attributes for our choice of text section, but
1359 then we would have to change GAS again if/when we change
1360 the text section name. */
1361 fprintf (asm_out_file
, "%s\n", TEXT_SECTION_ASM_OP
);
1363 /* Switch to the data section so that the coffsem symbol
1364 isn't in the text section. */
1367 if (TARGET_LITTLE_ENDIAN
)
1368 fputs ("\t.little\n", asm_out_file
);
1372 if (TARGET_SHCOMPACT
)
1373 fputs ("\t.mode\tSHcompact\n", asm_out_file
);
1374 else if (TARGET_SHMEDIA
)
1375 fprintf (asm_out_file
, "\t.mode\tSHmedia\n\t.abi\t%i\n",
1376 TARGET_SHMEDIA64
? 64 : 32);
1380 /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
1383 unspec_caller_rtx_p (pat
)
1386 switch (GET_CODE (pat
))
1389 return unspec_caller_rtx_p (XEXP (pat
, 0));
1392 if (unspec_caller_rtx_p (XEXP (pat
, 0)))
1394 return unspec_caller_rtx_p (XEXP (pat
, 1));
1396 if (XINT (pat
, 1) == UNSPEC_CALLER
)
1405 /* Indicate that INSN cannot be duplicated. This is true for insn
1406 that generates an unique label. */
1409 sh_cannot_copy_insn_p (insn
)
1414 if (!reload_completed
|| !flag_pic
)
1417 if (GET_CODE (insn
) != INSN
)
1419 if (asm_noperands (insn
) >= 0)
1422 pat
= PATTERN (insn
);
1423 if (GET_CODE (pat
) != SET
)
1425 pat
= SET_SRC (pat
);
1427 if (unspec_caller_rtx_p (pat
))
1433 /* Actual number of instructions used to make a shift by N. */
1434 static const char ashiftrt_insns
[] =
1435 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
1437 /* Left shift and logical right shift are the same. */
1438 static const char shift_insns
[] =
1439 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
1441 /* Individual shift amounts needed to get the above length sequences.
1442 One bit right shifts clobber the T bit, so when possible, put one bit
1443 shifts in the middle of the sequence, so the ends are eligible for
1444 branch delay slots. */
1445 static const short shift_amounts
[32][5] = {
1446 {0}, {1}, {2}, {2, 1},
1447 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
1448 {8}, {8, 1}, {8, 2}, {8, 1, 2},
1449 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
1450 {16}, {16, 1}, {16, 2}, {16, 1, 2},
1451 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
1452 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
1453 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
1455 /* Likewise, but for shift amounts < 16, up to three highmost bits
1456 might be clobbered. This is typically used when combined with some
1457 kind of sign or zero extension. */
1459 static const char ext_shift_insns
[] =
1460 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
1462 static const short ext_shift_amounts
[32][4] = {
1463 {0}, {1}, {2}, {2, 1},
1464 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
1465 {8}, {8, 1}, {8, 2}, {8, 1, 2},
1466 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
1467 {16}, {16, 1}, {16, 2}, {16, 1, 2},
1468 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
1469 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
1470 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
1472 /* Assuming we have a value that has been sign-extended by at least one bit,
1473 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
1474 to shift it by N without data loss, and quicker than by other means? */
1475 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
1477 /* This is used in length attributes in sh.md to help compute the length
1478 of arbitrary constant shift instructions. */
1481 shift_insns_rtx (insn
)
1484 rtx set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
1485 int shift_count
= INTVAL (XEXP (set_src
, 1));
1486 enum rtx_code shift_code
= GET_CODE (set_src
);
1491 return ashiftrt_insns
[shift_count
];
1494 return shift_insns
[shift_count
];
1500 /* Return the cost of a shift. */
1511 if (GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
1513 if (GET_MODE (x
) == DImode
1514 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1515 && INTVAL (XEXP (x
, 1)) == 1)
1518 /* Everything else is invalid, because there is no pattern for it. */
1521 /* If shift by a non constant, then this will be expensive. */
1522 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
1523 return SH_DYNAMIC_SHIFT_COST
;
1525 value
= INTVAL (XEXP (x
, 1));
1527 /* Otherwise, return the true cost in instructions. */
1528 if (GET_CODE (x
) == ASHIFTRT
)
1530 int cost
= ashiftrt_insns
[value
];
1531 /* If SH3, then we put the constant in a reg and use shad. */
1532 if (cost
> 1 + SH_DYNAMIC_SHIFT_COST
)
1533 cost
= 1 + SH_DYNAMIC_SHIFT_COST
;
1537 return shift_insns
[value
];
1540 /* Return the cost of an AND operation. */
1548 /* Anding with a register is a single cycle and instruction. */
1549 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
1552 i
= INTVAL (XEXP (x
, 1));
1556 if ((GET_CODE (XEXP (x
, 1)) == CONST_INT
1557 && CONST_OK_FOR_I16 (INTVAL (XEXP (x
, 1))))
1558 || EXTRA_CONSTRAINT_C16 (XEXP (x
, 1)))
1564 /* These constants are single cycle extu.[bw] instructions. */
1565 if (i
== 0xff || i
== 0xffff)
1567 /* Constants that can be used in an and immediate instruction in a single
1568 cycle, but this requires r0, so make it a little more expensive. */
1569 if (CONST_OK_FOR_K08 (i
))
1571 /* Constants that can be loaded with a mov immediate and an and.
1572 This case is probably unnecessary. */
1573 if (CONST_OK_FOR_I08 (i
))
1575 /* Any other constants requires a 2 cycle pc-relative load plus an and.
1576 This case is probably unnecessary. */
1580 /* Return the cost of an addition or a subtraction. */
1586 /* Adding a register is a single cycle insn. */
1587 if (GET_CODE (XEXP (x
, 1)) == REG
1588 || GET_CODE (XEXP (x
, 1)) == SUBREG
)
1591 /* Likewise for small constants. */
1592 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1593 && CONST_OK_FOR_ADD (INTVAL (XEXP (x
, 1))))
1597 switch (GET_CODE (XEXP (x
, 1)))
1602 return TARGET_SHMEDIA64
? 5 : 3;
1605 if (CONST_OK_FOR_I16 (INTVAL (XEXP (x
, 1))))
1607 else if (CONST_OK_FOR_I16 (INTVAL (XEXP (x
, 1)) >> 16))
1609 else if (CONST_OK_FOR_I16 ((INTVAL (XEXP (x
, 1)) >> 16) >> 16))
1617 /* Any other constant requires a 2 cycle pc-relative load plus an
1622 /* Return the cost of a multiply. */
1625 rtx x ATTRIBUTE_UNUSED
;
1632 /* We have a mul insn, so we can never take more than the mul and the
1633 read of the mac reg, but count more because of the latency and extra
1635 if (TARGET_SMALLCODE
)
1640 /* If we're aiming at small code, then just count the number of
1641 insns in a multiply call sequence. */
1642 if (TARGET_SMALLCODE
)
1645 /* Otherwise count all the insns in the routine we'd be calling too. */
1649 /* Compute a (partial) cost for rtx X. Return true if the complete
1650 cost has been computed, and false if subexpressions should be
1651 scanned. In either case, *TOTAL contains the cost result. */
1654 sh_rtx_costs (x
, code
, outer_code
, total
)
1656 int code
, outer_code
, *total
;
1663 if (INTVAL (x
) == 0)
1665 else if (outer_code
== AND
&& and_operand ((x
), DImode
))
1667 else if ((outer_code
== IOR
|| outer_code
== XOR
1668 || outer_code
== PLUS
)
1669 && CONST_OK_FOR_I10 (INTVAL (x
)))
1671 else if (CONST_OK_FOR_I16 (INTVAL (x
)))
1672 *total
= COSTS_N_INSNS (outer_code
!= SET
);
1673 else if (CONST_OK_FOR_I16 (INTVAL (x
) >> 16))
1674 *total
= COSTS_N_INSNS (2);
1675 else if (CONST_OK_FOR_I16 ((INTVAL (x
) >> 16) >> 16))
1676 *total
= COSTS_N_INSNS (3);
1678 *total
= COSTS_N_INSNS (4);
1681 if (CONST_OK_FOR_I08 (INTVAL (x
)))
1683 else if ((outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
1684 && CONST_OK_FOR_K08 (INTVAL (x
)))
1693 if (TARGET_SHMEDIA64
)
1694 *total
= COSTS_N_INSNS (4);
1695 else if (TARGET_SHMEDIA32
)
1696 *total
= COSTS_N_INSNS (2);
1703 *total
= COSTS_N_INSNS (4);
1709 *total
= COSTS_N_INSNS (addsubcosts (x
));
1713 *total
= COSTS_N_INSNS (andcosts (x
));
1717 *total
= COSTS_N_INSNS (multcosts (x
));
1723 *total
= COSTS_N_INSNS (shiftcosts (x
));
1730 *total
= COSTS_N_INSNS (20);
1743 /* Compute the cost of an address. For the SH, all valid addresses are
1744 the same cost. Use a slightly higher cost for reg + reg addressing,
1745 since it increases pressure on r0. */
1751 return (GET_CODE (X
) == PLUS
1752 && ! CONSTANT_P (XEXP (X
, 1))
1753 && ! TARGET_SHMEDIA
? 1 : 0);
1756 /* Code to expand a shift. */
1759 gen_ashift (type
, n
, reg
)
1764 /* Negative values here come from the shift_amounts array. */
1777 emit_insn (gen_ashrsi3_k (reg
, reg
, GEN_INT (n
)));
1781 emit_insn (gen_lshrsi3_m (reg
, reg
, GEN_INT (n
)));
1783 emit_insn (gen_lshrsi3_k (reg
, reg
, GEN_INT (n
)));
1786 emit_insn (gen_ashlsi3_std (reg
, reg
, GEN_INT (n
)));
1791 /* Same for HImode */
1794 gen_ashift_hi (type
, n
, reg
)
1799 /* Negative values here come from the shift_amounts array. */
1813 /* We don't have HImode right shift operations because using the
1814 ordinary 32 bit shift instructions for that doesn't generate proper
1815 zero/sign extension.
1816 gen_ashift_hi is only called in contexts where we know that the
1817 sign extension works out correctly. */
1820 if (GET_CODE (reg
) == SUBREG
)
1822 offset
= SUBREG_BYTE (reg
);
1823 reg
= SUBREG_REG (reg
);
1825 gen_ashift (type
, n
, gen_rtx_SUBREG (SImode
, reg
, offset
));
1829 emit_insn (gen_ashlhi3_k (reg
, reg
, GEN_INT (n
)));
1834 /* Output RTL to split a constant shift into its component SH constant
1835 shift instructions. */
1838 gen_shifty_op (code
, operands
)
1842 int value
= INTVAL (operands
[2]);
1845 /* Truncate the shift count in case it is out of bounds. */
1846 value
= value
& 0x1f;
1850 if (code
== LSHIFTRT
)
1852 emit_insn (gen_rotlsi3_1 (operands
[0], operands
[0]));
1853 emit_insn (gen_movt (operands
[0]));
1856 else if (code
== ASHIFT
)
1858 /* There is a two instruction sequence for 31 bit left shifts,
1859 but it requires r0. */
1860 if (GET_CODE (operands
[0]) == REG
&& REGNO (operands
[0]) == 0)
1862 emit_insn (gen_andsi3 (operands
[0], operands
[0], const1_rtx
));
1863 emit_insn (gen_rotlsi3_31 (operands
[0], operands
[0]));
1868 else if (value
== 0)
1870 /* This can happen when not optimizing. We must output something here
1871 to prevent the compiler from aborting in final.c after the try_split
1873 emit_insn (gen_nop ());
1877 max
= shift_insns
[value
];
1878 for (i
= 0; i
< max
; i
++)
1879 gen_ashift (code
, shift_amounts
[value
][i
], operands
[0]);
1882 /* Same as above, but optimized for values where the topmost bits don't
1886 gen_shifty_hi_op (code
, operands
)
1890 int value
= INTVAL (operands
[2]);
1892 void (*gen_fun
) PARAMS ((int, int, rtx
));
1894 /* This operation is used by and_shl for SImode values with a few
1895 high bits known to be cleared. */
1899 emit_insn (gen_nop ());
1903 gen_fun
= GET_MODE (operands
[0]) == HImode
? gen_ashift_hi
: gen_ashift
;
1906 max
= ext_shift_insns
[value
];
1907 for (i
= 0; i
< max
; i
++)
1908 gen_fun (code
, ext_shift_amounts
[value
][i
], operands
[0]);
1911 /* When shifting right, emit the shifts in reverse order, so that
1912 solitary negative values come first. */
1913 for (i
= ext_shift_insns
[value
] - 1; i
>= 0; i
--)
1914 gen_fun (code
, ext_shift_amounts
[value
][i
], operands
[0]);
1917 /* Output RTL for an arithmetic right shift. */
1919 /* ??? Rewrite to use super-optimizer sequences. */
1922 expand_ashiftrt (operands
)
1933 if (GET_CODE (operands
[2]) != CONST_INT
)
1935 rtx count
= copy_to_mode_reg (SImode
, operands
[2]);
1936 emit_insn (gen_negsi2 (count
, count
));
1937 emit_insn (gen_ashrsi3_d (operands
[0], operands
[1], count
));
1940 else if (ashiftrt_insns
[INTVAL (operands
[2]) & 31]
1941 > 1 + SH_DYNAMIC_SHIFT_COST
)
1944 = force_reg (SImode
, GEN_INT (- (INTVAL (operands
[2]) & 31)));
1945 emit_insn (gen_ashrsi3_d (operands
[0], operands
[1], count
));
1949 if (GET_CODE (operands
[2]) != CONST_INT
)
1952 value
= INTVAL (operands
[2]) & 31;
1956 emit_insn (gen_ashrsi2_31 (operands
[0], operands
[1]));
1959 else if (value
>= 16 && value
<= 19)
1961 wrk
= gen_reg_rtx (SImode
);
1962 emit_insn (gen_ashrsi2_16 (wrk
, operands
[1]));
1965 gen_ashift (ASHIFTRT
, 1, wrk
);
1966 emit_move_insn (operands
[0], wrk
);
1969 /* Expand a short sequence inline, longer call a magic routine. */
1970 else if (value
<= 5)
1972 wrk
= gen_reg_rtx (SImode
);
1973 emit_move_insn (wrk
, operands
[1]);
1975 gen_ashift (ASHIFTRT
, 1, wrk
);
1976 emit_move_insn (operands
[0], wrk
);
1980 wrk
= gen_reg_rtx (Pmode
);
1982 /* Load the value into an arg reg and call a helper. */
1983 emit_move_insn (gen_rtx_REG (SImode
, 4), operands
[1]);
1984 sprintf (func
, "__ashiftrt_r4_%d", value
);
1985 func_name
= get_identifier (func
);
1986 sym
= function_symbol (IDENTIFIER_POINTER (func_name
));
1987 emit_move_insn (wrk
, sym
);
1988 emit_insn (gen_ashrsi3_n (GEN_INT (value
), wrk
));
1989 emit_move_insn (operands
[0], gen_rtx_REG (SImode
, 4));
1994 sh_dynamicalize_shift_p (count
)
1997 return shift_insns
[INTVAL (count
)] > 1 + SH_DYNAMIC_SHIFT_COST
;
2000 /* Try to find a good way to implement the combiner pattern
2001 [(set (match_operand:SI 0 "register_operand" "r")
2002 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
2003 (match_operand:SI 2 "const_int_operand" "n"))
2004 (match_operand:SI 3 "const_int_operand" "n"))) .
2005 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
2006 return 0 for simple right / left or left/right shift combination.
2007 return 1 for a combination of shifts with zero_extend.
2008 return 2 for a combination of shifts with an AND that needs r0.
2009 return 3 for a combination of shifts with an AND that needs an extra
2010 scratch register, when the three highmost bits of the AND mask are clear.
2011 return 4 for a combination of shifts with an AND that needs an extra
2012 scratch register, when any of the three highmost bits of the AND mask
2014 If ATTRP is set, store an initial right shift width in ATTRP[0],
2015 and the instruction length in ATTRP[1] . These values are not valid
2017 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
2018 shift_amounts for the last shift value that is to be used before the
2021 shl_and_kind (left_rtx
, mask_rtx
, attrp
)
2022 rtx left_rtx
, mask_rtx
;
2025 unsigned HOST_WIDE_INT mask
, lsb
, mask2
, lsb2
;
2026 int left
= INTVAL (left_rtx
), right
;
2028 int cost
, best_cost
= 10000;
2029 int best_right
= 0, best_len
= 0;
2033 if (left
< 0 || left
> 31)
2035 if (GET_CODE (mask_rtx
) == CONST_INT
)
2036 mask
= (unsigned HOST_WIDE_INT
) INTVAL (mask_rtx
) >> left
;
2038 mask
= (unsigned HOST_WIDE_INT
) GET_MODE_MASK (SImode
) >> left
;
2039 /* Can this be expressed as a right shift / left shift pair ? */
2040 lsb
= ((mask
^ (mask
- 1)) >> 1) + 1;
2041 right
= exact_log2 (lsb
);
2042 mask2
= ~(mask
+ lsb
- 1);
2043 lsb2
= ((mask2
^ (mask2
- 1)) >> 1) + 1;
2044 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
2046 best_cost
= shift_insns
[right
] + shift_insns
[right
+ left
];
2047 /* mask has no trailing zeroes <==> ! right */
2048 else if (! right
&& mask2
== ~(lsb2
- 1))
2050 int late_right
= exact_log2 (lsb2
);
2051 best_cost
= shift_insns
[left
+ late_right
] + shift_insns
[late_right
];
2053 /* Try to use zero extend */
2054 if (mask2
== ~(lsb2
- 1))
2058 for (width
= 8; width
<= 16; width
+= 8)
2060 /* Can we zero-extend right away? */
2061 if (lsb2
== (unsigned HOST_WIDE_INT
)1 << width
)
2064 = 1 + ext_shift_insns
[right
] + ext_shift_insns
[left
+ right
];
2065 if (cost
< best_cost
)
2076 /* ??? Could try to put zero extend into initial right shift,
2077 or even shift a bit left before the right shift. */
2078 /* Determine value of first part of left shift, to get to the
2079 zero extend cut-off point. */
2080 first
= width
- exact_log2 (lsb2
) + right
;
2081 if (first
>= 0 && right
+ left
- first
>= 0)
2083 cost
= ext_shift_insns
[right
] + ext_shift_insns
[first
] + 1
2084 + ext_shift_insns
[right
+ left
- first
];
2085 if (cost
< best_cost
)
2097 /* Try to use r0 AND pattern */
2098 for (i
= 0; i
<= 2; i
++)
2102 if (! CONST_OK_FOR_K08 (mask
>> i
))
2104 cost
= (i
!= 0) + 2 + ext_shift_insns
[left
+ i
];
2105 if (cost
< best_cost
)
2110 best_len
= cost
- 1;
2113 /* Try to use a scratch register to hold the AND operand. */
2114 can_ext
= ((mask
<< left
) & ((unsigned HOST_WIDE_INT
)3 << 30)) == 0;
2115 for (i
= 0; i
<= 2; i
++)
2119 cost
= (i
!= 0) + (CONST_OK_FOR_I08 (mask
>> i
) ? 2 : 3)
2120 + (can_ext
? ext_shift_insns
: shift_insns
)[left
+ i
];
2121 if (cost
< best_cost
)
2126 best_len
= cost
- 1 - ! CONST_OK_FOR_I08 (mask
>> i
);
2132 attrp
[0] = best_right
;
2133 attrp
[1] = best_len
;
2138 /* This is used in length attributes of the unnamed instructions
2139 corresponding to shl_and_kind return values of 1 and 2. */
2141 shl_and_length (insn
)
2144 rtx set_src
, left_rtx
, mask_rtx
;
2147 set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
2148 left_rtx
= XEXP (XEXP (set_src
, 0), 1);
2149 mask_rtx
= XEXP (set_src
, 1);
2150 shl_and_kind (left_rtx
, mask_rtx
, attributes
);
2151 return attributes
[1];
2154 /* This is used in length attribute of the and_shl_scratch instruction. */
2157 shl_and_scr_length (insn
)
2160 rtx set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
2161 int len
= shift_insns
[INTVAL (XEXP (set_src
, 1))];
2162 rtx op
= XEXP (set_src
, 0);
2163 len
+= shift_insns
[INTVAL (XEXP (op
, 1))] + 1;
2164 op
= XEXP (XEXP (op
, 0), 0);
2165 return len
+ shift_insns
[INTVAL (XEXP (op
, 1))];
2168 /* Generating rtl? */
2169 extern int rtx_equal_function_value_matters
;
2171 /* Generate rtl for instructions for which shl_and_kind advised a particular
2172 method of generating them, i.e. returned zero. */
2175 gen_shl_and (dest
, left_rtx
, mask_rtx
, source
)
2176 rtx dest
, left_rtx
, mask_rtx
, source
;
2179 unsigned HOST_WIDE_INT mask
;
2180 int kind
= shl_and_kind (left_rtx
, mask_rtx
, attributes
);
2181 int right
, total_shift
;
2182 void (*shift_gen_fun
) PARAMS ((int, rtx
*)) = gen_shifty_hi_op
;
2184 right
= attributes
[0];
2185 total_shift
= INTVAL (left_rtx
) + right
;
2186 mask
= (unsigned HOST_WIDE_INT
) INTVAL (mask_rtx
) >> total_shift
;
2193 int first
= attributes
[2];
2198 emit_insn ((mask
<< right
) <= 0xff
2199 ? gen_zero_extendqisi2(dest
,
2200 gen_lowpart (QImode
, source
))
2201 : gen_zero_extendhisi2(dest
,
2202 gen_lowpart (HImode
, source
)));
2206 emit_insn (gen_movsi (dest
, source
));
2210 operands
[2] = GEN_INT (right
);
2211 gen_shifty_hi_op (LSHIFTRT
, operands
);
2215 operands
[2] = GEN_INT (first
);
2216 gen_shifty_hi_op (ASHIFT
, operands
);
2217 total_shift
-= first
;
2221 emit_insn (mask
<= 0xff
2222 ? gen_zero_extendqisi2(dest
, gen_lowpart (QImode
, dest
))
2223 : gen_zero_extendhisi2(dest
, gen_lowpart (HImode
, dest
)));
2224 if (total_shift
> 0)
2226 operands
[2] = GEN_INT (total_shift
);
2227 gen_shifty_hi_op (ASHIFT
, operands
);
2232 shift_gen_fun
= gen_shifty_op
;
2234 /* If the topmost bit that matters is set, set the topmost bits
2235 that don't matter. This way, we might be able to get a shorter
2237 if (mask
& ((HOST_WIDE_INT
)1 << (31 - total_shift
)))
2238 mask
|= (HOST_WIDE_INT
)~0 << (31 - total_shift
);
2240 /* Don't expand fine-grained when combining, because that will
2241 make the pattern fail. */
2242 if (rtx_equal_function_value_matters
2243 || reload_in_progress
|| reload_completed
)
2247 /* Cases 3 and 4 should be handled by this split
2248 only while combining */
2253 emit_insn (gen_lshrsi3 (dest
, source
, GEN_INT (right
)));
2256 emit_insn (gen_andsi3 (dest
, source
, GEN_INT (mask
)));
2261 operands
[2] = GEN_INT (total_shift
);
2262 shift_gen_fun (ASHIFT
, operands
);
2269 if (kind
!= 4 && total_shift
< 16)
2271 neg
= -ext_shift_amounts
[total_shift
][1];
2273 neg
-= ext_shift_amounts
[total_shift
][2];
2277 emit_insn (gen_and_shl_scratch (dest
, source
,
2280 GEN_INT (total_shift
+ neg
),
2282 emit_insn (gen_movsi (dest
, dest
));
2289 /* Try to find a good way to implement the combiner pattern
2290 [(set (match_operand:SI 0 "register_operand" "=r")
2291 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
2292 (match_operand:SI 2 "const_int_operand" "n")
2293 (match_operand:SI 3 "const_int_operand" "n")
2295 (clobber (reg:SI T_REG))]
2296 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
2297 return 0 for simple left / right shift combination.
2298 return 1 for left shift / 8 bit sign extend / left shift.
2299 return 2 for left shift / 16 bit sign extend / left shift.
2300 return 3 for left shift / 8 bit sign extend / shift / sign extend.
2301 return 4 for left shift / 16 bit sign extend / shift / sign extend.
2302 return 5 for left shift / 16 bit sign extend / right shift
2303 return 6 for < 8 bit sign extend / left shift.
2304 return 7 for < 8 bit sign extend / left shift / single right shift.
2305 If COSTP is nonzero, assign the calculated cost to *COSTP. */
2308 shl_sext_kind (left_rtx
, size_rtx
, costp
)
2309 rtx left_rtx
, size_rtx
;
2312 int left
, size
, insize
, ext
;
2313 int cost
= 0, best_cost
;
2316 left
= INTVAL (left_rtx
);
2317 size
= INTVAL (size_rtx
);
2318 insize
= size
- left
;
2321 /* Default to left / right shift. */
2323 best_cost
= shift_insns
[32 - insize
] + ashiftrt_insns
[32 - size
];
2326 /* 16 bit shift / sign extend / 16 bit shift */
2327 cost
= shift_insns
[16 - insize
] + 1 + ashiftrt_insns
[16 - size
];
2328 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
2329 below, by alternative 3 or something even better. */
2330 if (cost
< best_cost
)
2336 /* Try a plain sign extend between two shifts. */
2337 for (ext
= 16; ext
>= insize
; ext
-= 8)
2341 cost
= ext_shift_insns
[ext
- insize
] + 1 + shift_insns
[size
- ext
];
2342 if (cost
< best_cost
)
2344 kind
= ext
/ (unsigned) 8;
2348 /* Check if we can do a sloppy shift with a final signed shift
2349 restoring the sign. */
2350 if (EXT_SHIFT_SIGNED (size
- ext
))
2351 cost
= ext_shift_insns
[ext
- insize
] + ext_shift_insns
[size
- ext
] + 1;
2352 /* If not, maybe it's still cheaper to do the second shift sloppy,
2353 and do a final sign extend? */
2354 else if (size
<= 16)
2355 cost
= ext_shift_insns
[ext
- insize
] + 1
2356 + ext_shift_insns
[size
> ext
? size
- ext
: ext
- size
] + 1;
2359 if (cost
< best_cost
)
2361 kind
= ext
/ (unsigned) 8 + 2;
2365 /* Check if we can sign extend in r0 */
2368 cost
= 3 + shift_insns
[left
];
2369 if (cost
< best_cost
)
2374 /* Try the same with a final signed shift. */
2377 cost
= 3 + ext_shift_insns
[left
+ 1] + 1;
2378 if (cost
< best_cost
)
2387 /* Try to use a dynamic shift. */
2388 cost
= shift_insns
[32 - insize
] + 1 + SH_DYNAMIC_SHIFT_COST
;
2389 if (cost
< best_cost
)
2400 /* Function to be used in the length attribute of the instructions
2401 implementing this pattern. */
2404 shl_sext_length (insn
)
2407 rtx set_src
, left_rtx
, size_rtx
;
2410 set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
2411 left_rtx
= XEXP (XEXP (set_src
, 0), 1);
2412 size_rtx
= XEXP (set_src
, 1);
2413 shl_sext_kind (left_rtx
, size_rtx
, &cost
);
2417 /* Generate rtl for this pattern */
2420 gen_shl_sext (dest
, left_rtx
, size_rtx
, source
)
2421 rtx dest
, left_rtx
, size_rtx
, source
;
2424 int left
, size
, insize
, cost
;
2427 kind
= shl_sext_kind (left_rtx
, size_rtx
, &cost
);
2428 left
= INTVAL (left_rtx
);
2429 size
= INTVAL (size_rtx
);
2430 insize
= size
- left
;
2438 int ext
= kind
& 1 ? 8 : 16;
2439 int shift2
= size
- ext
;
2441 /* Don't expand fine-grained when combining, because that will
2442 make the pattern fail. */
2443 if (! rtx_equal_function_value_matters
2444 && ! reload_in_progress
&& ! reload_completed
)
2446 emit_insn (gen_shl_sext_ext (dest
, source
, left_rtx
, size_rtx
));
2447 emit_insn (gen_movsi (dest
, source
));
2451 emit_insn (gen_movsi (dest
, source
));
2455 operands
[2] = GEN_INT (ext
- insize
);
2456 gen_shifty_hi_op (ASHIFT
, operands
);
2459 ? gen_extendqisi2(dest
, gen_lowpart (QImode
, dest
))
2460 : gen_extendhisi2(dest
, gen_lowpart (HImode
, dest
)));
2465 operands
[2] = GEN_INT (shift2
);
2466 gen_shifty_op (ASHIFT
, operands
);
2473 if (EXT_SHIFT_SIGNED (shift2
))
2475 operands
[2] = GEN_INT (shift2
+ 1);
2476 gen_shifty_op (ASHIFT
, operands
);
2477 operands
[2] = GEN_INT (1);
2478 gen_shifty_op (ASHIFTRT
, operands
);
2481 operands
[2] = GEN_INT (shift2
);
2482 gen_shifty_hi_op (ASHIFT
, operands
);
2486 operands
[2] = GEN_INT (-shift2
);
2487 gen_shifty_hi_op (LSHIFTRT
, operands
);
2489 emit_insn (size
<= 8
2490 ? gen_extendqisi2 (dest
, gen_lowpart (QImode
, dest
))
2491 : gen_extendhisi2 (dest
, gen_lowpart (HImode
, dest
)));
2498 if (! rtx_equal_function_value_matters
2499 && ! reload_in_progress
&& ! reload_completed
)
2500 emit_insn (gen_shl_sext_ext (dest
, source
, left_rtx
, size_rtx
));
2504 operands
[2] = GEN_INT (16 - insize
);
2505 gen_shifty_hi_op (ASHIFT
, operands
);
2506 emit_insn (gen_extendhisi2 (dest
, gen_lowpart (HImode
, dest
)));
2508 /* Don't use gen_ashrsi3 because it generates new pseudos. */
2510 gen_ashift (ASHIFTRT
, 1, dest
);
2515 /* Don't expand fine-grained when combining, because that will
2516 make the pattern fail. */
2517 if (! rtx_equal_function_value_matters
2518 && ! reload_in_progress
&& ! reload_completed
)
2520 emit_insn (gen_shl_sext_ext (dest
, source
, left_rtx
, size_rtx
));
2521 emit_insn (gen_movsi (dest
, source
));
2524 emit_insn (gen_andsi3 (dest
, source
, GEN_INT ((1 << insize
) - 1)));
2525 emit_insn (gen_xorsi3 (dest
, dest
, GEN_INT (1 << (insize
- 1))));
2526 emit_insn (gen_addsi3 (dest
, dest
, GEN_INT (-1 << (insize
- 1))));
2528 operands
[2] = kind
== 7 ? GEN_INT (left
+ 1) : left_rtx
;
2529 gen_shifty_op (ASHIFT
, operands
);
2531 emit_insn (gen_ashrsi3_k (dest
, dest
, GEN_INT (1)));
2539 /* Prefix a symbol_ref name with "datalabel". */
2542 gen_datalabel_ref (sym
)
2545 if (GET_CODE (sym
) == LABEL_REF
)
2546 return gen_rtx_CONST (GET_MODE (sym
),
2547 gen_rtx_UNSPEC (GET_MODE (sym
),
2551 if (GET_CODE (sym
) != SYMBOL_REF
)
2558 /* The SH cannot load a large constant into a register, constants have to
2559 come from a pc relative load. The reference of a pc relative load
2560 instruction must be less than 1k infront of the instruction. This
2561 means that we often have to dump a constant inside a function, and
2562 generate code to branch around it.
2564 It is important to minimize this, since the branches will slow things
2565 down and make things bigger.
2567 Worst case code looks like:
2585 We fix this by performing a scan before scheduling, which notices which
2586 instructions need to have their operands fetched from the constant table
2587 and builds the table.
2591 scan, find an instruction which needs a pcrel move. Look forward, find the
2592 last barrier which is within MAX_COUNT bytes of the requirement.
2593 If there isn't one, make one. Process all the instructions between
2594 the find and the barrier.
2596 In the above example, we can tell that L3 is within 1k of L1, so
2597 the first move can be shrunk from the 3 insn+constant sequence into
2598 just 1 insn, and the constant moved to L3 to make:
2609 Then the second move becomes the target for the shortening process. */
2613 rtx value
; /* Value in table. */
2614 rtx label
; /* Label of value. */
2615 rtx wend
; /* End of window. */
2616 enum machine_mode mode
; /* Mode of value. */
2618 /* True if this constant is accessed as part of a post-increment
2619 sequence. Note that HImode constants are never accessed in this way. */
2620 bool part_of_sequence_p
;
2623 /* The maximum number of constants that can fit into one pool, since
2624 the pc relative range is 0...1020 bytes and constants are at least 4
2627 #define MAX_POOL_SIZE (1020/4)
2628 static pool_node pool_vector
[MAX_POOL_SIZE
];
2629 static int pool_size
;
2630 static rtx pool_window_label
;
2631 static int pool_window_last
;
2633 /* ??? If we need a constant in HImode which is the truncated value of a
2634 constant we need in SImode, we could combine the two entries thus saving
2635 two bytes. Is this common enough to be worth the effort of implementing
2638 /* ??? This stuff should be done at the same time that we shorten branches.
2639 As it is now, we must assume that all branches are the maximum size, and
2640 this causes us to almost always output constant pools sooner than
2643 /* Add a constant to the pool and return its label. */
2646 add_constant (x
, mode
, last_value
)
2648 enum machine_mode mode
;
2652 rtx lab
, new, ref
, newref
;
2654 /* First see if we've already got it. */
2655 for (i
= 0; i
< pool_size
; i
++)
2657 if (x
->code
== pool_vector
[i
].value
->code
2658 && mode
== pool_vector
[i
].mode
)
2660 if (x
->code
== CODE_LABEL
)
2662 if (XINT (x
, 3) != XINT (pool_vector
[i
].value
, 3))
2665 if (rtx_equal_p (x
, pool_vector
[i
].value
))
2670 || ! rtx_equal_p (last_value
, pool_vector
[i
-1].value
))
2672 new = gen_label_rtx ();
2673 LABEL_REFS (new) = pool_vector
[i
].label
;
2674 pool_vector
[i
].label
= lab
= new;
2676 if (lab
&& pool_window_label
)
2678 newref
= gen_rtx_LABEL_REF (VOIDmode
, pool_window_label
);
2679 ref
= pool_vector
[pool_window_last
].wend
;
2680 LABEL_NEXTREF (newref
) = ref
;
2681 pool_vector
[pool_window_last
].wend
= newref
;
2684 pool_window_label
= new;
2685 pool_window_last
= i
;
2691 /* Need a new one. */
2692 pool_vector
[pool_size
].value
= x
;
2693 if (last_value
&& rtx_equal_p (last_value
, pool_vector
[pool_size
- 1].value
))
2696 pool_vector
[pool_size
- 1].part_of_sequence_p
= true;
2699 lab
= gen_label_rtx ();
2700 pool_vector
[pool_size
].mode
= mode
;
2701 pool_vector
[pool_size
].label
= lab
;
2702 pool_vector
[pool_size
].wend
= NULL_RTX
;
2703 pool_vector
[pool_size
].part_of_sequence_p
= (lab
== 0);
2704 if (lab
&& pool_window_label
)
2706 newref
= gen_rtx_LABEL_REF (VOIDmode
, pool_window_label
);
2707 ref
= pool_vector
[pool_window_last
].wend
;
2708 LABEL_NEXTREF (newref
) = ref
;
2709 pool_vector
[pool_window_last
].wend
= newref
;
2712 pool_window_label
= lab
;
2713 pool_window_last
= pool_size
;
2718 /* Output the literal table. */
2729 /* Do two passes, first time dump out the HI sized constants. */
2731 for (i
= 0; i
< pool_size
; i
++)
2733 pool_node
*p
= &pool_vector
[i
];
2735 if (p
->mode
== HImode
)
2739 scan
= emit_insn_after (gen_align_2 (), scan
);
2742 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
2743 scan
= emit_label_after (lab
, scan
);
2744 scan
= emit_insn_after (gen_consttable_2 (p
->value
, const0_rtx
),
2746 for (ref
= p
->wend
; ref
; ref
= LABEL_NEXTREF (ref
))
2748 lab
= XEXP (ref
, 0);
2749 scan
= emit_insn_after (gen_consttable_window_end (lab
), scan
);
2752 else if (p
->mode
== DFmode
)
2758 if (TARGET_FMOVD
&& TARGET_ALIGN_DOUBLE
&& have_df
)
2760 rtx align_insn
= NULL_RTX
;
2762 scan
= emit_label_after (gen_label_rtx (), scan
);
2763 scan
= emit_insn_after (gen_align_log (GEN_INT (3)), scan
);
2766 for (i
= 0; i
< pool_size
; i
++)
2768 pool_node
*p
= &pool_vector
[i
];
2776 if (align_insn
&& !p
->part_of_sequence_p
)
2778 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
2779 emit_label_before (lab
, align_insn
);
2780 emit_insn_before (gen_consttable_4 (p
->value
, const0_rtx
),
2782 for (ref
= p
->wend
; ref
; ref
= LABEL_NEXTREF (ref
))
2784 lab
= XEXP (ref
, 0);
2785 emit_insn_before (gen_consttable_window_end (lab
),
2788 delete_insn (align_insn
);
2789 align_insn
= NULL_RTX
;
2794 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
2795 scan
= emit_label_after (lab
, scan
);
2796 scan
= emit_insn_after (gen_consttable_4 (p
->value
,
2798 need_align
= ! need_align
;
2804 scan
= emit_insn_after (gen_align_log (GEN_INT (3)), scan
);
2809 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
2810 scan
= emit_label_after (lab
, scan
);
2811 scan
= emit_insn_after (gen_consttable_8 (p
->value
, const0_rtx
),
2819 if (p
->mode
!= HImode
)
2821 for (ref
= p
->wend
; ref
; ref
= LABEL_NEXTREF (ref
))
2823 lab
= XEXP (ref
, 0);
2824 scan
= emit_insn_after (gen_consttable_window_end (lab
),
2833 for (i
= 0; i
< pool_size
; i
++)
2835 pool_node
*p
= &pool_vector
[i
];
2846 scan
= emit_label_after (gen_label_rtx (), scan
);
2847 scan
= emit_insn_after (gen_align_4 (), scan
);
2849 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
2850 scan
= emit_label_after (lab
, scan
);
2851 scan
= emit_insn_after (gen_consttable_4 (p
->value
, const0_rtx
),
2859 scan
= emit_label_after (gen_label_rtx (), scan
);
2860 scan
= emit_insn_after (gen_align_4 (), scan
);
2862 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
2863 scan
= emit_label_after (lab
, scan
);
2864 scan
= emit_insn_after (gen_consttable_8 (p
->value
, const0_rtx
),
2872 if (p
->mode
!= HImode
)
2874 for (ref
= p
->wend
; ref
; ref
= LABEL_NEXTREF (ref
))
2876 lab
= XEXP (ref
, 0);
2877 scan
= emit_insn_after (gen_consttable_window_end (lab
), scan
);
2882 scan
= emit_insn_after (gen_consttable_end (), scan
);
2883 scan
= emit_barrier_after (scan
);
2885 pool_window_label
= NULL_RTX
;
2886 pool_window_last
= 0;
2889 /* Return nonzero if constant would be an ok source for a
2890 mov.w instead of a mov.l. */
2896 return (GET_CODE (src
) == CONST_INT
2897 && INTVAL (src
) >= -32768
2898 && INTVAL (src
) <= 32767);
2901 /* Nonzero if the insn is a move instruction which needs to be fixed. */
2903 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
2904 CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
2905 need to fix it if the input value is CONST_OK_FOR_I08. */
2911 if (GET_CODE (insn
) == INSN
)
2913 rtx pat
= PATTERN (insn
);
2914 if (GET_CODE (pat
) == PARALLEL
)
2915 pat
= XVECEXP (pat
, 0, 0);
2916 if (GET_CODE (pat
) == SET
2917 /* We can load any 8 bit value if we don't care what the high
2918 order bits end up as. */
2919 && GET_MODE (SET_DEST (pat
)) != QImode
2920 && (CONSTANT_P (SET_SRC (pat
))
2921 /* Match mova_const. */
2922 || (GET_CODE (SET_SRC (pat
)) == UNSPEC
2923 && XINT (SET_SRC (pat
), 1) == UNSPEC_MOVA
2924 && GET_CODE (XVECEXP (SET_SRC (pat
), 0, 0)) == CONST
))
2926 && GET_CODE (SET_SRC (pat
)) == CONST_DOUBLE
2927 && (fp_zero_operand (SET_SRC (pat
))
2928 || fp_one_operand (SET_SRC (pat
)))
2929 /* ??? If this is a -m4 or -m4-single compilation, in general
2930 we don't know the current setting of fpscr, so disable fldi.
2931 There is an exception if this was a register-register move
2932 before reload - and hence it was ascertained that we have
2933 single precision setting - and in a post-reload optimization
2934 we changed this to do a constant load. In that case
2935 we don't have an r0 clobber, hence we must use fldi. */
2936 && (! TARGET_SH4
|| TARGET_FMOVD
2937 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn
), 0, 2), 0))
2939 && GET_CODE (SET_DEST (pat
)) == REG
2940 && FP_REGISTER_P (REGNO (SET_DEST (pat
))))
2941 && (GET_CODE (SET_SRC (pat
)) != CONST_INT
2942 || ! CONST_OK_FOR_I08 (INTVAL (SET_SRC (pat
)))))
2953 return (GET_CODE (insn
) == INSN
2954 && GET_CODE (PATTERN (insn
)) == SET
2955 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC
2956 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPEC_MOVA
2957 /* Don't match mova_const. */
2958 && GET_CODE (XVECEXP (SET_SRC (PATTERN (insn
)), 0, 0)) == LABEL_REF
);
2961 /* Find the last barrier from insn FROM which is close enough to hold the
2962 constant pool. If we can't find one, then create one near the end of
2966 find_barrier (num_mova
, mova
, from
)
2977 int leading_mova
= num_mova
;
2978 rtx barrier_before_mova
= 0, found_barrier
= 0, good_barrier
= 0;
2982 /* For HImode: range is 510, add 4 because pc counts from address of
2983 second instruction after this one, subtract 2 for the jump instruction
2984 that we may need to emit before the table, subtract 2 for the instruction
2985 that fills the jump delay slot (in very rare cases, reorg will take an
2986 instruction from after the constant pool or will leave the delay slot
2987 empty). This gives 510.
2988 For SImode: range is 1020, add 4 because pc counts from address of
2989 second instruction after this one, subtract 2 in case pc is 2 byte
2990 aligned, subtract 2 for the jump instruction that we may need to emit
2991 before the table, subtract 2 for the instruction that fills the jump
2992 delay slot. This gives 1018. */
2994 /* The branch will always be shortened now that the reference address for
2995 forward branches is the successor address, thus we need no longer make
2996 adjustments to the [sh]i_limit for -O0. */
3001 while (from
&& count_si
< si_limit
&& count_hi
< hi_limit
)
3003 int inc
= get_attr_length (from
);
3006 if (GET_CODE (from
) == CODE_LABEL
)
3009 new_align
= 1 << label_to_alignment (from
);
3010 else if (GET_CODE (prev_nonnote_insn (from
)) == BARRIER
)
3011 new_align
= 1 << barrier_align (from
);
3017 if (GET_CODE (from
) == BARRIER
)
3020 found_barrier
= from
;
3022 /* If we are at the end of the function, or in front of an alignment
3023 instruction, we need not insert an extra alignment. We prefer
3024 this kind of barrier. */
3025 if (barrier_align (from
) > 2)
3026 good_barrier
= from
;
3029 if (broken_move (from
))
3032 enum machine_mode mode
;
3034 pat
= PATTERN (from
);
3035 if (GET_CODE (pat
) == PARALLEL
)
3036 pat
= XVECEXP (pat
, 0, 0);
3037 src
= SET_SRC (pat
);
3038 dst
= SET_DEST (pat
);
3039 mode
= GET_MODE (dst
);
3041 /* We must explicitly check the mode, because sometimes the
3042 front end will generate code to load unsigned constants into
3043 HImode targets without properly sign extending them. */
3045 || (mode
== SImode
&& hi_const (src
) && REGNO (dst
) != FPUL_REG
))
3048 /* We put the short constants before the long constants, so
3049 we must count the length of short constants in the range
3050 for the long constants. */
3051 /* ??? This isn't optimal, but is easy to do. */
3056 /* We dump DF/DI constants before SF/SI ones, because
3057 the limit is the same, but the alignment requirements
3058 are higher. We may waste up to 4 additional bytes
3059 for alignment, and the DF/DI constant may have
3060 another SF/SI constant placed before it. */
3061 if (TARGET_SHCOMPACT
3063 && (mode
== DFmode
|| mode
== DImode
))
3068 while (si_align
> 2 && found_si
+ si_align
- 2 > count_si
)
3070 if (found_si
> count_si
)
3071 count_si
= found_si
;
3072 found_si
+= GET_MODE_SIZE (mode
);
3074 si_limit
-= GET_MODE_SIZE (mode
);
3077 /* See the code in machine_dependent_reorg, which has a similar if
3078 statement that generates a new mova insn in many cases. */
3079 if (GET_CODE (dst
) == REG
&& FP_ANY_REGISTER_P (REGNO (dst
)))
3089 barrier_before_mova
= good_barrier
? good_barrier
: found_barrier
;
3091 if (found_si
> count_si
)
3092 count_si
= found_si
;
3094 else if (GET_CODE (from
) == JUMP_INSN
3095 && (GET_CODE (PATTERN (from
)) == ADDR_VEC
3096 || GET_CODE (PATTERN (from
)) == ADDR_DIFF_VEC
))
3100 if (barrier_align (next_real_insn (from
)) == align_jumps_log
)
3102 /* We have just passed the barrier in front of the
3103 ADDR_DIFF_VEC, which is stored in found_barrier. Since
3104 the ADDR_DIFF_VEC is accessed as data, just like our pool
3105 constants, this is a good opportunity to accommodate what
3106 we have gathered so far.
3107 If we waited any longer, we could end up at a barrier in
3108 front of code, which gives worse cache usage for separated
3109 instruction / data caches. */
3110 good_barrier
= found_barrier
;
3115 rtx body
= PATTERN (from
);
3116 inc
= XVECLEN (body
, 1) * GET_MODE_SIZE (GET_MODE (body
));
3119 /* For the SH1, we generate alignments even after jumps-around-jumps. */
3120 else if (GET_CODE (from
) == JUMP_INSN
3122 && ! TARGET_SMALLCODE
)
3128 if (new_align
> si_align
)
3130 si_limit
-= (count_si
- 1) & (new_align
- si_align
);
3131 si_align
= new_align
;
3133 count_si
= (count_si
+ new_align
- 1) & -new_align
;
3138 if (new_align
> hi_align
)
3140 hi_limit
-= (count_hi
- 1) & (new_align
- hi_align
);
3141 hi_align
= new_align
;
3143 count_hi
= (count_hi
+ new_align
- 1) & -new_align
;
3145 from
= NEXT_INSN (from
);
3152 /* Try as we might, the leading mova is out of range. Change
3153 it into a load (which will become a pcload) and retry. */
3154 SET_SRC (PATTERN (mova
)) = XVECEXP (SET_SRC (PATTERN (mova
)), 0, 0);
3155 INSN_CODE (mova
) = -1;
3156 return find_barrier (0, 0, mova
);
3160 /* Insert the constant pool table before the mova instruction,
3161 to prevent the mova label reference from going out of range. */
3163 good_barrier
= found_barrier
= barrier_before_mova
;
3169 if (good_barrier
&& next_real_insn (found_barrier
))
3170 found_barrier
= good_barrier
;
3174 /* We didn't find a barrier in time to dump our stuff,
3175 so we'll make one. */
3176 rtx label
= gen_label_rtx ();
3178 /* If we exceeded the range, then we must back up over the last
3179 instruction we looked at. Otherwise, we just need to undo the
3180 NEXT_INSN at the end of the loop. */
3181 if (count_hi
> hi_limit
|| count_si
> si_limit
)
3182 from
= PREV_INSN (PREV_INSN (from
));
3184 from
= PREV_INSN (from
);
3186 /* Walk back to be just before any jump or label.
3187 Putting it before a label reduces the number of times the branch
3188 around the constant pool table will be hit. Putting it before
3189 a jump makes it more likely that the bra delay slot will be
3191 while (GET_CODE (from
) == JUMP_INSN
|| GET_CODE (from
) == NOTE
3192 || GET_CODE (from
) == CODE_LABEL
)
3193 from
= PREV_INSN (from
);
3195 from
= emit_jump_insn_after (gen_jump (label
), from
);
3196 JUMP_LABEL (from
) = label
;
3197 LABEL_NUSES (label
) = 1;
3198 found_barrier
= emit_barrier_after (from
);
3199 emit_label_after (label
, found_barrier
);
3202 return found_barrier
;
3205 /* If the instruction INSN is implemented by a special function, and we can
3206 positively find the register that is used to call the sfunc, and this
3207 register is not used anywhere else in this instruction - except as the
3208 destination of a set, return this register; else, return 0. */
3210 sfunc_uses_reg (insn
)
3214 rtx pattern
, part
, reg_part
, reg
;
3216 if (GET_CODE (insn
) != INSN
)
3218 pattern
= PATTERN (insn
);
3219 if (GET_CODE (pattern
) != PARALLEL
|| get_attr_type (insn
) != TYPE_SFUNC
)
3222 for (reg_part
= 0, i
= XVECLEN (pattern
, 0) - 1; i
>= 1; i
--)
3224 part
= XVECEXP (pattern
, 0, i
);
3225 if (GET_CODE (part
) == USE
&& GET_MODE (XEXP (part
, 0)) == SImode
)
3230 reg
= XEXP (reg_part
, 0);
3231 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 0; i
--)
3233 part
= XVECEXP (pattern
, 0, i
);
3234 if (part
== reg_part
|| GET_CODE (part
) == CLOBBER
)
3236 if (reg_mentioned_p (reg
, ((GET_CODE (part
) == SET
3237 && GET_CODE (SET_DEST (part
)) == REG
)
3238 ? SET_SRC (part
) : part
)))
3244 /* See if the only way in which INSN uses REG is by calling it, or by
3245 setting it while calling it. Set *SET to a SET rtx if the register
3249 noncall_uses_reg (reg
, insn
, set
)
3258 reg2
= sfunc_uses_reg (insn
);
3259 if (reg2
&& REGNO (reg2
) == REGNO (reg
))
3261 pattern
= single_set (insn
);
3263 && GET_CODE (SET_DEST (pattern
)) == REG
3264 && REGNO (reg
) == REGNO (SET_DEST (pattern
)))
3268 if (GET_CODE (insn
) != CALL_INSN
)
3270 /* We don't use rtx_equal_p because we don't care if the mode is
3272 pattern
= single_set (insn
);
3274 && GET_CODE (SET_DEST (pattern
)) == REG
3275 && REGNO (reg
) == REGNO (SET_DEST (pattern
)))
3281 par
= PATTERN (insn
);
3282 if (GET_CODE (par
) == PARALLEL
)
3283 for (i
= XVECLEN (par
, 0) - 1; i
>= 0; i
--)
3285 part
= XVECEXP (par
, 0, i
);
3286 if (GET_CODE (part
) != SET
&& reg_mentioned_p (reg
, part
))
3289 return reg_mentioned_p (reg
, SET_SRC (pattern
));
3295 pattern
= PATTERN (insn
);
3297 if (GET_CODE (pattern
) == PARALLEL
)
3301 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 1; i
--)
3302 if (reg_mentioned_p (reg
, XVECEXP (pattern
, 0, i
)))
3304 pattern
= XVECEXP (pattern
, 0, 0);
3307 if (GET_CODE (pattern
) == SET
)
3309 if (reg_mentioned_p (reg
, SET_DEST (pattern
)))
3311 /* We don't use rtx_equal_p, because we don't care if the
3312 mode is different. */
3313 if (GET_CODE (SET_DEST (pattern
)) != REG
3314 || REGNO (reg
) != REGNO (SET_DEST (pattern
)))
3320 pattern
= SET_SRC (pattern
);
3323 if (GET_CODE (pattern
) != CALL
3324 || GET_CODE (XEXP (pattern
, 0)) != MEM
3325 || ! rtx_equal_p (reg
, XEXP (XEXP (pattern
, 0), 0)))
3331 /* Given a X, a pattern of an insn or a part of it, return a mask of used
3332 general registers. Bits 0..15 mean that the respective registers
3333 are used as inputs in the instruction. Bits 16..31 mean that the
3334 registers 0..15, respectively, are used as outputs, or are clobbered.
3335 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
3337 regs_used (x
, is_dest
)
3346 code
= GET_CODE (x
);
3351 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x
))) - 1)
3352 << (REGNO (x
) + is_dest
));
3356 rtx y
= SUBREG_REG (x
);
3358 if (GET_CODE (y
) != REG
)
3361 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x
))) - 1)
3363 subreg_regno_offset (REGNO (y
),
3366 GET_MODE (x
)) + is_dest
));
3370 return regs_used (SET_SRC (x
), 0) | regs_used (SET_DEST (x
), 16);
3372 /* If there was a return value, it must have been indicated with USE. */
3387 fmt
= GET_RTX_FORMAT (code
);
3389 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3394 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3395 used
|= regs_used (XVECEXP (x
, i
, j
), is_dest
);
3397 else if (fmt
[i
] == 'e')
3398 used
|= regs_used (XEXP (x
, i
), is_dest
);
3403 /* Create an instruction that prevents redirection of a conditional branch
3404 to the destination of the JUMP with address ADDR.
3405 If the branch needs to be implemented as an indirect jump, try to find
3406 a scratch register for it.
3407 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
3408 If any preceding insn that doesn't fit into a delay slot is good enough,
3409 pass 1. Pass 2 if a definite blocking insn is needed.
3410 -1 is used internally to avoid deep recursion.
3411 If a blocking instruction is made or recognized, return it. */
3414 gen_block_redirect (jump
, addr
, need_block
)
3416 int addr
, need_block
;
3419 rtx prev
= prev_nonnote_insn (jump
);
3422 /* First, check if we already have an instruction that satisfies our need. */
3423 if (prev
&& GET_CODE (prev
) == INSN
&& ! INSN_DELETED_P (prev
))
3425 if (INSN_CODE (prev
) == CODE_FOR_indirect_jump_scratch
)
3427 if (GET_CODE (PATTERN (prev
)) == USE
3428 || GET_CODE (PATTERN (prev
)) == CLOBBER
3429 || get_attr_in_delay_slot (prev
) == IN_DELAY_SLOT_YES
)
3431 else if ((need_block
&= ~1) < 0)
3433 else if (recog_memoized (prev
) == CODE_FOR_block_branch_redirect
)
3436 /* We can't use JUMP_LABEL here because it might be undefined
3437 when not optimizing. */
3438 dest
= XEXP (SET_SRC (PATTERN (jump
)), 0);
3439 /* If the branch is out of range, try to find a scratch register for it. */
3441 && (INSN_ADDRESSES (INSN_UID (dest
)) - addr
+ (unsigned) 4092
3445 /* Don't look for the stack pointer as a scratch register,
3446 it would cause trouble if an interrupt occurred. */
3447 unsigned try = 0x7fff, used
;
3448 int jump_left
= flag_expensive_optimizations
+ 1;
3450 /* It is likely that the most recent eligible instruction is wanted for
3451 the delay slot. Therefore, find out which registers it uses, and
3452 try to avoid using them. */
3454 for (scan
= jump
; (scan
= PREV_INSN (scan
)); )
3458 if (INSN_DELETED_P (scan
))
3460 code
= GET_CODE (scan
);
3461 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
3464 && GET_CODE (PATTERN (scan
)) != USE
3465 && GET_CODE (PATTERN (scan
)) != CLOBBER
3466 && get_attr_in_delay_slot (scan
) == IN_DELAY_SLOT_YES
)
3468 try &= ~regs_used (PATTERN (scan
), 0);
3472 for (used
= dead
= 0, scan
= JUMP_LABEL (jump
);
3473 (scan
= NEXT_INSN (scan
)); )
3477 if (INSN_DELETED_P (scan
))
3479 code
= GET_CODE (scan
);
3480 if (GET_RTX_CLASS (code
) == 'i')
3482 used
|= regs_used (PATTERN (scan
), 0);
3483 if (code
== CALL_INSN
)
3484 used
|= regs_used (CALL_INSN_FUNCTION_USAGE (scan
), 0);
3485 dead
|= (used
>> 16) & ~used
;
3491 if (code
== JUMP_INSN
)
3493 if (jump_left
-- && simplejump_p (scan
))
3494 scan
= JUMP_LABEL (scan
);
3500 /* Mask out the stack pointer again, in case it was
3501 the only 'free' register we have found. */
3504 /* If the immediate destination is still in range, check for possible
3505 threading with a jump beyond the delay slot insn.
3506 Don't check if we are called recursively; the jump has been or will be
3507 checked in a different invocation then. */
3509 else if (optimize
&& need_block
>= 0)
3511 rtx next
= next_active_insn (next_active_insn (dest
));
3512 if (next
&& GET_CODE (next
) == JUMP_INSN
3513 && GET_CODE (PATTERN (next
)) == SET
3514 && recog_memoized (next
) == CODE_FOR_jump_compact
)
3516 dest
= JUMP_LABEL (next
);
3518 && (INSN_ADDRESSES (INSN_UID (dest
)) - addr
+ (unsigned) 4092
3520 gen_block_redirect (next
, INSN_ADDRESSES (INSN_UID (next
)), -1);
3526 rtx reg
= gen_rtx_REG (SImode
, exact_log2 (dead
& -dead
));
3528 /* It would be nice if we could convert the jump into an indirect
3529 jump / far branch right now, and thus exposing all constituent
3530 instructions to further optimization. However, reorg uses
3531 simplejump_p to determine if there is an unconditional jump where
3532 it should try to schedule instructions from the target of the
3533 branch; simplejump_p fails for indirect jumps even if they have
3535 rtx insn
= emit_insn_before (gen_indirect_jump_scratch
3536 (reg
, GEN_INT (INSN_UID (JUMP_LABEL (jump
))))
3538 /* ??? We would like this to have the scope of the jump, but that
3539 scope will change when a delay slot insn of an inner scope is added.
3540 Hence, after delay slot scheduling, we'll have to expect
3541 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
3544 INSN_LOCATOR (insn
) = INSN_LOCATOR (jump
);
3545 INSN_CODE (insn
) = CODE_FOR_indirect_jump_scratch
;
3548 else if (need_block
)
3549 /* We can't use JUMP_LABEL here because it might be undefined
3550 when not optimizing. */
3551 return emit_insn_before (gen_block_branch_redirect
3552 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump
)), 0))))
3557 #define CONDJUMP_MIN -252
3558 #define CONDJUMP_MAX 262
3561 /* A label (to be placed) in front of the jump
3562 that jumps to our ultimate destination. */
3564 /* Where we are going to insert it if we cannot move the jump any farther,
3565 or the jump itself if we have picked up an existing jump. */
3567 /* The ultimate destination. */
3569 struct far_branch
*prev
;
3570 /* If the branch has already been created, its address;
3571 else the address of its first prospective user. */
3575 static void gen_far_branch
PARAMS ((struct far_branch
*));
3576 enum mdep_reorg_phase_e mdep_reorg_phase
;
3579 struct far_branch
*bp
;
3581 rtx insn
= bp
->insert_place
;
3583 rtx label
= gen_label_rtx ();
3585 emit_label_after (label
, insn
);
3588 jump
= emit_jump_insn_after (gen_jump (bp
->far_label
), insn
);
3589 LABEL_NUSES (bp
->far_label
)++;
3592 jump
= emit_jump_insn_after (gen_return (), insn
);
3593 /* Emit a barrier so that reorg knows that any following instructions
3594 are not reachable via a fall-through path.
3595 But don't do this when not optimizing, since we wouldn't suppress the
3596 alignment for the barrier then, and could end up with out-of-range
3597 pc-relative loads. */
3599 emit_barrier_after (jump
);
3600 emit_label_after (bp
->near_label
, insn
);
3601 JUMP_LABEL (jump
) = bp
->far_label
;
3602 if (! invert_jump (insn
, label
, 1))
3605 (gen_stuff_delay_slot
3606 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump
)), 0))),
3607 GEN_INT (recog_memoized (insn
) == CODE_FOR_branch_false
)),
3609 /* Prevent reorg from undoing our splits. */
3610 gen_block_redirect (jump
, bp
->address
+= 2, 2);
3613 /* Fix up ADDR_DIFF_VECs. */
3615 fixup_addr_diff_vecs (first
)
3620 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
3622 rtx vec_lab
, pat
, prev
, prevpat
, x
, braf_label
;
3624 if (GET_CODE (insn
) != JUMP_INSN
3625 || GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
)
3627 pat
= PATTERN (insn
);
3628 vec_lab
= XEXP (XEXP (pat
, 0), 0);
3630 /* Search the matching casesi_jump_2. */
3631 for (prev
= vec_lab
; ; prev
= PREV_INSN (prev
))
3633 if (GET_CODE (prev
) != JUMP_INSN
)
3635 prevpat
= PATTERN (prev
);
3636 if (GET_CODE (prevpat
) != PARALLEL
|| XVECLEN (prevpat
, 0) != 2)
3638 x
= XVECEXP (prevpat
, 0, 1);
3639 if (GET_CODE (x
) != USE
)
3642 if (GET_CODE (x
) == LABEL_REF
&& XEXP (x
, 0) == vec_lab
)
3646 /* Emit the reference label of the braf where it belongs, right after
3647 the casesi_jump_2 (i.e. braf). */
3648 braf_label
= XEXP (XEXP (SET_SRC (XVECEXP (prevpat
, 0, 0)), 1), 0);
3649 emit_label_after (braf_label
, prev
);
3651 /* Fix up the ADDR_DIF_VEC to be relative
3652 to the reference address of the braf. */
3653 XEXP (XEXP (pat
, 0), 0) = braf_label
;
3657 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
3658 a barrier. Return the base 2 logarithm of the desired alignment. */
3660 barrier_align (barrier_or_label
)
3661 rtx barrier_or_label
;
3663 rtx next
= next_real_insn (barrier_or_label
), pat
, prev
;
3664 int slot
, credit
, jump_to_next
= 0;
3669 pat
= PATTERN (next
);
3671 if (GET_CODE (pat
) == ADDR_DIFF_VEC
)
3674 if (GET_CODE (pat
) == UNSPEC_VOLATILE
&& XINT (pat
, 1) == UNSPECV_ALIGN
)
3675 /* This is a barrier in front of a constant table. */
3678 prev
= prev_real_insn (barrier_or_label
);
3679 if (GET_CODE (PATTERN (prev
)) == ADDR_DIFF_VEC
)
3681 pat
= PATTERN (prev
);
3682 /* If this is a very small table, we want to keep the alignment after
3683 the table to the minimum for proper code alignment. */
3684 return ((TARGET_SMALLCODE
3685 || ((unsigned) XVECLEN (pat
, 1) * GET_MODE_SIZE (GET_MODE (pat
))
3686 <= (unsigned)1 << (CACHE_LOG
- 2)))
3687 ? 1 << TARGET_SHMEDIA
: align_jumps_log
);
3690 if (TARGET_SMALLCODE
)
3693 if (! TARGET_SH2
|| ! optimize
)
3694 return align_jumps_log
;
3696 /* When fixing up pcloads, a constant table might be inserted just before
3697 the basic block that ends with the barrier. Thus, we can't trust the
3698 instruction lengths before that. */
3699 if (mdep_reorg_phase
> SH_FIXUP_PCLOAD
)
3701 /* Check if there is an immediately preceding branch to the insn beyond
3702 the barrier. We must weight the cost of discarding useful information
3703 from the current cache line when executing this branch and there is
3704 an alignment, against that of fetching unneeded insn in front of the
3705 branch target when there is no alignment. */
3707 /* There are two delay_slot cases to consider. One is the simple case
3708 where the preceding branch is to the insn beyond the barrier (simple
3709 delay slot filling), and the other is where the preceding branch has
3710 a delay slot that is a duplicate of the insn after the barrier
3711 (fill_eager_delay_slots) and the branch is to the insn after the insn
3712 after the barrier. */
3714 /* PREV is presumed to be the JUMP_INSN for the barrier under
3715 investigation. Skip to the insn before it. */
3716 prev
= prev_real_insn (prev
);
3718 for (slot
= 2, credit
= (1 << (CACHE_LOG
- 2)) + 2;
3719 credit
>= 0 && prev
&& GET_CODE (prev
) == INSN
;
3720 prev
= prev_real_insn (prev
))
3723 if (GET_CODE (PATTERN (prev
)) == USE
3724 || GET_CODE (PATTERN (prev
)) == CLOBBER
)
3726 if (GET_CODE (PATTERN (prev
)) == SEQUENCE
)
3728 prev
= XVECEXP (PATTERN (prev
), 0, 1);
3729 if (INSN_UID (prev
) == INSN_UID (next
))
3731 /* Delay slot was filled with insn at jump target. */
3738 get_attr_in_delay_slot (prev
) == IN_DELAY_SLOT_YES
)
3740 credit
-= get_attr_length (prev
);
3743 && GET_CODE (prev
) == JUMP_INSN
3744 && JUMP_LABEL (prev
))
3748 || next_real_insn (JUMP_LABEL (prev
)) == next
3749 /* If relax_delay_slots() decides NEXT was redundant
3750 with some previous instruction, it will have
3751 redirected PREV's jump to the following insn. */
3752 || JUMP_LABEL (prev
) == next_nonnote_insn (next
)
3753 /* There is no upper bound on redundant instructions
3754 that might have been skipped, but we must not put an
3755 alignment where none had been before. */
3756 || (x
= (NEXT_INSN (NEXT_INSN (PREV_INSN (prev
)))),
3758 && (INSN_CODE (x
) == CODE_FOR_block_branch_redirect
3759 || INSN_CODE (x
) == CODE_FOR_indirect_jump_scratch
3760 || INSN_CODE (x
) == CODE_FOR_stuff_delay_slot
))))
3762 rtx pat
= PATTERN (prev
);
3763 if (GET_CODE (pat
) == PARALLEL
)
3764 pat
= XVECEXP (pat
, 0, 0);
3765 if (credit
- slot
>= (GET_CODE (SET_SRC (pat
)) == PC
? 2 : 0))
3771 return align_jumps_log
;
3774 /* If we are inside a phony loop, almost any kind of label can turn up as the
3775 first one in the loop. Aligning a braf label causes incorrect switch
3776 destination addresses; we can detect braf labels because they are
3777 followed by a BARRIER.
3778 Applying loop alignment to small constant or switch tables is a waste
3779 of space, so we suppress this too. */
3781 sh_loop_align (label
)
3787 next
= next_nonnote_insn (next
);
3788 while (next
&& GET_CODE (next
) == CODE_LABEL
);
3792 || GET_CODE (PATTERN (next
)) == ADDR_DIFF_VEC
3793 || recog_memoized (next
) == CODE_FOR_consttable_2
)
3796 return align_loops_log
;
3799 /* Do a final pass over the function, just before delayed branch
3805 rtx first
, insn
, mova
= NULL_RTX
;
3807 rtx r0_rtx
= gen_rtx_REG (Pmode
, 0);
3808 rtx r0_inc_rtx
= gen_rtx_POST_INC (Pmode
, r0_rtx
);
3810 first
= get_insns ();
3812 /* We must split call insns before introducing `mova's. If we're
3813 optimizing, they'll have already been split. Otherwise, make
3814 sure we don't split them too late. */
3816 split_all_insns_noflow ();
3821 /* If relaxing, generate pseudo-ops to associate function calls with
3822 the symbols they call. It does no harm to not generate these
3823 pseudo-ops. However, when we can generate them, it enables to
3824 linker to potentially relax the jsr to a bsr, and eliminate the
3825 register load and, possibly, the constant pool entry. */
3827 mdep_reorg_phase
= SH_INSERT_USES_LABELS
;
3830 /* Remove all REG_LABEL notes. We want to use them for our own
3831 purposes. This works because none of the remaining passes
3832 need to look at them.
3834 ??? But it may break in the future. We should use a machine
3835 dependent REG_NOTE, or some other approach entirely. */
3836 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
3842 while ((note
= find_reg_note (insn
, REG_LABEL
, NULL_RTX
)) != 0)
3843 remove_note (insn
, note
);
3847 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
3849 rtx pattern
, reg
, link
, set
, scan
, dies
, label
;
3850 int rescan
= 0, foundinsn
= 0;
3852 if (GET_CODE (insn
) == CALL_INSN
)
3854 pattern
= PATTERN (insn
);
3856 if (GET_CODE (pattern
) == PARALLEL
)
3857 pattern
= XVECEXP (pattern
, 0, 0);
3858 if (GET_CODE (pattern
) == SET
)
3859 pattern
= SET_SRC (pattern
);
3861 if (GET_CODE (pattern
) != CALL
3862 || GET_CODE (XEXP (pattern
, 0)) != MEM
)
3865 reg
= XEXP (XEXP (pattern
, 0), 0);
3869 reg
= sfunc_uses_reg (insn
);
3874 if (GET_CODE (reg
) != REG
)
3877 /* This is a function call via REG. If the only uses of REG
3878 between the time that it is set and the time that it dies
3879 are in function calls, then we can associate all the
3880 function calls with the setting of REG. */
3882 for (link
= LOG_LINKS (insn
); link
; link
= XEXP (link
, 1))
3884 if (REG_NOTE_KIND (link
) != 0)
3886 set
= single_set (XEXP (link
, 0));
3887 if (set
&& rtx_equal_p (reg
, SET_DEST (set
)))
3889 link
= XEXP (link
, 0);
3896 /* ??? Sometimes global register allocation will have
3897 deleted the insn pointed to by LOG_LINKS. Try
3898 scanning backward to find where the register is set. */
3899 for (scan
= PREV_INSN (insn
);
3900 scan
&& GET_CODE (scan
) != CODE_LABEL
;
3901 scan
= PREV_INSN (scan
))
3903 if (! INSN_P (scan
))
3906 if (! reg_mentioned_p (reg
, scan
))
3909 if (noncall_uses_reg (reg
, scan
, &set
))
3923 /* The register is set at LINK. */
3925 /* We can only optimize the function call if the register is
3926 being set to a symbol. In theory, we could sometimes
3927 optimize calls to a constant location, but the assembler
3928 and linker do not support that at present. */
3929 if (GET_CODE (SET_SRC (set
)) != SYMBOL_REF
3930 && GET_CODE (SET_SRC (set
)) != LABEL_REF
)
3933 /* Scan forward from LINK to the place where REG dies, and
3934 make sure that the only insns which use REG are
3935 themselves function calls. */
3937 /* ??? This doesn't work for call targets that were allocated
3938 by reload, since there may not be a REG_DEAD note for the
3942 for (scan
= NEXT_INSN (link
); scan
; scan
= NEXT_INSN (scan
))
3946 /* Don't try to trace forward past a CODE_LABEL if we haven't
3947 seen INSN yet. Ordinarily, we will only find the setting insn
3948 in LOG_LINKS if it is in the same basic block. However,
3949 cross-jumping can insert code labels in between the load and
3950 the call, and can result in situations where a single call
3951 insn may have two targets depending on where we came from. */
3953 if (GET_CODE (scan
) == CODE_LABEL
&& ! foundinsn
)
3956 if (! INSN_P (scan
))
3959 /* Don't try to trace forward past a JUMP. To optimize
3960 safely, we would have to check that all the
3961 instructions at the jump destination did not use REG. */
3963 if (GET_CODE (scan
) == JUMP_INSN
)
3966 if (! reg_mentioned_p (reg
, scan
))
3969 if (noncall_uses_reg (reg
, scan
, &scanset
))
3976 && (GET_CODE (scan
) == CALL_INSN
|| sfunc_uses_reg (scan
)))
3978 /* There is a function call to this register other
3979 than the one we are checking. If we optimize
3980 this call, we need to rescan again below. */
3984 /* ??? We shouldn't have to worry about SCANSET here.
3985 We should just be able to check for a REG_DEAD note
3986 on a function call. However, the REG_DEAD notes are
3987 apparently not dependable around libcalls; c-torture
3988 execute/920501-2 is a test case. If SCANSET is set,
3989 then this insn sets the register, so it must have
3990 died earlier. Unfortunately, this will only handle
3991 the cases in which the register is, in fact, set in a
3994 /* ??? We shouldn't have to use FOUNDINSN here.
3995 However, the LOG_LINKS fields are apparently not
3996 entirely reliable around libcalls;
3997 newlib/libm/math/e_pow.c is a test case. Sometimes
3998 an insn will appear in LOG_LINKS even though it is
3999 not the most recent insn which sets the register. */
4003 || find_reg_note (scan
, REG_DEAD
, reg
)))
4012 /* Either there was a branch, or some insn used REG
4013 other than as a function call address. */
4017 /* Create a code label, and put it in a REG_LABEL note on
4018 the insn which sets the register, and on each call insn
4019 which uses the register. In final_prescan_insn we look
4020 for the REG_LABEL notes, and output the appropriate label
4023 label
= gen_label_rtx ();
4024 REG_NOTES (link
) = gen_rtx_INSN_LIST (REG_LABEL
, label
,
4026 REG_NOTES (insn
) = gen_rtx_INSN_LIST (REG_LABEL
, label
,
4035 scan
= NEXT_INSN (scan
);
4037 && ((GET_CODE (scan
) == CALL_INSN
4038 && reg_mentioned_p (reg
, scan
))
4039 || ((reg2
= sfunc_uses_reg (scan
))
4040 && REGNO (reg2
) == REGNO (reg
))))
4042 = gen_rtx_INSN_LIST (REG_LABEL
, label
, REG_NOTES (scan
));
4044 while (scan
!= dies
);
4050 fixup_addr_diff_vecs (first
);
4054 mdep_reorg_phase
= SH_SHORTEN_BRANCHES0
;
4055 shorten_branches (first
);
4057 /* Scan the function looking for move instructions which have to be
4058 changed to pc-relative loads and insert the literal tables. */
4060 mdep_reorg_phase
= SH_FIXUP_PCLOAD
;
4061 for (insn
= first
, num_mova
= 0; insn
; insn
= NEXT_INSN (insn
))
4068 else if (GET_CODE (insn
) == JUMP_INSN
4069 && GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
4077 /* Some code might have been inserted between the mova and
4078 its ADDR_DIFF_VEC. Check if the mova is still in range. */
4079 for (scan
= mova
, total
= 0; scan
!= insn
; scan
= NEXT_INSN (scan
))
4080 total
+= get_attr_length (scan
);
4082 /* range of mova is 1020, add 4 because pc counts from address of
4083 second instruction after this one, subtract 2 in case pc is 2
4084 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
4085 cancels out with alignment effects of the mova itself. */
4088 /* Change the mova into a load, and restart scanning
4089 there. broken_move will then return true for mova. */
4090 SET_SRC (PATTERN (mova
))
4091 = XVECEXP (SET_SRC (PATTERN (mova
)), 0, 0);
4092 INSN_CODE (mova
) = -1;
4096 if (broken_move (insn
))
4099 /* Scan ahead looking for a barrier to stick the constant table
4101 rtx barrier
= find_barrier (num_mova
, mova
, insn
);
4102 rtx last_float_move
= NULL_RTX
, last_float
= 0, *last_float_addr
= NULL
;
4104 if (num_mova
&& ! mova_p (mova
))
4106 /* find_barrier had to change the first mova into a
4107 pcload; thus, we have to start with this new pcload. */
4111 /* Now find all the moves between the points and modify them. */
4112 for (scan
= insn
; scan
!= barrier
; scan
= NEXT_INSN (scan
))
4114 if (GET_CODE (scan
) == CODE_LABEL
)
4116 if (broken_move (scan
))
4118 rtx
*patp
= &PATTERN (scan
), pat
= *patp
;
4122 enum machine_mode mode
;
4124 if (GET_CODE (pat
) == PARALLEL
)
4125 patp
= &XVECEXP (pat
, 0, 0), pat
= *patp
;
4126 src
= SET_SRC (pat
);
4127 dst
= SET_DEST (pat
);
4128 mode
= GET_MODE (dst
);
4130 if (mode
== SImode
&& hi_const (src
)
4131 && REGNO (dst
) != FPUL_REG
)
4136 while (GET_CODE (dst
) == SUBREG
)
4138 offset
+= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
4139 GET_MODE (SUBREG_REG (dst
)),
4142 dst
= SUBREG_REG (dst
);
4144 dst
= gen_rtx_REG (HImode
, REGNO (dst
) + offset
);
4147 if (GET_CODE (dst
) == REG
&& FP_ANY_REGISTER_P (REGNO (dst
)))
4149 /* This must be an insn that clobbers r0. */
4150 rtx clobber
= XVECEXP (PATTERN (scan
), 0,
4151 XVECLEN (PATTERN (scan
), 0) - 1);
4153 if (GET_CODE (clobber
) != CLOBBER
4154 || ! rtx_equal_p (XEXP (clobber
, 0), r0_rtx
))
4158 && reg_set_between_p (r0_rtx
, last_float_move
, scan
))
4162 && GET_MODE_SIZE (mode
) != 4
4163 && GET_MODE_SIZE (GET_MODE (last_float
)) == 4)
4165 lab
= add_constant (src
, mode
, last_float
);
4167 emit_insn_before (gen_mova (lab
), scan
);
4170 /* There will be a REG_UNUSED note for r0 on
4171 LAST_FLOAT_MOVE; we have to change it to REG_INC,
4172 lest reorg:mark_target_live_regs will not
4173 consider r0 to be used, and we end up with delay
4174 slot insn in front of SCAN that clobbers r0. */
4176 = find_regno_note (last_float_move
, REG_UNUSED
, 0);
4178 /* If we are not optimizing, then there may not be
4181 PUT_MODE (note
, REG_INC
);
4183 *last_float_addr
= r0_inc_rtx
;
4185 last_float_move
= scan
;
4187 newsrc
= gen_rtx (MEM
, mode
,
4188 (((TARGET_SH4
&& ! TARGET_FMOVD
)
4189 || REGNO (dst
) == FPUL_REG
)
4192 last_float_addr
= &XEXP (newsrc
, 0);
4194 /* Remove the clobber of r0. */
4195 XEXP (clobber
, 0) = gen_rtx_SCRATCH (Pmode
);
4196 RTX_UNCHANGING_P (newsrc
) = 1;
4198 /* This is a mova needing a label. Create it. */
4199 else if (GET_CODE (src
) == UNSPEC
4200 && XINT (src
, 1) == UNSPEC_MOVA
4201 && GET_CODE (XVECEXP (src
, 0, 0)) == CONST
)
4203 lab
= add_constant (XVECEXP (src
, 0, 0), mode
, 0);
4204 newsrc
= gen_rtx_LABEL_REF (VOIDmode
, lab
);
4205 newsrc
= gen_rtx_UNSPEC (SImode
,
4206 gen_rtvec (1, newsrc
),
4211 lab
= add_constant (src
, mode
, 0);
4212 newsrc
= gen_rtx_MEM (mode
,
4213 gen_rtx_LABEL_REF (VOIDmode
, lab
));
4214 RTX_UNCHANGING_P (newsrc
) = 1;
4216 *patp
= gen_rtx_SET (VOIDmode
, dst
, newsrc
);
4217 INSN_CODE (scan
) = -1;
4220 dump_table (barrier
);
4225 mdep_reorg_phase
= SH_SHORTEN_BRANCHES1
;
4226 INSN_ADDRESSES_FREE ();
4227 split_branches (first
);
4229 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
4230 also has an effect on the register that holds the address of the sfunc.
4231 Insert an extra dummy insn in front of each sfunc that pretends to
4232 use this register. */
4233 if (flag_delayed_branch
)
4235 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
4237 rtx reg
= sfunc_uses_reg (insn
);
4241 emit_insn_before (gen_use_sfunc_addr (reg
), insn
);
4245 /* fpscr is not actually a user variable, but we pretend it is for the
4246 sake of the previous optimization passes, since we want it handled like
4247 one. However, we don't have any debugging information for it, so turn
4248 it into a non-user variable now. */
4250 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
4252 mdep_reorg_phase
= SH_AFTER_MDEP_REORG
;
4256 get_dest_uid (label
, max_uid
)
4260 rtx dest
= next_real_insn (label
);
4263 /* This can happen for an undefined label. */
4265 dest_uid
= INSN_UID (dest
);
4266 /* If this is a newly created branch redirection blocking instruction,
4267 we cannot index the branch_uid or insn_addresses arrays with its
4268 uid. But then, we won't need to, because the actual destination is
4269 the following branch. */
4270 while (dest_uid
>= max_uid
)
4272 dest
= NEXT_INSN (dest
);
4273 dest_uid
= INSN_UID (dest
);
4275 if (GET_CODE (dest
) == JUMP_INSN
&& GET_CODE (PATTERN (dest
)) == RETURN
)
4280 /* Split condbranches that are out of range. Also add clobbers for
4281 scratch registers that are needed in far jumps.
4282 We do this before delay slot scheduling, so that it can take our
4283 newly created instructions into account. It also allows us to
4284 find branches with common targets more easily. */
4287 split_branches (first
)
4291 struct far_branch
**uid_branch
, *far_branch_list
= 0;
4292 int max_uid
= get_max_uid ();
4294 /* Find out which branches are out of range. */
4295 shorten_branches (first
);
4297 uid_branch
= (struct far_branch
**) alloca (max_uid
* sizeof *uid_branch
);
4298 memset ((char *) uid_branch
, 0, max_uid
* sizeof *uid_branch
);
4300 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
4301 if (! INSN_P (insn
))
4303 else if (INSN_DELETED_P (insn
))
4305 /* Shorten_branches would split this instruction again,
4306 so transform it into a note. */
4307 PUT_CODE (insn
, NOTE
);
4308 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
4309 NOTE_SOURCE_FILE (insn
) = 0;
4311 else if (GET_CODE (insn
) == JUMP_INSN
4312 /* Don't mess with ADDR_DIFF_VEC */
4313 && (GET_CODE (PATTERN (insn
)) == SET
4314 || GET_CODE (PATTERN (insn
)) == RETURN
))
4316 enum attr_type type
= get_attr_type (insn
);
4317 if (type
== TYPE_CBRANCH
)
4321 if (get_attr_length (insn
) > 4)
4323 rtx src
= SET_SRC (PATTERN (insn
));
4324 rtx olabel
= XEXP (XEXP (src
, 1), 0);
4325 int addr
= INSN_ADDRESSES (INSN_UID (insn
));
4327 int dest_uid
= get_dest_uid (olabel
, max_uid
);
4328 struct far_branch
*bp
= uid_branch
[dest_uid
];
4330 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
4331 the label if the LABEL_NUSES count drops to zero. There is
4332 always a jump_optimize pass that sets these values, but it
4333 proceeds to delete unreferenced code, and then if not
4334 optimizing, to un-delete the deleted instructions, thus
4335 leaving labels with too low uses counts. */
4338 JUMP_LABEL (insn
) = olabel
;
4339 LABEL_NUSES (olabel
)++;
4343 bp
= (struct far_branch
*) alloca (sizeof *bp
);
4344 uid_branch
[dest_uid
] = bp
;
4345 bp
->prev
= far_branch_list
;
4346 far_branch_list
= bp
;
4348 = XEXP (XEXP (SET_SRC (PATTERN (insn
)), 1), 0);
4349 LABEL_NUSES (bp
->far_label
)++;
4353 label
= bp
->near_label
;
4354 if (! label
&& bp
->address
- addr
>= CONDJUMP_MIN
)
4356 rtx block
= bp
->insert_place
;
4358 if (GET_CODE (PATTERN (block
)) == RETURN
)
4359 block
= PREV_INSN (block
);
4361 block
= gen_block_redirect (block
,
4363 label
= emit_label_after (gen_label_rtx (),
4365 bp
->near_label
= label
;
4367 else if (label
&& ! NEXT_INSN (label
))
4369 if (addr
+ 2 - bp
->address
<= CONDJUMP_MAX
)
4370 bp
->insert_place
= insn
;
4372 gen_far_branch (bp
);
4376 || (NEXT_INSN (label
) && bp
->address
- addr
< CONDJUMP_MIN
))
4378 bp
->near_label
= label
= gen_label_rtx ();
4379 bp
->insert_place
= insn
;
4382 if (! redirect_jump (insn
, label
, 1))
4387 /* get_attr_length (insn) == 2 */
4388 /* Check if we have a pattern where reorg wants to redirect
4389 the branch to a label from an unconditional branch that
4391 /* We can't use JUMP_LABEL here because it might be undefined
4392 when not optimizing. */
4393 /* A syntax error might cause beyond to be NULL_RTX. */
4395 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn
)), 1),
4399 && (GET_CODE (beyond
) == JUMP_INSN
4400 || ((beyond
= next_active_insn (beyond
))
4401 && GET_CODE (beyond
) == JUMP_INSN
))
4402 && GET_CODE (PATTERN (beyond
)) == SET
4403 && recog_memoized (beyond
) == CODE_FOR_jump_compact
4405 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond
)), 0)))
4406 - INSN_ADDRESSES (INSN_UID (insn
)) + (unsigned) 252)
4408 gen_block_redirect (beyond
,
4409 INSN_ADDRESSES (INSN_UID (beyond
)), 1);
4412 next
= next_active_insn (insn
);
4414 if ((GET_CODE (next
) == JUMP_INSN
4415 || GET_CODE (next
= next_active_insn (next
)) == JUMP_INSN
)
4416 && GET_CODE (PATTERN (next
)) == SET
4417 && recog_memoized (next
) == CODE_FOR_jump_compact
4419 (INSN_UID (XEXP (SET_SRC (PATTERN (next
)), 0)))
4420 - INSN_ADDRESSES (INSN_UID (insn
)) + (unsigned) 252)
4422 gen_block_redirect (next
, INSN_ADDRESSES (INSN_UID (next
)), 1);
4424 else if (type
== TYPE_JUMP
|| type
== TYPE_RETURN
)
4426 int addr
= INSN_ADDRESSES (INSN_UID (insn
));
4429 struct far_branch
*bp
;
4431 if (type
== TYPE_JUMP
)
4433 far_label
= XEXP (SET_SRC (PATTERN (insn
)), 0);
4434 dest_uid
= get_dest_uid (far_label
, max_uid
);
4437 /* Parse errors can lead to labels outside
4439 if (! NEXT_INSN (far_label
))
4444 JUMP_LABEL (insn
) = far_label
;
4445 LABEL_NUSES (far_label
)++;
4447 redirect_jump (insn
, NULL_RTX
, 1);
4451 bp
= uid_branch
[dest_uid
];
4454 bp
= (struct far_branch
*) alloca (sizeof *bp
);
4455 uid_branch
[dest_uid
] = bp
;
4456 bp
->prev
= far_branch_list
;
4457 far_branch_list
= bp
;
4459 bp
->far_label
= far_label
;
4461 LABEL_NUSES (far_label
)++;
4463 else if (bp
->near_label
&& ! NEXT_INSN (bp
->near_label
))
4464 if (addr
- bp
->address
<= CONDJUMP_MAX
)
4465 emit_label_after (bp
->near_label
, PREV_INSN (insn
));
4468 gen_far_branch (bp
);
4474 bp
->insert_place
= insn
;
4476 emit_insn_before (gen_block_branch_redirect (const0_rtx
), insn
);
4478 gen_block_redirect (insn
, addr
, bp
->near_label
? 2 : 0);
4481 /* Generate all pending far branches,
4482 and free our references to the far labels. */
4483 while (far_branch_list
)
4485 if (far_branch_list
->near_label
4486 && ! NEXT_INSN (far_branch_list
->near_label
))
4487 gen_far_branch (far_branch_list
);
4489 && far_branch_list
->far_label
4490 && ! --LABEL_NUSES (far_branch_list
->far_label
))
4491 delete_insn (far_branch_list
->far_label
);
4492 far_branch_list
= far_branch_list
->prev
;
4495 /* Instruction length information is no longer valid due to the new
4496 instructions that have been generated. */
4497 init_insn_lengths ();
4500 /* Dump out instruction addresses, which is useful for debugging the
4501 constant pool table stuff.
4503 If relaxing, output the label and pseudo-ops used to link together
4504 calls and the instruction which set the registers. */
4506 /* ??? The addresses printed by this routine for insns are nonsense for
4507 insns which are inside of a sequence where none of the inner insns have
4508 variable length. This is because the second pass of shorten_branches
4509 does not bother to update them. */
4512 final_prescan_insn (insn
, opvec
, noperands
)
4514 rtx
*opvec ATTRIBUTE_UNUSED
;
4515 int noperands ATTRIBUTE_UNUSED
;
4517 if (TARGET_DUMPISIZE
)
4518 fprintf (asm_out_file
, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn
)));
4524 note
= find_reg_note (insn
, REG_LABEL
, NULL_RTX
);
4529 pattern
= PATTERN (insn
);
4530 if (GET_CODE (pattern
) == PARALLEL
)
4531 pattern
= XVECEXP (pattern
, 0, 0);
4532 if (GET_CODE (pattern
) == CALL
4533 || (GET_CODE (pattern
) == SET
4534 && (GET_CODE (SET_SRC (pattern
)) == CALL
4535 || get_attr_type (insn
) == TYPE_SFUNC
)))
4536 asm_fprintf (asm_out_file
, "\t.uses %LL%d\n",
4537 CODE_LABEL_NUMBER (XEXP (note
, 0)));
4538 else if (GET_CODE (pattern
) == SET
)
4539 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
4540 CODE_LABEL_NUMBER (XEXP (note
, 0)));
4547 /* Dump out any constants accumulated in the final pass. These will
4551 output_jump_label_table ()
4557 fprintf (asm_out_file
, "\t.align 2\n");
4558 for (i
= 0; i
< pool_size
; i
++)
4560 pool_node
*p
= &pool_vector
[i
];
4562 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
4563 CODE_LABEL_NUMBER (p
->label
));
4564 output_asm_insn (".long %O0", &p
->value
);
4572 /* A full frame looks like:
4576 [ if current_function_anonymous_args
4589 local-0 <- fp points here. */
4591 /* Number of bytes pushed for anonymous args, used to pass information
4592 between expand_prologue and expand_epilogue. */
4594 static int extra_push
;
4596 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register to be
4597 adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's
4598 for an epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET
4599 of all the registers that are about to be restored, and hence dead. */
4602 output_stack_adjust (int size
, rtx reg
, int epilogue_p
,
4603 HARD_REG_SET
*live_regs_mask
)
4605 rtx (*emit_fn
) (rtx
) = epilogue_p
? &emit_insn
: &frame_insn
;
4608 HOST_WIDE_INT align
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
4613 if (CONST_OK_FOR_ADD (size
))
4614 emit_fn (GEN_ADD3 (reg
, reg
, GEN_INT (size
)));
4615 /* Try to do it with two partial adjustments; however, we must make
4616 sure that the stack is properly aligned at all times, in case
4617 an interrupt occurs between the two partial adjustments. */
4618 else if (CONST_OK_FOR_ADD (size
/ 2 & -align
)
4619 && CONST_OK_FOR_ADD (size
- (size
/ 2 & -align
)))
4621 emit_fn (GEN_ADD3 (reg
, reg
, GEN_INT (size
/ 2 & -align
)));
4622 emit_fn (GEN_ADD3 (reg
, reg
, GEN_INT (size
- (size
/ 2 & -align
))));
4628 int temp
= epilogue_p
? 7 : (TARGET_SH5
? 0 : 1);
4631 /* If TEMP is invalid, we could temporarily save a general
4632 register to MACL. However, there is currently no need
4633 to handle this case, so just abort when we see it. */
4634 if (current_function_interrupt
4635 || ! call_used_regs
[temp
] || fixed_regs
[temp
])
4637 if (temp
< 0 && ! current_function_interrupt
)
4640 COPY_HARD_REG_SET (temps
, call_used_reg_set
);
4641 AND_COMPL_HARD_REG_SET (temps
, call_fixed_reg_set
);
4644 for (i
= 0; i
< HARD_REGNO_NREGS (FIRST_RET_REG
, DImode
); i
++)
4645 CLEAR_HARD_REG_BIT (temps
, FIRST_RET_REG
+ i
);
4646 if (current_function_calls_eh_return
)
4648 CLEAR_HARD_REG_BIT (temps
, EH_RETURN_STACKADJ_REGNO
);
4649 for (i
= 0; i
<= 3; i
++)
4650 CLEAR_HARD_REG_BIT (temps
, EH_RETURN_DATA_REGNO (i
));
4655 for (i
= FIRST_PARM_REG
;
4656 i
< FIRST_PARM_REG
+ NPARM_REGS (SImode
); i
++)
4657 CLEAR_HARD_REG_BIT (temps
, i
);
4658 if (current_function_needs_context
)
4659 CLEAR_HARD_REG_BIT (temps
, STATIC_CHAIN_REGNUM
);
4661 temp
= scavenge_reg (&temps
);
4663 if (temp
< 0 && live_regs_mask
)
4664 temp
= scavenge_reg (live_regs_mask
);
4667 const_reg
= gen_rtx_REG (GET_MODE (reg
), temp
);
4669 /* If SIZE is negative, subtract the positive value.
4670 This sometimes allows a constant pool entry to be shared
4671 between prologue and epilogue code. */
4674 emit_insn (GEN_MOV (const_reg
, GEN_INT (-size
)));
4675 insn
= emit_fn (GEN_SUB3 (reg
, reg
, const_reg
));
4679 emit_insn (GEN_MOV (const_reg
, GEN_INT (size
)));
4680 insn
= emit_fn (GEN_ADD3 (reg
, reg
, const_reg
));
4684 = (gen_rtx_EXPR_LIST
4685 (REG_FRAME_RELATED_EXPR
,
4686 gen_rtx_SET (VOIDmode
, reg
,
4687 gen_rtx_PLUS (SImode
, reg
, GEN_INT (size
))),
4698 RTX_FRAME_RELATED_P (x
) = 1;
4702 /* Output RTL to push register RN onto the stack. */
4710 x
= gen_push_fpul ();
4711 else if (rn
== FPSCR_REG
)
4712 x
= gen_push_fpscr ();
4713 else if (TARGET_SH4
&& TARGET_FMOVD
&& ! TARGET_FPU_SINGLE
4714 && FP_OR_XD_REGISTER_P (rn
))
4716 if (FP_REGISTER_P (rn
) && (rn
- FIRST_FP_REG
) & 1)
4718 x
= gen_push_4 (gen_rtx_REG (DFmode
, rn
));
4720 else if (TARGET_SH2E
&& FP_REGISTER_P (rn
))
4721 x
= gen_push_e (gen_rtx_REG (SFmode
, rn
));
4723 x
= gen_push (gen_rtx_REG (SImode
, rn
));
4727 = gen_rtx_EXPR_LIST (REG_INC
,
4728 gen_rtx_REG (SImode
, STACK_POINTER_REGNUM
), 0);
4732 /* Output RTL to pop register RN from the stack. */
4740 x
= gen_pop_fpul ();
4741 else if (rn
== FPSCR_REG
)
4742 x
= gen_pop_fpscr ();
4743 else if (TARGET_SH4
&& TARGET_FMOVD
&& ! TARGET_FPU_SINGLE
4744 && FP_OR_XD_REGISTER_P (rn
))
4746 if (FP_REGISTER_P (rn
) && (rn
- FIRST_FP_REG
) & 1)
4748 x
= gen_pop_4 (gen_rtx_REG (DFmode
, rn
));
4750 else if (TARGET_SH2E
&& FP_REGISTER_P (rn
))
4751 x
= gen_pop_e (gen_rtx_REG (SFmode
, rn
));
4753 x
= gen_pop (gen_rtx_REG (SImode
, rn
));
4757 = gen_rtx_EXPR_LIST (REG_INC
,
4758 gen_rtx_REG (SImode
, STACK_POINTER_REGNUM
), 0);
4761 /* Generate code to push the regs specified in the mask. */
4764 push_regs (mask
, interrupt_handler
)
4766 int interrupt_handler
;
4771 /* Push PR last; this gives better latencies after the prologue, and
4772 candidates for the return delay slot when there are no general
4773 registers pushed. */
4774 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4776 /* If this is an interrupt handler, and the SZ bit varies,
4777 and we have to push any floating point register, we need
4778 to switch to the correct precision first. */
4779 if (i
== FIRST_FP_REG
&& interrupt_handler
&& TARGET_FMOVD
4780 && hard_regs_intersect_p (mask
, ®_class_contents
[DF_REGS
]))
4782 HARD_REG_SET unsaved
;
4785 COMPL_HARD_REG_SET(unsaved
, *mask
);
4786 fpscr_set_from_mem (NORMAL_MODE (FP_MODE
), unsaved
);
4790 && (i
!= FPSCR_REG
|| ! skip_fpscr
)
4791 && TEST_HARD_REG_BIT (*mask
, i
))
4794 if (TEST_HARD_REG_BIT (*mask
, PR_REG
))
4798 /* Calculate how much extra space is needed to save all callee-saved
4800 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
4803 shmedia_target_regs_stack_space (HARD_REG_SET
*live_regs_mask
)
4806 int stack_space
= 0;
4807 int interrupt_handler
= sh_cfun_interrupt_handler_p ();
4809 for (reg
= LAST_TARGET_REG
; reg
>= FIRST_TARGET_REG
; reg
--)
4810 if ((! call_used_regs
[reg
] || interrupt_handler
)
4811 && ! TEST_HARD_REG_BIT (*live_regs_mask
, reg
))
4812 /* Leave space to save this target register on the stack,
4813 in case target register allocation wants to use it. */
4814 stack_space
+= GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg
));
4818 /* Decide whether we should reserve space for callee-save target registers,
4819 in case target register allocation wants to use them. REGS_SAVED is
4820 the space, in bytes, that is already required for register saves.
4821 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
4824 shmedia_reserve_space_for_target_registers_p (int regs_saved
,
4825 HARD_REG_SET
*live_regs_mask
)
4829 return shmedia_target_regs_stack_space (live_regs_mask
) <= regs_saved
;
4832 /* Decide how much space to reserve for callee-save target registers
4833 in case target register allocation wants to use them.
4834 LIVE_REGS_MASK is the register mask calculated by calc_live_regs. */
4837 shmedia_target_regs_stack_adjust (HARD_REG_SET
*live_regs_mask
)
4839 if (shmedia_space_reserved_for_target_registers
)
4840 return shmedia_target_regs_stack_space (live_regs_mask
);
4845 /* Work out the registers which need to be saved, both as a mask and a
4846 count of saved words. Return the count.
4848 If doing a pragma interrupt function, then push all regs used by the
4849 function, and if we call another function (we can tell by looking at PR),
4850 make sure that all the regs it clobbers are safe too. */
4853 calc_live_regs (live_regs_mask
)
4854 HARD_REG_SET
*live_regs_mask
;
4858 int interrupt_handler
;
4859 int pr_live
, has_call
;
4861 interrupt_handler
= sh_cfun_interrupt_handler_p ();
4863 CLEAR_HARD_REG_SET (*live_regs_mask
);
4864 if (TARGET_SH4
&& TARGET_FMOVD
&& interrupt_handler
4865 && regs_ever_live
[FPSCR_REG
])
4866 target_flags
&= ~FPU_SINGLE_BIT
;
4867 /* If we can save a lot of saves by switching to double mode, do that. */
4868 else if (TARGET_SH4
&& TARGET_FMOVD
&& TARGET_FPU_SINGLE
)
4869 for (count
= 0, reg
= FIRST_FP_REG
; reg
<= LAST_FP_REG
; reg
+= 2)
4870 if (regs_ever_live
[reg
] && regs_ever_live
[reg
+1]
4871 && (! call_used_regs
[reg
] || (interrupt_handler
&& ! pragma_trapa
))
4874 target_flags
&= ~FPU_SINGLE_BIT
;
4877 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
4878 knows how to use it. That means the pseudo originally allocated for
4879 the initial value can become the PR_MEDIA_REG hard register, as seen for
4880 execute/20010122-1.c:test9. */
4882 /* ??? this function is called from initial_elimination_offset, hence we
4883 can't use the result of sh_media_register_for_return here. */
4884 pr_live
= sh_pr_n_sets ();
4887 rtx pr_initial
= has_hard_reg_initial_val (Pmode
, PR_REG
);
4888 pr_live
= (pr_initial
4889 ? (GET_CODE (pr_initial
) != REG
4890 || REGNO (pr_initial
) != (PR_REG
))
4891 : regs_ever_live
[PR_REG
]);
4892 /* For Shcompact, if not optimizing, we end up with a memory reference
4893 using the return address pointer for __builtin_return_address even
4894 though there is no actual need to put the PR register on the stack. */
4895 pr_live
|= regs_ever_live
[RETURN_ADDRESS_POINTER_REGNUM
];
4897 /* Force PR to be live if the prologue has to call the SHmedia
4898 argument decoder or register saver. */
4899 if (TARGET_SHCOMPACT
4900 && ((current_function_args_info
.call_cookie
4901 & ~ CALL_COOKIE_RET_TRAMP (1))
4902 || current_function_has_nonlocal_label
))
4904 has_call
= TARGET_SHMEDIA
? ! leaf_function_p () : pr_live
;
4905 for (count
= 0, reg
= FIRST_PSEUDO_REGISTER
- 1; reg
>= 0; reg
--)
4907 if (reg
== (TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
)
4909 : (interrupt_handler
&& ! pragma_trapa
)
4910 ? (/* Need to save all the regs ever live. */
4911 (regs_ever_live
[reg
]
4912 || (call_used_regs
[reg
]
4913 && (! fixed_regs
[reg
] || reg
== MACH_REG
|| reg
== MACL_REG
)
4915 || (has_call
&& REGISTER_NATURAL_MODE (reg
) == SImode
4916 && (GENERAL_REGISTER_P (reg
) || TARGET_REGISTER_P (reg
))))
4917 && reg
!= STACK_POINTER_REGNUM
&& reg
!= ARG_POINTER_REGNUM
4918 && reg
!= RETURN_ADDRESS_POINTER_REGNUM
4919 && reg
!= T_REG
&& reg
!= GBR_REG
4920 /* Push fpscr only on targets which have FPU */
4921 && (reg
!= FPSCR_REG
|| TARGET_FPU_ANY
))
4922 : (/* Only push those regs which are used and need to be saved. */
4925 && current_function_args_info
.call_cookie
4926 && reg
== (int) PIC_OFFSET_TABLE_REGNUM
)
4927 || (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
4928 || (current_function_calls_eh_return
4929 && (reg
== (int) EH_RETURN_DATA_REGNO (0)
4930 || reg
== (int) EH_RETURN_DATA_REGNO (1)
4931 || reg
== (int) EH_RETURN_DATA_REGNO (2)
4932 || reg
== (int) EH_RETURN_DATA_REGNO (3)))
4933 || ((reg
== MACL_REG
|| reg
== MACH_REG
)
4934 && regs_ever_live
[reg
]
4935 && sh_cfun_attr_renesas_p ())
4938 SET_HARD_REG_BIT (*live_regs_mask
, reg
);
4939 count
+= GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg
));
4941 if ((TARGET_SH4
|| TARGET_SH5
) && TARGET_FMOVD
4942 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg
)) == MODE_FLOAT
)
4944 if (FP_REGISTER_P (reg
))
4946 if (! TARGET_FPU_SINGLE
&& ! regs_ever_live
[reg
^ 1])
4948 SET_HARD_REG_BIT (*live_regs_mask
, (reg
^ 1));
4949 count
+= GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg
^ 1));
4952 else if (XD_REGISTER_P (reg
))
4954 /* Must switch to double mode to access these registers. */
4955 target_flags
&= ~FPU_SINGLE_BIT
;
4960 /* If we have a target register optimization pass after prologue / epilogue
4961 threading, we need to assume all target registers will be live even if
4963 if (flag_branch_target_load_optimize2
4964 && TARGET_SAVE_ALL_TARGET_REGS
4965 && shmedia_space_reserved_for_target_registers
)
4966 for (reg
= LAST_TARGET_REG
; reg
>= FIRST_TARGET_REG
; reg
--)
4967 if ((! call_used_regs
[reg
] || interrupt_handler
)
4968 && ! TEST_HARD_REG_BIT (*live_regs_mask
, reg
))
4970 SET_HARD_REG_BIT (*live_regs_mask
, reg
);
4971 count
+= GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg
));
4973 /* If this is an interrupt handler, we don't have any call-clobbered
4974 registers we can conveniently use for target register save/restore.
4975 Make sure we save at least one general purpose register when we need
4976 to save target registers. */
4977 if (interrupt_handler
4978 && hard_regs_intersect_p (live_regs_mask
,
4979 ®_class_contents
[TARGET_REGS
])
4980 && ! hard_regs_intersect_p (live_regs_mask
,
4981 ®_class_contents
[GENERAL_REGS
]))
4983 SET_HARD_REG_BIT (*live_regs_mask
, R0_REG
);
4984 count
+= GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG
));
4990 /* Code to generate prologue and epilogue sequences */
4992 /* PUSHED is the number of bytes that are being pushed on the
4993 stack for register saves. Return the frame size, padded
4994 appropriately so that the stack stays properly aligned. */
4995 static HOST_WIDE_INT
4996 rounded_frame_size (pushed
)
4999 HOST_WIDE_INT size
= get_frame_size ();
5000 HOST_WIDE_INT align
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
5002 return ((size
+ pushed
+ align
- 1) & -align
) - pushed
;
5005 /* Choose a call-clobbered target-branch register that remains
5006 unchanged along the whole function. We set it up as the return
5007 value in the prologue. */
5009 sh_media_register_for_return ()
5014 if (! current_function_is_leaf
)
5016 if (lookup_attribute ("interrupt_handler",
5017 DECL_ATTRIBUTES (current_function_decl
)))
5020 tr0_used
= flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
];
5022 for (regno
= FIRST_TARGET_REG
+ tr0_used
; regno
<= LAST_TARGET_REG
; regno
++)
5023 if (call_used_regs
[regno
] && ! regs_ever_live
[regno
])
5029 /* The maximum registers we need to save are:
5030 - 62 general purpose registers (r15 is stack pointer, r63 is zero)
5031 - 32 floating point registers (for each pair, we save none,
5032 one single precision value, or a double precision value).
5033 - 8 target registers
5034 - add 1 entry for a delimiter. */
5035 #define MAX_SAVED_REGS (62+32+8)
5037 typedef struct save_entry_s
5046 /* There will be a delimiter entry with VOIDmode both at the start and the
5047 end of a filled in schedule. The end delimiter has the offset of the
5048 save with the smallest (i.e. most negative) offset. */
5049 typedef struct save_schedule_s
5051 save_entry entries
[MAX_SAVED_REGS
+ 2];
5052 int temps
[MAX_TEMPS
+1];
5055 /* Fill in SCHEDULE according to LIVE_REGS_MASK. If RESTORE is nonzero,
5056 use reverse order. Returns the last entry written to (not counting
5057 the delimiter). OFFSET_BASE is a number to be added to all offset
5061 sh5_schedule_saves (HARD_REG_SET
*live_regs_mask
, save_schedule
*schedule
,
5065 save_entry
*entry
= schedule
->entries
;
5069 if (! current_function_interrupt
)
5070 for (i
= FIRST_GENERAL_REG
; tmpx
< MAX_TEMPS
&& i
<= LAST_GENERAL_REG
; i
++)
5071 if (call_used_regs
[i
] && ! fixed_regs
[i
] && i
!= PR_MEDIA_REG
5072 && ! FUNCTION_ARG_REGNO_P (i
)
5073 && i
!= FIRST_RET_REG
5074 && ! (current_function_needs_context
&& i
== STATIC_CHAIN_REGNUM
)
5075 && ! (current_function_calls_eh_return
5076 && (i
== EH_RETURN_STACKADJ_REGNO
5077 || ((unsigned)i
<= EH_RETURN_DATA_REGNO (0)
5078 && (unsigned)i
>= EH_RETURN_DATA_REGNO (3)))))
5079 schedule
->temps
[tmpx
++] = i
;
5081 entry
->mode
= VOIDmode
;
5082 entry
->offset
= offset_base
;
5084 /* We loop twice: first, we save 8-byte aligned registers in the
5085 higher addresses, that are known to be aligned. Then, we
5086 proceed to saving 32-bit registers that don't need 8-byte
5088 If this is an interrupt function, all registers that need saving
5089 need to be saved in full. moreover, we need to postpone saving
5090 target registers till we have saved some general purpose registers
5091 we can then use as scratch registers. */
5092 offset
= offset_base
;
5093 for (align
= 1; align
>= 0; align
--)
5095 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
5096 if (TEST_HARD_REG_BIT (*live_regs_mask
, i
))
5098 enum machine_mode mode
= REGISTER_NATURAL_MODE (i
);
5101 if (current_function_interrupt
)
5103 if (TARGET_REGISTER_P (i
))
5105 if (GENERAL_REGISTER_P (i
))
5108 if (mode
== SFmode
&& (i
% 2) == 1
5109 && ! TARGET_FPU_SINGLE
&& FP_REGISTER_P (i
)
5110 && (TEST_HARD_REG_BIT (*live_regs_mask
, (i
^ 1))))
5117 /* If we're doing the aligned pass and this is not aligned,
5118 or we're doing the unaligned pass and this is aligned,
5120 if ((GET_MODE_SIZE (mode
) % (STACK_BOUNDARY
/ BITS_PER_UNIT
) == 0)
5124 if (current_function_interrupt
5125 && GENERAL_REGISTER_P (i
)
5126 && tmpx
< MAX_TEMPS
)
5127 schedule
->temps
[tmpx
++] = i
;
5129 offset
-= GET_MODE_SIZE (mode
);
5132 entry
->offset
= offset
;
5135 if (align
&& current_function_interrupt
)
5136 for (i
= LAST_TARGET_REG
; i
>= FIRST_TARGET_REG
; i
--)
5137 if (TEST_HARD_REG_BIT (*live_regs_mask
, i
))
5139 offset
-= GET_MODE_SIZE (DImode
);
5141 entry
->mode
= DImode
;
5142 entry
->offset
= offset
;
5147 entry
->mode
= VOIDmode
;
5148 entry
->offset
= offset
;
5149 schedule
->temps
[tmpx
] = -1;
5154 sh_expand_prologue ()
5156 HARD_REG_SET live_regs_mask
;
5159 int save_flags
= target_flags
;
5161 current_function_interrupt
= sh_cfun_interrupt_handler_p ();
5163 /* We have pretend args if we had an object sent partially in registers
5164 and partially on the stack, e.g. a large structure. */
5165 output_stack_adjust (-current_function_pretend_args_size
5166 - current_function_args_info
.stack_regs
* 8,
5167 stack_pointer_rtx
, 0, NULL
);
5171 if (TARGET_SHCOMPACT
&& flag_pic
&& current_function_args_info
.call_cookie
)
5172 /* We're going to use the PIC register to load the address of the
5173 incoming-argument decoder and/or of the return trampoline from
5174 the GOT, so make sure the PIC register is preserved and
5176 regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
] = 1;
5178 if (TARGET_SHCOMPACT
5179 && (current_function_args_info
.call_cookie
& ~ CALL_COOKIE_RET_TRAMP(1)))
5183 /* First, make all registers with incoming arguments that will
5184 be pushed onto the stack live, so that register renaming
5185 doesn't overwrite them. */
5186 for (reg
= 0; reg
< NPARM_REGS (SImode
); reg
++)
5187 if (CALL_COOKIE_STACKSEQ_GET (current_function_args_info
.call_cookie
)
5188 >= NPARM_REGS (SImode
) - reg
)
5189 for (; reg
< NPARM_REGS (SImode
); reg
++)
5190 emit_insn (gen_shcompact_preserve_incoming_args
5191 (gen_rtx_REG (SImode
, FIRST_PARM_REG
+ reg
)));
5192 else if (CALL_COOKIE_INT_REG_GET
5193 (current_function_args_info
.call_cookie
, reg
) == 1)
5194 emit_insn (gen_shcompact_preserve_incoming_args
5195 (gen_rtx_REG (SImode
, FIRST_PARM_REG
+ reg
)));
5197 emit_move_insn (gen_rtx_REG (Pmode
, MACL_REG
),
5199 emit_move_insn (gen_rtx_REG (SImode
, R0_REG
),
5200 GEN_INT (current_function_args_info
.call_cookie
));
5201 emit_move_insn (gen_rtx_REG (SImode
, MACH_REG
),
5202 gen_rtx_REG (SImode
, R0_REG
));
5204 else if (TARGET_SHMEDIA
)
5206 int tr
= sh_media_register_for_return ();
5210 rtx insn
= emit_move_insn (gen_rtx_REG (DImode
, tr
),
5211 gen_rtx_REG (DImode
, PR_MEDIA_REG
));
5213 /* ??? We should suppress saving pr when we don't need it, but this
5214 is tricky because of builtin_return_address. */
5216 /* If this function only exits with sibcalls, this copy
5217 will be flagged as dead. */
5218 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
,
5224 /* Emit the code for SETUP_VARARGS. */
5225 if (current_function_stdarg
)
5227 /* This is not used by the SH2E calling convention */
5228 if (TARGET_SH1
&& ! TARGET_SH2E
&& ! TARGET_SH5
5229 && ! (TARGET_HITACHI
|| sh_cfun_attr_renesas_p ()))
5231 /* Push arg regs as if they'd been provided by caller in stack. */
5232 for (i
= 0; i
< NPARM_REGS(SImode
); i
++)
5234 int rn
= NPARM_REGS(SImode
) + FIRST_PARM_REG
- i
- 1;
5237 if (i
>= (NPARM_REGS(SImode
)
5238 - current_function_args_info
.arg_count
[(int) SH_ARG_INT
]
5242 RTX_FRAME_RELATED_P (insn
) = 0;
5248 /* If we're supposed to switch stacks at function entry, do so now. */
5250 emit_insn (gen_sp_switch_1 ());
5252 d
= calc_live_regs (&live_regs_mask
);
5253 /* ??? Maybe we could save some switching if we can move a mode switch
5254 that already happens to be at the function start into the prologue. */
5255 if (target_flags
!= save_flags
&& ! current_function_interrupt
)
5256 emit_insn (gen_toggle_sz ());
5260 int offset_base
, offset
;
5262 int offset_in_r0
= -1;
5264 int tregs_space
= shmedia_target_regs_stack_adjust (&live_regs_mask
);
5265 int total_size
, save_size
;
5266 save_schedule schedule
;
5270 if (call_used_regs
[R0_REG
] && ! fixed_regs
[R0_REG
]
5271 && ! current_function_interrupt
)
5272 r0
= gen_rtx_REG (Pmode
, R0_REG
);
5274 /* D is the actual number of bytes that we need for saving registers,
5275 however, in initial_elimination_offset we have committed to using
5276 an additional TREGS_SPACE amount of bytes - in order to keep both
5277 addresses to arguments supplied by the caller and local variables
5278 valid, we must keep this gap. Place it between the incoming
5279 arguments and the actually saved registers in a bid to optimize
5280 locality of reference. */
5281 total_size
= d
+ tregs_space
;
5282 total_size
+= rounded_frame_size (total_size
);
5283 save_size
= total_size
- rounded_frame_size (d
);
5284 if (save_size
% (STACK_BOUNDARY
/ BITS_PER_UNIT
))
5285 d_rounding
= ((STACK_BOUNDARY
/ BITS_PER_UNIT
)
5286 - save_size
% (STACK_BOUNDARY
/ BITS_PER_UNIT
));
5288 /* If adjusting the stack in a single step costs nothing extra, do so.
5289 I.e. either if a single addi is enough, or we need a movi anyway,
5290 and we don't exceed the maximum offset range (the test for the
5291 latter is conservative for simplicity). */
5293 && (CONST_OK_FOR_I10 (-total_size
)
5294 || (! CONST_OK_FOR_I10 (-(save_size
+ d_rounding
))
5295 && total_size
<= 2044)))
5296 d_rounding
= total_size
- save_size
;
5298 offset_base
= d
+ d_rounding
;
5300 output_stack_adjust (-(save_size
+ d_rounding
), stack_pointer_rtx
,
5303 sh5_schedule_saves (&live_regs_mask
, &schedule
, offset_base
);
5304 tmp_pnt
= schedule
.temps
;
5305 for (entry
= &schedule
.entries
[1]; entry
->mode
!= VOIDmode
; entry
++)
5307 enum machine_mode mode
= entry
->mode
;
5308 int reg
= entry
->reg
;
5309 rtx reg_rtx
, mem_rtx
, pre_dec
= NULL_RTX
;
5311 offset
= entry
->offset
;
5313 reg_rtx
= gen_rtx_REG (mode
, reg
);
5315 mem_rtx
= gen_rtx_MEM (mode
,
5316 gen_rtx_PLUS (Pmode
,
5320 GO_IF_LEGITIMATE_ADDRESS (mode
, XEXP (mem_rtx
, 0), try_pre_dec
);
5328 if (HAVE_PRE_DECREMENT
5329 && (offset_in_r0
- offset
== GET_MODE_SIZE (mode
)
5330 || mem_rtx
== NULL_RTX
5331 || reg
== PR_REG
|| SPECIAL_REGISTER_P (reg
)))
5333 pre_dec
= gen_rtx_MEM (mode
,
5334 gen_rtx_PRE_DEC (Pmode
, r0
));
5336 GO_IF_LEGITIMATE_ADDRESS (mode
, XEXP (pre_dec
, 0),
5345 offset
+= GET_MODE_SIZE (mode
);
5349 if (mem_rtx
!= NULL_RTX
)
5352 if (offset_in_r0
== -1)
5354 emit_move_insn (r0
, GEN_INT (offset
));
5355 offset_in_r0
= offset
;
5357 else if (offset
!= offset_in_r0
)
5362 GEN_INT (offset
- offset_in_r0
)));
5363 offset_in_r0
+= offset
- offset_in_r0
;
5366 if (pre_dec
!= NULL_RTX
)
5372 (Pmode
, r0
, stack_pointer_rtx
));
5376 offset
-= GET_MODE_SIZE (mode
);
5377 offset_in_r0
-= GET_MODE_SIZE (mode
);
5382 mem_rtx
= gen_rtx_MEM (mode
, r0
);
5384 mem_rtx
= gen_rtx_MEM (mode
,
5385 gen_rtx_PLUS (Pmode
,
5389 /* We must not use an r0-based address for target-branch
5390 registers or for special registers without pre-dec
5391 memory addresses, since we store their values in r0
5393 if (TARGET_REGISTER_P (reg
)
5394 || ((reg
== PR_REG
|| SPECIAL_REGISTER_P (reg
))
5395 && mem_rtx
!= pre_dec
))
5399 if (TARGET_REGISTER_P (reg
)
5400 || ((reg
== PR_REG
|| SPECIAL_REGISTER_P (reg
))
5401 && mem_rtx
!= pre_dec
))
5403 rtx tmp_reg
= gen_rtx_REG (GET_MODE (reg_rtx
), *tmp_pnt
);
5405 emit_move_insn (tmp_reg
, reg_rtx
);
5407 if (REGNO (tmp_reg
) == R0_REG
)
5411 if (refers_to_regno_p (R0_REG
, R0_REG
+1, mem_rtx
, (rtx
*) 0))
5415 if (*++tmp_pnt
<= 0)
5416 tmp_pnt
= schedule
.temps
;
5423 /* Mark as interesting for dwarf cfi generator */
5424 insn
= emit_move_insn (mem_rtx
, reg_rtx
);
5425 RTX_FRAME_RELATED_P (insn
) = 1;
5427 if (TARGET_SHCOMPACT
&& (offset_in_r0
!= -1))
5429 rtx reg_rtx
= gen_rtx_REG (mode
, reg
);
5431 rtx mem_rtx
= gen_rtx_MEM (mode
,
5432 gen_rtx_PLUS (Pmode
,
5436 set
= gen_rtx_SET (VOIDmode
, mem_rtx
, reg_rtx
);
5437 note_rtx
= gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, set
,
5439 REG_NOTES (insn
) = note_rtx
;
5444 if (entry
->offset
!= d_rounding
)
5448 push_regs (&live_regs_mask
, current_function_interrupt
);
5450 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
5452 rtx insn
= get_last_insn ();
5453 rtx last
= emit_insn (gen_GOTaddr2picreg ());
5455 /* Mark these insns as possibly dead. Sometimes, flow2 may
5456 delete all uses of the PIC register. In this case, let it
5457 delete the initialization too. */
5460 insn
= NEXT_INSN (insn
);
5462 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
,
5466 while (insn
!= last
);
5469 if (SHMEDIA_REGS_STACK_ADJUST ())
5471 emit_move_insn (gen_rtx_REG (Pmode
, R0_REG
),
5472 function_symbol (TARGET_FPU_ANY
5473 ? "__GCC_push_shmedia_regs"
5474 : "__GCC_push_shmedia_regs_nofpu"));
5475 /* This must NOT go through the PLT, otherwise mach and macl
5476 may be clobbered. */
5477 emit_insn (gen_shmedia_save_restore_regs_compact
5478 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
5481 if (target_flags
!= save_flags
&& ! current_function_interrupt
)
5483 rtx insn
= emit_insn (gen_toggle_sz ());
5485 /* If we're lucky, a mode switch in the function body will
5486 overwrite fpscr, turning this insn dead. Tell flow this
5487 insn is ok to delete. */
5488 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
,
5493 target_flags
= save_flags
;
5495 output_stack_adjust (-rounded_frame_size (d
) + d_rounding
,
5496 stack_pointer_rtx
, 0, NULL
);
5498 if (frame_pointer_needed
)
5499 frame_insn (GEN_MOV (frame_pointer_rtx
, stack_pointer_rtx
));
5501 if (TARGET_SHCOMPACT
5502 && (current_function_args_info
.call_cookie
& ~ CALL_COOKIE_RET_TRAMP(1)))
5504 /* This must NOT go through the PLT, otherwise mach and macl
5505 may be clobbered. */
5506 emit_move_insn (gen_rtx_REG (Pmode
, R0_REG
),
5507 function_symbol ("__GCC_shcompact_incoming_args"));
5508 emit_insn (gen_shcompact_incoming_args ());
5513 sh_expand_epilogue ()
5515 HARD_REG_SET live_regs_mask
;
5519 int save_flags
= target_flags
;
5520 int frame_size
, save_size
;
5521 int fpscr_deferred
= 0;
5523 d
= calc_live_regs (&live_regs_mask
);
5526 frame_size
= rounded_frame_size (d
);
5530 int tregs_space
= shmedia_target_regs_stack_adjust (&live_regs_mask
);
5532 if (d
% (STACK_BOUNDARY
/ BITS_PER_UNIT
))
5533 d_rounding
= ((STACK_BOUNDARY
/ BITS_PER_UNIT
)
5534 - d
% (STACK_BOUNDARY
/ BITS_PER_UNIT
));
5536 total_size
= d
+ tregs_space
;
5537 total_size
+= rounded_frame_size (total_size
);
5538 save_size
= total_size
- frame_size
;
5540 /* If adjusting the stack in a single step costs nothing extra, do so.
5541 I.e. either if a single addi is enough, or we need a movi anyway,
5542 and we don't exceed the maximum offset range (the test for the
5543 latter is conservative for simplicity). */
5545 && ! frame_pointer_needed
5546 && (CONST_OK_FOR_I10 (total_size
)
5547 || (! CONST_OK_FOR_I10 (save_size
+ d_rounding
)
5548 && total_size
<= 2044)))
5549 d_rounding
= frame_size
;
5551 frame_size
-= d_rounding
;
5554 if (frame_pointer_needed
)
5556 output_stack_adjust (frame_size
, frame_pointer_rtx
, 1, &live_regs_mask
);
5558 /* We must avoid moving the stack pointer adjustment past code
5559 which reads from the local frame, else an interrupt could
5560 occur after the SP adjustment and clobber data in the local
5562 emit_insn (gen_blockage ());
5563 emit_insn (GEN_MOV (stack_pointer_rtx
, frame_pointer_rtx
));
5565 else if (frame_size
)
5567 /* We must avoid moving the stack pointer adjustment past code
5568 which reads from the local frame, else an interrupt could
5569 occur after the SP adjustment and clobber data in the local
5571 emit_insn (gen_blockage ());
5572 output_stack_adjust (frame_size
, stack_pointer_rtx
, 1, &live_regs_mask
);
5575 if (SHMEDIA_REGS_STACK_ADJUST ())
5577 emit_move_insn (gen_rtx_REG (Pmode
, R0_REG
),
5578 function_symbol (TARGET_FPU_ANY
5579 ? "__GCC_pop_shmedia_regs"
5580 : "__GCC_pop_shmedia_regs_nofpu"));
5581 /* This must NOT go through the PLT, otherwise mach and macl
5582 may be clobbered. */
5583 emit_insn (gen_shmedia_save_restore_regs_compact
5584 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
5587 /* Pop all the registers. */
5589 if (target_flags
!= save_flags
&& ! current_function_interrupt
)
5590 emit_insn (gen_toggle_sz ());
5593 int offset_base
, offset
;
5594 int offset_in_r0
= -1;
5596 rtx r0
= gen_rtx_REG (Pmode
, R0_REG
);
5597 save_schedule schedule
;
5601 entry
= sh5_schedule_saves (&live_regs_mask
, &schedule
, d_rounding
);
5602 offset_base
= -entry
[1].offset
+ d_rounding
;
5603 tmp_pnt
= schedule
.temps
;
5604 for (; entry
->mode
!= VOIDmode
; entry
--)
5606 enum machine_mode mode
= entry
->mode
;
5607 int reg
= entry
->reg
;
5608 rtx reg_rtx
, mem_rtx
, post_inc
= NULL_RTX
, insn
;
5610 offset
= offset_base
+ entry
->offset
;
5611 reg_rtx
= gen_rtx_REG (mode
, reg
);
5613 mem_rtx
= gen_rtx_MEM (mode
,
5614 gen_rtx_PLUS (Pmode
,
5618 GO_IF_LEGITIMATE_ADDRESS (mode
, XEXP (mem_rtx
, 0), try_post_inc
);
5624 if (HAVE_POST_INCREMENT
5625 && (offset
== offset_in_r0
5626 || (offset
+ GET_MODE_SIZE (mode
) != d
+ d_rounding
5627 && mem_rtx
== NULL_RTX
)
5628 || reg
== PR_REG
|| SPECIAL_REGISTER_P (reg
)))
5630 post_inc
= gen_rtx_MEM (mode
,
5631 gen_rtx_POST_INC (Pmode
, r0
));
5633 GO_IF_LEGITIMATE_ADDRESS (mode
, XEXP (post_inc
, 0),
5636 post_inc
= NULL_RTX
;
5645 if (mem_rtx
!= NULL_RTX
)
5648 if (offset_in_r0
== -1)
5650 emit_move_insn (r0
, GEN_INT (offset
));
5651 offset_in_r0
= offset
;
5653 else if (offset
!= offset_in_r0
)
5658 GEN_INT (offset
- offset_in_r0
)));
5659 offset_in_r0
+= offset
- offset_in_r0
;
5662 if (post_inc
!= NULL_RTX
)
5668 (Pmode
, r0
, stack_pointer_rtx
));
5674 offset_in_r0
+= GET_MODE_SIZE (mode
);
5677 mem_rtx
= gen_rtx_MEM (mode
, r0
);
5679 mem_rtx
= gen_rtx_MEM (mode
,
5680 gen_rtx_PLUS (Pmode
,
5684 if ((reg
== PR_REG
|| SPECIAL_REGISTER_P (reg
))
5685 && mem_rtx
!= post_inc
)
5689 if ((reg
== PR_REG
|| SPECIAL_REGISTER_P (reg
))
5690 && mem_rtx
!= post_inc
)
5692 insn
= emit_move_insn (r0
, mem_rtx
);
5695 else if (TARGET_REGISTER_P (reg
))
5697 rtx tmp_reg
= gen_rtx_REG (mode
, *tmp_pnt
);
5699 /* Give the scheduler a bit of freedom by using up to
5700 MAX_TEMPS registers in a round-robin fashion. */
5701 insn
= emit_move_insn (tmp_reg
, mem_rtx
);
5704 tmp_pnt
= schedule
.temps
;
5707 insn
= emit_move_insn (reg_rtx
, mem_rtx
);
5708 if (reg
== PR_MEDIA_REG
&& sh_media_register_for_return () >= 0)
5709 /* This is dead, unless we return with a sibcall. */
5710 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
,
5715 if (entry
->offset
+ offset_base
!= d
+ d_rounding
)
5718 else /* ! TARGET_SH5 */
5721 if (TEST_HARD_REG_BIT (live_regs_mask
, PR_REG
))
5723 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
5725 int j
= (FIRST_PSEUDO_REGISTER
- 1) - i
;
5727 if (j
== FPSCR_REG
&& current_function_interrupt
&& TARGET_FMOVD
5728 && hard_regs_intersect_p (&live_regs_mask
,
5729 ®_class_contents
[DF_REGS
]))
5731 else if (j
!= PR_REG
&& TEST_HARD_REG_BIT (live_regs_mask
, j
))
5733 if (j
== FIRST_FP_REG
&& fpscr_deferred
)
5738 if (target_flags
!= save_flags
&& ! current_function_interrupt
)
5739 emit_insn (gen_toggle_sz ());
5740 target_flags
= save_flags
;
5742 output_stack_adjust (extra_push
+ current_function_pretend_args_size
5743 + save_size
+ d_rounding
5744 + current_function_args_info
.stack_regs
* 8,
5745 stack_pointer_rtx
, 1, NULL
);
5747 if (current_function_calls_eh_return
)
5748 emit_insn (GEN_ADD3 (stack_pointer_rtx
, stack_pointer_rtx
,
5749 EH_RETURN_STACKADJ_RTX
));
5751 /* Switch back to the normal stack if necessary. */
5753 emit_insn (gen_sp_switch_2 ());
5755 /* Tell flow the insn that pops PR isn't dead. */
5756 /* PR_REG will never be live in SHmedia mode, and we don't need to
5757 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
5758 by the return pattern. */
5759 if (TEST_HARD_REG_BIT (live_regs_mask
, PR_REG
))
5760 emit_insn (gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, PR_REG
)));
5763 static int sh_need_epilogue_known
= 0;
5768 if (! sh_need_epilogue_known
)
5773 sh_expand_epilogue ();
5774 epilogue
= get_insns ();
5776 sh_need_epilogue_known
= (epilogue
== NULL
? -1 : 1);
5778 return sh_need_epilogue_known
> 0;
5781 /* Emit code to change the current function's return address to RA.
5782 TEMP is available as a scratch register, if needed. */
5785 sh_set_return_address (ra
, tmp
)
5788 HARD_REG_SET live_regs_mask
;
5790 int pr_reg
= TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
;
5793 d
= calc_live_regs (&live_regs_mask
);
5795 /* If pr_reg isn't life, we can set it (or the register given in
5796 sh_media_register_for_return) directly. */
5797 if (! TEST_HARD_REG_BIT (live_regs_mask
, pr_reg
))
5803 int rr_regno
= sh_media_register_for_return ();
5808 rr
= gen_rtx_REG (DImode
, rr_regno
);
5811 rr
= gen_rtx_REG (SImode
, pr_reg
);
5813 emit_insn (GEN_MOV (rr
, ra
));
5814 /* Tell flow the register for return isn't dead. */
5815 emit_insn (gen_rtx_USE (VOIDmode
, rr
));
5822 save_schedule schedule
;
5825 entry
= sh5_schedule_saves (&live_regs_mask
, &schedule
, 0);
5826 offset
= entry
[1].offset
;
5827 for (; entry
->mode
!= VOIDmode
; entry
--)
5828 if (entry
->reg
== pr_reg
)
5831 /* We can't find pr register. */
5835 offset
= entry
->offset
- offset
;
5836 pr_offset
= (rounded_frame_size (d
) + offset
5837 + SHMEDIA_REGS_STACK_ADJUST ());
5840 pr_offset
= rounded_frame_size (d
);
5842 emit_insn (GEN_MOV (tmp
, GEN_INT (pr_offset
)));
5843 emit_insn (GEN_ADD3 (tmp
, tmp
, frame_pointer_rtx
));
5845 tmp
= gen_rtx_MEM (Pmode
, tmp
);
5846 emit_insn (GEN_MOV (tmp
, ra
));
5849 /* Clear variables at function end. */
5852 sh_output_function_epilogue (file
, size
)
5853 FILE *file ATTRIBUTE_UNUSED
;
5854 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
5856 trap_exit
= pragma_interrupt
= pragma_trapa
= pragma_nosave_low_regs
= 0;
5857 sh_need_epilogue_known
= 0;
5858 sp_switch
= NULL_RTX
;
5862 sh_builtin_saveregs ()
5864 /* First unnamed integer register. */
5865 int first_intreg
= current_function_args_info
.arg_count
[(int) SH_ARG_INT
];
5866 /* Number of integer registers we need to save. */
5867 int n_intregs
= MAX (0, NPARM_REGS (SImode
) - first_intreg
);
5868 /* First unnamed SFmode float reg */
5869 int first_floatreg
= current_function_args_info
.arg_count
[(int) SH_ARG_FLOAT
];
5870 /* Number of SFmode float regs to save. */
5871 int n_floatregs
= MAX (0, NPARM_REGS (SFmode
) - first_floatreg
);
5874 HOST_WIDE_INT alias_set
;
5880 int pushregs
= n_intregs
;
5882 while (pushregs
< NPARM_REGS (SImode
) - 1
5883 && (CALL_COOKIE_INT_REG_GET
5884 (current_function_args_info
.call_cookie
,
5885 NPARM_REGS (SImode
) - pushregs
)
5888 current_function_args_info
.call_cookie
5889 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode
)
5894 if (pushregs
== NPARM_REGS (SImode
))
5895 current_function_args_info
.call_cookie
5896 |= (CALL_COOKIE_INT_REG (0, 1)
5897 | CALL_COOKIE_STACKSEQ (pushregs
- 1));
5899 current_function_args_info
.call_cookie
5900 |= CALL_COOKIE_STACKSEQ (pushregs
);
5902 current_function_pretend_args_size
+= 8 * n_intregs
;
5904 if (TARGET_SHCOMPACT
)
5908 if (! TARGET_SH2E
&& ! TARGET_SH4
&& ! TARGET_SH5
)
5910 error ("__builtin_saveregs not supported by this subtarget");
5917 /* Allocate block of memory for the regs. */
5918 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
5919 Or can assign_stack_local accept a 0 SIZE argument? */
5920 bufsize
= (n_intregs
* UNITS_PER_WORD
) + (n_floatregs
* UNITS_PER_WORD
);
5923 regbuf
= gen_rtx_MEM (BLKmode
,
5924 gen_rtx_REG (Pmode
, ARG_POINTER_REGNUM
));
5925 else if (n_floatregs
& 1)
5929 regbuf
= assign_stack_local (BLKmode
, bufsize
+ UNITS_PER_WORD
, 0);
5930 addr
= copy_to_mode_reg (Pmode
, XEXP (regbuf
, 0));
5931 emit_insn (gen_iorsi3 (addr
, addr
, GEN_INT (UNITS_PER_WORD
)));
5932 regbuf
= change_address (regbuf
, BLKmode
, addr
);
5935 regbuf
= assign_stack_local (BLKmode
, bufsize
, 0);
5936 alias_set
= get_varargs_alias_set ();
5937 set_mem_alias_set (regbuf
, alias_set
);
5940 This is optimized to only save the regs that are necessary. Explicitly
5941 named args need not be saved. */
5943 move_block_from_reg (BASE_ARG_REG (SImode
) + first_intreg
,
5944 adjust_address (regbuf
, BLKmode
,
5945 n_floatregs
* UNITS_PER_WORD
),
5949 /* Return the address of the regbuf. */
5950 return XEXP (regbuf
, 0);
5953 This is optimized to only save the regs that are necessary. Explicitly
5954 named args need not be saved.
5955 We explicitly build a pointer to the buffer because it halves the insn
5956 count when not optimizing (otherwise the pointer is built for each reg
5958 We emit the moves in reverse order so that we can use predecrement. */
5960 fpregs
= gen_reg_rtx (Pmode
);
5961 emit_move_insn (fpregs
, XEXP (regbuf
, 0));
5962 emit_insn (gen_addsi3 (fpregs
, fpregs
,
5963 GEN_INT (n_floatregs
* UNITS_PER_WORD
)));
5967 for (regno
= NPARM_REGS (DFmode
) - 2; regno
>= first_floatreg
; regno
-= 2)
5969 emit_insn (gen_addsi3 (fpregs
, fpregs
,
5970 GEN_INT (-2 * UNITS_PER_WORD
)));
5971 mem
= gen_rtx_MEM (DFmode
, fpregs
);
5972 set_mem_alias_set (mem
, alias_set
);
5973 emit_move_insn (mem
,
5974 gen_rtx (REG
, DFmode
, BASE_ARG_REG (DFmode
) + regno
));
5976 regno
= first_floatreg
;
5979 emit_insn (gen_addsi3 (fpregs
, fpregs
, GEN_INT (- UNITS_PER_WORD
)));
5980 mem
= gen_rtx_MEM (SFmode
, fpregs
);
5981 set_mem_alias_set (mem
, alias_set
);
5982 emit_move_insn (mem
,
5983 gen_rtx (REG
, SFmode
, BASE_ARG_REG (SFmode
) + regno
5984 - (TARGET_LITTLE_ENDIAN
!= 0)));
5988 for (regno
= NPARM_REGS (SFmode
) - 1; regno
>= first_floatreg
; regno
--)
5992 emit_insn (gen_addsi3 (fpregs
, fpregs
, GEN_INT (- UNITS_PER_WORD
)));
5993 mem
= gen_rtx_MEM (SFmode
, fpregs
);
5994 set_mem_alias_set (mem
, alias_set
);
5995 emit_move_insn (mem
,
5996 gen_rtx_REG (SFmode
, BASE_ARG_REG (SFmode
) + regno
));
5999 /* Return the address of the regbuf. */
6000 return XEXP (regbuf
, 0);
6003 /* Define the `__builtin_va_list' type for the ABI. */
6008 tree f_next_o
, f_next_o_limit
, f_next_fp
, f_next_fp_limit
, f_next_stack
;
6011 if (TARGET_SH5
|| (! TARGET_SH2E
&& ! TARGET_SH4
)
6012 || TARGET_HITACHI
|| sh_cfun_attr_renesas_p ())
6013 return ptr_type_node
;
6015 record
= make_node (RECORD_TYPE
);
6017 f_next_o
= build_decl (FIELD_DECL
, get_identifier ("__va_next_o"),
6019 f_next_o_limit
= build_decl (FIELD_DECL
,
6020 get_identifier ("__va_next_o_limit"),
6022 f_next_fp
= build_decl (FIELD_DECL
, get_identifier ("__va_next_fp"),
6024 f_next_fp_limit
= build_decl (FIELD_DECL
,
6025 get_identifier ("__va_next_fp_limit"),
6027 f_next_stack
= build_decl (FIELD_DECL
, get_identifier ("__va_next_stack"),
6030 DECL_FIELD_CONTEXT (f_next_o
) = record
;
6031 DECL_FIELD_CONTEXT (f_next_o_limit
) = record
;
6032 DECL_FIELD_CONTEXT (f_next_fp
) = record
;
6033 DECL_FIELD_CONTEXT (f_next_fp_limit
) = record
;
6034 DECL_FIELD_CONTEXT (f_next_stack
) = record
;
6036 TYPE_FIELDS (record
) = f_next_o
;
6037 TREE_CHAIN (f_next_o
) = f_next_o_limit
;
6038 TREE_CHAIN (f_next_o_limit
) = f_next_fp
;
6039 TREE_CHAIN (f_next_fp
) = f_next_fp_limit
;
6040 TREE_CHAIN (f_next_fp_limit
) = f_next_stack
;
6042 layout_type (record
);
6047 /* Implement `va_start' for varargs and stdarg. */
6050 sh_va_start (valist
, nextarg
)
6054 tree f_next_o
, f_next_o_limit
, f_next_fp
, f_next_fp_limit
, f_next_stack
;
6055 tree next_o
, next_o_limit
, next_fp
, next_fp_limit
, next_stack
;
6061 expand_builtin_saveregs ();
6062 std_expand_builtin_va_start (valist
, nextarg
);
6066 if ((! TARGET_SH2E
&& ! TARGET_SH4
)
6067 || TARGET_HITACHI
|| sh_cfun_attr_renesas_p ())
6069 std_expand_builtin_va_start (valist
, nextarg
);
6073 f_next_o
= TYPE_FIELDS (va_list_type_node
);
6074 f_next_o_limit
= TREE_CHAIN (f_next_o
);
6075 f_next_fp
= TREE_CHAIN (f_next_o_limit
);
6076 f_next_fp_limit
= TREE_CHAIN (f_next_fp
);
6077 f_next_stack
= TREE_CHAIN (f_next_fp_limit
);
6079 next_o
= build (COMPONENT_REF
, TREE_TYPE (f_next_o
), valist
, f_next_o
);
6080 next_o_limit
= build (COMPONENT_REF
, TREE_TYPE (f_next_o_limit
),
6081 valist
, f_next_o_limit
);
6082 next_fp
= build (COMPONENT_REF
, TREE_TYPE (f_next_fp
), valist
, f_next_fp
);
6083 next_fp_limit
= build (COMPONENT_REF
, TREE_TYPE (f_next_fp_limit
),
6084 valist
, f_next_fp_limit
);
6085 next_stack
= build (COMPONENT_REF
, TREE_TYPE (f_next_stack
),
6086 valist
, f_next_stack
);
6088 /* Call __builtin_saveregs. */
6089 u
= make_tree (ptr_type_node
, expand_builtin_saveregs ());
6090 t
= build (MODIFY_EXPR
, ptr_type_node
, next_fp
, u
);
6091 TREE_SIDE_EFFECTS (t
) = 1;
6092 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6094 nfp
= current_function_args_info
.arg_count
[SH_ARG_FLOAT
];
6099 u
= fold (build (PLUS_EXPR
, ptr_type_node
, u
,
6100 build_int_2 (UNITS_PER_WORD
* nfp
, 0)));
6101 t
= build (MODIFY_EXPR
, ptr_type_node
, next_fp_limit
, u
);
6102 TREE_SIDE_EFFECTS (t
) = 1;
6103 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6105 t
= build (MODIFY_EXPR
, ptr_type_node
, next_o
, u
);
6106 TREE_SIDE_EFFECTS (t
) = 1;
6107 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6109 nint
= current_function_args_info
.arg_count
[SH_ARG_INT
];
6114 u
= fold (build (PLUS_EXPR
, ptr_type_node
, u
,
6115 build_int_2 (UNITS_PER_WORD
* nint
, 0)));
6116 t
= build (MODIFY_EXPR
, ptr_type_node
, next_o_limit
, u
);
6117 TREE_SIDE_EFFECTS (t
) = 1;
6118 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6120 u
= make_tree (ptr_type_node
, nextarg
);
6121 t
= build (MODIFY_EXPR
, ptr_type_node
, next_stack
, u
);
6122 TREE_SIDE_EFFECTS (t
) = 1;
6123 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6126 /* Implement `va_arg'. */
6129 sh_va_arg (valist
, type
)
6132 HOST_WIDE_INT size
, rsize
;
6133 tree tmp
, pptr_type_node
;
6135 rtx result_ptr
, result
= NULL_RTX
;
6136 int pass_by_ref
= MUST_PASS_IN_STACK (TYPE_MODE (type
), type
);
6139 size
= int_size_in_bytes (type
);
6140 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
6141 pptr_type_node
= build_pointer_type (ptr_type_node
);
6144 type
= build_pointer_type (type
);
6146 if (! TARGET_SH5
&& (TARGET_SH2E
|| TARGET_SH4
)
6147 && ! (TARGET_HITACHI
|| sh_cfun_attr_renesas_p ()))
6149 tree f_next_o
, f_next_o_limit
, f_next_fp
, f_next_fp_limit
, f_next_stack
;
6150 tree next_o
, next_o_limit
, next_fp
, next_fp_limit
, next_stack
;
6154 f_next_o
= TYPE_FIELDS (va_list_type_node
);
6155 f_next_o_limit
= TREE_CHAIN (f_next_o
);
6156 f_next_fp
= TREE_CHAIN (f_next_o_limit
);
6157 f_next_fp_limit
= TREE_CHAIN (f_next_fp
);
6158 f_next_stack
= TREE_CHAIN (f_next_fp_limit
);
6160 next_o
= build (COMPONENT_REF
, TREE_TYPE (f_next_o
), valist
, f_next_o
);
6161 next_o_limit
= build (COMPONENT_REF
, TREE_TYPE (f_next_o_limit
),
6162 valist
, f_next_o_limit
);
6163 next_fp
= build (COMPONENT_REF
, TREE_TYPE (f_next_fp
),
6165 next_fp_limit
= build (COMPONENT_REF
, TREE_TYPE (f_next_fp_limit
),
6166 valist
, f_next_fp_limit
);
6167 next_stack
= build (COMPONENT_REF
, TREE_TYPE (f_next_stack
),
6168 valist
, f_next_stack
);
6170 /* Structures with a single member with a distinct mode are passed
6171 like their member. This is relevant if the latter has a REAL_TYPE
6172 or COMPLEX_TYPE type. */
6173 if (TREE_CODE (type
) == RECORD_TYPE
6174 && TYPE_FIELDS (type
)
6175 && TREE_CODE (TYPE_FIELDS (type
)) == FIELD_DECL
6176 && (TREE_CODE (TREE_TYPE (TYPE_FIELDS (type
))) == REAL_TYPE
6177 || TREE_CODE (TREE_TYPE (TYPE_FIELDS (type
))) == COMPLEX_TYPE
)
6178 && TREE_CHAIN (TYPE_FIELDS (type
)) == NULL_TREE
)
6179 type
= TREE_TYPE (TYPE_FIELDS (type
));
6182 pass_as_float
= ((TREE_CODE (type
) == REAL_TYPE
&& size
<= 8)
6183 || (TREE_CODE (type
) == COMPLEX_TYPE
6184 && TREE_CODE (TREE_TYPE (type
)) == REAL_TYPE
6189 pass_as_float
= (TREE_CODE (type
) == REAL_TYPE
&& size
== 4);
6192 addr_rtx
= gen_reg_rtx (Pmode
);
6193 lab_false
= gen_label_rtx ();
6194 lab_over
= gen_label_rtx ();
6196 tmp
= make_tree (pptr_type_node
, addr_rtx
);
6197 valist
= build1 (INDIRECT_REF
, ptr_type_node
, tmp
);
6202 = current_function_args_info
.arg_count
[(int) SH_ARG_FLOAT
];
6203 int n_floatregs
= MAX (0, NPARM_REGS (SFmode
) - first_floatreg
);
6205 emit_cmp_and_jump_insns (expand_expr (next_fp
, NULL_RTX
, Pmode
,
6207 expand_expr (next_fp_limit
, NULL_RTX
,
6208 Pmode
, EXPAND_NORMAL
),
6209 GE
, const1_rtx
, Pmode
, 1, lab_false
);
6211 if (TYPE_ALIGN (type
) > BITS_PER_WORD
6212 || (((TREE_CODE (type
) == REAL_TYPE
&& size
== 8) || size
== 16)
6213 && (n_floatregs
& 1)))
6215 tmp
= build (BIT_AND_EXPR
, ptr_type_node
, next_fp
,
6216 build_int_2 (UNITS_PER_WORD
, 0));
6217 tmp
= build (PLUS_EXPR
, ptr_type_node
, next_fp
, tmp
);
6218 tmp
= build (MODIFY_EXPR
, ptr_type_node
, next_fp
, tmp
);
6219 TREE_SIDE_EFFECTS (tmp
) = 1;
6220 expand_expr (tmp
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6223 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, next_fp
);
6224 r
= expand_expr (tmp
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
6226 emit_move_insn (addr_rtx
, r
);
6228 #ifdef FUNCTION_ARG_SCmode_WART
6229 if (TYPE_MODE (type
) == SCmode
&& TARGET_SH4
&& TARGET_LITTLE_ENDIAN
)
6231 rtx addr
, real
, imag
, result_value
, slot
;
6232 tree subtype
= TREE_TYPE (type
);
6234 addr
= std_expand_builtin_va_arg (valist
, subtype
);
6235 #ifdef POINTERS_EXTEND_UNSIGNED
6236 if (GET_MODE (addr
) != Pmode
)
6237 addr
= convert_memory_address (Pmode
, addr
);
6239 imag
= gen_rtx_MEM (TYPE_MODE (type
), addr
);
6240 set_mem_alias_set (imag
, get_varargs_alias_set ());
6242 addr
= std_expand_builtin_va_arg (valist
, subtype
);
6243 #ifdef POINTERS_EXTEND_UNSIGNED
6244 if (GET_MODE (addr
) != Pmode
)
6245 addr
= convert_memory_address (Pmode
, addr
);
6247 real
= gen_rtx_MEM (TYPE_MODE (type
), addr
);
6248 set_mem_alias_set (real
, get_varargs_alias_set ());
6250 result_value
= gen_rtx_CONCAT (SCmode
, real
, imag
);
6251 /* ??? this interface is stupid - why require a pointer? */
6252 result
= gen_reg_rtx (Pmode
);
6253 slot
= assign_stack_temp (SCmode
, 8, 0);
6254 emit_move_insn (slot
, result_value
);
6255 emit_move_insn (result
, XEXP (slot
, 0));
6257 #endif /* FUNCTION_ARG_SCmode_WART */
6259 emit_jump_insn (gen_jump (lab_over
));
6261 emit_label (lab_false
);
6263 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, next_stack
);
6264 r
= expand_expr (tmp
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
6266 emit_move_insn (addr_rtx
, r
);
6270 tmp
= build (PLUS_EXPR
, ptr_type_node
, next_o
,
6271 build_int_2 (rsize
, 0));
6273 emit_cmp_and_jump_insns (expand_expr (tmp
, NULL_RTX
, Pmode
,
6275 expand_expr (next_o_limit
, NULL_RTX
,
6276 Pmode
, EXPAND_NORMAL
),
6277 GT
, const1_rtx
, Pmode
, 1, lab_false
);
6279 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, next_o
);
6280 r
= expand_expr (tmp
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
6282 emit_move_insn (addr_rtx
, r
);
6284 emit_jump_insn (gen_jump (lab_over
));
6286 emit_label (lab_false
);
6288 if (size
> 4 && ! TARGET_SH4
)
6290 tmp
= build (MODIFY_EXPR
, ptr_type_node
, next_o
, next_o_limit
);
6291 TREE_SIDE_EFFECTS (tmp
) = 1;
6292 expand_expr (tmp
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6295 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, next_stack
);
6296 r
= expand_expr (tmp
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
6298 emit_move_insn (addr_rtx
, r
);
6302 emit_label (lab_over
);
6305 /* ??? In va-sh.h, there had been code to make values larger than
6306 size 8 indirect. This does not match the FUNCTION_ARG macros. */
6308 result_ptr
= std_expand_builtin_va_arg (valist
, type
);
6311 emit_move_insn (result
, result_ptr
);
6312 emit_label (lab_over
);
6315 result
= result_ptr
;
6319 #ifdef POINTERS_EXTEND_UNSIGNED
6320 if (GET_MODE (addr
) != Pmode
)
6321 addr
= convert_memory_address (Pmode
, result
);
6323 result
= gen_rtx_MEM (ptr_mode
, force_reg (Pmode
, result
));
6324 set_mem_alias_set (result
, get_varargs_alias_set ());
6326 /* ??? expand_builtin_va_arg will also set the alias set of the dereferenced
6327 argument to the varargs alias set. */
6332 sh_promote_prototypes (type
)
6339 return ! sh_attr_renesas_p (type
);
6342 /* Define where to put the arguments to a function.
6343 Value is zero to push the argument on the stack,
6344 or a hard register in which to store the argument.
6346 MODE is the argument's machine mode.
6347 TYPE is the data type of the argument (as a tree).
6348 This is null for libcalls where that information may
6350 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6351 the preceding args and about the function being called.
6352 NAMED is nonzero if this argument is a named parameter
6353 (otherwise it is an extra parameter matching an ellipsis).
6355 On SH the first args are normally in registers
6356 and the rest are pushed. Any arg that starts within the first
6357 NPARM_REGS words is at least partially passed in a register unless
6358 its data type forbids. */
6362 sh_function_arg (ca
, mode
, type
, named
)
6363 CUMULATIVE_ARGS
*ca
;
6364 enum machine_mode mode
;
6368 if (! TARGET_SH5
&& mode
== VOIDmode
)
6369 return GEN_INT (ca
->renesas_abi
? 1 : 0);
6372 && PASS_IN_REG_P (*ca
, mode
, type
)
6373 && (named
|| ! (TARGET_HITACHI
|| ca
->renesas_abi
)))
6377 if (mode
== SCmode
&& TARGET_SH4
&& TARGET_LITTLE_ENDIAN
6378 && (! FUNCTION_ARG_SCmode_WART
|| (ROUND_REG (*ca
, mode
) & 1)))
6380 rtx r1
= gen_rtx_EXPR_LIST (VOIDmode
,
6381 gen_rtx_REG (SFmode
,
6383 + (ROUND_REG (*ca
, mode
) ^ 1)),
6385 rtx r2
= gen_rtx_EXPR_LIST(VOIDmode
,
6386 gen_rtx_REG (SFmode
,
6388 + ((ROUND_REG (*ca
, mode
) + 1) ^ 1)),
6390 return gen_rtx_PARALLEL(SCmode
, gen_rtvec(2, r1
, r2
));
6393 /* If the alignment of a DF value causes an SF register to be
6394 skipped, we will use that skipped register for the next SF
6396 if ((TARGET_HITACHI
|| ca
->renesas_abi
)
6397 && ca
->free_single_fp_reg
6399 return gen_rtx_REG (mode
, ca
->free_single_fp_reg
);
6401 regno
= (BASE_ARG_REG (mode
) + ROUND_REG (*ca
, mode
))
6402 ^ (mode
== SFmode
&& TARGET_SH4
6403 && TARGET_LITTLE_ENDIAN
!= 0
6404 && ! TARGET_HITACHI
&& ! ca
->renesas_abi
);
6405 return gen_rtx_REG (mode
, regno
);
6411 if (mode
== VOIDmode
&& TARGET_SHCOMPACT
)
6412 return GEN_INT (ca
->call_cookie
);
6414 /* The following test assumes unnamed arguments are promoted to
6416 if (mode
== SFmode
&& ca
->free_single_fp_reg
)
6417 return SH5_PROTOTYPED_FLOAT_ARG (*ca
, mode
, ca
->free_single_fp_reg
);
6419 if ((GET_SH_ARG_CLASS (mode
) == SH_ARG_FLOAT
)
6420 && (named
|| ! ca
->prototype_p
)
6421 && ca
->arg_count
[(int) SH_ARG_FLOAT
] < NPARM_REGS (SFmode
))
6423 if (! ca
->prototype_p
&& TARGET_SHMEDIA
)
6424 return SH5_PROTOTYPELESS_FLOAT_ARG (*ca
, mode
);
6426 return SH5_PROTOTYPED_FLOAT_ARG (*ca
, mode
,
6428 + ca
->arg_count
[(int) SH_ARG_FLOAT
]);
6431 if (ca
->arg_count
[(int) SH_ARG_INT
] < NPARM_REGS (SImode
)
6432 && (! TARGET_SHCOMPACT
6433 || (! SHCOMPACT_FORCE_ON_STACK (mode
, type
)
6434 && ! SH5_WOULD_BE_PARTIAL_NREGS (*ca
, mode
,
6437 return gen_rtx_REG (mode
, (FIRST_PARM_REG
6438 + ca
->arg_count
[(int) SH_ARG_INT
]));
6447 /* Update the data in CUM to advance over an argument
6448 of mode MODE and data type TYPE.
6449 (TYPE is null for libcalls where that information may not be
6453 sh_function_arg_advance (ca
, mode
, type
, named
)
6454 CUMULATIVE_ARGS
*ca
;
6455 enum machine_mode mode
;
6461 else if (TARGET_SH5
)
6463 tree type2
= (ca
->byref
&& type
6466 enum machine_mode mode2
= (ca
->byref
&& type
6469 int dwords
= ((ca
->byref
6472 ? int_size_in_bytes (type2
)
6473 : GET_MODE_SIZE (mode2
)) + 7) / 8;
6474 int numregs
= MIN (dwords
, NPARM_REGS (SImode
)
6475 - ca
->arg_count
[(int) SH_ARG_INT
]);
6479 ca
->arg_count
[(int) SH_ARG_INT
] += numregs
;
6480 if (TARGET_SHCOMPACT
6481 && SHCOMPACT_FORCE_ON_STACK (mode2
, type2
))
6484 |= CALL_COOKIE_INT_REG (ca
->arg_count
[(int) SH_ARG_INT
]
6486 /* N.B. We want this also for outgoing. */
6487 ca
->stack_regs
+= numregs
;
6492 ca
->stack_regs
+= numregs
;
6493 ca
->byref_regs
+= numregs
;
6497 |= CALL_COOKIE_INT_REG (ca
->arg_count
[(int) SH_ARG_INT
]
6501 |= CALL_COOKIE_INT_REG (ca
->arg_count
[(int) SH_ARG_INT
]
6504 else if (dwords
> numregs
)
6506 int pushregs
= numregs
;
6508 if (TARGET_SHCOMPACT
)
6509 ca
->stack_regs
+= numregs
;
6510 while (pushregs
< NPARM_REGS (SImode
) - 1
6511 && (CALL_COOKIE_INT_REG_GET
6513 NPARM_REGS (SImode
) - pushregs
)
6517 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode
)
6521 if (numregs
== NPARM_REGS (SImode
))
6523 |= CALL_COOKIE_INT_REG (0, 1)
6524 | CALL_COOKIE_STACKSEQ (numregs
- 1);
6527 |= CALL_COOKIE_STACKSEQ (numregs
);
6530 if (GET_SH_ARG_CLASS (mode2
) == SH_ARG_FLOAT
6531 && (named
|| ! ca
->prototype_p
))
6533 if (mode2
== SFmode
&& ca
->free_single_fp_reg
)
6534 ca
->free_single_fp_reg
= 0;
6535 else if (ca
->arg_count
[(int) SH_ARG_FLOAT
]
6536 < NPARM_REGS (SFmode
))
6539 = MIN ((GET_MODE_SIZE (mode2
) + 7) / 8 * 2,
6541 - ca
->arg_count
[(int) SH_ARG_FLOAT
]);
6543 ca
->arg_count
[(int) SH_ARG_FLOAT
] += numfpregs
;
6545 if (TARGET_SHCOMPACT
&& ! ca
->prototype_p
)
6547 if (ca
->outgoing
&& numregs
> 0)
6551 |= (CALL_COOKIE_INT_REG
6552 (ca
->arg_count
[(int) SH_ARG_INT
]
6553 - numregs
+ ((numfpregs
- 2) / 2),
6554 4 + (ca
->arg_count
[(int) SH_ARG_FLOAT
]
6557 while (numfpregs
-= 2);
6559 else if (mode2
== SFmode
&& (named
)
6560 && (ca
->arg_count
[(int) SH_ARG_FLOAT
]
6561 < NPARM_REGS (SFmode
)))
6562 ca
->free_single_fp_reg
6563 = FIRST_FP_PARM_REG
- numfpregs
6564 + ca
->arg_count
[(int) SH_ARG_FLOAT
] + 1;
6570 if ((TARGET_HITACHI
|| ca
->renesas_abi
) && TARGET_FPU_DOUBLE
)
6572 /* Note that we've used the skipped register. */
6573 if (mode
== SFmode
&& ca
->free_single_fp_reg
)
6575 ca
->free_single_fp_reg
= 0;
6578 /* When we have a DF after an SF, there's an SF register that get
6579 skipped in order to align the DF value. We note this skipped
6580 register, because the next SF value will use it, and not the
6581 SF that follows the DF. */
6583 && ROUND_REG (*ca
, DFmode
) != ROUND_REG (*ca
, SFmode
))
6585 ca
->free_single_fp_reg
= (ROUND_REG (*ca
, SFmode
)
6586 + BASE_ARG_REG (mode
));
6590 if (! (TARGET_SH4
|| ca
->renesas_abi
)
6591 || PASS_IN_REG_P (*ca
, mode
, type
))
6592 (ca
->arg_count
[(int) GET_SH_ARG_CLASS (mode
)]
6593 = (ROUND_REG (*ca
, mode
)
6595 ? ROUND_ADVANCE (int_size_in_bytes (type
))
6596 : ROUND_ADVANCE (GET_MODE_SIZE (mode
)))));
6599 /* If the structure value address is not passed in a register, define
6600 `STRUCT_VALUE' as an expression returning an RTX for the place
6601 where the address is passed. If it returns 0, the address is
6602 passed as an "invisible" first argument. */
6603 /* The Renesas calling convention doesn't quite fit into this scheme since
6604 the address is passed like an invisible argument, but one that is always
6605 passed in memory. */
6607 sh_struct_value_rtx (fndecl
, incoming
)
6609 int incoming ATTRIBUTE_UNUSED
;
6611 if (TARGET_HITACHI
|| sh_attr_renesas_p (fndecl
))
6613 return gen_rtx_REG (Pmode
, 2);
6617 sh_return_in_memory (type
, fndecl
)
6623 if (TYPE_MODE (type
) == BLKmode
)
6624 return ((unsigned HOST_WIDE_INT
) int_size_in_bytes (type
)) > 8;
6626 return GET_MODE_SIZE (TYPE_MODE (type
)) > 8;
6630 return (TYPE_MODE (type
) == BLKmode
6631 || ((TARGET_HITACHI
|| sh_attr_renesas_p (fndecl
))
6632 && TREE_CODE (type
) == RECORD_TYPE
));
6636 /* We actually emit the code in sh_expand_prologue. We used to use
6637 a static variable to flag that we need to emit this code, but that
6638 doesn't when inlining, when functions are deferred and then emitted
6639 later. Fortunately, we already have two flags that are part of struct
6640 function that tell if a function uses varargs or stdarg. */
6642 sh_setup_incoming_varargs (ca
, mode
, type
, pretend_arg_size
, second_time
)
6643 CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
;
6644 enum machine_mode mode ATTRIBUTE_UNUSED
;
6645 tree type ATTRIBUTE_UNUSED
;
6646 int *pretend_arg_size ATTRIBUTE_UNUSED
;
6647 int second_time ATTRIBUTE_UNUSED
;
6649 if (! current_function_stdarg
)
6654 sh_strict_argument_naming (ca
)
6655 CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
;
6661 sh_pretend_outgoing_varargs_named (ca
)
6662 CUMULATIVE_ARGS
*ca
;
6664 return ! (TARGET_HITACHI
|| ca
->renesas_abi
) && ! TARGET_SH5
;
6668 /* Define the offset between two registers, one to be eliminated, and
6669 the other its replacement, at the start of a routine. */
6672 initial_elimination_offset (from
, to
)
6677 int regs_saved_rounding
= 0;
6678 int total_saved_regs_space
;
6679 int total_auto_space
;
6680 int save_flags
= target_flags
;
6682 HARD_REG_SET live_regs_mask
;
6684 shmedia_space_reserved_for_target_registers
= false;
6685 regs_saved
= calc_live_regs (&live_regs_mask
);
6686 regs_saved
+= SHMEDIA_REGS_STACK_ADJUST ();
6688 if (shmedia_reserve_space_for_target_registers_p (regs_saved
, &live_regs_mask
))
6690 shmedia_space_reserved_for_target_registers
= true;
6691 regs_saved
+= shmedia_target_regs_stack_adjust (&live_regs_mask
);
6694 if (TARGET_SH5
&& regs_saved
% (STACK_BOUNDARY
/ BITS_PER_UNIT
))
6695 regs_saved_rounding
= ((STACK_BOUNDARY
/ BITS_PER_UNIT
)
6696 - regs_saved
% (STACK_BOUNDARY
/ BITS_PER_UNIT
));
6698 total_auto_space
= rounded_frame_size (regs_saved
) - regs_saved_rounding
;
6699 copy_flags
= target_flags
;
6700 target_flags
= save_flags
;
6702 total_saved_regs_space
= regs_saved
+ regs_saved_rounding
;
6704 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
6705 return total_saved_regs_space
+ total_auto_space
6706 + current_function_args_info
.byref_regs
* 8;
6708 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
6709 return total_saved_regs_space
+ total_auto_space
6710 + current_function_args_info
.byref_regs
* 8;
6712 /* Initial gap between fp and sp is 0. */
6713 if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
6716 if (from
== RETURN_ADDRESS_POINTER_REGNUM
6717 && (to
== FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
))
6721 int n
= total_saved_regs_space
;
6722 int pr_reg
= TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
;
6723 save_schedule schedule
;
6726 n
+= total_auto_space
;
6728 /* If it wasn't saved, there's not much we can do. */
6729 if (! TEST_HARD_REG_BIT (live_regs_mask
, pr_reg
))
6732 target_flags
= copy_flags
;
6734 sh5_schedule_saves (&live_regs_mask
, &schedule
, n
);
6735 for (entry
= &schedule
.entries
[1]; entry
->mode
!= VOIDmode
; entry
++)
6736 if (entry
->reg
== pr_reg
)
6738 target_flags
= save_flags
;
6739 return entry
->offset
;
6744 return total_auto_space
;
6750 /* Handle machine specific pragmas to be semi-compatible with Renesas
6754 sh_pr_interrupt (pfile
)
6755 struct cpp_reader
*pfile ATTRIBUTE_UNUSED
;
6757 pragma_interrupt
= 1;
6762 struct cpp_reader
*pfile ATTRIBUTE_UNUSED
;
6764 pragma_interrupt
= pragma_trapa
= 1;
6768 sh_pr_nosave_low_regs (pfile
)
6769 struct cpp_reader
*pfile ATTRIBUTE_UNUSED
;
6771 pragma_nosave_low_regs
= 1;
6774 /* Generate 'handle_interrupt' attribute for decls */
6777 sh_insert_attributes (node
, attributes
)
6781 if (! pragma_interrupt
6782 || TREE_CODE (node
) != FUNCTION_DECL
)
6785 /* We are only interested in fields. */
6786 if (TREE_CODE_CLASS (TREE_CODE (node
)) != 'd')
6789 /* Add a 'handle_interrupt' attribute. */
6790 * attributes
= tree_cons (get_identifier ("interrupt_handler"), NULL
, * attributes
);
6795 /* Supported attributes:
6797 interrupt_handler -- specifies this function is an interrupt handler.
6799 sp_switch -- specifies an alternate stack for an interrupt handler
6802 trap_exit -- use a trapa to exit an interrupt function instead of
6805 renesas -- use Renesas calling/layout conventions (functions and
6810 const struct attribute_spec sh_attribute_table
[] =
6812 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
6813 { "interrupt_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute
},
6814 { "sp_switch", 1, 1, true, false, false, sh_handle_sp_switch_attribute
},
6815 { "trap_exit", 1, 1, true, false, false, sh_handle_trap_exit_attribute
},
6816 { "renesas", 0, 0, false, true, false, sh_handle_renesas_attribute
},
6817 { NULL
, 0, 0, false, false, false, NULL
}
6820 /* Handle an "interrupt_handler" attribute; arguments as in
6821 struct attribute_spec.handler. */
6823 sh_handle_interrupt_handler_attribute (node
, name
, args
, flags
, no_add_attrs
)
6826 tree args ATTRIBUTE_UNUSED
;
6827 int flags ATTRIBUTE_UNUSED
;
6830 if (TREE_CODE (*node
) != FUNCTION_DECL
)
6832 warning ("`%s' attribute only applies to functions",
6833 IDENTIFIER_POINTER (name
));
6834 *no_add_attrs
= true;
6836 else if (TARGET_SHCOMPACT
)
6838 error ("attribute interrupt_handler is not compatible with -m5-compact");
6839 *no_add_attrs
= true;
6845 /* Handle an "sp_switch" attribute; arguments as in
6846 struct attribute_spec.handler. */
6848 sh_handle_sp_switch_attribute (node
, name
, args
, flags
, no_add_attrs
)
6852 int flags ATTRIBUTE_UNUSED
;
6855 if (TREE_CODE (*node
) != FUNCTION_DECL
)
6857 warning ("`%s' attribute only applies to functions",
6858 IDENTIFIER_POINTER (name
));
6859 *no_add_attrs
= true;
6861 else if (!pragma_interrupt
)
6863 /* The sp_switch attribute only has meaning for interrupt functions. */
6864 warning ("`%s' attribute only applies to interrupt functions",
6865 IDENTIFIER_POINTER (name
));
6866 *no_add_attrs
= true;
6868 else if (TREE_CODE (TREE_VALUE (args
)) != STRING_CST
)
6870 /* The argument must be a constant string. */
6871 warning ("`%s' attribute argument not a string constant",
6872 IDENTIFIER_POINTER (name
));
6873 *no_add_attrs
= true;
6877 sp_switch
= gen_rtx_SYMBOL_REF (VOIDmode
,
6878 TREE_STRING_POINTER (TREE_VALUE (args
)));
6884 /* Handle an "trap_exit" attribute; arguments as in
6885 struct attribute_spec.handler. */
6887 sh_handle_trap_exit_attribute (node
, name
, args
, flags
, no_add_attrs
)
6891 int flags ATTRIBUTE_UNUSED
;
6894 if (TREE_CODE (*node
) != FUNCTION_DECL
)
6896 warning ("`%s' attribute only applies to functions",
6897 IDENTIFIER_POINTER (name
));
6898 *no_add_attrs
= true;
6900 else if (!pragma_interrupt
)
6902 /* The trap_exit attribute only has meaning for interrupt functions. */
6903 warning ("`%s' attribute only applies to interrupt functions",
6904 IDENTIFIER_POINTER (name
));
6905 *no_add_attrs
= true;
6907 else if (TREE_CODE (TREE_VALUE (args
)) != INTEGER_CST
)
6909 /* The argument must be a constant integer. */
6910 warning ("`%s' attribute argument not an integer constant",
6911 IDENTIFIER_POINTER (name
));
6912 *no_add_attrs
= true;
6916 trap_exit
= TREE_INT_CST_LOW (TREE_VALUE (args
));
6923 sh_handle_renesas_attribute (node
, name
, args
, flags
, no_add_attrs
)
6924 tree
*node ATTRIBUTE_UNUSED
;
6925 tree name ATTRIBUTE_UNUSED
;
6926 tree args ATTRIBUTE_UNUSED
;
6927 int flags ATTRIBUTE_UNUSED
;
6928 bool *no_add_attrs ATTRIBUTE_UNUSED
;
6933 /* True if __attribute__((renesas)) or -mrenesas. */
6935 sh_attr_renesas_p (td
)
6943 td
= TREE_TYPE (td
);
6944 return (lookup_attribute ("renesas", TYPE_ATTRIBUTES (td
))
6948 /* True if __attribute__((renesas)) or -mrenesas, for the current
6951 sh_cfun_attr_renesas_p ()
6953 return sh_attr_renesas_p (current_function_decl
);
6957 sh_cfun_interrupt_handler_p ()
6959 return (lookup_attribute ("interrupt_handler",
6960 DECL_ATTRIBUTES (current_function_decl
))
6964 /* Predicates used by the templates. */
6966 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
6967 Used only in general_movsrc_operand. */
6970 system_reg_operand (op
, mode
)
6972 enum machine_mode mode ATTRIBUTE_UNUSED
;
6984 /* Returns 1 if OP can be source of a simple move operation.
6985 Same as general_operand, but a LABEL_REF is valid, PRE_DEC is
6986 invalid as are subregs of system registers. */
6989 general_movsrc_operand (op
, mode
)
6991 enum machine_mode mode
;
6993 if (GET_CODE (op
) == MEM
)
6995 rtx inside
= XEXP (op
, 0);
6996 if (GET_CODE (inside
) == CONST
)
6997 inside
= XEXP (inside
, 0);
6999 if (GET_CODE (inside
) == LABEL_REF
)
7002 if (GET_CODE (inside
) == PLUS
7003 && GET_CODE (XEXP (inside
, 0)) == LABEL_REF
7004 && GET_CODE (XEXP (inside
, 1)) == CONST_INT
)
7007 /* Only post inc allowed. */
7008 if (GET_CODE (inside
) == PRE_DEC
)
7012 if ((mode
== QImode
|| mode
== HImode
)
7013 && (GET_CODE (op
) == SUBREG
7014 && GET_CODE (XEXP (op
, 0)) == REG
7015 && system_reg_operand (XEXP (op
, 0), mode
)))
7018 return general_operand (op
, mode
);
7021 /* Returns 1 if OP can be a destination of a move.
7022 Same as general_operand, but no preinc allowed. */
7025 general_movdst_operand (op
, mode
)
7027 enum machine_mode mode
;
7029 /* Only pre dec allowed. */
7030 if (GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) == POST_INC
)
7033 return general_operand (op
, mode
);
7036 /* Returns 1 if OP is a normal arithmetic register. */
7039 arith_reg_operand (op
, mode
)
7041 enum machine_mode mode
;
7043 if (register_operand (op
, mode
))
7047 if (GET_CODE (op
) == REG
)
7049 else if (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == REG
)
7050 regno
= REGNO (SUBREG_REG (op
));
7054 return (regno
!= T_REG
&& regno
!= PR_REG
7055 && ! TARGET_REGISTER_P (regno
)
7056 && (regno
!= FPUL_REG
|| TARGET_SH4
)
7057 && regno
!= MACH_REG
&& regno
!= MACL_REG
);
7062 /* Like above, but for DImode destinations: forbid paradoxical DImode subregs,
7063 because this would lead to missing sign extensions when truncating from
7064 DImode to SImode. */
7066 arith_reg_dest (op
, mode
)
7068 enum machine_mode mode
;
7070 if (mode
== DImode
&& GET_CODE (op
) == SUBREG
7071 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op
))) < 8)
7073 return arith_reg_operand (op
, mode
);
7077 int_gpr_dest (op
, mode
)
7079 enum machine_mode mode ATTRIBUTE_UNUSED
;
7081 enum machine_mode op_mode
= GET_MODE (op
);
7083 if (GET_MODE_CLASS (op_mode
) != MODE_INT
7084 || GET_MODE_SIZE (op_mode
) >= UNITS_PER_WORD
)
7086 if (! reload_completed
)
7088 return true_regnum (op
) <= LAST_GENERAL_REG
;
7092 fp_arith_reg_operand (op
, mode
)
7094 enum machine_mode mode
;
7096 if (register_operand (op
, mode
))
7100 if (GET_CODE (op
) == REG
)
7102 else if (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == REG
)
7103 regno
= REGNO (SUBREG_REG (op
));
7107 return (regno
>= FIRST_PSEUDO_REGISTER
7108 || FP_REGISTER_P (regno
));
7113 /* Returns 1 if OP is a valid source operand for an arithmetic insn. */
7116 arith_operand (op
, mode
)
7118 enum machine_mode mode
;
7120 if (arith_reg_operand (op
, mode
))
7125 /* FIXME: We should be checking whether the CONST_INT fits in a
7126 CONST_OK_FOR_I16 here, but this causes reload_cse to crash when
7127 attempting to transform a sequence of two 64-bit sets of the
7128 same register from literal constants into a set and an add,
7129 when the difference is too wide for an add. */
7130 if (GET_CODE (op
) == CONST_INT
7131 || EXTRA_CONSTRAINT_C16 (op
))
7136 else if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_I08 (INTVAL (op
)))
7142 /* Returns 1 if OP is a valid source operand for a compare insn. */
7145 arith_reg_or_0_operand (op
, mode
)
7147 enum machine_mode mode
;
7149 if (arith_reg_operand (op
, mode
))
7152 if (EXTRA_CONSTRAINT_Z (op
))
7158 /* Return 1 if OP is a valid source operand for an SHmedia operation
7159 that takes either a register or a 6-bit immediate. */
7162 shmedia_6bit_operand (op
, mode
)
7164 enum machine_mode mode
;
7166 return (arith_reg_operand (op
, mode
)
7167 || (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_I06 (INTVAL (op
))));
7170 /* Returns 1 if OP is a valid source operand for a logical operation. */
7173 logical_operand (op
, mode
)
7175 enum machine_mode mode
;
7177 if (arith_reg_operand (op
, mode
))
7182 if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_I10 (INTVAL (op
)))
7187 else if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_K08 (INTVAL (op
)))
7194 and_operand (op
, mode
)
7196 enum machine_mode mode
;
7198 if (logical_operand (op
, mode
))
7201 /* Check mshflo.l / mshflhi.l opportunities. */
7204 && GET_CODE (op
) == CONST_INT
7205 && CONST_OK_FOR_J16 (INTVAL (op
)))
7211 /* Nonzero if OP is a floating point value with value 0.0. */
7214 fp_zero_operand (op
)
7219 if (GET_MODE (op
) != SFmode
)
7222 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
7223 return REAL_VALUES_EQUAL (r
, dconst0
) && ! REAL_VALUE_MINUS_ZERO (r
);
7226 /* Nonzero if OP is a floating point value with value 1.0. */
7234 if (GET_MODE (op
) != SFmode
)
7237 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
7238 return REAL_VALUES_EQUAL (r
, dconst1
);
7241 /* For -m4 and -m4-single-only, mode switching is used. If we are
7242 compiling without -mfmovd, movsf_ie isn't taken into account for
7243 mode switching. We could check in machine_dependent_reorg for
7244 cases where we know we are in single precision mode, but there is
7245 interface to find that out during reload, so we must avoid
7246 choosing an fldi alternative during reload and thus failing to
7247 allocate a scratch register for the constant loading. */
7251 return ! TARGET_SH4
|| TARGET_FMOVD
|| reload_completed
;
7255 tertiary_reload_operand (op
, mode
)
7257 enum machine_mode mode ATTRIBUTE_UNUSED
;
7259 enum rtx_code code
= GET_CODE (op
);
7260 return code
== MEM
|| (TARGET_SH4
&& code
== CONST_DOUBLE
);
7264 fpscr_operand (op
, mode
)
7266 enum machine_mode mode ATTRIBUTE_UNUSED
;
7268 return (GET_CODE (op
) == REG
&& REGNO (op
) == FPSCR_REG
7269 && GET_MODE (op
) == PSImode
);
7273 fpul_operand (op
, mode
)
7275 enum machine_mode mode
;
7278 return fp_arith_reg_operand (op
, mode
);
7280 return (GET_CODE (op
) == REG
7281 && (REGNO (op
) == FPUL_REG
|| REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
7282 && GET_MODE (op
) == mode
);
7286 symbol_ref_operand (op
, mode
)
7288 enum machine_mode mode ATTRIBUTE_UNUSED
;
7290 return (GET_CODE (op
) == SYMBOL_REF
);
7293 /* Return the TLS type for TLS symbols, 0 for otherwise. */
7295 tls_symbolic_operand (op
, mode
)
7297 enum machine_mode mode ATTRIBUTE_UNUSED
;
7299 if (GET_CODE (op
) != SYMBOL_REF
)
7301 return SYMBOL_REF_TLS_MODEL (op
);
7305 commutative_float_operator (op
, mode
)
7307 enum machine_mode mode
;
7309 if (GET_MODE (op
) != mode
)
7311 switch (GET_CODE (op
))
7323 noncommutative_float_operator (op
, mode
)
7325 enum machine_mode mode
;
7327 if (GET_MODE (op
) != mode
)
7329 switch (GET_CODE (op
))
7341 unary_float_operator (op
, mode
)
7343 enum machine_mode mode
;
7345 if (GET_MODE (op
) != mode
)
7347 switch (GET_CODE (op
))
7360 binary_float_operator (op
, mode
)
7362 enum machine_mode mode
;
7364 if (GET_MODE (op
) != mode
)
7366 switch (GET_CODE (op
))
7380 binary_logical_operator (op
, mode
)
7382 enum machine_mode mode
;
7384 if (GET_MODE (op
) != mode
)
7386 switch (GET_CODE (op
))
7399 equality_comparison_operator (op
, mode
)
7401 enum machine_mode mode
;
7403 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
7404 && (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
));
7407 int greater_comparison_operator (op
, mode
)
7409 enum machine_mode mode
;
7411 if (mode
!= VOIDmode
&& GET_MODE (op
) == mode
)
7413 switch (GET_CODE (op
))
7425 int less_comparison_operator (op
, mode
)
7427 enum machine_mode mode
;
7429 if (mode
!= VOIDmode
&& GET_MODE (op
) == mode
)
7431 switch (GET_CODE (op
))
7443 /* Accept pseudos and branch target registers. */
7445 target_reg_operand (op
, mode
)
7447 enum machine_mode mode
;
7450 || GET_MODE (op
) != DImode
)
7453 if (GET_CODE (op
) == SUBREG
)
7456 if (GET_CODE (op
) != REG
)
7459 /* We must protect ourselves from matching pseudos that are virtual
7460 register, because they will eventually be replaced with hardware
7461 registers that aren't branch-target registers. */
7462 if (REGNO (op
) > LAST_VIRTUAL_REGISTER
7463 || TARGET_REGISTER_P (REGNO (op
)))
7469 /* Same as target_reg_operand, except that label_refs and symbol_refs
7470 are accepted before reload. */
7472 target_operand (op
, mode
)
7474 enum machine_mode mode
;
7479 if ((GET_MODE (op
) == DImode
|| GET_MODE (op
) == VOIDmode
)
7480 && EXTRA_CONSTRAINT_Csy (op
))
7481 return ! reload_completed
;
7483 return target_reg_operand (op
, mode
);
7487 mextr_bit_offset (op
, mode
)
7489 enum machine_mode mode ATTRIBUTE_UNUSED
;
7493 if (GET_CODE (op
) != CONST_INT
)
7496 return i
>= 1*8 && i
<= 7*8 && (i
& 7) == 0;
7500 extend_reg_operand (op
, mode
)
7502 enum machine_mode mode
;
7504 return (GET_CODE (op
) == TRUNCATE
7506 : arith_reg_operand
) (op
, mode
);
7510 trunc_hi_operand (op
, mode
)
7512 enum machine_mode mode
;
7514 enum machine_mode op_mode
= GET_MODE (op
);
7516 if (op_mode
!= SImode
&& op_mode
!= DImode
7517 && op_mode
!= V4HImode
&& op_mode
!= V2SImode
)
7519 return extend_reg_operand (op
, mode
);
7523 extend_reg_or_0_operand (op
, mode
)
7525 enum machine_mode mode
;
7527 return (GET_CODE (op
) == TRUNCATE
7529 : arith_reg_or_0_operand
) (op
, mode
);
7533 general_extend_operand (op
, mode
)
7535 enum machine_mode mode
;
7537 return (GET_CODE (op
) == TRUNCATE
7539 : nonimmediate_operand
) (op
, mode
);
7543 inqhi_operand (op
, mode
)
7545 enum machine_mode mode
;
7547 if (GET_CODE (op
) != TRUNCATE
|| mode
!= GET_MODE (op
))
7550 /* Can't use true_regnum here because copy_cost wants to know about
7551 SECONDARY_INPUT_RELOAD_CLASS. */
7552 return GET_CODE (op
) == REG
&& FP_REGISTER_P (REGNO (op
));
7556 sh_rep_vec (v
, mode
)
7558 enum machine_mode mode
;
7563 if ((GET_CODE (v
) != CONST_VECTOR
&& GET_CODE (v
) != PARALLEL
)
7564 || (GET_MODE (v
) != mode
&& mode
!= VOIDmode
))
7566 i
= XVECLEN (v
, 0) - 2;
7567 x
= XVECEXP (v
, 0, i
+ 1);
7568 if (GET_MODE_UNIT_SIZE (mode
) == 1)
7570 y
= XVECEXP (v
, 0, i
);
7571 for (i
-= 2 ; i
>= 0; i
-= 2)
7572 if (! rtx_equal_p (XVECEXP (v
, 0, i
+ 1), x
)
7573 || ! rtx_equal_p (XVECEXP (v
, 0, i
), y
))
7578 if (XVECEXP (v
, 0, i
) != x
)
7583 /* Determine if V is a constant vector matching MODE with only one element
7584 that is not a sign extension. Two byte-sized elements count as one. */
7586 sh_1el_vec (v
, mode
)
7588 enum machine_mode mode
;
7591 int i
, last
, least
, sign_ix
;
7594 if (GET_CODE (v
) != CONST_VECTOR
7595 || (GET_MODE (v
) != mode
&& mode
!= VOIDmode
))
7597 /* Determine numbers of last and of least significant elements. */
7598 last
= XVECLEN (v
, 0) - 1;
7599 least
= TARGET_LITTLE_ENDIAN
? 0 : last
;
7600 if (GET_CODE (XVECEXP (v
, 0, least
)) != CONST_INT
)
7603 if (GET_MODE_UNIT_SIZE (mode
) == 1)
7604 sign_ix
= TARGET_LITTLE_ENDIAN
? 1 : last
- 1;
7605 if (GET_CODE (XVECEXP (v
, 0, sign_ix
)) != CONST_INT
)
7607 unit_size
= GET_MODE_UNIT_SIZE (GET_MODE (v
));
7608 sign
= (INTVAL (XVECEXP (v
, 0, sign_ix
)) >> (unit_size
* BITS_PER_UNIT
- 1)
7609 ? constm1_rtx
: const0_rtx
);
7610 i
= XVECLEN (v
, 0) - 1;
7612 if (i
!= least
&& i
!= sign_ix
&& XVECEXP (v
, 0, i
) != sign
)
7619 sh_const_vec (v
, mode
)
7621 enum machine_mode mode
;
7625 if (GET_CODE (v
) != CONST_VECTOR
7626 || (GET_MODE (v
) != mode
&& mode
!= VOIDmode
))
7628 i
= XVECLEN (v
, 0) - 1;
7630 if (GET_CODE (XVECEXP (v
, 0, i
)) != CONST_INT
)
7635 /* Return the destination address of a branch. */
7638 branch_dest (branch
)
7641 rtx dest
= SET_SRC (PATTERN (branch
));
7644 if (GET_CODE (dest
) == IF_THEN_ELSE
)
7645 dest
= XEXP (dest
, 1);
7646 dest
= XEXP (dest
, 0);
7647 dest_uid
= INSN_UID (dest
);
7648 return INSN_ADDRESSES (dest_uid
);
7651 /* Return nonzero if REG is not used after INSN.
7652 We assume REG is a reload reg, and therefore does
7653 not live past labels. It may live past calls or jumps though. */
7655 reg_unused_after (reg
, insn
)
7662 /* If the reg is set by this instruction, then it is safe for our
7663 case. Disregard the case where this is a store to memory, since
7664 we are checking a register used in the store address. */
7665 set
= single_set (insn
);
7666 if (set
&& GET_CODE (SET_DEST (set
)) != MEM
7667 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
7670 while ((insn
= NEXT_INSN (insn
)))
7672 code
= GET_CODE (insn
);
7675 /* If this is a label that existed before reload, then the register
7676 if dead here. However, if this is a label added by reorg, then
7677 the register may still be live here. We can't tell the difference,
7678 so we just ignore labels completely. */
7679 if (code
== CODE_LABEL
)
7684 if (code
== JUMP_INSN
)
7687 /* If this is a sequence, we must handle them all at once.
7688 We could have for instance a call that sets the target register,
7689 and an insn in a delay slot that uses the register. In this case,
7690 we must return 0. */
7691 else if (code
== INSN
&& GET_CODE (PATTERN (insn
)) == SEQUENCE
)
7696 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
7698 rtx this_insn
= XVECEXP (PATTERN (insn
), 0, i
);
7699 rtx set
= single_set (this_insn
);
7701 if (GET_CODE (this_insn
) == CALL_INSN
)
7703 else if (GET_CODE (this_insn
) == JUMP_INSN
)
7705 if (INSN_ANNULLED_BRANCH_P (this_insn
))
7710 if (set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
)))
7712 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
7714 if (GET_CODE (SET_DEST (set
)) != MEM
)
7720 && reg_overlap_mentioned_p (reg
, PATTERN (this_insn
)))
7725 else if (code
== JUMP_INSN
)
7728 else if (GET_RTX_CLASS (code
) == 'i')
7730 rtx set
= single_set (insn
);
7732 if (set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
)))
7734 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
7735 return GET_CODE (SET_DEST (set
)) != MEM
;
7736 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
7740 if (code
== CALL_INSN
&& call_used_regs
[REGNO (reg
)])
7748 static GTY(()) rtx fpscr_rtx
;
7754 fpscr_rtx
= gen_rtx (REG
, PSImode
, FPSCR_REG
);
7755 REG_USERVAR_P (fpscr_rtx
) = 1;
7756 mark_user_reg (fpscr_rtx
);
7758 if (! reload_completed
|| mdep_reorg_phase
!= SH_AFTER_MDEP_REORG
)
7759 mark_user_reg (fpscr_rtx
);
7778 expand_sf_unop (fun
, operands
)
7779 rtx (*fun
) PARAMS ((rtx
, rtx
, rtx
));
7782 emit_sf_insn ((*fun
) (operands
[0], operands
[1], get_fpscr_rtx ()));
7786 expand_sf_binop (fun
, operands
)
7787 rtx (*fun
) PARAMS ((rtx
, rtx
, rtx
, rtx
));
7790 emit_sf_insn ((*fun
) (operands
[0], operands
[1], operands
[2],
7795 expand_df_unop (fun
, operands
)
7796 rtx (*fun
) PARAMS ((rtx
, rtx
, rtx
));
7799 emit_df_insn ((*fun
) (operands
[0], operands
[1], get_fpscr_rtx ()));
7803 expand_df_binop (fun
, operands
)
7804 rtx (*fun
) PARAMS ((rtx
, rtx
, rtx
, rtx
));
7807 emit_df_insn ((*fun
) (operands
[0], operands
[1], operands
[2],
7811 /* ??? gcc does flow analysis strictly after common subexpression
7812 elimination. As a result, common subexpression elimination fails
7813 when there are some intervening statements setting the same register.
7814 If we did nothing about this, this would hurt the precision switching
7815 for SH4 badly. There is some cse after reload, but it is unable to
7816 undo the extra register pressure from the unused instructions, and
7817 it cannot remove auto-increment loads.
7819 A C code example that shows this flow/cse weakness for (at least) SH
7820 and sparc (as of gcc ss-970706) is this:
7834 So we add another pass before common subexpression elimination, to
7835 remove assignments that are dead due to a following assignment in the
7836 same basic block. */
7839 mark_use (x
, reg_set_block
)
7840 rtx x
, *reg_set_block
;
7846 code
= GET_CODE (x
);
7851 int regno
= REGNO (x
);
7852 int nregs
= (regno
< FIRST_PSEUDO_REGISTER
7853 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
))
7857 reg_set_block
[regno
+ nregs
- 1] = 0;
7864 rtx dest
= SET_DEST (x
);
7866 if (GET_CODE (dest
) == SUBREG
)
7867 dest
= SUBREG_REG (dest
);
7868 if (GET_CODE (dest
) != REG
)
7869 mark_use (dest
, reg_set_block
);
7870 mark_use (SET_SRC (x
), reg_set_block
);
7877 const char *fmt
= GET_RTX_FORMAT (code
);
7879 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7882 mark_use (XEXP (x
, i
), reg_set_block
);
7883 else if (fmt
[i
] == 'E')
7884 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7885 mark_use (XVECEXP (x
, i
, j
), reg_set_block
);
7892 static rtx get_free_reg
PARAMS ((HARD_REG_SET
));
7894 /* This function returns a register to use to load the address to load
7895 the fpscr from. Currently it always returns r1 or r7, but when we are
7896 able to use pseudo registers after combine, or have a better mechanism
7897 for choosing a register, it should be done here. */
7898 /* REGS_LIVE is the liveness information for the point for which we
7899 need this allocation. In some bare-bones exit blocks, r1 is live at the
7900 start. We can even have all of r0..r3 being live:
7901 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
7902 INSN before which new insns are placed with will clobber the register
7903 we return. If a basic block consists only of setting the return value
7904 register to a pseudo and using that register, the return value is not
7905 live before or after this block, yet we we'll insert our insns right in
7909 get_free_reg (regs_live
)
7910 HARD_REG_SET regs_live
;
7912 if (! TEST_HARD_REG_BIT (regs_live
, 1))
7913 return gen_rtx_REG (Pmode
, 1);
7915 /* Hard reg 1 is live; since this is a SMALL_REGISTER_CLASSES target,
7916 there shouldn't be anything but a jump before the function end. */
7917 if (! TEST_HARD_REG_BIT (regs_live
, 7))
7918 return gen_rtx_REG (Pmode
, 7);
7923 /* This function will set the fpscr from memory.
7924 MODE is the mode we are setting it to. */
7926 fpscr_set_from_mem (mode
, regs_live
)
7928 HARD_REG_SET regs_live
;
7930 enum attr_fp_mode fp_mode
= mode
;
7931 rtx addr_reg
= get_free_reg (regs_live
);
7933 if (fp_mode
== (enum attr_fp_mode
) ACTUAL_NORMAL_MODE (FP_MODE
))
7934 emit_insn (gen_fpu_switch1 (addr_reg
));
7936 emit_insn (gen_fpu_switch0 (addr_reg
));
7939 /* Is the given character a logical line separator for the assembler? */
7940 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
7941 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == ';')
7945 sh_insn_length_adjustment (insn
)
7948 /* Instructions with unfilled delay slots take up an extra two bytes for
7949 the nop in the delay slot. */
7950 if (((GET_CODE (insn
) == INSN
7951 && GET_CODE (PATTERN (insn
)) != USE
7952 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
7953 || GET_CODE (insn
) == CALL_INSN
7954 || (GET_CODE (insn
) == JUMP_INSN
7955 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
7956 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
))
7957 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn
)))) != SEQUENCE
7958 && get_attr_needs_delay_slot (insn
) == NEEDS_DELAY_SLOT_YES
)
7961 /* SH2e has a bug that prevents the use of annulled branches, so if
7962 the delay slot is not filled, we'll have to put a NOP in it. */
7963 if (sh_cpu
== CPU_SH2E
7964 && GET_CODE (insn
) == JUMP_INSN
7965 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
7966 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
7967 && get_attr_type (insn
) == TYPE_CBRANCH
7968 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn
)))) != SEQUENCE
)
7971 /* sh-dsp parallel processing insn take four bytes instead of two. */
7973 if (GET_CODE (insn
) == INSN
)
7976 rtx body
= PATTERN (insn
);
7977 const char *template;
7979 int maybe_label
= 1;
7981 if (GET_CODE (body
) == ASM_INPUT
)
7982 template = XSTR (body
, 0);
7983 else if (asm_noperands (body
) >= 0)
7985 = decode_asm_operands (body
, NULL
, NULL
, NULL
, NULL
);
7994 while (c
== ' ' || c
== '\t');
7995 /* all sh-dsp parallel-processing insns start with p.
7996 The only non-ppi sh insn starting with p is pref.
7997 The only ppi starting with pr is prnd. */
7998 if ((c
== 'p' || c
== 'P') && strncasecmp ("re", template, 2))
8000 /* The repeat pseudo-insn expands two three insns, a total of
8001 six bytes in size. */
8002 else if ((c
== 'r' || c
== 'R')
8003 && ! strncasecmp ("epeat", template, 5))
8005 while (c
&& c
!= '\n' && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c
))
8007 /* If this is a label, it is obviously not a ppi insn. */
8008 if (c
== ':' && maybe_label
)
8013 else if (c
== '\'' || c
== '"')
8018 maybe_label
= c
!= ':';
8026 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
8027 isn't protected by a PIC unspec. */
8029 nonpic_symbol_mentioned_p (x
)
8032 register const char *fmt
;
8035 if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
8036 || GET_CODE (x
) == PC
)
8039 /* We don't want to look into the possible MEM location of a
8040 CONST_DOUBLE, since we're not going to use it, in general. */
8041 if (GET_CODE (x
) == CONST_DOUBLE
)
8044 if (GET_CODE (x
) == UNSPEC
8045 && (XINT (x
, 1) == UNSPEC_PIC
8046 || XINT (x
, 1) == UNSPEC_GOT
8047 || XINT (x
, 1) == UNSPEC_GOTOFF
8048 || XINT (x
, 1) == UNSPEC_GOTPLT
8049 || XINT (x
, 1) == UNSPEC_GOTTPOFF
8050 || XINT (x
, 1) == UNSPEC_DTPOFF
8051 || XINT (x
, 1) == UNSPEC_PLT
))
8054 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
8055 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
8061 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8062 if (nonpic_symbol_mentioned_p (XVECEXP (x
, i
, j
)))
8065 else if (fmt
[i
] == 'e' && nonpic_symbol_mentioned_p (XEXP (x
, i
)))
8072 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
8073 @GOTOFF in `reg'. */
8075 legitimize_pic_address (orig
, mode
, reg
)
8077 enum machine_mode mode ATTRIBUTE_UNUSED
;
8080 if (tls_symbolic_operand (orig
, Pmode
))
8083 if (GET_CODE (orig
) == LABEL_REF
8084 || (GET_CODE (orig
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (orig
)))
8087 reg
= gen_reg_rtx (Pmode
);
8089 emit_insn (gen_symGOTOFF2reg (reg
, orig
));
8092 else if (GET_CODE (orig
) == SYMBOL_REF
)
8095 reg
= gen_reg_rtx (Pmode
);
8097 emit_insn (gen_symGOT2reg (reg
, orig
));
8103 /* Mark the use of a constant in the literal table. If the constant
8104 has multiple labels, make it unique. */
8106 mark_constant_pool_use (x
)
8109 rtx insn
, lab
, pattern
;
8114 switch (GET_CODE (x
))
8124 /* Get the first label in the list of labels for the same constant
8125 and delete another labels in the list. */
8127 for (insn
= PREV_INSN (x
); insn
; insn
= PREV_INSN (insn
))
8129 if (GET_CODE (insn
) != CODE_LABEL
8130 || LABEL_REFS (insn
) != NEXT_INSN (insn
))
8135 for (insn
= LABEL_REFS (lab
); insn
; insn
= LABEL_REFS (insn
))
8136 INSN_DELETED_P (insn
) = 1;
8138 /* Mark constants in a window. */
8139 for (insn
= NEXT_INSN (x
); insn
; insn
= NEXT_INSN (insn
))
8141 if (GET_CODE (insn
) != INSN
)
8144 pattern
= PATTERN (insn
);
8145 if (GET_CODE (pattern
) != UNSPEC_VOLATILE
)
8148 switch (XINT (pattern
, 1))
8150 case UNSPECV_CONST2
:
8151 case UNSPECV_CONST4
:
8152 case UNSPECV_CONST8
:
8153 XVECEXP (pattern
, 0, 1) = const1_rtx
;
8155 case UNSPECV_WINDOW_END
:
8156 if (XVECEXP (pattern
, 0, 0) == x
)
8159 case UNSPECV_CONST_END
:
8169 /* Return true if it's possible to redirect BRANCH1 to the destination
8170 of an unconditional jump BRANCH2. We only want to do this if the
8171 resulting branch will have a short displacement. */
8173 sh_can_redirect_branch (branch1
, branch2
)
8177 if (flag_expensive_optimizations
&& simplejump_p (branch2
))
8179 rtx dest
= XEXP (SET_SRC (single_set (branch2
)), 0);
8183 for (distance
= 0, insn
= NEXT_INSN (branch1
);
8184 insn
&& distance
< 256;
8185 insn
= PREV_INSN (insn
))
8190 distance
+= get_attr_length (insn
);
8192 for (distance
= 0, insn
= NEXT_INSN (branch1
);
8193 insn
&& distance
< 256;
8194 insn
= NEXT_INSN (insn
))
8199 distance
+= get_attr_length (insn
);
8205 /* Return nonzero if register old_reg can be renamed to register new_reg. */
8207 sh_hard_regno_rename_ok (old_reg
, new_reg
)
8208 unsigned int old_reg ATTRIBUTE_UNUSED
;
8209 unsigned int new_reg
;
8212 /* Interrupt functions can only use registers that have already been
8213 saved by the prologue, even if they would normally be
8216 if (sh_cfun_interrupt_handler_p () && !regs_ever_live
[new_reg
])
8222 /* Function to update the integer COST
8223 based on the relationship between INSN that is dependent on
8224 DEP_INSN through the dependence LINK. The default is to make no
8225 adjustment to COST. This can be used for example to specify to
8226 the scheduler that an output- or anti-dependence does not incur
8227 the same cost as a data-dependence. The return value should be
8228 the new value for COST. */
8230 sh_adjust_cost (insn
, link
, dep_insn
, cost
)
8232 rtx link ATTRIBUTE_UNUSED
;
8240 /* On SHmedia, if the dependence is an anti-dependence or
8241 output-dependence, there is no cost. */
8242 if (REG_NOTE_KIND (link
) != 0)
8245 if (get_attr_is_mac_media (insn
)
8246 && get_attr_is_mac_media (dep_insn
))
8249 else if (REG_NOTE_KIND (link
) == 0)
8251 enum attr_type dep_type
, type
;
8253 if (recog_memoized (insn
) < 0
8254 || recog_memoized (dep_insn
) < 0)
8257 dep_type
= get_attr_type (dep_insn
);
8258 if (dep_type
== TYPE_FLOAD
|| dep_type
== TYPE_PCFLOAD
)
8260 if ((dep_type
== TYPE_LOAD_SI
|| dep_type
== TYPE_PCLOAD_SI
)
8261 && (type
= get_attr_type (insn
)) != TYPE_CALL
8262 && type
!= TYPE_SFUNC
)
8265 /* The only input for a call that is timing-critical is the
8266 function's address. */
8267 if (GET_CODE(insn
) == CALL_INSN
)
8269 rtx call
= PATTERN (insn
);
8271 if (GET_CODE (call
) == PARALLEL
)
8272 call
= XVECEXP (call
, 0 ,0);
8273 if (GET_CODE (call
) == SET
)
8274 call
= SET_SRC (call
);
8275 if (GET_CODE (call
) == CALL
&& GET_CODE (XEXP (call
, 0)) == MEM
8276 && ! reg_set_p (XEXP (XEXP (call
, 0), 0), dep_insn
))
8279 /* Likewise, the most timing critical input for an sfuncs call
8280 is the function address. However, sfuncs typically start
8281 using their arguments pretty quickly.
8282 Assume a four cycle delay before they are needed. */
8283 /* All sfunc calls are parallels with at least four components.
8284 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
8285 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
8286 && XVECLEN (PATTERN (insn
), 0) >= 4
8287 && (reg
= sfunc_uses_reg (insn
)))
8289 if (! reg_set_p (reg
, dep_insn
))
8292 /* When the preceding instruction loads the shift amount of
8293 the following SHAD/SHLD, the latency of the load is increased
8296 && get_attr_type (insn
) == TYPE_DYN_SHIFT
8297 && get_attr_any_int_load (dep_insn
) == ANY_INT_LOAD_YES
8298 && reg_overlap_mentioned_p (SET_DEST (PATTERN (dep_insn
)),
8299 XEXP (SET_SRC (single_set(insn
)),
8302 /* When an LS group instruction with a latency of less than
8303 3 cycles is followed by a double-precision floating-point
8304 instruction, FIPR, or FTRV, the latency of the first
8305 instruction is increased to 3 cycles. */
8307 && get_attr_insn_class (dep_insn
) == INSN_CLASS_LS_GROUP
8308 && get_attr_dfp_comp (insn
) == DFP_COMP_YES
)
8310 /* The lsw register of a double-precision computation is ready one
8312 else if (reload_completed
8313 && get_attr_dfp_comp (dep_insn
) == DFP_COMP_YES
8314 && (use_pat
= single_set (insn
))
8315 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn
))),
8319 if (get_attr_any_fp_comp (dep_insn
) == ANY_FP_COMP_YES
8320 && get_attr_late_fp_use (insn
) == LATE_FP_USE_YES
)
8323 /* An anti-dependence penalty of two applies if the first insn is a double
8324 precision fadd / fsub / fmul. */
8325 else if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
8326 && recog_memoized (dep_insn
) >= 0
8327 && get_attr_type (dep_insn
) == TYPE_DFP_ARITH
8328 /* A lot of alleged anti-flow dependences are fake,
8329 so check this one is real. */
8330 && flow_dependent_p (dep_insn
, insn
))
8337 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
8338 if DEP_INSN is anti-flow dependent on INSN. */
8340 flow_dependent_p (insn
, dep_insn
)
8343 rtx tmp
= PATTERN (insn
);
8345 note_stores (PATTERN (dep_insn
), flow_dependent_p_1
, &tmp
);
8346 return tmp
== NULL_RTX
;
8349 /* A helper function for flow_dependent_p called through note_stores. */
8351 flow_dependent_p_1 (x
, pat
, data
)
8353 rtx pat ATTRIBUTE_UNUSED
;
8356 rtx
* pinsn
= (rtx
*) data
;
8358 if (*pinsn
&& reg_referenced_p (x
, *pinsn
))
8362 /* For use by ALLOCATE_INITIAL_VALUE. Note that sh.md contains some
8363 'special function' patterns (type sfunc) that clobber pr, but that
8364 do not look like function calls to leaf_function_p. Hence we must
8365 do this extra check. */
8369 return REG_N_SETS (TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
);
8372 /* This Function returns nonzero if the DFA based scheduler interface
8373 is to be used. At present this is supported for the SH4 only. */
8375 sh_use_dfa_interface()
8377 if (TARGET_HARD_SH4
)
8383 /* This function returns "2" to indicate dual issue for the SH4
8384 processor. To be used by the DFA pipeline description. */
8388 if (TARGET_SUPERSCALAR
)
8394 /* SHmedia requires registers for branches, so we can't generate new
8395 branches past reload. */
8397 sh_cannot_modify_jumps_p ()
8399 return (TARGET_SHMEDIA
&& (reload_in_progress
|| reload_completed
));
8403 sh_target_reg_class (void)
8405 return TARGET_SHMEDIA
? TARGET_REGS
: NO_REGS
;
8409 sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen
)
8411 return (shmedia_space_reserved_for_target_registers
8412 && (! after_prologue_epilogue_gen
|| TARGET_SAVE_ALL_TARGET_REGS
));
8416 sh_ms_bitfield_layout_p (record_type
)
8417 tree record_type ATTRIBUTE_UNUSED
;
8419 return (TARGET_SH5
|| TARGET_HITACHI
|| sh_attr_renesas_p (record_type
));
8423 On the SH1..SH4, the trampoline looks like
8424 2 0002 D202 mov.l l2,r2
8425 1 0000 D301 mov.l l1,r3
8428 5 0008 00000000 l1: .long area
8429 6 000c 00000000 l2: .long function
8431 SH5 (compact) uses r1 instead of r3 for the static chain. */
8434 /* Emit RTL insns to initialize the variable parts of a trampoline.
8435 FNADDR is an RTX for the address of the function's pure code.
8436 CXT is an RTX for the static chain value for the function. */
8439 sh_initialize_trampoline (tramp
, fnaddr
, cxt
)
8440 rtx tramp
, fnaddr
, cxt
;
8442 if (TARGET_SHMEDIA64
)
8447 rtx movi1
= GEN_INT (0xcc000010);
8448 rtx shori1
= GEN_INT (0xc8000010);
8451 /* The following trampoline works within a +- 128 KB range for cxt:
8452 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
8453 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
8454 gettr tr1,r1; blink tr0,r63 */
8455 /* Address rounding makes it hard to compute the exact bounds of the
8456 offset for this trampoline, but we have a rather generous offset
8457 range, so frame_offset should do fine as an upper bound. */
8458 if (cxt
== virtual_stack_vars_rtx
&& frame_offset
< 0x20000)
8460 /* ??? could optimize this trampoline initialization
8461 by writing DImode words with two insns each. */
8462 rtx mask
= force_reg (DImode
, GEN_INT (0x3fffc00));
8463 rtx insn
= gen_rtx_MINUS (DImode
, cxt
, tramp
);
8464 insn
= gen_rtx_ASHIFT (DImode
, insn
, GEN_INT (10-2));
8465 insn
= gen_rtx_AND (DImode
, insn
, mask
);
8466 /* Or in ptb/u .,tr1 pattern */
8467 insn
= gen_rtx_IOR (DImode
, insn
, gen_int_mode (0xec000010, SImode
));
8468 insn
= force_operand (insn
, NULL_RTX
);
8469 insn
= gen_lowpart (SImode
, insn
);
8470 emit_move_insn (gen_rtx_MEM (SImode
, tramp
), insn
);
8471 insn
= gen_rtx_LSHIFTRT (DImode
, fnaddr
, GEN_INT (38));
8472 insn
= gen_rtx_AND (DImode
, insn
, mask
);
8473 insn
= force_operand (gen_rtx_IOR (DImode
, movi1
, insn
), NULL_RTX
);
8474 insn
= gen_lowpart (SImode
, insn
);
8475 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 4)), insn
);
8476 insn
= gen_rtx_LSHIFTRT (DImode
, fnaddr
, GEN_INT (22));
8477 insn
= gen_rtx_AND (DImode
, insn
, mask
);
8478 insn
= force_operand (gen_rtx_IOR (DImode
, shori1
, insn
), NULL_RTX
);
8479 insn
= gen_lowpart (SImode
, insn
);
8480 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 8)), insn
);
8481 insn
= gen_rtx_LSHIFTRT (DImode
, fnaddr
, GEN_INT (6));
8482 insn
= gen_rtx_AND (DImode
, insn
, mask
);
8483 insn
= force_operand (gen_rtx_IOR (DImode
, shori1
, insn
), NULL_RTX
);
8484 insn
= gen_lowpart (SImode
, insn
);
8485 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 12)),
8487 insn
= gen_rtx_ASHIFT (DImode
, fnaddr
, GEN_INT (10));
8488 insn
= gen_rtx_AND (DImode
, insn
, mask
);
8489 insn
= force_operand (gen_rtx_IOR (DImode
, shori1
, insn
), NULL_RTX
);
8490 insn
= gen_lowpart (SImode
, insn
);
8491 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 16)),
8493 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 20)),
8494 GEN_INT (0x6bf10600));
8495 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 24)),
8496 GEN_INT (0x4415fc10));
8497 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 28)),
8498 GEN_INT (0x4401fff0));
8499 emit_insn (gen_ic_invalidate_line (tramp
));
8502 tramp_templ
= gen_rtx_SYMBOL_REF (Pmode
,"__GCC_nested_trampoline");
8503 fixed_len
= TRAMPOLINE_SIZE
- 2 * GET_MODE_SIZE (Pmode
);
8505 tramp_templ
= gen_datalabel_ref (tramp_templ
);
8506 dst
= gen_rtx_MEM (BLKmode
, tramp
);
8507 src
= gen_rtx_MEM (BLKmode
, tramp_templ
);
8508 set_mem_align (dst
, 256);
8509 set_mem_align (src
, 64);
8510 emit_block_move (dst
, src
, GEN_INT (fixed_len
), BLOCK_OP_NORMAL
);
8512 emit_move_insn (gen_rtx_MEM (Pmode
, plus_constant (tramp
, fixed_len
)),
8514 emit_move_insn (gen_rtx_MEM (Pmode
,
8515 plus_constant (tramp
,
8517 + GET_MODE_SIZE (Pmode
))),
8519 emit_insn (gen_ic_invalidate_line (tramp
));
8522 else if (TARGET_SHMEDIA
)
8524 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
8525 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
8526 rtx quad0
= gen_reg_rtx (DImode
), cxtload
= gen_reg_rtx (DImode
);
8527 rtx quad1
= gen_reg_rtx (DImode
), quad2
= gen_reg_rtx (DImode
);
8528 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
8529 rotated 10 right, and higher 16 bit of every 32 selected. */
8531 = force_reg (V2HImode
, (simplify_gen_subreg
8532 (V2HImode
, GEN_INT (0x4330432), SImode
, 0)));
8533 rtx ptabs
= force_reg (DImode
, GEN_INT (0x6bf10600));
8534 rtx blink
= force_reg (DImode
, GEN_INT (0x4401fff0));
8536 tramp
= force_reg (Pmode
, tramp
);
8537 fnaddr
= force_reg (SImode
, fnaddr
);
8538 cxt
= force_reg (SImode
, cxt
);
8539 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode
, quad0
, 0),
8540 gen_rtx_SUBREG (V2HImode
, fnaddr
, 0),
8542 emit_insn (gen_rotrdi3_mextr (quad0
, quad0
,
8543 GEN_INT (TARGET_LITTLE_ENDIAN
? 24 : 56)));
8544 emit_insn (gen_ashldi3_media (quad0
, quad0
, GEN_INT (2)));
8545 emit_move_insn (gen_rtx_MEM (DImode
, tramp
), quad0
);
8546 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode
, cxtload
, 0),
8547 gen_rtx_SUBREG (V2HImode
, cxt
, 0),
8549 emit_insn (gen_rotrdi3_mextr (cxtload
, cxtload
,
8550 GEN_INT (TARGET_LITTLE_ENDIAN
? 24 : 56)));
8551 emit_insn (gen_ashldi3_media (cxtload
, cxtload
, GEN_INT (2)));
8552 if (TARGET_LITTLE_ENDIAN
)
8554 emit_insn (gen_mshflo_l_di (quad1
, ptabs
, cxtload
));
8555 emit_insn (gen_mextr4 (quad2
, cxtload
, blink
));
8559 emit_insn (gen_mextr4 (quad1
, cxtload
, ptabs
));
8560 emit_insn (gen_mshflo_l_di (quad2
, blink
, cxtload
));
8562 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, 8)), quad1
);
8563 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, 16)), quad2
);
8564 emit_insn (gen_ic_invalidate_line (tramp
));
8567 else if (TARGET_SHCOMPACT
)
8569 emit_insn (gen_initialize_trampoline (tramp
, cxt
, fnaddr
));
8572 emit_move_insn (gen_rtx_MEM (SImode
, tramp
),
8573 gen_int_mode (TARGET_LITTLE_ENDIAN
? 0xd301d202 : 0xd202d301,
8575 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 4)),
8576 gen_int_mode (TARGET_LITTLE_ENDIAN
? 0x0009422b : 0x422b0009,
8578 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 8)),
8580 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 12)),
8584 if (TARGET_USERMODE
)
8585 emit_library_call (function_symbol ("__ic_invalidate"),
8586 0, VOIDmode
, 1, tramp
, SImode
);
8588 emit_insn (gen_ic_invalidate_line (tramp
));
8592 /* FIXME: This is overly conservative. A SHcompact function that
8593 receives arguments ``by reference'' will have them stored in its
8594 own stack frame, so it must not pass pointers or references to
8595 these arguments to other functions by means of sibling calls. */
8597 sh_function_ok_for_sibcall (decl
, exp
)
8599 tree exp ATTRIBUTE_UNUSED
;
8602 && (! TARGET_SHCOMPACT
8603 || current_function_args_info
.stack_regs
== 0)
8604 && ! sh_cfun_interrupt_handler_p ());
8607 /* Machine specific built-in functions. */
8609 struct builtin_description
8611 const enum insn_code icode
;
8612 const char *const name
;
8616 /* describe number and signedness of arguments; arg[0] == result
8617 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
8618 static const char signature_args
[][4] =
8620 #define SH_BLTIN_V2SI2 0
8622 #define SH_BLTIN_V4HI2 1
8624 #define SH_BLTIN_V2SI3 2
8626 #define SH_BLTIN_V4HI3 3
8628 #define SH_BLTIN_V8QI3 4
8630 #define SH_BLTIN_MAC_HISI 5
8632 #define SH_BLTIN_SH_HI 6
8634 #define SH_BLTIN_SH_SI 7
8636 #define SH_BLTIN_V4HI2V2SI 8
8638 #define SH_BLTIN_V4HI2V8QI 9
8640 #define SH_BLTIN_SISF 10
8642 #define SH_BLTIN_LDUA_L 11
8644 #define SH_BLTIN_LDUA_Q 12
8646 #define SH_BLTIN_STUA_L 13
8648 #define SH_BLTIN_STUA_Q 14
8650 #define SH_BLTIN_UDI 15
8652 #define SH_BLTIN_NUM_SHARED_SIGNATURES 16
8653 #define SH_BLTIN_2 16
8654 #define SH_BLTIN_SU 16
8656 #define SH_BLTIN_3 17
8657 #define SH_BLTIN_SUS 17
8659 #define SH_BLTIN_PSSV 18
8661 #define SH_BLTIN_XXUU 19
8662 #define SH_BLTIN_UUUU 19
8664 #define SH_BLTIN_PV 20
8667 /* mcmv: operands considered unsigned. */
8668 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
8669 /* mperm: control value considered unsigned int. */
8670 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
8671 /* mshards_q: returns signed short. */
8672 /* nsb: takes long long arg, returns unsigned char. */
8673 static const struct builtin_description bdesc
[] =
8675 { CODE_FOR_absv2si2
, "__builtin_absv2si2", SH_BLTIN_V2SI2
},
8676 { CODE_FOR_absv4hi2
, "__builtin_absv4hi2", SH_BLTIN_V4HI2
},
8677 { CODE_FOR_addv2si3
, "__builtin_addv2si3", SH_BLTIN_V2SI3
},
8678 { CODE_FOR_addv4hi3
, "__builtin_addv4hi3", SH_BLTIN_V4HI3
},
8679 { CODE_FOR_ssaddv2si3
,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3
},
8680 { CODE_FOR_usaddv8qi3
,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3
},
8681 { CODE_FOR_ssaddv4hi3
,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3
},
8683 { CODE_FOR_alloco32
, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV
},
8684 { CODE_FOR_alloco64
, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV
},
8686 { CODE_FOR_negcmpeqv8qi
,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3
},
8687 { CODE_FOR_negcmpeqv2si
,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3
},
8688 { CODE_FOR_negcmpeqv4hi
,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3
},
8689 { CODE_FOR_negcmpgtuv8qi
,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3
},
8690 { CODE_FOR_negcmpgtv2si
,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3
},
8691 { CODE_FOR_negcmpgtv4hi
,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3
},
8692 { CODE_FOR_mcmv
, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU
},
8693 { CODE_FOR_mcnvs_lw
, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3
},
8694 { CODE_FOR_mcnvs_wb
, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI
},
8695 { CODE_FOR_mcnvs_wub
, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI
},
8696 { CODE_FOR_mextr1
, "__builtin_sh_media_MEXTR1", SH_BLTIN_UDI
},
8697 { CODE_FOR_mextr2
, "__builtin_sh_media_MEXTR2", SH_BLTIN_UDI
},
8698 { CODE_FOR_mextr3
, "__builtin_sh_media_MEXTR3", SH_BLTIN_UDI
},
8699 { CODE_FOR_mextr4
, "__builtin_sh_media_MEXTR4", SH_BLTIN_UDI
},
8700 { CODE_FOR_mextr5
, "__builtin_sh_media_MEXTR5", SH_BLTIN_UDI
},
8701 { CODE_FOR_mextr6
, "__builtin_sh_media_MEXTR6", SH_BLTIN_UDI
},
8702 { CODE_FOR_mextr7
, "__builtin_sh_media_MEXTR7", SH_BLTIN_UDI
},
8703 { CODE_FOR_mmacfx_wl
, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI
},
8704 { CODE_FOR_mmacnfx_wl
,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI
},
8705 { CODE_FOR_mulv2si3
, "__builtin_mulv2si3", SH_BLTIN_V2SI3
, },
8706 { CODE_FOR_mulv4hi3
, "__builtin_mulv4hi3", SH_BLTIN_V4HI3
},
8707 { CODE_FOR_mmulfx_l
, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3
},
8708 { CODE_FOR_mmulfx_w
, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3
},
8709 { CODE_FOR_mmulfxrp_w
,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3
},
8710 { CODE_FOR_mmulhi_wl
, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI
},
8711 { CODE_FOR_mmullo_wl
, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI
},
8712 { CODE_FOR_mmulsum_wq
,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU
},
8713 { CODE_FOR_mperm_w
, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI
},
8714 { CODE_FOR_msad_ubq
, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU
},
8715 { CODE_FOR_mshalds_l
, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI
},
8716 { CODE_FOR_mshalds_w
, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI
},
8717 { CODE_FOR_ashrv2si3
, "__builtin_ashrv2si3", SH_BLTIN_SH_SI
},
8718 { CODE_FOR_ashrv4hi3
, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI
},
8719 { CODE_FOR_mshards_q
, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS
},
8720 { CODE_FOR_mshfhi_b
, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3
},
8721 { CODE_FOR_mshfhi_l
, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3
},
8722 { CODE_FOR_mshfhi_w
, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3
},
8723 { CODE_FOR_mshflo_b
, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3
},
8724 { CODE_FOR_mshflo_l
, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3
},
8725 { CODE_FOR_mshflo_w
, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3
},
8726 { CODE_FOR_ashlv2si3
, "__builtin_ashlv2si3", SH_BLTIN_SH_SI
},
8727 { CODE_FOR_ashlv4hi3
, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI
},
8728 { CODE_FOR_lshrv2si3
, "__builtin_lshrv2si3", SH_BLTIN_SH_SI
},
8729 { CODE_FOR_lshrv4hi3
, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI
},
8730 { CODE_FOR_subv2si3
, "__builtin_subv2si3", SH_BLTIN_V2SI3
},
8731 { CODE_FOR_subv4hi3
, "__builtin_subv4hi3", SH_BLTIN_V4HI3
},
8732 { CODE_FOR_sssubv2si3
,"__builtin_sssubv2si3", SH_BLTIN_V2SI3
},
8733 { CODE_FOR_ussubv8qi3
,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3
},
8734 { CODE_FOR_sssubv4hi3
,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3
},
8735 { CODE_FOR_fcosa_s
, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF
},
8736 { CODE_FOR_fsina_s
, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF
},
8737 { CODE_FOR_fipr
, "__builtin_sh_media_FIPR_S", SH_BLTIN_3
},
8738 { CODE_FOR_ftrv
, "__builtin_sh_media_FTRV_S", SH_BLTIN_3
},
8739 { CODE_FOR_fsrra_s
, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2
},
8741 { CODE_FOR_ldhi_l
, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L
},
8742 { CODE_FOR_ldhi_q
, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q
},
8743 { CODE_FOR_ldlo_l
, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L
},
8744 { CODE_FOR_ldlo_q
, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q
},
8745 { CODE_FOR_sthi_l
, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L
},
8746 { CODE_FOR_sthi_q
, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q
},
8747 { CODE_FOR_stlo_l
, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L
},
8748 { CODE_FOR_stlo_q
, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q
},
8749 { CODE_FOR_ldhi_l64
, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L
},
8750 { CODE_FOR_ldhi_q64
, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q
},
8751 { CODE_FOR_ldlo_l64
, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L
},
8752 { CODE_FOR_ldlo_q64
, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q
},
8753 { CODE_FOR_sthi_l64
, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L
},
8754 { CODE_FOR_sthi_q64
, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q
},
8755 { CODE_FOR_stlo_l64
, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L
},
8756 { CODE_FOR_stlo_q64
, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q
},
8758 { CODE_FOR_nsb
, "__builtin_sh_media_NSB", SH_BLTIN_SU
},
8759 { CODE_FOR_byterev
, "__builtin_sh_media_BYTEREV", SH_BLTIN_2
},
8761 { CODE_FOR_prefetch32
,"__builtin_sh_media_PREFO", SH_BLTIN_PSSV
},
8762 { CODE_FOR_prefetch64
,"__builtin_sh_media_PREFO", SH_BLTIN_PSSV
}
8767 sh_media_init_builtins ()
8769 tree shared
[SH_BLTIN_NUM_SHARED_SIGNATURES
];
8770 const struct builtin_description
*d
;
8772 memset (shared
, 0, sizeof shared
);
8773 for (d
= bdesc
; d
- bdesc
< (int) ARRAY_SIZE (bdesc
); d
++)
8775 tree type
, arg_type
;
8776 int signature
= d
->signature
;
8779 if (signature
< SH_BLTIN_NUM_SHARED_SIGNATURES
&& shared
[signature
])
8780 type
= shared
[signature
];
8783 int has_result
= signature_args
[signature
][0] != 0;
8785 if (signature_args
[signature
][1] == 8
8786 && (insn_data
[d
->icode
].operand
[has_result
].mode
!= Pmode
))
8788 if (! TARGET_FPU_ANY
8789 && FLOAT_MODE_P (insn_data
[d
->icode
].operand
[0].mode
))
8791 type
= void_list_node
;
8794 int arg
= signature_args
[signature
][i
];
8795 int opno
= i
- 1 + has_result
;
8798 arg_type
= ptr_type_node
;
8800 arg_type
= ((*lang_hooks
.types
.type_for_mode
)
8801 (insn_data
[d
->icode
].operand
[opno
].mode
,
8806 arg_type
= void_type_node
;
8809 type
= tree_cons (NULL_TREE
, arg_type
, type
);
8811 type
= build_function_type (arg_type
, type
);
8812 if (signature
< SH_BLTIN_NUM_SHARED_SIGNATURES
)
8813 shared
[signature
] = type
;
8815 builtin_function (d
->name
, type
, d
- bdesc
, BUILT_IN_MD
,
8824 sh_media_init_builtins ();
8827 /* Expand an expression EXP that calls a built-in function,
8828 with result going to TARGET if that's convenient
8829 (and in mode MODE if that's convenient).
8830 SUBTARGET may be used as the target for computing one of EXP's operands.
8831 IGNORE is nonzero if the value is to be ignored. */
8834 sh_expand_builtin (exp
, target
, subtarget
, mode
, ignore
)
8837 rtx subtarget ATTRIBUTE_UNUSED
;
8838 enum machine_mode mode ATTRIBUTE_UNUSED
;
8841 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
8842 tree arglist
= TREE_OPERAND (exp
, 1);
8843 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8844 const struct builtin_description
*d
= &bdesc
[fcode
];
8845 enum insn_code icode
= d
->icode
;
8846 int signature
= d
->signature
;
8847 enum machine_mode tmode
= VOIDmode
;
8852 if (signature_args
[signature
][0])
8857 tmode
= insn_data
[icode
].operand
[0].mode
;
8859 || GET_MODE (target
) != tmode
8860 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8861 target
= gen_reg_rtx (tmode
);
8867 for (i
= 1; i
<= 3; i
++, nop
++)
8870 enum machine_mode opmode
, argmode
;
8872 if (! signature_args
[signature
][i
])
8874 arg
= TREE_VALUE (arglist
);
8875 if (arg
== error_mark_node
)
8877 arglist
= TREE_CHAIN (arglist
);
8878 opmode
= insn_data
[icode
].operand
[nop
].mode
;
8879 argmode
= TYPE_MODE (TREE_TYPE (arg
));
8880 if (argmode
!= opmode
)
8881 arg
= build1 (NOP_EXPR
,
8882 (*lang_hooks
.types
.type_for_mode
) (opmode
, 0), arg
);
8883 op
[nop
] = expand_expr (arg
, NULL_RTX
, opmode
, 0);
8884 if (! (*insn_data
[icode
].operand
[nop
].predicate
) (op
[nop
], opmode
))
8885 op
[nop
] = copy_to_mode_reg (opmode
, op
[nop
]);
8891 pat
= (*insn_data
[d
->icode
].genfun
) (op
[0]);
8894 pat
= (*insn_data
[d
->icode
].genfun
) (op
[0], op
[1]);
8897 pat
= (*insn_data
[d
->icode
].genfun
) (op
[0], op
[1], op
[2]);
8900 pat
= (*insn_data
[d
->icode
].genfun
) (op
[0], op
[1], op
[2], op
[3]);
8912 sh_expand_unop_v2sf (code
, op0
, op1
)
8916 rtx sel0
= const0_rtx
;
8917 rtx sel1
= const1_rtx
;
8918 rtx (*fn
) PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
)) = gen_unary_sf_op
;
8919 rtx op
= gen_rtx_fmt_e (code
, SFmode
, op1
);
8921 emit_insn ((*fn
) (op0
, op1
, op
, sel0
, sel0
));
8922 emit_insn ((*fn
) (op0
, op1
, op
, sel1
, sel1
));
8926 sh_expand_binop_v2sf (code
, op0
, op1
, op2
)
8930 rtx sel0
= const0_rtx
;
8931 rtx sel1
= const1_rtx
;
8932 rtx (*fn
) PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
))
8934 rtx op
= gen_rtx_fmt_ee (code
, SFmode
, op1
, op2
);
8936 emit_insn ((*fn
) (op0
, op1
, op2
, op
, sel0
, sel0
, sel0
, sel1
));
8937 emit_insn ((*fn
) (op0
, op1
, op2
, op
, sel1
, sel1
, sel1
, sel0
));
8940 /* Return the class of registers for which a mode change from FROM to TO
8943 sh_cannot_change_mode_class (from
, to
, class)
8944 enum machine_mode from
, to
;
8945 enum reg_class
class;
8947 if (GET_MODE_SIZE (from
) != GET_MODE_SIZE (to
))
8949 if (TARGET_LITTLE_ENDIAN
)
8951 if (GET_MODE_SIZE (to
) < 8 || GET_MODE_SIZE (from
) < 8)
8952 return reg_classes_intersect_p (DF_REGS
, class);
8956 if (GET_MODE_SIZE (from
) < 8)
8957 return reg_classes_intersect_p (DF_HI_REGS
, class);
8964 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
8965 that label is used. */
8968 sh_mark_label (address
, nuses
)
8972 if (GOTOFF_P (address
))
8974 /* Extract the label or symbol. */
8975 address
= XEXP (address
, 0);
8976 if (GET_CODE (address
) == PLUS
)
8977 address
= XEXP (address
, 0);
8978 address
= XVECEXP (address
, 0, 0);
8980 if (GET_CODE (address
) == LABEL_REF
8981 && GET_CODE (XEXP (address
, 0)) == CODE_LABEL
)
8982 LABEL_NUSES (XEXP (address
, 0)) += nuses
;
8985 /* Compute extra cost of moving data between one register class
8988 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
8989 uses this information. Hence, the general register <-> floating point
8990 register information here is not used for SFmode. */
8993 sh_register_move_cost (mode
, srcclass
, dstclass
)
8994 enum machine_mode mode
;
8995 enum reg_class srcclass
, dstclass
;
8997 if (dstclass
== T_REGS
|| dstclass
== PR_REGS
)
9000 if (dstclass
== MAC_REGS
&& srcclass
== MAC_REGS
)
9003 if (mode
== SImode
&& ! TARGET_SHMEDIA
&& TARGET_FMOVD
9004 && REGCLASS_HAS_FP_REG (srcclass
)
9005 && REGCLASS_HAS_FP_REG (dstclass
))
9008 if ((REGCLASS_HAS_FP_REG (dstclass
) && srcclass
== MAC_REGS
)
9009 || (dstclass
== MAC_REGS
&& REGCLASS_HAS_FP_REG (srcclass
)))
9012 if ((REGCLASS_HAS_FP_REG (dstclass
)
9013 && REGCLASS_HAS_GENERAL_REG (srcclass
))
9014 || (REGCLASS_HAS_GENERAL_REG (dstclass
)
9015 && REGCLASS_HAS_FP_REG (srcclass
)))
9016 return ((TARGET_SHMEDIA
? 4 : TARGET_FMOVD
? 8 : 12)
9017 * ((GET_MODE_SIZE (mode
) + 7) / 8U));
9019 if ((dstclass
== FPUL_REGS
9020 && REGCLASS_HAS_GENERAL_REG (srcclass
))
9021 || (srcclass
== FPUL_REGS
9022 && REGCLASS_HAS_GENERAL_REG (dstclass
)))
9025 if ((dstclass
== FPUL_REGS
9026 && (srcclass
== PR_REGS
|| srcclass
== MAC_REGS
|| srcclass
== T_REGS
))
9027 || (srcclass
== FPUL_REGS
9028 && (dstclass
== PR_REGS
|| dstclass
== MAC_REGS
)))
9031 if ((srcclass
== TARGET_REGS
&& ! REGCLASS_HAS_GENERAL_REG (dstclass
))
9032 || ((dstclass
) == TARGET_REGS
&& ! REGCLASS_HAS_GENERAL_REG (srcclass
)))
9035 if ((srcclass
== FPSCR_REGS
&& ! REGCLASS_HAS_GENERAL_REG (dstclass
))
9036 || (dstclass
== FPSCR_REGS
&& ! REGCLASS_HAS_GENERAL_REG (srcclass
)))
9041 && ! REGCLASS_HAS_GENERAL_REG (srcclass
)
9042 && ! REGCLASS_HAS_GENERAL_REG (dstclass
)))
9043 return 2 * ((GET_MODE_SIZE (mode
) + 7) / 8U);
9045 return 2 * ((GET_MODE_SIZE (mode
) + 3) / 4U);
9048 /* Like register_operand, but take into account that SHMEDIA can use
9049 the constant zero like a general register. */
9051 sh_register_operand (op
, mode
)
9053 enum machine_mode mode
;
9055 if (op
== CONST0_RTX (mode
) && TARGET_SHMEDIA
)
9057 return register_operand (op
, mode
);
9060 static rtx emit_load_ptr
PARAMS ((rtx
, rtx
));
9063 emit_load_ptr (reg
, addr
)
9066 rtx mem
= gen_rtx_MEM (ptr_mode
, addr
);
9068 if (Pmode
!= ptr_mode
)
9069 mem
= gen_rtx_SIGN_EXTEND (Pmode
, mem
);
9070 return emit_move_insn (reg
, mem
);
9074 sh_output_mi_thunk (file
, thunk_fndecl
, delta
, vcall_offset
, function
)
9076 tree thunk_fndecl ATTRIBUTE_UNUSED
;
9077 HOST_WIDE_INT delta
;
9078 HOST_WIDE_INT vcall_offset
;
9081 CUMULATIVE_ARGS cum
;
9082 int structure_value_byref
= 0;
9083 rtx
this, this_value
, sibcall
, insns
, funexp
;
9084 tree funtype
= TREE_TYPE (function
);
9085 int simple_add
= CONST_OK_FOR_ADD (delta
);
9087 rtx scratch0
, scratch1
, scratch2
;
9089 reload_completed
= 1;
9090 epilogue_completed
= 1;
9092 current_function_uses_only_leaf_regs
= 1;
9094 emit_note (NOTE_INSN_PROLOGUE_END
);
9096 /* Find the "this" pointer. We have such a wide range of ABIs for the
9097 SH that it's best to do this completely machine independently.
9098 "this" is passed as first argument, unless a structure return pointer
9099 comes first, in which case "this" comes second. */
9100 INIT_CUMULATIVE_ARGS (cum
, funtype
, NULL_RTX
, 0);
9101 #ifndef PCC_STATIC_STRUCT_RETURN
9102 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
9103 structure_value_byref
= 1;
9104 #endif /* not PCC_STATIC_STRUCT_RETURN */
9105 if (structure_value_byref
&& sh_struct_value_rtx (function
, 0) == 0)
9107 tree ptype
= build_pointer_type (TREE_TYPE (funtype
));
9109 FUNCTION_ARG_ADVANCE (cum
, Pmode
, ptype
, 1);
9111 this = FUNCTION_ARG (cum
, Pmode
, ptr_type_node
, 1);
9113 /* For SHcompact, we only have r0 for a scratch register: r1 is the
9114 static chain pointer (even if you can't have nested virtual functions
9115 right now, someone might implement them sometime), and the rest of the
9116 registers are used for argument passing, are callee-saved, or reserved. */
9117 scratch0
= scratch1
= scratch2
= gen_rtx_REG (Pmode
, 0);
9120 scratch1
= gen_rtx_REG (ptr_mode
, 1);
9121 /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer
9122 pointing where to return struct values. */
9123 scratch2
= gen_rtx_REG (Pmode
, 3);
9125 else if (TARGET_SHMEDIA
)
9127 scratch1
= gen_rtx_REG (ptr_mode
, 21);
9128 scratch2
= gen_rtx_REG (Pmode
, TR0_REG
);
9131 this_value
= plus_constant (this, delta
);
9133 && (simple_add
|| scratch0
!= scratch1
)
9134 && strict_memory_address_p (ptr_mode
, this_value
))
9136 emit_load_ptr (scratch0
, this_value
);
9142 else if (simple_add
)
9143 emit_move_insn (this, this_value
);
9146 emit_move_insn (scratch1
, GEN_INT (delta
));
9147 emit_insn (gen_add2_insn (this, scratch1
));
9155 emit_load_ptr (scratch0
, this);
9157 offset_addr
= plus_constant (scratch0
, vcall_offset
);
9158 if (strict_memory_address_p (ptr_mode
, offset_addr
))
9160 else if (! TARGET_SH5
)
9162 /* scratch0 != scratch1, and we have indexed loads. Get better
9163 schedule by loading the offset into r1 and using an indexed
9164 load - then the load of r1 can issue before the load from
9165 (this + delta) finishes. */
9166 emit_move_insn (scratch1
, GEN_INT (vcall_offset
));
9167 offset_addr
= gen_rtx_PLUS (Pmode
, scratch0
, scratch1
);
9169 else if (CONST_OK_FOR_ADD (vcall_offset
))
9171 emit_insn (gen_add2_insn (scratch0
, GEN_INT (vcall_offset
)));
9172 offset_addr
= scratch0
;
9174 else if (scratch0
!= scratch1
)
9176 emit_move_insn (scratch1
, GEN_INT (vcall_offset
));
9177 emit_insn (gen_add2_insn (scratch0
, scratch1
));
9178 offset_addr
= scratch0
;
9181 abort (); /* FIXME */
9182 emit_load_ptr (scratch0
, offset_addr
);
9184 if (Pmode
!= ptr_mode
)
9185 scratch0
= gen_rtx_TRUNCATE (ptr_mode
, scratch0
);
9186 emit_insn (gen_add2_insn (this, scratch0
));
9189 /* Generate a tail call to the target function. */
9190 if (! TREE_USED (function
))
9192 assemble_external (function
);
9193 TREE_USED (function
) = 1;
9195 funexp
= XEXP (DECL_RTL (function
), 0);
9196 emit_move_insn (scratch2
, funexp
);
9197 funexp
= gen_rtx_MEM (FUNCTION_MODE
, scratch2
);
9198 sibcall
= emit_call_insn (gen_sibcall (funexp
, const0_rtx
, NULL_RTX
));
9199 SIBLING_CALL_P (sibcall
) = 1;
9200 use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall
), this);
9203 /* Run just enough of rest_of_compilation to do scheduling and get
9204 the insns emitted. Note that use_thunk calls
9205 assemble_start_function and assemble_end_function. */
9207 insn_locators_initialize ();
9208 insns
= get_insns ();
9210 if (optimize
> 0 && flag_schedule_insns_after_reload
)
9213 find_basic_blocks (insns
, max_reg_num (), rtl_dump_file
);
9214 life_analysis (insns
, rtl_dump_file
, PROP_FINAL
);
9216 split_all_insns (1);
9218 schedule_insns (rtl_dump_file
);
9223 if (optimize
> 0 && flag_delayed_branch
)
9224 dbr_schedule (insns
, rtl_dump_file
);
9225 shorten_branches (insns
);
9226 final_start_function (insns
, file
, 1);
9227 final (insns
, file
, 1, 0);
9228 final_end_function ();
9230 if (optimize
> 0 && flag_schedule_insns_after_reload
)
9232 /* Release all memory allocated by flow. */
9233 free_basic_block_vars (0);
9235 /* Release all memory held by regsets now. */
9236 regset_release_memory ();
9239 reload_completed
= 0;
9240 epilogue_completed
= 0;
9245 function_symbol (const char *name
)
9247 rtx sym
= gen_rtx_SYMBOL_REF (Pmode
, name
);
9248 SYMBOL_REF_FLAGS (sym
) = SYMBOL_FLAG_FUNCTION
;
9252 /* Find the number of a general purpose register in S. */
9254 scavenge_reg (HARD_REG_SET
*s
)
9257 for (r
= FIRST_GENERAL_REG
; r
<= LAST_GENERAL_REG
; r
++)
9258 if (TEST_HARD_REG_BIT (*s
, r
))
9264 sh_get_pr_initial_val (void)
9268 /* ??? Unfortunately, get_hard_reg_initial_val doesn't always work for the
9269 PR register on SHcompact, because it might be clobbered by the prologue.
9270 We check first if that is known to be the case. */
9271 if (TARGET_SHCOMPACT
9272 && ((current_function_args_info
.call_cookie
9273 & ~ CALL_COOKIE_RET_TRAMP (1))
9274 || current_function_has_nonlocal_label
))
9275 return gen_rtx_MEM (SImode
, return_address_pointer_rtx
);
9277 /* If we haven't finished rtl generation, there might be a nonlocal label
9278 that we haven't seen yet.
9279 ??? get_hard_reg_initial_val fails if it is called while no_new_pseudos
9280 is set, unless it has been called before for the same register. And even
9281 then, we end in trouble if we didn't use the register in the same
9282 basic block before. So call get_hard_reg_initial_val now and wrap it
9283 in an unspec if we might need to replace it. */
9284 /* ??? We also must do this for TARGET_SH1 in general, because otherwise
9285 combine can put the pseudo returned by get_hard_reg_initial_val into
9286 instructions that need a general purpose registers, which will fail to
9287 be recognized when the pseudo becomes allocated to PR. */
9289 = get_hard_reg_initial_val (Pmode
, TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
);
9291 return gen_rtx_UNSPEC (SImode
, gen_rtvec (1, val
), UNSPEC_RA
);