1 ;;- Machine description for Renesas / SuperH SH.
2 ;; Copyright (C) 1993-2017 Free Software Foundation, Inc.
3 ;; Contributed by Steve Chamberlain (sac@cygnus.com).
4 ;; Improved by Jim Wilson (wilson@cygnus.com).
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
23 ;; ??? Should prepend a * to all pattern names which are not used.
24 ;; This will make the compiler smaller, and rebuilds after changes faster.
26 ;; ??? Should be enhanced to include support for many more GNU superoptimizer
27 ;; sequences. Especially the sequences for arithmetic right shifts.
29 ;; ??? Should check all DImode patterns for consistency and usefulness.
31 ;; ??? The MAC.W and MAC.L instructions are not supported. There is no
32 ;; way to generate them.
34 ;; BSR is not generated by the compiler proper, but when relaxing, it
35 ;; generates .uses pseudo-ops that allow linker relaxation to create
36 ;; BSR. This is actually implemented in bfd/{coff,elf32}-sh.c
38 ;; Special constraints for SH machine description:
45 ;; Special formats used for outputting SH instructions:
47 ;; %. -- print a .s if insn needs delay slot
48 ;; %@ -- print rte/rts if is/isn't an interrupt function
49 ;; %# -- output a nop if there is nothing to put in the delay slot
50 ;; %O -- print a constant without the #
51 ;; %R -- print the lsw reg of a double
52 ;; %S -- print the msw reg of a double
53 ;; %T -- print next word of a double REG or MEM
55 ;; Special predicates:
57 ;; arith_operand -- operand is valid source for arithmetic op
58 ;; arith_reg_operand -- operand is valid register for arithmetic op
59 ;; general_movdst_operand -- operand is valid move destination
60 ;; general_movsrc_operand -- operand is valid move source
61 ;; logical_operand -- operand is valid source for logical op
63 ;; -------------------------------------------------------------------------
65 ;; -------------------------------------------------------------------------
79 ;; Virtual FPSCR - bits that are used by FP ops.
82 ;; Virtual FPSCR - bits that are updated by FP ops.
111 (FPSCR_PR 524288) ;; 1 << 19
112 (FPSCR_SZ 1048576) ;; 1 << 20
113 (FPSCR_FR 2097152) ;; 1 << 21
116 (define_c_enum "unspec" [
117 ;; These are used with unspec.
146 ;; (unspec [TARGET ANCHOR] UNSPEC_SYMOFF) == TARGET - ANCHOR.
148 ;; (unspec [OFFSET ANCHOR] UNSPEC_PCREL_SYMOFF) == OFFSET - (ANCHOR - .).
152 UNSPEC_GOTOFFFUNCDESC
154 UNSPEC_BUILTIN_STRLEN
157 (define_c_enum "unspecv" [
158 ;; These are used with unspec_volatile.
175 ;; -------------------------------------------------------------------------
177 ;; -------------------------------------------------------------------------
182 "sh1,sh2,sh2e,sh2a,sh3,sh3e,sh4,sh4a"
183 (const (symbol_ref "sh_cpu_attr")))
185 (define_attr "endian" "big,little"
186 (const (if_then_else (symbol_ref "TARGET_LITTLE_ENDIAN")
187 (const_string "little") (const_string "big"))))
189 ;; Indicate if the default fpu mode is single precision.
190 (define_attr "fpu_single" "yes,no"
191 (const (if_then_else (symbol_ref "TARGET_FPU_SINGLE")
192 (const_string "yes") (const_string "no"))))
194 (define_attr "fmovd" "yes,no"
195 (const (if_then_else (symbol_ref "TARGET_FMOVD")
196 (const_string "yes") (const_string "no"))))
198 (define_attr "pipe_model" "sh1,sh4"
200 (cond [(symbol_ref "TARGET_SUPERSCALAR") (const_string "sh4")]
201 (const_string "sh1"))))
203 ;; cbranch conditional branch instructions
204 ;; jump unconditional jumps
205 ;; arith ordinary arithmetic
206 ;; arith3 a compound insn that behaves similarly to a sequence of
207 ;; three insns of type arith
208 ;; arith3b like above, but might end with a redirected branch
210 ;; load_si Likewise, SImode variant for general register.
211 ;; fload Likewise, but load to fp register.
213 ;; fstore floating point register to memory
214 ;; move general purpose register to register
215 ;; movi8 8-bit immediate to general purpose register
216 ;; mt_group other sh4 mt instructions
217 ;; fmove register to register, floating point
218 ;; smpy word precision integer multiply
219 ;; dmpy longword or doublelongword precision integer multiply
221 ;; pload load of pr reg, which can't be put into delay slot of rts
222 ;; prset copy register to pr reg, ditto
223 ;; pstore store of pr reg, which can't be put into delay slot of jsr
224 ;; prget copy pr to register, ditto
225 ;; pcload pc relative load of constant value
226 ;; pcfload Likewise, but load to fp register.
227 ;; pcload_si Likewise, SImode variant for general register.
228 ;; rte return from exception
229 ;; sfunc special function call with known used registers
230 ;; call function call
232 ;; fpscr_toggle toggle a bit in the fpscr
233 ;; fdiv floating point divide (or square root)
234 ;; gp_fpul move from general purpose register to fpul
235 ;; fpul_gp move from fpul to general purpose register
236 ;; mac_gp move from mac[lh] to general purpose register
237 ;; gp_mac move from general purpose register to mac[lh]
238 ;; mac_mem move from mac[lh] to memory
239 ;; mem_mac move from memory to mac[lh]
240 ;; dfp_arith,dfp_mul, fp_cmp,dfp_cmp,dfp_conv
241 ;; ftrc_s fix_truncsfsi2_i4
242 ;; dfdiv double precision floating point divide (or square root)
243 ;; cwb ic_invalidate_line_i
244 ;; movua SH4a unaligned load
245 ;; fsrra square root reciprocal approximate
246 ;; fsca sine and cosine approximate
247 ;; tls_load load TLS related address
248 ;; nil no-op move, will be deleted.
251 "mt_group,cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,load,load_si,
252 fload,store,fstore,move,movi8,fmove,smpy,dmpy,return,pload,prset,pstore,
253 prget,pcload,pcload_si,pcfload,rte,sfunc,call,fp,fpscr_toggle,fdiv,ftrc_s,
254 dfp_arith,dfp_mul,fp_cmp,dfp_cmp,dfp_conv,dfdiv,gp_fpul,fpul_gp,mac_gp,
255 gp_mac,mac_mem,mem_mac,mem_fpscr,gp_fpscr,cwb,movua,fsrra,fsca,tls_load,
257 (const_string "other"))
259 ;; We define a new attribute namely "insn_class".We use
260 ;; this for the DFA based pipeline description.
262 ;; mt_group SH4 "mt" group instructions.
264 ;; ex_group SH4 "ex" group instructions.
266 ;; ls_group SH4 "ls" group instructions.
268 (define_attr "insn_class"
269 "mt_group,ex_group,ls_group,br_group,fe_group,co_group,none"
270 (cond [(eq_attr "type" "move,mt_group") (const_string "mt_group")
271 (eq_attr "type" "movi8,arith,dyn_shift") (const_string "ex_group")
272 (eq_attr "type" "fmove,load,pcload,load_si,pcload_si,fload,pcfload,
273 store,fstore,gp_fpul,fpul_gp") (const_string "ls_group")
274 (eq_attr "type" "cbranch,jump") (const_string "br_group")
275 (eq_attr "type" "fp,fp_cmp,fdiv,ftrc_s,dfp_arith,dfp_mul,dfp_conv,dfdiv")
276 (const_string "fe_group")
277 (eq_attr "type" "jump_ind,smpy,dmpy,mac_gp,return,pload,prset,pstore,
278 prget,rte,sfunc,call,dfp_cmp,mem_fpscr,gp_fpscr,cwb,
279 gp_mac,mac_mem,mem_mac") (const_string "co_group")]
280 (const_string "none")))
282 ;; nil are zero instructions, and arith3 / arith3b are multiple instructions,
283 ;; so these do not belong in an insn group, although they are modeled
284 ;; with their own define_insn_reservations.
286 ;; Indicate what precision must be selected in fpscr for this insn, if any.
287 (define_attr "fp_mode" "single,double,none" (const_string "none"))
289 ;; Indicate if the fpu mode is set by this instruction
290 ;; "unknown" must have the value as "none" in fp_mode, and means
291 ;; that the instruction/abi has left the processor in an unknown
293 ;; "none" means that nothing has changed and no mode is set.
294 ;; This attribute is only used for the Renesas ABI.
295 (define_attr "fp_set" "single,double,unknown,none" (const_string "none"))
297 ; If a conditional branch destination is within -252..258 bytes away
298 ; from the instruction it can be 2 bytes long. Something in the
299 ; range -4090..4100 bytes can be 6 bytes long. All other conditional
300 ; branches are initially assumed to be 16 bytes long.
301 ; In machine_dependent_reorg, we split all branches that are longer than
304 ;; The maximum range used for SImode constant pool entries is 1018. A final
305 ;; instruction can add 8 bytes while only being 4 bytes in size, thus we
306 ;; can have a total of 1022 bytes in the pool. Add 4 bytes for a branch
307 ;; instruction around the pool table, 2 bytes of alignment before the table,
308 ;; and 30 bytes of alignment after the table. That gives a maximum total
309 ;; pool size of 1058 bytes.
310 ;; Worst case code/pool content size ratio is 1:2 (using asms).
311 ;; Thus, in the worst case, there is one instruction in front of a maximum
312 ;; sized pool, and then there are 1052 bytes of pool for every 508 bytes of
313 ;; code. For the last n bytes of code, there are 2n + 36 bytes of pool.
314 ;; If we have a forward branch, the initial table will be put after the
315 ;; unconditional branch.
317 ;; ??? We could do much better by keeping track of the actual pcloads within
318 ;; the branch range and in the pcload range in front of the branch range.
320 ;; ??? This looks ugly because genattrtab won't allow if_then_else or cond
322 (define_attr "short_cbranch_p" "no,yes"
323 (cond [(match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
325 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 506))
327 (match_test "NEXT_INSN (PREV_INSN (insn)) != insn")
329 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 508))
331 ] (const_string "no")))
333 (define_attr "med_branch_p" "no,yes"
334 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 990))
337 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
339 (leu (plus (minus (match_dup 0) (pc)) (const_int 4092))
342 ] (const_string "no")))
344 (define_attr "med_cbranch_p" "no,yes"
345 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 988))
348 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
350 (leu (plus (minus (match_dup 0) (pc)) (const_int 4090))
353 ] (const_string "no")))
355 (define_attr "braf_branch_p" "no,yes"
356 (cond [(match_test "! TARGET_SH2")
358 (leu (plus (minus (match_dup 0) (pc)) (const_int 10330))
361 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
363 (leu (plus (minus (match_dup 0) (pc)) (const_int 32764))
366 ] (const_string "no")))
368 (define_attr "braf_cbranch_p" "no,yes"
369 (cond [(match_test "! TARGET_SH2")
371 (leu (plus (minus (match_dup 0) (pc)) (const_int 10328))
374 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
376 (leu (plus (minus (match_dup 0) (pc)) (const_int 32762))
379 ] (const_string "no")))
381 ;; An unconditional jump in the range -4092..4098 can be 2 bytes long.
382 ;; For wider ranges, we need a combination of a code and a data part.
383 ;; If we can get a scratch register for a long range jump, the code
384 ;; part can be 4 bytes long; otherwise, it must be 8 bytes long.
385 ;; If the jump is in the range -32764..32770, the data part can be 2 bytes
386 ;; long; otherwise, it must be 6 bytes long.
388 ;; All other instructions are two bytes long by default.
390 ;; ??? This should use something like *branch_p (minus (match_dup 0) (pc)),
391 ;; but getattrtab doesn't understand this.
392 (define_attr "length" ""
393 (cond [(eq_attr "type" "cbranch")
394 (cond [(eq_attr "short_cbranch_p" "yes")
396 (eq_attr "med_cbranch_p" "yes")
398 (eq_attr "braf_cbranch_p" "yes")
400 ;; ??? using pc is not computed transitively.
401 (ne (match_dup 0) (match_dup 0))
403 (match_test "flag_pic")
406 (eq_attr "type" "jump")
407 (cond [(eq_attr "med_branch_p" "yes")
409 (and (match_test "prev_nonnote_insn (insn)")
410 (and (eq (symbol_ref "GET_CODE (prev_nonnote_insn (insn))")
412 (eq (symbol_ref "INSN_CODE (prev_nonnote_insn (insn))")
413 (symbol_ref "code_for_indirect_jump_scratch"))))
414 (cond [(eq_attr "braf_branch_p" "yes")
416 (not (match_test "flag_pic"))
418 (match_test "TARGET_SH2")
419 (const_int 10)] (const_int 18))
420 (eq_attr "braf_branch_p" "yes")
422 ;; ??? using pc is not computed transitively.
423 (ne (match_dup 0) (match_dup 0))
425 (match_test "flag_pic")
430 ;; DFA descriptions for the pipelines
435 (include "iterators.md")
436 (include "predicates.md")
437 (include "constraints.md")
439 ;; Definitions for filling delay slots
441 (define_attr "needs_delay_slot" "yes,no" (const_string "no"))
443 (define_attr "banked" "yes,no"
444 (cond [(match_test "sh_loads_bankedreg_p (insn)")
445 (const_string "yes")]
446 (const_string "no")))
448 ;; ??? This should be (nil) instead of (const_int 0)
449 (define_attr "hit_stack" "yes,no"
450 (cond [(not (match_test "find_regno_note (insn, REG_INC, SP_REG)"))
452 (const_string "yes")))
454 (define_attr "interrupt_function" "no,yes"
455 (const (symbol_ref "current_function_interrupt")))
457 (define_attr "in_delay_slot" "yes,no"
458 (cond [(eq_attr "type" "cbranch") (const_string "no")
459 (eq_attr "type" "pcload,pcload_si") (const_string "no")
460 (eq_attr "type" "fpscr_toggle") (const_string "no")
461 (eq_attr "needs_delay_slot" "yes") (const_string "no")
462 (eq_attr "length" "2") (const_string "yes")
463 ] (const_string "no")))
465 (define_attr "cond_delay_slot" "yes,no"
466 (cond [(eq_attr "in_delay_slot" "yes") (const_string "yes")
467 ] (const_string "no")))
469 (define_attr "is_sfunc" ""
470 (if_then_else (eq_attr "type" "sfunc") (const_int 1) (const_int 0)))
472 ;; SH4 Double-precision computation with double-precision result -
473 ;; the two halves are ready at different times.
474 (define_attr "dfp_comp" "yes,no"
475 (cond [(eq_attr "type" "dfp_arith,dfp_mul,dfp_conv,dfdiv") (const_string "yes")]
476 (const_string "no")))
478 ;; Insns for which the latency of a preceding fp insn is decreased by one.
479 (define_attr "late_fp_use" "yes,no" (const_string "no"))
480 ;; And feeding insns for which this relevant.
481 (define_attr "any_fp_comp" "yes,no"
482 (cond [(eq_attr "type" "fp,fdiv,ftrc_s,dfp_arith,dfp_mul,dfp_conv,dfdiv")
483 (const_string "yes")]
484 (const_string "no")))
486 (define_attr "any_int_load" "yes,no"
487 (cond [(eq_attr "type" "load,load_si,pcload,pcload_si")
488 (const_string "yes")]
489 (const_string "no")))
491 (define_attr "highpart" "user, ignore, extend, depend, must_split"
492 (const_string "user"))
495 (eq_attr "needs_delay_slot" "yes")
496 [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
498 ;; Since a normal return (rts) implicitly uses the PR register,
499 ;; we can't allow PR register loads in an rts delay slot.
500 ;; On the SH1* and SH2*, the rte instruction reads the return pc from the
501 ;; stack, and thus we can't put a pop instruction in its delay slot.
502 ;; On the SH3* and SH4*, the rte instruction does not use the stack, so a
503 ;; pop instruction can go in the delay slot, unless it references a banked
504 ;; register (the register bank is switched by rte).
506 (eq_attr "type" "return")
507 [(and (eq_attr "in_delay_slot" "yes")
508 (ior (and (eq_attr "interrupt_function" "no")
509 (eq_attr "type" "!pload,prset"))
510 (and (eq_attr "interrupt_function" "yes")
511 (ior (match_test "TARGET_SH3") (eq_attr "hit_stack" "no"))
512 (eq_attr "banked" "no"))))
515 ;; Since a call implicitly uses the PR register, we can't allow
516 ;; a PR register store in a jsr delay slot.
519 (ior (eq_attr "type" "call") (eq_attr "type" "sfunc"))
520 [(and (eq_attr "in_delay_slot" "yes")
521 (eq_attr "type" "!pstore,prget")) (nil) (nil)])
523 ;; Conditional branches with delay slots are available starting with SH2.
524 ;; If zero displacement conditional branches are fast, disable the delay
525 ;; slot if the branch jumps over only one 2-byte insn.
527 (and (eq_attr "type" "cbranch")
528 (match_test "TARGET_SH2")
529 (not (and (match_test "TARGET_ZDCBRANCH")
530 (match_test "sh_cbranch_distance (insn, 4) == 2"))))
531 [(eq_attr "cond_delay_slot" "yes") (nil) (nil)])
533 ;; -------------------------------------------------------------------------
534 ;; SImode signed integer comparisons
535 ;; -------------------------------------------------------------------------
537 ;; Patterns to generate the tst instruction which are usually formed by
539 ;; The canonical form here being used is (eq (and (op) (op)) 0).
540 ;; For some bit patterns, such as contiguous bits, we also must accept
541 ;; zero_extract forms. Single bit tests are also handled via zero_extract
542 ;; patterns in the 'bit field extract patterns' section. All variants
543 ;; are eventually converted to the 'tstsi_t' insn.
544 ;; As long as pseudos can be created (before RA), 'tstsi_t' will also accept
545 ;; constants that won't fit into 8 bits. After having captured the constant
546 ;; we can decide better whether/how to load it into a register and do other
547 ;; post-combine optimizations such as bypassing sign/zero extensions.
548 (define_insn_and_split "tstsi_t"
550 (eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "%z,r")
551 (match_operand:SI 1 "arith_or_int_operand" "K08,?r"))
554 && (can_create_pseudo_p () || arith_reg_operand (operands[1], SImode)
555 || satisfies_constraint_K08 (operands[1]))"
557 "TARGET_SH1 && can_create_pseudo_p () && CONST_INT_P (operands[1])
558 && !sh_in_recog_treg_set_expr ()"
561 gcc_assert (CONST_INT_P (operands[1]));
563 HOST_WIDE_INT op1val = INTVAL (operands[1]);
564 bool op0_dead_after_this =
565 sh_reg_dead_or_unused_after_insn (curr_insn, REGNO (operands[0]));
571 "tstsi_t: trying to optimize const_int 0x%08x\n",
574 /* See if we can convert a test with a reg and a constant into
575 something simpler, if the reg is known to be zero or sign
577 sh_extending_set_of_reg eop0 = sh_find_extending_set_of_reg (operands[0],
579 if (eop0.ext_code != UNKNOWN)
581 /* Adjust the constant, trying to eliminate bits that are not
582 contributing to the result. */
583 if (eop0.from_mode == QImode)
585 | (eop0.ext_code == SIGN_EXTEND && (op1val & 0xFFFFFF80)
587 else if (eop0.from_mode == HImode)
589 | (eop0.ext_code == SIGN_EXTEND && (op1val & 0xFFFF8000)
590 ? 0x8000 : 0)) & 0xFFFF;
593 fprintf (dump_file, "tstsi_t: using effective const_int: 0x%08x\n",
596 /* Try to bypass the sign/zero extension first if op0 dies after
598 if (op0_dead_after_this && eop0.can_use_as_unextended_reg ())
601 fprintf (dump_file, "tstsi_t: bypassing sign/zero extension\n");
603 operands[0] = eop0.use_as_unextended_reg (curr_insn);
605 else if ((eop0.from_mode == QImode && op1val == 0xFF)
606 || (eop0.from_mode == HImode && op1val == 0xFFFF))
609 fprintf (dump_file, "tstsi_t: converting to cmpeqsi_t\n");
610 emit_insn (gen_cmpeqsi_t (eop0.use_as_extended_reg (curr_insn),
614 else if (eop0.ext_code == SIGN_EXTEND
615 && ((eop0.from_mode == QImode && op1val == 0x80)
616 || (eop0.from_mode == HImode && op1val == 0x8000)))
619 fprintf (dump_file, "tstsi_t: converting to cmpgesi_t\n");
620 emit_insn (gen_cmpgesi_t (eop0.use_as_extended_reg (curr_insn),
624 else if (!CONST_OK_FOR_K08 (op1val))
627 fprintf (dump_file, "tstsi_t: converting const_int to signed "
630 /* If here we haven't done anything yet. Convert the constant
631 to a signed value to reduce the constant pool size. */
632 operands[0] = eop0.use_as_extended_reg (curr_insn);
634 if (eop0.from_mode == QImode)
635 op1val |= (op1val & 0x80) ? 0xFFFFFFFFFFFFFF00LL : 0;
636 else if (eop0.from_mode == HImode)
637 op1val |= (op1val & 0x8000) ? 0xFFFFFFFFFFFF0000LL : 0;
640 operands[0] = eop0.use_as_extended_reg (curr_insn);
645 fprintf (dump_file, "tstsi_t: using const_int 0x%08x\n",
648 /* Try to fit the constant into 8 bits by shuffling the value in the
650 Doing that usually results in smaller code as the constants in the
651 pools are avoided (32 bit constant = load + constant = 6 bytes).
652 However, if the constant load (LS insn) can be hoisted insn dependencies
653 can be avoided and chances for parallel execution increase. The common
659 FIXME: For now we do that only when optimizing for size until there is
662 FIXME: If there are multiple tst insns in the block with the same
663 constant, avoid the #imm variant to avoid R0 loads. Use the 'tst Rn,Rm'
664 variant instead and load the constant into a reg. For that we'd need
665 to do some analysis. */
667 if (CONST_OK_FOR_K08 (op1val))
671 else if ((op1val & 0xFFFF) == 0
672 && CONST_OK_FOR_K08 (op1val >> 16) && optimize_size)
674 /* Use a swap.w insn to do a shift + reg copy (to R0) in one insn. */
675 op1val = op1val >> 16;
676 rtx r = gen_reg_rtx (SImode);
677 emit_insn (gen_rotlsi3_16 (r, operands[0]));
680 else if ((op1val & 0xFF) == 0
681 && CONST_OK_FOR_K08 (op1val >> 8) && optimize_size)
683 /* Use a swap.b insn to do a shift + reg copy (to R0) in one insn. */
684 op1val = op1val >> 8;
685 rtx r = gen_reg_rtx (SImode);
686 emit_insn (gen_swapbsi2 (r, operands[0]));
689 else if ((op1val & 3) == 0
690 && CONST_OK_FOR_K08 (op1val >> 2) && optimize_size)
692 op1val = op1val >> 2;
693 rtx r = gen_reg_rtx (SImode);
694 emit_insn (gen_lshrsi3_k (r, operands[0], GEN_INT (2)));
697 else if ((op1val & 1) == 0
698 && CONST_OK_FOR_K08 (op1val >> 1) && optimize_size)
700 op1val = op1val >> 1;
701 rtx r = gen_reg_rtx (SImode);
702 emit_insn (gen_shlr (r, operands[0]));
706 operands[1] = GEN_INT (op1val);
708 if (!satisfies_constraint_K08 (operands[1]))
709 operands[1] = force_reg (SImode, operands[1]);
711 emit_insn (gen_tstsi_t (operands[0], operands[1]));
714 [(set_attr "type" "mt_group")])
716 ;; This pattern is used by combine when testing QI/HImode subregs with a
717 ;; negative constant. Ignore high bits by masking them out in the constant.
718 (define_insn_and_split "*tst<mode>_t"
721 (and:QIHI (match_operand:QIHI 0 "arith_reg_operand")
722 (match_operand 1 "const_int_operand")) 0)
724 "TARGET_SH1 && can_create_pseudo_p ()"
728 (eq:SI (and:SI (match_dup 0) (match_dup 1)) (const_int 0)))]
730 operands[0] = simplify_gen_subreg (SImode, operands[0], <MODE>mode, 0);
731 operands[1] = GEN_INT (INTVAL (operands[1])
732 & (<MODE>mode == HImode ? 0xFFFF : 0xFF));
735 ;; This pattern might be risky because it also tests the upper bits and not
736 ;; only the subreg. We have to check whether the operands have been sign
737 ;; or zero extended. In the worst case, a zero extension has to be inserted
738 ;; to mask out the unwanted bits.
739 (define_insn_and_split "*tst<mode>_t_subregs"
743 (and:SI (match_operand:SI 0 "arith_reg_operand")
744 (match_operand:SI 1 "arith_reg_operand")) <lowpart_le>)
746 "TARGET_SH1 && TARGET_LITTLE_ENDIAN && can_create_pseudo_p ()"
748 "&& !sh_in_recog_treg_set_expr ()"
751 sh_split_tst_subregs (curr_insn, <MODE>mode, <lowpart_le>, operands);
755 (define_insn_and_split "*tst<mode>_t_subregs"
759 (and:SI (match_operand:SI 0 "arith_reg_operand")
760 (match_operand:SI 1 "arith_reg_operand")) <lowpart_be>)
762 "TARGET_SH1 && TARGET_BIG_ENDIAN && can_create_pseudo_p ()"
764 "&& !sh_in_recog_treg_set_expr ()"
767 sh_split_tst_subregs (curr_insn, <MODE>mode, <lowpart_be>, operands);
771 ;; Extract contiguous bits and compare them against zero.
772 ;; Notice that this will not be used for single bits. Special single bit
773 ;; extraction patterns are in the 'bit field extract patterns' section.
774 (define_insn_and_split "*tst<mode>_t_zero_extract"
776 (eq:SI (zero_extract:SI (match_operand:QIHISI 0 "arith_reg_operand")
777 (match_operand 1 "const_int_operand")
778 (match_operand 2 "const_int_operand"))
780 "TARGET_SH1 && can_create_pseudo_p ()"
784 (eq:SI (and:SI (match_dup 0) (match_dup 1)) (const_int 0)))]
786 operands[1] = GEN_INT (ZERO_EXTRACT_ANDMASK (operands[1], operands[2]));
787 if (GET_MODE (operands[0]) != SImode)
788 operands[0] = simplify_gen_subreg (SImode, operands[0], <MODE>mode, 0);
791 ;; Convert '(reg << shift) & mask' into 'reg & (mask >> shift)'.
792 ;; The shifted-out bits in the mask will always be zero, since the
793 ;; shifted-in bits in the reg will also be always zero.
794 (define_insn_and_split "*tstsi_t_shift_mask"
796 (eq:SI (and:SI (ashift:SI (match_operand:SI 0 "arith_reg_operand")
797 (match_operand 1 "const_int_operand"))
798 (match_operand 2 "const_int_operand"))
800 "TARGET_SH1 && can_create_pseudo_p ()"
804 (eq:SI (and:SI (match_dup 0) (match_dup 2)) (const_int 0)))]
806 operands[2] = GEN_INT (INTVAL (operands[2]) >> INTVAL (operands[1]));
809 (define_insn "cmpeqsi_t"
811 (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
812 (match_operand:SI 1 "arith_operand" "N,rI08,r")))]
818 [(set_attr "type" "mt_group")])
820 ;; Sometimes combine fails to form the (eq (and (op) (op)) 0) tst insn.
821 ;; Try to fix that in the split1 pass by looking for the previous set
822 ;; of the tested op. Also see if there is a preceeding sign/zero
823 ;; extension that can be avoided.
826 (eq:SI (match_operand:SI 0 "arith_reg_operand") (const_int 0)))]
827 "TARGET_SH1 && can_create_pseudo_p () && optimize
828 && !sh_in_recog_treg_set_expr ()"
829 [(set (reg:SI T_REG) (eq:SI (match_dup 0) (const_int 0)))]
832 fprintf (dump_file, "cmpeqsi_t: trying to optimize const_int 0\n");
834 /* If the tested reg is not dead after this insn, it's probably used by
835 something else after the comparison. It's probably better to leave
837 if (find_regno_note (curr_insn, REG_DEAD, REGNO (operands[0])) == NULL_RTX)
840 /* FIXME: Maybe also search the predecessor basic blocks to catch
842 set_of_reg op = sh_find_set_of_reg (operands[0], curr_insn,
843 prev_nonnote_insn_bb);
845 if (op.set_src != NULL && GET_CODE (op.set_src) == AND
846 && !sh_insn_operands_modified_between_p (op.insn, op.insn, curr_insn))
849 fprintf (dump_file, "cmpeqsi_t: found preceeding and in insn %d\n",
852 if (!(arith_reg_operand (XEXP (op.set_src, 0), SImode)
853 && (arith_reg_operand (XEXP (op.set_src, 1), SImode)
854 || CONST_INT_P (XEXP (op.set_src, 1)))))
857 /* Assume that the operands of the andsi insn are compatible with the
858 operands of the tstsi_t insn, which is generally the case. */
860 fprintf (dump_file, "cmpeqsi_t: replacing with tstsi_t\n");
861 emit_insn (gen_tstsi_t (XEXP (op.set_src, 0), XEXP (op.set_src, 1)));
865 /* Converting HImode into tests against 0xFFFF tends to increase the code
866 size, as it will create constant pool entries. Disable it for now. */
867 const bool enable_himode = false;
869 /* FIXME: try to keep the (eq (reg) (const_int 0)). Even if the zero
870 extended reg is used after this insn, if we know that _before_ the zero
871 extension the value was loaded via sign extending mem load, we can just
872 use the value of the mem load directly. */
873 sh_extending_set_of_reg eop = sh_find_extending_set_of_reg (operands[0],
876 if (eop.ext_code != UNKNOWN
877 && (eop.from_mode == QImode || (eop.from_mode == HImode && enable_himode))
878 && eop.can_use_as_unextended_reg ()
879 && !reg_used_between_p (operands[0], eop.insn, curr_insn))
881 /* Bypass the sign/zero extension and test against the bit mask, but
882 only if it's the only use of the sign/zero extracted value.
883 Otherwise we'd be introducing new constants in the pool. */
885 fprintf (dump_file, "cmpeqsi_t: bypassing sign/zero extension in "
886 "insn %d and using tstsi_t\n", INSN_UID (op.insn));
888 emit_insn (gen_tstsi_t (
889 eop.use_as_unextended_reg (curr_insn),
890 GEN_INT (eop.from_mode == QImode ? 0xFF : 0xFFFF)));
895 fprintf (dump_file, "cmpeqsi_t: nothing optimized\n");
899 (define_insn "cmpgtsi_t"
901 (gt:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
902 (match_operand:SI 1 "arith_reg_or_0_operand" "N,r")))]
907 [(set_attr "type" "mt_group")])
909 (define_insn "cmpgesi_t"
911 (ge:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
912 (match_operand:SI 1 "arith_reg_or_0_operand" "N,r")))]
917 [(set_attr "type" "mt_group")])
919 ;; Recombine a cmp/pz followed by a nott into a shll.
920 ;; On non-SH2A recombine a cmp/pz followed by a movrt into shll-movt.
921 ;; On SH2A cmp/pz-movrt is slightly better, as it does not mutate the input.
924 (ge:SI (match_operand:SI 0 "arith_reg_operand") (const_int 0)))]
926 "TARGET_SH1 && can_create_pseudo_p () && optimize
927 && !sh_in_recog_treg_set_expr ()"
931 fprintf (dump_file, "cmpgesi_t: trying to optimize for const_int 0\n");
933 rtx_insn* i = next_nonnote_insn_bb (curr_insn);
937 fprintf (dump_file, "cmpgesi_t: following insn is \n");
938 print_rtl_single (dump_file, i);
939 fprintf (dump_file, "\n");
942 if (sh_is_nott_insn (i))
946 "cmpgesi_t: replacing (cmp/pz, nott) with (shll)\n");
947 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[0]));
948 set_insn_deleted (i);
952 /* On non-SH2A negc is used as movrt replacement, which sets T = 1.
953 Thus we can remove it only if T is marked as dead afterwards. */
954 if (rtx dest_reg = !TARGET_SH2A
955 && sh_reg_dead_or_unused_after_insn (i, T_REG)
956 ? sh_movrt_set_dest (i) : NULL)
960 "cmpgesi_t: replacing (cmp/pz, movrt) with (shll, movt)\n");
961 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[0]));
962 add_reg_note (emit_insn (gen_movt (dest_reg, get_t_reg_rtx ())),
963 REG_DEAD, get_t_reg_rtx ());
964 set_insn_deleted (i);
969 fprintf (dump_file, "cmpgesi_t: nothing optimized\n");
974 ;; FIXME: This is actually wrong. There is no way to literally move a
975 ;; general reg to t reg. Luckily, it seems that this pattern will be only
976 ;; used when the general reg is known be either '0' or '1' during combine.
977 ;; What we actually need is reg != 0 -> T, but we have only reg == 0 -> T.
978 ;; Due to interactions with other patterns, combine fails to pick the latter
979 ;; and invert the dependent logic.
980 (define_insn "*negtstsi"
981 [(set (reg:SI T_REG) (match_operand:SI 0 "arith_reg_operand" "r"))]
982 "TARGET_SH1 && !sh_in_recog_treg_set_expr ()"
984 [(set_attr "type" "mt_group")])
986 ;; Some integer sign comparison patterns can be realized with the div0s insn.
987 ;; div0s Rm,Rn T = (Rm >> 31) ^ (Rn >> 31)
989 ;; The 'cmp_div0s' pattern is our canonical form, into which all the other
990 ;; variations are converted. The negative forms will split into a trailing
991 ;; nott sequence, which will be eliminated either by the
992 ;; 'any_treg_expr_to_reg' pattern, or by the 'sh_treg_combine' pass.
993 (define_insn "cmp_div0s"
995 (lshiftrt:SI (xor:SI (match_operand:SI 0 "arith_reg_operand" "%r")
996 (match_operand:SI 1 "arith_reg_operand" "r"))
1000 [(set_attr "type" "arith")])
1002 (define_insn_and_split "*cmp_div0s_1"
1003 [(set (reg:SI T_REG)
1004 (xor:SI (ge:SI (match_operand:SI 0 "arith_reg_operand")
1006 (ge:SI (match_operand:SI 1 "arith_reg_operand")
1008 "TARGET_SH1 && can_create_pseudo_p ()"
1011 [(set (reg:SI T_REG)
1012 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))])
1014 (define_insn_and_split "*cmp_div0s_2"
1015 [(set (reg:SI T_REG)
1016 (eq:SI (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand")
1018 (ge:SI (match_operand:SI 1 "arith_reg_operand")
1020 "TARGET_SH1 && can_create_pseudo_p ()"
1023 [(set (reg:SI T_REG)
1024 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))])
1026 (define_insn_and_split "*cmp_div0s_3"
1027 [(set (reg:SI T_REG)
1028 (eq:SI (ge:SI (match_operand:SI 0 "arith_reg_operand")
1030 (ge:SI (match_operand:SI 1 "arith_reg_operand")
1032 "TARGET_SH1 && can_create_pseudo_p ()"
1035 [(set (reg:SI T_REG)
1036 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))
1037 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1039 (define_insn_and_split "*cmp_div0s_4"
1040 [(set (reg:SI T_REG)
1041 (ge:SI (xor:SI (match_operand:SI 0 "arith_reg_operand")
1042 (match_operand:SI 1 "arith_reg_operand"))
1044 "TARGET_SH1 && can_create_pseudo_p ()"
1047 [(set (reg:SI T_REG)
1048 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))
1049 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1051 (define_insn_and_split "*cmp_div0s_5"
1052 [(set (reg:SI T_REG)
1053 (xor:SI (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand")
1055 (ge:SI (match_operand:SI 1 "arith_reg_operand")
1057 "TARGET_SH1 && can_create_pseudo_p ()"
1060 [(set (reg:SI T_REG)
1061 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))
1062 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1064 (define_insn_and_split "*cmp_div0s_6"
1065 [(set (reg:SI T_REG)
1066 (eq:SI (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand")
1068 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
1070 "TARGET_SH1 && can_create_pseudo_p ()"
1073 [(set (reg:SI T_REG)
1074 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))
1075 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1077 ;; In some cases, it might be shorter to get a tested bit into bit 31 and
1078 ;; use div0s. Otherwise it's usually better to just leave the xor and tst
1079 ;; sequence. The only thing we can try to do here is avoiding the large
1081 (define_insn_and_split "*cmp_div0s_7"
1082 [(set (reg:SI T_REG)
1083 (zero_extract:SI (xor:SI (match_operand:SI 0 "arith_reg_operand")
1084 (match_operand:SI 1 "arith_reg_operand"))
1086 (match_operand 2 "const_int_operand")))]
1087 "TARGET_SH1 && can_create_pseudo_p ()
1088 && (INTVAL (operands[2]) == 7 || INTVAL (operands[2]) == 15
1089 || INTVAL (operands[2]) == 23 || INTVAL (operands[2]) == 29
1090 || INTVAL (operands[2]) == 30 || INTVAL (operands[2]) == 31)"
1095 const int bitpos = INTVAL (operands[2]);
1097 rtx op0 = gen_reg_rtx (SImode);
1098 rtx op1 = gen_reg_rtx (SImode);
1100 if (bitpos == 23 || bitpos == 30 || bitpos == 29)
1102 emit_insn (gen_ashlsi3 (op0, operands[0], GEN_INT (31 - bitpos)));
1103 emit_insn (gen_ashlsi3 (op1, operands[1], GEN_INT (31 - bitpos)));
1105 else if (bitpos == 15)
1107 emit_insn (gen_extendhisi2 (op0, gen_lowpart (HImode, operands[0])));
1108 emit_insn (gen_extendhisi2 (op1, gen_lowpart (HImode, operands[1])));
1110 else if (bitpos == 7)
1112 emit_insn (gen_extendqisi2 (op0, gen_lowpart (QImode, operands[0])));
1113 emit_insn (gen_extendqisi2 (op1, gen_lowpart (QImode, operands[1])));
1115 else if (bitpos == 31)
1123 emit_insn (gen_cmp_div0s (op0, op1));
1127 ;; For bits 0..7 using a xor and tst #imm,r0 sequence seems to be better.
1128 ;; Thus allow the following patterns only for higher bit positions where
1129 ;; we it's more likely to save the large tst constant.
1130 (define_insn_and_split "*cmp_div0s_8"
1131 [(set (reg:SI T_REG)
1132 (eq:SI (zero_extract:SI (match_operand:SI 0 "arith_reg_operand")
1134 (match_operand 2 "const_int_operand"))
1135 (zero_extract:SI (match_operand:SI 1 "arith_reg_operand")
1138 "TARGET_SH1 && can_create_pseudo_p ()
1139 && (INTVAL (operands[2]) == 15
1140 || INTVAL (operands[2]) == 23 || INTVAL (operands[2]) == 29
1141 || INTVAL (operands[2]) == 30 || INTVAL (operands[2]) == 31)"
1144 [(set (reg:SI T_REG)
1145 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
1146 (const_int 1) (match_dup 2)))
1147 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1149 (define_insn_and_split "*cmp_div0s_9"
1150 [(set (reg:SI T_REG)
1151 (zero_extract:SI (xor:SI (xor:SI (match_operand:SI 0 "arith_reg_operand")
1152 (match_operand:SI 1 "arith_reg_operand"))
1153 (match_operand 2 "const_int_operand"))
1155 (match_operand 3 "const_int_operand")))]
1156 "TARGET_SH1 && can_create_pseudo_p ()
1157 && (INTVAL (operands[2]) & 0xFFFFFFFF) == (1U << INTVAL (operands[3]))
1158 && (INTVAL (operands[3]) == 15
1159 || INTVAL (operands[3]) == 23 || INTVAL (operands[3]) == 29
1160 || INTVAL (operands[3]) == 30 || INTVAL (operands[3]) == 31)"
1163 [(set (reg:SI T_REG)
1164 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
1165 (const_int 1) (match_dup 3)))
1166 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1168 ;; -------------------------------------------------------------------------
1169 ;; SImode compare and branch
1170 ;; -------------------------------------------------------------------------
1172 (define_expand "cbranchsi4"
1174 (if_then_else (match_operator 0 "comparison_operator"
1175 [(match_operand:SI 1 "arith_operand" "")
1176 (match_operand:SI 2 "arith_operand" "")])
1177 (label_ref (match_operand 3 "" ""))
1179 (clobber (reg:SI T_REG))]
1180 "can_create_pseudo_p ()"
1182 expand_cbranchsi4 (operands, LAST_AND_UNUSED_RTX_CODE, -1);
1186 ;; Combine patterns to invert compare and branch operations for which we
1187 ;; don't have actual comparison insns. These patterns are used in cases
1188 ;; which appear after the initial cbranchsi expansion, which also does
1189 ;; some condition inversion.
1192 (if_then_else (ne (match_operand:SI 0 "arith_reg_operand" "")
1193 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
1194 (label_ref (match_operand 2))
1196 (clobber (reg:SI T_REG))]
1198 [(set (reg:SI T_REG) (eq:SI (match_dup 0) (match_dup 1)))
1199 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1200 (label_ref (match_dup 2))
1203 ;; FIXME: These don't seem to have any effect on the generated cbranch code
1204 ;; anymore, but only on some register allocation choices.
1207 (if_then_else (le (match_operand:SI 0 "arith_reg_operand" "")
1208 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
1209 (label_ref (match_operand 2))
1211 (clobber (reg:SI T_REG))]
1213 [(set (reg:SI T_REG) (gt:SI (match_dup 0) (match_dup 1)))
1214 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1215 (label_ref (match_dup 2))
1220 (if_then_else (lt (match_operand:SI 0 "arith_reg_operand" "")
1221 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
1222 (label_ref (match_operand 2))
1224 (clobber (reg:SI T_REG))]
1226 [(set (reg:SI T_REG) (ge:SI (match_dup 0) (match_dup 1)))
1227 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1228 (label_ref (match_dup 2))
1233 (if_then_else (leu (match_operand:SI 0 "arith_reg_operand" "")
1234 (match_operand:SI 1 "arith_reg_operand" ""))
1235 (label_ref (match_operand 2))
1237 (clobber (reg:SI T_REG))]
1239 [(set (reg:SI T_REG) (gtu:SI (match_dup 0) (match_dup 1)))
1240 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1241 (label_ref (match_dup 2))
1246 (if_then_else (ltu (match_operand:SI 0 "arith_reg_operand" "")
1247 (match_operand:SI 1 "arith_reg_operand" ""))
1248 (label_ref (match_operand 2))
1250 (clobber (reg:SI T_REG))]
1252 [(set (reg:SI T_REG) (geu:SI (match_dup 0) (match_dup 1)))
1253 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1254 (label_ref (match_dup 2))
1257 ;; -------------------------------------------------------------------------
1258 ;; SImode unsigned integer comparisons
1259 ;; -------------------------------------------------------------------------
1261 ;; Usually comparisons of 'unsigned int >= 0' are optimized away completely.
1262 ;; However, especially when optimizations are off (e.g. -O0) such comparisons
1263 ;; might remain and we have to handle them. If the '>= 0' case wasn't
1264 ;; handled here, something else would just load a '0' into the second operand
1265 ;; and do the comparison. We can do slightly better by just setting the
1267 (define_insn_and_split "cmpgeusi_t"
1268 [(set (reg:SI T_REG)
1269 (geu:SI (match_operand:SI 0 "arith_reg_operand" "r")
1270 (match_operand:SI 1 "arith_reg_or_0_operand" "r")))]
1273 "&& satisfies_constraint_Z (operands[1])"
1274 [(set (reg:SI T_REG) (const_int 1))]
1276 [(set_attr "type" "mt_group")])
1278 (define_insn "cmpgtusi_t"
1279 [(set (reg:SI T_REG)
1280 (gtu:SI (match_operand:SI 0 "arith_reg_operand" "r")
1281 (match_operand:SI 1 "arith_reg_operand" "r")))]
1284 [(set_attr "type" "mt_group")])
1286 ;; -------------------------------------------------------------------------
1287 ;; DImode compare and branch
1288 ;; -------------------------------------------------------------------------
1290 ;; arith3 patterns don't work well with the sh4-300 branch prediction mechanism.
1291 ;; Therefore, we aim to have a set of three branches that go straight to the
1292 ;; destination, i.e. only one of them is taken at any one time.
1293 ;; This mechanism should also be slightly better for the sh4-200.
1295 (define_expand "cbranchdi4"
1297 (if_then_else (match_operator 0 "comparison_operator"
1298 [(match_operand:DI 1 "arith_operand")
1299 (match_operand:DI 2 "arith_operand")])
1300 (label_ref (match_operand 3))
1302 (clobber (reg:SI T_REG))]
1303 "TARGET_SH2 && can_create_pseudo_p ()"
1305 if (!expand_cbranchdi4 (operands, GET_CODE (operands[0])))
1310 ;; -------------------------------------------------------------------------
1311 ;; DImode signed integer comparisons
1312 ;; -------------------------------------------------------------------------
1315 [(set (reg:SI T_REG)
1316 (eq:SI (and:DI (match_operand:DI 0 "arith_reg_operand" "r")
1317 (match_operand:DI 1 "arith_operand" "r"))
1321 return output_branchy_insn (EQ, "tst\t%S1,%S0;bf\t%l9;tst\t%R1,%R0",
1324 [(set_attr "length" "6")
1325 (set_attr "type" "arith3b")])
1327 (define_insn "cmpeqdi_t"
1328 [(set (reg:SI T_REG)
1329 (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
1330 (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
1333 static const char* alt[] =
1340 "cmp/eq %S1,%S0" "\n"
1342 " cmp/eq %R1,%R0" "\n"
1345 return alt[which_alternative];
1347 [(set_attr "length" "6")
1348 (set_attr "type" "arith3b")])
1351 [(set (reg:SI T_REG)
1352 (eq:SI (match_operand:DI 0 "arith_reg_operand" "")
1353 (match_operand:DI 1 "arith_reg_or_0_operand" "")))]
1354 ;; If we applied this split when not optimizing, it would only be
1355 ;; applied during the machine-dependent reorg, when no new basic blocks
1357 "TARGET_SH1 && reload_completed && optimize"
1358 [(set (reg:SI T_REG) (eq:SI (match_dup 2) (match_dup 3)))
1359 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1360 (label_ref (match_dup 6))
1362 (set (reg:SI T_REG) (eq:SI (match_dup 4) (match_dup 5)))
1365 operands[2] = gen_highpart (SImode, operands[0]);
1366 operands[3] = operands[1] == const0_rtx
1368 : gen_highpart (SImode, operands[1]);
1369 operands[4] = gen_lowpart (SImode, operands[0]);
1370 operands[5] = gen_lowpart (SImode, operands[1]);
1371 operands[6] = gen_label_rtx ();
1374 (define_insn "cmpgtdi_t"
1375 [(set (reg:SI T_REG)
1376 (gt:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
1377 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
1380 static const char* alt[] =
1382 "cmp/eq %S1,%S0" "\n"
1384 " cmp/gt %S1,%S0" "\n"
1385 " cmp/hi %R1,%R0" "\n"
1391 " cmp/hi %S0,%R0" "\n"
1394 return alt[which_alternative];
1396 [(set_attr "length" "8")
1397 (set_attr "type" "arith3")])
1399 (define_insn "cmpgedi_t"
1400 [(set (reg:SI T_REG)
1401 (ge:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
1402 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
1405 static const char* alt[] =
1407 "cmp/eq %S1,%S0" "\n"
1409 " cmp/ge %S1,%S0" "\n"
1410 " cmp/hs %R1,%R0" "\n"
1415 return alt[which_alternative];
1417 [(set_attr "length" "8,2")
1418 (set_attr "type" "arith3,mt_group")])
1420 ;; -------------------------------------------------------------------------
1421 ;; DImode unsigned integer comparisons
1422 ;; -------------------------------------------------------------------------
1424 (define_insn "cmpgeudi_t"
1425 [(set (reg:SI T_REG)
1426 (geu:SI (match_operand:DI 0 "arith_reg_operand" "r")
1427 (match_operand:DI 1 "arith_reg_operand" "r")))]
1430 return "cmp/eq %S1,%S0" "\n"
1432 " cmp/hs %S1,%S0" "\n"
1433 " cmp/hs %R1,%R0" "\n"
1436 [(set_attr "length" "8")
1437 (set_attr "type" "arith3")])
1439 (define_insn "cmpgtudi_t"
1440 [(set (reg:SI T_REG)
1441 (gtu:SI (match_operand:DI 0 "arith_reg_operand" "r")
1442 (match_operand:DI 1 "arith_reg_operand" "r")))]
1445 return "cmp/eq %S1,%S0" "\n"
1447 " cmp/hi %S1,%S0" "\n"
1448 " cmp/hi %R1,%R0" "\n"
1451 [(set_attr "length" "8")
1452 (set_attr "type" "arith3")])
1454 ;; -------------------------------------------------------------------------
1455 ;; Conditional move instructions
1456 ;; -------------------------------------------------------------------------
1458 (define_insn "*movsicc_t_false"
1459 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
1460 (if_then_else (eq (reg:SI T_REG) (const_int 0))
1461 (match_operand:SI 1 "general_movsrc_operand" "r,I08")
1462 (match_operand:SI 2 "arith_reg_operand" "0,0")))]
1463 "TARGET_PRETEND_CMOVE
1464 && (arith_reg_operand (operands[1], SImode)
1465 || (immediate_operand (operands[1], SImode)
1466 && satisfies_constraint_I08 (operands[1])))"
1472 [(set_attr "type" "mt_group,arith") ;; poor approximation
1473 (set_attr "length" "4")])
1475 (define_insn "*movsicc_t_true"
1476 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
1477 (if_then_else (ne (reg:SI T_REG) (const_int 0))
1478 (match_operand:SI 1 "general_movsrc_operand" "r,I08")
1479 (match_operand:SI 2 "arith_reg_operand" "0,0")))]
1480 "TARGET_PRETEND_CMOVE
1481 && (arith_reg_operand (operands[1], SImode)
1482 || (immediate_operand (operands[1], SImode)
1483 && satisfies_constraint_I08 (operands[1])))"
1489 [(set_attr "type" "mt_group,arith") ;; poor approximation
1490 (set_attr "length" "4")])
1492 (define_expand "movsicc"
1493 [(set (match_operand:SI 0 "arith_reg_dest" "")
1494 (if_then_else:SI (match_operand 1 "comparison_operator" "")
1495 (match_operand:SI 2 "arith_reg_or_0_operand" "")
1496 (match_operand:SI 3 "arith_reg_operand" "")))]
1497 "TARGET_PRETEND_CMOVE"
1499 rtx_code code = GET_CODE (operands[1]);
1500 rtx_code new_code = code;
1501 rtx op0 = XEXP (operands[1], 0);
1502 rtx op1 = XEXP (operands[1], 1);
1504 if (! currently_expanding_to_rtl)
1509 case LT: case LE: case LEU: case LTU:
1510 if (GET_MODE_CLASS (GET_MODE (op0)) != MODE_INT)
1514 new_code = reverse_condition (code);
1516 case EQ: case GT: case GE: case GEU: case GTU:
1522 sh_emit_scc_to_t (new_code, op0, op1);
1523 operands[1] = gen_rtx_fmt_ee (new_code == code ? NE : EQ, VOIDmode,
1524 gen_rtx_REG (SImode, T_REG), const0_rtx);
1527 ;; -------------------------------------------------------------------------
1528 ;; Addition instructions
1529 ;; -------------------------------------------------------------------------
1531 (define_insn_and_split "adddi3"
1532 [(set (match_operand:DI 0 "arith_reg_dest")
1533 (plus:DI (match_operand:DI 1 "arith_reg_operand")
1534 (match_operand:DI 2 "arith_reg_operand")))
1535 (clobber (reg:SI T_REG))]
1538 "&& can_create_pseudo_p ()"
1541 emit_insn (gen_clrt ());
1542 emit_insn (gen_addc (gen_lowpart (SImode, operands[0]),
1543 gen_lowpart (SImode, operands[1]),
1544 gen_lowpart (SImode, operands[2])));
1545 emit_insn (gen_addc (gen_highpart (SImode, operands[0]),
1546 gen_highpart (SImode, operands[1]),
1547 gen_highpart (SImode, operands[2])));
1552 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1553 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0")
1554 (match_operand:SI 2 "arith_reg_operand" "r"))
1557 (ltu:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
1560 [(set_attr "type" "arith")])
1562 ;; A simplified version of the addc insn, where the exact value of the
1563 ;; T bit doesn't matter. This is easier for combine to pick up.
1564 ;; We allow a reg or 0 for one of the operands in order to be able to
1565 ;; do 'reg + T' sequences.
1566 (define_insn_and_split "*addc"
1567 [(set (match_operand:SI 0 "arith_reg_dest")
1568 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand")
1569 (match_operand:SI 2 "arith_reg_or_0_operand"))
1570 (match_operand 3 "treg_set_expr")))
1571 (clobber (reg:SI T_REG))]
1572 "TARGET_SH1 && can_create_pseudo_p ()"
1577 sh_treg_insns ti = sh_split_treg_set_expr (operands[3], curr_insn);
1578 if (ti.has_trailing_nott ())
1580 if (operands[2] == const0_rtx)
1582 /* op1 + 0 + (1 - T) = op1 + 1 - T = op1 - (-1) - T */
1583 remove_insn (ti.trailing_nott ());
1584 emit_insn (gen_subc (operands[0], operands[1],
1585 force_reg (SImode, GEN_INT (-1))));
1588 else if (!TARGET_SH2A)
1590 /* op1 + op2 + (1 - T) = op1 - (0 - op2 - 1) - T = op1 - ~op2 - T
1591 On SH2A keep the nott insn, because nott-addc sequence doesn't
1592 mutate the inputs. */
1593 remove_insn (ti.trailing_nott ());
1594 rtx tmp = gen_reg_rtx (SImode);
1595 emit_insn (gen_one_cmplsi2 (tmp, operands[2]));
1596 emit_insn (gen_subc (operands[0], operands[1], tmp));
1601 emit_insn (gen_addc (operands[0], operands[1],
1602 force_reg (SImode, operands[2])));
1606 (define_insn_and_split "*addc"
1607 [(set (match_operand:SI 0 "arith_reg_dest")
1608 (plus:SI (plus:SI (match_operand 1 "treg_set_expr")
1609 (match_operand:SI 2 "arith_reg_operand"))
1610 (match_operand:SI 3 "arith_reg_operand")))
1611 (clobber (reg:SI T_REG))]
1612 "TARGET_SH1 && can_create_pseudo_p ()"
1615 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 3))
1617 (clobber (reg:SI T_REG))])])
1619 (define_insn_and_split "*addc"
1620 [(set (match_operand:SI 0 "arith_reg_dest")
1621 (plus:SI (match_operand 1 "treg_set_expr")
1622 (plus:SI (match_operand:SI 2 "arith_reg_operand")
1623 (match_operand:SI 3 "arith_reg_operand"))))
1624 (clobber (reg:SI T_REG))]
1625 "TARGET_SH1 && can_create_pseudo_p ()"
1628 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 3))
1630 (clobber (reg:SI T_REG))])])
1632 ;; Sometimes combine will try to do 'reg + (0-reg) + 1' if the *addc pattern
1633 ;; matched. Split this up into a simple sub add sequence, as this will save
1634 ;; us one sett insn.
1635 (define_insn_and_split "*minus_plus_one"
1636 [(set (match_operand:SI 0 "arith_reg_dest" "")
1637 (plus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "")
1638 (match_operand:SI 2 "arith_reg_operand" ""))
1643 [(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))
1644 (set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))])
1647 ;; The tree optimiziers canonicalize
1652 ;; On SH2A an add-bclr sequence will be used to handle this.
1653 ;; On non-SH2A re-emit the add-and sequence to improve register utilization.
1654 (define_insn_and_split "*round_int_even"
1655 [(set (match_operand:SI 0 "arith_reg_dest")
1656 (and:SI (plus:SI (match_operand:SI 1 "arith_reg_operand")
1659 "TARGET_SH1 && !TARGET_SH2A && can_create_pseudo_p ()
1660 && !reg_overlap_mentioned_p (operands[0], operands[1])"
1663 [(set (match_dup 0) (const_int -2))
1664 (set (match_dup 2) (plus:SI (match_dup 1) (const_int 1)))
1665 (set (match_dup 0) (and:SI (match_dup 0) (match_dup 2)))]
1667 operands[2] = gen_reg_rtx (SImode);
1670 ;; If the *round_int_even pattern is combined with another plus,
1671 ;; convert it into an addc pattern to emit an shlr-addc sequence.
1672 ;; This split is taken by combine on non-SH2A and SH2A.
1674 [(set (match_operand:SI 0 "arith_reg_dest")
1675 (plus:SI (and:SI (plus:SI (match_operand:SI 1 "arith_reg_operand")
1678 (match_operand:SI 2 "arith_reg_operand")))]
1679 "TARGET_SH1 && can_create_pseudo_p ()"
1680 [(parallel [(set (match_dup 0)
1681 (plus:SI (plus:SI (match_dup 1) (match_dup 2))
1682 (and:SI (match_dup 1) (const_int 1))))
1683 (clobber (reg:SI T_REG))])])
1685 ;; Split 'reg + T' into 'reg + 0 + T' to utilize the addc insn.
1686 ;; If the 0 constant can be CSE-ed, this becomes a one instruction
1687 ;; operation, as opposed to sequences such as
1691 ;; Even if the constant is not CSE-ed, a sequence such as
1694 ;; can be scheduled much better since the load of the constant can be
1695 ;; done earlier, before any comparison insns that store the result in
1697 ;; However, avoid things like 'reg + 1', which would expand into a
1698 ;; 3 insn sequence, instead of add #imm8.
1699 (define_insn_and_split "*addc_t_r"
1700 [(set (match_operand:SI 0 "arith_reg_dest")
1701 (plus:SI (match_operand 1 "treg_set_expr_not_const01")
1702 (match_operand:SI 2 "arith_reg_operand")))
1703 (clobber (reg:SI T_REG))]
1704 "TARGET_SH1 && can_create_pseudo_p ()"
1707 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (const_int 0))
1709 (clobber (reg:SI T_REG))])])
1711 (define_insn_and_split "*addc_r_t"
1712 [(set (match_operand:SI 0 "arith_reg_dest")
1713 (plus:SI (match_operand:SI 1 "arith_reg_operand")
1714 (match_operand 2 "treg_set_expr_not_const01")))
1715 (clobber (reg:SI T_REG))]
1716 "TARGET_SH1 && can_create_pseudo_p ()"
1719 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 1) (const_int 0))
1721 (clobber (reg:SI T_REG))])])
1723 ;; Convert '2 * reg + T' into 'reg + reg + T'.
1724 (define_insn_and_split "*addc_2r_t"
1725 [(set (match_operand:SI 0 "arith_reg_dest")
1726 (plus:SI (match_operand 1 "treg_set_expr")
1727 (ashift:SI (match_operand:SI 2 "arith_reg_operand")
1729 (clobber (reg:SI T_REG))]
1730 "TARGET_SH1 && can_create_pseudo_p ()"
1733 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 2))
1735 (clobber (reg:SI T_REG))])])
1737 (define_insn_and_split "*addc_2r_t"
1738 [(set (match_operand:SI 0 "arith_reg_dest")
1739 (plus:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
1741 (match_operand 2 "treg_set_expr")))
1742 (clobber (reg:SI T_REG))]
1743 "TARGET_SH1 && can_create_pseudo_p ()"
1746 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 1) (match_dup 1))
1748 (clobber (reg:SI T_REG))])])
1750 ;; Convert '(op2 + T) - op3' into 'op2 + (-op3) + T'
1751 (define_insn_and_split "*addc_negreg_t"
1752 [(set (match_operand:SI 0 "arith_reg_dest")
1753 (minus:SI (plus:SI (match_operand 1 "treg_set_expr")
1754 (match_operand:SI 2 "arith_reg_operand"))
1755 (match_operand:SI 3 "arith_reg_operand")))
1756 (clobber (reg:SI T_REG))]
1757 "TARGET_SH1 && can_create_pseudo_p ()"
1760 [(set (match_dup 4) (neg:SI (match_dup 3)))
1761 (parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 4))
1763 (clobber (reg:SI T_REG))])]
1765 operands[4] = gen_reg_rtx (SImode);
1768 (define_expand "addsi3"
1769 [(set (match_operand:SI 0 "arith_reg_dest")
1770 (plus:SI (match_operand:SI 1 "arith_reg_operand")
1771 (match_operand:SI 2 "arith_or_int_operand")))]
1774 if (!arith_operand (operands[2], SImode))
1776 if (!sh_lra_p () || reg_overlap_mentioned_p (operands[0], operands[1]))
1778 emit_insn (gen_addsi3_scr (operands[0], operands[1], operands[2]));
1784 ;; The *addsi3_compact is made an insn_and_split and accepts actually
1785 ;; impossible constraints to make LRA's register elimination work well on SH.
1786 ;; The problem is that LRA expects something like
1787 ;; (set rA (plus rB (const_int N)))
1788 ;; to work. We can do that, but we have to split out an additional reg-reg
1789 ;; copy or constant load before the actual add insn.
1790 ;; Use u constraint for that case to avoid the invalid value in the stack
1792 ;; This also results in better code when LRA is not used. However, we have
1793 ;; to use different sets of patterns and the order of these patterns is
1795 ;; In some cases the constant zero might end up in operands[2] of the
1796 ;; patterns. We have to accept that and convert it into a reg-reg move.
1797 (define_insn_and_split "*addsi3_compact_lra"
1798 [(set (match_operand:SI 0 "arith_reg_dest" "=r,&u")
1799 (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0,r")
1800 (match_operand:SI 2 "arith_or_int_operand" "rI08,rn")))]
1801 "TARGET_SH1 && sh_lra_p ()
1802 && (! reg_overlap_mentioned_p (operands[0], operands[1])
1803 || arith_operand (operands[2], SImode))"
1807 "&& reload_completed
1808 && ! reg_overlap_mentioned_p (operands[0], operands[1])"
1809 [(set (match_dup 0) (match_dup 2))
1810 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
1812 /* Prefer 'mov r0,r1; add #imm8,r1' over 'mov #imm8,r1; add r0,r1' */
1813 if (satisfies_constraint_I08 (operands[2]))
1814 std::swap (operands[1], operands[2]);
1816 [(set_attr "type" "arith")])
1818 (define_insn_and_split "addsi3_scr"
1819 [(set (match_operand:SI 0 "arith_reg_dest" "=r,&u,&u")
1820 (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0,r,r")
1821 (match_operand:SI 2 "arith_or_int_operand" "rI08,r,n")))
1822 (clobber (match_scratch:SI 3 "=X,X,&u"))]
1828 "&& reload_completed"
1829 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
1831 if (operands[2] == const0_rtx)
1833 emit_move_insn (operands[0], operands[1]);
1837 if (CONST_INT_P (operands[2]) && !satisfies_constraint_I08 (operands[2]))
1839 if (reg_overlap_mentioned_p (operands[0], operands[1]))
1841 emit_move_insn (operands[3], operands[2]);
1842 emit_move_insn (operands[0], operands[1]);
1843 operands[2] = operands[3];
1847 emit_move_insn (operands[0], operands[2]);
1848 operands[2] = operands[1];
1851 else if (!reg_overlap_mentioned_p (operands[0], operands[1]))
1853 if (!reg_overlap_mentioned_p (operands[0], operands[2]))
1854 emit_move_insn (operands[0], operands[1]);
1856 operands[2] = operands[1];
1859 [(set_attr "type" "arith")])
1861 ;; Old reload might generate add insns directly (not through the expander) for
1862 ;; address register calculations when reloading, in which case it won't try
1863 ;; the addsi_scr pattern. Because reload will sometimes try to validate
1864 ;; the generated insns and their constraints, this pattern must be
1865 ;; recognizable during and after reload. However, when reload generates
1866 ;; address register calculations for the stack pointer, we don't allow this
1867 ;; pattern. This will make reload prefer using indexed @(reg + reg) address
1868 ;; modes when the displacement of a @(disp + reg) doesn't fit.
1869 (define_insn_and_split "*addsi3"
1870 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1871 (plus:SI (match_operand:SI 1 "arith_reg_operand" "r")
1872 (match_operand:SI 2 "arith_or_int_operand" "rn")))]
1873 "TARGET_SH1 && !sh_lra_p ()
1874 && (reload_completed || reload_in_progress)
1875 && !reg_overlap_mentioned_p (operands[0], operands[1])
1876 && (!reload_in_progress
1877 || ((!REG_P (operands[1]) || REGNO (operands[1]) != SP_REG)
1878 && (!REG_P (operands[2]) || REGNO (operands[2]) != SP_REG)))"
1881 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
1883 if (operands[2] == const0_rtx)
1885 emit_move_insn (operands[0], operands[1]);
1889 if (CONST_INT_P (operands[2]))
1891 if (satisfies_constraint_I08 (operands[2]))
1892 emit_move_insn (operands[0], operands[1]);
1895 emit_move_insn (operands[0], operands[2]);
1896 operands[2] = operands[1];
1899 else if (!reg_overlap_mentioned_p (operands[0], operands[2]))
1900 emit_move_insn (operands[0], operands[1]);
1902 operands[2] = operands[1];
1905 (define_insn_and_split "*addsi3"
1906 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
1907 (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0,r")
1908 (match_operand:SI 2 "arith_operand" "rI08,Z")))]
1909 "TARGET_SH1 && !sh_lra_p ()"
1913 "&& operands[2] == const0_rtx"
1914 [(set (match_dup 0) (match_dup 1))]
1917 [(set_attr "type" "arith")])
1919 ;; -------------------------------------------------------------------------
1920 ;; Subtraction instructions
1921 ;; -------------------------------------------------------------------------
1923 (define_insn_and_split "subdi3"
1924 [(set (match_operand:DI 0 "arith_reg_dest")
1925 (minus:DI (match_operand:DI 1 "arith_reg_operand")
1926 (match_operand:DI 2 "arith_reg_operand")))
1927 (clobber (reg:SI T_REG))]
1930 "&& can_create_pseudo_p ()"
1933 emit_insn (gen_clrt ());
1934 emit_insn (gen_subc (gen_lowpart (SImode, operands[0]),
1935 gen_lowpart (SImode, operands[1]),
1936 gen_lowpart (SImode, operands[2])));
1937 emit_insn (gen_subc (gen_highpart (SImode, operands[0]),
1938 gen_highpart (SImode, operands[1]),
1939 gen_highpart (SImode, operands[2])));
1944 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1945 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
1946 (match_operand:SI 2 "arith_reg_operand" "r"))
1949 (gtu:SI (minus:SI (minus:SI (match_dup 1) (match_dup 2))
1954 [(set_attr "type" "arith")])
1956 ;; A simplified version of the subc insn, where the exact value of the
1957 ;; T bit doesn't matter. This is easier for combine to pick up.
1958 ;; We allow a reg or 0 for one of the operands in order to be able to
1959 ;; do 'reg - T' sequences. Reload will load the constant 0 into the reg
1961 (define_insn_and_split "*subc"
1962 [(set (match_operand:SI 0 "arith_reg_dest")
1963 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand")
1964 (match_operand:SI 2 "arith_reg_or_0_operand"))
1965 (match_operand 3 "treg_set_expr")))
1966 (clobber (reg:SI T_REG))]
1967 "TARGET_SH1 && can_create_pseudo_p ()"
1972 sh_treg_insns ti = sh_split_treg_set_expr (operands[3], curr_insn);
1973 if (ti.has_trailing_nott ())
1975 if (operands[2] == const0_rtx)
1977 /* op1 - (1 - T) = op1 - 1 + T = op1 + (-1) + T */
1978 remove_insn (ti.trailing_nott ());
1979 emit_insn (gen_addc (operands[0], operands[1],
1980 force_reg (SImode, GEN_INT (-1))));
1983 else if (!TARGET_SH2A)
1985 /* op1 - op2 - (1 - T) = op1 + (0 - op2 - 1) + T = op1 + ~op2 + T
1986 On SH2A keep the nott insn, because nott-subc sequence doesn't
1987 mutate the inputs. */
1988 remove_insn (ti.trailing_nott ());
1989 rtx tmp = gen_reg_rtx (SImode);
1990 emit_insn (gen_one_cmplsi2 (tmp, operands[2]));
1991 emit_insn (gen_addc (operands[0], operands[1], tmp));
1996 emit_insn (gen_subc (operands[0], operands[1],
1997 force_reg (SImode, operands[2])));
2001 ;; Convert reg - T - reg = reg - reg - T
2002 (define_insn_and_split "*subc"
2003 [(set (match_operand:SI 0 "arith_reg_dest")
2004 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand")
2005 (match_operand 2 "treg_set_expr"))
2006 (match_operand:SI 3 "arith_reg_operand")))
2007 (clobber (reg:SI T_REG))]
2008 "TARGET_SH1 && can_create_pseudo_p ()"
2011 [(parallel [(set (match_dup 0)
2012 (minus:SI (minus:SI (match_dup 1) (match_dup 3))
2014 (clobber (reg:SI T_REG))])])
2016 ;; Split reg - reg - 1 into a sett subc sequence, as it can be scheduled
2017 ;; better, if the sett insn can be done early.
2018 ;; Notice that combine turns 'a - b - 1' into 'a + (~b)'.
2019 (define_insn_and_split "*subc"
2020 [(set (match_operand:SI 0 "arith_reg_dest" "")
2021 (plus:SI (not:SI (match_operand:SI 1 "arith_reg_operand" ""))
2022 (match_operand:SI 2 "arith_reg_operand" "")))
2023 (clobber (reg:SI T_REG))]
2024 "TARGET_SH1 && can_create_pseudo_p ()"
2027 [(parallel [(set (match_dup 0)
2028 (minus:SI (minus:SI (match_dup 2) (match_dup 1))
2030 (clobber (reg:SI T_REG))])])
2032 ;; Split 'reg - T' into 'reg - 0 - T' to utilize the subc insn.
2033 ;; If the 0 constant can be CSE-ed, this becomes a one instruction
2034 ;; operation, as opposed to sequences such as
2038 ;; Even if the constant is not CSE-ed, a sequence such as
2041 ;; can be scheduled much better since the load of the constant can be
2042 ;; done earlier, before any comparison insns that store the result in
2044 ;; However, avoid things like 'reg - 1', which would expand into a
2045 ;; 3 insn sequence, instead of add #imm8.
2046 (define_insn_and_split "*subc"
2047 [(set (match_operand:SI 0 "arith_reg_dest" "")
2048 (minus:SI (match_operand:SI 1 "arith_reg_operand" "")
2049 (match_operand 2 "treg_set_expr_not_const01")))
2050 (clobber (reg:SI T_REG))]
2051 "TARGET_SH1 && can_create_pseudo_p ()"
2054 [(parallel [(set (match_dup 0)
2055 (minus:SI (minus:SI (match_dup 1) (const_int 0))
2057 (clobber (reg:SI T_REG))])])
2060 ;; (1 - T) - op2 = 1 - op2 - T
2061 (define_insn_and_split "*subc_negt_reg"
2062 [(set (match_operand:SI 0 "arith_reg_dest")
2063 (minus:SI (match_operand 1 "treg_set_expr_not_const01")
2064 (match_operand:SI 2 "arith_reg_operand")))
2065 (clobber (reg:SI T_REG))]
2066 "TARGET_SH1 && can_create_pseudo_p ()"
2071 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
2072 if (ti.remove_trailing_nott ())
2074 /* (1 - T) - op2 = 1 - op2 - T */
2075 emit_insn (gen_subc (operands[0],
2076 force_reg (SImode, GEN_INT (1)), operands[2]));
2080 /* T - op2: use movt,sub sequence. */
2081 rtx tmp = gen_reg_rtx (SImode);
2082 emit_insn (gen_movt (tmp, get_t_reg_rtx ()));
2083 emit_insn (gen_subsi3 (operands[0], tmp, operands[2]));
2089 ;; op1 - (1 - T) + op3 = op1 - 1 + T + op3
2090 ;; (op1 - T) + op3 = op1 - (-op3) - T
2091 (define_insn_and_split "*subc_negreg_t"
2092 [(set (match_operand:SI 0 "arith_reg_dest")
2093 (plus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand")
2094 (match_operand 2 "treg_set_expr"))
2095 (match_operand:SI 3 "arith_reg_operand")))
2096 (clobber (reg:SI T_REG))]
2097 "TARGET_SH1 && can_create_pseudo_p ()"
2102 sh_treg_insns ti = sh_split_treg_set_expr (operands[2], curr_insn);
2103 if (ti.remove_trailing_nott ())
2105 /* op1 - (1 - T) + op3 = (op1 - 1) + op3 + T */
2106 rtx tmp = gen_reg_rtx (SImode);
2107 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (-1)));
2108 emit_insn (gen_addc (operands[0], tmp, operands[3]));
2112 /* (op1 - T) + op3' = 'op1 - (-op3) - T */
2113 rtx tmp = gen_reg_rtx (SImode);
2114 emit_insn (gen_negsi2 (tmp, operands[3]));
2115 emit_insn (gen_subc (operands[0], operands[1], tmp));
2120 (define_insn "*subsi3_internal"
2121 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2122 (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
2123 (match_operand:SI 2 "arith_reg_operand" "r")))]
2126 [(set_attr "type" "arith")])
2133 ;; since this will sometimes save one instruction.
2134 ;; Otherwise we might get a sequence like
2138 ;; if the source and dest regs are the same.
2139 (define_expand "subsi3"
2140 [(set (match_operand:SI 0 "arith_reg_operand" "")
2141 (minus:SI (match_operand:SI 1 "arith_operand" "")
2142 (match_operand:SI 2 "arith_reg_operand" "")))]
2145 if (CONST_INT_P (operands[1]))
2147 emit_insn (gen_negsi2 (operands[0], operands[2]));
2148 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
2153 ;; -------------------------------------------------------------------------
2154 ;; Division instructions
2155 ;; -------------------------------------------------------------------------
2157 ;; We take advantage of the library routines which don't clobber as many
2158 ;; registers as a normal function call would.
2160 ;; The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
2161 ;; also has an effect on the register that holds the address of the sfunc.
2162 ;; To make this work, we have an extra dummy insn that shows the use
2163 ;; of this register for reorg.
2165 (define_insn "use_sfunc_addr"
2166 [(set (reg:SI PR_REG)
2167 (unspec:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_SFUNC))]
2168 "TARGET_SH1 && check_use_sfunc_addr (insn, operands[0])"
2170 [(set_attr "length" "0")])
2172 (define_insn "udivsi3_sh2a"
2173 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2174 (udiv:SI (match_operand:SI 1 "arith_reg_operand" "0")
2175 (match_operand:SI 2 "arith_reg_operand" "z")))]
2178 [(set_attr "type" "arith")
2179 (set_attr "in_delay_slot" "no")])
2181 ;; We must use a pseudo-reg forced to reg 0 in the SET_DEST rather than
2182 ;; hard register 0. If we used hard register 0, then the next instruction
2183 ;; would be a move from hard register 0 to a pseudo-reg. If the pseudo-reg
2184 ;; gets allocated to a stack slot that needs its address reloaded, then
2185 ;; there is nothing to prevent reload from using r0 to reload the address.
2186 ;; This reload would clobber the value in r0 we are trying to store.
2187 ;; If we let reload allocate r0, then this problem can never happen.
2188 (define_insn "udivsi3_i1"
2189 [(set (match_operand:SI 0 "register_operand" "=z,z")
2190 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2191 (clobber (reg:SI T_REG))
2192 (clobber (reg:SI PR_REG))
2193 (clobber (reg:SI R1_REG))
2194 (clobber (reg:SI R4_REG))
2195 (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
2196 (use (match_operand 2 "" "Z,Ccl"))]
2197 "TARGET_SH1 && TARGET_DIVIDE_CALL_DIV1"
2201 [(set_attr "type" "sfunc")
2202 (set_attr "needs_delay_slot" "yes")])
2204 (define_insn "udivsi3_i4"
2205 [(set (match_operand:SI 0 "register_operand" "=y,y")
2206 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2207 (clobber (reg:SI T_REG))
2208 (clobber (reg:SI PR_REG))
2209 (clobber (reg:DF DR0_REG))
2210 (clobber (reg:DF DR2_REG))
2211 (clobber (reg:DF DR4_REG))
2212 (clobber (reg:SI R0_REG))
2213 (clobber (reg:SI R1_REG))
2214 (clobber (reg:SI R4_REG))
2215 (clobber (reg:SI R5_REG))
2216 (clobber (reg:SI FPSCR_STAT_REG))
2217 (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
2218 (use (match_operand 2 "" "Z,Ccl"))
2219 (use (reg:SI FPSCR_MODES_REG))]
2220 "TARGET_FPU_DOUBLE && ! TARGET_FPU_SINGLE"
2224 [(set_attr "type" "sfunc")
2225 (set_attr "fp_mode" "double")
2226 (set_attr "needs_delay_slot" "yes")])
2228 (define_insn "udivsi3_i4_single"
2229 [(set (match_operand:SI 0 "register_operand" "=y,y")
2230 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2231 (clobber (reg:SI T_REG))
2232 (clobber (reg:SI PR_REG))
2233 (clobber (reg:DF DR0_REG))
2234 (clobber (reg:DF DR2_REG))
2235 (clobber (reg:DF DR4_REG))
2236 (clobber (reg:SI R0_REG))
2237 (clobber (reg:SI R1_REG))
2238 (clobber (reg:SI R4_REG))
2239 (clobber (reg:SI R5_REG))
2240 (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
2241 (use (match_operand 2 "" "Z,Ccl"))]
2242 "TARGET_FPU_ANY && TARGET_FPU_SINGLE"
2246 [(set_attr "type" "sfunc")
2247 (set_attr "needs_delay_slot" "yes")])
2249 (define_insn "udivsi3_i4_int"
2250 [(set (match_operand:SI 0 "register_operand" "=z")
2251 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2252 (clobber (reg:SI T_REG))
2253 (clobber (reg:SI R1_REG))
2254 (clobber (reg:SI PR_REG))
2255 (clobber (reg:SI MACH_REG))
2256 (clobber (reg:SI MACL_REG))
2257 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2260 [(set_attr "type" "sfunc")
2261 (set_attr "needs_delay_slot" "yes")])
2264 (define_expand "udivsi3"
2265 [(set (match_operand:SI 0 "register_operand")
2266 (udiv:SI (match_operand:SI 1 "general_operand")
2267 (match_operand:SI 2 "general_operand")))]
2272 operands[3] = gen_reg_rtx (Pmode);
2273 /* Emit the move of the address to a pseudo outside of the libcall. */
2274 if (TARGET_DIVIDE_CALL_TABLE)
2276 /* libgcc2:__udivmoddi4 is not supposed to use an actual division, since
2277 that causes problems when the divide code is supposed to come from a
2278 separate library. Division by zero is undefined, so dividing 1 can be
2279 implemented by comparing with the divisor. */
2280 if (operands[1] == const1_rtx && currently_expanding_to_rtl)
2282 rtx test = gen_rtx_GEU (VOIDmode, operands[1], operands[2]);
2283 emit_insn (gen_cstoresi4 (operands[0], test,
2284 operands[1], operands[2]));
2287 else if (operands[2] == const0_rtx)
2289 emit_move_insn (operands[0], operands[2]);
2292 function_symbol (operands[3], "__udivsi3_i4i", SFUNC_GOT);
2293 last = gen_udivsi3_i4_int (operands[0], operands[3]);
2295 else if (TARGET_DIVIDE_CALL_FP)
2297 rtx lab = function_symbol (operands[3], "__udivsi3_i4", SFUNC_STATIC).lab;
2298 if (TARGET_FPU_SINGLE)
2299 last = gen_udivsi3_i4_single (operands[0], operands[3], lab);
2301 last = gen_udivsi3_i4 (operands[0], operands[3], lab);
2303 else if (TARGET_SH2A)
2305 operands[1] = force_reg (SImode, operands[1]);
2306 operands[2] = force_reg (SImode, operands[2]);
2307 emit_insn (gen_udivsi3_sh2a (operands[0], operands[1], operands[2]));
2312 rtx lab = function_symbol (operands[3], "__udivsi3", SFUNC_STATIC).lab;
2313 last = gen_udivsi3_i1 (operands[0], operands[3], lab);
2315 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
2316 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
2321 (define_insn "divsi3_sh2a"
2322 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2323 (div:SI (match_operand:SI 1 "arith_reg_operand" "0")
2324 (match_operand:SI 2 "arith_reg_operand" "z")))]
2327 [(set_attr "type" "arith")
2328 (set_attr "in_delay_slot" "no")])
2330 (define_insn "divsi3_i1"
2331 [(set (match_operand:SI 0 "register_operand" "=z")
2332 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2333 (clobber (reg:SI T_REG))
2334 (clobber (reg:SI PR_REG))
2335 (clobber (reg:SI R1_REG))
2336 (clobber (reg:SI R2_REG))
2337 (clobber (reg:SI R3_REG))
2338 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2339 "TARGET_SH1 && TARGET_DIVIDE_CALL_DIV1"
2341 [(set_attr "type" "sfunc")
2342 (set_attr "needs_delay_slot" "yes")])
2344 (define_insn "divsi3_i4"
2345 [(set (match_operand:SI 0 "register_operand" "=y,y")
2346 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2347 (clobber (reg:SI PR_REG))
2348 (clobber (reg:DF DR0_REG))
2349 (clobber (reg:DF DR2_REG))
2350 (clobber (reg:SI FPSCR_STAT_REG))
2351 (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
2352 (use (match_operand 2 "" "Z,Ccl"))
2353 (use (reg:SI FPSCR_MODES_REG))]
2354 "TARGET_FPU_DOUBLE && ! TARGET_FPU_SINGLE"
2358 [(set_attr "type" "sfunc")
2359 (set_attr "fp_mode" "double")
2360 (set_attr "needs_delay_slot" "yes")])
2362 (define_insn "divsi3_i4_single"
2363 [(set (match_operand:SI 0 "register_operand" "=y,y")
2364 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2365 (clobber (reg:SI PR_REG))
2366 (clobber (reg:DF DR0_REG))
2367 (clobber (reg:DF DR2_REG))
2368 (clobber (reg:SI R2_REG))
2369 (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
2370 (use (match_operand 2 "" "Z,Ccl"))]
2371 "TARGET_FPU_ANY && TARGET_FPU_SINGLE"
2375 [(set_attr "type" "sfunc")
2376 (set_attr "needs_delay_slot" "yes")])
2378 (define_insn "divsi3_i4_int"
2379 [(set (match_operand:SI 0 "register_operand" "=z")
2380 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2381 (clobber (reg:SI T_REG))
2382 (clobber (reg:SI PR_REG))
2383 (clobber (reg:SI R1_REG))
2384 (clobber (reg:SI MACH_REG))
2385 (clobber (reg:SI MACL_REG))
2386 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2389 [(set_attr "type" "sfunc")
2390 (set_attr "needs_delay_slot" "yes")])
2392 (define_expand "divsi3"
2393 [(set (match_operand:SI 0 "register_operand")
2394 (div:SI (match_operand:SI 1 "general_operand")
2395 (match_operand:SI 2 "general_operand")))]
2400 operands[3] = gen_reg_rtx (Pmode);
2401 /* Emit the move of the address to a pseudo outside of the libcall. */
2402 if (TARGET_DIVIDE_CALL_TABLE)
2404 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_GOT);
2405 last = gen_divsi3_i4_int (operands[0], operands[3]);
2407 else if (TARGET_DIVIDE_CALL_FP)
2409 rtx lab = function_symbol (operands[3], sh_divsi3_libfunc,
2411 if (TARGET_FPU_SINGLE)
2412 last = gen_divsi3_i4_single (operands[0], operands[3], lab);
2414 last = gen_divsi3_i4 (operands[0], operands[3], lab);
2416 else if (TARGET_SH2A)
2418 operands[1] = force_reg (SImode, operands[1]);
2419 operands[2] = force_reg (SImode, operands[2]);
2420 emit_insn (gen_divsi3_sh2a (operands[0], operands[1], operands[2]));
2425 function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_GOT);
2426 last = gen_divsi3_i1 (operands[0], operands[3]);
2428 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
2429 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
2435 ;; -------------------------------------------------------------------------
2436 ;; Multiplication instructions
2437 ;; -------------------------------------------------------------------------
2439 (define_insn_and_split "mulhisi3"
2440 [(set (match_operand:SI 0 "arith_reg_dest")
2441 (mult:SI (sign_extend:SI (match_operand:HI 1 "arith_reg_operand"))
2442 (sign_extend:SI (match_operand:HI 2 "arith_reg_operand"))))
2443 (clobber (reg:SI MACL_REG))]
2444 "TARGET_SH1 && can_create_pseudo_p ()"
2447 [(set (reg:SI MACL_REG) (mult:SI (sign_extend:SI (match_dup 1))
2448 (sign_extend:SI (match_dup 2))))
2449 (set (match_dup 0) (reg:SI MACL_REG))])
2451 (define_insn_and_split "umulhisi3"
2452 [(set (match_operand:SI 0 "arith_reg_dest")
2453 (mult:SI (zero_extend:SI (match_operand:HI 1 "arith_reg_operand"))
2454 (zero_extend:SI (match_operand:HI 2 "arith_reg_operand"))))
2455 (clobber (reg:SI MACL_REG))]
2456 "TARGET_SH1 && can_create_pseudo_p ()"
2459 [(set (reg:SI MACL_REG) (mult:SI (zero_extend:SI (match_dup 1))
2460 (zero_extend:SI (match_dup 2))))
2461 (set (match_dup 0) (reg:SI MACL_REG))])
2463 (define_insn "umulhisi3_i"
2464 [(set (reg:SI MACL_REG)
2465 (mult:SI (zero_extend:SI
2466 (match_operand:HI 0 "arith_reg_operand" "r"))
2468 (match_operand:HI 1 "arith_reg_operand" "r"))))]
2471 [(set_attr "type" "smpy")])
2473 (define_insn "mulhisi3_i"
2474 [(set (reg:SI MACL_REG)
2475 (mult:SI (sign_extend:SI
2476 (match_operand:HI 0 "arith_reg_operand" "r"))
2478 (match_operand:HI 1 "arith_reg_operand" "r"))))]
2481 [(set_attr "type" "smpy")])
2484 ;; mulsi3 on the SH2 can be done in one instruction, on the SH1 we generate
2485 ;; a call to a routine which clobbers known registers.
2486 (define_insn "mulsi3_call"
2487 [(set (match_operand:SI 1 "register_operand" "=z")
2488 (mult:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2489 (clobber (reg:SI MACL_REG))
2490 (clobber (reg:SI T_REG))
2491 (clobber (reg:SI PR_REG))
2492 (clobber (reg:SI R3_REG))
2493 (clobber (reg:SI R2_REG))
2494 (clobber (reg:SI R1_REG))
2495 (use (match_operand:SI 0 "arith_reg_operand" "r"))]
2498 [(set_attr "type" "sfunc")
2499 (set_attr "needs_delay_slot" "yes")])
2501 (define_insn "mul_r"
2502 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2503 (mult:SI (match_operand:SI 1 "arith_reg_operand" "0")
2504 (match_operand:SI 2 "arith_reg_operand" "z")))]
2507 [(set_attr "type" "dmpy")])
2509 (define_insn "mul_l"
2510 [(set (reg:SI MACL_REG)
2511 (mult:SI (match_operand:SI 0 "arith_reg_operand" "r")
2512 (match_operand:SI 1 "arith_reg_operand" "r")))]
2515 [(set_attr "type" "dmpy")])
2517 (define_insn_and_split "mulsi3_i"
2518 [(set (match_operand:SI 0 "arith_reg_dest")
2519 (mult:SI (match_operand:SI 1 "arith_reg_operand")
2520 (match_operand:SI 2 "arith_reg_operand")))
2521 (clobber (reg:SI MACL_REG))]
2522 "TARGET_SH2 && can_create_pseudo_p ()"
2525 [(set (reg:SI MACL_REG) (mult:SI (match_dup 1) (match_dup 2)))
2526 (set (match_dup 0) (reg:SI MACL_REG))])
2528 (define_expand "mulsi3"
2529 [(set (match_operand:SI 0 "arith_reg_dest")
2530 (mult:SI (match_operand:SI 1 "arith_reg_operand")
2531 (match_operand:SI 2 "arith_reg_operand")))]
2536 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
2537 emit_move_insn (gen_rtx_REG (SImode, R5_REG), operands[2]);
2539 rtx sym = function_symbol (NULL, "__mulsi3", SFUNC_STATIC).sym;
2541 emit_insn (gen_mulsi3_call (force_reg (SImode, sym), operands[0]));
2545 /* FIXME: For some reason, expanding the mul_l insn and the macl store
2546 insn early gives slightly better code. In particular it prevents
2547 the decrement-test loop type to be used in some cases which saves
2548 one multiplication in the loop setup code.
2550 emit_insn (gen_mulsi3_i (operands[0], operands[1], operands[2]));
2553 emit_insn (gen_mul_l (operands[1], operands[2]));
2554 emit_move_insn (operands[0], gen_rtx_REG (SImode, MACL_REG));
2559 (define_insn "mulsidi3_i"
2560 [(set (reg:SI MACH_REG)
2564 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
2565 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
2567 (set (reg:SI MACL_REG)
2568 (mult:SI (match_dup 0)
2572 [(set_attr "type" "dmpy")])
2574 (define_expand "mulsidi3"
2575 [(set (match_operand:DI 0 "arith_reg_dest")
2576 (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand"))
2577 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand"))))]
2580 emit_insn (gen_mulsidi3_compact (operands[0], operands[1], operands[2]));
2584 (define_insn_and_split "mulsidi3_compact"
2585 [(set (match_operand:DI 0 "arith_reg_dest")
2586 (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand"))
2587 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand"))))
2588 (clobber (reg:SI MACH_REG))
2589 (clobber (reg:SI MACL_REG))]
2590 "TARGET_SH2 && can_create_pseudo_p ()"
2595 rtx low_dst = gen_lowpart (SImode, operands[0]);
2596 rtx high_dst = gen_highpart (SImode, operands[0]);
2598 emit_insn (gen_mulsidi3_i (operands[1], operands[2]));
2600 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
2601 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
2602 /* We need something to tag the possible REG_EQUAL notes on to. */
2603 emit_move_insn (operands[0], operands[0]);
2607 (define_insn "umulsidi3_i"
2608 [(set (reg:SI MACH_REG)
2612 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
2613 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
2615 (set (reg:SI MACL_REG)
2616 (mult:SI (match_dup 0)
2620 [(set_attr "type" "dmpy")])
2622 (define_expand "umulsidi3"
2623 [(set (match_operand:DI 0 "arith_reg_dest")
2624 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand"))
2625 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand"))))]
2628 emit_insn (gen_umulsidi3_compact (operands[0], operands[1], operands[2]));
2632 (define_insn_and_split "umulsidi3_compact"
2633 [(set (match_operand:DI 0 "arith_reg_dest")
2634 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand"))
2635 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand"))))
2636 (clobber (reg:SI MACH_REG))
2637 (clobber (reg:SI MACL_REG))]
2638 "TARGET_SH2 && can_create_pseudo_p ()"
2643 rtx low_dst = gen_lowpart (SImode, operands[0]);
2644 rtx high_dst = gen_highpart (SImode, operands[0]);
2646 emit_insn (gen_umulsidi3_i (operands[1], operands[2]));
2648 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
2649 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
2650 /* We need something to tag the possible REG_EQUAL notes on to. */
2651 emit_move_insn (operands[0], operands[0]);
2655 (define_insn "smulsi3_highpart_i"
2656 [(set (reg:SI MACH_REG)
2660 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
2661 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
2663 (clobber (reg:SI MACL_REG))]
2666 [(set_attr "type" "dmpy")])
2668 (define_insn_and_split "smulsi3_highpart"
2669 [(set (match_operand:SI 0 "arith_reg_dest")
2673 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand"))
2674 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand")))
2676 (clobber (reg:SI MACL_REG))
2677 (clobber (reg:SI MACH_REG))]
2678 "TARGET_SH2 && can_create_pseudo_p ()"
2683 emit_insn (gen_smulsi3_highpart_i (operands[1], operands[2]));
2684 emit_move_insn (operands[0], gen_rtx_REG (SImode, MACH_REG));
2687 (define_insn "umulsi3_highpart_i"
2688 [(set (reg:SI MACH_REG)
2692 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
2693 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
2695 (clobber (reg:SI MACL_REG))]
2698 [(set_attr "type" "dmpy")])
2700 (define_insn_and_split "umulsi3_highpart"
2701 [(set (match_operand:SI 0 "arith_reg_dest")
2705 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand"))
2706 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand")))
2708 (clobber (reg:SI MACL_REG))]
2709 "TARGET_SH2 && can_create_pseudo_p ()"
2714 emit_insn (gen_umulsi3_highpart_i (operands[1], operands[2]));
2715 emit_move_insn (operands[0], gen_rtx_REG (SImode, MACH_REG));
2718 ;; -------------------------------------------------------------------------
2719 ;; Logical operations
2720 ;; -------------------------------------------------------------------------
2722 (define_expand "andsi3"
2723 [(set (match_operand:SI 0 "arith_reg_dest")
2724 (and:SI (match_operand:SI 1 "arith_reg_operand")
2725 (match_operand:SI 2 "logical_and_operand")))]
2728 /* If it is possible to turn the and insn into a zero extension
2729 already, redundant zero extensions will be folded, which results
2731 Ideally the splitter of *andsi_compact would be enough, if redundant
2732 zero extensions were detected after the combine pass, which does not
2733 happen at the moment. */
2735 if (satisfies_constraint_Jmb (operands[2]))
2737 emit_insn (gen_zero_extendqisi2 (operands[0],
2738 gen_lowpart (QImode, operands[1])));
2741 else if (satisfies_constraint_Jmw (operands[2]))
2743 emit_insn (gen_zero_extendhisi2 (operands[0],
2744 gen_lowpart (HImode, operands[1])));
2749 (define_insn_and_split "*andsi_compact"
2750 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r,z,r")
2751 (and:SI (match_operand:SI 1 "arith_reg_operand" "%r,r,0,0")
2752 (match_operand:SI 2 "logical_and_operand" "Jmb,Jmw,K08,r")))]
2760 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))]
2762 if (satisfies_constraint_Jmb (operands[2]))
2763 operands[1] = gen_lowpart (QImode, operands[1]);
2764 else if (satisfies_constraint_Jmw (operands[2]))
2765 operands[1] = gen_lowpart (HImode, operands[1]);
2769 [(set_attr "type" "arith")])
2771 (define_insn "*andsi3_bclr"
2772 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2773 (and:SI (match_operand:SI 1 "arith_reg_operand" "%0")
2774 (match_operand:SI 2 "const_int_operand" "Psz")))]
2775 "TARGET_SH2A && satisfies_constraint_Psz (operands[2])"
2777 [(set_attr "type" "arith")])
2779 (define_expand "iorsi3"
2780 [(set (match_operand:SI 0 "arith_reg_dest")
2781 (ior:SI (match_operand:SI 1 "arith_reg_operand")
2782 (match_operand:SI 2 "logical_operand")))])
2784 (define_insn "*iorsi3_compact"
2785 [(set (match_operand:SI 0 "arith_reg_dest" "=r,z")
2786 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
2787 (match_operand:SI 2 "logical_operand" "r,K08")))]
2789 && !(TARGET_SH2A && satisfies_constraint_Pso (operands[2]))"
2791 [(set_attr "type" "arith")])
2793 (define_insn "*iorsi3_bset"
2794 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2795 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0")
2796 (match_operand:SI 2 "const_int_operand" "Pso")))]
2797 "TARGET_SH2A && satisfies_constraint_Pso (operands[2])"
2799 [(set_attr "type" "arith")])
2801 (define_insn "xorsi3"
2802 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r")
2803 (xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
2804 (match_operand:SI 2 "logical_operand" "K08,r")))]
2807 [(set_attr "type" "arith")])
2809 ;; The *logical_op_t pattern helps combine eliminating sign/zero extensions
2810 ;; of results where one of the inputs is a T bit store. Notice that this
2811 ;; pattern must not match during reload. If reload picks this pattern it
2812 ;; will be impossible to split it afterwards.
2813 (define_insn_and_split "*logical_op_t"
2814 [(set (match_operand:SI 0 "arith_reg_dest")
2815 (match_operator:SI 3 "logical_operator"
2816 [(match_operand:SI 1 "arith_reg_operand")
2817 (match_operand:SI 2 "t_reg_operand")]))]
2818 "TARGET_SH1 && can_create_pseudo_p ()"
2821 [(set (match_dup 4) (reg:SI T_REG))
2822 (set (match_dup 0) (match_dup 3))]
2824 operands[4] = gen_reg_rtx (SImode);
2825 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2826 operands[1], operands[4]);
2829 ;; -------------------------------------------------------------------------
2830 ;; Shifts and rotates
2831 ;; -------------------------------------------------------------------------
2833 ;; Let combine see that we can get the MSB and LSB into the T bit
2834 ;; via shll and shlr. This allows it to plug it into insns that can have
2835 ;; the T bit as an input (e.g. addc).
2836 ;; On SH2A use bld #0,Rn instead of shlr to avoid mutating the input.
2837 (define_insn_and_split "*reg_lsb_t"
2838 [(set (reg:SI T_REG)
2839 (and:SI (match_operand:SI 0 "arith_reg_operand")
2841 "TARGET_SH1 && can_create_pseudo_p ()"
2846 emit_insn (TARGET_SH2A ? gen_bldsi_reg (operands[0], const0_rtx)
2847 : gen_shlr (gen_reg_rtx (SImode), operands[0]));
2850 (define_insn_and_split "*reg_msb_t"
2851 [(set (reg:SI T_REG)
2852 (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand")
2854 "TARGET_SH1 && can_create_pseudo_p ()"
2859 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[0]));
2862 (define_expand "rotrsi3"
2863 [(set (match_operand:SI 0 "arith_reg_dest")
2864 (rotatert:SI (match_operand:SI 1 "arith_reg_operand")
2865 (match_operand:SI 2 "const_int_operand")))]
2868 HOST_WIDE_INT ival = INTVAL (operands[2]);
2871 emit_insn (gen_rotrsi3_1 (operands[0], operands[1]));
2878 (define_insn "rotrsi3_1"
2879 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2880 (rotatert:SI (match_operand:SI 1 "arith_reg_operand" "0")
2883 (and:SI (match_dup 1) (const_int 1)))]
2886 [(set_attr "type" "arith")])
2888 ;; A slimplified version of rotr for combine.
2889 (define_insn "*rotrsi3_1"
2890 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2891 (rotatert:SI (match_operand:SI 1 "arith_reg_operand" "0")
2893 (clobber (reg:SI T_REG))]
2896 [(set_attr "type" "arith")])
2898 (define_insn "rotlsi3_1"
2899 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2900 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
2903 (lshiftrt:SI (match_dup 1) (const_int 31)))]
2906 [(set_attr "type" "arith")])
2908 ;; A simplified version of rotl for combine.
2909 (define_insn "*rotlsi3_1"
2910 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2911 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
2913 (clobber (reg:SI T_REG))]
2916 [(set_attr "type" "arith")])
2918 (define_insn "rotlsi3_31"
2919 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2920 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
2922 (clobber (reg:SI T_REG))]
2925 [(set_attr "type" "arith")])
2927 (define_insn "rotlsi3_16"
2928 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2929 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "r")
2933 [(set_attr "type" "arith")])
2935 (define_expand "rotlsi3"
2936 [(set (match_operand:SI 0 "arith_reg_dest")
2937 (rotate:SI (match_operand:SI 1 "arith_reg_operand")
2938 (match_operand:SI 2 "const_int_operand")))]
2941 static const char rot_tab[] = {
2942 000, 000, 000, 000, 000, 000, 010, 001,
2943 001, 001, 011, 013, 003, 003, 003, 003,
2944 003, 003, 003, 003, 003, 013, 012, 002,
2945 002, 002, 010, 000, 000, 000, 000, 000,
2948 int count = INTVAL (operands[2]);
2949 int choice = rot_tab[count];
2950 if (choice & 010 && SH_DYNAMIC_SHIFT_COST <= 1)
2956 emit_move_insn (operands[0], operands[1]);
2957 count -= (count & 16) * 2;
2960 emit_insn (gen_rotlsi3_16 (operands[0], operands[1]));
2967 parts[0] = gen_reg_rtx (SImode);
2968 parts[1] = gen_reg_rtx (SImode);
2969 emit_insn (gen_rotlsi3_16 (parts[2-choice], operands[1]));
2970 emit_move_insn (parts[choice-1], operands[1]);
2971 emit_insn (gen_ashlsi3 (parts[0], parts[0], GEN_INT (8)));
2972 emit_insn (gen_lshrsi3 (parts[1], parts[1], GEN_INT (8)));
2973 emit_insn (gen_iorsi3 (operands[0], parts[0], parts[1]));
2974 count = (count & ~16) - 8;
2978 for (; count > 0; count--)
2979 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
2980 for (; count < 0; count++)
2981 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
2986 (define_insn "rotlhi3_8"
2987 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
2988 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "r")
2992 [(set_attr "type" "arith")])
2994 (define_expand "rotlhi3"
2995 [(set (match_operand:HI 0 "arith_reg_operand")
2996 (rotate:HI (match_operand:HI 1 "arith_reg_operand")
2997 (match_operand:HI 2 "const_int_operand")))]
3000 if (INTVAL (operands[2]) != 8)
3004 ;; The rotcr and rotcl insns are used primarily in DImode shifts by one.
3005 ;; They can also be used to implement things like
3007 ;; int x0 = (y >> 1) | (t << 31); // rotcr
3008 ;; int x1 = (y << 1) | t; // rotcl
3009 (define_insn "rotcr"
3010 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3011 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3013 (ashift:SI (match_operand:SI 2 "t_reg_operand")
3016 (and:SI (match_dup 1) (const_int 1)))]
3019 [(set_attr "type" "arith")])
3021 (define_insn "rotcl"
3022 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3023 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
3025 (match_operand:SI 2 "t_reg_operand")))
3027 (lshiftrt:SI (match_dup 1) (const_int 31)))]
3030 [(set_attr "type" "arith")])
3032 ;; Simplified rotcr version for combine, which allows arbitrary shift
3033 ;; amounts for the reg. If the shift amount is '1' rotcr can be used
3034 ;; directly. Otherwise we have to insert a shift in between.
3035 (define_insn_and_split "*rotcr"
3036 [(set (match_operand:SI 0 "arith_reg_dest")
3037 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_or_0_operand")
3038 (match_operand:SI 2 "const_int_operand"))
3039 (ashift:SI (match_operand 3 "arith_reg_or_treg_set_expr")
3041 (clobber (reg:SI T_REG))]
3042 "TARGET_SH1 && can_create_pseudo_p ()"
3047 rtx_insn *prev_set_t_insn = NULL;
3049 if (!arith_reg_operand (operands[3], SImode))
3051 sh_treg_insns ti = sh_split_treg_set_expr (operands[3], curr_insn);
3052 if (!ti.was_treg_operand ())
3053 prev_set_t_insn = ti.first_insn ();
3055 operands[3] = get_t_reg_rtx ();
3057 if (TARGET_SH2A && ti.has_trailing_nott () && operands[1] == const0_rtx)
3059 /* Convert to a movrt, rotr sequence. */
3060 remove_insn (ti.trailing_nott ());
3061 rtx tmp = gen_reg_rtx (SImode);
3062 emit_insn (gen_movnegt (tmp, get_t_reg_rtx ()));
3063 emit_insn (gen_rotrsi3_1 (operands[0], tmp));
3068 if (operands[1] == const0_rtx)
3070 operands[1] = gen_reg_rtx (SImode);
3071 emit_insn (gen_movt (operands[1], get_t_reg_rtx ()));
3074 if (INTVAL (operands[2]) > 1)
3076 const rtx shift_count = GEN_INT (INTVAL (operands[2]) - 1);
3077 rtx tmp_t_reg = NULL_RTX;
3079 /* If we're going to emit a shift sequence that clobbers the T_REG,
3080 try to find the previous insn that sets the T_REG and emit the
3081 shift insn before that insn, to remove the T_REG dependency.
3082 If the insn that sets the T_REG cannot be found, store the T_REG
3083 in a temporary reg and restore it after the shift. */
3084 if (sh_lshrsi_clobbers_t_reg_p (shift_count)
3085 && ! sh_dynamicalize_shift_p (shift_count))
3087 if (prev_set_t_insn == NULL)
3088 prev_set_t_insn = prev_nonnote_insn_bb (curr_insn);
3090 /* Skip the nott insn, which was probably inserted by the splitter
3091 of *rotcr_neg_t. Don't use one of the recog functions
3092 here during insn splitting, since that causes problems in later
3094 if (prev_set_t_insn != NULL_RTX)
3096 rtx pat = PATTERN (prev_set_t_insn);
3097 if (GET_CODE (pat) == SET
3098 && t_reg_operand (XEXP (pat, 0), SImode)
3099 && negt_reg_operand (XEXP (pat, 1), SImode))
3100 prev_set_t_insn = prev_nonnote_insn_bb (prev_set_t_insn);
3103 if (! (prev_set_t_insn != NULL_RTX
3104 && reg_set_p (get_t_reg_rtx (), prev_set_t_insn)
3105 && ! reg_referenced_p (get_t_reg_rtx (),
3106 PATTERN (prev_set_t_insn))))
3108 prev_set_t_insn = NULL;
3109 tmp_t_reg = gen_reg_rtx (SImode);
3110 emit_insn (gen_move_insn (tmp_t_reg, get_t_reg_rtx ()));
3114 rtx shift_result = gen_reg_rtx (SImode);
3115 rtx shift_insn = gen_lshrsi3 (shift_result, operands[1], shift_count);
3116 operands[1] = shift_result;
3118 /* Emit the shift insn before the insn that sets T_REG, if possible. */
3119 if (prev_set_t_insn != NULL_RTX)
3120 emit_insn_before (shift_insn, prev_set_t_insn);
3122 emit_insn (shift_insn);
3124 /* Restore T_REG if it has been saved before. */
3125 if (tmp_t_reg != NULL_RTX)
3126 emit_insn (gen_cmpgtsi_t (tmp_t_reg, const0_rtx));
3129 /* For the rotcr insn to work, operands[3] must be in T_REG.
3130 If it is not we can get it there by shifting it right one bit.
3131 In this case T_REG is not an input for this insn, thus we don't have to
3132 pay attention as of where to insert the shlr insn. */
3133 if (! t_reg_operand (operands[3], SImode))
3135 /* We don't care about the shifted result here, only the T_REG. */
3136 emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[3]));
3137 operands[3] = get_t_reg_rtx ();
3140 emit_insn (gen_rotcr (operands[0], operands[1], operands[3]));
3144 ;; If combine tries the same as above but with swapped operands, split
3145 ;; it so that it will try the pattern above.
3147 [(set (match_operand:SI 0 "arith_reg_dest")
3148 (ior:SI (ashift:SI (match_operand 1 "arith_reg_or_treg_set_expr")
3150 (lshiftrt:SI (match_operand:SI 2 "arith_reg_or_0_operand")
3151 (match_operand:SI 3 "const_int_operand"))))]
3152 "TARGET_SH1 && can_create_pseudo_p ()"
3153 [(parallel [(set (match_dup 0)
3154 (ior:SI (lshiftrt:SI (match_dup 2) (match_dup 3))
3155 (ashift:SI (match_dup 1) (const_int 31))))
3156 (clobber (reg:SI T_REG))])])
3158 ;; Basically the same as the rotcr pattern above, but for rotcl.
3159 ;; FIXME: Fold copy pasted split code for rotcr and rotcl.
3160 (define_insn_and_split "*rotcl"
3161 [(set (match_operand:SI 0 "arith_reg_dest")
3162 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
3163 (match_operand:SI 2 "const_int_operand"))
3164 (and:SI (match_operand:SI 3 "arith_reg_or_t_reg_operand")
3166 (clobber (reg:SI T_REG))]
3169 "&& can_create_pseudo_p ()"
3172 gcc_assert (INTVAL (operands[2]) > 0);
3174 if (INTVAL (operands[2]) > 1)
3176 const rtx shift_count = GEN_INT (INTVAL (operands[2]) - 1);
3177 rtx_insn *prev_set_t_insn = NULL;
3178 rtx tmp_t_reg = NULL_RTX;
3180 /* If we're going to emit a shift sequence that clobbers the T_REG,
3181 try to find the previous insn that sets the T_REG and emit the
3182 shift insn before that insn, to remove the T_REG dependency.
3183 If the insn that sets the T_REG cannot be found, store the T_REG
3184 in a temporary reg and restore it after the shift. */
3185 if (sh_ashlsi_clobbers_t_reg_p (shift_count)
3186 && ! sh_dynamicalize_shift_p (shift_count))
3188 prev_set_t_insn = prev_nonnote_insn_bb (curr_insn);
3190 /* Skip the nott insn, which was probably inserted by the splitter
3191 of *rotcl_neg_t. Don't use one of the recog functions
3192 here during insn splitting, since that causes problems in later
3194 if (prev_set_t_insn != NULL_RTX)
3196 rtx pat = PATTERN (prev_set_t_insn);
3197 if (GET_CODE (pat) == SET
3198 && t_reg_operand (XEXP (pat, 0), SImode)
3199 && negt_reg_operand (XEXP (pat, 1), SImode))
3200 prev_set_t_insn = prev_nonnote_insn_bb (prev_set_t_insn);
3203 if (! (prev_set_t_insn != NULL_RTX
3204 && reg_set_p (get_t_reg_rtx (), prev_set_t_insn)
3205 && ! reg_referenced_p (get_t_reg_rtx (),
3206 PATTERN (prev_set_t_insn))))
3208 prev_set_t_insn = NULL;
3209 tmp_t_reg = gen_reg_rtx (SImode);
3210 emit_insn (gen_move_insn (tmp_t_reg, get_t_reg_rtx ()));
3214 rtx shift_result = gen_reg_rtx (SImode);
3215 rtx shift_insn = gen_ashlsi3 (shift_result, operands[1], shift_count);
3216 operands[1] = shift_result;
3218 /* Emit the shift insn before the insn that sets T_REG, if possible. */
3219 if (prev_set_t_insn != NULL_RTX)
3220 emit_insn_before (shift_insn, prev_set_t_insn);
3222 emit_insn (shift_insn);
3224 /* Restore T_REG if it has been saved before. */
3225 if (tmp_t_reg != NULL_RTX)
3226 emit_insn (gen_cmpgtsi_t (tmp_t_reg, const0_rtx));
3229 /* For the rotcl insn to work, operands[3] must be in T_REG.
3230 If it is not we can get it there by shifting it right one bit.
3231 In this case T_REG is not an input for this insn, thus we don't have to
3232 pay attention as of where to insert the shlr insn. */
3233 if (! t_reg_operand (operands[3], SImode))
3235 /* We don't care about the shifted result here, only the T_REG. */
3236 emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[3]));
3237 operands[3] = get_t_reg_rtx ();
3240 emit_insn (gen_rotcl (operands[0], operands[1], operands[3]));
3244 ;; rotcl combine pattern variations
3245 (define_insn_and_split "*rotcl"
3246 [(set (match_operand:SI 0 "arith_reg_dest")
3247 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
3248 (match_operand:SI 2 "const_int_operand"))
3249 (match_operand 3 "treg_set_expr")))
3250 (clobber (reg:SI T_REG))]
3253 "&& can_create_pseudo_p ()"
3254 [(parallel [(set (match_dup 0)
3255 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
3256 (and:SI (match_dup 3) (const_int 1))))
3257 (clobber (reg:SI T_REG))])]
3259 sh_split_treg_set_expr (operands[3], curr_insn);
3260 operands[3] = get_t_reg_rtx ();
3263 (define_insn_and_split "*rotcl"
3264 [(set (match_operand:SI 0 "arith_reg_dest")
3265 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_or_t_reg_operand")
3267 (ashift:SI (match_operand:SI 2 "arith_reg_operand")
3268 (match_operand:SI 3 "const_int_operand"))))
3269 (clobber (reg:SI T_REG))]
3272 "&& can_create_pseudo_p ()"
3273 [(parallel [(set (match_dup 0)
3274 (ior:SI (ashift:SI (match_dup 2) (match_dup 3))
3275 (and:SI (match_dup 1) (const_int 1))))
3276 (clobber (reg:SI T_REG))])])
3278 (define_insn_and_split "*rotcl"
3279 [(set (match_operand:SI 0 "arith_reg_dest")
3280 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
3281 (match_operand:SI 2 "const_int_operand"))
3282 (lshiftrt:SI (match_operand:SI 3 "arith_reg_operand")
3284 (clobber (reg:SI T_REG))]
3287 "&& can_create_pseudo_p ()"
3288 [(parallel [(set (match_dup 0)
3289 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
3290 (and:SI (reg:SI T_REG) (const_int 1))))
3291 (clobber (reg:SI T_REG))])]
3293 /* We don't care about the result of the left shift, only the T_REG. */
3294 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[3]));
3297 (define_insn_and_split "*rotcl"
3298 [(set (match_operand:SI 0 "arith_reg_dest")
3299 (ior:SI (lshiftrt:SI (match_operand:SI 3 "arith_reg_operand")
3301 (ashift:SI (match_operand:SI 1 "arith_reg_operand")
3302 (match_operand:SI 2 "const_int_operand"))))
3303 (clobber (reg:SI T_REG))]
3306 "&& can_create_pseudo_p ()"
3307 [(parallel [(set (match_dup 0)
3308 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
3309 (and:SI (reg:SI T_REG) (const_int 1))))
3310 (clobber (reg:SI T_REG))])]
3312 /* We don't care about the result of the left shift, only the T_REG. */
3313 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[3]));
3316 (define_insn_and_split "*rotcl"
3317 [(set (match_operand:SI 0 "arith_reg_dest")
3318 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
3319 (match_operand 2 "const_int_operand"))
3320 (zero_extract:SI (match_operand:SI 3 "arith_reg_operand")
3322 (match_operand 4 "const_int_operand"))))
3323 (clobber (reg:SI T_REG))]
3326 "&& can_create_pseudo_p ()"
3327 [(parallel [(set (match_dup 0)
3328 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
3329 (and:SI (match_dup 5) (const_int 1))))
3330 (clobber (reg:SI T_REG))])]
3332 if (TARGET_SH2A && satisfies_constraint_K03 (operands[4]))
3334 /* On SH2A we can use the bld insn to zero extract a single bit
3336 operands[5] = get_t_reg_rtx ();
3337 emit_insn (gen_bldsi_reg (operands[3], operands[4]));
3341 /* If we can't use the bld insn we have to emit a tst + nott sequence
3342 to get the extracted bit into the T bit.
3343 This will probably be worse than pre-shifting the operand. */
3344 operands[5] = gen_reg_rtx (SImode);
3345 emit_insn (gen_lshrsi3 (operands[5], operands[3], operands[4]));
3349 ;; rotcr combine bridge pattern which will make combine try out more
3350 ;; complex patterns.
3351 (define_insn_and_split "*rotcr"
3352 [(set (match_operand:SI 0 "arith_reg_dest")
3353 (ashift:SI (match_operand 1 "treg_set_expr") (const_int 31)))]
3354 "TARGET_SH1 && can_create_pseudo_p ()"
3357 [(parallel [(set (match_dup 0)
3358 (ior:SI (lshiftrt:SI (const_int 0) (const_int 1))
3359 (ashift:SI (match_dup 1) (const_int 31))))
3360 (clobber (reg:SI T_REG))])])
3362 (define_insn_and_split "*rotcr"
3363 [(set (match_operand:SI 0 "arith_reg_dest")
3364 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand")
3365 (const_int -2147483648)) ;; 0xffffffff80000000
3366 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand")
3368 (clobber (reg:SI T_REG))]
3371 "&& can_create_pseudo_p ()"
3374 rtx tmp = gen_reg_rtx (SImode);
3375 emit_insn (gen_shll (tmp, operands[1]));
3376 emit_insn (gen_rotcr (operands[0], operands[2], get_t_reg_rtx ()));
3380 (define_insn_and_split "*rotcr"
3381 [(set (match_operand:SI 0 "arith_reg_dest")
3382 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
3384 (const_int -2147483648))) ;; 0xffffffff80000000
3385 (clobber (reg:SI T_REG))]
3388 "&& can_create_pseudo_p ()"
3391 emit_insn (gen_sett ());
3392 emit_insn (gen_rotcr (operands[0], operands[1], get_t_reg_rtx ()));
3396 ;; rotcr combine patterns for rotating in the negated T_REG value.
3397 (define_insn_and_split "*rotcr_neg_t"
3398 [(set (match_operand:SI 0 "arith_reg_dest")
3399 (ior:SI (match_operand:SI 1 "negt_reg_shl31_operand")
3400 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand")
3401 (match_operand:SI 3 "const_int_operand"))))
3402 (clobber (reg:SI T_REG))]
3405 "&& can_create_pseudo_p ()"
3406 [(parallel [(set (match_dup 0)
3407 (ior:SI (lshiftrt:SI (match_dup 2) (match_dup 3))
3408 (ashift:SI (reg:SI T_REG) (const_int 31))))
3409 (clobber (reg:SI T_REG))])]
3411 emit_insn (gen_nott (get_t_reg_rtx ()));
3414 (define_insn_and_split "*rotcr_neg_t"
3415 [(set (match_operand:SI 0 "arith_reg_dest")
3416 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
3417 (match_operand:SI 2 "const_int_operand"))
3418 (match_operand:SI 3 "negt_reg_shl31_operand")))
3419 (clobber (reg:SI T_REG))]
3422 "&& can_create_pseudo_p ()"
3423 [(parallel [(set (match_dup 0)
3424 (ior:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
3425 (ashift:SI (reg:SI T_REG) (const_int 31))))
3426 (clobber (reg:SI T_REG))])]
3428 emit_insn (gen_nott (get_t_reg_rtx ()));
3431 ;; rotcl combine patterns for rotating in the negated T_REG value.
3432 ;; For some strange reason these have to be specified as splits which combine
3433 ;; will pick up. If they are specified as insn_and_split like the
3434 ;; *rotcr_neg_t patterns above, combine would recognize them successfully
3435 ;; but not emit them on non-SH2A targets.
3437 [(set (match_operand:SI 0 "arith_reg_dest")
3438 (ior:SI (match_operand:SI 1 "negt_reg_operand")
3439 (ashift:SI (match_operand:SI 2 "arith_reg_operand")
3440 (match_operand:SI 3 "const_int_operand"))))]
3442 [(set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))
3443 (parallel [(set (match_dup 0)
3444 (ior:SI (ashift:SI (match_dup 2) (match_dup 3))
3445 (and:SI (reg:SI T_REG) (const_int 1))))
3446 (clobber (reg:SI T_REG))])])
3449 [(set (match_operand:SI 0 "arith_reg_dest")
3450 (ior:SI (ashift:SI (match_operand:SI 2 "arith_reg_operand")
3451 (match_operand:SI 3 "const_int_operand"))
3452 (match_operand:SI 1 "negt_reg_operand")))]
3454 [(set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))
3455 (parallel [(set (match_dup 0)
3456 (ior:SI (ashift:SI (match_dup 2) (match_dup 3))
3457 (and:SI (reg:SI T_REG) (const_int 1))))
3458 (clobber (reg:SI T_REG))])])
3460 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3461 ;; SImode shift left
3463 (define_expand "ashlsi3"
3464 [(set (match_operand:SI 0 "arith_reg_operand" "")
3465 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
3466 (match_operand:SI 2 "shift_count_operand" "")))]
3470 && CONST_INT_P (operands[2]) && sh_dynamicalize_shift_p (operands[2]))
3472 /* Don't force the constant into a reg yet. Some other optimizations
3473 might not see through the reg that holds the shift count. */
3476 /* If the ashlsi3_* insn is going to clobber the T_REG it must be
3478 if (CONST_INT_P (operands[2])
3479 && sh_ashlsi_clobbers_t_reg_p (operands[2])
3480 && ! sh_dynamicalize_shift_p (operands[2]))
3482 emit_insn (gen_ashlsi3_n_clobbers_t (operands[0], operands[1],
3487 /* Expand a library call for the dynamic shift. */
3488 if (!CONST_INT_P (operands[2]) && !TARGET_DYNSHIFT)
3490 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
3491 rtx funcaddr = gen_reg_rtx (Pmode);
3492 rtx lab = function_symbol (funcaddr, "__ashlsi3_r0", SFUNC_STATIC).lab;
3493 emit_insn (gen_ashlsi3_d_call (operands[0], operands[2], funcaddr, lab));
3499 (define_insn "ashlsi3_k"
3500 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
3501 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0")
3502 (match_operand:SI 2 "p27_shift_count_operand" "M,P27")))]
3507 [(set_attr "type" "arith")])
3509 (define_insn_and_split "ashlsi3_d"
3510 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3511 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
3512 (match_operand:SI 2 "shift_count_operand" "r")))]
3515 "&& CONST_INT_P (operands[2]) && ! sh_dynamicalize_shift_p (operands[2])
3516 && ! sh_ashlsi_clobbers_t_reg_p (operands[2])"
3519 if (satisfies_constraint_P27 (operands[2]))
3521 emit_insn (gen_ashlsi3_k (operands[0], operands[1], operands[2]));
3524 else if (! satisfies_constraint_P27 (operands[2]))
3526 /* This must happen before reload, otherwise the constant will be moved
3527 into a register due to the "r" constraint, after which this split
3528 cannot be done anymore.
3529 Unfortunately the move insn will not always be eliminated.
3530 Also, here we must not create a shift sequence that clobbers the
3532 emit_move_insn (operands[0], operands[1]);
3533 gen_shifty_op (ASHIFT, operands);
3539 [(set_attr "type" "dyn_shift")])
3541 ;; If dynamic shifts are not available use a library function.
3542 ;; By specifying the pattern we reduce the number of call clobbered regs.
3543 ;; In order to make combine understand the truncation of the shift amount
3544 ;; operand we have to allow it to use pseudo regs for the shift operands.
3545 (define_insn "ashlsi3_d_call"
3546 [(set (match_operand:SI 0 "arith_reg_dest" "=z,z")
3547 (ashift:SI (reg:SI R4_REG)
3548 (and:SI (match_operand:SI 1 "arith_reg_operand" "z,z")
3550 (use (match_operand:SI 2 "arith_reg_operand" "r,r"))
3551 (use (match_operand 3 "" "Z,Ccl"))
3552 (clobber (reg:SI T_REG))
3553 (clobber (reg:SI PR_REG))]
3554 "TARGET_SH1 && !TARGET_DYNSHIFT"
3558 [(set_attr "type" "sfunc")
3559 (set_attr "needs_delay_slot" "yes")])
3561 (define_insn_and_split "ashlsi3_n"
3562 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3563 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
3564 (match_operand:SI 2 "not_p27_shift_count_operand" "")))]
3565 "TARGET_SH1 && ! sh_ashlsi_clobbers_t_reg_p (operands[2])"
3567 "&& (reload_completed
3568 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
3571 if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
3573 /* If this pattern was picked and dynamic shifts are supported, switch
3574 to dynamic shift pattern before reload. */
3575 operands[2] = force_reg (SImode, operands[2]);
3576 emit_insn (gen_ashlsi3_d (operands[0], operands[1], operands[2]));
3579 gen_shifty_op (ASHIFT, operands);
3584 (define_insn_and_split "ashlsi3_n_clobbers_t"
3585 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3586 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
3587 (match_operand:SI 2 "not_p27_shift_count_operand" "")))
3588 (clobber (reg:SI T_REG))]
3589 "TARGET_SH1 && sh_ashlsi_clobbers_t_reg_p (operands[2])"
3591 "&& (reload_completed || INTVAL (operands[2]) == 31
3592 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
3595 if (INTVAL (operands[2]) == 31)
3597 /* If the shift amount is 31 we split into a different sequence before
3598 reload so that it gets a chance to allocate R0 for the sequence.
3599 If it fails to do so (due to pressure on R0), it will take one insn
3600 more for the and. */
3601 emit_insn (gen_andsi3 (operands[0], operands[1], const1_rtx));
3602 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
3604 else if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
3606 /* If this pattern was picked and dynamic shifts are supported, switch
3607 to dynamic shift pattern before reload. */
3608 operands[2] = force_reg (SImode, operands[2]);
3609 emit_insn (gen_ashlsi3_d (operands[0], operands[1], operands[2]));
3612 gen_shifty_op (ASHIFT, operands);
3618 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3619 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") (const_int 1)))
3621 (lt:SI (match_dup 1) (const_int 0)))]
3624 [(set_attr "type" "arith")])
3626 (define_insn "*ashlsi_c_void"
3627 [(set (reg:SI T_REG)
3628 (lt:SI (match_operand:SI 0 "arith_reg_operand" "r") (const_int 0)))
3629 (clobber (match_scratch:SI 1 "=0"))]
3630 "TARGET_SH1 && cse_not_expected"
3632 [(set_attr "type" "arith")])
3635 [(set (match_operand:SI 0 "arith_reg_dest" "") (const_int 0))
3637 (gt:SI (match_dup 0) (match_operand:SI 1 "arith_reg_operand" "")))]
3639 && peep2_reg_dead_p (2, operands[0])
3640 && peep2_reg_dead_p (2, operands[1])"
3643 emit_insn (gen_shll (operands[1], operands[1]));
3647 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3648 ;; HImode shift left
3650 (define_expand "ashlhi3"
3651 [(parallel [(set (match_operand:HI 0 "arith_reg_operand" "")
3652 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "")
3653 (match_operand:SI 2 "nonmemory_operand" "")))
3654 (clobber (reg:SI T_REG))])]
3657 if (!CONST_INT_P (operands[2]))
3659 /* It may be possible to call gen_ashlhi3 directly with more generic
3660 operands. Make sure operands[1] is a HImode register here. */
3661 if (!arith_reg_operand (operands[1], HImode))
3662 operands[1] = copy_to_mode_reg (HImode, operands[1]);
3665 (define_insn "ashlhi3_k"
3666 [(set (match_operand:HI 0 "arith_reg_dest" "=r,r")
3667 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0,0")
3668 (match_operand:HI 2 "const_int_operand" "M,P27")))]
3669 "TARGET_SH1 && satisfies_constraint_P27 (operands[2])"
3673 [(set_attr "type" "arith")])
3675 (define_insn_and_split "*ashlhi3_n"
3676 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
3677 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0")
3678 (match_operand:HI 2 "const_int_operand" "n")))
3679 (clobber (reg:SI T_REG))]
3682 "&& reload_completed"
3683 [(use (reg:SI R0_REG))]
3685 gen_shifty_hi_op (ASHIFT, operands);
3689 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3690 ;; DImode shift left
3692 (define_expand "ashldi3"
3693 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
3694 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "")
3695 (match_operand:DI 2 "immediate_operand" "")))
3696 (clobber (reg:SI T_REG))])]
3699 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1)
3701 emit_insn (gen_ashldi3_k (operands[0], operands[1]));
3704 else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 32)
3706 emit_insn (gen_ashldi3_std (operands[0], operands[1], operands[2]));
3713 ;; Expander for DImode shift left with SImode operations.
3714 (define_expand "ashldi3_std"
3715 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3716 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
3717 (match_operand:DI 2 "const_int_operand" "n")))]
3718 "TARGET_SH1 && INTVAL (operands[2]) < 32"
3720 rtx low_src = gen_lowpart (SImode, operands[1]);
3721 rtx high_src = gen_highpart (SImode, operands[1]);
3722 rtx dst = gen_reg_rtx (DImode);
3723 rtx low_dst = gen_lowpart (SImode, dst);
3724 rtx high_dst = gen_highpart (SImode, dst);
3725 rtx tmp0 = gen_reg_rtx (SImode);
3726 rtx tmp1 = gen_reg_rtx (SImode);
3728 emit_insn (gen_lshrsi3 (tmp0, low_src, GEN_INT (32 - INTVAL (operands[2]))));
3729 emit_insn (gen_ashlsi3 (low_dst, low_src, operands[2]));
3730 emit_insn (gen_ashlsi3 (tmp1, high_src, operands[2]));
3731 emit_insn (gen_iorsi3 (high_dst, tmp0, tmp1));
3732 emit_move_insn (operands[0], dst);
3736 (define_insn_and_split "ashldi3_k"
3737 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3738 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
3740 (clobber (reg:SI T_REG))]
3743 "&& reload_completed"
3746 rtx high = gen_highpart (SImode, operands[0]);
3747 rtx low = gen_lowpart (SImode, operands[0]);
3748 emit_insn (gen_shll (low, low));
3749 emit_insn (gen_rotcl (high, high, get_t_reg_rtx ()));
3753 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3754 ;; SImode arithmetic shift right
3756 ;; We can't do HImode right shifts correctly unless we start out with an
3757 ;; explicit zero / sign extension; doing that would result in worse overall
3758 ;; code, so just let the machine independent code widen the mode.
3759 ;; That's why we don't have ashrhi3_k / lshrhi3_k / lshrhi3_m / lshrhi3 .
3761 (define_expand "ashrsi3"
3762 [(parallel [(set (match_operand:SI 0 "arith_reg_dest" "")
3763 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
3764 (match_operand:SI 2 "nonmemory_operand" "")))
3765 (clobber (reg:SI T_REG))])]
3768 if (expand_ashiftrt (operands))
3775 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3776 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3779 (and:SI (match_dup 1) (const_int 1)))]
3782 [(set_attr "type" "arith")])
3784 (define_insn "ashrsi3_k"
3785 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3786 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3787 (match_operand:SI 2 "const_int_operand" "M")))
3788 (clobber (reg:SI T_REG))]
3789 "TARGET_SH1 && INTVAL (operands[2]) == 1"
3791 [(set_attr "type" "arith")])
3793 (define_insn_and_split "ashrsi2_16"
3794 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3795 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
3800 [(set (match_dup 0) (rotate:SI (match_dup 1) (const_int 16)))
3801 (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
3803 operands[2] = gen_lowpart (HImode, operands[0]);
3806 (define_insn_and_split "ashrsi2_31"
3807 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3808 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3810 (clobber (reg:SI T_REG))]
3816 emit_insn (gen_shll (operands[0], operands[1]));
3817 emit_insn (gen_mov_neg_si_t (operands[0], get_t_reg_rtx ()));
3821 ;; If the shift amount is changed by combine it will try to plug the
3822 ;; use on the symbol of the library function and the PR clobber.
3823 (define_insn_and_split "*ashrsi2_31"
3824 [(set (match_operand:SI 0 "arith_reg_dest")
3825 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand")
3827 (clobber (reg:SI T_REG))
3828 (clobber (reg:SI PR_REG))
3829 (use (match_operand:SI 2 "symbol_ref_operand"))]
3833 [(parallel [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 31)))
3834 (clobber (reg:SI T_REG))])])
3836 (define_insn "ashrsi3_d"
3837 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3838 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3839 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
3842 [(set_attr "type" "dyn_shift")])
3844 (define_insn "ashrsi3_n"
3845 [(set (reg:SI R4_REG)
3846 (ashiftrt:SI (reg:SI R4_REG)
3847 (match_operand:SI 0 "const_int_operand" "i,i")))
3848 (clobber (reg:SI T_REG))
3849 (clobber (reg:SI PR_REG))
3850 (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
3851 (use (match_operand 2 "" "Z,Ccl"))]
3856 [(set_attr "type" "sfunc")
3857 (set_attr "needs_delay_slot" "yes")])
3859 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3860 ;; DImode arithmetic shift right
3862 (define_expand "ashrdi3"
3863 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
3864 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
3865 (match_operand:DI 2 "immediate_operand" "")))
3866 (clobber (reg:SI T_REG))])]
3869 if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 1)
3873 (define_insn_and_split "ashrdi3_k"
3874 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3875 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
3877 (clobber (reg:SI T_REG))]
3880 "&& reload_completed"
3883 rtx high = gen_highpart (SImode, operands[0]);
3884 rtx low = gen_lowpart (SImode, operands[0]);
3885 emit_insn (gen_shar (high, high));
3886 emit_insn (gen_rotcr (low, low, get_t_reg_rtx ()));
3890 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3891 ;; SImode logical shift right
3893 (define_expand "lshrsi3"
3894 [(set (match_operand:SI 0 "arith_reg_dest" "")
3895 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
3896 (match_operand:SI 2 "shift_count_operand" "")))]
3899 /* If a dynamic shift is supposed to be used, expand the lshrsi3_d insn
3900 here, otherwise the pattern will never match due to the shift amount reg
3903 && CONST_INT_P (operands[2]) && sh_dynamicalize_shift_p (operands[2]))
3905 /* Don't force the constant into a reg yet. Some other optimizations
3906 might not see through the reg that holds the shift count. */
3907 if (sh_lshrsi_clobbers_t_reg_p (operands[2]))
3908 emit_insn (gen_lshrsi3_n_clobbers_t (operands[0], operands[1], operands[2]));
3910 emit_insn (gen_lshrsi3_n (operands[0], operands[1], operands[2]));
3914 if (TARGET_DYNSHIFT && ! CONST_INT_P (operands[2]))
3916 rtx neg_count = gen_reg_rtx (SImode);
3917 emit_insn (gen_negsi2 (neg_count, operands[2]));
3918 emit_insn (gen_lshrsi3_d (operands[0], operands[1], neg_count));
3922 /* If the lshrsi3_* insn is going to clobber the T_REG it must be
3924 if (CONST_INT_P (operands[2])
3925 && sh_lshrsi_clobbers_t_reg_p (operands[2])
3926 && ! sh_dynamicalize_shift_p (operands[2]))
3928 emit_insn (gen_lshrsi3_n_clobbers_t (operands[0], operands[1],
3933 /* Expand a library call for the dynamic shift. */
3934 if (!CONST_INT_P (operands[2]) && !TARGET_DYNSHIFT)
3936 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
3937 rtx funcaddr = gen_reg_rtx (Pmode);
3938 rtx lab = function_symbol (funcaddr, "__lshrsi3_r0", SFUNC_STATIC).lab;
3939 emit_insn (gen_lshrsi3_d_call (operands[0], operands[2], funcaddr, lab));
3944 (define_insn "lshrsi3_k"
3945 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3946 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3947 (match_operand:SI 2 "p27_rshift_count_operand" "P27")))]
3950 [(set_attr "type" "arith")])
3952 (define_insn_and_split "lshrsi3_d"
3953 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3954 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3955 (neg:SI (match_operand:SI 2 "shift_count_operand" "r"))))]
3958 "&& CONST_INT_P (operands[2]) && ! sh_dynamicalize_shift_p (operands[2])
3959 && ! sh_lshrsi_clobbers_t_reg_p (operands[2])"
3962 /* The shift count const_int is a negative value for all dynamic
3963 right shift insns. */
3964 operands[2] = GEN_INT (- INTVAL (operands[2]));
3966 if (satisfies_constraint_P27 (operands[2]))
3968 /* This will not be done for a shift amount of 1, because it would
3969 clobber the T_REG. */
3970 emit_insn (gen_lshrsi3_k (operands[0], operands[1], operands[2]));
3973 else if (! satisfies_constraint_P27 (operands[2]))
3975 /* This must happen before reload, otherwise the constant will be moved
3976 into a register due to the "r" constraint, after which this split
3977 cannot be done anymore.
3978 Unfortunately the move insn will not always be eliminated.
3979 Also, here we must not create a shift sequence that clobbers the
3981 emit_move_insn (operands[0], operands[1]);
3982 gen_shifty_op (LSHIFTRT, operands);
3988 [(set_attr "type" "dyn_shift")])
3990 ;; If dynamic shifts are not available use a library function.
3991 ;; By specifying the pattern we reduce the number of call clobbered regs.
3992 ;; In order to make combine understand the truncation of the shift amount
3993 ;; operand we have to allow it to use pseudo regs for the shift operands.
3994 (define_insn "lshrsi3_d_call"
3995 [(set (match_operand:SI 0 "arith_reg_dest" "=z,z")
3996 (lshiftrt:SI (reg:SI R4_REG)
3997 (and:SI (match_operand:SI 1 "arith_reg_operand" "z,z")
3999 (use (match_operand:SI 2 "arith_reg_operand" "r,r"))
4000 (use (match_operand 3 "" "Z,Ccl"))
4001 (clobber (reg:SI T_REG))
4002 (clobber (reg:SI PR_REG))]
4003 "TARGET_SH1 && !TARGET_DYNSHIFT"
4007 [(set_attr "type" "sfunc")
4008 (set_attr "needs_delay_slot" "yes")])
4010 (define_insn_and_split "lshrsi3_n"
4011 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4012 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4013 (match_operand:SI 2 "not_p27_rshift_count_operand")))]
4014 "TARGET_SH1 && ! sh_lshrsi_clobbers_t_reg_p (operands[2])"
4016 "&& (reload_completed
4017 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
4020 if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
4022 /* If this pattern was picked and dynamic shifts are supported, switch
4023 to dynamic shift pattern before reload. */
4024 operands[2] = GEN_INT (- INTVAL (operands[2]));
4025 emit_insn (gen_lshrsi3_d (operands[0], operands[1], operands[2]));
4028 gen_shifty_op (LSHIFTRT, operands);
4033 ;; The lshrsi3_n_clobbers_t pattern also works as a simplified version of
4034 ;; the shlr pattern.
4035 (define_insn_and_split "lshrsi3_n_clobbers_t"
4036 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4037 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4038 (match_operand:SI 2 "not_p27_rshift_count_operand")))
4039 (clobber (reg:SI T_REG))]
4040 "TARGET_SH1 && sh_lshrsi_clobbers_t_reg_p (operands[2])"
4042 "&& (reload_completed || INTVAL (operands[2]) == 31
4043 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
4046 if (INTVAL (operands[2]) == 31)
4048 emit_insn (gen_shll (operands[0], operands[1]));
4049 emit_insn (gen_movt (operands[0], get_t_reg_rtx ()));
4051 else if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
4053 /* If this pattern was picked and dynamic shifts are supported, switch
4054 to dynamic shift pattern before reload. */
4055 operands[2] = GEN_INT (- INTVAL (operands[2]));
4056 emit_insn (gen_lshrsi3_d (operands[0], operands[1], operands[2]));
4059 gen_shifty_op (LSHIFTRT, operands);
4065 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4066 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4069 (and:SI (match_dup 1) (const_int 1)))]
4072 [(set_attr "type" "arith")])
4074 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4075 ;; DImode logical shift right
4077 (define_expand "lshrdi3"
4078 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
4079 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
4080 (match_operand:DI 2 "immediate_operand" "")))
4081 (clobber (reg:SI T_REG))])]
4084 if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 1)
4088 (define_insn_and_split "lshrdi3_k"
4089 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
4090 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
4092 (clobber (reg:SI T_REG))]
4095 "&& reload_completed"
4098 rtx high = gen_highpart (SImode, operands[0]);
4099 rtx low = gen_lowpart (SImode, operands[0]);
4100 emit_insn (gen_shlr (high, high));
4101 emit_insn (gen_rotcr (low, low, get_t_reg_rtx ()));
4105 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4106 ;; Combined left/right shifts
4109 [(set (match_operand:SI 0 "register_operand" "")
4110 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
4111 (match_operand:SI 2 "const_int_operand" ""))
4112 (match_operand:SI 3 "const_int_operand" "")))]
4113 "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32"
4114 [(use (reg:SI R0_REG))]
4116 if (gen_shl_and (operands[0], operands[2], operands[3], operands[1]))
4122 [(set (match_operand:SI 0 "register_operand" "")
4123 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
4124 (match_operand:SI 2 "const_int_operand" ""))
4125 (match_operand:SI 3 "const_int_operand" "")))
4126 (clobber (reg:SI T_REG))]
4127 "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32"
4128 [(use (reg:SI R0_REG))]
4130 if (gen_shl_and (operands[0], operands[2], operands[3], operands[1]))
4136 [(set (match_operand:SI 0 "register_operand" "=r")
4137 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
4138 (match_operand:SI 2 "const_int_operand" "n"))
4139 (match_operand:SI 3 "const_int_operand" "n")))
4140 (clobber (reg:SI T_REG))]
4141 "TARGET_SH1 && shl_and_kind (operands[2], operands[3], 0) == 1"
4143 [(set (attr "length")
4144 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
4146 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
4148 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
4150 (eq (symbol_ref "shl_and_length (insn)") (const_int 5))
4152 (eq (symbol_ref "shl_and_length (insn)") (const_int 6))
4154 (eq (symbol_ref "shl_and_length (insn)") (const_int 7))
4156 (eq (symbol_ref "shl_and_length (insn)") (const_int 8))
4157 (const_string "16")]
4158 (const_string "18")))
4159 (set_attr "type" "arith")])
4162 [(set (match_operand:SI 0 "register_operand" "=z")
4163 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
4164 (match_operand:SI 2 "const_int_operand" "n"))
4165 (match_operand:SI 3 "const_int_operand" "n")))
4166 (clobber (reg:SI T_REG))]
4167 "TARGET_SH1 && shl_and_kind (operands[2], operands[3], 0) == 2"
4169 [(set (attr "length")
4170 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
4172 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
4174 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
4176 (const_string "10")))
4177 (set_attr "type" "arith")])
4179 ;; shift left / and combination with a scratch register: The combine pass
4180 ;; does not accept the individual instructions, even though they are
4181 ;; cheap. But it needs a precise description so that it is usable after
4183 (define_insn "and_shl_scratch"
4184 [(set (match_operand:SI 0 "register_operand" "=r,&r")
4188 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
4189 (match_operand:SI 2 "const_int_operand" "N,n"))
4190 (match_operand:SI 3 "" "0,r"))
4191 (match_operand:SI 4 "const_int_operand" "n,n"))
4192 (match_operand:SI 5 "const_int_operand" "n,n")))
4193 (clobber (reg:SI T_REG))]
4196 [(set (attr "length")
4197 (cond [(eq (symbol_ref "shl_and_scr_length (insn)") (const_int 2))
4199 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 3))
4201 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 4))
4203 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 5))
4204 (const_string "10")]
4205 (const_string "12")))
4206 (set_attr "type" "arith")])
4209 [(set (match_operand:SI 0 "register_operand" "")
4213 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
4214 (match_operand:SI 2 "const_int_operand" ""))
4215 (match_operand:SI 3 "register_operand" ""))
4216 (match_operand:SI 4 "const_int_operand" ""))
4217 (match_operand:SI 5 "const_int_operand" "")))
4218 (clobber (reg:SI T_REG))]
4220 [(use (reg:SI R0_REG))]
4222 rtx and_source = operands[rtx_equal_p (operands[0], operands[1]) ? 3 : 1];
4224 if (INTVAL (operands[2]))
4226 gen_shifty_op (LSHIFTRT, operands);
4228 emit_insn (gen_andsi3 (operands[0], operands[0], and_source));
4229 operands[2] = operands[4];
4230 gen_shifty_op (ASHIFT, operands);
4231 if (INTVAL (operands[5]))
4233 operands[2] = operands[5];
4234 gen_shifty_op (LSHIFTRT, operands);
4239 ;; signed left/right shift combination.
4241 [(set (match_operand:SI 0 "register_operand" "")
4243 (ashift:SI (match_operand:SI 1 "register_operand" "")
4244 (match_operand:SI 2 "const_int_operand" ""))
4245 (match_operand:SI 3 "const_int_operand" "")
4247 (clobber (reg:SI T_REG))]
4249 [(use (reg:SI R0_REG))]
4251 if (gen_shl_sext (operands[0], operands[2], operands[3], operands[1]))
4256 (define_insn "shl_sext_ext"
4257 [(set (match_operand:SI 0 "register_operand" "=r")
4259 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4260 (match_operand:SI 2 "const_int_operand" "n"))
4261 (match_operand:SI 3 "const_int_operand" "n")
4263 (clobber (reg:SI T_REG))]
4264 "TARGET_SH1 && (unsigned)shl_sext_kind (operands[2], operands[3], 0) - 1 < 5"
4266 [(set (attr "length")
4267 (cond [(match_test "shl_sext_length (insn)")
4269 (eq (symbol_ref "shl_sext_length (insn)") (const_int 2))
4271 (eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
4273 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
4275 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
4277 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
4279 (eq (symbol_ref "shl_sext_length (insn)") (const_int 7))
4281 (eq (symbol_ref "shl_sext_length (insn)") (const_int 8))
4282 (const_string "16")]
4283 (const_string "18")))
4284 (set_attr "type" "arith")])
4286 (define_insn "shl_sext_sub"
4287 [(set (match_operand:SI 0 "register_operand" "=z")
4289 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4290 (match_operand:SI 2 "const_int_operand" "n"))
4291 (match_operand:SI 3 "const_int_operand" "n")
4293 (clobber (reg:SI T_REG))]
4294 "TARGET_SH1 && (shl_sext_kind (operands[2], operands[3], 0) & ~1) == 6"
4296 [(set (attr "length")
4297 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
4299 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
4301 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
4303 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
4304 (const_string "12")]
4305 (const_string "14")))
4306 (set_attr "type" "arith")])
4308 ;; The xtrct_left and xtrct_right patterns are used in expansions of DImode
4309 ;; shifts by 16, and allow the xtrct instruction to be generated from C
4311 (define_insn "xtrct_left"
4312 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4313 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
4315 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand" "0")
4319 [(set_attr "type" "arith")])
4321 (define_insn "xtrct_right"
4322 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4323 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4325 (ashift:SI (match_operand:SI 2 "arith_reg_operand" "r")
4329 [(set_attr "type" "arith")])
4331 ;; -------------------------------------------------------------------------
4333 ;; -------------------------------------------------------------------------
4336 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4337 (neg:SI (plus:SI (reg:SI T_REG)
4338 (match_operand:SI 1 "arith_reg_operand" "r"))))
4340 (ne:SI (ior:SI (reg:SI T_REG) (match_dup 1))
4344 [(set_attr "type" "arith")])
4346 ;; A simplified version of the negc insn, where the exact value of the
4347 ;; T bit doesn't matter. This is easier for combine to pick up.
4348 ;; Notice that '0 - x - 1' is the same as '~x', thus we don't specify
4349 ;; extra patterns for this case.
4350 (define_insn_and_split "*negc"
4351 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4352 (minus:SI (neg:SI (match_operand:SI 1 "arith_reg_operand" "r"))
4353 (match_operand 2 "treg_set_expr")))
4354 (clobber (reg:SI T_REG))]
4355 "TARGET_SH1 && can_create_pseudo_p ()"
4360 sh_split_treg_set_expr (operands[2], curr_insn);
4361 emit_insn (gen_negc (operands[0], operands[1]));
4365 ;; Don't split into individual negc insns immediately so that neg:DI (abs:DI)
4367 (define_insn_and_split "negdi2"
4368 [(set (match_operand:DI 0 "arith_reg_dest")
4369 (neg:DI (match_operand:DI 1 "arith_reg_operand")))
4370 (clobber (reg:SI T_REG))]
4373 "&& can_create_pseudo_p ()"
4376 emit_insn (gen_clrt ());
4377 emit_insn (gen_negc (gen_lowpart (SImode, operands[0]),
4378 gen_lowpart (SImode, operands[1])));
4379 emit_insn (gen_negc (gen_highpart (SImode, operands[0]),
4380 gen_highpart (SImode, operands[1])));
4384 (define_insn "negsi2"
4385 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4386 (neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
4389 [(set_attr "type" "arith")])
4391 (define_insn_and_split "one_cmplsi2"
4392 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4393 (not:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
4396 "&& can_create_pseudo_p ()"
4397 [(set (reg:SI T_REG) (ge:SI (match_dup 1) (const_int 0)))
4398 (set (match_dup 0) (reg:SI T_REG))]
4401 If the result of 'unsigned int <= 0x7FFFFFFF' ends up as the following
4404 (set (reg0) (not:SI (reg0) (reg1)))
4405 (parallel [(set (reg2) (lshiftrt:SI (reg0) (const_int 31)))
4406 (clobber (reg:SI T_REG))])
4408 ... match and combine the sequence manually in the split pass after the
4409 combine pass. Notice that combine does try the target pattern of this
4410 split, but if the pattern is added it interferes with other patterns, in
4411 particular with the div0s comparisons.
4412 This could also be done with a peephole but doing it here before register
4413 allocation can save one temporary.
4414 When we're here, the not:SI pattern obviously has been matched already
4415 and we only have to see whether the following insn is the left shift. */
4417 rtx_insn *i = next_nonnote_insn_bb (curr_insn);
4418 if (i == NULL_RTX || !NONJUMP_INSN_P (i))
4421 rtx p = PATTERN (i);
4422 if (GET_CODE (p) != PARALLEL || XVECLEN (p, 0) != 2)
4425 rtx p0 = XVECEXP (p, 0, 0);
4426 rtx p1 = XVECEXP (p, 0, 1);
4428 if (/* (set (reg2) (lshiftrt:SI (reg0) (const_int 31))) */
4429 GET_CODE (p0) == SET
4430 && GET_CODE (XEXP (p0, 1)) == LSHIFTRT
4431 && REG_P (XEXP (XEXP (p0, 1), 0))
4432 && REGNO (XEXP (XEXP (p0, 1), 0)) == REGNO (operands[0])
4433 && CONST_INT_P (XEXP (XEXP (p0, 1), 1))
4434 && INTVAL (XEXP (XEXP (p0, 1), 1)) == 31
4436 /* (clobber (reg:SI T_REG)) */
4437 && GET_CODE (p1) == CLOBBER && REG_P (XEXP (p1, 0))
4438 && REGNO (XEXP (p1, 0)) == T_REG)
4440 operands[0] = XEXP (p0, 0);
4441 set_insn_deleted (i);
4446 [(set_attr "type" "arith")])
4448 (define_insn_and_split "abs<mode>2"
4449 [(set (match_operand:SIDI 0 "arith_reg_dest")
4450 (abs:SIDI (match_operand:SIDI 1 "arith_reg_operand")))
4451 (clobber (reg:SI T_REG))]
4454 "&& can_create_pseudo_p ()"
4457 if (<MODE>mode == SImode)
4458 emit_insn (gen_cmpgesi_t (operands[1], const0_rtx));
4461 rtx high_src = gen_highpart (SImode, operands[1]);
4462 emit_insn (gen_cmpgesi_t (high_src, const0_rtx));
4465 emit_insn (gen_neg<mode>_cond (operands[0], operands[1], operands[1],
4470 (define_insn_and_split "*negabs<mode>2"
4471 [(set (match_operand:SIDI 0 "arith_reg_dest")
4472 (neg:SIDI (abs:SIDI (match_operand:SIDI 1 "arith_reg_operand"))))
4473 (clobber (reg:SI T_REG))]
4476 "&& can_create_pseudo_p ()"
4479 if (<MODE>mode == SImode)
4480 emit_insn (gen_cmpgesi_t (operands[1], const0_rtx));
4483 rtx high_src = gen_highpart (SImode, operands[1]);
4484 emit_insn (gen_cmpgesi_t (high_src, const0_rtx));
4487 emit_insn (gen_neg<mode>_cond (operands[0], operands[1], operands[1],
4492 ;; The SH4 202 can do zero-offset branches without pipeline stalls.
4493 ;; This can be used as some kind of conditional execution, which is useful
4495 ;; Actually the instruction scheduling should decide whether to use a
4496 ;; zero-offset branch or not for any generic case involving a single
4497 ;; instruction on SH4 202.
4498 (define_insn_and_split "negsi_cond"
4499 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
4501 (eq:SI (reg:SI T_REG) (match_operand:SI 3 "const_int_operand" "M,N"))
4502 (match_operand:SI 1 "arith_reg_operand" "0,0")
4503 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r,r"))))]
4504 "TARGET_SH1 && TARGET_ZDCBRANCH"
4506 static const char* alt[] =
4516 return alt[which_alternative];
4518 "TARGET_SH1 && ! TARGET_ZDCBRANCH"
4521 rtx_code_label *skip_neg_label = gen_label_rtx ();
4523 emit_move_insn (operands[0], operands[1]);
4525 emit_jump_insn (INTVAL (operands[3])
4526 ? gen_branch_true (skip_neg_label)
4527 : gen_branch_false (skip_neg_label));
4529 emit_label_after (skip_neg_label,
4530 emit_insn (gen_negsi2 (operands[0], operands[1])));
4533 [(set_attr "type" "arith") ;; poor approximation
4534 (set_attr "length" "4")])
4536 (define_insn_and_split "negdi_cond"
4537 [(set (match_operand:DI 0 "arith_reg_dest")
4539 (eq:SI (reg:SI T_REG) (match_operand:SI 3 "const_int_operand"))
4540 (match_operand:DI 1 "arith_reg_operand")
4541 (neg:DI (match_operand:DI 2 "arith_reg_operand"))))
4542 (clobber (reg:SI T_REG))]
4545 "&& can_create_pseudo_p ()"
4548 rtx_code_label *skip_neg_label = gen_label_rtx ();
4550 emit_move_insn (operands[0], operands[1]);
4552 emit_jump_insn (INTVAL (operands[3])
4553 ? gen_branch_true (skip_neg_label)
4554 : gen_branch_false (skip_neg_label));
4556 if (!INTVAL (operands[3]))
4557 emit_insn (gen_clrt ());
4559 emit_insn (gen_negc (gen_lowpart (SImode, operands[0]),
4560 gen_lowpart (SImode, operands[1])));
4561 emit_label_after (skip_neg_label,
4562 emit_insn (gen_negc (gen_highpart (SImode, operands[0]),
4563 gen_highpart (SImode, operands[1]))));
4567 (define_expand "bswapsi2"
4568 [(set (match_operand:SI 0 "arith_reg_dest" "")
4569 (bswap:SI (match_operand:SI 1 "arith_reg_operand" "")))]
4572 if (! can_create_pseudo_p ())
4576 rtx tmp0 = gen_reg_rtx (SImode);
4577 rtx tmp1 = gen_reg_rtx (SImode);
4579 emit_insn (gen_swapbsi2 (tmp0, operands[1]));
4580 emit_insn (gen_rotlsi3_16 (tmp1, tmp0));
4581 emit_insn (gen_swapbsi2 (operands[0], tmp1));
4586 (define_insn "swapbsi2"
4587 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4588 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "r")
4589 (const_int -65536)) ;; 0xFFFF0000
4590 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
4592 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
4593 (const_int 255)))))]
4596 [(set_attr "type" "arith")])
4598 ;; The *swapbisi2_and_shl8 pattern helps the combine pass simplifying
4599 ;; partial byte swap expressions such as...
4600 ;; ((x & 0xFF) << 8) | ((x >> 8) & 0xFF).
4601 ;; ...which are currently not handled by the tree optimizers.
4602 ;; The combine pass will not initially try to combine the full expression,
4603 ;; but only some sub-expressions. In such a case the *swapbisi2_and_shl8
4604 ;; pattern acts as an intermediate pattern that will eventually lead combine
4605 ;; to the swapbsi2 pattern above.
4606 ;; As a side effect this also improves code that does (x & 0xFF) << 8
4607 ;; or (x << 8) & 0xFF00.
4608 (define_insn_and_split "*swapbisi2_and_shl8"
4609 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4610 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
4613 (match_operand:SI 2 "arith_reg_operand" "r")))]
4614 "TARGET_SH1 && ! reload_in_progress && ! reload_completed"
4616 "&& can_create_pseudo_p ()"
4619 rtx tmp0 = gen_reg_rtx (SImode);
4620 rtx tmp1 = gen_reg_rtx (SImode);
4622 emit_insn (gen_zero_extendqisi2 (tmp0, gen_lowpart (QImode, operands[1])));
4623 emit_insn (gen_swapbsi2 (tmp1, tmp0));
4624 emit_insn (gen_iorsi3 (operands[0], tmp1, operands[2]));
4628 ;; The *swapbhisi2 pattern is, like the *swapbisi2_and_shl8 pattern, another
4629 ;; intermediate pattern that will help the combine pass arriving at swapbsi2.
4630 (define_insn_and_split "*swapbhisi2"
4631 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4632 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
4635 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))))]
4636 "TARGET_SH1 && ! reload_in_progress && ! reload_completed"
4638 "&& can_create_pseudo_p ()"
4641 rtx tmp = gen_reg_rtx (SImode);
4643 emit_insn (gen_zero_extendhisi2 (tmp, gen_lowpart (HImode, operands[1])));
4644 emit_insn (gen_swapbsi2 (operands[0], tmp));
4648 ;; In some cases the swapbsi2 pattern might leave a sequence such as...
4652 ;; which can be simplified to...
4655 [(set (match_operand:SI 0 "arith_reg_dest" "")
4656 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "")
4657 (const_int -65536)) ;; 0xFFFF0000
4658 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
4660 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
4662 (set (match_operand:SI 2 "arith_reg_dest" "")
4664 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
4666 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "")
4667 (const_int -65536)) ;; 0xFFFF0000
4668 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
4670 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
4671 (const_int 255)))))])
4673 ;; -------------------------------------------------------------------------
4674 ;; Zero extension instructions
4675 ;; -------------------------------------------------------------------------
4677 (define_expand "zero_extend<mode>si2"
4678 [(set (match_operand:SI 0 "arith_reg_dest")
4679 (zero_extend:SI (match_operand:QIHI 1 "arith_reg_operand")))])
4681 (define_insn_and_split "*zero_extend<mode>si2_compact"
4682 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4683 (zero_extend:SI (match_operand:QIHI 1 "arith_reg_operand" "r")))]
4686 "&& can_create_pseudo_p ()"
4687 [(set (match_dup 0) (match_dup 2))]
4689 /* Sometimes combine fails to combine a T bit or negated T bit store to a
4690 reg with a following zero extension. In the split pass after combine,
4691 try to figure out how the extended reg was set. If it originated from
4692 the T bit we can replace the zero extension with a reg move, which will
4693 be eliminated. Notice that this also helps the *cbranch_t splitter when
4694 it tries to post-combine tests and conditional branches, as it does not
4695 check for zero extensions. */
4696 operands[2] = sh_try_omit_signzero_extend (operands[1], curr_insn);
4697 if (operands[2] == NULL_RTX)
4700 [(set_attr "type" "arith")])
4702 (define_insn "zero_extendqihi2"
4703 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
4704 (zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
4707 [(set_attr "type" "arith")])
4709 ;; SH2A supports two zero extending load instructions: movu.b and movu.w.
4710 ;; They could also be used for simple memory addresses like @Rn by setting
4711 ;; the displacement value to zero. However, doing so too early results in
4712 ;; missed opportunities for other optimizations such as post-inc or index
4713 ;; addressing loads.
4714 ;; We don't allow the zero extending loads to match during RTL expansion,
4715 ;; as this would pessimize other optimization opportunities such as bit
4716 ;; extractions of unsigned mems, where the zero extraction is irrelevant.
4717 ;; If the zero extracting mem loads are emitted early it will be more
4718 ;; difficult to change them back to sign extending loads (which are preferred).
4719 ;; The combine pass will also try to combine mem loads and zero extends,
4720 ;; which is prevented by 'sh_legitimate_combined_insn'.
4721 (define_insn "*zero_extend<mode>si2_disp_mem"
4722 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
4724 (match_operand:QIHI 1 "zero_extend_movu_operand" "Sdd,Sra")))]
4728 movu.<bw> @(0,%t1),%0"
4729 [(set_attr "type" "load")
4730 (set_attr "length" "4")])
4732 ;; Convert the zero extending loads in sequences such as:
4733 ;; movu.b @(1,r5),r0 movu.w @(2,r5),r0
4734 ;; mov.b r0,@(1,r4) mov.b r0,@(1,r4)
4736 ;; back to sign extending loads like:
4737 ;; mov.b @(1,r5),r0 mov.w @(2,r5),r0
4738 ;; mov.b r0,@(1,r4) mov.b r0,@(1,r4)
4740 ;; if the extension type is irrelevant. The sign extending mov.{b|w} insn
4741 ;; is only 2 bytes in size if the displacement is {K04|K05}.
4742 ;; If the displacement is greater it doesn't matter, so we convert anyways.
4744 [(set (match_operand:SI 0 "arith_reg_dest" "")
4745 (zero_extend:SI (match_operand 1 "displacement_mem_operand" "")))
4746 (set (match_operand 2 "nonimmediate_operand" "")
4747 (match_operand 3 "arith_reg_operand" ""))]
4749 && REGNO (operands[0]) == REGNO (operands[3])
4750 && peep2_reg_dead_p (2, operands[0])
4751 && GET_MODE_SIZE (GET_MODE (operands[2]))
4752 <= GET_MODE_SIZE (GET_MODE (operands[1]))"
4753 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))
4754 (set (match_dup 2) (match_dup 3))])
4756 ;; Fold sequences such as
4760 ;; movu.b @(0,r3),r7
4761 ;; This does not reduce the code size but the number of instructions is
4762 ;; halved, which results in faster code.
4764 [(set (match_operand:SI 0 "arith_reg_dest" "")
4765 (sign_extend:SI (match_operand 1 "simple_mem_operand" "")))
4766 (set (match_operand:SI 2 "arith_reg_dest" "")
4767 (zero_extend:SI (match_operand 3 "arith_reg_operand" "")))]
4769 && GET_MODE (operands[1]) == GET_MODE (operands[3])
4770 && (GET_MODE (operands[1]) == QImode || GET_MODE (operands[1]) == HImode)
4771 && REGNO (operands[0]) == REGNO (operands[3])
4772 && (REGNO (operands[2]) == REGNO (operands[0])
4773 || peep2_reg_dead_p (2, operands[0]))"
4774 [(set (match_dup 2) (zero_extend:SI (match_dup 4)))]
4777 = replace_equiv_address (operands[1],
4778 gen_rtx_PLUS (SImode, XEXP (operands[1], 0),
4782 ;; -------------------------------------------------------------------------
4783 ;; Sign extension instructions
4784 ;; -------------------------------------------------------------------------
4786 ;; ??? This should be a define expand.
4787 ;; ??? Or perhaps it should be dropped?
4789 ;; convert_move generates good code for SH[1-4].
4791 (define_expand "extend<mode>si2"
4792 [(set (match_operand:SI 0 "arith_reg_dest")
4793 (sign_extend:SI (match_operand:QIHI 1 "general_extend_operand")))])
4795 (define_insn_and_split "*extend<mode>si2_compact_reg"
4796 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4797 (sign_extend:SI (match_operand:QIHI 1 "arith_reg_operand" "r")))]
4800 "&& can_create_pseudo_p ()"
4801 [(set (match_dup 0) (match_dup 2))]
4803 /* Sometimes combine fails to combine a T bit or negated T bit store to a
4804 reg with a following sign extension. In the split pass after combine,
4805 try to figure the extended reg was set. If it originated from the T
4806 bit we can replace the sign extension with a reg move, which will be
4808 operands[2] = sh_try_omit_signzero_extend (operands[1], curr_insn);
4809 if (operands[2] == NULL_RTX)
4812 [(set_attr "type" "arith")])
4814 ;; FIXME: Fold non-SH2A and SH2A alternatives with "enabled" attribute.
4816 (define_insn "*extend<mode>si2_compact_mem_disp"
4817 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r")
4821 (match_operand:SI 1 "arith_reg_operand" "%r,r")
4822 (match_operand:SI 2 "const_int_operand" "<disp04>,N")))))]
4823 "TARGET_SH1 && ! TARGET_SH2A
4824 && sh_legitimate_index_p (<MODE>mode, operands[2], false, true)"
4826 mov.<bw> @(%O2,%1),%0
4828 [(set_attr "type" "load")])
4830 (define_insn "*extend<mode>si2_compact_mem_disp"
4831 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r,r")
4835 (match_operand:SI 1 "arith_reg_operand" "%r,r,r")
4836 (match_operand:SI 2 "const_int_operand" "<disp04>,N,<disp12>")))))]
4837 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[2], true, true)"
4839 mov.<bw> @(%O2,%1),%0
4841 mov.<bw> @(%O2,%1),%0"
4842 [(set_attr "type" "load")
4843 (set_attr "length" "2,2,4")])
4845 ;; The pre-dec and post-inc mems must be captured by the '<' and '>'
4846 ;; constraints, otherwise wrong code might get generated.
4847 (define_insn "*extend<mode>si2_predec"
4848 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
4849 (sign_extend:SI (match_operand:QIHI 1 "pre_dec_mem" "<")))]
4852 [(set_attr "type" "load")])
4854 ;; The *_snd patterns will take care of other QImode/HImode addressing
4855 ;; modes than displacement addressing. They must be defined _after_ the
4856 ;; displacement addressing patterns. Otherwise the displacement addressing
4857 ;; patterns will not be picked.
4858 (define_insn "*extend<mode>si2_compact_snd"
4859 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4861 (match_operand:QIHI 1 "movsrc_no_disp_mem_operand" "Snd")))]
4864 [(set_attr "type" "load")])
4866 (define_expand "extendqihi2"
4867 [(set (match_operand:HI 0 "arith_reg_dest")
4868 (sign_extend:HI (match_operand:QI 1 "arith_reg_operand")))]
4871 (define_insn "*extendqihi2_compact_reg"
4872 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
4873 (sign_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
4876 [(set_attr "type" "arith")])
4878 ;; -------------------------------------------------------------------------
4879 ;; Move instructions
4880 ;; -------------------------------------------------------------------------
4882 (define_expand "push"
4883 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4884 (match_operand:SI 0 "register_operand"))])
4886 (define_expand "pop"
4887 [(set (match_operand:SI 0 "register_operand")
4888 (mem:SI (post_inc:SI (reg:SI SP_REG))))])
4890 (define_expand "push_e"
4891 [(parallel [(set (mem:SF (pre_dec:SI (reg:SI SP_REG)))
4892 (match_operand:SF 0 "" ""))
4893 (use (reg:SI FPSCR_MODES_REG))
4894 (clobber (scratch:SI))])])
4896 (define_insn "push_fpul"
4897 [(set (mem:SF (pre_dec:SI (reg:SI SP_REG))) (reg:SF FPUL_REG))]
4900 [(set_attr "type" "fstore")
4901 (set_attr "late_fp_use" "yes")
4902 (set_attr "hit_stack" "yes")])
4904 ;; DFmode pushes for sh4 require a lot of what is defined for movdf_i4,
4906 (define_expand "push_4"
4907 [(parallel [(set (mem:DF (pre_dec:SI (reg:SI SP_REG)))
4908 (match_operand:DF 0 "" ""))
4909 (use (reg:SI FPSCR_MODES_REG))
4910 (clobber (scratch:SI))])])
4912 (define_expand "pop_e"
4913 [(parallel [(set (match_operand:SF 0 "" "")
4914 (mem:SF (post_inc:SI (reg:SI SP_REG))))
4915 (use (reg:SI FPSCR_MODES_REG))
4916 (clobber (scratch:SI))])])
4918 (define_insn "pop_fpul"
4919 [(set (reg:SF FPUL_REG) (mem:SF (post_inc:SI (reg:SI SP_REG))))]
4922 [(set_attr "type" "load")
4923 (set_attr "hit_stack" "yes")])
4925 (define_expand "pop_4"
4926 [(parallel [(set (match_operand:DF 0 "" "")
4927 (mem:DF (post_inc:SI (reg:SI SP_REG))))
4928 (use (reg:SI FPSCR_MODES_REG))
4929 (clobber (scratch:SI))])])
4931 (define_expand "push_fpscr"
4938 gen_frame_mem (SImode, gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx)))),
4939 REG_INC, stack_pointer_rtx);
4943 (define_expand "pop_fpscr"
4950 gen_frame_mem (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)))),
4951 REG_INC, stack_pointer_rtx);
4955 ;; The clrt and sett patterns can happen as the result of optimization and
4957 ;; Comparisons might get simplified to a move of zero or 1 into the T reg.
4958 ;; In this case they might not disappear completely, because the T reg is
4959 ;; a fixed hard reg.
4960 ;; When DImode operations that use the T reg as carry/borrow are split into
4961 ;; individual SImode operations, the T reg is usually cleared before the
4962 ;; first SImode insn.
4964 [(set (reg:SI T_REG) (const_int 0))]
4967 [(set_attr "type" "mt_group")])
4970 [(set (reg:SI T_REG) (const_int 1))]
4973 [(set_attr "type" "mt_group")])
4975 ;; Use the combine pass to transform sequences such as
4979 ;; mov.l @(r0,r4),r0
4985 ;; See also PR 39423.
4986 ;; Notice that these patterns have a T_REG clobber, because the shift
4987 ;; sequence that will be split out might clobber the T_REG. Ideally, the
4988 ;; clobber would be added conditionally, depending on the result of
4989 ;; sh_ashlsi_clobbers_t_reg_p. When splitting out the shifts we must go
4990 ;; through the ashlsi3 expander in order to get the right shift insn --
4991 ;; a T_REG clobbering or non-clobbering shift sequence or dynamic shift.
4992 ;; FIXME: Combine never tries this kind of patterns for DImode.
4993 (define_insn_and_split "*movsi_index_disp_load"
4994 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4995 (match_operand:SI 1 "mem_index_disp_operand" "m"))
4996 (clobber (reg:SI T_REG))]
4999 "&& can_create_pseudo_p ()"
5000 [(set (match_dup 6) (plus:SI (match_dup 5) (match_dup 3)))
5001 (set (match_dup 0) (match_dup 7))]
5003 rtx mem = operands[1];
5004 rtx plus0_rtx = XEXP (mem, 0);
5005 rtx plus1_rtx = XEXP (plus0_rtx, 0);
5006 rtx mult_rtx = XEXP (plus1_rtx, 0);
5008 operands[1] = XEXP (mult_rtx, 0);
5009 operands[2] = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
5010 operands[3] = XEXP (plus1_rtx, 1);
5011 operands[4] = XEXP (plus0_rtx, 1);
5012 operands[5] = gen_reg_rtx (SImode);
5013 operands[6] = gen_reg_rtx (SImode);
5015 replace_equiv_address (mem,
5016 gen_rtx_PLUS (SImode, operands[6], operands[4]));
5018 emit_insn (gen_ashlsi3 (operands[5], operands[1], operands[2]));
5021 (define_insn_and_split "*movhi_index_disp_load"
5022 [(set (match_operand:SI 0 "arith_reg_dest")
5023 (SZ_EXTEND:SI (match_operand:HI 1 "mem_index_disp_operand")))
5024 (clobber (reg:SI T_REG))]
5027 "&& can_create_pseudo_p ()"
5030 rtx mem = operands[1];
5031 rtx plus0_rtx = XEXP (mem, 0);
5032 rtx plus1_rtx = XEXP (plus0_rtx, 0);
5033 rtx mult_rtx = XEXP (plus1_rtx, 0);
5035 rtx op_1 = XEXP (mult_rtx, 0);
5036 rtx op_2 = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
5037 rtx op_3 = XEXP (plus1_rtx, 1);
5038 rtx op_4 = XEXP (plus0_rtx, 1);
5039 rtx op_5 = gen_reg_rtx (SImode);
5040 rtx op_6 = gen_reg_rtx (SImode);
5041 rtx op_7 = replace_equiv_address (mem, gen_rtx_PLUS (SImode, op_6, op_4));
5043 emit_insn (gen_ashlsi3 (op_5, op_1, op_2));
5044 emit_insn (gen_addsi3 (op_6, op_5, op_3));
5046 if (<CODE> == SIGN_EXTEND)
5048 emit_insn (gen_extendhisi2 (operands[0], op_7));
5051 else if (<CODE> == ZERO_EXTEND)
5053 /* On SH2A the movu.w insn can be used for zero extending loads. */
5055 emit_insn (gen_zero_extendhisi2 (operands[0], op_7));
5058 emit_insn (gen_extendhisi2 (operands[0], op_7));
5059 emit_insn (gen_zero_extendhisi2 (operands[0],
5060 gen_lowpart (HImode, operands[0])));
5068 (define_insn_and_split "*mov<mode>_index_disp_store"
5069 [(set (match_operand:HISI 0 "mem_index_disp_operand" "=m")
5070 (match_operand:HISI 1 "arith_reg_operand" "r"))
5071 (clobber (reg:SI T_REG))]
5074 "&& can_create_pseudo_p ()"
5075 [(set (match_dup 6) (plus:SI (match_dup 5) (match_dup 3)))
5076 (set (match_dup 7) (match_dup 1))]
5078 rtx mem = operands[0];
5079 rtx plus0_rtx = XEXP (mem, 0);
5080 rtx plus1_rtx = XEXP (plus0_rtx, 0);
5081 rtx mult_rtx = XEXP (plus1_rtx, 0);
5083 operands[0] = XEXP (mult_rtx, 0);
5084 operands[2] = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
5085 operands[3] = XEXP (plus1_rtx, 1);
5086 operands[4] = XEXP (plus0_rtx, 1);
5087 operands[5] = gen_reg_rtx (SImode);
5088 operands[6] = gen_reg_rtx (SImode);
5090 replace_equiv_address (mem,
5091 gen_rtx_PLUS (SImode, operands[6], operands[4]));
5093 emit_insn (gen_ashlsi3 (operands[5], operands[0], operands[2]));
5096 ;; t/r must come after r/r, lest reload will try to reload stuff like
5097 ;; (set (subreg:SI (mem:QI (plus:SI (reg:SI SP_REG) (const_int 12)) 0) 0)
5098 ;; (made from (set (subreg:SI (reg:QI ###) 0) ) into T.
5099 ;; Notice that although this pattern allows movi20 and movi20s on non-SH2A,
5100 ;; those alternatives will not be taken, as they will be converted into
5101 ;; PC-relative loads.
5102 (define_insn "movsi_i"
5103 [(set (match_operand:SI 0 "general_movdst_operand"
5104 "=r,r, r, r, r, r,r,r,m,<,<,x,l,x,l,r")
5105 (match_operand:SI 1 "general_movsrc_operand"
5106 " Q,r,I08,I20,I28,mr,x,l,r,x,l,r,r,>,>,i"))]
5107 "TARGET_SH1 && !TARGET_FPU_ANY
5108 && (register_operand (operands[0], SImode)
5109 || register_operand (operands[1], SImode))"
5127 [(set_attr "type" "pcload_si,move,movi8,move,move,load_si,mac_gp,prget,store,
5128 mac_mem,pstore,gp_mac,prset,mem_mac,pload,pcload_si")
5129 (set_attr_alternative "length"
5135 (if_then_else (match_operand 1 "long_displacement_mem_operand")
5136 (const_int 4) (const_int 2))
5139 (if_then_else (match_operand 0 "long_displacement_mem_operand")
5140 (const_int 4) (const_int 2))
5149 ;; t/r must come after r/r, lest reload will try to reload stuff like
5150 ;; (subreg:SI (reg:SF FR14_REG) 0) into T (compiling stdlib/strtod.c -m3e -O2)
5151 ;; ??? This allows moves from macl to fpul to be recognized, but these moves
5152 ;; will require a reload.
5153 ;; ??? We can't include f/f because we need the proper FPSCR setting when
5154 ;; TARGET_FMOVD is in effect, and mode switching is done before reload.
5155 ;; Notice that although this pattern allows movi20 and movi20s on non-SH2A,
5156 ;; those alternatives will not be taken, as they will be converted into
5157 ;; PC-relative loads.
5158 (define_insn "movsi_ie"
5159 [(set (match_operand:SI 0 "general_movdst_operand"
5160 "=r,r, r, r, r, r,r,r,mr,<,<,x,l,x,l,y,<,r,y,r,*f, y,*f,y")
5161 (match_operand:SI 1 "general_movsrc_operand"
5162 " Q,r,I08,I20,I28,mr,x,l, r,x,l,r,r,>,>,>,y,i,r,y, y,*f,*f,y"))]
5163 "TARGET_SH1 && TARGET_FPU_ANY
5164 && ((register_operand (operands[0], SImode)
5165 && !fpscr_operand (operands[0], SImode))
5166 || (register_operand (operands[1], SImode)
5167 && !fpscr_operand (operands[1], SImode)))"
5192 ! move optimized away"
5193 [(set_attr "type" "pcload_si,move,movi8,move,move,load_si,mac_gp,prget,store,
5194 mac_mem,pstore,gp_mac,prset,mem_mac,pload,load,fstore,
5195 pcload_si,gp_fpul,fpul_gp,fmove,fmove,fmove,nil")
5196 (set_attr "late_fp_use" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*")
5197 (set_attr_alternative "length"
5203 (if_then_else (match_operand 1 "long_displacement_mem_operand")
5204 (const_int 4) (const_int 2))
5207 (if_then_else (match_operand 0 "long_displacement_mem_operand")
5208 (const_int 4) (const_int 2))
5225 ;; Notice that although this pattern allows movi20 and movi20s on non-SH2A,
5226 ;; those alternatives will not be taken, as they will be converted into
5227 ;; PC-relative loads.
5228 (define_insn "movsi_i_lowpart"
5229 [(set (strict_low_part
5230 (match_operand:SI 0 "general_movdst_operand"
5231 "+r,r, r, r, r, r,r,r,m,r"))
5232 (match_operand:SI 1 "general_movsrc_operand"
5233 " Q,r,I08,I20,I28,mr,x,l,r,i"))]
5235 && (register_operand (operands[0], SImode)
5236 || register_operand (operands[1], SImode))"
5248 [(set_attr "type" "pcload,move,movi8,move,move,load,mac_gp,prget,store,
5250 (set_attr_alternative "length"
5256 (if_then_else (match_operand 1 "long_displacement_mem_operand")
5257 (const_int 4) (const_int 2))
5260 (if_then_else (match_operand 0 "long_displacement_mem_operand")
5261 (const_int 4) (const_int 2))
5264 (define_insn_and_split "load_ra"
5265 [(set (match_operand:SI 0 "general_movdst_operand" "")
5266 (unspec:SI [(match_operand:SI 1 "register_operand" "")] UNSPEC_RA))]
5269 "&& ! currently_expanding_to_rtl"
5270 [(set (match_dup 0) (match_dup 1))])
5272 (define_expand "movsi"
5273 [(set (match_operand:SI 0 "general_movdst_operand" "")
5274 (match_operand:SI 1 "general_movsrc_operand" ""))]
5277 prepare_move_operands (operands, SImode);
5280 (define_expand "ic_invalidate_line"
5281 [(parallel [(unspec_volatile [(match_operand:SI 0 "register_operand")
5282 (match_dup 1)] UNSPEC_ICACHE)
5283 (clobber (scratch:SI))])]
5286 emit_insn (gen_ic_invalidate_line_sh4a (operands[0]));
5290 ;; The address %0 is assumed to be 4-aligned at least. Thus, by ORing
5291 ;; 0xf0000008, we get the low-oder bits *1*00 (binary), which fits
5292 ;; the requirement *1*00 for associative address writes. The alignment of
5293 ;; %0 implies that its least significant bit is cleared,
5294 ;; thus we clear the V bit of a matching entry if there is one.
5295 (define_insn "ic_invalidate_line_i"
5296 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")
5297 (match_operand:SI 1 "register_operand" "r")]
5299 (clobber (match_scratch:SI 2 "=&r"))]
5302 return "ocbwb @%0" "\n"
5303 " extu.w %0,%2" "\n"
5307 [(set_attr "length" "8")
5308 (set_attr "type" "cwb")])
5310 (define_insn "ic_invalidate_line_sh4a"
5311 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
5313 "TARGET_SH4A || TARGET_SH4_300"
5315 return "ocbwb @%0" "\n"
5319 [(set_attr "length" "6")
5320 (set_attr "type" "cwb")])
5322 (define_expand "mov<mode>"
5323 [(set (match_operand:QIHI 0 "general_movdst_operand")
5324 (match_operand:QIHI 1 "general_movsrc_operand"))]
5327 if (can_create_pseudo_p () && CONST_INT_P (operands[1])
5328 && REG_P (operands[0]) && REGNO (operands[0]) != R0_REG)
5330 rtx reg = gen_reg_rtx(SImode);
5331 emit_move_insn (reg, operands[1]);
5332 operands[1] = gen_lowpart (<MODE>mode, reg);
5335 prepare_move_operands (operands, <MODE>mode);
5338 ;; The pre-dec and post-inc mems must be captured by the '<' and '>'
5339 ;; constraints, otherwise wrong code might get generated.
5340 (define_insn "*mov<mode>_load_predec"
5341 [(set (match_operand:QIHISI 0 "arith_reg_dest" "=z")
5342 (match_operand:QIHISI 1 "pre_dec_mem" "<"))]
5345 [(set_attr "type" "load")])
5347 (define_insn "*mov<mode>_store_postinc"
5348 [(set (match_operand:QIHISI 0 "post_inc_mem" "=>")
5349 (match_operand:QIHISI 1 "arith_reg_operand" "z"))]
5352 [(set_attr "type" "store")])
5354 ;; Specifying the displacement addressing load / store patterns separately
5355 ;; before the generic movqi / movhi pattern allows controlling the order
5356 ;; in which load / store insns are selected in a more fine grained way.
5357 ;; FIXME: The non-SH2A and SH2A variants should be combined by adding
5358 ;; "enabled" attribute as it is done in other targets.
5359 (define_insn "*mov<mode>_store_mem_disp04"
5361 (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r,r")
5362 (match_operand:SI 1 "const_int_operand" "<disp04>,N")))
5363 (match_operand:QIHI 2 "arith_reg_operand" "z,r"))]
5364 "TARGET_SH1 && sh_legitimate_index_p (<MODE>mode, operands[1], false, true)"
5366 mov.<bw> %2,@(%O1,%0)
5368 [(set_attr "type" "store")])
5370 (define_insn "*mov<mode>_store_mem_disp12"
5372 (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r")
5373 (match_operand:SI 1 "const_int_operand" "<disp12>")))
5374 (match_operand:QIHI 2 "arith_reg_operand" "r"))]
5375 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[1], true, true)"
5376 "mov.<bw> %2,@(%O1,%0)"
5377 [(set_attr "type" "store")
5378 (set_attr "length" "4")])
5380 (define_insn "*mov<mode>_load_mem_disp04"
5381 [(set (match_operand:QIHI 0 "arith_reg_dest" "=z,r")
5383 (plus:SI (match_operand:SI 1 "arith_reg_operand" "%r,r")
5384 (match_operand:SI 2 "const_int_operand" "<disp04>,N"))))]
5385 "TARGET_SH1 && ! TARGET_SH2A
5386 && sh_legitimate_index_p (<MODE>mode, operands[2], false, true)"
5388 mov.<bw> @(%O2,%1),%0
5390 [(set_attr "type" "load")])
5392 (define_insn "*mov<mode>_load_mem_disp12"
5393 [(set (match_operand:QIHI 0 "arith_reg_dest" "=z,r,r")
5396 (match_operand:SI 1 "arith_reg_operand" "%r,r,r")
5397 (match_operand:SI 2 "const_int_operand" "<disp04>,N,<disp12>"))))]
5398 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[2], true, true)"
5400 mov.<bw> @(%O2,%1),%0
5402 mov.<bw> @(%O2,%1),%0"
5403 [(set_attr "type" "load")
5404 (set_attr "length" "2,2,4")])
5406 ;; The order of the constraint alternatives is important here.
5407 ;; Q/r has to come first, otherwise PC relative loads might wrongly get
5408 ;; placed into delay slots. Since there is no QImode PC relative load, the
5409 ;; Q constraint and general_movsrc_operand will reject it for QImode.
5410 ;; The Sid/Ssd alternatives should come before Sdd in order to avoid
5411 ;; a preference of using r0 als the register operand for addressing modes
5412 ;; other than displacement addressing.
5413 ;; The Sdd alternatives allow only r0 as register operand, even though on
5414 ;; SH2A any register could be allowed by switching to a 32 bit insn.
5415 ;; Generally sticking to the r0 is preferrable, since it generates smaller
5416 ;; code. Obvious r0 reloads can then be eliminated with a peephole on SH2A.
5417 (define_insn "*mov<mode>"
5418 [(set (match_operand:QIHI 0 "general_movdst_operand"
5419 "=r,r,r,Sid,^zr,Ssd,r, Sdd,z, r,l")
5420 (match_operand:QIHI 1 "general_movsrc_operand"
5421 "Q,r,i,^zr,Sid,r, Ssd,z, Sdd,l,r"))]
5423 && (arith_reg_operand (operands[0], <MODE>mode)
5424 || arith_reg_operand (operands[1], <MODE>mode))"
5437 [(set_attr "type" "pcload,move,movi8,store,load,store,load,store,load,prget,prset")
5438 (set (attr "length")
5439 (cond [(match_operand 0 "long_displacement_mem_operand") (const_int 4)
5440 (match_operand 1 "long_displacement_mem_operand") (const_int 4)]
5443 ;; x/r can be created by inlining/cse, e.g. for execute/961213-1.c
5444 ;; compiled with -m2 -ml -O3 -funroll-loops
5445 (define_insn "*movdi_i"
5446 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m, r,r,r,*!x")
5447 (match_operand:DI 1 "general_movsrc_operand" " Q,r,m,r,I08,i,x, r"))]
5449 && (arith_reg_operand (operands[0], DImode)
5450 || arith_reg_operand (operands[1], DImode))"
5452 return output_movedouble (insn, operands, DImode);
5454 [(set_attr "type" "pcload,move,load,store,move,pcload,move,move")
5455 (set (attr "length")
5456 (cond [(match_operand 0 "long_displacement_mem_operand") (const_int 8)
5457 (match_operand 1 "long_displacement_mem_operand") (const_int 8)]
5460 ;; If the output is a register and the input is memory or a register, we have
5461 ;; to be careful and see which word needs to be loaded first.
5463 [(set (match_operand:DI 0 "general_movdst_operand" "")
5464 (match_operand:DI 1 "general_movsrc_operand" ""))]
5465 "TARGET_SH1 && reload_completed"
5466 [(set (match_dup 2) (match_dup 3))
5467 (set (match_dup 4) (match_dup 5))]
5471 if ((MEM_P (operands[0])
5472 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
5473 || (MEM_P (operands[1])
5474 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
5477 switch (GET_CODE (operands[0]))
5480 regno = REGNO (operands[0]);
5483 regno = subreg_regno (operands[0]);
5492 if (regno == -1 || ! refers_to_regno_p (regno, operands[1]))
5494 operands[2] = operand_subword (operands[0], 0, 0, DImode);
5495 operands[3] = operand_subword (operands[1], 0, 0, DImode);
5496 operands[4] = operand_subword (operands[0], 1, 0, DImode);
5497 operands[5] = operand_subword (operands[1], 1, 0, DImode);
5501 operands[2] = operand_subword (operands[0], 1, 0, DImode);
5502 operands[3] = operand_subword (operands[1], 1, 0, DImode);
5503 operands[4] = operand_subword (operands[0], 0, 0, DImode);
5504 operands[5] = operand_subword (operands[1], 0, 0, DImode);
5507 if (operands[2] == 0 || operands[3] == 0
5508 || operands[4] == 0 || operands[5] == 0)
5512 (define_expand "movdi"
5513 [(set (match_operand:DI 0 "general_movdst_operand" "")
5514 (match_operand:DI 1 "general_movsrc_operand" ""))]
5517 prepare_move_operands (operands, DImode);
5519 /* When the dest operand is (R0, R1) register pair, split it to
5520 two movsi of which dest is R1 and R0 so as to lower R0-register
5521 pressure on the first movsi. Apply only for simple source not
5522 to make complex rtl here. */
5523 if (REG_P (operands[0]) && REGNO (operands[0]) == R0_REG
5524 && REG_P (operands[1]) && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
5526 emit_insn (gen_movsi (gen_rtx_REG (SImode, R1_REG),
5527 gen_rtx_SUBREG (SImode, operands[1], 4)));
5528 emit_insn (gen_movsi (gen_rtx_REG (SImode, R0_REG),
5529 gen_rtx_SUBREG (SImode, operands[1], 0)));
5534 ;; FIXME: This should be a define_insn_and_split.
5535 (define_insn "movdf_k"
5536 [(set (match_operand:DF 0 "general_movdst_operand" "=r, r,r,m")
5537 (match_operand:DF 1 "general_movsrc_operand" " r,FQ,m,r"))]
5539 && (!TARGET_FPU_DOUBLE || reload_completed
5540 /* ??? We provide some insn so that direct_{load,store}[DFmode] get set */
5541 || (REG_P (operands[0]) && REGNO (operands[0]) == 3)
5542 || (REG_P (operands[1]) && REGNO (operands[1]) == 3))
5543 && (arith_reg_operand (operands[0], DFmode)
5544 || arith_reg_operand (operands[1], DFmode))"
5546 return output_movedouble (insn, operands, DFmode);
5548 [(set_attr "type" "move,pcload,load,store")
5549 (set (attr "length")
5550 (cond [(match_operand 0 "long_displacement_mem_operand") (const_int 8)
5551 (match_operand 1 "long_displacement_mem_operand") (const_int 8)]
5554 ;; All alternatives of movdf_i4 are split for ! TARGET_FMOVD.
5555 ;; However, the d/F/c/z alternative cannot be split directly; it is converted
5556 ;; with special code in machine_dependent_reorg into a load of the R0_REG and
5557 ;; the d/m/c/X alternative, which is split later into single-precision
5558 ;; instructions. And when not optimizing, no splits are done before fixing
5559 ;; up pcloads, so we need usable length information for that.
5560 ;; A DF constant load results in the following worst-case 8 byte sequence:
5565 (define_insn "movdf_i4"
5566 [(set (match_operand:DF 0 "general_movdst_operand"
5567 "=d,r, d,d,m, r,r,m,!??r,!???d")
5568 (match_operand:DF 1 "general_movsrc_operand"
5569 " d,r, F,m,d,FQ,m,r, d, r"))
5570 (use (reg:SI FPSCR_MODES_REG))
5571 (clobber (match_scratch:SI 2
5572 "=X,X,&z,X,X, X,X,X, X, X"))]
5574 && (arith_reg_operand (operands[0], DFmode)
5575 || arith_reg_operand (operands[1], DFmode))"
5577 switch (which_alternative)
5581 return "fmov %1,%0";
5582 else if (REGNO (operands[0]) != REGNO (operands[1]) + 1)
5583 return "fmov %R1,%R0" "\n"
5586 return "fmov %S1,%S0" "\n"
5590 return "fmov.d %1,%0";
5595 [(set_attr_alternative "length"
5596 [(if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 4))
5598 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 8))
5599 (if_then_else (match_operand 1 "displacement_mem_operand")
5600 (if_then_else (eq_attr "fmovd" "yes")
5601 (const_int 4) (const_int 8))
5602 (if_then_else (eq_attr "fmovd" "yes")
5603 (const_int 2) (const_int 4)))
5604 (if_then_else (match_operand 0 "displacement_mem_operand")
5605 (if_then_else (eq_attr "fmovd" "yes")
5606 (const_int 4) (const_int 8))
5607 (if_then_else (eq_attr "fmovd" "yes")
5608 (const_int 2) (const_int 4)))
5610 (if_then_else (match_operand 1 "long_displacement_mem_operand")
5611 (const_int 8) (const_int 4))
5612 (if_then_else (match_operand 0 "long_displacement_mem_operand")
5613 (const_int 8) (const_int 4))
5616 (set_attr "type" "fmove,move,pcfload,fload,fstore,pcload,load,store,load,
5618 (set_attr "late_fp_use" "*,*,*,*,yes,*,*,*,*,*")
5619 (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
5620 (const_string "double")
5621 (const_string "none")))])
5623 ;; Moving DFmode between fp/general registers through memory
5624 ;; (the top of the stack) is faster than moving through fpul even for
5625 ;; little endian. Because the type of an instruction is important for its
5626 ;; scheduling, it is beneficial to split these operations, rather than
5627 ;; emitting them in one single chunk, even if this will expose a stack
5628 ;; use that will prevent scheduling of other stack accesses beyond this
5631 [(set (match_operand:DF 0 "register_operand")
5632 (match_operand:DF 1 "register_operand"))
5633 (use (reg:SI FPSCR_MODES_REG))
5634 (clobber (match_scratch:SI 2))]
5635 "TARGET_FPU_DOUBLE && reload_completed
5636 && (true_regnum (operands[0]) < 16) != (true_regnum (operands[1]) < 16)"
5641 tos = gen_tmp_stack_mem (DFmode, gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
5642 insn = emit_insn (gen_movdf_i4 (tos, operands[1]));
5643 add_reg_note (insn, REG_INC, stack_pointer_rtx);
5644 tos = gen_tmp_stack_mem (DFmode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx));
5645 insn = emit_insn (gen_movdf_i4 (operands[0], tos));
5646 add_reg_note (insn, REG_INC, stack_pointer_rtx);
5650 ;; local-alloc sometimes allocates scratch registers even when not required,
5651 ;; so we must be prepared to handle these.
5653 ;; Remove the use and clobber from a movdf_i4 so that we can use movdf_k.
5655 [(set (match_operand:DF 0 "general_movdst_operand" "")
5656 (match_operand:DF 1 "general_movsrc_operand" ""))
5657 (use (reg:SI FPSCR_MODES_REG))
5658 (clobber (match_scratch:SI 2))]
5661 && true_regnum (operands[0]) < 16
5662 && true_regnum (operands[1]) < 16"
5663 [(set (match_dup 0) (match_dup 1))]
5665 /* If this was a reg <-> mem operation with base + index reg addressing,
5666 we have to handle this in a special way. */
5667 rtx mem = operands[0];
5669 if (! memory_operand (mem, DFmode))
5674 if (GET_CODE (mem) == SUBREG && SUBREG_BYTE (mem) == 0)
5675 mem = SUBREG_REG (mem);
5678 rtx addr = XEXP (mem, 0);
5679 if (GET_CODE (addr) == PLUS
5680 && REG_P (XEXP (addr, 0))
5681 && REG_P (XEXP (addr, 1)))
5684 rtx reg0 = gen_rtx_REG (Pmode, 0);
5685 rtx regop = operands[store_p], word0 ,word1;
5687 if (GET_CODE (regop) == SUBREG)
5688 alter_subreg (®op, true);
5689 if (REGNO (XEXP (addr, 0)) == REGNO (XEXP (addr, 1)))
5693 mem = copy_rtx (mem);
5694 PUT_MODE (mem, SImode);
5695 word0 = gen_rtx_SUBREG (SImode, regop, 0);
5696 alter_subreg (&word0, true);
5697 word1 = gen_rtx_SUBREG (SImode, regop, 4);
5698 alter_subreg (&word1, true);
5699 if (store_p || ! refers_to_regno_p (REGNO (word0), addr))
5702 ? gen_movsi_ie (mem, word0)
5703 : gen_movsi_ie (word0, mem));
5704 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
5705 mem = copy_rtx (mem);
5707 ? gen_movsi_ie (mem, word1)
5708 : gen_movsi_ie (word1, mem));
5709 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
5713 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
5714 emit_insn (gen_movsi_ie (word1, mem));
5715 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
5716 mem = copy_rtx (mem);
5717 emit_insn (gen_movsi_ie (word0, mem));
5724 ;; Split away the clobber of r0 after machine_dependent_reorg has fixed pcloads.
5726 [(set (match_operand:DF 0 "register_operand" "")
5727 (match_operand:DF 1 "memory_operand" ""))
5728 (use (reg:SI FPSCR_MODES_REG))
5729 (clobber (reg:SI R0_REG))]
5730 "TARGET_FPU_DOUBLE && reload_completed"
5731 [(parallel [(set (match_dup 0) (match_dup 1))
5732 (use (reg:SI FPSCR_MODES_REG))
5733 (clobber (scratch:SI))])]
5736 (define_expand "reload_indf__frn"
5737 [(parallel [(set (match_operand:DF 0 "register_operand" "=a")
5738 (match_operand:DF 1 "immediate_operand" "FQ"))
5739 (use (reg:SI FPSCR_MODES_REG))
5740 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
5744 (define_expand "reload_outdf__RnFRm"
5745 [(parallel [(set (match_operand:DF 0 "register_operand" "=r,f")
5746 (match_operand:DF 1 "register_operand" "af,r"))
5747 (clobber (match_operand:SI 2 "register_operand" "=&y,y"))])]
5751 ;; Simplify no-op moves.
5753 [(set (match_operand:SF 0 "register_operand" "")
5754 (match_operand:SF 1 "register_operand" ""))
5755 (use (reg:SI FPSCR_MODES_REG))
5756 (clobber (match_scratch:SI 2))]
5757 "TARGET_SH2E && reload_completed
5758 && true_regnum (operands[0]) == true_regnum (operands[1])"
5759 [(set (match_dup 0) (match_dup 0))]
5762 ;; fmovd substitute post-reload splits
5764 [(set (match_operand:DF 0 "register_operand" "")
5765 (match_operand:DF 1 "register_operand" ""))
5766 (use (reg:SI FPSCR_MODES_REG))
5767 (clobber (match_scratch:SI 2))]
5768 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
5769 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
5770 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
5773 int dst = true_regnum (operands[0]), src = true_regnum (operands[1]);
5774 emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, dst),
5775 gen_rtx_REG (SFmode, src)));
5776 emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, dst + 1),
5777 gen_rtx_REG (SFmode, src + 1)));
5782 [(set (match_operand:DF 0 "register_operand" "")
5783 (mem:DF (match_operand:SI 1 "register_operand" "")))
5784 (use (reg:SI FPSCR_MODES_REG))
5785 (clobber (match_scratch:SI 2))]
5786 "TARGET_FPU_DOUBLE && ! TARGET_FMOVD && reload_completed
5787 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
5788 && find_regno_note (insn, REG_DEAD, true_regnum (operands[1]))"
5791 int regno = true_regnum (operands[0]);
5793 rtx mem = SET_SRC (XVECEXP (PATTERN (curr_insn), 0, 0));
5795 = change_address (mem, SFmode, gen_rtx_POST_INC (Pmode, operands[1]));
5796 insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode,
5797 regno + SH_REG_MSW_OFFSET),
5799 add_reg_note (insn, REG_INC, operands[1]);
5800 insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode,
5801 regno + SH_REG_LSW_OFFSET),
5802 change_address (mem, SFmode, NULL_RTX)));
5807 [(set (match_operand:DF 0 "register_operand" "")
5808 (match_operand:DF 1 "memory_operand" ""))
5809 (use (reg:SI FPSCR_MODES_REG))
5810 (clobber (match_scratch:SI 2))]
5811 "TARGET_FPU_DOUBLE && ! TARGET_FMOVD && reload_completed
5812 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))"
5815 int regno = true_regnum (operands[0]);
5817 rtx mem2 = change_address (operands[1], SFmode, NULL_RTX);
5818 rtx reg0 = gen_rtx_REG (SFmode, regno + SH_REG_MSW_OFFSET);
5819 rtx reg1 = gen_rtx_REG (SFmode, regno + SH_REG_LSW_OFFSET);
5821 operands[1] = copy_rtx (mem2);
5822 addr = XEXP (mem2, 0);
5824 switch (GET_CODE (addr))
5827 /* This is complicated. If the register is an arithmetic register
5828 we can just fall through to the REG+DISP case below. Otherwise
5829 we have to use a combination of POST_INC and REG addressing... */
5830 if (! arith_reg_operand (operands[1], SFmode))
5832 XEXP (mem2, 0) = addr = gen_rtx_POST_INC (SImode, addr);
5833 insn = emit_insn (gen_movsf_ie (reg0, mem2));
5834 add_reg_note (insn, REG_INC, XEXP (addr, 0));
5836 emit_insn (gen_movsf_ie (reg1, operands[1]));
5838 /* If we have modified the stack pointer, the value that we have
5839 read with post-increment might be modified by an interrupt,
5840 so write it back. */
5841 if (REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
5842 emit_insn (gen_push_e (reg0));
5844 emit_insn (gen_addsi3 (XEXP (operands[1], 0), XEXP (operands[1], 0),
5851 emit_insn (gen_movsf_ie (reg0, operands[1]));
5852 operands[1] = copy_rtx (operands[1]);
5853 XEXP (operands[1], 0) = plus_constant (Pmode, addr, 4);
5854 emit_insn (gen_movsf_ie (reg1, operands[1]));
5858 insn = emit_insn (gen_movsf_ie (reg0, operands[1]));
5859 add_reg_note (insn, REG_INC, XEXP (addr, 0));
5861 insn = emit_insn (gen_movsf_ie (reg1, operands[1]));
5862 add_reg_note (insn, REG_INC, XEXP (addr, 0));
5874 [(set (match_operand:DF 0 "memory_operand" "")
5875 (match_operand:DF 1 "register_operand" ""))
5876 (use (reg:SI FPSCR_MODES_REG))
5877 (clobber (match_scratch:SI 2))]
5878 "TARGET_FPU_DOUBLE && ! TARGET_FMOVD && reload_completed
5879 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
5882 int regno = true_regnum (operands[1]);
5884 rtx reg0 = gen_rtx_REG (SFmode, regno + SH_REG_MSW_OFFSET);
5885 rtx reg1 = gen_rtx_REG (SFmode, regno + SH_REG_LSW_OFFSET);
5887 operands[0] = copy_rtx (operands[0]);
5888 PUT_MODE (operands[0], SFmode);
5889 addr = XEXP (operands[0], 0);
5891 switch (GET_CODE (addr))
5894 /* This is complicated. If the register is an arithmetic register
5895 we can just fall through to the REG+DISP case below. Otherwise
5896 we have to use a combination of REG and PRE_DEC addressing... */
5897 if (! arith_reg_operand (operands[0], SFmode))
5899 emit_insn (gen_addsi3 (addr, addr, GEN_INT (4)));
5900 emit_insn (gen_movsf_ie (operands[0], reg1));
5902 operands[0] = copy_rtx (operands[0]);
5903 XEXP (operands[0], 0) = addr = gen_rtx_PRE_DEC (SImode, addr);
5905 insn = emit_insn (gen_movsf_ie (operands[0], reg0));
5906 add_reg_note (insn, REG_INC, XEXP (addr, 0));
5912 /* Since REG+DISP addressing has already been decided upon by gcc
5913 we can rely upon it having chosen an arithmetic register as the
5914 register component of the address. Just emit the lower numbered
5915 register first, to the lower address, then the higher numbered
5916 register to the higher address. */
5917 emit_insn (gen_movsf_ie (operands[0], reg0));
5919 operands[0] = copy_rtx (operands[0]);
5920 XEXP (operands[0], 0) = plus_constant (Pmode, addr, 4);
5922 emit_insn (gen_movsf_ie (operands[0], reg1));
5926 /* This is easy. Output the word to go to the higher address
5927 first (ie the word in the higher numbered register) then the
5928 word to go to the lower address. */
5930 insn = emit_insn (gen_movsf_ie (operands[0], reg1));
5931 add_reg_note (insn, REG_INC, XEXP (addr, 0));
5933 insn = emit_insn (gen_movsf_ie (operands[0], reg0));
5934 add_reg_note (insn, REG_INC, XEXP (addr, 0));
5946 ;; If the output is a register and the input is memory or a register, we have
5947 ;; to be careful and see which word needs to be loaded first.
5949 [(set (match_operand:DF 0 "general_movdst_operand" "")
5950 (match_operand:DF 1 "general_movsrc_operand" ""))]
5951 "TARGET_SH1 && reload_completed"
5952 [(set (match_dup 2) (match_dup 3))
5953 (set (match_dup 4) (match_dup 5))]
5957 if ((MEM_P (operands[0])
5958 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
5959 || (MEM_P (operands[1])
5960 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
5963 switch (GET_CODE (operands[0]))
5966 regno = REGNO (operands[0]);
5969 regno = subreg_regno (operands[0]);
5978 if (regno == -1 || ! refers_to_regno_p (regno, operands[1]))
5980 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
5981 operands[3] = operand_subword (operands[1], 0, 0, DFmode);
5982 operands[4] = operand_subword (operands[0], 1, 0, DFmode);
5983 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
5987 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
5988 operands[3] = operand_subword (operands[1], 1, 0, DFmode);
5989 operands[4] = operand_subword (operands[0], 0, 0, DFmode);
5990 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
5993 if (operands[2] == 0 || operands[3] == 0
5994 || operands[4] == 0 || operands[5] == 0)
5998 (define_expand "movdf"
5999 [(set (match_operand:DF 0 "general_movdst_operand" "")
6000 (match_operand:DF 1 "general_movsrc_operand" ""))]
6003 prepare_move_operands (operands, DFmode);
6004 if (TARGET_FPU_DOUBLE)
6006 emit_insn (gen_movdf_i4 (operands[0], operands[1]));
6011 ;; FIXME Although the movsf_i pattern is not used when there's an FPU,
6012 ;; it somehow influences some RA choices also on FPU targets.
6013 ;; For non-FPU targets it's actually not needed.
6014 (define_insn "movsf_i"
6015 [(set (match_operand:SF 0 "general_movdst_operand" "=r,r, r, r,m,l,r")
6016 (match_operand:SF 1 "general_movsrc_operand" "r,G,FQ,mr,r,r,l"))]
6019 /* ??? We provide some insn so that direct_{load,store}[SFmode] get set */
6020 || (REG_P (operands[0]) && REGNO (operands[0]) == 3)
6021 || (REG_P (operands[1]) && REGNO (operands[1]) == 3))
6022 && (arith_reg_operand (operands[0], SFmode)
6023 || arith_reg_operand (operands[1], SFmode))"
6032 [(set_attr "type" "move,move,pcload,load,store,move,move")
6033 (set_attr_alternative "length"
6036 (if_then_else (match_operand 1 "long_displacement_mem_operand")
6037 (const_int 4) (const_int 2))
6038 (if_then_else (match_operand 1 "long_displacement_mem_operand")
6039 (const_int 4) (const_int 2))
6040 (if_then_else (match_operand 0 "long_displacement_mem_operand")
6041 (const_int 4) (const_int 2))
6045 ;; We may not split the ry/yr/XX alternatives to movsi_ie, since
6046 ;; update_flow_info would not know where to put REG_EQUAL notes
6047 ;; when the destination changes mode.
6048 (define_insn "movsf_ie"
6049 [(set (match_operand:SF 0 "general_movdst_operand"
6050 "=f,r,f,f,fy, f,m, r, r,m,f,y,y,rf,r,y,<,y,y")
6051 (match_operand:SF 1 "general_movsrc_operand"
6052 " f,r,G,H,FQ,mf,f,FQ,mr,r,y,f,>,fr,y,r,y,>,y"))
6053 (use (reg:SI FPSCR_MODES_REG))
6054 (clobber (match_scratch:SI 2 "=X,X,X,X,&z, X,X, X, X,X,X,X,X, y,X,X,X,X,X"))]
6056 && (arith_reg_operand (operands[0], SFmode)
6057 || fpul_operand (operands[0], SFmode)
6058 || arith_reg_operand (operands[1], SFmode)
6059 || fpul_operand (operands[1], SFmode)
6060 || arith_reg_operand (operands[2], SImode))"
6080 ! move optimized away"
6081 [(set_attr "type" "fmove,move,fmove,fmove,pcfload,fload,fstore,pcload,load,
6082 store,fmove,fmove,load,*,fpul_gp,gp_fpul,fstore,load,nil")
6083 (set_attr "late_fp_use" "*,*,*,*,*,*,yes,*,*,*,*,*,*,*,yes,*,yes,*,*")
6084 (set_attr_alternative "length"
6090 (if_then_else (match_operand 1 "displacement_mem_operand")
6091 (const_int 4) (const_int 2))
6092 (if_then_else (match_operand 0 "displacement_mem_operand")
6093 (const_int 4) (const_int 2))
6095 (if_then_else (match_operand 1 "long_displacement_mem_operand")
6096 (const_int 4) (const_int 2))
6097 (if_then_else (match_operand 0 "long_displacement_mem_operand")
6098 (const_int 4) (const_int 2))
6108 (set_attr_alternative "fp_mode"
6109 [(if_then_else (eq_attr "fmovd" "yes")
6110 (const_string "single") (const_string "none"))
6111 (const_string "none")
6112 (const_string "single")
6113 (const_string "single")
6114 (const_string "none")
6115 (if_then_else (eq_attr "fmovd" "yes")
6116 (const_string "single") (const_string "none"))
6117 (if_then_else (eq_attr "fmovd" "yes")
6118 (const_string "single") (const_string "none"))
6119 (const_string "none")
6120 (const_string "none")
6121 (const_string "none")
6122 (const_string "none")
6123 (const_string "none")
6124 (const_string "none")
6125 (const_string "none")
6126 (const_string "none")
6127 (const_string "none")
6128 (const_string "none")
6129 (const_string "none")
6130 (const_string "none")])])
6132 (define_insn_and_split "movsf_ie_ra"
6133 [(set (match_operand:SF 0 "general_movdst_operand"
6134 "=f,r,f,f,fy,f,m, r,r,m,f,y,y,rf,r,y,<,y,y")
6135 (match_operand:SF 1 "general_movsrc_operand"
6136 " f,r,G,H,FQ,m,f,FQ,m,r,y,f,>,fr,y,r,y,>,y"))
6137 (use (reg:SI FPSCR_MODES_REG))
6138 (clobber (match_scratch:SF 2 "=r,r,X,X,&z,r,r, X,r,r,r,r,r, y,r,r,r,r,r"))
6141 && (arith_reg_operand (operands[0], SFmode)
6142 || fpul_operand (operands[0], SFmode)
6143 || arith_reg_operand (operands[1], SFmode)
6144 || fpul_operand (operands[1], SFmode))"
6164 ! move optimized away"
6166 && sh_movsf_ie_ra_split_p (operands[0], operands[1], operands[2])"
6169 if (! rtx_equal_p (operands[0], operands[1]))
6171 emit_insn (gen_movsf_ie (operands[2], operands[1]));
6172 emit_insn (gen_movsf_ie (operands[0], operands[2]));
6175 [(set_attr "type" "fmove,move,fmove,fmove,pcfload,fload,fstore,pcload,load,
6176 store,fmove,fmove,load,*,fpul_gp,gp_fpul,fstore,load,nil")
6177 (set_attr "late_fp_use" "*,*,*,*,*,*,yes,*,*,*,*,*,*,*,yes,*,yes,*,*")
6178 (set_attr_alternative "length"
6184 (if_then_else (match_operand 1 "displacement_mem_operand")
6185 (const_int 4) (const_int 2))
6186 (if_then_else (match_operand 0 "displacement_mem_operand")
6187 (const_int 4) (const_int 2))
6189 (if_then_else (match_operand 1 "long_displacement_mem_operand")
6190 (const_int 4) (const_int 2))
6191 (if_then_else (match_operand 0 "long_displacement_mem_operand")
6192 (const_int 4) (const_int 2))
6202 (set_attr_alternative "fp_mode"
6203 [(if_then_else (eq_attr "fmovd" "yes")
6204 (const_string "single") (const_string "none"))
6205 (const_string "none")
6206 (const_string "single")
6207 (const_string "single")
6208 (const_string "none")
6209 (if_then_else (eq_attr "fmovd" "yes")
6210 (const_string "single") (const_string "none"))
6211 (if_then_else (eq_attr "fmovd" "yes")
6212 (const_string "single") (const_string "none"))
6213 (const_string "none")
6214 (const_string "none")
6215 (const_string "none")
6216 (const_string "none")
6217 (const_string "none")
6218 (const_string "none")
6219 (const_string "none")
6220 (const_string "none")
6221 (const_string "none")
6222 (const_string "none")
6223 (const_string "none")
6224 (const_string "none")])])
6227 [(set (match_operand:SF 0 "register_operand" "")
6228 (match_operand:SF 1 "register_operand" ""))
6229 (use (reg:SI FPSCR_MODES_REG))
6230 (clobber (reg:SI FPUL_REG))]
6232 [(parallel [(set (reg:SF FPUL_REG) (match_dup 1))
6233 (use (reg:SI FPSCR_MODES_REG))
6234 (clobber (scratch:SI))])
6235 (parallel [(set (match_dup 0) (reg:SF FPUL_REG))
6236 (use (reg:SI FPSCR_MODES_REG))
6237 (clobber (scratch:SI))])]
6240 (define_expand "movsf"
6241 [(set (match_operand:SF 0 "general_movdst_operand" "")
6242 (match_operand:SF 1 "general_movsrc_operand" ""))]
6245 prepare_move_operands (operands, SFmode);
6248 if (lra_in_progress)
6250 if (GET_CODE (operands[0]) == SCRATCH)
6252 emit_insn (gen_movsf_ie_ra (operands[0], operands[1]));
6256 emit_insn (gen_movsf_ie (operands[0], operands[1]));
6261 (define_expand "reload_insf__frn"
6262 [(parallel [(set (match_operand:SF 0 "register_operand" "=a")
6263 (match_operand:SF 1 "immediate_operand" "FQ"))
6264 (use (reg:SI FPSCR_MODES_REG))
6265 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
6269 (define_expand "reload_insi__i_fpul"
6270 [(parallel [(set (match_operand:SI 0 "fpul_operand" "=y")
6271 (match_operand:SI 1 "immediate_operand" "i"))
6272 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
6276 (define_insn "*movsi_y"
6277 [(set (match_operand:SI 0 "register_operand" "=y,y")
6278 (match_operand:SI 1 "immediate_operand" "Qi,I08"))
6279 (clobber (match_scratch:SI 2 "=&z,r"))]
6281 && (reload_in_progress || reload_completed)"
6283 [(set_attr "length" "4")
6284 (set_attr "type" "pcload,move")])
6287 [(set (match_operand:SI 0 "register_operand" "")
6288 (match_operand:SI 1 "immediate_operand" ""))
6289 (clobber (match_operand:SI 2 "register_operand" ""))]
6291 [(set (match_dup 2) (match_dup 1))
6292 (set (match_dup 0) (match_dup 2))]
6295 ;; ------------------------------------------------------------------------
6296 ;; Define the real conditional branch instructions.
6297 ;; ------------------------------------------------------------------------
6299 (define_expand "branch_true"
6300 [(set (pc) (if_then_else (ne (reg:SI T_REG) (const_int 0))
6301 (label_ref (match_operand 0))
6305 (define_expand "branch_false"
6306 [(set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
6307 (label_ref (match_operand 0))
6311 (define_insn_and_split "*cbranch_t"
6312 [(set (pc) (if_then_else (match_operand 1 "cbranch_treg_value")
6313 (label_ref (match_operand 0))
6317 return output_branch (sh_eval_treg_value (operands[1]), insn, operands);
6322 /* Try to canonicalize the branch condition if it is not one of:
6323 (ne (reg:SI T_REG) (const_int 0))
6324 (eq (reg:SI T_REG) (const_int 0))
6326 Instead of splitting out a new insn, we modify the current insn's
6327 operands as needed. This preserves things such as REG_DEAD notes. */
6329 if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
6330 && REG_P (XEXP (operands[1], 0)) && REGNO (XEXP (operands[1], 0)) == T_REG
6331 && XEXP (operands[1], 1) == const0_rtx)
6334 int branch_cond = sh_eval_treg_value (operands[1]);
6335 rtx new_cond_rtx = NULL_RTX;
6337 if (branch_cond == 0)
6338 new_cond_rtx = gen_rtx_EQ (VOIDmode, get_t_reg_rtx (), const0_rtx);
6339 else if (branch_cond == 1)
6340 new_cond_rtx = gen_rtx_NE (VOIDmode, get_t_reg_rtx (), const0_rtx);
6342 if (new_cond_rtx != NULL_RTX)
6343 validate_change (curr_insn, &XEXP (XEXP (PATTERN (curr_insn), 1), 0),
6344 new_cond_rtx, false);
6347 [(set_attr "type" "cbranch")])
6349 ;; Patterns to prevent reorg from re-combining a condbranch with a branch
6350 ;; which destination is too far away.
6351 ;; The const_int_operand is distinct for each branch target; it avoids
6352 ;; unwanted matches with redundant_insn.
6353 (define_insn "block_branch_redirect"
6354 [(set (pc) (unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BBR))]
6357 [(set_attr "length" "0")])
6359 ;; This one has the additional purpose to record a possible scratch register
6360 ;; for the following branch.
6361 ;; ??? Unfortunately, just setting the scratch register is not good enough,
6362 ;; because the insn then might be deemed dead and deleted. And we can't
6363 ;; make the use in the jump insn explicit because that would disable
6364 ;; delay slot scheduling from the target.
6365 (define_insn "indirect_jump_scratch"
6366 [(set (match_operand:SI 0 "register_operand" "=r")
6367 (unspec:SI [(match_operand 1 "const_int_operand" "")] UNSPEC_BBR))
6368 (set (pc) (unspec [(const_int 0)] UNSPEC_BBR))]
6371 [(set_attr "length" "0")])
6373 ;; This one is used to preemt an insn from beyond the bra / braf / jmp
6374 ;; being pulled into the delay slot of a condbranch that has been made to
6375 ;; jump around the unconditional jump because it was out of range.
6376 (define_insn "stuff_delay_slot"
6378 (unspec [(match_operand:SI 0 "const_int_operand" "") (pc)
6379 (match_operand:SI 1 "const_int_operand" "")] UNSPEC_BBR))]
6382 [(set_attr "length" "0")
6383 (set_attr "cond_delay_slot" "yes")])
6385 ;; Conditional branch insns
6387 ; operand 0 is the loop count pseudo register
6388 ; operand 1 is the label to jump to at the top of the loop
6389 (define_expand "doloop_end"
6390 [(parallel [(set (pc)
6391 (if_then_else (ne:SI (match_operand:SI 0 "" "")
6393 (label_ref (match_operand 1 "" ""))
6396 (plus:SI (match_dup 0) (const_int -1)))
6397 (clobber (reg:SI T_REG))])]
6400 if (GET_MODE (operands[0]) != SImode)
6402 emit_jump_insn (gen_doloop_end_split (operands[0], operands[1], operands[0]));
6406 (define_insn_and_split "doloop_end_split"
6408 (if_then_else (ne:SI (match_operand:SI 2 "arith_reg_dest" "0")
6410 (label_ref (match_operand 1 "" ""))
6412 (set (match_operand:SI 0 "arith_reg_dest" "=r")
6413 (plus:SI (match_dup 2) (const_int -1)))
6414 (clobber (reg:SI T_REG))]
6418 [(parallel [(set (reg:SI T_REG)
6419 (eq:SI (match_dup 2) (const_int 1)))
6420 (set (match_dup 0) (plus:SI (match_dup 2) (const_int -1)))])
6421 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
6422 (label_ref (match_dup 1))
6425 [(set_attr "type" "cbranch")])
6427 ;; ------------------------------------------------------------------------
6428 ;; Jump and linkage insns
6429 ;; ------------------------------------------------------------------------
6431 (define_insn "jump_compact"
6433 (label_ref (match_operand 0 "" "")))]
6434 "TARGET_SH1 && !CROSSING_JUMP_P (insn)"
6436 /* The length is 16 if the delay slot is unfilled. */
6437 if (get_attr_length(insn) > 4)
6438 return output_far_jump(insn, operands[0]);
6442 [(set_attr "type" "jump")
6443 (set_attr "needs_delay_slot" "yes")])
6445 (define_insn "*jump_compact_crossing"
6447 (label_ref (match_operand 0 "" "")))]
6449 && flag_reorder_blocks_and_partition
6450 && CROSSING_JUMP_P (insn)"
6452 /* The length is 16 if the delay slot is unfilled. */
6453 return output_far_jump(insn, operands[0]);
6455 [(set_attr "type" "jump")
6456 (set_attr "length" "16")])
6458 (define_expand "jump"
6460 (label_ref (match_operand 0 "" "")))]
6463 emit_jump_insn (gen_jump_compact (operands[0]));
6467 (define_insn "calli"
6468 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
6469 (match_operand 1 "" ""))
6470 (use (reg:SI FPSCR_MODES_REG))
6471 (clobber (reg:SI PR_REG))]
6472 "TARGET_SH1 && !TARGET_FDPIC"
6474 if (TARGET_SH2A && dbr_sequence_length () == 0)
6479 [(set_attr "type" "call")
6480 (set (attr "fp_mode")
6481 (if_then_else (eq_attr "fpu_single" "yes")
6482 (const_string "single") (const_string "double")))
6483 (set_attr "needs_delay_slot" "yes")
6484 (set_attr "fp_set" "unknown")])
6486 (define_insn "calli_fdpic"
6487 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
6489 (use (reg:SI FPSCR_MODES_REG))
6490 (use (reg:SI PIC_REG))
6491 (clobber (reg:SI PR_REG))]
6494 if (TARGET_SH2A && dbr_sequence_length () == 0)
6499 [(set_attr "type" "call")
6500 (set (attr "fp_mode")
6501 (if_then_else (eq_attr "fpu_single" "yes")
6502 (const_string "single") (const_string "double")))
6503 (set_attr "needs_delay_slot" "yes")
6504 (set_attr "fp_set" "unknown")])
6506 ;; This is TBR relative jump instruction for SH2A architecture.
6507 ;; Its use is enabled by assigning an attribute "function_vector"
6508 ;; and the vector number to a function during its declaration.
6509 (define_insn "calli_tbr_rel"
6510 [(call (mem (match_operand:SI 0 "symbol_ref_operand" ""))
6511 (match_operand 1 "" ""))
6512 (use (reg:SI FPSCR_MODES_REG))
6513 (clobber (reg:SI PR_REG))]
6514 "TARGET_SH2A && sh2a_is_function_vector_call (operands[0])"
6516 unsigned HOST_WIDE_INT vect_num;
6517 vect_num = sh2a_get_function_vector_number (operands[0]);
6518 operands[2] = GEN_INT (vect_num * 4);
6520 return "jsr/n @@(%O2,tbr)";
6522 [(set_attr "type" "call")
6523 (set (attr "fp_mode")
6524 (if_then_else (eq_attr "fpu_single" "yes")
6525 (const_string "single") (const_string "double")))
6526 (set_attr "needs_delay_slot" "no")
6527 (set_attr "fp_set" "unknown")])
6529 ;; This is a pc-rel call, using bsrf, for use with PIC.
6530 (define_insn "calli_pcrel"
6531 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
6532 (match_operand 1 "" ""))
6533 (use (reg:SI FPSCR_MODES_REG))
6534 (use (reg:SI PIC_REG))
6535 (use (match_operand 2 "" ""))
6536 (clobber (reg:SI PR_REG))]
6539 return "bsrf %0" "\n"
6542 [(set_attr "type" "call")
6543 (set (attr "fp_mode")
6544 (if_then_else (eq_attr "fpu_single" "yes")
6545 (const_string "single") (const_string "double")))
6546 (set_attr "needs_delay_slot" "yes")
6547 (set_attr "fp_set" "unknown")])
6549 (define_insn_and_split "call_pcrel"
6550 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
6551 (match_operand 1 "" ""))
6552 (use (reg:SI FPSCR_MODES_REG))
6553 (use (reg:SI PIC_REG))
6554 (clobber (reg:SI PR_REG))
6555 (clobber (match_scratch:SI 2 "=&r"))]
6561 rtx lab = PATTERN (gen_call_site ());
6563 sh_expand_sym_label2reg (operands[2], operands[0], lab, false);
6564 emit_call_insn (gen_calli_pcrel (operands[2], operands[1], copy_rtx (lab)));
6567 [(set_attr "type" "call")
6568 (set (attr "fp_mode")
6569 (if_then_else (eq_attr "fpu_single" "yes")
6570 (const_string "single") (const_string "double")))
6571 (set_attr "needs_delay_slot" "yes")
6572 (set_attr "fp_set" "unknown")])
6574 (define_insn "call_valuei"
6575 [(set (match_operand 0 "" "=rf")
6576 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
6577 (match_operand 2 "" "")))
6578 (use (reg:SI FPSCR_MODES_REG))
6579 (clobber (reg:SI PR_REG))]
6580 "TARGET_SH1 && !TARGET_FDPIC"
6582 if (TARGET_SH2A && dbr_sequence_length () == 0)
6587 [(set_attr "type" "call")
6588 (set (attr "fp_mode")
6589 (if_then_else (eq_attr "fpu_single" "yes")
6590 (const_string "single") (const_string "double")))
6591 (set_attr "needs_delay_slot" "yes")
6592 (set_attr "fp_set" "unknown")])
6594 (define_insn "call_valuei_fdpic"
6595 [(set (match_operand 0 "" "=rf")
6596 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
6598 (use (reg:SI FPSCR_REG))
6599 (use (reg:SI PIC_REG))
6600 (clobber (reg:SI PR_REG))]
6603 if (TARGET_SH2A && dbr_sequence_length () == 0)
6608 [(set_attr "type" "call")
6609 (set (attr "fp_mode")
6610 (if_then_else (eq_attr "fpu_single" "yes")
6611 (const_string "single") (const_string "double")))
6612 (set_attr "needs_delay_slot" "yes")
6613 (set_attr "fp_set" "unknown")])
6615 ;; This is TBR relative jump instruction for SH2A architecture.
6616 ;; Its use is enabled by assigning an attribute "function_vector"
6617 ;; and the vector number to a function during its declaration.
6618 (define_insn "call_valuei_tbr_rel"
6619 [(set (match_operand 0 "" "=rf")
6620 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
6621 (match_operand 2 "" "")))
6622 (use (reg:SI FPSCR_MODES_REG))
6623 (clobber (reg:SI PR_REG))]
6624 "TARGET_SH2A && sh2a_is_function_vector_call (operands[1])"
6626 unsigned HOST_WIDE_INT vect_num;
6627 vect_num = sh2a_get_function_vector_number (operands[1]);
6628 operands[3] = GEN_INT (vect_num * 4);
6630 return "jsr/n @@(%O3,tbr)";
6632 [(set_attr "type" "call")
6633 (set (attr "fp_mode")
6634 (if_then_else (eq_attr "fpu_single" "yes")
6635 (const_string "single") (const_string "double")))
6636 (set_attr "needs_delay_slot" "no")
6637 (set_attr "fp_set" "unknown")])
6639 (define_insn "call_valuei_pcrel"
6640 [(set (match_operand 0 "" "=rf")
6641 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
6642 (match_operand 2 "" "")))
6643 (use (reg:SI FPSCR_MODES_REG))
6644 (use (reg:SI PIC_REG))
6645 (use (match_operand 3 "" ""))
6646 (clobber (reg:SI PR_REG))]
6649 return "bsrf %1" "\n"
6652 [(set_attr "type" "call")
6653 (set (attr "fp_mode")
6654 (if_then_else (eq_attr "fpu_single" "yes")
6655 (const_string "single") (const_string "double")))
6656 (set_attr "needs_delay_slot" "yes")
6657 (set_attr "fp_set" "unknown")])
6659 (define_insn_and_split "call_value_pcrel"
6660 [(set (match_operand 0 "" "=rf")
6661 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
6662 (match_operand 2 "" "")))
6663 (use (reg:SI FPSCR_MODES_REG))
6664 (use (reg:SI PIC_REG))
6665 (clobber (reg:SI PR_REG))
6666 (clobber (match_scratch:SI 3 "=&r"))]
6672 rtx lab = PATTERN (gen_call_site ());
6674 sh_expand_sym_label2reg (operands[3], operands[1], lab, false);
6675 emit_call_insn (gen_call_valuei_pcrel (operands[0], operands[3],
6676 operands[2], copy_rtx (lab)));
6679 [(set_attr "type" "call")
6680 (set (attr "fp_mode")
6681 (if_then_else (eq_attr "fpu_single" "yes")
6682 (const_string "single") (const_string "double")))
6683 (set_attr "needs_delay_slot" "yes")
6684 (set_attr "fp_set" "unknown")])
6686 (define_expand "call"
6687 [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
6688 (match_operand 1 "" ""))
6689 (match_operand 2 "" "")
6690 (use (reg:SI FPSCR_MODES_REG))
6691 (clobber (reg:SI PR_REG))])]
6696 rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
6697 emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
6700 if (!flag_pic && TARGET_SH2A
6701 && MEM_P (operands[0])
6702 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6704 if (sh2a_is_function_vector_call (XEXP (operands[0], 0)))
6706 emit_call_insn (gen_calli_tbr_rel (XEXP (operands[0], 0),
6711 if (flag_pic && TARGET_SH2
6712 && MEM_P (operands[0])
6713 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6715 emit_call_insn (gen_call_pcrel (XEXP (operands[0], 0), operands[1]));
6720 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
6721 operands[1] = operands[2];
6726 operands[0] = sh_load_function_descriptor (operands[0]);
6727 emit_call_insn (gen_calli_fdpic (operands[0], operands[1]));
6730 emit_call_insn (gen_calli (operands[0], operands[1]));
6734 (define_expand "call_value"
6735 [(parallel [(set (match_operand 0 "arith_reg_operand" "")
6736 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
6737 (match_operand 2 "" "")))
6738 (match_operand 3 "" "")
6739 (use (reg:SI FPSCR_MODES_REG))
6740 (clobber (reg:SI PR_REG))])]
6745 rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
6746 emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
6749 if (!flag_pic && TARGET_SH2A
6750 && MEM_P (operands[1])
6751 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6753 if (sh2a_is_function_vector_call (XEXP (operands[1], 0)))
6755 emit_call_insn (gen_call_valuei_tbr_rel (operands[0],
6756 XEXP (operands[1], 0), operands[2]));
6760 if (flag_pic && TARGET_SH2
6761 && MEM_P (operands[1])
6762 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6764 emit_call_insn (gen_call_value_pcrel (operands[0], XEXP (operands[1], 0),
6769 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
6773 operands[1] = sh_load_function_descriptor (operands[1]);
6774 emit_call_insn (gen_call_valuei_fdpic (operands[0], operands[1],
6778 emit_call_insn (gen_call_valuei (operands[0], operands[1], operands[2]));
6782 (define_insn "sibcalli"
6783 [(call (mem:SI (match_operand:SI 0 "register_operand" "k"))
6784 (match_operand 1 "" ""))
6785 (use (reg:SI FPSCR_MODES_REG))
6787 "TARGET_SH1 && !TARGET_FDPIC"
6789 [(set_attr "needs_delay_slot" "yes")
6790 (set (attr "fp_mode")
6791 (if_then_else (eq_attr "fpu_single" "yes")
6792 (const_string "single") (const_string "double")))
6793 (set_attr "type" "jump_ind")])
6795 (define_insn "sibcalli_fdpic"
6796 [(call (mem:SI (match_operand:SI 0 "register_operand" "k"))
6798 (use (reg:SI FPSCR_MODES_REG))
6799 (use (reg:SI PIC_REG))
6803 [(set_attr "needs_delay_slot" "yes")
6804 (set (attr "fp_mode")
6805 (if_then_else (eq_attr "fpu_single" "yes")
6806 (const_string "single") (const_string "double")))
6807 (set_attr "type" "jump_ind")])
6809 (define_insn "sibcalli_pcrel"
6810 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "k"))
6811 (match_operand 1 "" ""))
6812 (use (match_operand 2 "" ""))
6813 (use (reg:SI FPSCR_MODES_REG))
6815 "TARGET_SH2 && !TARGET_FDPIC"
6817 return "braf %0" "\n"
6820 [(set_attr "needs_delay_slot" "yes")
6821 (set (attr "fp_mode")
6822 (if_then_else (eq_attr "fpu_single" "yes")
6823 (const_string "single") (const_string "double")))
6824 (set_attr "type" "jump_ind")])
6826 (define_insn "sibcalli_pcrel_fdpic"
6827 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "k"))
6829 (use (match_operand 2))
6830 (use (reg:SI FPSCR_MODES_REG))
6831 (use (reg:SI PIC_REG))
6833 "TARGET_SH2 && TARGET_FDPIC"
6835 return "braf %0" "\n"
6838 [(set_attr "needs_delay_slot" "yes")
6839 (set (attr "fp_mode")
6840 (if_then_else (eq_attr "fpu_single" "yes")
6841 (const_string "single") (const_string "double")))
6842 (set_attr "type" "jump_ind")])
6844 ;; This uses an unspec to describe that the symbol_ref is very close.
6845 (define_insn "sibcalli_thunk"
6846 [(call (mem:SI (unspec:SI [(match_operand:SI 0 "symbol_ref_operand" "")]
6848 (match_operand 1 "" ""))
6849 (use (reg:SI FPSCR_MODES_REG))
6853 [(set_attr "needs_delay_slot" "yes")
6854 (set (attr "fp_mode")
6855 (if_then_else (eq_attr "fpu_single" "yes")
6856 (const_string "single") (const_string "double")))
6857 (set_attr "type" "jump")
6858 (set_attr "length" "2")])
6860 (define_insn_and_split "sibcall_pcrel"
6861 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
6862 (match_operand 1 "" ""))
6863 (use (reg:SI FPSCR_MODES_REG))
6864 (clobber (match_scratch:SI 2 "=&k"))
6866 "TARGET_SH2 && !TARGET_FDPIC"
6871 rtx lab = PATTERN (gen_call_site ());
6874 sh_expand_sym_label2reg (operands[2], operands[0], lab, true);
6875 call_insn = emit_call_insn (gen_sibcalli_pcrel (operands[2], operands[1],
6877 SIBLING_CALL_P (call_insn) = 1;
6880 [(set_attr "needs_delay_slot" "yes")
6881 (set (attr "fp_mode")
6882 (if_then_else (eq_attr "fpu_single" "yes")
6883 (const_string "single") (const_string "double")))
6884 (set_attr "type" "jump_ind")])
6886 (define_insn_and_split "sibcall_pcrel_fdpic"
6887 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand"))
6889 (use (reg:SI FPSCR_MODES_REG))
6890 (use (reg:SI PIC_REG))
6891 (clobber (match_scratch:SI 2 "=k"))
6893 "TARGET_SH2 && TARGET_FDPIC"
6895 "&& reload_completed"
6898 rtx lab = PATTERN (gen_call_site ());
6900 sh_expand_sym_label2reg (operands[2], operands[0], lab, true);
6901 rtx i = emit_call_insn (gen_sibcalli_pcrel_fdpic (operands[2], operands[1],
6903 SIBLING_CALL_P (i) = 1;
6906 [(set_attr "needs_delay_slot" "yes")
6907 (set (attr "fp_mode")
6908 (if_then_else (eq_attr "fpu_single" "yes")
6909 (const_string "single") (const_string "double")))
6910 (set_attr "type" "jump_ind")])
6912 (define_expand "sibcall"
6914 [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
6915 (match_operand 1 "" ""))
6916 (match_operand 2 "" "")
6917 (use (reg:SI FPSCR_MODES_REG))
6923 rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
6924 emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
6927 if (flag_pic && TARGET_SH2
6928 && MEM_P (operands[0])
6929 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
6930 /* The PLT needs the PIC register, but the epilogue would have
6931 to restore it, so we can only use PC-relative PIC calls for
6932 static functions. */
6933 && SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
6936 emit_call_insn (gen_sibcall_pcrel_fdpic (XEXP (operands[0], 0),
6939 emit_call_insn (gen_sibcall_pcrel (XEXP (operands[0], 0), operands[1]));
6943 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
6947 operands[0] = sh_load_function_descriptor (operands[0]);
6948 emit_call_insn (gen_sibcalli_fdpic (operands[0], operands[1]));
6951 emit_call_insn (gen_sibcalli (operands[0], operands[1]));
6955 (define_insn "sibcall_valuei"
6956 [(set (match_operand 0 "" "=rf")
6957 (call (mem:SI (match_operand:SI 1 "register_operand" "k"))
6958 (match_operand 2 "" "")))
6959 (use (reg:SI FPSCR_MODES_REG))
6961 "TARGET_SH1 && !TARGET_FDPIC"
6963 [(set_attr "needs_delay_slot" "yes")
6964 (set (attr "fp_mode")
6965 (if_then_else (eq_attr "fpu_single" "yes")
6966 (const_string "single") (const_string "double")))
6967 (set_attr "type" "jump_ind")])
6969 (define_insn "sibcall_valuei_fdpic"
6970 [(set (match_operand 0 "" "=rf")
6971 (call (mem:SI (match_operand:SI 1 "register_operand" "k"))
6973 (use (reg:SI FPSCR_MODES_REG))
6974 (use (reg:SI PIC_REG))
6978 [(set_attr "needs_delay_slot" "yes")
6979 (set (attr "fp_mode")
6980 (if_then_else (eq_attr "fpu_single" "yes")
6981 (const_string "single") (const_string "double")))
6982 (set_attr "type" "jump_ind")])
6984 (define_insn "sibcall_valuei_pcrel"
6985 [(set (match_operand 0 "" "=rf")
6986 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "k"))
6987 (match_operand 2 "" "")))
6988 (use (match_operand 3 "" ""))
6989 (use (reg:SI FPSCR_MODES_REG))
6991 "TARGET_SH2 && !TARGET_FDPIC"
6993 return "braf %1" "\n"
6996 [(set_attr "needs_delay_slot" "yes")
6997 (set (attr "fp_mode")
6998 (if_then_else (eq_attr "fpu_single" "yes")
6999 (const_string "single") (const_string "double")))
7000 (set_attr "type" "jump_ind")])
7002 (define_insn "sibcall_valuei_pcrel_fdpic"
7003 [(set (match_operand 0 "" "=rf")
7004 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "k"))
7006 (use (match_operand 3))
7007 (use (reg:SI FPSCR_MODES_REG))
7008 (use (reg:SI PIC_REG))
7010 "TARGET_SH2 && TARGET_FDPIC"
7012 return "braf %1" "\n"
7015 [(set_attr "needs_delay_slot" "yes")
7016 (set (attr "fp_mode")
7017 (if_then_else (eq_attr "fpu_single" "yes")
7018 (const_string "single") (const_string "double")))
7019 (set_attr "type" "jump_ind")])
7021 ;; sibcall_value_pcrel used to have a =&k clobber for the scratch register
7022 ;; that it needs for the branch address. This causes troubles when there
7023 ;; is a big overlap of argument and return value registers. Hence, use a
7024 ;; fixed call clobbered register for the address. See also PR 67260.
7025 (define_insn_and_split "sibcall_value_pcrel"
7026 [(set (match_operand 0 "" "=rf")
7027 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
7028 (match_operand 2 "" "")))
7029 (use (reg:SI FPSCR_MODES_REG))
7030 (clobber (reg:SI R1_REG))
7032 "TARGET_SH2 && !TARGET_FDPIC"
7037 rtx lab = PATTERN (gen_call_site ());
7040 operands[3] = gen_rtx_REG (SImode, R1_REG);
7042 sh_expand_sym_label2reg (operands[3], operands[1], lab, true);
7043 call_insn = emit_call_insn (gen_sibcall_valuei_pcrel (operands[0],
7047 SIBLING_CALL_P (call_insn) = 1;
7050 [(set_attr "needs_delay_slot" "yes")
7051 (set (attr "fp_mode")
7052 (if_then_else (eq_attr "fpu_single" "yes")
7053 (const_string "single") (const_string "double")))
7054 (set_attr "type" "jump_ind")])
7056 ;; Like for sibcall_value_pcrel, use a fixed call clobbered register for
7057 ;; the branch address.
7058 (define_insn_and_split "sibcall_value_pcrel_fdpic"
7059 [(set (match_operand 0 "" "=rf")
7060 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand"))
7062 (use (reg:SI FPSCR_MODES_REG))
7063 (use (reg:SI PIC_REG))
7064 (clobber (reg:SI R1_REG))
7066 "TARGET_SH2 && TARGET_FDPIC"
7068 "&& reload_completed"
7071 rtx lab = PATTERN (gen_call_site ());
7073 operands[3] = gen_rtx_REG (SImode, R1_REG);
7075 sh_expand_sym_label2reg (operands[3], operands[1], lab, true);
7076 rtx i = emit_call_insn (gen_sibcall_valuei_pcrel_fdpic (operands[0],
7080 SIBLING_CALL_P (i) = 1;
7083 [(set_attr "needs_delay_slot" "yes")
7084 (set (attr "fp_mode")
7085 (if_then_else (eq_attr "fpu_single" "yes")
7086 (const_string "single") (const_string "double")))
7087 (set_attr "type" "jump_ind")])
7089 (define_expand "sibcall_value"
7091 [(set (match_operand 0 "arith_reg_operand" "")
7092 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
7093 (match_operand 2 "" "")))
7094 (match_operand 3 "" "")
7095 (use (reg:SI FPSCR_MODES_REG))
7101 rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
7102 emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
7105 if (flag_pic && TARGET_SH2
7106 && MEM_P (operands[1])
7107 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
7108 /* The PLT needs the PIC register, but the epilogue would have
7109 to restore it, so we can only use PC-relative PIC calls for
7110 static functions. */
7111 && SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0)))
7114 emit_call_insn (gen_sibcall_value_pcrel_fdpic (operands[0],
7115 XEXP (operands[1], 0),
7118 emit_call_insn (gen_sibcall_value_pcrel (operands[0],
7119 XEXP (operands[1], 0),
7124 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
7128 operands[1] = sh_load_function_descriptor (operands[1]);
7129 emit_call_insn (gen_sibcall_valuei_fdpic (operands[0], operands[1],
7133 emit_call_insn (gen_sibcall_valuei (operands[0], operands[1], operands[2]));
7137 (define_expand "sibcall_epilogue"
7141 sh_expand_epilogue (true);
7145 (define_insn "indirect_jump_compact"
7147 (match_operand:SI 0 "arith_reg_operand" "r"))]
7150 [(set_attr "needs_delay_slot" "yes")
7151 (set_attr "type" "jump_ind")])
7153 (define_expand "indirect_jump"
7155 (match_operand 0 "register_operand" ""))]
7158 if (GET_MODE (operands[0]) != Pmode)
7159 operands[0] = gen_rtx_SUBREG (Pmode, operands[0], 0);
7162 ;; The use of operand 1 / 2 helps us distinguish case table jumps
7163 ;; which can be present in structured code from indirect jumps which can not
7164 ;; be present in structured code. This allows -fprofile-arcs to work.
7166 ;; For SH1 processors.
7167 (define_insn "casesi_jump_1"
7169 (match_operand:SI 0 "register_operand" "r"))
7170 (use (label_ref (match_operand 1 "" "")))]
7173 [(set_attr "needs_delay_slot" "yes")
7174 (set_attr "type" "jump_ind")])
7176 ;; For all later processors.
7177 (define_insn "casesi_jump_2"
7178 [(set (pc) (plus:SI (match_operand:SI 0 "register_operand" "r")
7179 (label_ref (match_operand 1 "" ""))))
7180 (use (label_ref (match_operand 2 "" "")))]
7182 && (! INSN_UID (operands[1])
7183 || prev_real_insn (as_a<rtx_insn *> (operands[1])) == insn)"
7185 [(set_attr "needs_delay_slot" "yes")
7186 (set_attr "type" "jump_ind")])
7188 ;; Call subroutine returning any type.
7189 ;; ??? This probably doesn't work.
7190 (define_expand "untyped_call"
7191 [(parallel [(call (match_operand 0 "" "")
7193 (match_operand 1 "" "")
7194 (match_operand 2 "" "")])]
7195 "TARGET_SH2E || TARGET_SH2A"
7197 /* RA does not know that the call sets the function value registers.
7198 We avoid problems by claiming that those registers are clobbered
7200 for (int i = 0; i < XVECLEN (operands[2], 0); i++)
7201 emit_clobber (SET_SRC (XVECEXP (operands[2], 0, i)));
7203 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
7205 for (int i = 0; i < XVECLEN (operands[2], 0); i++)
7207 rtx set = XVECEXP (operands[2], 0, i);
7208 emit_move_insn (SET_DEST (set), SET_SRC (set));
7211 /* The optimizer does not know that the call sets the function value
7212 registers we stored in the result block. We avoid problems by
7213 claiming that all hard registers are used and clobbered at this
7215 emit_insn (gen_blockage ());
7220 ;; ------------------------------------------------------------------------
7222 ;; ------------------------------------------------------------------------
7225 [(set (reg:SI T_REG)
7226 (eq:SI (match_operand:SI 1 "arith_reg_dest" "0") (const_int 1)))
7227 (set (match_operand:SI 0 "arith_reg_dest" "=r")
7228 (plus:SI (match_dup 1) (const_int -1)))]
7231 [(set_attr "type" "arith")])
7238 ;; Load address of a label. This is only generated by the casesi expand,
7239 ;; and by machine_dependent_reorg (fixing up fp moves).
7240 ;; This must use unspec, because this only works for labels that are
7243 [(set (reg:SI R0_REG)
7244 (unspec:SI [(label_ref (match_operand 0 "" ""))] UNSPEC_MOVA))]
7247 [(set_attr "in_delay_slot" "no")
7248 (set_attr "type" "arith")])
7250 ;; machine_dependent_reorg will make this a `mova'.
7251 (define_insn "mova_const"
7252 [(set (reg:SI R0_REG)
7253 (unspec:SI [(match_operand 0 "immediate_operand" "i")] UNSPEC_MOVA))]
7256 [(set_attr "in_delay_slot" "no")
7257 (set_attr "type" "arith")])
7259 ;; Loads of the GOTPC relocation values must not be optimized away
7260 ;; by e.g. any kind of CSE and must stay as they are. Although there
7261 ;; are other various ways to ensure this, we use an artificial counter
7262 ;; operand to generate unique symbols.
7263 (define_expand "GOTaddr2picreg"
7264 [(set (reg:SI R0_REG)
7265 (unspec:SI [(const:SI (unspec:SI [(match_dup 2)
7266 (match_operand:SI 0 "" "")]
7267 UNSPEC_PIC))] UNSPEC_MOVA))
7269 (const:SI (unspec:SI [(match_dup 2) (match_dup 0)] UNSPEC_PIC)))
7270 (set (match_dup 1) (plus:SI (match_dup 1) (reg:SI R0_REG)))]
7273 if (TARGET_VXWORKS_RTP)
7275 rtx gott_base = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE);
7276 rtx gott_index = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
7277 emit_insn (gen_vxworks_picreg (gott_base, gott_index));
7283 rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
7284 emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
7288 operands[1] = gen_rtx_REG (Pmode, PIC_REG);
7289 operands[2] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
7292 ;; A helper for GOTaddr2picreg to finish up the initialization of the
7294 (define_expand "vxworks_picreg"
7295 [(set (reg:SI PIC_REG)
7296 (const:SI (unspec:SI [(match_operand:SI 0 "" "")] UNSPEC_PIC)))
7297 (set (reg:SI R0_REG)
7298 (const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PIC)))
7299 (set (reg:SI PIC_REG)
7300 (mem:SI (reg:SI PIC_REG)))
7301 (set (reg:SI PIC_REG)
7302 (mem:SI (plus:SI (reg:SI PIC_REG)
7304 "TARGET_VXWORKS_RTP")
7306 (define_expand "builtin_setjmp_receiver"
7307 [(match_operand 0 "" "")]
7310 emit_insn (gen_GOTaddr2picreg (const0_rtx));
7314 (define_expand "call_site"
7315 [(unspec [(match_dup 0)] UNSPEC_CALLER)]
7318 static HOST_WIDE_INT i = 0;
7319 operands[0] = GEN_INT (i);
7323 ;; op0 = op1 + r12 but hide it before reload completed. See the comment
7324 ;; in symGOT_load expand.
7325 (define_insn_and_split "chk_guard_add"
7326 [(set (match_operand:SI 0 "register_operand" "=&r")
7327 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
7332 "TARGET_SH1 && reload_completed"
7333 [(set (match_dup 0) (reg:SI PIC_REG))
7334 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
7336 [(set_attr "type" "arith")])
7338 (define_expand "sym_label2reg"
7339 [(set (match_operand:SI 0 "" "")
7340 (const:SI (unspec:SI [(match_operand:SI 1 "" "")
7341 (const (plus:SI (match_operand:SI 2 "" "")
7346 (define_expand "symPCREL_label2reg"
7347 [(set (match_operand:SI 0 "" "")
7350 [(const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PCREL))
7351 (const:SI (plus:SI (match_operand:SI 2 "" "")
7352 (const_int 2)))] UNSPEC_PCREL_SYMOFF)))]
7356 (define_expand "symGOT_load"
7357 [(set (match_dup 2) (match_operand 1 "" ""))
7358 (set (match_dup 3) (plus (match_dup 2) (reg PIC_REG)))
7359 (set (match_operand 0 "" "") (mem (match_dup 3)))]
7363 bool stack_chk_guard_p = false;
7365 rtx picreg = TARGET_FDPIC ? sh_get_fdpic_reg_initial_val ()
7366 : gen_rtx_REG (Pmode, PIC_REG);
7368 operands[2] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
7369 operands[3] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
7372 && flag_stack_protect
7373 && GET_CODE (operands[1]) == CONST
7374 && GET_CODE (XEXP (operands[1], 0)) == UNSPEC
7375 && GET_CODE (XVECEXP (XEXP (operands[1], 0), 0, 0)) == SYMBOL_REF
7376 && strcmp (XSTR (XVECEXP (XEXP (operands[1], 0), 0, 0), 0),
7377 "__stack_chk_guard") == 0)
7378 stack_chk_guard_p = true;
7380 emit_move_insn (operands[2], operands[1]);
7382 /* When stack protector inserts codes after the result is set to
7383 R0, @(rX, r12) will cause a spill failure for R0. Use a unspec
7384 insn to avoid combining (set A (plus rX r12)) and (set op0 (mem A))
7385 when rX is a GOT address for the guard symbol. Ugly but doesn't
7386 matter because this is a rare situation. */
7387 if (stack_chk_guard_p)
7388 emit_insn (gen_chk_guard_add (operands[3], operands[2]));
7390 emit_move_insn (operands[3], gen_rtx_PLUS (Pmode, operands[2], picreg));
7392 /* N.B. This is not constant for a GOTPLT relocation. */
7393 mem = gen_rtx_MEM (Pmode, operands[3]);
7394 MEM_NOTRAP_P (mem) = 1;
7395 /* ??? Should we have a special alias set for the GOT? */
7396 emit_move_insn (operands[0], mem);
7401 (define_expand "sym2GOT"
7402 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOT))]
7406 (define_expand "symGOT2reg"
7407 [(match_operand 0 "" "") (match_operand 1 "" "")]
7412 gotsym = gen_sym2GOT (operands[1]);
7413 PUT_MODE (gotsym, Pmode);
7414 insn = emit_insn (gen_symGOT_load (operands[0], gotsym));
7416 MEM_READONLY_P (SET_SRC (PATTERN (insn))) = 1;
7421 (define_expand "sym2GOTFUNCDESC"
7422 [(const (unspec [(match_operand 0)] UNSPEC_GOTFUNCDESC))]
7425 (define_expand "symGOTFUNCDESC2reg"
7426 [(match_operand 0) (match_operand 1)]
7429 rtx gotsym = gen_sym2GOTFUNCDESC (operands[1]);
7430 PUT_MODE (gotsym, Pmode);
7431 rtx insn = emit_insn (gen_symGOT_load (operands[0], gotsym));
7433 MEM_READONLY_P (SET_SRC (PATTERN (insn))) = 1;
7438 (define_expand "symGOTPLT2reg"
7439 [(match_operand 0 "" "") (match_operand 1 "" "")]
7442 rtx pltsym = gen_rtx_CONST (Pmode,
7443 gen_rtx_UNSPEC (Pmode,
7444 gen_rtvec (1, operands[1]),
7446 emit_insn (gen_symGOT_load (operands[0], pltsym));
7450 (define_expand "sym2GOTOFF"
7451 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTOFF))]
7455 (define_expand "symGOTOFF2reg"
7456 [(match_operand 0 "" "") (match_operand 1 "" "")]
7460 rtx t = (!can_create_pseudo_p ()
7462 : gen_reg_rtx (GET_MODE (operands[0])));
7464 rtx picreg = TARGET_FDPIC ? sh_get_fdpic_reg_initial_val ()
7465 : gen_rtx_REG (Pmode, PIC_REG);
7467 gotoffsym = gen_sym2GOTOFF (operands[1]);
7468 PUT_MODE (gotoffsym, Pmode);
7469 emit_move_insn (t, gotoffsym);
7470 rtx_insn *insn = emit_move_insn (operands[0], gen_rtx_PLUS (Pmode, t, picreg));
7472 set_unique_reg_note (insn, REG_EQUAL, operands[1]);
7477 (define_expand "sym2GOTOFFFUNCDESC"
7478 [(const (unspec [(match_operand 0)] UNSPEC_GOTOFFFUNCDESC))]
7481 (define_expand "symGOTOFFFUNCDESC2reg"
7482 [(match_operand 0) (match_operand 1)]
7485 rtx picreg = sh_get_fdpic_reg_initial_val ();
7486 rtx t = !can_create_pseudo_p ()
7488 : gen_reg_rtx (GET_MODE (operands[0]));
7490 rtx gotoffsym = gen_sym2GOTOFFFUNCDESC (operands[1]);
7491 PUT_MODE (gotoffsym, Pmode);
7492 emit_move_insn (t, gotoffsym);
7493 emit_move_insn (operands[0], gen_rtx_PLUS (Pmode, t, picreg));
7497 (define_expand "symPLT_label2reg"
7498 [(set (match_operand:SI 0 "" "")
7501 [(const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PLT))
7502 (const:SI (plus:SI (match_operand:SI 2 "" "")
7503 (const_int 2)))] UNSPEC_PCREL_SYMOFF)))
7504 ;; Even though the PIC register is not really used by the call
7505 ;; sequence in which this is expanded, the PLT code assumes the PIC
7506 ;; register is set, so we must not skip its initialization. Since
7507 ;; we only use this expand as part of calling sequences, and never
7508 ;; to take the address of a function, this is the best point to
7509 ;; insert the (use). Using the PLT to take the address of a
7510 ;; function would be wrong, not only because the PLT entry could
7511 ;; then be called from a function that doesn't initialize the PIC
7512 ;; register to the proper GOT, but also because pointers to the
7513 ;; same function might not compare equal, should they be set by
7514 ;; different shared libraries.
7515 (use (reg:SI PIC_REG))]
7519 (define_expand "sym2PIC"
7520 [(const (unspec [(match_operand:SI 0 "" "")] UNSPEC_PIC))]
7524 ;; -------------------------------------------------------------------------
7525 ;; TLS code generation.
7527 ;; FIXME: The multi-insn asm blocks should be converted to use
7528 ;; define_insn_and_split.
7529 ;; See the thread [PATCH/RFA] SH TLS support on gcc-patches
7530 ;; <http://gcc.gnu.org/ml/gcc-patches/2003-02/msg01898.html>
7533 (define_insn "tls_global_dynamic"
7534 [(set (match_operand:SI 0 "register_operand" "=&z")
7535 (call:SI (mem:SI (unspec:SI [(match_operand:SI 1 "" "")]
7538 (use (reg:SI FPSCR_MODES_REG))
7539 (use (reg:SI PIC_REG))
7540 (clobber (reg:SI PR_REG))
7541 (clobber (scratch:SI))]
7544 return "mov.l 1f,r4" "\n"
7553 "1: .long %a1@TLSGD" "\n"
7554 "2: .long __tls_get_addr@PLT" "\n"
7557 [(set_attr "type" "tls_load")
7558 (set_attr "length" "26")])
7560 (define_insn "tls_local_dynamic"
7561 [(set (match_operand:SI 0 "register_operand" "=&z")
7562 (call:SI (mem:SI (unspec:SI [(match_operand:SI 1 "" "")]
7565 (use (reg:SI FPSCR_MODES_REG))
7566 (use (reg:SI PIC_REG))
7567 (clobber (reg:SI PR_REG))
7568 (clobber (scratch:SI))]
7571 return "mov.l 1f,r4" "\n"
7580 "1: .long %a1@TLSLDM" "\n"
7581 "2: .long __tls_get_addr@PLT" "\n"
7584 [(set_attr "type" "tls_load")
7585 (set_attr "length" "26")])
7587 (define_expand "sym2DTPOFF"
7588 [(const (unspec [(match_operand 0 "" "")] UNSPEC_DTPOFF))]
7592 (define_expand "symDTPOFF2reg"
7593 [(match_operand 0 "" "") (match_operand 1 "" "") (match_operand 2 "" "")]
7597 rtx t = (!can_create_pseudo_p ()
7599 : gen_reg_rtx (GET_MODE (operands[0])));
7601 dtpoffsym = gen_sym2DTPOFF (operands[1]);
7602 PUT_MODE (dtpoffsym, Pmode);
7603 emit_move_insn (t, dtpoffsym);
7604 emit_move_insn (operands[0], gen_rtx_PLUS (Pmode, t, operands[2]));
7608 (define_expand "sym2GOTTPOFF"
7609 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTTPOFF))]
7613 (define_insn "tls_initial_exec"
7614 [(set (match_operand:SI 0 "register_operand" "=&r")
7615 (unspec:SI [(match_operand:SI 1 "" "")]
7617 (use (reg:SI GBR_REG))
7618 (use (reg:SI PIC_REG))
7619 (clobber (reg:SI R0_REG))]
7622 return "mov.l 1f,r0" "\n"
7624 " mov.l @(r0,r12),r0" "\n"
7631 [(set_attr "type" "tls_load")
7632 (set_attr "length" "16")])
7634 (define_expand "sym2TPOFF"
7635 [(const (unspec [(match_operand 0 "" "")] UNSPEC_TPOFF))]
7639 (define_expand "symTPOFF2reg"
7640 [(match_operand 0 "" "") (match_operand 1 "" "")]
7645 tpoffsym = gen_sym2TPOFF (operands[1]);
7646 PUT_MODE (tpoffsym, Pmode);
7647 emit_move_insn (operands[0], tpoffsym);
7651 ;;------------------------------------------------------------------------------
7652 ;; Thread pointer getter and setter.
7654 ;; On SH the thread pointer is kept in the GBR.
7655 ;; These patterns are usually expanded from the respective built-in functions.
7656 (define_expand "get_thread_pointersi"
7657 [(set (match_operand:SI 0 "arith_reg_dest") (reg:SI GBR_REG))]
7660 ;; The store_gbr insn can also be used on !TARGET_SH1 for doing TLS accesses.
7661 (define_insn "store_gbr"
7662 [(set (match_operand:SI 0 "arith_reg_dest" "=r") (reg:SI GBR_REG))]
7665 [(set_attr "type" "tls_load")])
7667 (define_expand "set_thread_pointersi"
7668 [(set (reg:SI GBR_REG)
7669 (unspec_volatile:SI [(match_operand:SI 0 "arith_reg_operand")]
7673 (define_insn "load_gbr"
7674 [(set (reg:SI GBR_REG)
7675 (unspec_volatile:SI [(match_operand:SI 0 "arith_reg_operand" "r")]
7679 [(set_attr "type" "move")])
7681 ;;------------------------------------------------------------------------------
7682 ;; Thread pointer relative memory loads and stores.
7684 ;; On SH there are GBR displacement address modes which can be utilized to
7685 ;; access memory behind the thread pointer.
7686 ;; Since we do not allow using GBR for general purpose memory accesses, these
7687 ;; GBR addressing modes are formed by the combine pass.
7688 ;; This could be done with fewer patterns than below by using a mem predicate
7689 ;; for the GBR mem, but then reload would try to reload addresses with a
7690 ;; zero displacement for some strange reason.
7692 (define_insn "*mov<mode>_gbr_load"
7693 [(set (match_operand:QIHISI 0 "arith_reg_dest" "=z")
7694 (mem:QIHISI (plus:SI (reg:SI GBR_REG)
7695 (match_operand:QIHISI 1 "gbr_displacement"))))]
7697 "mov.<bwl> @(%O1,gbr),%0"
7698 [(set_attr "type" "load")])
7700 (define_insn "*mov<mode>_gbr_load"
7701 [(set (match_operand:QIHISI 0 "arith_reg_dest" "=z")
7702 (mem:QIHISI (reg:SI GBR_REG)))]
7704 "mov.<bwl> @(0,gbr),%0"
7705 [(set_attr "type" "load")])
7707 (define_insn "*mov<mode>_gbr_load"
7708 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
7710 (mem:QIHI (plus:SI (reg:SI GBR_REG)
7711 (match_operand:QIHI 1 "gbr_displacement")))))]
7713 "mov.<bw> @(%O1,gbr),%0"
7714 [(set_attr "type" "load")])
7716 (define_insn "*mov<mode>_gbr_load"
7717 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
7718 (sign_extend:SI (mem:QIHI (reg:SI GBR_REG))))]
7720 "mov.<bw> @(0,gbr),%0"
7721 [(set_attr "type" "load")])
7723 (define_insn "*mov<mode>_gbr_store"
7724 [(set (mem:QIHISI (plus:SI (reg:SI GBR_REG)
7725 (match_operand:QIHISI 0 "gbr_displacement")))
7726 (match_operand:QIHISI 1 "register_operand" "z"))]
7728 "mov.<bwl> %1,@(%O0,gbr)"
7729 [(set_attr "type" "store")])
7731 (define_insn "*mov<mode>_gbr_store"
7732 [(set (mem:QIHISI (reg:SI GBR_REG))
7733 (match_operand:QIHISI 0 "register_operand" "z"))]
7735 "mov.<bwl> %0,@(0,gbr)"
7736 [(set_attr "type" "store")])
7738 ;; DImode memory accesses have to be split in two SImode accesses.
7739 ;; Split them before reload, so that it gets a better chance to figure out
7740 ;; how to deal with the R0 restriction for the individual SImode accesses.
7741 ;; Do not match this insn during or after reload because it can't be split
7743 (define_insn_and_split "*movdi_gbr_load"
7744 [(set (match_operand:DI 0 "arith_reg_dest")
7745 (match_operand:DI 1 "gbr_address_mem"))]
7746 "TARGET_SH1 && can_create_pseudo_p ()"
7749 [(set (match_dup 3) (match_dup 5))
7750 (set (match_dup 4) (match_dup 6))]
7752 /* Swap low/high part load order on little endian, so that the result reg
7753 of the second load can be used better. */
7754 int off = TARGET_LITTLE_ENDIAN ? 1 : 0;
7755 operands[3 + off] = gen_lowpart (SImode, operands[0]);
7756 operands[5 + off] = gen_lowpart (SImode, operands[1]);
7757 operands[4 - off] = gen_highpart (SImode, operands[0]);
7758 operands[6 - off] = gen_highpart (SImode, operands[1]);
7761 (define_insn_and_split "*movdi_gbr_store"
7762 [(set (match_operand:DI 0 "gbr_address_mem")
7763 (match_operand:DI 1 "register_operand"))]
7764 "TARGET_SH1 && can_create_pseudo_p ()"
7767 [(set (match_dup 3) (match_dup 5))
7768 (set (match_dup 4) (match_dup 6))]
7770 /* Swap low/high part store order on big endian, so that stores of function
7771 call results can save a reg copy. */
7772 int off = TARGET_LITTLE_ENDIAN ? 0 : 1;
7773 operands[3 + off] = gen_lowpart (SImode, operands[0]);
7774 operands[5 + off] = gen_lowpart (SImode, operands[1]);
7775 operands[4 - off] = gen_highpart (SImode, operands[0]);
7776 operands[6 - off] = gen_highpart (SImode, operands[1]);
7779 ;; Sometimes memory accesses do not get combined with the store_gbr insn,
7780 ;; in particular when the displacements are in the range of the regular move
7781 ;; insns. Thus, in the first split pass after the combine pass we search
7782 ;; for missed opportunities and try to fix them up ourselves.
7783 ;; If an equivalent GBR address can be determined the load / store is split
7784 ;; into one of the GBR load / store patterns.
7785 ;; All of that must happen before reload (GBR address modes use R0 as the
7786 ;; other operand) and there's no point of doing it if the GBR is not
7787 ;; referenced in a function at all.
7789 [(set (match_operand:QIHISIDI 0 "register_operand")
7790 (match_operand:QIHISIDI 1 "memory_operand"))]
7791 "TARGET_SH1 && !reload_in_progress && !reload_completed
7792 && df_regs_ever_live_p (GBR_REG)"
7793 [(set (match_dup 0) (match_dup 1))]
7795 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]);
7796 if (gbr_mem != NULL_RTX)
7797 operands[1] = replace_equiv_address (operands[1], gbr_mem);
7803 [(set (match_operand:SI 0 "register_operand")
7804 (sign_extend:SI (match_operand:QIHI 1 "memory_operand")))]
7805 "TARGET_SH1 && !reload_in_progress && !reload_completed
7806 && df_regs_ever_live_p (GBR_REG)"
7807 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))]
7809 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]);
7810 if (gbr_mem != NULL_RTX)
7811 operands[1] = replace_equiv_address (operands[1], gbr_mem);
7816 ;; On SH2A we've got movu.b and movu.w for doing zero-extending mem loads.
7817 ;; Split those so that a GBR load can be used.
7819 [(set (match_operand:SI 0 "register_operand")
7820 (zero_extend:SI (match_operand:QIHI 1 "memory_operand")))]
7821 "TARGET_SH2A && !reload_in_progress && !reload_completed
7822 && df_regs_ever_live_p (GBR_REG)"
7823 [(set (match_dup 2) (match_dup 1))
7824 (set (match_dup 0) (zero_extend:SI (match_dup 2)))]
7826 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]);
7827 if (gbr_mem != NULL_RTX)
7829 operands[2] = gen_reg_rtx (GET_MODE (operands[1]));
7830 operands[1] = replace_equiv_address (operands[1], gbr_mem);
7837 [(set (match_operand:QIHISIDI 0 "memory_operand")
7838 (match_operand:QIHISIDI 1 "register_operand"))]
7839 "TARGET_SH1 && !reload_in_progress && !reload_completed
7840 && df_regs_ever_live_p (GBR_REG)"
7841 [(set (match_dup 0) (match_dup 1))]
7843 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[0]);
7844 if (gbr_mem != NULL_RTX)
7845 operands[0] = replace_equiv_address (operands[0], gbr_mem);
7850 ;;------------------------------------------------------------------------------
7851 ;; case instruction for switch statements.
7853 ;; operand 0 is index
7854 ;; operand 1 is the minimum bound
7855 ;; operand 2 is the maximum bound - minimum bound + 1
7856 ;; operand 3 is CODE_LABEL for the table;
7857 ;; operand 4 is the CODE_LABEL to go to if index out of range.
7858 (define_expand "casesi"
7859 [(match_operand:SI 0 "arith_reg_operand" "")
7860 (match_operand:SI 1 "arith_reg_operand" "")
7861 (match_operand:SI 2 "arith_reg_operand" "")
7862 (match_operand 3 "" "") (match_operand 4 "" "")]
7865 rtx reg = gen_reg_rtx (SImode);
7866 rtx reg2 = gen_reg_rtx (SImode);
7868 operands[1] = copy_to_mode_reg (SImode, operands[1]);
7869 operands[2] = copy_to_mode_reg (SImode, operands[2]);
7870 /* If optimizing, casesi_worker depends on the mode of the instruction
7871 before label it 'uses' - operands[3]. */
7872 emit_insn (gen_casesi_0 (operands[0], operands[1], operands[2], operands[4],
7874 emit_insn (gen_casesi_worker_0 (reg2, reg, operands[3]));
7876 emit_jump_insn (gen_casesi_jump_2 (reg2, gen_label_rtx (), operands[3]));
7878 emit_jump_insn (gen_casesi_jump_1 (reg2, operands[3]));
7879 /* For SH2 and newer, the ADDR_DIFF_VEC is not actually relative to
7880 operands[3], but to lab. We will fix this up in
7881 machine_dependent_reorg. */
7886 (define_expand "casesi_0"
7887 [(set (match_operand:SI 4 "" "") (match_operand:SI 0 "arith_reg_operand" ""))
7888 (set (match_dup 4) (minus:SI (match_dup 4)
7889 (match_operand:SI 1 "arith_operand" "")))
7891 (gtu:SI (match_dup 4)
7892 (match_operand:SI 2 "arith_reg_operand" "")))
7894 (if_then_else (ne (reg:SI T_REG)
7896 (label_ref (match_operand 3 "" ""))
7901 ;; ??? reload might clobber r0 if we use it explicitly in the RTL before
7902 ;; reload; using a R0_REGS pseudo reg is likely to give poor code.
7903 ;; So we keep the use of r0 hidden in a R0_REGS clobber until after reload.
7905 ;; The use on the T_REG in the casesi_worker* patterns links the bounds
7906 ;; checking insns and the table memory access. See also PR 69713.
7907 (define_insn "casesi_worker_0"
7908 [(set (match_operand:SI 0 "register_operand" "=r,r")
7909 (unspec:SI [(match_operand:SI 1 "register_operand" "0,r")
7910 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
7911 (clobber (match_scratch:SI 3 "=X,1"))
7912 (clobber (match_scratch:SI 4 "=&z,z"))
7913 (use (reg:SI T_REG))]
7918 [(set (match_operand:SI 0 "register_operand" "")
7919 (unspec:SI [(match_operand:SI 1 "register_operand" "")
7920 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
7921 (clobber (match_scratch:SI 3 ""))
7922 (clobber (match_scratch:SI 4))
7923 (use (reg:SI T_REG))]
7924 "TARGET_SH1 && ! TARGET_SH2 && reload_completed"
7925 [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA))
7926 (parallel [(set (match_dup 0)
7927 (unspec:SI [(reg:SI R0_REG) (match_dup 1)
7928 (label_ref (match_dup 2))] UNSPEC_CASESI))
7929 (clobber (match_dup 3))])
7930 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
7932 if (GET_CODE (operands[2]) == CODE_LABEL)
7933 LABEL_NUSES (operands[2])++;
7937 [(set (match_operand:SI 0 "register_operand" "")
7938 (unspec:SI [(match_operand:SI 1 "register_operand" "")
7939 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
7940 (clobber (match_scratch:SI 3 ""))
7941 (clobber (match_scratch:SI 4))
7942 (use (reg:SI T_REG))]
7943 "TARGET_SH2 && reload_completed"
7944 [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA))
7945 (parallel [(set (match_dup 0)
7946 (unspec:SI [(reg:SI R0_REG) (match_dup 1)
7947 (label_ref (match_dup 2))] UNSPEC_CASESI))
7948 (clobber (match_dup 3))])]
7950 if (GET_CODE (operands[2]) == CODE_LABEL)
7951 LABEL_NUSES (operands[2])++;
7954 ;; This may be replaced with casesi_worker_2 in sh_reorg for PIC.
7955 ;; The insn length is set to 8 for that case.
7956 (define_insn "casesi_worker_1"
7957 [(set (match_operand:SI 0 "register_operand" "=r,r")
7958 (unspec:SI [(reg:SI R0_REG)
7959 (match_operand:SI 1 "register_operand" "0,r")
7960 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
7961 (clobber (match_scratch:SI 3 "=X,1"))]
7964 rtx diff_vec = PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[2])));
7966 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
7968 switch (GET_MODE (diff_vec))
7971 return "shll2 %1" "\n"
7972 " mov.l @(r0,%1),%0";
7974 return "add %1,%1" "\n"
7975 " mov.w @(r0,%1),%0";
7977 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
7978 return "mov.b @(r0,%1),%0" "\n"
7981 return "mov.b @(r0,%1),%0";
7987 [(set_attr_alternative "length"
7988 [(if_then_else (match_test "flag_pic") (const_int 8) (const_int 4))
7989 (if_then_else (match_test "flag_pic") (const_int 8) (const_int 4))])])
7991 (define_insn "casesi_worker_2"
7992 [(set (match_operand:SI 0 "register_operand" "=r,r")
7993 (unspec:SI [(reg:SI R0_REG)
7994 (match_operand:SI 1 "register_operand" "0,r")
7995 (label_ref (match_operand 2 "" ""))
7996 (label_ref (match_operand 3 "" ""))] UNSPEC_CASESI))
7997 (clobber (match_operand:SI 4 "" "=X,1"))]
7998 "TARGET_SH2 && reload_completed && flag_pic"
8000 rtx diff_vec = PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[2])));
8001 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
8003 switch (GET_MODE (diff_vec))
8006 return "shll2 %1" "\n"
8009 " mov.l @(r0,%1),%0";
8011 return "add %1,%1" "\n"
8014 " mov.w @(r0,%1),%0";
8016 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
8017 return "add r0,%1" "\n"
8019 " mov.b @(r0,%1),%0" "\n"
8022 return "add r0,%1" "\n"
8024 " mov.b @(r0,%1),%0";
8029 [(set_attr "length" "8")])
8031 (define_expand "simple_return"
8033 "sh_can_use_simple_return_p ()")
8035 (define_expand "return"
8037 "reload_completed && epilogue_completed")
8039 (define_insn "*<code>_i"
8043 && ! sh_cfun_trap_exit_p ()"
8045 if (TARGET_SH2A && (dbr_sequence_length () == 0)
8046 && !current_function_interrupt)
8051 [(set_attr "type" "return")
8052 (set_attr "needs_delay_slot" "yes")])
8054 ;; trapa has no delay slot.
8055 (define_insn "*return_trapa"
8057 "TARGET_SH1 && reload_completed"
8059 [(set_attr "type" "return")])
8061 (define_expand "prologue"
8065 sh_expand_prologue ();
8069 (define_expand "epilogue"
8073 sh_expand_epilogue (false);
8076 (define_expand "eh_return"
8077 [(use (match_operand 0 "register_operand" ""))]
8080 emit_insn (gen_eh_set_ra_si (operands[0]));
8084 ;; Clobber the return address on the stack. We can't expand this
8085 ;; until we know where it will be put in the stack frame.
8087 (define_insn "eh_set_ra_si"
8088 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
8090 (clobber (match_scratch:SI 1 "=&r"))]
8095 [(unspec_volatile [(match_operand 0 "register_operand" "")]
8097 (clobber (match_scratch 1 ""))]
8101 sh_set_return_address (operands[0], operands[1]);
8105 (define_insn "blockage"
8106 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
8109 [(set_attr "length" "0")])
8111 ;; Define movml instructions for SH2A target. Currently they are
8112 ;; used to push and pop all banked registers only.
8114 (define_insn "movml_push_banked"
8115 [(set (match_operand:SI 0 "register_operand" "=r")
8116 (plus (match_dup 0) (const_int -32)))
8117 (set (mem:SI (plus:SI (match_dup 0) (const_int 28))) (reg:SI R7_REG))
8118 (set (mem:SI (plus:SI (match_dup 0) (const_int 24))) (reg:SI R6_REG))
8119 (set (mem:SI (plus:SI (match_dup 0) (const_int 20))) (reg:SI R5_REG))
8120 (set (mem:SI (plus:SI (match_dup 0) (const_int 16))) (reg:SI R4_REG))
8121 (set (mem:SI (plus:SI (match_dup 0) (const_int 12))) (reg:SI R3_REG))
8122 (set (mem:SI (plus:SI (match_dup 0) (const_int 8))) (reg:SI R2_REG))
8123 (set (mem:SI (plus:SI (match_dup 0) (const_int 4))) (reg:SI R1_REG))
8124 (set (mem:SI (plus:SI (match_dup 0) (const_int 0))) (reg:SI R0_REG))]
8125 "TARGET_SH2A && REGNO (operands[0]) == 15"
8127 [(set_attr "in_delay_slot" "no")])
8129 (define_insn "movml_pop_banked"
8130 [(set (match_operand:SI 0 "register_operand" "=r")
8131 (plus (match_dup 0) (const_int 32)))
8132 (set (reg:SI R0_REG) (mem:SI (plus:SI (match_dup 0) (const_int -32))))
8133 (set (reg:SI R1_REG) (mem:SI (plus:SI (match_dup 0) (const_int -28))))
8134 (set (reg:SI R2_REG) (mem:SI (plus:SI (match_dup 0) (const_int -24))))
8135 (set (reg:SI R3_REG) (mem:SI (plus:SI (match_dup 0) (const_int -20))))
8136 (set (reg:SI R4_REG) (mem:SI (plus:SI (match_dup 0) (const_int -16))))
8137 (set (reg:SI R5_REG) (mem:SI (plus:SI (match_dup 0) (const_int -12))))
8138 (set (reg:SI R6_REG) (mem:SI (plus:SI (match_dup 0) (const_int -8))))
8139 (set (reg:SI R7_REG) (mem:SI (plus:SI (match_dup 0) (const_int -4))))]
8140 "TARGET_SH2A && REGNO (operands[0]) == 15"
8142 [(set_attr "in_delay_slot" "no")])
8144 ;; ------------------------------------------------------------------------
8146 ;; ------------------------------------------------------------------------
8149 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8150 (match_operand:SI 1 "t_reg_operand"))]
8153 [(set_attr "type" "arith")])
8155 (define_insn "movrt"
8156 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8157 (xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))]
8160 [(set_attr "type" "arith")])
8162 (define_expand "cstoresi4"
8163 [(set (match_operand:SI 0 "register_operand")
8164 (match_operator:SI 1 "comparison_operator"
8165 [(match_operand:SI 2 "cmpsi_operand")
8166 (match_operand:SI 3 "arith_operand")]))]
8169 if (sh_expand_t_scc (operands))
8172 if (! currently_expanding_to_rtl)
8175 sh_emit_compare_and_set (operands, SImode);
8179 (define_expand "cstoredi4"
8180 [(set (match_operand:SI 0 "register_operand")
8181 (match_operator:SI 1 "comparison_operator"
8182 [(match_operand:DI 2 "arith_operand")
8183 (match_operand:DI 3 "arith_operand")]))]
8186 if (sh_expand_t_scc (operands))
8189 if (! currently_expanding_to_rtl)
8192 sh_emit_compare_and_set (operands, DImode);
8196 ;; Move the complement of the T reg to a reg.
8197 ;; On SH2A the movrt insn can be used.
8198 ;; On anything else than SH2A this has to be done with multiple instructions.
8199 ;; One obvious way would be:
8204 ;; However, this puts pressure on r0 in most cases and thus the following is
8210 ;; If the constant -1 can be CSE-ed or lifted out of a loop it effectively
8211 ;; becomes a one instruction operation. Moreover, care must be taken that
8212 ;; the insn can still be combined with inverted compare and branch code
8213 ;; around it. On the other hand, if a function returns the complement of
8214 ;; a previous comparison result in the T bit, the xor #1,r0 approach might
8215 ;; lead to better code.
8216 (define_expand "movnegt"
8217 [(set (match_operand:SI 0 "arith_reg_dest" "")
8218 (xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))]
8222 emit_insn (gen_movrt (operands[0], operands[1]));
8225 rtx val = force_reg (SImode, gen_int_mode (-1, SImode));
8226 emit_insn (gen_movrt_negc (operands[0], operands[1], val));
8231 (define_insn_and_split "movrt_negc"
8232 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8233 (xor:SI (match_operand:SI 1 "t_reg_operand") (const_int 1)))
8234 (set (reg:SI T_REG) (const_int 1))
8235 (use (match_operand:SI 2 "arith_reg_operand" "r"))]
8238 "&& !sh_in_recog_treg_set_expr ()"
8241 if (sh_split_movrt_negc_to_movt_xor (curr_insn, operands))
8246 [(set_attr "type" "arith")])
8248 ;; The -1 constant will not be CSE-ed for the *movrt_negc pattern, but the
8249 ;; pattern can be used by the combine pass. Using a scratch reg for the
8250 ;; -1 constant results in slightly better register allocations compared to
8251 ;; generating a pseudo reg before reload.
8252 (define_insn_and_split "*movrt_negc"
8253 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8254 (xor:SI (match_operand:SI 1 "t_reg_operand") (const_int 1)))
8255 (clobber (match_scratch:SI 2 "=r"))
8256 (clobber (reg:SI T_REG))]
8257 "TARGET_SH1 && ! TARGET_SH2A"
8259 "&& !sh_in_recog_treg_set_expr ()"
8262 if (sh_split_movrt_negc_to_movt_xor (curr_insn, operands))
8264 else if (reload_completed)
8266 emit_move_insn (operands[2], gen_int_mode (-1, SImode));
8267 emit_insn (gen_movrt_negc (operands[0], operands[1], operands[2]));
8274 ;; Store the negated T bit in a reg using r0 and xor. This one doesn't
8275 ;; clobber the T bit, which is useful when storing the T bit and the
8276 ;; negated T bit in parallel. On SH2A the movrt insn can be used for that.
8277 ;; Usually we don't want this insn to be matched, except for cases where the
8278 ;; T bit clobber is really not appreciated. Hence the extra use on T_REG.
8279 (define_insn_and_split "movrt_xor"
8280 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
8281 (xor:SI (match_operand:SI 1 "t_reg_operand") (const_int 1)))
8282 (use (reg:SI T_REG))]
8285 "&& reload_completed"
8286 [(set (match_dup 0) (reg:SI T_REG))
8287 (set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))])
8290 ;; 0x7fffffff + (1-T) = 0 - 0x80000000 - T
8292 ;; Notice that 0 - 0x80000000 = 0x80000000.
8294 ;; Single bit tests are usually done with zero_extract. On non-SH2A this
8295 ;; will use a tst-negc sequence. On SH2A it will use a bld-addc sequence.
8296 ;; The zeroth bit requires a special pattern, otherwise we get a shlr-addc.
8297 ;; This is a special case of the generic treg_set_expr pattern and thus has
8298 ;; to come first or it will never match.
8299 (define_insn_and_split "*mov_t_msb_neg"
8300 [(set (match_operand:SI 0 "arith_reg_dest")
8301 (plus:SI (and:SI (match_operand:SI 1 "arith_reg_operand")
8303 (const_int 2147483647)))
8304 (clobber (reg:SI T_REG))]
8307 "&& can_create_pseudo_p ()"
8308 [(parallel [(set (match_dup 0)
8309 (plus:SI (zero_extract:SI (match_dup 1)
8310 (const_int 1) (const_int 0))
8311 (const_int 2147483647)))
8312 (clobber (reg:SI T_REG))])])
8314 (define_insn_and_split "*mov_t_msb_neg"
8315 [(set (match_operand:SI 0 "arith_reg_dest")
8316 (plus:SI (match_operand 1 "treg_set_expr")
8317 (const_int 2147483647))) ;; 0x7fffffff
8318 (clobber (reg:SI T_REG))]
8321 "&& can_create_pseudo_p ()"
8324 if (negt_reg_operand (operands[1], VOIDmode))
8326 emit_insn (gen_negc (operands[0],
8327 force_reg (SImode, GEN_INT (-2147483648LL))));
8331 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
8332 if (ti.remove_trailing_nott ())
8333 emit_insn (gen_negc (operands[0],
8334 force_reg (SImode, GEN_INT (-2147483648LL))));
8336 emit_insn (gen_addc (operands[0],
8337 force_reg (SImode, const0_rtx),
8338 force_reg (SImode, GEN_INT (2147483647))));
8342 (define_insn_and_split "*mov_t_msb_neg"
8343 [(set (match_operand:SI 0 "arith_reg_dest")
8344 (if_then_else:SI (match_operand 1 "treg_set_expr")
8345 (match_operand 2 "const_int_operand")
8346 (match_operand 3 "const_int_operand")))
8347 (clobber (reg:SI T_REG))]
8348 "TARGET_SH1 && can_create_pseudo_p ()
8349 && ((INTVAL (operands[2]) == -2147483648LL
8350 && INTVAL (operands[3]) == 2147483647LL)
8351 || (INTVAL (operands[2]) == 2147483647LL
8352 && INTVAL (operands[3]) == -2147483648LL))"
8357 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
8359 if (INTVAL (operands[2]) == -2147483648LL)
8361 if (ti.remove_trailing_nott ())
8362 emit_insn (gen_negc (operands[0],
8363 force_reg (SImode, GEN_INT (-2147483648LL))));
8365 emit_insn (gen_addc (operands[0],
8366 force_reg (SImode, const0_rtx),
8367 force_reg (SImode, operands[3])));
8370 else if (INTVAL (operands[2]) == 2147483647LL)
8372 if (ti.remove_trailing_nott ())
8373 emit_insn (gen_addc (operands[0],
8374 force_reg (SImode, const0_rtx),
8375 force_reg (SImode, GEN_INT (2147483647LL))));
8377 emit_insn (gen_negc (operands[0],
8378 force_reg (SImode, GEN_INT (-2147483648LL))));
8385 ;; Store (negated) T bit as all zeros or ones in a reg.
8386 ;; subc Rn,Rn ! Rn = Rn - Rn - T; T = T
8387 ;; not Rn,Rn ! Rn = 0 - Rn
8388 (define_insn_and_split "mov_neg_si_t"
8389 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8390 (neg:SI (match_operand 1 "treg_set_expr")))]
8393 gcc_assert (t_reg_operand (operands[1], VOIDmode));
8394 return "subc %0,%0";
8396 "&& can_create_pseudo_p () && !t_reg_operand (operands[1], VOIDmode)"
8399 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
8400 emit_insn (gen_mov_neg_si_t (operands[0], get_t_reg_rtx ()));
8402 if (ti.remove_trailing_nott ())
8403 emit_insn (gen_one_cmplsi2 (operands[0], operands[0]));
8407 [(set_attr "type" "arith")])
8409 ;; Invert the T bit.
8410 ;; On SH2A we can use the nott insn. On anything else this must be done with
8411 ;; multiple insns like:
8414 ;; This requires an additional pseudo. The SH specific sh_treg_combine RTL
8415 ;; pass will look for this insn. Disallow using it if pseudos can't be
8417 ;; Don't split the nott inside the splitting of a treg_set_expr, or else
8418 ;; surrounding insns might not see and recombine it. Defer the splitting
8419 ;; of the nott until after the whole insn containing the treg_set_expr
8421 (define_insn_and_split "nott"
8422 [(set (reg:SI T_REG)
8423 (xor:SI (match_operand:SI 0 "t_reg_operand") (const_int 1)))]
8424 "TARGET_SH2A || (TARGET_SH1 && can_create_pseudo_p ())"
8426 gcc_assert (TARGET_SH2A);
8429 "!TARGET_SH2A && can_create_pseudo_p () && !sh_in_recog_treg_set_expr ()"
8430 [(set (match_dup 0) (reg:SI T_REG))
8431 (set (reg:SI T_REG) (eq:SI (match_dup 0) (const_int 0)))]
8433 operands[0] = gen_reg_rtx (SImode);
8436 ;; Store T bit as MSB in a reg.
8437 ;; T = 0: 0x00000000 -> reg
8438 ;; T = 1: 0x80000000 -> reg
8439 (define_insn_and_split "*movt_msb"
8440 [(set (match_operand:SI 0 "arith_reg_dest")
8441 (mult:SI (match_operand:SI 1 "t_reg_operand")
8442 (const_int -2147483648))) ;; 0xffffffff80000000
8443 (clobber (reg:SI T_REG))]
8447 [(set (match_dup 0) (ashift:SI (reg:SI T_REG) (const_int 31)))])
8449 ;; Store inverted T bit as MSB in a reg.
8450 ;; T = 0: 0x80000000 -> reg
8451 ;; T = 1: 0x00000000 -> reg
8452 ;; On SH2A we can get away without clobbering the T_REG using the movrt insn.
8453 ;; On non SH2A we resort to the following sequence:
8457 ;; The T bit value will be modified during the sequence, but the rotcr insn
8458 ;; will restore its original value.
8459 (define_insn_and_split "*negt_msb"
8460 [(set (match_operand:SI 0 "arith_reg_dest")
8461 (match_operand:SI 1 "negt_reg_shl31_operand"))]
8464 "&& can_create_pseudo_p ()"
8467 rtx tmp = gen_reg_rtx (SImode);
8471 emit_insn (gen_movrt (tmp, get_t_reg_rtx ()));
8472 emit_insn (gen_rotrsi3 (operands[0], tmp, const1_rtx));
8476 emit_move_insn (tmp, get_t_reg_rtx ());
8477 emit_insn (gen_cmpeqsi_t (tmp, const0_rtx));
8478 emit_insn (gen_rotcr (operands[0], tmp, get_t_reg_rtx ()));
8483 ;; The *cset_zero patterns convert optimizations such as
8484 ;; "if (test) x = 0;"
8486 ;; "x &= -(test == 0);"
8487 ;; back to conditional branch sequences if zero-displacement branches
8489 ;; FIXME: These patterns can be removed when conditional execution patterns
8490 ;; are implemented, since ifcvt will not perform these optimizations if
8491 ;; conditional execution is supported.
8492 (define_insn "*cset_zero"
8493 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8494 (and:SI (plus:SI (match_operand:SI 1 "t_reg_operand")
8496 (match_operand:SI 2 "arith_reg_operand" "0")))]
8497 "TARGET_SH1 && TARGET_ZDCBRANCH"
8503 [(set_attr "type" "arith") ;; poor approximation
8504 (set_attr "length" "4")])
8506 (define_insn "*cset_zero"
8507 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8508 (if_then_else:SI (match_operand:SI 1 "cbranch_treg_value")
8509 (match_operand:SI 2 "arith_reg_operand" "0")
8511 "TARGET_SH1 && TARGET_ZDCBRANCH"
8513 int tval = sh_eval_treg_value (operands[1]);
8518 else if (tval == false)
8525 [(set_attr "type" "arith") ;; poor approximation
8526 (set_attr "length" "4")])
8528 (define_insn_and_split "*cset_zero"
8529 [(set (match_operand:SI 0 "arith_reg_dest")
8530 (if_then_else:SI (match_operand 1 "treg_set_expr_not_const01")
8531 (match_dup 0) (const_int 0)))
8532 (clobber (reg:SI T_REG))]
8533 "TARGET_SH1 && TARGET_ZDCBRANCH && can_create_pseudo_p ()"
8537 (if_then_else:SI (match_dup 1) (match_dup 0) (const_int 0)))]
8539 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
8540 if (ti.remove_trailing_nott ())
8541 operands[1] = gen_rtx_EQ (SImode, get_t_reg_rtx (), const0_rtx);
8543 operands[1] = gen_rtx_EQ (SImode, get_t_reg_rtx (), const1_rtx);
8546 (define_expand "cstoresf4"
8547 [(set (match_operand:SI 0 "register_operand")
8548 (match_operator:SI 1 "ordered_comparison_operator"
8549 [(match_operand:SF 2 "arith_operand")
8550 (match_operand:SF 3 "arith_operand")]))]
8553 if (! currently_expanding_to_rtl)
8556 sh_emit_compare_and_set (operands, SFmode);
8560 (define_expand "cstoredf4"
8561 [(set (match_operand:SI 0 "register_operand")
8562 (match_operator:SI 1 "ordered_comparison_operator"
8563 [(match_operand:DF 2 "arith_operand")
8564 (match_operand:DF 3 "arith_operand")]))]
8567 if (! currently_expanding_to_rtl)
8570 sh_emit_compare_and_set (operands, DFmode);
8574 ;; Sometimes the T bit result of insns is needed in normal registers.
8575 ;; Instead of open coding all the pattern variations, use the treg_set_expr
8576 ;; predicate to match any T bit output insn and split it out after.
8577 ;; This pattern should be below all other related patterns so that it is
8578 ;; considered as a last resort option during matching. This allows
8579 ;; overriding it with special case patterns.
8580 (define_insn_and_split "any_treg_expr_to_reg"
8581 [(set (match_operand:SI 0 "arith_reg_dest")
8582 (match_operand 1 "treg_set_expr"))
8583 (clobber (reg:SI T_REG))]
8584 "TARGET_SH1 && can_create_pseudo_p ()"
8586 "&& !sh_in_recog_treg_set_expr ()"
8590 fprintf (dump_file, "splitting any_treg_expr_to_reg\n");
8592 if (t_reg_operand (operands[1], VOIDmode))
8595 fprintf (dump_file, "t_reg_operand: emitting movt\n");
8596 emit_insn (gen_movt (operands[0], get_t_reg_rtx ()));
8599 if (negt_reg_operand (operands[1], VOIDmode))
8602 fprintf (dump_file, "negt_reg_operand: emitting movrt\n");
8603 emit_insn (gen_movnegt (operands[0], get_t_reg_rtx ()));
8607 /* If the split out insns ended with a nott, emit a movrt sequence,
8608 otherwise a normal movt. */
8609 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
8611 if (ti.remove_trailing_nott ())
8613 /* Emit this same insn_and_split again. However, the next time it
8614 is split, it will emit the actual negc/movrt insn. This gives
8615 other surrounding insns the chance to see the trailing movrt. */
8618 "any_treg_expr_to_reg: replacing trailing nott with movrt\n");
8619 i = emit_insn (gen_any_treg_expr_to_reg (
8620 operands[0], gen_rtx_XOR (SImode, get_t_reg_rtx (),
8625 i = emit_insn (gen_movt (operands[0], get_t_reg_rtx ()));
8627 fprintf (dump_file, "any_treg_expr_to_reg: appending movt\n");
8630 add_reg_note (i, REG_UNUSED, get_t_reg_rtx ());
8634 ;; -------------------------------------------------------------------------
8635 ;; Instructions to cope with inline literal tables
8636 ;; -------------------------------------------------------------------------
8638 ;; 2 byte integer in line
8639 (define_insn "consttable_2"
8640 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
8641 (match_operand 1 "" "")]
8645 if (operands[1] != const0_rtx)
8646 assemble_integer (operands[0], 2, BITS_PER_UNIT * 2, 1);
8649 [(set_attr "length" "2")
8650 (set_attr "in_delay_slot" "no")])
8652 ;; 4 byte integer in line
8653 (define_insn "consttable_4"
8654 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
8655 (match_operand 1 "" "")]
8659 if (operands[1] != const0_rtx)
8661 assemble_integer (operands[0], 4, BITS_PER_UNIT * 4, 1);
8662 mark_symbol_refs_as_used (operands[0]);
8666 [(set_attr "length" "4")
8667 (set_attr "in_delay_slot" "no")])
8669 ;; 8 byte integer in line
8670 (define_insn "consttable_8"
8671 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
8672 (match_operand 1 "" "")]
8676 if (operands[1] != const0_rtx)
8677 assemble_integer (operands[0], 8, BITS_PER_UNIT * 8, 1);
8680 [(set_attr "length" "8")
8681 (set_attr "in_delay_slot" "no")])
8683 ;; 4 byte floating point
8684 (define_insn "consttable_sf"
8685 [(unspec_volatile [(match_operand:SF 0 "general_operand" "=g")
8686 (match_operand 1 "" "")]
8690 if (operands[1] != const0_rtx)
8691 assemble_real (*CONST_DOUBLE_REAL_VALUE (operands[0]),
8692 SFmode, GET_MODE_ALIGNMENT (SFmode));
8695 [(set_attr "length" "4")
8696 (set_attr "in_delay_slot" "no")])
8698 ;; 8 byte floating point
8699 (define_insn "consttable_df"
8700 [(unspec_volatile [(match_operand:DF 0 "general_operand" "=g")
8701 (match_operand 1 "" "")]
8705 if (operands[1] != const0_rtx)
8706 assemble_real (*CONST_DOUBLE_REAL_VALUE (operands[0]),
8707 DFmode, GET_MODE_ALIGNMENT (DFmode));
8710 [(set_attr "length" "8")
8711 (set_attr "in_delay_slot" "no")])
8713 ;; Alignment is needed for some constant tables; it may also be added for
8714 ;; Instructions at the start of loops, or after unconditional branches.
8715 ;; ??? We would get more accurate lengths if we did instruction
8716 ;; alignment based on the value of INSN_CURRENT_ADDRESS; the approach used
8717 ;; here is too conservative.
8719 ;; align to a two byte boundary
8720 (define_expand "align_2"
8721 [(unspec_volatile [(const_int 1)] UNSPECV_ALIGN)]
8725 ;; Align to a four byte boundary.
8726 ;; align_4 and align_log are instructions for the starts of loops, or
8727 ;; after unconditional branches, which may take up extra room.
8728 (define_expand "align_4"
8729 [(unspec_volatile [(const_int 2)] UNSPECV_ALIGN)]
8733 ;; Align to a cache line boundary.
8734 (define_insn "align_log"
8735 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPECV_ALIGN)]
8738 [(set_attr "length" "0")
8739 (set_attr "in_delay_slot" "no")])
8741 ;; Emitted at the end of the literal table, used to emit the
8742 ;; 32bit branch labels if needed.
8743 (define_insn "consttable_end"
8744 [(unspec_volatile [(const_int 0)] UNSPECV_CONST_END)]
8747 return output_jump_label_table ();
8749 [(set_attr "in_delay_slot" "no")])
8751 ;; Emitted at the end of the window in the literal table.
8752 (define_insn "consttable_window_end"
8753 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_WINDOW_END)]
8756 [(set_attr "length" "0")
8757 (set_attr "in_delay_slot" "no")])
8759 ;; -------------------------------------------------------------------------
8760 ;; Minimum / maximum operations.
8761 ;; -------------------------------------------------------------------------
8763 ;; The SH2A clips.b and clips.w insns do a signed min-max function. If smin
8764 ;; and smax standard name patterns are defined, they will be used during
8765 ;; initial expansion and combine will then be able to form the actual min-max
8767 ;; The clips.b and clips.w set the SR.CS bit if the value in the register is
8768 ;; clipped, but there is currently no way of making use of this information.
8769 ;; The only way to read or reset the SR.CS bit is by accessing the SR.
8770 (define_expand "<code>si3"
8771 [(parallel [(set (match_operand:SI 0 "arith_reg_dest")
8772 (SMIN_SMAX:SI (match_operand:SI 1 "arith_reg_operand")
8773 (match_operand 2 "const_int_operand")))
8774 (clobber (reg:SI T_REG))])]
8777 /* Force the comparison value into a register, because greater-than
8778 comparisons can work only on registers. Combine will be able to pick up
8779 the constant value from the REG_EQUAL note when trying to form a min-max
8781 operands[2] = force_reg (SImode, operands[2]);
8785 ;; smax (smin (...))
8787 ;; smin (smax (...))
8788 (define_insn_and_split "*clips"
8789 [(set (match_operand:SI 0 "arith_reg_dest")
8790 (smax:SI (smin:SI (match_operand:SI 1 "arith_reg_operand")
8791 (match_operand 2 "clips_max_const_int"))
8792 (match_operand 3 "clips_min_const_int")))]
8797 (smin:SI (smax:SI (match_dup 1) (match_dup 3)) (match_dup 2)))])
8799 (define_insn "*clips"
8800 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8801 (smin:SI (smax:SI (match_operand:SI 1 "arith_reg_operand" "0")
8802 (match_operand 2 "clips_min_const_int"))
8803 (match_operand 3 "clips_max_const_int")))]
8806 if (INTVAL (operands[3]) == 127)
8807 return "clips.b %0";
8808 else if (INTVAL (operands[3]) == 32767)
8809 return "clips.w %0";
8813 [(set_attr "type" "arith")])
8815 ;; If the expanded smin or smax patterns were not combined, split them into
8816 ;; a compare and branch sequence, because there are no real smin or smax
8818 (define_insn_and_split "*<code>si3"
8819 [(set (match_operand:SI 0 "arith_reg_dest")
8820 (SMIN_SMAX:SI (match_operand:SI 1 "arith_reg_operand")
8821 (match_operand:SI 2 "arith_reg_or_0_or_1_operand")))
8822 (clobber (reg:SI T_REG))]
8823 "TARGET_SH2A && can_create_pseudo_p ()"
8828 rtx_code_label *skip_label = gen_label_rtx ();
8829 emit_move_insn (operands[0], operands[1]);
8831 rtx cmp_val = operands[2];
8832 if (satisfies_constraint_M (cmp_val))
8833 cmp_val = const0_rtx;
8835 emit_insn (gen_cmpgtsi_t (operands[0], cmp_val));
8836 emit_jump_insn (<CODE> == SMIN
8837 ? gen_branch_false (skip_label)
8838 : gen_branch_true (skip_label));
8840 emit_label_after (skip_label, emit_move_insn (operands[0], operands[2]));
8844 ;; The SH2A clipu.b and clipu.w insns can be used to implement a min function
8845 ;; with a register and a constant.
8846 ;; The clipu.b and clipu.w set the SR.CS bit if the value in the register is
8847 ;; clipped, but there is currently no way of making use of this information.
8848 ;; The only way to read or reset the SR.CS bit is by accessing the SR.
8849 (define_expand "uminsi3"
8850 [(set (match_operand:SI 0 "arith_reg_dest")
8851 (umin:SI (match_operand:SI 1 "arith_reg_operand")
8852 (match_operand 2 "const_int_operand")))]
8855 if (INTVAL (operands[2]) == 1)
8857 emit_insn (gen_clipu_one (operands[0], operands[1]));
8860 else if (! clipu_max_const_int (operands[2], VOIDmode))
8864 (define_insn "*clipu"
8865 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8866 (umin:SI (match_operand:SI 1 "arith_reg_operand" "0")
8867 (match_operand 2 "clipu_max_const_int")))]
8870 if (INTVAL (operands[2]) == 255)
8871 return "clipu.b %0";
8872 else if (INTVAL (operands[2]) == 65535)
8873 return "clipu.w %0";
8877 [(set_attr "type" "arith")])
8879 (define_insn_and_split "clipu_one"
8880 [(set (match_operand:SI 0 "arith_reg_dest")
8881 (umin:SI (match_operand:SI 1 "arith_reg_operand") (const_int 1)))
8882 (clobber (reg:SI T_REG))]
8885 "&& can_create_pseudo_p ()"
8888 emit_insn (gen_cmpeqsi_t (operands[1], const0_rtx));
8889 emit_insn (gen_movnegt (operands[0], get_t_reg_rtx ()));
8893 ;; -------------------------------------------------------------------------
8895 ;; -------------------------------------------------------------------------
8897 ;; String/block move insn.
8899 (define_expand "movmemsi"
8900 [(parallel [(set (mem:BLK (match_operand:BLK 0))
8901 (mem:BLK (match_operand:BLK 1)))
8902 (use (match_operand:SI 2 "nonmemory_operand"))
8903 (use (match_operand:SI 3 "immediate_operand"))
8904 (clobber (reg:SI PR_REG))
8905 (clobber (reg:SI R4_REG))
8906 (clobber (reg:SI R5_REG))
8907 (clobber (reg:SI R0_REG))])]
8910 if (expand_block_move (operands))
8916 (define_insn "block_move_real"
8917 [(parallel [(set (mem:BLK (reg:SI R4_REG))
8918 (mem:BLK (reg:SI R5_REG)))
8919 (use (match_operand:SI 0 "arith_reg_operand" "r,r"))
8920 (use (match_operand 1 "" "Z,Ccl"))
8921 (clobber (reg:SI PR_REG))
8922 (clobber (reg:SI R0_REG))])]
8923 "TARGET_SH1 && ! TARGET_HARD_SH4"
8927 [(set_attr "type" "sfunc")
8928 (set_attr "needs_delay_slot" "yes")])
8930 (define_insn "block_lump_real"
8931 [(parallel [(set (mem:BLK (reg:SI R4_REG))
8932 (mem:BLK (reg:SI R5_REG)))
8933 (use (match_operand:SI 0 "arith_reg_operand" "r,r"))
8934 (use (match_operand 1 "" "Z,Ccl"))
8935 (use (reg:SI R6_REG))
8936 (clobber (reg:SI PR_REG))
8937 (clobber (reg:SI T_REG))
8938 (clobber (reg:SI R4_REG))
8939 (clobber (reg:SI R5_REG))
8940 (clobber (reg:SI R6_REG))
8941 (clobber (reg:SI R0_REG))])]
8942 "TARGET_SH1 && ! TARGET_HARD_SH4"
8946 [(set_attr "type" "sfunc")
8947 (set_attr "needs_delay_slot" "yes")])
8949 (define_insn "block_move_real_i4"
8950 [(parallel [(set (mem:BLK (reg:SI R4_REG))
8951 (mem:BLK (reg:SI R5_REG)))
8952 (use (match_operand:SI 0 "arith_reg_operand" "r,r"))
8953 (use (match_operand 1 "" "Z,Ccl"))
8954 (clobber (reg:SI PR_REG))
8955 (clobber (reg:SI R0_REG))
8956 (clobber (reg:SI R1_REG))
8957 (clobber (reg:SI R2_REG))])]
8962 [(set_attr "type" "sfunc")
8963 (set_attr "needs_delay_slot" "yes")])
8965 (define_insn "block_lump_real_i4"
8966 [(parallel [(set (mem:BLK (reg:SI R4_REG))
8967 (mem:BLK (reg:SI R5_REG)))
8968 (use (match_operand:SI 0 "arith_reg_operand" "r,r"))
8969 (use (match_operand 1 "" "Z,Ccl"))
8970 (use (reg:SI R6_REG))
8971 (clobber (reg:SI PR_REG))
8972 (clobber (reg:SI T_REG))
8973 (clobber (reg:SI R4_REG))
8974 (clobber (reg:SI R5_REG))
8975 (clobber (reg:SI R6_REG))
8976 (clobber (reg:SI R0_REG))
8977 (clobber (reg:SI R1_REG))
8978 (clobber (reg:SI R2_REG))
8979 (clobber (reg:SI R3_REG))])]
8984 [(set_attr "type" "sfunc")
8985 (set_attr "needs_delay_slot" "yes")])
8987 ;; byte compare pattern
8989 ;; !((temp & 0xF000) && (temp & 0x0F00) && (temp & 0x00F0) && (temp & 0x000F))
8990 (define_insn "cmpstr_t"
8991 [(set (reg:SI T_REG)
8996 (xor:SI (match_operand:SI 0 "arith_reg_operand" "r")
8997 (match_operand:SI 1 "arith_reg_operand" "r"))
8998 (const_int 8) (const_int 0))
8999 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
9000 (const_int 8) (const_int 8)))
9001 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
9002 (const_int 8) (const_int 16)))
9003 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
9004 (const_int 8) (const_int 24)))
9008 [(set_attr "type" "mt_group")])
9010 (define_expand "cmpstrsi"
9011 [(set (match_operand:SI 0 "register_operand")
9012 (compare:SI (match_operand:BLK 1 "memory_operand")
9013 (match_operand:BLK 2 "memory_operand")))
9014 (use (match_operand 3 "immediate_operand"))]
9015 "TARGET_SH1 && optimize"
9017 if (! optimize_insn_for_size_p () && sh_expand_cmpstr (operands))
9023 (define_expand "cmpstrnsi"
9024 [(set (match_operand:SI 0 "register_operand")
9025 (compare:SI (match_operand:BLK 1 "memory_operand")
9026 (match_operand:BLK 2 "memory_operand")))
9027 (use (match_operand:SI 3 "nonmemory_operand"))
9028 (use (match_operand:SI 4 "immediate_operand"))]
9029 "TARGET_SH1 && optimize"
9031 if (! optimize_insn_for_size_p () && sh_expand_cmpnstr (operands))
9037 (define_expand "strlensi"
9038 [(set (match_operand:SI 0 "register_operand")
9039 (unspec:SI [(match_operand:BLK 1 "memory_operand")
9040 (match_operand:SI 2 "immediate_operand")
9041 (match_operand:SI 3 "immediate_operand")]
9042 UNSPEC_BUILTIN_STRLEN))]
9043 "TARGET_SH1 && optimize"
9045 if (! optimize_insn_for_size_p () && sh_expand_strlen (operands))
9051 (define_expand "setmemqi"
9052 [(parallel [(set (match_operand:BLK 0 "memory_operand")
9053 (match_operand 2 "const_int_operand"))
9054 (use (match_operand:QI 1 "const_int_operand"))
9055 (use (match_operand:QI 3 "const_int_operand"))])]
9056 "TARGET_SH1 && optimize"
9058 if (optimize_insn_for_size_p ())
9061 sh_expand_setmem (operands);
9066 ;; -------------------------------------------------------------------------
9067 ;; Floating point instructions.
9068 ;; -------------------------------------------------------------------------
9070 ;; FIXME: For now we disallow any memory operands for fpscr loads/stores,
9071 ;; except for post-inc loads and pre-dec stores for push/pop purposes.
9072 ;; This avoids problems with reload. As a consequence, user initiated fpscr
9073 ;; stores to memory will always be ferried through a general register.
9074 ;; User initiated fpscr loads always have to undergo bit masking to preserve
9075 ;; the current fpu mode settings for the compiler generated code. Thus such
9076 ;; fpscr loads will always have to go through general registers anyways.
9077 (define_insn "lds_fpscr"
9078 [(set (reg:SI FPSCR_REG)
9079 (match_operand:SI 0 "fpscr_movsrc_operand" "r,>"))
9080 (set (reg:SI FPSCR_STAT_REG)
9081 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_STAT))
9082 (set (reg:SI FPSCR_MODES_REG)
9083 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))]
9088 [(set_attr "type" "gp_fpscr,mem_fpscr")])
9090 ;; A move fpscr -> reg schedules like a move mac -> reg. Thus we use mac_gp
9092 (define_insn "sts_fpscr"
9093 [(set (match_operand:SI 0 "fpscr_movdst_operand" "=r,<")
9095 (use (reg:SI FPSCR_STAT_REG))
9096 (use (reg:SI FPSCR_MODES_REG))]
9101 [(set_attr "type" "mac_gp,fstore")])
9103 (define_expand "set_fpscr"
9104 [(parallel [(set (reg:SI FPSCR_REG)
9105 (match_operand:SI 0 "general_operand"))
9106 (set (reg:SI FPSCR_STAT_REG)
9107 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))])]
9110 /* We have to mask out the FR, SZ and PR bits. To do that, we need to
9111 get the current FPSCR value first.
9112 (a & ~mask) | (b & mask) = a ^ ((a ^ b) & mask) */
9114 rtx mask = force_reg (SImode, GEN_INT (FPSCR_FR | FPSCR_SZ | FPSCR_PR));
9116 rtx a = force_reg (SImode, operands[0]);
9118 rtx b = gen_reg_rtx (SImode);
9119 emit_insn (gen_sts_fpscr (b));
9121 rtx a_xor_b = gen_reg_rtx (SImode);
9122 emit_insn (gen_xorsi3 (a_xor_b, a, b));
9124 rtx a_xor_b_and_mask = gen_reg_rtx (SImode);
9125 emit_insn (gen_andsi3 (a_xor_b_and_mask, a_xor_b, mask));
9127 rtx r = gen_reg_rtx (SImode);
9128 emit_insn (gen_xorsi3 (r, a_xor_b_and_mask, a));
9129 emit_insn (gen_lds_fpscr (r));
9134 ;; ??? This uses the fp unit, but has no type indicating that.
9135 ;; If we did that, this would either give a bogus latency or introduce
9136 ;; a bogus FIFO constraint.
9137 ;; Since this insn is currently only used for prologues/epilogues,
9138 ;; it is probably best to claim no function unit, which matches the
9140 (define_insn "toggle_sz"
9141 [(set (reg:SI FPSCR_REG)
9142 (xor:SI (reg:SI FPSCR_REG) (const_int FPSCR_SZ)))
9143 (set (reg:SI FPSCR_MODES_REG)
9144 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))]
9147 [(set_attr "type" "fpscr_toggle") (set_attr "fp_set" "unknown")])
9149 ;; Toggle FPU precision PR mode.
9151 (define_insn "toggle_pr"
9152 [(set (reg:SI FPSCR_REG)
9153 (xor:SI (reg:SI FPSCR_REG) (const_int FPSCR_PR)))
9154 (set (reg:SI FPSCR_MODES_REG)
9155 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))]
9158 [(set_attr "type" "fpscr_toggle")])
9160 (define_expand "addsf3"
9161 [(set (match_operand:SF 0 "fp_arith_reg_operand")
9162 (plus:SF (match_operand:SF 1 "fp_arith_reg_operand")
9163 (match_operand:SF 2 "fp_arith_reg_operand")))]
9166 emit_insn (gen_addsf3_i (operands[0], operands[1], operands[2]));
9170 (define_insn "addsf3_i"
9171 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9172 (plus:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
9173 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
9174 (clobber (reg:SI FPSCR_STAT_REG))
9175 (use (reg:SI FPSCR_MODES_REG))]
9178 [(set_attr "type" "fp")
9179 (set_attr "fp_mode" "single")])
9181 (define_expand "subsf3"
9182 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
9183 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
9184 (match_operand:SF 2 "fp_arith_reg_operand" "")))]
9187 emit_insn (gen_subsf3_i (operands[0], operands[1], operands[2]));
9191 (define_insn "subsf3_i"
9192 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9193 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
9194 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
9195 (clobber (reg:SI FPSCR_STAT_REG))
9196 (use (reg:SI FPSCR_MODES_REG))]
9199 [(set_attr "type" "fp")
9200 (set_attr "fp_mode" "single")])
9202 (define_expand "mulsf3"
9203 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
9204 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
9205 (match_operand:SF 2 "fp_arith_reg_operand" "")))]
9208 emit_insn (gen_mulsf3_i (operands[0], operands[1], operands[2]));
9212 (define_insn "mulsf3_i"
9213 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9214 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
9215 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
9216 (clobber (reg:SI FPSCR_STAT_REG))
9217 (use (reg:SI FPSCR_MODES_REG))]
9220 [(set_attr "type" "fp")
9221 (set_attr "fp_mode" "single")])
9223 ;; FMA (fused multiply-add) patterns
9224 (define_expand "fmasf4"
9225 [(set (match_operand:SF 0 "fp_arith_reg_operand")
9226 (fma:SF (match_operand:SF 1 "fp_arith_reg_operand")
9227 (match_operand:SF 2 "fp_arith_reg_operand")
9228 (match_operand:SF 3 "fp_arith_reg_operand")))]
9231 emit_insn (gen_fmasf4_i (operands[0], operands[1], operands[2], operands[3]));
9235 (define_insn "fmasf4_i"
9236 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9237 (fma:SF (match_operand:SF 1 "fp_arith_reg_operand" "w")
9238 (match_operand:SF 2 "fp_arith_reg_operand" "f")
9239 (match_operand:SF 3 "fp_arith_reg_operand" "0")))
9240 (clobber (reg:SI FPSCR_STAT_REG))
9241 (use (reg:SI FPSCR_MODES_REG))]
9244 [(set_attr "type" "fp")
9245 (set_attr "fp_mode" "single")])
9247 ;; For some cases such as 'a * b + a' the FMA pattern is not generated by
9248 ;; previous transformations. If FMA is generally allowed, let the combine
9250 (define_insn_and_split "*fmasf4"
9251 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9252 (plus:SF (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%w")
9253 (match_operand:SF 2 "fp_arith_reg_operand" "f"))
9254 (match_operand:SF 3 "arith_reg_operand" "0")))
9255 (clobber (reg:SI FPSCR_STAT_REG))
9256 (use (reg:SI FPSCR_MODES_REG))]
9257 "TARGET_SH2E && flag_fp_contract_mode != FP_CONTRACT_OFF"
9259 "&& can_create_pseudo_p ()"
9260 [(parallel [(set (match_dup 0)
9261 (fma:SF (match_dup 1) (match_dup 2) (match_dup 3)))
9262 (clobber (reg:SI FPSCR_STAT_REG))
9263 (use (reg:SI FPSCR_MODES_REG))])]
9265 /* Change 'b * a + a' into 'a * b + a'.
9266 This is better for register allocation. */
9267 if (REGNO (operands[2]) == REGNO (operands[3]))
9268 std::swap (operands[1], operands[2]);
9270 [(set_attr "type" "fp")
9271 (set_attr "fp_mode" "single")])
9273 (define_expand "divsf3"
9274 [(set (match_operand:SF 0 "fp_arith_reg_operand")
9275 (div:SF (match_operand:SF 1 "fp_arith_reg_operand")
9276 (match_operand:SF 2 "fp_arith_reg_operand")))]
9279 emit_insn (gen_divsf3_i (operands[0], operands[1], operands[2]));
9283 (define_insn "divsf3_i"
9284 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9285 (div:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
9286 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
9287 (clobber (reg:SI FPSCR_STAT_REG))
9288 (use (reg:SI FPSCR_MODES_REG))]
9291 [(set_attr "type" "fdiv")
9292 (set_attr "fp_mode" "single")])
9294 (define_expand "floatsisf2"
9295 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
9296 (float:SF (match_operand:SI 1 "fpul_operand" "")))]
9299 emit_insn (gen_floatsisf2_i4 (operands[0], operands[1]));
9303 (define_insn "floatsisf2_i4"
9304 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9305 (float:SF (match_operand:SI 1 "fpul_operand" "y")))
9306 (clobber (reg:SI FPSCR_STAT_REG))
9307 (use (reg:SI FPSCR_MODES_REG))]
9310 [(set_attr "type" "fp")
9311 (set_attr "fp_mode" "single")])
9313 (define_expand "fix_truncsfsi2"
9314 [(set (match_operand:SI 0 "fpul_operand")
9315 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand")))]
9318 emit_insn (gen_fix_truncsfsi2_i4 (operands[0], operands[1]));
9322 (define_insn "fix_truncsfsi2_i4"
9323 [(set (match_operand:SI 0 "fpul_operand" "=y")
9324 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))
9325 (clobber (reg:SI FPSCR_STAT_REG))
9326 (use (reg:SI FPSCR_MODES_REG))]
9329 [(set_attr "type" "ftrc_s")
9330 (set_attr "fp_mode" "single")])
9332 (define_insn "cmpgtsf_t"
9333 [(set (reg:SI T_REG)
9334 (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
9335 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
9336 (clobber (reg:SI FPSCR_STAT_REG))
9337 (use (reg:SI FPSCR_MODES_REG))]
9338 "TARGET_SH2E || TARGET_SH4 || TARGET_SH2A_SINGLE"
9340 [(set_attr "type" "fp_cmp")
9341 (set_attr "fp_mode" "single")])
9343 (define_insn "cmpeqsf_t"
9344 [(set (reg:SI T_REG)
9345 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
9346 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
9347 (clobber (reg:SI FPSCR_STAT_REG))
9348 (use (reg:SI FPSCR_MODES_REG))]
9349 "TARGET_SH2E || TARGET_SH4 || TARGET_SH2A_SINGLE"
9351 [(set_attr "type" "fp_cmp")
9352 (set_attr "fp_mode" "single")])
9354 (define_insn "ieee_ccmpeqsf_t"
9355 [(set (reg:SI T_REG)
9356 (ior:SI (reg:SI T_REG)
9357 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
9358 (match_operand:SF 1 "fp_arith_reg_operand" "f"))))
9359 (clobber (reg:SI FPSCR_STAT_REG))
9360 (use (reg:SI FPSCR_MODES_REG))]
9361 "TARGET_IEEE && TARGET_SH2E"
9363 return output_ieee_ccmpeq (insn, operands);
9365 [(set_attr "length" "4")
9366 (set_attr "fp_mode" "single")])
9368 (define_expand "cbranchsf4"
9370 (if_then_else (match_operator 0 "ordered_comparison_operator"
9371 [(match_operand:SF 1 "arith_operand" "")
9372 (match_operand:SF 2 "arith_operand" "")])
9373 (match_operand 3 "" "")
9377 sh_emit_compare_and_branch (operands, SFmode);
9381 (define_expand "negsf2"
9382 [(set (match_operand:SF 0 "fp_arith_reg_operand")
9383 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand")))]
9386 (define_insn "*negsf2_i"
9387 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9388 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))]
9391 [(set_attr "type" "fmove")])
9393 (define_expand "sqrtsf2"
9394 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
9395 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
9398 emit_insn (gen_sqrtsf2_i (operands[0], operands[1]));
9402 (define_insn "sqrtsf2_i"
9403 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9404 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
9405 (clobber (reg:SI FPSCR_STAT_REG))
9406 (use (reg:SI FPSCR_MODES_REG))]
9409 [(set_attr "type" "fdiv")
9410 (set_attr "fp_mode" "single")])
9412 (define_insn "rsqrtsf2"
9413 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9414 (unspec:SF [(match_operand:SF 1 "fp_arith_reg_operand" "0")]
9416 (clobber (reg:SI FPSCR_STAT_REG))
9417 (use (reg:SI FPSCR_MODES_REG))]
9418 "TARGET_FPU_ANY && TARGET_FSRRA"
9420 [(set_attr "type" "fsrra")
9421 (set_attr "fp_mode" "single")])
9423 ;; When the sincos pattern is defined, the builtin functions sin and cos
9424 ;; will be expanded to the sincos pattern and one of the output values will
9426 (define_expand "sincossf3"
9427 [(set (match_operand:SF 0 "nonimmediate_operand")
9428 (unspec:SF [(match_operand:SF 2 "fp_arith_reg_operand")] UNSPEC_FCOSA))
9429 (set (match_operand:SF 1 "nonimmediate_operand")
9430 (unspec:SF [(match_dup 2)] UNSPEC_FSINA))]
9431 "TARGET_FPU_ANY && TARGET_FSCA"
9433 rtx scaled = gen_reg_rtx (SFmode);
9434 rtx truncated = gen_reg_rtx (SImode);
9435 rtx fsca = gen_reg_rtx (V2SFmode);
9436 rtx scale_reg = force_reg (SFmode, sh_fsca_sf2int ());
9438 emit_insn (gen_mulsf3 (scaled, operands[2], scale_reg));
9439 emit_insn (gen_fix_truncsfsi2 (truncated, scaled));
9440 emit_insn (gen_fsca (fsca, truncated, sh_fsca_int2sf ()));
9442 emit_move_insn (operands[0], gen_rtx_SUBREG (SFmode, fsca, 4));
9443 emit_move_insn (operands[1], gen_rtx_SUBREG (SFmode, fsca, 0));
9447 (define_insn_and_split "fsca"
9448 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
9450 (unspec:SF [(mult:SF
9451 (float:SF (match_operand:SI 1 "fpul_fsca_operand" "y"))
9452 (match_operand:SF 2 "fsca_scale_factor" "i"))
9454 (unspec:SF [(mult:SF (float:SF (match_dup 1)) (match_dup 2))
9456 (clobber (reg:SI FPSCR_STAT_REG))
9457 (use (reg:SI FPSCR_MODES_REG))]
9458 "TARGET_FPU_ANY && TARGET_FSCA"
9460 "&& !fpul_operand (operands[1], SImode)"
9463 /* If operands[1] is something like (fix:SF (float:SF (reg:SI))) reduce it
9464 to a simple reg, otherwise reload will have trouble reloading the
9465 pseudo into fpul. */
9466 rtx x = XEXP (operands[1], 0);
9467 while (x != NULL_RTX && !fpul_operand (x, SImode))
9469 gcc_assert (GET_CODE (x) == FIX || GET_CODE (x) == FLOAT);
9472 gcc_assert (x != NULL_RTX && fpul_operand (x, SImode));
9473 emit_insn (gen_fsca (operands[0], x, operands[2]));
9476 [(set_attr "type" "fsca")
9477 (set_attr "fp_mode" "single")])
9479 (define_expand "abssf2"
9480 [(set (match_operand:SF 0 "fp_arith_reg_operand")
9481 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand")))]
9484 (define_insn "*abssf2_i"
9485 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9486 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))]
9489 [(set_attr "type" "fmove")])
9491 (define_expand "adddf3"
9492 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
9493 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
9494 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
9497 emit_insn (gen_adddf3_i (operands[0], operands[1], operands[2]));
9501 (define_insn "adddf3_i"
9502 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9503 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
9504 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
9505 (clobber (reg:SI FPSCR_STAT_REG))
9506 (use (reg:SI FPSCR_MODES_REG))]
9509 [(set_attr "type" "dfp_arith")
9510 (set_attr "fp_mode" "double")])
9512 (define_expand "subdf3"
9513 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
9514 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
9515 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
9518 emit_insn (gen_subdf3_i (operands[0], operands[1], operands[2]));
9522 (define_insn "subdf3_i"
9523 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9524 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
9525 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
9526 (clobber (reg:SI FPSCR_STAT_REG))
9527 (use (reg:SI FPSCR_MODES_REG))]
9530 [(set_attr "type" "dfp_arith")
9531 (set_attr "fp_mode" "double")])
9533 (define_expand "muldf3"
9534 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
9535 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
9536 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
9539 emit_insn (gen_muldf3_i (operands[0], operands[1], operands[2]));
9543 (define_insn "muldf3_i"
9544 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9545 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
9546 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
9547 (clobber (reg:SI FPSCR_STAT_REG))
9548 (use (reg:SI FPSCR_MODES_REG))]
9551 [(set_attr "type" "dfp_mul")
9552 (set_attr "fp_mode" "double")])
9554 (define_expand "divdf3"
9555 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
9556 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
9557 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
9560 emit_insn (gen_divdf3_i (operands[0], operands[1], operands[2]));
9564 (define_insn "divdf3_i"
9565 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9566 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
9567 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
9568 (clobber (reg:SI FPSCR_STAT_REG))
9569 (use (reg:SI FPSCR_MODES_REG))]
9572 [(set_attr "type" "dfdiv")
9573 (set_attr "fp_mode" "double")])
9575 (define_expand "floatsidf2"
9576 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
9577 (float:DF (match_operand:SI 1 "fpul_operand" "")))]
9580 emit_insn (gen_floatsidf2_i (operands[0], operands[1]));
9584 (define_insn "floatsidf2_i"
9585 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9586 (float:DF (match_operand:SI 1 "fpul_operand" "y")))
9587 (clobber (reg:SI FPSCR_STAT_REG))
9588 (use (reg:SI FPSCR_MODES_REG))]
9591 [(set_attr "type" "dfp_conv")
9592 (set_attr "fp_mode" "double")])
9594 (define_expand "fix_truncdfsi2"
9595 [(set (match_operand:SI 0 "fpul_operand" "")
9596 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "")))]
9599 emit_insn (gen_fix_truncdfsi2_i (operands[0], operands[1]));
9603 (define_insn "fix_truncdfsi2_i"
9604 [(set (match_operand:SI 0 "fpul_operand" "=y")
9605 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")))
9606 (clobber (reg:SI FPSCR_STAT_REG))
9607 (use (reg:SI FPSCR_MODES_REG))]
9610 [(set_attr "type" "dfp_conv")
9611 (set_attr "dfp_comp" "no")
9612 (set_attr "fp_mode" "double")])
9614 (define_insn "cmpgtdf_t"
9615 [(set (reg:SI T_REG)
9616 (gt:SI (match_operand:DF 0 "fp_arith_reg_operand" "f")
9617 (match_operand:DF 1 "fp_arith_reg_operand" "f")))
9618 (clobber (reg:SI FPSCR_STAT_REG))
9619 (use (reg:SI FPSCR_MODES_REG))]
9622 [(set_attr "type" "dfp_cmp")
9623 (set_attr "fp_mode" "double")])
9625 (define_insn "cmpeqdf_t"
9626 [(set (reg:SI T_REG)
9627 (eq:SI (match_operand:DF 0 "fp_arith_reg_operand" "f")
9628 (match_operand:DF 1 "fp_arith_reg_operand" "f")))
9629 (clobber (reg:SI FPSCR_STAT_REG))
9630 (use (reg:SI FPSCR_MODES_REG))]
9633 [(set_attr "type" "dfp_cmp")
9634 (set_attr "fp_mode" "double")])
9636 (define_insn "*ieee_ccmpeqdf_t"
9637 [(set (reg:SI T_REG)
9638 (ior:SI (reg:SI T_REG)
9639 (eq:SI (match_operand:DF 0 "fp_arith_reg_operand" "f")
9640 (match_operand:DF 1 "fp_arith_reg_operand" "f"))))
9641 (clobber (reg:SI FPSCR_STAT_REG))
9642 (use (reg:SI FPSCR_MODES_REG))]
9643 "TARGET_IEEE && TARGET_FPU_DOUBLE"
9645 return output_ieee_ccmpeq (insn, operands);
9647 [(set_attr "length" "4")
9648 (set_attr "fp_mode" "double")])
9650 (define_expand "cbranchdf4"
9652 (if_then_else (match_operator 0 "ordered_comparison_operator"
9653 [(match_operand:DF 1 "arith_operand" "")
9654 (match_operand:DF 2 "arith_operand" "")])
9655 (match_operand 3 "" "")
9659 sh_emit_compare_and_branch (operands, DFmode);
9663 (define_expand "negdf2"
9664 [(set (match_operand:DF 0 "fp_arith_reg_operand")
9665 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
9666 "TARGET_FPU_DOUBLE")
9668 (define_insn "*negdf2_i"
9669 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9670 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))]
9673 [(set_attr "type" "fmove")])
9675 (define_expand "sqrtdf2"
9676 [(set (match_operand:DF 0 "fp_arith_reg_operand")
9677 (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
9680 emit_insn (gen_sqrtdf2_i (operands[0], operands[1]));
9684 (define_insn "sqrtdf2_i"
9685 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9686 (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))
9687 (clobber (reg:SI FPSCR_STAT_REG))
9688 (use (reg:SI FPSCR_MODES_REG))]
9691 [(set_attr "type" "dfdiv")
9692 (set_attr "fp_mode" "double")])
9694 (define_expand "absdf2"
9695 [(set (match_operand:DF 0 "fp_arith_reg_operand")
9696 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
9697 "TARGET_FPU_DOUBLE")
9699 (define_insn "*absdf2_i"
9700 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9701 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))]
9704 [(set_attr "type" "fmove")])
9706 (define_expand "extendsfdf2"
9707 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
9708 (float_extend:DF (match_operand:SF 1 "fpul_operand" "")))]
9711 emit_insn (gen_extendsfdf2_i4 (operands[0], operands[1]));
9715 (define_insn "extendsfdf2_i4"
9716 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9717 (float_extend:DF (match_operand:SF 1 "fpul_operand" "y")))
9718 (clobber (reg:SI FPSCR_STAT_REG))
9719 (use (reg:SI FPSCR_MODES_REG))]
9722 [(set_attr "type" "fp")
9723 (set_attr "fp_mode" "double")])
9725 (define_expand "truncdfsf2"
9726 [(set (match_operand:SF 0 "fpul_operand" "")
9727 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "")))]
9730 emit_insn (gen_truncdfsf2_i4 (operands[0], operands[1]));
9734 (define_insn "truncdfsf2_i4"
9735 [(set (match_operand:SF 0 "fpul_operand" "=y")
9736 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f")))
9737 (clobber (reg:SI FPSCR_STAT_REG))
9738 (use (reg:SI FPSCR_MODES_REG))]
9741 [(set_attr "type" "fp")
9742 (set_attr "fp_mode" "double")])
9744 ;; -------------------------------------------------------------------------
9745 ;; Bit field extract patterns.
9746 ;; -------------------------------------------------------------------------
9748 ;; These give better code for packed bitfields, because they allow
9749 ;; auto-increment addresses to be generated.
9751 (define_expand "insv"
9752 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "")
9753 (match_operand:SI 1 "immediate_operand" "")
9754 (match_operand:SI 2 "immediate_operand" ""))
9755 (match_operand:SI 3 "general_operand" ""))]
9756 "TARGET_SH1 && TARGET_BIG_ENDIAN"
9758 rtx addr_target, orig_address, shift_reg, qi_val;
9759 HOST_WIDE_INT bitsize, size, v = 0;
9760 rtx x = operands[3];
9762 if (TARGET_SH2A && TARGET_BITOPS
9763 && (satisfies_constraint_Sbw (operands[0])
9764 || satisfies_constraint_Sbv (operands[0]))
9765 && satisfies_constraint_M (operands[1])
9766 && satisfies_constraint_K03 (operands[2]))
9768 if (satisfies_constraint_N (operands[3]))
9770 emit_insn (gen_bclr_m2a (operands[0], operands[2]));
9773 else if (satisfies_constraint_M (operands[3]))
9775 emit_insn (gen_bset_m2a (operands[0], operands[2]));
9778 else if ((REG_P (operands[3]) && REGNO (operands[3]) == T_REG)
9779 && satisfies_constraint_M (operands[1]))
9781 emit_insn (gen_bst_m2a (operands[0], operands[2]));
9784 else if (REG_P (operands[3])
9785 && satisfies_constraint_M (operands[1]))
9787 emit_insn (gen_bldsi_reg (operands[3], const0_rtx));
9788 emit_insn (gen_bst_m2a (operands[0], operands[2]));
9792 /* ??? expmed doesn't care for non-register predicates. */
9793 if (! memory_operand (operands[0], VOIDmode)
9794 || ! immediate_operand (operands[1], VOIDmode)
9795 || ! immediate_operand (operands[2], VOIDmode)
9796 || ! general_operand (x, VOIDmode))
9798 /* If this isn't a 16 / 24 / 32 bit field, or if
9799 it doesn't start on a byte boundary, then fail. */
9800 bitsize = INTVAL (operands[1]);
9801 if (bitsize < 16 || bitsize > 32 || bitsize % 8 != 0
9802 || (INTVAL (operands[2]) % 8) != 0)
9806 orig_address = XEXP (operands[0], 0);
9807 shift_reg = gen_reg_rtx (SImode);
9808 if (CONST_INT_P (x))
9811 qi_val = force_reg (QImode, GEN_INT (trunc_int_for_mode (v, QImode)));
9815 emit_insn (gen_movsi (shift_reg, operands[3]));
9816 qi_val = gen_rtx_SUBREG (QImode, shift_reg, 3);
9818 addr_target = copy_addr_to_reg (plus_constant (Pmode,
9819 orig_address, size - 1));
9821 operands[0] = replace_equiv_address (operands[0], addr_target);
9822 emit_insn (gen_movqi (operands[0], qi_val));
9826 if (CONST_INT_P (x))
9828 = force_reg (QImode, GEN_INT (trunc_int_for_mode (v >>= 8, QImode)));
9831 emit_insn (gen_lshrsi3_k (shift_reg, shift_reg, GEN_INT (8)));
9832 qi_val = gen_rtx_SUBREG (QImode, shift_reg, 3);
9834 emit_insn (gen_addsi3 (addr_target, addr_target, constm1_rtx));
9835 emit_insn (gen_movqi (operands[0], qi_val));
9841 (define_insn "movua"
9842 [(set (match_operand:SI 0 "register_operand" "=z")
9843 (unspec:SI [(match_operand:BLK 1 "unaligned_load_operand" "Sua>")]
9847 [(set_attr "type" "movua")])
9849 ;; We shouldn't need this, but cse replaces increments with references
9850 ;; to other regs before flow has a chance to create post_inc
9851 ;; addressing modes, and only postreload's cse_move2add brings the
9852 ;; increments back to a usable form.
9854 [(set (match_operand:SI 0 "register_operand" "")
9855 (sign_extract:SI (mem:SI (match_operand:SI 1 "register_operand" ""))
9856 (const_int 32) (const_int 0)))
9857 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
9858 "TARGET_SH4A && REGNO (operands[0]) != REGNO (operands[1])"
9859 [(set (match_operand:SI 0 "register_operand" "")
9860 (sign_extract:SI (mem:SI (post_inc:SI
9861 (match_operand:SI 1 "register_operand" "")))
9862 (const_int 32) (const_int 0)))]
9865 (define_expand "extv"
9866 [(set (match_operand:SI 0 "register_operand" "")
9867 (sign_extract:SI (match_operand:QI 1 "unaligned_load_operand" "")
9868 (match_operand 2 "const_int_operand" "")
9869 (match_operand 3 "const_int_operand" "")))]
9870 "TARGET_SH4A || TARGET_SH2A"
9872 if (TARGET_SH2A && TARGET_BITOPS
9873 && (satisfies_constraint_Sbw (operands[1])
9874 || satisfies_constraint_Sbv (operands[1]))
9875 && satisfies_constraint_M (operands[2])
9876 && satisfies_constraint_K03 (operands[3]))
9878 emit_insn (gen_bldsign_m2a (operands[1], operands[3]));
9879 if (REGNO (operands[0]) != T_REG)
9880 emit_insn (gen_movsi (operands[0], gen_rtx_REG (SImode, T_REG)));
9884 && INTVAL (operands[2]) == 32
9885 && INTVAL (operands[3]) == 0
9886 && MEM_P (operands[1]) && MEM_ALIGN (operands[1]) < 32)
9888 rtx src = adjust_address (operands[1], BLKmode, 0);
9889 set_mem_size (src, 4);
9890 emit_insn (gen_movua (operands[0], src));
9897 (define_expand "extzv"
9898 [(set (match_operand:SI 0 "register_operand" "")
9899 (zero_extract:SI (match_operand:QI 1 "unaligned_load_operand" "")
9900 (match_operand 2 "const_int_operand" "")
9901 (match_operand 3 "const_int_operand" "")))]
9902 "TARGET_SH4A || TARGET_SH2A"
9904 if (TARGET_SH2A && TARGET_BITOPS
9905 && (satisfies_constraint_Sbw (operands[1])
9906 || satisfies_constraint_Sbv (operands[1]))
9907 && satisfies_constraint_M (operands[2])
9908 && satisfies_constraint_K03 (operands[3]))
9910 emit_insn (gen_bld_m2a (operands[1], operands[3]));
9911 if (REGNO (operands[0]) != T_REG)
9912 emit_insn (gen_movsi (operands[0], gen_rtx_REG (SImode, T_REG)));
9916 && INTVAL (operands[2]) == 32
9917 && INTVAL (operands[3]) == 0
9918 && MEM_P (operands[1]) && MEM_ALIGN (operands[1]) < 32)
9920 rtx src = adjust_address (operands[1], BLKmode, 0);
9921 set_mem_size (src, 4);
9922 emit_insn (gen_movua (operands[0], src));
9929 ;; -------------------------------------------------------------------------
9930 ;; Extract negated single bit and zero extend it.
9931 ;; Generally we don't care about the exact xor const_int value, as long
9932 ;; as it contains the extracted bit. For simplicity, the pattern variations
9933 ;; that convert everything into the primary '*neg_zero_extract_0' pattern use
9934 ;; a xor const_int -1 value.
9936 (define_insn_and_split "*neg_zero_extract_0"
9937 [(set (reg:SI T_REG)
9938 (zero_extract:SI (xor:QIHISI (match_operand:QIHISI 0 "arith_reg_operand")
9939 (match_operand 1 "const_int_operand"))
9941 (match_operand 2 "const_int_operand")))]
9942 "TARGET_SH1 && can_create_pseudo_p ()
9943 && INTVAL (operands[1]) & (1LL << INTVAL (operands[2]))"
9946 [(set (reg:SI T_REG) (eq:SI (and:SI (match_dup 0) (match_dup 2))
9949 if (INTVAL (operands[2]) == 31 && <MODE>mode == SImode)
9951 /* Use cmp/pz to extract bit 31 into the T bit. */
9952 emit_insn (gen_cmpgesi_t (operands[0], const0_rtx));
9956 operands[2] = GEN_INT ((1 << INTVAL (operands[2])));
9957 if (GET_MODE (operands[0]) != SImode)
9958 operands[0] = simplify_gen_subreg (SImode, operands[0], <MODE>mode, 0);
9961 (define_insn_and_split "*neg_zero_extract_1"
9962 [(set (reg:SI T_REG)
9963 (and:SI (not:SI (match_operand:SI 0 "arith_reg_operand"))
9968 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1))
9969 (const_int 1) (const_int 0)))])
9971 ;; x & (1 << n) == 0: 0x00000000 + 1 = 1
9972 ;; x & (1 << n) != 0: 0xFFFFFFFF + 1 = 0
9973 (define_insn_and_split "*neg_zero_extract_2"
9974 [(set (reg:SI T_REG)
9975 (plus:SI (sign_extract:SI (match_operand:QIHISI 0 "arith_reg_operand")
9977 (match_operand 1 "const_int_operand"))
9979 "TARGET_SH1 && can_create_pseudo_p ()"
9982 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1))
9983 (const_int 1) (match_dup 1)))])
9985 ;; (signed)x >> 31 + 1 = (x >= 0) ^ 1
9986 (define_insn_and_split "*neg_zero_extract_3"
9987 [(set (reg:SI T_REG)
9988 (plus:SI (ashiftrt:SI (match_operand:SI 0 "arith_reg_operand")
9991 "TARGET_SH1 && can_create_pseudo_p ()"
9994 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1))
9995 (const_int 1) (const_int 31)))])
9997 ;; This is required for some bit patterns of DImode subregs.
9998 ;; It looks like combine gets confused by the DImode right shift and fails
9999 ;; to simplify things.
10000 (define_insn_and_split "*neg_zero_extract_4"
10001 [(set (reg:SI T_REG)
10003 (lshiftrt:SI (xor:SI (match_operand:SI 0 "arith_reg_operand")
10004 (match_operand 1 "const_int_operand"))
10005 (match_operand 2 "const_int_operand"))
10006 (not:SI (ashift:SI (match_operand:SI 3 "arith_reg_operand")
10007 (match_operand 4 "const_int_operand"))))
10009 "TARGET_SH1 && can_create_pseudo_p ()
10010 && INTVAL (operands[4]) > 0
10011 && INTVAL (operands[1]) & (1LL << INTVAL (operands[2]))"
10014 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
10015 (const_int 1) (match_dup 2)))])
10017 (define_insn_and_split "*neg_zero_extract_5"
10018 [(set (reg:SI T_REG)
10019 (and:SI (not:SI (subreg:SI
10020 (lshiftrt:DI (match_operand:DI 0 "arith_reg_operand")
10021 (match_operand 1 "const_int_operand"))
10024 "TARGET_SH1 && TARGET_LITTLE_ENDIAN && can_create_pseudo_p ()
10025 && INTVAL (operands[1]) < 32"
10028 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1))
10029 (const_int 1) (match_dup 1)))]
10031 operands[0] = gen_lowpart (SImode, operands[0]);
10034 (define_insn_and_split "*neg_zero_extract_6"
10035 [(set (reg:SI T_REG)
10036 (and:SI (not:SI (subreg:SI
10037 (lshiftrt:DI (match_operand:DI 0 "arith_reg_operand")
10038 (match_operand 1 "const_int_operand"))
10041 "TARGET_SH1 && TARGET_BIG_ENDIAN && can_create_pseudo_p ()
10042 && INTVAL (operands[1]) < 32"
10045 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1))
10046 (const_int 1) (match_dup 1)))]
10048 operands[0] = gen_lowpart (SImode, operands[0]);
10051 ;; -------------------------------------------------------------------------
10052 ;; Extract single bit and zero extend it.
10053 ;; All patterns store the result bit in the T bit, although that is not
10054 ;; always possible to do with a single insn and a nott must be appended.
10055 ;; The trailing nott will be optimized away in most cases. E.g. if the
10056 ;; extracted bit is fed into a branch condition, the condition can be
10057 ;; inverted and the nott will be eliminated.
10058 ;; FIXME: In cases where the trailing nott can't be eliminated, try to
10059 ;; convert it into a (not, tst) sequence, which could be better on non-SH2A.
10061 ;; On SH2A the 'bld<mode>_reg' insn will be used if the bit position fits.
10062 (define_insn_and_split "*zero_extract_0"
10063 [(set (reg:SI T_REG)
10064 (zero_extract:SI (match_operand:QIHISI 0 "arith_reg_operand")
10066 (match_operand 1 "const_int_operand")))]
10067 "TARGET_SH1 && can_create_pseudo_p ()
10068 && !(TARGET_SH2A && satisfies_constraint_K03 (operands[1]))"
10071 [(set (reg:SI T_REG) (eq:SI (and:SI (match_dup 0) (match_dup 1))
10073 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))]
10075 if (INTVAL (operands[1]) == 31 && <MODE>mode == SImode)
10077 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[0]));
10081 operands[1] = GEN_INT (1 << INTVAL (operands[1]));
10082 if (GET_MODE (operands[0]) != SImode)
10083 operands[0] = simplify_gen_subreg (SImode, operands[0], <MODE>mode, 0);
10086 ;; This is required for some bit patterns of DImode subregs.
10087 ;; It looks like combine gets confused by the DImode right shift and fails
10088 ;; to simplify things.
10089 (define_insn_and_split "*zero_extract_1"
10090 [(set (reg:SI T_REG)
10091 (subreg:SI (zero_extract:DI (match_operand:SI 0 "arith_reg_operand")
10093 (match_operand 1 "const_int_operand"))
10095 "TARGET_SH1 && TARGET_LITTLE_ENDIAN && can_create_pseudo_p ()
10096 && INTVAL (operands[1]) < 32"
10099 [(set (reg:SI T_REG)
10100 (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1)))])
10102 (define_insn_and_split "*zero_extract_2"
10103 [(set (reg:SI T_REG)
10104 (subreg:SI (zero_extract:DI (match_operand:SI 0 "arith_reg_operand")
10106 (match_operand 1 "const_int_operand"))
10108 "TARGET_SH1 && TARGET_BIG_ENDIAN && can_create_pseudo_p ()
10109 && INTVAL (operands[1]) < 32"
10112 [(set (reg:SI T_REG)
10113 (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1)))])
10115 (define_insn_and_split "*zero_extract_3"
10116 [(set (match_operand:SI 0 "arith_reg_dest")
10117 (and:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
10118 (match_operand 2 "const_int_operand"))
10119 (match_operand 3 "const_int_operand")))
10120 (clobber (reg:SI T_REG))]
10121 "TARGET_SH1 && can_create_pseudo_p ()
10122 && exact_log2 (INTVAL (operands[3])) >= 0"
10127 int rshift = INTVAL (operands[2]);
10128 int lshift = exact_log2 (INTVAL (operands[3]));
10130 rtx tmp = gen_reg_rtx (SImode);
10131 emit_insn (gen_rtx_PARALLEL (VOIDmode,
10134 gen_rtx_ZERO_EXTRACT (SImode, operands[1], const1_rtx,
10135 GEN_INT (rshift + lshift))),
10136 gen_rtx_CLOBBER (VOIDmode, get_t_reg_rtx ()))));
10137 emit_insn (gen_ashlsi3 (operands[0], tmp, GEN_INT (lshift)));
10140 ;; -------------------------------------------------------------------------
10141 ;; SH2A instructions for bitwise operations.
10142 ;; FIXME: Convert multiple instruction insns to insn_and_split.
10143 ;; FIXME: Use iterators to fold at least and,xor,or insn variations.
10145 ;; Clear a bit in a memory location.
10146 (define_insn "bclr_m2a"
10147 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
10149 (not:QI (ashift:QI (const_int 1)
10150 (match_operand:QI 1 "const_int_operand" "K03,K03")))
10152 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10155 bclr.b %1,@(0,%t0)"
10156 [(set_attr "length" "4,4")])
10158 (define_insn "bclrmem_m2a"
10159 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
10160 (and:QI (match_dup 0)
10161 (match_operand:QI 1 "const_int_operand" "Psz,Psz")))]
10162 "TARGET_SH2A && satisfies_constraint_Psz (operands[1]) && TARGET_BITOPS"
10165 bclr.b %W1,@(0,%t0)"
10166 [(set_attr "length" "4,4")])
10168 ;; Set a bit in a memory location.
10169 (define_insn "bset_m2a"
10170 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
10172 (ashift:QI (const_int 1)
10173 (match_operand:QI 1 "const_int_operand" "K03,K03"))
10175 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10178 bset.b %1,@(0,%t0)"
10179 [(set_attr "length" "4,4")])
10181 (define_insn "bsetmem_m2a"
10182 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
10183 (ior:QI (match_dup 0)
10184 (match_operand:QI 1 "const_int_operand" "Pso,Pso")))]
10185 "TARGET_SH2A && satisfies_constraint_Pso (operands[1]) && TARGET_BITOPS"
10188 bset.b %V1,@(0,%t0)"
10189 [(set_attr "length" "4,4")])
10191 ;;; Transfer the contents of the T bit to a specified bit of memory.
10192 (define_insn "bst_m2a"
10193 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,m")
10194 (if_then_else (eq (reg:SI T_REG) (const_int 0))
10196 (not:QI (ashift:QI (const_int 1)
10197 (match_operand:QI 1 "const_int_operand" "K03,K03")))
10200 (ashift:QI (const_int 1) (match_dup 1))
10202 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10206 [(set_attr "length" "4")])
10208 ;; Store a specified bit of memory in the T bit.
10209 (define_insn "bld_m2a"
10210 [(set (reg:SI T_REG)
10212 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,Sbv")
10214 (match_operand 1 "const_int_operand" "K03,K03")))]
10215 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10219 [(set_attr "length" "4,4")])
10221 ;; Store a specified bit of memory in the T bit.
10222 (define_insn "bldsign_m2a"
10223 [(set (reg:SI T_REG)
10225 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
10227 (match_operand 1 "const_int_operand" "K03,K03")))]
10228 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10232 [(set_attr "length" "4,4")])
10234 ;; Store a specified bit of the LSB 8 bits of a register in the T bit.
10235 (define_insn "bld<mode>_reg"
10236 [(set (reg:SI T_REG)
10237 (zero_extract:SI (match_operand:QIHISI 0 "arith_reg_operand" "r")
10239 (match_operand 1 "const_int_operand" "K03")))]
10240 "TARGET_SH2A && satisfies_constraint_K03 (operands[1])"
10243 ;; Take logical and of a specified bit of memory with the T bit and
10244 ;; store its result in the T bit.
10245 (define_insn "band_m2a"
10246 [(set (reg:SI T_REG)
10247 (and:SI (reg:SI T_REG)
10249 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
10251 (match_operand 1 "const_int_operand" "K03,K03"))))]
10252 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10255 band.b %1,@(0,%t0)"
10256 [(set_attr "length" "4,4")])
10258 (define_insn "bandreg_m2a"
10259 [(set (match_operand:SI 0 "register_operand" "=r,r")
10260 (and:SI (zero_extract:SI
10261 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
10263 (match_operand 2 "const_int_operand" "K03,K03"))
10264 (match_operand:SI 3 "register_operand" "r,r")))]
10265 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])"
10267 static const char* alt[] =
10269 "band.b %2,%1" "\n"
10272 "band.b %2,@(0,%t1)" "\n"
10275 return alt[which_alternative];
10277 [(set_attr "length" "6,6")])
10279 ;; Take logical or of a specified bit of memory with the T bit and
10280 ;; store its result in the T bit.
10281 (define_insn "bor_m2a"
10282 [(set (reg:SI T_REG)
10283 (ior:SI (reg:SI T_REG)
10285 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
10287 (match_operand 1 "const_int_operand" "K03,K03"))))]
10288 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10292 [(set_attr "length" "4,4")])
10294 (define_insn "borreg_m2a"
10295 [(set (match_operand:SI 0 "register_operand" "=r,r")
10296 (ior:SI (zero_extract:SI
10297 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
10299 (match_operand 2 "const_int_operand" "K03,K03"))
10300 (match_operand:SI 3 "register_operand" "=r,r")))]
10301 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])"
10303 static const char* alt[] =
10308 "bor.b %2,@(0,%t1)" "\n"
10311 return alt[which_alternative];
10313 [(set_attr "length" "6,6")])
10315 ;; Take exclusive or of a specified bit of memory with the T bit and
10316 ;; store its result in the T bit.
10317 (define_insn "bxor_m2a"
10318 [(set (reg:SI T_REG)
10319 (xor:SI (reg:SI T_REG)
10321 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
10323 (match_operand 1 "const_int_operand" "K03,K03"))))]
10324 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10327 bxor.b %1,@(0,%t0)"
10328 [(set_attr "length" "4,4")])
10330 (define_insn "bxorreg_m2a"
10331 [(set (match_operand:SI 0 "register_operand" "=r,r")
10332 (xor:SI (zero_extract:SI
10333 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
10335 (match_operand 2 "const_int_operand" "K03,K03"))
10336 (match_operand:SI 3 "register_operand" "=r,r")))]
10337 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])"
10339 static const char* alt[] =
10341 "bxor.b %2,%1" "\n"
10344 "bxor.b %2,@(0,%t1)" "\n"
10347 return alt[which_alternative];
10349 [(set_attr "length" "6,6")])
10351 ;; -------------------------------------------------------------------------
10353 ;; -------------------------------------------------------------------------
10354 ;; This matches cases where the bit in a memory location is set.
10356 [(set (match_operand:SI 0 "register_operand")
10357 (sign_extend:SI (match_operand:QI 1 "bitwise_memory_operand")))
10359 (ior:SI (match_dup 0)
10360 (match_operand:SI 2 "const_int_operand")))
10362 (match_operand 3 "arith_reg_operand"))]
10363 "TARGET_SH2A && TARGET_BITOPS
10364 && satisfies_constraint_Pso (operands[2])
10365 && REGNO (operands[0]) == REGNO (operands[3])"
10366 [(set (match_dup 1)
10367 (ior:QI (match_dup 1) (match_dup 2)))]
10370 ;; This matches cases where the bit in a memory location is cleared.
10372 [(set (match_operand:SI 0 "register_operand")
10373 (sign_extend:SI (match_operand:QI 1 "bitwise_memory_operand")))
10375 (and:SI (match_dup 0)
10376 (match_operand:SI 2 "const_int_operand")))
10378 (match_operand 3 "arith_reg_operand"))]
10379 "TARGET_SH2A && TARGET_BITOPS
10380 && satisfies_constraint_Psz (operands[2])
10381 && REGNO (operands[0]) == REGNO (operands[3])"
10382 [(set (match_dup 1)
10383 (and:QI (match_dup 1) (match_dup 2)))]
10386 ;; This matches cases where a stack pointer increment at the start of the
10387 ;; epilogue combines with a stack slot read loading the return value.
10389 [(set (match_operand:SI 0 "arith_reg_operand" "")
10390 (mem:SI (match_operand:SI 1 "arith_reg_operand" "")))
10391 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
10392 "TARGET_SH1 && REGNO (operands[1]) != REGNO (operands[0])"
10395 ;; See the comment on the dt combiner pattern above.
10397 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
10398 (plus:SI (match_dup 0)
10400 (set (reg:SI T_REG)
10401 (eq:SI (match_dup 0) (const_int 0)))]
10405 ;; The following peepholes fold load sequences for which reload was not
10406 ;; able to generate a displacement addressing move insn.
10407 ;; This can happen when reload has to transform a move insn
10408 ;; without displacement into one with displacement. Or when reload can't
10409 ;; fit a displacement into the insn's constraints. In the latter case, the
10410 ;; load destination reg remains at r0, which reload compensates by inserting
10411 ;; another mov insn.
10415 ;; mov.{b,w} @(r0,r15),r0
10418 ;; mov.{b,w} @(54,r15),r3
10421 [(set (match_operand:SI 0 "arith_reg_dest" "")
10422 (match_operand:SI 1 "const_int_operand" ""))
10423 (set (match_operand:SI 2 "arith_reg_dest" "")
10425 (mem:QI (plus:SI (match_dup 0)
10426 (match_operand:SI 3 "arith_reg_operand" "")))))
10427 (set (match_operand:QI 4 "arith_reg_dest" "")
10428 (match_operand:QI 5 "arith_reg_operand" ""))]
10430 && sh_legitimate_index_p (QImode, operands[1], true, true)
10431 && REGNO (operands[2]) == REGNO (operands[5])
10432 && peep2_reg_dead_p (3, operands[5])"
10433 [(set (match_dup 4) (mem:QI (plus:SI (match_dup 3) (match_dup 1))))]
10437 [(set (match_operand:SI 0 "arith_reg_dest" "")
10438 (match_operand:SI 1 "const_int_operand" ""))
10439 (set (match_operand:SI 2 "arith_reg_dest" "")
10441 (mem:HI (plus:SI (match_dup 0)
10442 (match_operand:SI 3 "arith_reg_operand" "")))))
10443 (set (match_operand:HI 4 "arith_reg_dest" "")
10444 (match_operand:HI 5 "arith_reg_operand" ""))]
10446 && sh_legitimate_index_p (HImode, operands[1], true, true)
10447 && REGNO (operands[2]) == REGNO (operands[5])
10448 && peep2_reg_dead_p (3, operands[5])"
10449 [(set (match_dup 4) (mem:HI (plus:SI (match_dup 3) (match_dup 1))))]
10454 ;; mov.{b,w} @(r0,r15),r1
10456 ;; mov.{b,w} @(54,r15),r1
10459 [(set (match_operand:SI 0 "arith_reg_dest" "")
10460 (match_operand:SI 1 "const_int_operand" ""))
10461 (set (match_operand:SI 2 "arith_reg_dest" "")
10463 (mem:QI (plus:SI (match_dup 0)
10464 (match_operand:SI 3 "arith_reg_operand" "")))))]
10466 && sh_legitimate_index_p (QImode, operands[1], true, true)
10467 && (peep2_reg_dead_p (2, operands[0])
10468 || REGNO (operands[0]) == REGNO (operands[2]))"
10469 [(set (match_dup 2)
10470 (sign_extend:SI (mem:QI (plus:SI (match_dup 3) (match_dup 1)))))]
10474 [(set (match_operand:SI 0 "arith_reg_dest" "")
10475 (match_operand:SI 1 "const_int_operand" ""))
10476 (set (match_operand:SI 2 "arith_reg_dest" "")
10478 (mem:HI (plus:SI (match_dup 0)
10479 (match_operand:SI 3 "arith_reg_operand" "")))))]
10481 && sh_legitimate_index_p (HImode, operands[1], true, true)
10482 && (peep2_reg_dead_p (2, operands[0])
10483 || REGNO (operands[0]) == REGNO (operands[2]))"
10484 [(set (match_dup 2)
10485 (sign_extend:SI (mem:HI (plus:SI (match_dup 3) (match_dup 1)))))]
10489 ;; mov.{b,w} @(r0,r15),r0
10492 ;; mov.{b,w} @(r0,r15),r3
10494 ;; This can happen when initially a displacement address is picked, where
10495 ;; the destination reg is fixed to r0, and then the address is transformed
10496 ;; into 'r0 + reg'.
10498 [(set (match_operand:SI 0 "arith_reg_dest" "")
10500 (mem:QI (plus:SI (match_operand:SI 1 "arith_reg_operand" "")
10501 (match_operand:SI 2 "arith_reg_operand" "")))))
10502 (set (match_operand:QI 3 "arith_reg_dest" "")
10503 (match_operand:QI 4 "arith_reg_operand" ""))]
10505 && REGNO (operands[0]) == REGNO (operands[4])
10506 && peep2_reg_dead_p (2, operands[0])"
10507 [(set (match_dup 3)
10508 (mem:QI (plus:SI (match_dup 1) (match_dup 2))))]
10512 [(set (match_operand:SI 0 "arith_reg_dest" "")
10514 (mem:HI (plus:SI (match_operand:SI 1 "arith_reg_operand" "")
10515 (match_operand:SI 2 "arith_reg_operand" "")))))
10516 (set (match_operand:HI 3 "arith_reg_dest" "")
10517 (match_operand:HI 4 "arith_reg_operand" ""))]
10519 && REGNO (operands[0]) == REGNO (operands[4])
10520 && peep2_reg_dead_p (2, operands[0])"
10521 [(set (match_dup 3)
10522 (mem:HI (plus:SI (match_dup 1) (match_dup 2))))]
10526 ;; mov b,c -> extu.bw a,c
10528 [(set (match_operand:SI 0 "arith_reg_dest")
10529 (zero_extend:SI (match_operand:QIHI 1 "arith_reg_operand")))
10530 (set (match_operand:SI 2 "arith_reg_dest")
10532 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
10533 [(set (match_dup 2) (zero_extend:SI (match_dup 1)))])
10536 ;; extu.bw r1,r1 -> extu.bw r0,r1
10538 [(set (match_operand 0 "arith_reg_dest")
10539 (match_operand 1 "arith_reg_operand"))
10540 (set (match_operand:SI 2 "arith_reg_dest")
10541 (zero_extend:SI (match_operand:QIHI 3 "arith_reg_operand")))]
10543 && REGNO (operands[0]) == REGNO (operands[3])
10544 && (REGNO (operands[0]) == REGNO (operands[2])
10545 || peep2_reg_dead_p (2, operands[0]))"
10546 [(set (match_dup 2) (zero_extend:SI (match_dup 1)))]
10548 operands[1] = gen_rtx_REG (<MODE>mode, REGNO (operands[1]));
10552 ;; mov b,a -> < nop >
10554 [(set (match_operand 0 "register_operand")
10555 (match_operand 1 "register_operand"))
10556 (set (match_operand 2 "register_operand")
10557 (match_operand 3 "register_operand"))]
10559 && REGNO (operands[0]) == REGNO (operands[3])
10560 && REGNO (operands[1]) == REGNO (operands[2])
10561 && peep2_reg_dead_p (2, operands[3])"
10565 ;; and r4,r1 -> mov r1,r0
10566 ;; mov r1,r0 and #3,r0
10567 (define_code_iterator ANDIORXOR [and ior xor])
10569 [(set (match_operand:SI 0 "register_operand")
10570 (match_operand:SI 1 "const_logical_operand"))
10571 (set (match_operand:SI 2) (ANDIORXOR:SI (match_dup 2) (match_dup 0)))
10572 (set (reg:SI R0_REG) (match_dup 2))]
10574 && peep2_reg_dead_p (3, operands[0]) && peep2_reg_dead_p (3, operands[2])"
10575 [(set (reg:SI R0_REG) (match_dup 2))
10576 (set (reg:SI R0_REG) (ANDIORXOR:SI (reg:SI R0_REG) (match_dup 1)))])
10578 ;; ... r2,r0 ... r2,r0
10579 ;; or r1,r0 -> or r0,r1
10582 (define_code_iterator ANDIORXORPLUS [and ior xor plus])
10584 [(set (match_operand:SI 0 "arith_reg_dest")
10585 (ANDIORXORPLUS:SI (match_dup 0) (match_operand:SI 1 "arith_reg_dest")))
10586 (set (match_dup 1) (match_dup 0))]
10587 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
10588 [(set (match_dup 1) (ANDIORXORPLUS:SI (match_dup 1) (match_dup 0)))])
10591 ;; add #-48,r0 -> add #-48,r12
10592 ;; mov.l r0,@(4,r10) mov.l r12,@(4,r10)
10595 [(set (match_operand:SI 0 "arith_reg_dest")
10596 (match_operand:SI 1 "arith_reg_dest"))
10597 (set (match_dup 0) (plus:SI (match_dup 0)
10598 (match_operand:SI 2 "const_int_operand")))
10599 (set (match_operand:SI 3 "general_movdst_operand") (match_dup 0))]
10601 && peep2_reg_dead_p (2, operands[1]) && peep2_reg_dead_p (3, operands[0])"
10604 emit_insn (gen_addsi3 (operands[1], operands[1], operands[2]));
10605 sh_peephole_emit_move_insn (operands[3], operands[1]);
10608 ;; mov.l @(r0,r9),r1
10609 ;; mov r1,r0 -> mov @(r0,r9),r0
10611 [(set (match_operand:SI 0 "arith_reg_dest")
10612 (match_operand:SI 1 "general_movsrc_operand"))
10613 (set (match_operand:SI 2 "arith_reg_dest")
10615 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
10618 sh_peephole_emit_move_insn (operands[2], operands[1]);
10622 [(set (match_operand:QIHI 0 "register_operand")
10623 (match_operand:QIHI 1 "movsrc_no_disp_mem_operand"))
10624 (set (match_operand:QIHI 2 "register_operand")
10626 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
10629 sh_peephole_emit_move_insn (operands[2], operands[1]);
10633 [(set (match_operand:SI 0 "arith_reg_dest")
10634 (sign_extend:SI (match_operand:QIHI 1 "movsrc_no_disp_mem_operand")))
10635 (set (match_operand:SI 2 "arith_reg_dest")
10637 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
10640 sh_check_add_incdec_notes (emit_insn (gen_extend<mode>si2 (operands[2],
10641 sh_remove_overlapping_post_inc (operands[2], operands[1]))));
10644 ;; mov.w @(18,r1),r0 (r0 = HImode)
10645 ;; mov r0,r1 (r0 = r1 = HImode) mov.w @(18,r1),r0
10646 ;; ... ..,r13 (r13 = SImode) -> ... ..,r13
10647 ;; tst r1,r13 tst r0,r13
10649 [(set (match_operand 0 "arith_reg_dest")
10650 (match_operand 1 "arith_reg_dest"))
10651 (set (match_operand:SI 2 "arith_reg_dest")
10652 (match_operand:SI 3))
10653 (set (reg:SI T_REG)
10654 (eq:SI (and:SI (match_operand:SI 4 "arith_reg_operand")
10655 (match_operand:SI 5 "arith_reg_operand"))
10658 && peep2_reg_dead_p (3, operands[0])
10659 && !reg_overlap_mentioned_p (operands[0], operands[3])
10660 && (REGNO (operands[0]) == REGNO (operands[4])
10661 || REGNO (operands[0]) == REGNO (operands[5]))
10662 && (REGNO (operands[2]) == REGNO (operands[4])
10663 || REGNO (operands[2]) == REGNO (operands[5]))"
10666 if (REGNO (operands[1]) == REGNO (operands[2]))
10667 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));
10669 // We don't know what the new set insn will be in detail. Just make sure
10670 // that it still can be recognized and the constraints are satisfied.
10671 rtx_insn* i = emit_insn (gen_rtx_SET (operands[2],
10672 sh_remove_overlapping_post_inc (operands[2], operands[3])));
10674 recog_data_d prev_recog_data = recog_data;
10675 bool i_invalid = insn_invalid_p (i, false);
10676 recog_data = prev_recog_data;
10681 sh_check_add_incdec_notes (i);
10683 emit_insn (gen_tstsi_t (operands[2],
10684 gen_rtx_REG (SImode, (REGNO (operands[1])))));
10687 ;; mov.w @(18,r1),r0 (r0 = HImode)
10688 ;; ... ..,r13 (r13 = SImode) mov.w @(18,r1),r0
10689 ;; mov r0,r1 (r0 = r1 = HImode) -> ... ..,r13
10690 ;; tst r1,r13 tst r0,r13
10692 [(set (match_operand:SI 2 "arith_reg_dest")
10693 (match_operand:SI 3))
10694 (set (match_operand 0 "arith_reg_dest")
10695 (match_operand 1 "arith_reg_operand"))
10696 (set (reg:SI T_REG)
10697 (eq:SI (and:SI (match_operand:SI 4 "arith_reg_operand")
10698 (match_operand:SI 5 "arith_reg_operand"))
10701 && peep2_reg_dead_p (3, operands[0])
10702 && !reg_overlap_mentioned_p (operands[0], operands[3])
10703 && (REGNO (operands[0]) == REGNO (operands[4])
10704 || REGNO (operands[0]) == REGNO (operands[5]))
10705 && (REGNO (operands[2]) == REGNO (operands[4])
10706 || REGNO (operands[2]) == REGNO (operands[5]))"
10709 // We don't know what the new set insn will be in detail. Just make sure
10710 // that it still can be recognized and the constraints are satisfied.
10711 rtx_insn* i = emit_insn (gen_rtx_SET (operands[2],
10712 sh_remove_overlapping_post_inc (operands[2], operands[3])));
10714 recog_data_d prev_recog_data = recog_data;
10715 bool i_invalid = insn_invalid_p (i, false);
10716 recog_data = prev_recog_data;
10721 sh_check_add_incdec_notes (i);
10723 emit_insn (gen_tstsi_t (operands[2],
10724 gen_rtx_REG (SImode, (REGNO (operands[1])))));
10727 ;; This is not a peephole, but it's here because it's actually supposed
10728 ;; to be one. It tries to convert a sequence such as
10729 ;; movt r2 -> movt r2
10730 ;; movt r13 mov r2,r13
10731 ;; This gives the schduler a bit more freedom to hoist a following
10732 ;; comparison insn. Moreover, it the reg-reg mov insn is MT group which has
10733 ;; better chances for parallel execution.
10734 ;; We can do this with a peephole2 pattern, but then the cprop_hardreg
10735 ;; pass will revert the change. See also PR 64331.
10736 ;; Thus do it manually in one of the split passes after register allocation.
10737 ;; Sometimes the cprop_hardreg pass might also eliminate the reg-reg copy.
10739 [(set (match_operand:SI 0 "arith_reg_dest")
10740 (match_operand:SI 1 "t_reg_operand"))]
10741 "TARGET_SH1 && reload_completed"
10742 [(set (match_dup 0) (match_dup 1))]
10744 rtx t_reg = get_t_reg_rtx ();
10746 for (rtx_insn* i = prev_nonnote_insn_bb (curr_insn); i != NULL;
10747 i = prev_nonnote_insn_bb (i))
10749 if (!INSN_P (i) || DEBUG_INSN_P (i))
10752 if (modified_in_p (t_reg, i) || BARRIER_P (i))
10755 if (sh_is_movt_insn (i))
10757 rtx r = sh_movt_set_dest (i);
10758 if (!modified_between_p (r, i, curr_insn))
10768 [(set (match_operand:SI 0 "register_operand" "=r")
10769 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
10770 (set (mem:SF (match_dup 0))
10771 (match_operand:SF 2 "general_movsrc_operand" ""))]
10772 "TARGET_SH1 && REGNO (operands[0]) == 0
10773 && ((REG_P (operands[2]) && REGNO (operands[2]) < 16)
10774 || (GET_CODE (operands[2]) == SUBREG
10775 && REGNO (SUBREG_REG (operands[2])) < 16))
10776 && reg_unused_after (operands[0], insn)"
10777 "mov.l %2,@(%0,%1)")
10780 [(set (match_operand:SI 0 "register_operand" "=r")
10781 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
10782 (set (match_operand:SF 2 "general_movdst_operand" "")
10784 (mem:SF (match_dup 0)))]
10785 "TARGET_SH1 && REGNO (operands[0]) == 0
10786 && ((REG_P (operands[2]) && REGNO (operands[2]) < 16)
10787 || (GET_CODE (operands[2]) == SUBREG
10788 && REGNO (SUBREG_REG (operands[2])) < 16))
10789 && reg_unused_after (operands[0], insn)"
10790 "mov.l @(%0,%1),%2")
10793 [(set (match_operand:SI 0 "register_operand" "=r")
10794 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
10795 (set (mem:SF (match_dup 0))
10796 (match_operand:SF 2 "general_movsrc_operand" ""))]
10797 "TARGET_SH2E && REGNO (operands[0]) == 0
10798 && ((REG_P (operands[2])
10799 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
10800 || (GET_CODE (operands[2]) == SUBREG
10801 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
10802 && reg_unused_after (operands[0], insn)"
10803 "fmov{.s|} %2,@(%0,%1)")
10806 [(set (match_operand:SI 0 "register_operand" "=r")
10807 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
10808 (set (match_operand:SF 2 "general_movdst_operand" "")
10810 (mem:SF (match_dup 0)))]
10811 "TARGET_SH2E && REGNO (operands[0]) == 0
10812 && ((REG_P (operands[2])
10813 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
10814 || (GET_CODE (operands[2]) == SUBREG
10815 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
10816 && reg_unused_after (operands[0], insn)"
10817 "fmov{.s|} @(%0,%1),%2")
10819 ;; Switch to a new stack with its address in sp_switch (a SYMBOL_REF).
10820 (define_insn "sp_switch_1"
10821 [(set (reg:SI SP_REG) (unspec_volatile [(match_operand:SI 0 "" "")]
10822 UNSPECV_SP_SWITCH_B))]
10825 return "mov.l r0,@-r15" "\n"
10826 " mov.l %0,r0" "\n"
10827 " mov.l @r0,r0" "\n"
10828 " mov.l r15,@-r0" "\n"
10831 [(set_attr "length" "10")])
10833 ;; Switch back to the original stack for interrupt functions with the
10834 ;; sp_switch attribute.
10835 (define_insn "sp_switch_2"
10836 [(unspec_volatile [(const_int 0)]
10837 UNSPECV_SP_SWITCH_E)]
10840 return "mov.l @r15,r15" "\n"
10843 [(set_attr "length" "4")])
10846 ;; In user mode, the "pref" instruction will raise a RADDERR exception
10847 ;; for accesses to [0x80000000,0xffffffff]. This makes it an unsuitable
10848 ;; implementation of __builtin_prefetch for VxWorks RTPs.
10849 (define_expand "prefetch"
10850 [(prefetch (match_operand 0 "address_operand" "")
10851 (match_operand:SI 1 "const_int_operand" "")
10852 (match_operand:SI 2 "const_int_operand" ""))]
10853 "(TARGET_SH2A || TARGET_SH3) && !TARGET_VXWORKS_RTP")
10855 (define_insn "*prefetch"
10856 [(prefetch (match_operand:SI 0 "register_operand" "r")
10857 (match_operand:SI 1 "const_int_operand" "n")
10858 (match_operand:SI 2 "const_int_operand" "n"))]
10859 "(TARGET_SH2A || TARGET_SH3) && ! TARGET_VXWORKS_RTP"
10861 [(set_attr "type" "other")])
10863 ;; -------------------------------------------------------------------------
10864 ;; Stack Protector Patterns
10865 ;; -------------------------------------------------------------------------
10867 (define_expand "stack_protect_set"
10868 [(set (match_operand 0 "memory_operand" "")
10869 (match_operand 1 "memory_operand" ""))]
10872 emit_insn (gen_stack_protect_set_si (operands[0], operands[1]));
10876 (define_insn "stack_protect_set_si"
10877 [(set (match_operand:SI 0 "memory_operand" "=m")
10878 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
10879 (set (match_scratch:SI 2 "=&r") (const_int 0))]
10882 return "mov.l %1,%2" "\n"
10883 " mov.l %2,%0" "\n"
10886 [(set_attr "type" "other")
10887 (set_attr "length" "6")])
10889 (define_expand "stack_protect_test"
10890 [(match_operand 0 "memory_operand" "")
10891 (match_operand 1 "memory_operand" "")
10892 (match_operand 2 "" "")]
10895 emit_insn (gen_stack_protect_test_si (operands[0], operands[1]));
10896 emit_jump_insn (gen_branch_true (operands[2]));
10900 (define_insn "stack_protect_test_si"
10901 [(set (reg:SI T_REG)
10902 (unspec:SI [(match_operand:SI 0 "memory_operand" "m")
10903 (match_operand:SI 1 "memory_operand" "m")]
10905 (set (match_scratch:SI 2 "=&r") (const_int 0))
10906 (set (match_scratch:SI 3 "=&r") (const_int 0))]
10909 return "mov.l %0,%2" "\n"
10910 " mov.l %1,%3" "\n"
10911 " cmp/eq %2,%3" "\n"
10915 [(set_attr "type" "other")
10916 (set_attr "length" "10")])
10918 ;; -------------------------------------------------------------------------
10919 ;; Atomic operations
10920 ;; -------------------------------------------------------------------------
10922 (include "sync.md")