gcc/config/sh/sh4-300.md

   1 ;; DFA scheduling description for ST40-300.
   2 ;; Copyright (C) 2004, 2006, 2007 Free Software Foundation, Inc.
   3
   4 ;; This file is part of GCC.
   5
   6 ;; GCC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 3, or (at your option)
   9 ;; any later version.
  10
  11 ;; GCC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.
  19
  20 ;; Load and store instructions save a cycle if they are aligned on a
  21 ;; four byte boundary.  Using a function unit for stores encourages
  22 ;; gcc to separate load and store instructions by one instruction,
  23 ;; which makes it more likely that the linker will be able to word
  24 ;; align them when relaxing.
  25
  26 ;; The following description models the ST40-300 pipeline using the DFA based
  27 ;; scheduler.
  28
  29 ;; Two automata are defined to reduce number of states
  30 ;; which a single large automaton will have. (Factoring)
  31
  32 (define_automaton "sh4_300_inst_pipeline,sh4_300_fpu_pipe")
  33
  34 ;; This unit is basically the decode unit of the processor.
  35 ;; Since SH4 is a dual issue machine,it is as if there are two
  36 ;; units so that any insn can be processed by either one
  37 ;; of the decoding unit.
  38
  39 (define_cpu_unit "sh4_300_pipe_01,sh4_300_pipe_02" "sh4_300_inst_pipeline")
  40
  41 ;; The floating point units.
  42
  43 (define_cpu_unit "sh4_300_fpt,sh4_300_fpu,sh4_300_fds" "sh4_300_fpu_pipe")
  44
  45 ;; integer multiplier unit
  46
  47 (define_cpu_unit "sh4_300_mul" "sh4_300_inst_pipeline")
  48
  49 ;; LS unit
  50
  51 (define_cpu_unit "sh4_300_ls" "sh4_300_inst_pipeline")
  52
  53 ;; The address calculator used for branch instructions.
  54 ;; This will be reserved after "issue" of branch instructions
  55 ;; and this is to make sure that no two branch instructions
  56 ;; can be issued in parallel.
  57
  58 (define_cpu_unit "sh4_300_br" "sh4_300_inst_pipeline")
  59
  60 ;; ----------------------------------------------------
  61 ;; This reservation is to simplify the dual issue description.
  62
  63 (define_reservation  "sh4_300_issue"  "sh4_300_pipe_01|sh4_300_pipe_02")
  64
  65 (define_reservation "all" "sh4_300_pipe_01+sh4_300_pipe_02")
  66
  67 ;;(define_insn_reservation "nil" 0 (eq_attr "type" "nil") "nothing")
  68
  69 ;; MOV RM,RN / MOV #imm8,RN / STS PR,RN
  70 (define_insn_reservation "sh4_300_mov" 0
  71   (and (eq_attr "pipe_model" "sh4_300")
  72        (eq_attr "type" "move,movi8,prget"))
  73   "sh4_300_issue")
  74
  75 ;; Fixed STS from MACL / MACH
  76 (define_insn_reservation "sh4_300_mac_gp" 0
  77   (and (eq_attr "pipe_model" "sh4_300")
  78        (eq_attr "type" "mac_gp"))
  79   "sh4_300_issue+sh4_300_mul")
  80
  81 ;; Fixed LDS to MACL / MACH
  82 (define_insn_reservation "sh4_300_gp_mac" 1
  83   (and (eq_attr "pipe_model" "sh4_300")
  84        (eq_attr "type" "gp_mac"))
  85   "sh4_300_issue+sh4_300_mul")
  86
  87 ;; Instructions without specific resource requirements with latency 1.
  88
  89 (define_insn_reservation "sh4_300_simple_arith" 1
  90   (and (eq_attr "pipe_model" "sh4_300")
  91        (eq_attr "type" "mt_group,arith,dyn_shift,prset"))
  92   "sh4_300_issue")
  93
  94 ;; Load and store instructions have no alignment peculiarities for the ST40-300,
  95 ;; but they use the load-store unit, which they share with the fmove type
  96 ;; insns (fldi[01]; fmov frn,frm; flds; fsts; fabs; fneg) .
  97 ;; Loads have a latency of three.
  98
  99 ;; Load Store instructions.
 100 (define_insn_reservation "sh4_300_load" 3
 101   (and (eq_attr "pipe_model" "sh4_300")
 102        (eq_attr "type" "load,pcload,load_si,pcload_si,pload"))
 103   "sh4_300_issue+sh4_300_ls")
 104
 105 (define_insn_reservation "sh4_300_mac_load" 3
 106   (and (eq_attr "pipe_model" "sh4_300")
 107        (eq_attr "type" "mem_mac"))
 108   "sh4_300_issue+sh4_300_ls+sh4_300_mul")
 109
 110 (define_insn_reservation "sh4_300_fload" 4
 111   (and (eq_attr "pipe_model" "sh4_300")
 112        (eq_attr "type" "fload,pcfload"))
 113   "sh4_300_issue+sh4_300_ls+sh4_300_fpt")
 114
 115 ;; sh_adjust_cost describes the reduced latency of the feeding insns of a store.
 116 ;; The latency of an auto-increment register is 1; the latency of the memory
 117 ;; output is not actually considered here anyway.
 118 (define_insn_reservation "sh4_300_store" 1
 119   (and (eq_attr "pipe_model" "sh4_300")
 120        (eq_attr "type" "store,pstore"))
 121   "sh4_300_issue+sh4_300_ls")
 122
 123 (define_insn_reservation "sh4_300_fstore" 1
 124   (and (eq_attr "pipe_model" "sh4_300")
 125        (eq_attr "type" "fstore"))
 126   "sh4_300_issue+sh4_300_ls+sh4_300_fpt")
 127
 128 ;; Fixed STS.L from MACL / MACH
 129 (define_insn_reservation "sh4_300_mac_store" 1
 130   (and (eq_attr "pipe_model" "sh4_300")
 131        (eq_attr "type" "mac_mem"))
 132   "sh4_300_issue+sh4_300_mul+sh4_300_ls")
 133
 134 (define_insn_reservation "sh4_300_gp_fpul" 2
 135   (and (eq_attr "pipe_model" "sh4_300")
 136        (eq_attr "type" "gp_fpul"))
 137   "sh4_300_issue+sh4_300_fpt")
 138
 139 (define_insn_reservation "sh4_300_fpul_gp" 1
 140   (and (eq_attr "pipe_model" "sh4_300")
 141        (eq_attr "type" "fpul_gp"))
 142   "sh4_300_issue+sh4_300_fpt")
 143
 144 ;; Branch (BF,BF/S,BT,BT/S,BRA)
 145 ;; Branch Far (JMP,RTS,BRAF)
 146 ;; Group:       BR
 147 ;; When displacement is 0 for BF / BT, we have effectively conditional
 148 ;; execution of one instruction, without pipeline disruption.
 149 ;; Otherwise, the latency depends on prediction success.
 150 ;; We can't really do much with the latency, even if we could express it,
 151 ;; but the pairing restrictions are useful to take into account.
 152 ;; ??? If the branch is likely, and not paired with a preceding insn,
 153 ;; or likely and likely not predicted, we might want to fill the delay slot.
 154 ;; However, there appears to be no machinery to make the compiler
 155 ;; recognize these scenarios.
 156
 157 (define_insn_reservation "sh4_300_branch"  1
 158   (and (eq_attr "pipe_model" "sh4_300")
 159        (eq_attr "type" "cbranch,jump,return,jump_ind"))
 160   "sh4_300_issue+sh4_300_br")
 161
 162 ;; RTE
 163 (define_insn_reservation "sh4_300_return_from_exp" 9
 164   (and (eq_attr "pipe_model" "sh4_300")
 165        (eq_attr "type" "rte"))
 166   "sh4_300_pipe_01+sh4_300_pipe_02*9")
 167
 168 ;; OCBP, OCBWB
 169 ;; Group:       CO
 170 ;; Latency:     1-5
 171 ;; Issue Rate:  1
 172
 173 ;; cwb is used for the sequence ocbwb @%0; extu.w %0,%2; or %1,%2; mov.l %0,@%2
 174 ;; This description is likely inexact, but this pattern should not actually
 175 ;; appear when compiling for sh4-300; we should use isbi instead.
 176 ;; If a -mtune option is added later, we should use the icache array
 177 ;; dispatch method instead.
 178 (define_insn_reservation "sh4_300_ocbwb"  3
 179   (and (eq_attr "pipe_model" "sh4_300")
 180        (eq_attr "type" "cwb"))
 181   "all*3")
 182
 183 ;; JSR,BSR,BSRF
 184 ;; Calls have a mandatory delay slot, which we'd like to fill with an insn
 185 ;; that can be paired with the call itself.
 186 ;; Scheduling runs before reorg, so we approximate this by saying that we
 187 ;; want the call to be paired with a preceding insn.
 188 ;; In most cases, the insn that loads the address of the call should have
 189 ;; a nonzero latency (mov rn,rm doesn't make sense since we could use rn
 190 ;; for the address then).  Thus, a preceding insn that can be paired with
 191 ;; a call should be eligible for the delay slot.
 192 ;;
 193 ;; calls introduce a longisch delay that is likely to flush the pipelines
 194 ;; of the caller's instructions.  Ordinary functions tend to end with a
 195 ;; load to restore a register (in the delay slot of rts), while sfuncs
 196 ;; tend to end with an EX or MT insn.  But that is not actually relevant,
 197 ;; since there are no instructions that contend for memory access early.
 198 ;; We could, of course, provide exact scheduling information for specific
 199 ;; sfuncs, if that should prove useful.
 200
 201 (define_insn_reservation "sh4_300_call" 16
 202   (and (eq_attr "pipe_model" "sh4_300")
 203        (eq_attr "type" "call,sfunc"))
 204   "sh4_300_issue+sh4_300_br,all*15")
 205
 206 ;; FMOV.S / FMOV.D
 207 (define_insn_reservation "sh4_300_fmov" 1
 208   (and (eq_attr "pipe_model" "sh4_300")
 209        (eq_attr "type" "fmove"))
 210   "sh4_300_issue+sh4_300_fpt")
 211
 212 ;; LDS to FPSCR
 213 (define_insn_reservation "sh4_300_fpscr_load" 8
 214   (and (eq_attr "pipe_model" "sh4_300")
 215        (eq_attr "type" "gp_fpscr"))
 216   "sh4_300_issue+sh4_300_fpu+sh4_300_fpt")
 217
 218 ;; LDS.L to FPSCR
 219 (define_insn_reservation "sh4_300_fpscr_load_mem" 8
 220   (and (eq_attr "pipe_model" "sh4_300")
 221        (eq_attr "type"  "mem_fpscr"))
 222   "sh4_300_issue+sh4_300_fpu+sh4_300_fpt+sh4_300_ls")
 223
 224 \f
 225 ;; Fixed point multiplication (DMULS.L DMULU.L MUL.L MULS.W,MULU.W)
 226 (define_insn_reservation "multi" 2
 227   (and (eq_attr "pipe_model" "sh4_300")
 228        (eq_attr "type" "smpy,dmpy"))
 229   "sh4_300_issue+sh4_300_mul")
 230
 231 ;; FPCHG, FRCHG, FSCHG
 232 (define_insn_reservation "fpscr_toggle"  1
 233   (and (eq_attr "pipe_model" "sh4_300")
 234        (eq_attr "type" "fpscr_toggle"))
 235   "sh4_300_issue+sh4_300_fpu+sh4_300_fpt")
 236
 237 ;; FCMP/EQ, FCMP/GT
 238 (define_insn_reservation "fp_cmp"  3
 239   (and (eq_attr "pipe_model" "sh4_300")
 240        (eq_attr "type" "fp_cmp,dfp_cmp"))
 241   "sh4_300_issue+sh4_300_fpu")
 242
 243 ;; Single precision floating point (FADD,FLOAT,FMAC,FMUL,FSUB,FTRC)
 244 ;; Double-precision floating-point (FADD,FCNVDS,FCNVSD,FLOAT,FSUB,FTRC)
 245 (define_insn_reservation "fp_arith"  6
 246   (and (eq_attr "pipe_model" "sh4_300")
 247        (eq_attr "type" "fp,ftrc_s,dfp_arith,dfp_conv"))
 248   "sh4_300_issue+sh4_300_fpu")
 249
 250 ;; Single Precision FDIV/SQRT
 251 (define_insn_reservation "fp_div" 19
 252   (and (eq_attr "pipe_model" "sh4_300")
 253        (eq_attr "type" "fdiv"))
 254   "sh4_300_issue+sh4_300_fpu+sh4_300_fds,sh4_300_fds*15")
 255
 256 ;; Double-precision floating-point FMUL
 257 (define_insn_reservation "dfp_mul" 9
 258   (and (eq_attr "pipe_model" "sh4_300")
 259        (eq_attr "type" "dfp_mul"))
 260   "sh4_300_issue+sh4_300_fpu,sh4_300_fpu*3")
 261
 262 ;; Double precision FDIV/SQRT
 263 (define_insn_reservation "dp_div" 35
 264   (and (eq_attr "pipe_model" "sh4_300")
 265        (eq_attr "type" "dfdiv"))
 266   "sh4_300_issue+sh4_300_fpu+sh4_300_fds,sh4_300_fds*31")
 267
 268
 269 ;; ??? We don't really want these for sh4-300.
 270 ;; this pattern itself is likely to finish in 3 cycles, but also
 271 ;; to disrupt branch prediction for taken branches for the following
 272 ;; condbranch.
 273 (define_insn_reservation "sh4_300_arith3" 5
 274   (and (eq_attr "pipe_model" "sh4_300")
 275        (eq_attr "type" "arith3"))
 276   "sh4_300_issue,all*4")
 277
 278 ;; arith3b insns without brach redirection make use of the 0-offset 0-latency
 279 ;; branch feature, and thus schedule the same no matter if the branch is taken
 280 ;; or not.  If the branch is redirected, the taken branch might take longer,
 281 ;; but then, we don't have to take the next branch.
 282 ;; ??? should we suppress branch redirection for sh4-300 to improve branch
 283 ;; target hit rates?
 284 (define_insn_reservation "arith3b" 2
 285   (and (eq_attr "pipe_model" "sh4")
 286        (eq_attr "type" "arith3"))
 287   "issue,all")