1 /* Subroutines for insn-output.c for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
47 #include "target-def.h"
49 /* 1 if the caller has placed an "unimp" insn immediately after the call.
50 This is used in v8 code when calling a function that returns a structure.
51 v9 doesn't have this. Be careful to have this test be the same as that
54 #define SKIP_CALLERS_UNIMP_P \
55 (!TARGET_ARCH64 && current_function_returns_struct \
56 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
57 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
60 /* Global variables for machine-dependent things. */
62 /* Size of frame. Need to know this to emit return insns from leaf procedures.
63 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
64 reload pass. This is important as the value is later used in insn
65 scheduling (to see what can go in a delay slot).
66 APPARENT_FSIZE is the size of the stack less the register save area and less
67 the outgoing argument area. It is used when saving call preserved regs. */
68 static int apparent_fsize
;
69 static int actual_fsize
;
71 /* Number of live general or floating point registers needed to be
72 saved (as 4-byte quantities). */
73 static int num_gfregs
;
75 /* Save the operands last given to a compare for use when we
76 generate a scc or bcc insn. */
77 rtx sparc_compare_op0
, sparc_compare_op1
;
79 /* Coordinate with the md file wrt special insns created by
80 sparc_nonflat_function_epilogue. */
81 bool sparc_emitting_epilogue
;
83 /* Vector to say how input registers are mapped to output registers.
84 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
85 eliminate it. You must use -fomit-frame-pointer to get that. */
86 char leaf_reg_remap
[] =
87 { 0, 1, 2, 3, 4, 5, 6, 7,
88 -1, -1, -1, -1, -1, -1, 14, -1,
89 -1, -1, -1, -1, -1, -1, -1, -1,
90 8, 9, 10, 11, 12, 13, -1, 15,
92 32, 33, 34, 35, 36, 37, 38, 39,
93 40, 41, 42, 43, 44, 45, 46, 47,
94 48, 49, 50, 51, 52, 53, 54, 55,
95 56, 57, 58, 59, 60, 61, 62, 63,
96 64, 65, 66, 67, 68, 69, 70, 71,
97 72, 73, 74, 75, 76, 77, 78, 79,
98 80, 81, 82, 83, 84, 85, 86, 87,
99 88, 89, 90, 91, 92, 93, 94, 95,
100 96, 97, 98, 99, 100};
102 /* Vector, indexed by hard register number, which contains 1
103 for a register that is allowable in a candidate for leaf
104 function treatment. */
105 char sparc_leaf_regs
[] =
106 { 1, 1, 1, 1, 1, 1, 1, 1,
107 0, 0, 0, 0, 0, 0, 1, 0,
108 0, 0, 0, 0, 0, 0, 0, 0,
109 1, 1, 1, 1, 1, 1, 0, 1,
110 1, 1, 1, 1, 1, 1, 1, 1,
111 1, 1, 1, 1, 1, 1, 1, 1,
112 1, 1, 1, 1, 1, 1, 1, 1,
113 1, 1, 1, 1, 1, 1, 1, 1,
114 1, 1, 1, 1, 1, 1, 1, 1,
115 1, 1, 1, 1, 1, 1, 1, 1,
116 1, 1, 1, 1, 1, 1, 1, 1,
117 1, 1, 1, 1, 1, 1, 1, 1,
120 /* Name of where we pretend to think the frame pointer points.
121 Normally, this is "%fp", but if we are in a leaf procedure,
122 this is "%sp+something". We record "something" separately as it may be
123 too big for reg+constant addressing. */
125 static const char *frame_base_name
;
126 static int frame_base_offset
;
128 static void sparc_init_modes
PARAMS ((void));
129 static int save_regs
PARAMS ((FILE *, int, int, const char *,
131 static int restore_regs
PARAMS ((FILE *, int, int, const char *, int, int));
132 static void build_big_number
PARAMS ((FILE *, int, const char *));
133 static int function_arg_slotno
PARAMS ((const CUMULATIVE_ARGS
*,
134 enum machine_mode
, tree
, int, int,
137 static int supersparc_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
138 static int hypersparc_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
140 static void sparc_output_addr_vec
PARAMS ((rtx
));
141 static void sparc_output_addr_diff_vec
PARAMS ((rtx
));
142 static void sparc_output_deferred_case_vectors
PARAMS ((void));
143 static void sparc_add_gc_roots
PARAMS ((void));
144 static int check_return_regs
PARAMS ((rtx
));
145 static int epilogue_renumber
PARAMS ((rtx
*, int));
146 static bool sparc_assemble_integer
PARAMS ((rtx
, unsigned int, int));
147 static int set_extends
PARAMS ((rtx
));
148 static void output_restore_regs
PARAMS ((FILE *, int));
149 static void sparc_output_function_prologue
PARAMS ((FILE *, HOST_WIDE_INT
));
150 static void sparc_output_function_epilogue
PARAMS ((FILE *, HOST_WIDE_INT
));
151 static void sparc_flat_function_epilogue
PARAMS ((FILE *, HOST_WIDE_INT
));
152 static void sparc_flat_function_prologue
PARAMS ((FILE *, HOST_WIDE_INT
));
153 static void sparc_nonflat_function_epilogue
PARAMS ((FILE *, HOST_WIDE_INT
,
155 static void sparc_nonflat_function_prologue
PARAMS ((FILE *, HOST_WIDE_INT
,
157 #ifdef OBJECT_FORMAT_ELF
158 static void sparc_elf_asm_named_section
PARAMS ((const char *, unsigned int));
160 static void sparc_aout_select_section
PARAMS ((tree
, int,
161 unsigned HOST_WIDE_INT
))
163 static void sparc_aout_select_rtx_section
PARAMS ((enum machine_mode
, rtx
,
164 unsigned HOST_WIDE_INT
))
167 static int sparc_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
168 static int sparc_issue_rate
PARAMS ((void));
169 static void sparc_sched_init
PARAMS ((FILE *, int, int));
170 static int sparc_use_dfa_pipeline_interface
PARAMS ((void));
171 static int sparc_use_sched_lookahead
PARAMS ((void));
173 static void emit_soft_tfmode_libcall
PARAMS ((const char *, int, rtx
*));
174 static void emit_soft_tfmode_binop
PARAMS ((enum rtx_code
, rtx
*));
175 static void emit_soft_tfmode_unop
PARAMS ((enum rtx_code
, rtx
*));
176 static void emit_soft_tfmode_cvt
PARAMS ((enum rtx_code
, rtx
*));
177 static void emit_hard_tfmode_operation
PARAMS ((enum rtx_code
, rtx
*));
179 /* Option handling. */
181 /* Code model option as passed by user. */
182 const char *sparc_cmodel_string
;
184 enum cmodel sparc_cmodel
;
186 char sparc_hard_reg_printed
[8];
188 struct sparc_cpu_select sparc_select
[] =
190 /* switch name, tune arch */
191 { (char *)0, "default", 1, 1 },
192 { (char *)0, "-mcpu=", 1, 1 },
193 { (char *)0, "-mtune=", 1, 0 },
197 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
198 enum processor_type sparc_cpu
;
200 /* Initialize the GCC target structure. */
202 /* The sparc default is to use .half rather than .short for aligned
203 HI objects. Use .word instead of .long on non-ELF systems. */
204 #undef TARGET_ASM_ALIGNED_HI_OP
205 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
206 #ifndef OBJECT_FORMAT_ELF
207 #undef TARGET_ASM_ALIGNED_SI_OP
208 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
211 #undef TARGET_ASM_UNALIGNED_HI_OP
212 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
213 #undef TARGET_ASM_UNALIGNED_SI_OP
214 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
215 #undef TARGET_ASM_UNALIGNED_DI_OP
216 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
218 /* The target hook has to handle DI-mode values. */
219 #undef TARGET_ASM_INTEGER
220 #define TARGET_ASM_INTEGER sparc_assemble_integer
222 #undef TARGET_ASM_FUNCTION_PROLOGUE
223 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_output_function_prologue
224 #undef TARGET_ASM_FUNCTION_EPILOGUE
225 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_output_function_epilogue
227 #undef TARGET_SCHED_ADJUST_COST
228 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
229 #undef TARGET_SCHED_ISSUE_RATE
230 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
231 #undef TARGET_SCHED_INIT
232 #define TARGET_SCHED_INIT sparc_sched_init
233 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
234 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface
235 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
236 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
238 struct gcc_target targetm
= TARGET_INITIALIZER
;
240 /* Validate and override various options, and do some machine dependent
244 sparc_override_options ()
246 static struct code_model
{
247 const char *const name
;
249 } const cmodels
[] = {
251 { "medlow", CM_MEDLOW
},
252 { "medmid", CM_MEDMID
},
253 { "medany", CM_MEDANY
},
254 { "embmedany", CM_EMBMEDANY
},
257 const struct code_model
*cmodel
;
258 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
259 static struct cpu_default
{
261 const char *const name
;
262 } const cpu_default
[] = {
263 /* There must be one entry here for each TARGET_CPU value. */
264 { TARGET_CPU_sparc
, "cypress" },
265 { TARGET_CPU_sparclet
, "tsc701" },
266 { TARGET_CPU_sparclite
, "f930" },
267 { TARGET_CPU_v8
, "v8" },
268 { TARGET_CPU_hypersparc
, "hypersparc" },
269 { TARGET_CPU_sparclite86x
, "sparclite86x" },
270 { TARGET_CPU_supersparc
, "supersparc" },
271 { TARGET_CPU_v9
, "v9" },
272 { TARGET_CPU_ultrasparc
, "ultrasparc" },
273 { TARGET_CPU_ultrasparc3
, "ultrasparc3" },
276 const struct cpu_default
*def
;
277 /* Table of values for -m{cpu,tune}=. */
278 static struct cpu_table
{
279 const char *const name
;
280 const enum processor_type processor
;
283 } const cpu_table
[] = {
284 { "v7", PROCESSOR_V7
, MASK_ISA
, 0 },
285 { "cypress", PROCESSOR_CYPRESS
, MASK_ISA
, 0 },
286 { "v8", PROCESSOR_V8
, MASK_ISA
, MASK_V8
},
287 /* TI TMS390Z55 supersparc */
288 { "supersparc", PROCESSOR_SUPERSPARC
, MASK_ISA
, MASK_V8
},
289 { "sparclite", PROCESSOR_SPARCLITE
, MASK_ISA
, MASK_SPARCLITE
},
290 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
291 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
292 { "f930", PROCESSOR_F930
, MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
293 { "f934", PROCESSOR_F934
, MASK_ISA
, MASK_SPARCLITE
|MASK_FPU
},
294 { "hypersparc", PROCESSOR_HYPERSPARC
, MASK_ISA
, MASK_V8
|MASK_FPU
},
295 { "sparclite86x", PROCESSOR_SPARCLITE86X
, MASK_ISA
|MASK_FPU
,
297 { "sparclet", PROCESSOR_SPARCLET
, MASK_ISA
, MASK_SPARCLET
},
299 { "tsc701", PROCESSOR_TSC701
, MASK_ISA
, MASK_SPARCLET
},
300 { "v9", PROCESSOR_V9
, MASK_ISA
, MASK_V9
},
301 /* TI ultrasparc I, II, IIi */
302 { "ultrasparc", PROCESSOR_ULTRASPARC
, MASK_ISA
, MASK_V9
303 /* Although insns using %y are deprecated, it is a clear win on current
305 |MASK_DEPRECATED_V8_INSNS
},
306 /* TI ultrasparc III */
307 /* ??? Check if %y issue still holds true in ultra3. */
308 { "ultrasparc3", PROCESSOR_ULTRASPARC3
, MASK_ISA
, MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
311 const struct cpu_table
*cpu
;
312 const struct sparc_cpu_select
*sel
;
315 #ifndef SPARC_BI_ARCH
316 /* Check for unsupported architecture size. */
317 if (! TARGET_64BIT
!= DEFAULT_ARCH32_P
)
318 error ("%s is not supported by this configuration",
319 DEFAULT_ARCH32_P
? "-m64" : "-m32");
322 /* We force all 64bit archs to use 128 bit long double */
323 if (TARGET_64BIT
&& ! TARGET_LONG_DOUBLE_128
)
325 error ("-mlong-double-64 not allowed with -m64");
326 target_flags
|= MASK_LONG_DOUBLE_128
;
329 /* Code model selection. */
330 sparc_cmodel
= SPARC_DEFAULT_CMODEL
;
334 sparc_cmodel
= CM_32
;
337 if (sparc_cmodel_string
!= NULL
)
341 for (cmodel
= &cmodels
[0]; cmodel
->name
; cmodel
++)
342 if (strcmp (sparc_cmodel_string
, cmodel
->name
) == 0)
344 if (cmodel
->name
== NULL
)
345 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string
);
347 sparc_cmodel
= cmodel
->value
;
350 error ("-mcmodel= is not supported on 32 bit systems");
353 fpu
= TARGET_FPU
; /* save current -mfpu status */
355 /* Set the default CPU. */
356 for (def
= &cpu_default
[0]; def
->name
; ++def
)
357 if (def
->cpu
== TARGET_CPU_DEFAULT
)
361 sparc_select
[0].string
= def
->name
;
363 for (sel
= &sparc_select
[0]; sel
->name
; ++sel
)
367 for (cpu
= &cpu_table
[0]; cpu
->name
; ++cpu
)
368 if (! strcmp (sel
->string
, cpu
->name
))
371 sparc_cpu
= cpu
->processor
;
375 target_flags
&= ~cpu
->disable
;
376 target_flags
|= cpu
->enable
;
382 error ("bad value (%s) for %s switch", sel
->string
, sel
->name
);
386 /* If -mfpu or -mno-fpu was explicitly used, don't override with
387 the processor default. Clear MASK_FPU_SET to avoid confusing
388 the reverse mapping from switch values to names. */
391 target_flags
= (target_flags
& ~MASK_FPU
) | fpu
;
392 target_flags
&= ~MASK_FPU_SET
;
395 /* Don't allow -mvis if FPU is disabled. */
397 target_flags
&= ~MASK_VIS
;
399 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
401 -m64 also implies v9. */
402 if (TARGET_VIS
|| TARGET_ARCH64
)
404 target_flags
|= MASK_V9
;
405 target_flags
&= ~(MASK_V8
| MASK_SPARCLET
| MASK_SPARCLITE
);
408 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
409 if (TARGET_V9
&& TARGET_ARCH32
)
410 target_flags
|= MASK_DEPRECATED_V8_INSNS
;
412 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
413 if (! TARGET_V9
|| TARGET_ARCH64
)
414 target_flags
&= ~MASK_V8PLUS
;
416 /* Don't use stack biasing in 32 bit mode. */
418 target_flags
&= ~MASK_STACK_BIAS
;
420 /* Supply a default value for align_functions. */
421 if (align_functions
== 0
422 && (sparc_cpu
== PROCESSOR_ULTRASPARC
423 || sparc_cpu
== PROCESSOR_ULTRASPARC3
))
424 align_functions
= 32;
426 /* Validate PCC_STRUCT_RETURN. */
427 if (flag_pcc_struct_return
== DEFAULT_PCC_STRUCT_RETURN
)
428 flag_pcc_struct_return
= (TARGET_ARCH64
? 0 : 1);
430 /* Only use .uaxword when compiling for a 64-bit target. */
432 targetm
.asm_out
.unaligned_op
.di
= NULL
;
434 /* Do various machine dependent initializations. */
437 /* Register global variables with the garbage collector. */
438 sparc_add_gc_roots ();
441 /* Miscellaneous utilities. */
443 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
444 or branch on register contents instructions. */
450 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
451 || code
== LE
|| code
== GT
);
455 /* Operand constraints. */
457 /* Return non-zero only if OP is a register of mode MODE,
461 reg_or_0_operand (op
, mode
)
463 enum machine_mode mode
;
465 if (register_operand (op
, mode
))
467 if (op
== const0_rtx
)
469 if (GET_MODE (op
) == VOIDmode
&& GET_CODE (op
) == CONST_DOUBLE
470 && CONST_DOUBLE_HIGH (op
) == 0
471 && CONST_DOUBLE_LOW (op
) == 0)
473 if (fp_zero_operand (op
, mode
))
478 /* Return non-zero only if OP is const1_rtx. */
481 const1_operand (op
, mode
)
483 enum machine_mode mode ATTRIBUTE_UNUSED
;
485 return op
== const1_rtx
;
488 /* Nonzero if OP is a floating point value with value 0.0. */
491 fp_zero_operand (op
, mode
)
493 enum machine_mode mode
;
495 if (GET_MODE_CLASS (GET_MODE (op
)) != MODE_FLOAT
)
497 return op
== CONST0_RTX (mode
);
500 /* Nonzero if OP is a register operand in floating point register. */
503 fp_register_operand (op
, mode
)
505 enum machine_mode mode
;
507 if (! register_operand (op
, mode
))
509 if (GET_CODE (op
) == SUBREG
)
510 op
= SUBREG_REG (op
);
511 return GET_CODE (op
) == REG
&& SPARC_FP_REG_P (REGNO (op
));
514 /* Nonzero if OP is a floating point constant which can
515 be loaded into an integer register using a single
516 sethi instruction. */
522 if (GET_CODE (op
) == CONST_DOUBLE
)
527 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
528 if (REAL_VALUES_EQUAL (r
, dconst0
) &&
529 ! REAL_VALUE_MINUS_ZERO (r
))
531 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
532 if (SPARC_SETHI_P (i
))
539 /* Nonzero if OP is a floating point constant which can
540 be loaded into an integer register using a single
547 if (GET_CODE (op
) == CONST_DOUBLE
)
552 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
553 if (REAL_VALUES_EQUAL (r
, dconst0
) &&
554 ! REAL_VALUE_MINUS_ZERO (r
))
556 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
557 if (SPARC_SIMM13_P (i
))
564 /* Nonzero if OP is a floating point constant which can
565 be loaded into an integer register using a high/losum
566 instruction sequence. */
572 /* The constraints calling this should only be in
573 SFmode move insns, so any constant which cannot
574 be moved using a single insn will do. */
575 if (GET_CODE (op
) == CONST_DOUBLE
)
580 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
581 if (REAL_VALUES_EQUAL (r
, dconst0
) &&
582 ! REAL_VALUE_MINUS_ZERO (r
))
584 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
585 if (! SPARC_SETHI_P (i
)
586 && ! SPARC_SIMM13_P (i
))
593 /* Nonzero if OP is an integer register. */
596 intreg_operand (op
, mode
)
598 enum machine_mode mode ATTRIBUTE_UNUSED
;
600 return (register_operand (op
, SImode
)
601 || (TARGET_ARCH64
&& register_operand (op
, DImode
)));
604 /* Nonzero if OP is a floating point condition code register. */
607 fcc_reg_operand (op
, mode
)
609 enum machine_mode mode
;
611 /* This can happen when recog is called from combine. Op may be a MEM.
612 Fail instead of calling abort in this case. */
613 if (GET_CODE (op
) != REG
)
616 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
619 && (GET_MODE (op
) != CCFPmode
&& GET_MODE (op
) != CCFPEmode
))
622 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
623 if (reg_renumber
== 0)
624 return REGNO (op
) >= FIRST_PSEUDO_REGISTER
;
625 return REGNO_OK_FOR_CCFP_P (REGNO (op
));
627 return (unsigned) REGNO (op
) - SPARC_FIRST_V9_FCC_REG
< 4;
631 /* Nonzero if OP is a floating point condition code fcc0 register. */
634 fcc0_reg_operand (op
, mode
)
636 enum machine_mode mode
;
638 /* This can happen when recog is called from combine. Op may be a MEM.
639 Fail instead of calling abort in this case. */
640 if (GET_CODE (op
) != REG
)
643 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
646 && (GET_MODE (op
) != CCFPmode
&& GET_MODE (op
) != CCFPEmode
))
649 return REGNO (op
) == SPARC_FCC_REG
;
652 /* Nonzero if OP is an integer or floating point condition code register. */
655 icc_or_fcc_reg_operand (op
, mode
)
657 enum machine_mode mode
;
659 if (GET_CODE (op
) == REG
&& REGNO (op
) == SPARC_ICC_REG
)
661 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
664 && GET_MODE (op
) != CCmode
&& GET_MODE (op
) != CCXmode
)
669 return fcc_reg_operand (op
, mode
);
672 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
674 restore_operand (op
, mode
)
676 enum machine_mode mode
;
678 return (GET_CODE (op
) == REG
&& GET_MODE (op
) == mode
679 && (REGNO (op
) < 8 || (REGNO (op
) >= 24 && REGNO (op
) < 32)));
682 /* Call insn on SPARC can take a PC-relative constant address, or any regular
686 call_operand (op
, mode
)
688 enum machine_mode mode
;
690 if (GET_CODE (op
) != MEM
)
693 return (symbolic_operand (op
, mode
) || memory_address_p (Pmode
, op
));
697 call_operand_address (op
, mode
)
699 enum machine_mode mode
;
701 return (symbolic_operand (op
, mode
) || memory_address_p (Pmode
, op
));
704 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
705 reference and a constant. */
708 symbolic_operand (op
, mode
)
710 enum machine_mode mode
;
712 enum machine_mode omode
= GET_MODE (op
);
714 if (omode
!= mode
&& omode
!= VOIDmode
&& mode
!= VOIDmode
)
717 switch (GET_CODE (op
))
725 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
726 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
727 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
734 /* Return truth value of statement that OP is a symbolic memory
735 operand of mode MODE. */
738 symbolic_memory_operand (op
, mode
)
740 enum machine_mode mode ATTRIBUTE_UNUSED
;
742 if (GET_CODE (op
) == SUBREG
)
743 op
= SUBREG_REG (op
);
744 if (GET_CODE (op
) != MEM
)
747 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
748 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
751 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
754 label_ref_operand (op
, mode
)
756 enum machine_mode mode
;
758 if (GET_CODE (op
) != LABEL_REF
)
760 if (GET_MODE (op
) != mode
)
765 /* Return 1 if the operand is an argument used in generating pic references
766 in either the medium/low or medium/anywhere code models of sparc64. */
769 sp64_medium_pic_operand (op
, mode
)
771 enum machine_mode mode ATTRIBUTE_UNUSED
;
773 /* Check for (const (minus (symbol_ref:GOT)
774 (const (minus (label) (pc))))). */
775 if (GET_CODE (op
) != CONST
)
778 if (GET_CODE (op
) != MINUS
)
780 if (GET_CODE (XEXP (op
, 0)) != SYMBOL_REF
)
782 /* ??? Ensure symbol is GOT. */
783 if (GET_CODE (XEXP (op
, 1)) != CONST
)
785 if (GET_CODE (XEXP (XEXP (op
, 1), 0)) != MINUS
)
790 /* Return 1 if the operand is a data segment reference. This includes
791 the readonly data segment, or in other words anything but the text segment.
792 This is needed in the medium/anywhere code model on v9. These values
793 are accessed with EMBMEDANY_BASE_REG. */
796 data_segment_operand (op
, mode
)
798 enum machine_mode mode ATTRIBUTE_UNUSED
;
800 switch (GET_CODE (op
))
803 return ! SYMBOL_REF_FLAG (op
);
805 /* Assume canonical format of symbol + constant.
808 return data_segment_operand (XEXP (op
, 0), VOIDmode
);
814 /* Return 1 if the operand is a text segment reference.
815 This is needed in the medium/anywhere code model on v9. */
818 text_segment_operand (op
, mode
)
820 enum machine_mode mode ATTRIBUTE_UNUSED
;
822 switch (GET_CODE (op
))
827 return SYMBOL_REF_FLAG (op
);
829 /* Assume canonical format of symbol + constant.
832 return text_segment_operand (XEXP (op
, 0), VOIDmode
);
838 /* Return 1 if the operand is either a register or a memory operand that is
842 reg_or_nonsymb_mem_operand (op
, mode
)
844 enum machine_mode mode
;
846 if (register_operand (op
, mode
))
849 if (memory_operand (op
, mode
) && ! symbolic_memory_operand (op
, mode
))
856 splittable_symbolic_memory_operand (op
, mode
)
858 enum machine_mode mode ATTRIBUTE_UNUSED
;
860 if (GET_CODE (op
) != MEM
)
862 if (! symbolic_operand (XEXP (op
, 0), Pmode
))
868 splittable_immediate_memory_operand (op
, mode
)
870 enum machine_mode mode ATTRIBUTE_UNUSED
;
872 if (GET_CODE (op
) != MEM
)
874 if (! immediate_operand (XEXP (op
, 0), Pmode
))
879 /* Return truth value of whether OP is EQ or NE. */
884 enum machine_mode mode ATTRIBUTE_UNUSED
;
886 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
889 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
890 or LTU for non-floating-point. We handle those specially. */
893 normal_comp_operator (op
, mode
)
895 enum machine_mode mode ATTRIBUTE_UNUSED
;
897 enum rtx_code code
= GET_CODE (op
);
899 if (GET_RTX_CLASS (code
) != '<')
902 if (GET_MODE (XEXP (op
, 0)) == CCFPmode
903 || GET_MODE (XEXP (op
, 0)) == CCFPEmode
)
906 return (code
!= NE
&& code
!= EQ
&& code
!= GEU
&& code
!= LTU
);
909 /* Return 1 if this is a comparison operator. This allows the use of
910 MATCH_OPERATOR to recognize all the branch insns. */
913 noov_compare_op (op
, mode
)
915 enum machine_mode mode ATTRIBUTE_UNUSED
;
917 enum rtx_code code
= GET_CODE (op
);
919 if (GET_RTX_CLASS (code
) != '<')
922 if (GET_MODE (XEXP (op
, 0)) == CC_NOOVmode
923 || GET_MODE (XEXP (op
, 0)) == CCX_NOOVmode
)
924 /* These are the only branches which work with CC_NOOVmode. */
925 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
);
929 /* Return 1 if this is a 64-bit comparison operator. This allows the use of
930 MATCH_OPERATOR to recognize all the branch insns. */
933 noov_compare64_op (op
, mode
)
935 enum machine_mode mode ATTRIBUTE_UNUSED
;
937 enum rtx_code code
= GET_CODE (op
);
942 if (GET_RTX_CLASS (code
) != '<')
945 if (GET_MODE (XEXP (op
, 0)) == CCX_NOOVmode
)
946 /* These are the only branches which work with CCX_NOOVmode. */
947 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
);
948 return (GET_MODE (XEXP (op
, 0)) == CCXmode
);
951 /* Nonzero if OP is a comparison operator suitable for use in v9
952 conditional move or branch on register contents instructions. */
955 v9_regcmp_op (op
, mode
)
957 enum machine_mode mode ATTRIBUTE_UNUSED
;
959 enum rtx_code code
= GET_CODE (op
);
961 if (GET_RTX_CLASS (code
) != '<')
964 return v9_regcmp_p (code
);
967 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
972 enum machine_mode mode ATTRIBUTE_UNUSED
;
974 return GET_CODE (op
) == SIGN_EXTEND
|| GET_CODE (op
) == ZERO_EXTEND
;
977 /* Return nonzero if OP is an operator of mode MODE which can set
978 the condition codes explicitly. We do not include PLUS and MINUS
979 because these require CC_NOOVmode, which we handle explicitly. */
982 cc_arithop (op
, mode
)
984 enum machine_mode mode ATTRIBUTE_UNUSED
;
986 if (GET_CODE (op
) == AND
987 || GET_CODE (op
) == IOR
988 || GET_CODE (op
) == XOR
)
994 /* Return nonzero if OP is an operator of mode MODE which can bitwise
995 complement its second operand and set the condition codes explicitly. */
998 cc_arithopn (op
, mode
)
1000 enum machine_mode mode ATTRIBUTE_UNUSED
;
1002 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
1003 and (xor ... (not ...)) to (not (xor ...)). */
1004 return (GET_CODE (op
) == AND
1005 || GET_CODE (op
) == IOR
);
1008 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1009 signed 13 bit immediate field. This is an acceptable SImode operand for
1010 most 3 address instructions. */
1013 arith_operand (op
, mode
)
1015 enum machine_mode mode
;
1017 if (register_operand (op
, mode
))
1019 if (GET_CODE (op
) != CONST_INT
)
1021 return SMALL_INT32 (op
);
1024 /* Return true if OP is a constant 4096 */
1027 arith_4096_operand (op
, mode
)
1029 enum machine_mode mode ATTRIBUTE_UNUSED
;
1031 if (GET_CODE (op
) != CONST_INT
)
1034 return INTVAL (op
) == 4096;
1037 /* Return true if OP is suitable as second operand for add/sub */
1040 arith_add_operand (op
, mode
)
1042 enum machine_mode mode
;
1044 return arith_operand (op
, mode
) || arith_4096_operand (op
, mode
);
1047 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
1048 immediate field of OR and XOR instructions. Used for 64-bit
1049 constant formation patterns. */
1051 const64_operand (op
, mode
)
1053 enum machine_mode mode ATTRIBUTE_UNUSED
;
1055 return ((GET_CODE (op
) == CONST_INT
1056 && SPARC_SIMM13_P (INTVAL (op
)))
1057 #if HOST_BITS_PER_WIDE_INT != 64
1058 || (GET_CODE (op
) == CONST_DOUBLE
1059 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op
))
1060 && (CONST_DOUBLE_HIGH (op
) ==
1061 ((CONST_DOUBLE_LOW (op
) & 0x80000000) != 0 ?
1062 (HOST_WIDE_INT
)-1 : 0)))
1067 /* The same, but only for sethi instructions. */
1069 const64_high_operand (op
, mode
)
1071 enum machine_mode mode
;
1073 return ((GET_CODE (op
) == CONST_INT
1074 && (INTVAL (op
) & ~(HOST_WIDE_INT
)0x3ff) != 0
1075 && SPARC_SETHI_P (INTVAL (op
) & GET_MODE_MASK (mode
))
1077 || (GET_CODE (op
) == CONST_DOUBLE
1078 && CONST_DOUBLE_HIGH (op
) == 0
1079 && (CONST_DOUBLE_LOW (op
) & ~(HOST_WIDE_INT
)0x3ff) != 0
1080 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op
))));
1083 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1084 signed 11 bit immediate field. This is an acceptable SImode operand for
1085 the movcc instructions. */
1088 arith11_operand (op
, mode
)
1090 enum machine_mode mode
;
1092 return (register_operand (op
, mode
)
1093 || (GET_CODE (op
) == CONST_INT
&& SPARC_SIMM11_P (INTVAL (op
))));
1096 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1097 signed 10 bit immediate field. This is an acceptable SImode operand for
1098 the movrcc instructions. */
1101 arith10_operand (op
, mode
)
1103 enum machine_mode mode
;
1105 return (register_operand (op
, mode
)
1106 || (GET_CODE (op
) == CONST_INT
&& SPARC_SIMM10_P (INTVAL (op
))));
1109 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
1110 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
1112 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1113 can fit in a 13 bit immediate field. This is an acceptable DImode operand
1114 for most 3 address instructions. */
1117 arith_double_operand (op
, mode
)
1119 enum machine_mode mode
;
1121 return (register_operand (op
, mode
)
1122 || (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
1124 && GET_CODE (op
) == CONST_DOUBLE
1125 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_LOW (op
) + 0x1000) < 0x2000
1126 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_HIGH (op
) + 0x1000) < 0x2000)
1128 && GET_CODE (op
) == CONST_DOUBLE
1129 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_LOW (op
) + 0x1000) < 0x2000
1130 && ((CONST_DOUBLE_HIGH (op
) == -1
1131 && (CONST_DOUBLE_LOW (op
) & 0x1000) == 0x1000)
1132 || (CONST_DOUBLE_HIGH (op
) == 0
1133 && (CONST_DOUBLE_LOW (op
) & 0x1000) == 0))));
1136 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1139 arith_double_4096_operand (op
, mode
)
1141 enum machine_mode mode ATTRIBUTE_UNUSED
;
1143 return (TARGET_ARCH64
&&
1144 ((GET_CODE (op
) == CONST_INT
&& INTVAL (op
) == 4096) ||
1145 (GET_CODE (op
) == CONST_DOUBLE
&&
1146 CONST_DOUBLE_LOW (op
) == 4096 &&
1147 CONST_DOUBLE_HIGH (op
) == 0)));
1150 /* Return true if OP is suitable as second operand for add/sub in DImode */
1153 arith_double_add_operand (op
, mode
)
1155 enum machine_mode mode
;
1157 return arith_double_operand (op
, mode
) || arith_double_4096_operand (op
, mode
);
1160 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1161 can fit in an 11 bit immediate field. This is an acceptable DImode
1162 operand for the movcc instructions. */
1163 /* ??? Replace with arith11_operand? */
1166 arith11_double_operand (op
, mode
)
1168 enum machine_mode mode
;
1170 return (register_operand (op
, mode
)
1171 || (GET_CODE (op
) == CONST_DOUBLE
1172 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
1173 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_LOW (op
) + 0x400) < 0x800
1174 && ((CONST_DOUBLE_HIGH (op
) == -1
1175 && (CONST_DOUBLE_LOW (op
) & 0x400) == 0x400)
1176 || (CONST_DOUBLE_HIGH (op
) == 0
1177 && (CONST_DOUBLE_LOW (op
) & 0x400) == 0)))
1178 || (GET_CODE (op
) == CONST_INT
1179 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
1180 && (unsigned HOST_WIDE_INT
) (INTVAL (op
) + 0x400) < 0x800));
1183 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1184 can fit in an 10 bit immediate field. This is an acceptable DImode
1185 operand for the movrcc instructions. */
1186 /* ??? Replace with arith10_operand? */
1189 arith10_double_operand (op
, mode
)
1191 enum machine_mode mode
;
1193 return (register_operand (op
, mode
)
1194 || (GET_CODE (op
) == CONST_DOUBLE
1195 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
1196 && (unsigned) (CONST_DOUBLE_LOW (op
) + 0x200) < 0x400
1197 && ((CONST_DOUBLE_HIGH (op
) == -1
1198 && (CONST_DOUBLE_LOW (op
) & 0x200) == 0x200)
1199 || (CONST_DOUBLE_HIGH (op
) == 0
1200 && (CONST_DOUBLE_LOW (op
) & 0x200) == 0)))
1201 || (GET_CODE (op
) == CONST_INT
1202 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
1203 && (unsigned HOST_WIDE_INT
) (INTVAL (op
) + 0x200) < 0x400));
1206 /* Return truth value of whether OP is an integer which fits the
1207 range constraining immediate operands in most three-address insns,
1208 which have a 13 bit immediate field. */
1211 small_int (op
, mode
)
1213 enum machine_mode mode ATTRIBUTE_UNUSED
;
1215 return (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
));
1219 small_int_or_double (op
, mode
)
1221 enum machine_mode mode ATTRIBUTE_UNUSED
;
1223 return ((GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
1224 || (GET_CODE (op
) == CONST_DOUBLE
1225 && CONST_DOUBLE_HIGH (op
) == 0
1226 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op
))));
1229 /* Recognize operand values for the umul instruction. That instruction sign
1230 extends immediate values just like all other sparc instructions, but
1231 interprets the extended result as an unsigned number. */
1234 uns_small_int (op
, mode
)
1236 enum machine_mode mode ATTRIBUTE_UNUSED
;
1238 #if HOST_BITS_PER_WIDE_INT > 32
1239 /* All allowed constants will fit a CONST_INT. */
1240 return (GET_CODE (op
) == CONST_INT
1241 && ((INTVAL (op
) >= 0 && INTVAL (op
) < 0x1000)
1242 || (INTVAL (op
) >= 0xFFFFF000
1243 && INTVAL (op
) <= 0xFFFFFFFF)));
1245 return ((GET_CODE (op
) == CONST_INT
&& (unsigned) INTVAL (op
) < 0x1000)
1246 || (GET_CODE (op
) == CONST_DOUBLE
1247 && CONST_DOUBLE_HIGH (op
) == 0
1248 && (unsigned) CONST_DOUBLE_LOW (op
) - 0xFFFFF000 < 0x1000));
1253 uns_arith_operand (op
, mode
)
1255 enum machine_mode mode
;
1257 return register_operand (op
, mode
) || uns_small_int (op
, mode
);
1260 /* Return truth value of statement that OP is a call-clobbered register. */
1262 clobbered_register (op
, mode
)
1264 enum machine_mode mode ATTRIBUTE_UNUSED
;
1266 return (GET_CODE (op
) == REG
&& call_used_regs
[REGNO (op
)]);
1269 /* Return 1 if OP is a valid operand for the source of a move insn. */
1272 input_operand (op
, mode
)
1274 enum machine_mode mode
;
1276 /* If both modes are non-void they must be the same. */
1277 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1280 /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */
1281 if (GET_CODE (op
) == CONST
&& GET_CODE (XEXP (op
, 0)) == CONSTANT_P_RTX
)
1284 /* Allow any one instruction integer constant, and all CONST_INT
1285 variants when we are working in DImode and !arch64. */
1286 if (GET_MODE_CLASS (mode
) == MODE_INT
1287 && ((GET_CODE (op
) == CONST_INT
1288 && (SPARC_SETHI_P (INTVAL (op
) & GET_MODE_MASK (mode
))
1289 || SPARC_SIMM13_P (INTVAL (op
))
1291 && ! TARGET_ARCH64
)))
1293 && GET_CODE (op
) == CONST_DOUBLE
1294 && ((CONST_DOUBLE_HIGH (op
) == 0
1295 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op
)))
1297 #if HOST_BITS_PER_WIDE_INT == 64
1298 (CONST_DOUBLE_HIGH (op
) == 0
1299 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op
)))
1301 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op
))
1302 && (((CONST_DOUBLE_LOW (op
) & 0x80000000) == 0
1303 && CONST_DOUBLE_HIGH (op
) == 0)
1304 || (CONST_DOUBLE_HIGH (op
) == -1
1305 && CONST_DOUBLE_LOW (op
) & 0x80000000) != 0))
1310 /* If !arch64 and this is a DImode const, allow it so that
1311 the splits can be generated. */
1314 && GET_CODE (op
) == CONST_DOUBLE
)
1317 if (register_operand (op
, mode
))
1320 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
1321 && GET_CODE (op
) == CONST_DOUBLE
)
1324 /* If this is a SUBREG, look inside so that we handle
1325 paradoxical ones. */
1326 if (GET_CODE (op
) == SUBREG
)
1327 op
= SUBREG_REG (op
);
1329 /* Check for valid MEM forms. */
1330 if (GET_CODE (op
) == MEM
)
1332 rtx inside
= XEXP (op
, 0);
1334 if (GET_CODE (inside
) == LO_SUM
)
1336 /* We can't allow these because all of the splits
1337 (eventually as they trickle down into DFmode
1338 splits) require offsettable memory references. */
1340 && GET_MODE (op
) == TFmode
)
1343 return (register_operand (XEXP (inside
, 0), Pmode
)
1344 && CONSTANT_P (XEXP (inside
, 1)));
1346 return memory_address_p (mode
, inside
);
1353 /* We know it can't be done in one insn when we get here,
1354 the movsi expander guarentees this. */
1356 sparc_emit_set_const32 (op0
, op1
)
1360 enum machine_mode mode
= GET_MODE (op0
);
1363 if (GET_CODE (op1
) == CONST_INT
)
1365 HOST_WIDE_INT value
= INTVAL (op1
);
1367 if (SPARC_SETHI_P (value
& GET_MODE_MASK (mode
))
1368 || SPARC_SIMM13_P (value
))
1372 /* Full 2-insn decomposition is needed. */
1373 if (reload_in_progress
|| reload_completed
)
1376 temp
= gen_reg_rtx (mode
);
1378 if (GET_CODE (op1
) == CONST_INT
)
1380 /* Emit them as real moves instead of a HIGH/LO_SUM,
1381 this way CSE can see everything and reuse intermediate
1382 values if it wants. */
1384 && HOST_BITS_PER_WIDE_INT
!= 64
1385 && (INTVAL (op1
) & 0x80000000) != 0)
1386 emit_insn (gen_rtx_SET
1388 immed_double_const (INTVAL (op1
) & ~(HOST_WIDE_INT
)0x3ff,
1391 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1392 GEN_INT (INTVAL (op1
)
1393 & ~(HOST_WIDE_INT
)0x3ff)));
1395 emit_insn (gen_rtx_SET (VOIDmode
,
1397 gen_rtx_IOR (mode
, temp
,
1398 GEN_INT (INTVAL (op1
) & 0x3ff))));
1402 /* A symbol, emit in the traditional way. */
1403 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1404 gen_rtx_HIGH (mode
, op1
)));
1405 emit_insn (gen_rtx_SET (VOIDmode
,
1406 op0
, gen_rtx_LO_SUM (mode
, temp
, op1
)));
1412 /* Sparc-v9 code-model support. */
1414 sparc_emit_set_symbolic_const64 (op0
, op1
, temp1
)
1421 if (temp1
&& GET_MODE (temp1
) == TImode
)
1424 temp1
= gen_rtx_REG (DImode
, REGNO (temp1
));
1427 switch (sparc_cmodel
)
1430 /* The range spanned by all instructions in the object is less
1431 than 2^31 bytes (2GB) and the distance from any instruction
1432 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1433 than 2^31 bytes (2GB).
1435 The executable must be in the low 4TB of the virtual address
1438 sethi %hi(symbol), %temp
1439 or %temp, %lo(symbol), %reg */
1440 emit_insn (gen_rtx_SET (VOIDmode
, temp1
, gen_rtx_HIGH (DImode
, op1
)));
1441 emit_insn (gen_rtx_SET (VOIDmode
, op0
, gen_rtx_LO_SUM (DImode
, temp1
, op1
)));
1445 /* The range spanned by all instructions in the object is less
1446 than 2^31 bytes (2GB) and the distance from any instruction
1447 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1448 than 2^31 bytes (2GB).
1450 The executable must be in the low 16TB of the virtual address
1453 sethi %h44(symbol), %temp1
1454 or %temp1, %m44(symbol), %temp2
1455 sllx %temp2, 12, %temp3
1456 or %temp3, %l44(symbol), %reg */
1457 emit_insn (gen_seth44 (op0
, op1
));
1458 emit_insn (gen_setm44 (op0
, op0
, op1
));
1459 emit_insn (gen_rtx_SET (VOIDmode
, temp1
,
1460 gen_rtx_ASHIFT (DImode
, op0
, GEN_INT (12))));
1461 emit_insn (gen_setl44 (op0
, temp1
, op1
));
1465 /* The range spanned by all instructions in the object is less
1466 than 2^31 bytes (2GB) and the distance from any instruction
1467 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1468 than 2^31 bytes (2GB).
1470 The executable can be placed anywhere in the virtual address
1473 sethi %hh(symbol), %temp1
1474 sethi %lm(symbol), %temp2
1475 or %temp1, %hm(symbol), %temp3
1476 or %temp2, %lo(symbol), %temp4
1477 sllx %temp3, 32, %temp5
1478 or %temp4, %temp5, %reg */
1480 /* It is possible that one of the registers we got for operands[2]
1481 might coincide with that of operands[0] (which is why we made
1482 it TImode). Pick the other one to use as our scratch. */
1483 if (rtx_equal_p (temp1
, op0
))
1486 temp1
= gen_rtx_REG (DImode
, REGNO (temp1
) + 1);
1491 emit_insn (gen_sethh (op0
, op1
));
1492 emit_insn (gen_setlm (temp1
, op1
));
1493 emit_insn (gen_sethm (op0
, op0
, op1
));
1494 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1495 gen_rtx_ASHIFT (DImode
, op0
, GEN_INT (32))));
1496 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1497 gen_rtx_PLUS (DImode
, op0
, temp1
)));
1498 emit_insn (gen_setlo (op0
, op0
, op1
));
1502 /* Old old old backwards compatibility kruft here.
1503 Essentially it is MEDLOW with a fixed 64-bit
1504 virtual base added to all data segment addresses.
1505 Text-segment stuff is computed like MEDANY, we can't
1506 reuse the code above because the relocation knobs
1509 Data segment: sethi %hi(symbol), %temp1
1510 or %temp1, %lo(symbol), %temp2
1511 add %temp2, EMBMEDANY_BASE_REG, %reg
1513 Text segment: sethi %uhi(symbol), %temp1
1514 sethi %hi(symbol), %temp2
1515 or %temp1, %ulo(symbol), %temp3
1516 or %temp2, %lo(symbol), %temp4
1517 sllx %temp3, 32, %temp5
1518 or %temp4, %temp5, %reg */
1519 if (data_segment_operand (op1
, GET_MODE (op1
)))
1521 emit_insn (gen_embmedany_sethi (temp1
, op1
));
1522 emit_insn (gen_embmedany_brsum (op0
, temp1
));
1523 emit_insn (gen_embmedany_losum (op0
, op0
, op1
));
1527 /* It is possible that one of the registers we got for operands[2]
1528 might coincide with that of operands[0] (which is why we made
1529 it TImode). Pick the other one to use as our scratch. */
1530 if (rtx_equal_p (temp1
, op0
))
1533 temp1
= gen_rtx_REG (DImode
, REGNO (temp1
) + 1);
1538 emit_insn (gen_embmedany_textuhi (op0
, op1
));
1539 emit_insn (gen_embmedany_texthi (temp1
, op1
));
1540 emit_insn (gen_embmedany_textulo (op0
, op0
, op1
));
1541 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1542 gen_rtx_ASHIFT (DImode
, op0
, GEN_INT (32))));
1543 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1544 gen_rtx_PLUS (DImode
, op0
, temp1
)));
1545 emit_insn (gen_embmedany_textlo (op0
, op0
, op1
));
1554 /* These avoid problems when cross compiling. If we do not
1555 go through all this hair then the optimizer will see
1556 invalid REG_EQUAL notes or in some cases none at all. */
1557 static void sparc_emit_set_safe_HIGH64
PARAMS ((rtx
, HOST_WIDE_INT
));
1558 static rtx gen_safe_SET64
PARAMS ((rtx
, HOST_WIDE_INT
));
1559 static rtx gen_safe_OR64
PARAMS ((rtx
, HOST_WIDE_INT
));
1560 static rtx gen_safe_XOR64
PARAMS ((rtx
, HOST_WIDE_INT
));
1562 #if HOST_BITS_PER_WIDE_INT == 64
1563 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
1564 #define GEN_INT64(__x) GEN_INT (__x)
1566 #define GEN_HIGHINT64(__x) \
1567 immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode)
1568 #define GEN_INT64(__x) \
1569 immed_double_const ((__x) & 0xffffffff, \
1570 ((__x) & 0x80000000 ? -1 : 0), DImode)
1573 /* The optimizer is not to assume anything about exactly
1574 which bits are set for a HIGH, they are unspecified.
1575 Unfortunately this leads to many missed optimizations
1576 during CSE. We mask out the non-HIGH bits, and matches
1577 a plain movdi, to alleviate this problem. */
1579 sparc_emit_set_safe_HIGH64 (dest
, val
)
1583 emit_insn (gen_rtx_SET (VOIDmode
, dest
, GEN_HIGHINT64 (val
)));
1587 gen_safe_SET64 (dest
, val
)
1591 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT64 (val
));
1595 gen_safe_OR64 (src
, val
)
1599 return gen_rtx_IOR (DImode
, src
, GEN_INT64 (val
));
1603 gen_safe_XOR64 (src
, val
)
1607 return gen_rtx_XOR (DImode
, src
, GEN_INT64 (val
));
1610 /* Worker routines for 64-bit constant formation on arch64.
1611 One of the key things to be doing in these emissions is
1612 to create as many temp REGs as possible. This makes it
1613 possible for half-built constants to be used later when
1614 such values are similar to something required later on.
1615 Without doing this, the optimizer cannot see such
1618 static void sparc_emit_set_const64_quick1
1619 PARAMS ((rtx
, rtx
, unsigned HOST_WIDE_INT
, int));
1622 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
, is_neg
)
1625 unsigned HOST_WIDE_INT low_bits
;
1628 unsigned HOST_WIDE_INT high_bits
;
1631 high_bits
= (~low_bits
) & 0xffffffff;
1633 high_bits
= low_bits
;
1635 sparc_emit_set_safe_HIGH64 (temp
, high_bits
);
1638 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1639 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1643 /* If we are XOR'ing with -1, then we should emit a one's complement
1644 instead. This way the combiner will notice logical operations
1645 such as ANDN later on and substitute. */
1646 if ((low_bits
& 0x3ff) == 0x3ff)
1648 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1649 gen_rtx_NOT (DImode
, temp
)));
1653 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1654 gen_safe_XOR64 (temp
,
1655 (-(HOST_WIDE_INT
)0x400
1656 | (low_bits
& 0x3ff)))));
1661 static void sparc_emit_set_const64_quick2
1662 PARAMS ((rtx
, rtx
, unsigned HOST_WIDE_INT
,
1663 unsigned HOST_WIDE_INT
, int));
1666 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_immediate
, shift_count
)
1669 unsigned HOST_WIDE_INT high_bits
;
1670 unsigned HOST_WIDE_INT low_immediate
;
1675 if ((high_bits
& 0xfffffc00) != 0)
1677 sparc_emit_set_safe_HIGH64 (temp
, high_bits
);
1678 if ((high_bits
& ~0xfffffc00) != 0)
1679 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1680 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1686 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1690 /* Now shift it up into place. */
1691 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1692 gen_rtx_ASHIFT (DImode
, temp2
,
1693 GEN_INT (shift_count
))));
1695 /* If there is a low immediate part piece, finish up by
1696 putting that in as well. */
1697 if (low_immediate
!= 0)
1698 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1699 gen_safe_OR64 (op0
, low_immediate
)));
1702 static void sparc_emit_set_const64_longway
1703 PARAMS ((rtx
, rtx
, unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
));
1705 /* Full 64-bit constant decomposition. Even though this is the
1706 'worst' case, we still optimize a few things away. */
1708 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
)
1711 unsigned HOST_WIDE_INT high_bits
;
1712 unsigned HOST_WIDE_INT low_bits
;
1716 if (reload_in_progress
|| reload_completed
)
1719 sub_temp
= gen_reg_rtx (DImode
);
1721 if ((high_bits
& 0xfffffc00) != 0)
1723 sparc_emit_set_safe_HIGH64 (temp
, high_bits
);
1724 if ((high_bits
& ~0xfffffc00) != 0)
1725 emit_insn (gen_rtx_SET (VOIDmode
,
1727 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1733 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1737 if (!reload_in_progress
&& !reload_completed
)
1739 rtx temp2
= gen_reg_rtx (DImode
);
1740 rtx temp3
= gen_reg_rtx (DImode
);
1741 rtx temp4
= gen_reg_rtx (DImode
);
1743 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1744 gen_rtx_ASHIFT (DImode
, sub_temp
,
1747 sparc_emit_set_safe_HIGH64 (temp2
, low_bits
);
1748 if ((low_bits
& ~0xfffffc00) != 0)
1750 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
1751 gen_safe_OR64 (temp2
, (low_bits
& 0x3ff))));
1752 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1753 gen_rtx_PLUS (DImode
, temp4
, temp3
)));
1757 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1758 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1763 rtx low1
= GEN_INT ((low_bits
>> (32 - 12)) & 0xfff);
1764 rtx low2
= GEN_INT ((low_bits
>> (32 - 12 - 12)) & 0xfff);
1765 rtx low3
= GEN_INT ((low_bits
>> (32 - 12 - 12 - 8)) & 0x0ff);
1768 /* We are in the middle of reload, so this is really
1769 painful. However we do still make an attempt to
1770 avoid emitting truly stupid code. */
1771 if (low1
!= const0_rtx
)
1773 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1774 gen_rtx_ASHIFT (DImode
, sub_temp
,
1775 GEN_INT (to_shift
))));
1776 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1777 gen_rtx_IOR (DImode
, op0
, low1
)));
1785 if (low2
!= const0_rtx
)
1787 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1788 gen_rtx_ASHIFT (DImode
, sub_temp
,
1789 GEN_INT (to_shift
))));
1790 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1791 gen_rtx_IOR (DImode
, op0
, low2
)));
1799 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1800 gen_rtx_ASHIFT (DImode
, sub_temp
,
1801 GEN_INT (to_shift
))));
1802 if (low3
!= const0_rtx
)
1803 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1804 gen_rtx_IOR (DImode
, op0
, low3
)));
1809 /* Analyze a 64-bit constant for certain properties. */
1810 static void analyze_64bit_constant
1811 PARAMS ((unsigned HOST_WIDE_INT
,
1812 unsigned HOST_WIDE_INT
,
1813 int *, int *, int *));
1816 analyze_64bit_constant (high_bits
, low_bits
, hbsp
, lbsp
, abbasp
)
1817 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1818 int *hbsp
, *lbsp
, *abbasp
;
1820 int lowest_bit_set
, highest_bit_set
, all_bits_between_are_set
;
1823 lowest_bit_set
= highest_bit_set
= -1;
1827 if ((lowest_bit_set
== -1)
1828 && ((low_bits
>> i
) & 1))
1830 if ((highest_bit_set
== -1)
1831 && ((high_bits
>> (32 - i
- 1)) & 1))
1832 highest_bit_set
= (64 - i
- 1);
1835 && ((highest_bit_set
== -1)
1836 || (lowest_bit_set
== -1)));
1842 if ((lowest_bit_set
== -1)
1843 && ((high_bits
>> i
) & 1))
1844 lowest_bit_set
= i
+ 32;
1845 if ((highest_bit_set
== -1)
1846 && ((low_bits
>> (32 - i
- 1)) & 1))
1847 highest_bit_set
= 32 - i
- 1;
1850 && ((highest_bit_set
== -1)
1851 || (lowest_bit_set
== -1)));
1853 /* If there are no bits set this should have gone out
1854 as one instruction! */
1855 if (lowest_bit_set
== -1
1856 || highest_bit_set
== -1)
1858 all_bits_between_are_set
= 1;
1859 for (i
= lowest_bit_set
; i
<= highest_bit_set
; i
++)
1863 if ((low_bits
& (1 << i
)) != 0)
1868 if ((high_bits
& (1 << (i
- 32))) != 0)
1871 all_bits_between_are_set
= 0;
1874 *hbsp
= highest_bit_set
;
1875 *lbsp
= lowest_bit_set
;
1876 *abbasp
= all_bits_between_are_set
;
1879 static int const64_is_2insns
1880 PARAMS ((unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
));
1883 const64_is_2insns (high_bits
, low_bits
)
1884 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1886 int highest_bit_set
, lowest_bit_set
, all_bits_between_are_set
;
1889 || high_bits
== 0xffffffff)
1892 analyze_64bit_constant (high_bits
, low_bits
,
1893 &highest_bit_set
, &lowest_bit_set
,
1894 &all_bits_between_are_set
);
1896 if ((highest_bit_set
== 63
1897 || lowest_bit_set
== 0)
1898 && all_bits_between_are_set
!= 0)
1901 if ((highest_bit_set
- lowest_bit_set
) < 21)
1907 static unsigned HOST_WIDE_INT create_simple_focus_bits
1908 PARAMS ((unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
,
1911 static unsigned HOST_WIDE_INT
1912 create_simple_focus_bits (high_bits
, low_bits
, lowest_bit_set
, shift
)
1913 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1914 int lowest_bit_set
, shift
;
1916 HOST_WIDE_INT hi
, lo
;
1918 if (lowest_bit_set
< 32)
1920 lo
= (low_bits
>> lowest_bit_set
) << shift
;
1921 hi
= ((high_bits
<< (32 - lowest_bit_set
)) << shift
);
1926 hi
= ((high_bits
>> (lowest_bit_set
- 32)) << shift
);
1933 /* Here we are sure to be arch64 and this is an integer constant
1934 being loaded into a register. Emit the most efficient
1935 insn sequence possible. Detection of all the 1-insn cases
1936 has been done already. */
1938 sparc_emit_set_const64 (op0
, op1
)
1942 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1943 int lowest_bit_set
, highest_bit_set
;
1944 int all_bits_between_are_set
;
1947 /* Sanity check that we know what we are working with. */
1948 if (! TARGET_ARCH64
)
1951 if (GET_CODE (op0
) != SUBREG
)
1953 if (GET_CODE (op0
) != REG
1954 || (REGNO (op0
) >= SPARC_FIRST_FP_REG
1955 && REGNO (op0
) <= SPARC_LAST_V9_FP_REG
))
1959 if (reload_in_progress
|| reload_completed
)
1962 temp
= gen_reg_rtx (DImode
);
1964 if (GET_CODE (op1
) != CONST_DOUBLE
1965 && GET_CODE (op1
) != CONST_INT
)
1967 sparc_emit_set_symbolic_const64 (op0
, op1
, temp
);
1971 if (GET_CODE (op1
) == CONST_DOUBLE
)
1973 #if HOST_BITS_PER_WIDE_INT == 64
1974 high_bits
= (CONST_DOUBLE_LOW (op1
) >> 32) & 0xffffffff;
1975 low_bits
= CONST_DOUBLE_LOW (op1
) & 0xffffffff;
1977 high_bits
= CONST_DOUBLE_HIGH (op1
);
1978 low_bits
= CONST_DOUBLE_LOW (op1
);
1983 #if HOST_BITS_PER_WIDE_INT == 64
1984 high_bits
= ((INTVAL (op1
) >> 32) & 0xffffffff);
1985 low_bits
= (INTVAL (op1
) & 0xffffffff);
1987 high_bits
= ((INTVAL (op1
) < 0) ?
1990 low_bits
= INTVAL (op1
);
1994 /* low_bits bits 0 --> 31
1995 high_bits bits 32 --> 63 */
1997 analyze_64bit_constant (high_bits
, low_bits
,
1998 &highest_bit_set
, &lowest_bit_set
,
1999 &all_bits_between_are_set
);
2001 /* First try for a 2-insn sequence. */
2003 /* These situations are preferred because the optimizer can
2004 * do more things with them:
2006 * sllx %reg, shift, %reg
2008 * srlx %reg, shift, %reg
2009 * 3) mov some_small_const, %reg
2010 * sllx %reg, shift, %reg
2012 if (((highest_bit_set
== 63
2013 || lowest_bit_set
== 0)
2014 && all_bits_between_are_set
!= 0)
2015 || ((highest_bit_set
- lowest_bit_set
) < 12))
2017 HOST_WIDE_INT the_const
= -1;
2018 int shift
= lowest_bit_set
;
2020 if ((highest_bit_set
!= 63
2021 && lowest_bit_set
!= 0)
2022 || all_bits_between_are_set
== 0)
2025 create_simple_focus_bits (high_bits
, low_bits
,
2028 else if (lowest_bit_set
== 0)
2029 shift
= -(63 - highest_bit_set
);
2031 if (! SPARC_SIMM13_P (the_const
))
2034 emit_insn (gen_safe_SET64 (temp
, the_const
));
2036 emit_insn (gen_rtx_SET (VOIDmode
,
2038 gen_rtx_ASHIFT (DImode
,
2042 emit_insn (gen_rtx_SET (VOIDmode
,
2044 gen_rtx_LSHIFTRT (DImode
,
2046 GEN_INT (-shift
))));
2052 /* Now a range of 22 or less bits set somewhere.
2053 * 1) sethi %hi(focus_bits), %reg
2054 * sllx %reg, shift, %reg
2055 * 2) sethi %hi(focus_bits), %reg
2056 * srlx %reg, shift, %reg
2058 if ((highest_bit_set
- lowest_bit_set
) < 21)
2060 unsigned HOST_WIDE_INT focus_bits
=
2061 create_simple_focus_bits (high_bits
, low_bits
,
2062 lowest_bit_set
, 10);
2064 if (! SPARC_SETHI_P (focus_bits
))
2067 sparc_emit_set_safe_HIGH64 (temp
, focus_bits
);
2069 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2070 if (lowest_bit_set
< 10)
2071 emit_insn (gen_rtx_SET (VOIDmode
,
2073 gen_rtx_LSHIFTRT (DImode
, temp
,
2074 GEN_INT (10 - lowest_bit_set
))));
2075 else if (lowest_bit_set
> 10)
2076 emit_insn (gen_rtx_SET (VOIDmode
,
2078 gen_rtx_ASHIFT (DImode
, temp
,
2079 GEN_INT (lowest_bit_set
- 10))));
2085 /* 1) sethi %hi(low_bits), %reg
2086 * or %reg, %lo(low_bits), %reg
2087 * 2) sethi %hi(~low_bits), %reg
2088 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2091 || high_bits
== 0xffffffff)
2093 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
,
2094 (high_bits
== 0xffffffff));
2098 /* Now, try 3-insn sequences. */
2100 /* 1) sethi %hi(high_bits), %reg
2101 * or %reg, %lo(high_bits), %reg
2102 * sllx %reg, 32, %reg
2106 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, 0, 32);
2110 /* We may be able to do something quick
2111 when the constant is negated, so try that. */
2112 if (const64_is_2insns ((~high_bits
) & 0xffffffff,
2113 (~low_bits
) & 0xfffffc00))
2115 /* NOTE: The trailing bits get XOR'd so we need the
2116 non-negated bits, not the negated ones. */
2117 unsigned HOST_WIDE_INT trailing_bits
= low_bits
& 0x3ff;
2119 if ((((~high_bits
) & 0xffffffff) == 0
2120 && ((~low_bits
) & 0x80000000) == 0)
2121 || (((~high_bits
) & 0xffffffff) == 0xffffffff
2122 && ((~low_bits
) & 0x80000000) != 0))
2124 int fast_int
= (~low_bits
& 0xffffffff);
2126 if ((SPARC_SETHI_P (fast_int
)
2127 && (~high_bits
& 0xffffffff) == 0)
2128 || SPARC_SIMM13_P (fast_int
))
2129 emit_insn (gen_safe_SET64 (temp
, fast_int
));
2131 sparc_emit_set_const64 (temp
, GEN_INT64 (fast_int
));
2136 #if HOST_BITS_PER_WIDE_INT == 64
2137 negated_const
= GEN_INT (((~low_bits
) & 0xfffffc00) |
2138 (((HOST_WIDE_INT
)((~high_bits
) & 0xffffffff))<<32));
2140 negated_const
= immed_double_const ((~low_bits
) & 0xfffffc00,
2141 (~high_bits
) & 0xffffffff,
2144 sparc_emit_set_const64 (temp
, negated_const
);
2147 /* If we are XOR'ing with -1, then we should emit a one's complement
2148 instead. This way the combiner will notice logical operations
2149 such as ANDN later on and substitute. */
2150 if (trailing_bits
== 0x3ff)
2152 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2153 gen_rtx_NOT (DImode
, temp
)));
2157 emit_insn (gen_rtx_SET (VOIDmode
,
2159 gen_safe_XOR64 (temp
,
2160 (-0x400 | trailing_bits
))));
2165 /* 1) sethi %hi(xxx), %reg
2166 * or %reg, %lo(xxx), %reg
2167 * sllx %reg, yyy, %reg
2169 * ??? This is just a generalized version of the low_bits==0
2170 * thing above, FIXME...
2172 if ((highest_bit_set
- lowest_bit_set
) < 32)
2174 unsigned HOST_WIDE_INT focus_bits
=
2175 create_simple_focus_bits (high_bits
, low_bits
,
2178 /* We can't get here in this state. */
2179 if (highest_bit_set
< 32
2180 || lowest_bit_set
>= 32)
2183 /* So what we know is that the set bits straddle the
2184 middle of the 64-bit word. */
2185 sparc_emit_set_const64_quick2 (op0
, temp
,
2191 /* 1) sethi %hi(high_bits), %reg
2192 * or %reg, %lo(high_bits), %reg
2193 * sllx %reg, 32, %reg
2194 * or %reg, low_bits, %reg
2196 if (SPARC_SIMM13_P(low_bits
)
2197 && ((int)low_bits
> 0))
2199 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_bits
, 32);
2203 /* The easiest way when all else fails, is full decomposition. */
2205 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2206 high_bits
, low_bits
, ~high_bits
, ~low_bits
);
2208 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
);
2211 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2212 return the mode to be used for the comparison. For floating-point,
2213 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2214 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2215 processing is needed. */
2218 select_cc_mode (op
, x
, y
)
2221 rtx y ATTRIBUTE_UNUSED
;
2223 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2249 else if (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
2250 || GET_CODE (x
) == NEG
|| GET_CODE (x
) == ASHIFT
)
2252 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2253 return CCX_NOOVmode
;
2259 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2266 /* X and Y are two things to compare using CODE. Emit the compare insn and
2267 return the rtx for the cc reg in the proper mode. */
2270 gen_compare_reg (code
, x
, y
)
2274 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
2277 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2278 fcc regs (cse can't tell they're really call clobbered regs and will
2279 remove a duplicate comparison even if there is an intervening function
2280 call - it will then try to reload the cc reg via an int reg which is why
2281 we need the movcc patterns). It is possible to provide the movcc
2282 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2283 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2284 to tell cse that CCFPE mode registers (even pseudos) are call
2287 /* ??? This is an experiment. Rather than making changes to cse which may
2288 or may not be easy/clean, we do our own cse. This is possible because
2289 we will generate hard registers. Cse knows they're call clobbered (it
2290 doesn't know the same thing about pseudos). If we guess wrong, no big
2291 deal, but if we win, great! */
2293 if (TARGET_V9
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2294 #if 1 /* experiment */
2297 /* We cycle through the registers to ensure they're all exercised. */
2298 static int next_fcc_reg
= 0;
2299 /* Previous x,y for each fcc reg. */
2300 static rtx prev_args
[4][2];
2302 /* Scan prev_args for x,y. */
2303 for (reg
= 0; reg
< 4; reg
++)
2304 if (prev_args
[reg
][0] == x
&& prev_args
[reg
][1] == y
)
2309 prev_args
[reg
][0] = x
;
2310 prev_args
[reg
][1] = y
;
2311 next_fcc_reg
= (next_fcc_reg
+ 1) & 3;
2313 cc_reg
= gen_rtx_REG (mode
, reg
+ SPARC_FIRST_V9_FCC_REG
);
2316 cc_reg
= gen_reg_rtx (mode
);
2317 #endif /* ! experiment */
2318 else if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2319 cc_reg
= gen_rtx_REG (mode
, SPARC_FCC_REG
);
2321 cc_reg
= gen_rtx_REG (mode
, SPARC_ICC_REG
);
2323 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
2324 gen_rtx_COMPARE (mode
, x
, y
)));
2329 /* This function is used for v9 only.
2330 CODE is the code for an Scc's comparison.
2331 OPERANDS[0] is the target of the Scc insn.
2332 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2333 been generated yet).
2335 This function is needed to turn
2338 (gt (reg:CCX 100 %icc)
2342 (gt:DI (reg:CCX 100 %icc)
2345 IE: The instruction recognizer needs to see the mode of the comparison to
2346 find the right instruction. We could use "gt:DI" right in the
2347 define_expand, but leaving it out allows us to handle DI, SI, etc.
2349 We refer to the global sparc compare operands sparc_compare_op0 and
2350 sparc_compare_op1. */
2353 gen_v9_scc (compare_code
, operands
)
2354 enum rtx_code compare_code
;
2355 register rtx
*operands
;
2360 && (GET_MODE (sparc_compare_op0
) == DImode
2361 || GET_MODE (operands
[0]) == DImode
))
2364 op0
= sparc_compare_op0
;
2365 op1
= sparc_compare_op1
;
2367 /* Try to use the movrCC insns. */
2369 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
2370 && op1
== const0_rtx
2371 && v9_regcmp_p (compare_code
))
2373 /* Special case for op0 != 0. This can be done with one instruction if
2374 operands[0] == sparc_compare_op0. */
2376 if (compare_code
== NE
2377 && GET_MODE (operands
[0]) == DImode
2378 && rtx_equal_p (op0
, operands
[0]))
2380 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2381 gen_rtx_IF_THEN_ELSE (DImode
,
2382 gen_rtx_fmt_ee (compare_code
, DImode
,
2389 if (reg_overlap_mentioned_p (operands
[0], op0
))
2391 /* Handle the case where operands[0] == sparc_compare_op0.
2392 We "early clobber" the result. */
2393 op0
= gen_reg_rtx (GET_MODE (sparc_compare_op0
));
2394 emit_move_insn (op0
, sparc_compare_op0
);
2397 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], const0_rtx
));
2398 if (GET_MODE (op0
) != DImode
)
2400 temp
= gen_reg_rtx (DImode
);
2401 convert_move (temp
, op0
, 0);
2405 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2406 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
2407 gen_rtx_fmt_ee (compare_code
, DImode
,
2415 operands
[1] = gen_compare_reg (compare_code
, op0
, op1
);
2417 switch (GET_MODE (operands
[1]))
2427 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], const0_rtx
));
2428 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2429 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
2430 gen_rtx_fmt_ee (compare_code
,
2431 GET_MODE (operands
[1]),
2432 operands
[1], const0_rtx
),
2433 const1_rtx
, operands
[0])));
2438 /* Emit a conditional jump insn for the v9 architecture using comparison code
2439 CODE and jump target LABEL.
2440 This function exists to take advantage of the v9 brxx insns. */
2443 emit_v9_brxx_insn (code
, op0
, label
)
2447 emit_jump_insn (gen_rtx_SET (VOIDmode
,
2449 gen_rtx_IF_THEN_ELSE (VOIDmode
,
2450 gen_rtx_fmt_ee (code
, GET_MODE (op0
),
2452 gen_rtx_LABEL_REF (VOIDmode
, label
),
2456 /* Generate a DFmode part of a hard TFmode register.
2457 REG is the TFmode hard register, LOW is 1 for the
2458 low 64bit of the register and 0 otherwise.
2461 gen_df_reg (reg
, low
)
2465 int regno
= REGNO (reg
);
2467 if ((WORDS_BIG_ENDIAN
== 0) ^ (low
!= 0))
2468 regno
+= (TARGET_ARCH64
&& regno
< 32) ? 1 : 2;
2469 return gen_rtx_REG (DFmode
, regno
);
2472 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2473 Unlike normal calls, TFmode operands are passed by reference. It is
2474 assumed that no more than 3 operands are required. */
2477 emit_soft_tfmode_libcall (func_name
, nargs
, operands
)
2478 const char *func_name
;
2482 rtx ret_slot
= NULL
, arg
[3], func_sym
;
2485 /* We only expect to be called for conversions, unary, and binary ops. */
2486 if (nargs
< 2 || nargs
> 3)
2489 for (i
= 0; i
< nargs
; ++i
)
2491 rtx this_arg
= operands
[i
];
2494 /* TFmode arguments and return values are passed by reference. */
2495 if (GET_MODE (this_arg
) == TFmode
)
2497 int force_stack_temp
;
2499 force_stack_temp
= 0;
2500 if (TARGET_BUGGY_QP_LIB
&& i
== 0)
2501 force_stack_temp
= 1;
2503 if (GET_CODE (this_arg
) == MEM
2504 && ! force_stack_temp
)
2505 this_arg
= XEXP (this_arg
, 0);
2506 else if (CONSTANT_P (this_arg
)
2507 && ! force_stack_temp
)
2509 this_slot
= force_const_mem (TFmode
, this_arg
);
2510 this_arg
= XEXP (this_slot
, 0);
2514 this_slot
= assign_stack_temp (TFmode
, GET_MODE_SIZE (TFmode
), 0);
2516 /* Operand 0 is the return value. We'll copy it out later. */
2518 emit_move_insn (this_slot
, this_arg
);
2520 ret_slot
= this_slot
;
2522 this_arg
= XEXP (this_slot
, 0);
2529 func_sym
= gen_rtx_SYMBOL_REF (Pmode
, func_name
);
2531 if (GET_MODE (operands
[0]) == TFmode
)
2534 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 2,
2535 arg
[0], GET_MODE (arg
[0]),
2536 arg
[1], GET_MODE (arg
[1]));
2538 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 3,
2539 arg
[0], GET_MODE (arg
[0]),
2540 arg
[1], GET_MODE (arg
[1]),
2541 arg
[2], GET_MODE (arg
[2]));
2544 emit_move_insn (operands
[0], ret_slot
);
2553 ret
= emit_library_call_value (func_sym
, operands
[0], LCT_NORMAL
,
2554 GET_MODE (operands
[0]), 1,
2555 arg
[1], GET_MODE (arg
[1]));
2557 if (ret
!= operands
[0])
2558 emit_move_insn (operands
[0], ret
);
2562 /* Expand soft-float TFmode calls to sparc abi routines. */
2565 emit_soft_tfmode_binop (code
, operands
)
2589 emit_soft_tfmode_libcall (func
, 3, operands
);
2593 emit_soft_tfmode_unop (code
, operands
)
2608 emit_soft_tfmode_libcall (func
, 2, operands
);
2612 emit_soft_tfmode_cvt (code
, operands
)
2621 switch (GET_MODE (operands
[1]))
2634 case FLOAT_TRUNCATE
:
2635 switch (GET_MODE (operands
[0]))
2649 switch (GET_MODE (operands
[1]))
2662 case UNSIGNED_FLOAT
:
2663 switch (GET_MODE (operands
[1]))
2677 switch (GET_MODE (operands
[0]))
2691 switch (GET_MODE (operands
[0]))
2708 emit_soft_tfmode_libcall (func
, 2, operands
);
2711 /* Expand a hard-float tfmode operation. All arguments must be in
2715 emit_hard_tfmode_operation (code
, operands
)
2721 if (GET_RTX_CLASS (code
) == '1')
2723 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
2724 op
= gen_rtx_fmt_e (code
, GET_MODE (operands
[0]), operands
[1]);
2728 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
2729 operands
[2] = force_reg (GET_MODE (operands
[2]), operands
[2]);
2730 op
= gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
2731 operands
[1], operands
[2]);
2734 if (register_operand (operands
[0], VOIDmode
))
2737 dest
= gen_reg_rtx (GET_MODE (operands
[0]));
2739 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op
));
2741 if (dest
!= operands
[0])
2742 emit_move_insn (operands
[0], dest
);
2746 emit_tfmode_binop (code
, operands
)
2750 if (TARGET_HARD_QUAD
)
2751 emit_hard_tfmode_operation (code
, operands
);
2753 emit_soft_tfmode_binop (code
, operands
);
2757 emit_tfmode_unop (code
, operands
)
2761 if (TARGET_HARD_QUAD
)
2762 emit_hard_tfmode_operation (code
, operands
);
2764 emit_soft_tfmode_unop (code
, operands
);
2768 emit_tfmode_cvt (code
, operands
)
2772 if (TARGET_HARD_QUAD
)
2773 emit_hard_tfmode_operation (code
, operands
);
2775 emit_soft_tfmode_cvt (code
, operands
);
2778 /* Return nonzero if a return peephole merging return with
2779 setting of output register is ok. */
2781 leaf_return_peephole_ok ()
2783 return (actual_fsize
== 0);
2786 /* Return nonzero if a branch/jump/call instruction will be emitting
2787 nop into its delay slot. */
2790 empty_delay_slot (insn
)
2795 /* If no previous instruction (should not happen), return true. */
2796 if (PREV_INSN (insn
) == NULL
)
2799 seq
= NEXT_INSN (PREV_INSN (insn
));
2800 if (GET_CODE (PATTERN (seq
)) == SEQUENCE
)
2806 /* Return nonzero if TRIAL can go into the function epilogue's
2807 delay slot. SLOT is the slot we are trying to fill. */
2810 eligible_for_epilogue_delay (trial
, slot
)
2819 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
2822 if (get_attr_length (trial
) != 1)
2825 /* If there are any call-saved registers, we should scan TRIAL if it
2826 does not reference them. For now just make it easy. */
2830 /* If the function uses __builtin_eh_return, the eh_return machinery
2831 occupies the delay slot. */
2832 if (current_function_calls_eh_return
)
2835 /* In the case of a true leaf function, anything can go into the delay slot.
2836 A delay slot only exists however if the frame size is zero, otherwise
2837 we will put an insn to adjust the stack after the return. */
2838 if (current_function_uses_only_leaf_regs
)
2840 if (leaf_return_peephole_ok ())
2841 return ((get_attr_in_uncond_branch_delay (trial
)
2842 == IN_BRANCH_DELAY_TRUE
));
2846 pat
= PATTERN (trial
);
2848 /* Otherwise, only operations which can be done in tandem with
2849 a `restore' or `return' insn can go into the delay slot. */
2850 if (GET_CODE (SET_DEST (pat
)) != REG
2851 || REGNO (SET_DEST (pat
)) < 24)
2854 /* If this instruction sets up floating point register and we have a return
2855 instruction, it can probably go in. But restore will not work
2857 if (REGNO (SET_DEST (pat
)) >= 32)
2859 if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1)
2860 && (get_attr_in_uncond_branch_delay (trial
) == IN_BRANCH_DELAY_TRUE
))
2865 /* The set of insns matched here must agree precisely with the set of
2866 patterns paired with a RETURN in sparc.md. */
2868 src
= SET_SRC (pat
);
2870 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */
2871 if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2872 && arith_operand (src
, GET_MODE (src
)))
2875 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2877 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
2880 /* This matches "*return_di". */
2881 else if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2882 && arith_double_operand (src
, GET_MODE (src
)))
2883 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2885 /* This matches "*return_sf_no_fpu". */
2886 else if (! TARGET_FPU
&& restore_operand (SET_DEST (pat
), SFmode
)
2887 && register_operand (src
, SFmode
))
2890 /* If we have return instruction, anything that does not use
2891 local or output registers and can go into a delay slot wins. */
2892 else if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1)
2893 && (get_attr_in_uncond_branch_delay (trial
) == IN_BRANCH_DELAY_TRUE
))
2896 /* This matches "*return_addsi". */
2897 else if (GET_CODE (src
) == PLUS
2898 && arith_operand (XEXP (src
, 0), SImode
)
2899 && arith_operand (XEXP (src
, 1), SImode
)
2900 && (register_operand (XEXP (src
, 0), SImode
)
2901 || register_operand (XEXP (src
, 1), SImode
)))
2904 /* This matches "*return_adddi". */
2905 else if (GET_CODE (src
) == PLUS
2906 && arith_double_operand (XEXP (src
, 0), DImode
)
2907 && arith_double_operand (XEXP (src
, 1), DImode
)
2908 && (register_operand (XEXP (src
, 0), DImode
)
2909 || register_operand (XEXP (src
, 1), DImode
)))
2912 /* This can match "*return_losum_[sd]i".
2913 Catch only some cases, so that return_losum* don't have
2915 else if (GET_CODE (src
) == LO_SUM
2916 && ! TARGET_CM_MEDMID
2917 && ((register_operand (XEXP (src
, 0), SImode
)
2918 && immediate_operand (XEXP (src
, 1), SImode
))
2920 && register_operand (XEXP (src
, 0), DImode
)
2921 && immediate_operand (XEXP (src
, 1), DImode
))))
2924 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */
2925 else if (GET_CODE (src
) == ASHIFT
2926 && (register_operand (XEXP (src
, 0), SImode
)
2927 || register_operand (XEXP (src
, 0), DImode
))
2928 && XEXP (src
, 1) == const1_rtx
)
2934 /* Return nonzero if TRIAL can go into the sibling call
2938 eligible_for_sibcall_delay (trial
)
2943 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
2946 if (get_attr_length (trial
) != 1)
2949 pat
= PATTERN (trial
);
2951 if (current_function_uses_only_leaf_regs
)
2953 /* If the tail call is done using the call instruction,
2954 we have to restore %o7 in the delay slot. */
2955 if ((TARGET_ARCH64
&& ! TARGET_CM_MEDLOW
) || flag_pic
)
2958 /* %g1 is used to build the function address */
2959 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 1), pat
))
2965 /* Otherwise, only operations which can be done in tandem with
2966 a `restore' insn can go into the delay slot. */
2967 if (GET_CODE (SET_DEST (pat
)) != REG
2968 || REGNO (SET_DEST (pat
)) < 24
2969 || REGNO (SET_DEST (pat
)) >= 32)
2972 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2974 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 15), pat
))
2977 src
= SET_SRC (pat
);
2979 if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2980 && arith_operand (src
, GET_MODE (src
)))
2983 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2985 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
2988 else if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2989 && arith_double_operand (src
, GET_MODE (src
)))
2990 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2992 else if (! TARGET_FPU
&& restore_operand (SET_DEST (pat
), SFmode
)
2993 && register_operand (src
, SFmode
))
2996 else if (GET_CODE (src
) == PLUS
2997 && arith_operand (XEXP (src
, 0), SImode
)
2998 && arith_operand (XEXP (src
, 1), SImode
)
2999 && (register_operand (XEXP (src
, 0), SImode
)
3000 || register_operand (XEXP (src
, 1), SImode
)))
3003 else if (GET_CODE (src
) == PLUS
3004 && arith_double_operand (XEXP (src
, 0), DImode
)
3005 && arith_double_operand (XEXP (src
, 1), DImode
)
3006 && (register_operand (XEXP (src
, 0), DImode
)
3007 || register_operand (XEXP (src
, 1), DImode
)))
3010 else if (GET_CODE (src
) == LO_SUM
3011 && ! TARGET_CM_MEDMID
3012 && ((register_operand (XEXP (src
, 0), SImode
)
3013 && immediate_operand (XEXP (src
, 1), SImode
))
3015 && register_operand (XEXP (src
, 0), DImode
)
3016 && immediate_operand (XEXP (src
, 1), DImode
))))
3019 else if (GET_CODE (src
) == ASHIFT
3020 && (register_operand (XEXP (src
, 0), SImode
)
3021 || register_operand (XEXP (src
, 0), DImode
))
3022 && XEXP (src
, 1) == const1_rtx
)
3029 check_return_regs (x
)
3032 switch (GET_CODE (x
))
3035 return IN_OR_GLOBAL_P (x
);
3050 if (check_return_regs (XEXP (x
, 1)) == 0)
3055 return check_return_regs (XEXP (x
, 0));
3063 /* Return 1 if TRIAL references only in and global registers. */
3065 eligible_for_return_delay (trial
)
3068 if (GET_CODE (PATTERN (trial
)) != SET
)
3071 return check_return_regs (PATTERN (trial
));
3075 short_branch (uid1
, uid2
)
3078 int delta
= INSN_ADDRESSES (uid1
) - INSN_ADDRESSES (uid2
);
3080 /* Leave a few words of "slop". */
3081 if (delta
>= -1023 && delta
<= 1022)
3087 /* Return non-zero if REG is not used after INSN.
3088 We assume REG is a reload reg, and therefore does
3089 not live past labels or calls or jumps. */
3091 reg_unused_after (reg
, insn
)
3095 enum rtx_code code
, prev_code
= UNKNOWN
;
3097 while ((insn
= NEXT_INSN (insn
)))
3099 if (prev_code
== CALL_INSN
&& call_used_regs
[REGNO (reg
)])
3102 code
= GET_CODE (insn
);
3103 if (GET_CODE (insn
) == CODE_LABEL
)
3106 if (GET_RTX_CLASS (code
) == 'i')
3108 rtx set
= single_set (insn
);
3109 int in_src
= set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
));
3112 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
3114 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
3122 /* The table we use to reference PIC data. */
3123 static rtx global_offset_table
;
3125 /* The function we use to get at it. */
3126 static rtx get_pc_symbol
;
3127 static char get_pc_symbol_name
[256];
3129 /* Ensure that we are not using patterns that are not OK with PIC. */
3138 if (GET_CODE (recog_data
.operand
[i
]) == SYMBOL_REF
3139 || (GET_CODE (recog_data
.operand
[i
]) == CONST
3140 && ! (GET_CODE (XEXP (recog_data
.operand
[i
], 0)) == MINUS
3141 && (XEXP (XEXP (recog_data
.operand
[i
], 0), 0)
3142 == global_offset_table
)
3143 && (GET_CODE (XEXP (XEXP (recog_data
.operand
[i
], 0), 1))
3152 /* Return true if X is an address which needs a temporary register when
3153 reloaded while generating PIC code. */
3156 pic_address_needs_scratch (x
)
3159 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3160 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
3161 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
3162 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3163 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
3169 /* Legitimize PIC addresses. If the address is already position-independent,
3170 we return ORIG. Newly generated position-independent addresses go into a
3171 reg. This is REG if non zero, otherwise we allocate register(s) as
3175 legitimize_pic_address (orig
, mode
, reg
)
3177 enum machine_mode mode ATTRIBUTE_UNUSED
;
3180 if (GET_CODE (orig
) == SYMBOL_REF
)
3182 rtx pic_ref
, address
;
3187 if (reload_in_progress
|| reload_completed
)
3190 reg
= gen_reg_rtx (Pmode
);
3195 /* If not during reload, allocate another temp reg here for loading
3196 in the address, so that these instructions can be optimized
3198 rtx temp_reg
= ((reload_in_progress
|| reload_completed
)
3199 ? reg
: gen_reg_rtx (Pmode
));
3201 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3202 won't get confused into thinking that these two instructions
3203 are loading in the true address of the symbol. If in the
3204 future a PIC rtx exists, that should be used instead. */
3205 if (Pmode
== SImode
)
3207 emit_insn (gen_movsi_high_pic (temp_reg
, orig
));
3208 emit_insn (gen_movsi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3212 emit_insn (gen_movdi_high_pic (temp_reg
, orig
));
3213 emit_insn (gen_movdi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3220 pic_ref
= gen_rtx_MEM (Pmode
,
3221 gen_rtx_PLUS (Pmode
,
3222 pic_offset_table_rtx
, address
));
3223 current_function_uses_pic_offset_table
= 1;
3224 RTX_UNCHANGING_P (pic_ref
) = 1;
3225 insn
= emit_move_insn (reg
, pic_ref
);
3226 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3228 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
3232 else if (GET_CODE (orig
) == CONST
)
3236 if (GET_CODE (XEXP (orig
, 0)) == PLUS
3237 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
3242 if (reload_in_progress
|| reload_completed
)
3245 reg
= gen_reg_rtx (Pmode
);
3248 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
3250 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
3251 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
3252 base
== reg
? 0 : reg
);
3257 if (GET_CODE (offset
) == CONST_INT
)
3259 if (SMALL_INT (offset
))
3260 return plus_constant (base
, INTVAL (offset
));
3261 else if (! reload_in_progress
&& ! reload_completed
)
3262 offset
= force_reg (Pmode
, offset
);
3264 /* If we reach here, then something is seriously wrong. */
3267 return gen_rtx_PLUS (Pmode
, base
, offset
);
3269 else if (GET_CODE (orig
) == LABEL_REF
)
3270 /* ??? Why do we do this? */
3271 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3272 the register is live instead, in case it is eliminated. */
3273 current_function_uses_pic_offset_table
= 1;
3278 /* Emit special PIC prologues. */
3281 load_pic_register ()
3283 /* Labels to get the PC in the prologue of this function. */
3284 int orig_flag_pic
= flag_pic
;
3289 /* If we haven't emitted the special get_pc helper function, do so now. */
3290 if (get_pc_symbol_name
[0] == 0)
3294 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name
, "LGETPC", 0);
3297 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
3299 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
3300 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "LGETPC", 0);
3301 fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file
);
3304 /* Initialize every time through, since we can't easily
3305 know this to be permanent. */
3306 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3307 get_pc_symbol
= gen_rtx_SYMBOL_REF (Pmode
, get_pc_symbol_name
);
3310 emit_insn (gen_get_pc (pic_offset_table_rtx
, global_offset_table
,
3313 flag_pic
= orig_flag_pic
;
3315 /* Need to emit this whether or not we obey regdecls,
3316 since setjmp/longjmp can cause life info to screw up.
3317 ??? In the case where we don't obey regdecls, this is not sufficient
3318 since we may not fall out the bottom. */
3319 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
3322 /* Return 1 if RTX is a MEM which is known to be aligned to at
3323 least a DESIRED byte boundary. */
3326 mem_min_alignment (mem
, desired
)
3330 rtx addr
, base
, offset
;
3332 /* If it's not a MEM we can't accept it. */
3333 if (GET_CODE (mem
) != MEM
)
3336 addr
= XEXP (mem
, 0);
3337 base
= offset
= NULL_RTX
;
3338 if (GET_CODE (addr
) == PLUS
)
3340 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3342 base
= XEXP (addr
, 0);
3344 /* What we are saying here is that if the base
3345 REG is aligned properly, the compiler will make
3346 sure any REG based index upon it will be so
3348 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
3349 offset
= XEXP (addr
, 1);
3351 offset
= const0_rtx
;
3354 else if (GET_CODE (addr
) == REG
)
3357 offset
= const0_rtx
;
3360 if (base
!= NULL_RTX
)
3362 int regno
= REGNO (base
);
3364 if (regno
!= HARD_FRAME_POINTER_REGNUM
&& regno
!= STACK_POINTER_REGNUM
)
3366 /* Check if the compiler has recorded some information
3367 about the alignment of the base REG. If reload has
3368 completed, we already matched with proper alignments.
3369 If not running global_alloc, reload might give us
3370 unaligned pointer to local stack though. */
3372 && REGNO_POINTER_ALIGN (regno
) >= desired
* BITS_PER_UNIT
)
3373 || (optimize
&& reload_completed
))
3374 && (INTVAL (offset
) & (desired
- 1)) == 0)
3379 if (((INTVAL (offset
) - SPARC_STACK_BIAS
) & (desired
- 1)) == 0)
3383 else if (! TARGET_UNALIGNED_DOUBLES
3384 || CONSTANT_P (addr
)
3385 || GET_CODE (addr
) == LO_SUM
)
3387 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3388 is true, in which case we can only assume that an access is aligned if
3389 it is to a constant address, or the address involves a LO_SUM. */
3393 /* An obviously unaligned address. */
3398 /* Vectors to keep interesting information about registers where it can easily
3399 be got. We use to use the actual mode value as the bit number, but there
3400 are more than 32 modes now. Instead we use two tables: one indexed by
3401 hard register number, and one indexed by mode. */
3403 /* The purpose of sparc_mode_class is to shrink the range of modes so that
3404 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
3405 mapped into one sparc_mode_class mode. */
3407 enum sparc_mode_class
{
3408 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
3409 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
3413 /* Modes for single-word and smaller quantities. */
3414 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3416 /* Modes for double-word and smaller quantities. */
3417 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3419 /* Modes for quad-word and smaller quantities. */
3420 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
3422 /* Modes for 8-word and smaller quantities. */
3423 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3425 /* Modes for single-float quantities. We must allow any single word or
3426 smaller quantity. This is because the fix/float conversion instructions
3427 take integer inputs/outputs from the float registers. */
3428 #define SF_MODES (S_MODES)
3430 /* Modes for double-float and smaller quantities. */
3431 #define DF_MODES (S_MODES | D_MODES)
3433 /* Modes for double-float only quantities. */
3434 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
3436 /* Modes for quad-float only quantities. */
3437 #define TF_ONLY_MODES (1 << (int) TF_MODE)
3439 /* Modes for quad-float and smaller quantities. */
3440 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
3442 /* Modes for quad-float and double-float quantities. */
3443 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
3445 /* Modes for quad-float pair only quantities. */
3446 #define OF_ONLY_MODES (1 << (int) OF_MODE)
3448 /* Modes for quad-float pairs and smaller quantities. */
3449 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
3451 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
3453 /* Modes for condition codes. */
3454 #define CC_MODES (1 << (int) CC_MODE)
3455 #define CCFP_MODES (1 << (int) CCFP_MODE)
3457 /* Value is 1 if register/mode pair is acceptable on sparc.
3458 The funny mixture of D and T modes is because integer operations
3459 do not specially operate on tetra quantities, so non-quad-aligned
3460 registers can hold quadword quantities (except %o4 and %i4 because
3461 they cross fixed registers). */
3463 /* This points to either the 32 bit or the 64 bit version. */
3464 const int *hard_regno_mode_classes
;
3466 static const int hard_32bit_mode_classes
[] = {
3467 S_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
3468 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
3469 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
3470 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
3472 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3473 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3474 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3475 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3477 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3478 and none can hold SFmode/SImode values. */
3479 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3480 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3481 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3482 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3485 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
3491 static const int hard_64bit_mode_classes
[] = {
3492 D_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3493 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3494 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3495 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3497 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3498 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3499 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3500 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3502 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3503 and none can hold SFmode/SImode values. */
3504 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3505 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3506 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3507 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3510 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
3516 int sparc_mode_class
[NUM_MACHINE_MODES
];
3518 enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
3525 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
3527 switch (GET_MODE_CLASS (i
))
3530 case MODE_PARTIAL_INT
:
3531 case MODE_COMPLEX_INT
:
3532 if (GET_MODE_SIZE (i
) <= 4)
3533 sparc_mode_class
[i
] = 1 << (int) S_MODE
;
3534 else if (GET_MODE_SIZE (i
) == 8)
3535 sparc_mode_class
[i
] = 1 << (int) D_MODE
;
3536 else if (GET_MODE_SIZE (i
) == 16)
3537 sparc_mode_class
[i
] = 1 << (int) T_MODE
;
3538 else if (GET_MODE_SIZE (i
) == 32)
3539 sparc_mode_class
[i
] = 1 << (int) O_MODE
;
3541 sparc_mode_class
[i
] = 0;
3544 case MODE_COMPLEX_FLOAT
:
3545 if (GET_MODE_SIZE (i
) <= 4)
3546 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
3547 else if (GET_MODE_SIZE (i
) == 8)
3548 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
3549 else if (GET_MODE_SIZE (i
) == 16)
3550 sparc_mode_class
[i
] = 1 << (int) TF_MODE
;
3551 else if (GET_MODE_SIZE (i
) == 32)
3552 sparc_mode_class
[i
] = 1 << (int) OF_MODE
;
3554 sparc_mode_class
[i
] = 0;
3558 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
3559 we must explicitly check for them here. */
3560 if (i
== (int) CCFPmode
|| i
== (int) CCFPEmode
)
3561 sparc_mode_class
[i
] = 1 << (int) CCFP_MODE
;
3562 else if (i
== (int) CCmode
|| i
== (int) CC_NOOVmode
3563 || i
== (int) CCXmode
|| i
== (int) CCX_NOOVmode
)
3564 sparc_mode_class
[i
] = 1 << (int) CC_MODE
;
3566 sparc_mode_class
[i
] = 0;
3572 hard_regno_mode_classes
= hard_64bit_mode_classes
;
3574 hard_regno_mode_classes
= hard_32bit_mode_classes
;
3576 /* Initialize the array used by REGNO_REG_CLASS. */
3577 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3579 if (i
< 16 && TARGET_V8PLUS
)
3580 sparc_regno_reg_class
[i
] = I64_REGS
;
3581 else if (i
< 32 || i
== FRAME_POINTER_REGNUM
)
3582 sparc_regno_reg_class
[i
] = GENERAL_REGS
;
3584 sparc_regno_reg_class
[i
] = FP_REGS
;
3586 sparc_regno_reg_class
[i
] = EXTRA_FP_REGS
;
3588 sparc_regno_reg_class
[i
] = FPCC_REGS
;
3590 sparc_regno_reg_class
[i
] = NO_REGS
;
3594 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
3595 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3596 v9 int regs as it simplifies the code. */
3599 save_regs (file
, low
, high
, base
, offset
, n_regs
, real_offset
)
3609 if (TARGET_ARCH64
&& high
<= 32)
3611 for (i
= low
; i
< high
; i
++)
3613 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3615 fprintf (file
, "\tstx\t%s, [%s+%d]\n",
3616 reg_names
[i
], base
, offset
+ 4 * n_regs
);
3617 if (dwarf2out_do_frame ())
3618 dwarf2out_reg_save ("", i
, real_offset
+ 4 * n_regs
);
3625 for (i
= low
; i
< high
; i
+= 2)
3627 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3629 if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
3631 fprintf (file
, "\tstd\t%s, [%s+%d]\n",
3632 reg_names
[i
], base
, offset
+ 4 * n_regs
);
3633 if (dwarf2out_do_frame ())
3635 char *l
= dwarf2out_cfi_label ();
3636 dwarf2out_reg_save (l
, i
, real_offset
+ 4 * n_regs
);
3637 dwarf2out_reg_save (l
, i
+1, real_offset
+ 4 * n_regs
+ 4);
3643 fprintf (file
, "\tst\t%s, [%s+%d]\n",
3644 reg_names
[i
], base
, offset
+ 4 * n_regs
);
3645 if (dwarf2out_do_frame ())
3646 dwarf2out_reg_save ("", i
, real_offset
+ 4 * n_regs
);
3652 if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
3654 fprintf (file
, "\tst\t%s, [%s+%d]\n",
3655 reg_names
[i
+1], base
, offset
+ 4 * n_regs
+ 4);
3656 if (dwarf2out_do_frame ())
3657 dwarf2out_reg_save ("", i
+ 1, real_offset
+ 4 * n_regs
+ 4);
3666 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
3668 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3669 v9 int regs as it simplifies the code. */
3672 restore_regs (file
, low
, high
, base
, offset
, n_regs
)
3681 if (TARGET_ARCH64
&& high
<= 32)
3683 for (i
= low
; i
< high
; i
++)
3685 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3686 fprintf (file
, "\tldx\t[%s+%d], %s\n",
3687 base
, offset
+ 4 * n_regs
, reg_names
[i
]),
3693 for (i
= low
; i
< high
; i
+= 2)
3695 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3696 if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
3697 fprintf (file
, "\tldd\t[%s+%d], %s\n",
3698 base
, offset
+ 4 * n_regs
, reg_names
[i
]),
3701 fprintf (file
, "\tld\t[%s+%d], %s\n",
3702 base
, offset
+ 4 * n_regs
, reg_names
[i
]),
3704 else if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
3705 fprintf (file
, "\tld\t[%s+%d], %s\n",
3706 base
, offset
+ 4 * n_regs
+ 4, reg_names
[i
+1]),
3713 /* Compute the frame size required by the function. This function is called
3714 during the reload pass and also by output_function_prologue(). */
3717 compute_frame_size (size
, leaf_function
)
3722 int outgoing_args_size
= (current_function_outgoing_args_size
3723 + REG_PARM_STACK_SPACE (current_function_decl
));
3725 /* N_REGS is the number of 4-byte regs saved thus far. This applies
3726 even to v9 int regs to be consistent with save_regs/restore_regs. */
3730 for (i
= 0; i
< 8; i
++)
3731 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3736 for (i
= 0; i
< 8; i
+= 2)
3737 if ((regs_ever_live
[i
] && ! call_used_regs
[i
])
3738 || (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1]))
3742 for (i
= 32; i
< (TARGET_V9
? 96 : 64); i
+= 2)
3743 if ((regs_ever_live
[i
] && ! call_used_regs
[i
])
3744 || (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1]))
3747 /* Set up values for use in `function_epilogue'. */
3748 num_gfregs
= n_regs
;
3750 if (leaf_function
&& n_regs
== 0
3751 && size
== 0 && current_function_outgoing_args_size
== 0)
3753 actual_fsize
= apparent_fsize
= 0;
3757 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
3758 apparent_fsize
= (size
- STARTING_FRAME_OFFSET
+ 7) & -8;
3759 apparent_fsize
+= n_regs
* 4;
3760 actual_fsize
= apparent_fsize
+ ((outgoing_args_size
+ 7) & -8);
3763 /* Make sure nothing can clobber our register windows.
3764 If a SAVE must be done, or there is a stack-local variable,
3765 the register window area must be allocated.
3766 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
3767 if (leaf_function
== 0 || size
> 0)
3768 actual_fsize
+= (16 * UNITS_PER_WORD
) + (TARGET_ARCH64
? 0 : 8);
3770 return SPARC_STACK_ALIGN (actual_fsize
);
3773 /* Build a (32 bit) big number in a register. */
3774 /* ??? We may be able to use the set macro here too. */
3777 build_big_number (file
, num
, reg
)
3782 if (num
>= 0 || ! TARGET_ARCH64
)
3784 fprintf (file
, "\tsethi\t%%hi(%d), %s\n", num
, reg
);
3785 if ((num
& 0x3ff) != 0)
3786 fprintf (file
, "\tor\t%s, %%lo(%d), %s\n", reg
, num
, reg
);
3788 else /* num < 0 && TARGET_ARCH64 */
3790 /* Sethi does not sign extend, so we must use a little trickery
3791 to use it for negative numbers. Invert the constant before
3792 loading it in, then use xor immediate to invert the loaded bits
3793 (along with the upper 32 bits) to the desired constant. This
3794 works because the sethi and immediate fields overlap. */
3797 int low
= -0x400 + (asize
& 0x3FF);
3799 fprintf (file
, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n",
3800 inv
, reg
, reg
, low
, reg
);
3804 /* Output any necessary .register pseudo-ops. */
3806 sparc_output_scratch_registers (file
)
3807 FILE *file ATTRIBUTE_UNUSED
;
3809 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
3815 /* Check if %g[2367] were used without
3816 .register being printed for them already. */
3817 for (i
= 2; i
< 8; i
++)
3819 if (regs_ever_live
[i
]
3820 && ! sparc_hard_reg_printed
[i
])
3822 sparc_hard_reg_printed
[i
] = 1;
3823 fprintf (file
, "\t.register\t%%g%d, #scratch\n", i
);
3830 /* This function generates the assembly code for function entry.
3831 FILE is a stdio stream to output the code to.
3832 SIZE is an int: how many units of temporary storage to allocate.
3833 Refer to the array `regs_ever_live' to determine which registers
3834 to save; `regs_ever_live[I]' is nonzero if register number I
3835 is ever used in the function. This macro is responsible for
3836 knowing which registers should not be saved even if used. */
3838 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
3839 of memory. If any fpu reg is used in the function, we allocate
3840 such a block here, at the bottom of the frame, just in case it's needed.
3842 If this function is a leaf procedure, then we may choose not
3843 to do a "save" insn. The decision about whether or not
3844 to do this is made in regclass.c. */
3847 sparc_output_function_prologue (file
, size
)
3852 sparc_flat_function_prologue (file
, size
);
3854 sparc_nonflat_function_prologue (file
, size
,
3855 current_function_uses_only_leaf_regs
);
3858 /* Output code for the function prologue. */
3861 sparc_nonflat_function_prologue (file
, size
, leaf_function
)
3866 sparc_output_scratch_registers (file
);
3868 /* Need to use actual_fsize, since we are also allocating
3869 space for our callee (and our own register save area). */
3870 actual_fsize
= compute_frame_size (size
, leaf_function
);
3874 frame_base_name
= "%sp";
3875 frame_base_offset
= actual_fsize
+ SPARC_STACK_BIAS
;
3879 frame_base_name
= "%fp";
3880 frame_base_offset
= SPARC_STACK_BIAS
;
3883 /* This is only for the human reader. */
3884 fprintf (file
, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START
);
3886 if (actual_fsize
== 0)
3888 else if (! leaf_function
)
3890 if (actual_fsize
<= 4096)
3891 fprintf (file
, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize
);
3892 else if (actual_fsize
<= 8192)
3894 fprintf (file
, "\tsave\t%%sp, -4096, %%sp\n");
3895 fprintf (file
, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize
- 4096);
3899 build_big_number (file
, -actual_fsize
, "%g1");
3900 fprintf (file
, "\tsave\t%%sp, %%g1, %%sp\n");
3903 else /* leaf function */
3905 if (actual_fsize
<= 4096)
3906 fprintf (file
, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize
);
3907 else if (actual_fsize
<= 8192)
3909 fprintf (file
, "\tadd\t%%sp, -4096, %%sp\n");
3910 fprintf (file
, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize
- 4096);
3914 build_big_number (file
, -actual_fsize
, "%g1");
3915 fprintf (file
, "\tadd\t%%sp, %%g1, %%sp\n");
3919 if (dwarf2out_do_frame () && actual_fsize
)
3921 char *label
= dwarf2out_cfi_label ();
3923 /* The canonical frame address refers to the top of the frame. */
3924 dwarf2out_def_cfa (label
, (leaf_function
? STACK_POINTER_REGNUM
3925 : HARD_FRAME_POINTER_REGNUM
),
3928 if (! leaf_function
)
3930 /* Note the register window save. This tells the unwinder that
3931 it needs to restore the window registers from the previous
3932 frame's window save area at 0(cfa). */
3933 dwarf2out_window_save (label
);
3935 /* The return address (-8) is now in %i7. */
3936 dwarf2out_return_reg (label
, 31);
3940 /* If doing anything with PIC, do it now. */
3942 fprintf (file
, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START
);
3944 /* Call saved registers are saved just above the outgoing argument area. */
3947 int offset
, real_offset
, n_regs
;
3950 real_offset
= -apparent_fsize
;
3951 offset
= -apparent_fsize
+ frame_base_offset
;
3952 if (offset
< -4096 || offset
+ num_gfregs
* 4 > 4096)
3954 /* ??? This might be optimized a little as %g1 might already have a
3955 value close enough that a single add insn will do. */
3956 /* ??? Although, all of this is probably only a temporary fix
3957 because if %g1 can hold a function result, then
3958 output_function_epilogue will lose (the result will get
3960 build_big_number (file
, offset
, "%g1");
3961 fprintf (file
, "\tadd\t%s, %%g1, %%g1\n", frame_base_name
);
3967 base
= frame_base_name
;
3970 n_regs
= save_regs (file
, 0, 8, base
, offset
, 0, real_offset
);
3971 save_regs (file
, 32, TARGET_V9
? 96 : 64, base
, offset
, n_regs
,
3976 /* Output code to restore any call saved registers. */
3979 output_restore_regs (file
, leaf_function
)
3981 int leaf_function ATTRIBUTE_UNUSED
;
3986 offset
= -apparent_fsize
+ frame_base_offset
;
3987 if (offset
< -4096 || offset
+ num_gfregs
* 4 > 4096 - 8 /*double*/)
3989 build_big_number (file
, offset
, "%g1");
3990 fprintf (file
, "\tadd\t%s, %%g1, %%g1\n", frame_base_name
);
3996 base
= frame_base_name
;
3999 n_regs
= restore_regs (file
, 0, 8, base
, offset
, 0);
4000 restore_regs (file
, 32, TARGET_V9
? 96 : 64, base
, offset
, n_regs
);
4003 /* This function generates the assembly code for function exit,
4004 on machines that need it.
4006 The function epilogue should not depend on the current stack pointer!
4007 It should use the frame pointer only. This is mandatory because
4008 of alloca; we also take advantage of it to omit stack adjustments
4009 before returning. */
4012 sparc_output_function_epilogue (file
, size
)
4017 sparc_flat_function_epilogue (file
, size
);
4019 sparc_nonflat_function_epilogue (file
, size
,
4020 current_function_uses_only_leaf_regs
);
4023 /* Output code for the function epilogue. */
4026 sparc_nonflat_function_epilogue (file
, size
, leaf_function
)
4028 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
4033 if (current_function_epilogue_delay_list
== 0)
4035 /* If code does not drop into the epilogue, we need
4036 do nothing except output pending case vectors.
4038 We have to still output a dummy nop for the sake of
4039 sane backtraces. Otherwise, if the last two instructions
4040 of a function were call foo; dslot; this can make the return
4041 PC of foo (ie. address of call instruction plus 8) point to
4042 the first instruction in the next function. */
4045 fputs("\tnop\n", file
);
4047 insn
= get_last_insn ();
4048 if (GET_CODE (insn
) == NOTE
)
4049 insn
= prev_nonnote_insn (insn
);
4050 if (insn
&& GET_CODE (insn
) == BARRIER
)
4051 goto output_vectors
;
4055 output_restore_regs (file
, leaf_function
);
4057 /* Work out how to skip the caller's unimp instruction if required. */
4059 ret
= (SKIP_CALLERS_UNIMP_P
? "jmp\t%o7+12" : "retl");
4061 ret
= (SKIP_CALLERS_UNIMP_P
? "jmp\t%i7+12" : "ret");
4063 if (! leaf_function
)
4065 if (current_function_calls_eh_return
)
4067 if (current_function_epilogue_delay_list
)
4069 if (SKIP_CALLERS_UNIMP_P
)
4072 fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file
);
4074 /* If we wound up with things in our delay slot, flush them here. */
4075 else if (current_function_epilogue_delay_list
)
4077 rtx delay
= PATTERN (XEXP (current_function_epilogue_delay_list
, 0));
4079 if (TARGET_V9
&& ! epilogue_renumber (&delay
, 1))
4081 epilogue_renumber (&delay
, 0);
4082 fputs (SKIP_CALLERS_UNIMP_P
4083 ? "\treturn\t%i7+12\n"
4084 : "\treturn\t%i7+8\n", file
);
4085 final_scan_insn (XEXP (current_function_epilogue_delay_list
, 0),
4092 if (GET_CODE (delay
) != SET
)
4095 src
= SET_SRC (delay
);
4096 if (GET_CODE (src
) == ASHIFT
)
4098 if (XEXP (src
, 1) != const1_rtx
)
4101 = gen_rtx_PLUS (GET_MODE (src
), XEXP (src
, 0),
4105 insn
= gen_rtx_PARALLEL (VOIDmode
,
4106 gen_rtvec (2, delay
,
4107 gen_rtx_RETURN (VOIDmode
)));
4108 insn
= emit_jump_insn (insn
);
4110 sparc_emitting_epilogue
= true;
4111 final_scan_insn (insn
, file
, 1, 0, 1);
4112 sparc_emitting_epilogue
= false;
4115 else if (TARGET_V9
&& ! SKIP_CALLERS_UNIMP_P
)
4116 fputs ("\treturn\t%i7+8\n\tnop\n", file
);
4118 fprintf (file
, "\t%s\n\trestore\n", ret
);
4120 /* All of the following cases are for leaf functions. */
4121 else if (current_function_calls_eh_return
)
4123 else if (current_function_epilogue_delay_list
)
4125 /* eligible_for_epilogue_delay_slot ensures that if this is a
4126 leaf function, then we will only have insn in the delay slot
4127 if the frame size is zero, thus no adjust for the stack is
4129 if (actual_fsize
!= 0)
4131 fprintf (file
, "\t%s\n", ret
);
4132 final_scan_insn (XEXP (current_function_epilogue_delay_list
, 0),
4135 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
4136 avoid generating confusing assembly language output. */
4137 else if (actual_fsize
== 0)
4138 fprintf (file
, "\t%s\n\tnop\n", ret
);
4139 else if (actual_fsize
<= 4096)
4140 fprintf (file
, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret
, actual_fsize
);
4141 else if (actual_fsize
<= 8192)
4142 fprintf (file
, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n",
4143 ret
, actual_fsize
- 4096);
4144 else if ((actual_fsize
& 0x3ff) == 0)
4145 fprintf (file
, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
4148 fprintf (file
, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
4149 actual_fsize
, actual_fsize
, ret
);
4152 sparc_output_deferred_case_vectors ();
4155 /* Output a sibling call. */
4158 output_sibcall (insn
, call_operand
)
4159 rtx insn
, call_operand
;
4161 int leaf_regs
= current_function_uses_only_leaf_regs
;
4163 int delay_slot
= dbr_sequence_length () > 0;
4167 /* Call to restore global regs might clobber
4168 the delay slot. Instead of checking for this
4169 output the delay slot now. */
4172 rtx delay
= NEXT_INSN (insn
);
4177 final_scan_insn (delay
, asm_out_file
, 1, 0, 1);
4178 PATTERN (delay
) = gen_blockage ();
4179 INSN_CODE (delay
) = -1;
4182 output_restore_regs (asm_out_file
, leaf_regs
);
4185 operands
[0] = call_operand
;
4189 #ifdef HAVE_AS_RELAX_OPTION
4190 /* If as and ld are relaxing tail call insns into branch always,
4191 use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can
4192 be optimized. With sethi/jmpl as nor ld has no easy way how to
4193 find out if somebody does not branch between the sethi and jmpl. */
4196 int spare_slot
= ((TARGET_ARCH32
|| TARGET_CM_MEDLOW
) && ! flag_pic
);
4200 if ((actual_fsize
|| ! spare_slot
) && delay_slot
)
4202 rtx delay
= NEXT_INSN (insn
);
4207 final_scan_insn (delay
, asm_out_file
, 1, 0, 1);
4208 PATTERN (delay
) = gen_blockage ();
4209 INSN_CODE (delay
) = -1;
4214 if (actual_fsize
<= 4096)
4215 size
= actual_fsize
;
4216 else if (actual_fsize
<= 8192)
4218 fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file
);
4219 size
= actual_fsize
- 4096;
4221 else if ((actual_fsize
& 0x3ff) == 0)
4222 fprintf (asm_out_file
,
4223 "\tsethi\t%%hi(%d), %%g1\n\tadd\t%%sp, %%g1, %%sp\n",
4227 fprintf (asm_out_file
,
4228 "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n",
4229 actual_fsize
, actual_fsize
);
4230 fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file
);
4235 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands
);
4236 output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands
);
4238 fprintf (asm_out_file
, "\t sub\t%%sp, -%d, %%sp\n", size
);
4239 else if (! delay_slot
)
4240 fputs ("\t nop\n", asm_out_file
);
4245 fprintf (asm_out_file
, "\tsub\t%%sp, -%d, %%sp\n", size
);
4246 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4247 it into branch if possible. */
4248 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands
);
4249 output_asm_insn ("call\t%a0, 0", operands
);
4250 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands
);
4255 output_asm_insn ("call\t%a0, 0", operands
);
4258 rtx delay
= NEXT_INSN (insn
), pat
;
4263 pat
= PATTERN (delay
);
4264 if (GET_CODE (pat
) != SET
)
4267 operands
[0] = SET_DEST (pat
);
4268 pat
= SET_SRC (pat
);
4269 switch (GET_CODE (pat
))
4272 operands
[1] = XEXP (pat
, 0);
4273 operands
[2] = XEXP (pat
, 1);
4274 output_asm_insn (" restore %r1, %2, %Y0", operands
);
4277 operands
[1] = XEXP (pat
, 0);
4278 operands
[2] = XEXP (pat
, 1);
4279 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands
);
4282 operands
[1] = XEXP (pat
, 0);
4283 output_asm_insn (" restore %r1, %r1, %Y0", operands
);
4287 output_asm_insn (" restore %%g0, %1, %Y0", operands
);
4290 PATTERN (delay
) = gen_blockage ();
4291 INSN_CODE (delay
) = -1;
4294 fputs ("\t restore\n", asm_out_file
);
4298 /* Functions for handling argument passing.
4300 For v8 the first six args are normally in registers and the rest are
4301 pushed. Any arg that starts within the first 6 words is at least
4302 partially passed in a register unless its data type forbids.
4304 For v9, the argument registers are laid out as an array of 16 elements
4305 and arguments are added sequentially. The first 6 int args and up to the
4306 first 16 fp args (depending on size) are passed in regs.
4308 Slot Stack Integral Float Float in structure Double Long Double
4309 ---- ----- -------- ----- ------------------ ------ -----------
4310 15 [SP+248] %f31 %f30,%f31 %d30
4311 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4312 13 [SP+232] %f27 %f26,%f27 %d26
4313 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4314 11 [SP+216] %f23 %f22,%f23 %d22
4315 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4316 9 [SP+200] %f19 %f18,%f19 %d18
4317 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4318 7 [SP+184] %f15 %f14,%f15 %d14
4319 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4320 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4321 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4322 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4323 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4324 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4325 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4327 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4329 Integral arguments are always passed as 64 bit quantities appropriately
4332 Passing of floating point values is handled as follows.
4333 If a prototype is in scope:
4334 If the value is in a named argument (i.e. not a stdarg function or a
4335 value not part of the `...') then the value is passed in the appropriate
4337 If the value is part of the `...' and is passed in one of the first 6
4338 slots then the value is passed in the appropriate int reg.
4339 If the value is part of the `...' and is not passed in one of the first 6
4340 slots then the value is passed in memory.
4341 If a prototype is not in scope:
4342 If the value is one of the first 6 arguments the value is passed in the
4343 appropriate integer reg and the appropriate fp reg.
4344 If the value is not one of the first 6 arguments the value is passed in
4345 the appropriate fp reg and in memory.
4348 /* Maximum number of int regs for args. */
4349 #define SPARC_INT_ARG_MAX 6
4350 /* Maximum number of fp regs for args. */
4351 #define SPARC_FP_ARG_MAX 16
4353 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4355 /* Handle the INIT_CUMULATIVE_ARGS macro.
4356 Initialize a variable CUM of type CUMULATIVE_ARGS
4357 for a call to a function whose data type is FNTYPE.
4358 For a library call, FNTYPE is 0. */
4361 init_cumulative_args (cum
, fntype
, libname
, indirect
)
4362 CUMULATIVE_ARGS
*cum
;
4364 rtx libname ATTRIBUTE_UNUSED
;
4365 int indirect ATTRIBUTE_UNUSED
;
4368 cum
->prototype_p
= fntype
&& TYPE_ARG_TYPES (fntype
);
4369 cum
->libcall_p
= fntype
== 0;
4372 /* Compute the slot number to pass an argument in.
4373 Returns the slot number or -1 if passing on the stack.
4375 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4376 the preceding args and about the function being called.
4377 MODE is the argument's machine mode.
4378 TYPE is the data type of the argument (as a tree).
4379 This is null for libcalls where that information may
4381 NAMED is nonzero if this argument is a named parameter
4382 (otherwise it is an extra parameter matching an ellipsis).
4383 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
4384 *PREGNO records the register number to use if scalar type.
4385 *PPADDING records the amount of padding needed in words. */
4388 function_arg_slotno (cum
, mode
, type
, named
, incoming_p
, pregno
, ppadding
)
4389 const CUMULATIVE_ARGS
*cum
;
4390 enum machine_mode mode
;
4397 int regbase
= (incoming_p
4398 ? SPARC_INCOMING_INT_ARG_FIRST
4399 : SPARC_OUTGOING_INT_ARG_FIRST
);
4400 int slotno
= cum
->words
;
4405 if (type
!= 0 && TREE_ADDRESSABLE (type
))
4408 && type
!= 0 && mode
== BLKmode
4409 && TYPE_ALIGN (type
) % PARM_BOUNDARY
!= 0)
4415 /* MODE is VOIDmode when generating the actual call.
4419 case QImode
: case CQImode
:
4420 case HImode
: case CHImode
:
4421 case SImode
: case CSImode
:
4422 case DImode
: case CDImode
:
4423 case TImode
: case CTImode
:
4424 if (slotno
>= SPARC_INT_ARG_MAX
)
4426 regno
= regbase
+ slotno
;
4429 case SFmode
: case SCmode
:
4430 case DFmode
: case DCmode
:
4431 case TFmode
: case TCmode
:
4434 if (slotno
>= SPARC_INT_ARG_MAX
)
4436 regno
= regbase
+ slotno
;
4440 if ((mode
== TFmode
|| mode
== TCmode
)
4441 && (slotno
& 1) != 0)
4442 slotno
++, *ppadding
= 1;
4443 if (TARGET_FPU
&& named
)
4445 if (slotno
>= SPARC_FP_ARG_MAX
)
4447 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
4453 if (slotno
>= SPARC_INT_ARG_MAX
)
4455 regno
= regbase
+ slotno
;
4461 /* For sparc64, objects requiring 16 byte alignment get it. */
4464 if (type
&& TYPE_ALIGN (type
) == 128 && (slotno
& 1) != 0)
4465 slotno
++, *ppadding
= 1;
4469 || (type
&& TREE_CODE (type
) == UNION_TYPE
))
4471 if (slotno
>= SPARC_INT_ARG_MAX
)
4473 regno
= regbase
+ slotno
;
4478 int intregs_p
= 0, fpregs_p
= 0;
4479 /* The ABI obviously doesn't specify how packed
4480 structures are passed. These are defined to be passed
4481 in int regs if possible, otherwise memory. */
4484 /* First see what kinds of registers we need. */
4485 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4487 if (TREE_CODE (field
) == FIELD_DECL
)
4489 if (TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
4494 if (DECL_PACKED (field
))
4498 if (packed_p
|| !named
)
4499 fpregs_p
= 0, intregs_p
= 1;
4501 /* If all arg slots are filled, then must pass on stack. */
4502 if (fpregs_p
&& slotno
>= SPARC_FP_ARG_MAX
)
4504 /* If there are only int args and all int arg slots are filled,
4505 then must pass on stack. */
4506 if (!fpregs_p
&& intregs_p
&& slotno
>= SPARC_INT_ARG_MAX
)
4508 /* Note that even if all int arg slots are filled, fp members may
4509 still be passed in regs if such regs are available.
4510 *PREGNO isn't set because there may be more than one, it's up
4511 to the caller to compute them. */
4524 /* Handle recursive register counting for structure field layout. */
4526 struct function_arg_record_value_parms
4529 int slotno
, named
, regbase
;
4534 static void function_arg_record_value_3
4535 PARAMS ((HOST_WIDE_INT
, struct function_arg_record_value_parms
*));
4536 static void function_arg_record_value_2
4537 PARAMS ((tree
, HOST_WIDE_INT
,
4538 struct function_arg_record_value_parms
*));
4539 static void function_arg_record_value_1
4540 PARAMS ((tree
, HOST_WIDE_INT
,
4541 struct function_arg_record_value_parms
*));
4542 static rtx function_arg_record_value
4543 PARAMS ((tree
, enum machine_mode
, int, int, int));
4545 /* A subroutine of function_arg_record_value. Traverse the structure
4546 recusively and determine how many registers will be required. */
4549 function_arg_record_value_1 (type
, startbitpos
, parms
)
4551 HOST_WIDE_INT startbitpos
;
4552 struct function_arg_record_value_parms
*parms
;
4556 /* The ABI obviously doesn't specify how packed structures are
4557 passed. These are defined to be passed in int regs if possible,
4558 otherwise memory. */
4561 /* We need to compute how many registers are needed so we can
4562 allocate the PARALLEL but before we can do that we need to know
4563 whether there are any packed fields. If there are, int regs are
4564 used regardless of whether there are fp values present. */
4565 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4567 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
4574 /* Compute how many registers we need. */
4575 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4577 if (TREE_CODE (field
) == FIELD_DECL
)
4579 HOST_WIDE_INT bitpos
= startbitpos
;
4581 if (DECL_SIZE (field
) != 0
4582 && host_integerp (bit_position (field
), 1))
4583 bitpos
+= int_bit_position (field
);
4585 /* ??? FIXME: else assume zero offset. */
4587 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
4588 function_arg_record_value_1 (TREE_TYPE (field
), bitpos
, parms
);
4589 else if ((TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
4590 || (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
4591 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field
)))
4597 if (parms
->intoffset
!= -1)
4599 int intslots
, this_slotno
;
4601 intslots
= (bitpos
- parms
->intoffset
+ BITS_PER_WORD
- 1)
4603 this_slotno
= parms
->slotno
+ parms
->intoffset
4606 intslots
= MIN (intslots
, SPARC_INT_ARG_MAX
- this_slotno
);
4607 intslots
= MAX (intslots
, 0);
4608 parms
->nregs
+= intslots
;
4609 parms
->intoffset
= -1;
4612 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
4613 If it wasn't true we wouldn't be here. */
4615 if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
4620 if (parms
->intoffset
== -1)
4621 parms
->intoffset
= bitpos
;
4627 /* A subroutine of function_arg_record_value. Assign the bits of the
4628 structure between parms->intoffset and bitpos to integer registers. */
4631 function_arg_record_value_3 (bitpos
, parms
)
4632 HOST_WIDE_INT bitpos
;
4633 struct function_arg_record_value_parms
*parms
;
4635 enum machine_mode mode
;
4637 unsigned int startbit
, endbit
;
4638 int this_slotno
, intslots
, intoffset
;
4641 if (parms
->intoffset
== -1)
4644 intoffset
= parms
->intoffset
;
4645 parms
->intoffset
= -1;
4647 startbit
= intoffset
& -BITS_PER_WORD
;
4648 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
4649 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
4650 this_slotno
= parms
->slotno
+ intoffset
/ BITS_PER_WORD
;
4652 intslots
= MIN (intslots
, SPARC_INT_ARG_MAX
- this_slotno
);
4656 /* If this is the trailing part of a word, only load that much into
4657 the register. Otherwise load the whole register. Note that in
4658 the latter case we may pick up unwanted bits. It's not a problem
4659 at the moment but may wish to revisit. */
4661 if (intoffset
% BITS_PER_WORD
!= 0)
4662 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
4667 intoffset
/= BITS_PER_UNIT
;
4670 regno
= parms
->regbase
+ this_slotno
;
4671 reg
= gen_rtx_REG (mode
, regno
);
4672 XVECEXP (parms
->ret
, 0, parms
->nregs
)
4673 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
4676 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
4680 while (intslots
> 0);
4683 /* A subroutine of function_arg_record_value. Traverse the structure
4684 recursively and assign bits to floating point registers. Track which
4685 bits in between need integer registers; invoke function_arg_record_value_3
4686 to make that happen. */
4689 function_arg_record_value_2 (type
, startbitpos
, parms
)
4691 HOST_WIDE_INT startbitpos
;
4692 struct function_arg_record_value_parms
*parms
;
4697 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4699 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
4706 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4708 if (TREE_CODE (field
) == FIELD_DECL
)
4710 HOST_WIDE_INT bitpos
= startbitpos
;
4712 if (DECL_SIZE (field
) != 0
4713 && host_integerp (bit_position (field
), 1))
4714 bitpos
+= int_bit_position (field
);
4716 /* ??? FIXME: else assume zero offset. */
4718 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
4719 function_arg_record_value_2 (TREE_TYPE (field
), bitpos
, parms
);
4720 else if ((TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
4721 || (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
4722 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field
)))
4728 int this_slotno
= parms
->slotno
+ bitpos
/ BITS_PER_WORD
;
4730 enum machine_mode mode
= DECL_MODE (field
);
4733 function_arg_record_value_3 (bitpos
, parms
);
4734 regno
= SPARC_FP_ARG_FIRST
+ this_slotno
* 2
4735 + ((mode
== SFmode
|| mode
== SCmode
)
4736 && (bitpos
& 32) != 0);
4739 case SCmode
: mode
= SFmode
; break;
4740 case DCmode
: mode
= DFmode
; break;
4741 case TCmode
: mode
= TFmode
; break;
4744 reg
= gen_rtx_REG (mode
, regno
);
4745 XVECEXP (parms
->ret
, 0, parms
->nregs
)
4746 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
4747 GEN_INT (bitpos
/ BITS_PER_UNIT
));
4749 if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
4751 regno
+= GET_MODE_SIZE (mode
) / 4;
4752 reg
= gen_rtx_REG (mode
, regno
);
4753 XVECEXP (parms
->ret
, 0, parms
->nregs
)
4754 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
4755 GEN_INT ((bitpos
+ GET_MODE_BITSIZE (mode
))
4762 if (parms
->intoffset
== -1)
4763 parms
->intoffset
= bitpos
;
4769 /* Used by function_arg and function_value to implement the complex
4770 Sparc64 structure calling conventions. */
4773 function_arg_record_value (type
, mode
, slotno
, named
, regbase
)
4775 enum machine_mode mode
;
4776 int slotno
, named
, regbase
;
4778 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
4779 struct function_arg_record_value_parms parms
;
4782 parms
.ret
= NULL_RTX
;
4783 parms
.slotno
= slotno
;
4784 parms
.named
= named
;
4785 parms
.regbase
= regbase
;
4787 /* Compute how many registers we need. */
4789 parms
.intoffset
= 0;
4790 function_arg_record_value_1 (type
, 0, &parms
);
4792 if (parms
.intoffset
!= -1)
4794 unsigned int startbit
, endbit
;
4795 int intslots
, this_slotno
;
4797 startbit
= parms
.intoffset
& -BITS_PER_WORD
;
4798 endbit
= (typesize
*BITS_PER_UNIT
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
4799 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
4800 this_slotno
= slotno
+ parms
.intoffset
/ BITS_PER_WORD
;
4802 intslots
= MIN (intslots
, SPARC_INT_ARG_MAX
- this_slotno
);
4803 intslots
= MAX (intslots
, 0);
4805 parms
.nregs
+= intslots
;
4807 nregs
= parms
.nregs
;
4809 /* Allocate the vector and handle some annoying special cases. */
4812 /* ??? Empty structure has no value? Duh? */
4815 /* Though there's nothing really to store, return a word register
4816 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
4817 leads to breakage due to the fact that there are zero bytes to
4819 return gen_rtx_REG (mode
, regbase
);
4823 /* ??? C++ has structures with no fields, and yet a size. Give up
4824 for now and pass everything back in integer registers. */
4825 nregs
= (typesize
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4827 if (nregs
+ slotno
> SPARC_INT_ARG_MAX
)
4828 nregs
= SPARC_INT_ARG_MAX
- slotno
;
4833 parms
.ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (nregs
));
4835 /* Fill in the entries. */
4837 parms
.intoffset
= 0;
4838 function_arg_record_value_2 (type
, 0, &parms
);
4839 function_arg_record_value_3 (typesize
* BITS_PER_UNIT
, &parms
);
4841 if (parms
.nregs
!= nregs
)
4847 /* Handle the FUNCTION_ARG macro.
4848 Determine where to put an argument to a function.
4849 Value is zero to push the argument on the stack,
4850 or a hard register in which to store the argument.
4852 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4853 the preceding args and about the function being called.
4854 MODE is the argument's machine mode.
4855 TYPE is the data type of the argument (as a tree).
4856 This is null for libcalls where that information may
4858 NAMED is nonzero if this argument is a named parameter
4859 (otherwise it is an extra parameter matching an ellipsis).
4860 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
4863 function_arg (cum
, mode
, type
, named
, incoming_p
)
4864 const CUMULATIVE_ARGS
*cum
;
4865 enum machine_mode mode
;
4870 int regbase
= (incoming_p
4871 ? SPARC_INCOMING_INT_ARG_FIRST
4872 : SPARC_OUTGOING_INT_ARG_FIRST
);
4873 int slotno
, regno
, padding
;
4876 slotno
= function_arg_slotno (cum
, mode
, type
, named
, incoming_p
,
4884 reg
= gen_rtx_REG (mode
, regno
);
4888 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
4889 but also have the slot allocated for them.
4890 If no prototype is in scope fp values in register slots get passed
4891 in two places, either fp regs and int regs or fp regs and memory. */
4892 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
4893 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4894 && SPARC_FP_REG_P (regno
))
4896 reg
= gen_rtx_REG (mode
, regno
);
4897 if (cum
->prototype_p
|| cum
->libcall_p
)
4899 /* "* 2" because fp reg numbers are recorded in 4 byte
4902 /* ??? This will cause the value to be passed in the fp reg and
4903 in the stack. When a prototype exists we want to pass the
4904 value in the reg but reserve space on the stack. That's an
4905 optimization, and is deferred [for a bit]. */
4906 if ((regno
- SPARC_FP_ARG_FIRST
) >= SPARC_INT_ARG_MAX
* 2)
4907 return gen_rtx_PARALLEL (mode
,
4909 gen_rtx_EXPR_LIST (VOIDmode
,
4910 NULL_RTX
, const0_rtx
),
4911 gen_rtx_EXPR_LIST (VOIDmode
,
4915 /* ??? It seems that passing back a register even when past
4916 the area declared by REG_PARM_STACK_SPACE will allocate
4917 space appropriately, and will not copy the data onto the
4918 stack, exactly as we desire.
4920 This is due to locate_and_pad_parm being called in
4921 expand_call whenever reg_parm_stack_space > 0, which
4922 while benefical to our example here, would seem to be
4923 in error from what had been intended. Ho hum... -- r~ */
4931 if ((regno
- SPARC_FP_ARG_FIRST
) < SPARC_INT_ARG_MAX
* 2)
4935 /* On incoming, we don't need to know that the value
4936 is passed in %f0 and %i0, and it confuses other parts
4937 causing needless spillage even on the simplest cases. */
4941 intreg
= (SPARC_OUTGOING_INT_ARG_FIRST
4942 + (regno
- SPARC_FP_ARG_FIRST
) / 2);
4944 v0
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
4945 v1
= gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (mode
, intreg
),
4947 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
4951 v0
= gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
4952 v1
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
4953 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
4957 else if (type
&& TREE_CODE (type
) == RECORD_TYPE
)
4959 /* Structures up to 16 bytes in size are passed in arg slots on the
4960 stack and are promoted to registers where possible. */
4962 if (int_size_in_bytes (type
) > 16)
4963 abort (); /* shouldn't get here */
4965 return function_arg_record_value (type
, mode
, slotno
, named
, regbase
);
4967 else if (type
&& TREE_CODE (type
) == UNION_TYPE
)
4969 enum machine_mode mode
;
4970 int bytes
= int_size_in_bytes (type
);
4975 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 0);
4976 reg
= gen_rtx_REG (mode
, regno
);
4980 /* Scalar or complex int. */
4981 reg
= gen_rtx_REG (mode
, regno
);
4987 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
4988 For an arg passed partly in registers and partly in memory,
4989 this is the number of registers used.
4990 For args passed entirely in registers or entirely in memory, zero.
4992 Any arg that starts in the first 6 regs but won't entirely fit in them
4993 needs partial registers on v8. On v9, structures with integer
4994 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
4995 values that begin in the last fp reg [where "last fp reg" varies with the
4996 mode] will be split between that reg and memory. */
4999 function_arg_partial_nregs (cum
, mode
, type
, named
)
5000 const CUMULATIVE_ARGS
*cum
;
5001 enum machine_mode mode
;
5005 int slotno
, regno
, padding
;
5007 /* We pass 0 for incoming_p here, it doesn't matter. */
5008 slotno
= function_arg_slotno (cum
, mode
, type
, named
, 0, ®no
, &padding
);
5015 if ((slotno
+ (mode
== BLKmode
5016 ? ROUND_ADVANCE (int_size_in_bytes (type
))
5017 : ROUND_ADVANCE (GET_MODE_SIZE (mode
))))
5018 > NPARM_REGS (SImode
))
5019 return NPARM_REGS (SImode
) - slotno
;
5024 if (type
&& AGGREGATE_TYPE_P (type
))
5026 int size
= int_size_in_bytes (type
);
5027 int align
= TYPE_ALIGN (type
);
5030 slotno
+= slotno
& 1;
5031 if (size
> 8 && size
<= 16
5032 && slotno
== SPARC_INT_ARG_MAX
- 1)
5035 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
5036 || (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5039 if (GET_MODE_ALIGNMENT (mode
) == 128)
5041 slotno
+= slotno
& 1;
5042 if (slotno
== SPARC_INT_ARG_MAX
- 2)
5047 if (slotno
== SPARC_INT_ARG_MAX
- 1)
5051 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5053 if (GET_MODE_ALIGNMENT (mode
) == 128)
5054 slotno
+= slotno
& 1;
5055 if ((slotno
+ GET_MODE_SIZE (mode
) / UNITS_PER_WORD
)
5063 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
5064 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
5065 quad-precision floats by invisible reference.
5066 v9: Aggregates greater than 16 bytes are passed by reference.
5067 For Pascal, also pass arrays by reference. */
5070 function_arg_pass_by_reference (cum
, mode
, type
, named
)
5071 const CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
;
5072 enum machine_mode mode
;
5074 int named ATTRIBUTE_UNUSED
;
5078 return ((type
&& AGGREGATE_TYPE_P (type
))
5079 || mode
== TFmode
|| mode
== TCmode
);
5083 return ((type
&& TREE_CODE (type
) == ARRAY_TYPE
)
5084 /* Consider complex values as aggregates, so care for TCmode. */
5085 || GET_MODE_SIZE (mode
) > 16
5087 && AGGREGATE_TYPE_P (type
)
5088 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 16));
5092 /* Handle the FUNCTION_ARG_ADVANCE macro.
5093 Update the data in CUM to advance over an argument
5094 of mode MODE and data type TYPE.
5095 TYPE is null for libcalls where that information may not be available. */
5098 function_arg_advance (cum
, mode
, type
, named
)
5099 CUMULATIVE_ARGS
*cum
;
5100 enum machine_mode mode
;
5104 int slotno
, regno
, padding
;
5106 /* We pass 0 for incoming_p here, it doesn't matter. */
5107 slotno
= function_arg_slotno (cum
, mode
, type
, named
, 0, ®no
, &padding
);
5109 /* If register required leading padding, add it. */
5111 cum
->words
+= padding
;
5115 cum
->words
+= (mode
!= BLKmode
5116 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
5117 : ROUND_ADVANCE (int_size_in_bytes (type
)));
5121 if (type
&& AGGREGATE_TYPE_P (type
))
5123 int size
= int_size_in_bytes (type
);
5127 else if (size
<= 16)
5129 else /* passed by reference */
5132 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
)
5136 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5138 cum
->words
+= GET_MODE_SIZE (mode
) / UNITS_PER_WORD
;
5142 cum
->words
+= (mode
!= BLKmode
5143 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
5144 : ROUND_ADVANCE (int_size_in_bytes (type
)));
5149 /* Handle the FUNCTION_ARG_PADDING macro.
5150 For the 64 bit ABI structs are always stored left shifted in their
5154 function_arg_padding (mode
, type
)
5155 enum machine_mode mode
;
5158 if (TARGET_ARCH64
&& type
!= 0 && AGGREGATE_TYPE_P (type
))
5161 /* This is the default definition. */
5162 return (! BYTES_BIG_ENDIAN
5165 ? (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
5166 && int_size_in_bytes (type
) < (PARM_BOUNDARY
/ BITS_PER_UNIT
))
5167 : GET_MODE_BITSIZE (mode
) < PARM_BOUNDARY
)
5168 ? downward
: upward
));
5171 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5172 For v9, function return values are subject to the same rules as arguments,
5173 except that up to 32-bytes may be returned in registers. */
5176 function_value (type
, mode
, incoming_p
)
5178 enum machine_mode mode
;
5182 int regbase
= (incoming_p
5183 ? SPARC_OUTGOING_INT_ARG_FIRST
5184 : SPARC_INCOMING_INT_ARG_FIRST
);
5186 if (TARGET_ARCH64
&& type
)
5188 if (TREE_CODE (type
) == RECORD_TYPE
)
5190 /* Structures up to 32 bytes in size are passed in registers,
5191 promoted to fp registers where possible. */
5193 if (int_size_in_bytes (type
) > 32)
5194 abort (); /* shouldn't get here */
5196 return function_arg_record_value (type
, mode
, 0, 1, regbase
);
5198 else if (AGGREGATE_TYPE_P (type
))
5200 /* All other aggregate types are passed in an integer register
5201 in a mode corresponding to the size of the type. */
5202 HOST_WIDE_INT bytes
= int_size_in_bytes (type
);
5207 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 0);
5212 && GET_MODE_CLASS (mode
) == MODE_INT
5213 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
5214 && type
&& ! AGGREGATE_TYPE_P (type
))
5218 regno
= BASE_RETURN_VALUE_REG (mode
);
5220 regno
= BASE_OUTGOING_VALUE_REG (mode
);
5222 return gen_rtx_REG (mode
, regno
);
5225 /* Do what is necessary for `va_start'. We look at the current function
5226 to determine if stdarg or varargs is used and return the address of
5227 the first unnamed parameter. */
5230 sparc_builtin_saveregs ()
5232 int first_reg
= current_function_args_info
.words
;
5236 for (regno
= first_reg
; regno
< NPARM_REGS (word_mode
); regno
++)
5237 emit_move_insn (gen_rtx_MEM (word_mode
,
5238 gen_rtx_PLUS (Pmode
,
5240 GEN_INT (FIRST_PARM_OFFSET (0)
5243 gen_rtx_REG (word_mode
,
5244 BASE_INCOMING_ARG_REG (word_mode
) + regno
));
5246 address
= gen_rtx_PLUS (Pmode
,
5248 GEN_INT (FIRST_PARM_OFFSET (0)
5249 + UNITS_PER_WORD
* first_reg
));
5254 /* Implement `va_start' for varargs and stdarg. */
5257 sparc_va_start (stdarg_p
, valist
, nextarg
)
5258 int stdarg_p ATTRIBUTE_UNUSED
;
5262 nextarg
= expand_builtin_saveregs ();
5263 std_expand_builtin_va_start (1, valist
, nextarg
);
5266 /* Implement `va_arg'. */
5269 sparc_va_arg (valist
, type
)
5272 HOST_WIDE_INT size
, rsize
, align
;
5277 /* Round up sizeof(type) to a word. */
5278 size
= int_size_in_bytes (type
);
5279 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
5284 if (TYPE_ALIGN (type
) >= 2 * (unsigned) BITS_PER_WORD
)
5285 align
= 2 * UNITS_PER_WORD
;
5287 if (AGGREGATE_TYPE_P (type
))
5289 if ((unsigned HOST_WIDE_INT
) size
> 16)
5292 size
= rsize
= UNITS_PER_WORD
;
5294 /* SPARC v9 ABI states that structures up to 8 bytes in size are
5295 given one 8 byte slot. */
5297 size
= rsize
= UNITS_PER_WORD
;
5304 if (AGGREGATE_TYPE_P (type
)
5305 || TYPE_MODE (type
) == TFmode
5306 || TYPE_MODE (type
) == TCmode
)
5309 size
= rsize
= UNITS_PER_WORD
;
5316 incr
= fold (build (PLUS_EXPR
, ptr_type_node
, incr
,
5317 build_int_2 (align
- 1, 0)));
5318 incr
= fold (build (BIT_AND_EXPR
, ptr_type_node
, incr
,
5319 build_int_2 (-align
, -1)));
5322 addr
= incr
= save_expr (incr
);
5323 if (BYTES_BIG_ENDIAN
&& size
< rsize
)
5325 addr
= fold (build (PLUS_EXPR
, ptr_type_node
, incr
,
5326 build_int_2 (rsize
- size
, 0)));
5328 incr
= fold (build (PLUS_EXPR
, ptr_type_node
, incr
,
5329 build_int_2 (rsize
, 0)));
5331 incr
= build (MODIFY_EXPR
, ptr_type_node
, valist
, incr
);
5332 TREE_SIDE_EFFECTS (incr
) = 1;
5333 expand_expr (incr
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5335 addr_rtx
= expand_expr (addr
, NULL
, Pmode
, EXPAND_NORMAL
);
5337 /* If the address isn't aligned properly for the type,
5338 we may need to copy to a temporary.
5339 FIXME: This is inefficient. Usually we can do this
5342 && TYPE_ALIGN (type
) > BITS_PER_WORD
5345 /* FIXME: We really need to specify that the temporary is live
5346 for the whole function because expand_builtin_va_arg wants
5347 the alias set to be get_varargs_alias_set (), but in this
5348 case the alias set is that for TYPE and if the memory gets
5349 reused it will be reused with alias set TYPE. */
5350 rtx tmp
= assign_temp (type
, 0, 1, 0);
5353 addr_rtx
= force_reg (Pmode
, addr_rtx
);
5354 addr_rtx
= gen_rtx_MEM (BLKmode
, addr_rtx
);
5355 set_mem_alias_set (addr_rtx
, get_varargs_alias_set ());
5356 set_mem_align (addr_rtx
, BITS_PER_WORD
);
5357 tmp
= shallow_copy_rtx (tmp
);
5358 PUT_MODE (tmp
, BLKmode
);
5359 set_mem_alias_set (tmp
, 0);
5361 dest_addr
= emit_block_move (tmp
, addr_rtx
, GEN_INT (rsize
));
5362 if (dest_addr
!= NULL_RTX
)
5363 addr_rtx
= dest_addr
;
5365 addr_rtx
= XCEXP (tmp
, 0, MEM
);
5370 addr_rtx
= force_reg (Pmode
, addr_rtx
);
5371 addr_rtx
= gen_rtx_MEM (Pmode
, addr_rtx
);
5372 set_mem_alias_set (addr_rtx
, get_varargs_alias_set ());
5378 /* Return the string to output a conditional branch to LABEL, which is
5379 the operand number of the label. OP is the conditional expression.
5380 XEXP (OP, 0) is assumed to be a condition code register (integer or
5381 floating point) and its mode specifies what kind of comparison we made.
5383 REVERSED is non-zero if we should reverse the sense of the comparison.
5385 ANNUL is non-zero if we should generate an annulling branch.
5387 NOOP is non-zero if we have to follow this branch by a noop.
5389 INSN, if set, is the insn. */
5392 output_cbranch (op
, dest
, label
, reversed
, annul
, noop
, insn
)
5395 int reversed
, annul
, noop
;
5398 static char string
[50];
5399 enum rtx_code code
= GET_CODE (op
);
5400 rtx cc_reg
= XEXP (op
, 0);
5401 enum machine_mode mode
= GET_MODE (cc_reg
);
5402 const char *labelno
, *branch
;
5403 int spaces
= 8, far
;
5406 /* v9 branches are limited to +-1MB. If it is too far away,
5419 fbne,a,pn %fcc2, .LC29
5427 far
= get_attr_length (insn
) >= 3;
5430 /* Reversal of FP compares takes care -- an ordered compare
5431 becomes an unordered compare and vice versa. */
5432 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
5433 code
= reverse_condition_maybe_unordered (code
);
5435 code
= reverse_condition (code
);
5438 /* Start by writing the branch condition. */
5439 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
5490 /* ??? !v9: FP branches cannot be preceded by another floating point
5491 insn. Because there is currently no concept of pre-delay slots,
5492 we can fix this only by always emitting a nop before a floating
5497 strcpy (string
, "nop\n\t");
5498 strcat (string
, branch
);
5511 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
5523 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
5544 strcpy (string
, branch
);
5546 spaces
-= strlen (branch
);
5547 p
= strchr (string
, '\0');
5549 /* Now add the annulling, the label, and a possible noop. */
5564 if (! far
&& insn
&& INSN_ADDRESSES_SET_P ())
5566 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
5567 - INSN_ADDRESSES (INSN_UID (insn
)));
5568 /* Leave some instructions for "slop". */
5569 if (delta
< -260000 || delta
>= 260000)
5573 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
5575 static char v9_fcc_labelno
[] = "%%fccX, ";
5576 /* Set the char indicating the number of the fcc reg to use. */
5577 v9_fcc_labelno
[5] = REGNO (cc_reg
) - SPARC_FIRST_V9_FCC_REG
+ '0';
5578 labelno
= v9_fcc_labelno
;
5581 if (REGNO (cc_reg
) == SPARC_FCC_REG
)
5587 else if (mode
== CCXmode
|| mode
== CCX_NOOVmode
)
5589 labelno
= "%%xcc, ";
5595 labelno
= "%%icc, ";
5600 if (*labelno
&& insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
5603 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
5613 strcpy (p
, labelno
);
5614 p
= strchr (p
, '\0');
5617 strcpy (p
, ".+12\n\tnop\n\tb\t");
5624 /* Set the char indicating the number of the operand containing the
5629 strcpy (p
, "\n\tnop");
5634 /* Emit a library call comparison between floating point X and Y.
5635 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
5636 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
5637 values as arguments instead of the TFmode registers themselves,
5638 that's why we cannot call emit_float_lib_cmp. */
5640 sparc_emit_float_lib_cmp (x
, y
, comparison
)
5642 enum rtx_code comparison
;
5645 rtx slot0
, slot1
, result
, tem
, tem2
;
5646 enum machine_mode mode
;
5651 qpfunc
= (TARGET_ARCH64
) ? "_Qp_feq" : "_Q_feq";
5655 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fne" : "_Q_fne";
5659 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fgt" : "_Q_fgt";
5663 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fge" : "_Q_fge";
5667 qpfunc
= (TARGET_ARCH64
) ? "_Qp_flt" : "_Q_flt";
5671 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fle" : "_Q_fle";
5682 qpfunc
= (TARGET_ARCH64
) ? "_Qp_cmp" : "_Q_cmp";
5692 if (GET_CODE (x
) != MEM
)
5694 slot0
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
5695 emit_insn (gen_rtx_SET (VOIDmode
, slot0
, x
));
5700 if (GET_CODE (y
) != MEM
)
5702 slot1
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
5703 emit_insn (gen_rtx_SET (VOIDmode
, slot1
, y
));
5708 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, qpfunc
), LCT_NORMAL
,
5710 XEXP (slot0
, 0), Pmode
,
5711 XEXP (slot1
, 0), Pmode
);
5717 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, qpfunc
), LCT_NORMAL
,
5719 x
, TFmode
, y
, TFmode
);
5725 /* Immediately move the result of the libcall into a pseudo
5726 register so reload doesn't clobber the value if it needs
5727 the return register for a spill reg. */
5728 result
= gen_reg_rtx (mode
);
5729 emit_move_insn (result
, hard_libcall_value (mode
));
5734 emit_cmp_insn (result
, const0_rtx
, NE
, NULL_RTX
, mode
, 0);
5738 emit_cmp_insn (result
, GEN_INT(3), comparison
== UNORDERED
? EQ
: NE
,
5743 emit_cmp_insn (result
, const1_rtx
,
5744 comparison
== UNGT
? GT
: NE
, NULL_RTX
, mode
, 0);
5747 emit_cmp_insn (result
, const2_rtx
, NE
, NULL_RTX
, mode
, 0);
5750 tem
= gen_reg_rtx (mode
);
5752 emit_insn (gen_andsi3 (tem
, result
, const1_rtx
));
5754 emit_insn (gen_anddi3 (tem
, result
, const1_rtx
));
5755 emit_cmp_insn (tem
, const0_rtx
, NE
, NULL_RTX
, mode
, 0);
5759 tem
= gen_reg_rtx (mode
);
5761 emit_insn (gen_addsi3 (tem
, result
, const1_rtx
));
5763 emit_insn (gen_adddi3 (tem
, result
, const1_rtx
));
5764 tem2
= gen_reg_rtx (mode
);
5766 emit_insn (gen_andsi3 (tem2
, tem
, const2_rtx
));
5768 emit_insn (gen_anddi3 (tem2
, tem
, const2_rtx
));
5769 emit_cmp_insn (tem2
, const0_rtx
, comparison
== UNEQ
? EQ
: NE
,
5775 /* Generate an unsigned DImode to FP conversion. This is the same code
5776 optabs would emit if we didn't have TFmode patterns. */
5779 sparc_emit_floatunsdi (operands
)
5782 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
5783 enum machine_mode mode
;
5786 in
= force_reg (DImode
, operands
[1]);
5787 mode
= GET_MODE (out
);
5788 neglab
= gen_label_rtx ();
5789 donelab
= gen_label_rtx ();
5790 i0
= gen_reg_rtx (DImode
);
5791 i1
= gen_reg_rtx (DImode
);
5792 f0
= gen_reg_rtx (mode
);
5794 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
5796 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
5797 emit_jump_insn (gen_jump (donelab
));
5800 emit_label (neglab
);
5802 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
5803 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
5804 emit_insn (gen_iordi3 (i0
, i0
, i1
));
5805 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
5806 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
5808 emit_label (donelab
);
5811 /* Return the string to output a conditional branch to LABEL, testing
5812 register REG. LABEL is the operand number of the label; REG is the
5813 operand number of the reg. OP is the conditional expression. The mode
5814 of REG says what kind of comparison we made.
5816 REVERSED is non-zero if we should reverse the sense of the comparison.
5818 ANNUL is non-zero if we should generate an annulling branch.
5820 NOOP is non-zero if we have to follow this branch by a noop. */
5823 output_v9branch (op
, dest
, reg
, label
, reversed
, annul
, noop
, insn
)
5826 int reversed
, annul
, noop
;
5829 static char string
[50];
5830 enum rtx_code code
= GET_CODE (op
);
5831 enum machine_mode mode
= GET_MODE (XEXP (op
, 0));
5836 /* branch on register are limited to +-128KB. If it is too far away,
5849 brgez,a,pn %o1, .LC29
5855 ba,pt %xcc, .LC29 */
5857 far
= get_attr_length (insn
) >= 3;
5859 /* If not floating-point or if EQ or NE, we can just reverse the code. */
5861 code
= reverse_condition (code
);
5863 /* Only 64 bit versions of these instructions exist. */
5867 /* Start by writing the branch condition. */
5872 strcpy (string
, "brnz");
5876 strcpy (string
, "brz");
5880 strcpy (string
, "brgez");
5884 strcpy (string
, "brlz");
5888 strcpy (string
, "brlez");
5892 strcpy (string
, "brgz");
5899 p
= strchr (string
, '\0');
5901 /* Now add the annulling, reg, label, and nop. */
5908 if (insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
5911 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
5916 *p
= p
< string
+ 8 ? '\t' : ' ';
5924 int veryfar
= 1, delta
;
5926 if (INSN_ADDRESSES_SET_P ())
5928 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
5929 - INSN_ADDRESSES (INSN_UID (insn
)));
5930 /* Leave some instructions for "slop". */
5931 if (delta
>= -260000 && delta
< 260000)
5935 strcpy (p
, ".+12\n\tnop\n\t");
5946 strcpy (p
, "ba,pt\t%%xcc, ");
5956 strcpy (p
, "\n\tnop");
5961 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
5962 Such instructions cannot be used in the delay slot of return insn on v9.
5963 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
5967 epilogue_renumber (where
, test
)
5968 register rtx
*where
;
5971 register const char *fmt
;
5973 register enum rtx_code code
;
5978 code
= GET_CODE (*where
);
5983 if (REGNO (*where
) >= 8 && REGNO (*where
) < 24) /* oX or lX */
5985 if (! test
&& REGNO (*where
) >= 24 && REGNO (*where
) < 32)
5986 *where
= gen_rtx (REG
, GET_MODE (*where
), OUTGOING_REGNO (REGNO(*where
)));
5994 /* Do not replace the frame pointer with the stack pointer because
5995 it can cause the delayed instruction to load below the stack.
5996 This occurs when instructions like:
5998 (set (reg/i:SI 24 %i0)
5999 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
6000 (const_int -20 [0xffffffec])) 0))
6002 are in the return delayed slot. */
6004 if (GET_CODE (XEXP (*where
, 0)) == REG
6005 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
6006 && (GET_CODE (XEXP (*where
, 1)) != CONST_INT
6007 || INTVAL (XEXP (*where
, 1)) < SPARC_STACK_BIAS
))
6012 if (SPARC_STACK_BIAS
6013 && GET_CODE (XEXP (*where
, 0)) == REG
6014 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
)
6022 fmt
= GET_RTX_FORMAT (code
);
6024 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
6029 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
6030 if (epilogue_renumber (&(XVECEXP (*where
, i
, j
)), test
))
6033 else if (fmt
[i
] == 'e'
6034 && epilogue_renumber (&(XEXP (*where
, i
)), test
))
6040 /* Leaf functions and non-leaf functions have different needs. */
6043 reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
6046 reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
6048 static const int *const reg_alloc_orders
[] = {
6049 reg_leaf_alloc_order
,
6050 reg_nonleaf_alloc_order
};
6053 order_regs_for_local_alloc ()
6055 static int last_order_nonleaf
= 1;
6057 if (regs_ever_live
[15] != last_order_nonleaf
)
6059 last_order_nonleaf
= !last_order_nonleaf
;
6060 memcpy ((char *) reg_alloc_order
,
6061 (const char *) reg_alloc_orders
[last_order_nonleaf
],
6062 FIRST_PSEUDO_REGISTER
* sizeof (int));
6066 /* Return 1 if REG and MEM are legitimate enough to allow the various
6067 mem<-->reg splits to be run. */
6070 sparc_splitdi_legitimate (reg
, mem
)
6074 /* Punt if we are here by mistake. */
6075 if (! reload_completed
)
6078 /* We must have an offsettable memory reference. */
6079 if (! offsettable_memref_p (mem
))
6082 /* If we have legitimate args for ldd/std, we do not want
6083 the split to happen. */
6084 if ((REGNO (reg
) % 2) == 0
6085 && mem_min_alignment (mem
, 8))
6092 /* Return 1 if x and y are some kind of REG and they refer to
6093 different hard registers. This test is guarenteed to be
6094 run after reload. */
6097 sparc_absnegfloat_split_legitimate (x
, y
)
6100 if (GET_CODE (x
) != REG
)
6102 if (GET_CODE (y
) != REG
)
6104 if (REGNO (x
) == REGNO (y
))
6109 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6110 This makes them candidates for using ldd and std insns.
6112 Note reg1 and reg2 *must* be hard registers. */
6115 registers_ok_for_ldd_peep (reg1
, reg2
)
6118 /* We might have been passed a SUBREG. */
6119 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
6122 if (REGNO (reg1
) % 2 != 0)
6125 /* Integer ldd is deprecated in SPARC V9 */
6126 if (TARGET_V9
&& REGNO (reg1
) < 32)
6129 return (REGNO (reg1
) == REGNO (reg2
) - 1);
6132 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
6135 This can only happen when addr1 and addr2, the addresses in mem1
6136 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
6137 addr1 must also be aligned on a 64-bit boundary.
6139 Also iff dependent_reg_rtx is not null it should not be used to
6140 compute the address for mem1, i.e. we cannot optimize a sequence
6152 But, note that the transformation from:
6157 is perfectly fine. Thus, the peephole2 patterns always pass us
6158 the destination register of the first load, never the second one.
6160 For stores we don't have a similar problem, so dependent_reg_rtx is
6164 mems_ok_for_ldd_peep (mem1
, mem2
, dependent_reg_rtx
)
6165 rtx mem1
, mem2
, dependent_reg_rtx
;
6171 /* The mems cannot be volatile. */
6172 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
6175 /* MEM1 should be aligned on a 64-bit boundary. */
6176 if (MEM_ALIGN (mem1
) < 64)
6179 addr1
= XEXP (mem1
, 0);
6180 addr2
= XEXP (mem2
, 0);
6182 /* Extract a register number and offset (if used) from the first addr. */
6183 if (GET_CODE (addr1
) == PLUS
)
6185 /* If not a REG, return zero. */
6186 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
6190 reg1
= REGNO (XEXP (addr1
, 0));
6191 /* The offset must be constant! */
6192 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
6194 offset1
= INTVAL (XEXP (addr1
, 1));
6197 else if (GET_CODE (addr1
) != REG
)
6201 reg1
= REGNO (addr1
);
6202 /* This was a simple (mem (reg)) expression. Offset is 0. */
6206 /* Make sure the second address is a (mem (plus (reg) (const_int). */
6207 if (GET_CODE (addr2
) != PLUS
)
6210 if (GET_CODE (XEXP (addr2
, 0)) != REG
6211 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
6214 if (reg1
!= REGNO (XEXP (addr2
, 0)))
6217 if (dependent_reg_rtx
!= NULL_RTX
&& reg1
== REGNO (dependent_reg_rtx
))
6220 /* The first offset must be evenly divisible by 8 to ensure the
6221 address is 64 bit aligned. */
6222 if (offset1
% 8 != 0)
6225 /* The offset for the second addr must be 4 more than the first addr. */
6226 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
6229 /* All the tests passed. addr1 and addr2 are valid for ldd and std
6234 /* Return 1 if reg is a pseudo, or is the first register in
6235 a hard register pair. This makes it a candidate for use in
6236 ldd and std insns. */
6239 register_ok_for_ldd (reg
)
6242 /* We might have been passed a SUBREG. */
6243 if (GET_CODE (reg
) != REG
)
6246 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
6247 return (REGNO (reg
) % 2 == 0);
6252 /* Print operand X (an rtx) in assembler syntax to file FILE.
6253 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
6254 For `%' followed by punctuation, CODE is the punctuation and X is null. */
6257 print_operand (file
, x
, code
)
6265 /* Output a 'nop' if there's nothing for the delay slot. */
6266 if (dbr_sequence_length () == 0)
6267 fputs ("\n\t nop", file
);
6270 /* Output an annul flag if there's nothing for the delay slot and we
6271 are optimizing. This is always used with '(' below. */
6272 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
6273 this is a dbx bug. So, we only do this when optimizing. */
6274 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
6275 Always emit a nop in case the next instruction is a branch. */
6276 if (dbr_sequence_length () == 0
6277 && (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
6281 /* Output a 'nop' if there's nothing for the delay slot and we are
6282 not optimizing. This is always used with '*' above. */
6283 if (dbr_sequence_length () == 0
6284 && ! (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
6285 fputs ("\n\t nop", file
);
6288 /* Output the Embedded Medium/Anywhere code model base register. */
6289 fputs (EMBMEDANY_BASE_REG
, file
);
6292 /* Print out what we are using as the frame pointer. This might
6293 be %fp, or might be %sp+offset. */
6294 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
6295 fprintf (file
, "%s+%d", frame_base_name
, frame_base_offset
);
6298 /* Adjust the operand to take into account a RESTORE operation. */
6299 if (GET_CODE (x
) == CONST_INT
)
6301 else if (GET_CODE (x
) != REG
)
6302 output_operand_lossage ("invalid %%Y operand");
6303 else if (REGNO (x
) < 8)
6304 fputs (reg_names
[REGNO (x
)], file
);
6305 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
6306 fputs (reg_names
[REGNO (x
)-16], file
);
6308 output_operand_lossage ("invalid %%Y operand");
6311 /* Print out the low order register name of a register pair. */
6312 if (WORDS_BIG_ENDIAN
)
6313 fputs (reg_names
[REGNO (x
)+1], file
);
6315 fputs (reg_names
[REGNO (x
)], file
);
6318 /* Print out the high order register name of a register pair. */
6319 if (WORDS_BIG_ENDIAN
)
6320 fputs (reg_names
[REGNO (x
)], file
);
6322 fputs (reg_names
[REGNO (x
)+1], file
);
6325 /* Print out the second register name of a register pair or quad.
6326 I.e., R (%o0) => %o1. */
6327 fputs (reg_names
[REGNO (x
)+1], file
);
6330 /* Print out the third register name of a register quad.
6331 I.e., S (%o0) => %o2. */
6332 fputs (reg_names
[REGNO (x
)+2], file
);
6335 /* Print out the fourth register name of a register quad.
6336 I.e., T (%o0) => %o3. */
6337 fputs (reg_names
[REGNO (x
)+3], file
);
6340 /* Print a condition code register. */
6341 if (REGNO (x
) == SPARC_ICC_REG
)
6343 /* We don't handle CC[X]_NOOVmode because they're not supposed
6345 if (GET_MODE (x
) == CCmode
)
6346 fputs ("%icc", file
);
6347 else if (GET_MODE (x
) == CCXmode
)
6348 fputs ("%xcc", file
);
6353 /* %fccN register */
6354 fputs (reg_names
[REGNO (x
)], file
);
6357 /* Print the operand's address only. */
6358 output_address (XEXP (x
, 0));
6361 /* In this case we need a register. Use %g0 if the
6362 operand is const0_rtx. */
6364 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
6366 fputs ("%g0", file
);
6373 switch (GET_CODE (x
))
6375 case IOR
: fputs ("or", file
); break;
6376 case AND
: fputs ("and", file
); break;
6377 case XOR
: fputs ("xor", file
); break;
6378 default: output_operand_lossage ("invalid %%A operand");
6383 switch (GET_CODE (x
))
6385 case IOR
: fputs ("orn", file
); break;
6386 case AND
: fputs ("andn", file
); break;
6387 case XOR
: fputs ("xnor", file
); break;
6388 default: output_operand_lossage ("invalid %%B operand");
6392 /* These are used by the conditional move instructions. */
6396 enum rtx_code rc
= GET_CODE (x
);
6400 enum machine_mode mode
= GET_MODE (XEXP (x
, 0));
6401 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
6402 rc
= reverse_condition_maybe_unordered (GET_CODE (x
));
6404 rc
= reverse_condition (GET_CODE (x
));
6408 case NE
: fputs ("ne", file
); break;
6409 case EQ
: fputs ("e", file
); break;
6410 case GE
: fputs ("ge", file
); break;
6411 case GT
: fputs ("g", file
); break;
6412 case LE
: fputs ("le", file
); break;
6413 case LT
: fputs ("l", file
); break;
6414 case GEU
: fputs ("geu", file
); break;
6415 case GTU
: fputs ("gu", file
); break;
6416 case LEU
: fputs ("leu", file
); break;
6417 case LTU
: fputs ("lu", file
); break;
6418 case LTGT
: fputs ("lg", file
); break;
6419 case UNORDERED
: fputs ("u", file
); break;
6420 case ORDERED
: fputs ("o", file
); break;
6421 case UNLT
: fputs ("ul", file
); break;
6422 case UNLE
: fputs ("ule", file
); break;
6423 case UNGT
: fputs ("ug", file
); break;
6424 case UNGE
: fputs ("uge", file
); break;
6425 case UNEQ
: fputs ("ue", file
); break;
6426 default: output_operand_lossage (code
== 'c'
6427 ? "invalid %%c operand"
6428 : "invalid %%C operand");
6433 /* These are used by the movr instruction pattern. */
6437 enum rtx_code rc
= (code
== 'd'
6438 ? reverse_condition (GET_CODE (x
))
6442 case NE
: fputs ("ne", file
); break;
6443 case EQ
: fputs ("e", file
); break;
6444 case GE
: fputs ("gez", file
); break;
6445 case LT
: fputs ("lz", file
); break;
6446 case LE
: fputs ("lez", file
); break;
6447 case GT
: fputs ("gz", file
); break;
6448 default: output_operand_lossage (code
== 'd'
6449 ? "invalid %%d operand"
6450 : "invalid %%D operand");
6457 /* Print a sign-extended character. */
6458 int i
= trunc_int_for_mode (INTVAL (x
), QImode
);
6459 fprintf (file
, "%d", i
);
6464 /* Operand must be a MEM; write its address. */
6465 if (GET_CODE (x
) != MEM
)
6466 output_operand_lossage ("invalid %%f operand");
6467 output_address (XEXP (x
, 0));
6471 /* Do nothing special. */
6475 /* Undocumented flag. */
6476 output_operand_lossage ("invalid operand output code");
6479 if (GET_CODE (x
) == REG
)
6480 fputs (reg_names
[REGNO (x
)], file
);
6481 else if (GET_CODE (x
) == MEM
)
6484 /* Poor Sun assembler doesn't understand absolute addressing. */
6485 if (CONSTANT_P (XEXP (x
, 0)))
6486 fputs ("%g0+", file
);
6487 output_address (XEXP (x
, 0));
6490 else if (GET_CODE (x
) == HIGH
)
6492 fputs ("%hi(", file
);
6493 output_addr_const (file
, XEXP (x
, 0));
6496 else if (GET_CODE (x
) == LO_SUM
)
6498 print_operand (file
, XEXP (x
, 0), 0);
6499 if (TARGET_CM_MEDMID
)
6500 fputs ("+%l44(", file
);
6502 fputs ("+%lo(", file
);
6503 output_addr_const (file
, XEXP (x
, 1));
6506 else if (GET_CODE (x
) == CONST_DOUBLE
6507 && (GET_MODE (x
) == VOIDmode
6508 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
))
6510 if (CONST_DOUBLE_HIGH (x
) == 0)
6511 fprintf (file
, "%u", (unsigned int) CONST_DOUBLE_LOW (x
));
6512 else if (CONST_DOUBLE_HIGH (x
) == -1
6513 && CONST_DOUBLE_LOW (x
) < 0)
6514 fprintf (file
, "%d", (int) CONST_DOUBLE_LOW (x
));
6516 output_operand_lossage ("long long constant not a valid immediate operand");
6518 else if (GET_CODE (x
) == CONST_DOUBLE
)
6519 output_operand_lossage ("floating point constant not a valid immediate operand");
6520 else { output_addr_const (file
, x
); }
6523 /* Target hook for assembling integer objects. The sparc version has
6524 special handling for aligned DI-mode objects. */
6527 sparc_assemble_integer (x
, size
, aligned_p
)
6532 /* ??? We only output .xword's for symbols and only then in environments
6533 where the assembler can handle them. */
6534 if (aligned_p
&& size
== 8
6535 && (GET_CODE (x
) != CONST_INT
&& GET_CODE (x
) != CONST_DOUBLE
))
6539 assemble_integer_with_op ("\t.xword\t", x
);
6544 assemble_aligned_integer (4, const0_rtx
);
6545 assemble_aligned_integer (4, x
);
6549 return default_assemble_integer (x
, size
, aligned_p
);
6552 /* Return the value of a code used in the .proc pseudo-op that says
6553 what kind of result this function returns. For non-C types, we pick
6554 the closest C type. */
6556 #ifndef SHORT_TYPE_SIZE
6557 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
6560 #ifndef INT_TYPE_SIZE
6561 #define INT_TYPE_SIZE BITS_PER_WORD
6564 #ifndef LONG_TYPE_SIZE
6565 #define LONG_TYPE_SIZE BITS_PER_WORD
6568 #ifndef LONG_LONG_TYPE_SIZE
6569 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
6572 #ifndef FLOAT_TYPE_SIZE
6573 #define FLOAT_TYPE_SIZE BITS_PER_WORD
6576 #ifndef DOUBLE_TYPE_SIZE
6577 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6580 #ifndef LONG_DOUBLE_TYPE_SIZE
6581 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6585 sparc_type_code (type
)
6588 register unsigned long qualifiers
= 0;
6589 register unsigned shift
;
6591 /* Only the first 30 bits of the qualifier are valid. We must refrain from
6592 setting more, since some assemblers will give an error for this. Also,
6593 we must be careful to avoid shifts of 32 bits or more to avoid getting
6594 unpredictable results. */
6596 for (shift
= 6; shift
< 30; shift
+= 2, type
= TREE_TYPE (type
))
6598 switch (TREE_CODE (type
))
6604 qualifiers
|= (3 << shift
);
6609 qualifiers
|= (2 << shift
);
6613 case REFERENCE_TYPE
:
6615 qualifiers
|= (1 << shift
);
6619 return (qualifiers
| 8);
6622 case QUAL_UNION_TYPE
:
6623 return (qualifiers
| 9);
6626 return (qualifiers
| 10);
6629 return (qualifiers
| 16);
6632 /* If this is a range type, consider it to be the underlying
6634 if (TREE_TYPE (type
) != 0)
6637 /* Carefully distinguish all the standard types of C,
6638 without messing up if the language is not C. We do this by
6639 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
6640 look at both the names and the above fields, but that's redundant.
6641 Any type whose size is between two C types will be considered
6642 to be the wider of the two types. Also, we do not have a
6643 special code to use for "long long", so anything wider than
6644 long is treated the same. Note that we can't distinguish
6645 between "int" and "long" in this code if they are the same
6646 size, but that's fine, since neither can the assembler. */
6648 if (TYPE_PRECISION (type
) <= CHAR_TYPE_SIZE
)
6649 return (qualifiers
| (TREE_UNSIGNED (type
) ? 12 : 2));
6651 else if (TYPE_PRECISION (type
) <= SHORT_TYPE_SIZE
)
6652 return (qualifiers
| (TREE_UNSIGNED (type
) ? 13 : 3));
6654 else if (TYPE_PRECISION (type
) <= INT_TYPE_SIZE
)
6655 return (qualifiers
| (TREE_UNSIGNED (type
) ? 14 : 4));
6658 return (qualifiers
| (TREE_UNSIGNED (type
) ? 15 : 5));
6661 /* If this is a range type, consider it to be the underlying
6663 if (TREE_TYPE (type
) != 0)
6666 /* Carefully distinguish all the standard types of C,
6667 without messing up if the language is not C. */
6669 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
6670 return (qualifiers
| 6);
6673 return (qualifiers
| 7);
6675 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
6676 /* ??? We need to distinguish between double and float complex types,
6677 but I don't know how yet because I can't reach this code from
6678 existing front-ends. */
6679 return (qualifiers
| 7); /* Who knows? */
6681 case CHAR_TYPE
: /* GNU Pascal CHAR type. Not used in C. */
6682 case BOOLEAN_TYPE
: /* GNU Fortran BOOLEAN type. */
6683 case FILE_TYPE
: /* GNU Pascal FILE type. */
6684 case SET_TYPE
: /* GNU Pascal SET type. */
6685 case LANG_TYPE
: /* ? */
6689 abort (); /* Not a type! */
6696 /* Nested function support. */
6698 /* Emit RTL insns to initialize the variable parts of a trampoline.
6699 FNADDR is an RTX for the address of the function's pure code.
6700 CXT is an RTX for the static chain value for the function.
6702 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
6703 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
6704 (to store insns). This is a bit excessive. Perhaps a different
6705 mechanism would be better here.
6707 Emit enough FLUSH insns to synchronize the data and instruction caches. */
6710 sparc_initialize_trampoline (tramp
, fnaddr
, cxt
)
6711 rtx tramp
, fnaddr
, cxt
;
6713 /* SPARC 32 bit trampoline:
6716 sethi %hi(static), %g2
6718 or %g2, %lo(static), %g2
6720 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
6721 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
6723 #ifdef TRANSFER_FROM_TRAMPOLINE
6724 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "__enable_execute_stack"),
6725 LCT_NORMAL
, VOIDmode
, 1, tramp
, Pmode
);
6729 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 0)),
6730 expand_binop (SImode
, ior_optab
,
6731 expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
,
6732 size_int (10), 0, 1),
6733 GEN_INT (trunc_int_for_mode (0x03000000, SImode
)),
6734 NULL_RTX
, 1, OPTAB_DIRECT
));
6737 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 4)),
6738 expand_binop (SImode
, ior_optab
,
6739 expand_shift (RSHIFT_EXPR
, SImode
, cxt
,
6740 size_int (10), 0, 1),
6741 GEN_INT (trunc_int_for_mode (0x05000000, SImode
)),
6742 NULL_RTX
, 1, OPTAB_DIRECT
));
6745 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 8)),
6746 expand_binop (SImode
, ior_optab
,
6747 expand_and (SImode
, fnaddr
, GEN_INT (0x3ff), NULL_RTX
),
6748 GEN_INT (trunc_int_for_mode (0x81c06000, SImode
)),
6749 NULL_RTX
, 1, OPTAB_DIRECT
));
6752 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 12)),
6753 expand_binop (SImode
, ior_optab
,
6754 expand_and (SImode
, cxt
, GEN_INT (0x3ff), NULL_RTX
),
6755 GEN_INT (trunc_int_for_mode (0x8410a000, SImode
)),
6756 NULL_RTX
, 1, OPTAB_DIRECT
));
6758 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
6759 aligned on a 16 byte boundary so one flush clears it all. */
6760 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode
, tramp
))));
6761 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
6762 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
)
6763 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode
,
6764 plus_constant (tramp
, 8)))));
6767 /* The 64 bit version is simpler because it makes more sense to load the
6768 values as "immediate" data out of the trampoline. It's also easier since
6769 we can read the PC without clobbering a register. */
6772 sparc64_initialize_trampoline (tramp
, fnaddr
, cxt
)
6773 rtx tramp
, fnaddr
, cxt
;
6775 #ifdef TRANSFER_FROM_TRAMPOLINE
6776 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "__enable_execute_stack"),
6777 LCT_NORMAL
, VOIDmode
, 1, tramp
, Pmode
);
6788 emit_move_insn (gen_rtx_MEM (SImode
, tramp
),
6789 GEN_INT (trunc_int_for_mode (0x83414000, SImode
)));
6790 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 4)),
6791 GEN_INT (trunc_int_for_mode (0xca586018, SImode
)));
6792 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 8)),
6793 GEN_INT (trunc_int_for_mode (0x81c14000, SImode
)));
6794 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 12)),
6795 GEN_INT (trunc_int_for_mode (0xca586010, SImode
)));
6796 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, 16)), cxt
);
6797 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, 24)), fnaddr
);
6798 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode
, tramp
))));
6800 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
6801 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
)
6802 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode
, plus_constant (tramp
, 8)))));
6805 /* Subroutines to support a flat (single) register window calling
6808 /* Single-register window sparc stack frames look like:
6810 Before call After call
6811 +-----------------------+ +-----------------------+
6813 mem | caller's temps. | | caller's temps. |
6815 +-----------------------+ +-----------------------+
6817 | arguments on stack. | | arguments on stack. |
6819 +-----------------------+FP+92->+-----------------------+
6820 | 6 words to save | | 6 words to save |
6821 | arguments passed | | arguments passed |
6822 | in registers, even | | in registers, even |
6823 | if not passed. | | if not passed. |
6824 SP+68->+-----------------------+FP+68->+-----------------------+
6825 | 1 word struct addr | | 1 word struct addr |
6826 +-----------------------+FP+64->+-----------------------+
6828 | 16 word reg save area | | 16 word reg save area |
6830 SP->+-----------------------+ FP->+-----------------------+
6832 | fp/alu reg moves |
6833 FP-16->+-----------------------+
6837 +-----------------------+
6839 | fp register save |
6841 +-----------------------+
6843 | gp register save |
6845 +-----------------------+
6847 | alloca allocations |
6849 +-----------------------+
6851 | arguments on stack |
6853 SP+92->+-----------------------+
6855 | arguments passed |
6856 | in registers, even |
6857 low | if not passed. |
6858 memory SP+68->+-----------------------+
6859 | 1 word struct addr |
6860 SP+64->+-----------------------+
6862 I 16 word reg save area |
6864 SP->+-----------------------+ */
6866 /* Structure to be filled in by sparc_flat_compute_frame_size with register
6867 save masks, and offsets for the current function. */
6869 struct sparc_frame_info
6871 unsigned long total_size
; /* # bytes that the entire frame takes up. */
6872 unsigned long var_size
; /* # bytes that variables take up. */
6873 unsigned long args_size
; /* # bytes that outgoing arguments take up. */
6874 unsigned long extra_size
; /* # bytes of extra gunk. */
6875 unsigned int gp_reg_size
; /* # bytes needed to store gp regs. */
6876 unsigned int fp_reg_size
; /* # bytes needed to store fp regs. */
6877 unsigned long gmask
; /* Mask of saved gp registers. */
6878 unsigned long fmask
; /* Mask of saved fp registers. */
6879 unsigned long reg_offset
; /* Offset from new sp to store regs. */
6880 int initialized
; /* Nonzero if frame size already calculated. */
6883 /* Current frame information calculated by sparc_flat_compute_frame_size. */
6884 struct sparc_frame_info current_frame_info
;
6886 /* Zero structure to initialize current_frame_info. */
6887 struct sparc_frame_info zero_frame_info
;
6889 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
6891 #define RETURN_ADDR_REGNUM 15
6892 #define HARD_FRAME_POINTER_MASK (1 << (HARD_FRAME_POINTER_REGNUM))
6893 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
6895 #define MUST_SAVE_REGISTER(regno) \
6896 ((regs_ever_live[regno] && !call_used_regs[regno]) \
6897 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
6898 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM]))
6900 /* Return the bytes needed to compute the frame pointer from the current
6904 sparc_flat_compute_frame_size (size
)
6905 int size
; /* # of var. bytes allocated. */
6908 unsigned long total_size
; /* # bytes that the entire frame takes up. */
6909 unsigned long var_size
; /* # bytes that variables take up. */
6910 unsigned long args_size
; /* # bytes that outgoing arguments take up. */
6911 unsigned long extra_size
; /* # extra bytes. */
6912 unsigned int gp_reg_size
; /* # bytes needed to store gp regs. */
6913 unsigned int fp_reg_size
; /* # bytes needed to store fp regs. */
6914 unsigned long gmask
; /* Mask of saved gp registers. */
6915 unsigned long fmask
; /* Mask of saved fp registers. */
6916 unsigned long reg_offset
; /* Offset to register save area. */
6917 int need_aligned_p
; /* 1 if need the save area 8 byte aligned. */
6919 /* This is the size of the 16 word reg save area, 1 word struct addr
6920 area, and 4 word fp/alu register copy area. */
6921 extra_size
= -STARTING_FRAME_OFFSET
+ FIRST_PARM_OFFSET(0);
6931 if (!leaf_function_p ())
6933 /* Also include the size needed for the 6 parameter registers. */
6934 args_size
= current_function_outgoing_args_size
+ 24;
6936 total_size
= var_size
+ args_size
;
6938 /* Calculate space needed for gp registers. */
6939 for (regno
= 1; regno
<= 31; regno
++)
6941 if (MUST_SAVE_REGISTER (regno
))
6943 /* If we need to save two regs in a row, ensure there's room to bump
6944 up the address to align it to a doubleword boundary. */
6945 if ((regno
& 0x1) == 0 && MUST_SAVE_REGISTER (regno
+1))
6947 if (gp_reg_size
% 8 != 0)
6949 gp_reg_size
+= 2 * UNITS_PER_WORD
;
6950 gmask
|= 3 << regno
;
6956 gp_reg_size
+= UNITS_PER_WORD
;
6957 gmask
|= 1 << regno
;
6962 /* Calculate space needed for fp registers. */
6963 for (regno
= 32; regno
<= 63; regno
++)
6965 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
6967 fp_reg_size
+= UNITS_PER_WORD
;
6968 fmask
|= 1 << (regno
- 32);
6975 reg_offset
= FIRST_PARM_OFFSET(0) + args_size
;
6976 /* Ensure save area is 8 byte aligned if we need it. */
6978 if (need_aligned_p
&& n
!= 0)
6980 total_size
+= 8 - n
;
6981 reg_offset
+= 8 - n
;
6983 total_size
+= gp_reg_size
+ fp_reg_size
;
6986 /* If we must allocate a stack frame at all, we must also allocate
6987 room for register window spillage, so as to be binary compatible
6988 with libraries and operating systems that do not use -mflat. */
6990 total_size
+= extra_size
;
6994 total_size
= SPARC_STACK_ALIGN (total_size
);
6996 /* Save other computed information. */
6997 current_frame_info
.total_size
= total_size
;
6998 current_frame_info
.var_size
= var_size
;
6999 current_frame_info
.args_size
= args_size
;
7000 current_frame_info
.extra_size
= extra_size
;
7001 current_frame_info
.gp_reg_size
= gp_reg_size
;
7002 current_frame_info
.fp_reg_size
= fp_reg_size
;
7003 current_frame_info
.gmask
= gmask
;
7004 current_frame_info
.fmask
= fmask
;
7005 current_frame_info
.reg_offset
= reg_offset
;
7006 current_frame_info
.initialized
= reload_completed
;
7008 /* Ok, we're done. */
7012 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
7015 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
7016 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
7017 [BASE_REG+OFFSET] will always be a valid address.
7019 WORD_OP is either "st" for save, "ld" for restore.
7020 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
7023 sparc_flat_save_restore (file
, base_reg
, offset
, gmask
, fmask
, word_op
,
7024 doubleword_op
, base_offset
)
7026 const char *base_reg
;
7027 unsigned int offset
;
7028 unsigned long gmask
;
7029 unsigned long fmask
;
7030 const char *word_op
;
7031 const char *doubleword_op
;
7032 unsigned long base_offset
;
7036 if (gmask
== 0 && fmask
== 0)
7039 /* Save registers starting from high to low. We've already saved the
7040 previous frame pointer and previous return address for the debugger's
7041 sake. The debugger allows us to not need a nop in the epilog if at least
7042 one register is reloaded in addition to return address. */
7046 for (regno
= 1; regno
<= 31; regno
++)
7048 if ((gmask
& (1L << regno
)) != 0)
7050 if ((regno
& 0x1) == 0 && ((gmask
& (1L << (regno
+1))) != 0))
7052 /* We can save two registers in a row. If we're not at a
7053 double word boundary, move to one.
7054 sparc_flat_compute_frame_size ensures there's room to do
7056 if (offset
% 8 != 0)
7057 offset
+= UNITS_PER_WORD
;
7059 if (word_op
[0] == 's')
7061 fprintf (file
, "\t%s\t%s, [%s+%d]\n",
7062 doubleword_op
, reg_names
[regno
],
7064 if (dwarf2out_do_frame ())
7066 char *l
= dwarf2out_cfi_label ();
7067 dwarf2out_reg_save (l
, regno
, offset
+ base_offset
);
7069 (l
, regno
+1, offset
+base_offset
+ UNITS_PER_WORD
);
7073 fprintf (file
, "\t%s\t[%s+%d], %s\n",
7074 doubleword_op
, base_reg
, offset
,
7077 offset
+= 2 * UNITS_PER_WORD
;
7082 if (word_op
[0] == 's')
7084 fprintf (file
, "\t%s\t%s, [%s+%d]\n",
7085 word_op
, reg_names
[regno
],
7087 if (dwarf2out_do_frame ())
7088 dwarf2out_reg_save ("", regno
, offset
+ base_offset
);
7091 fprintf (file
, "\t%s\t[%s+%d], %s\n",
7092 word_op
, base_reg
, offset
, reg_names
[regno
]);
7094 offset
+= UNITS_PER_WORD
;
7102 for (regno
= 32; regno
<= 63; regno
++)
7104 if ((fmask
& (1L << (regno
- 32))) != 0)
7106 if (word_op
[0] == 's')
7108 fprintf (file
, "\t%s\t%s, [%s+%d]\n",
7109 word_op
, reg_names
[regno
],
7111 if (dwarf2out_do_frame ())
7112 dwarf2out_reg_save ("", regno
, offset
+ base_offset
);
7115 fprintf (file
, "\t%s\t[%s+%d], %s\n",
7116 word_op
, base_reg
, offset
, reg_names
[regno
]);
7118 offset
+= UNITS_PER_WORD
;
7124 /* Set up the stack and frame (if desired) for the function. */
7127 sparc_flat_function_prologue (file
, size
)
7131 const char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
7132 unsigned long gmask
= current_frame_info
.gmask
;
7134 sparc_output_scratch_registers (file
);
7136 /* This is only for the human reader. */
7137 fprintf (file
, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START
);
7138 fprintf (file
, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
7140 current_frame_info
.var_size
,
7141 current_frame_info
.gp_reg_size
/ 4,
7142 current_frame_info
.fp_reg_size
/ 4,
7143 current_function_outgoing_args_size
,
7144 current_frame_info
.extra_size
);
7146 size
= SPARC_STACK_ALIGN (size
);
7147 size
= (! current_frame_info
.initialized
7148 ? sparc_flat_compute_frame_size (size
)
7149 : current_frame_info
.total_size
);
7151 /* These cases shouldn't happen. Catch them now. */
7152 if (size
== 0 && (gmask
|| current_frame_info
.fmask
))
7155 /* Allocate our stack frame by decrementing %sp.
7156 At present, the only algorithm gdb can use to determine if this is a
7157 flat frame is if we always set %i7 if we set %sp. This can be optimized
7158 in the future by putting in some sort of debugging information that says
7159 this is a `flat' function. However, there is still the case of debugging
7160 code without such debugging information (including cases where most fns
7161 have such info, but there is one that doesn't). So, always do this now
7162 so we don't get a lot of code out there that gdb can't handle.
7163 If the frame pointer isn't needn't then that's ok - gdb won't be able to
7164 distinguish us from a non-flat function but there won't (and shouldn't)
7165 be any differences anyway. The return pc is saved (if necessary) right
7166 after %i7 so gdb won't have to look too far to find it. */
7169 unsigned int reg_offset
= current_frame_info
.reg_offset
;
7170 const char *const fp_str
= reg_names
[HARD_FRAME_POINTER_REGNUM
];
7171 static const char *const t1_str
= "%g1";
7173 /* Things get a little tricky if local variables take up more than ~4096
7174 bytes and outgoing arguments take up more than ~4096 bytes. When that
7175 happens, the register save area can't be accessed from either end of
7176 the frame. Handle this by decrementing %sp to the start of the gp
7177 register save area, save the regs, update %i7, and then set %sp to its
7178 final value. Given that we only have one scratch register to play
7179 with it is the cheapest solution, and it helps gdb out as it won't
7180 slow down recognition of flat functions.
7181 Don't change the order of insns emitted here without checking with
7182 the gdb folk first. */
7184 /* Is the entire register save area offsettable from %sp? */
7185 if (reg_offset
< 4096 - 64 * (unsigned) UNITS_PER_WORD
)
7189 fprintf (file
, "\tadd\t%s, %d, %s\n",
7190 sp_str
, (int) -size
, sp_str
);
7191 if (gmask
& HARD_FRAME_POINTER_MASK
)
7193 fprintf (file
, "\tst\t%s, [%s+%d]\n",
7194 fp_str
, sp_str
, reg_offset
);
7195 fprintf (file
, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
7196 sp_str
, (int) -size
, fp_str
, ASM_COMMENT_START
);
7202 fprintf (file
, "\tset\t");
7203 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, size
);
7204 fprintf (file
, ", %s\n\tsub\t%s, %s, %s\n",
7205 t1_str
, sp_str
, t1_str
, sp_str
);
7206 if (gmask
& HARD_FRAME_POINTER_MASK
)
7208 fprintf (file
, "\tst\t%s, [%s+%d]\n",
7209 fp_str
, sp_str
, reg_offset
);
7210 fprintf (file
, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7211 sp_str
, t1_str
, fp_str
, ASM_COMMENT_START
);
7215 if (dwarf2out_do_frame ())
7217 char *l
= dwarf2out_cfi_label ();
7218 if (gmask
& HARD_FRAME_POINTER_MASK
)
7220 dwarf2out_reg_save (l
, HARD_FRAME_POINTER_REGNUM
,
7221 reg_offset
- 4 - size
);
7222 dwarf2out_def_cfa (l
, HARD_FRAME_POINTER_REGNUM
, 0);
7225 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, size
);
7227 if (gmask
& RETURN_ADDR_MASK
)
7229 fprintf (file
, "\tst\t%s, [%s+%d]\n",
7230 reg_names
[RETURN_ADDR_REGNUM
], sp_str
, reg_offset
);
7231 if (dwarf2out_do_frame ())
7232 dwarf2out_return_save ("", reg_offset
- size
);
7235 sparc_flat_save_restore (file
, sp_str
, reg_offset
,
7236 gmask
& ~(HARD_FRAME_POINTER_MASK
| RETURN_ADDR_MASK
),
7237 current_frame_info
.fmask
,
7238 "st", "std", -size
);
7242 /* Subtract %sp in two steps, but make sure there is always a
7243 64 byte register save area, and %sp is properly aligned. */
7244 /* Amount to decrement %sp by, the first time. */
7245 unsigned HOST_WIDE_INT size1
= ((size
- reg_offset
+ 64) + 15) & -16;
7246 /* Offset to register save area from %sp. */
7247 unsigned HOST_WIDE_INT offset
= size1
- (size
- reg_offset
);
7251 fprintf (file
, "\tadd\t%s, %d, %s\n",
7252 sp_str
, (int) -size1
, sp_str
);
7253 if (gmask
& HARD_FRAME_POINTER_MASK
)
7255 fprintf (file
, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
7256 fp_str
, sp_str
, (int) offset
, sp_str
, (int) -size1
,
7257 fp_str
, ASM_COMMENT_START
);
7263 fprintf (file
, "\tset\t");
7264 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, size1
);
7265 fprintf (file
, ", %s\n\tsub\t%s, %s, %s\n",
7266 t1_str
, sp_str
, t1_str
, sp_str
);
7267 if (gmask
& HARD_FRAME_POINTER_MASK
)
7269 fprintf (file
, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7270 fp_str
, sp_str
, (int) offset
, sp_str
, t1_str
,
7271 fp_str
, ASM_COMMENT_START
);
7275 if (dwarf2out_do_frame ())
7277 char *l
= dwarf2out_cfi_label ();
7278 if (gmask
& HARD_FRAME_POINTER_MASK
)
7280 dwarf2out_reg_save (l
, HARD_FRAME_POINTER_REGNUM
,
7281 offset
- 4 - size1
);
7282 dwarf2out_def_cfa (l
, HARD_FRAME_POINTER_REGNUM
, 0);
7285 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, size1
);
7287 if (gmask
& RETURN_ADDR_MASK
)
7289 fprintf (file
, "\tst\t%s, [%s+%d]\n",
7290 reg_names
[RETURN_ADDR_REGNUM
], sp_str
, (int) offset
);
7291 if (dwarf2out_do_frame ())
7292 /* offset - size1 == reg_offset - size
7293 if reg_offset were updated above like offset. */
7294 dwarf2out_return_save ("", offset
- size1
);
7297 sparc_flat_save_restore (file
, sp_str
, offset
,
7298 gmask
& ~(HARD_FRAME_POINTER_MASK
| RETURN_ADDR_MASK
),
7299 current_frame_info
.fmask
,
7300 "st", "std", -size1
);
7301 fprintf (file
, "\tset\t");
7302 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, size
- size1
);
7303 fprintf (file
, ", %s\n\tsub\t%s, %s, %s\n",
7304 t1_str
, sp_str
, t1_str
, sp_str
);
7305 if (dwarf2out_do_frame ())
7306 if (! (gmask
& HARD_FRAME_POINTER_MASK
))
7307 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, size
);
7311 fprintf (file
, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START
);
7314 /* Do any necessary cleanup after a function to restore stack, frame,
7318 sparc_flat_function_epilogue (file
, size
)
7322 rtx epilogue_delay
= current_function_epilogue_delay_list
;
7323 int noepilogue
= FALSE
;
7325 /* This is only for the human reader. */
7326 fprintf (file
, "\t%s#EPILOGUE#\n", ASM_COMMENT_START
);
7328 /* The epilogue does not depend on any registers, but the stack
7329 registers, so we assume that if we have 1 pending nop, it can be
7330 ignored, and 2 it must be filled (2 nops occur for integer
7331 multiply and divide). */
7333 size
= SPARC_STACK_ALIGN (size
);
7334 size
= (!current_frame_info
.initialized
7335 ? sparc_flat_compute_frame_size (size
)
7336 : current_frame_info
.total_size
);
7338 if (size
== 0 && epilogue_delay
== 0)
7340 rtx insn
= get_last_insn ();
7342 /* If the last insn was a BARRIER, we don't have to write any code
7343 because a jump (aka return) was put there. */
7344 if (GET_CODE (insn
) == NOTE
)
7345 insn
= prev_nonnote_insn (insn
);
7346 if (insn
&& GET_CODE (insn
) == BARRIER
)
7352 unsigned HOST_WIDE_INT reg_offset
= current_frame_info
.reg_offset
;
7353 unsigned HOST_WIDE_INT size1
;
7354 const char *const sp_str
= reg_names
[STACK_POINTER_REGNUM
];
7355 const char *const fp_str
= reg_names
[HARD_FRAME_POINTER_REGNUM
];
7356 static const char *const t1_str
= "%g1";
7358 /* In the reload sequence, we don't need to fill the load delay
7359 slots for most of the loads, also see if we can fill the final
7360 delay slot if not otherwise filled by the reload sequence. */
7364 fprintf (file
, "\tset\t");
7365 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, size
);
7366 fprintf (file
, ", %s\n", t1_str
);
7369 if (frame_pointer_needed
)
7372 fprintf (file
,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n",
7373 fp_str
, t1_str
, sp_str
, ASM_COMMENT_START
);
7375 fprintf (file
,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n",
7376 fp_str
, (int) size
, sp_str
, ASM_COMMENT_START
);
7379 /* Is the entire register save area offsettable from %sp? */
7380 if (reg_offset
< 4096 - 64 * (unsigned) UNITS_PER_WORD
)
7386 /* Restore %sp in two steps, but make sure there is always a
7387 64 byte register save area, and %sp is properly aligned. */
7388 /* Amount to increment %sp by, the first time. */
7389 size1
= ((reg_offset
- 64 - 16) + 15) & -16;
7390 /* Offset to register save area from %sp. */
7391 reg_offset
= size1
- reg_offset
;
7393 fprintf (file
, "\tset\t");
7394 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, size1
);
7395 fprintf (file
, ", %s\n\tadd\t%s, %s, %s\n",
7396 t1_str
, sp_str
, t1_str
, sp_str
);
7399 /* We must restore the frame pointer and return address reg first
7400 because they are treated specially by the prologue output code. */
7401 if (current_frame_info
.gmask
& HARD_FRAME_POINTER_MASK
)
7403 fprintf (file
, "\tld\t[%s+%d], %s\n",
7404 sp_str
, (int) reg_offset
, fp_str
);
7407 if (current_frame_info
.gmask
& RETURN_ADDR_MASK
)
7409 fprintf (file
, "\tld\t[%s+%d], %s\n",
7410 sp_str
, (int) reg_offset
, reg_names
[RETURN_ADDR_REGNUM
]);
7414 /* Restore any remaining saved registers. */
7415 sparc_flat_save_restore (file
, sp_str
, reg_offset
,
7416 current_frame_info
.gmask
& ~(HARD_FRAME_POINTER_MASK
| RETURN_ADDR_MASK
),
7417 current_frame_info
.fmask
,
7420 /* If we had to increment %sp in two steps, record it so the second
7421 restoration in the epilogue finishes up. */
7427 fprintf (file
, "\tset\t");
7428 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, size
);
7429 fprintf (file
, ", %s\n", t1_str
);
7433 if (current_function_returns_struct
)
7434 fprintf (file
, "\tjmp\t%%o7+12\n");
7436 fprintf (file
, "\tretl\n");
7438 /* If the only register saved is the return address, we need a
7439 nop, unless we have an instruction to put into it. Otherwise
7440 we don't since reloading multiple registers doesn't reference
7441 the register being loaded. */
7447 final_scan_insn (XEXP (epilogue_delay
, 0), file
, 1, -2, 1);
7450 else if (size
> 4095)
7451 fprintf (file
, "\tadd\t%s, %s, %s\n", sp_str
, t1_str
, sp_str
);
7454 fprintf (file
, "\tadd\t%s, %d, %s\n", sp_str
, (int) size
, sp_str
);
7457 fprintf (file
, "\tnop\n");
7460 /* Reset state info for each function. */
7461 current_frame_info
= zero_frame_info
;
7463 sparc_output_deferred_case_vectors ();
7466 /* Define the number of delay slots needed for the function epilogue.
7468 On the sparc, we need a slot if either no stack has been allocated,
7469 or the only register saved is the return register. */
7472 sparc_flat_epilogue_delay_slots ()
7474 if (!current_frame_info
.initialized
)
7475 (void) sparc_flat_compute_frame_size (get_frame_size ());
7477 if (current_frame_info
.total_size
== 0)
7483 /* Return true if TRIAL is a valid insn for the epilogue delay slot.
7484 Any single length instruction which doesn't reference the stack or frame
7488 sparc_flat_eligible_for_epilogue_delay (trial
, slot
)
7490 int slot ATTRIBUTE_UNUSED
;
7492 rtx pat
= PATTERN (trial
);
7494 if (get_attr_length (trial
) != 1)
7497 if (! reg_mentioned_p (stack_pointer_rtx
, pat
)
7498 && ! reg_mentioned_p (frame_pointer_rtx
, pat
))
7504 /* Adjust the cost of a scheduling dependency. Return the new cost of
7505 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7508 supersparc_adjust_cost (insn
, link
, dep_insn
, cost
)
7514 enum attr_type insn_type
;
7516 if (! recog_memoized (insn
))
7519 insn_type
= get_attr_type (insn
);
7521 if (REG_NOTE_KIND (link
) == 0)
7523 /* Data dependency; DEP_INSN writes a register that INSN reads some
7526 /* if a load, then the dependence must be on the memory address;
7527 add an extra "cycle". Note that the cost could be two cycles
7528 if the reg was written late in an instruction group; we ca not tell
7530 if (insn_type
== TYPE_LOAD
|| insn_type
== TYPE_FPLOAD
)
7533 /* Get the delay only if the address of the store is the dependence. */
7534 if (insn_type
== TYPE_STORE
|| insn_type
== TYPE_FPSTORE
)
7536 rtx pat
= PATTERN(insn
);
7537 rtx dep_pat
= PATTERN (dep_insn
);
7539 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
7540 return cost
; /* This should not happen! */
7542 /* The dependency between the two instructions was on the data that
7543 is being stored. Assume that this implies that the address of the
7544 store is not dependent. */
7545 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
7548 return cost
+ 3; /* An approximation. */
7551 /* A shift instruction cannot receive its data from an instruction
7552 in the same cycle; add a one cycle penalty. */
7553 if (insn_type
== TYPE_SHIFT
)
7554 return cost
+ 3; /* Split before cascade into shift. */
7558 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7559 INSN writes some cycles later. */
7561 /* These are only significant for the fpu unit; writing a fp reg before
7562 the fpu has finished with it stalls the processor. */
7564 /* Reusing an integer register causes no problems. */
7565 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
7573 hypersparc_adjust_cost (insn
, link
, dep_insn
, cost
)
7579 enum attr_type insn_type
, dep_type
;
7580 rtx pat
= PATTERN(insn
);
7581 rtx dep_pat
= PATTERN (dep_insn
);
7583 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
7586 insn_type
= get_attr_type (insn
);
7587 dep_type
= get_attr_type (dep_insn
);
7589 switch (REG_NOTE_KIND (link
))
7592 /* Data dependency; DEP_INSN writes a register that INSN reads some
7599 /* Get the delay iff the address of the store is the dependence. */
7600 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
7603 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
7610 /* If a load, then the dependence must be on the memory address. If
7611 the addresses aren't equal, then it might be a false dependency */
7612 if (dep_type
== TYPE_STORE
|| dep_type
== TYPE_FPSTORE
)
7614 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
7615 || GET_CODE (SET_DEST (dep_pat
)) != MEM
7616 || GET_CODE (SET_SRC (pat
)) != MEM
7617 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat
), 0),
7618 XEXP (SET_SRC (pat
), 0)))
7626 /* Compare to branch latency is 0. There is no benefit from
7627 separating compare and branch. */
7628 if (dep_type
== TYPE_COMPARE
)
7630 /* Floating point compare to branch latency is less than
7631 compare to conditional move. */
7632 if (dep_type
== TYPE_FPCMP
)
7641 /* Anti-dependencies only penalize the fpu unit. */
7642 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
7654 sparc_adjust_cost(insn
, link
, dep
, cost
)
7662 case PROCESSOR_SUPERSPARC
:
7663 cost
= supersparc_adjust_cost (insn
, link
, dep
, cost
);
7665 case PROCESSOR_HYPERSPARC
:
7666 case PROCESSOR_SPARCLITE86X
:
7667 cost
= hypersparc_adjust_cost (insn
, link
, dep
, cost
);
7676 sparc_sched_init (dump
, sched_verbose
, max_ready
)
7677 FILE *dump ATTRIBUTE_UNUSED
;
7678 int sched_verbose ATTRIBUTE_UNUSED
;
7679 int max_ready ATTRIBUTE_UNUSED
;
7684 sparc_use_dfa_pipeline_interface ()
7686 if ((1 << sparc_cpu
) &
7687 ((1 << PROCESSOR_ULTRASPARC
) | (1 << PROCESSOR_CYPRESS
) |
7688 (1 << PROCESSOR_SUPERSPARC
) | (1 << PROCESSOR_HYPERSPARC
) |
7689 (1 << PROCESSOR_SPARCLITE86X
) | (1 << PROCESSOR_TSC701
) |
7690 (1 << PROCESSOR_ULTRASPARC3
)))
7696 sparc_use_sched_lookahead ()
7698 if (sparc_cpu
== PROCESSOR_ULTRASPARC
7699 || sparc_cpu
== PROCESSOR_ULTRASPARC3
)
7701 if ((1 << sparc_cpu
) &
7702 ((1 << PROCESSOR_SUPERSPARC
) | (1 << PROCESSOR_HYPERSPARC
) |
7703 (1 << PROCESSOR_SPARCLITE86X
)))
7716 /* Assume V9 processors are capable of at least dual-issue. */
7718 case PROCESSOR_SUPERSPARC
:
7720 case PROCESSOR_HYPERSPARC
:
7721 case PROCESSOR_SPARCLITE86X
:
7723 case PROCESSOR_ULTRASPARC
:
7724 case PROCESSOR_ULTRASPARC3
:
7733 register rtx pat
= PATTERN (insn
);
7735 switch (GET_CODE (SET_SRC (pat
)))
7737 /* Load and some shift instructions zero extend. */
7740 /* sethi clears the high bits */
7742 /* LO_SUM is used with sethi. sethi cleared the high
7743 bits and the values used with lo_sum are positive */
7745 /* Store flag stores 0 or 1 */
7755 rtx op0
= XEXP (SET_SRC (pat
), 0);
7756 rtx op1
= XEXP (SET_SRC (pat
), 1);
7757 if (GET_CODE (op1
) == CONST_INT
)
7758 return INTVAL (op1
) >= 0;
7759 if (GET_CODE (op0
) != REG
)
7761 if (sparc_check_64 (op0
, insn
) == 1)
7763 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
7768 rtx op0
= XEXP (SET_SRC (pat
), 0);
7769 rtx op1
= XEXP (SET_SRC (pat
), 1);
7770 if (GET_CODE (op0
) != REG
|| sparc_check_64 (op0
, insn
) <= 0)
7772 if (GET_CODE (op1
) == CONST_INT
)
7773 return INTVAL (op1
) >= 0;
7774 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
7778 return GET_MODE (SET_SRC (pat
)) == SImode
;
7779 /* Positive integers leave the high bits zero. */
7781 return ! (CONST_DOUBLE_LOW (SET_SRC (pat
)) & 0x80000000);
7783 return ! (INTVAL (SET_SRC (pat
)) & 0x80000000);
7786 return - (GET_MODE (SET_SRC (pat
)) == SImode
);
7788 return sparc_check_64 (SET_SRC (pat
), insn
);
7794 /* We _ought_ to have only one kind per function, but... */
7795 static rtx sparc_addr_diff_list
;
7796 static rtx sparc_addr_list
;
7799 sparc_defer_case_vector (lab
, vec
, diff
)
7803 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
7805 sparc_addr_diff_list
7806 = gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_diff_list
);
7808 sparc_addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_list
);
7812 sparc_output_addr_vec (vec
)
7815 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
7816 int idx
, vlen
= XVECLEN (body
, 0);
7818 #ifdef ASM_OUTPUT_ADDR_VEC_START
7819 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
7822 #ifdef ASM_OUTPUT_CASE_LABEL
7823 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
7826 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
7829 for (idx
= 0; idx
< vlen
; idx
++)
7831 ASM_OUTPUT_ADDR_VEC_ELT
7832 (asm_out_file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
7835 #ifdef ASM_OUTPUT_ADDR_VEC_END
7836 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
7841 sparc_output_addr_diff_vec (vec
)
7844 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
7845 rtx base
= XEXP (XEXP (body
, 0), 0);
7846 int idx
, vlen
= XVECLEN (body
, 1);
7848 #ifdef ASM_OUTPUT_ADDR_VEC_START
7849 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
7852 #ifdef ASM_OUTPUT_CASE_LABEL
7853 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
7856 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
7859 for (idx
= 0; idx
< vlen
; idx
++)
7861 ASM_OUTPUT_ADDR_DIFF_ELT
7864 CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 1, idx
), 0)),
7865 CODE_LABEL_NUMBER (base
));
7868 #ifdef ASM_OUTPUT_ADDR_VEC_END
7869 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
7874 sparc_output_deferred_case_vectors ()
7879 if (sparc_addr_list
== NULL_RTX
7880 && sparc_addr_diff_list
== NULL_RTX
)
7883 /* Align to cache line in the function's code section. */
7884 function_section (current_function_decl
);
7886 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
7888 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
7890 for (t
= sparc_addr_list
; t
; t
= XEXP (t
, 1))
7891 sparc_output_addr_vec (XEXP (t
, 0));
7892 for (t
= sparc_addr_diff_list
; t
; t
= XEXP (t
, 1))
7893 sparc_output_addr_diff_vec (XEXP (t
, 0));
7895 sparc_addr_list
= sparc_addr_diff_list
= NULL_RTX
;
7898 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
7899 unknown. Return 1 if the high bits are zero, -1 if the register is
7902 sparc_check_64 (x
, insn
)
7905 /* If a register is set only once it is safe to ignore insns this
7906 code does not know how to handle. The loop will either recognize
7907 the single set and return the correct value or fail to recognize
7912 if (GET_CODE (x
) != REG
)
7915 if (GET_MODE (x
) == DImode
)
7916 y
= gen_rtx_REG (SImode
, REGNO (x
) + WORDS_BIG_ENDIAN
);
7918 if (flag_expensive_optimizations
7919 && REG_N_SETS (REGNO (y
)) == 1)
7925 insn
= get_last_insn_anywhere ();
7930 while ((insn
= PREV_INSN (insn
)))
7932 switch (GET_CODE (insn
))
7945 rtx pat
= PATTERN (insn
);
7946 if (GET_CODE (pat
) != SET
)
7948 if (rtx_equal_p (x
, SET_DEST (pat
)))
7949 return set_extends (insn
);
7950 if (y
&& rtx_equal_p (y
, SET_DEST (pat
)))
7951 return set_extends (insn
);
7952 if (reg_overlap_mentioned_p (SET_DEST (pat
), y
))
7961 sparc_v8plus_shift (operands
, insn
, opcode
)
7966 static char asm_code
[60];
7968 if (GET_CODE (operands
[3]) == SCRATCH
)
7969 operands
[3] = operands
[0];
7970 if (GET_CODE (operands
[1]) == CONST_INT
)
7972 output_asm_insn ("mov\t%1, %3", operands
);
7976 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
7977 if (sparc_check_64 (operands
[1], insn
) <= 0)
7978 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
7979 output_asm_insn ("or\t%L1, %3, %3", operands
);
7982 strcpy(asm_code
, opcode
);
7983 if (which_alternative
!= 2)
7984 return strcat (asm_code
, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
7986 return strcat (asm_code
, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
7989 /* Output rtl to increment the profiler label LABELNO
7990 for profiling a function entry. */
7993 sparc_profile_hook (labelno
)
7999 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
8000 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
8001 fun
= gen_rtx_SYMBOL_REF (Pmode
, MCOUNT_FUNCTION
);
8003 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 1, lab
, Pmode
);
8006 /* Called to register all of our global variables with the garbage
8010 sparc_add_gc_roots ()
8012 ggc_add_rtx_root (&sparc_compare_op0
, 1);
8013 ggc_add_rtx_root (&sparc_compare_op1
, 1);
8014 ggc_add_rtx_root (&global_offset_table
, 1);
8015 ggc_add_rtx_root (&get_pc_symbol
, 1);
8016 ggc_add_rtx_root (&sparc_addr_diff_list
, 1);
8017 ggc_add_rtx_root (&sparc_addr_list
, 1);
8020 #ifdef OBJECT_FORMAT_ELF
8022 sparc_elf_asm_named_section (name
, flags
)
8026 if (flags
& SECTION_MERGE
)
8028 /* entsize cannot be expressed in this section attributes
8030 default_elf_asm_named_section (name
, flags
);
8034 fprintf (asm_out_file
, "\t.section\t\"%s\"", name
);
8036 if (!(flags
& SECTION_DEBUG
))
8037 fputs (",#alloc", asm_out_file
);
8038 if (flags
& SECTION_WRITE
)
8039 fputs (",#write", asm_out_file
);
8040 if (flags
& SECTION_CODE
)
8041 fputs (",#execinstr", asm_out_file
);
8043 /* ??? Handle SECTION_BSS. */
8045 fputc ('\n', asm_out_file
);
8047 #endif /* OBJECT_FORMAT_ELF */
8049 /* ??? Similar to the standard section selection, but force reloc-y-ness
8050 if SUNOS4_SHARED_LIBRARIES. Unclear why this helps (as opposed to
8051 pretending PIC always on), but that's what the old code did. */
8054 sparc_aout_select_section (t
, reloc
, align
)
8057 unsigned HOST_WIDE_INT align
;
8059 default_select_section (t
, reloc
| SUNOS4_SHARED_LIBRARIES
, align
);
8062 /* Use text section for a constant unless we need more alignment than
8066 sparc_aout_select_rtx_section (mode
, x
, align
)
8067 enum machine_mode mode
;
8069 unsigned HOST_WIDE_INT align
;
8071 if (align
<= MAX_TEXT_ALIGN
8072 && ! (flag_pic
&& (symbolic_operand (x
, mode
)
8073 || SUNOS4_SHARED_LIBRARIES
)))
8074 readonly_data_section ();
8080 sparc_extra_constraint_check (op
, c
, strict
)
8088 && (c
== 'T' || c
== 'U'))
8094 return fp_sethi_p (op
);
8097 return fp_mov_p (op
);
8100 return fp_high_losum_p (op
);
8104 || (GET_CODE (op
) == REG
8105 && (REGNO (op
) < FIRST_PSEUDO_REGISTER
8106 || reg_renumber
[REGNO (op
)] >= 0)))
8107 return register_ok_for_ldd (op
);
8119 /* Our memory extra constraints have to emulate the
8120 behavior of 'm' and 'o' in order for reload to work
8122 if (GET_CODE (op
) == MEM
)
8125 if ((TARGET_ARCH64
|| mem_min_alignment (op
, 8))
8127 || strict_memory_address_p (Pmode
, XEXP (op
, 0))))
8132 reload_ok_mem
= (reload_in_progress
8133 && GET_CODE (op
) == REG
8134 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
8135 && reg_renumber
[REGNO (op
)] < 0);
8138 return reload_ok_mem
;
8141 /* ??? This duplicates information provided to the compiler by the
8142 ??? scheduler description. Some day, teach genautomata to output
8143 ??? the latencies and then CSE will just use that. */
8146 sparc_rtx_costs (x
, code
, outer_code
)
8148 enum rtx_code code
, outer_code
;
8152 case PLUS
: case MINUS
: case ABS
: case NEG
:
8153 case FLOAT
: case UNSIGNED_FLOAT
:
8154 case FIX
: case UNSIGNED_FIX
:
8155 case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
8156 if (FLOAT_MODE_P (GET_MODE (x
)))
8160 case PROCESSOR_ULTRASPARC
:
8161 case PROCESSOR_ULTRASPARC3
:
8162 return COSTS_N_INSNS (4);
8164 case PROCESSOR_SUPERSPARC
:
8165 return COSTS_N_INSNS (3);
8167 case PROCESSOR_CYPRESS
:
8168 return COSTS_N_INSNS (5);
8170 case PROCESSOR_HYPERSPARC
:
8171 case PROCESSOR_SPARCLITE86X
:
8173 return COSTS_N_INSNS (1);
8177 return COSTS_N_INSNS (1);
8182 case PROCESSOR_ULTRASPARC
:
8183 if (GET_MODE (x
) == SFmode
)
8184 return COSTS_N_INSNS (13);
8186 return COSTS_N_INSNS (23);
8188 case PROCESSOR_ULTRASPARC3
:
8189 if (GET_MODE (x
) == SFmode
)
8190 return COSTS_N_INSNS (20);
8192 return COSTS_N_INSNS (29);
8194 case PROCESSOR_SUPERSPARC
:
8195 return COSTS_N_INSNS (12);
8197 case PROCESSOR_CYPRESS
:
8198 return COSTS_N_INSNS (63);
8200 case PROCESSOR_HYPERSPARC
:
8201 case PROCESSOR_SPARCLITE86X
:
8202 return COSTS_N_INSNS (17);
8205 return COSTS_N_INSNS (30);
8209 if (FLOAT_MODE_P (GET_MODE (x
)))
8213 case PROCESSOR_ULTRASPARC
:
8214 case PROCESSOR_ULTRASPARC3
:
8215 return COSTS_N_INSNS (1);
8217 case PROCESSOR_SUPERSPARC
:
8218 return COSTS_N_INSNS (3);
8220 case PROCESSOR_CYPRESS
:
8221 return COSTS_N_INSNS (5);
8223 case PROCESSOR_HYPERSPARC
:
8224 case PROCESSOR_SPARCLITE86X
:
8226 return COSTS_N_INSNS (1);
8230 /* ??? Maybe mark integer compares as zero cost on
8231 ??? all UltraSPARC processors because the result
8232 ??? can be bypassed to a branch in the same group. */
8234 return COSTS_N_INSNS (1);
8237 if (FLOAT_MODE_P (GET_MODE (x
)))
8241 case PROCESSOR_ULTRASPARC
:
8242 case PROCESSOR_ULTRASPARC3
:
8243 return COSTS_N_INSNS (4);
8245 case PROCESSOR_SUPERSPARC
:
8246 return COSTS_N_INSNS (3);
8248 case PROCESSOR_CYPRESS
:
8249 return COSTS_N_INSNS (7);
8251 case PROCESSOR_HYPERSPARC
:
8252 case PROCESSOR_SPARCLITE86X
:
8253 return COSTS_N_INSNS (1);
8256 return COSTS_N_INSNS (5);
8260 /* The latency is actually variable for Ultra-I/II
8261 And if one of the inputs have a known constant
8262 value, we could calculate this precisely.
8264 However, for that to be useful we would need to
8265 add some machine description changes which would
8266 make sure small constants ended up in rs1 of the
8267 multiply instruction. This is because the multiply
8268 latency is determined by the number of clear (or
8269 set if the value is negative) bits starting from
8270 the most significant bit of the first input.
8272 The algorithm for computing num_cycles of a multiply
8276 highest_bit = highest_clear_bit(rs1);
8278 highest_bit = highest_set_bit(rs1);
8281 num_cycles = 4 + ((highest_bit - 3) / 2);
8283 If we did that we would have to also consider register
8284 allocation issues that would result from forcing such
8285 a value into a register.
8287 There are other similar tricks we could play if we
8288 knew, for example, that one input was an array index.
8290 Since we do not play any such tricks currently the
8291 safest thing to do is report the worst case latency. */
8292 if (sparc_cpu
== PROCESSOR_ULTRASPARC
)
8293 return (GET_MODE (x
) == DImode
?
8294 COSTS_N_INSNS (34) : COSTS_N_INSNS (19));
8296 /* Multiply latency on Ultra-III, fortunately, is constant. */
8297 if (sparc_cpu
== PROCESSOR_ULTRASPARC3
)
8298 return COSTS_N_INSNS (6);
8300 if (sparc_cpu
== PROCESSOR_HYPERSPARC
8301 || sparc_cpu
== PROCESSOR_SPARCLITE86X
)
8302 return COSTS_N_INSNS (17);
8304 return (TARGET_HARD_MUL
8306 : COSTS_N_INSNS (25));
8312 if (FLOAT_MODE_P (GET_MODE (x
)))
8316 case PROCESSOR_ULTRASPARC
:
8317 if (GET_MODE (x
) == SFmode
)
8318 return COSTS_N_INSNS (13);
8320 return COSTS_N_INSNS (23);
8322 case PROCESSOR_ULTRASPARC3
:
8323 if (GET_MODE (x
) == SFmode
)
8324 return COSTS_N_INSNS (17);
8326 return COSTS_N_INSNS (20);
8328 case PROCESSOR_SUPERSPARC
:
8329 if (GET_MODE (x
) == SFmode
)
8330 return COSTS_N_INSNS (6);
8332 return COSTS_N_INSNS (9);
8334 case PROCESSOR_HYPERSPARC
:
8335 case PROCESSOR_SPARCLITE86X
:
8336 if (GET_MODE (x
) == SFmode
)
8337 return COSTS_N_INSNS (8);
8339 return COSTS_N_INSNS (12);
8342 return COSTS_N_INSNS (7);
8346 if (sparc_cpu
== PROCESSOR_ULTRASPARC
)
8347 return (GET_MODE (x
) == DImode
?
8348 COSTS_N_INSNS (68) : COSTS_N_INSNS (37));
8349 if (sparc_cpu
== PROCESSOR_ULTRASPARC3
)
8350 return (GET_MODE (x
) == DImode
?
8351 COSTS_N_INSNS (71) : COSTS_N_INSNS (40));
8352 return COSTS_N_INSNS (25);
8355 /* Conditional moves. */
8358 case PROCESSOR_ULTRASPARC
:
8359 return COSTS_N_INSNS (2);
8361 case PROCESSOR_ULTRASPARC3
:
8362 if (FLOAT_MODE_P (GET_MODE (x
)))
8363 return COSTS_N_INSNS (3);
8365 return COSTS_N_INSNS (2);
8368 return COSTS_N_INSNS (1);
8372 /* If outer-code is SIGN/ZERO extension we have to subtract
8373 out COSTS_N_INSNS (1) from whatever we return in determining
8377 case PROCESSOR_ULTRASPARC
:
8378 if (outer_code
== ZERO_EXTEND
)
8379 return COSTS_N_INSNS (1);
8381 return COSTS_N_INSNS (2);
8383 case PROCESSOR_ULTRASPARC3
:
8384 if (outer_code
== ZERO_EXTEND
)
8386 if (GET_MODE (x
) == QImode
8387 || GET_MODE (x
) == HImode
8388 || outer_code
== SIGN_EXTEND
)
8389 return COSTS_N_INSNS (2);
8391 return COSTS_N_INSNS (1);
8395 /* This handles sign extension (3 cycles)
8396 and everything else (2 cycles). */
8397 return COSTS_N_INSNS (2);
8400 case PROCESSOR_SUPERSPARC
:
8401 if (FLOAT_MODE_P (GET_MODE (x
))
8402 || outer_code
== ZERO_EXTEND
8403 || outer_code
== SIGN_EXTEND
)
8404 return COSTS_N_INSNS (0);
8406 return COSTS_N_INSNS (1);
8408 case PROCESSOR_TSC701
:
8409 if (outer_code
== ZERO_EXTEND
8410 || outer_code
== SIGN_EXTEND
)
8411 return COSTS_N_INSNS (2);
8413 return COSTS_N_INSNS (3);
8415 case PROCESSOR_CYPRESS
:
8416 if (outer_code
== ZERO_EXTEND
8417 || outer_code
== SIGN_EXTEND
)
8418 return COSTS_N_INSNS (1);
8420 return COSTS_N_INSNS (2);
8422 case PROCESSOR_HYPERSPARC
:
8423 case PROCESSOR_SPARCLITE86X
:
8425 if (outer_code
== ZERO_EXTEND
8426 || outer_code
== SIGN_EXTEND
)
8427 return COSTS_N_INSNS (0);
8429 return COSTS_N_INSNS (1);
8433 if (INTVAL (x
) < 0x1000 && INTVAL (x
) >= -0x1000)
8446 if (GET_MODE (x
) == DImode
)
8447 if ((XINT (x
, 3) == 0
8448 && (unsigned) XINT (x
, 2) < 0x1000)
8449 || (XINT (x
, 3) == -1
8451 && XINT (x
, 2) >= -0x1000))