1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 Free Software Foundation, Inc.
6 Contributed by Michael Tiemann (tiemann@cygnus.com)
7 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "insn-codes.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
45 #include "diagnostic-core.h"
50 #include "target-def.h"
51 #include "common/common-target.h"
52 #include "cfglayout.h"
54 #include "langhooks.h"
58 #include "dwarf2out.h"
63 struct processor_costs cypress_costs
= {
64 COSTS_N_INSNS (2), /* int load */
65 COSTS_N_INSNS (2), /* int signed load */
66 COSTS_N_INSNS (2), /* int zeroed load */
67 COSTS_N_INSNS (2), /* float load */
68 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
69 COSTS_N_INSNS (5), /* fadd, fsub */
70 COSTS_N_INSNS (1), /* fcmp */
71 COSTS_N_INSNS (1), /* fmov, fmovr */
72 COSTS_N_INSNS (7), /* fmul */
73 COSTS_N_INSNS (37), /* fdivs */
74 COSTS_N_INSNS (37), /* fdivd */
75 COSTS_N_INSNS (63), /* fsqrts */
76 COSTS_N_INSNS (63), /* fsqrtd */
77 COSTS_N_INSNS (1), /* imul */
78 COSTS_N_INSNS (1), /* imulX */
79 0, /* imul bit factor */
80 COSTS_N_INSNS (1), /* idiv */
81 COSTS_N_INSNS (1), /* idivX */
82 COSTS_N_INSNS (1), /* movcc/movr */
83 0, /* shift penalty */
87 struct processor_costs supersparc_costs
= {
88 COSTS_N_INSNS (1), /* int load */
89 COSTS_N_INSNS (1), /* int signed load */
90 COSTS_N_INSNS (1), /* int zeroed load */
91 COSTS_N_INSNS (0), /* float load */
92 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
93 COSTS_N_INSNS (3), /* fadd, fsub */
94 COSTS_N_INSNS (3), /* fcmp */
95 COSTS_N_INSNS (1), /* fmov, fmovr */
96 COSTS_N_INSNS (3), /* fmul */
97 COSTS_N_INSNS (6), /* fdivs */
98 COSTS_N_INSNS (9), /* fdivd */
99 COSTS_N_INSNS (12), /* fsqrts */
100 COSTS_N_INSNS (12), /* fsqrtd */
101 COSTS_N_INSNS (4), /* imul */
102 COSTS_N_INSNS (4), /* imulX */
103 0, /* imul bit factor */
104 COSTS_N_INSNS (4), /* idiv */
105 COSTS_N_INSNS (4), /* idivX */
106 COSTS_N_INSNS (1), /* movcc/movr */
107 1, /* shift penalty */
111 struct processor_costs hypersparc_costs
= {
112 COSTS_N_INSNS (1), /* int load */
113 COSTS_N_INSNS (1), /* int signed load */
114 COSTS_N_INSNS (1), /* int zeroed load */
115 COSTS_N_INSNS (1), /* float load */
116 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
117 COSTS_N_INSNS (1), /* fadd, fsub */
118 COSTS_N_INSNS (1), /* fcmp */
119 COSTS_N_INSNS (1), /* fmov, fmovr */
120 COSTS_N_INSNS (1), /* fmul */
121 COSTS_N_INSNS (8), /* fdivs */
122 COSTS_N_INSNS (12), /* fdivd */
123 COSTS_N_INSNS (17), /* fsqrts */
124 COSTS_N_INSNS (17), /* fsqrtd */
125 COSTS_N_INSNS (17), /* imul */
126 COSTS_N_INSNS (17), /* imulX */
127 0, /* imul bit factor */
128 COSTS_N_INSNS (17), /* idiv */
129 COSTS_N_INSNS (17), /* idivX */
130 COSTS_N_INSNS (1), /* movcc/movr */
131 0, /* shift penalty */
135 struct processor_costs leon_costs
= {
136 COSTS_N_INSNS (1), /* int load */
137 COSTS_N_INSNS (1), /* int signed load */
138 COSTS_N_INSNS (1), /* int zeroed load */
139 COSTS_N_INSNS (1), /* float load */
140 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
141 COSTS_N_INSNS (1), /* fadd, fsub */
142 COSTS_N_INSNS (1), /* fcmp */
143 COSTS_N_INSNS (1), /* fmov, fmovr */
144 COSTS_N_INSNS (1), /* fmul */
145 COSTS_N_INSNS (15), /* fdivs */
146 COSTS_N_INSNS (15), /* fdivd */
147 COSTS_N_INSNS (23), /* fsqrts */
148 COSTS_N_INSNS (23), /* fsqrtd */
149 COSTS_N_INSNS (5), /* imul */
150 COSTS_N_INSNS (5), /* imulX */
151 0, /* imul bit factor */
152 COSTS_N_INSNS (5), /* idiv */
153 COSTS_N_INSNS (5), /* idivX */
154 COSTS_N_INSNS (1), /* movcc/movr */
155 0, /* shift penalty */
159 struct processor_costs sparclet_costs
= {
160 COSTS_N_INSNS (3), /* int load */
161 COSTS_N_INSNS (3), /* int signed load */
162 COSTS_N_INSNS (1), /* int zeroed load */
163 COSTS_N_INSNS (1), /* float load */
164 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
165 COSTS_N_INSNS (1), /* fadd, fsub */
166 COSTS_N_INSNS (1), /* fcmp */
167 COSTS_N_INSNS (1), /* fmov, fmovr */
168 COSTS_N_INSNS (1), /* fmul */
169 COSTS_N_INSNS (1), /* fdivs */
170 COSTS_N_INSNS (1), /* fdivd */
171 COSTS_N_INSNS (1), /* fsqrts */
172 COSTS_N_INSNS (1), /* fsqrtd */
173 COSTS_N_INSNS (5), /* imul */
174 COSTS_N_INSNS (5), /* imulX */
175 0, /* imul bit factor */
176 COSTS_N_INSNS (5), /* idiv */
177 COSTS_N_INSNS (5), /* idivX */
178 COSTS_N_INSNS (1), /* movcc/movr */
179 0, /* shift penalty */
183 struct processor_costs ultrasparc_costs
= {
184 COSTS_N_INSNS (2), /* int load */
185 COSTS_N_INSNS (3), /* int signed load */
186 COSTS_N_INSNS (2), /* int zeroed load */
187 COSTS_N_INSNS (2), /* float load */
188 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
189 COSTS_N_INSNS (4), /* fadd, fsub */
190 COSTS_N_INSNS (1), /* fcmp */
191 COSTS_N_INSNS (2), /* fmov, fmovr */
192 COSTS_N_INSNS (4), /* fmul */
193 COSTS_N_INSNS (13), /* fdivs */
194 COSTS_N_INSNS (23), /* fdivd */
195 COSTS_N_INSNS (13), /* fsqrts */
196 COSTS_N_INSNS (23), /* fsqrtd */
197 COSTS_N_INSNS (4), /* imul */
198 COSTS_N_INSNS (4), /* imulX */
199 2, /* imul bit factor */
200 COSTS_N_INSNS (37), /* idiv */
201 COSTS_N_INSNS (68), /* idivX */
202 COSTS_N_INSNS (2), /* movcc/movr */
203 2, /* shift penalty */
207 struct processor_costs ultrasparc3_costs
= {
208 COSTS_N_INSNS (2), /* int load */
209 COSTS_N_INSNS (3), /* int signed load */
210 COSTS_N_INSNS (3), /* int zeroed load */
211 COSTS_N_INSNS (2), /* float load */
212 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
213 COSTS_N_INSNS (4), /* fadd, fsub */
214 COSTS_N_INSNS (5), /* fcmp */
215 COSTS_N_INSNS (3), /* fmov, fmovr */
216 COSTS_N_INSNS (4), /* fmul */
217 COSTS_N_INSNS (17), /* fdivs */
218 COSTS_N_INSNS (20), /* fdivd */
219 COSTS_N_INSNS (20), /* fsqrts */
220 COSTS_N_INSNS (29), /* fsqrtd */
221 COSTS_N_INSNS (6), /* imul */
222 COSTS_N_INSNS (6), /* imulX */
223 0, /* imul bit factor */
224 COSTS_N_INSNS (40), /* idiv */
225 COSTS_N_INSNS (71), /* idivX */
226 COSTS_N_INSNS (2), /* movcc/movr */
227 0, /* shift penalty */
231 struct processor_costs niagara_costs
= {
232 COSTS_N_INSNS (3), /* int load */
233 COSTS_N_INSNS (3), /* int signed load */
234 COSTS_N_INSNS (3), /* int zeroed load */
235 COSTS_N_INSNS (9), /* float load */
236 COSTS_N_INSNS (8), /* fmov, fneg, fabs */
237 COSTS_N_INSNS (8), /* fadd, fsub */
238 COSTS_N_INSNS (26), /* fcmp */
239 COSTS_N_INSNS (8), /* fmov, fmovr */
240 COSTS_N_INSNS (29), /* fmul */
241 COSTS_N_INSNS (54), /* fdivs */
242 COSTS_N_INSNS (83), /* fdivd */
243 COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */
244 COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */
245 COSTS_N_INSNS (11), /* imul */
246 COSTS_N_INSNS (11), /* imulX */
247 0, /* imul bit factor */
248 COSTS_N_INSNS (72), /* idiv */
249 COSTS_N_INSNS (72), /* idivX */
250 COSTS_N_INSNS (1), /* movcc/movr */
251 0, /* shift penalty */
255 struct processor_costs niagara2_costs
= {
256 COSTS_N_INSNS (3), /* int load */
257 COSTS_N_INSNS (3), /* int signed load */
258 COSTS_N_INSNS (3), /* int zeroed load */
259 COSTS_N_INSNS (3), /* float load */
260 COSTS_N_INSNS (6), /* fmov, fneg, fabs */
261 COSTS_N_INSNS (6), /* fadd, fsub */
262 COSTS_N_INSNS (6), /* fcmp */
263 COSTS_N_INSNS (6), /* fmov, fmovr */
264 COSTS_N_INSNS (6), /* fmul */
265 COSTS_N_INSNS (19), /* fdivs */
266 COSTS_N_INSNS (33), /* fdivd */
267 COSTS_N_INSNS (19), /* fsqrts */
268 COSTS_N_INSNS (33), /* fsqrtd */
269 COSTS_N_INSNS (5), /* imul */
270 COSTS_N_INSNS (5), /* imulX */
271 0, /* imul bit factor */
272 COSTS_N_INSNS (26), /* idiv, average of 12 - 41 cycle range */
273 COSTS_N_INSNS (26), /* idivX, average of 12 - 41 cycle range */
274 COSTS_N_INSNS (1), /* movcc/movr */
275 0, /* shift penalty */
279 struct processor_costs niagara3_costs
= {
280 COSTS_N_INSNS (3), /* int load */
281 COSTS_N_INSNS (3), /* int signed load */
282 COSTS_N_INSNS (3), /* int zeroed load */
283 COSTS_N_INSNS (3), /* float load */
284 COSTS_N_INSNS (9), /* fmov, fneg, fabs */
285 COSTS_N_INSNS (9), /* fadd, fsub */
286 COSTS_N_INSNS (9), /* fcmp */
287 COSTS_N_INSNS (9), /* fmov, fmovr */
288 COSTS_N_INSNS (9), /* fmul */
289 COSTS_N_INSNS (23), /* fdivs */
290 COSTS_N_INSNS (37), /* fdivd */
291 COSTS_N_INSNS (23), /* fsqrts */
292 COSTS_N_INSNS (37), /* fsqrtd */
293 COSTS_N_INSNS (9), /* imul */
294 COSTS_N_INSNS (9), /* imulX */
295 0, /* imul bit factor */
296 COSTS_N_INSNS (31), /* idiv, average of 17 - 45 cycle range */
297 COSTS_N_INSNS (30), /* idivX, average of 16 - 44 cycle range */
298 COSTS_N_INSNS (1), /* movcc/movr */
299 0, /* shift penalty */
302 const struct processor_costs
*sparc_costs
= &cypress_costs
;
304 #ifdef HAVE_AS_RELAX_OPTION
305 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
306 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
307 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
308 somebody does not branch between the sethi and jmp. */
309 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
311 #define LEAF_SIBCALL_SLOT_RESERVED_P \
312 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
315 /* Vector to say how input registers are mapped to output registers.
316 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
317 eliminate it. You must use -fomit-frame-pointer to get that. */
318 char leaf_reg_remap
[] =
319 { 0, 1, 2, 3, 4, 5, 6, 7,
320 -1, -1, -1, -1, -1, -1, 14, -1,
321 -1, -1, -1, -1, -1, -1, -1, -1,
322 8, 9, 10, 11, 12, 13, -1, 15,
324 32, 33, 34, 35, 36, 37, 38, 39,
325 40, 41, 42, 43, 44, 45, 46, 47,
326 48, 49, 50, 51, 52, 53, 54, 55,
327 56, 57, 58, 59, 60, 61, 62, 63,
328 64, 65, 66, 67, 68, 69, 70, 71,
329 72, 73, 74, 75, 76, 77, 78, 79,
330 80, 81, 82, 83, 84, 85, 86, 87,
331 88, 89, 90, 91, 92, 93, 94, 95,
332 96, 97, 98, 99, 100, 101, 102};
334 /* Vector, indexed by hard register number, which contains 1
335 for a register that is allowable in a candidate for leaf
336 function treatment. */
337 char sparc_leaf_regs
[] =
338 { 1, 1, 1, 1, 1, 1, 1, 1,
339 0, 0, 0, 0, 0, 0, 1, 0,
340 0, 0, 0, 0, 0, 0, 0, 0,
341 1, 1, 1, 1, 1, 1, 0, 1,
342 1, 1, 1, 1, 1, 1, 1, 1,
343 1, 1, 1, 1, 1, 1, 1, 1,
344 1, 1, 1, 1, 1, 1, 1, 1,
345 1, 1, 1, 1, 1, 1, 1, 1,
346 1, 1, 1, 1, 1, 1, 1, 1,
347 1, 1, 1, 1, 1, 1, 1, 1,
348 1, 1, 1, 1, 1, 1, 1, 1,
349 1, 1, 1, 1, 1, 1, 1, 1,
350 1, 1, 1, 1, 1, 1, 1};
352 struct GTY(()) machine_function
354 /* Size of the frame of the function. */
355 HOST_WIDE_INT frame_size
;
357 /* Size of the frame of the function minus the register window save area
358 and the outgoing argument area. */
359 HOST_WIDE_INT apparent_frame_size
;
361 /* Register we pretend the frame pointer is allocated to. Normally, this
362 is %fp, but if we are in a leaf procedure, this is (%sp + offset). We
363 record "offset" separately as it may be too big for (reg + disp). */
365 HOST_WIDE_INT frame_base_offset
;
367 /* Some local-dynamic TLS symbol name. */
368 const char *some_ld_name
;
370 /* Number of global or FP registers to be saved (as 4-byte quantities). */
371 int n_global_fp_regs
;
373 /* True if the current function is leaf and uses only leaf regs,
374 so that the SPARC leaf function optimization can be applied.
375 Private version of current_function_uses_only_leaf_regs, see
376 sparc_expand_prologue for the rationale. */
379 /* True if the prologue saves local or in registers. */
380 bool save_local_in_regs_p
;
382 /* True if the data calculated by sparc_expand_prologue are valid. */
383 bool prologue_data_valid_p
;
386 #define sparc_frame_size cfun->machine->frame_size
387 #define sparc_apparent_frame_size cfun->machine->apparent_frame_size
388 #define sparc_frame_base_reg cfun->machine->frame_base_reg
389 #define sparc_frame_base_offset cfun->machine->frame_base_offset
390 #define sparc_n_global_fp_regs cfun->machine->n_global_fp_regs
391 #define sparc_leaf_function_p cfun->machine->leaf_function_p
392 #define sparc_save_local_in_regs_p cfun->machine->save_local_in_regs_p
393 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
395 /* 1 if the next opcode is to be specially indented. */
396 int sparc_indent_opcode
= 0;
398 static void sparc_option_override (void);
399 static void sparc_init_modes (void);
400 static void scan_record_type (const_tree
, int *, int *, int *);
401 static int function_arg_slotno (const CUMULATIVE_ARGS
*, enum machine_mode
,
402 const_tree
, bool, bool, int *, int *);
404 static int supersparc_adjust_cost (rtx
, rtx
, rtx
, int);
405 static int hypersparc_adjust_cost (rtx
, rtx
, rtx
, int);
407 static void sparc_emit_set_const32 (rtx
, rtx
);
408 static void sparc_emit_set_const64 (rtx
, rtx
);
409 static void sparc_output_addr_vec (rtx
);
410 static void sparc_output_addr_diff_vec (rtx
);
411 static void sparc_output_deferred_case_vectors (void);
412 static bool sparc_legitimate_address_p (enum machine_mode
, rtx
, bool);
413 static bool sparc_legitimate_constant_p (enum machine_mode
, rtx
);
414 static rtx
sparc_builtin_saveregs (void);
415 static int epilogue_renumber (rtx
*, int);
416 static bool sparc_assemble_integer (rtx
, unsigned int, int);
417 static int set_extends (rtx
);
418 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT
);
419 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT
);
420 #ifdef TARGET_SOLARIS
421 static void sparc_solaris_elf_asm_named_section (const char *, unsigned int,
422 tree
) ATTRIBUTE_UNUSED
;
424 static int sparc_adjust_cost (rtx
, rtx
, rtx
, int);
425 static int sparc_issue_rate (void);
426 static void sparc_sched_init (FILE *, int, int);
427 static int sparc_use_sched_lookahead (void);
429 static void emit_soft_tfmode_libcall (const char *, int, rtx
*);
430 static void emit_soft_tfmode_binop (enum rtx_code
, rtx
*);
431 static void emit_soft_tfmode_unop (enum rtx_code
, rtx
*);
432 static void emit_soft_tfmode_cvt (enum rtx_code
, rtx
*);
433 static void emit_hard_tfmode_operation (enum rtx_code
, rtx
*);
435 static bool sparc_function_ok_for_sibcall (tree
, tree
);
436 static void sparc_init_libfuncs (void);
437 static void sparc_init_builtins (void);
438 static void sparc_vis_init_builtins (void);
439 static rtx
sparc_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
440 static tree
sparc_fold_builtin (tree
, int, tree
*, bool);
441 static int sparc_vis_mul8x16 (int, int);
442 static tree
sparc_handle_vis_mul8x16 (int, tree
, tree
, tree
);
443 static void sparc_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
444 HOST_WIDE_INT
, tree
);
445 static bool sparc_can_output_mi_thunk (const_tree
, HOST_WIDE_INT
,
446 HOST_WIDE_INT
, const_tree
);
447 static struct machine_function
* sparc_init_machine_status (void);
448 static bool sparc_cannot_force_const_mem (enum machine_mode
, rtx
);
449 static rtx
sparc_tls_get_addr (void);
450 static rtx
sparc_tls_got (void);
451 static const char *get_some_local_dynamic_name (void);
452 static int get_some_local_dynamic_name_1 (rtx
*, void *);
453 static int sparc_register_move_cost (enum machine_mode
,
454 reg_class_t
, reg_class_t
);
455 static bool sparc_rtx_costs (rtx
, int, int, int, int *, bool);
456 static rtx
sparc_function_value (const_tree
, const_tree
, bool);
457 static rtx
sparc_libcall_value (enum machine_mode
, const_rtx
);
458 static bool sparc_function_value_regno_p (const unsigned int);
459 static rtx
sparc_struct_value_rtx (tree
, int);
460 static enum machine_mode
sparc_promote_function_mode (const_tree
, enum machine_mode
,
461 int *, const_tree
, int);
462 static bool sparc_return_in_memory (const_tree
, const_tree
);
463 static bool sparc_strict_argument_naming (cumulative_args_t
);
464 static void sparc_va_start (tree
, rtx
);
465 static tree
sparc_gimplify_va_arg (tree
, tree
, gimple_seq
*, gimple_seq
*);
466 static bool sparc_vector_mode_supported_p (enum machine_mode
);
467 static bool sparc_tls_referenced_p (rtx
);
468 static rtx
sparc_legitimize_tls_address (rtx
);
469 static rtx
sparc_legitimize_pic_address (rtx
, rtx
);
470 static rtx
sparc_legitimize_address (rtx
, rtx
, enum machine_mode
);
471 static rtx
sparc_delegitimize_address (rtx
);
472 static bool sparc_mode_dependent_address_p (const_rtx
);
473 static bool sparc_pass_by_reference (cumulative_args_t
,
474 enum machine_mode
, const_tree
, bool);
475 static void sparc_function_arg_advance (cumulative_args_t
,
476 enum machine_mode
, const_tree
, bool);
477 static rtx
sparc_function_arg_1 (cumulative_args_t
,
478 enum machine_mode
, const_tree
, bool, bool);
479 static rtx
sparc_function_arg (cumulative_args_t
,
480 enum machine_mode
, const_tree
, bool);
481 static rtx
sparc_function_incoming_arg (cumulative_args_t
,
482 enum machine_mode
, const_tree
, bool);
483 static unsigned int sparc_function_arg_boundary (enum machine_mode
,
485 static int sparc_arg_partial_bytes (cumulative_args_t
,
486 enum machine_mode
, tree
, bool);
487 static void sparc_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
488 static void sparc_file_end (void);
489 static bool sparc_frame_pointer_required (void);
490 static bool sparc_can_eliminate (const int, const int);
491 static rtx
sparc_builtin_setjmp_frame_value (void);
492 static void sparc_conditional_register_usage (void);
493 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
494 static const char *sparc_mangle_type (const_tree
);
496 static void sparc_trampoline_init (rtx
, tree
, rtx
);
497 static enum machine_mode
sparc_preferred_simd_mode (enum machine_mode
);
498 static reg_class_t
sparc_preferred_reload_class (rtx x
, reg_class_t rclass
);
499 static bool sparc_print_operand_punct_valid_p (unsigned char);
500 static void sparc_print_operand (FILE *, rtx
, int);
501 static void sparc_print_operand_address (FILE *, rtx
);
503 #ifdef SUBTARGET_ATTRIBUTE_TABLE
504 /* Table of valid machine attributes. */
505 static const struct attribute_spec sparc_attribute_table
[] =
507 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
509 SUBTARGET_ATTRIBUTE_TABLE
,
510 { NULL
, 0, 0, false, false, false, NULL
, false }
514 /* Option handling. */
517 enum cmodel sparc_cmodel
;
519 char sparc_hard_reg_printed
[8];
521 /* Initialize the GCC target structure. */
523 /* The default is to use .half rather than .short for aligned HI objects. */
524 #undef TARGET_ASM_ALIGNED_HI_OP
525 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
527 #undef TARGET_ASM_UNALIGNED_HI_OP
528 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
529 #undef TARGET_ASM_UNALIGNED_SI_OP
530 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
531 #undef TARGET_ASM_UNALIGNED_DI_OP
532 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
534 /* The target hook has to handle DI-mode values. */
535 #undef TARGET_ASM_INTEGER
536 #define TARGET_ASM_INTEGER sparc_assemble_integer
538 #undef TARGET_ASM_FUNCTION_PROLOGUE
539 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
540 #undef TARGET_ASM_FUNCTION_EPILOGUE
541 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
543 #undef TARGET_SCHED_ADJUST_COST
544 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
545 #undef TARGET_SCHED_ISSUE_RATE
546 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
547 #undef TARGET_SCHED_INIT
548 #define TARGET_SCHED_INIT sparc_sched_init
549 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
550 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
552 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
553 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
555 #undef TARGET_INIT_LIBFUNCS
556 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
557 #undef TARGET_INIT_BUILTINS
558 #define TARGET_INIT_BUILTINS sparc_init_builtins
560 #undef TARGET_LEGITIMIZE_ADDRESS
561 #define TARGET_LEGITIMIZE_ADDRESS sparc_legitimize_address
562 #undef TARGET_DELEGITIMIZE_ADDRESS
563 #define TARGET_DELEGITIMIZE_ADDRESS sparc_delegitimize_address
564 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
565 #define TARGET_MODE_DEPENDENT_ADDRESS_P sparc_mode_dependent_address_p
567 #undef TARGET_EXPAND_BUILTIN
568 #define TARGET_EXPAND_BUILTIN sparc_expand_builtin
569 #undef TARGET_FOLD_BUILTIN
570 #define TARGET_FOLD_BUILTIN sparc_fold_builtin
573 #undef TARGET_HAVE_TLS
574 #define TARGET_HAVE_TLS true
577 #undef TARGET_CANNOT_FORCE_CONST_MEM
578 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
580 #undef TARGET_ASM_OUTPUT_MI_THUNK
581 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
582 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
583 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
585 #undef TARGET_RTX_COSTS
586 #define TARGET_RTX_COSTS sparc_rtx_costs
587 #undef TARGET_ADDRESS_COST
588 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
589 #undef TARGET_REGISTER_MOVE_COST
590 #define TARGET_REGISTER_MOVE_COST sparc_register_move_cost
592 #undef TARGET_PROMOTE_FUNCTION_MODE
593 #define TARGET_PROMOTE_FUNCTION_MODE sparc_promote_function_mode
595 #undef TARGET_FUNCTION_VALUE
596 #define TARGET_FUNCTION_VALUE sparc_function_value
597 #undef TARGET_LIBCALL_VALUE
598 #define TARGET_LIBCALL_VALUE sparc_libcall_value
599 #undef TARGET_FUNCTION_VALUE_REGNO_P
600 #define TARGET_FUNCTION_VALUE_REGNO_P sparc_function_value_regno_p
602 #undef TARGET_STRUCT_VALUE_RTX
603 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
604 #undef TARGET_RETURN_IN_MEMORY
605 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
606 #undef TARGET_MUST_PASS_IN_STACK
607 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
608 #undef TARGET_PASS_BY_REFERENCE
609 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
610 #undef TARGET_ARG_PARTIAL_BYTES
611 #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
612 #undef TARGET_FUNCTION_ARG_ADVANCE
613 #define TARGET_FUNCTION_ARG_ADVANCE sparc_function_arg_advance
614 #undef TARGET_FUNCTION_ARG
615 #define TARGET_FUNCTION_ARG sparc_function_arg
616 #undef TARGET_FUNCTION_INCOMING_ARG
617 #define TARGET_FUNCTION_INCOMING_ARG sparc_function_incoming_arg
618 #undef TARGET_FUNCTION_ARG_BOUNDARY
619 #define TARGET_FUNCTION_ARG_BOUNDARY sparc_function_arg_boundary
621 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
622 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
623 #undef TARGET_STRICT_ARGUMENT_NAMING
624 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
626 #undef TARGET_EXPAND_BUILTIN_VA_START
627 #define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start
628 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
629 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
631 #undef TARGET_VECTOR_MODE_SUPPORTED_P
632 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
634 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
635 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE sparc_preferred_simd_mode
637 #ifdef SUBTARGET_INSERT_ATTRIBUTES
638 #undef TARGET_INSERT_ATTRIBUTES
639 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
642 #ifdef SUBTARGET_ATTRIBUTE_TABLE
643 #undef TARGET_ATTRIBUTE_TABLE
644 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
647 #undef TARGET_RELAXED_ORDERING
648 #define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING
650 #undef TARGET_OPTION_OVERRIDE
651 #define TARGET_OPTION_OVERRIDE sparc_option_override
653 #if TARGET_GNU_TLS && defined(HAVE_AS_SPARC_UA_PCREL)
654 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
655 #define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel
658 #undef TARGET_ASM_FILE_END
659 #define TARGET_ASM_FILE_END sparc_file_end
661 #undef TARGET_FRAME_POINTER_REQUIRED
662 #define TARGET_FRAME_POINTER_REQUIRED sparc_frame_pointer_required
664 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
665 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE sparc_builtin_setjmp_frame_value
667 #undef TARGET_CAN_ELIMINATE
668 #define TARGET_CAN_ELIMINATE sparc_can_eliminate
670 #undef TARGET_PREFERRED_RELOAD_CLASS
671 #define TARGET_PREFERRED_RELOAD_CLASS sparc_preferred_reload_class
673 #undef TARGET_CONDITIONAL_REGISTER_USAGE
674 #define TARGET_CONDITIONAL_REGISTER_USAGE sparc_conditional_register_usage
676 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
677 #undef TARGET_MANGLE_TYPE
678 #define TARGET_MANGLE_TYPE sparc_mangle_type
681 #undef TARGET_LEGITIMATE_ADDRESS_P
682 #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p
684 #undef TARGET_LEGITIMATE_CONSTANT_P
685 #define TARGET_LEGITIMATE_CONSTANT_P sparc_legitimate_constant_p
687 #undef TARGET_TRAMPOLINE_INIT
688 #define TARGET_TRAMPOLINE_INIT sparc_trampoline_init
690 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
691 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sparc_print_operand_punct_valid_p
692 #undef TARGET_PRINT_OPERAND
693 #define TARGET_PRINT_OPERAND sparc_print_operand
694 #undef TARGET_PRINT_OPERAND_ADDRESS
695 #define TARGET_PRINT_OPERAND_ADDRESS sparc_print_operand_address
697 struct gcc_target targetm
= TARGET_INITIALIZER
;
699 /* Validate and override various options, and do some machine dependent
703 sparc_option_override (void)
705 static struct code_model
{
706 const char *const name
;
707 const enum cmodel value
;
708 } const cmodels
[] = {
710 { "medlow", CM_MEDLOW
},
711 { "medmid", CM_MEDMID
},
712 { "medany", CM_MEDANY
},
713 { "embmedany", CM_EMBMEDANY
},
714 { NULL
, (enum cmodel
) 0 }
716 const struct code_model
*cmodel
;
717 /* Map TARGET_CPU_DEFAULT to value for -m{cpu,tune}=. */
718 static struct cpu_default
{
720 const enum processor_type processor
;
721 } const cpu_default
[] = {
722 /* There must be one entry here for each TARGET_CPU value. */
723 { TARGET_CPU_sparc
, PROCESSOR_CYPRESS
},
724 { TARGET_CPU_v8
, PROCESSOR_V8
},
725 { TARGET_CPU_supersparc
, PROCESSOR_SUPERSPARC
},
726 { TARGET_CPU_hypersparc
, PROCESSOR_HYPERSPARC
},
727 { TARGET_CPU_leon
, PROCESSOR_LEON
},
728 { TARGET_CPU_sparclite
, PROCESSOR_F930
},
729 { TARGET_CPU_sparclite86x
, PROCESSOR_SPARCLITE86X
},
730 { TARGET_CPU_sparclet
, PROCESSOR_TSC701
},
731 { TARGET_CPU_v9
, PROCESSOR_V9
},
732 { TARGET_CPU_ultrasparc
, PROCESSOR_ULTRASPARC
},
733 { TARGET_CPU_ultrasparc3
, PROCESSOR_ULTRASPARC3
},
734 { TARGET_CPU_niagara
, PROCESSOR_NIAGARA
},
735 { TARGET_CPU_niagara2
, PROCESSOR_NIAGARA2
},
736 { TARGET_CPU_niagara3
, PROCESSOR_NIAGARA3
},
737 { TARGET_CPU_niagara4
, PROCESSOR_NIAGARA4
},
740 const struct cpu_default
*def
;
741 /* Table of values for -m{cpu,tune}=. This must match the order of
742 the PROCESSOR_* enumeration. */
743 static struct cpu_table
{
746 } const cpu_table
[] = {
749 { MASK_ISA
, MASK_V8
},
750 /* TI TMS390Z55 supersparc */
751 { MASK_ISA
, MASK_V8
},
752 { MASK_ISA
, MASK_V8
|MASK_FPU
},
754 { MASK_ISA
, MASK_V8
|MASK_FPU
},
755 { MASK_ISA
, MASK_SPARCLITE
},
756 /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
757 { MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
758 /* The Fujitsu MB86934 is the recent sparclite chip, with an FPU. */
759 { MASK_ISA
, MASK_SPARCLITE
|MASK_FPU
},
760 { MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
761 { MASK_ISA
, MASK_SPARCLET
},
763 { MASK_ISA
, MASK_SPARCLET
},
764 { MASK_ISA
, MASK_V9
},
765 /* UltraSPARC I, II, IIi */
767 /* Although insns using %y are deprecated, it is a clear win. */
768 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
770 /* ??? Check if %y issue still holds true. */
772 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
775 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
777 { MASK_ISA
, MASK_V9
},
779 { MASK_ISA
, MASK_V9
| MASK_FMAF
},
781 { MASK_ISA
, MASK_V9
| MASK_FMAF
},
783 const struct cpu_table
*cpu
;
787 #ifdef SUBTARGET_OVERRIDE_OPTIONS
788 SUBTARGET_OVERRIDE_OPTIONS
;
791 #ifndef SPARC_BI_ARCH
792 /* Check for unsupported architecture size. */
793 if (! TARGET_64BIT
!= DEFAULT_ARCH32_P
)
794 error ("%s is not supported by this configuration",
795 DEFAULT_ARCH32_P
? "-m64" : "-m32");
798 /* We force all 64bit archs to use 128 bit long double */
799 if (TARGET_64BIT
&& ! TARGET_LONG_DOUBLE_128
)
801 error ("-mlong-double-64 not allowed with -m64");
802 target_flags
|= MASK_LONG_DOUBLE_128
;
805 /* Code model selection. */
806 sparc_cmodel
= SPARC_DEFAULT_CMODEL
;
810 sparc_cmodel
= CM_32
;
813 if (sparc_cmodel_string
!= NULL
)
817 for (cmodel
= &cmodels
[0]; cmodel
->name
; cmodel
++)
818 if (strcmp (sparc_cmodel_string
, cmodel
->name
) == 0)
820 if (cmodel
->name
== NULL
)
821 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string
);
823 sparc_cmodel
= cmodel
->value
;
826 error ("-mcmodel= is not supported on 32 bit systems");
829 /* Check that -fcall-saved-REG wasn't specified for out registers. */
830 for (i
= 8; i
< 16; i
++)
831 if (!call_used_regs
[i
])
833 error ("-fcall-saved-REG is not supported for out registers");
834 call_used_regs
[i
] = 1;
837 fpu
= target_flags
& MASK_FPU
; /* save current -mfpu status */
839 /* Set the default CPU. */
840 if (!global_options_set
.x_sparc_cpu_and_features
)
842 for (def
= &cpu_default
[0]; def
->cpu
!= -1; ++def
)
843 if (def
->cpu
== TARGET_CPU_DEFAULT
)
845 gcc_assert (def
->cpu
!= -1);
846 sparc_cpu_and_features
= def
->processor
;
848 if (!global_options_set
.x_sparc_cpu
)
849 sparc_cpu
= sparc_cpu_and_features
;
851 cpu
= &cpu_table
[(int) sparc_cpu_and_features
];
852 target_flags
&= ~cpu
->disable
;
853 target_flags
|= cpu
->enable
;
855 /* If -mfpu or -mno-fpu was explicitly used, don't override with
856 the processor default. */
857 if (target_flags_explicit
& MASK_FPU
)
858 target_flags
= (target_flags
& ~MASK_FPU
) | fpu
;
860 /* Don't allow -mvis or -mfmaf if FPU is disabled. */
862 target_flags
&= ~(MASK_VIS
| MASK_FMAF
);
864 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
866 -m64 also implies v9. */
867 if (TARGET_VIS
|| TARGET_ARCH64
)
869 target_flags
|= MASK_V9
;
870 target_flags
&= ~(MASK_V8
| MASK_SPARCLET
| MASK_SPARCLITE
);
873 /* -mvis also implies -mv8plus on 32-bit */
874 if (TARGET_VIS
&& ! TARGET_ARCH64
)
875 target_flags
|= MASK_V8PLUS
;
877 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
878 if (TARGET_V9
&& TARGET_ARCH32
)
879 target_flags
|= MASK_DEPRECATED_V8_INSNS
;
881 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
882 if (! TARGET_V9
|| TARGET_ARCH64
)
883 target_flags
&= ~MASK_V8PLUS
;
885 /* Don't use stack biasing in 32 bit mode. */
887 target_flags
&= ~MASK_STACK_BIAS
;
889 /* Supply a default value for align_functions. */
890 if (align_functions
== 0
891 && (sparc_cpu
== PROCESSOR_ULTRASPARC
892 || sparc_cpu
== PROCESSOR_ULTRASPARC3
893 || sparc_cpu
== PROCESSOR_NIAGARA
894 || sparc_cpu
== PROCESSOR_NIAGARA2
895 || sparc_cpu
== PROCESSOR_NIAGARA3
896 || sparc_cpu
== PROCESSOR_NIAGARA4
))
897 align_functions
= 32;
899 /* Validate PCC_STRUCT_RETURN. */
900 if (flag_pcc_struct_return
== DEFAULT_PCC_STRUCT_RETURN
)
901 flag_pcc_struct_return
= (TARGET_ARCH64
? 0 : 1);
903 /* Only use .uaxword when compiling for a 64-bit target. */
905 targetm
.asm_out
.unaligned_op
.di
= NULL
;
907 /* Do various machine dependent initializations. */
910 /* Set up function hooks. */
911 init_machine_status
= sparc_init_machine_status
;
916 case PROCESSOR_CYPRESS
:
917 sparc_costs
= &cypress_costs
;
920 case PROCESSOR_SPARCLITE
:
921 case PROCESSOR_SUPERSPARC
:
922 sparc_costs
= &supersparc_costs
;
926 case PROCESSOR_HYPERSPARC
:
927 case PROCESSOR_SPARCLITE86X
:
928 sparc_costs
= &hypersparc_costs
;
931 sparc_costs
= &leon_costs
;
933 case PROCESSOR_SPARCLET
:
934 case PROCESSOR_TSC701
:
935 sparc_costs
= &sparclet_costs
;
938 case PROCESSOR_ULTRASPARC
:
939 sparc_costs
= &ultrasparc_costs
;
941 case PROCESSOR_ULTRASPARC3
:
942 sparc_costs
= &ultrasparc3_costs
;
944 case PROCESSOR_NIAGARA
:
945 sparc_costs
= &niagara_costs
;
947 case PROCESSOR_NIAGARA2
:
948 sparc_costs
= &niagara2_costs
;
950 case PROCESSOR_NIAGARA3
:
951 case PROCESSOR_NIAGARA4
:
952 sparc_costs
= &niagara3_costs
;
954 case PROCESSOR_NATIVE
:
958 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
959 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
960 target_flags
|= MASK_LONG_DOUBLE_128
;
963 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
964 ((sparc_cpu
== PROCESSOR_ULTRASPARC
965 || sparc_cpu
== PROCESSOR_NIAGARA
966 || sparc_cpu
== PROCESSOR_NIAGARA2
967 || sparc_cpu
== PROCESSOR_NIAGARA3
968 || sparc_cpu
== PROCESSOR_NIAGARA4
)
970 : (sparc_cpu
== PROCESSOR_ULTRASPARC3
972 global_options
.x_param_values
,
973 global_options_set
.x_param_values
);
974 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
975 ((sparc_cpu
== PROCESSOR_ULTRASPARC
976 || sparc_cpu
== PROCESSOR_ULTRASPARC3
977 || sparc_cpu
== PROCESSOR_NIAGARA
978 || sparc_cpu
== PROCESSOR_NIAGARA2
979 || sparc_cpu
== PROCESSOR_NIAGARA3
980 || sparc_cpu
== PROCESSOR_NIAGARA4
)
982 global_options
.x_param_values
,
983 global_options_set
.x_param_values
);
985 /* Disable save slot sharing for call-clobbered registers by default.
986 The IRA sharing algorithm works on single registers only and this
987 pessimizes for double floating-point registers. */
988 if (!global_options_set
.x_flag_ira_share_save_slots
)
989 flag_ira_share_save_slots
= 0;
992 /* Miscellaneous utilities. */
994 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
995 or branch on register contents instructions. */
998 v9_regcmp_p (enum rtx_code code
)
1000 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
1001 || code
== LE
|| code
== GT
);
1004 /* Nonzero if OP is a floating point constant which can
1005 be loaded into an integer register using a single
1006 sethi instruction. */
1011 if (GET_CODE (op
) == CONST_DOUBLE
)
1016 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1017 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1018 return !SPARC_SIMM13_P (i
) && SPARC_SETHI_P (i
);
1024 /* Nonzero if OP is a floating point constant which can
1025 be loaded into an integer register using a single
1031 if (GET_CODE (op
) == CONST_DOUBLE
)
1036 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1037 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1038 return SPARC_SIMM13_P (i
);
1044 /* Nonzero if OP is a floating point constant which can
1045 be loaded into an integer register using a high/losum
1046 instruction sequence. */
1049 fp_high_losum_p (rtx op
)
1051 /* The constraints calling this should only be in
1052 SFmode move insns, so any constant which cannot
1053 be moved using a single insn will do. */
1054 if (GET_CODE (op
) == CONST_DOUBLE
)
1059 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1060 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1061 return !SPARC_SIMM13_P (i
) && !SPARC_SETHI_P (i
);
1067 /* Return true if the address of LABEL can be loaded by means of the
1068 mov{si,di}_pic_label_ref patterns in PIC mode. */
1071 can_use_mov_pic_label_ref (rtx label
)
1073 /* VxWorks does not impose a fixed gap between segments; the run-time
1074 gap can be different from the object-file gap. We therefore can't
1075 assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
1076 are absolutely sure that X is in the same segment as the GOT.
1077 Unfortunately, the flexibility of linker scripts means that we
1078 can't be sure of that in general, so assume that GOT-relative
1079 accesses are never valid on VxWorks. */
1080 if (TARGET_VXWORKS_RTP
)
1083 /* Similarly, if the label is non-local, it might end up being placed
1084 in a different section than the current one; now mov_pic_label_ref
1085 requires the label and the code to be in the same section. */
1086 if (LABEL_REF_NONLOCAL_P (label
))
1089 /* Finally, if we are reordering basic blocks and partition into hot
1090 and cold sections, this might happen for any label. */
1091 if (flag_reorder_blocks_and_partition
)
1097 /* Expand a move instruction. Return true if all work is done. */
1100 sparc_expand_move (enum machine_mode mode
, rtx
*operands
)
1102 /* Handle sets of MEM first. */
1103 if (GET_CODE (operands
[0]) == MEM
)
1105 /* 0 is a register (or a pair of registers) on SPARC. */
1106 if (register_or_zero_operand (operands
[1], mode
))
1109 if (!reload_in_progress
)
1111 operands
[0] = validize_mem (operands
[0]);
1112 operands
[1] = force_reg (mode
, operands
[1]);
1116 /* Fixup TLS cases. */
1118 && CONSTANT_P (operands
[1])
1119 && sparc_tls_referenced_p (operands
[1]))
1121 operands
[1] = sparc_legitimize_tls_address (operands
[1]);
1125 /* Fixup PIC cases. */
1126 if (flag_pic
&& CONSTANT_P (operands
[1]))
1128 if (pic_address_needs_scratch (operands
[1]))
1129 operands
[1] = sparc_legitimize_pic_address (operands
[1], NULL_RTX
);
1131 /* We cannot use the mov{si,di}_pic_label_ref patterns in all cases. */
1132 if (GET_CODE (operands
[1]) == LABEL_REF
1133 && can_use_mov_pic_label_ref (operands
[1]))
1137 emit_insn (gen_movsi_pic_label_ref (operands
[0], operands
[1]));
1143 gcc_assert (TARGET_ARCH64
);
1144 emit_insn (gen_movdi_pic_label_ref (operands
[0], operands
[1]));
1149 if (symbolic_operand (operands
[1], mode
))
1152 = sparc_legitimize_pic_address (operands
[1],
1154 ? operands
[0] : NULL_RTX
);
1159 /* If we are trying to toss an integer constant into FP registers,
1160 or loading a FP or vector constant, force it into memory. */
1161 if (CONSTANT_P (operands
[1])
1162 && REG_P (operands
[0])
1163 && (SPARC_FP_REG_P (REGNO (operands
[0]))
1164 || SCALAR_FLOAT_MODE_P (mode
)
1165 || VECTOR_MODE_P (mode
)))
1167 /* emit_group_store will send such bogosity to us when it is
1168 not storing directly into memory. So fix this up to avoid
1169 crashes in output_constant_pool. */
1170 if (operands
[1] == const0_rtx
)
1171 operands
[1] = CONST0_RTX (mode
);
1173 /* We can clear or set to all-ones FP registers if TARGET_VIS, and
1174 always other regs. */
1175 if ((TARGET_VIS
|| REGNO (operands
[0]) < SPARC_FIRST_FP_REG
)
1176 && (const_zero_operand (operands
[1], mode
)
1177 || const_all_ones_operand (operands
[1], mode
)))
1180 if (REGNO (operands
[0]) < SPARC_FIRST_FP_REG
1181 /* We are able to build any SF constant in integer registers
1182 with at most 2 instructions. */
1184 /* And any DF constant in integer registers. */
1186 && (reload_completed
|| reload_in_progress
))))
1189 operands
[1] = force_const_mem (mode
, operands
[1]);
1190 if (!reload_in_progress
)
1191 operands
[1] = validize_mem (operands
[1]);
1195 /* Accept non-constants and valid constants unmodified. */
1196 if (!CONSTANT_P (operands
[1])
1197 || GET_CODE (operands
[1]) == HIGH
1198 || input_operand (operands
[1], mode
))
1204 /* All QImode constants require only one insn, so proceed. */
1209 sparc_emit_set_const32 (operands
[0], operands
[1]);
1213 /* input_operand should have filtered out 32-bit mode. */
1214 sparc_emit_set_const64 (operands
[0], operands
[1]);
1224 /* Load OP1, a 32-bit constant, into OP0, a register.
1225 We know it can't be done in one insn when we get
1226 here, the move expander guarantees this. */
1229 sparc_emit_set_const32 (rtx op0
, rtx op1
)
1231 enum machine_mode mode
= GET_MODE (op0
);
1234 if (reload_in_progress
|| reload_completed
)
1237 temp
= gen_reg_rtx (mode
);
1239 if (GET_CODE (op1
) == CONST_INT
)
1241 gcc_assert (!small_int_operand (op1
, mode
)
1242 && !const_high_operand (op1
, mode
));
1244 /* Emit them as real moves instead of a HIGH/LO_SUM,
1245 this way CSE can see everything and reuse intermediate
1246 values if it wants. */
1247 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1248 GEN_INT (INTVAL (op1
)
1249 & ~(HOST_WIDE_INT
)0x3ff)));
1251 emit_insn (gen_rtx_SET (VOIDmode
,
1253 gen_rtx_IOR (mode
, temp
,
1254 GEN_INT (INTVAL (op1
) & 0x3ff))));
1258 /* A symbol, emit in the traditional way. */
1259 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1260 gen_rtx_HIGH (mode
, op1
)));
1261 emit_insn (gen_rtx_SET (VOIDmode
,
1262 op0
, gen_rtx_LO_SUM (mode
, temp
, op1
)));
1266 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1267 If TEMP is nonzero, we are forbidden to use any other scratch
1268 registers. Otherwise, we are allowed to generate them as needed.
1270 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1271 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1274 sparc_emit_set_symbolic_const64 (rtx op0
, rtx op1
, rtx temp
)
1276 rtx temp1
, temp2
, temp3
, temp4
, temp5
;
1279 if (temp
&& GET_MODE (temp
) == TImode
)
1282 temp
= gen_rtx_REG (DImode
, REGNO (temp
));
1285 /* SPARC-V9 code-model support. */
1286 switch (sparc_cmodel
)
1289 /* The range spanned by all instructions in the object is less
1290 than 2^31 bytes (2GB) and the distance from any instruction
1291 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1292 than 2^31 bytes (2GB).
1294 The executable must be in the low 4TB of the virtual address
1297 sethi %hi(symbol), %temp1
1298 or %temp1, %lo(symbol), %reg */
1300 temp1
= temp
; /* op0 is allowed. */
1302 temp1
= gen_reg_rtx (DImode
);
1304 emit_insn (gen_rtx_SET (VOIDmode
, temp1
, gen_rtx_HIGH (DImode
, op1
)));
1305 emit_insn (gen_rtx_SET (VOIDmode
, op0
, gen_rtx_LO_SUM (DImode
, temp1
, op1
)));
1309 /* The range spanned by all instructions in the object is less
1310 than 2^31 bytes (2GB) and the distance from any instruction
1311 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1312 than 2^31 bytes (2GB).
1314 The executable must be in the low 16TB of the virtual address
1317 sethi %h44(symbol), %temp1
1318 or %temp1, %m44(symbol), %temp2
1319 sllx %temp2, 12, %temp3
1320 or %temp3, %l44(symbol), %reg */
1325 temp3
= temp
; /* op0 is allowed. */
1329 temp1
= gen_reg_rtx (DImode
);
1330 temp2
= gen_reg_rtx (DImode
);
1331 temp3
= gen_reg_rtx (DImode
);
1334 emit_insn (gen_seth44 (temp1
, op1
));
1335 emit_insn (gen_setm44 (temp2
, temp1
, op1
));
1336 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
1337 gen_rtx_ASHIFT (DImode
, temp2
, GEN_INT (12))));
1338 emit_insn (gen_setl44 (op0
, temp3
, op1
));
1342 /* The range spanned by all instructions in the object is less
1343 than 2^31 bytes (2GB) and the distance from any instruction
1344 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1345 than 2^31 bytes (2GB).
1347 The executable can be placed anywhere in the virtual address
1350 sethi %hh(symbol), %temp1
1351 sethi %lm(symbol), %temp2
1352 or %temp1, %hm(symbol), %temp3
1353 sllx %temp3, 32, %temp4
1354 or %temp4, %temp2, %temp5
1355 or %temp5, %lo(symbol), %reg */
1358 /* It is possible that one of the registers we got for operands[2]
1359 might coincide with that of operands[0] (which is why we made
1360 it TImode). Pick the other one to use as our scratch. */
1361 if (rtx_equal_p (temp
, op0
))
1363 gcc_assert (ti_temp
);
1364 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
1367 temp2
= temp
; /* op0 is _not_ allowed, see above. */
1374 temp1
= gen_reg_rtx (DImode
);
1375 temp2
= gen_reg_rtx (DImode
);
1376 temp3
= gen_reg_rtx (DImode
);
1377 temp4
= gen_reg_rtx (DImode
);
1378 temp5
= gen_reg_rtx (DImode
);
1381 emit_insn (gen_sethh (temp1
, op1
));
1382 emit_insn (gen_setlm (temp2
, op1
));
1383 emit_insn (gen_sethm (temp3
, temp1
, op1
));
1384 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1385 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
1386 emit_insn (gen_rtx_SET (VOIDmode
, temp5
,
1387 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1388 emit_insn (gen_setlo (op0
, temp5
, op1
));
1392 /* Old old old backwards compatibility kruft here.
1393 Essentially it is MEDLOW with a fixed 64-bit
1394 virtual base added to all data segment addresses.
1395 Text-segment stuff is computed like MEDANY, we can't
1396 reuse the code above because the relocation knobs
1399 Data segment: sethi %hi(symbol), %temp1
1400 add %temp1, EMBMEDANY_BASE_REG, %temp2
1401 or %temp2, %lo(symbol), %reg */
1402 if (data_segment_operand (op1
, GET_MODE (op1
)))
1406 temp1
= temp
; /* op0 is allowed. */
1411 temp1
= gen_reg_rtx (DImode
);
1412 temp2
= gen_reg_rtx (DImode
);
1415 emit_insn (gen_embmedany_sethi (temp1
, op1
));
1416 emit_insn (gen_embmedany_brsum (temp2
, temp1
));
1417 emit_insn (gen_embmedany_losum (op0
, temp2
, op1
));
1420 /* Text segment: sethi %uhi(symbol), %temp1
1421 sethi %hi(symbol), %temp2
1422 or %temp1, %ulo(symbol), %temp3
1423 sllx %temp3, 32, %temp4
1424 or %temp4, %temp2, %temp5
1425 or %temp5, %lo(symbol), %reg */
1430 /* It is possible that one of the registers we got for operands[2]
1431 might coincide with that of operands[0] (which is why we made
1432 it TImode). Pick the other one to use as our scratch. */
1433 if (rtx_equal_p (temp
, op0
))
1435 gcc_assert (ti_temp
);
1436 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
1439 temp2
= temp
; /* op0 is _not_ allowed, see above. */
1446 temp1
= gen_reg_rtx (DImode
);
1447 temp2
= gen_reg_rtx (DImode
);
1448 temp3
= gen_reg_rtx (DImode
);
1449 temp4
= gen_reg_rtx (DImode
);
1450 temp5
= gen_reg_rtx (DImode
);
1453 emit_insn (gen_embmedany_textuhi (temp1
, op1
));
1454 emit_insn (gen_embmedany_texthi (temp2
, op1
));
1455 emit_insn (gen_embmedany_textulo (temp3
, temp1
, op1
));
1456 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1457 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
1458 emit_insn (gen_rtx_SET (VOIDmode
, temp5
,
1459 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1460 emit_insn (gen_embmedany_textlo (op0
, temp5
, op1
));
1469 #if HOST_BITS_PER_WIDE_INT == 32
1471 sparc_emit_set_const64 (rtx op0 ATTRIBUTE_UNUSED
, rtx op1 ATTRIBUTE_UNUSED
)
1476 /* These avoid problems when cross compiling. If we do not
1477 go through all this hair then the optimizer will see
1478 invalid REG_EQUAL notes or in some cases none at all. */
1479 static rtx
gen_safe_HIGH64 (rtx
, HOST_WIDE_INT
);
1480 static rtx
gen_safe_SET64 (rtx
, HOST_WIDE_INT
);
1481 static rtx
gen_safe_OR64 (rtx
, HOST_WIDE_INT
);
1482 static rtx
gen_safe_XOR64 (rtx
, HOST_WIDE_INT
);
1484 /* The optimizer is not to assume anything about exactly
1485 which bits are set for a HIGH, they are unspecified.
1486 Unfortunately this leads to many missed optimizations
1487 during CSE. We mask out the non-HIGH bits, and matches
1488 a plain movdi, to alleviate this problem. */
1490 gen_safe_HIGH64 (rtx dest
, HOST_WIDE_INT val
)
1492 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT (val
& ~(HOST_WIDE_INT
)0x3ff));
1496 gen_safe_SET64 (rtx dest
, HOST_WIDE_INT val
)
1498 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT (val
));
1502 gen_safe_OR64 (rtx src
, HOST_WIDE_INT val
)
1504 return gen_rtx_IOR (DImode
, src
, GEN_INT (val
));
1508 gen_safe_XOR64 (rtx src
, HOST_WIDE_INT val
)
1510 return gen_rtx_XOR (DImode
, src
, GEN_INT (val
));
1513 /* Worker routines for 64-bit constant formation on arch64.
1514 One of the key things to be doing in these emissions is
1515 to create as many temp REGs as possible. This makes it
1516 possible for half-built constants to be used later when
1517 such values are similar to something required later on.
1518 Without doing this, the optimizer cannot see such
1521 static void sparc_emit_set_const64_quick1 (rtx
, rtx
,
1522 unsigned HOST_WIDE_INT
, int);
1525 sparc_emit_set_const64_quick1 (rtx op0
, rtx temp
,
1526 unsigned HOST_WIDE_INT low_bits
, int is_neg
)
1528 unsigned HOST_WIDE_INT high_bits
;
1531 high_bits
= (~low_bits
) & 0xffffffff;
1533 high_bits
= low_bits
;
1535 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
1538 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1539 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1543 /* If we are XOR'ing with -1, then we should emit a one's complement
1544 instead. This way the combiner will notice logical operations
1545 such as ANDN later on and substitute. */
1546 if ((low_bits
& 0x3ff) == 0x3ff)
1548 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1549 gen_rtx_NOT (DImode
, temp
)));
1553 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1554 gen_safe_XOR64 (temp
,
1555 (-(HOST_WIDE_INT
)0x400
1556 | (low_bits
& 0x3ff)))));
1561 static void sparc_emit_set_const64_quick2 (rtx
, rtx
, unsigned HOST_WIDE_INT
,
1562 unsigned HOST_WIDE_INT
, int);
1565 sparc_emit_set_const64_quick2 (rtx op0
, rtx temp
,
1566 unsigned HOST_WIDE_INT high_bits
,
1567 unsigned HOST_WIDE_INT low_immediate
,
1572 if ((high_bits
& 0xfffffc00) != 0)
1574 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
1575 if ((high_bits
& ~0xfffffc00) != 0)
1576 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1577 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1583 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1587 /* Now shift it up into place. */
1588 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1589 gen_rtx_ASHIFT (DImode
, temp2
,
1590 GEN_INT (shift_count
))));
1592 /* If there is a low immediate part piece, finish up by
1593 putting that in as well. */
1594 if (low_immediate
!= 0)
1595 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1596 gen_safe_OR64 (op0
, low_immediate
)));
1599 static void sparc_emit_set_const64_longway (rtx
, rtx
, unsigned HOST_WIDE_INT
,
1600 unsigned HOST_WIDE_INT
);
1602 /* Full 64-bit constant decomposition. Even though this is the
1603 'worst' case, we still optimize a few things away. */
1605 sparc_emit_set_const64_longway (rtx op0
, rtx temp
,
1606 unsigned HOST_WIDE_INT high_bits
,
1607 unsigned HOST_WIDE_INT low_bits
)
1611 if (reload_in_progress
|| reload_completed
)
1614 sub_temp
= gen_reg_rtx (DImode
);
1616 if ((high_bits
& 0xfffffc00) != 0)
1618 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
1619 if ((high_bits
& ~0xfffffc00) != 0)
1620 emit_insn (gen_rtx_SET (VOIDmode
,
1622 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1628 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1632 if (!reload_in_progress
&& !reload_completed
)
1634 rtx temp2
= gen_reg_rtx (DImode
);
1635 rtx temp3
= gen_reg_rtx (DImode
);
1636 rtx temp4
= gen_reg_rtx (DImode
);
1638 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1639 gen_rtx_ASHIFT (DImode
, sub_temp
,
1642 emit_insn (gen_safe_HIGH64 (temp2
, low_bits
));
1643 if ((low_bits
& ~0xfffffc00) != 0)
1645 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
1646 gen_safe_OR64 (temp2
, (low_bits
& 0x3ff))));
1647 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1648 gen_rtx_PLUS (DImode
, temp4
, temp3
)));
1652 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1653 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1658 rtx low1
= GEN_INT ((low_bits
>> (32 - 12)) & 0xfff);
1659 rtx low2
= GEN_INT ((low_bits
>> (32 - 12 - 12)) & 0xfff);
1660 rtx low3
= GEN_INT ((low_bits
>> (32 - 12 - 12 - 8)) & 0x0ff);
1663 /* We are in the middle of reload, so this is really
1664 painful. However we do still make an attempt to
1665 avoid emitting truly stupid code. */
1666 if (low1
!= const0_rtx
)
1668 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1669 gen_rtx_ASHIFT (DImode
, sub_temp
,
1670 GEN_INT (to_shift
))));
1671 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1672 gen_rtx_IOR (DImode
, op0
, low1
)));
1680 if (low2
!= const0_rtx
)
1682 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1683 gen_rtx_ASHIFT (DImode
, sub_temp
,
1684 GEN_INT (to_shift
))));
1685 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1686 gen_rtx_IOR (DImode
, op0
, low2
)));
1694 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1695 gen_rtx_ASHIFT (DImode
, sub_temp
,
1696 GEN_INT (to_shift
))));
1697 if (low3
!= const0_rtx
)
1698 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1699 gen_rtx_IOR (DImode
, op0
, low3
)));
1704 /* Analyze a 64-bit constant for certain properties. */
1705 static void analyze_64bit_constant (unsigned HOST_WIDE_INT
,
1706 unsigned HOST_WIDE_INT
,
1707 int *, int *, int *);
1710 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits
,
1711 unsigned HOST_WIDE_INT low_bits
,
1712 int *hbsp
, int *lbsp
, int *abbasp
)
1714 int lowest_bit_set
, highest_bit_set
, all_bits_between_are_set
;
1717 lowest_bit_set
= highest_bit_set
= -1;
1721 if ((lowest_bit_set
== -1)
1722 && ((low_bits
>> i
) & 1))
1724 if ((highest_bit_set
== -1)
1725 && ((high_bits
>> (32 - i
- 1)) & 1))
1726 highest_bit_set
= (64 - i
- 1);
1729 && ((highest_bit_set
== -1)
1730 || (lowest_bit_set
== -1)));
1736 if ((lowest_bit_set
== -1)
1737 && ((high_bits
>> i
) & 1))
1738 lowest_bit_set
= i
+ 32;
1739 if ((highest_bit_set
== -1)
1740 && ((low_bits
>> (32 - i
- 1)) & 1))
1741 highest_bit_set
= 32 - i
- 1;
1744 && ((highest_bit_set
== -1)
1745 || (lowest_bit_set
== -1)));
1747 /* If there are no bits set this should have gone out
1748 as one instruction! */
1749 gcc_assert (lowest_bit_set
!= -1 && highest_bit_set
!= -1);
1750 all_bits_between_are_set
= 1;
1751 for (i
= lowest_bit_set
; i
<= highest_bit_set
; i
++)
1755 if ((low_bits
& (1 << i
)) != 0)
1760 if ((high_bits
& (1 << (i
- 32))) != 0)
1763 all_bits_between_are_set
= 0;
1766 *hbsp
= highest_bit_set
;
1767 *lbsp
= lowest_bit_set
;
1768 *abbasp
= all_bits_between_are_set
;
1771 static int const64_is_2insns (unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
);
1774 const64_is_2insns (unsigned HOST_WIDE_INT high_bits
,
1775 unsigned HOST_WIDE_INT low_bits
)
1777 int highest_bit_set
, lowest_bit_set
, all_bits_between_are_set
;
1780 || high_bits
== 0xffffffff)
1783 analyze_64bit_constant (high_bits
, low_bits
,
1784 &highest_bit_set
, &lowest_bit_set
,
1785 &all_bits_between_are_set
);
1787 if ((highest_bit_set
== 63
1788 || lowest_bit_set
== 0)
1789 && all_bits_between_are_set
!= 0)
1792 if ((highest_bit_set
- lowest_bit_set
) < 21)
1798 static unsigned HOST_WIDE_INT
create_simple_focus_bits (unsigned HOST_WIDE_INT
,
1799 unsigned HOST_WIDE_INT
,
1802 static unsigned HOST_WIDE_INT
1803 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits
,
1804 unsigned HOST_WIDE_INT low_bits
,
1805 int lowest_bit_set
, int shift
)
1807 HOST_WIDE_INT hi
, lo
;
1809 if (lowest_bit_set
< 32)
1811 lo
= (low_bits
>> lowest_bit_set
) << shift
;
1812 hi
= ((high_bits
<< (32 - lowest_bit_set
)) << shift
);
1817 hi
= ((high_bits
>> (lowest_bit_set
- 32)) << shift
);
1819 gcc_assert (! (hi
& lo
));
1823 /* Here we are sure to be arch64 and this is an integer constant
1824 being loaded into a register. Emit the most efficient
1825 insn sequence possible. Detection of all the 1-insn cases
1826 has been done already. */
1828 sparc_emit_set_const64 (rtx op0
, rtx op1
)
1830 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1831 int lowest_bit_set
, highest_bit_set
;
1832 int all_bits_between_are_set
;
1835 /* Sanity check that we know what we are working with. */
1836 gcc_assert (TARGET_ARCH64
1837 && (GET_CODE (op0
) == SUBREG
1838 || (REG_P (op0
) && ! SPARC_FP_REG_P (REGNO (op0
)))));
1840 if (reload_in_progress
|| reload_completed
)
1843 if (GET_CODE (op1
) != CONST_INT
)
1845 sparc_emit_set_symbolic_const64 (op0
, op1
, temp
);
1850 temp
= gen_reg_rtx (DImode
);
1852 high_bits
= ((INTVAL (op1
) >> 32) & 0xffffffff);
1853 low_bits
= (INTVAL (op1
) & 0xffffffff);
1855 /* low_bits bits 0 --> 31
1856 high_bits bits 32 --> 63 */
1858 analyze_64bit_constant (high_bits
, low_bits
,
1859 &highest_bit_set
, &lowest_bit_set
,
1860 &all_bits_between_are_set
);
1862 /* First try for a 2-insn sequence. */
1864 /* These situations are preferred because the optimizer can
1865 * do more things with them:
1867 * sllx %reg, shift, %reg
1869 * srlx %reg, shift, %reg
1870 * 3) mov some_small_const, %reg
1871 * sllx %reg, shift, %reg
1873 if (((highest_bit_set
== 63
1874 || lowest_bit_set
== 0)
1875 && all_bits_between_are_set
!= 0)
1876 || ((highest_bit_set
- lowest_bit_set
) < 12))
1878 HOST_WIDE_INT the_const
= -1;
1879 int shift
= lowest_bit_set
;
1881 if ((highest_bit_set
!= 63
1882 && lowest_bit_set
!= 0)
1883 || all_bits_between_are_set
== 0)
1886 create_simple_focus_bits (high_bits
, low_bits
,
1889 else if (lowest_bit_set
== 0)
1890 shift
= -(63 - highest_bit_set
);
1892 gcc_assert (SPARC_SIMM13_P (the_const
));
1893 gcc_assert (shift
!= 0);
1895 emit_insn (gen_safe_SET64 (temp
, the_const
));
1897 emit_insn (gen_rtx_SET (VOIDmode
,
1899 gen_rtx_ASHIFT (DImode
,
1903 emit_insn (gen_rtx_SET (VOIDmode
,
1905 gen_rtx_LSHIFTRT (DImode
,
1907 GEN_INT (-shift
))));
1911 /* Now a range of 22 or less bits set somewhere.
1912 * 1) sethi %hi(focus_bits), %reg
1913 * sllx %reg, shift, %reg
1914 * 2) sethi %hi(focus_bits), %reg
1915 * srlx %reg, shift, %reg
1917 if ((highest_bit_set
- lowest_bit_set
) < 21)
1919 unsigned HOST_WIDE_INT focus_bits
=
1920 create_simple_focus_bits (high_bits
, low_bits
,
1921 lowest_bit_set
, 10);
1923 gcc_assert (SPARC_SETHI_P (focus_bits
));
1924 gcc_assert (lowest_bit_set
!= 10);
1926 emit_insn (gen_safe_HIGH64 (temp
, focus_bits
));
1928 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
1929 if (lowest_bit_set
< 10)
1930 emit_insn (gen_rtx_SET (VOIDmode
,
1932 gen_rtx_LSHIFTRT (DImode
, temp
,
1933 GEN_INT (10 - lowest_bit_set
))));
1934 else if (lowest_bit_set
> 10)
1935 emit_insn (gen_rtx_SET (VOIDmode
,
1937 gen_rtx_ASHIFT (DImode
, temp
,
1938 GEN_INT (lowest_bit_set
- 10))));
1942 /* 1) sethi %hi(low_bits), %reg
1943 * or %reg, %lo(low_bits), %reg
1944 * 2) sethi %hi(~low_bits), %reg
1945 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
1948 || high_bits
== 0xffffffff)
1950 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
,
1951 (high_bits
== 0xffffffff));
1955 /* Now, try 3-insn sequences. */
1957 /* 1) sethi %hi(high_bits), %reg
1958 * or %reg, %lo(high_bits), %reg
1959 * sllx %reg, 32, %reg
1963 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, 0, 32);
1967 /* We may be able to do something quick
1968 when the constant is negated, so try that. */
1969 if (const64_is_2insns ((~high_bits
) & 0xffffffff,
1970 (~low_bits
) & 0xfffffc00))
1972 /* NOTE: The trailing bits get XOR'd so we need the
1973 non-negated bits, not the negated ones. */
1974 unsigned HOST_WIDE_INT trailing_bits
= low_bits
& 0x3ff;
1976 if ((((~high_bits
) & 0xffffffff) == 0
1977 && ((~low_bits
) & 0x80000000) == 0)
1978 || (((~high_bits
) & 0xffffffff) == 0xffffffff
1979 && ((~low_bits
) & 0x80000000) != 0))
1981 unsigned HOST_WIDE_INT fast_int
= (~low_bits
& 0xffffffff);
1983 if ((SPARC_SETHI_P (fast_int
)
1984 && (~high_bits
& 0xffffffff) == 0)
1985 || SPARC_SIMM13_P (fast_int
))
1986 emit_insn (gen_safe_SET64 (temp
, fast_int
));
1988 sparc_emit_set_const64 (temp
, GEN_INT (fast_int
));
1993 negated_const
= GEN_INT (((~low_bits
) & 0xfffffc00) |
1994 (((HOST_WIDE_INT
)((~high_bits
) & 0xffffffff))<<32));
1995 sparc_emit_set_const64 (temp
, negated_const
);
1998 /* If we are XOR'ing with -1, then we should emit a one's complement
1999 instead. This way the combiner will notice logical operations
2000 such as ANDN later on and substitute. */
2001 if (trailing_bits
== 0x3ff)
2003 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2004 gen_rtx_NOT (DImode
, temp
)));
2008 emit_insn (gen_rtx_SET (VOIDmode
,
2010 gen_safe_XOR64 (temp
,
2011 (-0x400 | trailing_bits
))));
2016 /* 1) sethi %hi(xxx), %reg
2017 * or %reg, %lo(xxx), %reg
2018 * sllx %reg, yyy, %reg
2020 * ??? This is just a generalized version of the low_bits==0
2021 * thing above, FIXME...
2023 if ((highest_bit_set
- lowest_bit_set
) < 32)
2025 unsigned HOST_WIDE_INT focus_bits
=
2026 create_simple_focus_bits (high_bits
, low_bits
,
2029 /* We can't get here in this state. */
2030 gcc_assert (highest_bit_set
>= 32 && lowest_bit_set
< 32);
2032 /* So what we know is that the set bits straddle the
2033 middle of the 64-bit word. */
2034 sparc_emit_set_const64_quick2 (op0
, temp
,
2040 /* 1) sethi %hi(high_bits), %reg
2041 * or %reg, %lo(high_bits), %reg
2042 * sllx %reg, 32, %reg
2043 * or %reg, low_bits, %reg
2045 if (SPARC_SIMM13_P(low_bits
)
2046 && ((int)low_bits
> 0))
2048 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_bits
, 32);
2052 /* The easiest way when all else fails, is full decomposition. */
2053 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
);
2055 #endif /* HOST_BITS_PER_WIDE_INT == 32 */
2057 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2058 return the mode to be used for the comparison. For floating-point,
2059 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2060 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2061 processing is needed. */
2064 select_cc_mode (enum rtx_code op
, rtx x
, rtx y ATTRIBUTE_UNUSED
)
2066 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2092 else if (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
2093 || GET_CODE (x
) == NEG
|| GET_CODE (x
) == ASHIFT
)
2095 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2096 return CCX_NOOVmode
;
2102 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2109 /* Emit the compare insn and return the CC reg for a CODE comparison
2110 with operands X and Y. */
2113 gen_compare_reg_1 (enum rtx_code code
, rtx x
, rtx y
)
2115 enum machine_mode mode
;
2118 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
2121 mode
= SELECT_CC_MODE (code
, x
, y
);
2123 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2124 fcc regs (cse can't tell they're really call clobbered regs and will
2125 remove a duplicate comparison even if there is an intervening function
2126 call - it will then try to reload the cc reg via an int reg which is why
2127 we need the movcc patterns). It is possible to provide the movcc
2128 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2129 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2130 to tell cse that CCFPE mode registers (even pseudos) are call
2133 /* ??? This is an experiment. Rather than making changes to cse which may
2134 or may not be easy/clean, we do our own cse. This is possible because
2135 we will generate hard registers. Cse knows they're call clobbered (it
2136 doesn't know the same thing about pseudos). If we guess wrong, no big
2137 deal, but if we win, great! */
2139 if (TARGET_V9
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2140 #if 1 /* experiment */
2143 /* We cycle through the registers to ensure they're all exercised. */
2144 static int next_fcc_reg
= 0;
2145 /* Previous x,y for each fcc reg. */
2146 static rtx prev_args
[4][2];
2148 /* Scan prev_args for x,y. */
2149 for (reg
= 0; reg
< 4; reg
++)
2150 if (prev_args
[reg
][0] == x
&& prev_args
[reg
][1] == y
)
2155 prev_args
[reg
][0] = x
;
2156 prev_args
[reg
][1] = y
;
2157 next_fcc_reg
= (next_fcc_reg
+ 1) & 3;
2159 cc_reg
= gen_rtx_REG (mode
, reg
+ SPARC_FIRST_V9_FCC_REG
);
2162 cc_reg
= gen_reg_rtx (mode
);
2163 #endif /* ! experiment */
2164 else if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2165 cc_reg
= gen_rtx_REG (mode
, SPARC_FCC_REG
);
2167 cc_reg
= gen_rtx_REG (mode
, SPARC_ICC_REG
);
2169 /* We shouldn't get there for TFmode if !TARGET_HARD_QUAD. If we do, this
2170 will only result in an unrecognizable insn so no point in asserting. */
2171 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
, gen_rtx_COMPARE (mode
, x
, y
)));
2177 /* Emit the compare insn and return the CC reg for the comparison in CMP. */
2180 gen_compare_reg (rtx cmp
)
2182 return gen_compare_reg_1 (GET_CODE (cmp
), XEXP (cmp
, 0), XEXP (cmp
, 1));
2185 /* This function is used for v9 only.
2186 DEST is the target of the Scc insn.
2187 CODE is the code for an Scc's comparison.
2188 X and Y are the values we compare.
2190 This function is needed to turn
2193 (gt (reg:CCX 100 %icc)
2197 (gt:DI (reg:CCX 100 %icc)
2200 IE: The instruction recognizer needs to see the mode of the comparison to
2201 find the right instruction. We could use "gt:DI" right in the
2202 define_expand, but leaving it out allows us to handle DI, SI, etc. */
2205 gen_v9_scc (rtx dest
, enum rtx_code compare_code
, rtx x
, rtx y
)
2208 && (GET_MODE (x
) == DImode
2209 || GET_MODE (dest
) == DImode
))
2212 /* Try to use the movrCC insns. */
2214 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
2216 && v9_regcmp_p (compare_code
))
2221 /* Special case for op0 != 0. This can be done with one instruction if
2224 if (compare_code
== NE
2225 && GET_MODE (dest
) == DImode
2226 && rtx_equal_p (op0
, dest
))
2228 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2229 gen_rtx_IF_THEN_ELSE (DImode
,
2230 gen_rtx_fmt_ee (compare_code
, DImode
,
2237 if (reg_overlap_mentioned_p (dest
, op0
))
2239 /* Handle the case where dest == x.
2240 We "early clobber" the result. */
2241 op0
= gen_reg_rtx (GET_MODE (x
));
2242 emit_move_insn (op0
, x
);
2245 emit_insn (gen_rtx_SET (VOIDmode
, dest
, const0_rtx
));
2246 if (GET_MODE (op0
) != DImode
)
2248 temp
= gen_reg_rtx (DImode
);
2249 convert_move (temp
, op0
, 0);
2253 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2254 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
2255 gen_rtx_fmt_ee (compare_code
, DImode
,
2263 x
= gen_compare_reg_1 (compare_code
, x
, y
);
2266 gcc_assert (GET_MODE (x
) != CC_NOOVmode
2267 && GET_MODE (x
) != CCX_NOOVmode
);
2269 emit_insn (gen_rtx_SET (VOIDmode
, dest
, const0_rtx
));
2270 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2271 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
2272 gen_rtx_fmt_ee (compare_code
,
2273 GET_MODE (x
), x
, y
),
2274 const1_rtx
, dest
)));
2280 /* Emit an scc insn. For seq, sne, sgeu, and sltu, we can do this
2281 without jumps using the addx/subx instructions. */
2284 emit_scc_insn (rtx operands
[])
2291 /* The quad-word fp compare library routines all return nonzero to indicate
2292 true, which is different from the equivalent libgcc routines, so we must
2293 handle them specially here. */
2294 if (GET_MODE (operands
[2]) == TFmode
&& ! TARGET_HARD_QUAD
)
2296 operands
[1] = sparc_emit_float_lib_cmp (operands
[2], operands
[3],
2297 GET_CODE (operands
[1]));
2298 operands
[2] = XEXP (operands
[1], 0);
2299 operands
[3] = XEXP (operands
[1], 1);
2302 code
= GET_CODE (operands
[1]);
2306 /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has
2307 more applications). The exception to this is "reg != 0" which can
2308 be done in one instruction on v9 (so we do it). */
2311 if (GET_MODE (x
) == SImode
)
2313 rtx pat
= gen_seqsi_special (operands
[0], x
, y
);
2317 else if (GET_MODE (x
) == DImode
)
2319 rtx pat
= gen_seqdi_special (operands
[0], x
, y
);
2327 if (GET_MODE (x
) == SImode
)
2329 rtx pat
= gen_snesi_special (operands
[0], x
, y
);
2333 else if (GET_MODE (x
) == DImode
)
2335 rtx pat
= gen_snedi_special (operands
[0], x
, y
);
2341 /* For the rest, on v9 we can use conditional moves. */
2345 if (gen_v9_scc (operands
[0], code
, x
, y
))
2349 /* We can do LTU and GEU using the addx/subx instructions too. And
2350 for GTU/LEU, if both operands are registers swap them and fall
2351 back to the easy case. */
2352 if (code
== GTU
|| code
== LEU
)
2354 if ((GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
2355 && (GET_CODE (y
) == REG
|| GET_CODE (y
) == SUBREG
))
2360 code
= swap_condition (code
);
2364 if (code
== LTU
|| code
== GEU
)
2366 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2367 gen_rtx_fmt_ee (code
, SImode
,
2368 gen_compare_reg_1 (code
, x
, y
),
2373 /* Nope, do branches. */
2377 /* Emit a conditional jump insn for the v9 architecture using comparison code
2378 CODE and jump target LABEL.
2379 This function exists to take advantage of the v9 brxx insns. */
2382 emit_v9_brxx_insn (enum rtx_code code
, rtx op0
, rtx label
)
2384 emit_jump_insn (gen_rtx_SET (VOIDmode
,
2386 gen_rtx_IF_THEN_ELSE (VOIDmode
,
2387 gen_rtx_fmt_ee (code
, GET_MODE (op0
),
2389 gen_rtx_LABEL_REF (VOIDmode
, label
),
2394 emit_conditional_branch_insn (rtx operands
[])
2396 /* The quad-word fp compare library routines all return nonzero to indicate
2397 true, which is different from the equivalent libgcc routines, so we must
2398 handle them specially here. */
2399 if (GET_MODE (operands
[1]) == TFmode
&& ! TARGET_HARD_QUAD
)
2401 operands
[0] = sparc_emit_float_lib_cmp (operands
[1], operands
[2],
2402 GET_CODE (operands
[0]));
2403 operands
[1] = XEXP (operands
[0], 0);
2404 operands
[2] = XEXP (operands
[0], 1);
2407 if (TARGET_ARCH64
&& operands
[2] == const0_rtx
2408 && GET_CODE (operands
[1]) == REG
2409 && GET_MODE (operands
[1]) == DImode
)
2411 emit_v9_brxx_insn (GET_CODE (operands
[0]), operands
[1], operands
[3]);
2415 operands
[1] = gen_compare_reg (operands
[0]);
2416 operands
[2] = const0_rtx
;
2417 operands
[0] = gen_rtx_fmt_ee (GET_CODE (operands
[0]), VOIDmode
,
2418 operands
[1], operands
[2]);
2419 emit_jump_insn (gen_cbranchcc4 (operands
[0], operands
[1], operands
[2],
2424 /* Generate a DFmode part of a hard TFmode register.
2425 REG is the TFmode hard register, LOW is 1 for the
2426 low 64bit of the register and 0 otherwise.
2429 gen_df_reg (rtx reg
, int low
)
2431 int regno
= REGNO (reg
);
2433 if ((WORDS_BIG_ENDIAN
== 0) ^ (low
!= 0))
2434 regno
+= (TARGET_ARCH64
&& regno
< 32) ? 1 : 2;
2435 return gen_rtx_REG (DFmode
, regno
);
2438 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2439 Unlike normal calls, TFmode operands are passed by reference. It is
2440 assumed that no more than 3 operands are required. */
2443 emit_soft_tfmode_libcall (const char *func_name
, int nargs
, rtx
*operands
)
2445 rtx ret_slot
= NULL
, arg
[3], func_sym
;
2448 /* We only expect to be called for conversions, unary, and binary ops. */
2449 gcc_assert (nargs
== 2 || nargs
== 3);
2451 for (i
= 0; i
< nargs
; ++i
)
2453 rtx this_arg
= operands
[i
];
2456 /* TFmode arguments and return values are passed by reference. */
2457 if (GET_MODE (this_arg
) == TFmode
)
2459 int force_stack_temp
;
2461 force_stack_temp
= 0;
2462 if (TARGET_BUGGY_QP_LIB
&& i
== 0)
2463 force_stack_temp
= 1;
2465 if (GET_CODE (this_arg
) == MEM
2466 && ! force_stack_temp
)
2467 this_arg
= XEXP (this_arg
, 0);
2468 else if (CONSTANT_P (this_arg
)
2469 && ! force_stack_temp
)
2471 this_slot
= force_const_mem (TFmode
, this_arg
);
2472 this_arg
= XEXP (this_slot
, 0);
2476 this_slot
= assign_stack_temp (TFmode
, GET_MODE_SIZE (TFmode
), 0);
2478 /* Operand 0 is the return value. We'll copy it out later. */
2480 emit_move_insn (this_slot
, this_arg
);
2482 ret_slot
= this_slot
;
2484 this_arg
= XEXP (this_slot
, 0);
2491 func_sym
= gen_rtx_SYMBOL_REF (Pmode
, func_name
);
2493 if (GET_MODE (operands
[0]) == TFmode
)
2496 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 2,
2497 arg
[0], GET_MODE (arg
[0]),
2498 arg
[1], GET_MODE (arg
[1]));
2500 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 3,
2501 arg
[0], GET_MODE (arg
[0]),
2502 arg
[1], GET_MODE (arg
[1]),
2503 arg
[2], GET_MODE (arg
[2]));
2506 emit_move_insn (operands
[0], ret_slot
);
2512 gcc_assert (nargs
== 2);
2514 ret
= emit_library_call_value (func_sym
, operands
[0], LCT_NORMAL
,
2515 GET_MODE (operands
[0]), 1,
2516 arg
[1], GET_MODE (arg
[1]));
2518 if (ret
!= operands
[0])
2519 emit_move_insn (operands
[0], ret
);
2523 /* Expand soft-float TFmode calls to sparc abi routines. */
2526 emit_soft_tfmode_binop (enum rtx_code code
, rtx
*operands
)
2548 emit_soft_tfmode_libcall (func
, 3, operands
);
2552 emit_soft_tfmode_unop (enum rtx_code code
, rtx
*operands
)
2556 gcc_assert (code
== SQRT
);
2559 emit_soft_tfmode_libcall (func
, 2, operands
);
2563 emit_soft_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
2570 switch (GET_MODE (operands
[1]))
2583 case FLOAT_TRUNCATE
:
2584 switch (GET_MODE (operands
[0]))
2598 switch (GET_MODE (operands
[1]))
2603 operands
[1] = gen_rtx_SIGN_EXTEND (DImode
, operands
[1]);
2613 case UNSIGNED_FLOAT
:
2614 switch (GET_MODE (operands
[1]))
2619 operands
[1] = gen_rtx_ZERO_EXTEND (DImode
, operands
[1]);
2630 switch (GET_MODE (operands
[0]))
2644 switch (GET_MODE (operands
[0]))
2661 emit_soft_tfmode_libcall (func
, 2, operands
);
2664 /* Expand a hard-float tfmode operation. All arguments must be in
2668 emit_hard_tfmode_operation (enum rtx_code code
, rtx
*operands
)
2672 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
2674 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
2675 op
= gen_rtx_fmt_e (code
, GET_MODE (operands
[0]), operands
[1]);
2679 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
2680 operands
[2] = force_reg (GET_MODE (operands
[2]), operands
[2]);
2681 op
= gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
2682 operands
[1], operands
[2]);
2685 if (register_operand (operands
[0], VOIDmode
))
2688 dest
= gen_reg_rtx (GET_MODE (operands
[0]));
2690 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op
));
2692 if (dest
!= operands
[0])
2693 emit_move_insn (operands
[0], dest
);
2697 emit_tfmode_binop (enum rtx_code code
, rtx
*operands
)
2699 if (TARGET_HARD_QUAD
)
2700 emit_hard_tfmode_operation (code
, operands
);
2702 emit_soft_tfmode_binop (code
, operands
);
2706 emit_tfmode_unop (enum rtx_code code
, rtx
*operands
)
2708 if (TARGET_HARD_QUAD
)
2709 emit_hard_tfmode_operation (code
, operands
);
2711 emit_soft_tfmode_unop (code
, operands
);
2715 emit_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
2717 if (TARGET_HARD_QUAD
)
2718 emit_hard_tfmode_operation (code
, operands
);
2720 emit_soft_tfmode_cvt (code
, operands
);
2723 /* Return nonzero if a branch/jump/call instruction will be emitting
2724 nop into its delay slot. */
2727 empty_delay_slot (rtx insn
)
2731 /* If no previous instruction (should not happen), return true. */
2732 if (PREV_INSN (insn
) == NULL
)
2735 seq
= NEXT_INSN (PREV_INSN (insn
));
2736 if (GET_CODE (PATTERN (seq
)) == SEQUENCE
)
2742 /* Return nonzero if TRIAL can go into the call delay slot. */
2745 tls_call_delay (rtx trial
)
2750 call __tls_get_addr, %tgd_call (foo)
2751 add %l7, %o0, %o0, %tgd_add (foo)
2752 while Sun as/ld does not. */
2753 if (TARGET_GNU_TLS
|| !TARGET_TLS
)
2756 pat
= PATTERN (trial
);
2758 /* We must reject tgd_add{32|64}, i.e.
2759 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD)))
2760 and tldm_add{32|64}, i.e.
2761 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM)))
2763 if (GET_CODE (pat
) == SET
2764 && GET_CODE (SET_SRC (pat
)) == PLUS
)
2766 rtx unspec
= XEXP (SET_SRC (pat
), 1);
2768 if (GET_CODE (unspec
) == UNSPEC
2769 && (XINT (unspec
, 1) == UNSPEC_TLSGD
2770 || XINT (unspec
, 1) == UNSPEC_TLSLDM
))
2777 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
2778 instruction. RETURN_P is true if the v9 variant 'return' is to be
2779 considered in the test too.
2781 TRIAL must be a SET whose destination is a REG appropriate for the
2782 'restore' instruction or, if RETURN_P is true, for the 'return'
2786 eligible_for_restore_insn (rtx trial
, bool return_p
)
2788 rtx pat
= PATTERN (trial
);
2789 rtx src
= SET_SRC (pat
);
2791 /* The 'restore src,%g0,dest' pattern for word mode and below. */
2792 if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2793 && arith_operand (src
, GET_MODE (src
)))
2796 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2798 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
2801 /* The 'restore src,%g0,dest' pattern for double-word mode. */
2802 else if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2803 && arith_double_operand (src
, GET_MODE (src
)))
2804 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2806 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
2807 else if (! TARGET_FPU
&& register_operand (src
, SFmode
))
2810 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
2811 else if (! TARGET_FPU
&& TARGET_ARCH64
&& register_operand (src
, DFmode
))
2814 /* If we have the 'return' instruction, anything that does not use
2815 local or output registers and can go into a delay slot wins. */
2818 && !epilogue_renumber (&pat
, 1)
2819 && get_attr_in_uncond_branch_delay (trial
)
2820 == IN_UNCOND_BRANCH_DELAY_TRUE
)
2823 /* The 'restore src1,src2,dest' pattern for SImode. */
2824 else if (GET_CODE (src
) == PLUS
2825 && register_operand (XEXP (src
, 0), SImode
)
2826 && arith_operand (XEXP (src
, 1), SImode
))
2829 /* The 'restore src1,src2,dest' pattern for DImode. */
2830 else if (GET_CODE (src
) == PLUS
2831 && register_operand (XEXP (src
, 0), DImode
)
2832 && arith_double_operand (XEXP (src
, 1), DImode
))
2835 /* The 'restore src1,%lo(src2),dest' pattern. */
2836 else if (GET_CODE (src
) == LO_SUM
2837 && ! TARGET_CM_MEDMID
2838 && ((register_operand (XEXP (src
, 0), SImode
)
2839 && immediate_operand (XEXP (src
, 1), SImode
))
2841 && register_operand (XEXP (src
, 0), DImode
)
2842 && immediate_operand (XEXP (src
, 1), DImode
))))
2845 /* The 'restore src,src,dest' pattern. */
2846 else if (GET_CODE (src
) == ASHIFT
2847 && (register_operand (XEXP (src
, 0), SImode
)
2848 || register_operand (XEXP (src
, 0), DImode
))
2849 && XEXP (src
, 1) == const1_rtx
)
2855 /* Return nonzero if TRIAL can go into the function return's delay slot. */
2858 eligible_for_return_delay (rtx trial
)
2862 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
2865 if (get_attr_length (trial
) != 1)
2868 /* If the function uses __builtin_eh_return, the eh_return machinery
2869 occupies the delay slot. */
2870 if (crtl
->calls_eh_return
)
2873 /* In the case of a leaf or flat function, anything can go into the slot. */
2874 if (sparc_leaf_function_p
|| TARGET_FLAT
)
2876 get_attr_in_uncond_branch_delay (trial
) == IN_UNCOND_BRANCH_DELAY_TRUE
;
2878 pat
= PATTERN (trial
);
2880 /* Otherwise, only operations which can be done in tandem with
2881 a `restore' or `return' insn can go into the delay slot. */
2882 if (GET_CODE (SET_DEST (pat
)) != REG
2883 || (REGNO (SET_DEST (pat
)) >= 8 && REGNO (SET_DEST (pat
)) < 24))
2886 /* If this instruction sets up floating point register and we have a return
2887 instruction, it can probably go in. But restore will not work
2889 if (REGNO (SET_DEST (pat
)) >= 32)
2891 && !epilogue_renumber (&pat
, 1)
2892 && get_attr_in_uncond_branch_delay (trial
)
2893 == IN_UNCOND_BRANCH_DELAY_TRUE
);
2895 return eligible_for_restore_insn (trial
, true);
2898 /* Return nonzero if TRIAL can go into the sibling call's delay slot. */
2901 eligible_for_sibcall_delay (rtx trial
)
2905 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
2908 if (get_attr_length (trial
) != 1)
2911 pat
= PATTERN (trial
);
2913 if (sparc_leaf_function_p
|| TARGET_FLAT
)
2915 /* If the tail call is done using the call instruction,
2916 we have to restore %o7 in the delay slot. */
2917 if (LEAF_SIBCALL_SLOT_RESERVED_P
)
2920 /* %g1 is used to build the function address */
2921 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 1), pat
))
2927 /* Otherwise, only operations which can be done in tandem with
2928 a `restore' insn can go into the delay slot. */
2929 if (GET_CODE (SET_DEST (pat
)) != REG
2930 || (REGNO (SET_DEST (pat
)) >= 8 && REGNO (SET_DEST (pat
)) < 24)
2931 || REGNO (SET_DEST (pat
)) >= 32)
2934 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2936 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 15), pat
))
2939 return eligible_for_restore_insn (trial
, false);
2943 short_branch (int uid1
, int uid2
)
2945 int delta
= INSN_ADDRESSES (uid1
) - INSN_ADDRESSES (uid2
);
2947 /* Leave a few words of "slop". */
2948 if (delta
>= -1023 && delta
<= 1022)
2954 /* Return nonzero if REG is not used after INSN.
2955 We assume REG is a reload reg, and therefore does
2956 not live past labels or calls or jumps. */
2958 reg_unused_after (rtx reg
, rtx insn
)
2960 enum rtx_code code
, prev_code
= UNKNOWN
;
2962 while ((insn
= NEXT_INSN (insn
)))
2964 if (prev_code
== CALL_INSN
&& call_used_regs
[REGNO (reg
)])
2967 code
= GET_CODE (insn
);
2968 if (GET_CODE (insn
) == CODE_LABEL
)
2973 rtx set
= single_set (insn
);
2974 int in_src
= set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
));
2977 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
2979 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
2987 /* Determine if it's legal to put X into the constant pool. This
2988 is not possible if X contains the address of a symbol that is
2989 not constant (TLS) or not known at final link time (PIC). */
2992 sparc_cannot_force_const_mem (enum machine_mode mode
, rtx x
)
2994 switch (GET_CODE (x
))
2999 /* Accept all non-symbolic constants. */
3003 /* Labels are OK iff we are non-PIC. */
3004 return flag_pic
!= 0;
3007 /* 'Naked' TLS symbol references are never OK,
3008 non-TLS symbols are OK iff we are non-PIC. */
3009 if (SYMBOL_REF_TLS_MODEL (x
))
3012 return flag_pic
!= 0;
3015 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0));
3018 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0))
3019 || sparc_cannot_force_const_mem (mode
, XEXP (x
, 1));
3027 /* Global Offset Table support. */
3028 static GTY(()) rtx got_helper_rtx
= NULL_RTX
;
3029 static GTY(()) rtx global_offset_table_rtx
= NULL_RTX
;
3031 /* Return the SYMBOL_REF for the Global Offset Table. */
3033 static GTY(()) rtx sparc_got_symbol
= NULL_RTX
;
3038 if (!sparc_got_symbol
)
3039 sparc_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3041 return sparc_got_symbol
;
3044 /* Ensure that we are not using patterns that are not OK with PIC. */
3054 op
= recog_data
.operand
[i
];
3055 gcc_assert (GET_CODE (op
) != SYMBOL_REF
3056 && (GET_CODE (op
) != CONST
3057 || (GET_CODE (XEXP (op
, 0)) == MINUS
3058 && XEXP (XEXP (op
, 0), 0) == sparc_got ()
3059 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST
)));
3066 /* Return true if X is an address which needs a temporary register when
3067 reloaded while generating PIC code. */
3070 pic_address_needs_scratch (rtx x
)
3072 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3073 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
3074 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
3075 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3076 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
3082 /* Determine if a given RTX is a valid constant. We already know this
3083 satisfies CONSTANT_P. */
3086 sparc_legitimate_constant_p (enum machine_mode mode
, rtx x
)
3088 switch (GET_CODE (x
))
3092 if (sparc_tls_referenced_p (x
))
3097 if (GET_MODE (x
) == VOIDmode
)
3100 /* Floating point constants are generally not ok.
3101 The only exception is 0.0 and all-ones in VIS. */
3103 && SCALAR_FLOAT_MODE_P (mode
)
3104 && (const_zero_operand (x
, mode
)
3105 || const_all_ones_operand (x
, mode
)))
3111 /* Vector constants are generally not ok.
3112 The only exception is 0 or -1 in VIS. */
3114 && (const_zero_operand (x
, mode
)
3115 || const_all_ones_operand (x
, mode
)))
3127 /* Determine if a given RTX is a valid constant address. */
3130 constant_address_p (rtx x
)
3132 switch (GET_CODE (x
))
3140 if (flag_pic
&& pic_address_needs_scratch (x
))
3142 return sparc_legitimate_constant_p (Pmode
, x
);
3145 return !flag_pic
&& sparc_legitimate_constant_p (Pmode
, x
);
3152 /* Nonzero if the constant value X is a legitimate general operand
3153 when generating PIC code. It is given that flag_pic is on and
3154 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3157 legitimate_pic_operand_p (rtx x
)
3159 if (pic_address_needs_scratch (x
))
3161 if (sparc_tls_referenced_p (x
))
3166 #define RTX_OK_FOR_OFFSET_P(X, MODE) \
3168 && INTVAL (X) >= -0x1000 \
3169 && INTVAL (X) < (0x1000 - GET_MODE_SIZE (MODE)))
3171 #define RTX_OK_FOR_OLO10_P(X, MODE) \
3173 && INTVAL (X) >= -0x1000 \
3174 && INTVAL (X) < (0xc00 - GET_MODE_SIZE (MODE)))
3176 /* Handle the TARGET_LEGITIMATE_ADDRESS_P target hook.
3178 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
3179 ordinarily. This changes a bit when generating PIC. */
3182 sparc_legitimate_address_p (enum machine_mode mode
, rtx addr
, bool strict
)
3184 rtx rs1
= NULL
, rs2
= NULL
, imm1
= NULL
;
3186 if (REG_P (addr
) || GET_CODE (addr
) == SUBREG
)
3188 else if (GET_CODE (addr
) == PLUS
)
3190 rs1
= XEXP (addr
, 0);
3191 rs2
= XEXP (addr
, 1);
3193 /* Canonicalize. REG comes first, if there are no regs,
3194 LO_SUM comes first. */
3196 && GET_CODE (rs1
) != SUBREG
3198 || GET_CODE (rs2
) == SUBREG
3199 || (GET_CODE (rs2
) == LO_SUM
&& GET_CODE (rs1
) != LO_SUM
)))
3201 rs1
= XEXP (addr
, 1);
3202 rs2
= XEXP (addr
, 0);
3206 && rs1
== pic_offset_table_rtx
3208 && GET_CODE (rs2
) != SUBREG
3209 && GET_CODE (rs2
) != LO_SUM
3210 && GET_CODE (rs2
) != MEM
3211 && !(GET_CODE (rs2
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs2
))
3212 && (! symbolic_operand (rs2
, VOIDmode
) || mode
== Pmode
)
3213 && (GET_CODE (rs2
) != CONST_INT
|| SMALL_INT (rs2
)))
3215 || GET_CODE (rs1
) == SUBREG
)
3216 && RTX_OK_FOR_OFFSET_P (rs2
, mode
)))
3221 else if ((REG_P (rs1
) || GET_CODE (rs1
) == SUBREG
)
3222 && (REG_P (rs2
) || GET_CODE (rs2
) == SUBREG
))
3224 /* We prohibit REG + REG for TFmode when there are no quad move insns
3225 and we consequently need to split. We do this because REG+REG
3226 is not an offsettable address. If we get the situation in reload
3227 where source and destination of a movtf pattern are both MEMs with
3228 REG+REG address, then only one of them gets converted to an
3229 offsettable address. */
3231 && ! (TARGET_FPU
&& TARGET_ARCH64
&& TARGET_HARD_QUAD
))
3234 /* We prohibit REG + REG on ARCH32 if not optimizing for
3235 DFmode/DImode because then mem_min_alignment is likely to be zero
3236 after reload and the forced split would lack a matching splitter
3238 if (TARGET_ARCH32
&& !optimize
3239 && (mode
== DFmode
|| mode
== DImode
))
3242 else if (USE_AS_OFFSETABLE_LO10
3243 && GET_CODE (rs1
) == LO_SUM
3245 && ! TARGET_CM_MEDMID
3246 && RTX_OK_FOR_OLO10_P (rs2
, mode
))
3249 imm1
= XEXP (rs1
, 1);
3250 rs1
= XEXP (rs1
, 0);
3251 if (!CONSTANT_P (imm1
)
3252 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
3256 else if (GET_CODE (addr
) == LO_SUM
)
3258 rs1
= XEXP (addr
, 0);
3259 imm1
= XEXP (addr
, 1);
3261 if (!CONSTANT_P (imm1
)
3262 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
3265 /* We can't allow TFmode in 32-bit mode, because an offset greater
3266 than the alignment (8) may cause the LO_SUM to overflow. */
3267 if (mode
== TFmode
&& TARGET_ARCH32
)
3270 else if (GET_CODE (addr
) == CONST_INT
&& SMALL_INT (addr
))
3275 if (GET_CODE (rs1
) == SUBREG
)
3276 rs1
= SUBREG_REG (rs1
);
3282 if (GET_CODE (rs2
) == SUBREG
)
3283 rs2
= SUBREG_REG (rs2
);
3290 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1
))
3291 || (rs2
&& !REGNO_OK_FOR_BASE_P (REGNO (rs2
))))
3296 if ((REGNO (rs1
) >= 32
3297 && REGNO (rs1
) != FRAME_POINTER_REGNUM
3298 && REGNO (rs1
) < FIRST_PSEUDO_REGISTER
)
3300 && (REGNO (rs2
) >= 32
3301 && REGNO (rs2
) != FRAME_POINTER_REGNUM
3302 && REGNO (rs2
) < FIRST_PSEUDO_REGISTER
)))
3308 /* Return the SYMBOL_REF for the tls_get_addr function. */
3310 static GTY(()) rtx sparc_tls_symbol
= NULL_RTX
;
3313 sparc_tls_get_addr (void)
3315 if (!sparc_tls_symbol
)
3316 sparc_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
3318 return sparc_tls_symbol
;
3321 /* Return the Global Offset Table to be used in TLS mode. */
3324 sparc_tls_got (void)
3326 /* In PIC mode, this is just the PIC offset table. */
3329 crtl
->uses_pic_offset_table
= 1;
3330 return pic_offset_table_rtx
;
3333 /* In non-PIC mode, Sun as (unlike GNU as) emits PC-relative relocations for
3334 the GOT symbol with the 32-bit ABI, so we reload the GOT register. */
3335 if (TARGET_SUN_TLS
&& TARGET_ARCH32
)
3337 load_got_register ();
3338 return global_offset_table_rtx
;
3341 /* In all other cases, we load a new pseudo with the GOT symbol. */
3342 return copy_to_reg (sparc_got ());
3345 /* Return true if X contains a thread-local symbol. */
3348 sparc_tls_referenced_p (rtx x
)
3350 if (!TARGET_HAVE_TLS
)
3353 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
3354 x
= XEXP (XEXP (x
, 0), 0);
3356 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
))
3359 /* That's all we handle in sparc_legitimize_tls_address for now. */
3363 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3364 this (thread-local) address. */
3367 sparc_legitimize_tls_address (rtx addr
)
3369 rtx temp1
, temp2
, temp3
, ret
, o0
, got
, insn
;
3371 gcc_assert (can_create_pseudo_p ());
3373 if (GET_CODE (addr
) == SYMBOL_REF
)
3374 switch (SYMBOL_REF_TLS_MODEL (addr
))
3376 case TLS_MODEL_GLOBAL_DYNAMIC
:
3378 temp1
= gen_reg_rtx (SImode
);
3379 temp2
= gen_reg_rtx (SImode
);
3380 ret
= gen_reg_rtx (Pmode
);
3381 o0
= gen_rtx_REG (Pmode
, 8);
3382 got
= sparc_tls_got ();
3383 emit_insn (gen_tgd_hi22 (temp1
, addr
));
3384 emit_insn (gen_tgd_lo10 (temp2
, temp1
, addr
));
3387 emit_insn (gen_tgd_add32 (o0
, got
, temp2
, addr
));
3388 insn
= emit_call_insn (gen_tgd_call32 (o0
, sparc_tls_get_addr (),
3393 emit_insn (gen_tgd_add64 (o0
, got
, temp2
, addr
));
3394 insn
= emit_call_insn (gen_tgd_call64 (o0
, sparc_tls_get_addr (),
3397 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
3398 insn
= get_insns ();
3400 emit_libcall_block (insn
, ret
, o0
, addr
);
3403 case TLS_MODEL_LOCAL_DYNAMIC
:
3405 temp1
= gen_reg_rtx (SImode
);
3406 temp2
= gen_reg_rtx (SImode
);
3407 temp3
= gen_reg_rtx (Pmode
);
3408 ret
= gen_reg_rtx (Pmode
);
3409 o0
= gen_rtx_REG (Pmode
, 8);
3410 got
= sparc_tls_got ();
3411 emit_insn (gen_tldm_hi22 (temp1
));
3412 emit_insn (gen_tldm_lo10 (temp2
, temp1
));
3415 emit_insn (gen_tldm_add32 (o0
, got
, temp2
));
3416 insn
= emit_call_insn (gen_tldm_call32 (o0
, sparc_tls_get_addr (),
3421 emit_insn (gen_tldm_add64 (o0
, got
, temp2
));
3422 insn
= emit_call_insn (gen_tldm_call64 (o0
, sparc_tls_get_addr (),
3425 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
3426 insn
= get_insns ();
3428 emit_libcall_block (insn
, temp3
, o0
,
3429 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3430 UNSPEC_TLSLD_BASE
));
3431 temp1
= gen_reg_rtx (SImode
);
3432 temp2
= gen_reg_rtx (SImode
);
3433 emit_insn (gen_tldo_hix22 (temp1
, addr
));
3434 emit_insn (gen_tldo_lox10 (temp2
, temp1
, addr
));
3436 emit_insn (gen_tldo_add32 (ret
, temp3
, temp2
, addr
));
3438 emit_insn (gen_tldo_add64 (ret
, temp3
, temp2
, addr
));
3441 case TLS_MODEL_INITIAL_EXEC
:
3442 temp1
= gen_reg_rtx (SImode
);
3443 temp2
= gen_reg_rtx (SImode
);
3444 temp3
= gen_reg_rtx (Pmode
);
3445 got
= sparc_tls_got ();
3446 emit_insn (gen_tie_hi22 (temp1
, addr
));
3447 emit_insn (gen_tie_lo10 (temp2
, temp1
, addr
));
3449 emit_insn (gen_tie_ld32 (temp3
, got
, temp2
, addr
));
3451 emit_insn (gen_tie_ld64 (temp3
, got
, temp2
, addr
));
3454 ret
= gen_reg_rtx (Pmode
);
3456 emit_insn (gen_tie_add32 (ret
, gen_rtx_REG (Pmode
, 7),
3459 emit_insn (gen_tie_add64 (ret
, gen_rtx_REG (Pmode
, 7),
3463 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp3
);
3466 case TLS_MODEL_LOCAL_EXEC
:
3467 temp1
= gen_reg_rtx (Pmode
);
3468 temp2
= gen_reg_rtx (Pmode
);
3471 emit_insn (gen_tle_hix22_sp32 (temp1
, addr
));
3472 emit_insn (gen_tle_lox10_sp32 (temp2
, temp1
, addr
));
3476 emit_insn (gen_tle_hix22_sp64 (temp1
, addr
));
3477 emit_insn (gen_tle_lox10_sp64 (temp2
, temp1
, addr
));
3479 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp2
);
3486 else if (GET_CODE (addr
) == CONST
)
3490 gcc_assert (GET_CODE (XEXP (addr
, 0)) == PLUS
);
3492 base
= sparc_legitimize_tls_address (XEXP (XEXP (addr
, 0), 0));
3493 offset
= XEXP (XEXP (addr
, 0), 1);
3495 base
= force_operand (base
, NULL_RTX
);
3496 if (!(GET_CODE (offset
) == CONST_INT
&& SMALL_INT (offset
)))
3497 offset
= force_reg (Pmode
, offset
);
3498 ret
= gen_rtx_PLUS (Pmode
, base
, offset
);
3502 gcc_unreachable (); /* for now ... */
3507 /* Legitimize PIC addresses. If the address is already position-independent,
3508 we return ORIG. Newly generated position-independent addresses go into a
3509 reg. This is REG if nonzero, otherwise we allocate register(s) as
3513 sparc_legitimize_pic_address (rtx orig
, rtx reg
)
3515 bool gotdata_op
= false;
3517 if (GET_CODE (orig
) == SYMBOL_REF
3518 /* See the comment in sparc_expand_move. */
3519 || (GET_CODE (orig
) == LABEL_REF
&& !can_use_mov_pic_label_ref (orig
)))
3521 rtx pic_ref
, address
;
3526 gcc_assert (! reload_in_progress
&& ! reload_completed
);
3527 reg
= gen_reg_rtx (Pmode
);
3532 /* If not during reload, allocate another temp reg here for loading
3533 in the address, so that these instructions can be optimized
3535 rtx temp_reg
= ((reload_in_progress
|| reload_completed
)
3536 ? reg
: gen_reg_rtx (Pmode
));
3538 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3539 won't get confused into thinking that these two instructions
3540 are loading in the true address of the symbol. If in the
3541 future a PIC rtx exists, that should be used instead. */
3544 emit_insn (gen_movdi_high_pic (temp_reg
, orig
));
3545 emit_insn (gen_movdi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3549 emit_insn (gen_movsi_high_pic (temp_reg
, orig
));
3550 emit_insn (gen_movsi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3558 crtl
->uses_pic_offset_table
= 1;
3562 insn
= emit_insn (gen_movdi_pic_gotdata_op (reg
,
3563 pic_offset_table_rtx
,
3566 insn
= emit_insn (gen_movsi_pic_gotdata_op (reg
,
3567 pic_offset_table_rtx
,
3573 = gen_const_mem (Pmode
,
3574 gen_rtx_PLUS (Pmode
,
3575 pic_offset_table_rtx
, address
));
3576 insn
= emit_move_insn (reg
, pic_ref
);
3579 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3581 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
3584 else if (GET_CODE (orig
) == CONST
)
3588 if (GET_CODE (XEXP (orig
, 0)) == PLUS
3589 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
3594 gcc_assert (! reload_in_progress
&& ! reload_completed
);
3595 reg
= gen_reg_rtx (Pmode
);
3598 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
3599 base
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), reg
);
3600 offset
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
3601 base
== reg
? NULL_RTX
: reg
);
3603 if (GET_CODE (offset
) == CONST_INT
)
3605 if (SMALL_INT (offset
))
3606 return plus_constant (base
, INTVAL (offset
));
3607 else if (! reload_in_progress
&& ! reload_completed
)
3608 offset
= force_reg (Pmode
, offset
);
3610 /* If we reach here, then something is seriously wrong. */
3613 return gen_rtx_PLUS (Pmode
, base
, offset
);
3615 else if (GET_CODE (orig
) == LABEL_REF
)
3616 /* ??? We ought to be checking that the register is live instead, in case
3617 it is eliminated. */
3618 crtl
->uses_pic_offset_table
= 1;
3623 /* Try machine-dependent ways of modifying an illegitimate address X
3624 to be legitimate. If we find one, return the new, valid address.
3626 OLDX is the address as it was before break_out_memory_refs was called.
3627 In some cases it is useful to look at this to decide what needs to be done.
3629 MODE is the mode of the operand pointed to by X.
3631 On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
3634 sparc_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3635 enum machine_mode mode
)
3639 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
)
3640 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
3641 force_operand (XEXP (x
, 0), NULL_RTX
));
3642 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == MULT
)
3643 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3644 force_operand (XEXP (x
, 1), NULL_RTX
));
3645 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
3646 x
= gen_rtx_PLUS (Pmode
, force_operand (XEXP (x
, 0), NULL_RTX
),
3648 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == PLUS
)
3649 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3650 force_operand (XEXP (x
, 1), NULL_RTX
));
3652 if (x
!= orig_x
&& sparc_legitimate_address_p (mode
, x
, FALSE
))
3655 if (sparc_tls_referenced_p (x
))
3656 x
= sparc_legitimize_tls_address (x
);
3658 x
= sparc_legitimize_pic_address (x
, NULL_RTX
);
3659 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 1)))
3660 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
3661 copy_to_mode_reg (Pmode
, XEXP (x
, 1)));
3662 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 0)))
3663 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
3664 copy_to_mode_reg (Pmode
, XEXP (x
, 0)));
3665 else if (GET_CODE (x
) == SYMBOL_REF
3666 || GET_CODE (x
) == CONST
3667 || GET_CODE (x
) == LABEL_REF
)
3668 x
= copy_to_suggested_reg (x
, NULL_RTX
, Pmode
);
3673 /* Delegitimize an address that was legitimized by the above function. */
3676 sparc_delegitimize_address (rtx x
)
3678 x
= delegitimize_mem_from_attrs (x
);
3680 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 1)) == UNSPEC
)
3681 switch (XINT (XEXP (x
, 1), 1))
3683 case UNSPEC_MOVE_PIC
:
3685 x
= XVECEXP (XEXP (x
, 1), 0, 0);
3686 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
3692 /* This is generated by mov{si,di}_pic_label_ref in PIC mode. */
3693 if (GET_CODE (x
) == MINUS
3694 && REG_P (XEXP (x
, 0))
3695 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
3696 && GET_CODE (XEXP (x
, 1)) == LO_SUM
3697 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == UNSPEC
3698 && XINT (XEXP (XEXP (x
, 1), 1), 1) == UNSPEC_MOVE_PIC_LABEL
)
3700 x
= XVECEXP (XEXP (XEXP (x
, 1), 1), 0, 0);
3701 gcc_assert (GET_CODE (x
) == LABEL_REF
);
3707 /* SPARC implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3708 replace the input X, or the original X if no replacement is called for.
3709 The output parameter *WIN is 1 if the calling macro should goto WIN,
3712 For SPARC, we wish to handle addresses by splitting them into
3713 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
3714 This cuts the number of extra insns by one.
3716 Do nothing when generating PIC code and the address is a symbolic
3717 operand or requires a scratch register. */
3720 sparc_legitimize_reload_address (rtx x
, enum machine_mode mode
,
3721 int opnum
, int type
,
3722 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
3724 /* Decompose SImode constants into HIGH+LO_SUM. */
3726 && (mode
!= TFmode
|| TARGET_ARCH64
)
3727 && GET_MODE (x
) == SImode
3728 && GET_CODE (x
) != LO_SUM
3729 && GET_CODE (x
) != HIGH
3730 && sparc_cmodel
<= CM_MEDLOW
3732 && (symbolic_operand (x
, Pmode
) || pic_address_needs_scratch (x
))))
3734 x
= gen_rtx_LO_SUM (GET_MODE (x
), gen_rtx_HIGH (GET_MODE (x
), x
), x
);
3735 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3736 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
3737 opnum
, (enum reload_type
)type
);
3742 /* We have to recognize what we have already generated above. */
3743 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == HIGH
)
3745 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
3746 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
3747 opnum
, (enum reload_type
)type
);
3756 /* Return true if ADDR (a legitimate address expression)
3757 has an effect that depends on the machine mode it is used for.
3763 is not equivalent to
3765 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
3767 because [%l7+a+1] is interpreted as the address of (a+1). */
3771 sparc_mode_dependent_address_p (const_rtx addr
)
3773 if (flag_pic
&& GET_CODE (addr
) == PLUS
)
3775 rtx op0
= XEXP (addr
, 0);
3776 rtx op1
= XEXP (addr
, 1);
3777 if (op0
== pic_offset_table_rtx
3778 && symbolic_operand (op1
, VOIDmode
))
3785 #ifdef HAVE_GAS_HIDDEN
3786 # define USE_HIDDEN_LINKONCE 1
3788 # define USE_HIDDEN_LINKONCE 0
3792 get_pc_thunk_name (char name
[32], unsigned int regno
)
3794 const char *reg_name
= reg_names
[regno
];
3796 /* Skip the leading '%' as that cannot be used in a
3800 if (USE_HIDDEN_LINKONCE
)
3801 sprintf (name
, "__sparc_get_pc_thunk.%s", reg_name
);
3803 ASM_GENERATE_INTERNAL_LABEL (name
, "LADDPC", regno
);
3806 /* Wrapper around the load_pcrel_sym{si,di} patterns. */
3809 gen_load_pcrel_sym (rtx op0
, rtx op1
, rtx op2
, rtx op3
)
3811 int orig_flag_pic
= flag_pic
;
3814 /* The load_pcrel_sym{si,di} patterns require absolute addressing. */
3817 insn
= gen_load_pcrel_symdi (op0
, op1
, op2
, op3
);
3819 insn
= gen_load_pcrel_symsi (op0
, op1
, op2
, op3
);
3820 flag_pic
= orig_flag_pic
;
3825 /* Emit code to load the GOT register. */
3828 load_got_register (void)
3830 /* In PIC mode, this will retrieve pic_offset_table_rtx. */
3831 if (!global_offset_table_rtx
)
3832 global_offset_table_rtx
= gen_rtx_REG (Pmode
, GLOBAL_OFFSET_TABLE_REGNUM
);
3834 if (TARGET_VXWORKS_RTP
)
3835 emit_insn (gen_vxworks_load_got ());
3838 /* The GOT symbol is subject to a PC-relative relocation so we need a
3839 helper function to add the PC value and thus get the final value. */
3840 if (!got_helper_rtx
)
3843 get_pc_thunk_name (name
, GLOBAL_OFFSET_TABLE_REGNUM
);
3844 got_helper_rtx
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
3847 emit_insn (gen_load_pcrel_sym (global_offset_table_rtx
, sparc_got (),
3849 GEN_INT (GLOBAL_OFFSET_TABLE_REGNUM
)));
3852 /* Need to emit this whether or not we obey regdecls,
3853 since setjmp/longjmp can cause life info to screw up.
3854 ??? In the case where we don't obey regdecls, this is not sufficient
3855 since we may not fall out the bottom. */
3856 emit_use (global_offset_table_rtx
);
3859 /* Emit a call instruction with the pattern given by PAT. ADDR is the
3860 address of the call target. */
3863 sparc_emit_call_insn (rtx pat
, rtx addr
)
3867 insn
= emit_call_insn (pat
);
3869 /* The PIC register is live on entry to VxWorks PIC PLT entries. */
3870 if (TARGET_VXWORKS_RTP
3872 && GET_CODE (addr
) == SYMBOL_REF
3873 && (SYMBOL_REF_DECL (addr
)
3874 ? !targetm
.binds_local_p (SYMBOL_REF_DECL (addr
))
3875 : !SYMBOL_REF_LOCAL_P (addr
)))
3877 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
3878 crtl
->uses_pic_offset_table
= 1;
3882 /* Return 1 if RTX is a MEM which is known to be aligned to at
3883 least a DESIRED byte boundary. */
3886 mem_min_alignment (rtx mem
, int desired
)
3888 rtx addr
, base
, offset
;
3890 /* If it's not a MEM we can't accept it. */
3891 if (GET_CODE (mem
) != MEM
)
3895 if (!TARGET_UNALIGNED_DOUBLES
3896 && MEM_ALIGN (mem
) / BITS_PER_UNIT
>= (unsigned)desired
)
3899 /* ??? The rest of the function predates MEM_ALIGN so
3900 there is probably a bit of redundancy. */
3901 addr
= XEXP (mem
, 0);
3902 base
= offset
= NULL_RTX
;
3903 if (GET_CODE (addr
) == PLUS
)
3905 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3907 base
= XEXP (addr
, 0);
3909 /* What we are saying here is that if the base
3910 REG is aligned properly, the compiler will make
3911 sure any REG based index upon it will be so
3913 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
3914 offset
= XEXP (addr
, 1);
3916 offset
= const0_rtx
;
3919 else if (GET_CODE (addr
) == REG
)
3922 offset
= const0_rtx
;
3925 if (base
!= NULL_RTX
)
3927 int regno
= REGNO (base
);
3929 if (regno
!= HARD_FRAME_POINTER_REGNUM
&& regno
!= STACK_POINTER_REGNUM
)
3931 /* Check if the compiler has recorded some information
3932 about the alignment of the base REG. If reload has
3933 completed, we already matched with proper alignments.
3934 If not running global_alloc, reload might give us
3935 unaligned pointer to local stack though. */
3937 && REGNO_POINTER_ALIGN (regno
) >= desired
* BITS_PER_UNIT
)
3938 || (optimize
&& reload_completed
))
3939 && (INTVAL (offset
) & (desired
- 1)) == 0)
3944 if (((INTVAL (offset
) - SPARC_STACK_BIAS
) & (desired
- 1)) == 0)
3948 else if (! TARGET_UNALIGNED_DOUBLES
3949 || CONSTANT_P (addr
)
3950 || GET_CODE (addr
) == LO_SUM
)
3952 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3953 is true, in which case we can only assume that an access is aligned if
3954 it is to a constant address, or the address involves a LO_SUM. */
3958 /* An obviously unaligned address. */
3963 /* Vectors to keep interesting information about registers where it can easily
3964 be got. We used to use the actual mode value as the bit number, but there
3965 are more than 32 modes now. Instead we use two tables: one indexed by
3966 hard register number, and one indexed by mode. */
3968 /* The purpose of sparc_mode_class is to shrink the range of modes so that
3969 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
3970 mapped into one sparc_mode_class mode. */
3972 enum sparc_mode_class
{
3973 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
3974 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
3978 /* Modes for single-word and smaller quantities. */
3979 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3981 /* Modes for double-word and smaller quantities. */
3982 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3984 /* Modes for quad-word and smaller quantities. */
3985 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
3987 /* Modes for 8-word and smaller quantities. */
3988 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3990 /* Modes for single-float quantities. We must allow any single word or
3991 smaller quantity. This is because the fix/float conversion instructions
3992 take integer inputs/outputs from the float registers. */
3993 #define SF_MODES (S_MODES)
3995 /* Modes for double-float and smaller quantities. */
3996 #define DF_MODES (D_MODES)
3998 /* Modes for quad-float and smaller quantities. */
3999 #define TF_MODES (DF_MODES | (1 << (int) TF_MODE))
4001 /* Modes for quad-float pairs and smaller quantities. */
4002 #define OF_MODES (TF_MODES | (1 << (int) OF_MODE))
4004 /* Modes for double-float only quantities. */
4005 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
4007 /* Modes for quad-float and double-float only quantities. */
4008 #define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE))
4010 /* Modes for quad-float pairs and double-float only quantities. */
4011 #define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE))
4013 /* Modes for condition codes. */
4014 #define CC_MODES (1 << (int) CC_MODE)
4015 #define CCFP_MODES (1 << (int) CCFP_MODE)
4017 /* Value is 1 if register/mode pair is acceptable on sparc.
4018 The funny mixture of D and T modes is because integer operations
4019 do not specially operate on tetra quantities, so non-quad-aligned
4020 registers can hold quadword quantities (except %o4 and %i4 because
4021 they cross fixed registers). */
4023 /* This points to either the 32 bit or the 64 bit version. */
4024 const int *hard_regno_mode_classes
;
4026 static const int hard_32bit_mode_classes
[] = {
4027 S_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
4028 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
4029 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
4030 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
4032 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4033 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4034 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4035 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4037 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4038 and none can hold SFmode/SImode values. */
4039 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4040 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4041 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4042 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4045 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
4047 /* %icc, %sfp, %gsr */
4048 CC_MODES
, 0, D_MODES
4051 static const int hard_64bit_mode_classes
[] = {
4052 D_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4053 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4054 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4055 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4057 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4058 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4059 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4060 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4062 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4063 and none can hold SFmode/SImode values. */
4064 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4065 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4066 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4067 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4070 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
4072 /* %icc, %sfp, %gsr */
4073 CC_MODES
, 0, D_MODES
4076 int sparc_mode_class
[NUM_MACHINE_MODES
];
4078 enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
4081 sparc_init_modes (void)
4085 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
4087 switch (GET_MODE_CLASS (i
))
4090 case MODE_PARTIAL_INT
:
4091 case MODE_COMPLEX_INT
:
4092 if (GET_MODE_SIZE (i
) <= 4)
4093 sparc_mode_class
[i
] = 1 << (int) S_MODE
;
4094 else if (GET_MODE_SIZE (i
) == 8)
4095 sparc_mode_class
[i
] = 1 << (int) D_MODE
;
4096 else if (GET_MODE_SIZE (i
) == 16)
4097 sparc_mode_class
[i
] = 1 << (int) T_MODE
;
4098 else if (GET_MODE_SIZE (i
) == 32)
4099 sparc_mode_class
[i
] = 1 << (int) O_MODE
;
4101 sparc_mode_class
[i
] = 0;
4103 case MODE_VECTOR_INT
:
4104 if (GET_MODE_SIZE (i
) <= 4)
4105 sparc_mode_class
[i
] = 1 << (int)SF_MODE
;
4106 else if (GET_MODE_SIZE (i
) == 8)
4107 sparc_mode_class
[i
] = 1 << (int)DF_MODE
;
4110 case MODE_COMPLEX_FLOAT
:
4111 if (GET_MODE_SIZE (i
) <= 4)
4112 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
4113 else if (GET_MODE_SIZE (i
) == 8)
4114 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
4115 else if (GET_MODE_SIZE (i
) == 16)
4116 sparc_mode_class
[i
] = 1 << (int) TF_MODE
;
4117 else if (GET_MODE_SIZE (i
) == 32)
4118 sparc_mode_class
[i
] = 1 << (int) OF_MODE
;
4120 sparc_mode_class
[i
] = 0;
4123 if (i
== (int) CCFPmode
|| i
== (int) CCFPEmode
)
4124 sparc_mode_class
[i
] = 1 << (int) CCFP_MODE
;
4126 sparc_mode_class
[i
] = 1 << (int) CC_MODE
;
4129 sparc_mode_class
[i
] = 0;
4135 hard_regno_mode_classes
= hard_64bit_mode_classes
;
4137 hard_regno_mode_classes
= hard_32bit_mode_classes
;
4139 /* Initialize the array used by REGNO_REG_CLASS. */
4140 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4142 if (i
< 16 && TARGET_V8PLUS
)
4143 sparc_regno_reg_class
[i
] = I64_REGS
;
4144 else if (i
< 32 || i
== FRAME_POINTER_REGNUM
)
4145 sparc_regno_reg_class
[i
] = GENERAL_REGS
;
4147 sparc_regno_reg_class
[i
] = FP_REGS
;
4149 sparc_regno_reg_class
[i
] = EXTRA_FP_REGS
;
4151 sparc_regno_reg_class
[i
] = FPCC_REGS
;
4153 sparc_regno_reg_class
[i
] = NO_REGS
;
4157 /* Return whether REGNO, a global or FP register, must be saved/restored. */
4160 save_global_or_fp_reg_p (unsigned int regno
,
4161 int leaf_function ATTRIBUTE_UNUSED
)
4163 return !call_used_regs
[regno
] && df_regs_ever_live_p (regno
);
4166 /* Return whether the return address register (%i7) is needed. */
4169 return_addr_reg_needed_p (int leaf_function
)
4171 /* If it is live, for example because of __builtin_return_address (0). */
4172 if (df_regs_ever_live_p (RETURN_ADDR_REGNUM
))
4175 /* Otherwise, it is needed as save register if %o7 is clobbered. */
4177 /* Loading the GOT register clobbers %o7. */
4178 || crtl
->uses_pic_offset_table
4179 || df_regs_ever_live_p (INCOMING_RETURN_ADDR_REGNUM
))
4185 /* Return whether REGNO, a local or in register, must be saved/restored. */
4188 save_local_or_in_reg_p (unsigned int regno
, int leaf_function
)
4190 /* General case: call-saved registers live at some point. */
4191 if (!call_used_regs
[regno
] && df_regs_ever_live_p (regno
))
4194 /* Frame pointer register (%fp) if needed. */
4195 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
4198 /* Return address register (%i7) if needed. */
4199 if (regno
== RETURN_ADDR_REGNUM
&& return_addr_reg_needed_p (leaf_function
))
4202 /* GOT register (%l7) if needed. */
4203 if (regno
== PIC_OFFSET_TABLE_REGNUM
&& crtl
->uses_pic_offset_table
)
4206 /* If the function accesses prior frames, the frame pointer and the return
4207 address of the previous frame must be saved on the stack. */
4208 if (crtl
->accesses_prior_frames
4209 && (regno
== HARD_FRAME_POINTER_REGNUM
|| regno
== RETURN_ADDR_REGNUM
))
4215 /* Compute the frame size required by the function. This function is called
4216 during the reload pass and also by sparc_expand_prologue. */
4219 sparc_compute_frame_size (HOST_WIDE_INT size
, int leaf_function
)
4221 HOST_WIDE_INT frame_size
, apparent_frame_size
;
4222 int args_size
, n_global_fp_regs
= 0;
4223 bool save_local_in_regs_p
= false;
4226 /* If the function allocates dynamic stack space, the dynamic offset is
4227 computed early and contains REG_PARM_STACK_SPACE, so we need to cope. */
4228 if (leaf_function
&& !cfun
->calls_alloca
)
4231 args_size
= crtl
->outgoing_args_size
+ REG_PARM_STACK_SPACE (cfun
->decl
);
4233 /* Calculate space needed for global registers. */
4235 for (i
= 0; i
< 8; i
++)
4236 if (save_global_or_fp_reg_p (i
, 0))
4237 n_global_fp_regs
+= 2;
4239 for (i
= 0; i
< 8; i
+= 2)
4240 if (save_global_or_fp_reg_p (i
, 0) || save_global_or_fp_reg_p (i
+ 1, 0))
4241 n_global_fp_regs
+= 2;
4243 /* In the flat window model, find out which local and in registers need to
4244 be saved. We don't reserve space in the current frame for them as they
4245 will be spilled into the register window save area of the caller's frame.
4246 However, as soon as we use this register window save area, we must create
4247 that of the current frame to make it the live one. */
4249 for (i
= 16; i
< 32; i
++)
4250 if (save_local_or_in_reg_p (i
, leaf_function
))
4252 save_local_in_regs_p
= true;
4256 /* Calculate space needed for FP registers. */
4257 for (i
= 32; i
< (TARGET_V9
? 96 : 64); i
+= 2)
4258 if (save_global_or_fp_reg_p (i
, 0) || save_global_or_fp_reg_p (i
+ 1, 0))
4259 n_global_fp_regs
+= 2;
4262 && n_global_fp_regs
== 0
4264 && !save_local_in_regs_p
)
4265 frame_size
= apparent_frame_size
= 0;
4268 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4269 apparent_frame_size
= (size
- STARTING_FRAME_OFFSET
+ 7) & -8;
4270 apparent_frame_size
+= n_global_fp_regs
* 4;
4272 /* We need to add the size of the outgoing argument area. */
4273 frame_size
= apparent_frame_size
+ ((args_size
+ 7) & -8);
4275 /* And that of the register window save area. */
4276 frame_size
+= FIRST_PARM_OFFSET (cfun
->decl
);
4278 /* Finally, bump to the appropriate alignment. */
4279 frame_size
= SPARC_STACK_ALIGN (frame_size
);
4282 /* Set up values for use in prologue and epilogue. */
4283 sparc_frame_size
= frame_size
;
4284 sparc_apparent_frame_size
= apparent_frame_size
;
4285 sparc_n_global_fp_regs
= n_global_fp_regs
;
4286 sparc_save_local_in_regs_p
= save_local_in_regs_p
;
4291 /* Output any necessary .register pseudo-ops. */
4294 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED
)
4296 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4302 /* Check if %g[2367] were used without
4303 .register being printed for them already. */
4304 for (i
= 2; i
< 8; i
++)
4306 if (df_regs_ever_live_p (i
)
4307 && ! sparc_hard_reg_printed
[i
])
4309 sparc_hard_reg_printed
[i
] = 1;
4310 /* %g7 is used as TLS base register, use #ignore
4311 for it instead of #scratch. */
4312 fprintf (file
, "\t.register\t%%g%d, #%s\n", i
,
4313 i
== 7 ? "ignore" : "scratch");
4320 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
4322 #if PROBE_INTERVAL > 4096
4323 #error Cannot use indexed addressing mode for stack probing
4326 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
4327 inclusive. These are offsets from the current stack pointer.
4329 Note that we don't use the REG+REG addressing mode for the probes because
4330 of the stack bias in 64-bit mode. And it doesn't really buy us anything
4331 so the advantages of having a single code win here. */
4334 sparc_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
4336 rtx g1
= gen_rtx_REG (Pmode
, 1);
4338 /* See if we have a constant small number of probes to generate. If so,
4339 that's the easy case. */
4340 if (size
<= PROBE_INTERVAL
)
4342 emit_move_insn (g1
, GEN_INT (first
));
4343 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
4344 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
4345 emit_stack_probe (plus_constant (g1
, -size
));
4348 /* The run-time loop is made up of 10 insns in the generic case while the
4349 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
4350 else if (size
<= 5 * PROBE_INTERVAL
)
4354 emit_move_insn (g1
, GEN_INT (first
+ PROBE_INTERVAL
));
4355 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
4356 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
4357 emit_stack_probe (g1
);
4359 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
4360 it exceeds SIZE. If only two probes are needed, this will not
4361 generate any code. Then probe at FIRST + SIZE. */
4362 for (i
= 2 * PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
4364 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
4365 plus_constant (g1
, -PROBE_INTERVAL
)));
4366 emit_stack_probe (g1
);
4369 emit_stack_probe (plus_constant (g1
, (i
- PROBE_INTERVAL
) - size
));
4372 /* Otherwise, do the same as above, but in a loop. Note that we must be
4373 extra careful with variables wrapping around because we might be at
4374 the very top (or the very bottom) of the address space and we have
4375 to be able to handle this case properly; in particular, we use an
4376 equality test for the loop condition. */
4379 HOST_WIDE_INT rounded_size
;
4380 rtx g4
= gen_rtx_REG (Pmode
, 4);
4382 emit_move_insn (g1
, GEN_INT (first
));
4385 /* Step 1: round SIZE to the previous multiple of the interval. */
4387 rounded_size
= size
& -PROBE_INTERVAL
;
4388 emit_move_insn (g4
, GEN_INT (rounded_size
));
4391 /* Step 2: compute initial and final value of the loop counter. */
4393 /* TEST_ADDR = SP + FIRST. */
4394 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
4395 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
4397 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
4398 emit_insn (gen_rtx_SET (VOIDmode
, g4
, gen_rtx_MINUS (Pmode
, g1
, g4
)));
4403 while (TEST_ADDR != LAST_ADDR)
4405 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
4409 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
4410 until it is equal to ROUNDED_SIZE. */
4413 emit_insn (gen_probe_stack_rangedi (g1
, g1
, g4
));
4415 emit_insn (gen_probe_stack_rangesi (g1
, g1
, g4
));
4418 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
4419 that SIZE is equal to ROUNDED_SIZE. */
4421 if (size
!= rounded_size
)
4422 emit_stack_probe (plus_constant (g4
, rounded_size
- size
));
4425 /* Make sure nothing is scheduled before we are done. */
4426 emit_insn (gen_blockage ());
4429 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
4430 absolute addresses. */
4433 output_probe_stack_range (rtx reg1
, rtx reg2
)
4435 static int labelno
= 0;
4436 char loop_lab
[32], end_lab
[32];
4439 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
4440 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
4442 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
4444 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
4447 output_asm_insn ("cmp\t%0, %1", xops
);
4449 fputs ("\tbe,pn\t%xcc,", asm_out_file
);
4451 fputs ("\tbe\t", asm_out_file
);
4452 assemble_name_raw (asm_out_file
, end_lab
);
4453 fputc ('\n', asm_out_file
);
4455 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
4456 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
4457 output_asm_insn (" add\t%0, %1, %0", xops
);
4459 /* Probe at TEST_ADDR and branch. */
4461 fputs ("\tba,pt\t%xcc,", asm_out_file
);
4463 fputs ("\tba\t", asm_out_file
);
4464 assemble_name_raw (asm_out_file
, loop_lab
);
4465 fputc ('\n', asm_out_file
);
4466 xops
[1] = GEN_INT (SPARC_STACK_BIAS
);
4467 output_asm_insn (" st\t%%g0, [%0+%1]", xops
);
4469 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
4474 /* Emit code to save/restore registers from LOW to HIGH at BASE+OFFSET as
4475 needed. LOW is supposed to be double-word aligned for 32-bit registers.
4476 SAVE_P decides whether a register must be saved/restored. ACTION_TRUE
4477 is the action to be performed if SAVE_P returns true and ACTION_FALSE
4478 the action to be performed if it returns false. Return the new offset. */
4480 typedef bool (*sorr_pred_t
) (unsigned int, int);
4481 typedef enum { SORR_NONE
, SORR_ADVANCE
, SORR_SAVE
, SORR_RESTORE
} sorr_act_t
;
4484 emit_save_or_restore_regs (unsigned int low
, unsigned int high
, rtx base
,
4485 int offset
, int leaf_function
, sorr_pred_t save_p
,
4486 sorr_act_t action_true
, sorr_act_t action_false
)
4491 if (TARGET_ARCH64
&& high
<= 32)
4495 for (i
= low
; i
< high
; i
++)
4497 if (save_p (i
, leaf_function
))
4499 mem
= gen_frame_mem (DImode
, plus_constant (base
, offset
));
4500 if (action_true
== SORR_SAVE
)
4502 insn
= emit_move_insn (mem
, gen_rtx_REG (DImode
, i
));
4503 RTX_FRAME_RELATED_P (insn
) = 1;
4505 else /* action_true == SORR_RESTORE */
4507 /* The frame pointer must be restored last since its old
4508 value may be used as base address for the frame. This
4509 is problematic in 64-bit mode only because of the lack
4510 of double-word load instruction. */
4511 if (i
== HARD_FRAME_POINTER_REGNUM
)
4514 emit_move_insn (gen_rtx_REG (DImode
, i
), mem
);
4518 else if (action_false
== SORR_ADVANCE
)
4524 mem
= gen_frame_mem (DImode
, plus_constant (base
, fp_offset
));
4525 emit_move_insn (hard_frame_pointer_rtx
, mem
);
4530 for (i
= low
; i
< high
; i
+= 2)
4532 bool reg0
= save_p (i
, leaf_function
);
4533 bool reg1
= save_p (i
+ 1, leaf_function
);
4534 enum machine_mode mode
;
4539 mode
= i
< 32 ? DImode
: DFmode
;
4544 mode
= i
< 32 ? SImode
: SFmode
;
4549 mode
= i
< 32 ? SImode
: SFmode
;
4555 if (action_false
== SORR_ADVANCE
)
4560 mem
= gen_frame_mem (mode
, plus_constant (base
, offset
));
4561 if (action_true
== SORR_SAVE
)
4563 insn
= emit_move_insn (mem
, gen_rtx_REG (mode
, regno
));
4564 RTX_FRAME_RELATED_P (insn
) = 1;
4568 mem
= gen_frame_mem (SImode
, plus_constant (base
, offset
));
4569 set1
= gen_rtx_SET (VOIDmode
, mem
,
4570 gen_rtx_REG (SImode
, regno
));
4571 RTX_FRAME_RELATED_P (set1
) = 1;
4573 = gen_frame_mem (SImode
, plus_constant (base
, offset
+ 4));
4574 set2
= gen_rtx_SET (VOIDmode
, mem
,
4575 gen_rtx_REG (SImode
, regno
+ 1));
4576 RTX_FRAME_RELATED_P (set2
) = 1;
4577 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
4578 gen_rtx_PARALLEL (VOIDmode
,
4579 gen_rtvec (2, set1
, set2
)));
4582 else /* action_true == SORR_RESTORE */
4583 emit_move_insn (gen_rtx_REG (mode
, regno
), mem
);
4585 /* Always preserve double-word alignment. */
4586 offset
= (offset
+ 8) & -8;
4593 /* Emit code to adjust BASE to OFFSET. Return the new base. */
4596 emit_adjust_base_to_offset (rtx base
, int offset
)
4598 /* ??? This might be optimized a little as %g1 might already have a
4599 value close enough that a single add insn will do. */
4600 /* ??? Although, all of this is probably only a temporary fix because
4601 if %g1 can hold a function result, then sparc_expand_epilogue will
4602 lose (the result will be clobbered). */
4603 rtx new_base
= gen_rtx_REG (Pmode
, 1);
4604 emit_move_insn (new_base
, GEN_INT (offset
));
4605 emit_insn (gen_rtx_SET (VOIDmode
,
4606 new_base
, gen_rtx_PLUS (Pmode
, base
, new_base
)));
4610 /* Emit code to save/restore call-saved global and FP registers. */
4613 emit_save_or_restore_global_fp_regs (rtx base
, int offset
, sorr_act_t action
)
4615 if (offset
< -4096 || offset
+ sparc_n_global_fp_regs
* 4 > 4095)
4617 base
= emit_adjust_base_to_offset (base
, offset
);
4622 = emit_save_or_restore_regs (0, 8, base
, offset
, 0,
4623 save_global_or_fp_reg_p
, action
, SORR_NONE
);
4624 emit_save_or_restore_regs (32, TARGET_V9
? 96 : 64, base
, offset
, 0,
4625 save_global_or_fp_reg_p
, action
, SORR_NONE
);
4628 /* Emit code to save/restore call-saved local and in registers. */
4631 emit_save_or_restore_local_in_regs (rtx base
, int offset
, sorr_act_t action
)
4633 if (offset
< -4096 || offset
+ 16 * UNITS_PER_WORD
> 4095)
4635 base
= emit_adjust_base_to_offset (base
, offset
);
4639 emit_save_or_restore_regs (16, 32, base
, offset
, sparc_leaf_function_p
,
4640 save_local_or_in_reg_p
, action
, SORR_ADVANCE
);
4643 /* Emit a window_save insn. */
4646 emit_window_save (rtx increment
)
4648 rtx insn
= emit_insn (gen_window_save (increment
));
4649 RTX_FRAME_RELATED_P (insn
) = 1;
4651 /* The incoming return address (%o7) is saved in %i7. */
4652 add_reg_note (insn
, REG_CFA_REGISTER
,
4653 gen_rtx_SET (VOIDmode
,
4654 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
),
4656 INCOMING_RETURN_ADDR_REGNUM
)));
4658 /* The window save event. */
4659 add_reg_note (insn
, REG_CFA_WINDOW_SAVE
, const0_rtx
);
4661 /* The CFA is %fp, the hard frame pointer. */
4662 add_reg_note (insn
, REG_CFA_DEF_CFA
,
4663 plus_constant (hard_frame_pointer_rtx
,
4664 INCOMING_FRAME_SP_OFFSET
));
4669 /* Generate an increment for the stack pointer. */
4672 gen_stack_pointer_inc (rtx increment
)
4674 return gen_rtx_SET (VOIDmode
,
4676 gen_rtx_PLUS (Pmode
,
4681 /* Generate a decrement for the stack pointer. */
4684 gen_stack_pointer_dec (rtx decrement
)
4686 return gen_rtx_SET (VOIDmode
,
4688 gen_rtx_MINUS (Pmode
,
4693 /* Expand the function prologue. The prologue is responsible for reserving
4694 storage for the frame, saving the call-saved registers and loading the
4695 GOT register if needed. */
4698 sparc_expand_prologue (void)
4703 /* Compute a snapshot of current_function_uses_only_leaf_regs. Relying
4704 on the final value of the flag means deferring the prologue/epilogue
4705 expansion until just before the second scheduling pass, which is too
4706 late to emit multiple epilogues or return insns.
4708 Of course we are making the assumption that the value of the flag
4709 will not change between now and its final value. Of the three parts
4710 of the formula, only the last one can reasonably vary. Let's take a
4711 closer look, after assuming that the first two ones are set to true
4712 (otherwise the last value is effectively silenced).
4714 If only_leaf_regs_used returns false, the global predicate will also
4715 be false so the actual frame size calculated below will be positive.
4716 As a consequence, the save_register_window insn will be emitted in
4717 the instruction stream; now this insn explicitly references %fp
4718 which is not a leaf register so only_leaf_regs_used will always
4719 return false subsequently.
4721 If only_leaf_regs_used returns true, we hope that the subsequent
4722 optimization passes won't cause non-leaf registers to pop up. For
4723 example, the regrename pass has special provisions to not rename to
4724 non-leaf registers in a leaf function. */
4725 sparc_leaf_function_p
4726 = optimize
> 0 && current_function_is_leaf
&& only_leaf_regs_used ();
4728 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
4730 if (flag_stack_usage_info
)
4731 current_function_static_stack_size
= size
;
4733 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
&& size
)
4734 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
4738 else if (sparc_leaf_function_p
)
4740 rtx size_int_rtx
= GEN_INT (-size
);
4743 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
4744 else if (size
<= 8192)
4746 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
4747 /* %sp is still the CFA register. */
4748 RTX_FRAME_RELATED_P (insn
) = 1;
4749 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
4753 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
4754 emit_move_insn (size_rtx
, size_int_rtx
);
4755 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
4756 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
4757 gen_stack_pointer_inc (size_int_rtx
));
4760 RTX_FRAME_RELATED_P (insn
) = 1;
4764 rtx size_int_rtx
= GEN_INT (-size
);
4767 emit_window_save (size_int_rtx
);
4768 else if (size
<= 8192)
4770 emit_window_save (GEN_INT (-4096));
4771 /* %sp is not the CFA register anymore. */
4772 emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
4776 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
4777 emit_move_insn (size_rtx
, size_int_rtx
);
4778 emit_window_save (size_rtx
);
4782 if (sparc_leaf_function_p
)
4784 sparc_frame_base_reg
= stack_pointer_rtx
;
4785 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
4789 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
4790 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
4793 if (sparc_n_global_fp_regs
> 0)
4794 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
4795 sparc_frame_base_offset
4796 - sparc_apparent_frame_size
,
4799 /* Load the GOT register if needed. */
4800 if (crtl
->uses_pic_offset_table
)
4801 load_got_register ();
4803 /* Advertise that the data calculated just above are now valid. */
4804 sparc_prologue_data_valid_p
= true;
4807 /* Expand the function prologue. The prologue is responsible for reserving
4808 storage for the frame, saving the call-saved registers and loading the
4809 GOT register if needed. */
4812 sparc_flat_expand_prologue (void)
4817 sparc_leaf_function_p
= optimize
> 0 && current_function_is_leaf
;
4819 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
4821 if (flag_stack_usage_info
)
4822 current_function_static_stack_size
= size
;
4824 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
&& size
)
4825 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
4827 if (sparc_save_local_in_regs_p
)
4828 emit_save_or_restore_local_in_regs (stack_pointer_rtx
, SPARC_STACK_BIAS
,
4835 rtx size_int_rtx
, size_rtx
;
4837 size_rtx
= size_int_rtx
= GEN_INT (-size
);
4839 /* We establish the frame (i.e. decrement the stack pointer) first, even
4840 if we use a frame pointer, because we cannot clobber any call-saved
4841 registers, including the frame pointer, if we haven't created a new
4842 register save area, for the sake of compatibility with the ABI. */
4844 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
4845 else if (size
<= 8192 && !frame_pointer_needed
)
4847 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
4848 RTX_FRAME_RELATED_P (insn
) = 1;
4849 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
4853 size_rtx
= gen_rtx_REG (Pmode
, 1);
4854 emit_move_insn (size_rtx
, size_int_rtx
);
4855 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
4856 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
4857 gen_stack_pointer_inc (size_int_rtx
));
4859 RTX_FRAME_RELATED_P (insn
) = 1;
4861 /* Ensure nothing is scheduled until after the frame is established. */
4862 emit_insn (gen_blockage ());
4864 if (frame_pointer_needed
)
4866 insn
= emit_insn (gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
4867 gen_rtx_MINUS (Pmode
,
4870 RTX_FRAME_RELATED_P (insn
) = 1;
4872 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
4873 gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
4874 plus_constant (stack_pointer_rtx
,
4878 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
4880 rtx o7
= gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
);
4881 rtx i7
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
4883 insn
= emit_move_insn (i7
, o7
);
4884 RTX_FRAME_RELATED_P (insn
) = 1;
4886 add_reg_note (insn
, REG_CFA_REGISTER
,
4887 gen_rtx_SET (VOIDmode
, i7
, o7
));
4889 /* Prevent this instruction from ever being considered dead,
4890 even if this function has no epilogue. */
4891 emit_insn (gen_rtx_USE (VOIDmode
, i7
));
4895 if (frame_pointer_needed
)
4897 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
4898 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
4902 sparc_frame_base_reg
= stack_pointer_rtx
;
4903 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
4906 if (sparc_n_global_fp_regs
> 0)
4907 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
4908 sparc_frame_base_offset
4909 - sparc_apparent_frame_size
,
4912 /* Load the GOT register if needed. */
4913 if (crtl
->uses_pic_offset_table
)
4914 load_got_register ();
4916 /* Advertise that the data calculated just above are now valid. */
4917 sparc_prologue_data_valid_p
= true;
4920 /* This function generates the assembly code for function entry, which boils
4921 down to emitting the necessary .register directives. */
4924 sparc_asm_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
4926 /* Check that the assumption we made in sparc_expand_prologue is valid. */
4928 gcc_assert (sparc_leaf_function_p
== current_function_uses_only_leaf_regs
);
4930 sparc_output_scratch_registers (file
);
4933 /* Expand the function epilogue, either normal or part of a sibcall.
4934 We emit all the instructions except the return or the call. */
4937 sparc_expand_epilogue (bool for_eh
)
4939 HOST_WIDE_INT size
= sparc_frame_size
;
4941 if (sparc_n_global_fp_regs
> 0)
4942 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
4943 sparc_frame_base_offset
4944 - sparc_apparent_frame_size
,
4947 if (size
== 0 || for_eh
)
4949 else if (sparc_leaf_function_p
)
4952 emit_insn (gen_stack_pointer_dec (GEN_INT (-size
)));
4953 else if (size
<= 8192)
4955 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096)));
4956 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - size
)));
4960 rtx reg
= gen_rtx_REG (Pmode
, 1);
4961 emit_move_insn (reg
, GEN_INT (-size
));
4962 emit_insn (gen_stack_pointer_dec (reg
));
4967 /* Expand the function epilogue, either normal or part of a sibcall.
4968 We emit all the instructions except the return or the call. */
4971 sparc_flat_expand_epilogue (bool for_eh
)
4973 HOST_WIDE_INT size
= sparc_frame_size
;
4975 if (sparc_n_global_fp_regs
> 0)
4976 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
4977 sparc_frame_base_offset
4978 - sparc_apparent_frame_size
,
4981 /* If we have a frame pointer, we'll need both to restore it before the
4982 frame is destroyed and use its current value in destroying the frame.
4983 Since we don't have an atomic way to do that in the flat window model,
4984 we save the current value into a temporary register (%g1). */
4985 if (frame_pointer_needed
&& !for_eh
)
4986 emit_move_insn (gen_rtx_REG (Pmode
, 1), hard_frame_pointer_rtx
);
4988 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
4989 emit_move_insn (gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
),
4990 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
));
4992 if (sparc_save_local_in_regs_p
)
4993 emit_save_or_restore_local_in_regs (sparc_frame_base_reg
,
4994 sparc_frame_base_offset
,
4997 if (size
== 0 || for_eh
)
4999 else if (frame_pointer_needed
)
5001 /* Make sure the frame is destroyed after everything else is done. */
5002 emit_insn (gen_blockage ());
5004 emit_move_insn (stack_pointer_rtx
, gen_rtx_REG (Pmode
, 1));
5009 emit_insn (gen_blockage ());
5012 emit_insn (gen_stack_pointer_dec (GEN_INT (-size
)));
5013 else if (size
<= 8192)
5015 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096)));
5016 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - size
)));
5020 rtx reg
= gen_rtx_REG (Pmode
, 1);
5021 emit_move_insn (reg
, GEN_INT (-size
));
5022 emit_insn (gen_stack_pointer_dec (reg
));
5027 /* Return true if it is appropriate to emit `return' instructions in the
5028 body of a function. */
5031 sparc_can_use_return_insn_p (void)
5033 return sparc_prologue_data_valid_p
5034 && sparc_n_global_fp_regs
== 0
5036 ? (sparc_frame_size
== 0 && !sparc_save_local_in_regs_p
)
5037 : (sparc_frame_size
== 0 || !sparc_leaf_function_p
);
5040 /* This function generates the assembly code for function exit. */
5043 sparc_asm_function_epilogue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
5045 /* If the last two instructions of a function are "call foo; dslot;"
5046 the return address might point to the first instruction in the next
5047 function and we have to output a dummy nop for the sake of sane
5048 backtraces in such cases. This is pointless for sibling calls since
5049 the return address is explicitly adjusted. */
5051 rtx insn
, last_real_insn
;
5053 insn
= get_last_insn ();
5055 last_real_insn
= prev_real_insn (insn
);
5057 && GET_CODE (last_real_insn
) == INSN
5058 && GET_CODE (PATTERN (last_real_insn
)) == SEQUENCE
)
5059 last_real_insn
= XVECEXP (PATTERN (last_real_insn
), 0, 0);
5062 && CALL_P (last_real_insn
)
5063 && !SIBLING_CALL_P (last_real_insn
))
5064 fputs("\tnop\n", file
);
5066 sparc_output_deferred_case_vectors ();
5069 /* Output a 'restore' instruction. */
5072 output_restore (rtx pat
)
5078 fputs ("\t restore\n", asm_out_file
);
5082 gcc_assert (GET_CODE (pat
) == SET
);
5084 operands
[0] = SET_DEST (pat
);
5085 pat
= SET_SRC (pat
);
5087 switch (GET_CODE (pat
))
5090 operands
[1] = XEXP (pat
, 0);
5091 operands
[2] = XEXP (pat
, 1);
5092 output_asm_insn (" restore %r1, %2, %Y0", operands
);
5095 operands
[1] = XEXP (pat
, 0);
5096 operands
[2] = XEXP (pat
, 1);
5097 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands
);
5100 operands
[1] = XEXP (pat
, 0);
5101 gcc_assert (XEXP (pat
, 1) == const1_rtx
);
5102 output_asm_insn (" restore %r1, %r1, %Y0", operands
);
5106 output_asm_insn (" restore %%g0, %1, %Y0", operands
);
5111 /* Output a return. */
5114 output_return (rtx insn
)
5116 if (crtl
->calls_eh_return
)
5118 /* If the function uses __builtin_eh_return, the eh_return
5119 machinery occupies the delay slot. */
5120 gcc_assert (!final_sequence
);
5122 if (flag_delayed_branch
)
5124 if (!TARGET_FLAT
&& TARGET_V9
)
5125 fputs ("\treturn\t%i7+8\n", asm_out_file
);
5129 fputs ("\trestore\n", asm_out_file
);
5131 fputs ("\tjmp\t%o7+8\n", asm_out_file
);
5134 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file
);
5139 fputs ("\trestore\n", asm_out_file
);
5141 fputs ("\tadd\t%sp, %g1, %sp\n", asm_out_file
);
5142 fputs ("\tjmp\t%o7+8\n\t nop\n", asm_out_file
);
5145 else if (sparc_leaf_function_p
|| TARGET_FLAT
)
5147 /* This is a leaf or flat function so we don't have to bother restoring
5148 the register window, which frees us from dealing with the convoluted
5149 semantics of restore/return. We simply output the jump to the
5150 return address and the insn in the delay slot (if any). */
5152 return "jmp\t%%o7+%)%#";
5156 /* This is a regular function so we have to restore the register window.
5157 We may have a pending insn for the delay slot, which will be either
5158 combined with the 'restore' instruction or put in the delay slot of
5159 the 'return' instruction. */
5165 delay
= NEXT_INSN (insn
);
5168 pat
= PATTERN (delay
);
5170 if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1))
5172 epilogue_renumber (&pat
, 0);
5173 return "return\t%%i7+%)%#";
5177 output_asm_insn ("jmp\t%%i7+%)", NULL
);
5178 output_restore (pat
);
5179 PATTERN (delay
) = gen_blockage ();
5180 INSN_CODE (delay
) = -1;
5185 /* The delay slot is empty. */
5187 return "return\t%%i7+%)\n\t nop";
5188 else if (flag_delayed_branch
)
5189 return "jmp\t%%i7+%)\n\t restore";
5191 return "restore\n\tjmp\t%%o7+%)\n\t nop";
5198 /* Output a sibling call. */
5201 output_sibcall (rtx insn
, rtx call_operand
)
5205 gcc_assert (flag_delayed_branch
);
5207 operands
[0] = call_operand
;
5209 if (sparc_leaf_function_p
|| TARGET_FLAT
)
5211 /* This is a leaf or flat function so we don't have to bother restoring
5212 the register window. We simply output the jump to the function and
5213 the insn in the delay slot (if any). */
5215 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P
&& final_sequence
));
5218 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
5221 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
5222 it into branch if possible. */
5223 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
5228 /* This is a regular function so we have to restore the register window.
5229 We may have a pending insn for the delay slot, which will be combined
5230 with the 'restore' instruction. */
5232 output_asm_insn ("call\t%a0, 0", operands
);
5236 rtx delay
= NEXT_INSN (insn
);
5239 output_restore (PATTERN (delay
));
5241 PATTERN (delay
) = gen_blockage ();
5242 INSN_CODE (delay
) = -1;
5245 output_restore (NULL_RTX
);
5251 /* Functions for handling argument passing.
5253 For 32-bit, the first 6 args are normally in registers and the rest are
5254 pushed. Any arg that starts within the first 6 words is at least
5255 partially passed in a register unless its data type forbids.
5257 For 64-bit, the argument registers are laid out as an array of 16 elements
5258 and arguments are added sequentially. The first 6 int args and up to the
5259 first 16 fp args (depending on size) are passed in regs.
5261 Slot Stack Integral Float Float in structure Double Long Double
5262 ---- ----- -------- ----- ------------------ ------ -----------
5263 15 [SP+248] %f31 %f30,%f31 %d30
5264 14 [SP+240] %f29 %f28,%f29 %d28 %q28
5265 13 [SP+232] %f27 %f26,%f27 %d26
5266 12 [SP+224] %f25 %f24,%f25 %d24 %q24
5267 11 [SP+216] %f23 %f22,%f23 %d22
5268 10 [SP+208] %f21 %f20,%f21 %d20 %q20
5269 9 [SP+200] %f19 %f18,%f19 %d18
5270 8 [SP+192] %f17 %f16,%f17 %d16 %q16
5271 7 [SP+184] %f15 %f14,%f15 %d14
5272 6 [SP+176] %f13 %f12,%f13 %d12 %q12
5273 5 [SP+168] %o5 %f11 %f10,%f11 %d10
5274 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
5275 3 [SP+152] %o3 %f7 %f6,%f7 %d6
5276 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
5277 1 [SP+136] %o1 %f3 %f2,%f3 %d2
5278 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
5280 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
5282 Integral arguments are always passed as 64-bit quantities appropriately
5285 Passing of floating point values is handled as follows.
5286 If a prototype is in scope:
5287 If the value is in a named argument (i.e. not a stdarg function or a
5288 value not part of the `...') then the value is passed in the appropriate
5290 If the value is part of the `...' and is passed in one of the first 6
5291 slots then the value is passed in the appropriate int reg.
5292 If the value is part of the `...' and is not passed in one of the first 6
5293 slots then the value is passed in memory.
5294 If a prototype is not in scope:
5295 If the value is one of the first 6 arguments the value is passed in the
5296 appropriate integer reg and the appropriate fp reg.
5297 If the value is not one of the first 6 arguments the value is passed in
5298 the appropriate fp reg and in memory.
5301 Summary of the calling conventions implemented by GCC on the SPARC:
5304 size argument return value
5306 small integer <4 int. reg. int. reg.
5307 word 4 int. reg. int. reg.
5308 double word 8 int. reg. int. reg.
5310 _Complex small integer <8 int. reg. int. reg.
5311 _Complex word 8 int. reg. int. reg.
5312 _Complex double word 16 memory int. reg.
5314 vector integer <=8 int. reg. FP reg.
5315 vector integer >8 memory memory
5317 float 4 int. reg. FP reg.
5318 double 8 int. reg. FP reg.
5319 long double 16 memory memory
5321 _Complex float 8 memory FP reg.
5322 _Complex double 16 memory FP reg.
5323 _Complex long double 32 memory FP reg.
5325 vector float any memory memory
5327 aggregate any memory memory
5332 size argument return value
5334 small integer <8 int. reg. int. reg.
5335 word 8 int. reg. int. reg.
5336 double word 16 int. reg. int. reg.
5338 _Complex small integer <16 int. reg. int. reg.
5339 _Complex word 16 int. reg. int. reg.
5340 _Complex double word 32 memory int. reg.
5342 vector integer <=16 FP reg. FP reg.
5343 vector integer 16<s<=32 memory FP reg.
5344 vector integer >32 memory memory
5346 float 4 FP reg. FP reg.
5347 double 8 FP reg. FP reg.
5348 long double 16 FP reg. FP reg.
5350 _Complex float 8 FP reg. FP reg.
5351 _Complex double 16 FP reg. FP reg.
5352 _Complex long double 32 memory FP reg.
5354 vector float <=16 FP reg. FP reg.
5355 vector float 16<s<=32 memory FP reg.
5356 vector float >32 memory memory
5358 aggregate <=16 reg. reg.
5359 aggregate 16<s<=32 memory reg.
5360 aggregate >32 memory memory
5364 Note #1: complex floating-point types follow the extended SPARC ABIs as
5365 implemented by the Sun compiler.
5367 Note #2: integral vector types follow the scalar floating-point types
5368 conventions to match what is implemented by the Sun VIS SDK.
5370 Note #3: floating-point vector types follow the aggregate types
5374 /* Maximum number of int regs for args. */
5375 #define SPARC_INT_ARG_MAX 6
5376 /* Maximum number of fp regs for args. */
5377 #define SPARC_FP_ARG_MAX 16
5379 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
5381 /* Handle the INIT_CUMULATIVE_ARGS macro.
5382 Initialize a variable CUM of type CUMULATIVE_ARGS
5383 for a call to a function whose data type is FNTYPE.
5384 For a library call, FNTYPE is 0. */
5387 init_cumulative_args (struct sparc_args
*cum
, tree fntype
,
5388 rtx libname ATTRIBUTE_UNUSED
,
5389 tree fndecl ATTRIBUTE_UNUSED
)
5392 cum
->prototype_p
= fntype
&& prototype_p (fntype
);
5393 cum
->libcall_p
= fntype
== 0;
5396 /* Handle promotion of pointer and integer arguments. */
5398 static enum machine_mode
5399 sparc_promote_function_mode (const_tree type
,
5400 enum machine_mode mode
,
5402 const_tree fntype ATTRIBUTE_UNUSED
,
5403 int for_return ATTRIBUTE_UNUSED
)
5405 if (type
!= NULL_TREE
&& POINTER_TYPE_P (type
))
5407 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
5411 /* Integral arguments are passed as full words, as per the ABI. */
5412 if (GET_MODE_CLASS (mode
) == MODE_INT
5413 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
5419 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
5422 sparc_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
5424 return TARGET_ARCH64
? true : false;
5427 /* Scan the record type TYPE and return the following predicates:
5428 - INTREGS_P: the record contains at least one field or sub-field
5429 that is eligible for promotion in integer registers.
5430 - FP_REGS_P: the record contains at least one field or sub-field
5431 that is eligible for promotion in floating-point registers.
5432 - PACKED_P: the record contains at least one field that is packed.
5434 Sub-fields are not taken into account for the PACKED_P predicate. */
5437 scan_record_type (const_tree type
, int *intregs_p
, int *fpregs_p
,
5442 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5444 if (TREE_CODE (field
) == FIELD_DECL
)
5446 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
5447 scan_record_type (TREE_TYPE (field
), intregs_p
, fpregs_p
, 0);
5448 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
5449 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
5455 if (packed_p
&& DECL_PACKED (field
))
5461 /* Compute the slot number to pass an argument in.
5462 Return the slot number or -1 if passing on the stack.
5464 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5465 the preceding args and about the function being called.
5466 MODE is the argument's machine mode.
5467 TYPE is the data type of the argument (as a tree).
5468 This is null for libcalls where that information may
5470 NAMED is nonzero if this argument is a named parameter
5471 (otherwise it is an extra parameter matching an ellipsis).
5472 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
5473 *PREGNO records the register number to use if scalar type.
5474 *PPADDING records the amount of padding needed in words. */
5477 function_arg_slotno (const struct sparc_args
*cum
, enum machine_mode mode
,
5478 const_tree type
, bool named
, bool incoming_p
,
5479 int *pregno
, int *ppadding
)
5481 int regbase
= (incoming_p
5482 ? SPARC_INCOMING_INT_ARG_FIRST
5483 : SPARC_OUTGOING_INT_ARG_FIRST
);
5484 int slotno
= cum
->words
;
5485 enum mode_class mclass
;
5490 if (type
&& TREE_ADDRESSABLE (type
))
5496 && TYPE_ALIGN (type
) % PARM_BOUNDARY
!= 0)
5499 /* For SPARC64, objects requiring 16-byte alignment get it. */
5501 && (type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
)) >= 128
5502 && (slotno
& 1) != 0)
5503 slotno
++, *ppadding
= 1;
5505 mclass
= GET_MODE_CLASS (mode
);
5506 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
5508 /* Vector types deserve special treatment because they are
5509 polymorphic wrt their mode, depending upon whether VIS
5510 instructions are enabled. */
5511 if (TREE_CODE (TREE_TYPE (type
)) == REAL_TYPE
)
5513 /* The SPARC port defines no floating-point vector modes. */
5514 gcc_assert (mode
== BLKmode
);
5518 /* Integral vector types should either have a vector
5519 mode or an integral mode, because we are guaranteed
5520 by pass_by_reference that their size is not greater
5521 than 16 bytes and TImode is 16-byte wide. */
5522 gcc_assert (mode
!= BLKmode
);
5524 /* Vector integers are handled like floats according to
5526 mclass
= MODE_FLOAT
;
5533 case MODE_COMPLEX_FLOAT
:
5534 case MODE_VECTOR_INT
:
5535 if (TARGET_ARCH64
&& TARGET_FPU
&& named
)
5537 if (slotno
>= SPARC_FP_ARG_MAX
)
5539 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
5540 /* Arguments filling only one single FP register are
5541 right-justified in the outer double FP register. */
5542 if (GET_MODE_SIZE (mode
) <= 4)
5549 case MODE_COMPLEX_INT
:
5550 if (slotno
>= SPARC_INT_ARG_MAX
)
5552 regno
= regbase
+ slotno
;
5556 if (mode
== VOIDmode
)
5557 /* MODE is VOIDmode when generating the actual call. */
5560 gcc_assert (mode
== BLKmode
);
5564 || (TREE_CODE (type
) != VECTOR_TYPE
5565 && TREE_CODE (type
) != RECORD_TYPE
))
5567 if (slotno
>= SPARC_INT_ARG_MAX
)
5569 regno
= regbase
+ slotno
;
5571 else /* TARGET_ARCH64 && type */
5573 int intregs_p
= 0, fpregs_p
= 0, packed_p
= 0;
5575 /* First see what kinds of registers we would need. */
5576 if (TREE_CODE (type
) == VECTOR_TYPE
)
5579 scan_record_type (type
, &intregs_p
, &fpregs_p
, &packed_p
);
5581 /* The ABI obviously doesn't specify how packed structures
5582 are passed. These are defined to be passed in int regs
5583 if possible, otherwise memory. */
5584 if (packed_p
|| !named
)
5585 fpregs_p
= 0, intregs_p
= 1;
5587 /* If all arg slots are filled, then must pass on stack. */
5588 if (fpregs_p
&& slotno
>= SPARC_FP_ARG_MAX
)
5591 /* If there are only int args and all int arg slots are filled,
5592 then must pass on stack. */
5593 if (!fpregs_p
&& intregs_p
&& slotno
>= SPARC_INT_ARG_MAX
)
5596 /* Note that even if all int arg slots are filled, fp members may
5597 still be passed in regs if such regs are available.
5598 *PREGNO isn't set because there may be more than one, it's up
5599 to the caller to compute them. */
5612 /* Handle recursive register counting for structure field layout. */
5614 struct function_arg_record_value_parms
5616 rtx ret
; /* return expression being built. */
5617 int slotno
; /* slot number of the argument. */
5618 int named
; /* whether the argument is named. */
5619 int regbase
; /* regno of the base register. */
5620 int stack
; /* 1 if part of the argument is on the stack. */
5621 int intoffset
; /* offset of the first pending integer field. */
5622 unsigned int nregs
; /* number of words passed in registers. */
5625 static void function_arg_record_value_3
5626 (HOST_WIDE_INT
, struct function_arg_record_value_parms
*);
5627 static void function_arg_record_value_2
5628 (const_tree
, HOST_WIDE_INT
, struct function_arg_record_value_parms
*, bool);
5629 static void function_arg_record_value_1
5630 (const_tree
, HOST_WIDE_INT
, struct function_arg_record_value_parms
*, bool);
5631 static rtx
function_arg_record_value (const_tree
, enum machine_mode
, int, int, int);
5632 static rtx
function_arg_union_value (int, enum machine_mode
, int, int);
5634 /* A subroutine of function_arg_record_value. Traverse the structure
5635 recursively and determine how many registers will be required. */
5638 function_arg_record_value_1 (const_tree type
, HOST_WIDE_INT startbitpos
,
5639 struct function_arg_record_value_parms
*parms
,
5644 /* We need to compute how many registers are needed so we can
5645 allocate the PARALLEL but before we can do that we need to know
5646 whether there are any packed fields. The ABI obviously doesn't
5647 specify how structures are passed in this case, so they are
5648 defined to be passed in int regs if possible, otherwise memory,
5649 regardless of whether there are fp values present. */
5652 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
5654 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
5661 /* Compute how many registers we need. */
5662 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5664 if (TREE_CODE (field
) == FIELD_DECL
)
5666 HOST_WIDE_INT bitpos
= startbitpos
;
5668 if (DECL_SIZE (field
) != 0)
5670 if (integer_zerop (DECL_SIZE (field
)))
5673 if (host_integerp (bit_position (field
), 1))
5674 bitpos
+= int_bit_position (field
);
5677 /* ??? FIXME: else assume zero offset. */
5679 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
5680 function_arg_record_value_1 (TREE_TYPE (field
),
5684 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
5685 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
5690 if (parms
->intoffset
!= -1)
5692 unsigned int startbit
, endbit
;
5693 int intslots
, this_slotno
;
5695 startbit
= parms
->intoffset
& -BITS_PER_WORD
;
5696 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5698 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
5699 this_slotno
= parms
->slotno
+ parms
->intoffset
5702 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
5704 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
5705 /* We need to pass this field on the stack. */
5709 parms
->nregs
+= intslots
;
5710 parms
->intoffset
= -1;
5713 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
5714 If it wasn't true we wouldn't be here. */
5715 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
5716 && DECL_MODE (field
) == BLKmode
)
5717 parms
->nregs
+= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
5718 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
5725 if (parms
->intoffset
== -1)
5726 parms
->intoffset
= bitpos
;
5732 /* A subroutine of function_arg_record_value. Assign the bits of the
5733 structure between parms->intoffset and bitpos to integer registers. */
5736 function_arg_record_value_3 (HOST_WIDE_INT bitpos
,
5737 struct function_arg_record_value_parms
*parms
)
5739 enum machine_mode mode
;
5741 unsigned int startbit
, endbit
;
5742 int this_slotno
, intslots
, intoffset
;
5745 if (parms
->intoffset
== -1)
5748 intoffset
= parms
->intoffset
;
5749 parms
->intoffset
= -1;
5751 startbit
= intoffset
& -BITS_PER_WORD
;
5752 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5753 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
5754 this_slotno
= parms
->slotno
+ intoffset
/ BITS_PER_WORD
;
5756 intslots
= MIN (intslots
, SPARC_INT_ARG_MAX
- this_slotno
);
5760 /* If this is the trailing part of a word, only load that much into
5761 the register. Otherwise load the whole register. Note that in
5762 the latter case we may pick up unwanted bits. It's not a problem
5763 at the moment but may wish to revisit. */
5765 if (intoffset
% BITS_PER_WORD
!= 0)
5766 mode
= smallest_mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
5771 intoffset
/= BITS_PER_UNIT
;
5774 regno
= parms
->regbase
+ this_slotno
;
5775 reg
= gen_rtx_REG (mode
, regno
);
5776 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
5777 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
5780 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
5785 while (intslots
> 0);
5788 /* A subroutine of function_arg_record_value. Traverse the structure
5789 recursively and assign bits to floating point registers. Track which
5790 bits in between need integer registers; invoke function_arg_record_value_3
5791 to make that happen. */
5794 function_arg_record_value_2 (const_tree type
, HOST_WIDE_INT startbitpos
,
5795 struct function_arg_record_value_parms
*parms
,
5801 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5803 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
5810 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5812 if (TREE_CODE (field
) == FIELD_DECL
)
5814 HOST_WIDE_INT bitpos
= startbitpos
;
5816 if (DECL_SIZE (field
) != 0)
5818 if (integer_zerop (DECL_SIZE (field
)))
5821 if (host_integerp (bit_position (field
), 1))
5822 bitpos
+= int_bit_position (field
);
5825 /* ??? FIXME: else assume zero offset. */
5827 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
5828 function_arg_record_value_2 (TREE_TYPE (field
),
5832 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
5833 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
5838 int this_slotno
= parms
->slotno
+ bitpos
/ BITS_PER_WORD
;
5839 int regno
, nregs
, pos
;
5840 enum machine_mode mode
= DECL_MODE (field
);
5843 function_arg_record_value_3 (bitpos
, parms
);
5845 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
5848 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
5849 nregs
= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
5851 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
5853 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
5859 regno
= SPARC_FP_ARG_FIRST
+ this_slotno
* 2;
5860 if (GET_MODE_SIZE (mode
) <= 4 && (bitpos
& 32) != 0)
5862 reg
= gen_rtx_REG (mode
, regno
);
5863 pos
= bitpos
/ BITS_PER_UNIT
;
5864 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
5865 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
5869 regno
+= GET_MODE_SIZE (mode
) / 4;
5870 reg
= gen_rtx_REG (mode
, regno
);
5871 pos
+= GET_MODE_SIZE (mode
);
5872 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
5873 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
5879 if (parms
->intoffset
== -1)
5880 parms
->intoffset
= bitpos
;
5886 /* Used by function_arg and sparc_function_value_1 to implement the complex
5887 conventions of the 64-bit ABI for passing and returning structures.
5888 Return an expression valid as a return value for the FUNCTION_ARG
5889 and TARGET_FUNCTION_VALUE.
5891 TYPE is the data type of the argument (as a tree).
5892 This is null for libcalls where that information may
5894 MODE is the argument's machine mode.
5895 SLOTNO is the index number of the argument's slot in the parameter array.
5896 NAMED is nonzero if this argument is a named parameter
5897 (otherwise it is an extra parameter matching an ellipsis).
5898 REGBASE is the regno of the base register for the parameter array. */
5901 function_arg_record_value (const_tree type
, enum machine_mode mode
,
5902 int slotno
, int named
, int regbase
)
5904 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
5905 struct function_arg_record_value_parms parms
;
5908 parms
.ret
= NULL_RTX
;
5909 parms
.slotno
= slotno
;
5910 parms
.named
= named
;
5911 parms
.regbase
= regbase
;
5914 /* Compute how many registers we need. */
5916 parms
.intoffset
= 0;
5917 function_arg_record_value_1 (type
, 0, &parms
, false);
5919 /* Take into account pending integer fields. */
5920 if (parms
.intoffset
!= -1)
5922 unsigned int startbit
, endbit
;
5923 int intslots
, this_slotno
;
5925 startbit
= parms
.intoffset
& -BITS_PER_WORD
;
5926 endbit
= (typesize
*BITS_PER_UNIT
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
5927 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
5928 this_slotno
= slotno
+ parms
.intoffset
/ BITS_PER_WORD
;
5930 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
5932 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
5933 /* We need to pass this field on the stack. */
5937 parms
.nregs
+= intslots
;
5939 nregs
= parms
.nregs
;
5941 /* Allocate the vector and handle some annoying special cases. */
5944 /* ??? Empty structure has no value? Duh? */
5947 /* Though there's nothing really to store, return a word register
5948 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
5949 leads to breakage due to the fact that there are zero bytes to
5951 return gen_rtx_REG (mode
, regbase
);
5955 /* ??? C++ has structures with no fields, and yet a size. Give up
5956 for now and pass everything back in integer registers. */
5957 nregs
= (typesize
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
5959 if (nregs
+ slotno
> SPARC_INT_ARG_MAX
)
5960 nregs
= SPARC_INT_ARG_MAX
- slotno
;
5962 gcc_assert (nregs
!= 0);
5964 parms
.ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (parms
.stack
+ nregs
));
5966 /* If at least one field must be passed on the stack, generate
5967 (parallel [(expr_list (nil) ...) ...]) so that all fields will
5968 also be passed on the stack. We can't do much better because the
5969 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
5970 of structures for which the fields passed exclusively in registers
5971 are not at the beginning of the structure. */
5973 XVECEXP (parms
.ret
, 0, 0)
5974 = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
5976 /* Fill in the entries. */
5978 parms
.intoffset
= 0;
5979 function_arg_record_value_2 (type
, 0, &parms
, false);
5980 function_arg_record_value_3 (typesize
* BITS_PER_UNIT
, &parms
);
5982 gcc_assert (parms
.nregs
== nregs
);
5987 /* Used by function_arg and sparc_function_value_1 to implement the conventions
5988 of the 64-bit ABI for passing and returning unions.
5989 Return an expression valid as a return value for the FUNCTION_ARG
5990 and TARGET_FUNCTION_VALUE.
5992 SIZE is the size in bytes of the union.
5993 MODE is the argument's machine mode.
5994 REGNO is the hard register the union will be passed in. */
5997 function_arg_union_value (int size
, enum machine_mode mode
, int slotno
,
6000 int nwords
= ROUND_ADVANCE (size
), i
;
6003 /* See comment in previous function for empty structures. */
6005 return gen_rtx_REG (mode
, regno
);
6007 if (slotno
== SPARC_INT_ARG_MAX
- 1)
6010 regs
= gen_rtx_PARALLEL (mode
, rtvec_alloc (nwords
));
6012 for (i
= 0; i
< nwords
; i
++)
6014 /* Unions are passed left-justified. */
6015 XVECEXP (regs
, 0, i
)
6016 = gen_rtx_EXPR_LIST (VOIDmode
,
6017 gen_rtx_REG (word_mode
, regno
),
6018 GEN_INT (UNITS_PER_WORD
* i
));
6025 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6026 for passing and returning large (BLKmode) vectors.
6027 Return an expression valid as a return value for the FUNCTION_ARG
6028 and TARGET_FUNCTION_VALUE.
6030 SIZE is the size in bytes of the vector (at least 8 bytes).
6031 REGNO is the FP hard register the vector will be passed in. */
6034 function_arg_vector_value (int size
, int regno
)
6036 int i
, nregs
= size
/ 8;
6039 regs
= gen_rtx_PARALLEL (BLKmode
, rtvec_alloc (nregs
));
6041 for (i
= 0; i
< nregs
; i
++)
6043 XVECEXP (regs
, 0, i
)
6044 = gen_rtx_EXPR_LIST (VOIDmode
,
6045 gen_rtx_REG (DImode
, regno
+ 2*i
),
6052 /* Determine where to put an argument to a function.
6053 Value is zero to push the argument on the stack,
6054 or a hard register in which to store the argument.
6056 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6057 the preceding args and about the function being called.
6058 MODE is the argument's machine mode.
6059 TYPE is the data type of the argument (as a tree).
6060 This is null for libcalls where that information may
6062 NAMED is true if this argument is a named parameter
6063 (otherwise it is an extra parameter matching an ellipsis).
6064 INCOMING_P is false for TARGET_FUNCTION_ARG, true for
6065 TARGET_FUNCTION_INCOMING_ARG. */
6068 sparc_function_arg_1 (cumulative_args_t cum_v
, enum machine_mode mode
,
6069 const_tree type
, bool named
, bool incoming_p
)
6071 const CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
6073 int regbase
= (incoming_p
6074 ? SPARC_INCOMING_INT_ARG_FIRST
6075 : SPARC_OUTGOING_INT_ARG_FIRST
);
6076 int slotno
, regno
, padding
;
6077 enum mode_class mclass
= GET_MODE_CLASS (mode
);
6079 slotno
= function_arg_slotno (cum
, mode
, type
, named
, incoming_p
,
6084 /* Vector types deserve special treatment because they are polymorphic wrt
6085 their mode, depending upon whether VIS instructions are enabled. */
6086 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
6088 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6089 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
6090 || (TARGET_ARCH64
&& size
<= 16));
6092 if (mode
== BLKmode
)
6093 return function_arg_vector_value (size
,
6094 SPARC_FP_ARG_FIRST
+ 2*slotno
);
6096 mclass
= MODE_FLOAT
;
6100 return gen_rtx_REG (mode
, regno
);
6102 /* Structures up to 16 bytes in size are passed in arg slots on the stack
6103 and are promoted to registers if possible. */
6104 if (type
&& TREE_CODE (type
) == RECORD_TYPE
)
6106 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6107 gcc_assert (size
<= 16);
6109 return function_arg_record_value (type
, mode
, slotno
, named
, regbase
);
6112 /* Unions up to 16 bytes in size are passed in integer registers. */
6113 else if (type
&& TREE_CODE (type
) == UNION_TYPE
)
6115 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6116 gcc_assert (size
<= 16);
6118 return function_arg_union_value (size
, mode
, slotno
, regno
);
6121 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
6122 but also have the slot allocated for them.
6123 If no prototype is in scope fp values in register slots get passed
6124 in two places, either fp regs and int regs or fp regs and memory. */
6125 else if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
6126 && SPARC_FP_REG_P (regno
))
6128 rtx reg
= gen_rtx_REG (mode
, regno
);
6129 if (cum
->prototype_p
|| cum
->libcall_p
)
6131 /* "* 2" because fp reg numbers are recorded in 4 byte
6134 /* ??? This will cause the value to be passed in the fp reg and
6135 in the stack. When a prototype exists we want to pass the
6136 value in the reg but reserve space on the stack. That's an
6137 optimization, and is deferred [for a bit]. */
6138 if ((regno
- SPARC_FP_ARG_FIRST
) >= SPARC_INT_ARG_MAX
* 2)
6139 return gen_rtx_PARALLEL (mode
,
6141 gen_rtx_EXPR_LIST (VOIDmode
,
6142 NULL_RTX
, const0_rtx
),
6143 gen_rtx_EXPR_LIST (VOIDmode
,
6147 /* ??? It seems that passing back a register even when past
6148 the area declared by REG_PARM_STACK_SPACE will allocate
6149 space appropriately, and will not copy the data onto the
6150 stack, exactly as we desire.
6152 This is due to locate_and_pad_parm being called in
6153 expand_call whenever reg_parm_stack_space > 0, which
6154 while beneficial to our example here, would seem to be
6155 in error from what had been intended. Ho hum... -- r~ */
6163 if ((regno
- SPARC_FP_ARG_FIRST
) < SPARC_INT_ARG_MAX
* 2)
6167 /* On incoming, we don't need to know that the value
6168 is passed in %f0 and %i0, and it confuses other parts
6169 causing needless spillage even on the simplest cases. */
6173 intreg
= (SPARC_OUTGOING_INT_ARG_FIRST
6174 + (regno
- SPARC_FP_ARG_FIRST
) / 2);
6176 v0
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
6177 v1
= gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (mode
, intreg
),
6179 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
6183 v0
= gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
6184 v1
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
6185 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
6190 /* All other aggregate types are passed in an integer register in a mode
6191 corresponding to the size of the type. */
6192 else if (type
&& AGGREGATE_TYPE_P (type
))
6194 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6195 gcc_assert (size
<= 16);
6197 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
6200 return gen_rtx_REG (mode
, regno
);
6203 /* Handle the TARGET_FUNCTION_ARG target hook. */
6206 sparc_function_arg (cumulative_args_t cum
, enum machine_mode mode
,
6207 const_tree type
, bool named
)
6209 return sparc_function_arg_1 (cum
, mode
, type
, named
, false);
6212 /* Handle the TARGET_FUNCTION_INCOMING_ARG target hook. */
6215 sparc_function_incoming_arg (cumulative_args_t cum
, enum machine_mode mode
,
6216 const_tree type
, bool named
)
6218 return sparc_function_arg_1 (cum
, mode
, type
, named
, true);
6221 /* For sparc64, objects requiring 16 byte alignment are passed that way. */
6224 sparc_function_arg_boundary (enum machine_mode mode
, const_tree type
)
6226 return ((TARGET_ARCH64
6227 && (GET_MODE_ALIGNMENT (mode
) == 128
6228 || (type
&& TYPE_ALIGN (type
) == 128)))
6233 /* For an arg passed partly in registers and partly in memory,
6234 this is the number of bytes of registers used.
6235 For args passed entirely in registers or entirely in memory, zero.
6237 Any arg that starts in the first 6 regs but won't entirely fit in them
6238 needs partial registers on v8. On v9, structures with integer
6239 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
6240 values that begin in the last fp reg [where "last fp reg" varies with the
6241 mode] will be split between that reg and memory. */
6244 sparc_arg_partial_bytes (cumulative_args_t cum
, enum machine_mode mode
,
6245 tree type
, bool named
)
6247 int slotno
, regno
, padding
;
6249 /* We pass false for incoming_p here, it doesn't matter. */
6250 slotno
= function_arg_slotno (get_cumulative_args (cum
), mode
, type
, named
,
6251 false, ®no
, &padding
);
6258 if ((slotno
+ (mode
== BLKmode
6259 ? ROUND_ADVANCE (int_size_in_bytes (type
))
6260 : ROUND_ADVANCE (GET_MODE_SIZE (mode
))))
6261 > SPARC_INT_ARG_MAX
)
6262 return (SPARC_INT_ARG_MAX
- slotno
) * UNITS_PER_WORD
;
6266 /* We are guaranteed by pass_by_reference that the size of the
6267 argument is not greater than 16 bytes, so we only need to return
6268 one word if the argument is partially passed in registers. */
6270 if (type
&& AGGREGATE_TYPE_P (type
))
6272 int size
= int_size_in_bytes (type
);
6274 if (size
> UNITS_PER_WORD
6275 && slotno
== SPARC_INT_ARG_MAX
- 1)
6276 return UNITS_PER_WORD
;
6278 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
6279 || (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
6280 && ! (TARGET_FPU
&& named
)))
6282 /* The complex types are passed as packed types. */
6283 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
6284 && slotno
== SPARC_INT_ARG_MAX
- 1)
6285 return UNITS_PER_WORD
;
6287 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
6289 if ((slotno
+ GET_MODE_SIZE (mode
) / UNITS_PER_WORD
)
6291 return UNITS_PER_WORD
;
6298 /* Handle the TARGET_PASS_BY_REFERENCE target hook.
6299 Specify whether to pass the argument by reference. */
6302 sparc_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
6303 enum machine_mode mode
, const_tree type
,
6304 bool named ATTRIBUTE_UNUSED
)
6307 /* Original SPARC 32-bit ABI says that structures and unions,
6308 and quad-precision floats are passed by reference. For Pascal,
6309 also pass arrays by reference. All other base types are passed
6312 Extended ABI (as implemented by the Sun compiler) says that all
6313 complex floats are passed by reference. Pass complex integers
6314 in registers up to 8 bytes. More generally, enforce the 2-word
6315 cap for passing arguments in registers.
6317 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6318 integers are passed like floats of the same size, that is in
6319 registers up to 8 bytes. Pass all vector floats by reference
6320 like structure and unions. */
6321 return ((type
&& (AGGREGATE_TYPE_P (type
) || VECTOR_FLOAT_TYPE_P (type
)))
6323 /* Catch CDImode, TFmode, DCmode and TCmode. */
6324 || GET_MODE_SIZE (mode
) > 8
6326 && TREE_CODE (type
) == VECTOR_TYPE
6327 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
6329 /* Original SPARC 64-bit ABI says that structures and unions
6330 smaller than 16 bytes are passed in registers, as well as
6331 all other base types.
6333 Extended ABI (as implemented by the Sun compiler) says that
6334 complex floats are passed in registers up to 16 bytes. Pass
6335 all complex integers in registers up to 16 bytes. More generally,
6336 enforce the 2-word cap for passing arguments in registers.
6338 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6339 integers are passed like floats of the same size, that is in
6340 registers (up to 16 bytes). Pass all vector floats like structure
6343 && (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == VECTOR_TYPE
)
6344 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 16)
6345 /* Catch CTImode and TCmode. */
6346 || GET_MODE_SIZE (mode
) > 16);
6349 /* Handle the TARGET_FUNCTION_ARG_ADVANCE hook.
6350 Update the data in CUM to advance over an argument
6351 of mode MODE and data type TYPE.
6352 TYPE is null for libcalls where that information may not be available. */
6355 sparc_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
6356 const_tree type
, bool named
)
6358 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
6361 /* We pass false for incoming_p here, it doesn't matter. */
6362 function_arg_slotno (cum
, mode
, type
, named
, false, ®no
, &padding
);
6364 /* If argument requires leading padding, add it. */
6365 cum
->words
+= padding
;
6369 cum
->words
+= (mode
!= BLKmode
6370 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
6371 : ROUND_ADVANCE (int_size_in_bytes (type
)));
6375 if (type
&& AGGREGATE_TYPE_P (type
))
6377 int size
= int_size_in_bytes (type
);
6381 else if (size
<= 16)
6383 else /* passed by reference */
6388 cum
->words
+= (mode
!= BLKmode
6389 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
6390 : ROUND_ADVANCE (int_size_in_bytes (type
)));
6395 /* Handle the FUNCTION_ARG_PADDING macro.
6396 For the 64 bit ABI structs are always stored left shifted in their
6400 function_arg_padding (enum machine_mode mode
, const_tree type
)
6402 if (TARGET_ARCH64
&& type
!= 0 && AGGREGATE_TYPE_P (type
))
6405 /* Fall back to the default. */
6406 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
6409 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
6410 Specify whether to return the return value in memory. */
6413 sparc_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
6416 /* Original SPARC 32-bit ABI says that structures and unions,
6417 and quad-precision floats are returned in memory. All other
6418 base types are returned in registers.
6420 Extended ABI (as implemented by the Sun compiler) says that
6421 all complex floats are returned in registers (8 FP registers
6422 at most for '_Complex long double'). Return all complex integers
6423 in registers (4 at most for '_Complex long long').
6425 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6426 integers are returned like floats of the same size, that is in
6427 registers up to 8 bytes and in memory otherwise. Return all
6428 vector floats in memory like structure and unions; note that
6429 they always have BLKmode like the latter. */
6430 return (TYPE_MODE (type
) == BLKmode
6431 || TYPE_MODE (type
) == TFmode
6432 || (TREE_CODE (type
) == VECTOR_TYPE
6433 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
6435 /* Original SPARC 64-bit ABI says that structures and unions
6436 smaller than 32 bytes are returned in registers, as well as
6437 all other base types.
6439 Extended ABI (as implemented by the Sun compiler) says that all
6440 complex floats are returned in registers (8 FP registers at most
6441 for '_Complex long double'). Return all complex integers in
6442 registers (4 at most for '_Complex TItype').
6444 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6445 integers are returned like floats of the same size, that is in
6446 registers. Return all vector floats like structure and unions;
6447 note that they always have BLKmode like the latter. */
6448 return (TYPE_MODE (type
) == BLKmode
6449 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 32);
6452 /* Handle the TARGET_STRUCT_VALUE target hook.
6453 Return where to find the structure return value address. */
6456 sparc_struct_value_rtx (tree fndecl
, int incoming
)
6465 mem
= gen_frame_mem (Pmode
, plus_constant (frame_pointer_rtx
,
6466 STRUCT_VALUE_OFFSET
));
6468 mem
= gen_frame_mem (Pmode
, plus_constant (stack_pointer_rtx
,
6469 STRUCT_VALUE_OFFSET
));
6471 /* Only follow the SPARC ABI for fixed-size structure returns.
6472 Variable size structure returns are handled per the normal
6473 procedures in GCC. This is enabled by -mstd-struct-return */
6475 && sparc_std_struct_return
6476 && TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))
6477 && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))) == INTEGER_CST
)
6479 /* We must check and adjust the return address, as it is
6480 optional as to whether the return object is really
6482 rtx ret_reg
= gen_rtx_REG (Pmode
, 31);
6483 rtx scratch
= gen_reg_rtx (SImode
);
6484 rtx endlab
= gen_label_rtx ();
6486 /* Calculate the return object size */
6487 tree size
= TYPE_SIZE_UNIT (TREE_TYPE (fndecl
));
6488 rtx size_rtx
= GEN_INT (TREE_INT_CST_LOW (size
) & 0xfff);
6489 /* Construct a temporary return value */
6491 = assign_stack_local (Pmode
, TREE_INT_CST_LOW (size
), 0);
6493 /* Implement SPARC 32-bit psABI callee return struct checking:
6495 Fetch the instruction where we will return to and see if
6496 it's an unimp instruction (the most significant 10 bits
6498 emit_move_insn (scratch
, gen_rtx_MEM (SImode
,
6499 plus_constant (ret_reg
, 8)));
6500 /* Assume the size is valid and pre-adjust */
6501 emit_insn (gen_add3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
6502 emit_cmp_and_jump_insns (scratch
, size_rtx
, EQ
, const0_rtx
, SImode
,
6504 emit_insn (gen_sub3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
6505 /* Write the address of the memory pointed to by temp_val into
6506 the memory pointed to by mem */
6507 emit_move_insn (mem
, XEXP (temp_val
, 0));
6508 emit_label (endlab
);
6515 /* Handle TARGET_FUNCTION_VALUE, and TARGET_LIBCALL_VALUE target hook.
6516 For v9, function return values are subject to the same rules as arguments,
6517 except that up to 32 bytes may be returned in registers. */
6520 sparc_function_value_1 (const_tree type
, enum machine_mode mode
,
6523 /* Beware that the two values are swapped here wrt function_arg. */
6524 int regbase
= (outgoing
6525 ? SPARC_INCOMING_INT_ARG_FIRST
6526 : SPARC_OUTGOING_INT_ARG_FIRST
);
6527 enum mode_class mclass
= GET_MODE_CLASS (mode
);
6530 /* Vector types deserve special treatment because they are polymorphic wrt
6531 their mode, depending upon whether VIS instructions are enabled. */
6532 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
6534 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6535 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
6536 || (TARGET_ARCH64
&& size
<= 32));
6538 if (mode
== BLKmode
)
6539 return function_arg_vector_value (size
,
6540 SPARC_FP_ARG_FIRST
);
6542 mclass
= MODE_FLOAT
;
6545 if (TARGET_ARCH64
&& type
)
6547 /* Structures up to 32 bytes in size are returned in registers. */
6548 if (TREE_CODE (type
) == RECORD_TYPE
)
6550 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6551 gcc_assert (size
<= 32);
6553 return function_arg_record_value (type
, mode
, 0, 1, regbase
);
6556 /* Unions up to 32 bytes in size are returned in integer registers. */
6557 else if (TREE_CODE (type
) == UNION_TYPE
)
6559 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6560 gcc_assert (size
<= 32);
6562 return function_arg_union_value (size
, mode
, 0, regbase
);
6565 /* Objects that require it are returned in FP registers. */
6566 else if (mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
6569 /* All other aggregate types are returned in an integer register in a
6570 mode corresponding to the size of the type. */
6571 else if (AGGREGATE_TYPE_P (type
))
6573 /* All other aggregate types are passed in an integer register
6574 in a mode corresponding to the size of the type. */
6575 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6576 gcc_assert (size
<= 32);
6578 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
6580 /* ??? We probably should have made the same ABI change in
6581 3.4.0 as the one we made for unions. The latter was
6582 required by the SCD though, while the former is not
6583 specified, so we favored compatibility and efficiency.
6585 Now we're stuck for aggregates larger than 16 bytes,
6586 because OImode vanished in the meantime. Let's not
6587 try to be unduly clever, and simply follow the ABI
6588 for unions in that case. */
6589 if (mode
== BLKmode
)
6590 return function_arg_union_value (size
, mode
, 0, regbase
);
6595 /* We should only have pointer and integer types at this point. This
6596 must match sparc_promote_function_mode. */
6597 else if (mclass
== MODE_INT
&& GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
6601 /* We should only have pointer and integer types at this point. This must
6602 match sparc_promote_function_mode. */
6603 else if (TARGET_ARCH32
6604 && mclass
== MODE_INT
6605 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
6608 if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
) && TARGET_FPU
)
6609 regno
= SPARC_FP_ARG_FIRST
;
6613 return gen_rtx_REG (mode
, regno
);
6616 /* Handle TARGET_FUNCTION_VALUE.
6617 On the SPARC, the value is found in the first "output" register, but the
6618 called function leaves it in the first "input" register. */
6621 sparc_function_value (const_tree valtype
,
6622 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
6625 return sparc_function_value_1 (valtype
, TYPE_MODE (valtype
), outgoing
);
6628 /* Handle TARGET_LIBCALL_VALUE. */
6631 sparc_libcall_value (enum machine_mode mode
,
6632 const_rtx fun ATTRIBUTE_UNUSED
)
6634 return sparc_function_value_1 (NULL_TREE
, mode
, false);
6637 /* Handle FUNCTION_VALUE_REGNO_P.
6638 On the SPARC, the first "output" reg is used for integer values, and the
6639 first floating point register is used for floating point values. */
6642 sparc_function_value_regno_p (const unsigned int regno
)
6644 return (regno
== 8 || regno
== 32);
6647 /* Do what is necessary for `va_start'. We look at the current function
6648 to determine if stdarg or varargs is used and return the address of
6649 the first unnamed parameter. */
6652 sparc_builtin_saveregs (void)
6654 int first_reg
= crtl
->args
.info
.words
;
6658 for (regno
= first_reg
; regno
< SPARC_INT_ARG_MAX
; regno
++)
6659 emit_move_insn (gen_rtx_MEM (word_mode
,
6660 gen_rtx_PLUS (Pmode
,
6662 GEN_INT (FIRST_PARM_OFFSET (0)
6665 gen_rtx_REG (word_mode
,
6666 SPARC_INCOMING_INT_ARG_FIRST
+ regno
));
6668 address
= gen_rtx_PLUS (Pmode
,
6670 GEN_INT (FIRST_PARM_OFFSET (0)
6671 + UNITS_PER_WORD
* first_reg
));
6676 /* Implement `va_start' for stdarg. */
6679 sparc_va_start (tree valist
, rtx nextarg
)
6681 nextarg
= expand_builtin_saveregs ();
6682 std_expand_builtin_va_start (valist
, nextarg
);
6685 /* Implement `va_arg' for stdarg. */
6688 sparc_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
6691 HOST_WIDE_INT size
, rsize
, align
;
6694 tree ptrtype
= build_pointer_type (type
);
6696 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
6699 size
= rsize
= UNITS_PER_WORD
;
6705 size
= int_size_in_bytes (type
);
6706 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
6711 /* For SPARC64, objects requiring 16-byte alignment get it. */
6712 if (TYPE_ALIGN (type
) >= 2 * (unsigned) BITS_PER_WORD
)
6713 align
= 2 * UNITS_PER_WORD
;
6715 /* SPARC-V9 ABI states that structures up to 16 bytes in size
6716 are left-justified in their slots. */
6717 if (AGGREGATE_TYPE_P (type
))
6720 size
= rsize
= UNITS_PER_WORD
;
6730 incr
= fold_build_pointer_plus_hwi (incr
, align
- 1);
6731 incr
= fold_convert (sizetype
, incr
);
6732 incr
= fold_build2 (BIT_AND_EXPR
, sizetype
, incr
,
6734 incr
= fold_convert (ptr_type_node
, incr
);
6737 gimplify_expr (&incr
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
6740 if (BYTES_BIG_ENDIAN
&& size
< rsize
)
6741 addr
= fold_build_pointer_plus_hwi (incr
, rsize
- size
);
6745 addr
= fold_convert (build_pointer_type (ptrtype
), addr
);
6746 addr
= build_va_arg_indirect_ref (addr
);
6749 /* If the address isn't aligned properly for the type, we need a temporary.
6750 FIXME: This is inefficient, usually we can do this in registers. */
6751 else if (align
== 0 && TYPE_ALIGN (type
) > BITS_PER_WORD
)
6753 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
6754 tree dest_addr
= build_fold_addr_expr (tmp
);
6755 tree copy
= build_call_expr (implicit_built_in_decls
[BUILT_IN_MEMCPY
],
6756 3, dest_addr
, addr
, size_int (rsize
));
6757 TREE_ADDRESSABLE (tmp
) = 1;
6758 gimplify_and_add (copy
, pre_p
);
6763 addr
= fold_convert (ptrtype
, addr
);
6765 incr
= fold_build_pointer_plus_hwi (incr
, rsize
);
6766 gimplify_assign (valist
, incr
, post_p
);
6768 return build_va_arg_indirect_ref (addr
);
6771 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
6772 Specify whether the vector mode is supported by the hardware. */
6775 sparc_vector_mode_supported_p (enum machine_mode mode
)
6777 return TARGET_VIS
&& VECTOR_MODE_P (mode
) ? true : false;
6780 /* Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook. */
6782 static enum machine_mode
6783 sparc_preferred_simd_mode (enum machine_mode mode
)
6801 /* Return the string to output an unconditional branch to LABEL, which is
6802 the operand number of the label.
6804 DEST is the destination insn (i.e. the label), INSN is the source. */
6807 output_ubranch (rtx dest
, int label
, rtx insn
)
6809 static char string
[64];
6810 bool v9_form
= false;
6813 if (TARGET_V9
&& INSN_ADDRESSES_SET_P ())
6815 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
6816 - INSN_ADDRESSES (INSN_UID (insn
)));
6817 /* Leave some instructions for "slop". */
6818 if (delta
>= -260000 && delta
< 260000)
6823 strcpy (string
, "ba%*,pt\t%%xcc, ");
6825 strcpy (string
, "b%*\t");
6827 p
= strchr (string
, '\0');
6838 /* Return the string to output a conditional branch to LABEL, which is
6839 the operand number of the label. OP is the conditional expression.
6840 XEXP (OP, 0) is assumed to be a condition code register (integer or
6841 floating point) and its mode specifies what kind of comparison we made.
6843 DEST is the destination insn (i.e. the label), INSN is the source.
6845 REVERSED is nonzero if we should reverse the sense of the comparison.
6847 ANNUL is nonzero if we should generate an annulling branch. */
6850 output_cbranch (rtx op
, rtx dest
, int label
, int reversed
, int annul
,
6853 static char string
[64];
6854 enum rtx_code code
= GET_CODE (op
);
6855 rtx cc_reg
= XEXP (op
, 0);
6856 enum machine_mode mode
= GET_MODE (cc_reg
);
6857 const char *labelno
, *branch
;
6858 int spaces
= 8, far
;
6861 /* v9 branches are limited to +-1MB. If it is too far away,
6874 fbne,a,pn %fcc2, .LC29
6882 far
= TARGET_V9
&& (get_attr_length (insn
) >= 3);
6885 /* Reversal of FP compares takes care -- an ordered compare
6886 becomes an unordered compare and vice versa. */
6887 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
6888 code
= reverse_condition_maybe_unordered (code
);
6890 code
= reverse_condition (code
);
6893 /* Start by writing the branch condition. */
6894 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
6945 /* ??? !v9: FP branches cannot be preceded by another floating point
6946 insn. Because there is currently no concept of pre-delay slots,
6947 we can fix this only by always emitting a nop before a floating
6952 strcpy (string
, "nop\n\t");
6953 strcat (string
, branch
);
6966 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
6978 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
6999 strcpy (string
, branch
);
7001 spaces
-= strlen (branch
);
7002 p
= strchr (string
, '\0');
7004 /* Now add the annulling, the label, and a possible noop. */
7017 if (! far
&& insn
&& INSN_ADDRESSES_SET_P ())
7019 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
7020 - INSN_ADDRESSES (INSN_UID (insn
)));
7021 /* Leave some instructions for "slop". */
7022 if (delta
< -260000 || delta
>= 260000)
7026 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7028 static char v9_fcc_labelno
[] = "%%fccX, ";
7029 /* Set the char indicating the number of the fcc reg to use. */
7030 v9_fcc_labelno
[5] = REGNO (cc_reg
) - SPARC_FIRST_V9_FCC_REG
+ '0';
7031 labelno
= v9_fcc_labelno
;
7034 gcc_assert (REGNO (cc_reg
) == SPARC_FCC_REG
);
7038 else if (mode
== CCXmode
|| mode
== CCX_NOOVmode
)
7040 labelno
= "%%xcc, ";
7045 labelno
= "%%icc, ";
7050 if (*labelno
&& insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
7053 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
7066 strcpy (p
, labelno
);
7067 p
= strchr (p
, '\0');
7070 strcpy (p
, ".+12\n\t nop\n\tb\t");
7071 /* Skip the next insn if requested or
7072 if we know that it will be a nop. */
7073 if (annul
|| ! final_sequence
)
7087 /* Emit a library call comparison between floating point X and Y.
7088 COMPARISON is the operator to compare with (EQ, NE, GT, etc).
7089 Return the new operator to be used in the comparison sequence.
7091 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
7092 values as arguments instead of the TFmode registers themselves,
7093 that's why we cannot call emit_float_lib_cmp. */
7096 sparc_emit_float_lib_cmp (rtx x
, rtx y
, enum rtx_code comparison
)
7099 rtx slot0
, slot1
, result
, tem
, tem2
, libfunc
;
7100 enum machine_mode mode
;
7101 enum rtx_code new_comparison
;
7106 qpfunc
= (TARGET_ARCH64
? "_Qp_feq" : "_Q_feq");
7110 qpfunc
= (TARGET_ARCH64
? "_Qp_fne" : "_Q_fne");
7114 qpfunc
= (TARGET_ARCH64
? "_Qp_fgt" : "_Q_fgt");
7118 qpfunc
= (TARGET_ARCH64
? "_Qp_fge" : "_Q_fge");
7122 qpfunc
= (TARGET_ARCH64
? "_Qp_flt" : "_Q_flt");
7126 qpfunc
= (TARGET_ARCH64
? "_Qp_fle" : "_Q_fle");
7137 qpfunc
= (TARGET_ARCH64
? "_Qp_cmp" : "_Q_cmp");
7150 slot0
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
7151 emit_move_insn (slot0
, x
);
7158 slot1
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
7159 emit_move_insn (slot1
, y
);
7162 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
7163 emit_library_call (libfunc
, LCT_NORMAL
,
7165 XEXP (slot0
, 0), Pmode
,
7166 XEXP (slot1
, 0), Pmode
);
7171 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
7172 emit_library_call (libfunc
, LCT_NORMAL
,
7174 x
, TFmode
, y
, TFmode
);
7179 /* Immediately move the result of the libcall into a pseudo
7180 register so reload doesn't clobber the value if it needs
7181 the return register for a spill reg. */
7182 result
= gen_reg_rtx (mode
);
7183 emit_move_insn (result
, hard_libcall_value (mode
, libfunc
));
7188 return gen_rtx_NE (VOIDmode
, result
, const0_rtx
);
7191 new_comparison
= (comparison
== UNORDERED
? EQ
: NE
);
7192 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, GEN_INT(3));
7195 new_comparison
= (comparison
== UNGT
? GT
: NE
);
7196 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, const1_rtx
);
7198 return gen_rtx_NE (VOIDmode
, result
, const2_rtx
);
7200 tem
= gen_reg_rtx (mode
);
7202 emit_insn (gen_andsi3 (tem
, result
, const1_rtx
));
7204 emit_insn (gen_anddi3 (tem
, result
, const1_rtx
));
7205 return gen_rtx_NE (VOIDmode
, tem
, const0_rtx
);
7208 tem
= gen_reg_rtx (mode
);
7210 emit_insn (gen_addsi3 (tem
, result
, const1_rtx
));
7212 emit_insn (gen_adddi3 (tem
, result
, const1_rtx
));
7213 tem2
= gen_reg_rtx (mode
);
7215 emit_insn (gen_andsi3 (tem2
, tem
, const2_rtx
));
7217 emit_insn (gen_anddi3 (tem2
, tem
, const2_rtx
));
7218 new_comparison
= (comparison
== UNEQ
? EQ
: NE
);
7219 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, tem2
, const0_rtx
);
7225 /* Generate an unsigned DImode to FP conversion. This is the same code
7226 optabs would emit if we didn't have TFmode patterns. */
7229 sparc_emit_floatunsdi (rtx
*operands
, enum machine_mode mode
)
7231 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
7234 in
= force_reg (DImode
, operands
[1]);
7235 neglab
= gen_label_rtx ();
7236 donelab
= gen_label_rtx ();
7237 i0
= gen_reg_rtx (DImode
);
7238 i1
= gen_reg_rtx (DImode
);
7239 f0
= gen_reg_rtx (mode
);
7241 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
7243 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
7244 emit_jump_insn (gen_jump (donelab
));
7247 emit_label (neglab
);
7249 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
7250 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
7251 emit_insn (gen_iordi3 (i0
, i0
, i1
));
7252 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
7253 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
7255 emit_label (donelab
);
7258 /* Generate an FP to unsigned DImode conversion. This is the same code
7259 optabs would emit if we didn't have TFmode patterns. */
7262 sparc_emit_fixunsdi (rtx
*operands
, enum machine_mode mode
)
7264 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
, limit
;
7267 in
= force_reg (mode
, operands
[1]);
7268 neglab
= gen_label_rtx ();
7269 donelab
= gen_label_rtx ();
7270 i0
= gen_reg_rtx (DImode
);
7271 i1
= gen_reg_rtx (DImode
);
7272 limit
= gen_reg_rtx (mode
);
7273 f0
= gen_reg_rtx (mode
);
7275 emit_move_insn (limit
,
7276 CONST_DOUBLE_FROM_REAL_VALUE (
7277 REAL_VALUE_ATOF ("9223372036854775808.0", mode
), mode
));
7278 emit_cmp_and_jump_insns (in
, limit
, GE
, NULL_RTX
, mode
, 0, neglab
);
7280 emit_insn (gen_rtx_SET (VOIDmode
,
7282 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, in
))));
7283 emit_jump_insn (gen_jump (donelab
));
7286 emit_label (neglab
);
7288 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_MINUS (mode
, in
, limit
)));
7289 emit_insn (gen_rtx_SET (VOIDmode
,
7291 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, f0
))));
7292 emit_insn (gen_movdi (i1
, const1_rtx
));
7293 emit_insn (gen_ashldi3 (i1
, i1
, GEN_INT (63)));
7294 emit_insn (gen_xordi3 (out
, i0
, i1
));
7296 emit_label (donelab
);
7299 /* Return the string to output a conditional branch to LABEL, testing
7300 register REG. LABEL is the operand number of the label; REG is the
7301 operand number of the reg. OP is the conditional expression. The mode
7302 of REG says what kind of comparison we made.
7304 DEST is the destination insn (i.e. the label), INSN is the source.
7306 REVERSED is nonzero if we should reverse the sense of the comparison.
7308 ANNUL is nonzero if we should generate an annulling branch. */
7311 output_v9branch (rtx op
, rtx dest
, int reg
, int label
, int reversed
,
7312 int annul
, rtx insn
)
7314 static char string
[64];
7315 enum rtx_code code
= GET_CODE (op
);
7316 enum machine_mode mode
= GET_MODE (XEXP (op
, 0));
7321 /* branch on register are limited to +-128KB. If it is too far away,
7334 brgez,a,pn %o1, .LC29
7340 ba,pt %xcc, .LC29 */
7342 far
= get_attr_length (insn
) >= 3;
7344 /* If not floating-point or if EQ or NE, we can just reverse the code. */
7346 code
= reverse_condition (code
);
7348 /* Only 64 bit versions of these instructions exist. */
7349 gcc_assert (mode
== DImode
);
7351 /* Start by writing the branch condition. */
7356 strcpy (string
, "brnz");
7360 strcpy (string
, "brz");
7364 strcpy (string
, "brgez");
7368 strcpy (string
, "brlz");
7372 strcpy (string
, "brlez");
7376 strcpy (string
, "brgz");
7383 p
= strchr (string
, '\0');
7385 /* Now add the annulling, reg, label, and nop. */
7392 if (insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
7395 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
7400 *p
= p
< string
+ 8 ? '\t' : ' ';
7408 int veryfar
= 1, delta
;
7410 if (INSN_ADDRESSES_SET_P ())
7412 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
7413 - INSN_ADDRESSES (INSN_UID (insn
)));
7414 /* Leave some instructions for "slop". */
7415 if (delta
>= -260000 && delta
< 260000)
7419 strcpy (p
, ".+12\n\t nop\n\t");
7420 /* Skip the next insn if requested or
7421 if we know that it will be a nop. */
7422 if (annul
|| ! final_sequence
)
7432 strcpy (p
, "ba,pt\t%%xcc, ");
7446 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
7447 Such instructions cannot be used in the delay slot of return insn on v9.
7448 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
7452 epilogue_renumber (register rtx
*where
, int test
)
7454 register const char *fmt
;
7456 register enum rtx_code code
;
7461 code
= GET_CODE (*where
);
7466 if (REGNO (*where
) >= 8 && REGNO (*where
) < 24) /* oX or lX */
7468 if (! test
&& REGNO (*where
) >= 24 && REGNO (*where
) < 32)
7469 *where
= gen_rtx_REG (GET_MODE (*where
), OUTGOING_REGNO (REGNO(*where
)));
7477 /* Do not replace the frame pointer with the stack pointer because
7478 it can cause the delayed instruction to load below the stack.
7479 This occurs when instructions like:
7481 (set (reg/i:SI 24 %i0)
7482 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
7483 (const_int -20 [0xffffffec])) 0))
7485 are in the return delayed slot. */
7487 if (GET_CODE (XEXP (*where
, 0)) == REG
7488 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
7489 && (GET_CODE (XEXP (*where
, 1)) != CONST_INT
7490 || INTVAL (XEXP (*where
, 1)) < SPARC_STACK_BIAS
))
7495 if (SPARC_STACK_BIAS
7496 && GET_CODE (XEXP (*where
, 0)) == REG
7497 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
)
7505 fmt
= GET_RTX_FORMAT (code
);
7507 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7512 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
7513 if (epilogue_renumber (&(XVECEXP (*where
, i
, j
)), test
))
7516 else if (fmt
[i
] == 'e'
7517 && epilogue_renumber (&(XEXP (*where
, i
)), test
))
7523 /* Leaf functions and non-leaf functions have different needs. */
7526 reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
7529 reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
7531 static const int *const reg_alloc_orders
[] = {
7532 reg_leaf_alloc_order
,
7533 reg_nonleaf_alloc_order
};
7536 order_regs_for_local_alloc (void)
7538 static int last_order_nonleaf
= 1;
7540 if (df_regs_ever_live_p (15) != last_order_nonleaf
)
7542 last_order_nonleaf
= !last_order_nonleaf
;
7543 memcpy ((char *) reg_alloc_order
,
7544 (const char *) reg_alloc_orders
[last_order_nonleaf
],
7545 FIRST_PSEUDO_REGISTER
* sizeof (int));
7549 /* Return 1 if REG and MEM are legitimate enough to allow the various
7550 mem<-->reg splits to be run. */
7553 sparc_splitdi_legitimate (rtx reg
, rtx mem
)
7555 /* Punt if we are here by mistake. */
7556 gcc_assert (reload_completed
);
7558 /* We must have an offsettable memory reference. */
7559 if (! offsettable_memref_p (mem
))
7562 /* If we have legitimate args for ldd/std, we do not want
7563 the split to happen. */
7564 if ((REGNO (reg
) % 2) == 0
7565 && mem_min_alignment (mem
, 8))
7572 /* Return 1 if x and y are some kind of REG and they refer to
7573 different hard registers. This test is guaranteed to be
7574 run after reload. */
7577 sparc_absnegfloat_split_legitimate (rtx x
, rtx y
)
7579 if (GET_CODE (x
) != REG
)
7581 if (GET_CODE (y
) != REG
)
7583 if (REGNO (x
) == REGNO (y
))
7588 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
7589 This makes them candidates for using ldd and std insns.
7591 Note reg1 and reg2 *must* be hard registers. */
7594 registers_ok_for_ldd_peep (rtx reg1
, rtx reg2
)
7596 /* We might have been passed a SUBREG. */
7597 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
7600 if (REGNO (reg1
) % 2 != 0)
7603 /* Integer ldd is deprecated in SPARC V9 */
7604 if (TARGET_V9
&& REGNO (reg1
) < 32)
7607 return (REGNO (reg1
) == REGNO (reg2
) - 1);
7610 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
7613 This can only happen when addr1 and addr2, the addresses in mem1
7614 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
7615 addr1 must also be aligned on a 64-bit boundary.
7617 Also iff dependent_reg_rtx is not null it should not be used to
7618 compute the address for mem1, i.e. we cannot optimize a sequence
7630 But, note that the transformation from:
7635 is perfectly fine. Thus, the peephole2 patterns always pass us
7636 the destination register of the first load, never the second one.
7638 For stores we don't have a similar problem, so dependent_reg_rtx is
7642 mems_ok_for_ldd_peep (rtx mem1
, rtx mem2
, rtx dependent_reg_rtx
)
7646 HOST_WIDE_INT offset1
;
7648 /* The mems cannot be volatile. */
7649 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
7652 /* MEM1 should be aligned on a 64-bit boundary. */
7653 if (MEM_ALIGN (mem1
) < 64)
7656 addr1
= XEXP (mem1
, 0);
7657 addr2
= XEXP (mem2
, 0);
7659 /* Extract a register number and offset (if used) from the first addr. */
7660 if (GET_CODE (addr1
) == PLUS
)
7662 /* If not a REG, return zero. */
7663 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
7667 reg1
= REGNO (XEXP (addr1
, 0));
7668 /* The offset must be constant! */
7669 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
7671 offset1
= INTVAL (XEXP (addr1
, 1));
7674 else if (GET_CODE (addr1
) != REG
)
7678 reg1
= REGNO (addr1
);
7679 /* This was a simple (mem (reg)) expression. Offset is 0. */
7683 /* Make sure the second address is a (mem (plus (reg) (const_int). */
7684 if (GET_CODE (addr2
) != PLUS
)
7687 if (GET_CODE (XEXP (addr2
, 0)) != REG
7688 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
7691 if (reg1
!= REGNO (XEXP (addr2
, 0)))
7694 if (dependent_reg_rtx
!= NULL_RTX
&& reg1
== REGNO (dependent_reg_rtx
))
7697 /* The first offset must be evenly divisible by 8 to ensure the
7698 address is 64 bit aligned. */
7699 if (offset1
% 8 != 0)
7702 /* The offset for the second addr must be 4 more than the first addr. */
7703 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
7706 /* All the tests passed. addr1 and addr2 are valid for ldd and std
7711 /* Return 1 if reg is a pseudo, or is the first register in
7712 a hard register pair. This makes it suitable for use in
7713 ldd and std insns. */
7716 register_ok_for_ldd (rtx reg
)
7718 /* We might have been passed a SUBREG. */
7722 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
7723 return (REGNO (reg
) % 2 == 0);
7728 /* Return 1 if OP is a memory whose address is known to be
7729 aligned to 8-byte boundary, or a pseudo during reload.
7730 This makes it suitable for use in ldd and std insns. */
7733 memory_ok_for_ldd (rtx op
)
7737 /* In 64-bit mode, we assume that the address is word-aligned. */
7738 if (TARGET_ARCH32
&& !mem_min_alignment (op
, 8))
7741 if ((reload_in_progress
|| reload_completed
)
7742 && !strict_memory_address_p (Pmode
, XEXP (op
, 0)))
7745 else if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
7747 if (!(reload_in_progress
&& reg_renumber
[REGNO (op
)] < 0))
7756 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
7759 sparc_print_operand_punct_valid_p (unsigned char code
)
7772 /* Implement TARGET_PRINT_OPERAND.
7773 Print operand X (an rtx) in assembler syntax to file FILE.
7774 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
7775 For `%' followed by punctuation, CODE is the punctuation and X is null. */
7778 sparc_print_operand (FILE *file
, rtx x
, int code
)
7783 /* Output an insn in a delay slot. */
7785 sparc_indent_opcode
= 1;
7787 fputs ("\n\t nop", file
);
7790 /* Output an annul flag if there's nothing for the delay slot and we
7791 are optimizing. This is always used with '(' below.
7792 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
7793 this is a dbx bug. So, we only do this when optimizing.
7794 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
7795 Always emit a nop in case the next instruction is a branch. */
7796 if (! final_sequence
&& (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
7800 /* Output a 'nop' if there's nothing for the delay slot and we are
7801 not optimizing. This is always used with '*' above. */
7802 if (! final_sequence
&& ! (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
7803 fputs ("\n\t nop", file
);
7804 else if (final_sequence
)
7805 sparc_indent_opcode
= 1;
7808 /* Output the right displacement from the saved PC on function return.
7809 The caller may have placed an "unimp" insn immediately after the call
7810 so we have to account for it. This insn is used in the 32-bit ABI
7811 when calling a function that returns a non zero-sized structure. The
7812 64-bit ABI doesn't have it. Be careful to have this test be the same
7813 as that for the call. The exception is when sparc_std_struct_return
7814 is enabled, the psABI is followed exactly and the adjustment is made
7815 by the code in sparc_struct_value_rtx. The call emitted is the same
7816 when sparc_std_struct_return is enabled. */
7818 && cfun
->returns_struct
7819 && !sparc_std_struct_return
7820 && DECL_SIZE (DECL_RESULT (current_function_decl
))
7821 && TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl
)))
7823 && !integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl
))))
7829 /* Output the Embedded Medium/Anywhere code model base register. */
7830 fputs (EMBMEDANY_BASE_REG
, file
);
7833 /* Print some local dynamic TLS name. */
7834 assemble_name (file
, get_some_local_dynamic_name ());
7838 /* Adjust the operand to take into account a RESTORE operation. */
7839 if (GET_CODE (x
) == CONST_INT
)
7841 else if (GET_CODE (x
) != REG
)
7842 output_operand_lossage ("invalid %%Y operand");
7843 else if (REGNO (x
) < 8)
7844 fputs (reg_names
[REGNO (x
)], file
);
7845 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
7846 fputs (reg_names
[REGNO (x
)-16], file
);
7848 output_operand_lossage ("invalid %%Y operand");
7851 /* Print out the low order register name of a register pair. */
7852 if (WORDS_BIG_ENDIAN
)
7853 fputs (reg_names
[REGNO (x
)+1], file
);
7855 fputs (reg_names
[REGNO (x
)], file
);
7858 /* Print out the high order register name of a register pair. */
7859 if (WORDS_BIG_ENDIAN
)
7860 fputs (reg_names
[REGNO (x
)], file
);
7862 fputs (reg_names
[REGNO (x
)+1], file
);
7865 /* Print out the second register name of a register pair or quad.
7866 I.e., R (%o0) => %o1. */
7867 fputs (reg_names
[REGNO (x
)+1], file
);
7870 /* Print out the third register name of a register quad.
7871 I.e., S (%o0) => %o2. */
7872 fputs (reg_names
[REGNO (x
)+2], file
);
7875 /* Print out the fourth register name of a register quad.
7876 I.e., T (%o0) => %o3. */
7877 fputs (reg_names
[REGNO (x
)+3], file
);
7880 /* Print a condition code register. */
7881 if (REGNO (x
) == SPARC_ICC_REG
)
7883 /* We don't handle CC[X]_NOOVmode because they're not supposed
7885 if (GET_MODE (x
) == CCmode
)
7886 fputs ("%icc", file
);
7887 else if (GET_MODE (x
) == CCXmode
)
7888 fputs ("%xcc", file
);
7893 /* %fccN register */
7894 fputs (reg_names
[REGNO (x
)], file
);
7897 /* Print the operand's address only. */
7898 output_address (XEXP (x
, 0));
7901 /* In this case we need a register. Use %g0 if the
7902 operand is const0_rtx. */
7904 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
7906 fputs ("%g0", file
);
7913 switch (GET_CODE (x
))
7915 case IOR
: fputs ("or", file
); break;
7916 case AND
: fputs ("and", file
); break;
7917 case XOR
: fputs ("xor", file
); break;
7918 default: output_operand_lossage ("invalid %%A operand");
7923 switch (GET_CODE (x
))
7925 case IOR
: fputs ("orn", file
); break;
7926 case AND
: fputs ("andn", file
); break;
7927 case XOR
: fputs ("xnor", file
); break;
7928 default: output_operand_lossage ("invalid %%B operand");
7932 /* These are used by the conditional move instructions. */
7936 enum rtx_code rc
= GET_CODE (x
);
7940 enum machine_mode mode
= GET_MODE (XEXP (x
, 0));
7941 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7942 rc
= reverse_condition_maybe_unordered (GET_CODE (x
));
7944 rc
= reverse_condition (GET_CODE (x
));
7948 case NE
: fputs ("ne", file
); break;
7949 case EQ
: fputs ("e", file
); break;
7950 case GE
: fputs ("ge", file
); break;
7951 case GT
: fputs ("g", file
); break;
7952 case LE
: fputs ("le", file
); break;
7953 case LT
: fputs ("l", file
); break;
7954 case GEU
: fputs ("geu", file
); break;
7955 case GTU
: fputs ("gu", file
); break;
7956 case LEU
: fputs ("leu", file
); break;
7957 case LTU
: fputs ("lu", file
); break;
7958 case LTGT
: fputs ("lg", file
); break;
7959 case UNORDERED
: fputs ("u", file
); break;
7960 case ORDERED
: fputs ("o", file
); break;
7961 case UNLT
: fputs ("ul", file
); break;
7962 case UNLE
: fputs ("ule", file
); break;
7963 case UNGT
: fputs ("ug", file
); break;
7964 case UNGE
: fputs ("uge", file
); break;
7965 case UNEQ
: fputs ("ue", file
); break;
7966 default: output_operand_lossage (code
== 'c'
7967 ? "invalid %%c operand"
7968 : "invalid %%C operand");
7973 /* These are used by the movr instruction pattern. */
7977 enum rtx_code rc
= (code
== 'd'
7978 ? reverse_condition (GET_CODE (x
))
7982 case NE
: fputs ("ne", file
); break;
7983 case EQ
: fputs ("e", file
); break;
7984 case GE
: fputs ("gez", file
); break;
7985 case LT
: fputs ("lz", file
); break;
7986 case LE
: fputs ("lez", file
); break;
7987 case GT
: fputs ("gz", file
); break;
7988 default: output_operand_lossage (code
== 'd'
7989 ? "invalid %%d operand"
7990 : "invalid %%D operand");
7997 /* Print a sign-extended character. */
7998 int i
= trunc_int_for_mode (INTVAL (x
), QImode
);
7999 fprintf (file
, "%d", i
);
8004 /* Operand must be a MEM; write its address. */
8005 if (GET_CODE (x
) != MEM
)
8006 output_operand_lossage ("invalid %%f operand");
8007 output_address (XEXP (x
, 0));
8012 /* Print a sign-extended 32-bit value. */
8014 if (GET_CODE(x
) == CONST_INT
)
8016 else if (GET_CODE(x
) == CONST_DOUBLE
)
8017 i
= CONST_DOUBLE_LOW (x
);
8020 output_operand_lossage ("invalid %%s operand");
8023 i
= trunc_int_for_mode (i
, SImode
);
8024 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, i
);
8029 /* Do nothing special. */
8033 /* Undocumented flag. */
8034 output_operand_lossage ("invalid operand output code");
8037 if (GET_CODE (x
) == REG
)
8038 fputs (reg_names
[REGNO (x
)], file
);
8039 else if (GET_CODE (x
) == MEM
)
8042 /* Poor Sun assembler doesn't understand absolute addressing. */
8043 if (CONSTANT_P (XEXP (x
, 0)))
8044 fputs ("%g0+", file
);
8045 output_address (XEXP (x
, 0));
8048 else if (GET_CODE (x
) == HIGH
)
8050 fputs ("%hi(", file
);
8051 output_addr_const (file
, XEXP (x
, 0));
8054 else if (GET_CODE (x
) == LO_SUM
)
8056 sparc_print_operand (file
, XEXP (x
, 0), 0);
8057 if (TARGET_CM_MEDMID
)
8058 fputs ("+%l44(", file
);
8060 fputs ("+%lo(", file
);
8061 output_addr_const (file
, XEXP (x
, 1));
8064 else if (GET_CODE (x
) == CONST_DOUBLE
8065 && (GET_MODE (x
) == VOIDmode
8066 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
))
8068 if (CONST_DOUBLE_HIGH (x
) == 0)
8069 fprintf (file
, "%u", (unsigned int) CONST_DOUBLE_LOW (x
));
8070 else if (CONST_DOUBLE_HIGH (x
) == -1
8071 && CONST_DOUBLE_LOW (x
) < 0)
8072 fprintf (file
, "%d", (int) CONST_DOUBLE_LOW (x
));
8074 output_operand_lossage ("long long constant not a valid immediate operand");
8076 else if (GET_CODE (x
) == CONST_DOUBLE
)
8077 output_operand_lossage ("floating point constant not a valid immediate operand");
8078 else { output_addr_const (file
, x
); }
8081 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8084 sparc_print_operand_address (FILE *file
, rtx x
)
8086 register rtx base
, index
= 0;
8088 register rtx addr
= x
;
8091 fputs (reg_names
[REGNO (addr
)], file
);
8092 else if (GET_CODE (addr
) == PLUS
)
8094 if (CONST_INT_P (XEXP (addr
, 0)))
8095 offset
= INTVAL (XEXP (addr
, 0)), base
= XEXP (addr
, 1);
8096 else if (CONST_INT_P (XEXP (addr
, 1)))
8097 offset
= INTVAL (XEXP (addr
, 1)), base
= XEXP (addr
, 0);
8099 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
8100 if (GET_CODE (base
) == LO_SUM
)
8102 gcc_assert (USE_AS_OFFSETABLE_LO10
8104 && ! TARGET_CM_MEDMID
);
8105 output_operand (XEXP (base
, 0), 0);
8106 fputs ("+%lo(", file
);
8107 output_address (XEXP (base
, 1));
8108 fprintf (file
, ")+%d", offset
);
8112 fputs (reg_names
[REGNO (base
)], file
);
8114 fprintf (file
, "%+d", offset
);
8115 else if (REG_P (index
))
8116 fprintf (file
, "+%s", reg_names
[REGNO (index
)]);
8117 else if (GET_CODE (index
) == SYMBOL_REF
8118 || GET_CODE (index
) == LABEL_REF
8119 || GET_CODE (index
) == CONST
)
8120 fputc ('+', file
), output_addr_const (file
, index
);
8121 else gcc_unreachable ();
8124 else if (GET_CODE (addr
) == MINUS
8125 && GET_CODE (XEXP (addr
, 1)) == LABEL_REF
)
8127 output_addr_const (file
, XEXP (addr
, 0));
8129 output_addr_const (file
, XEXP (addr
, 1));
8130 fputs ("-.)", file
);
8132 else if (GET_CODE (addr
) == LO_SUM
)
8134 output_operand (XEXP (addr
, 0), 0);
8135 if (TARGET_CM_MEDMID
)
8136 fputs ("+%l44(", file
);
8138 fputs ("+%lo(", file
);
8139 output_address (XEXP (addr
, 1));
8143 && GET_CODE (addr
) == CONST
8144 && GET_CODE (XEXP (addr
, 0)) == MINUS
8145 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST
8146 && GET_CODE (XEXP (XEXP (XEXP (addr
, 0), 1), 0)) == MINUS
8147 && XEXP (XEXP (XEXP (XEXP (addr
, 0), 1), 0), 1) == pc_rtx
)
8149 addr
= XEXP (addr
, 0);
8150 output_addr_const (file
, XEXP (addr
, 0));
8151 /* Group the args of the second CONST in parenthesis. */
8153 /* Skip past the second CONST--it does nothing for us. */
8154 output_addr_const (file
, XEXP (XEXP (addr
, 1), 0));
8155 /* Close the parenthesis. */
8160 output_addr_const (file
, addr
);
8164 /* Target hook for assembling integer objects. The sparc version has
8165 special handling for aligned DI-mode objects. */
8168 sparc_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
8170 /* ??? We only output .xword's for symbols and only then in environments
8171 where the assembler can handle them. */
8172 if (aligned_p
&& size
== 8
8173 && (GET_CODE (x
) != CONST_INT
&& GET_CODE (x
) != CONST_DOUBLE
))
8177 assemble_integer_with_op ("\t.xword\t", x
);
8182 assemble_aligned_integer (4, const0_rtx
);
8183 assemble_aligned_integer (4, x
);
8187 return default_assemble_integer (x
, size
, aligned_p
);
8190 /* Return the value of a code used in the .proc pseudo-op that says
8191 what kind of result this function returns. For non-C types, we pick
8192 the closest C type. */
8194 #ifndef SHORT_TYPE_SIZE
8195 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
8198 #ifndef INT_TYPE_SIZE
8199 #define INT_TYPE_SIZE BITS_PER_WORD
8202 #ifndef LONG_TYPE_SIZE
8203 #define LONG_TYPE_SIZE BITS_PER_WORD
8206 #ifndef LONG_LONG_TYPE_SIZE
8207 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
8210 #ifndef FLOAT_TYPE_SIZE
8211 #define FLOAT_TYPE_SIZE BITS_PER_WORD
8214 #ifndef DOUBLE_TYPE_SIZE
8215 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
8218 #ifndef LONG_DOUBLE_TYPE_SIZE
8219 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
8223 sparc_type_code (register tree type
)
8225 register unsigned long qualifiers
= 0;
8226 register unsigned shift
;
8228 /* Only the first 30 bits of the qualifier are valid. We must refrain from
8229 setting more, since some assemblers will give an error for this. Also,
8230 we must be careful to avoid shifts of 32 bits or more to avoid getting
8231 unpredictable results. */
8233 for (shift
= 6; shift
< 30; shift
+= 2, type
= TREE_TYPE (type
))
8235 switch (TREE_CODE (type
))
8241 qualifiers
|= (3 << shift
);
8246 qualifiers
|= (2 << shift
);
8250 case REFERENCE_TYPE
:
8252 qualifiers
|= (1 << shift
);
8256 return (qualifiers
| 8);
8259 case QUAL_UNION_TYPE
:
8260 return (qualifiers
| 9);
8263 return (qualifiers
| 10);
8266 return (qualifiers
| 16);
8269 /* If this is a range type, consider it to be the underlying
8271 if (TREE_TYPE (type
) != 0)
8274 /* Carefully distinguish all the standard types of C,
8275 without messing up if the language is not C. We do this by
8276 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
8277 look at both the names and the above fields, but that's redundant.
8278 Any type whose size is between two C types will be considered
8279 to be the wider of the two types. Also, we do not have a
8280 special code to use for "long long", so anything wider than
8281 long is treated the same. Note that we can't distinguish
8282 between "int" and "long" in this code if they are the same
8283 size, but that's fine, since neither can the assembler. */
8285 if (TYPE_PRECISION (type
) <= CHAR_TYPE_SIZE
)
8286 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 12 : 2));
8288 else if (TYPE_PRECISION (type
) <= SHORT_TYPE_SIZE
)
8289 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 13 : 3));
8291 else if (TYPE_PRECISION (type
) <= INT_TYPE_SIZE
)
8292 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 14 : 4));
8295 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 15 : 5));
8298 /* If this is a range type, consider it to be the underlying
8300 if (TREE_TYPE (type
) != 0)
8303 /* Carefully distinguish all the standard types of C,
8304 without messing up if the language is not C. */
8306 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
8307 return (qualifiers
| 6);
8310 return (qualifiers
| 7);
8312 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
8313 /* ??? We need to distinguish between double and float complex types,
8314 but I don't know how yet because I can't reach this code from
8315 existing front-ends. */
8316 return (qualifiers
| 7); /* Who knows? */
8319 case BOOLEAN_TYPE
: /* Boolean truth value type. */
8325 gcc_unreachable (); /* Not a type! */
8332 /* Nested function support. */
8334 /* Emit RTL insns to initialize the variable parts of a trampoline.
8335 FNADDR is an RTX for the address of the function's pure code.
8336 CXT is an RTX for the static chain value for the function.
8338 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
8339 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
8340 (to store insns). This is a bit excessive. Perhaps a different
8341 mechanism would be better here.
8343 Emit enough FLUSH insns to synchronize the data and instruction caches. */
8346 sparc32_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
8348 /* SPARC 32-bit trampoline:
8351 sethi %hi(static), %g2
8353 or %g2, %lo(static), %g2
8355 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
8356 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
8360 (adjust_address (m_tramp
, SImode
, 0),
8361 expand_binop (SImode
, ior_optab
,
8362 expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
, 10, 0, 1),
8363 GEN_INT (trunc_int_for_mode (0x03000000, SImode
)),
8364 NULL_RTX
, 1, OPTAB_DIRECT
));
8367 (adjust_address (m_tramp
, SImode
, 4),
8368 expand_binop (SImode
, ior_optab
,
8369 expand_shift (RSHIFT_EXPR
, SImode
, cxt
, 10, 0, 1),
8370 GEN_INT (trunc_int_for_mode (0x05000000, SImode
)),
8371 NULL_RTX
, 1, OPTAB_DIRECT
));
8374 (adjust_address (m_tramp
, SImode
, 8),
8375 expand_binop (SImode
, ior_optab
,
8376 expand_and (SImode
, fnaddr
, GEN_INT (0x3ff), NULL_RTX
),
8377 GEN_INT (trunc_int_for_mode (0x81c06000, SImode
)),
8378 NULL_RTX
, 1, OPTAB_DIRECT
));
8381 (adjust_address (m_tramp
, SImode
, 12),
8382 expand_binop (SImode
, ior_optab
,
8383 expand_and (SImode
, cxt
, GEN_INT (0x3ff), NULL_RTX
),
8384 GEN_INT (trunc_int_for_mode (0x8410a000, SImode
)),
8385 NULL_RTX
, 1, OPTAB_DIRECT
));
8387 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
8388 aligned on a 16 byte boundary so one flush clears it all. */
8389 emit_insn (gen_flush (validize_mem (adjust_address (m_tramp
, SImode
, 0))));
8390 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
8391 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
8392 && sparc_cpu
!= PROCESSOR_NIAGARA
8393 && sparc_cpu
!= PROCESSOR_NIAGARA2
8394 && sparc_cpu
!= PROCESSOR_NIAGARA3
8395 && sparc_cpu
!= PROCESSOR_NIAGARA4
)
8396 emit_insn (gen_flush (validize_mem (adjust_address (m_tramp
, SImode
, 8))));
8398 /* Call __enable_execute_stack after writing onto the stack to make sure
8399 the stack address is accessible. */
8400 #ifdef HAVE_ENABLE_EXECUTE_STACK
8401 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
8402 LCT_NORMAL
, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
8407 /* The 64-bit version is simpler because it makes more sense to load the
8408 values as "immediate" data out of the trampoline. It's also easier since
8409 we can read the PC without clobbering a register. */
8412 sparc64_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
8414 /* SPARC 64-bit trampoline:
8423 emit_move_insn (adjust_address (m_tramp
, SImode
, 0),
8424 GEN_INT (trunc_int_for_mode (0x83414000, SImode
)));
8425 emit_move_insn (adjust_address (m_tramp
, SImode
, 4),
8426 GEN_INT (trunc_int_for_mode (0xca586018, SImode
)));
8427 emit_move_insn (adjust_address (m_tramp
, SImode
, 8),
8428 GEN_INT (trunc_int_for_mode (0x81c14000, SImode
)));
8429 emit_move_insn (adjust_address (m_tramp
, SImode
, 12),
8430 GEN_INT (trunc_int_for_mode (0xca586010, SImode
)));
8431 emit_move_insn (adjust_address (m_tramp
, DImode
, 16), cxt
);
8432 emit_move_insn (adjust_address (m_tramp
, DImode
, 24), fnaddr
);
8433 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 0))));
8435 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
8436 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
8437 && sparc_cpu
!= PROCESSOR_NIAGARA
8438 && sparc_cpu
!= PROCESSOR_NIAGARA2
8439 && sparc_cpu
!= PROCESSOR_NIAGARA3
8440 && sparc_cpu
!= PROCESSOR_NIAGARA4
)
8441 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 8))));
8443 /* Call __enable_execute_stack after writing onto the stack to make sure
8444 the stack address is accessible. */
8445 #ifdef HAVE_ENABLE_EXECUTE_STACK
8446 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
8447 LCT_NORMAL
, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
8451 /* Worker for TARGET_TRAMPOLINE_INIT. */
8454 sparc_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
8456 rtx fnaddr
= force_reg (Pmode
, XEXP (DECL_RTL (fndecl
), 0));
8457 cxt
= force_reg (Pmode
, cxt
);
8459 sparc64_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
8461 sparc32_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
8464 /* Adjust the cost of a scheduling dependency. Return the new cost of
8465 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
8468 supersparc_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
8470 enum attr_type insn_type
;
8472 if (! recog_memoized (insn
))
8475 insn_type
= get_attr_type (insn
);
8477 if (REG_NOTE_KIND (link
) == 0)
8479 /* Data dependency; DEP_INSN writes a register that INSN reads some
8482 /* if a load, then the dependence must be on the memory address;
8483 add an extra "cycle". Note that the cost could be two cycles
8484 if the reg was written late in an instruction group; we ca not tell
8486 if (insn_type
== TYPE_LOAD
|| insn_type
== TYPE_FPLOAD
)
8489 /* Get the delay only if the address of the store is the dependence. */
8490 if (insn_type
== TYPE_STORE
|| insn_type
== TYPE_FPSTORE
)
8492 rtx pat
= PATTERN(insn
);
8493 rtx dep_pat
= PATTERN (dep_insn
);
8495 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
8496 return cost
; /* This should not happen! */
8498 /* The dependency between the two instructions was on the data that
8499 is being stored. Assume that this implies that the address of the
8500 store is not dependent. */
8501 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
8504 return cost
+ 3; /* An approximation. */
8507 /* A shift instruction cannot receive its data from an instruction
8508 in the same cycle; add a one cycle penalty. */
8509 if (insn_type
== TYPE_SHIFT
)
8510 return cost
+ 3; /* Split before cascade into shift. */
8514 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
8515 INSN writes some cycles later. */
8517 /* These are only significant for the fpu unit; writing a fp reg before
8518 the fpu has finished with it stalls the processor. */
8520 /* Reusing an integer register causes no problems. */
8521 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
8529 hypersparc_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
8531 enum attr_type insn_type
, dep_type
;
8532 rtx pat
= PATTERN(insn
);
8533 rtx dep_pat
= PATTERN (dep_insn
);
8535 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
8538 insn_type
= get_attr_type (insn
);
8539 dep_type
= get_attr_type (dep_insn
);
8541 switch (REG_NOTE_KIND (link
))
8544 /* Data dependency; DEP_INSN writes a register that INSN reads some
8551 /* Get the delay iff the address of the store is the dependence. */
8552 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
8555 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
8562 /* If a load, then the dependence must be on the memory address. If
8563 the addresses aren't equal, then it might be a false dependency */
8564 if (dep_type
== TYPE_STORE
|| dep_type
== TYPE_FPSTORE
)
8566 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
8567 || GET_CODE (SET_DEST (dep_pat
)) != MEM
8568 || GET_CODE (SET_SRC (pat
)) != MEM
8569 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat
), 0),
8570 XEXP (SET_SRC (pat
), 0)))
8578 /* Compare to branch latency is 0. There is no benefit from
8579 separating compare and branch. */
8580 if (dep_type
== TYPE_COMPARE
)
8582 /* Floating point compare to branch latency is less than
8583 compare to conditional move. */
8584 if (dep_type
== TYPE_FPCMP
)
8593 /* Anti-dependencies only penalize the fpu unit. */
8594 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
8606 sparc_adjust_cost(rtx insn
, rtx link
, rtx dep
, int cost
)
8610 case PROCESSOR_SUPERSPARC
:
8611 cost
= supersparc_adjust_cost (insn
, link
, dep
, cost
);
8613 case PROCESSOR_HYPERSPARC
:
8614 case PROCESSOR_SPARCLITE86X
:
8615 cost
= hypersparc_adjust_cost (insn
, link
, dep
, cost
);
8624 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
8625 int sched_verbose ATTRIBUTE_UNUSED
,
8626 int max_ready ATTRIBUTE_UNUSED
)
8630 sparc_use_sched_lookahead (void)
8632 if (sparc_cpu
== PROCESSOR_NIAGARA
8633 || sparc_cpu
== PROCESSOR_NIAGARA2
8634 || sparc_cpu
== PROCESSOR_NIAGARA3
8635 || sparc_cpu
== PROCESSOR_NIAGARA4
)
8637 if (sparc_cpu
== PROCESSOR_ULTRASPARC
8638 || sparc_cpu
== PROCESSOR_ULTRASPARC3
)
8640 if ((1 << sparc_cpu
) &
8641 ((1 << PROCESSOR_SUPERSPARC
) | (1 << PROCESSOR_HYPERSPARC
) |
8642 (1 << PROCESSOR_SPARCLITE86X
)))
8648 sparc_issue_rate (void)
8652 case PROCESSOR_NIAGARA
:
8653 case PROCESSOR_NIAGARA2
:
8654 case PROCESSOR_NIAGARA3
:
8655 case PROCESSOR_NIAGARA4
:
8659 /* Assume V9 processors are capable of at least dual-issue. */
8661 case PROCESSOR_SUPERSPARC
:
8663 case PROCESSOR_HYPERSPARC
:
8664 case PROCESSOR_SPARCLITE86X
:
8666 case PROCESSOR_ULTRASPARC
:
8667 case PROCESSOR_ULTRASPARC3
:
8673 set_extends (rtx insn
)
8675 register rtx pat
= PATTERN (insn
);
8677 switch (GET_CODE (SET_SRC (pat
)))
8679 /* Load and some shift instructions zero extend. */
8682 /* sethi clears the high bits */
8684 /* LO_SUM is used with sethi. sethi cleared the high
8685 bits and the values used with lo_sum are positive */
8687 /* Store flag stores 0 or 1 */
8697 rtx op0
= XEXP (SET_SRC (pat
), 0);
8698 rtx op1
= XEXP (SET_SRC (pat
), 1);
8699 if (GET_CODE (op1
) == CONST_INT
)
8700 return INTVAL (op1
) >= 0;
8701 if (GET_CODE (op0
) != REG
)
8703 if (sparc_check_64 (op0
, insn
) == 1)
8705 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
8710 rtx op0
= XEXP (SET_SRC (pat
), 0);
8711 rtx op1
= XEXP (SET_SRC (pat
), 1);
8712 if (GET_CODE (op0
) != REG
|| sparc_check_64 (op0
, insn
) <= 0)
8714 if (GET_CODE (op1
) == CONST_INT
)
8715 return INTVAL (op1
) >= 0;
8716 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
8719 return GET_MODE (SET_SRC (pat
)) == SImode
;
8720 /* Positive integers leave the high bits zero. */
8722 return ! (CONST_DOUBLE_LOW (SET_SRC (pat
)) & 0x80000000);
8724 return ! (INTVAL (SET_SRC (pat
)) & 0x80000000);
8727 return - (GET_MODE (SET_SRC (pat
)) == SImode
);
8729 return sparc_check_64 (SET_SRC (pat
), insn
);
8735 /* We _ought_ to have only one kind per function, but... */
8736 static GTY(()) rtx sparc_addr_diff_list
;
8737 static GTY(()) rtx sparc_addr_list
;
8740 sparc_defer_case_vector (rtx lab
, rtx vec
, int diff
)
8742 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
8744 sparc_addr_diff_list
8745 = gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_diff_list
);
8747 sparc_addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_list
);
8751 sparc_output_addr_vec (rtx vec
)
8753 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
8754 int idx
, vlen
= XVECLEN (body
, 0);
8756 #ifdef ASM_OUTPUT_ADDR_VEC_START
8757 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
8760 #ifdef ASM_OUTPUT_CASE_LABEL
8761 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
8764 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
8767 for (idx
= 0; idx
< vlen
; idx
++)
8769 ASM_OUTPUT_ADDR_VEC_ELT
8770 (asm_out_file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
8773 #ifdef ASM_OUTPUT_ADDR_VEC_END
8774 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
8779 sparc_output_addr_diff_vec (rtx vec
)
8781 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
8782 rtx base
= XEXP (XEXP (body
, 0), 0);
8783 int idx
, vlen
= XVECLEN (body
, 1);
8785 #ifdef ASM_OUTPUT_ADDR_VEC_START
8786 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
8789 #ifdef ASM_OUTPUT_CASE_LABEL
8790 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
8793 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
8796 for (idx
= 0; idx
< vlen
; idx
++)
8798 ASM_OUTPUT_ADDR_DIFF_ELT
8801 CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 1, idx
), 0)),
8802 CODE_LABEL_NUMBER (base
));
8805 #ifdef ASM_OUTPUT_ADDR_VEC_END
8806 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
8811 sparc_output_deferred_case_vectors (void)
8816 if (sparc_addr_list
== NULL_RTX
8817 && sparc_addr_diff_list
== NULL_RTX
)
8820 /* Align to cache line in the function's code section. */
8821 switch_to_section (current_function_section ());
8823 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
8825 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
8827 for (t
= sparc_addr_list
; t
; t
= XEXP (t
, 1))
8828 sparc_output_addr_vec (XEXP (t
, 0));
8829 for (t
= sparc_addr_diff_list
; t
; t
= XEXP (t
, 1))
8830 sparc_output_addr_diff_vec (XEXP (t
, 0));
8832 sparc_addr_list
= sparc_addr_diff_list
= NULL_RTX
;
8835 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
8836 unknown. Return 1 if the high bits are zero, -1 if the register is
8839 sparc_check_64 (rtx x
, rtx insn
)
8841 /* If a register is set only once it is safe to ignore insns this
8842 code does not know how to handle. The loop will either recognize
8843 the single set and return the correct value or fail to recognize
8848 gcc_assert (GET_CODE (x
) == REG
);
8850 if (GET_MODE (x
) == DImode
)
8851 y
= gen_rtx_REG (SImode
, REGNO (x
) + WORDS_BIG_ENDIAN
);
8853 if (flag_expensive_optimizations
8854 && df
&& DF_REG_DEF_COUNT (REGNO (y
)) == 1)
8860 insn
= get_last_insn_anywhere ();
8865 while ((insn
= PREV_INSN (insn
)))
8867 switch (GET_CODE (insn
))
8880 rtx pat
= PATTERN (insn
);
8881 if (GET_CODE (pat
) != SET
)
8883 if (rtx_equal_p (x
, SET_DEST (pat
)))
8884 return set_extends (insn
);
8885 if (y
&& rtx_equal_p (y
, SET_DEST (pat
)))
8886 return set_extends (insn
);
8887 if (reg_overlap_mentioned_p (SET_DEST (pat
), y
))
8895 /* Returns assembly code to perform a DImode shift using
8896 a 64-bit global or out register on SPARC-V8+. */
8898 output_v8plus_shift (rtx
*operands
, rtx insn
, const char *opcode
)
8900 static char asm_code
[60];
8902 /* The scratch register is only required when the destination
8903 register is not a 64-bit global or out register. */
8904 if (which_alternative
!= 2)
8905 operands
[3] = operands
[0];
8907 /* We can only shift by constants <= 63. */
8908 if (GET_CODE (operands
[2]) == CONST_INT
)
8909 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0x3f);
8911 if (GET_CODE (operands
[1]) == CONST_INT
)
8913 output_asm_insn ("mov\t%1, %3", operands
);
8917 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
8918 if (sparc_check_64 (operands
[1], insn
) <= 0)
8919 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
8920 output_asm_insn ("or\t%L1, %3, %3", operands
);
8923 strcpy(asm_code
, opcode
);
8925 if (which_alternative
!= 2)
8926 return strcat (asm_code
, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
8928 return strcat (asm_code
, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
8931 /* Output rtl to increment the profiler label LABELNO
8932 for profiling a function entry. */
8935 sparc_profile_hook (int labelno
)
8940 fun
= gen_rtx_SYMBOL_REF (Pmode
, MCOUNT_FUNCTION
);
8941 if (NO_PROFILE_COUNTERS
)
8943 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 0);
8947 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
8948 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
8949 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 1, lab
, Pmode
);
8953 #ifdef TARGET_SOLARIS
8954 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
8957 sparc_solaris_elf_asm_named_section (const char *name
, unsigned int flags
,
8958 tree decl ATTRIBUTE_UNUSED
)
8960 if (HAVE_COMDAT_GROUP
&& flags
& SECTION_LINKONCE
)
8962 solaris_elf_asm_comdat_section (name
, flags
, decl
);
8966 fprintf (asm_out_file
, "\t.section\t\"%s\"", name
);
8968 if (!(flags
& SECTION_DEBUG
))
8969 fputs (",#alloc", asm_out_file
);
8970 if (flags
& SECTION_WRITE
)
8971 fputs (",#write", asm_out_file
);
8972 if (flags
& SECTION_TLS
)
8973 fputs (",#tls", asm_out_file
);
8974 if (flags
& SECTION_CODE
)
8975 fputs (",#execinstr", asm_out_file
);
8977 /* ??? Handle SECTION_BSS. */
8979 fputc ('\n', asm_out_file
);
8981 #endif /* TARGET_SOLARIS */
8983 /* We do not allow indirect calls to be optimized into sibling calls.
8985 We cannot use sibling calls when delayed branches are disabled
8986 because they will likely require the call delay slot to be filled.
8988 Also, on SPARC 32-bit we cannot emit a sibling call when the
8989 current function returns a structure. This is because the "unimp
8990 after call" convention would cause the callee to return to the
8991 wrong place. The generic code already disallows cases where the
8992 function being called returns a structure.
8994 It may seem strange how this last case could occur. Usually there
8995 is code after the call which jumps to epilogue code which dumps the
8996 return value into the struct return area. That ought to invalidate
8997 the sibling call right? Well, in the C++ case we can end up passing
8998 the pointer to the struct return area to a constructor (which returns
8999 void) and then nothing else happens. Such a sibling call would look
9000 valid without the added check here.
9002 VxWorks PIC PLT entries require the global pointer to be initialized
9003 on entry. We therefore can't emit sibling calls to them. */
9005 sparc_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
9008 && flag_delayed_branch
9009 && (TARGET_ARCH64
|| ! cfun
->returns_struct
)
9010 && !(TARGET_VXWORKS_RTP
9012 && !targetm
.binds_local_p (decl
)));
9015 /* libfunc renaming. */
9018 sparc_init_libfuncs (void)
9022 /* Use the subroutines that Sun's library provides for integer
9023 multiply and divide. The `*' prevents an underscore from
9024 being prepended by the compiler. .umul is a little faster
9026 set_optab_libfunc (smul_optab
, SImode
, "*.umul");
9027 set_optab_libfunc (sdiv_optab
, SImode
, "*.div");
9028 set_optab_libfunc (udiv_optab
, SImode
, "*.udiv");
9029 set_optab_libfunc (smod_optab
, SImode
, "*.rem");
9030 set_optab_libfunc (umod_optab
, SImode
, "*.urem");
9032 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
9033 set_optab_libfunc (add_optab
, TFmode
, "_Q_add");
9034 set_optab_libfunc (sub_optab
, TFmode
, "_Q_sub");
9035 set_optab_libfunc (neg_optab
, TFmode
, "_Q_neg");
9036 set_optab_libfunc (smul_optab
, TFmode
, "_Q_mul");
9037 set_optab_libfunc (sdiv_optab
, TFmode
, "_Q_div");
9039 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
9040 is because with soft-float, the SFmode and DFmode sqrt
9041 instructions will be absent, and the compiler will notice and
9042 try to use the TFmode sqrt instruction for calls to the
9043 builtin function sqrt, but this fails. */
9045 set_optab_libfunc (sqrt_optab
, TFmode
, "_Q_sqrt");
9047 set_optab_libfunc (eq_optab
, TFmode
, "_Q_feq");
9048 set_optab_libfunc (ne_optab
, TFmode
, "_Q_fne");
9049 set_optab_libfunc (gt_optab
, TFmode
, "_Q_fgt");
9050 set_optab_libfunc (ge_optab
, TFmode
, "_Q_fge");
9051 set_optab_libfunc (lt_optab
, TFmode
, "_Q_flt");
9052 set_optab_libfunc (le_optab
, TFmode
, "_Q_fle");
9054 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_Q_stoq");
9055 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_Q_dtoq");
9056 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_Q_qtos");
9057 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_Q_qtod");
9059 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_Q_qtoi");
9060 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_Q_qtou");
9061 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_Q_itoq");
9062 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_Q_utoq");
9064 if (DITF_CONVERSION_LIBFUNCS
)
9066 set_conv_libfunc (sfix_optab
, DImode
, TFmode
, "_Q_qtoll");
9067 set_conv_libfunc (ufix_optab
, DImode
, TFmode
, "_Q_qtoull");
9068 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
, "_Q_lltoq");
9069 set_conv_libfunc (ufloat_optab
, TFmode
, DImode
, "_Q_ulltoq");
9072 if (SUN_CONVERSION_LIBFUNCS
)
9074 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
9075 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
9076 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
9077 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
9082 /* In the SPARC 64bit ABI, SImode multiply and divide functions
9083 do not exist in the library. Make sure the compiler does not
9084 emit calls to them by accident. (It should always use the
9085 hardware instructions.) */
9086 set_optab_libfunc (smul_optab
, SImode
, 0);
9087 set_optab_libfunc (sdiv_optab
, SImode
, 0);
9088 set_optab_libfunc (udiv_optab
, SImode
, 0);
9089 set_optab_libfunc (smod_optab
, SImode
, 0);
9090 set_optab_libfunc (umod_optab
, SImode
, 0);
9092 if (SUN_INTEGER_MULTIPLY_64
)
9094 set_optab_libfunc (smul_optab
, DImode
, "__mul64");
9095 set_optab_libfunc (sdiv_optab
, DImode
, "__div64");
9096 set_optab_libfunc (udiv_optab
, DImode
, "__udiv64");
9097 set_optab_libfunc (smod_optab
, DImode
, "__rem64");
9098 set_optab_libfunc (umod_optab
, DImode
, "__urem64");
9101 if (SUN_CONVERSION_LIBFUNCS
)
9103 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftol");
9104 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoul");
9105 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtol");
9106 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoul");
9111 static tree
def_builtin(const char *name
, int code
, tree type
)
9113 return add_builtin_function(name
, type
, code
, BUILT_IN_MD
, NULL
,
9117 static tree
def_builtin_const(const char *name
, int code
, tree type
)
9119 tree t
= def_builtin(name
, code
, type
);
9122 TREE_READONLY (t
) = 1;
9127 /* Implement the TARGET_INIT_BUILTINS target hook.
9128 Create builtin functions for special SPARC instructions. */
9131 sparc_init_builtins (void)
9134 sparc_vis_init_builtins ();
9137 /* Create builtin functions for VIS 1.0 instructions. */
9140 sparc_vis_init_builtins (void)
9142 tree v4qi
= build_vector_type (unsigned_intQI_type_node
, 4);
9143 tree v8qi
= build_vector_type (unsigned_intQI_type_node
, 8);
9144 tree v4hi
= build_vector_type (intHI_type_node
, 4);
9145 tree v2hi
= build_vector_type (intHI_type_node
, 2);
9146 tree v2si
= build_vector_type (intSI_type_node
, 2);
9148 tree v4qi_ftype_v4hi
= build_function_type_list (v4qi
, v4hi
, 0);
9149 tree v8qi_ftype_v2si_v8qi
= build_function_type_list (v8qi
, v2si
, v8qi
, 0);
9150 tree v2hi_ftype_v2si
= build_function_type_list (v2hi
, v2si
, 0);
9151 tree v4hi_ftype_v4qi
= build_function_type_list (v4hi
, v4qi
, 0);
9152 tree v8qi_ftype_v4qi_v4qi
= build_function_type_list (v8qi
, v4qi
, v4qi
, 0);
9153 tree v4hi_ftype_v4qi_v4hi
= build_function_type_list (v4hi
, v4qi
, v4hi
, 0);
9154 tree v4hi_ftype_v4qi_v2hi
= build_function_type_list (v4hi
, v4qi
, v2hi
, 0);
9155 tree v2si_ftype_v4qi_v2hi
= build_function_type_list (v2si
, v4qi
, v2hi
, 0);
9156 tree v4hi_ftype_v8qi_v4hi
= build_function_type_list (v4hi
, v8qi
, v4hi
, 0);
9157 tree v4hi_ftype_v4hi_v4hi
= build_function_type_list (v4hi
, v4hi
, v4hi
, 0);
9158 tree v2si_ftype_v2si_v2si
= build_function_type_list (v2si
, v2si
, v2si
, 0);
9159 tree v8qi_ftype_v8qi_v8qi
= build_function_type_list (v8qi
, v8qi
, v8qi
, 0);
9160 tree di_ftype_v8qi_v8qi_di
= build_function_type_list (intDI_type_node
,
9162 intDI_type_node
, 0);
9163 tree di_ftype_di_di
= build_function_type_list (intDI_type_node
,
9165 intDI_type_node
, 0);
9166 tree ptr_ftype_ptr_si
= build_function_type_list (ptr_type_node
,
9168 intSI_type_node
, 0);
9169 tree ptr_ftype_ptr_di
= build_function_type_list (ptr_type_node
,
9171 intDI_type_node
, 0);
9172 tree si_ftype_ptr_ptr
= build_function_type_list (intSI_type_node
,
9175 tree si_ftype_v4hi_v4hi
= build_function_type_list (intSI_type_node
,
9177 tree si_ftype_v2si_v2si
= build_function_type_list (intSI_type_node
,
9179 tree void_ftype_di
= build_function_type_list (void_type_node
,
9180 intDI_type_node
, 0);
9181 tree di_ftype_void
= build_function_type_list (intDI_type_node
,
9184 /* Packing and expanding vectors. */
9185 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis
,
9187 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis
,
9188 v8qi_ftype_v2si_v8qi
);
9189 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis
,
9191 def_builtin_const ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis
,
9193 def_builtin_const ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis
,
9194 v8qi_ftype_v4qi_v4qi
);
9196 /* Multiplications. */
9197 def_builtin_const ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis
,
9198 v4hi_ftype_v4qi_v4hi
);
9199 def_builtin_const ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis
,
9200 v4hi_ftype_v4qi_v2hi
);
9201 def_builtin_const ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis
,
9202 v4hi_ftype_v4qi_v2hi
);
9203 def_builtin_const ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis
,
9204 v4hi_ftype_v8qi_v4hi
);
9205 def_builtin_const ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis
,
9206 v4hi_ftype_v8qi_v4hi
);
9207 def_builtin_const ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis
,
9208 v2si_ftype_v4qi_v2hi
);
9209 def_builtin_const ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis
,
9210 v2si_ftype_v4qi_v2hi
);
9212 /* Data aligning. */
9213 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis
,
9214 v4hi_ftype_v4hi_v4hi
);
9215 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis
,
9216 v8qi_ftype_v8qi_v8qi
);
9217 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis
,
9218 v2si_ftype_v2si_v2si
);
9219 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatadi_vis
,
9222 def_builtin ("__builtin_vis_write_gsr", CODE_FOR_wrgsr_vis
,
9224 def_builtin ("__builtin_vis_read_gsr", CODE_FOR_rdgsr_vis
,
9229 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis
,
9231 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrldi_vis
,
9236 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis
,
9238 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrlsi_vis
,
9242 /* Pixel distance. */
9243 def_builtin_const ("__builtin_vis_pdist", CODE_FOR_pdist_vis
,
9244 di_ftype_v8qi_v8qi_di
);
9246 /* Edge handling. */
9249 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8di_vis
,
9251 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8ldi_vis
,
9253 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16di_vis
,
9255 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16ldi_vis
,
9257 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32di_vis
,
9259 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32ldi_vis
,
9264 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8si_vis
,
9266 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8lsi_vis
,
9268 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16si_vis
,
9270 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16lsi_vis
,
9272 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32si_vis
,
9274 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32lsi_vis
,
9278 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16_vis
,
9279 si_ftype_v4hi_v4hi
);
9280 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32_vis
,
9281 si_ftype_v2si_v2si
);
9282 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16_vis
,
9283 si_ftype_v4hi_v4hi
);
9284 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32_vis
,
9285 si_ftype_v2si_v2si
);
9286 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16_vis
,
9287 si_ftype_v4hi_v4hi
);
9288 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32_vis
,
9289 si_ftype_v2si_v2si
);
9290 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16_vis
,
9291 si_ftype_v4hi_v4hi
);
9292 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32_vis
,
9293 si_ftype_v2si_v2si
);
9296 /* Handle TARGET_EXPAND_BUILTIN target hook.
9297 Expand builtin functions for sparc intrinsics. */
9300 sparc_expand_builtin (tree exp
, rtx target
,
9301 rtx subtarget ATTRIBUTE_UNUSED
,
9302 enum machine_mode tmode ATTRIBUTE_UNUSED
,
9303 int ignore ATTRIBUTE_UNUSED
)
9306 call_expr_arg_iterator iter
;
9307 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
9308 unsigned int icode
= DECL_FUNCTION_CODE (fndecl
);
9313 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
9317 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
9319 || GET_MODE (target
) != tmode
9320 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
9321 op
[0] = gen_reg_rtx (tmode
);
9325 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
9327 const struct insn_operand_data
*insn_op
;
9329 if (arg
== error_mark_node
)
9333 insn_op
= &insn_data
[icode
].operand
[arg_count
- !nonvoid
];
9334 op
[arg_count
] = expand_normal (arg
);
9336 if (! (*insn_data
[icode
].operand
[arg_count
].predicate
) (op
[arg_count
],
9338 op
[arg_count
] = copy_to_mode_reg (insn_op
->mode
, op
[arg_count
]);
9344 pat
= GEN_FCN (icode
) (op
[0]);
9348 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
9350 pat
= GEN_FCN (icode
) (op
[1]);
9353 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
9356 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
9374 sparc_vis_mul8x16 (int e8
, int e16
)
9376 return (e8
* e16
+ 128) / 256;
9379 /* Multiply the vector elements in ELTS0 to the elements in ELTS1 as specified
9380 by FNCODE. All of the elements in ELTS0 and ELTS1 lists must be integer
9381 constants. A tree list with the results of the multiplications is returned,
9382 and each element in the list is of INNER_TYPE. */
9385 sparc_handle_vis_mul8x16 (int fncode
, tree inner_type
, tree elts0
, tree elts1
)
9387 tree n_elts
= NULL_TREE
;
9392 case CODE_FOR_fmul8x16_vis
:
9393 for (; elts0
&& elts1
;
9394 elts0
= TREE_CHAIN (elts0
), elts1
= TREE_CHAIN (elts1
))
9397 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
9398 TREE_INT_CST_LOW (TREE_VALUE (elts1
)));
9399 n_elts
= tree_cons (NULL_TREE
,
9400 build_int_cst (inner_type
, val
),
9405 case CODE_FOR_fmul8x16au_vis
:
9406 scale
= TREE_INT_CST_LOW (TREE_VALUE (elts1
));
9408 for (; elts0
; elts0
= TREE_CHAIN (elts0
))
9411 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
9413 n_elts
= tree_cons (NULL_TREE
,
9414 build_int_cst (inner_type
, val
),
9419 case CODE_FOR_fmul8x16al_vis
:
9420 scale
= TREE_INT_CST_LOW (TREE_VALUE (TREE_CHAIN (elts1
)));
9422 for (; elts0
; elts0
= TREE_CHAIN (elts0
))
9425 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
9427 n_elts
= tree_cons (NULL_TREE
,
9428 build_int_cst (inner_type
, val
),
9437 return nreverse (n_elts
);
9440 /* Handle TARGET_FOLD_BUILTIN target hook.
9441 Fold builtin functions for SPARC intrinsics. If IGNORE is true the
9442 result of the function call is ignored. NULL_TREE is returned if the
9443 function could not be folded. */
9446 sparc_fold_builtin (tree fndecl
, int n_args ATTRIBUTE_UNUSED
,
9447 tree
*args
, bool ignore
)
9449 tree arg0
, arg1
, arg2
;
9450 tree rtype
= TREE_TYPE (TREE_TYPE (fndecl
));
9451 enum insn_code icode
= (enum insn_code
) DECL_FUNCTION_CODE (fndecl
);
9454 && icode
!= CODE_FOR_alignaddrsi_vis
9455 && icode
!= CODE_FOR_alignaddrdi_vis
9456 && icode
!= CODE_FOR_wrgsr_vis
)
9457 return build_zero_cst (rtype
);
9461 case CODE_FOR_fexpand_vis
:
9465 if (TREE_CODE (arg0
) == VECTOR_CST
)
9467 tree inner_type
= TREE_TYPE (rtype
);
9468 tree elts
= TREE_VECTOR_CST_ELTS (arg0
);
9469 tree n_elts
= NULL_TREE
;
9471 for (; elts
; elts
= TREE_CHAIN (elts
))
9473 unsigned int val
= TREE_INT_CST_LOW (TREE_VALUE (elts
)) << 4;
9474 n_elts
= tree_cons (NULL_TREE
,
9475 build_int_cst (inner_type
, val
),
9478 return build_vector (rtype
, nreverse (n_elts
));
9482 case CODE_FOR_fmul8x16_vis
:
9483 case CODE_FOR_fmul8x16au_vis
:
9484 case CODE_FOR_fmul8x16al_vis
:
9490 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
9492 tree inner_type
= TREE_TYPE (rtype
);
9493 tree elts0
= TREE_VECTOR_CST_ELTS (arg0
);
9494 tree elts1
= TREE_VECTOR_CST_ELTS (arg1
);
9495 tree n_elts
= sparc_handle_vis_mul8x16 (icode
, inner_type
, elts0
,
9498 return build_vector (rtype
, n_elts
);
9502 case CODE_FOR_fpmerge_vis
:
9508 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
9510 tree elts0
= TREE_VECTOR_CST_ELTS (arg0
);
9511 tree elts1
= TREE_VECTOR_CST_ELTS (arg1
);
9512 tree n_elts
= NULL_TREE
;
9514 for (; elts0
&& elts1
;
9515 elts0
= TREE_CHAIN (elts0
), elts1
= TREE_CHAIN (elts1
))
9517 n_elts
= tree_cons (NULL_TREE
, TREE_VALUE (elts0
), n_elts
);
9518 n_elts
= tree_cons (NULL_TREE
, TREE_VALUE (elts1
), n_elts
);
9521 return build_vector (rtype
, nreverse (n_elts
));
9525 case CODE_FOR_pdist_vis
:
9533 if (TREE_CODE (arg0
) == VECTOR_CST
9534 && TREE_CODE (arg1
) == VECTOR_CST
9535 && TREE_CODE (arg2
) == INTEGER_CST
)
9538 unsigned HOST_WIDE_INT low
= TREE_INT_CST_LOW (arg2
);
9539 HOST_WIDE_INT high
= TREE_INT_CST_HIGH (arg2
);
9540 tree elts0
= TREE_VECTOR_CST_ELTS (arg0
);
9541 tree elts1
= TREE_VECTOR_CST_ELTS (arg1
);
9543 for (; elts0
&& elts1
;
9544 elts0
= TREE_CHAIN (elts0
), elts1
= TREE_CHAIN (elts1
))
9546 unsigned HOST_WIDE_INT
9547 low0
= TREE_INT_CST_LOW (TREE_VALUE (elts0
)),
9548 low1
= TREE_INT_CST_LOW (TREE_VALUE (elts1
));
9549 HOST_WIDE_INT high0
= TREE_INT_CST_HIGH (TREE_VALUE (elts0
));
9550 HOST_WIDE_INT high1
= TREE_INT_CST_HIGH (TREE_VALUE (elts1
));
9552 unsigned HOST_WIDE_INT l
;
9555 overflow
|= neg_double (low1
, high1
, &l
, &h
);
9556 overflow
|= add_double (low0
, high0
, l
, h
, &l
, &h
);
9558 overflow
|= neg_double (l
, h
, &l
, &h
);
9560 overflow
|= add_double (low
, high
, l
, h
, &low
, &high
);
9563 gcc_assert (overflow
== 0);
9565 return build_int_cst_wide (rtype
, low
, high
);
9575 /* ??? This duplicates information provided to the compiler by the
9576 ??? scheduler description. Some day, teach genautomata to output
9577 ??? the latencies and then CSE will just use that. */
9580 sparc_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
9581 int *total
, bool speed ATTRIBUTE_UNUSED
)
9583 enum machine_mode mode
= GET_MODE (x
);
9584 bool float_mode_p
= FLOAT_MODE_P (mode
);
9589 if (INTVAL (x
) < 0x1000 && INTVAL (x
) >= -0x1000)
9607 if (GET_MODE (x
) == VOIDmode
9608 && ((CONST_DOUBLE_HIGH (x
) == 0
9609 && CONST_DOUBLE_LOW (x
) < 0x1000)
9610 || (CONST_DOUBLE_HIGH (x
) == -1
9611 && CONST_DOUBLE_LOW (x
) < 0
9612 && CONST_DOUBLE_LOW (x
) >= -0x1000)))
9619 /* If outer-code was a sign or zero extension, a cost
9620 of COSTS_N_INSNS (1) was already added in. This is
9621 why we are subtracting it back out. */
9622 if (outer_code
== ZERO_EXTEND
)
9624 *total
= sparc_costs
->int_zload
- COSTS_N_INSNS (1);
9626 else if (outer_code
== SIGN_EXTEND
)
9628 *total
= sparc_costs
->int_sload
- COSTS_N_INSNS (1);
9630 else if (float_mode_p
)
9632 *total
= sparc_costs
->float_load
;
9636 *total
= sparc_costs
->int_load
;
9644 *total
= sparc_costs
->float_plusminus
;
9646 *total
= COSTS_N_INSNS (1);
9653 gcc_assert (float_mode_p
);
9654 *total
= sparc_costs
->float_mul
;
9657 if (GET_CODE (sub
) == NEG
)
9658 sub
= XEXP (sub
, 0);
9659 *total
+= rtx_cost (sub
, FMA
, 0, speed
);
9662 if (GET_CODE (sub
) == NEG
)
9663 sub
= XEXP (sub
, 0);
9664 *total
+= rtx_cost (sub
, FMA
, 2, speed
);
9670 *total
= sparc_costs
->float_mul
;
9671 else if (! TARGET_HARD_MUL
)
9672 *total
= COSTS_N_INSNS (25);
9678 if (sparc_costs
->int_mul_bit_factor
)
9682 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9684 unsigned HOST_WIDE_INT value
= INTVAL (XEXP (x
, 1));
9685 for (nbits
= 0; value
!= 0; value
&= value
- 1)
9688 else if (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
9689 && GET_MODE (XEXP (x
, 1)) == VOIDmode
)
9691 rtx x1
= XEXP (x
, 1);
9692 unsigned HOST_WIDE_INT value1
= CONST_DOUBLE_LOW (x1
);
9693 unsigned HOST_WIDE_INT value2
= CONST_DOUBLE_HIGH (x1
);
9695 for (nbits
= 0; value1
!= 0; value1
&= value1
- 1)
9697 for (; value2
!= 0; value2
&= value2
- 1)
9705 bit_cost
= (nbits
- 3) / sparc_costs
->int_mul_bit_factor
;
9706 bit_cost
= COSTS_N_INSNS (bit_cost
);
9710 *total
= sparc_costs
->int_mulX
+ bit_cost
;
9712 *total
= sparc_costs
->int_mul
+ bit_cost
;
9719 *total
= COSTS_N_INSNS (1) + sparc_costs
->shift_penalty
;
9729 *total
= sparc_costs
->float_div_df
;
9731 *total
= sparc_costs
->float_div_sf
;
9736 *total
= sparc_costs
->int_divX
;
9738 *total
= sparc_costs
->int_div
;
9745 *total
= COSTS_N_INSNS (1);
9752 case UNSIGNED_FLOAT
:
9756 case FLOAT_TRUNCATE
:
9757 *total
= sparc_costs
->float_move
;
9762 *total
= sparc_costs
->float_sqrt_df
;
9764 *total
= sparc_costs
->float_sqrt_sf
;
9769 *total
= sparc_costs
->float_cmp
;
9771 *total
= COSTS_N_INSNS (1);
9776 *total
= sparc_costs
->float_cmove
;
9778 *total
= sparc_costs
->int_cmove
;
9782 /* Handle the NAND vector patterns. */
9783 if (sparc_vector_mode_supported_p (GET_MODE (x
))
9784 && GET_CODE (XEXP (x
, 0)) == NOT
9785 && GET_CODE (XEXP (x
, 1)) == NOT
)
9787 *total
= COSTS_N_INSNS (1);
9798 /* Return true if CLASS is either GENERAL_REGS or I64_REGS. */
9801 general_or_i64_p (reg_class_t rclass
)
9803 return (rclass
== GENERAL_REGS
|| rclass
== I64_REGS
);
9806 /* Implement TARGET_REGISTER_MOVE_COST. */
9809 sparc_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
9810 reg_class_t from
, reg_class_t to
)
9812 if ((FP_REG_CLASS_P (from
) && general_or_i64_p (to
))
9813 || (general_or_i64_p (from
) && FP_REG_CLASS_P (to
))
9814 || from
== FPCC_REGS
9817 if (sparc_cpu
== PROCESSOR_ULTRASPARC
9818 || sparc_cpu
== PROCESSOR_ULTRASPARC3
9819 || sparc_cpu
== PROCESSOR_NIAGARA
9820 || sparc_cpu
== PROCESSOR_NIAGARA2
9821 || sparc_cpu
== PROCESSOR_NIAGARA3
9822 || sparc_cpu
== PROCESSOR_NIAGARA4
)
9831 /* Emit the sequence of insns SEQ while preserving the registers REG and REG2.
9832 This is achieved by means of a manual dynamic stack space allocation in
9833 the current frame. We make the assumption that SEQ doesn't contain any
9834 function calls, with the possible exception of calls to the GOT helper. */
9837 emit_and_preserve (rtx seq
, rtx reg
, rtx reg2
)
9839 /* We must preserve the lowest 16 words for the register save area. */
9840 HOST_WIDE_INT offset
= 16*UNITS_PER_WORD
;
9841 /* We really need only 2 words of fresh stack space. */
9842 HOST_WIDE_INT size
= SPARC_STACK_ALIGN (offset
+ 2*UNITS_PER_WORD
);
9845 = gen_rtx_MEM (word_mode
, plus_constant (stack_pointer_rtx
,
9846 SPARC_STACK_BIAS
+ offset
));
9848 emit_insn (gen_stack_pointer_dec (GEN_INT (size
)));
9849 emit_insn (gen_rtx_SET (VOIDmode
, slot
, reg
));
9851 emit_insn (gen_rtx_SET (VOIDmode
,
9852 adjust_address (slot
, word_mode
, UNITS_PER_WORD
),
9856 emit_insn (gen_rtx_SET (VOIDmode
,
9858 adjust_address (slot
, word_mode
, UNITS_PER_WORD
)));
9859 emit_insn (gen_rtx_SET (VOIDmode
, reg
, slot
));
9860 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
9863 /* Output the assembler code for a thunk function. THUNK_DECL is the
9864 declaration for the thunk function itself, FUNCTION is the decl for
9865 the target function. DELTA is an immediate constant offset to be
9866 added to THIS. If VCALL_OFFSET is nonzero, the word at address
9867 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
9870 sparc_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
9871 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
9874 rtx this_rtx
, insn
, funexp
;
9875 unsigned int int_arg_first
;
9877 reload_completed
= 1;
9878 epilogue_completed
= 1;
9880 emit_note (NOTE_INSN_PROLOGUE_END
);
9884 sparc_leaf_function_p
= 1;
9886 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
9888 else if (flag_delayed_branch
)
9890 /* We will emit a regular sibcall below, so we need to instruct
9891 output_sibcall that we are in a leaf function. */
9892 sparc_leaf_function_p
= current_function_uses_only_leaf_regs
= 1;
9894 /* This will cause final.c to invoke leaf_renumber_regs so we
9895 must behave as if we were in a not-yet-leafified function. */
9896 int_arg_first
= SPARC_INCOMING_INT_ARG_FIRST
;
9900 /* We will emit the sibcall manually below, so we will need to
9901 manually spill non-leaf registers. */
9902 sparc_leaf_function_p
= current_function_uses_only_leaf_regs
= 0;
9904 /* We really are in a leaf function. */
9905 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
9908 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
9909 returns a structure, the structure return pointer is there instead. */
9911 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
9912 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
+ 1);
9914 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
);
9916 /* Add DELTA. When possible use a plain add, otherwise load it into
9917 a register first. */
9920 rtx delta_rtx
= GEN_INT (delta
);
9922 if (! SPARC_SIMM13_P (delta
))
9924 rtx scratch
= gen_rtx_REG (Pmode
, 1);
9925 emit_move_insn (scratch
, delta_rtx
);
9926 delta_rtx
= scratch
;
9929 /* THIS_RTX += DELTA. */
9930 emit_insn (gen_add2_insn (this_rtx
, delta_rtx
));
9933 /* Add the word at address (*THIS_RTX + VCALL_OFFSET). */
9936 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
9937 rtx scratch
= gen_rtx_REG (Pmode
, 1);
9939 gcc_assert (vcall_offset
< 0);
9941 /* SCRATCH = *THIS_RTX. */
9942 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
, this_rtx
));
9944 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
9945 may not have any available scratch register at this point. */
9946 if (SPARC_SIMM13_P (vcall_offset
))
9948 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
9949 else if (! fixed_regs
[5]
9950 /* The below sequence is made up of at least 2 insns,
9951 while the default method may need only one. */
9952 && vcall_offset
< -8192)
9954 rtx scratch2
= gen_rtx_REG (Pmode
, 5);
9955 emit_move_insn (scratch2
, vcall_offset_rtx
);
9956 vcall_offset_rtx
= scratch2
;
9960 rtx increment
= GEN_INT (-4096);
9962 /* VCALL_OFFSET is a negative number whose typical range can be
9963 estimated as -32768..0 in 32-bit mode. In almost all cases
9964 it is therefore cheaper to emit multiple add insns than
9965 spilling and loading the constant into a register (at least
9967 while (! SPARC_SIMM13_P (vcall_offset
))
9969 emit_insn (gen_add2_insn (scratch
, increment
));
9970 vcall_offset
+= 4096;
9972 vcall_offset_rtx
= GEN_INT (vcall_offset
); /* cannot be 0 */
9975 /* SCRATCH = *(*THIS_RTX + VCALL_OFFSET). */
9976 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
,
9977 gen_rtx_PLUS (Pmode
,
9979 vcall_offset_rtx
)));
9981 /* THIS_RTX += *(*THIS_RTX + VCALL_OFFSET). */
9982 emit_insn (gen_add2_insn (this_rtx
, scratch
));
9985 /* Generate a tail call to the target function. */
9986 if (! TREE_USED (function
))
9988 assemble_external (function
);
9989 TREE_USED (function
) = 1;
9991 funexp
= XEXP (DECL_RTL (function
), 0);
9993 if (flag_delayed_branch
)
9995 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
9996 insn
= emit_call_insn (gen_sibcall (funexp
));
9997 SIBLING_CALL_P (insn
) = 1;
10001 /* The hoops we have to jump through in order to generate a sibcall
10002 without using delay slots... */
10003 rtx spill_reg
, seq
, scratch
= gen_rtx_REG (Pmode
, 1);
10007 spill_reg
= gen_rtx_REG (word_mode
, 15); /* %o7 */
10009 load_got_register (); /* clobbers %o7 */
10010 scratch
= sparc_legitimize_pic_address (funexp
, scratch
);
10011 seq
= get_insns ();
10013 emit_and_preserve (seq
, spill_reg
, pic_offset_table_rtx
);
10015 else if (TARGET_ARCH32
)
10017 emit_insn (gen_rtx_SET (VOIDmode
,
10019 gen_rtx_HIGH (SImode
, funexp
)));
10020 emit_insn (gen_rtx_SET (VOIDmode
,
10022 gen_rtx_LO_SUM (SImode
, scratch
, funexp
)));
10024 else /* TARGET_ARCH64 */
10026 switch (sparc_cmodel
)
10030 /* The destination can serve as a temporary. */
10031 sparc_emit_set_symbolic_const64 (scratch
, funexp
, scratch
);
10036 /* The destination cannot serve as a temporary. */
10037 spill_reg
= gen_rtx_REG (DImode
, 15); /* %o7 */
10039 sparc_emit_set_symbolic_const64 (scratch
, funexp
, spill_reg
);
10040 seq
= get_insns ();
10042 emit_and_preserve (seq
, spill_reg
, 0);
10046 gcc_unreachable ();
10050 emit_jump_insn (gen_indirect_jump (scratch
));
10055 /* Run just enough of rest_of_compilation to get the insns emitted.
10056 There's not really enough bulk here to make other passes such as
10057 instruction scheduling worth while. Note that use_thunk calls
10058 assemble_start_function and assemble_end_function. */
10059 insn
= get_insns ();
10060 insn_locators_alloc ();
10061 shorten_branches (insn
);
10062 final_start_function (insn
, file
, 1);
10063 final (insn
, file
, 1);
10064 final_end_function ();
10066 reload_completed
= 0;
10067 epilogue_completed
= 0;
10070 /* Return true if sparc_output_mi_thunk would be able to output the
10071 assembler code for the thunk function specified by the arguments
10072 it is passed, and false otherwise. */
10074 sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED
,
10075 HOST_WIDE_INT delta ATTRIBUTE_UNUSED
,
10076 HOST_WIDE_INT vcall_offset
,
10077 const_tree function ATTRIBUTE_UNUSED
)
10079 /* Bound the loop used in the default method above. */
10080 return (vcall_offset
>= -32768 || ! fixed_regs
[5]);
10083 /* How to allocate a 'struct machine_function'. */
10085 static struct machine_function
*
10086 sparc_init_machine_status (void)
10088 return ggc_alloc_cleared_machine_function ();
10091 /* Locate some local-dynamic symbol still in use by this function
10092 so that we can print its name in local-dynamic base patterns. */
10094 static const char *
10095 get_some_local_dynamic_name (void)
10099 if (cfun
->machine
->some_ld_name
)
10100 return cfun
->machine
->some_ld_name
;
10102 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10104 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
10105 return cfun
->machine
->some_ld_name
;
10107 gcc_unreachable ();
10111 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
10116 && GET_CODE (x
) == SYMBOL_REF
10117 && SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
10119 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
10126 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
10127 We need to emit DTP-relative relocations. */
10130 sparc_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
10135 fputs ("\t.word\t%r_tls_dtpoff32(", file
);
10138 fputs ("\t.xword\t%r_tls_dtpoff64(", file
);
10141 gcc_unreachable ();
10143 output_addr_const (file
, x
);
10147 /* Do whatever processing is required at the end of a file. */
10150 sparc_file_end (void)
10152 /* If we need to emit the special GOT helper function, do so now. */
10153 if (got_helper_rtx
)
10155 const char *name
= XSTR (got_helper_rtx
, 0);
10156 const char *reg_name
= reg_names
[GLOBAL_OFFSET_TABLE_REGNUM
];
10157 #ifdef DWARF2_UNWIND_INFO
10161 if (USE_HIDDEN_LINKONCE
)
10163 tree decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
10164 get_identifier (name
),
10165 build_function_type_list (void_type_node
,
10167 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
10168 NULL_TREE
, void_type_node
);
10169 TREE_STATIC (decl
) = 1;
10170 make_decl_one_only (decl
, DECL_ASSEMBLER_NAME (decl
));
10171 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
10172 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
10173 resolve_unique_section (decl
, 0, flag_function_sections
);
10174 allocate_struct_function (decl
, true);
10175 cfun
->is_thunk
= 1;
10176 current_function_decl
= decl
;
10177 init_varasm_status ();
10178 assemble_start_function (decl
, name
);
10182 const int align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
10183 switch_to_section (text_section
);
10185 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
10186 ASM_OUTPUT_LABEL (asm_out_file
, name
);
10189 #ifdef DWARF2_UNWIND_INFO
10190 do_cfi
= dwarf2out_do_cfi_asm ();
10192 fprintf (asm_out_file
, "\t.cfi_startproc\n");
10194 if (flag_delayed_branch
)
10195 fprintf (asm_out_file
, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
10196 reg_name
, reg_name
);
10198 fprintf (asm_out_file
, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
10199 reg_name
, reg_name
);
10200 #ifdef DWARF2_UNWIND_INFO
10202 fprintf (asm_out_file
, "\t.cfi_endproc\n");
10206 if (NEED_INDICATE_EXEC_STACK
)
10207 file_end_indicate_exec_stack ();
10209 #ifdef TARGET_SOLARIS
10210 solaris_file_end ();
10214 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
10215 /* Implement TARGET_MANGLE_TYPE. */
10217 static const char *
10218 sparc_mangle_type (const_tree type
)
10221 && TYPE_MAIN_VARIANT (type
) == long_double_type_node
10222 && TARGET_LONG_DOUBLE_128
)
10225 /* For all other types, use normal C++ mangling. */
10230 /* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit
10231 compare and swap on the word containing the byte or half-word. */
10234 sparc_expand_compare_and_swap_12 (rtx result
, rtx mem
, rtx oldval
, rtx newval
)
10236 rtx addr1
= force_reg (Pmode
, XEXP (mem
, 0));
10237 rtx addr
= gen_reg_rtx (Pmode
);
10238 rtx off
= gen_reg_rtx (SImode
);
10239 rtx oldv
= gen_reg_rtx (SImode
);
10240 rtx newv
= gen_reg_rtx (SImode
);
10241 rtx oldvalue
= gen_reg_rtx (SImode
);
10242 rtx newvalue
= gen_reg_rtx (SImode
);
10243 rtx res
= gen_reg_rtx (SImode
);
10244 rtx resv
= gen_reg_rtx (SImode
);
10245 rtx memsi
, val
, mask
, end_label
, loop_label
, cc
;
10247 emit_insn (gen_rtx_SET (VOIDmode
, addr
,
10248 gen_rtx_AND (Pmode
, addr1
, GEN_INT (-4))));
10250 if (Pmode
!= SImode
)
10251 addr1
= gen_lowpart (SImode
, addr1
);
10252 emit_insn (gen_rtx_SET (VOIDmode
, off
,
10253 gen_rtx_AND (SImode
, addr1
, GEN_INT (3))));
10255 memsi
= gen_rtx_MEM (SImode
, addr
);
10256 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
10257 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
10259 val
= force_reg (SImode
, memsi
);
10261 emit_insn (gen_rtx_SET (VOIDmode
, off
,
10262 gen_rtx_XOR (SImode
, off
,
10263 GEN_INT (GET_MODE (mem
) == QImode
10266 emit_insn (gen_rtx_SET (VOIDmode
, off
,
10267 gen_rtx_ASHIFT (SImode
, off
, GEN_INT (3))));
10269 if (GET_MODE (mem
) == QImode
)
10270 mask
= force_reg (SImode
, GEN_INT (0xff));
10272 mask
= force_reg (SImode
, GEN_INT (0xffff));
10274 emit_insn (gen_rtx_SET (VOIDmode
, mask
,
10275 gen_rtx_ASHIFT (SImode
, mask
, off
)));
10277 emit_insn (gen_rtx_SET (VOIDmode
, val
,
10278 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
10281 oldval
= gen_lowpart (SImode
, oldval
);
10282 emit_insn (gen_rtx_SET (VOIDmode
, oldv
,
10283 gen_rtx_ASHIFT (SImode
, oldval
, off
)));
10285 newval
= gen_lowpart_common (SImode
, newval
);
10286 emit_insn (gen_rtx_SET (VOIDmode
, newv
,
10287 gen_rtx_ASHIFT (SImode
, newval
, off
)));
10289 emit_insn (gen_rtx_SET (VOIDmode
, oldv
,
10290 gen_rtx_AND (SImode
, oldv
, mask
)));
10292 emit_insn (gen_rtx_SET (VOIDmode
, newv
,
10293 gen_rtx_AND (SImode
, newv
, mask
)));
10295 end_label
= gen_label_rtx ();
10296 loop_label
= gen_label_rtx ();
10297 emit_label (loop_label
);
10299 emit_insn (gen_rtx_SET (VOIDmode
, oldvalue
,
10300 gen_rtx_IOR (SImode
, oldv
, val
)));
10302 emit_insn (gen_rtx_SET (VOIDmode
, newvalue
,
10303 gen_rtx_IOR (SImode
, newv
, val
)));
10305 emit_insn (gen_sync_compare_and_swapsi (res
, memsi
, oldvalue
, newvalue
));
10307 emit_cmp_and_jump_insns (res
, oldvalue
, EQ
, NULL
, SImode
, 0, end_label
);
10309 emit_insn (gen_rtx_SET (VOIDmode
, resv
,
10310 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
10313 cc
= gen_compare_reg_1 (NE
, resv
, val
);
10314 emit_insn (gen_rtx_SET (VOIDmode
, val
, resv
));
10316 /* Use cbranchcc4 to separate the compare and branch! */
10317 emit_jump_insn (gen_cbranchcc4 (gen_rtx_NE (VOIDmode
, cc
, const0_rtx
),
10318 cc
, const0_rtx
, loop_label
));
10320 emit_label (end_label
);
10322 emit_insn (gen_rtx_SET (VOIDmode
, res
,
10323 gen_rtx_AND (SImode
, res
, mask
)));
10325 emit_insn (gen_rtx_SET (VOIDmode
, res
,
10326 gen_rtx_LSHIFTRT (SImode
, res
, off
)));
10328 emit_move_insn (result
, gen_lowpart (GET_MODE (result
), res
));
10331 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
10334 sparc_frame_pointer_required (void)
10336 /* If the stack pointer is dynamically modified in the function, it cannot
10337 serve as the frame pointer. */
10338 if (cfun
->calls_alloca
)
10341 /* If the function receives nonlocal gotos, it needs to save the frame
10342 pointer in the nonlocal_goto_save_area object. */
10343 if (cfun
->has_nonlocal_label
)
10346 /* In flat mode, that's it. */
10350 /* Otherwise, the frame pointer is required if the function isn't leaf. */
10351 return !(current_function_is_leaf
&& only_leaf_regs_used ());
10354 /* The way this is structured, we can't eliminate SFP in favor of SP
10355 if the frame pointer is required: we want to use the SFP->HFP elimination
10356 in that case. But the test in update_eliminables doesn't know we are
10357 assuming below that we only do the former elimination. */
10360 sparc_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
10362 return to
== HARD_FRAME_POINTER_REGNUM
|| !sparc_frame_pointer_required ();
10365 /* Return the hard frame pointer directly to bypass the stack bias. */
10368 sparc_builtin_setjmp_frame_value (void)
10370 return hard_frame_pointer_rtx
;
10373 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
10374 they won't be allocated. */
10377 sparc_conditional_register_usage (void)
10379 if (PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
10381 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
10382 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
10384 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */
10385 /* then honor it. */
10386 if (TARGET_ARCH32
&& fixed_regs
[5])
10388 else if (TARGET_ARCH64
&& fixed_regs
[5] == 2)
10393 for (regno
= SPARC_FIRST_V9_FP_REG
;
10394 regno
<= SPARC_LAST_V9_FP_REG
;
10396 fixed_regs
[regno
] = 1;
10397 /* %fcc0 is used by v8 and v9. */
10398 for (regno
= SPARC_FIRST_V9_FCC_REG
+ 1;
10399 regno
<= SPARC_LAST_V9_FCC_REG
;
10401 fixed_regs
[regno
] = 1;
10406 for (regno
= 32; regno
< SPARC_LAST_V9_FCC_REG
; regno
++)
10407 fixed_regs
[regno
] = 1;
10409 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */
10410 /* then honor it. Likewise with g3 and g4. */
10411 if (fixed_regs
[2] == 2)
10412 fixed_regs
[2] = ! TARGET_APP_REGS
;
10413 if (fixed_regs
[3] == 2)
10414 fixed_regs
[3] = ! TARGET_APP_REGS
;
10415 if (TARGET_ARCH32
&& fixed_regs
[4] == 2)
10416 fixed_regs
[4] = ! TARGET_APP_REGS
;
10417 else if (TARGET_CM_EMBMEDANY
)
10419 else if (fixed_regs
[4] == 2)
10424 /* Disable leaf functions. */
10425 memset (sparc_leaf_regs
, 0, FIRST_PSEUDO_REGISTER
);
10426 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
10427 leaf_reg_remap
[regno
] = regno
;
10431 /* Implement TARGET_PREFERRED_RELOAD_CLASS
10433 - We can't load constants into FP registers.
10434 - We can't load FP constants into integer registers when soft-float,
10435 because there is no soft-float pattern with a r/F constraint.
10436 - We can't load FP constants into integer registers for TFmode unless
10437 it is 0.0L, because there is no movtf pattern with a r/F constraint.
10438 - Try and reload integer constants (symbolic or otherwise) back into
10439 registers directly, rather than having them dumped to memory. */
10442 sparc_preferred_reload_class (rtx x
, reg_class_t rclass
)
10444 if (CONSTANT_P (x
))
10446 if (FP_REG_CLASS_P (rclass
)
10447 || rclass
== GENERAL_OR_FP_REGS
10448 || rclass
== GENERAL_OR_EXTRA_FP_REGS
10449 || (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
&& ! TARGET_FPU
)
10450 || (GET_MODE (x
) == TFmode
&& ! const_zero_operand (x
, TFmode
)))
10453 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
)
10454 return GENERAL_REGS
;
10460 #include "gt-sparc.h"