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* config/sparc/sparc.c (mem_min_alignment): Check MEM_ALIGN.
[thirdparty/gcc.git] / gcc / config / sparc / sparc.c
1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
6 at Cygnus Support.
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
24
25 #include "config.h"
26 #include "system.h"
27 #include "coretypes.h"
28 #include "tm.h"
29 #include "tree.h"
30 #include "rtl.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "real.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "output.h"
37 #include "insn-attr.h"
38 #include "flags.h"
39 #include "function.h"
40 #include "expr.h"
41 #include "optabs.h"
42 #include "recog.h"
43 #include "toplev.h"
44 #include "ggc.h"
45 #include "tm_p.h"
46 #include "debug.h"
47 #include "target.h"
48 #include "target-def.h"
49 #include "cfglayout.h"
50 #include "tree-gimple.h"
51
52 /* Processor costs */
53 static const
54 struct processor_costs cypress_costs = {
55 COSTS_N_INSNS (2), /* int load */
56 COSTS_N_INSNS (2), /* int signed load */
57 COSTS_N_INSNS (2), /* int zeroed load */
58 COSTS_N_INSNS (2), /* float load */
59 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
60 COSTS_N_INSNS (5), /* fadd, fsub */
61 COSTS_N_INSNS (1), /* fcmp */
62 COSTS_N_INSNS (1), /* fmov, fmovr */
63 COSTS_N_INSNS (7), /* fmul */
64 COSTS_N_INSNS (37), /* fdivs */
65 COSTS_N_INSNS (37), /* fdivd */
66 COSTS_N_INSNS (63), /* fsqrts */
67 COSTS_N_INSNS (63), /* fsqrtd */
68 COSTS_N_INSNS (1), /* imul */
69 COSTS_N_INSNS (1), /* imulX */
70 0, /* imul bit factor */
71 COSTS_N_INSNS (1), /* idiv */
72 COSTS_N_INSNS (1), /* idivX */
73 COSTS_N_INSNS (1), /* movcc/movr */
74 0, /* shift penalty */
75 };
76
77 static const
78 struct processor_costs supersparc_costs = {
79 COSTS_N_INSNS (1), /* int load */
80 COSTS_N_INSNS (1), /* int signed load */
81 COSTS_N_INSNS (1), /* int zeroed load */
82 COSTS_N_INSNS (0), /* float load */
83 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
84 COSTS_N_INSNS (3), /* fadd, fsub */
85 COSTS_N_INSNS (3), /* fcmp */
86 COSTS_N_INSNS (1), /* fmov, fmovr */
87 COSTS_N_INSNS (3), /* fmul */
88 COSTS_N_INSNS (6), /* fdivs */
89 COSTS_N_INSNS (9), /* fdivd */
90 COSTS_N_INSNS (12), /* fsqrts */
91 COSTS_N_INSNS (12), /* fsqrtd */
92 COSTS_N_INSNS (4), /* imul */
93 COSTS_N_INSNS (4), /* imulX */
94 0, /* imul bit factor */
95 COSTS_N_INSNS (4), /* idiv */
96 COSTS_N_INSNS (4), /* idivX */
97 COSTS_N_INSNS (1), /* movcc/movr */
98 1, /* shift penalty */
99 };
100
101 static const
102 struct processor_costs hypersparc_costs = {
103 COSTS_N_INSNS (1), /* int load */
104 COSTS_N_INSNS (1), /* int signed load */
105 COSTS_N_INSNS (1), /* int zeroed load */
106 COSTS_N_INSNS (1), /* float load */
107 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
108 COSTS_N_INSNS (1), /* fadd, fsub */
109 COSTS_N_INSNS (1), /* fcmp */
110 COSTS_N_INSNS (1), /* fmov, fmovr */
111 COSTS_N_INSNS (1), /* fmul */
112 COSTS_N_INSNS (8), /* fdivs */
113 COSTS_N_INSNS (12), /* fdivd */
114 COSTS_N_INSNS (17), /* fsqrts */
115 COSTS_N_INSNS (17), /* fsqrtd */
116 COSTS_N_INSNS (17), /* imul */
117 COSTS_N_INSNS (17), /* imulX */
118 0, /* imul bit factor */
119 COSTS_N_INSNS (17), /* idiv */
120 COSTS_N_INSNS (17), /* idivX */
121 COSTS_N_INSNS (1), /* movcc/movr */
122 0, /* shift penalty */
123 };
124
125 static const
126 struct processor_costs sparclet_costs = {
127 COSTS_N_INSNS (3), /* int load */
128 COSTS_N_INSNS (3), /* int signed load */
129 COSTS_N_INSNS (1), /* int zeroed load */
130 COSTS_N_INSNS (1), /* float load */
131 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
132 COSTS_N_INSNS (1), /* fadd, fsub */
133 COSTS_N_INSNS (1), /* fcmp */
134 COSTS_N_INSNS (1), /* fmov, fmovr */
135 COSTS_N_INSNS (1), /* fmul */
136 COSTS_N_INSNS (1), /* fdivs */
137 COSTS_N_INSNS (1), /* fdivd */
138 COSTS_N_INSNS (1), /* fsqrts */
139 COSTS_N_INSNS (1), /* fsqrtd */
140 COSTS_N_INSNS (5), /* imul */
141 COSTS_N_INSNS (5), /* imulX */
142 0, /* imul bit factor */
143 COSTS_N_INSNS (5), /* idiv */
144 COSTS_N_INSNS (5), /* idivX */
145 COSTS_N_INSNS (1), /* movcc/movr */
146 0, /* shift penalty */
147 };
148
149 static const
150 struct processor_costs ultrasparc_costs = {
151 COSTS_N_INSNS (2), /* int load */
152 COSTS_N_INSNS (3), /* int signed load */
153 COSTS_N_INSNS (2), /* int zeroed load */
154 COSTS_N_INSNS (2), /* float load */
155 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
156 COSTS_N_INSNS (4), /* fadd, fsub */
157 COSTS_N_INSNS (1), /* fcmp */
158 COSTS_N_INSNS (2), /* fmov, fmovr */
159 COSTS_N_INSNS (4), /* fmul */
160 COSTS_N_INSNS (13), /* fdivs */
161 COSTS_N_INSNS (23), /* fdivd */
162 COSTS_N_INSNS (13), /* fsqrts */
163 COSTS_N_INSNS (23), /* fsqrtd */
164 COSTS_N_INSNS (4), /* imul */
165 COSTS_N_INSNS (4), /* imulX */
166 2, /* imul bit factor */
167 COSTS_N_INSNS (37), /* idiv */
168 COSTS_N_INSNS (68), /* idivX */
169 COSTS_N_INSNS (2), /* movcc/movr */
170 2, /* shift penalty */
171 };
172
173 static const
174 struct processor_costs ultrasparc3_costs = {
175 COSTS_N_INSNS (2), /* int load */
176 COSTS_N_INSNS (3), /* int signed load */
177 COSTS_N_INSNS (3), /* int zeroed load */
178 COSTS_N_INSNS (2), /* float load */
179 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
180 COSTS_N_INSNS (4), /* fadd, fsub */
181 COSTS_N_INSNS (5), /* fcmp */
182 COSTS_N_INSNS (3), /* fmov, fmovr */
183 COSTS_N_INSNS (4), /* fmul */
184 COSTS_N_INSNS (17), /* fdivs */
185 COSTS_N_INSNS (20), /* fdivd */
186 COSTS_N_INSNS (20), /* fsqrts */
187 COSTS_N_INSNS (29), /* fsqrtd */
188 COSTS_N_INSNS (6), /* imul */
189 COSTS_N_INSNS (6), /* imulX */
190 0, /* imul bit factor */
191 COSTS_N_INSNS (40), /* idiv */
192 COSTS_N_INSNS (71), /* idivX */
193 COSTS_N_INSNS (2), /* movcc/movr */
194 0, /* shift penalty */
195 };
196
197 const struct processor_costs *sparc_costs = &cypress_costs;
198
199 #ifdef HAVE_AS_RELAX_OPTION
200 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
201 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
202 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
203 somebody does not branch between the sethi and jmp. */
204 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
205 #else
206 #define LEAF_SIBCALL_SLOT_RESERVED_P \
207 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
208 #endif
209
210 /* Global variables for machine-dependent things. */
211
212 /* Size of frame. Need to know this to emit return insns from leaf procedures.
213 ACTUAL_FSIZE is set by sparc_compute_frame_size() which is called during the
214 reload pass. This is important as the value is later used for scheduling
215 (to see what can go in a delay slot).
216 APPARENT_FSIZE is the size of the stack less the register save area and less
217 the outgoing argument area. It is used when saving call preserved regs. */
218 static HOST_WIDE_INT apparent_fsize;
219 static HOST_WIDE_INT actual_fsize;
220
221 /* Number of live general or floating point registers needed to be
222 saved (as 4-byte quantities). */
223 static int num_gfregs;
224
225 /* The alias set for prologue/epilogue register save/restore. */
226 static GTY(()) int sparc_sr_alias_set;
227
228 /* Save the operands last given to a compare for use when we
229 generate a scc or bcc insn. */
230 rtx sparc_compare_op0, sparc_compare_op1;
231
232 /* Vector to say how input registers are mapped to output registers.
233 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
234 eliminate it. You must use -fomit-frame-pointer to get that. */
235 char leaf_reg_remap[] =
236 { 0, 1, 2, 3, 4, 5, 6, 7,
237 -1, -1, -1, -1, -1, -1, 14, -1,
238 -1, -1, -1, -1, -1, -1, -1, -1,
239 8, 9, 10, 11, 12, 13, -1, 15,
240
241 32, 33, 34, 35, 36, 37, 38, 39,
242 40, 41, 42, 43, 44, 45, 46, 47,
243 48, 49, 50, 51, 52, 53, 54, 55,
244 56, 57, 58, 59, 60, 61, 62, 63,
245 64, 65, 66, 67, 68, 69, 70, 71,
246 72, 73, 74, 75, 76, 77, 78, 79,
247 80, 81, 82, 83, 84, 85, 86, 87,
248 88, 89, 90, 91, 92, 93, 94, 95,
249 96, 97, 98, 99, 100};
250
251 /* Vector, indexed by hard register number, which contains 1
252 for a register that is allowable in a candidate for leaf
253 function treatment. */
254 char sparc_leaf_regs[] =
255 { 1, 1, 1, 1, 1, 1, 1, 1,
256 0, 0, 0, 0, 0, 0, 1, 0,
257 0, 0, 0, 0, 0, 0, 0, 0,
258 1, 1, 1, 1, 1, 1, 0, 1,
259 1, 1, 1, 1, 1, 1, 1, 1,
260 1, 1, 1, 1, 1, 1, 1, 1,
261 1, 1, 1, 1, 1, 1, 1, 1,
262 1, 1, 1, 1, 1, 1, 1, 1,
263 1, 1, 1, 1, 1, 1, 1, 1,
264 1, 1, 1, 1, 1, 1, 1, 1,
265 1, 1, 1, 1, 1, 1, 1, 1,
266 1, 1, 1, 1, 1, 1, 1, 1,
267 1, 1, 1, 1, 1};
268
269 struct machine_function GTY(())
270 {
271 /* Some local-dynamic TLS symbol name. */
272 const char *some_ld_name;
273
274 /* True if the current function is leaf and uses only leaf regs,
275 so that the SPARC leaf function optimization can be applied.
276 Private version of current_function_uses_only_leaf_regs, see
277 sparc_expand_prologue for the rationale. */
278 int leaf_function_p;
279
280 /* True if the data calculated by sparc_expand_prologue are valid. */
281 bool prologue_data_valid_p;
282 };
283
284 #define sparc_leaf_function_p cfun->machine->leaf_function_p
285 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
286
287 /* Register we pretend to think the frame pointer is allocated to.
288 Normally, this is %fp, but if we are in a leaf procedure, this
289 is %sp+"something". We record "something" separately as it may
290 be too big for reg+constant addressing. */
291 static rtx frame_base_reg;
292 static HOST_WIDE_INT frame_base_offset;
293
294 /* 1 if the next opcode is to be specially indented. */
295 int sparc_indent_opcode = 0;
296
297 static void sparc_init_modes (void);
298 static void scan_record_type (tree, int *, int *, int *);
299 static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
300 tree, int, int, int *, int *);
301
302 static int supersparc_adjust_cost (rtx, rtx, rtx, int);
303 static int hypersparc_adjust_cost (rtx, rtx, rtx, int);
304
305 static void sparc_output_addr_vec (rtx);
306 static void sparc_output_addr_diff_vec (rtx);
307 static void sparc_output_deferred_case_vectors (void);
308 static rtx sparc_builtin_saveregs (void);
309 static int epilogue_renumber (rtx *, int);
310 static bool sparc_assemble_integer (rtx, unsigned int, int);
311 static int set_extends (rtx);
312 static void load_pic_register (void);
313 static int save_or_restore_regs (int, int, rtx, int, int);
314 static void emit_save_regs (void);
315 static void emit_restore_regs (void);
316 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT);
317 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT);
318 #ifdef OBJECT_FORMAT_ELF
319 static void sparc_elf_asm_named_section (const char *, unsigned int, tree);
320 #endif
321
322 static int sparc_adjust_cost (rtx, rtx, rtx, int);
323 static int sparc_issue_rate (void);
324 static void sparc_sched_init (FILE *, int, int);
325 static int sparc_use_sched_lookahead (void);
326
327 static void emit_soft_tfmode_libcall (const char *, int, rtx *);
328 static void emit_soft_tfmode_binop (enum rtx_code, rtx *);
329 static void emit_soft_tfmode_unop (enum rtx_code, rtx *);
330 static void emit_soft_tfmode_cvt (enum rtx_code, rtx *);
331 static void emit_hard_tfmode_operation (enum rtx_code, rtx *);
332
333 static bool sparc_function_ok_for_sibcall (tree, tree);
334 static void sparc_init_libfuncs (void);
335 static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
336 HOST_WIDE_INT, tree);
337 static bool sparc_can_output_mi_thunk (tree, HOST_WIDE_INT,
338 HOST_WIDE_INT, tree);
339 static struct machine_function * sparc_init_machine_status (void);
340 static bool sparc_cannot_force_const_mem (rtx);
341 static rtx sparc_tls_get_addr (void);
342 static rtx sparc_tls_got (void);
343 static const char *get_some_local_dynamic_name (void);
344 static int get_some_local_dynamic_name_1 (rtx *, void *);
345 static bool sparc_rtx_costs (rtx, int, int, int *);
346 static bool sparc_promote_prototypes (tree);
347 static rtx sparc_struct_value_rtx (tree, int);
348 static bool sparc_return_in_memory (tree, tree);
349 static bool sparc_strict_argument_naming (CUMULATIVE_ARGS *);
350 static tree sparc_gimplify_va_arg (tree, tree, tree *, tree *);
351 static bool sparc_vector_mode_supported_p (enum machine_mode);
352 static bool sparc_pass_by_reference (CUMULATIVE_ARGS *,
353 enum machine_mode, tree, bool);
354 #ifdef SUBTARGET_ATTRIBUTE_TABLE
355 const struct attribute_spec sparc_attribute_table[];
356 #endif
357 \f
358 /* Option handling. */
359
360 /* Code model option as passed by user. */
361 const char *sparc_cmodel_string;
362 /* Parsed value. */
363 enum cmodel sparc_cmodel;
364
365 char sparc_hard_reg_printed[8];
366
367 struct sparc_cpu_select sparc_select[] =
368 {
369 /* switch name, tune arch */
370 { (char *)0, "default", 1, 1 },
371 { (char *)0, "-mcpu=", 1, 1 },
372 { (char *)0, "-mtune=", 1, 0 },
373 { 0, 0, 0, 0 }
374 };
375
376 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
377 enum processor_type sparc_cpu;
378 \f
379 /* Initialize the GCC target structure. */
380
381 /* The sparc default is to use .half rather than .short for aligned
382 HI objects. Use .word instead of .long on non-ELF systems. */
383 #undef TARGET_ASM_ALIGNED_HI_OP
384 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
385 #ifndef OBJECT_FORMAT_ELF
386 #undef TARGET_ASM_ALIGNED_SI_OP
387 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
388 #endif
389
390 #undef TARGET_ASM_UNALIGNED_HI_OP
391 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
392 #undef TARGET_ASM_UNALIGNED_SI_OP
393 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
394 #undef TARGET_ASM_UNALIGNED_DI_OP
395 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
396
397 /* The target hook has to handle DI-mode values. */
398 #undef TARGET_ASM_INTEGER
399 #define TARGET_ASM_INTEGER sparc_assemble_integer
400
401 #undef TARGET_ASM_FUNCTION_PROLOGUE
402 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
403 #undef TARGET_ASM_FUNCTION_EPILOGUE
404 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
405
406 #undef TARGET_SCHED_ADJUST_COST
407 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
408 #undef TARGET_SCHED_ISSUE_RATE
409 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
410 #undef TARGET_SCHED_INIT
411 #define TARGET_SCHED_INIT sparc_sched_init
412 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
413 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
414
415 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
416 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
417
418 #undef TARGET_INIT_LIBFUNCS
419 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
420
421 #ifdef HAVE_AS_TLS
422 #undef TARGET_HAVE_TLS
423 #define TARGET_HAVE_TLS true
424 #endif
425 #undef TARGET_CANNOT_FORCE_CONST_MEM
426 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
427
428 #undef TARGET_ASM_OUTPUT_MI_THUNK
429 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
430 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
431 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
432
433 #undef TARGET_RTX_COSTS
434 #define TARGET_RTX_COSTS sparc_rtx_costs
435 #undef TARGET_ADDRESS_COST
436 #define TARGET_ADDRESS_COST hook_int_rtx_0
437
438 /* This is only needed for TARGET_ARCH64, but since PROMOTE_FUNCTION_MODE is a
439 no-op for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime
440 test for this value. */
441 #undef TARGET_PROMOTE_FUNCTION_ARGS
442 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
443
444 /* This is only needed for TARGET_ARCH64, but since PROMOTE_FUNCTION_MODE is a
445 no-op for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime
446 test for this value. */
447 #undef TARGET_PROMOTE_FUNCTION_RETURN
448 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
449
450 #undef TARGET_PROMOTE_PROTOTYPES
451 #define TARGET_PROMOTE_PROTOTYPES sparc_promote_prototypes
452
453 #undef TARGET_STRUCT_VALUE_RTX
454 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
455 #undef TARGET_RETURN_IN_MEMORY
456 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
457 #undef TARGET_MUST_PASS_IN_STACK
458 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
459 #undef TARGET_PASS_BY_REFERENCE
460 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
461
462 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
463 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
464 #undef TARGET_STRICT_ARGUMENT_NAMING
465 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
466
467 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
468 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
469
470 #undef TARGET_VECTOR_MODE_SUPPORTED_P
471 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
472
473 #ifdef SUBTARGET_INSERT_ATTRIBUTES
474 #undef TARGET_INSERT_ATTRIBUTES
475 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
476 #endif
477
478 #ifdef SUBTARGET_ATTRIBUTE_TABLE
479 #undef TARGET_ATTRIBUTE_TABLE
480 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
481 #endif
482
483 struct gcc_target targetm = TARGET_INITIALIZER;
484 \f
485 /* Validate and override various options, and do some machine dependent
486 initialization. */
487
488 void
489 sparc_override_options (void)
490 {
491 static struct code_model {
492 const char *const name;
493 const int value;
494 } const cmodels[] = {
495 { "32", CM_32 },
496 { "medlow", CM_MEDLOW },
497 { "medmid", CM_MEDMID },
498 { "medany", CM_MEDANY },
499 { "embmedany", CM_EMBMEDANY },
500 { 0, 0 }
501 };
502 const struct code_model *cmodel;
503 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
504 static struct cpu_default {
505 const int cpu;
506 const char *const name;
507 } const cpu_default[] = {
508 /* There must be one entry here for each TARGET_CPU value. */
509 { TARGET_CPU_sparc, "cypress" },
510 { TARGET_CPU_sparclet, "tsc701" },
511 { TARGET_CPU_sparclite, "f930" },
512 { TARGET_CPU_v8, "v8" },
513 { TARGET_CPU_hypersparc, "hypersparc" },
514 { TARGET_CPU_sparclite86x, "sparclite86x" },
515 { TARGET_CPU_supersparc, "supersparc" },
516 { TARGET_CPU_v9, "v9" },
517 { TARGET_CPU_ultrasparc, "ultrasparc" },
518 { TARGET_CPU_ultrasparc3, "ultrasparc3" },
519 { 0, 0 }
520 };
521 const struct cpu_default *def;
522 /* Table of values for -m{cpu,tune}=. */
523 static struct cpu_table {
524 const char *const name;
525 const enum processor_type processor;
526 const int disable;
527 const int enable;
528 } const cpu_table[] = {
529 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
530 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
531 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
532 /* TI TMS390Z55 supersparc */
533 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
534 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
535 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
536 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
537 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
538 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
539 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
540 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
541 MASK_SPARCLITE },
542 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
543 /* TEMIC sparclet */
544 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
545 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
546 /* TI ultrasparc I, II, IIi */
547 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
548 /* Although insns using %y are deprecated, it is a clear win on current
549 ultrasparcs. */
550 |MASK_DEPRECATED_V8_INSNS},
551 /* TI ultrasparc III */
552 /* ??? Check if %y issue still holds true in ultra3. */
553 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
554 { 0, 0, 0, 0 }
555 };
556 const struct cpu_table *cpu;
557 const struct sparc_cpu_select *sel;
558 int fpu;
559
560 #ifndef SPARC_BI_ARCH
561 /* Check for unsupported architecture size. */
562 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
563 error ("%s is not supported by this configuration",
564 DEFAULT_ARCH32_P ? "-m64" : "-m32");
565 #endif
566
567 /* We force all 64bit archs to use 128 bit long double */
568 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
569 {
570 error ("-mlong-double-64 not allowed with -m64");
571 target_flags |= MASK_LONG_DOUBLE_128;
572 }
573
574 /* Code model selection. */
575 sparc_cmodel = SPARC_DEFAULT_CMODEL;
576
577 #ifdef SPARC_BI_ARCH
578 if (TARGET_ARCH32)
579 sparc_cmodel = CM_32;
580 #endif
581
582 if (sparc_cmodel_string != NULL)
583 {
584 if (TARGET_ARCH64)
585 {
586 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
587 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
588 break;
589 if (cmodel->name == NULL)
590 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
591 else
592 sparc_cmodel = cmodel->value;
593 }
594 else
595 error ("-mcmodel= is not supported on 32 bit systems");
596 }
597
598 fpu = TARGET_FPU; /* save current -mfpu status */
599
600 /* Set the default CPU. */
601 for (def = &cpu_default[0]; def->name; ++def)
602 if (def->cpu == TARGET_CPU_DEFAULT)
603 break;
604 if (! def->name)
605 abort ();
606 sparc_select[0].string = def->name;
607
608 for (sel = &sparc_select[0]; sel->name; ++sel)
609 {
610 if (sel->string)
611 {
612 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
613 if (! strcmp (sel->string, cpu->name))
614 {
615 if (sel->set_tune_p)
616 sparc_cpu = cpu->processor;
617
618 if (sel->set_arch_p)
619 {
620 target_flags &= ~cpu->disable;
621 target_flags |= cpu->enable;
622 }
623 break;
624 }
625
626 if (! cpu->name)
627 error ("bad value (%s) for %s switch", sel->string, sel->name);
628 }
629 }
630
631 /* If -mfpu or -mno-fpu was explicitly used, don't override with
632 the processor default. Clear MASK_FPU_SET to avoid confusing
633 the reverse mapping from switch values to names. */
634 if (TARGET_FPU_SET)
635 {
636 target_flags = (target_flags & ~MASK_FPU) | fpu;
637 target_flags &= ~MASK_FPU_SET;
638 }
639
640 /* Don't allow -mvis if FPU is disabled. */
641 if (! TARGET_FPU)
642 target_flags &= ~MASK_VIS;
643
644 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
645 are available.
646 -m64 also implies v9. */
647 if (TARGET_VIS || TARGET_ARCH64)
648 {
649 target_flags |= MASK_V9;
650 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
651 }
652
653 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
654 if (TARGET_V9 && TARGET_ARCH32)
655 target_flags |= MASK_DEPRECATED_V8_INSNS;
656
657 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
658 if (! TARGET_V9 || TARGET_ARCH64)
659 target_flags &= ~MASK_V8PLUS;
660
661 /* Don't use stack biasing in 32 bit mode. */
662 if (TARGET_ARCH32)
663 target_flags &= ~MASK_STACK_BIAS;
664
665 /* Supply a default value for align_functions. */
666 if (align_functions == 0
667 && (sparc_cpu == PROCESSOR_ULTRASPARC
668 || sparc_cpu == PROCESSOR_ULTRASPARC3))
669 align_functions = 32;
670
671 /* Validate PCC_STRUCT_RETURN. */
672 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
673 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
674
675 /* Only use .uaxword when compiling for a 64-bit target. */
676 if (!TARGET_ARCH64)
677 targetm.asm_out.unaligned_op.di = NULL;
678
679 /* Do various machine dependent initializations. */
680 sparc_init_modes ();
681
682 /* Acquire a unique set number for our register saves and restores. */
683 sparc_sr_alias_set = new_alias_set ();
684
685 /* Set up function hooks. */
686 init_machine_status = sparc_init_machine_status;
687
688 switch (sparc_cpu)
689 {
690 case PROCESSOR_V7:
691 case PROCESSOR_CYPRESS:
692 sparc_costs = &cypress_costs;
693 break;
694 case PROCESSOR_V8:
695 case PROCESSOR_SPARCLITE:
696 case PROCESSOR_SUPERSPARC:
697 sparc_costs = &supersparc_costs;
698 break;
699 case PROCESSOR_F930:
700 case PROCESSOR_F934:
701 case PROCESSOR_HYPERSPARC:
702 case PROCESSOR_SPARCLITE86X:
703 sparc_costs = &hypersparc_costs;
704 break;
705 case PROCESSOR_SPARCLET:
706 case PROCESSOR_TSC701:
707 sparc_costs = &sparclet_costs;
708 break;
709 case PROCESSOR_V9:
710 case PROCESSOR_ULTRASPARC:
711 sparc_costs = &ultrasparc_costs;
712 break;
713 case PROCESSOR_ULTRASPARC3:
714 sparc_costs = &ultrasparc3_costs;
715 break;
716 };
717 }
718 \f
719 #ifdef SUBTARGET_ATTRIBUTE_TABLE
720 /* Table of valid machine attributes. */
721 const struct attribute_spec sparc_attribute_table[] =
722 {
723 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
724 SUBTARGET_ATTRIBUTE_TABLE,
725 { NULL, 0, 0, false, false, false, NULL }
726 };
727 #endif
728 \f
729 /* Miscellaneous utilities. */
730
731 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
732 or branch on register contents instructions. */
733
734 int
735 v9_regcmp_p (enum rtx_code code)
736 {
737 return (code == EQ || code == NE || code == GE || code == LT
738 || code == LE || code == GT);
739 }
740
741 \f
742 /* Operand constraints. */
743
744 /* Return nonzero only if OP is a register of mode MODE,
745 or const0_rtx. */
746
747 int
748 reg_or_0_operand (rtx op, enum machine_mode mode)
749 {
750 if (register_operand (op, mode))
751 return 1;
752 if (op == const0_rtx)
753 return 1;
754 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
755 && CONST_DOUBLE_HIGH (op) == 0
756 && CONST_DOUBLE_LOW (op) == 0)
757 return 1;
758 if (fp_zero_operand (op, mode))
759 return 1;
760 return 0;
761 }
762
763 /* Return nonzero only if OP is const1_rtx. */
764
765 int
766 const1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
767 {
768 return op == const1_rtx;
769 }
770
771 /* Nonzero if OP is a floating point value with value 0.0. */
772
773 int
774 fp_zero_operand (rtx op, enum machine_mode mode)
775 {
776 enum mode_class mclass = GET_MODE_CLASS (GET_MODE (op));
777 if (mclass != MODE_FLOAT && mclass != MODE_VECTOR_INT)
778 return 0;
779 return op == CONST0_RTX (mode);
780 }
781
782 /* Nonzero if OP is a register operand in floating point register. */
783
784 int
785 fp_register_operand (rtx op, enum machine_mode mode)
786 {
787 if (! register_operand (op, mode))
788 return 0;
789 if (GET_CODE (op) == SUBREG)
790 op = SUBREG_REG (op);
791 return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op));
792 }
793
794 /* Nonzero if OP is a floating point constant which can
795 be loaded into an integer register using a single
796 sethi instruction. */
797
798 int
799 fp_sethi_p (rtx op)
800 {
801 if (GET_CODE (op) == CONST_DOUBLE)
802 {
803 REAL_VALUE_TYPE r;
804 long i;
805
806 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
807 if (REAL_VALUES_EQUAL (r, dconst0) &&
808 ! REAL_VALUE_MINUS_ZERO (r))
809 return 0;
810 REAL_VALUE_TO_TARGET_SINGLE (r, i);
811 if (SPARC_SETHI_P (i))
812 return 1;
813 }
814
815 return 0;
816 }
817
818 /* Nonzero if OP is a floating point constant which can
819 be loaded into an integer register using a single
820 mov instruction. */
821
822 int
823 fp_mov_p (rtx op)
824 {
825 if (GET_CODE (op) == CONST_DOUBLE)
826 {
827 REAL_VALUE_TYPE r;
828 long i;
829
830 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
831 if (REAL_VALUES_EQUAL (r, dconst0) &&
832 ! REAL_VALUE_MINUS_ZERO (r))
833 return 0;
834 REAL_VALUE_TO_TARGET_SINGLE (r, i);
835 if (SPARC_SIMM13_P (i))
836 return 1;
837 }
838
839 return 0;
840 }
841
842 /* Nonzero if OP is a floating point constant which can
843 be loaded into an integer register using a high/losum
844 instruction sequence. */
845
846 int
847 fp_high_losum_p (rtx op)
848 {
849 /* The constraints calling this should only be in
850 SFmode move insns, so any constant which cannot
851 be moved using a single insn will do. */
852 if (GET_CODE (op) == CONST_DOUBLE)
853 {
854 REAL_VALUE_TYPE r;
855 long i;
856
857 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
858 if (REAL_VALUES_EQUAL (r, dconst0) &&
859 ! REAL_VALUE_MINUS_ZERO (r))
860 return 0;
861 REAL_VALUE_TO_TARGET_SINGLE (r, i);
862 if (! SPARC_SETHI_P (i)
863 && ! SPARC_SIMM13_P (i))
864 return 1;
865 }
866
867 return 0;
868 }
869
870 /* Nonzero if OP is an integer register. */
871
872 int
873 intreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
874 {
875 return (register_operand (op, SImode)
876 || (TARGET_ARCH64 && register_operand (op, DImode)));
877 }
878
879 /* Nonzero if OP is a floating point condition code register. */
880
881 int
882 fcc_reg_operand (rtx op, enum machine_mode mode)
883 {
884 /* This can happen when recog is called from combine. Op may be a MEM.
885 Fail instead of calling abort in this case. */
886 if (GET_CODE (op) != REG)
887 return 0;
888
889 if (mode != VOIDmode && mode != GET_MODE (op))
890 return 0;
891 if (mode == VOIDmode
892 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
893 return 0;
894
895 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
896 if (reg_renumber == 0)
897 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
898 return REGNO_OK_FOR_CCFP_P (REGNO (op));
899 #else
900 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
901 #endif
902 }
903
904 /* Nonzero if OP is a floating point condition code fcc0 register. */
905
906 int
907 fcc0_reg_operand (rtx op, enum machine_mode mode)
908 {
909 /* This can happen when recog is called from combine. Op may be a MEM.
910 Fail instead of calling abort in this case. */
911 if (GET_CODE (op) != REG)
912 return 0;
913
914 if (mode != VOIDmode && mode != GET_MODE (op))
915 return 0;
916 if (mode == VOIDmode
917 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
918 return 0;
919
920 return REGNO (op) == SPARC_FCC_REG;
921 }
922
923 /* Nonzero if OP is an integer or floating point condition code register. */
924
925 int
926 icc_or_fcc_reg_operand (rtx op, enum machine_mode mode)
927 {
928 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
929 {
930 if (mode != VOIDmode && mode != GET_MODE (op))
931 return 0;
932 if (mode == VOIDmode
933 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
934 return 0;
935 return 1;
936 }
937
938 return fcc_reg_operand (op, mode);
939 }
940
941 /* Call insn on SPARC can take a PC-relative constant address, or any regular
942 memory address. */
943
944 int
945 call_operand (rtx op, enum machine_mode mode)
946 {
947 if (GET_CODE (op) != MEM)
948 abort ();
949 op = XEXP (op, 0);
950 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
951 }
952
953 int
954 call_operand_address (rtx op, enum machine_mode mode)
955 {
956 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
957 }
958
959 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
960 otherwise return 0. */
961
962 int
963 tls_symbolic_operand (rtx op)
964 {
965 if (GET_CODE (op) != SYMBOL_REF)
966 return 0;
967 return SYMBOL_REF_TLS_MODEL (op);
968 }
969
970 int
971 tgd_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
972 {
973 return tls_symbolic_operand (op) == TLS_MODEL_GLOBAL_DYNAMIC;
974 }
975
976 int
977 tld_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
978 {
979 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_DYNAMIC;
980 }
981
982 int
983 tie_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
984 {
985 return tls_symbolic_operand (op) == TLS_MODEL_INITIAL_EXEC;
986 }
987
988 int
989 tle_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
990 {
991 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_EXEC;
992 }
993
994 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
995 reference and a constant. */
996
997 int
998 symbolic_operand (register rtx op, enum machine_mode mode)
999 {
1000 enum machine_mode omode = GET_MODE (op);
1001
1002 if (omode != mode && omode != VOIDmode && mode != VOIDmode)
1003 return 0;
1004
1005 switch (GET_CODE (op))
1006 {
1007 case SYMBOL_REF:
1008 return !SYMBOL_REF_TLS_MODEL (op);
1009
1010 case LABEL_REF:
1011 return 1;
1012
1013 case CONST:
1014 op = XEXP (op, 0);
1015 return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1016 && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
1017 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1018 && GET_CODE (XEXP (op, 1)) == CONST_INT);
1019
1020 default:
1021 return 0;
1022 }
1023 }
1024
1025 /* Return truth value of statement that OP is a symbolic memory
1026 operand of mode MODE. */
1027
1028 int
1029 symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1030 {
1031 if (GET_CODE (op) == SUBREG)
1032 op = SUBREG_REG (op);
1033 if (GET_CODE (op) != MEM)
1034 return 0;
1035 op = XEXP (op, 0);
1036 return ((GET_CODE (op) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (op))
1037 || GET_CODE (op) == CONST || GET_CODE (op) == HIGH
1038 || GET_CODE (op) == LABEL_REF);
1039 }
1040
1041 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
1042
1043 int
1044 label_ref_operand (rtx op, enum machine_mode mode)
1045 {
1046 if (GET_CODE (op) != LABEL_REF)
1047 return 0;
1048 if (GET_MODE (op) != mode)
1049 return 0;
1050 return 1;
1051 }
1052
1053 /* Return 1 if the operand is an argument used in generating pic references
1054 in either the medium/low or medium/anywhere code models of sparc64. */
1055
1056 int
1057 sp64_medium_pic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1058 {
1059 /* Check for (const (minus (symbol_ref:GOT)
1060 (const (minus (label) (pc))))). */
1061 if (GET_CODE (op) != CONST)
1062 return 0;
1063 op = XEXP (op, 0);
1064 if (GET_CODE (op) != MINUS)
1065 return 0;
1066 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
1067 return 0;
1068 /* ??? Ensure symbol is GOT. */
1069 if (GET_CODE (XEXP (op, 1)) != CONST)
1070 return 0;
1071 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
1072 return 0;
1073 return 1;
1074 }
1075
1076 /* Return 1 if the operand is a data segment reference. This includes
1077 the readonly data segment, or in other words anything but the text segment.
1078 This is needed in the medium/anywhere code model on v9. These values
1079 are accessed with EMBMEDANY_BASE_REG. */
1080
1081 int
1082 data_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1083 {
1084 switch (GET_CODE (op))
1085 {
1086 case SYMBOL_REF :
1087 return ! SYMBOL_REF_FUNCTION_P (op);
1088 case PLUS :
1089 /* Assume canonical format of symbol + constant.
1090 Fall through. */
1091 case CONST :
1092 return data_segment_operand (XEXP (op, 0), VOIDmode);
1093 default :
1094 return 0;
1095 }
1096 }
1097
1098 /* Return 1 if the operand is a text segment reference.
1099 This is needed in the medium/anywhere code model on v9. */
1100
1101 int
1102 text_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1103 {
1104 switch (GET_CODE (op))
1105 {
1106 case LABEL_REF :
1107 return 1;
1108 case SYMBOL_REF :
1109 return SYMBOL_REF_FUNCTION_P (op);
1110 case PLUS :
1111 /* Assume canonical format of symbol + constant.
1112 Fall through. */
1113 case CONST :
1114 return text_segment_operand (XEXP (op, 0), VOIDmode);
1115 default :
1116 return 0;
1117 }
1118 }
1119
1120 /* Return 1 if the operand is either a register or a memory operand that is
1121 not symbolic. */
1122
1123 int
1124 reg_or_nonsymb_mem_operand (register rtx op, enum machine_mode mode)
1125 {
1126 if (register_operand (op, mode))
1127 return 1;
1128
1129 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
1130 return 1;
1131
1132 return 0;
1133 }
1134
1135 int
1136 splittable_symbolic_memory_operand (rtx op,
1137 enum machine_mode mode ATTRIBUTE_UNUSED)
1138 {
1139 if (GET_CODE (op) != MEM)
1140 return 0;
1141 if (! symbolic_operand (XEXP (op, 0), Pmode))
1142 return 0;
1143 return 1;
1144 }
1145
1146 int
1147 splittable_immediate_memory_operand (rtx op,
1148 enum machine_mode mode ATTRIBUTE_UNUSED)
1149 {
1150 if (GET_CODE (op) != MEM)
1151 return 0;
1152 if (! immediate_operand (XEXP (op, 0), Pmode))
1153 return 0;
1154 return 1;
1155 }
1156
1157 /* Return truth value of whether OP is EQ or NE. */
1158
1159 int
1160 eq_or_neq (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1161 {
1162 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
1163 }
1164
1165 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
1166 or LTU for non-floating-point. We handle those specially. */
1167
1168 int
1169 normal_comp_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1170 {
1171 enum rtx_code code;
1172
1173 if (!COMPARISON_P (op))
1174 return 0;
1175
1176 if (GET_MODE (XEXP (op, 0)) == CCFPmode
1177 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
1178 return 1;
1179
1180 code = GET_CODE (op);
1181 return (code != NE && code != EQ && code != GEU && code != LTU);
1182 }
1183
1184 /* Return 1 if this is a comparison operator. This allows the use of
1185 MATCH_OPERATOR to recognize all the branch insns. */
1186
1187 int
1188 noov_compare_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1189 {
1190 enum rtx_code code;
1191
1192 if (!COMPARISON_P (op))
1193 return 0;
1194
1195 code = GET_CODE (op);
1196 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode
1197 || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
1198 /* These are the only branches which work with CC_NOOVmode. */
1199 return (code == EQ || code == NE || code == GE || code == LT);
1200 return 1;
1201 }
1202
1203 /* Return 1 if this is a 64-bit comparison operator. This allows the use of
1204 MATCH_OPERATOR to recognize all the branch insns. */
1205
1206 int
1207 noov_compare64_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1208 {
1209 enum rtx_code code;
1210
1211 if (! TARGET_V9)
1212 return 0;
1213
1214 if (!COMPARISON_P (op))
1215 return 0;
1216
1217 code = GET_CODE (op);
1218 if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
1219 /* These are the only branches which work with CCX_NOOVmode. */
1220 return (code == EQ || code == NE || code == GE || code == LT);
1221 return (GET_MODE (XEXP (op, 0)) == CCXmode);
1222 }
1223
1224 /* Nonzero if OP is a comparison operator suitable for use in v9
1225 conditional move or branch on register contents instructions. */
1226
1227 int
1228 v9_regcmp_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1229 {
1230 enum rtx_code code;
1231
1232 if (!COMPARISON_P (op))
1233 return 0;
1234
1235 code = GET_CODE (op);
1236 return v9_regcmp_p (code);
1237 }
1238
1239 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
1240
1241 int
1242 extend_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1243 {
1244 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
1245 }
1246
1247 /* Return nonzero if OP is an operator of mode MODE which can set
1248 the condition codes explicitly. We do not include PLUS and MINUS
1249 because these require CC_NOOVmode, which we handle explicitly. */
1250
1251 int
1252 cc_arithop (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1253 {
1254 if (GET_CODE (op) == AND
1255 || GET_CODE (op) == IOR
1256 || GET_CODE (op) == XOR)
1257 return 1;
1258
1259 return 0;
1260 }
1261
1262 /* Return nonzero if OP is an operator of mode MODE which can bitwise
1263 complement its second operand and set the condition codes explicitly. */
1264
1265 int
1266 cc_arithopn (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1267 {
1268 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
1269 and (xor ... (not ...)) to (not (xor ...)). */
1270 return (GET_CODE (op) == AND
1271 || GET_CODE (op) == IOR);
1272 }
1273 \f
1274 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1275 signed 13 bit immediate field. This is an acceptable SImode operand for
1276 most 3 address instructions. */
1277
1278 int
1279 arith_operand (rtx op, enum machine_mode mode)
1280 {
1281 if (register_operand (op, mode))
1282 return 1;
1283 if (GET_CODE (op) != CONST_INT)
1284 return 0;
1285 return SMALL_INT32 (op);
1286 }
1287
1288 /* Return true if OP is a constant 4096 */
1289
1290 int
1291 arith_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1292 {
1293 if (GET_CODE (op) != CONST_INT)
1294 return 0;
1295 else
1296 return INTVAL (op) == 4096;
1297 }
1298
1299 /* Return true if OP is suitable as second operand for add/sub */
1300
1301 int
1302 arith_add_operand (rtx op, enum machine_mode mode)
1303 {
1304 return arith_operand (op, mode) || arith_4096_operand (op, mode);
1305 }
1306
1307 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
1308 immediate field of OR and XOR instructions. Used for 64-bit
1309 constant formation patterns. */
1310 int
1311 const64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1312 {
1313 return ((GET_CODE (op) == CONST_INT
1314 && SPARC_SIMM13_P (INTVAL (op)))
1315 #if HOST_BITS_PER_WIDE_INT != 64
1316 || (GET_CODE (op) == CONST_DOUBLE
1317 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1318 && (CONST_DOUBLE_HIGH (op) ==
1319 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
1320 (HOST_WIDE_INT)-1 : 0)))
1321 #endif
1322 );
1323 }
1324
1325 /* The same, but only for sethi instructions. */
1326 int
1327 const64_high_operand (rtx op, enum machine_mode mode)
1328 {
1329 return ((GET_CODE (op) == CONST_INT
1330 && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1331 && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1332 )
1333 || (GET_CODE (op) == CONST_DOUBLE
1334 && CONST_DOUBLE_HIGH (op) == 0
1335 && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1336 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
1337 }
1338
1339 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1340 signed 11 bit immediate field. This is an acceptable SImode operand for
1341 the movcc instructions. */
1342
1343 int
1344 arith11_operand (rtx op, enum machine_mode mode)
1345 {
1346 return (register_operand (op, mode)
1347 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
1348 }
1349
1350 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1351 signed 10 bit immediate field. This is an acceptable SImode operand for
1352 the movrcc instructions. */
1353
1354 int
1355 arith10_operand (rtx op, enum machine_mode mode)
1356 {
1357 return (register_operand (op, mode)
1358 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
1359 }
1360
1361 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
1362 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
1363 immediate field.
1364 ARCH64: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1365 can fit in a 13 bit immediate field. This is an acceptable DImode operand
1366 for most 3 address instructions. */
1367
1368 int
1369 arith_double_operand (rtx op, enum machine_mode mode)
1370 {
1371 return (register_operand (op, mode)
1372 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
1373 || (! TARGET_ARCH64
1374 && GET_CODE (op) == CONST_DOUBLE
1375 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1376 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
1377 || (TARGET_ARCH64
1378 && GET_CODE (op) == CONST_DOUBLE
1379 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1380 && ((CONST_DOUBLE_HIGH (op) == -1
1381 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
1382 || (CONST_DOUBLE_HIGH (op) == 0
1383 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
1384 }
1385
1386 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1387
1388 int
1389 arith_double_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1390 {
1391 return (TARGET_ARCH64 &&
1392 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
1393 (GET_CODE (op) == CONST_DOUBLE &&
1394 CONST_DOUBLE_LOW (op) == 4096 &&
1395 CONST_DOUBLE_HIGH (op) == 0)));
1396 }
1397
1398 /* Return true if OP is suitable as second operand for add/sub in DImode */
1399
1400 int
1401 arith_double_add_operand (rtx op, enum machine_mode mode)
1402 {
1403 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
1404 }
1405
1406 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1407 can fit in an 11 bit immediate field. This is an acceptable DImode
1408 operand for the movcc instructions. */
1409 /* ??? Replace with arith11_operand? */
1410
1411 int
1412 arith11_double_operand (rtx op, enum machine_mode mode)
1413 {
1414 return (register_operand (op, mode)
1415 || (GET_CODE (op) == CONST_DOUBLE
1416 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1417 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
1418 && ((CONST_DOUBLE_HIGH (op) == -1
1419 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
1420 || (CONST_DOUBLE_HIGH (op) == 0
1421 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
1422 || (GET_CODE (op) == CONST_INT
1423 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1424 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
1425 }
1426
1427 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1428 can fit in an 10 bit immediate field. This is an acceptable DImode
1429 operand for the movrcc instructions. */
1430 /* ??? Replace with arith10_operand? */
1431
1432 int
1433 arith10_double_operand (rtx op, enum machine_mode mode)
1434 {
1435 return (register_operand (op, mode)
1436 || (GET_CODE (op) == CONST_DOUBLE
1437 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1438 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
1439 && ((CONST_DOUBLE_HIGH (op) == -1
1440 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
1441 || (CONST_DOUBLE_HIGH (op) == 0
1442 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
1443 || (GET_CODE (op) == CONST_INT
1444 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1445 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
1446 }
1447
1448 /* Return truth value of whether OP is an integer which fits the
1449 range constraining immediate operands in most three-address insns,
1450 which have a 13 bit immediate field. */
1451
1452 int
1453 small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1454 {
1455 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1456 }
1457
1458 int
1459 small_int_or_double (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1460 {
1461 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1462 || (GET_CODE (op) == CONST_DOUBLE
1463 && CONST_DOUBLE_HIGH (op) == 0
1464 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))));
1465 }
1466
1467 /* Recognize operand values for the umul instruction. That instruction sign
1468 extends immediate values just like all other sparc instructions, but
1469 interprets the extended result as an unsigned number. */
1470
1471 int
1472 uns_small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1473 {
1474 #if HOST_BITS_PER_WIDE_INT > 32
1475 /* All allowed constants will fit a CONST_INT. */
1476 return (GET_CODE (op) == CONST_INT
1477 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
1478 || (INTVAL (op) >= 0xFFFFF000
1479 && INTVAL (op) <= 0xFFFFFFFF)));
1480 #else
1481 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1482 || (GET_CODE (op) == CONST_DOUBLE
1483 && CONST_DOUBLE_HIGH (op) == 0
1484 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
1485 #endif
1486 }
1487
1488 int
1489 uns_arith_operand (rtx op, enum machine_mode mode)
1490 {
1491 return register_operand (op, mode) || uns_small_int (op, mode);
1492 }
1493
1494 /* Return truth value of statement that OP is a call-clobbered register. */
1495 int
1496 clobbered_register (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1497 {
1498 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1499 }
1500
1501 /* Return 1 if OP is a valid operand for the source of a move insn. */
1502
1503 int
1504 input_operand (rtx op, enum machine_mode mode)
1505 {
1506 enum mode_class mclass;
1507
1508 /* If both modes are non-void they must be the same. */
1509 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1510 return 0;
1511
1512 /* Allow any one instruction integer constant, and all CONST_INT
1513 variants when we are working in DImode and !arch64. */
1514 if (GET_MODE_CLASS (mode) == MODE_INT
1515 && ((GET_CODE (op) == CONST_INT
1516 && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1517 || SPARC_SIMM13_P (INTVAL (op))
1518 || (mode == DImode
1519 && ! TARGET_ARCH64)))
1520 || (TARGET_ARCH64
1521 && GET_CODE (op) == CONST_DOUBLE
1522 && ((CONST_DOUBLE_HIGH (op) == 0
1523 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1524 ||
1525 #if HOST_BITS_PER_WIDE_INT == 64
1526 (CONST_DOUBLE_HIGH (op) == 0
1527 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1528 #else
1529 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1530 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1531 && CONST_DOUBLE_HIGH (op) == 0)
1532 || (CONST_DOUBLE_HIGH (op) == -1
1533 && CONST_DOUBLE_LOW (op) & 0x80000000) != 0))
1534 #endif
1535 ))))
1536 return 1;
1537
1538 /* If !arch64 and this is a DImode const, allow it so that
1539 the splits can be generated. */
1540 if (! TARGET_ARCH64
1541 && mode == DImode
1542 && GET_CODE (op) == CONST_DOUBLE)
1543 return 1;
1544
1545 if (register_operand (op, mode))
1546 return 1;
1547
1548 mclass = GET_MODE_CLASS (mode);
1549 if ((mclass == MODE_FLOAT && GET_CODE (op) == CONST_DOUBLE)
1550 || (mclass == MODE_VECTOR_INT && GET_CODE (op) == CONST_VECTOR))
1551 return 1;
1552
1553 /* If this is a SUBREG, look inside so that we handle
1554 paradoxical ones. */
1555 if (GET_CODE (op) == SUBREG)
1556 op = SUBREG_REG (op);
1557
1558 /* Check for valid MEM forms. */
1559 if (GET_CODE (op) == MEM)
1560 return memory_address_p (mode, XEXP (op, 0));
1561
1562 return 0;
1563 }
1564
1565 /* Return 1 if OP is valid for the lhs of a compare insn. */
1566
1567 int
1568 compare_operand (rtx op, enum machine_mode mode)
1569 {
1570 if (GET_CODE (op) == ZERO_EXTRACT)
1571 return (register_operand (XEXP (op, 0), mode)
1572 && small_int_or_double (XEXP (op, 1), mode)
1573 && small_int_or_double (XEXP (op, 2), mode)
1574 /* This matches cmp_zero_extract. */
1575 && ((mode == SImode
1576 && ((GET_CODE (XEXP (op, 2)) == CONST_INT
1577 && INTVAL (XEXP (op, 2)) > 19)
1578 || (GET_CODE (XEXP (op, 2)) == CONST_DOUBLE
1579 && CONST_DOUBLE_LOW (XEXP (op, 2)) > 19)))
1580 /* This matches cmp_zero_extract_sp64. */
1581 || (mode == DImode
1582 && TARGET_ARCH64
1583 && ((GET_CODE (XEXP (op, 2)) == CONST_INT
1584 && INTVAL (XEXP (op, 2)) > 51)
1585 || (GET_CODE (XEXP (op, 2)) == CONST_DOUBLE
1586 && CONST_DOUBLE_LOW (XEXP (op, 2)) > 51)))));
1587 else
1588 return register_operand (op, mode);
1589 }
1590
1591 \f
1592 /* We know it can't be done in one insn when we get here,
1593 the movsi expander guarantees this. */
1594 void
1595 sparc_emit_set_const32 (rtx op0, rtx op1)
1596 {
1597 enum machine_mode mode = GET_MODE (op0);
1598 rtx temp;
1599
1600 if (GET_CODE (op1) == CONST_INT)
1601 {
1602 HOST_WIDE_INT value = INTVAL (op1);
1603
1604 if (SPARC_SETHI_P (value & GET_MODE_MASK (mode))
1605 || SPARC_SIMM13_P (value))
1606 abort ();
1607 }
1608
1609 /* Full 2-insn decomposition is needed. */
1610 if (reload_in_progress || reload_completed)
1611 temp = op0;
1612 else
1613 temp = gen_reg_rtx (mode);
1614
1615 if (GET_CODE (op1) == CONST_INT)
1616 {
1617 /* Emit them as real moves instead of a HIGH/LO_SUM,
1618 this way CSE can see everything and reuse intermediate
1619 values if it wants. */
1620 if (TARGET_ARCH64
1621 && HOST_BITS_PER_WIDE_INT != 64
1622 && (INTVAL (op1) & 0x80000000) != 0)
1623 emit_insn (gen_rtx_SET
1624 (VOIDmode, temp,
1625 immed_double_const (INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff,
1626 0, DImode)));
1627 else
1628 emit_insn (gen_rtx_SET (VOIDmode, temp,
1629 GEN_INT (INTVAL (op1)
1630 & ~(HOST_WIDE_INT)0x3ff)));
1631
1632 emit_insn (gen_rtx_SET (VOIDmode,
1633 op0,
1634 gen_rtx_IOR (mode, temp,
1635 GEN_INT (INTVAL (op1) & 0x3ff))));
1636 }
1637 else
1638 {
1639 /* A symbol, emit in the traditional way. */
1640 emit_insn (gen_rtx_SET (VOIDmode, temp,
1641 gen_rtx_HIGH (mode, op1)));
1642 emit_insn (gen_rtx_SET (VOIDmode,
1643 op0, gen_rtx_LO_SUM (mode, temp, op1)));
1644
1645 }
1646 }
1647
1648 \f
1649 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1650 If TEMP is nonzero, we are forbidden to use any other scratch
1651 registers. Otherwise, we are allowed to generate them as needed.
1652
1653 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1654 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1655 void
1656 sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp)
1657 {
1658 rtx temp1, temp2, temp3, temp4, temp5;
1659 rtx ti_temp = 0;
1660
1661 if (temp && GET_MODE (temp) == TImode)
1662 {
1663 ti_temp = temp;
1664 temp = gen_rtx_REG (DImode, REGNO (temp));
1665 }
1666
1667 /* SPARC-V9 code-model support. */
1668 switch (sparc_cmodel)
1669 {
1670 case CM_MEDLOW:
1671 /* The range spanned by all instructions in the object is less
1672 than 2^31 bytes (2GB) and the distance from any instruction
1673 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1674 than 2^31 bytes (2GB).
1675
1676 The executable must be in the low 4TB of the virtual address
1677 space.
1678
1679 sethi %hi(symbol), %temp1
1680 or %temp1, %lo(symbol), %reg */
1681 if (temp)
1682 temp1 = temp; /* op0 is allowed. */
1683 else
1684 temp1 = gen_reg_rtx (DImode);
1685
1686 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1687 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1688 break;
1689
1690 case CM_MEDMID:
1691 /* The range spanned by all instructions in the object is less
1692 than 2^31 bytes (2GB) and the distance from any instruction
1693 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1694 than 2^31 bytes (2GB).
1695
1696 The executable must be in the low 16TB of the virtual address
1697 space.
1698
1699 sethi %h44(symbol), %temp1
1700 or %temp1, %m44(symbol), %temp2
1701 sllx %temp2, 12, %temp3
1702 or %temp3, %l44(symbol), %reg */
1703 if (temp)
1704 {
1705 temp1 = op0;
1706 temp2 = op0;
1707 temp3 = temp; /* op0 is allowed. */
1708 }
1709 else
1710 {
1711 temp1 = gen_reg_rtx (DImode);
1712 temp2 = gen_reg_rtx (DImode);
1713 temp3 = gen_reg_rtx (DImode);
1714 }
1715
1716 emit_insn (gen_seth44 (temp1, op1));
1717 emit_insn (gen_setm44 (temp2, temp1, op1));
1718 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1719 gen_rtx_ASHIFT (DImode, temp2, GEN_INT (12))));
1720 emit_insn (gen_setl44 (op0, temp3, op1));
1721 break;
1722
1723 case CM_MEDANY:
1724 /* The range spanned by all instructions in the object is less
1725 than 2^31 bytes (2GB) and the distance from any instruction
1726 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1727 than 2^31 bytes (2GB).
1728
1729 The executable can be placed anywhere in the virtual address
1730 space.
1731
1732 sethi %hh(symbol), %temp1
1733 sethi %lm(symbol), %temp2
1734 or %temp1, %hm(symbol), %temp3
1735 sllx %temp3, 32, %temp4
1736 or %temp4, %temp2, %temp5
1737 or %temp5, %lo(symbol), %reg */
1738 if (temp)
1739 {
1740 /* It is possible that one of the registers we got for operands[2]
1741 might coincide with that of operands[0] (which is why we made
1742 it TImode). Pick the other one to use as our scratch. */
1743 if (rtx_equal_p (temp, op0))
1744 {
1745 if (ti_temp)
1746 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1747 else
1748 abort();
1749 }
1750 temp1 = op0;
1751 temp2 = temp; /* op0 is _not_ allowed, see above. */
1752 temp3 = op0;
1753 temp4 = op0;
1754 temp5 = op0;
1755 }
1756 else
1757 {
1758 temp1 = gen_reg_rtx (DImode);
1759 temp2 = gen_reg_rtx (DImode);
1760 temp3 = gen_reg_rtx (DImode);
1761 temp4 = gen_reg_rtx (DImode);
1762 temp5 = gen_reg_rtx (DImode);
1763 }
1764
1765 emit_insn (gen_sethh (temp1, op1));
1766 emit_insn (gen_setlm (temp2, op1));
1767 emit_insn (gen_sethm (temp3, temp1, op1));
1768 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1769 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1770 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1771 gen_rtx_PLUS (DImode, temp4, temp2)));
1772 emit_insn (gen_setlo (op0, temp5, op1));
1773 break;
1774
1775 case CM_EMBMEDANY:
1776 /* Old old old backwards compatibility kruft here.
1777 Essentially it is MEDLOW with a fixed 64-bit
1778 virtual base added to all data segment addresses.
1779 Text-segment stuff is computed like MEDANY, we can't
1780 reuse the code above because the relocation knobs
1781 look different.
1782
1783 Data segment: sethi %hi(symbol), %temp1
1784 add %temp1, EMBMEDANY_BASE_REG, %temp2
1785 or %temp2, %lo(symbol), %reg */
1786 if (data_segment_operand (op1, GET_MODE (op1)))
1787 {
1788 if (temp)
1789 {
1790 temp1 = temp; /* op0 is allowed. */
1791 temp2 = op0;
1792 }
1793 else
1794 {
1795 temp1 = gen_reg_rtx (DImode);
1796 temp2 = gen_reg_rtx (DImode);
1797 }
1798
1799 emit_insn (gen_embmedany_sethi (temp1, op1));
1800 emit_insn (gen_embmedany_brsum (temp2, temp1));
1801 emit_insn (gen_embmedany_losum (op0, temp2, op1));
1802 }
1803
1804 /* Text segment: sethi %uhi(symbol), %temp1
1805 sethi %hi(symbol), %temp2
1806 or %temp1, %ulo(symbol), %temp3
1807 sllx %temp3, 32, %temp4
1808 or %temp4, %temp2, %temp5
1809 or %temp5, %lo(symbol), %reg */
1810 else
1811 {
1812 if (temp)
1813 {
1814 /* It is possible that one of the registers we got for operands[2]
1815 might coincide with that of operands[0] (which is why we made
1816 it TImode). Pick the other one to use as our scratch. */
1817 if (rtx_equal_p (temp, op0))
1818 {
1819 if (ti_temp)
1820 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1821 else
1822 abort();
1823 }
1824 temp1 = op0;
1825 temp2 = temp; /* op0 is _not_ allowed, see above. */
1826 temp3 = op0;
1827 temp4 = op0;
1828 temp5 = op0;
1829 }
1830 else
1831 {
1832 temp1 = gen_reg_rtx (DImode);
1833 temp2 = gen_reg_rtx (DImode);
1834 temp3 = gen_reg_rtx (DImode);
1835 temp4 = gen_reg_rtx (DImode);
1836 temp5 = gen_reg_rtx (DImode);
1837 }
1838
1839 emit_insn (gen_embmedany_textuhi (temp1, op1));
1840 emit_insn (gen_embmedany_texthi (temp2, op1));
1841 emit_insn (gen_embmedany_textulo (temp3, temp1, op1));
1842 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1843 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1844 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1845 gen_rtx_PLUS (DImode, temp4, temp2)));
1846 emit_insn (gen_embmedany_textlo (op0, temp5, op1));
1847 }
1848 break;
1849
1850 default:
1851 abort();
1852 }
1853 }
1854
1855 /* These avoid problems when cross compiling. If we do not
1856 go through all this hair then the optimizer will see
1857 invalid REG_EQUAL notes or in some cases none at all. */
1858 static void sparc_emit_set_safe_HIGH64 (rtx, HOST_WIDE_INT);
1859 static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
1860 static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
1861 static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
1862
1863 #if HOST_BITS_PER_WIDE_INT == 64
1864 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
1865 #define GEN_INT64(__x) GEN_INT (__x)
1866 #else
1867 #define GEN_HIGHINT64(__x) \
1868 immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode)
1869 #define GEN_INT64(__x) \
1870 immed_double_const ((__x) & 0xffffffff, \
1871 ((__x) & 0x80000000 ? -1 : 0), DImode)
1872 #endif
1873
1874 /* The optimizer is not to assume anything about exactly
1875 which bits are set for a HIGH, they are unspecified.
1876 Unfortunately this leads to many missed optimizations
1877 during CSE. We mask out the non-HIGH bits, and matches
1878 a plain movdi, to alleviate this problem. */
1879 static void
1880 sparc_emit_set_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
1881 {
1882 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1883 }
1884
1885 static rtx
1886 gen_safe_SET64 (rtx dest, HOST_WIDE_INT val)
1887 {
1888 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1889 }
1890
1891 static rtx
1892 gen_safe_OR64 (rtx src, HOST_WIDE_INT val)
1893 {
1894 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1895 }
1896
1897 static rtx
1898 gen_safe_XOR64 (rtx src, HOST_WIDE_INT val)
1899 {
1900 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
1901 }
1902
1903 /* Worker routines for 64-bit constant formation on arch64.
1904 One of the key things to be doing in these emissions is
1905 to create as many temp REGs as possible. This makes it
1906 possible for half-built constants to be used later when
1907 such values are similar to something required later on.
1908 Without doing this, the optimizer cannot see such
1909 opportunities. */
1910
1911 static void sparc_emit_set_const64_quick1 (rtx, rtx,
1912 unsigned HOST_WIDE_INT, int);
1913
1914 static void
1915 sparc_emit_set_const64_quick1 (rtx op0, rtx temp,
1916 unsigned HOST_WIDE_INT low_bits, int is_neg)
1917 {
1918 unsigned HOST_WIDE_INT high_bits;
1919
1920 if (is_neg)
1921 high_bits = (~low_bits) & 0xffffffff;
1922 else
1923 high_bits = low_bits;
1924
1925 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1926 if (!is_neg)
1927 {
1928 emit_insn (gen_rtx_SET (VOIDmode, op0,
1929 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1930 }
1931 else
1932 {
1933 /* If we are XOR'ing with -1, then we should emit a one's complement
1934 instead. This way the combiner will notice logical operations
1935 such as ANDN later on and substitute. */
1936 if ((low_bits & 0x3ff) == 0x3ff)
1937 {
1938 emit_insn (gen_rtx_SET (VOIDmode, op0,
1939 gen_rtx_NOT (DImode, temp)));
1940 }
1941 else
1942 {
1943 emit_insn (gen_rtx_SET (VOIDmode, op0,
1944 gen_safe_XOR64 (temp,
1945 (-(HOST_WIDE_INT)0x400
1946 | (low_bits & 0x3ff)))));
1947 }
1948 }
1949 }
1950
1951 static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT,
1952 unsigned HOST_WIDE_INT, int);
1953
1954 static void
1955 sparc_emit_set_const64_quick2 (rtx op0, rtx temp,
1956 unsigned HOST_WIDE_INT high_bits,
1957 unsigned HOST_WIDE_INT low_immediate,
1958 int shift_count)
1959 {
1960 rtx temp2 = op0;
1961
1962 if ((high_bits & 0xfffffc00) != 0)
1963 {
1964 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1965 if ((high_bits & ~0xfffffc00) != 0)
1966 emit_insn (gen_rtx_SET (VOIDmode, op0,
1967 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1968 else
1969 temp2 = temp;
1970 }
1971 else
1972 {
1973 emit_insn (gen_safe_SET64 (temp, high_bits));
1974 temp2 = temp;
1975 }
1976
1977 /* Now shift it up into place. */
1978 emit_insn (gen_rtx_SET (VOIDmode, op0,
1979 gen_rtx_ASHIFT (DImode, temp2,
1980 GEN_INT (shift_count))));
1981
1982 /* If there is a low immediate part piece, finish up by
1983 putting that in as well. */
1984 if (low_immediate != 0)
1985 emit_insn (gen_rtx_SET (VOIDmode, op0,
1986 gen_safe_OR64 (op0, low_immediate)));
1987 }
1988
1989 static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT,
1990 unsigned HOST_WIDE_INT);
1991
1992 /* Full 64-bit constant decomposition. Even though this is the
1993 'worst' case, we still optimize a few things away. */
1994 static void
1995 sparc_emit_set_const64_longway (rtx op0, rtx temp,
1996 unsigned HOST_WIDE_INT high_bits,
1997 unsigned HOST_WIDE_INT low_bits)
1998 {
1999 rtx sub_temp;
2000
2001 if (reload_in_progress || reload_completed)
2002 sub_temp = op0;
2003 else
2004 sub_temp = gen_reg_rtx (DImode);
2005
2006 if ((high_bits & 0xfffffc00) != 0)
2007 {
2008 sparc_emit_set_safe_HIGH64 (temp, high_bits);
2009 if ((high_bits & ~0xfffffc00) != 0)
2010 emit_insn (gen_rtx_SET (VOIDmode,
2011 sub_temp,
2012 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
2013 else
2014 sub_temp = temp;
2015 }
2016 else
2017 {
2018 emit_insn (gen_safe_SET64 (temp, high_bits));
2019 sub_temp = temp;
2020 }
2021
2022 if (!reload_in_progress && !reload_completed)
2023 {
2024 rtx temp2 = gen_reg_rtx (DImode);
2025 rtx temp3 = gen_reg_rtx (DImode);
2026 rtx temp4 = gen_reg_rtx (DImode);
2027
2028 emit_insn (gen_rtx_SET (VOIDmode, temp4,
2029 gen_rtx_ASHIFT (DImode, sub_temp,
2030 GEN_INT (32))));
2031
2032 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
2033 if ((low_bits & ~0xfffffc00) != 0)
2034 {
2035 emit_insn (gen_rtx_SET (VOIDmode, temp3,
2036 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
2037 emit_insn (gen_rtx_SET (VOIDmode, op0,
2038 gen_rtx_PLUS (DImode, temp4, temp3)));
2039 }
2040 else
2041 {
2042 emit_insn (gen_rtx_SET (VOIDmode, op0,
2043 gen_rtx_PLUS (DImode, temp4, temp2)));
2044 }
2045 }
2046 else
2047 {
2048 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
2049 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
2050 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
2051 int to_shift = 12;
2052
2053 /* We are in the middle of reload, so this is really
2054 painful. However we do still make an attempt to
2055 avoid emitting truly stupid code. */
2056 if (low1 != const0_rtx)
2057 {
2058 emit_insn (gen_rtx_SET (VOIDmode, op0,
2059 gen_rtx_ASHIFT (DImode, sub_temp,
2060 GEN_INT (to_shift))));
2061 emit_insn (gen_rtx_SET (VOIDmode, op0,
2062 gen_rtx_IOR (DImode, op0, low1)));
2063 sub_temp = op0;
2064 to_shift = 12;
2065 }
2066 else
2067 {
2068 to_shift += 12;
2069 }
2070 if (low2 != const0_rtx)
2071 {
2072 emit_insn (gen_rtx_SET (VOIDmode, op0,
2073 gen_rtx_ASHIFT (DImode, sub_temp,
2074 GEN_INT (to_shift))));
2075 emit_insn (gen_rtx_SET (VOIDmode, op0,
2076 gen_rtx_IOR (DImode, op0, low2)));
2077 sub_temp = op0;
2078 to_shift = 8;
2079 }
2080 else
2081 {
2082 to_shift += 8;
2083 }
2084 emit_insn (gen_rtx_SET (VOIDmode, op0,
2085 gen_rtx_ASHIFT (DImode, sub_temp,
2086 GEN_INT (to_shift))));
2087 if (low3 != const0_rtx)
2088 emit_insn (gen_rtx_SET (VOIDmode, op0,
2089 gen_rtx_IOR (DImode, op0, low3)));
2090 /* phew... */
2091 }
2092 }
2093
2094 /* Analyze a 64-bit constant for certain properties. */
2095 static void analyze_64bit_constant (unsigned HOST_WIDE_INT,
2096 unsigned HOST_WIDE_INT,
2097 int *, int *, int *);
2098
2099 static void
2100 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits,
2101 unsigned HOST_WIDE_INT low_bits,
2102 int *hbsp, int *lbsp, int *abbasp)
2103 {
2104 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
2105 int i;
2106
2107 lowest_bit_set = highest_bit_set = -1;
2108 i = 0;
2109 do
2110 {
2111 if ((lowest_bit_set == -1)
2112 && ((low_bits >> i) & 1))
2113 lowest_bit_set = i;
2114 if ((highest_bit_set == -1)
2115 && ((high_bits >> (32 - i - 1)) & 1))
2116 highest_bit_set = (64 - i - 1);
2117 }
2118 while (++i < 32
2119 && ((highest_bit_set == -1)
2120 || (lowest_bit_set == -1)));
2121 if (i == 32)
2122 {
2123 i = 0;
2124 do
2125 {
2126 if ((lowest_bit_set == -1)
2127 && ((high_bits >> i) & 1))
2128 lowest_bit_set = i + 32;
2129 if ((highest_bit_set == -1)
2130 && ((low_bits >> (32 - i - 1)) & 1))
2131 highest_bit_set = 32 - i - 1;
2132 }
2133 while (++i < 32
2134 && ((highest_bit_set == -1)
2135 || (lowest_bit_set == -1)));
2136 }
2137 /* If there are no bits set this should have gone out
2138 as one instruction! */
2139 if (lowest_bit_set == -1
2140 || highest_bit_set == -1)
2141 abort ();
2142 all_bits_between_are_set = 1;
2143 for (i = lowest_bit_set; i <= highest_bit_set; i++)
2144 {
2145 if (i < 32)
2146 {
2147 if ((low_bits & (1 << i)) != 0)
2148 continue;
2149 }
2150 else
2151 {
2152 if ((high_bits & (1 << (i - 32))) != 0)
2153 continue;
2154 }
2155 all_bits_between_are_set = 0;
2156 break;
2157 }
2158 *hbsp = highest_bit_set;
2159 *lbsp = lowest_bit_set;
2160 *abbasp = all_bits_between_are_set;
2161 }
2162
2163 static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT);
2164
2165 static int
2166 const64_is_2insns (unsigned HOST_WIDE_INT high_bits,
2167 unsigned HOST_WIDE_INT low_bits)
2168 {
2169 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
2170
2171 if (high_bits == 0
2172 || high_bits == 0xffffffff)
2173 return 1;
2174
2175 analyze_64bit_constant (high_bits, low_bits,
2176 &highest_bit_set, &lowest_bit_set,
2177 &all_bits_between_are_set);
2178
2179 if ((highest_bit_set == 63
2180 || lowest_bit_set == 0)
2181 && all_bits_between_are_set != 0)
2182 return 1;
2183
2184 if ((highest_bit_set - lowest_bit_set) < 21)
2185 return 1;
2186
2187 return 0;
2188 }
2189
2190 static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT,
2191 unsigned HOST_WIDE_INT,
2192 int, int);
2193
2194 static unsigned HOST_WIDE_INT
2195 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits,
2196 unsigned HOST_WIDE_INT low_bits,
2197 int lowest_bit_set, int shift)
2198 {
2199 HOST_WIDE_INT hi, lo;
2200
2201 if (lowest_bit_set < 32)
2202 {
2203 lo = (low_bits >> lowest_bit_set) << shift;
2204 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
2205 }
2206 else
2207 {
2208 lo = 0;
2209 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
2210 }
2211 if (hi & lo)
2212 abort ();
2213 return (hi | lo);
2214 }
2215
2216 /* Here we are sure to be arch64 and this is an integer constant
2217 being loaded into a register. Emit the most efficient
2218 insn sequence possible. Detection of all the 1-insn cases
2219 has been done already. */
2220 void
2221 sparc_emit_set_const64 (rtx op0, rtx op1)
2222 {
2223 unsigned HOST_WIDE_INT high_bits, low_bits;
2224 int lowest_bit_set, highest_bit_set;
2225 int all_bits_between_are_set;
2226 rtx temp = 0;
2227
2228 /* Sanity check that we know what we are working with. */
2229 if (! TARGET_ARCH64)
2230 abort ();
2231
2232 if (GET_CODE (op0) != SUBREG)
2233 {
2234 if (GET_CODE (op0) != REG
2235 || (REGNO (op0) >= SPARC_FIRST_FP_REG
2236 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
2237 abort ();
2238 }
2239
2240 if (reload_in_progress || reload_completed)
2241 temp = op0;
2242
2243 if (GET_CODE (op1) != CONST_DOUBLE
2244 && GET_CODE (op1) != CONST_INT)
2245 {
2246 sparc_emit_set_symbolic_const64 (op0, op1, temp);
2247 return;
2248 }
2249
2250 if (! temp)
2251 temp = gen_reg_rtx (DImode);
2252
2253 if (GET_CODE (op1) == CONST_DOUBLE)
2254 {
2255 #if HOST_BITS_PER_WIDE_INT == 64
2256 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
2257 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
2258 #else
2259 high_bits = CONST_DOUBLE_HIGH (op1);
2260 low_bits = CONST_DOUBLE_LOW (op1);
2261 #endif
2262 }
2263 else
2264 {
2265 #if HOST_BITS_PER_WIDE_INT == 64
2266 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
2267 low_bits = (INTVAL (op1) & 0xffffffff);
2268 #else
2269 high_bits = ((INTVAL (op1) < 0) ?
2270 0xffffffff :
2271 0x00000000);
2272 low_bits = INTVAL (op1);
2273 #endif
2274 }
2275
2276 /* low_bits bits 0 --> 31
2277 high_bits bits 32 --> 63 */
2278
2279 analyze_64bit_constant (high_bits, low_bits,
2280 &highest_bit_set, &lowest_bit_set,
2281 &all_bits_between_are_set);
2282
2283 /* First try for a 2-insn sequence. */
2284
2285 /* These situations are preferred because the optimizer can
2286 * do more things with them:
2287 * 1) mov -1, %reg
2288 * sllx %reg, shift, %reg
2289 * 2) mov -1, %reg
2290 * srlx %reg, shift, %reg
2291 * 3) mov some_small_const, %reg
2292 * sllx %reg, shift, %reg
2293 */
2294 if (((highest_bit_set == 63
2295 || lowest_bit_set == 0)
2296 && all_bits_between_are_set != 0)
2297 || ((highest_bit_set - lowest_bit_set) < 12))
2298 {
2299 HOST_WIDE_INT the_const = -1;
2300 int shift = lowest_bit_set;
2301
2302 if ((highest_bit_set != 63
2303 && lowest_bit_set != 0)
2304 || all_bits_between_are_set == 0)
2305 {
2306 the_const =
2307 create_simple_focus_bits (high_bits, low_bits,
2308 lowest_bit_set, 0);
2309 }
2310 else if (lowest_bit_set == 0)
2311 shift = -(63 - highest_bit_set);
2312
2313 if (! SPARC_SIMM13_P (the_const))
2314 abort ();
2315
2316 emit_insn (gen_safe_SET64 (temp, the_const));
2317 if (shift > 0)
2318 emit_insn (gen_rtx_SET (VOIDmode,
2319 op0,
2320 gen_rtx_ASHIFT (DImode,
2321 temp,
2322 GEN_INT (shift))));
2323 else if (shift < 0)
2324 emit_insn (gen_rtx_SET (VOIDmode,
2325 op0,
2326 gen_rtx_LSHIFTRT (DImode,
2327 temp,
2328 GEN_INT (-shift))));
2329 else
2330 abort ();
2331 return;
2332 }
2333
2334 /* Now a range of 22 or less bits set somewhere.
2335 * 1) sethi %hi(focus_bits), %reg
2336 * sllx %reg, shift, %reg
2337 * 2) sethi %hi(focus_bits), %reg
2338 * srlx %reg, shift, %reg
2339 */
2340 if ((highest_bit_set - lowest_bit_set) < 21)
2341 {
2342 unsigned HOST_WIDE_INT focus_bits =
2343 create_simple_focus_bits (high_bits, low_bits,
2344 lowest_bit_set, 10);
2345
2346 if (! SPARC_SETHI_P (focus_bits))
2347 abort ();
2348
2349 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
2350
2351 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2352 if (lowest_bit_set < 10)
2353 emit_insn (gen_rtx_SET (VOIDmode,
2354 op0,
2355 gen_rtx_LSHIFTRT (DImode, temp,
2356 GEN_INT (10 - lowest_bit_set))));
2357 else if (lowest_bit_set > 10)
2358 emit_insn (gen_rtx_SET (VOIDmode,
2359 op0,
2360 gen_rtx_ASHIFT (DImode, temp,
2361 GEN_INT (lowest_bit_set - 10))));
2362 else
2363 abort ();
2364 return;
2365 }
2366
2367 /* 1) sethi %hi(low_bits), %reg
2368 * or %reg, %lo(low_bits), %reg
2369 * 2) sethi %hi(~low_bits), %reg
2370 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2371 */
2372 if (high_bits == 0
2373 || high_bits == 0xffffffff)
2374 {
2375 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
2376 (high_bits == 0xffffffff));
2377 return;
2378 }
2379
2380 /* Now, try 3-insn sequences. */
2381
2382 /* 1) sethi %hi(high_bits), %reg
2383 * or %reg, %lo(high_bits), %reg
2384 * sllx %reg, 32, %reg
2385 */
2386 if (low_bits == 0)
2387 {
2388 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
2389 return;
2390 }
2391
2392 /* We may be able to do something quick
2393 when the constant is negated, so try that. */
2394 if (const64_is_2insns ((~high_bits) & 0xffffffff,
2395 (~low_bits) & 0xfffffc00))
2396 {
2397 /* NOTE: The trailing bits get XOR'd so we need the
2398 non-negated bits, not the negated ones. */
2399 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
2400
2401 if ((((~high_bits) & 0xffffffff) == 0
2402 && ((~low_bits) & 0x80000000) == 0)
2403 || (((~high_bits) & 0xffffffff) == 0xffffffff
2404 && ((~low_bits) & 0x80000000) != 0))
2405 {
2406 int fast_int = (~low_bits & 0xffffffff);
2407
2408 if ((SPARC_SETHI_P (fast_int)
2409 && (~high_bits & 0xffffffff) == 0)
2410 || SPARC_SIMM13_P (fast_int))
2411 emit_insn (gen_safe_SET64 (temp, fast_int));
2412 else
2413 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
2414 }
2415 else
2416 {
2417 rtx negated_const;
2418 #if HOST_BITS_PER_WIDE_INT == 64
2419 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2420 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2421 #else
2422 negated_const = immed_double_const ((~low_bits) & 0xfffffc00,
2423 (~high_bits) & 0xffffffff,
2424 DImode);
2425 #endif
2426 sparc_emit_set_const64 (temp, negated_const);
2427 }
2428
2429 /* If we are XOR'ing with -1, then we should emit a one's complement
2430 instead. This way the combiner will notice logical operations
2431 such as ANDN later on and substitute. */
2432 if (trailing_bits == 0x3ff)
2433 {
2434 emit_insn (gen_rtx_SET (VOIDmode, op0,
2435 gen_rtx_NOT (DImode, temp)));
2436 }
2437 else
2438 {
2439 emit_insn (gen_rtx_SET (VOIDmode,
2440 op0,
2441 gen_safe_XOR64 (temp,
2442 (-0x400 | trailing_bits))));
2443 }
2444 return;
2445 }
2446
2447 /* 1) sethi %hi(xxx), %reg
2448 * or %reg, %lo(xxx), %reg
2449 * sllx %reg, yyy, %reg
2450 *
2451 * ??? This is just a generalized version of the low_bits==0
2452 * thing above, FIXME...
2453 */
2454 if ((highest_bit_set - lowest_bit_set) < 32)
2455 {
2456 unsigned HOST_WIDE_INT focus_bits =
2457 create_simple_focus_bits (high_bits, low_bits,
2458 lowest_bit_set, 0);
2459
2460 /* We can't get here in this state. */
2461 if (highest_bit_set < 32
2462 || lowest_bit_set >= 32)
2463 abort ();
2464
2465 /* So what we know is that the set bits straddle the
2466 middle of the 64-bit word. */
2467 sparc_emit_set_const64_quick2 (op0, temp,
2468 focus_bits, 0,
2469 lowest_bit_set);
2470 return;
2471 }
2472
2473 /* 1) sethi %hi(high_bits), %reg
2474 * or %reg, %lo(high_bits), %reg
2475 * sllx %reg, 32, %reg
2476 * or %reg, low_bits, %reg
2477 */
2478 if (SPARC_SIMM13_P(low_bits)
2479 && ((int)low_bits > 0))
2480 {
2481 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2482 return;
2483 }
2484
2485 /* The easiest way when all else fails, is full decomposition. */
2486 #if 0
2487 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2488 high_bits, low_bits, ~high_bits, ~low_bits);
2489 #endif
2490 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2491 }
2492
2493 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2494 return the mode to be used for the comparison. For floating-point,
2495 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2496 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2497 processing is needed. */
2498
2499 enum machine_mode
2500 select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED)
2501 {
2502 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2503 {
2504 switch (op)
2505 {
2506 case EQ:
2507 case NE:
2508 case UNORDERED:
2509 case ORDERED:
2510 case UNLT:
2511 case UNLE:
2512 case UNGT:
2513 case UNGE:
2514 case UNEQ:
2515 case LTGT:
2516 return CCFPmode;
2517
2518 case LT:
2519 case LE:
2520 case GT:
2521 case GE:
2522 return CCFPEmode;
2523
2524 default:
2525 abort ();
2526 }
2527 }
2528 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2529 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2530 {
2531 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2532 return CCX_NOOVmode;
2533 else
2534 return CC_NOOVmode;
2535 }
2536 else
2537 {
2538 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2539 return CCXmode;
2540 else
2541 return CCmode;
2542 }
2543 }
2544
2545 /* X and Y are two things to compare using CODE. Emit the compare insn and
2546 return the rtx for the cc reg in the proper mode. */
2547
2548 rtx
2549 gen_compare_reg (enum rtx_code code, rtx x, rtx y)
2550 {
2551 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
2552 rtx cc_reg;
2553
2554 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2555 fcc regs (cse can't tell they're really call clobbered regs and will
2556 remove a duplicate comparison even if there is an intervening function
2557 call - it will then try to reload the cc reg via an int reg which is why
2558 we need the movcc patterns). It is possible to provide the movcc
2559 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2560 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2561 to tell cse that CCFPE mode registers (even pseudos) are call
2562 clobbered. */
2563
2564 /* ??? This is an experiment. Rather than making changes to cse which may
2565 or may not be easy/clean, we do our own cse. This is possible because
2566 we will generate hard registers. Cse knows they're call clobbered (it
2567 doesn't know the same thing about pseudos). If we guess wrong, no big
2568 deal, but if we win, great! */
2569
2570 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2571 #if 1 /* experiment */
2572 {
2573 int reg;
2574 /* We cycle through the registers to ensure they're all exercised. */
2575 static int next_fcc_reg = 0;
2576 /* Previous x,y for each fcc reg. */
2577 static rtx prev_args[4][2];
2578
2579 /* Scan prev_args for x,y. */
2580 for (reg = 0; reg < 4; reg++)
2581 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2582 break;
2583 if (reg == 4)
2584 {
2585 reg = next_fcc_reg;
2586 prev_args[reg][0] = x;
2587 prev_args[reg][1] = y;
2588 next_fcc_reg = (next_fcc_reg + 1) & 3;
2589 }
2590 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2591 }
2592 #else
2593 cc_reg = gen_reg_rtx (mode);
2594 #endif /* ! experiment */
2595 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2596 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2597 else
2598 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2599
2600 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2601 gen_rtx_COMPARE (mode, x, y)));
2602
2603 return cc_reg;
2604 }
2605
2606 /* This function is used for v9 only.
2607 CODE is the code for an Scc's comparison.
2608 OPERANDS[0] is the target of the Scc insn.
2609 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2610 been generated yet).
2611
2612 This function is needed to turn
2613
2614 (set (reg:SI 110)
2615 (gt (reg:CCX 100 %icc)
2616 (const_int 0)))
2617 into
2618 (set (reg:SI 110)
2619 (gt:DI (reg:CCX 100 %icc)
2620 (const_int 0)))
2621
2622 IE: The instruction recognizer needs to see the mode of the comparison to
2623 find the right instruction. We could use "gt:DI" right in the
2624 define_expand, but leaving it out allows us to handle DI, SI, etc.
2625
2626 We refer to the global sparc compare operands sparc_compare_op0 and
2627 sparc_compare_op1. */
2628
2629 int
2630 gen_v9_scc (enum rtx_code compare_code, register rtx *operands)
2631 {
2632 rtx temp, op0, op1;
2633
2634 if (! TARGET_ARCH64
2635 && (GET_MODE (sparc_compare_op0) == DImode
2636 || GET_MODE (operands[0]) == DImode))
2637 return 0;
2638
2639 op0 = sparc_compare_op0;
2640 op1 = sparc_compare_op1;
2641
2642 /* Try to use the movrCC insns. */
2643 if (TARGET_ARCH64
2644 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2645 && op1 == const0_rtx
2646 && v9_regcmp_p (compare_code))
2647 {
2648 /* Special case for op0 != 0. This can be done with one instruction if
2649 operands[0] == sparc_compare_op0. */
2650
2651 if (compare_code == NE
2652 && GET_MODE (operands[0]) == DImode
2653 && rtx_equal_p (op0, operands[0]))
2654 {
2655 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2656 gen_rtx_IF_THEN_ELSE (DImode,
2657 gen_rtx_fmt_ee (compare_code, DImode,
2658 op0, const0_rtx),
2659 const1_rtx,
2660 operands[0])));
2661 return 1;
2662 }
2663
2664 if (reg_overlap_mentioned_p (operands[0], op0))
2665 {
2666 /* Handle the case where operands[0] == sparc_compare_op0.
2667 We "early clobber" the result. */
2668 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2669 emit_move_insn (op0, sparc_compare_op0);
2670 }
2671
2672 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2673 if (GET_MODE (op0) != DImode)
2674 {
2675 temp = gen_reg_rtx (DImode);
2676 convert_move (temp, op0, 0);
2677 }
2678 else
2679 temp = op0;
2680 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2681 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2682 gen_rtx_fmt_ee (compare_code, DImode,
2683 temp, const0_rtx),
2684 const1_rtx,
2685 operands[0])));
2686 return 1;
2687 }
2688 else
2689 {
2690 operands[1] = gen_compare_reg (compare_code, op0, op1);
2691
2692 switch (GET_MODE (operands[1]))
2693 {
2694 case CCmode :
2695 case CCXmode :
2696 case CCFPEmode :
2697 case CCFPmode :
2698 break;
2699 default :
2700 abort ();
2701 }
2702 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2703 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2704 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2705 gen_rtx_fmt_ee (compare_code,
2706 GET_MODE (operands[1]),
2707 operands[1], const0_rtx),
2708 const1_rtx, operands[0])));
2709 return 1;
2710 }
2711 }
2712
2713 /* Emit a conditional jump insn for the v9 architecture using comparison code
2714 CODE and jump target LABEL.
2715 This function exists to take advantage of the v9 brxx insns. */
2716
2717 void
2718 emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label)
2719 {
2720 emit_jump_insn (gen_rtx_SET (VOIDmode,
2721 pc_rtx,
2722 gen_rtx_IF_THEN_ELSE (VOIDmode,
2723 gen_rtx_fmt_ee (code, GET_MODE (op0),
2724 op0, const0_rtx),
2725 gen_rtx_LABEL_REF (VOIDmode, label),
2726 pc_rtx)));
2727 }
2728
2729 /* Generate a DFmode part of a hard TFmode register.
2730 REG is the TFmode hard register, LOW is 1 for the
2731 low 64bit of the register and 0 otherwise.
2732 */
2733 rtx
2734 gen_df_reg (rtx reg, int low)
2735 {
2736 int regno = REGNO (reg);
2737
2738 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2739 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
2740 return gen_rtx_REG (DFmode, regno);
2741 }
2742 \f
2743 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2744 Unlike normal calls, TFmode operands are passed by reference. It is
2745 assumed that no more than 3 operands are required. */
2746
2747 static void
2748 emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
2749 {
2750 rtx ret_slot = NULL, arg[3], func_sym;
2751 int i;
2752
2753 /* We only expect to be called for conversions, unary, and binary ops. */
2754 if (nargs < 2 || nargs > 3)
2755 abort ();
2756
2757 for (i = 0; i < nargs; ++i)
2758 {
2759 rtx this_arg = operands[i];
2760 rtx this_slot;
2761
2762 /* TFmode arguments and return values are passed by reference. */
2763 if (GET_MODE (this_arg) == TFmode)
2764 {
2765 int force_stack_temp;
2766
2767 force_stack_temp = 0;
2768 if (TARGET_BUGGY_QP_LIB && i == 0)
2769 force_stack_temp = 1;
2770
2771 if (GET_CODE (this_arg) == MEM
2772 && ! force_stack_temp)
2773 this_arg = XEXP (this_arg, 0);
2774 else if (CONSTANT_P (this_arg)
2775 && ! force_stack_temp)
2776 {
2777 this_slot = force_const_mem (TFmode, this_arg);
2778 this_arg = XEXP (this_slot, 0);
2779 }
2780 else
2781 {
2782 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2783
2784 /* Operand 0 is the return value. We'll copy it out later. */
2785 if (i > 0)
2786 emit_move_insn (this_slot, this_arg);
2787 else
2788 ret_slot = this_slot;
2789
2790 this_arg = XEXP (this_slot, 0);
2791 }
2792 }
2793
2794 arg[i] = this_arg;
2795 }
2796
2797 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2798
2799 if (GET_MODE (operands[0]) == TFmode)
2800 {
2801 if (nargs == 2)
2802 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2803 arg[0], GET_MODE (arg[0]),
2804 arg[1], GET_MODE (arg[1]));
2805 else
2806 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2807 arg[0], GET_MODE (arg[0]),
2808 arg[1], GET_MODE (arg[1]),
2809 arg[2], GET_MODE (arg[2]));
2810
2811 if (ret_slot)
2812 emit_move_insn (operands[0], ret_slot);
2813 }
2814 else
2815 {
2816 rtx ret;
2817
2818 if (nargs != 2)
2819 abort ();
2820
2821 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2822 GET_MODE (operands[0]), 1,
2823 arg[1], GET_MODE (arg[1]));
2824
2825 if (ret != operands[0])
2826 emit_move_insn (operands[0], ret);
2827 }
2828 }
2829
2830 /* Expand soft-float TFmode calls to sparc abi routines. */
2831
2832 static void
2833 emit_soft_tfmode_binop (enum rtx_code code, rtx *operands)
2834 {
2835 const char *func;
2836
2837 switch (code)
2838 {
2839 case PLUS:
2840 func = "_Qp_add";
2841 break;
2842 case MINUS:
2843 func = "_Qp_sub";
2844 break;
2845 case MULT:
2846 func = "_Qp_mul";
2847 break;
2848 case DIV:
2849 func = "_Qp_div";
2850 break;
2851 default:
2852 abort ();
2853 }
2854
2855 emit_soft_tfmode_libcall (func, 3, operands);
2856 }
2857
2858 static void
2859 emit_soft_tfmode_unop (enum rtx_code code, rtx *operands)
2860 {
2861 const char *func;
2862
2863 switch (code)
2864 {
2865 case SQRT:
2866 func = "_Qp_sqrt";
2867 break;
2868 default:
2869 abort ();
2870 }
2871
2872 emit_soft_tfmode_libcall (func, 2, operands);
2873 }
2874
2875 static void
2876 emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
2877 {
2878 const char *func;
2879
2880 switch (code)
2881 {
2882 case FLOAT_EXTEND:
2883 switch (GET_MODE (operands[1]))
2884 {
2885 case SFmode:
2886 func = "_Qp_stoq";
2887 break;
2888 case DFmode:
2889 func = "_Qp_dtoq";
2890 break;
2891 default:
2892 abort ();
2893 }
2894 break;
2895
2896 case FLOAT_TRUNCATE:
2897 switch (GET_MODE (operands[0]))
2898 {
2899 case SFmode:
2900 func = "_Qp_qtos";
2901 break;
2902 case DFmode:
2903 func = "_Qp_qtod";
2904 break;
2905 default:
2906 abort ();
2907 }
2908 break;
2909
2910 case FLOAT:
2911 switch (GET_MODE (operands[1]))
2912 {
2913 case SImode:
2914 func = "_Qp_itoq";
2915 break;
2916 case DImode:
2917 func = "_Qp_xtoq";
2918 break;
2919 default:
2920 abort ();
2921 }
2922 break;
2923
2924 case UNSIGNED_FLOAT:
2925 switch (GET_MODE (operands[1]))
2926 {
2927 case SImode:
2928 func = "_Qp_uitoq";
2929 break;
2930 case DImode:
2931 func = "_Qp_uxtoq";
2932 break;
2933 default:
2934 abort ();
2935 }
2936 break;
2937
2938 case FIX:
2939 switch (GET_MODE (operands[0]))
2940 {
2941 case SImode:
2942 func = "_Qp_qtoi";
2943 break;
2944 case DImode:
2945 func = "_Qp_qtox";
2946 break;
2947 default:
2948 abort ();
2949 }
2950 break;
2951
2952 case UNSIGNED_FIX:
2953 switch (GET_MODE (operands[0]))
2954 {
2955 case SImode:
2956 func = "_Qp_qtoui";
2957 break;
2958 case DImode:
2959 func = "_Qp_qtoux";
2960 break;
2961 default:
2962 abort ();
2963 }
2964 break;
2965
2966 default:
2967 abort ();
2968 }
2969
2970 emit_soft_tfmode_libcall (func, 2, operands);
2971 }
2972
2973 /* Expand a hard-float tfmode operation. All arguments must be in
2974 registers. */
2975
2976 static void
2977 emit_hard_tfmode_operation (enum rtx_code code, rtx *operands)
2978 {
2979 rtx op, dest;
2980
2981 if (GET_RTX_CLASS (code) == RTX_UNARY)
2982 {
2983 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2984 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2985 }
2986 else
2987 {
2988 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2989 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2990 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2991 operands[1], operands[2]);
2992 }
2993
2994 if (register_operand (operands[0], VOIDmode))
2995 dest = operands[0];
2996 else
2997 dest = gen_reg_rtx (GET_MODE (operands[0]));
2998
2999 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
3000
3001 if (dest != operands[0])
3002 emit_move_insn (operands[0], dest);
3003 }
3004
3005 void
3006 emit_tfmode_binop (enum rtx_code code, rtx *operands)
3007 {
3008 if (TARGET_HARD_QUAD)
3009 emit_hard_tfmode_operation (code, operands);
3010 else
3011 emit_soft_tfmode_binop (code, operands);
3012 }
3013
3014 void
3015 emit_tfmode_unop (enum rtx_code code, rtx *operands)
3016 {
3017 if (TARGET_HARD_QUAD)
3018 emit_hard_tfmode_operation (code, operands);
3019 else
3020 emit_soft_tfmode_unop (code, operands);
3021 }
3022
3023 void
3024 emit_tfmode_cvt (enum rtx_code code, rtx *operands)
3025 {
3026 if (TARGET_HARD_QUAD)
3027 emit_hard_tfmode_operation (code, operands);
3028 else
3029 emit_soft_tfmode_cvt (code, operands);
3030 }
3031 \f
3032 /* Return nonzero if a branch/jump/call instruction will be emitting
3033 nop into its delay slot. */
3034
3035 int
3036 empty_delay_slot (rtx insn)
3037 {
3038 rtx seq;
3039
3040 /* If no previous instruction (should not happen), return true. */
3041 if (PREV_INSN (insn) == NULL)
3042 return 1;
3043
3044 seq = NEXT_INSN (PREV_INSN (insn));
3045 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
3046 return 0;
3047
3048 return 1;
3049 }
3050
3051 /* Return nonzero if TRIAL can go into the call delay slot. */
3052
3053 int
3054 tls_call_delay (rtx trial)
3055 {
3056 rtx pat, unspec;
3057
3058 /* Binutils allows
3059 call __tls_get_addr, %tgd_call (foo)
3060 add %l7, %o0, %o0, %tgd_add (foo)
3061 while Sun as/ld does not. */
3062 if (TARGET_GNU_TLS || !TARGET_TLS)
3063 return 1;
3064
3065 pat = PATTERN (trial);
3066 if (GET_CODE (pat) != SET || GET_CODE (SET_DEST (pat)) != PLUS)
3067 return 1;
3068
3069 unspec = XEXP (SET_DEST (pat), 1);
3070 if (GET_CODE (unspec) != UNSPEC
3071 || (XINT (unspec, 1) != UNSPEC_TLSGD
3072 && XINT (unspec, 1) != UNSPEC_TLSLDM))
3073 return 1;
3074
3075 return 0;
3076 }
3077
3078 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
3079 instruction. RETURN_P is true if the v9 variant 'return' is to be
3080 considered in the test too.
3081
3082 TRIAL must be a SET whose destination is a REG appropriate for the
3083 'restore' instruction or, if RETURN_P is true, for the 'return'
3084 instruction. */
3085
3086 static int
3087 eligible_for_restore_insn (rtx trial, bool return_p)
3088 {
3089 rtx pat = PATTERN (trial);
3090 rtx src = SET_SRC (pat);
3091
3092 /* The 'restore src,%g0,dest' pattern for word mode and below. */
3093 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
3094 && arith_operand (src, GET_MODE (src)))
3095 {
3096 if (TARGET_ARCH64)
3097 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3098 else
3099 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
3100 }
3101
3102 /* The 'restore src,%g0,dest' pattern for double-word mode. */
3103 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
3104 && arith_double_operand (src, GET_MODE (src)))
3105 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3106
3107 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
3108 else if (! TARGET_FPU && register_operand (src, SFmode))
3109 return 1;
3110
3111 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
3112 else if (! TARGET_FPU && TARGET_ARCH64 && register_operand (src, DFmode))
3113 return 1;
3114
3115 /* If we have the 'return' instruction, anything that does not use
3116 local or output registers and can go into a delay slot wins. */
3117 else if (return_p && TARGET_V9 && ! epilogue_renumber (&pat, 1)
3118 && (get_attr_in_uncond_branch_delay (trial)
3119 == IN_UNCOND_BRANCH_DELAY_TRUE))
3120 return 1;
3121
3122 /* The 'restore src1,src2,dest' pattern for SImode. */
3123 else if (GET_CODE (src) == PLUS
3124 && register_operand (XEXP (src, 0), SImode)
3125 && arith_operand (XEXP (src, 1), SImode))
3126 return 1;
3127
3128 /* The 'restore src1,src2,dest' pattern for DImode. */
3129 else if (GET_CODE (src) == PLUS
3130 && register_operand (XEXP (src, 0), DImode)
3131 && arith_double_operand (XEXP (src, 1), DImode))
3132 return 1;
3133
3134 /* The 'restore src1,%lo(src2),dest' pattern. */
3135 else if (GET_CODE (src) == LO_SUM
3136 && ! TARGET_CM_MEDMID
3137 && ((register_operand (XEXP (src, 0), SImode)
3138 && immediate_operand (XEXP (src, 1), SImode))
3139 || (TARGET_ARCH64
3140 && register_operand (XEXP (src, 0), DImode)
3141 && immediate_operand (XEXP (src, 1), DImode))))
3142 return 1;
3143
3144 /* The 'restore src,src,dest' pattern. */
3145 else if (GET_CODE (src) == ASHIFT
3146 && (register_operand (XEXP (src, 0), SImode)
3147 || register_operand (XEXP (src, 0), DImode))
3148 && XEXP (src, 1) == const1_rtx)
3149 return 1;
3150
3151 return 0;
3152 }
3153
3154 /* Return nonzero if TRIAL can go into the function return's
3155 delay slot. */
3156
3157 int
3158 eligible_for_return_delay (rtx trial)
3159 {
3160 rtx pat;
3161
3162 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
3163 return 0;
3164
3165 if (get_attr_length (trial) != 1)
3166 return 0;
3167
3168 /* If there are any call-saved registers, we should scan TRIAL if it
3169 does not reference them. For now just make it easy. */
3170 if (num_gfregs)
3171 return 0;
3172
3173 /* If the function uses __builtin_eh_return, the eh_return machinery
3174 occupies the delay slot. */
3175 if (current_function_calls_eh_return)
3176 return 0;
3177
3178 /* In the case of a true leaf function, anything can go into the slot. */
3179 if (sparc_leaf_function_p)
3180 return get_attr_in_uncond_branch_delay (trial)
3181 == IN_UNCOND_BRANCH_DELAY_TRUE;
3182
3183 pat = PATTERN (trial);
3184
3185 /* Otherwise, only operations which can be done in tandem with
3186 a `restore' or `return' insn can go into the delay slot. */
3187 if (GET_CODE (SET_DEST (pat)) != REG
3188 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24))
3189 return 0;
3190
3191 /* If this instruction sets up floating point register and we have a return
3192 instruction, it can probably go in. But restore will not work
3193 with FP_REGS. */
3194 if (REGNO (SET_DEST (pat)) >= 32)
3195 return (TARGET_V9
3196 && ! epilogue_renumber (&pat, 1)
3197 && (get_attr_in_uncond_branch_delay (trial)
3198 == IN_UNCOND_BRANCH_DELAY_TRUE));
3199
3200 return eligible_for_restore_insn (trial, true);
3201 }
3202
3203 /* Return nonzero if TRIAL can go into the sibling call's
3204 delay slot. */
3205
3206 int
3207 eligible_for_sibcall_delay (rtx trial)
3208 {
3209 rtx pat;
3210
3211 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
3212 return 0;
3213
3214 if (get_attr_length (trial) != 1)
3215 return 0;
3216
3217 pat = PATTERN (trial);
3218
3219 if (sparc_leaf_function_p)
3220 {
3221 /* If the tail call is done using the call instruction,
3222 we have to restore %o7 in the delay slot. */
3223 if (LEAF_SIBCALL_SLOT_RESERVED_P)
3224 return 0;
3225
3226 /* %g1 is used to build the function address */
3227 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
3228 return 0;
3229
3230 return 1;
3231 }
3232
3233 /* Otherwise, only operations which can be done in tandem with
3234 a `restore' insn can go into the delay slot. */
3235 if (GET_CODE (SET_DEST (pat)) != REG
3236 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24)
3237 || REGNO (SET_DEST (pat)) >= 32)
3238 return 0;
3239
3240 /* If it mentions %o7, it can't go in, because sibcall will clobber it
3241 in most cases. */
3242 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
3243 return 0;
3244
3245 return eligible_for_restore_insn (trial, false);
3246 }
3247
3248 int
3249 short_branch (int uid1, int uid2)
3250 {
3251 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
3252
3253 /* Leave a few words of "slop". */
3254 if (delta >= -1023 && delta <= 1022)
3255 return 1;
3256
3257 return 0;
3258 }
3259
3260 /* Return nonzero if REG is not used after INSN.
3261 We assume REG is a reload reg, and therefore does
3262 not live past labels or calls or jumps. */
3263 int
3264 reg_unused_after (rtx reg, rtx insn)
3265 {
3266 enum rtx_code code, prev_code = UNKNOWN;
3267
3268 while ((insn = NEXT_INSN (insn)))
3269 {
3270 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
3271 return 1;
3272
3273 code = GET_CODE (insn);
3274 if (GET_CODE (insn) == CODE_LABEL)
3275 return 1;
3276
3277 if (INSN_P (insn))
3278 {
3279 rtx set = single_set (insn);
3280 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
3281 if (set && in_src)
3282 return 0;
3283 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
3284 return 1;
3285 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
3286 return 0;
3287 }
3288 prev_code = code;
3289 }
3290 return 1;
3291 }
3292 \f
3293 /* Determine if it's legal to put X into the constant pool. This
3294 is not possible if X contains the address of a symbol that is
3295 not constant (TLS) or not known at final link time (PIC). */
3296
3297 static bool
3298 sparc_cannot_force_const_mem (rtx x)
3299 {
3300 switch (GET_CODE (x))
3301 {
3302 case CONST_INT:
3303 case CONST_DOUBLE:
3304 case CONST_VECTOR:
3305 /* Accept all non-symbolic constants. */
3306 return false;
3307
3308 case LABEL_REF:
3309 /* Labels are OK iff we are non-PIC. */
3310 return flag_pic != 0;
3311
3312 case SYMBOL_REF:
3313 /* 'Naked' TLS symbol references are never OK,
3314 non-TLS symbols are OK iff we are non-PIC. */
3315 if (SYMBOL_REF_TLS_MODEL (x))
3316 return true;
3317 else
3318 return flag_pic != 0;
3319
3320 case CONST:
3321 return sparc_cannot_force_const_mem (XEXP (x, 0));
3322 case PLUS:
3323 case MINUS:
3324 return sparc_cannot_force_const_mem (XEXP (x, 0))
3325 || sparc_cannot_force_const_mem (XEXP (x, 1));
3326 case UNSPEC:
3327 return true;
3328 default:
3329 abort ();
3330 }
3331 }
3332 \f
3333 /* The table we use to reference PIC data. */
3334 static GTY(()) rtx global_offset_table;
3335
3336 /* The function we use to get at it. */
3337 static GTY(()) rtx add_pc_to_pic_symbol;
3338 static GTY(()) char add_pc_to_pic_symbol_name[256];
3339
3340 /* Ensure that we are not using patterns that are not OK with PIC. */
3341
3342 int
3343 check_pic (int i)
3344 {
3345 switch (flag_pic)
3346 {
3347 case 1:
3348 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF
3349 || (GET_CODE (recog_data.operand[i]) == CONST
3350 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
3351 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
3352 == global_offset_table)
3353 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
3354 == CONST))))
3355 abort ();
3356 case 2:
3357 default:
3358 return 1;
3359 }
3360 }
3361
3362 /* Return true if X is an address which needs a temporary register when
3363 reloaded while generating PIC code. */
3364
3365 int
3366 pic_address_needs_scratch (rtx x)
3367 {
3368 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3369 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3370 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3371 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3372 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3373 return 1;
3374
3375 return 0;
3376 }
3377
3378 /* Determine if a given RTX is a valid constant. We already know this
3379 satisfies CONSTANT_P. */
3380
3381 bool
3382 legitimate_constant_p (rtx x)
3383 {
3384 rtx inner;
3385
3386 switch (GET_CODE (x))
3387 {
3388 case SYMBOL_REF:
3389 /* TLS symbols are not constant. */
3390 if (SYMBOL_REF_TLS_MODEL (x))
3391 return false;
3392 break;
3393
3394 case CONST:
3395 inner = XEXP (x, 0);
3396
3397 /* Offsets of TLS symbols are never valid.
3398 Discourage CSE from creating them. */
3399 if (GET_CODE (inner) == PLUS
3400 && tls_symbolic_operand (XEXP (inner, 0)))
3401 return false;
3402 break;
3403
3404 case CONST_DOUBLE:
3405 if (GET_MODE (x) == VOIDmode)
3406 return true;
3407
3408 /* Floating point constants are generally not ok.
3409 The only exception is 0.0 in VIS. */
3410 if (TARGET_VIS
3411 && (GET_MODE (x) == SFmode
3412 || GET_MODE (x) == DFmode
3413 || GET_MODE (x) == TFmode)
3414 && fp_zero_operand (x, GET_MODE (x)))
3415 return true;
3416
3417 return false;
3418
3419 default:
3420 break;
3421 }
3422
3423 return true;
3424 }
3425
3426 /* Determine if a given RTX is a valid constant address. */
3427
3428 bool
3429 constant_address_p (rtx x)
3430 {
3431 switch (GET_CODE (x))
3432 {
3433 case LABEL_REF:
3434 case CONST_INT:
3435 case HIGH:
3436 return true;
3437
3438 case CONST:
3439 if (flag_pic && pic_address_needs_scratch (x))
3440 return false;
3441 return legitimate_constant_p (x);
3442
3443 case SYMBOL_REF:
3444 return !flag_pic && legitimate_constant_p (x);
3445
3446 default:
3447 return false;
3448 }
3449 }
3450
3451 /* Nonzero if the constant value X is a legitimate general operand
3452 when generating PIC code. It is given that flag_pic is on and
3453 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3454
3455 bool
3456 legitimate_pic_operand_p (rtx x)
3457 {
3458 if (pic_address_needs_scratch (x))
3459 return false;
3460 if (tls_symbolic_operand (x)
3461 || (GET_CODE (x) == CONST
3462 && GET_CODE (XEXP (x, 0)) == PLUS
3463 && tls_symbolic_operand (XEXP (XEXP (x, 0), 0))))
3464 return false;
3465 return true;
3466 }
3467
3468 /* Return nonzero if ADDR is a valid memory address.
3469 STRICT specifies whether strict register checking applies. */
3470
3471 int
3472 legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
3473 {
3474 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL, imm2;
3475
3476 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
3477 rs1 = addr;
3478 else if (GET_CODE (addr) == PLUS)
3479 {
3480 rs1 = XEXP (addr, 0);
3481 rs2 = XEXP (addr, 1);
3482
3483 /* Canonicalize. REG comes first, if there are no regs,
3484 LO_SUM comes first. */
3485 if (!REG_P (rs1)
3486 && GET_CODE (rs1) != SUBREG
3487 && (REG_P (rs2)
3488 || GET_CODE (rs2) == SUBREG
3489 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
3490 {
3491 rs1 = XEXP (addr, 1);
3492 rs2 = XEXP (addr, 0);
3493 }
3494
3495 if ((flag_pic == 1
3496 && rs1 == pic_offset_table_rtx
3497 && !REG_P (rs2)
3498 && GET_CODE (rs2) != SUBREG
3499 && GET_CODE (rs2) != LO_SUM
3500 && GET_CODE (rs2) != MEM
3501 && !tls_symbolic_operand (rs2)
3502 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
3503 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
3504 || ((REG_P (rs1)
3505 || GET_CODE (rs1) == SUBREG)
3506 && RTX_OK_FOR_OFFSET_P (rs2)))
3507 {
3508 imm1 = rs2;
3509 rs2 = NULL;
3510 }
3511 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
3512 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
3513 {
3514 /* We prohibit REG + REG for TFmode when there are no quad move insns
3515 and we consequently need to split. We do this because REG+REG
3516 is not an offsettable address. If we get the situation in reload
3517 where source and destination of a movtf pattern are both MEMs with
3518 REG+REG address, then only one of them gets converted to an
3519 offsettable address. */
3520 if (mode == TFmode
3521 && ! (TARGET_FPU && TARGET_ARCH64 && TARGET_HARD_QUAD))
3522 return 0;
3523
3524 /* We prohibit REG + REG on ARCH32 if not optimizing for
3525 DFmode/DImode because then mem_min_alignment is likely to be zero
3526 after reload and the forced split would lack a matching splitter
3527 pattern. */
3528 if (TARGET_ARCH32 && !optimize
3529 && (mode == DFmode || mode == DImode))
3530 return 0;
3531 }
3532 else if (USE_AS_OFFSETABLE_LO10
3533 && GET_CODE (rs1) == LO_SUM
3534 && TARGET_ARCH64
3535 && ! TARGET_CM_MEDMID
3536 && RTX_OK_FOR_OLO10_P (rs2))
3537 {
3538 imm2 = rs2;
3539 rs2 = NULL;
3540 imm1 = XEXP (rs1, 1);
3541 rs1 = XEXP (rs1, 0);
3542 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3543 return 0;
3544 }
3545 }
3546 else if (GET_CODE (addr) == LO_SUM)
3547 {
3548 rs1 = XEXP (addr, 0);
3549 imm1 = XEXP (addr, 1);
3550
3551 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3552 return 0;
3553
3554 if (USE_AS_OFFSETABLE_LO10)
3555 {
3556 /* We can't allow TFmode, because an offset greater than or equal to
3557 the alignment (8) may cause the LO_SUM to overflow if !v9. */
3558 if (mode == TFmode && ! TARGET_V9)
3559 return 0;
3560 }
3561 else
3562 {
3563 /* We prohibit LO_SUM for TFmode when there are no quad move insns
3564 and we consequently need to split. We do this because LO_SUM
3565 is not an offsettable address. If we get the situation in reload
3566 where source and destination of a movtf pattern are both MEMs with
3567 LO_SUM address, then only one of them gets converted to an
3568 offsettable address. */
3569 if (mode == TFmode
3570 && ! (TARGET_FPU && TARGET_ARCH64 && TARGET_HARD_QUAD))
3571 return 0;
3572 }
3573 }
3574 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
3575 return 1;
3576 else
3577 return 0;
3578
3579 if (GET_CODE (rs1) == SUBREG)
3580 rs1 = SUBREG_REG (rs1);
3581 if (!REG_P (rs1))
3582 return 0;
3583
3584 if (rs2)
3585 {
3586 if (GET_CODE (rs2) == SUBREG)
3587 rs2 = SUBREG_REG (rs2);
3588 if (!REG_P (rs2))
3589 return 0;
3590 }
3591
3592 if (strict)
3593 {
3594 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
3595 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
3596 return 0;
3597 }
3598 else
3599 {
3600 if ((REGNO (rs1) >= 32
3601 && REGNO (rs1) != FRAME_POINTER_REGNUM
3602 && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
3603 || (rs2
3604 && (REGNO (rs2) >= 32
3605 && REGNO (rs2) != FRAME_POINTER_REGNUM
3606 && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
3607 return 0;
3608 }
3609 return 1;
3610 }
3611
3612 /* Construct the SYMBOL_REF for the tls_get_offset function. */
3613
3614 static GTY(()) rtx sparc_tls_symbol;
3615 static rtx
3616 sparc_tls_get_addr (void)
3617 {
3618 if (!sparc_tls_symbol)
3619 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
3620
3621 return sparc_tls_symbol;
3622 }
3623
3624 static rtx
3625 sparc_tls_got (void)
3626 {
3627 rtx temp;
3628 if (flag_pic)
3629 {
3630 current_function_uses_pic_offset_table = 1;
3631 return pic_offset_table_rtx;
3632 }
3633
3634 if (!global_offset_table)
3635 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3636 temp = gen_reg_rtx (Pmode);
3637 emit_move_insn (temp, global_offset_table);
3638 return temp;
3639 }
3640
3641
3642 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3643 this (thread-local) address. */
3644
3645 rtx
3646 legitimize_tls_address (rtx addr)
3647 {
3648 rtx temp1, temp2, temp3, ret, o0, got, insn;
3649
3650 if (no_new_pseudos)
3651 abort ();
3652
3653 if (GET_CODE (addr) == SYMBOL_REF)
3654 switch (SYMBOL_REF_TLS_MODEL (addr))
3655 {
3656 case TLS_MODEL_GLOBAL_DYNAMIC:
3657 start_sequence ();
3658 temp1 = gen_reg_rtx (SImode);
3659 temp2 = gen_reg_rtx (SImode);
3660 ret = gen_reg_rtx (Pmode);
3661 o0 = gen_rtx_REG (Pmode, 8);
3662 got = sparc_tls_got ();
3663 emit_insn (gen_tgd_hi22 (temp1, addr));
3664 emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
3665 if (TARGET_ARCH32)
3666 {
3667 emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
3668 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (),
3669 addr, const1_rtx));
3670 }
3671 else
3672 {
3673 emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
3674 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (),
3675 addr, const1_rtx));
3676 }
3677 CALL_INSN_FUNCTION_USAGE (insn)
3678 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3679 CALL_INSN_FUNCTION_USAGE (insn));
3680 insn = get_insns ();
3681 end_sequence ();
3682 emit_libcall_block (insn, ret, o0, addr);
3683 break;
3684
3685 case TLS_MODEL_LOCAL_DYNAMIC:
3686 start_sequence ();
3687 temp1 = gen_reg_rtx (SImode);
3688 temp2 = gen_reg_rtx (SImode);
3689 temp3 = gen_reg_rtx (Pmode);
3690 ret = gen_reg_rtx (Pmode);
3691 o0 = gen_rtx_REG (Pmode, 8);
3692 got = sparc_tls_got ();
3693 emit_insn (gen_tldm_hi22 (temp1));
3694 emit_insn (gen_tldm_lo10 (temp2, temp1));
3695 if (TARGET_ARCH32)
3696 {
3697 emit_insn (gen_tldm_add32 (o0, got, temp2));
3698 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (),
3699 const1_rtx));
3700 }
3701 else
3702 {
3703 emit_insn (gen_tldm_add64 (o0, got, temp2));
3704 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (),
3705 const1_rtx));
3706 }
3707 CALL_INSN_FUNCTION_USAGE (insn)
3708 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3709 CALL_INSN_FUNCTION_USAGE (insn));
3710 insn = get_insns ();
3711 end_sequence ();
3712 emit_libcall_block (insn, temp3, o0,
3713 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3714 UNSPEC_TLSLD_BASE));
3715 temp1 = gen_reg_rtx (SImode);
3716 temp2 = gen_reg_rtx (SImode);
3717 emit_insn (gen_tldo_hix22 (temp1, addr));
3718 emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
3719 if (TARGET_ARCH32)
3720 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
3721 else
3722 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
3723 break;
3724
3725 case TLS_MODEL_INITIAL_EXEC:
3726 temp1 = gen_reg_rtx (SImode);
3727 temp2 = gen_reg_rtx (SImode);
3728 temp3 = gen_reg_rtx (Pmode);
3729 got = sparc_tls_got ();
3730 emit_insn (gen_tie_hi22 (temp1, addr));
3731 emit_insn (gen_tie_lo10 (temp2, temp1, addr));
3732 if (TARGET_ARCH32)
3733 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
3734 else
3735 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
3736 if (TARGET_SUN_TLS)
3737 {
3738 ret = gen_reg_rtx (Pmode);
3739 if (TARGET_ARCH32)
3740 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7),
3741 temp3, addr));
3742 else
3743 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7),
3744 temp3, addr));
3745 }
3746 else
3747 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
3748 break;
3749
3750 case TLS_MODEL_LOCAL_EXEC:
3751 temp1 = gen_reg_rtx (Pmode);
3752 temp2 = gen_reg_rtx (Pmode);
3753 if (TARGET_ARCH32)
3754 {
3755 emit_insn (gen_tle_hix22_sp32 (temp1, addr));
3756 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
3757 }
3758 else
3759 {
3760 emit_insn (gen_tle_hix22_sp64 (temp1, addr));
3761 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
3762 }
3763 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
3764 break;
3765
3766 default:
3767 abort ();
3768 }
3769
3770 else
3771 abort (); /* for now ... */
3772
3773 return ret;
3774 }
3775
3776
3777 /* Legitimize PIC addresses. If the address is already position-independent,
3778 we return ORIG. Newly generated position-independent addresses go into a
3779 reg. This is REG if nonzero, otherwise we allocate register(s) as
3780 necessary. */
3781
3782 rtx
3783 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
3784 rtx reg)
3785 {
3786 if (GET_CODE (orig) == SYMBOL_REF)
3787 {
3788 rtx pic_ref, address;
3789 rtx insn;
3790
3791 if (reg == 0)
3792 {
3793 if (reload_in_progress || reload_completed)
3794 abort ();
3795 else
3796 reg = gen_reg_rtx (Pmode);
3797 }
3798
3799 if (flag_pic == 2)
3800 {
3801 /* If not during reload, allocate another temp reg here for loading
3802 in the address, so that these instructions can be optimized
3803 properly. */
3804 rtx temp_reg = ((reload_in_progress || reload_completed)
3805 ? reg : gen_reg_rtx (Pmode));
3806
3807 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3808 won't get confused into thinking that these two instructions
3809 are loading in the true address of the symbol. If in the
3810 future a PIC rtx exists, that should be used instead. */
3811 if (Pmode == SImode)
3812 {
3813 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3814 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
3815 }
3816 else
3817 {
3818 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3819 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
3820 }
3821 address = temp_reg;
3822 }
3823 else
3824 address = orig;
3825
3826 pic_ref = gen_const_mem (Pmode,
3827 gen_rtx_PLUS (Pmode,
3828 pic_offset_table_rtx, address));
3829 current_function_uses_pic_offset_table = 1;
3830 insn = emit_move_insn (reg, pic_ref);
3831 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3832 by loop. */
3833 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
3834 REG_NOTES (insn));
3835 return reg;
3836 }
3837 else if (GET_CODE (orig) == CONST)
3838 {
3839 rtx base, offset;
3840
3841 if (GET_CODE (XEXP (orig, 0)) == PLUS
3842 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3843 return orig;
3844
3845 if (reg == 0)
3846 {
3847 if (reload_in_progress || reload_completed)
3848 abort ();
3849 else
3850 reg = gen_reg_rtx (Pmode);
3851 }
3852
3853 if (GET_CODE (XEXP (orig, 0)) == PLUS)
3854 {
3855 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3856 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3857 base == reg ? 0 : reg);
3858 }
3859 else
3860 abort ();
3861
3862 if (GET_CODE (offset) == CONST_INT)
3863 {
3864 if (SMALL_INT (offset))
3865 return plus_constant (base, INTVAL (offset));
3866 else if (! reload_in_progress && ! reload_completed)
3867 offset = force_reg (Pmode, offset);
3868 else
3869 /* If we reach here, then something is seriously wrong. */
3870 abort ();
3871 }
3872 return gen_rtx_PLUS (Pmode, base, offset);
3873 }
3874 else if (GET_CODE (orig) == LABEL_REF)
3875 /* ??? Why do we do this? */
3876 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3877 the register is live instead, in case it is eliminated. */
3878 current_function_uses_pic_offset_table = 1;
3879
3880 return orig;
3881 }
3882
3883 /* Try machine-dependent ways of modifying an illegitimate address X
3884 to be legitimate. If we find one, return the new, valid address.
3885
3886 OLDX is the address as it was before break_out_memory_refs was called.
3887 In some cases it is useful to look at this to decide what needs to be done.
3888
3889 MODE is the mode of the operand pointed to by X. */
3890
3891 rtx
3892 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
3893 {
3894 rtx orig_x = x;
3895
3896 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT)
3897 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3898 force_operand (XEXP (x, 0), NULL_RTX));
3899 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT)
3900 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3901 force_operand (XEXP (x, 1), NULL_RTX));
3902 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS)
3903 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX),
3904 XEXP (x, 1));
3905 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS)
3906 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3907 force_operand (XEXP (x, 1), NULL_RTX));
3908
3909 if (x != orig_x && legitimate_address_p (mode, x, FALSE))
3910 return x;
3911
3912 if (tls_symbolic_operand (x))
3913 x = legitimize_tls_address (x);
3914 else if (flag_pic)
3915 x = legitimize_pic_address (x, mode, 0);
3916 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1)))
3917 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3918 copy_to_mode_reg (Pmode, XEXP (x, 1)));
3919 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0)))
3920 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3921 copy_to_mode_reg (Pmode, XEXP (x, 0)));
3922 else if (GET_CODE (x) == SYMBOL_REF
3923 || GET_CODE (x) == CONST
3924 || GET_CODE (x) == LABEL_REF)
3925 x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
3926 return x;
3927 }
3928
3929 /* Emit the special PIC prologue. */
3930
3931 static void
3932 load_pic_register (void)
3933 {
3934 int orig_flag_pic = flag_pic;
3935
3936 /* If we haven't emitted the special helper function, do so now. */
3937 if (add_pc_to_pic_symbol_name[0] == 0)
3938 {
3939 const char *pic_name = reg_names[REGNO (pic_offset_table_rtx)];
3940 int align;
3941
3942 ASM_GENERATE_INTERNAL_LABEL (add_pc_to_pic_symbol_name, "LADDPC", 0);
3943 text_section ();
3944
3945 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
3946 if (align > 0)
3947 ASM_OUTPUT_ALIGN (asm_out_file, align);
3948 ASM_OUTPUT_LABEL (asm_out_file, add_pc_to_pic_symbol_name);
3949 if (flag_delayed_branch)
3950 fprintf (asm_out_file, "\tjmp %%o7+8\n\t add\t%%o7, %s, %s\n",
3951 pic_name, pic_name);
3952 else
3953 fprintf (asm_out_file, "\tadd\t%%o7, %s, %s\n\tjmp %%o7+8\n\t nop\n",
3954 pic_name, pic_name);
3955 }
3956
3957 /* Initialize every time through, since we can't easily
3958 know this to be permanent. */
3959 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3960 add_pc_to_pic_symbol = gen_rtx_SYMBOL_REF (Pmode, add_pc_to_pic_symbol_name);
3961
3962 flag_pic = 0;
3963 emit_insn (gen_load_pcrel_sym (pic_offset_table_rtx, global_offset_table,
3964 add_pc_to_pic_symbol));
3965 flag_pic = orig_flag_pic;
3966
3967 /* Need to emit this whether or not we obey regdecls,
3968 since setjmp/longjmp can cause life info to screw up.
3969 ??? In the case where we don't obey regdecls, this is not sufficient
3970 since we may not fall out the bottom. */
3971 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
3972 }
3973 \f
3974 /* Return 1 if RTX is a MEM which is known to be aligned to at
3975 least a DESIRED byte boundary. */
3976
3977 int
3978 mem_min_alignment (rtx mem, int desired)
3979 {
3980 rtx addr, base, offset;
3981
3982 /* If it's not a MEM we can't accept it. */
3983 if (GET_CODE (mem) != MEM)
3984 return 0;
3985
3986 /* Obviously... */
3987 if (MEM_ALIGN (mem) / BITS_PER_UNIT >= (unsigned)desired)
3988 return 1;
3989
3990 /* ??? The rest of the function predates MEM_ALIGN so
3991 there is probably a bit of redundancy. */
3992 addr = XEXP (mem, 0);
3993 base = offset = NULL_RTX;
3994 if (GET_CODE (addr) == PLUS)
3995 {
3996 if (GET_CODE (XEXP (addr, 0)) == REG)
3997 {
3998 base = XEXP (addr, 0);
3999
4000 /* What we are saying here is that if the base
4001 REG is aligned properly, the compiler will make
4002 sure any REG based index upon it will be so
4003 as well. */
4004 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
4005 offset = XEXP (addr, 1);
4006 else
4007 offset = const0_rtx;
4008 }
4009 }
4010 else if (GET_CODE (addr) == REG)
4011 {
4012 base = addr;
4013 offset = const0_rtx;
4014 }
4015
4016 if (base != NULL_RTX)
4017 {
4018 int regno = REGNO (base);
4019
4020 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
4021 {
4022 /* Check if the compiler has recorded some information
4023 about the alignment of the base REG. If reload has
4024 completed, we already matched with proper alignments.
4025 If not running global_alloc, reload might give us
4026 unaligned pointer to local stack though. */
4027 if (((cfun != 0
4028 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
4029 || (optimize && reload_completed))
4030 && (INTVAL (offset) & (desired - 1)) == 0)
4031 return 1;
4032 }
4033 else
4034 {
4035 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
4036 return 1;
4037 }
4038 }
4039 else if (! TARGET_UNALIGNED_DOUBLES
4040 || CONSTANT_P (addr)
4041 || GET_CODE (addr) == LO_SUM)
4042 {
4043 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
4044 is true, in which case we can only assume that an access is aligned if
4045 it is to a constant address, or the address involves a LO_SUM. */
4046 return 1;
4047 }
4048
4049 /* An obviously unaligned address. */
4050 return 0;
4051 }
4052
4053 \f
4054 /* Vectors to keep interesting information about registers where it can easily
4055 be got. We used to use the actual mode value as the bit number, but there
4056 are more than 32 modes now. Instead we use two tables: one indexed by
4057 hard register number, and one indexed by mode. */
4058
4059 /* The purpose of sparc_mode_class is to shrink the range of modes so that
4060 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
4061 mapped into one sparc_mode_class mode. */
4062
4063 enum sparc_mode_class {
4064 S_MODE, D_MODE, T_MODE, O_MODE,
4065 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
4066 CC_MODE, CCFP_MODE
4067 };
4068
4069 /* Modes for single-word and smaller quantities. */
4070 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
4071
4072 /* Modes for double-word and smaller quantities. */
4073 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
4074
4075 /* Modes for quad-word and smaller quantities. */
4076 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
4077
4078 /* Modes for 8-word and smaller quantities. */
4079 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
4080
4081 /* Modes for single-float quantities. We must allow any single word or
4082 smaller quantity. This is because the fix/float conversion instructions
4083 take integer inputs/outputs from the float registers. */
4084 #define SF_MODES (S_MODES)
4085
4086 /* Modes for double-float and smaller quantities. */
4087 #define DF_MODES (S_MODES | D_MODES)
4088
4089 /* Modes for double-float only quantities. */
4090 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
4091
4092 /* Modes for quad-float only quantities. */
4093 #define TF_ONLY_MODES (1 << (int) TF_MODE)
4094
4095 /* Modes for quad-float and smaller quantities. */
4096 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
4097
4098 /* Modes for quad-float and double-float quantities. */
4099 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
4100
4101 /* Modes for quad-float pair only quantities. */
4102 #define OF_ONLY_MODES (1 << (int) OF_MODE)
4103
4104 /* Modes for quad-float pairs and smaller quantities. */
4105 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
4106
4107 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
4108
4109 /* Modes for condition codes. */
4110 #define CC_MODES (1 << (int) CC_MODE)
4111 #define CCFP_MODES (1 << (int) CCFP_MODE)
4112
4113 /* Value is 1 if register/mode pair is acceptable on sparc.
4114 The funny mixture of D and T modes is because integer operations
4115 do not specially operate on tetra quantities, so non-quad-aligned
4116 registers can hold quadword quantities (except %o4 and %i4 because
4117 they cross fixed registers). */
4118
4119 /* This points to either the 32 bit or the 64 bit version. */
4120 const int *hard_regno_mode_classes;
4121
4122 static const int hard_32bit_mode_classes[] = {
4123 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
4124 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
4125 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
4126 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
4127
4128 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4129 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4130 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4131 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
4132
4133 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4134 and none can hold SFmode/SImode values. */
4135 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4136 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4137 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4138 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4139
4140 /* %fcc[0123] */
4141 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
4142
4143 /* %icc */
4144 CC_MODES
4145 };
4146
4147 static const int hard_64bit_mode_classes[] = {
4148 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4149 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4150 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4151 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4152
4153 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4154 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4155 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4156 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
4157
4158 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4159 and none can hold SFmode/SImode values. */
4160 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4161 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4162 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4163 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4164
4165 /* %fcc[0123] */
4166 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
4167
4168 /* %icc */
4169 CC_MODES
4170 };
4171
4172 int sparc_mode_class [NUM_MACHINE_MODES];
4173
4174 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
4175
4176 static void
4177 sparc_init_modes (void)
4178 {
4179 int i;
4180
4181 for (i = 0; i < NUM_MACHINE_MODES; i++)
4182 {
4183 switch (GET_MODE_CLASS (i))
4184 {
4185 case MODE_INT:
4186 case MODE_PARTIAL_INT:
4187 case MODE_COMPLEX_INT:
4188 if (GET_MODE_SIZE (i) <= 4)
4189 sparc_mode_class[i] = 1 << (int) S_MODE;
4190 else if (GET_MODE_SIZE (i) == 8)
4191 sparc_mode_class[i] = 1 << (int) D_MODE;
4192 else if (GET_MODE_SIZE (i) == 16)
4193 sparc_mode_class[i] = 1 << (int) T_MODE;
4194 else if (GET_MODE_SIZE (i) == 32)
4195 sparc_mode_class[i] = 1 << (int) O_MODE;
4196 else
4197 sparc_mode_class[i] = 0;
4198 break;
4199 case MODE_VECTOR_INT:
4200 if (GET_MODE_SIZE (i) <= 4)
4201 sparc_mode_class[i] = 1 << (int)SF_MODE;
4202 else if (GET_MODE_SIZE (i) == 8)
4203 sparc_mode_class[i] = 1 << (int)DF_MODE;
4204 break;
4205 case MODE_FLOAT:
4206 case MODE_COMPLEX_FLOAT:
4207 if (GET_MODE_SIZE (i) <= 4)
4208 sparc_mode_class[i] = 1 << (int) SF_MODE;
4209 else if (GET_MODE_SIZE (i) == 8)
4210 sparc_mode_class[i] = 1 << (int) DF_MODE;
4211 else if (GET_MODE_SIZE (i) == 16)
4212 sparc_mode_class[i] = 1 << (int) TF_MODE;
4213 else if (GET_MODE_SIZE (i) == 32)
4214 sparc_mode_class[i] = 1 << (int) OF_MODE;
4215 else
4216 sparc_mode_class[i] = 0;
4217 break;
4218 case MODE_CC:
4219 if (i == (int) CCFPmode || i == (int) CCFPEmode)
4220 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
4221 else
4222 sparc_mode_class[i] = 1 << (int) CC_MODE;
4223 break;
4224 default:
4225 sparc_mode_class[i] = 0;
4226 break;
4227 }
4228 }
4229
4230 if (TARGET_ARCH64)
4231 hard_regno_mode_classes = hard_64bit_mode_classes;
4232 else
4233 hard_regno_mode_classes = hard_32bit_mode_classes;
4234
4235 /* Initialize the array used by REGNO_REG_CLASS. */
4236 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4237 {
4238 if (i < 16 && TARGET_V8PLUS)
4239 sparc_regno_reg_class[i] = I64_REGS;
4240 else if (i < 32 || i == FRAME_POINTER_REGNUM)
4241 sparc_regno_reg_class[i] = GENERAL_REGS;
4242 else if (i < 64)
4243 sparc_regno_reg_class[i] = FP_REGS;
4244 else if (i < 96)
4245 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
4246 else if (i < 100)
4247 sparc_regno_reg_class[i] = FPCC_REGS;
4248 else
4249 sparc_regno_reg_class[i] = NO_REGS;
4250 }
4251 }
4252 \f
4253 /* Compute the frame size required by the function. This function is called
4254 during the reload pass and also by sparc_expand_prologue. */
4255
4256 HOST_WIDE_INT
4257 sparc_compute_frame_size (HOST_WIDE_INT size, int leaf_function_p)
4258 {
4259 int outgoing_args_size = (current_function_outgoing_args_size
4260 + REG_PARM_STACK_SPACE (current_function_decl));
4261 int n_regs = 0; /* N_REGS is the number of 4-byte regs saved thus far. */
4262 int i;
4263
4264 if (TARGET_ARCH64)
4265 {
4266 for (i = 0; i < 8; i++)
4267 if (regs_ever_live[i] && ! call_used_regs[i])
4268 n_regs += 2;
4269 }
4270 else
4271 {
4272 for (i = 0; i < 8; i += 2)
4273 if ((regs_ever_live[i] && ! call_used_regs[i])
4274 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4275 n_regs += 2;
4276 }
4277
4278 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
4279 if ((regs_ever_live[i] && ! call_used_regs[i])
4280 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4281 n_regs += 2;
4282
4283 /* Set up values for use in prologue and epilogue. */
4284 num_gfregs = n_regs;
4285
4286 if (leaf_function_p
4287 && n_regs == 0
4288 && size == 0
4289 && current_function_outgoing_args_size == 0)
4290 actual_fsize = apparent_fsize = 0;
4291 else
4292 {
4293 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4294 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8;
4295 apparent_fsize += n_regs * 4;
4296 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
4297 }
4298
4299 /* Make sure nothing can clobber our register windows.
4300 If a SAVE must be done, or there is a stack-local variable,
4301 the register window area must be allocated.
4302 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
4303 if (! leaf_function_p || size > 0)
4304 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
4305
4306 return SPARC_STACK_ALIGN (actual_fsize);
4307 }
4308
4309 /* Output any necessary .register pseudo-ops. */
4310
4311 void
4312 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED)
4313 {
4314 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4315 int i;
4316
4317 if (TARGET_ARCH32)
4318 return;
4319
4320 /* Check if %g[2367] were used without
4321 .register being printed for them already. */
4322 for (i = 2; i < 8; i++)
4323 {
4324 if (regs_ever_live [i]
4325 && ! sparc_hard_reg_printed [i])
4326 {
4327 sparc_hard_reg_printed [i] = 1;
4328 fprintf (file, "\t.register\t%%g%d, #scratch\n", i);
4329 }
4330 if (i == 3) i = 5;
4331 }
4332 #endif
4333 }
4334
4335 /* Save/restore call-saved registers from LOW to HIGH at BASE+OFFSET
4336 as needed. LOW should be double-word aligned for 32-bit registers.
4337 Return the new OFFSET. */
4338
4339 #define SORR_SAVE 0
4340 #define SORR_RESTORE 1
4341
4342 static int
4343 save_or_restore_regs (int low, int high, rtx base, int offset, int action)
4344 {
4345 rtx mem, insn;
4346 int i;
4347
4348 if (TARGET_ARCH64 && high <= 32)
4349 {
4350 for (i = low; i < high; i++)
4351 {
4352 if (regs_ever_live[i] && ! call_used_regs[i])
4353 {
4354 mem = gen_rtx_MEM (DImode, plus_constant (base, offset));
4355 set_mem_alias_set (mem, sparc_sr_alias_set);
4356 if (action == SORR_SAVE)
4357 {
4358 insn = emit_move_insn (mem, gen_rtx_REG (DImode, i));
4359 RTX_FRAME_RELATED_P (insn) = 1;
4360 }
4361 else /* action == SORR_RESTORE */
4362 emit_move_insn (gen_rtx_REG (DImode, i), mem);
4363 offset += 8;
4364 }
4365 }
4366 }
4367 else
4368 {
4369 for (i = low; i < high; i += 2)
4370 {
4371 bool reg0 = regs_ever_live[i] && ! call_used_regs[i];
4372 bool reg1 = regs_ever_live[i+1] && ! call_used_regs[i+1];
4373 enum machine_mode mode;
4374 int regno;
4375
4376 if (reg0 && reg1)
4377 {
4378 mode = i < 32 ? DImode : DFmode;
4379 regno = i;
4380 }
4381 else if (reg0)
4382 {
4383 mode = i < 32 ? SImode : SFmode;
4384 regno = i;
4385 }
4386 else if (reg1)
4387 {
4388 mode = i < 32 ? SImode : SFmode;
4389 regno = i + 1;
4390 offset += 4;
4391 }
4392 else
4393 continue;
4394
4395 mem = gen_rtx_MEM (mode, plus_constant (base, offset));
4396 set_mem_alias_set (mem, sparc_sr_alias_set);
4397 if (action == SORR_SAVE)
4398 {
4399 insn = emit_move_insn (mem, gen_rtx_REG (mode, regno));
4400 RTX_FRAME_RELATED_P (insn) = 1;
4401 }
4402 else /* action == SORR_RESTORE */
4403 emit_move_insn (gen_rtx_REG (mode, regno), mem);
4404
4405 /* Always preserve double-word alignment. */
4406 offset = (offset + 7) & -8;
4407 }
4408 }
4409
4410 return offset;
4411 }
4412
4413 /* Emit code to save call-saved registers. */
4414
4415 static void
4416 emit_save_regs (void)
4417 {
4418 HOST_WIDE_INT offset;
4419 rtx base;
4420
4421 offset = frame_base_offset - apparent_fsize;
4422
4423 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
4424 {
4425 /* ??? This might be optimized a little as %g1 might already have a
4426 value close enough that a single add insn will do. */
4427 /* ??? Although, all of this is probably only a temporary fix
4428 because if %g1 can hold a function result, then
4429 sparc_expand_epilogue will lose (the result will be
4430 clobbered). */
4431 base = gen_rtx_REG (Pmode, 1);
4432 emit_move_insn (base, GEN_INT (offset));
4433 emit_insn (gen_rtx_SET (VOIDmode,
4434 base,
4435 gen_rtx_PLUS (Pmode, frame_base_reg, base)));
4436 offset = 0;
4437 }
4438 else
4439 base = frame_base_reg;
4440
4441 offset = save_or_restore_regs (0, 8, base, offset, SORR_SAVE);
4442 save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, SORR_SAVE);
4443 }
4444
4445 /* Emit code to restore call-saved registers. */
4446
4447 static void
4448 emit_restore_regs (void)
4449 {
4450 HOST_WIDE_INT offset;
4451 rtx base;
4452
4453 offset = frame_base_offset - apparent_fsize;
4454
4455 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
4456 {
4457 base = gen_rtx_REG (Pmode, 1);
4458 emit_move_insn (base, GEN_INT (offset));
4459 emit_insn (gen_rtx_SET (VOIDmode,
4460 base,
4461 gen_rtx_PLUS (Pmode, frame_base_reg, base)));
4462 offset = 0;
4463 }
4464 else
4465 base = frame_base_reg;
4466
4467 offset = save_or_restore_regs (0, 8, base, offset, SORR_RESTORE);
4468 save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, SORR_RESTORE);
4469 }
4470
4471 /* Emit an increment for the stack pointer. */
4472
4473 static void
4474 emit_stack_pointer_increment (rtx increment)
4475 {
4476 if (TARGET_ARCH64)
4477 emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, increment));
4478 else
4479 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, increment));
4480 }
4481
4482 /* Emit a decrement for the stack pointer. */
4483
4484 static void
4485 emit_stack_pointer_decrement (rtx decrement)
4486 {
4487 if (TARGET_ARCH64)
4488 emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, decrement));
4489 else
4490 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, decrement));
4491 }
4492
4493 /* Expand the function prologue. The prologue is responsible for reserving
4494 storage for the frame, saving the call-saved registers and loading the
4495 PIC register if needed. */
4496
4497 void
4498 sparc_expand_prologue (void)
4499 {
4500 /* Compute a snapshot of current_function_uses_only_leaf_regs. Relying
4501 on the final value of the flag means deferring the prologue/epilogue
4502 expansion until just before the second scheduling pass, which is too
4503 late to emit multiple epilogues or return insns.
4504
4505 Of course we are making the assumption that the value of the flag
4506 will not change between now and its final value. Of the three parts
4507 of the formula, only the last one can reasonably vary. Let's take a
4508 closer look, after assuming that the first two ones are set to true
4509 (otherwise the last value is effectively silenced).
4510
4511 If only_leaf_regs_used returns false, the global predicate will also
4512 be false so the actual frame size calculated below will be positive.
4513 As a consequence, the save_register_window insn will be emitted in
4514 the instruction stream; now this insn explicitly references %fp
4515 which is not a leaf register so only_leaf_regs_used will always
4516 return false subsequently.
4517
4518 If only_leaf_regs_used returns true, we hope that the subsequent
4519 optimization passes won't cause non-leaf registers to pop up. For
4520 example, the regrename pass has special provisions to not rename to
4521 non-leaf registers in a leaf function. */
4522 sparc_leaf_function_p
4523 = optimize > 0 && leaf_function_p () && only_leaf_regs_used ();
4524
4525 /* Need to use actual_fsize, since we are also allocating
4526 space for our callee (and our own register save area). */
4527 actual_fsize
4528 = sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p);
4529
4530 /* Advertise that the data calculated just above are now valid. */
4531 sparc_prologue_data_valid_p = true;
4532
4533 if (sparc_leaf_function_p)
4534 {
4535 frame_base_reg = stack_pointer_rtx;
4536 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
4537 }
4538 else
4539 {
4540 frame_base_reg = hard_frame_pointer_rtx;
4541 frame_base_offset = SPARC_STACK_BIAS;
4542 }
4543
4544 if (actual_fsize == 0)
4545 /* do nothing. */ ;
4546 else if (sparc_leaf_function_p)
4547 {
4548 if (actual_fsize <= 4096)
4549 emit_stack_pointer_increment (GEN_INT (- actual_fsize));
4550 else if (actual_fsize <= 8192)
4551 {
4552 emit_stack_pointer_increment (GEN_INT (-4096));
4553 emit_stack_pointer_increment (GEN_INT (4096 - actual_fsize));
4554 }
4555 else
4556 {
4557 rtx reg = gen_rtx_REG (Pmode, 1);
4558 emit_move_insn (reg, GEN_INT (-actual_fsize));
4559 emit_stack_pointer_increment (reg);
4560 }
4561 }
4562 else
4563 {
4564 if (actual_fsize <= 4096)
4565 emit_insn (gen_save_register_window (GEN_INT (-actual_fsize)));
4566 else if (actual_fsize <= 8192)
4567 {
4568 emit_insn (gen_save_register_window (GEN_INT (-4096)));
4569 emit_stack_pointer_increment (GEN_INT (4096 - actual_fsize));
4570 }
4571 else
4572 {
4573 rtx reg = gen_rtx_REG (Pmode, 1);
4574 emit_move_insn (reg, GEN_INT (-actual_fsize));
4575 emit_insn (gen_save_register_window (reg));
4576 }
4577 }
4578
4579 /* Call-saved registers are saved just above the outgoing argument area. */
4580 if (num_gfregs)
4581 emit_save_regs ();
4582
4583 /* Load the PIC register if needed. */
4584 if (flag_pic && current_function_uses_pic_offset_table)
4585 load_pic_register ();
4586 }
4587
4588 /* This function generates the assembly code for function entry, which boils
4589 down to emitting the necessary .register directives. It also informs the
4590 DWARF-2 back-end on the layout of the frame.
4591
4592 ??? Historical cruft: "On SPARC, move-double insns between fpu and cpu need
4593 an 8-byte block of memory. If any fpu reg is used in the function, we
4594 allocate such a block here, at the bottom of the frame, just in case it's
4595 needed." Could this explain the -8 in emit_restore_regs? */
4596
4597 static void
4598 sparc_asm_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4599 {
4600 /* Check that the assumption we made in sparc_expand_prologue is valid. */
4601 if (sparc_leaf_function_p != current_function_uses_only_leaf_regs)
4602 abort();
4603
4604 sparc_output_scratch_registers (file);
4605
4606 if (dwarf2out_do_frame () && actual_fsize)
4607 {
4608 char *label = dwarf2out_cfi_label ();
4609
4610 /* The canonical frame address refers to the top of the frame. */
4611 dwarf2out_def_cfa (label,
4612 sparc_leaf_function_p
4613 ? STACK_POINTER_REGNUM
4614 : HARD_FRAME_POINTER_REGNUM,
4615 frame_base_offset);
4616
4617 if (! sparc_leaf_function_p)
4618 {
4619 /* Note the register window save. This tells the unwinder that
4620 it needs to restore the window registers from the previous
4621 frame's window save area at 0(cfa). */
4622 dwarf2out_window_save (label);
4623
4624 /* The return address (-8) is now in %i7. */
4625 dwarf2out_return_reg (label, 31);
4626 }
4627 }
4628 }
4629
4630 /* Expand the function epilogue, either normal or part of a sibcall.
4631 We emit all the instructions except the return or the call. */
4632
4633 void
4634 sparc_expand_epilogue (void)
4635 {
4636 if (num_gfregs)
4637 emit_restore_regs ();
4638
4639 if (actual_fsize == 0)
4640 /* do nothing. */ ;
4641 else if (sparc_leaf_function_p)
4642 {
4643 if (actual_fsize <= 4096)
4644 emit_stack_pointer_decrement (GEN_INT (- actual_fsize));
4645 else if (actual_fsize <= 8192)
4646 {
4647 emit_stack_pointer_decrement (GEN_INT (-4096));
4648 emit_stack_pointer_decrement (GEN_INT (4096 - actual_fsize));
4649 }
4650 else
4651 {
4652 rtx reg = gen_rtx_REG (Pmode, 1);
4653 emit_move_insn (reg, GEN_INT (-actual_fsize));
4654 emit_stack_pointer_decrement (reg);
4655 }
4656 }
4657 }
4658
4659 /* Return true if it is appropriate to emit `return' instructions in the
4660 body of a function. */
4661
4662 bool
4663 sparc_can_use_return_insn_p (void)
4664 {
4665 return sparc_prologue_data_valid_p
4666 && (actual_fsize == 0 || !sparc_leaf_function_p);
4667 }
4668
4669 /* This function generates the assembly code for function exit. */
4670
4671 static void
4672 sparc_asm_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4673 {
4674 /* If code does not drop into the epilogue, we have to still output
4675 a dummy nop for the sake of sane backtraces. Otherwise, if the
4676 last two instructions of a function were "call foo; dslot;" this
4677 can make the return PC of foo (i.e. address of call instruction
4678 plus 8) point to the first instruction in the next function. */
4679
4680 rtx insn, last_real_insn;
4681
4682 insn = get_last_insn ();
4683
4684 last_real_insn = prev_real_insn (insn);
4685 if (last_real_insn
4686 && GET_CODE (last_real_insn) == INSN
4687 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE)
4688 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0);
4689
4690 if (last_real_insn && GET_CODE (last_real_insn) == CALL_INSN)
4691 fputs("\tnop\n", file);
4692
4693 sparc_output_deferred_case_vectors ();
4694 }
4695
4696 /* Output a 'restore' instruction. */
4697
4698 static void
4699 output_restore (rtx pat)
4700 {
4701 rtx operands[3];
4702
4703 if (! pat)
4704 {
4705 fputs ("\t restore\n", asm_out_file);
4706 return;
4707 }
4708
4709 if (GET_CODE (pat) != SET)
4710 abort ();
4711
4712 operands[0] = SET_DEST (pat);
4713 pat = SET_SRC (pat);
4714
4715 switch (GET_CODE (pat))
4716 {
4717 case PLUS:
4718 operands[1] = XEXP (pat, 0);
4719 operands[2] = XEXP (pat, 1);
4720 output_asm_insn (" restore %r1, %2, %Y0", operands);
4721 break;
4722 case LO_SUM:
4723 operands[1] = XEXP (pat, 0);
4724 operands[2] = XEXP (pat, 1);
4725 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
4726 break;
4727 case ASHIFT:
4728 operands[1] = XEXP (pat, 0);
4729 if (XEXP (pat, 1) != const1_rtx)
4730 abort();
4731 output_asm_insn (" restore %r1, %r1, %Y0", operands);
4732 break;
4733 default:
4734 operands[1] = pat;
4735 output_asm_insn (" restore %%g0, %1, %Y0", operands);
4736 break;
4737 }
4738 }
4739
4740 /* Output a return. */
4741
4742 const char *
4743 output_return (rtx insn)
4744 {
4745 if (sparc_leaf_function_p)
4746 {
4747 /* This is a leaf function so we don't have to bother restoring the
4748 register window, which frees us from dealing with the convoluted
4749 semantics of restore/return. We simply output the jump to the
4750 return address and the insn in the delay slot (if any). */
4751
4752 if (current_function_calls_eh_return)
4753 abort ();
4754
4755 return "jmp\t%%o7+%)%#";
4756 }
4757 else
4758 {
4759 /* This is a regular function so we have to restore the register window.
4760 We may have a pending insn for the delay slot, which will be either
4761 combined with the 'restore' instruction or put in the delay slot of
4762 the 'return' instruction. */
4763
4764 if (current_function_calls_eh_return)
4765 {
4766 /* If the function uses __builtin_eh_return, the eh_return
4767 machinery occupies the delay slot. */
4768 if (final_sequence)
4769 abort ();
4770
4771 if (! flag_delayed_branch)
4772 fputs ("\tadd\t%fp, %g1, %fp\n", asm_out_file);
4773
4774 if (TARGET_V9)
4775 fputs ("\treturn\t%i7+8\n", asm_out_file);
4776 else
4777 fputs ("\trestore\n\tjmp\t%o7+8\n", asm_out_file);
4778
4779 if (flag_delayed_branch)
4780 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file);
4781 else
4782 fputs ("\t nop\n", asm_out_file);
4783 }
4784 else if (final_sequence)
4785 {
4786 rtx delay, pat;
4787
4788 delay = NEXT_INSN (insn);
4789 if (! delay)
4790 abort ();
4791
4792 pat = PATTERN (delay);
4793
4794 if (TARGET_V9 && ! epilogue_renumber (&pat, 1))
4795 {
4796 epilogue_renumber (&pat, 0);
4797 return "return\t%%i7+%)%#";
4798 }
4799 else
4800 {
4801 output_asm_insn ("jmp\t%%i7+%)", NULL);
4802 output_restore (pat);
4803 PATTERN (delay) = gen_blockage ();
4804 INSN_CODE (delay) = -1;
4805 }
4806 }
4807 else
4808 {
4809 /* The delay slot is empty. */
4810 if (TARGET_V9)
4811 return "return\t%%i7+%)\n\t nop";
4812 else if (flag_delayed_branch)
4813 return "jmp\t%%i7+%)\n\t restore";
4814 else
4815 return "restore\n\tjmp\t%%o7+%)\n\t nop";
4816 }
4817 }
4818
4819 return "";
4820 }
4821
4822 /* Output a sibling call. */
4823
4824 const char *
4825 output_sibcall (rtx insn, rtx call_operand)
4826 {
4827 rtx operands[1];
4828
4829 if (! flag_delayed_branch)
4830 abort();
4831
4832 operands[0] = call_operand;
4833
4834 if (sparc_leaf_function_p)
4835 {
4836 /* This is a leaf function so we don't have to bother restoring the
4837 register window. We simply output the jump to the function and
4838 the insn in the delay slot (if any). */
4839
4840 if (LEAF_SIBCALL_SLOT_RESERVED_P && final_sequence)
4841 abort();
4842
4843 if (final_sequence)
4844 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
4845 operands);
4846 else
4847 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4848 it into branch if possible. */
4849 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
4850 operands);
4851 }
4852 else
4853 {
4854 /* This is a regular function so we have to restore the register window.
4855 We may have a pending insn for the delay slot, which will be combined
4856 with the 'restore' instruction. */
4857
4858 output_asm_insn ("call\t%a0, 0", operands);
4859
4860 if (final_sequence)
4861 {
4862 rtx delay = NEXT_INSN (insn);
4863 if (! delay)
4864 abort ();
4865
4866 output_restore (PATTERN (delay));
4867
4868 PATTERN (delay) = gen_blockage ();
4869 INSN_CODE (delay) = -1;
4870 }
4871 else
4872 output_restore (NULL_RTX);
4873 }
4874
4875 return "";
4876 }
4877 \f
4878 /* Functions for handling argument passing.
4879
4880 For 32-bit, the first 6 args are normally in registers and the rest are
4881 pushed. Any arg that starts within the first 6 words is at least
4882 partially passed in a register unless its data type forbids.
4883
4884 For 64-bit, the argument registers are laid out as an array of 16 elements
4885 and arguments are added sequentially. The first 6 int args and up to the
4886 first 16 fp args (depending on size) are passed in regs.
4887
4888 Slot Stack Integral Float Float in structure Double Long Double
4889 ---- ----- -------- ----- ------------------ ------ -----------
4890 15 [SP+248] %f31 %f30,%f31 %d30
4891 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4892 13 [SP+232] %f27 %f26,%f27 %d26
4893 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4894 11 [SP+216] %f23 %f22,%f23 %d22
4895 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4896 9 [SP+200] %f19 %f18,%f19 %d18
4897 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4898 7 [SP+184] %f15 %f14,%f15 %d14
4899 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4900 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4901 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4902 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4903 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4904 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4905 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4906
4907 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4908
4909 Integral arguments are always passed as 64-bit quantities appropriately
4910 extended.
4911
4912 Passing of floating point values is handled as follows.
4913 If a prototype is in scope:
4914 If the value is in a named argument (i.e. not a stdarg function or a
4915 value not part of the `...') then the value is passed in the appropriate
4916 fp reg.
4917 If the value is part of the `...' and is passed in one of the first 6
4918 slots then the value is passed in the appropriate int reg.
4919 If the value is part of the `...' and is not passed in one of the first 6
4920 slots then the value is passed in memory.
4921 If a prototype is not in scope:
4922 If the value is one of the first 6 arguments the value is passed in the
4923 appropriate integer reg and the appropriate fp reg.
4924 If the value is not one of the first 6 arguments the value is passed in
4925 the appropriate fp reg and in memory.
4926
4927
4928 Summary of the calling conventions implemented by GCC on SPARC:
4929
4930 32-bit ABI:
4931 size argument return value
4932
4933 small integer <4 int. reg. int. reg.
4934 word 4 int. reg. int. reg.
4935 double word 8 int. reg. int. reg.
4936
4937 _Complex small integer <8 int. reg. int. reg.
4938 _Complex word 8 int. reg. int. reg.
4939 _Complex double word 16 memory int. reg.
4940
4941 vector integer <=8 int. reg. FP reg.
4942 vector integer >8 memory memory
4943
4944 float 4 int. reg. FP reg.
4945 double 8 int. reg. FP reg.
4946 long double 16 memory memory
4947
4948 _Complex float 8 memory FP reg.
4949 _Complex double 16 memory FP reg.
4950 _Complex long double 32 memory FP reg.
4951
4952 vector float any memory memory
4953
4954 aggregate any memory memory
4955
4956
4957
4958 64-bit ABI:
4959 size argument return value
4960
4961 small integer <8 int. reg. int. reg.
4962 word 8 int. reg. int. reg.
4963 double word 16 int. reg. int. reg.
4964
4965 _Complex small integer <16 int. reg. int. reg.
4966 _Complex word 16 int. reg. int. reg.
4967 _Complex double word 32 memory int. reg.
4968
4969 vector integer <=16 FP reg. FP reg.
4970 vector integer 16<s<=32 memory FP reg.
4971 vector integer >32 memory memory
4972
4973 float 4 FP reg. FP reg.
4974 double 8 FP reg. FP reg.
4975 long double 16 FP reg. FP reg.
4976
4977 _Complex float 8 FP reg. FP reg.
4978 _Complex double 16 FP reg. FP reg.
4979 _Complex long double 32 memory FP reg.
4980
4981 vector float <=16 FP reg. FP reg.
4982 vector float 16<s<=32 memory FP reg.
4983 vector float >32 memory memory
4984
4985 aggregate <=16 reg. reg.
4986 aggregate 16<s<=32 memory reg.
4987 aggregate >32 memory memory
4988
4989
4990
4991 Note #1: complex floating-point types follow the extended SPARC ABIs as
4992 implemented by the Sun compiler.
4993
4994 Note #2: integral vector types follow the scalar floating-point types
4995 conventions to match what is implemented by the Sun VIS SDK.
4996
4997 Note #3: floating-point vector types follow the aggregate types
4998 conventions. */
4999
5000
5001 /* Maximum number of int regs for args. */
5002 #define SPARC_INT_ARG_MAX 6
5003 /* Maximum number of fp regs for args. */
5004 #define SPARC_FP_ARG_MAX 16
5005
5006 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
5007
5008 /* Handle the INIT_CUMULATIVE_ARGS macro.
5009 Initialize a variable CUM of type CUMULATIVE_ARGS
5010 for a call to a function whose data type is FNTYPE.
5011 For a library call, FNTYPE is 0. */
5012
5013 void
5014 init_cumulative_args (struct sparc_args *cum, tree fntype,
5015 rtx libname ATTRIBUTE_UNUSED,
5016 tree fndecl ATTRIBUTE_UNUSED)
5017 {
5018 cum->words = 0;
5019 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
5020 cum->libcall_p = fntype == 0;
5021 }
5022
5023 /* Handle the TARGET_PROMOTE_PROTOTYPES target hook.
5024 When a prototype says `char' or `short', really pass an `int'. */
5025
5026 static bool
5027 sparc_promote_prototypes (tree fntype ATTRIBUTE_UNUSED)
5028 {
5029 return TARGET_ARCH32 ? true : false;
5030 }
5031
5032 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
5033
5034 static bool
5035 sparc_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
5036 {
5037 return TARGET_ARCH64 ? true : false;
5038 }
5039
5040 /* Scan the record type TYPE and return the following predicates:
5041 - INTREGS_P: the record contains at least one field or sub-field
5042 that is eligible for promotion in integer registers.
5043 - FP_REGS_P: the record contains at least one field or sub-field
5044 that is eligible for promotion in floating-point registers.
5045 - PACKED_P: the record contains at least one field that is packed.
5046
5047 Sub-fields are not taken into account for the PACKED_P predicate. */
5048
5049 static void
5050 scan_record_type (tree type, int *intregs_p, int *fpregs_p, int *packed_p)
5051 {
5052 tree field;
5053
5054 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5055 {
5056 if (TREE_CODE (field) == FIELD_DECL)
5057 {
5058 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5059 scan_record_type (TREE_TYPE (field), intregs_p, fpregs_p, 0);
5060 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5061 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5062 && TARGET_FPU)
5063 *fpregs_p = 1;
5064 else
5065 *intregs_p = 1;
5066
5067 if (packed_p && DECL_PACKED (field))
5068 *packed_p = 1;
5069 }
5070 }
5071 }
5072
5073 /* Compute the slot number to pass an argument in.
5074 Return the slot number or -1 if passing on the stack.
5075
5076 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5077 the preceding args and about the function being called.
5078 MODE is the argument's machine mode.
5079 TYPE is the data type of the argument (as a tree).
5080 This is null for libcalls where that information may
5081 not be available.
5082 NAMED is nonzero if this argument is a named parameter
5083 (otherwise it is an extra parameter matching an ellipsis).
5084 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
5085 *PREGNO records the register number to use if scalar type.
5086 *PPADDING records the amount of padding needed in words. */
5087
5088 static int
5089 function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode,
5090 tree type, int named, int incoming_p,
5091 int *pregno, int *ppadding)
5092 {
5093 int regbase = (incoming_p
5094 ? SPARC_INCOMING_INT_ARG_FIRST
5095 : SPARC_OUTGOING_INT_ARG_FIRST);
5096 int slotno = cum->words;
5097 enum mode_class mclass;
5098 int regno;
5099
5100 *ppadding = 0;
5101
5102 if (type && TREE_ADDRESSABLE (type))
5103 return -1;
5104
5105 if (TARGET_ARCH32
5106 && mode == BLKmode
5107 && type
5108 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
5109 return -1;
5110
5111 /* For SPARC64, objects requiring 16-byte alignment get it. */
5112 if (TARGET_ARCH64
5113 && GET_MODE_ALIGNMENT (mode) >= 2 * BITS_PER_WORD
5114 && (slotno & 1) != 0)
5115 slotno++, *ppadding = 1;
5116
5117 mclass = GET_MODE_CLASS (mode);
5118 if (type && TREE_CODE (type) == VECTOR_TYPE)
5119 {
5120 /* Vector types deserve special treatment because they are
5121 polymorphic wrt their mode, depending upon whether VIS
5122 instructions are enabled. */
5123 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
5124 {
5125 /* The SPARC port defines no floating-point vector modes. */
5126 if (mode != BLKmode)
5127 abort ();
5128 }
5129 else
5130 {
5131 /* Integral vector types should either have a vector
5132 mode or an integral mode, because we are guaranteed
5133 by pass_by_reference that their size is not greater
5134 than 16 bytes and TImode is 16-byte wide. */
5135 if (mode == BLKmode)
5136 abort ();
5137
5138 /* Vector integers are handled like floats according to
5139 the Sun VIS SDK. */
5140 mclass = MODE_FLOAT;
5141 }
5142 }
5143
5144 switch (mclass)
5145 {
5146 case MODE_FLOAT:
5147 case MODE_COMPLEX_FLOAT:
5148 if (TARGET_ARCH64 && TARGET_FPU && named)
5149 {
5150 if (slotno >= SPARC_FP_ARG_MAX)
5151 return -1;
5152 regno = SPARC_FP_ARG_FIRST + slotno * 2;
5153 /* Arguments filling only one single FP register are
5154 right-justified in the outer double FP register. */
5155 if (GET_MODE_SIZE (mode) <= 4)
5156 regno++;
5157 break;
5158 }
5159 /* fallthrough */
5160
5161 case MODE_INT:
5162 case MODE_COMPLEX_INT:
5163 if (slotno >= SPARC_INT_ARG_MAX)
5164 return -1;
5165 regno = regbase + slotno;
5166 break;
5167
5168 case MODE_RANDOM:
5169 if (mode == VOIDmode)
5170 /* MODE is VOIDmode when generating the actual call. */
5171 return -1;
5172
5173 if (mode != BLKmode)
5174 abort ();
5175
5176 /* For SPARC64, objects requiring 16-byte alignment get it. */
5177 if (TARGET_ARCH64
5178 && type
5179 && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5180 && (slotno & 1) != 0)
5181 slotno++, *ppadding = 1;
5182
5183 if (TARGET_ARCH32 || !type || (TREE_CODE (type) == UNION_TYPE))
5184 {
5185 if (slotno >= SPARC_INT_ARG_MAX)
5186 return -1;
5187 regno = regbase + slotno;
5188 }
5189 else /* TARGET_ARCH64 && type */
5190 {
5191 int intregs_p = 0, fpregs_p = 0, packed_p = 0;
5192
5193 /* First see what kinds of registers we would need. */
5194 if (TREE_CODE (type) == VECTOR_TYPE)
5195 fpregs_p = 1;
5196 else
5197 scan_record_type (type, &intregs_p, &fpregs_p, &packed_p);
5198
5199 /* The ABI obviously doesn't specify how packed structures
5200 are passed. These are defined to be passed in int regs
5201 if possible, otherwise memory. */
5202 if (packed_p || !named)
5203 fpregs_p = 0, intregs_p = 1;
5204
5205 /* If all arg slots are filled, then must pass on stack. */
5206 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
5207 return -1;
5208
5209 /* If there are only int args and all int arg slots are filled,
5210 then must pass on stack. */
5211 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
5212 return -1;
5213
5214 /* Note that even if all int arg slots are filled, fp members may
5215 still be passed in regs if such regs are available.
5216 *PREGNO isn't set because there may be more than one, it's up
5217 to the caller to compute them. */
5218 return slotno;
5219 }
5220 break;
5221
5222 default :
5223 abort ();
5224 }
5225
5226 *pregno = regno;
5227 return slotno;
5228 }
5229
5230 /* Handle recursive register counting for structure field layout. */
5231
5232 struct function_arg_record_value_parms
5233 {
5234 rtx ret; /* return expression being built. */
5235 int slotno; /* slot number of the argument. */
5236 int named; /* whether the argument is named. */
5237 int regbase; /* regno of the base register. */
5238 int stack; /* 1 if part of the argument is on the stack. */
5239 int intoffset; /* offset of the first pending integer field. */
5240 unsigned int nregs; /* number of words passed in registers. */
5241 };
5242
5243 static void function_arg_record_value_3
5244 (HOST_WIDE_INT, struct function_arg_record_value_parms *);
5245 static void function_arg_record_value_2
5246 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5247 static void function_arg_record_value_1
5248 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5249 static rtx function_arg_record_value (tree, enum machine_mode, int, int, int);
5250 static rtx function_arg_union_value (int, enum machine_mode, int, int);
5251
5252 /* A subroutine of function_arg_record_value. Traverse the structure
5253 recursively and determine how many registers will be required. */
5254
5255 static void
5256 function_arg_record_value_1 (tree type, HOST_WIDE_INT startbitpos,
5257 struct function_arg_record_value_parms *parms,
5258 bool packed_p)
5259 {
5260 tree field;
5261
5262 /* We need to compute how many registers are needed so we can
5263 allocate the PARALLEL but before we can do that we need to know
5264 whether there are any packed fields. The ABI obviously doesn't
5265 specify how structures are passed in this case, so they are
5266 defined to be passed in int regs if possible, otherwise memory,
5267 regardless of whether there are fp values present. */
5268
5269 if (! packed_p)
5270 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5271 {
5272 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5273 {
5274 packed_p = true;
5275 break;
5276 }
5277 }
5278
5279 /* Compute how many registers we need. */
5280 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5281 {
5282 if (TREE_CODE (field) == FIELD_DECL)
5283 {
5284 HOST_WIDE_INT bitpos = startbitpos;
5285
5286 if (DECL_SIZE (field) != 0)
5287 {
5288 if (integer_zerop (DECL_SIZE (field)))
5289 continue;
5290
5291 if (host_integerp (bit_position (field), 1))
5292 bitpos += int_bit_position (field);
5293 }
5294
5295 /* ??? FIXME: else assume zero offset. */
5296
5297 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5298 function_arg_record_value_1 (TREE_TYPE (field),
5299 bitpos,
5300 parms,
5301 packed_p);
5302 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5303 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5304 && TARGET_FPU
5305 && parms->named
5306 && ! packed_p)
5307 {
5308 if (parms->intoffset != -1)
5309 {
5310 unsigned int startbit, endbit;
5311 int intslots, this_slotno;
5312
5313 startbit = parms->intoffset & -BITS_PER_WORD;
5314 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5315
5316 intslots = (endbit - startbit) / BITS_PER_WORD;
5317 this_slotno = parms->slotno + parms->intoffset
5318 / BITS_PER_WORD;
5319
5320 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5321 {
5322 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5323 /* We need to pass this field on the stack. */
5324 parms->stack = 1;
5325 }
5326
5327 parms->nregs += intslots;
5328 parms->intoffset = -1;
5329 }
5330
5331 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
5332 If it wasn't true we wouldn't be here. */
5333 if (TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE
5334 && DECL_MODE (field) == BLKmode)
5335 parms->nregs += TYPE_VECTOR_SUBPARTS (TREE_TYPE (field));
5336 else if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5337 parms->nregs += 2;
5338 else
5339 parms->nregs += 1;
5340 }
5341 else
5342 {
5343 if (parms->intoffset == -1)
5344 parms->intoffset = bitpos;
5345 }
5346 }
5347 }
5348 }
5349
5350 /* A subroutine of function_arg_record_value. Assign the bits of the
5351 structure between parms->intoffset and bitpos to integer registers. */
5352
5353 static void
5354 function_arg_record_value_3 (HOST_WIDE_INT bitpos,
5355 struct function_arg_record_value_parms *parms)
5356 {
5357 enum machine_mode mode;
5358 unsigned int regno;
5359 unsigned int startbit, endbit;
5360 int this_slotno, intslots, intoffset;
5361 rtx reg;
5362
5363 if (parms->intoffset == -1)
5364 return;
5365
5366 intoffset = parms->intoffset;
5367 parms->intoffset = -1;
5368
5369 startbit = intoffset & -BITS_PER_WORD;
5370 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5371 intslots = (endbit - startbit) / BITS_PER_WORD;
5372 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
5373
5374 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
5375 if (intslots <= 0)
5376 return;
5377
5378 /* If this is the trailing part of a word, only load that much into
5379 the register. Otherwise load the whole register. Note that in
5380 the latter case we may pick up unwanted bits. It's not a problem
5381 at the moment but may wish to revisit. */
5382
5383 if (intoffset % BITS_PER_WORD != 0)
5384 mode = smallest_mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5385 MODE_INT);
5386 else
5387 mode = word_mode;
5388
5389 intoffset /= BITS_PER_UNIT;
5390 do
5391 {
5392 regno = parms->regbase + this_slotno;
5393 reg = gen_rtx_REG (mode, regno);
5394 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5395 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5396
5397 this_slotno += 1;
5398 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5399 mode = word_mode;
5400 parms->nregs += 1;
5401 intslots -= 1;
5402 }
5403 while (intslots > 0);
5404 }
5405
5406 /* A subroutine of function_arg_record_value. Traverse the structure
5407 recursively and assign bits to floating point registers. Track which
5408 bits in between need integer registers; invoke function_arg_record_value_3
5409 to make that happen. */
5410
5411 static void
5412 function_arg_record_value_2 (tree type, HOST_WIDE_INT startbitpos,
5413 struct function_arg_record_value_parms *parms,
5414 bool packed_p)
5415 {
5416 tree field;
5417
5418 if (! packed_p)
5419 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5420 {
5421 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5422 {
5423 packed_p = true;
5424 break;
5425 }
5426 }
5427
5428 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5429 {
5430 if (TREE_CODE (field) == FIELD_DECL)
5431 {
5432 HOST_WIDE_INT bitpos = startbitpos;
5433
5434 if (DECL_SIZE (field) != 0)
5435 {
5436 if (integer_zerop (DECL_SIZE (field)))
5437 continue;
5438
5439 if (host_integerp (bit_position (field), 1))
5440 bitpos += int_bit_position (field);
5441 }
5442
5443 /* ??? FIXME: else assume zero offset. */
5444
5445 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5446 function_arg_record_value_2 (TREE_TYPE (field),
5447 bitpos,
5448 parms,
5449 packed_p);
5450 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5451 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5452 && TARGET_FPU
5453 && parms->named
5454 && ! packed_p)
5455 {
5456 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
5457 int regno, nregs, pos;
5458 enum machine_mode mode = DECL_MODE (field);
5459 rtx reg;
5460
5461 function_arg_record_value_3 (bitpos, parms);
5462
5463 if (TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE
5464 && mode == BLKmode)
5465 {
5466 mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field)));
5467 nregs = TYPE_VECTOR_SUBPARTS (TREE_TYPE (field));
5468 }
5469 else if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5470 {
5471 mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field)));
5472 nregs = 2;
5473 }
5474 else
5475 nregs = 1;
5476
5477 regno = SPARC_FP_ARG_FIRST + this_slotno * 2;
5478 if (GET_MODE_SIZE (mode) <= 4 && (bitpos & 32) != 0)
5479 regno++;
5480 reg = gen_rtx_REG (mode, regno);
5481 pos = bitpos / BITS_PER_UNIT;
5482 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5483 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (pos));
5484 parms->nregs += 1;
5485 while (--nregs > 0)
5486 {
5487 regno += GET_MODE_SIZE (mode) / 4;
5488 reg = gen_rtx_REG (mode, regno);
5489 pos += GET_MODE_SIZE (mode);
5490 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5491 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (pos));
5492 parms->nregs += 1;
5493 }
5494 }
5495 else
5496 {
5497 if (parms->intoffset == -1)
5498 parms->intoffset = bitpos;
5499 }
5500 }
5501 }
5502 }
5503
5504 /* Used by function_arg and function_value to implement the complex
5505 conventions of the 64-bit ABI for passing and returning structures.
5506 Return an expression valid as a return value for the two macros
5507 FUNCTION_ARG and FUNCTION_VALUE.
5508
5509 TYPE is the data type of the argument (as a tree).
5510 This is null for libcalls where that information may
5511 not be available.
5512 MODE is the argument's machine mode.
5513 SLOTNO is the index number of the argument's slot in the parameter array.
5514 NAMED is nonzero if this argument is a named parameter
5515 (otherwise it is an extra parameter matching an ellipsis).
5516 REGBASE is the regno of the base register for the parameter array. */
5517
5518 static rtx
5519 function_arg_record_value (tree type, enum machine_mode mode,
5520 int slotno, int named, int regbase)
5521 {
5522 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5523 struct function_arg_record_value_parms parms;
5524 unsigned int nregs;
5525
5526 parms.ret = NULL_RTX;
5527 parms.slotno = slotno;
5528 parms.named = named;
5529 parms.regbase = regbase;
5530 parms.stack = 0;
5531
5532 /* Compute how many registers we need. */
5533 parms.nregs = 0;
5534 parms.intoffset = 0;
5535 function_arg_record_value_1 (type, 0, &parms, false);
5536
5537 /* Take into account pending integer fields. */
5538 if (parms.intoffset != -1)
5539 {
5540 unsigned int startbit, endbit;
5541 int intslots, this_slotno;
5542
5543 startbit = parms.intoffset & -BITS_PER_WORD;
5544 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5545 intslots = (endbit - startbit) / BITS_PER_WORD;
5546 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
5547
5548 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5549 {
5550 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5551 /* We need to pass this field on the stack. */
5552 parms.stack = 1;
5553 }
5554
5555 parms.nregs += intslots;
5556 }
5557 nregs = parms.nregs;
5558
5559 /* Allocate the vector and handle some annoying special cases. */
5560 if (nregs == 0)
5561 {
5562 /* ??? Empty structure has no value? Duh? */
5563 if (typesize <= 0)
5564 {
5565 /* Though there's nothing really to store, return a word register
5566 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
5567 leads to breakage due to the fact that there are zero bytes to
5568 load. */
5569 return gen_rtx_REG (mode, regbase);
5570 }
5571 else
5572 {
5573 /* ??? C++ has structures with no fields, and yet a size. Give up
5574 for now and pass everything back in integer registers. */
5575 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5576 }
5577 if (nregs + slotno > SPARC_INT_ARG_MAX)
5578 nregs = SPARC_INT_ARG_MAX - slotno;
5579 }
5580 if (nregs == 0)
5581 abort ();
5582
5583 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs));
5584
5585 /* If at least one field must be passed on the stack, generate
5586 (parallel [(expr_list (nil) ...) ...]) so that all fields will
5587 also be passed on the stack. We can't do much better because the
5588 semantics of FUNCTION_ARG_PARTIAL_NREGS doesn't handle the case
5589 of structures for which the fields passed exclusively in registers
5590 are not at the beginning of the structure. */
5591 if (parms.stack)
5592 XVECEXP (parms.ret, 0, 0)
5593 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5594
5595 /* Fill in the entries. */
5596 parms.nregs = 0;
5597 parms.intoffset = 0;
5598 function_arg_record_value_2 (type, 0, &parms, false);
5599 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
5600
5601 if (parms.nregs != nregs)
5602 abort ();
5603
5604 return parms.ret;
5605 }
5606
5607 /* Used by function_arg and function_value to implement the conventions
5608 of the 64-bit ABI for passing and returning unions.
5609 Return an expression valid as a return value for the two macros
5610 FUNCTION_ARG and FUNCTION_VALUE.
5611
5612 SIZE is the size in bytes of the union.
5613 MODE is the argument's machine mode.
5614 REGNO is the hard register the union will be passed in. */
5615
5616 static rtx
5617 function_arg_union_value (int size, enum machine_mode mode, int slotno,
5618 int regno)
5619 {
5620 int nwords = ROUND_ADVANCE (size), i;
5621 rtx regs;
5622
5623 /* See comment in previous function for empty structures. */
5624 if (nwords == 0)
5625 return gen_rtx_REG (mode, regno);
5626
5627 if (slotno == SPARC_INT_ARG_MAX - 1)
5628 nwords = 1;
5629
5630 regs = gen_rtx_PARALLEL (mode, rtvec_alloc (nwords));
5631
5632 for (i = 0; i < nwords; i++)
5633 {
5634 /* Unions are passed left-justified. */
5635 XVECEXP (regs, 0, i)
5636 = gen_rtx_EXPR_LIST (VOIDmode,
5637 gen_rtx_REG (word_mode, regno),
5638 GEN_INT (UNITS_PER_WORD * i));
5639 regno++;
5640 }
5641
5642 return regs;
5643 }
5644
5645 /* Used by function_arg and function_value to implement the conventions
5646 for passing and returning large (BLKmode) vectors.
5647 Return an expression valid as a return value for the two macros
5648 FUNCTION_ARG and FUNCTION_VALUE.
5649
5650 SIZE is the size in bytes of the vector.
5651 BASE_MODE is the argument's base machine mode.
5652 REGNO is the FP hard register the vector will be passed in. */
5653
5654 static rtx
5655 function_arg_vector_value (int size, enum machine_mode base_mode, int regno)
5656 {
5657 unsigned short base_mode_size = GET_MODE_SIZE (base_mode);
5658 int nregs = size / base_mode_size, i;
5659 rtx regs;
5660
5661 regs = gen_rtx_PARALLEL (BLKmode, rtvec_alloc (nregs));
5662
5663 for (i = 0; i < nregs; i++)
5664 {
5665 XVECEXP (regs, 0, i)
5666 = gen_rtx_EXPR_LIST (VOIDmode,
5667 gen_rtx_REG (base_mode, regno),
5668 GEN_INT (base_mode_size * i));
5669 regno += base_mode_size / 4;
5670 }
5671
5672 return regs;
5673 }
5674
5675 /* Handle the FUNCTION_ARG macro.
5676 Determine where to put an argument to a function.
5677 Value is zero to push the argument on the stack,
5678 or a hard register in which to store the argument.
5679
5680 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5681 the preceding args and about the function being called.
5682 MODE is the argument's machine mode.
5683 TYPE is the data type of the argument (as a tree).
5684 This is null for libcalls where that information may
5685 not be available.
5686 NAMED is nonzero if this argument is a named parameter
5687 (otherwise it is an extra parameter matching an ellipsis).
5688 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
5689
5690 rtx
5691 function_arg (const struct sparc_args *cum, enum machine_mode mode,
5692 tree type, int named, int incoming_p)
5693 {
5694 int regbase = (incoming_p
5695 ? SPARC_INCOMING_INT_ARG_FIRST
5696 : SPARC_OUTGOING_INT_ARG_FIRST);
5697 int slotno, regno, padding;
5698 enum mode_class mclass = GET_MODE_CLASS (mode);
5699 rtx reg;
5700
5701 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
5702 &regno, &padding);
5703
5704 if (slotno == -1)
5705 return 0;
5706
5707 if (TARGET_ARCH32)
5708 {
5709 reg = gen_rtx_REG (mode, regno);
5710 return reg;
5711 }
5712
5713 if (type && TREE_CODE (type) == RECORD_TYPE)
5714 {
5715 /* Structures up to 16 bytes in size are passed in arg slots on the
5716 stack and are promoted to registers where possible. */
5717
5718 if (int_size_in_bytes (type) > 16)
5719 abort (); /* shouldn't get here */
5720
5721 return function_arg_record_value (type, mode, slotno, named, regbase);
5722 }
5723 else if (type && TREE_CODE (type) == UNION_TYPE)
5724 {
5725 HOST_WIDE_INT size = int_size_in_bytes (type);
5726
5727 if (size > 16)
5728 abort (); /* shouldn't get here */
5729
5730 return function_arg_union_value (size, mode, slotno, regno);
5731 }
5732 else if (type && TREE_CODE (type) == VECTOR_TYPE)
5733 {
5734 /* Vector types deserve special treatment because they are
5735 polymorphic wrt their mode, depending upon whether VIS
5736 instructions are enabled. */
5737 HOST_WIDE_INT size = int_size_in_bytes (type);
5738
5739 if (size > 16)
5740 abort (); /* shouldn't get here */
5741
5742 if (mode == BLKmode)
5743 return function_arg_vector_value (size,
5744 TYPE_MODE (TREE_TYPE (type)),
5745 SPARC_FP_ARG_FIRST + 2*slotno);
5746 else
5747 mclass = MODE_FLOAT;
5748 }
5749
5750 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
5751 but also have the slot allocated for them.
5752 If no prototype is in scope fp values in register slots get passed
5753 in two places, either fp regs and int regs or fp regs and memory. */
5754 if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
5755 && SPARC_FP_REG_P (regno))
5756 {
5757 reg = gen_rtx_REG (mode, regno);
5758 if (cum->prototype_p || cum->libcall_p)
5759 {
5760 /* "* 2" because fp reg numbers are recorded in 4 byte
5761 quantities. */
5762 #if 0
5763 /* ??? This will cause the value to be passed in the fp reg and
5764 in the stack. When a prototype exists we want to pass the
5765 value in the reg but reserve space on the stack. That's an
5766 optimization, and is deferred [for a bit]. */
5767 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
5768 return gen_rtx_PARALLEL (mode,
5769 gen_rtvec (2,
5770 gen_rtx_EXPR_LIST (VOIDmode,
5771 NULL_RTX, const0_rtx),
5772 gen_rtx_EXPR_LIST (VOIDmode,
5773 reg, const0_rtx)));
5774 else
5775 #else
5776 /* ??? It seems that passing back a register even when past
5777 the area declared by REG_PARM_STACK_SPACE will allocate
5778 space appropriately, and will not copy the data onto the
5779 stack, exactly as we desire.
5780
5781 This is due to locate_and_pad_parm being called in
5782 expand_call whenever reg_parm_stack_space > 0, which
5783 while beneficial to our example here, would seem to be
5784 in error from what had been intended. Ho hum... -- r~ */
5785 #endif
5786 return reg;
5787 }
5788 else
5789 {
5790 rtx v0, v1;
5791
5792 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
5793 {
5794 int intreg;
5795
5796 /* On incoming, we don't need to know that the value
5797 is passed in %f0 and %i0, and it confuses other parts
5798 causing needless spillage even on the simplest cases. */
5799 if (incoming_p)
5800 return reg;
5801
5802 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
5803 + (regno - SPARC_FP_ARG_FIRST) / 2);
5804
5805 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5806 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
5807 const0_rtx);
5808 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5809 }
5810 else
5811 {
5812 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5813 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5814 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5815 }
5816 }
5817 }
5818 else
5819 {
5820 /* Scalar or complex int. */
5821 reg = gen_rtx_REG (mode, regno);
5822 }
5823
5824 return reg;
5825 }
5826
5827 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
5828 For an arg passed partly in registers and partly in memory,
5829 this is the number of registers used.
5830 For args passed entirely in registers or entirely in memory, zero.
5831
5832 Any arg that starts in the first 6 regs but won't entirely fit in them
5833 needs partial registers on v8. On v9, structures with integer
5834 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
5835 values that begin in the last fp reg [where "last fp reg" varies with the
5836 mode] will be split between that reg and memory. */
5837
5838 int
5839 function_arg_partial_nregs (const struct sparc_args *cum,
5840 enum machine_mode mode, tree type, int named)
5841 {
5842 int slotno, regno, padding;
5843
5844 /* We pass 0 for incoming_p here, it doesn't matter. */
5845 slotno = function_arg_slotno (cum, mode, type, named, 0, &regno, &padding);
5846
5847 if (slotno == -1)
5848 return 0;
5849
5850 if (TARGET_ARCH32)
5851 {
5852 if ((slotno + (mode == BLKmode
5853 ? ROUND_ADVANCE (int_size_in_bytes (type))
5854 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
5855 > SPARC_INT_ARG_MAX)
5856 return SPARC_INT_ARG_MAX - slotno;
5857 }
5858 else
5859 {
5860 /* We are guaranteed by pass_by_reference that the size of the
5861 argument is not greater than 16 bytes, so we only need to
5862 return 1 if the argument is partially passed in registers. */
5863
5864 if (type && AGGREGATE_TYPE_P (type))
5865 {
5866 int size = int_size_in_bytes (type);
5867
5868 if (size > UNITS_PER_WORD
5869 && slotno == SPARC_INT_ARG_MAX - 1)
5870 return 1;
5871 }
5872 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
5873 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5874 && ! (TARGET_FPU && named)))
5875 {
5876 /* The complex types are passed as packed types. */
5877 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
5878 && slotno == SPARC_INT_ARG_MAX - 1)
5879 return 1;
5880 }
5881 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5882 {
5883 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
5884 > SPARC_FP_ARG_MAX)
5885 return 1;
5886 }
5887 }
5888
5889 return 0;
5890 }
5891
5892 /* Handle the TARGET_PASS_BY_REFERENCE target hook.
5893 Specify whether to pass the argument by reference. */
5894
5895 static bool
5896 sparc_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5897 enum machine_mode mode, tree type,
5898 bool named ATTRIBUTE_UNUSED)
5899 {
5900 if (TARGET_ARCH32)
5901 {
5902 /* Original SPARC 32-bit ABI says that structures and unions,
5903 and quad-precision floats are passed by reference. For Pascal,
5904 also pass arrays by reference. All other base types are passed
5905 in registers.
5906
5907 Extended ABI (as implemented by the Sun compiler) says that all
5908 complex floats are passed by reference. Pass complex integers
5909 in registers up to 8 bytes. More generally, enforce the 2-word
5910 cap for passing arguments in registers.
5911
5912 Vector ABI (as implemented by the Sun VIS SDK) says that vector
5913 integers are passed like floats of the same size, that is in
5914 registers up to 8 bytes. Pass all vector floats by reference
5915 like structure and unions. */
5916 return ((type && (AGGREGATE_TYPE_P (type) || VECTOR_FLOAT_TYPE_P (type)))
5917 || mode == SCmode
5918 /* Catch CDImode, TFmode, DCmode and TCmode. */
5919 || GET_MODE_SIZE (mode) > 8
5920 || (type
5921 && TREE_CODE (type) == VECTOR_TYPE
5922 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8));
5923 }
5924 else
5925 {
5926 /* Original SPARC 64-bit ABI says that structures and unions
5927 smaller than 16 bytes are passed in registers, as well as
5928 all other base types. For Pascal, pass arrays by reference.
5929
5930 Extended ABI (as implemented by the Sun compiler) says that
5931 complex floats are passed in registers up to 16 bytes. Pass
5932 all complex integers in registers up to 16 bytes. More generally,
5933 enforce the 2-word cap for passing arguments in registers.
5934
5935 Vector ABI (as implemented by the Sun VIS SDK) says that vector
5936 integers are passed like floats of the same size, that is in
5937 registers (up to 16 bytes). Pass all vector floats like structure
5938 and unions. */
5939 return ((type && TREE_CODE (type) == ARRAY_TYPE)
5940 || (type
5941 && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == VECTOR_TYPE)
5942 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16)
5943 /* Catch CTImode and TCmode. */
5944 || GET_MODE_SIZE (mode) > 16);
5945 }
5946 }
5947
5948 /* Handle the FUNCTION_ARG_ADVANCE macro.
5949 Update the data in CUM to advance over an argument
5950 of mode MODE and data type TYPE.
5951 TYPE is null for libcalls where that information may not be available. */
5952
5953 void
5954 function_arg_advance (struct sparc_args *cum, enum machine_mode mode,
5955 tree type, int named)
5956 {
5957 int slotno, regno, padding;
5958
5959 /* We pass 0 for incoming_p here, it doesn't matter. */
5960 slotno = function_arg_slotno (cum, mode, type, named, 0, &regno, &padding);
5961
5962 /* If register required leading padding, add it. */
5963 if (slotno != -1)
5964 cum->words += padding;
5965
5966 if (TARGET_ARCH32)
5967 {
5968 cum->words += (mode != BLKmode
5969 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5970 : ROUND_ADVANCE (int_size_in_bytes (type)));
5971 }
5972 else
5973 {
5974 if (type && AGGREGATE_TYPE_P (type))
5975 {
5976 int size = int_size_in_bytes (type);
5977
5978 if (size <= 8)
5979 ++cum->words;
5980 else if (size <= 16)
5981 cum->words += 2;
5982 else /* passed by reference */
5983 ++cum->words;
5984 }
5985 else
5986 {
5987 cum->words += (mode != BLKmode
5988 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5989 : ROUND_ADVANCE (int_size_in_bytes (type)));
5990 }
5991 }
5992 }
5993
5994 /* Handle the FUNCTION_ARG_PADDING macro.
5995 For the 64 bit ABI structs are always stored left shifted in their
5996 argument slot. */
5997
5998 enum direction
5999 function_arg_padding (enum machine_mode mode, tree type)
6000 {
6001 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
6002 return upward;
6003
6004 /* Fall back to the default. */
6005 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
6006 }
6007
6008 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
6009 Specify whether to return the return value in memory. */
6010
6011 static bool
6012 sparc_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
6013 {
6014 if (TARGET_ARCH32)
6015 /* Original SPARC 32-bit ABI says that structures and unions,
6016 and quad-precision floats are returned in memory. All other
6017 base types are returned in registers.
6018
6019 Extended ABI (as implemented by the Sun compiler) says that
6020 all complex floats are returned in registers (8 FP registers
6021 at most for '_Complex long double'). Return all complex integers
6022 in registers (4 at most for '_Complex long long').
6023
6024 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6025 integers are returned like floats of the same size, that is in
6026 registers up to 8 bytes and in memory otherwise. Return all
6027 vector floats in memory like structure and unions; note that
6028 they always have BLKmode like the latter. */
6029 return (TYPE_MODE (type) == BLKmode
6030 || TYPE_MODE (type) == TFmode
6031 || (TREE_CODE (type) == VECTOR_TYPE
6032 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8));
6033 else
6034 /* Original SPARC 64-bit ABI says that structures and unions
6035 smaller than 32 bytes are returned in registers, as well as
6036 all other base types.
6037
6038 Extended ABI (as implemented by the Sun compiler) says that all
6039 complex floats are returned in registers (8 FP registers at most
6040 for '_Complex long double'). Return all complex integers in
6041 registers (4 at most for '_Complex TItype').
6042
6043 Vector ABI (as implemented by the Sun VIS SDK) says that vector
6044 integers are returned like floats of the same size, that is in
6045 registers. Return all vector floats like structure and unions;
6046 note that they always have BLKmode like the latter. */
6047 return ((TYPE_MODE (type) == BLKmode
6048 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 32));
6049 }
6050
6051 /* Handle the TARGET_STRUCT_VALUE target hook.
6052 Return where to find the structure return value address. */
6053
6054 static rtx
6055 sparc_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED, int incoming)
6056 {
6057 if (TARGET_ARCH64)
6058 return 0;
6059 else
6060 {
6061 if (incoming)
6062 return gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx,
6063 STRUCT_VALUE_OFFSET));
6064 else
6065 return gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx,
6066 STRUCT_VALUE_OFFSET));
6067 }
6068 }
6069
6070 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
6071 For v9, function return values are subject to the same rules as arguments,
6072 except that up to 32 bytes may be returned in registers. */
6073
6074 rtx
6075 function_value (tree type, enum machine_mode mode, int incoming_p)
6076 {
6077 /* Beware that the two values are swapped here wrt function_arg. */
6078 int regbase = (incoming_p
6079 ? SPARC_OUTGOING_INT_ARG_FIRST
6080 : SPARC_INCOMING_INT_ARG_FIRST);
6081 enum mode_class mclass = GET_MODE_CLASS (mode);
6082 int regno;
6083
6084 if (type && TREE_CODE (type) == VECTOR_TYPE)
6085 {
6086 /* Vector types deserve special treatment because they are
6087 polymorphic wrt their mode, depending upon whether VIS
6088 instructions are enabled. */
6089 HOST_WIDE_INT size = int_size_in_bytes (type);
6090
6091 if ((TARGET_ARCH32 && size > 8) || (TARGET_ARCH64 && size > 32))
6092 abort (); /* shouldn't get here */
6093
6094 if (mode == BLKmode)
6095 return function_arg_vector_value (size,
6096 TYPE_MODE (TREE_TYPE (type)),
6097 SPARC_FP_ARG_FIRST);
6098 else
6099 mclass = MODE_FLOAT;
6100 }
6101 else if (type && TARGET_ARCH64)
6102 {
6103 if (TREE_CODE (type) == RECORD_TYPE)
6104 {
6105 /* Structures up to 32 bytes in size are passed in registers,
6106 promoted to fp registers where possible. */
6107
6108 if (int_size_in_bytes (type) > 32)
6109 abort (); /* shouldn't get here */
6110
6111 return function_arg_record_value (type, mode, 0, 1, regbase);
6112 }
6113 else if (TREE_CODE (type) == UNION_TYPE)
6114 {
6115 HOST_WIDE_INT size = int_size_in_bytes (type);
6116
6117 if (size > 32)
6118 abort (); /* shouldn't get here */
6119
6120 return function_arg_union_value (size, mode, 0, regbase);
6121 }
6122 else if (AGGREGATE_TYPE_P (type))
6123 {
6124 /* All other aggregate types are passed in an integer register
6125 in a mode corresponding to the size of the type. */
6126 HOST_WIDE_INT bytes = int_size_in_bytes (type);
6127
6128 if (bytes > 32)
6129 abort (); /* shouldn't get here */
6130
6131 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
6132
6133 /* ??? We probably should have made the same ABI change in
6134 3.4.0 as the one we made for unions. The latter was
6135 required by the SCD though, while the former is not
6136 specified, so we favored compatibility and efficiency.
6137
6138 Now we're stuck for aggregates larger than 16 bytes,
6139 because OImode vanished in the meantime. Let's not
6140 try to be unduly clever, and simply follow the ABI
6141 for unions in that case. */
6142 if (mode == BLKmode)
6143 return function_arg_union_value (bytes, mode, 0, regbase);
6144 else
6145 mclass = MODE_INT;
6146 }
6147 else if (mclass == MODE_INT
6148 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
6149 mode = word_mode;
6150 }
6151
6152 if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
6153 && TARGET_FPU)
6154 regno = SPARC_FP_ARG_FIRST;
6155 else
6156 regno = regbase;
6157
6158 return gen_rtx_REG (mode, regno);
6159 }
6160
6161 /* Do what is necessary for `va_start'. We look at the current function
6162 to determine if stdarg or varargs is used and return the address of
6163 the first unnamed parameter. */
6164
6165 static rtx
6166 sparc_builtin_saveregs (void)
6167 {
6168 int first_reg = current_function_args_info.words;
6169 rtx address;
6170 int regno;
6171
6172 for (regno = first_reg; regno < SPARC_INT_ARG_MAX; regno++)
6173 emit_move_insn (gen_rtx_MEM (word_mode,
6174 gen_rtx_PLUS (Pmode,
6175 frame_pointer_rtx,
6176 GEN_INT (FIRST_PARM_OFFSET (0)
6177 + (UNITS_PER_WORD
6178 * regno)))),
6179 gen_rtx_REG (word_mode,
6180 SPARC_INCOMING_INT_ARG_FIRST + regno));
6181
6182 address = gen_rtx_PLUS (Pmode,
6183 frame_pointer_rtx,
6184 GEN_INT (FIRST_PARM_OFFSET (0)
6185 + UNITS_PER_WORD * first_reg));
6186
6187 return address;
6188 }
6189
6190 /* Implement `va_start' for stdarg. */
6191
6192 void
6193 sparc_va_start (tree valist, rtx nextarg)
6194 {
6195 nextarg = expand_builtin_saveregs ();
6196 std_expand_builtin_va_start (valist, nextarg);
6197 }
6198
6199 /* Implement `va_arg' for stdarg. */
6200
6201 static tree
6202 sparc_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
6203 {
6204 HOST_WIDE_INT size, rsize, align;
6205 tree addr, incr;
6206 bool indirect;
6207 tree ptrtype = build_pointer_type (type);
6208
6209 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
6210 {
6211 indirect = true;
6212 size = rsize = UNITS_PER_WORD;
6213 align = 0;
6214 }
6215 else
6216 {
6217 indirect = false;
6218 size = int_size_in_bytes (type);
6219 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
6220 align = 0;
6221
6222 if (TARGET_ARCH64)
6223 {
6224 /* For SPARC64, objects requiring 16-byte alignment get it. */
6225 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
6226 align = 2 * UNITS_PER_WORD;
6227
6228 /* SPARC-V9 ABI states that structures up to 16 bytes in size
6229 are left-justified in their slots. */
6230 if (AGGREGATE_TYPE_P (type))
6231 {
6232 if (size == 0)
6233 size = rsize = UNITS_PER_WORD;
6234 else
6235 size = rsize;
6236 }
6237 }
6238 }
6239
6240 incr = valist;
6241 if (align)
6242 {
6243 incr = fold (build2 (PLUS_EXPR, ptr_type_node, incr,
6244 ssize_int (align - 1)));
6245 incr = fold (build2 (BIT_AND_EXPR, ptr_type_node, incr,
6246 ssize_int (-align)));
6247 }
6248
6249 gimplify_expr (&incr, pre_p, post_p, is_gimple_val, fb_rvalue);
6250 addr = incr;
6251
6252 if (BYTES_BIG_ENDIAN && size < rsize)
6253 addr = fold (build2 (PLUS_EXPR, ptr_type_node, incr,
6254 ssize_int (rsize - size)));
6255
6256 if (indirect)
6257 {
6258 addr = fold_convert (build_pointer_type (ptrtype), addr);
6259 addr = build_va_arg_indirect_ref (addr);
6260 }
6261 /* If the address isn't aligned properly for the type,
6262 we may need to copy to a temporary.
6263 FIXME: This is inefficient. Usually we can do this
6264 in registers. */
6265 else if (align == 0
6266 && TYPE_ALIGN (type) > BITS_PER_WORD)
6267 {
6268 tree tmp = create_tmp_var (type, "va_arg_tmp");
6269 tree dest_addr = build_fold_addr_expr (tmp);
6270
6271 tree copy = build_function_call_expr
6272 (implicit_built_in_decls[BUILT_IN_MEMCPY],
6273 tree_cons (NULL_TREE, dest_addr,
6274 tree_cons (NULL_TREE, addr,
6275 tree_cons (NULL_TREE, size_int (rsize),
6276 NULL_TREE))));
6277
6278 gimplify_and_add (copy, pre_p);
6279 addr = dest_addr;
6280 }
6281 else
6282 addr = fold_convert (ptrtype, addr);
6283
6284 incr = fold (build2 (PLUS_EXPR, ptr_type_node, incr, ssize_int (rsize)));
6285 incr = build2 (MODIFY_EXPR, ptr_type_node, valist, incr);
6286 gimplify_and_add (incr, post_p);
6287
6288 return build_va_arg_indirect_ref (addr);
6289 }
6290 \f
6291 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
6292 Specify whether the vector mode is supported by the hardware. */
6293
6294 static bool
6295 sparc_vector_mode_supported_p (enum machine_mode mode)
6296 {
6297 return TARGET_VIS && VECTOR_MODE_P (mode) ? true : false;
6298 }
6299 \f
6300 /* Return the string to output an unconditional branch to LABEL, which is
6301 the operand number of the label.
6302
6303 DEST is the destination insn (i.e. the label), INSN is the source. */
6304
6305 const char *
6306 output_ubranch (rtx dest, int label, rtx insn)
6307 {
6308 static char string[64];
6309 bool v9_form = false;
6310 char *p;
6311
6312 if (TARGET_V9 && INSN_ADDRESSES_SET_P ())
6313 {
6314 int delta = (INSN_ADDRESSES (INSN_UID (dest))
6315 - INSN_ADDRESSES (INSN_UID (insn)));
6316 /* Leave some instructions for "slop". */
6317 if (delta >= -260000 && delta < 260000)
6318 v9_form = true;
6319 }
6320
6321 if (v9_form)
6322 strcpy (string, "ba%*,pt\t%%xcc, ");
6323 else
6324 strcpy (string, "b%*\t");
6325
6326 p = strchr (string, '\0');
6327 *p++ = '%';
6328 *p++ = 'l';
6329 *p++ = '0' + label;
6330 *p++ = '%';
6331 *p++ = '(';
6332 *p = '\0';
6333
6334 return string;
6335 }
6336
6337 /* Return the string to output a conditional branch to LABEL, which is
6338 the operand number of the label. OP is the conditional expression.
6339 XEXP (OP, 0) is assumed to be a condition code register (integer or
6340 floating point) and its mode specifies what kind of comparison we made.
6341
6342 DEST is the destination insn (i.e. the label), INSN is the source.
6343
6344 REVERSED is nonzero if we should reverse the sense of the comparison.
6345
6346 ANNUL is nonzero if we should generate an annulling branch. */
6347
6348 const char *
6349 output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
6350 rtx insn)
6351 {
6352 static char string[64];
6353 enum rtx_code code = GET_CODE (op);
6354 rtx cc_reg = XEXP (op, 0);
6355 enum machine_mode mode = GET_MODE (cc_reg);
6356 const char *labelno, *branch;
6357 int spaces = 8, far;
6358 char *p;
6359
6360 /* v9 branches are limited to +-1MB. If it is too far away,
6361 change
6362
6363 bne,pt %xcc, .LC30
6364
6365 to
6366
6367 be,pn %xcc, .+12
6368 nop
6369 ba .LC30
6370
6371 and
6372
6373 fbne,a,pn %fcc2, .LC29
6374
6375 to
6376
6377 fbe,pt %fcc2, .+16
6378 nop
6379 ba .LC29 */
6380
6381 far = TARGET_V9 && (get_attr_length (insn) >= 3);
6382 if (reversed ^ far)
6383 {
6384 /* Reversal of FP compares takes care -- an ordered compare
6385 becomes an unordered compare and vice versa. */
6386 if (mode == CCFPmode || mode == CCFPEmode)
6387 code = reverse_condition_maybe_unordered (code);
6388 else
6389 code = reverse_condition (code);
6390 }
6391
6392 /* Start by writing the branch condition. */
6393 if (mode == CCFPmode || mode == CCFPEmode)
6394 {
6395 switch (code)
6396 {
6397 case NE:
6398 branch = "fbne";
6399 break;
6400 case EQ:
6401 branch = "fbe";
6402 break;
6403 case GE:
6404 branch = "fbge";
6405 break;
6406 case GT:
6407 branch = "fbg";
6408 break;
6409 case LE:
6410 branch = "fble";
6411 break;
6412 case LT:
6413 branch = "fbl";
6414 break;
6415 case UNORDERED:
6416 branch = "fbu";
6417 break;
6418 case ORDERED:
6419 branch = "fbo";
6420 break;
6421 case UNGT:
6422 branch = "fbug";
6423 break;
6424 case UNLT:
6425 branch = "fbul";
6426 break;
6427 case UNEQ:
6428 branch = "fbue";
6429 break;
6430 case UNGE:
6431 branch = "fbuge";
6432 break;
6433 case UNLE:
6434 branch = "fbule";
6435 break;
6436 case LTGT:
6437 branch = "fblg";
6438 break;
6439
6440 default:
6441 abort ();
6442 }
6443
6444 /* ??? !v9: FP branches cannot be preceded by another floating point
6445 insn. Because there is currently no concept of pre-delay slots,
6446 we can fix this only by always emitting a nop before a floating
6447 point branch. */
6448
6449 string[0] = '\0';
6450 if (! TARGET_V9)
6451 strcpy (string, "nop\n\t");
6452 strcat (string, branch);
6453 }
6454 else
6455 {
6456 switch (code)
6457 {
6458 case NE:
6459 branch = "bne";
6460 break;
6461 case EQ:
6462 branch = "be";
6463 break;
6464 case GE:
6465 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
6466 branch = "bpos";
6467 else
6468 branch = "bge";
6469 break;
6470 case GT:
6471 branch = "bg";
6472 break;
6473 case LE:
6474 branch = "ble";
6475 break;
6476 case LT:
6477 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
6478 branch = "bneg";
6479 else
6480 branch = "bl";
6481 break;
6482 case GEU:
6483 branch = "bgeu";
6484 break;
6485 case GTU:
6486 branch = "bgu";
6487 break;
6488 case LEU:
6489 branch = "bleu";
6490 break;
6491 case LTU:
6492 branch = "blu";
6493 break;
6494
6495 default:
6496 abort ();
6497 }
6498 strcpy (string, branch);
6499 }
6500 spaces -= strlen (branch);
6501 p = strchr (string, '\0');
6502
6503 /* Now add the annulling, the label, and a possible noop. */
6504 if (annul && ! far)
6505 {
6506 strcpy (p, ",a");
6507 p += 2;
6508 spaces -= 2;
6509 }
6510
6511 if (TARGET_V9)
6512 {
6513 rtx note;
6514 int v8 = 0;
6515
6516 if (! far && insn && INSN_ADDRESSES_SET_P ())
6517 {
6518 int delta = (INSN_ADDRESSES (INSN_UID (dest))
6519 - INSN_ADDRESSES (INSN_UID (insn)));
6520 /* Leave some instructions for "slop". */
6521 if (delta < -260000 || delta >= 260000)
6522 v8 = 1;
6523 }
6524
6525 if (mode == CCFPmode || mode == CCFPEmode)
6526 {
6527 static char v9_fcc_labelno[] = "%%fccX, ";
6528 /* Set the char indicating the number of the fcc reg to use. */
6529 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
6530 labelno = v9_fcc_labelno;
6531 if (v8)
6532 {
6533 if (REGNO (cc_reg) == SPARC_FCC_REG)
6534 labelno = "";
6535 else
6536 abort ();
6537 }
6538 }
6539 else if (mode == CCXmode || mode == CCX_NOOVmode)
6540 {
6541 labelno = "%%xcc, ";
6542 if (v8)
6543 abort ();
6544 }
6545 else
6546 {
6547 labelno = "%%icc, ";
6548 if (v8)
6549 labelno = "";
6550 }
6551
6552 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6553 {
6554 strcpy (p,
6555 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6556 ? ",pt" : ",pn");
6557 p += 3;
6558 spaces -= 3;
6559 }
6560 }
6561 else
6562 labelno = "";
6563
6564 if (spaces > 0)
6565 *p++ = '\t';
6566 else
6567 *p++ = ' ';
6568 strcpy (p, labelno);
6569 p = strchr (p, '\0');
6570 if (far)
6571 {
6572 strcpy (p, ".+12\n\t nop\n\tb\t");
6573 /* Skip the next insn if requested or
6574 if we know that it will be a nop. */
6575 if (annul || ! final_sequence)
6576 p[3] = '6';
6577 p += 14;
6578 }
6579 *p++ = '%';
6580 *p++ = 'l';
6581 *p++ = label + '0';
6582 *p++ = '%';
6583 *p++ = '#';
6584 *p = '\0';
6585
6586 return string;
6587 }
6588
6589 /* Emit a library call comparison between floating point X and Y.
6590 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
6591 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
6592 values as arguments instead of the TFmode registers themselves,
6593 that's why we cannot call emit_float_lib_cmp. */
6594 void
6595 sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison)
6596 {
6597 const char *qpfunc;
6598 rtx slot0, slot1, result, tem, tem2;
6599 enum machine_mode mode;
6600
6601 switch (comparison)
6602 {
6603 case EQ:
6604 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq";
6605 break;
6606
6607 case NE:
6608 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne";
6609 break;
6610
6611 case GT:
6612 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt";
6613 break;
6614
6615 case GE:
6616 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge";
6617 break;
6618
6619 case LT:
6620 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt";
6621 break;
6622
6623 case LE:
6624 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle";
6625 break;
6626
6627 case ORDERED:
6628 case UNORDERED:
6629 case UNGT:
6630 case UNLT:
6631 case UNEQ:
6632 case UNGE:
6633 case UNLE:
6634 case LTGT:
6635 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp";
6636 break;
6637
6638 default:
6639 abort();
6640 break;
6641 }
6642
6643 if (TARGET_ARCH64)
6644 {
6645 if (GET_CODE (x) != MEM)
6646 {
6647 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6648 emit_insn (gen_rtx_SET (VOIDmode, slot0, x));
6649 }
6650 else
6651 slot0 = x;
6652
6653 if (GET_CODE (y) != MEM)
6654 {
6655 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6656 emit_insn (gen_rtx_SET (VOIDmode, slot1, y));
6657 }
6658 else
6659 slot1 = y;
6660
6661 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6662 DImode, 2,
6663 XEXP (slot0, 0), Pmode,
6664 XEXP (slot1, 0), Pmode);
6665
6666 mode = DImode;
6667 }
6668 else
6669 {
6670 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6671 SImode, 2,
6672 x, TFmode, y, TFmode);
6673
6674 mode = SImode;
6675 }
6676
6677
6678 /* Immediately move the result of the libcall into a pseudo
6679 register so reload doesn't clobber the value if it needs
6680 the return register for a spill reg. */
6681 result = gen_reg_rtx (mode);
6682 emit_move_insn (result, hard_libcall_value (mode));
6683
6684 switch (comparison)
6685 {
6686 default:
6687 emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0);
6688 break;
6689 case ORDERED:
6690 case UNORDERED:
6691 emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE,
6692 NULL_RTX, mode, 0);
6693 break;
6694 case UNGT:
6695 case UNGE:
6696 emit_cmp_insn (result, const1_rtx,
6697 comparison == UNGT ? GT : NE, NULL_RTX, mode, 0);
6698 break;
6699 case UNLE:
6700 emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0);
6701 break;
6702 case UNLT:
6703 tem = gen_reg_rtx (mode);
6704 if (TARGET_ARCH32)
6705 emit_insn (gen_andsi3 (tem, result, const1_rtx));
6706 else
6707 emit_insn (gen_anddi3 (tem, result, const1_rtx));
6708 emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0);
6709 break;
6710 case UNEQ:
6711 case LTGT:
6712 tem = gen_reg_rtx (mode);
6713 if (TARGET_ARCH32)
6714 emit_insn (gen_addsi3 (tem, result, const1_rtx));
6715 else
6716 emit_insn (gen_adddi3 (tem, result, const1_rtx));
6717 tem2 = gen_reg_rtx (mode);
6718 if (TARGET_ARCH32)
6719 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
6720 else
6721 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
6722 emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE,
6723 NULL_RTX, mode, 0);
6724 break;
6725 }
6726 }
6727
6728 /* Generate an unsigned DImode to FP conversion. This is the same code
6729 optabs would emit if we didn't have TFmode patterns. */
6730
6731 void
6732 sparc_emit_floatunsdi (rtx *operands, enum machine_mode mode)
6733 {
6734 rtx neglab, donelab, i0, i1, f0, in, out;
6735
6736 out = operands[0];
6737 in = force_reg (DImode, operands[1]);
6738 neglab = gen_label_rtx ();
6739 donelab = gen_label_rtx ();
6740 i0 = gen_reg_rtx (DImode);
6741 i1 = gen_reg_rtx (DImode);
6742 f0 = gen_reg_rtx (mode);
6743
6744 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
6745
6746 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
6747 emit_jump_insn (gen_jump (donelab));
6748 emit_barrier ();
6749
6750 emit_label (neglab);
6751
6752 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
6753 emit_insn (gen_anddi3 (i1, in, const1_rtx));
6754 emit_insn (gen_iordi3 (i0, i0, i1));
6755 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
6756 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
6757
6758 emit_label (donelab);
6759 }
6760
6761 /* Generate an FP to unsigned DImode conversion. This is the same code
6762 optabs would emit if we didn't have TFmode patterns. */
6763
6764 void
6765 sparc_emit_fixunsdi (rtx *operands, enum machine_mode mode)
6766 {
6767 rtx neglab, donelab, i0, i1, f0, in, out, limit;
6768
6769 out = operands[0];
6770 in = force_reg (mode, operands[1]);
6771 neglab = gen_label_rtx ();
6772 donelab = gen_label_rtx ();
6773 i0 = gen_reg_rtx (DImode);
6774 i1 = gen_reg_rtx (DImode);
6775 limit = gen_reg_rtx (mode);
6776 f0 = gen_reg_rtx (mode);
6777
6778 emit_move_insn (limit,
6779 CONST_DOUBLE_FROM_REAL_VALUE (
6780 REAL_VALUE_ATOF ("9223372036854775808.0", mode), mode));
6781 emit_cmp_and_jump_insns (in, limit, GE, NULL_RTX, mode, 0, neglab);
6782
6783 emit_insn (gen_rtx_SET (VOIDmode,
6784 out,
6785 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, in))));
6786 emit_jump_insn (gen_jump (donelab));
6787 emit_barrier ();
6788
6789 emit_label (neglab);
6790
6791 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_MINUS (mode, in, limit)));
6792 emit_insn (gen_rtx_SET (VOIDmode,
6793 i0,
6794 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, f0))));
6795 emit_insn (gen_movdi (i1, const1_rtx));
6796 emit_insn (gen_ashldi3 (i1, i1, GEN_INT (63)));
6797 emit_insn (gen_xordi3 (out, i0, i1));
6798
6799 emit_label (donelab);
6800 }
6801
6802 /* Return the string to output a conditional branch to LABEL, testing
6803 register REG. LABEL is the operand number of the label; REG is the
6804 operand number of the reg. OP is the conditional expression. The mode
6805 of REG says what kind of comparison we made.
6806
6807 DEST is the destination insn (i.e. the label), INSN is the source.
6808
6809 REVERSED is nonzero if we should reverse the sense of the comparison.
6810
6811 ANNUL is nonzero if we should generate an annulling branch. */
6812
6813 const char *
6814 output_v9branch (rtx op, rtx dest, int reg, int label, int reversed,
6815 int annul, rtx insn)
6816 {
6817 static char string[64];
6818 enum rtx_code code = GET_CODE (op);
6819 enum machine_mode mode = GET_MODE (XEXP (op, 0));
6820 rtx note;
6821 int far;
6822 char *p;
6823
6824 /* branch on register are limited to +-128KB. If it is too far away,
6825 change
6826
6827 brnz,pt %g1, .LC30
6828
6829 to
6830
6831 brz,pn %g1, .+12
6832 nop
6833 ba,pt %xcc, .LC30
6834
6835 and
6836
6837 brgez,a,pn %o1, .LC29
6838
6839 to
6840
6841 brlz,pt %o1, .+16
6842 nop
6843 ba,pt %xcc, .LC29 */
6844
6845 far = get_attr_length (insn) >= 3;
6846
6847 /* If not floating-point or if EQ or NE, we can just reverse the code. */
6848 if (reversed ^ far)
6849 code = reverse_condition (code);
6850
6851 /* Only 64 bit versions of these instructions exist. */
6852 if (mode != DImode)
6853 abort ();
6854
6855 /* Start by writing the branch condition. */
6856
6857 switch (code)
6858 {
6859 case NE:
6860 strcpy (string, "brnz");
6861 break;
6862
6863 case EQ:
6864 strcpy (string, "brz");
6865 break;
6866
6867 case GE:
6868 strcpy (string, "brgez");
6869 break;
6870
6871 case LT:
6872 strcpy (string, "brlz");
6873 break;
6874
6875 case LE:
6876 strcpy (string, "brlez");
6877 break;
6878
6879 case GT:
6880 strcpy (string, "brgz");
6881 break;
6882
6883 default:
6884 abort ();
6885 }
6886
6887 p = strchr (string, '\0');
6888
6889 /* Now add the annulling, reg, label, and nop. */
6890 if (annul && ! far)
6891 {
6892 strcpy (p, ",a");
6893 p += 2;
6894 }
6895
6896 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6897 {
6898 strcpy (p,
6899 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6900 ? ",pt" : ",pn");
6901 p += 3;
6902 }
6903
6904 *p = p < string + 8 ? '\t' : ' ';
6905 p++;
6906 *p++ = '%';
6907 *p++ = '0' + reg;
6908 *p++ = ',';
6909 *p++ = ' ';
6910 if (far)
6911 {
6912 int veryfar = 1, delta;
6913
6914 if (INSN_ADDRESSES_SET_P ())
6915 {
6916 delta = (INSN_ADDRESSES (INSN_UID (dest))
6917 - INSN_ADDRESSES (INSN_UID (insn)));
6918 /* Leave some instructions for "slop". */
6919 if (delta >= -260000 && delta < 260000)
6920 veryfar = 0;
6921 }
6922
6923 strcpy (p, ".+12\n\t nop\n\t");
6924 /* Skip the next insn if requested or
6925 if we know that it will be a nop. */
6926 if (annul || ! final_sequence)
6927 p[3] = '6';
6928 p += 12;
6929 if (veryfar)
6930 {
6931 strcpy (p, "b\t");
6932 p += 2;
6933 }
6934 else
6935 {
6936 strcpy (p, "ba,pt\t%%xcc, ");
6937 p += 13;
6938 }
6939 }
6940 *p++ = '%';
6941 *p++ = 'l';
6942 *p++ = '0' + label;
6943 *p++ = '%';
6944 *p++ = '#';
6945 *p = '\0';
6946
6947 return string;
6948 }
6949
6950 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
6951 Such instructions cannot be used in the delay slot of return insn on v9.
6952 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
6953 */
6954
6955 static int
6956 epilogue_renumber (register rtx *where, int test)
6957 {
6958 register const char *fmt;
6959 register int i;
6960 register enum rtx_code code;
6961
6962 if (*where == 0)
6963 return 0;
6964
6965 code = GET_CODE (*where);
6966
6967 switch (code)
6968 {
6969 case REG:
6970 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
6971 return 1;
6972 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
6973 *where = gen_rtx_REG (GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
6974 case SCRATCH:
6975 case CC0:
6976 case PC:
6977 case CONST_INT:
6978 case CONST_DOUBLE:
6979 return 0;
6980
6981 /* Do not replace the frame pointer with the stack pointer because
6982 it can cause the delayed instruction to load below the stack.
6983 This occurs when instructions like:
6984
6985 (set (reg/i:SI 24 %i0)
6986 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
6987 (const_int -20 [0xffffffec])) 0))
6988
6989 are in the return delayed slot. */
6990 case PLUS:
6991 if (GET_CODE (XEXP (*where, 0)) == REG
6992 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
6993 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
6994 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
6995 return 1;
6996 break;
6997
6998 case MEM:
6999 if (SPARC_STACK_BIAS
7000 && GET_CODE (XEXP (*where, 0)) == REG
7001 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
7002 return 1;
7003 break;
7004
7005 default:
7006 break;
7007 }
7008
7009 fmt = GET_RTX_FORMAT (code);
7010
7011 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7012 {
7013 if (fmt[i] == 'E')
7014 {
7015 register int j;
7016 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
7017 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
7018 return 1;
7019 }
7020 else if (fmt[i] == 'e'
7021 && epilogue_renumber (&(XEXP (*where, i)), test))
7022 return 1;
7023 }
7024 return 0;
7025 }
7026 \f
7027 /* Leaf functions and non-leaf functions have different needs. */
7028
7029 static const int
7030 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
7031
7032 static const int
7033 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
7034
7035 static const int *const reg_alloc_orders[] = {
7036 reg_leaf_alloc_order,
7037 reg_nonleaf_alloc_order};
7038
7039 void
7040 order_regs_for_local_alloc (void)
7041 {
7042 static int last_order_nonleaf = 1;
7043
7044 if (regs_ever_live[15] != last_order_nonleaf)
7045 {
7046 last_order_nonleaf = !last_order_nonleaf;
7047 memcpy ((char *) reg_alloc_order,
7048 (const char *) reg_alloc_orders[last_order_nonleaf],
7049 FIRST_PSEUDO_REGISTER * sizeof (int));
7050 }
7051 }
7052 \f
7053 /* Return 1 if REG and MEM are legitimate enough to allow the various
7054 mem<-->reg splits to be run. */
7055
7056 int
7057 sparc_splitdi_legitimate (rtx reg, rtx mem)
7058 {
7059 /* Punt if we are here by mistake. */
7060 if (! reload_completed)
7061 abort ();
7062
7063 /* We must have an offsettable memory reference. */
7064 if (! offsettable_memref_p (mem))
7065 return 0;
7066
7067 /* If we have legitimate args for ldd/std, we do not want
7068 the split to happen. */
7069 if ((REGNO (reg) % 2) == 0
7070 && mem_min_alignment (mem, 8))
7071 return 0;
7072
7073 /* Success. */
7074 return 1;
7075 }
7076
7077 /* Return 1 if x and y are some kind of REG and they refer to
7078 different hard registers. This test is guaranteed to be
7079 run after reload. */
7080
7081 int
7082 sparc_absnegfloat_split_legitimate (rtx x, rtx y)
7083 {
7084 if (GET_CODE (x) != REG)
7085 return 0;
7086 if (GET_CODE (y) != REG)
7087 return 0;
7088 if (REGNO (x) == REGNO (y))
7089 return 0;
7090 return 1;
7091 }
7092
7093 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
7094 This makes them candidates for using ldd and std insns.
7095
7096 Note reg1 and reg2 *must* be hard registers. */
7097
7098 int
7099 registers_ok_for_ldd_peep (rtx reg1, rtx reg2)
7100 {
7101 /* We might have been passed a SUBREG. */
7102 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
7103 return 0;
7104
7105 if (REGNO (reg1) % 2 != 0)
7106 return 0;
7107
7108 /* Integer ldd is deprecated in SPARC V9 */
7109 if (TARGET_V9 && REGNO (reg1) < 32)
7110 return 0;
7111
7112 return (REGNO (reg1) == REGNO (reg2) - 1);
7113 }
7114
7115 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
7116 an ldd or std insn.
7117
7118 This can only happen when addr1 and addr2, the addresses in mem1
7119 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
7120 addr1 must also be aligned on a 64-bit boundary.
7121
7122 Also iff dependent_reg_rtx is not null it should not be used to
7123 compute the address for mem1, i.e. we cannot optimize a sequence
7124 like:
7125 ld [%o0], %o0
7126 ld [%o0 + 4], %o1
7127 to
7128 ldd [%o0], %o0
7129 nor:
7130 ld [%g3 + 4], %g3
7131 ld [%g3], %g2
7132 to
7133 ldd [%g3], %g2
7134
7135 But, note that the transformation from:
7136 ld [%g2 + 4], %g3
7137 ld [%g2], %g2
7138 to
7139 ldd [%g2], %g2
7140 is perfectly fine. Thus, the peephole2 patterns always pass us
7141 the destination register of the first load, never the second one.
7142
7143 For stores we don't have a similar problem, so dependent_reg_rtx is
7144 NULL_RTX. */
7145
7146 int
7147 mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
7148 {
7149 rtx addr1, addr2;
7150 unsigned int reg1;
7151 HOST_WIDE_INT offset1;
7152
7153 /* The mems cannot be volatile. */
7154 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
7155 return 0;
7156
7157 /* MEM1 should be aligned on a 64-bit boundary. */
7158 if (MEM_ALIGN (mem1) < 64)
7159 return 0;
7160
7161 addr1 = XEXP (mem1, 0);
7162 addr2 = XEXP (mem2, 0);
7163
7164 /* Extract a register number and offset (if used) from the first addr. */
7165 if (GET_CODE (addr1) == PLUS)
7166 {
7167 /* If not a REG, return zero. */
7168 if (GET_CODE (XEXP (addr1, 0)) != REG)
7169 return 0;
7170 else
7171 {
7172 reg1 = REGNO (XEXP (addr1, 0));
7173 /* The offset must be constant! */
7174 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
7175 return 0;
7176 offset1 = INTVAL (XEXP (addr1, 1));
7177 }
7178 }
7179 else if (GET_CODE (addr1) != REG)
7180 return 0;
7181 else
7182 {
7183 reg1 = REGNO (addr1);
7184 /* This was a simple (mem (reg)) expression. Offset is 0. */
7185 offset1 = 0;
7186 }
7187
7188 /* Make sure the second address is a (mem (plus (reg) (const_int). */
7189 if (GET_CODE (addr2) != PLUS)
7190 return 0;
7191
7192 if (GET_CODE (XEXP (addr2, 0)) != REG
7193 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
7194 return 0;
7195
7196 if (reg1 != REGNO (XEXP (addr2, 0)))
7197 return 0;
7198
7199 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
7200 return 0;
7201
7202 /* The first offset must be evenly divisible by 8 to ensure the
7203 address is 64 bit aligned. */
7204 if (offset1 % 8 != 0)
7205 return 0;
7206
7207 /* The offset for the second addr must be 4 more than the first addr. */
7208 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
7209 return 0;
7210
7211 /* All the tests passed. addr1 and addr2 are valid for ldd and std
7212 instructions. */
7213 return 1;
7214 }
7215
7216 /* Return 1 if reg is a pseudo, or is the first register in
7217 a hard register pair. This makes it a candidate for use in
7218 ldd and std insns. */
7219
7220 int
7221 register_ok_for_ldd (rtx reg)
7222 {
7223 /* We might have been passed a SUBREG. */
7224 if (GET_CODE (reg) != REG)
7225 return 0;
7226
7227 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
7228 return (REGNO (reg) % 2 == 0);
7229 else
7230 return 1;
7231 }
7232 \f
7233 /* Print operand X (an rtx) in assembler syntax to file FILE.
7234 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
7235 For `%' followed by punctuation, CODE is the punctuation and X is null. */
7236
7237 void
7238 print_operand (FILE *file, rtx x, int code)
7239 {
7240 switch (code)
7241 {
7242 case '#':
7243 /* Output an insn in a delay slot. */
7244 if (final_sequence)
7245 sparc_indent_opcode = 1;
7246 else
7247 fputs ("\n\t nop", file);
7248 return;
7249 case '*':
7250 /* Output an annul flag if there's nothing for the delay slot and we
7251 are optimizing. This is always used with '(' below.
7252 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
7253 this is a dbx bug. So, we only do this when optimizing.
7254 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
7255 Always emit a nop in case the next instruction is a branch. */
7256 if (! final_sequence && (optimize && (int)sparc_cpu < PROCESSOR_V9))
7257 fputs (",a", file);
7258 return;
7259 case '(':
7260 /* Output a 'nop' if there's nothing for the delay slot and we are
7261 not optimizing. This is always used with '*' above. */
7262 if (! final_sequence && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
7263 fputs ("\n\t nop", file);
7264 else if (final_sequence)
7265 sparc_indent_opcode = 1;
7266 return;
7267 case ')':
7268 /* Output the right displacement from the saved PC on function return.
7269 The caller may have placed an "unimp" insn immediately after the call
7270 so we have to account for it. This insn is used in the 32-bit ABI
7271 when calling a function that returns a non zero-sized structure. The
7272 64-bit ABI doesn't have it. Be careful to have this test be the same
7273 as that used on the call. */
7274 if (! TARGET_ARCH64
7275 && current_function_returns_struct
7276 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl)))
7277 == INTEGER_CST)
7278 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))))
7279 fputs ("12", file);
7280 else
7281 fputc ('8', file);
7282 return;
7283 case '_':
7284 /* Output the Embedded Medium/Anywhere code model base register. */
7285 fputs (EMBMEDANY_BASE_REG, file);
7286 return;
7287 case '&':
7288 /* Print some local dynamic TLS name. */
7289 assemble_name (file, get_some_local_dynamic_name ());
7290 return;
7291
7292 case 'Y':
7293 /* Adjust the operand to take into account a RESTORE operation. */
7294 if (GET_CODE (x) == CONST_INT)
7295 break;
7296 else if (GET_CODE (x) != REG)
7297 output_operand_lossage ("invalid %%Y operand");
7298 else if (REGNO (x) < 8)
7299 fputs (reg_names[REGNO (x)], file);
7300 else if (REGNO (x) >= 24 && REGNO (x) < 32)
7301 fputs (reg_names[REGNO (x)-16], file);
7302 else
7303 output_operand_lossage ("invalid %%Y operand");
7304 return;
7305 case 'L':
7306 /* Print out the low order register name of a register pair. */
7307 if (WORDS_BIG_ENDIAN)
7308 fputs (reg_names[REGNO (x)+1], file);
7309 else
7310 fputs (reg_names[REGNO (x)], file);
7311 return;
7312 case 'H':
7313 /* Print out the high order register name of a register pair. */
7314 if (WORDS_BIG_ENDIAN)
7315 fputs (reg_names[REGNO (x)], file);
7316 else
7317 fputs (reg_names[REGNO (x)+1], file);
7318 return;
7319 case 'R':
7320 /* Print out the second register name of a register pair or quad.
7321 I.e., R (%o0) => %o1. */
7322 fputs (reg_names[REGNO (x)+1], file);
7323 return;
7324 case 'S':
7325 /* Print out the third register name of a register quad.
7326 I.e., S (%o0) => %o2. */
7327 fputs (reg_names[REGNO (x)+2], file);
7328 return;
7329 case 'T':
7330 /* Print out the fourth register name of a register quad.
7331 I.e., T (%o0) => %o3. */
7332 fputs (reg_names[REGNO (x)+3], file);
7333 return;
7334 case 'x':
7335 /* Print a condition code register. */
7336 if (REGNO (x) == SPARC_ICC_REG)
7337 {
7338 /* We don't handle CC[X]_NOOVmode because they're not supposed
7339 to occur here. */
7340 if (GET_MODE (x) == CCmode)
7341 fputs ("%icc", file);
7342 else if (GET_MODE (x) == CCXmode)
7343 fputs ("%xcc", file);
7344 else
7345 abort ();
7346 }
7347 else
7348 /* %fccN register */
7349 fputs (reg_names[REGNO (x)], file);
7350 return;
7351 case 'm':
7352 /* Print the operand's address only. */
7353 output_address (XEXP (x, 0));
7354 return;
7355 case 'r':
7356 /* In this case we need a register. Use %g0 if the
7357 operand is const0_rtx. */
7358 if (x == const0_rtx
7359 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
7360 {
7361 fputs ("%g0", file);
7362 return;
7363 }
7364 else
7365 break;
7366
7367 case 'A':
7368 switch (GET_CODE (x))
7369 {
7370 case IOR: fputs ("or", file); break;
7371 case AND: fputs ("and", file); break;
7372 case XOR: fputs ("xor", file); break;
7373 default: output_operand_lossage ("invalid %%A operand");
7374 }
7375 return;
7376
7377 case 'B':
7378 switch (GET_CODE (x))
7379 {
7380 case IOR: fputs ("orn", file); break;
7381 case AND: fputs ("andn", file); break;
7382 case XOR: fputs ("xnor", file); break;
7383 default: output_operand_lossage ("invalid %%B operand");
7384 }
7385 return;
7386
7387 /* These are used by the conditional move instructions. */
7388 case 'c' :
7389 case 'C':
7390 {
7391 enum rtx_code rc = GET_CODE (x);
7392
7393 if (code == 'c')
7394 {
7395 enum machine_mode mode = GET_MODE (XEXP (x, 0));
7396 if (mode == CCFPmode || mode == CCFPEmode)
7397 rc = reverse_condition_maybe_unordered (GET_CODE (x));
7398 else
7399 rc = reverse_condition (GET_CODE (x));
7400 }
7401 switch (rc)
7402 {
7403 case NE: fputs ("ne", file); break;
7404 case EQ: fputs ("e", file); break;
7405 case GE: fputs ("ge", file); break;
7406 case GT: fputs ("g", file); break;
7407 case LE: fputs ("le", file); break;
7408 case LT: fputs ("l", file); break;
7409 case GEU: fputs ("geu", file); break;
7410 case GTU: fputs ("gu", file); break;
7411 case LEU: fputs ("leu", file); break;
7412 case LTU: fputs ("lu", file); break;
7413 case LTGT: fputs ("lg", file); break;
7414 case UNORDERED: fputs ("u", file); break;
7415 case ORDERED: fputs ("o", file); break;
7416 case UNLT: fputs ("ul", file); break;
7417 case UNLE: fputs ("ule", file); break;
7418 case UNGT: fputs ("ug", file); break;
7419 case UNGE: fputs ("uge", file); break;
7420 case UNEQ: fputs ("ue", file); break;
7421 default: output_operand_lossage (code == 'c'
7422 ? "invalid %%c operand"
7423 : "invalid %%C operand");
7424 }
7425 return;
7426 }
7427
7428 /* These are used by the movr instruction pattern. */
7429 case 'd':
7430 case 'D':
7431 {
7432 enum rtx_code rc = (code == 'd'
7433 ? reverse_condition (GET_CODE (x))
7434 : GET_CODE (x));
7435 switch (rc)
7436 {
7437 case NE: fputs ("ne", file); break;
7438 case EQ: fputs ("e", file); break;
7439 case GE: fputs ("gez", file); break;
7440 case LT: fputs ("lz", file); break;
7441 case LE: fputs ("lez", file); break;
7442 case GT: fputs ("gz", file); break;
7443 default: output_operand_lossage (code == 'd'
7444 ? "invalid %%d operand"
7445 : "invalid %%D operand");
7446 }
7447 return;
7448 }
7449
7450 case 'b':
7451 {
7452 /* Print a sign-extended character. */
7453 int i = trunc_int_for_mode (INTVAL (x), QImode);
7454 fprintf (file, "%d", i);
7455 return;
7456 }
7457
7458 case 'f':
7459 /* Operand must be a MEM; write its address. */
7460 if (GET_CODE (x) != MEM)
7461 output_operand_lossage ("invalid %%f operand");
7462 output_address (XEXP (x, 0));
7463 return;
7464
7465 case 's':
7466 {
7467 /* Print a sign-extended 32-bit value. */
7468 HOST_WIDE_INT i;
7469 if (GET_CODE(x) == CONST_INT)
7470 i = INTVAL (x);
7471 else if (GET_CODE(x) == CONST_DOUBLE)
7472 i = CONST_DOUBLE_LOW (x);
7473 else
7474 {
7475 output_operand_lossage ("invalid %%s operand");
7476 return;
7477 }
7478 i = trunc_int_for_mode (i, SImode);
7479 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i);
7480 return;
7481 }
7482
7483 case 0:
7484 /* Do nothing special. */
7485 break;
7486
7487 default:
7488 /* Undocumented flag. */
7489 output_operand_lossage ("invalid operand output code");
7490 }
7491
7492 if (GET_CODE (x) == REG)
7493 fputs (reg_names[REGNO (x)], file);
7494 else if (GET_CODE (x) == MEM)
7495 {
7496 fputc ('[', file);
7497 /* Poor Sun assembler doesn't understand absolute addressing. */
7498 if (CONSTANT_P (XEXP (x, 0)))
7499 fputs ("%g0+", file);
7500 output_address (XEXP (x, 0));
7501 fputc (']', file);
7502 }
7503 else if (GET_CODE (x) == HIGH)
7504 {
7505 fputs ("%hi(", file);
7506 output_addr_const (file, XEXP (x, 0));
7507 fputc (')', file);
7508 }
7509 else if (GET_CODE (x) == LO_SUM)
7510 {
7511 print_operand (file, XEXP (x, 0), 0);
7512 if (TARGET_CM_MEDMID)
7513 fputs ("+%l44(", file);
7514 else
7515 fputs ("+%lo(", file);
7516 output_addr_const (file, XEXP (x, 1));
7517 fputc (')', file);
7518 }
7519 else if (GET_CODE (x) == CONST_DOUBLE
7520 && (GET_MODE (x) == VOIDmode
7521 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
7522 {
7523 if (CONST_DOUBLE_HIGH (x) == 0)
7524 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
7525 else if (CONST_DOUBLE_HIGH (x) == -1
7526 && CONST_DOUBLE_LOW (x) < 0)
7527 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
7528 else
7529 output_operand_lossage ("long long constant not a valid immediate operand");
7530 }
7531 else if (GET_CODE (x) == CONST_DOUBLE)
7532 output_operand_lossage ("floating point constant not a valid immediate operand");
7533 else { output_addr_const (file, x); }
7534 }
7535 \f
7536 /* Target hook for assembling integer objects. The sparc version has
7537 special handling for aligned DI-mode objects. */
7538
7539 static bool
7540 sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
7541 {
7542 /* ??? We only output .xword's for symbols and only then in environments
7543 where the assembler can handle them. */
7544 if (aligned_p && size == 8
7545 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
7546 {
7547 if (TARGET_V9)
7548 {
7549 assemble_integer_with_op ("\t.xword\t", x);
7550 return true;
7551 }
7552 else
7553 {
7554 assemble_aligned_integer (4, const0_rtx);
7555 assemble_aligned_integer (4, x);
7556 return true;
7557 }
7558 }
7559 return default_assemble_integer (x, size, aligned_p);
7560 }
7561 \f
7562 /* Return the value of a code used in the .proc pseudo-op that says
7563 what kind of result this function returns. For non-C types, we pick
7564 the closest C type. */
7565
7566 #ifndef SHORT_TYPE_SIZE
7567 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
7568 #endif
7569
7570 #ifndef INT_TYPE_SIZE
7571 #define INT_TYPE_SIZE BITS_PER_WORD
7572 #endif
7573
7574 #ifndef LONG_TYPE_SIZE
7575 #define LONG_TYPE_SIZE BITS_PER_WORD
7576 #endif
7577
7578 #ifndef LONG_LONG_TYPE_SIZE
7579 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
7580 #endif
7581
7582 #ifndef FLOAT_TYPE_SIZE
7583 #define FLOAT_TYPE_SIZE BITS_PER_WORD
7584 #endif
7585
7586 #ifndef DOUBLE_TYPE_SIZE
7587 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7588 #endif
7589
7590 #ifndef LONG_DOUBLE_TYPE_SIZE
7591 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7592 #endif
7593
7594 unsigned long
7595 sparc_type_code (register tree type)
7596 {
7597 register unsigned long qualifiers = 0;
7598 register unsigned shift;
7599
7600 /* Only the first 30 bits of the qualifier are valid. We must refrain from
7601 setting more, since some assemblers will give an error for this. Also,
7602 we must be careful to avoid shifts of 32 bits or more to avoid getting
7603 unpredictable results. */
7604
7605 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
7606 {
7607 switch (TREE_CODE (type))
7608 {
7609 case ERROR_MARK:
7610 return qualifiers;
7611
7612 case ARRAY_TYPE:
7613 qualifiers |= (3 << shift);
7614 break;
7615
7616 case FUNCTION_TYPE:
7617 case METHOD_TYPE:
7618 qualifiers |= (2 << shift);
7619 break;
7620
7621 case POINTER_TYPE:
7622 case REFERENCE_TYPE:
7623 case OFFSET_TYPE:
7624 qualifiers |= (1 << shift);
7625 break;
7626
7627 case RECORD_TYPE:
7628 return (qualifiers | 8);
7629
7630 case UNION_TYPE:
7631 case QUAL_UNION_TYPE:
7632 return (qualifiers | 9);
7633
7634 case ENUMERAL_TYPE:
7635 return (qualifiers | 10);
7636
7637 case VOID_TYPE:
7638 return (qualifiers | 16);
7639
7640 case INTEGER_TYPE:
7641 /* If this is a range type, consider it to be the underlying
7642 type. */
7643 if (TREE_TYPE (type) != 0)
7644 break;
7645
7646 /* Carefully distinguish all the standard types of C,
7647 without messing up if the language is not C. We do this by
7648 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
7649 look at both the names and the above fields, but that's redundant.
7650 Any type whose size is between two C types will be considered
7651 to be the wider of the two types. Also, we do not have a
7652 special code to use for "long long", so anything wider than
7653 long is treated the same. Note that we can't distinguish
7654 between "int" and "long" in this code if they are the same
7655 size, but that's fine, since neither can the assembler. */
7656
7657 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
7658 return (qualifiers | (TYPE_UNSIGNED (type) ? 12 : 2));
7659
7660 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
7661 return (qualifiers | (TYPE_UNSIGNED (type) ? 13 : 3));
7662
7663 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
7664 return (qualifiers | (TYPE_UNSIGNED (type) ? 14 : 4));
7665
7666 else
7667 return (qualifiers | (TYPE_UNSIGNED (type) ? 15 : 5));
7668
7669 case REAL_TYPE:
7670 /* If this is a range type, consider it to be the underlying
7671 type. */
7672 if (TREE_TYPE (type) != 0)
7673 break;
7674
7675 /* Carefully distinguish all the standard types of C,
7676 without messing up if the language is not C. */
7677
7678 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
7679 return (qualifiers | 6);
7680
7681 else
7682 return (qualifiers | 7);
7683
7684 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
7685 /* ??? We need to distinguish between double and float complex types,
7686 but I don't know how yet because I can't reach this code from
7687 existing front-ends. */
7688 return (qualifiers | 7); /* Who knows? */
7689
7690 case VECTOR_TYPE:
7691 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
7692 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
7693 case FILE_TYPE: /* GNU Pascal FILE type. */
7694 case SET_TYPE: /* GNU Pascal SET type. */
7695 case LANG_TYPE: /* ? */
7696 return qualifiers;
7697
7698 default:
7699 abort (); /* Not a type! */
7700 }
7701 }
7702
7703 return qualifiers;
7704 }
7705 \f
7706 /* Nested function support. */
7707
7708 /* Emit RTL insns to initialize the variable parts of a trampoline.
7709 FNADDR is an RTX for the address of the function's pure code.
7710 CXT is an RTX for the static chain value for the function.
7711
7712 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
7713 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
7714 (to store insns). This is a bit excessive. Perhaps a different
7715 mechanism would be better here.
7716
7717 Emit enough FLUSH insns to synchronize the data and instruction caches. */
7718
7719 void
7720 sparc_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7721 {
7722 /* SPARC 32-bit trampoline:
7723
7724 sethi %hi(fn), %g1
7725 sethi %hi(static), %g2
7726 jmp %g1+%lo(fn)
7727 or %g2, %lo(static), %g2
7728
7729 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
7730 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
7731 */
7732
7733 emit_move_insn
7734 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
7735 expand_binop (SImode, ior_optab,
7736 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
7737 size_int (10), 0, 1),
7738 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
7739 NULL_RTX, 1, OPTAB_DIRECT));
7740
7741 emit_move_insn
7742 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7743 expand_binop (SImode, ior_optab,
7744 expand_shift (RSHIFT_EXPR, SImode, cxt,
7745 size_int (10), 0, 1),
7746 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
7747 NULL_RTX, 1, OPTAB_DIRECT));
7748
7749 emit_move_insn
7750 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7751 expand_binop (SImode, ior_optab,
7752 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
7753 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
7754 NULL_RTX, 1, OPTAB_DIRECT));
7755
7756 emit_move_insn
7757 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7758 expand_binop (SImode, ior_optab,
7759 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
7760 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
7761 NULL_RTX, 1, OPTAB_DIRECT));
7762
7763 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
7764 aligned on a 16 byte boundary so one flush clears it all. */
7765 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
7766 if (sparc_cpu != PROCESSOR_ULTRASPARC
7767 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7768 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
7769 plus_constant (tramp, 8)))));
7770
7771 /* Call __enable_execute_stack after writing onto the stack to make sure
7772 the stack address is accessible. */
7773 #ifdef ENABLE_EXECUTE_STACK
7774 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
7775 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7776 #endif
7777
7778 }
7779
7780 /* The 64-bit version is simpler because it makes more sense to load the
7781 values as "immediate" data out of the trampoline. It's also easier since
7782 we can read the PC without clobbering a register. */
7783
7784 void
7785 sparc64_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7786 {
7787 /* SPARC 64-bit trampoline:
7788
7789 rd %pc, %g1
7790 ldx [%g1+24], %g5
7791 jmp %g5
7792 ldx [%g1+16], %g5
7793 +16 bytes data
7794 */
7795
7796 emit_move_insn (gen_rtx_MEM (SImode, tramp),
7797 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
7798 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7799 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
7800 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7801 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
7802 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7803 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
7804 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
7805 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
7806 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
7807
7808 if (sparc_cpu != PROCESSOR_ULTRASPARC
7809 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7810 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
7811
7812 /* Call __enable_execute_stack after writing onto the stack to make sure
7813 the stack address is accessible. */
7814 #ifdef ENABLE_EXECUTE_STACK
7815 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
7816 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7817 #endif
7818 }
7819 \f
7820 /* Adjust the cost of a scheduling dependency. Return the new cost of
7821 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7822
7823 static int
7824 supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
7825 {
7826 enum attr_type insn_type;
7827
7828 if (! recog_memoized (insn))
7829 return 0;
7830
7831 insn_type = get_attr_type (insn);
7832
7833 if (REG_NOTE_KIND (link) == 0)
7834 {
7835 /* Data dependency; DEP_INSN writes a register that INSN reads some
7836 cycles later. */
7837
7838 /* if a load, then the dependence must be on the memory address;
7839 add an extra "cycle". Note that the cost could be two cycles
7840 if the reg was written late in an instruction group; we ca not tell
7841 here. */
7842 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
7843 return cost + 3;
7844
7845 /* Get the delay only if the address of the store is the dependence. */
7846 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
7847 {
7848 rtx pat = PATTERN(insn);
7849 rtx dep_pat = PATTERN (dep_insn);
7850
7851 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7852 return cost; /* This should not happen! */
7853
7854 /* The dependency between the two instructions was on the data that
7855 is being stored. Assume that this implies that the address of the
7856 store is not dependent. */
7857 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7858 return cost;
7859
7860 return cost + 3; /* An approximation. */
7861 }
7862
7863 /* A shift instruction cannot receive its data from an instruction
7864 in the same cycle; add a one cycle penalty. */
7865 if (insn_type == TYPE_SHIFT)
7866 return cost + 3; /* Split before cascade into shift. */
7867 }
7868 else
7869 {
7870 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7871 INSN writes some cycles later. */
7872
7873 /* These are only significant for the fpu unit; writing a fp reg before
7874 the fpu has finished with it stalls the processor. */
7875
7876 /* Reusing an integer register causes no problems. */
7877 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7878 return 0;
7879 }
7880
7881 return cost;
7882 }
7883
7884 static int
7885 hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
7886 {
7887 enum attr_type insn_type, dep_type;
7888 rtx pat = PATTERN(insn);
7889 rtx dep_pat = PATTERN (dep_insn);
7890
7891 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
7892 return cost;
7893
7894 insn_type = get_attr_type (insn);
7895 dep_type = get_attr_type (dep_insn);
7896
7897 switch (REG_NOTE_KIND (link))
7898 {
7899 case 0:
7900 /* Data dependency; DEP_INSN writes a register that INSN reads some
7901 cycles later. */
7902
7903 switch (insn_type)
7904 {
7905 case TYPE_STORE:
7906 case TYPE_FPSTORE:
7907 /* Get the delay iff the address of the store is the dependence. */
7908 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7909 return cost;
7910
7911 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7912 return cost;
7913 return cost + 3;
7914
7915 case TYPE_LOAD:
7916 case TYPE_SLOAD:
7917 case TYPE_FPLOAD:
7918 /* If a load, then the dependence must be on the memory address. If
7919 the addresses aren't equal, then it might be a false dependency */
7920 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
7921 {
7922 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
7923 || GET_CODE (SET_DEST (dep_pat)) != MEM
7924 || GET_CODE (SET_SRC (pat)) != MEM
7925 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
7926 XEXP (SET_SRC (pat), 0)))
7927 return cost + 2;
7928
7929 return cost + 8;
7930 }
7931 break;
7932
7933 case TYPE_BRANCH:
7934 /* Compare to branch latency is 0. There is no benefit from
7935 separating compare and branch. */
7936 if (dep_type == TYPE_COMPARE)
7937 return 0;
7938 /* Floating point compare to branch latency is less than
7939 compare to conditional move. */
7940 if (dep_type == TYPE_FPCMP)
7941 return cost - 1;
7942 break;
7943 default:
7944 break;
7945 }
7946 break;
7947
7948 case REG_DEP_ANTI:
7949 /* Anti-dependencies only penalize the fpu unit. */
7950 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7951 return 0;
7952 break;
7953
7954 default:
7955 break;
7956 }
7957
7958 return cost;
7959 }
7960
7961 static int
7962 sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost)
7963 {
7964 switch (sparc_cpu)
7965 {
7966 case PROCESSOR_SUPERSPARC:
7967 cost = supersparc_adjust_cost (insn, link, dep, cost);
7968 break;
7969 case PROCESSOR_HYPERSPARC:
7970 case PROCESSOR_SPARCLITE86X:
7971 cost = hypersparc_adjust_cost (insn, link, dep, cost);
7972 break;
7973 default:
7974 break;
7975 }
7976 return cost;
7977 }
7978
7979 static void
7980 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED,
7981 int sched_verbose ATTRIBUTE_UNUSED,
7982 int max_ready ATTRIBUTE_UNUSED)
7983 {
7984 }
7985
7986 static int
7987 sparc_use_sched_lookahead (void)
7988 {
7989 if (sparc_cpu == PROCESSOR_ULTRASPARC
7990 || sparc_cpu == PROCESSOR_ULTRASPARC3)
7991 return 4;
7992 if ((1 << sparc_cpu) &
7993 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
7994 (1 << PROCESSOR_SPARCLITE86X)))
7995 return 3;
7996 return 0;
7997 }
7998
7999 static int
8000 sparc_issue_rate (void)
8001 {
8002 switch (sparc_cpu)
8003 {
8004 default:
8005 return 1;
8006 case PROCESSOR_V9:
8007 /* Assume V9 processors are capable of at least dual-issue. */
8008 return 2;
8009 case PROCESSOR_SUPERSPARC:
8010 return 3;
8011 case PROCESSOR_HYPERSPARC:
8012 case PROCESSOR_SPARCLITE86X:
8013 return 2;
8014 case PROCESSOR_ULTRASPARC:
8015 case PROCESSOR_ULTRASPARC3:
8016 return 4;
8017 }
8018 }
8019
8020 static int
8021 set_extends (rtx insn)
8022 {
8023 register rtx pat = PATTERN (insn);
8024
8025 switch (GET_CODE (SET_SRC (pat)))
8026 {
8027 /* Load and some shift instructions zero extend. */
8028 case MEM:
8029 case ZERO_EXTEND:
8030 /* sethi clears the high bits */
8031 case HIGH:
8032 /* LO_SUM is used with sethi. sethi cleared the high
8033 bits and the values used with lo_sum are positive */
8034 case LO_SUM:
8035 /* Store flag stores 0 or 1 */
8036 case LT: case LTU:
8037 case GT: case GTU:
8038 case LE: case LEU:
8039 case GE: case GEU:
8040 case EQ:
8041 case NE:
8042 return 1;
8043 case AND:
8044 {
8045 rtx op0 = XEXP (SET_SRC (pat), 0);
8046 rtx op1 = XEXP (SET_SRC (pat), 1);
8047 if (GET_CODE (op1) == CONST_INT)
8048 return INTVAL (op1) >= 0;
8049 if (GET_CODE (op0) != REG)
8050 return 0;
8051 if (sparc_check_64 (op0, insn) == 1)
8052 return 1;
8053 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8054 }
8055 case IOR:
8056 case XOR:
8057 {
8058 rtx op0 = XEXP (SET_SRC (pat), 0);
8059 rtx op1 = XEXP (SET_SRC (pat), 1);
8060 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
8061 return 0;
8062 if (GET_CODE (op1) == CONST_INT)
8063 return INTVAL (op1) >= 0;
8064 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8065 }
8066 case LSHIFTRT:
8067 return GET_MODE (SET_SRC (pat)) == SImode;
8068 /* Positive integers leave the high bits zero. */
8069 case CONST_DOUBLE:
8070 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
8071 case CONST_INT:
8072 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
8073 case ASHIFTRT:
8074 case SIGN_EXTEND:
8075 return - (GET_MODE (SET_SRC (pat)) == SImode);
8076 case REG:
8077 return sparc_check_64 (SET_SRC (pat), insn);
8078 default:
8079 return 0;
8080 }
8081 }
8082
8083 /* We _ought_ to have only one kind per function, but... */
8084 static GTY(()) rtx sparc_addr_diff_list;
8085 static GTY(()) rtx sparc_addr_list;
8086
8087 void
8088 sparc_defer_case_vector (rtx lab, rtx vec, int diff)
8089 {
8090 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
8091 if (diff)
8092 sparc_addr_diff_list
8093 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
8094 else
8095 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
8096 }
8097
8098 static void
8099 sparc_output_addr_vec (rtx vec)
8100 {
8101 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8102 int idx, vlen = XVECLEN (body, 0);
8103
8104 #ifdef ASM_OUTPUT_ADDR_VEC_START
8105 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8106 #endif
8107
8108 #ifdef ASM_OUTPUT_CASE_LABEL
8109 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8110 NEXT_INSN (lab));
8111 #else
8112 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8113 #endif
8114
8115 for (idx = 0; idx < vlen; idx++)
8116 {
8117 ASM_OUTPUT_ADDR_VEC_ELT
8118 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
8119 }
8120
8121 #ifdef ASM_OUTPUT_ADDR_VEC_END
8122 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8123 #endif
8124 }
8125
8126 static void
8127 sparc_output_addr_diff_vec (rtx vec)
8128 {
8129 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8130 rtx base = XEXP (XEXP (body, 0), 0);
8131 int idx, vlen = XVECLEN (body, 1);
8132
8133 #ifdef ASM_OUTPUT_ADDR_VEC_START
8134 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8135 #endif
8136
8137 #ifdef ASM_OUTPUT_CASE_LABEL
8138 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8139 NEXT_INSN (lab));
8140 #else
8141 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8142 #endif
8143
8144 for (idx = 0; idx < vlen; idx++)
8145 {
8146 ASM_OUTPUT_ADDR_DIFF_ELT
8147 (asm_out_file,
8148 body,
8149 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
8150 CODE_LABEL_NUMBER (base));
8151 }
8152
8153 #ifdef ASM_OUTPUT_ADDR_VEC_END
8154 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8155 #endif
8156 }
8157
8158 static void
8159 sparc_output_deferred_case_vectors (void)
8160 {
8161 rtx t;
8162 int align;
8163
8164 if (sparc_addr_list == NULL_RTX
8165 && sparc_addr_diff_list == NULL_RTX)
8166 return;
8167
8168 /* Align to cache line in the function's code section. */
8169 function_section (current_function_decl);
8170
8171 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
8172 if (align > 0)
8173 ASM_OUTPUT_ALIGN (asm_out_file, align);
8174
8175 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
8176 sparc_output_addr_vec (XEXP (t, 0));
8177 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
8178 sparc_output_addr_diff_vec (XEXP (t, 0));
8179
8180 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
8181 }
8182
8183 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
8184 unknown. Return 1 if the high bits are zero, -1 if the register is
8185 sign extended. */
8186 int
8187 sparc_check_64 (rtx x, rtx insn)
8188 {
8189 /* If a register is set only once it is safe to ignore insns this
8190 code does not know how to handle. The loop will either recognize
8191 the single set and return the correct value or fail to recognize
8192 it and return 0. */
8193 int set_once = 0;
8194 rtx y = x;
8195
8196 if (GET_CODE (x) != REG)
8197 abort ();
8198
8199 if (GET_MODE (x) == DImode)
8200 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
8201
8202 if (flag_expensive_optimizations
8203 && REG_N_SETS (REGNO (y)) == 1)
8204 set_once = 1;
8205
8206 if (insn == 0)
8207 {
8208 if (set_once)
8209 insn = get_last_insn_anywhere ();
8210 else
8211 return 0;
8212 }
8213
8214 while ((insn = PREV_INSN (insn)))
8215 {
8216 switch (GET_CODE (insn))
8217 {
8218 case JUMP_INSN:
8219 case NOTE:
8220 break;
8221 case CODE_LABEL:
8222 case CALL_INSN:
8223 default:
8224 if (! set_once)
8225 return 0;
8226 break;
8227 case INSN:
8228 {
8229 rtx pat = PATTERN (insn);
8230 if (GET_CODE (pat) != SET)
8231 return 0;
8232 if (rtx_equal_p (x, SET_DEST (pat)))
8233 return set_extends (insn);
8234 if (y && rtx_equal_p (y, SET_DEST (pat)))
8235 return set_extends (insn);
8236 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
8237 return 0;
8238 }
8239 }
8240 }
8241 return 0;
8242 }
8243
8244 /* Returns assembly code to perform a DImode shift using
8245 a 64-bit global or out register on SPARC-V8+. */
8246 const char *
8247 output_v8plus_shift (rtx *operands, rtx insn, const char *opcode)
8248 {
8249 static char asm_code[60];
8250
8251 /* The scratch register is only required when the destination
8252 register is not a 64-bit global or out register. */
8253 if (which_alternative != 2)
8254 operands[3] = operands[0];
8255
8256 /* We can only shift by constants <= 63. */
8257 if (GET_CODE (operands[2]) == CONST_INT)
8258 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
8259
8260 if (GET_CODE (operands[1]) == CONST_INT)
8261 {
8262 output_asm_insn ("mov\t%1, %3", operands);
8263 }
8264 else
8265 {
8266 output_asm_insn ("sllx\t%H1, 32, %3", operands);
8267 if (sparc_check_64 (operands[1], insn) <= 0)
8268 output_asm_insn ("srl\t%L1, 0, %L1", operands);
8269 output_asm_insn ("or\t%L1, %3, %3", operands);
8270 }
8271
8272 strcpy(asm_code, opcode);
8273
8274 if (which_alternative != 2)
8275 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
8276 else
8277 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
8278 }
8279 \f
8280 /* Output rtl to increment the profiler label LABELNO
8281 for profiling a function entry. */
8282
8283 void
8284 sparc_profile_hook (int labelno)
8285 {
8286 char buf[32];
8287 rtx lab, fun;
8288
8289 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
8290 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
8291 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
8292
8293 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
8294 }
8295 \f
8296 #ifdef OBJECT_FORMAT_ELF
8297 static void
8298 sparc_elf_asm_named_section (const char *name, unsigned int flags,
8299 tree decl)
8300 {
8301 if (flags & SECTION_MERGE)
8302 {
8303 /* entsize cannot be expressed in this section attributes
8304 encoding style. */
8305 default_elf_asm_named_section (name, flags, decl);
8306 return;
8307 }
8308
8309 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
8310
8311 if (!(flags & SECTION_DEBUG))
8312 fputs (",#alloc", asm_out_file);
8313 if (flags & SECTION_WRITE)
8314 fputs (",#write", asm_out_file);
8315 if (flags & SECTION_TLS)
8316 fputs (",#tls", asm_out_file);
8317 if (flags & SECTION_CODE)
8318 fputs (",#execinstr", asm_out_file);
8319
8320 /* ??? Handle SECTION_BSS. */
8321
8322 fputc ('\n', asm_out_file);
8323 }
8324 #endif /* OBJECT_FORMAT_ELF */
8325
8326 /* We do not allow indirect calls to be optimized into sibling calls.
8327
8328 We cannot use sibling calls when delayed branches are disabled
8329 because they will likely require the call delay slot to be filled.
8330
8331 Also, on SPARC 32-bit we cannot emit a sibling call when the
8332 current function returns a structure. This is because the "unimp
8333 after call" convention would cause the callee to return to the
8334 wrong place. The generic code already disallows cases where the
8335 function being called returns a structure.
8336
8337 It may seem strange how this last case could occur. Usually there
8338 is code after the call which jumps to epilogue code which dumps the
8339 return value into the struct return area. That ought to invalidate
8340 the sibling call right? Well, in the C++ case we can end up passing
8341 the pointer to the struct return area to a constructor (which returns
8342 void) and then nothing else happens. Such a sibling call would look
8343 valid without the added check here. */
8344 static bool
8345 sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8346 {
8347 return (decl
8348 && flag_delayed_branch
8349 && (TARGET_ARCH64 || ! current_function_returns_struct));
8350 }
8351 \f
8352 /* libfunc renaming. */
8353 #include "config/gofast.h"
8354
8355 static void
8356 sparc_init_libfuncs (void)
8357 {
8358 if (TARGET_ARCH32)
8359 {
8360 /* Use the subroutines that Sun's library provides for integer
8361 multiply and divide. The `*' prevents an underscore from
8362 being prepended by the compiler. .umul is a little faster
8363 than .mul. */
8364 set_optab_libfunc (smul_optab, SImode, "*.umul");
8365 set_optab_libfunc (sdiv_optab, SImode, "*.div");
8366 set_optab_libfunc (udiv_optab, SImode, "*.udiv");
8367 set_optab_libfunc (smod_optab, SImode, "*.rem");
8368 set_optab_libfunc (umod_optab, SImode, "*.urem");
8369
8370 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
8371 set_optab_libfunc (add_optab, TFmode, "_Q_add");
8372 set_optab_libfunc (sub_optab, TFmode, "_Q_sub");
8373 set_optab_libfunc (neg_optab, TFmode, "_Q_neg");
8374 set_optab_libfunc (smul_optab, TFmode, "_Q_mul");
8375 set_optab_libfunc (sdiv_optab, TFmode, "_Q_div");
8376
8377 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
8378 is because with soft-float, the SFmode and DFmode sqrt
8379 instructions will be absent, and the compiler will notice and
8380 try to use the TFmode sqrt instruction for calls to the
8381 builtin function sqrt, but this fails. */
8382 if (TARGET_FPU)
8383 set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt");
8384
8385 set_optab_libfunc (eq_optab, TFmode, "_Q_feq");
8386 set_optab_libfunc (ne_optab, TFmode, "_Q_fne");
8387 set_optab_libfunc (gt_optab, TFmode, "_Q_fgt");
8388 set_optab_libfunc (ge_optab, TFmode, "_Q_fge");
8389 set_optab_libfunc (lt_optab, TFmode, "_Q_flt");
8390 set_optab_libfunc (le_optab, TFmode, "_Q_fle");
8391
8392 set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq");
8393 set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq");
8394 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos");
8395 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod");
8396
8397 set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi");
8398 set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou");
8399 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq");
8400
8401 if (DITF_CONVERSION_LIBFUNCS)
8402 {
8403 set_conv_libfunc (sfix_optab, DImode, TFmode, "_Q_qtoll");
8404 set_conv_libfunc (ufix_optab, DImode, TFmode, "_Q_qtoull");
8405 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_Q_lltoq");
8406 }
8407
8408 if (SUN_CONVERSION_LIBFUNCS)
8409 {
8410 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8411 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8412 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8413 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8414 }
8415 }
8416 if (TARGET_ARCH64)
8417 {
8418 /* In the SPARC 64bit ABI, SImode multiply and divide functions
8419 do not exist in the library. Make sure the compiler does not
8420 emit calls to them by accident. (It should always use the
8421 hardware instructions.) */
8422 set_optab_libfunc (smul_optab, SImode, 0);
8423 set_optab_libfunc (sdiv_optab, SImode, 0);
8424 set_optab_libfunc (udiv_optab, SImode, 0);
8425 set_optab_libfunc (smod_optab, SImode, 0);
8426 set_optab_libfunc (umod_optab, SImode, 0);
8427
8428 if (SUN_INTEGER_MULTIPLY_64)
8429 {
8430 set_optab_libfunc (smul_optab, DImode, "__mul64");
8431 set_optab_libfunc (sdiv_optab, DImode, "__div64");
8432 set_optab_libfunc (udiv_optab, DImode, "__udiv64");
8433 set_optab_libfunc (smod_optab, DImode, "__rem64");
8434 set_optab_libfunc (umod_optab, DImode, "__urem64");
8435 }
8436
8437 if (SUN_CONVERSION_LIBFUNCS)
8438 {
8439 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol");
8440 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul");
8441 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol");
8442 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul");
8443 }
8444 }
8445
8446 gofast_maybe_init_libfuncs ();
8447 }
8448 \f
8449 int
8450 sparc_extra_constraint_check (rtx op, int c, int strict)
8451 {
8452 int reload_ok_mem;
8453
8454 if (TARGET_ARCH64
8455 && (c == 'T' || c == 'U'))
8456 return 0;
8457
8458 switch (c)
8459 {
8460 case 'Q':
8461 return fp_sethi_p (op);
8462
8463 case 'R':
8464 return fp_mov_p (op);
8465
8466 case 'S':
8467 return fp_high_losum_p (op);
8468
8469 case 'U':
8470 if (! strict
8471 || (GET_CODE (op) == REG
8472 && (REGNO (op) < FIRST_PSEUDO_REGISTER
8473 || reg_renumber[REGNO (op)] >= 0)))
8474 return register_ok_for_ldd (op);
8475
8476 return 0;
8477
8478 case 'W':
8479 case 'T':
8480 break;
8481
8482 case 'Y':
8483 return fp_zero_operand (op, GET_MODE (op));
8484
8485 default:
8486 return 0;
8487 }
8488
8489 /* Our memory extra constraints have to emulate the
8490 behavior of 'm' and 'o' in order for reload to work
8491 correctly. */
8492 if (GET_CODE (op) == MEM)
8493 {
8494 reload_ok_mem = 0;
8495 if ((TARGET_ARCH64 || mem_min_alignment (op, 8))
8496 && (! strict
8497 || strict_memory_address_p (Pmode, XEXP (op, 0))))
8498 reload_ok_mem = 1;
8499 }
8500 else
8501 {
8502 reload_ok_mem = (reload_in_progress
8503 && GET_CODE (op) == REG
8504 && REGNO (op) >= FIRST_PSEUDO_REGISTER
8505 && reg_renumber [REGNO (op)] < 0);
8506 }
8507
8508 return reload_ok_mem;
8509 }
8510
8511 /* ??? This duplicates information provided to the compiler by the
8512 ??? scheduler description. Some day, teach genautomata to output
8513 ??? the latencies and then CSE will just use that. */
8514
8515 static bool
8516 sparc_rtx_costs (rtx x, int code, int outer_code, int *total)
8517 {
8518 enum machine_mode mode = GET_MODE (x);
8519 bool float_mode_p = FLOAT_MODE_P (mode);
8520
8521 switch (code)
8522 {
8523 case CONST_INT:
8524 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
8525 {
8526 *total = 0;
8527 return true;
8528 }
8529 /* FALLTHRU */
8530
8531 case HIGH:
8532 *total = 2;
8533 return true;
8534
8535 case CONST:
8536 case LABEL_REF:
8537 case SYMBOL_REF:
8538 *total = 4;
8539 return true;
8540
8541 case CONST_DOUBLE:
8542 if (GET_MODE (x) == DImode
8543 && ((XINT (x, 3) == 0
8544 && (unsigned HOST_WIDE_INT) XINT (x, 2) < 0x1000)
8545 || (XINT (x, 3) == -1
8546 && XINT (x, 2) < 0
8547 && XINT (x, 2) >= -0x1000)))
8548 *total = 0;
8549 else
8550 *total = 8;
8551 return true;
8552
8553 case MEM:
8554 /* If outer-code was a sign or zero extension, a cost
8555 of COSTS_N_INSNS (1) was already added in. This is
8556 why we are subtracting it back out. */
8557 if (outer_code == ZERO_EXTEND)
8558 {
8559 *total = sparc_costs->int_zload - COSTS_N_INSNS (1);
8560 }
8561 else if (outer_code == SIGN_EXTEND)
8562 {
8563 *total = sparc_costs->int_sload - COSTS_N_INSNS (1);
8564 }
8565 else if (float_mode_p)
8566 {
8567 *total = sparc_costs->float_load;
8568 }
8569 else
8570 {
8571 *total = sparc_costs->int_load;
8572 }
8573
8574 return true;
8575
8576 case PLUS:
8577 case MINUS:
8578 if (float_mode_p)
8579 *total = sparc_costs->float_plusminus;
8580 else
8581 *total = COSTS_N_INSNS (1);
8582 return false;
8583
8584 case MULT:
8585 if (float_mode_p)
8586 *total = sparc_costs->float_mul;
8587 else if (! TARGET_HARD_MUL)
8588 *total = COSTS_N_INSNS (25);
8589 else
8590 {
8591 int bit_cost;
8592
8593 bit_cost = 0;
8594 if (sparc_costs->int_mul_bit_factor)
8595 {
8596 int nbits;
8597
8598 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8599 {
8600 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
8601 for (nbits = 0; value != 0; value &= value - 1)
8602 nbits++;
8603 }
8604 else if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
8605 && GET_MODE (XEXP (x, 1)) == DImode)
8606 {
8607 rtx x1 = XEXP (x, 1);
8608 unsigned HOST_WIDE_INT value1 = XINT (x1, 2);
8609 unsigned HOST_WIDE_INT value2 = XINT (x1, 3);
8610
8611 for (nbits = 0; value1 != 0; value1 &= value1 - 1)
8612 nbits++;
8613 for (; value2 != 0; value2 &= value2 - 1)
8614 nbits++;
8615 }
8616 else
8617 nbits = 7;
8618
8619 if (nbits < 3)
8620 nbits = 3;
8621 bit_cost = (nbits - 3) / sparc_costs->int_mul_bit_factor;
8622 bit_cost = COSTS_N_INSNS (bit_cost);
8623 }
8624
8625 if (mode == DImode)
8626 *total = sparc_costs->int_mulX + bit_cost;
8627 else
8628 *total = sparc_costs->int_mul + bit_cost;
8629 }
8630 return false;
8631
8632 case ASHIFT:
8633 case ASHIFTRT:
8634 case LSHIFTRT:
8635 *total = COSTS_N_INSNS (1) + sparc_costs->shift_penalty;
8636 return false;
8637
8638 case DIV:
8639 case UDIV:
8640 case MOD:
8641 case UMOD:
8642 if (float_mode_p)
8643 {
8644 if (mode == DFmode)
8645 *total = sparc_costs->float_div_df;
8646 else
8647 *total = sparc_costs->float_div_sf;
8648 }
8649 else
8650 {
8651 if (mode == DImode)
8652 *total = sparc_costs->int_divX;
8653 else
8654 *total = sparc_costs->int_div;
8655 }
8656 return false;
8657
8658 case NEG:
8659 if (! float_mode_p)
8660 {
8661 *total = COSTS_N_INSNS (1);
8662 return false;
8663 }
8664 /* FALLTHRU */
8665
8666 case ABS:
8667 case FLOAT:
8668 case UNSIGNED_FLOAT:
8669 case FIX:
8670 case UNSIGNED_FIX:
8671 case FLOAT_EXTEND:
8672 case FLOAT_TRUNCATE:
8673 *total = sparc_costs->float_move;
8674 return false;
8675
8676 case SQRT:
8677 if (mode == DFmode)
8678 *total = sparc_costs->float_sqrt_df;
8679 else
8680 *total = sparc_costs->float_sqrt_sf;
8681 return false;
8682
8683 case COMPARE:
8684 if (float_mode_p)
8685 *total = sparc_costs->float_cmp;
8686 else
8687 *total = COSTS_N_INSNS (1);
8688 return false;
8689
8690 case IF_THEN_ELSE:
8691 if (float_mode_p)
8692 *total = sparc_costs->float_cmove;
8693 else
8694 *total = sparc_costs->int_cmove;
8695 return false;
8696
8697 case IOR:
8698 /* Handle the NAND vector patterns. */
8699 if (sparc_vector_mode_supported_p (GET_MODE (x))
8700 && GET_CODE (XEXP (x, 0)) == NOT
8701 && GET_CODE (XEXP (x, 1)) == NOT)
8702 {
8703 *total = COSTS_N_INSNS (1);
8704 return true;
8705 }
8706 else
8707 return false;
8708
8709 default:
8710 return false;
8711 }
8712 }
8713
8714 /* Emit the sequence of insns SEQ while preserving the register REG. */
8715
8716 static void
8717 emit_and_preserve (rtx seq, rtx reg)
8718 {
8719 rtx slot = gen_rtx_MEM (word_mode,
8720 plus_constant (stack_pointer_rtx, SPARC_STACK_BIAS));
8721
8722 emit_stack_pointer_decrement (GEN_INT (STACK_BOUNDARY/BITS_PER_UNIT));
8723 emit_insn (gen_rtx_SET (VOIDmode, slot, reg));
8724 emit_insn (seq);
8725 emit_insn (gen_rtx_SET (VOIDmode, reg, slot));
8726 emit_stack_pointer_increment (GEN_INT (STACK_BOUNDARY/BITS_PER_UNIT));
8727 }
8728
8729 /* Output the assembler code for a thunk function. THUNK_DECL is the
8730 declaration for the thunk function itself, FUNCTION is the decl for
8731 the target function. DELTA is an immediate constant offset to be
8732 added to THIS. If VCALL_OFFSET is nonzero, the word at address
8733 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
8734
8735 static void
8736 sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
8737 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
8738 tree function)
8739 {
8740 rtx this, insn, funexp;
8741 unsigned int int_arg_first;
8742
8743 reload_completed = 1;
8744 epilogue_completed = 1;
8745 no_new_pseudos = 1;
8746 reset_block_changes ();
8747
8748 emit_note (NOTE_INSN_PROLOGUE_END);
8749
8750 if (flag_delayed_branch)
8751 {
8752 /* We will emit a regular sibcall below, so we need to instruct
8753 output_sibcall that we are in a leaf function. */
8754 sparc_leaf_function_p = current_function_uses_only_leaf_regs = 1;
8755
8756 /* This will cause final.c to invoke leaf_renumber_regs so we
8757 must behave as if we were in a not-yet-leafified function. */
8758 int_arg_first = SPARC_INCOMING_INT_ARG_FIRST;
8759 }
8760 else
8761 {
8762 /* We will emit the sibcall manually below, so we will need to
8763 manually spill non-leaf registers. */
8764 sparc_leaf_function_p = current_function_uses_only_leaf_regs = 0;
8765
8766 /* We really are in a leaf function. */
8767 int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST;
8768 }
8769
8770 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
8771 returns a structure, the structure return pointer is there instead. */
8772 if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8773 this = gen_rtx_REG (Pmode, int_arg_first + 1);
8774 else
8775 this = gen_rtx_REG (Pmode, int_arg_first);
8776
8777 /* Add DELTA. When possible use a plain add, otherwise load it into
8778 a register first. */
8779 if (delta)
8780 {
8781 rtx delta_rtx = GEN_INT (delta);
8782
8783 if (! SPARC_SIMM13_P (delta))
8784 {
8785 rtx scratch = gen_rtx_REG (Pmode, 1);
8786 emit_move_insn (scratch, delta_rtx);
8787 delta_rtx = scratch;
8788 }
8789
8790 /* THIS += DELTA. */
8791 emit_insn (gen_add2_insn (this, delta_rtx));
8792 }
8793
8794 /* Add the word at address (*THIS + VCALL_OFFSET). */
8795 if (vcall_offset)
8796 {
8797 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
8798 rtx scratch = gen_rtx_REG (Pmode, 1);
8799
8800 if (vcall_offset >= 0)
8801 abort ();
8802
8803 /* SCRATCH = *THIS. */
8804 emit_move_insn (scratch, gen_rtx_MEM (Pmode, this));
8805
8806 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
8807 may not have any available scratch register at this point. */
8808 if (SPARC_SIMM13_P (vcall_offset))
8809 ;
8810 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
8811 else if (! fixed_regs[5]
8812 /* The below sequence is made up of at least 2 insns,
8813 while the default method may need only one. */
8814 && vcall_offset < -8192)
8815 {
8816 rtx scratch2 = gen_rtx_REG (Pmode, 5);
8817 emit_move_insn (scratch2, vcall_offset_rtx);
8818 vcall_offset_rtx = scratch2;
8819 }
8820 else
8821 {
8822 rtx increment = GEN_INT (-4096);
8823
8824 /* VCALL_OFFSET is a negative number whose typical range can be
8825 estimated as -32768..0 in 32-bit mode. In almost all cases
8826 it is therefore cheaper to emit multiple add insns than
8827 spilling and loading the constant into a register (at least
8828 6 insns). */
8829 while (! SPARC_SIMM13_P (vcall_offset))
8830 {
8831 emit_insn (gen_add2_insn (scratch, increment));
8832 vcall_offset += 4096;
8833 }
8834 vcall_offset_rtx = GEN_INT (vcall_offset); /* cannot be 0 */
8835 }
8836
8837 /* SCRATCH = *(*THIS + VCALL_OFFSET). */
8838 emit_move_insn (scratch, gen_rtx_MEM (Pmode,
8839 gen_rtx_PLUS (Pmode,
8840 scratch,
8841 vcall_offset_rtx)));
8842
8843 /* THIS += *(*THIS + VCALL_OFFSET). */
8844 emit_insn (gen_add2_insn (this, scratch));
8845 }
8846
8847 /* Generate a tail call to the target function. */
8848 if (! TREE_USED (function))
8849 {
8850 assemble_external (function);
8851 TREE_USED (function) = 1;
8852 }
8853 funexp = XEXP (DECL_RTL (function), 0);
8854
8855 if (flag_delayed_branch)
8856 {
8857 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
8858 insn = emit_call_insn (gen_sibcall (funexp));
8859 SIBLING_CALL_P (insn) = 1;
8860 }
8861 else
8862 {
8863 /* The hoops we have to jump through in order to generate a sibcall
8864 without using delay slots... */
8865 rtx spill_reg, seq, scratch = gen_rtx_REG (Pmode, 1);
8866
8867 if (flag_pic)
8868 {
8869 spill_reg = gen_rtx_REG (word_mode, 15); /* %o7 */
8870 start_sequence ();
8871 load_pic_register (); /* clobbers %o7 */
8872 scratch = legitimize_pic_address (funexp, Pmode, scratch);
8873 seq = get_insns ();
8874 end_sequence ();
8875 emit_and_preserve (seq, spill_reg);
8876 }
8877 else if (TARGET_ARCH32)
8878 {
8879 emit_insn (gen_rtx_SET (VOIDmode,
8880 scratch,
8881 gen_rtx_HIGH (SImode, funexp)));
8882 emit_insn (gen_rtx_SET (VOIDmode,
8883 scratch,
8884 gen_rtx_LO_SUM (SImode, scratch, funexp)));
8885 }
8886 else /* TARGET_ARCH64 */
8887 {
8888 switch (sparc_cmodel)
8889 {
8890 case CM_MEDLOW:
8891 case CM_MEDMID:
8892 /* The destination can serve as a temporary. */
8893 sparc_emit_set_symbolic_const64 (scratch, funexp, scratch);
8894 break;
8895
8896 case CM_MEDANY:
8897 case CM_EMBMEDANY:
8898 /* The destination cannot serve as a temporary. */
8899 spill_reg = gen_rtx_REG (DImode, 15); /* %o7 */
8900 start_sequence ();
8901 sparc_emit_set_symbolic_const64 (scratch, funexp, spill_reg);
8902 seq = get_insns ();
8903 end_sequence ();
8904 emit_and_preserve (seq, spill_reg);
8905 break;
8906
8907 default:
8908 abort();
8909 }
8910 }
8911
8912 emit_jump_insn (gen_indirect_jump (scratch));
8913 }
8914
8915 emit_barrier ();
8916
8917 /* Run just enough of rest_of_compilation to get the insns emitted.
8918 There's not really enough bulk here to make other passes such as
8919 instruction scheduling worth while. Note that use_thunk calls
8920 assemble_start_function and assemble_end_function. */
8921 insn = get_insns ();
8922 insn_locators_initialize ();
8923 shorten_branches (insn);
8924 final_start_function (insn, file, 1);
8925 final (insn, file, 1, 0);
8926 final_end_function ();
8927
8928 reload_completed = 0;
8929 epilogue_completed = 0;
8930 no_new_pseudos = 0;
8931 }
8932
8933 /* Return true if sparc_output_mi_thunk would be able to output the
8934 assembler code for the thunk function specified by the arguments
8935 it is passed, and false otherwise. */
8936 static bool
8937 sparc_can_output_mi_thunk (tree thunk_fndecl ATTRIBUTE_UNUSED,
8938 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
8939 HOST_WIDE_INT vcall_offset,
8940 tree function ATTRIBUTE_UNUSED)
8941 {
8942 /* Bound the loop used in the default method above. */
8943 return (vcall_offset >= -32768 || ! fixed_regs[5]);
8944 }
8945
8946 /* How to allocate a 'struct machine_function'. */
8947
8948 static struct machine_function *
8949 sparc_init_machine_status (void)
8950 {
8951 return ggc_alloc_cleared (sizeof (struct machine_function));
8952 }
8953
8954 /* Locate some local-dynamic symbol still in use by this function
8955 so that we can print its name in local-dynamic base patterns. */
8956
8957 static const char *
8958 get_some_local_dynamic_name (void)
8959 {
8960 rtx insn;
8961
8962 if (cfun->machine->some_ld_name)
8963 return cfun->machine->some_ld_name;
8964
8965 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
8966 if (INSN_P (insn)
8967 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
8968 return cfun->machine->some_ld_name;
8969
8970 abort ();
8971 }
8972
8973 static int
8974 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
8975 {
8976 rtx x = *px;
8977
8978 if (x
8979 && GET_CODE (x) == SYMBOL_REF
8980 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
8981 {
8982 cfun->machine->some_ld_name = XSTR (x, 0);
8983 return 1;
8984 }
8985
8986 return 0;
8987 }
8988
8989 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
8990 We need to emit DTP-relative relocations. */
8991
8992 void
8993 sparc_output_dwarf_dtprel (FILE *file, int size, rtx x)
8994 {
8995 switch (size)
8996 {
8997 case 4:
8998 fputs ("\t.word\t%r_tls_dtpoff32(", file);
8999 break;
9000 case 8:
9001 fputs ("\t.xword\t%r_tls_dtpoff64(", file);
9002 break;
9003 default:
9004 abort ();
9005 }
9006 output_addr_const (file, x);
9007 fputs (")", file);
9008 }
9009
9010 #include "gt-sparc.h"
Mirror of https://gcc.gnu.org/git/gcc.git