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rtl.h (MEM_READONLY_P): Replace RTX_UNCHANGING_P.
[thirdparty/gcc.git] / gcc / config / sparc / sparc.c
1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
6 at Cygnus Support.
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
24
25 #include "config.h"
26 #include "system.h"
27 #include "coretypes.h"
28 #include "tm.h"
29 #include "tree.h"
30 #include "rtl.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "real.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "output.h"
37 #include "insn-attr.h"
38 #include "flags.h"
39 #include "function.h"
40 #include "expr.h"
41 #include "optabs.h"
42 #include "recog.h"
43 #include "toplev.h"
44 #include "ggc.h"
45 #include "tm_p.h"
46 #include "debug.h"
47 #include "target.h"
48 #include "target-def.h"
49 #include "cfglayout.h"
50 #include "tree-gimple.h"
51
52 /* Processor costs */
53 static const
54 struct processor_costs cypress_costs = {
55 COSTS_N_INSNS (2), /* int load */
56 COSTS_N_INSNS (2), /* int signed load */
57 COSTS_N_INSNS (2), /* int zeroed load */
58 COSTS_N_INSNS (2), /* float load */
59 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
60 COSTS_N_INSNS (5), /* fadd, fsub */
61 COSTS_N_INSNS (1), /* fcmp */
62 COSTS_N_INSNS (1), /* fmov, fmovr */
63 COSTS_N_INSNS (7), /* fmul */
64 COSTS_N_INSNS (37), /* fdivs */
65 COSTS_N_INSNS (37), /* fdivd */
66 COSTS_N_INSNS (63), /* fsqrts */
67 COSTS_N_INSNS (63), /* fsqrtd */
68 COSTS_N_INSNS (1), /* imul */
69 COSTS_N_INSNS (1), /* imulX */
70 0, /* imul bit factor */
71 COSTS_N_INSNS (1), /* idiv */
72 COSTS_N_INSNS (1), /* idivX */
73 COSTS_N_INSNS (1), /* movcc/movr */
74 0, /* shift penalty */
75 };
76
77 static const
78 struct processor_costs supersparc_costs = {
79 COSTS_N_INSNS (1), /* int load */
80 COSTS_N_INSNS (1), /* int signed load */
81 COSTS_N_INSNS (1), /* int zeroed load */
82 COSTS_N_INSNS (0), /* float load */
83 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
84 COSTS_N_INSNS (3), /* fadd, fsub */
85 COSTS_N_INSNS (3), /* fcmp */
86 COSTS_N_INSNS (1), /* fmov, fmovr */
87 COSTS_N_INSNS (3), /* fmul */
88 COSTS_N_INSNS (6), /* fdivs */
89 COSTS_N_INSNS (9), /* fdivd */
90 COSTS_N_INSNS (12), /* fsqrts */
91 COSTS_N_INSNS (12), /* fsqrtd */
92 COSTS_N_INSNS (4), /* imul */
93 COSTS_N_INSNS (4), /* imulX */
94 0, /* imul bit factor */
95 COSTS_N_INSNS (4), /* idiv */
96 COSTS_N_INSNS (4), /* idivX */
97 COSTS_N_INSNS (1), /* movcc/movr */
98 1, /* shift penalty */
99 };
100
101 static const
102 struct processor_costs hypersparc_costs = {
103 COSTS_N_INSNS (1), /* int load */
104 COSTS_N_INSNS (1), /* int signed load */
105 COSTS_N_INSNS (1), /* int zeroed load */
106 COSTS_N_INSNS (1), /* float load */
107 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
108 COSTS_N_INSNS (1), /* fadd, fsub */
109 COSTS_N_INSNS (1), /* fcmp */
110 COSTS_N_INSNS (1), /* fmov, fmovr */
111 COSTS_N_INSNS (1), /* fmul */
112 COSTS_N_INSNS (8), /* fdivs */
113 COSTS_N_INSNS (12), /* fdivd */
114 COSTS_N_INSNS (17), /* fsqrts */
115 COSTS_N_INSNS (17), /* fsqrtd */
116 COSTS_N_INSNS (17), /* imul */
117 COSTS_N_INSNS (17), /* imulX */
118 0, /* imul bit factor */
119 COSTS_N_INSNS (17), /* idiv */
120 COSTS_N_INSNS (17), /* idivX */
121 COSTS_N_INSNS (1), /* movcc/movr */
122 0, /* shift penalty */
123 };
124
125 static const
126 struct processor_costs sparclet_costs = {
127 COSTS_N_INSNS (3), /* int load */
128 COSTS_N_INSNS (3), /* int signed load */
129 COSTS_N_INSNS (1), /* int zeroed load */
130 COSTS_N_INSNS (1), /* float load */
131 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
132 COSTS_N_INSNS (1), /* fadd, fsub */
133 COSTS_N_INSNS (1), /* fcmp */
134 COSTS_N_INSNS (1), /* fmov, fmovr */
135 COSTS_N_INSNS (1), /* fmul */
136 COSTS_N_INSNS (1), /* fdivs */
137 COSTS_N_INSNS (1), /* fdivd */
138 COSTS_N_INSNS (1), /* fsqrts */
139 COSTS_N_INSNS (1), /* fsqrtd */
140 COSTS_N_INSNS (5), /* imul */
141 COSTS_N_INSNS (5), /* imulX */
142 0, /* imul bit factor */
143 COSTS_N_INSNS (5), /* idiv */
144 COSTS_N_INSNS (5), /* idivX */
145 COSTS_N_INSNS (1), /* movcc/movr */
146 0, /* shift penalty */
147 };
148
149 static const
150 struct processor_costs ultrasparc_costs = {
151 COSTS_N_INSNS (2), /* int load */
152 COSTS_N_INSNS (3), /* int signed load */
153 COSTS_N_INSNS (2), /* int zeroed load */
154 COSTS_N_INSNS (2), /* float load */
155 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
156 COSTS_N_INSNS (4), /* fadd, fsub */
157 COSTS_N_INSNS (1), /* fcmp */
158 COSTS_N_INSNS (2), /* fmov, fmovr */
159 COSTS_N_INSNS (4), /* fmul */
160 COSTS_N_INSNS (13), /* fdivs */
161 COSTS_N_INSNS (23), /* fdivd */
162 COSTS_N_INSNS (13), /* fsqrts */
163 COSTS_N_INSNS (23), /* fsqrtd */
164 COSTS_N_INSNS (4), /* imul */
165 COSTS_N_INSNS (4), /* imulX */
166 2, /* imul bit factor */
167 COSTS_N_INSNS (37), /* idiv */
168 COSTS_N_INSNS (68), /* idivX */
169 COSTS_N_INSNS (2), /* movcc/movr */
170 2, /* shift penalty */
171 };
172
173 static const
174 struct processor_costs ultrasparc3_costs = {
175 COSTS_N_INSNS (2), /* int load */
176 COSTS_N_INSNS (3), /* int signed load */
177 COSTS_N_INSNS (3), /* int zeroed load */
178 COSTS_N_INSNS (2), /* float load */
179 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
180 COSTS_N_INSNS (4), /* fadd, fsub */
181 COSTS_N_INSNS (5), /* fcmp */
182 COSTS_N_INSNS (3), /* fmov, fmovr */
183 COSTS_N_INSNS (4), /* fmul */
184 COSTS_N_INSNS (17), /* fdivs */
185 COSTS_N_INSNS (20), /* fdivd */
186 COSTS_N_INSNS (20), /* fsqrts */
187 COSTS_N_INSNS (29), /* fsqrtd */
188 COSTS_N_INSNS (6), /* imul */
189 COSTS_N_INSNS (6), /* imulX */
190 0, /* imul bit factor */
191 COSTS_N_INSNS (40), /* idiv */
192 COSTS_N_INSNS (71), /* idivX */
193 COSTS_N_INSNS (2), /* movcc/movr */
194 0, /* shift penalty */
195 };
196
197 const struct processor_costs *sparc_costs = &cypress_costs;
198
199 #ifdef HAVE_AS_RELAX_OPTION
200 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
201 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
202 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
203 somebody does not branch between the sethi and jmp. */
204 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
205 #else
206 #define LEAF_SIBCALL_SLOT_RESERVED_P \
207 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
208 #endif
209
210 /* Global variables for machine-dependent things. */
211
212 /* Size of frame. Need to know this to emit return insns from leaf procedures.
213 ACTUAL_FSIZE is set by sparc_compute_frame_size() which is called during the
214 reload pass. This is important as the value is later used for scheduling
215 (to see what can go in a delay slot).
216 APPARENT_FSIZE is the size of the stack less the register save area and less
217 the outgoing argument area. It is used when saving call preserved regs. */
218 static HOST_WIDE_INT apparent_fsize;
219 static HOST_WIDE_INT actual_fsize;
220
221 /* Number of live general or floating point registers needed to be
222 saved (as 4-byte quantities). */
223 static int num_gfregs;
224
225 /* The alias set for prologue/epilogue register save/restore. */
226 static GTY(()) int sparc_sr_alias_set;
227
228 /* Save the operands last given to a compare for use when we
229 generate a scc or bcc insn. */
230 rtx sparc_compare_op0, sparc_compare_op1;
231
232 /* Vector to say how input registers are mapped to output registers.
233 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
234 eliminate it. You must use -fomit-frame-pointer to get that. */
235 char leaf_reg_remap[] =
236 { 0, 1, 2, 3, 4, 5, 6, 7,
237 -1, -1, -1, -1, -1, -1, 14, -1,
238 -1, -1, -1, -1, -1, -1, -1, -1,
239 8, 9, 10, 11, 12, 13, -1, 15,
240
241 32, 33, 34, 35, 36, 37, 38, 39,
242 40, 41, 42, 43, 44, 45, 46, 47,
243 48, 49, 50, 51, 52, 53, 54, 55,
244 56, 57, 58, 59, 60, 61, 62, 63,
245 64, 65, 66, 67, 68, 69, 70, 71,
246 72, 73, 74, 75, 76, 77, 78, 79,
247 80, 81, 82, 83, 84, 85, 86, 87,
248 88, 89, 90, 91, 92, 93, 94, 95,
249 96, 97, 98, 99, 100};
250
251 /* Vector, indexed by hard register number, which contains 1
252 for a register that is allowable in a candidate for leaf
253 function treatment. */
254 char sparc_leaf_regs[] =
255 { 1, 1, 1, 1, 1, 1, 1, 1,
256 0, 0, 0, 0, 0, 0, 1, 0,
257 0, 0, 0, 0, 0, 0, 0, 0,
258 1, 1, 1, 1, 1, 1, 0, 1,
259 1, 1, 1, 1, 1, 1, 1, 1,
260 1, 1, 1, 1, 1, 1, 1, 1,
261 1, 1, 1, 1, 1, 1, 1, 1,
262 1, 1, 1, 1, 1, 1, 1, 1,
263 1, 1, 1, 1, 1, 1, 1, 1,
264 1, 1, 1, 1, 1, 1, 1, 1,
265 1, 1, 1, 1, 1, 1, 1, 1,
266 1, 1, 1, 1, 1, 1, 1, 1,
267 1, 1, 1, 1, 1};
268
269 struct machine_function GTY(())
270 {
271 /* Some local-dynamic TLS symbol name. */
272 const char *some_ld_name;
273 };
274
275 /* Register we pretend to think the frame pointer is allocated to.
276 Normally, this is %fp, but if we are in a leaf procedure, this
277 is %sp+"something". We record "something" separately as it may
278 be too big for reg+constant addressing. */
279
280 static rtx frame_base_reg;
281 static HOST_WIDE_INT frame_base_offset;
282
283 static void sparc_init_modes (void);
284 static void scan_record_type (tree, int *, int *, int *);
285 static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
286 tree, int, int, int *, int *);
287
288 static int supersparc_adjust_cost (rtx, rtx, rtx, int);
289 static int hypersparc_adjust_cost (rtx, rtx, rtx, int);
290
291 static void sparc_output_addr_vec (rtx);
292 static void sparc_output_addr_diff_vec (rtx);
293 static void sparc_output_deferred_case_vectors (void);
294 static rtx sparc_builtin_saveregs (void);
295 static int epilogue_renumber (rtx *, int);
296 static bool sparc_assemble_integer (rtx, unsigned int, int);
297 static int set_extends (rtx);
298 static void load_pic_register (void);
299 static int save_or_restore_regs (int, int, rtx, int, int);
300 static void emit_save_regs (void);
301 static void emit_restore_regs (void);
302 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT);
303 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT);
304 #ifdef OBJECT_FORMAT_ELF
305 static void sparc_elf_asm_named_section (const char *, unsigned int);
306 #endif
307
308 static int sparc_adjust_cost (rtx, rtx, rtx, int);
309 static int sparc_issue_rate (void);
310 static void sparc_sched_init (FILE *, int, int);
311 static int sparc_use_sched_lookahead (void);
312
313 static void emit_soft_tfmode_libcall (const char *, int, rtx *);
314 static void emit_soft_tfmode_binop (enum rtx_code, rtx *);
315 static void emit_soft_tfmode_unop (enum rtx_code, rtx *);
316 static void emit_soft_tfmode_cvt (enum rtx_code, rtx *);
317 static void emit_hard_tfmode_operation (enum rtx_code, rtx *);
318
319 static bool sparc_function_ok_for_sibcall (tree, tree);
320 static void sparc_init_libfuncs (void);
321 static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
322 HOST_WIDE_INT, tree);
323 static struct machine_function * sparc_init_machine_status (void);
324 static bool sparc_cannot_force_const_mem (rtx);
325 static rtx sparc_tls_get_addr (void);
326 static rtx sparc_tls_got (void);
327 static const char *get_some_local_dynamic_name (void);
328 static int get_some_local_dynamic_name_1 (rtx *, void *);
329 static bool sparc_rtx_costs (rtx, int, int, int *);
330 static bool sparc_promote_prototypes (tree);
331 static rtx sparc_struct_value_rtx (tree, int);
332 static bool sparc_return_in_memory (tree, tree);
333 static bool sparc_strict_argument_naming (CUMULATIVE_ARGS *);
334 static tree sparc_gimplify_va_arg (tree, tree, tree *, tree *);
335 static bool sparc_pass_by_reference (CUMULATIVE_ARGS *,
336 enum machine_mode, tree, bool);
337 #ifdef SUBTARGET_ATTRIBUTE_TABLE
338 const struct attribute_spec sparc_attribute_table[];
339 #endif
340 \f
341 /* Option handling. */
342
343 /* Code model option as passed by user. */
344 const char *sparc_cmodel_string;
345 /* Parsed value. */
346 enum cmodel sparc_cmodel;
347
348 char sparc_hard_reg_printed[8];
349
350 struct sparc_cpu_select sparc_select[] =
351 {
352 /* switch name, tune arch */
353 { (char *)0, "default", 1, 1 },
354 { (char *)0, "-mcpu=", 1, 1 },
355 { (char *)0, "-mtune=", 1, 0 },
356 { 0, 0, 0, 0 }
357 };
358
359 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
360 enum processor_type sparc_cpu;
361 \f
362 /* Initialize the GCC target structure. */
363
364 /* The sparc default is to use .half rather than .short for aligned
365 HI objects. Use .word instead of .long on non-ELF systems. */
366 #undef TARGET_ASM_ALIGNED_HI_OP
367 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
368 #ifndef OBJECT_FORMAT_ELF
369 #undef TARGET_ASM_ALIGNED_SI_OP
370 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
371 #endif
372
373 #undef TARGET_ASM_UNALIGNED_HI_OP
374 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
375 #undef TARGET_ASM_UNALIGNED_SI_OP
376 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
377 #undef TARGET_ASM_UNALIGNED_DI_OP
378 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
379
380 /* The target hook has to handle DI-mode values. */
381 #undef TARGET_ASM_INTEGER
382 #define TARGET_ASM_INTEGER sparc_assemble_integer
383
384 #undef TARGET_ASM_FUNCTION_PROLOGUE
385 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
386 #undef TARGET_ASM_FUNCTION_EPILOGUE
387 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
388
389 #undef TARGET_SCHED_ADJUST_COST
390 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
391 #undef TARGET_SCHED_ISSUE_RATE
392 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
393 #undef TARGET_SCHED_INIT
394 #define TARGET_SCHED_INIT sparc_sched_init
395 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
396 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
397
398 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
399 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
400
401 #undef TARGET_INIT_LIBFUNCS
402 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
403
404 #ifdef HAVE_AS_TLS
405 #undef TARGET_HAVE_TLS
406 #define TARGET_HAVE_TLS true
407 #endif
408 #undef TARGET_CANNOT_FORCE_CONST_MEM
409 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
410
411 #undef TARGET_ASM_OUTPUT_MI_THUNK
412 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
413 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
414 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
415
416 #undef TARGET_RTX_COSTS
417 #define TARGET_RTX_COSTS sparc_rtx_costs
418 #undef TARGET_ADDRESS_COST
419 #define TARGET_ADDRESS_COST hook_int_rtx_0
420
421 /* This is only needed for TARGET_ARCH64, but since PROMOTE_FUNCTION_MODE is a
422 no-op for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime
423 test for this value. */
424 #undef TARGET_PROMOTE_FUNCTION_ARGS
425 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
426
427 /* This is only needed for TARGET_ARCH64, but since PROMOTE_FUNCTION_MODE is a
428 no-op for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime
429 test for this value. */
430 #undef TARGET_PROMOTE_FUNCTION_RETURN
431 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
432
433 #undef TARGET_PROMOTE_PROTOTYPES
434 #define TARGET_PROMOTE_PROTOTYPES sparc_promote_prototypes
435
436 #undef TARGET_STRUCT_VALUE_RTX
437 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
438 #undef TARGET_RETURN_IN_MEMORY
439 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
440 #undef TARGET_MUST_PASS_IN_STACK
441 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
442 #undef TARGET_PASS_BY_REFERENCE
443 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
444
445 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
446 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
447 #undef TARGET_STRICT_ARGUMENT_NAMING
448 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
449
450 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
451 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
452
453 #undef TARGET_LATE_RTL_PROLOGUE_EPILOGUE
454 #define TARGET_LATE_RTL_PROLOGUE_EPILOGUE true
455
456 #ifdef SUBTARGET_INSERT_ATTRIBUTES
457 #undef TARGET_INSERT_ATTRIBUTES
458 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
459 #endif
460
461 #ifdef SUBTARGET_ATTRIBUTE_TABLE
462 #undef TARGET_ATTRIBUTE_TABLE
463 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
464 #endif
465
466 struct gcc_target targetm = TARGET_INITIALIZER;
467 \f
468 /* Validate and override various options, and do some machine dependent
469 initialization. */
470
471 void
472 sparc_override_options (void)
473 {
474 static struct code_model {
475 const char *const name;
476 const int value;
477 } const cmodels[] = {
478 { "32", CM_32 },
479 { "medlow", CM_MEDLOW },
480 { "medmid", CM_MEDMID },
481 { "medany", CM_MEDANY },
482 { "embmedany", CM_EMBMEDANY },
483 { 0, 0 }
484 };
485 const struct code_model *cmodel;
486 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
487 static struct cpu_default {
488 const int cpu;
489 const char *const name;
490 } const cpu_default[] = {
491 /* There must be one entry here for each TARGET_CPU value. */
492 { TARGET_CPU_sparc, "cypress" },
493 { TARGET_CPU_sparclet, "tsc701" },
494 { TARGET_CPU_sparclite, "f930" },
495 { TARGET_CPU_v8, "v8" },
496 { TARGET_CPU_hypersparc, "hypersparc" },
497 { TARGET_CPU_sparclite86x, "sparclite86x" },
498 { TARGET_CPU_supersparc, "supersparc" },
499 { TARGET_CPU_v9, "v9" },
500 { TARGET_CPU_ultrasparc, "ultrasparc" },
501 { TARGET_CPU_ultrasparc3, "ultrasparc3" },
502 { 0, 0 }
503 };
504 const struct cpu_default *def;
505 /* Table of values for -m{cpu,tune}=. */
506 static struct cpu_table {
507 const char *const name;
508 const enum processor_type processor;
509 const int disable;
510 const int enable;
511 } const cpu_table[] = {
512 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
513 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
514 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
515 /* TI TMS390Z55 supersparc */
516 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
517 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
518 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
519 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
520 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
521 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
522 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
523 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
524 MASK_SPARCLITE },
525 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
526 /* TEMIC sparclet */
527 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
528 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
529 /* TI ultrasparc I, II, IIi */
530 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
531 /* Although insns using %y are deprecated, it is a clear win on current
532 ultrasparcs. */
533 |MASK_DEPRECATED_V8_INSNS},
534 /* TI ultrasparc III */
535 /* ??? Check if %y issue still holds true in ultra3. */
536 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
537 { 0, 0, 0, 0 }
538 };
539 const struct cpu_table *cpu;
540 const struct sparc_cpu_select *sel;
541 int fpu;
542
543 #ifndef SPARC_BI_ARCH
544 /* Check for unsupported architecture size. */
545 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
546 error ("%s is not supported by this configuration",
547 DEFAULT_ARCH32_P ? "-m64" : "-m32");
548 #endif
549
550 /* We force all 64bit archs to use 128 bit long double */
551 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
552 {
553 error ("-mlong-double-64 not allowed with -m64");
554 target_flags |= MASK_LONG_DOUBLE_128;
555 }
556
557 /* Code model selection. */
558 sparc_cmodel = SPARC_DEFAULT_CMODEL;
559
560 #ifdef SPARC_BI_ARCH
561 if (TARGET_ARCH32)
562 sparc_cmodel = CM_32;
563 #endif
564
565 if (sparc_cmodel_string != NULL)
566 {
567 if (TARGET_ARCH64)
568 {
569 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
570 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
571 break;
572 if (cmodel->name == NULL)
573 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
574 else
575 sparc_cmodel = cmodel->value;
576 }
577 else
578 error ("-mcmodel= is not supported on 32 bit systems");
579 }
580
581 fpu = TARGET_FPU; /* save current -mfpu status */
582
583 /* Set the default CPU. */
584 for (def = &cpu_default[0]; def->name; ++def)
585 if (def->cpu == TARGET_CPU_DEFAULT)
586 break;
587 if (! def->name)
588 abort ();
589 sparc_select[0].string = def->name;
590
591 for (sel = &sparc_select[0]; sel->name; ++sel)
592 {
593 if (sel->string)
594 {
595 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
596 if (! strcmp (sel->string, cpu->name))
597 {
598 if (sel->set_tune_p)
599 sparc_cpu = cpu->processor;
600
601 if (sel->set_arch_p)
602 {
603 target_flags &= ~cpu->disable;
604 target_flags |= cpu->enable;
605 }
606 break;
607 }
608
609 if (! cpu->name)
610 error ("bad value (%s) for %s switch", sel->string, sel->name);
611 }
612 }
613
614 /* If -mfpu or -mno-fpu was explicitly used, don't override with
615 the processor default. Clear MASK_FPU_SET to avoid confusing
616 the reverse mapping from switch values to names. */
617 if (TARGET_FPU_SET)
618 {
619 target_flags = (target_flags & ~MASK_FPU) | fpu;
620 target_flags &= ~MASK_FPU_SET;
621 }
622
623 /* Don't allow -mvis if FPU is disabled. */
624 if (! TARGET_FPU)
625 target_flags &= ~MASK_VIS;
626
627 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
628 are available.
629 -m64 also implies v9. */
630 if (TARGET_VIS || TARGET_ARCH64)
631 {
632 target_flags |= MASK_V9;
633 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
634 }
635
636 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
637 if (TARGET_V9 && TARGET_ARCH32)
638 target_flags |= MASK_DEPRECATED_V8_INSNS;
639
640 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
641 if (! TARGET_V9 || TARGET_ARCH64)
642 target_flags &= ~MASK_V8PLUS;
643
644 /* Don't use stack biasing in 32 bit mode. */
645 if (TARGET_ARCH32)
646 target_flags &= ~MASK_STACK_BIAS;
647
648 /* Supply a default value for align_functions. */
649 if (align_functions == 0
650 && (sparc_cpu == PROCESSOR_ULTRASPARC
651 || sparc_cpu == PROCESSOR_ULTRASPARC3))
652 align_functions = 32;
653
654 /* Validate PCC_STRUCT_RETURN. */
655 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
656 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
657
658 /* Only use .uaxword when compiling for a 64-bit target. */
659 if (!TARGET_ARCH64)
660 targetm.asm_out.unaligned_op.di = NULL;
661
662 /* Do various machine dependent initializations. */
663 sparc_init_modes ();
664
665 /* Acquire a unique set number for our register saves and restores. */
666 sparc_sr_alias_set = new_alias_set ();
667
668 /* Set up function hooks. */
669 init_machine_status = sparc_init_machine_status;
670
671 switch (sparc_cpu)
672 {
673 case PROCESSOR_V7:
674 case PROCESSOR_CYPRESS:
675 sparc_costs = &cypress_costs;
676 break;
677 case PROCESSOR_V8:
678 case PROCESSOR_SPARCLITE:
679 case PROCESSOR_SUPERSPARC:
680 sparc_costs = &supersparc_costs;
681 break;
682 case PROCESSOR_F930:
683 case PROCESSOR_F934:
684 case PROCESSOR_HYPERSPARC:
685 case PROCESSOR_SPARCLITE86X:
686 sparc_costs = &hypersparc_costs;
687 break;
688 case PROCESSOR_SPARCLET:
689 case PROCESSOR_TSC701:
690 sparc_costs = &sparclet_costs;
691 break;
692 case PROCESSOR_V9:
693 case PROCESSOR_ULTRASPARC:
694 sparc_costs = &ultrasparc_costs;
695 break;
696 case PROCESSOR_ULTRASPARC3:
697 sparc_costs = &ultrasparc3_costs;
698 break;
699 };
700 }
701 \f
702 #ifdef SUBTARGET_ATTRIBUTE_TABLE
703 /* Table of valid machine attributes. */
704 const struct attribute_spec sparc_attribute_table[] =
705 {
706 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
707 SUBTARGET_ATTRIBUTE_TABLE,
708 { NULL, 0, 0, false, false, false, NULL }
709 };
710 #endif
711 \f
712 /* Miscellaneous utilities. */
713
714 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
715 or branch on register contents instructions. */
716
717 int
718 v9_regcmp_p (enum rtx_code code)
719 {
720 return (code == EQ || code == NE || code == GE || code == LT
721 || code == LE || code == GT);
722 }
723
724 \f
725 /* Operand constraints. */
726
727 /* Return nonzero only if OP is a register of mode MODE,
728 or const0_rtx. */
729
730 int
731 reg_or_0_operand (rtx op, enum machine_mode mode)
732 {
733 if (register_operand (op, mode))
734 return 1;
735 if (op == const0_rtx)
736 return 1;
737 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
738 && CONST_DOUBLE_HIGH (op) == 0
739 && CONST_DOUBLE_LOW (op) == 0)
740 return 1;
741 if (fp_zero_operand (op, mode))
742 return 1;
743 return 0;
744 }
745
746 /* Return nonzero only if OP is const1_rtx. */
747
748 int
749 const1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
750 {
751 return op == const1_rtx;
752 }
753
754 /* Nonzero if OP is a floating point value with value 0.0. */
755
756 int
757 fp_zero_operand (rtx op, enum machine_mode mode)
758 {
759 if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT)
760 return 0;
761 return op == CONST0_RTX (mode);
762 }
763
764 /* Nonzero if OP is a register operand in floating point register. */
765
766 int
767 fp_register_operand (rtx op, enum machine_mode mode)
768 {
769 if (! register_operand (op, mode))
770 return 0;
771 if (GET_CODE (op) == SUBREG)
772 op = SUBREG_REG (op);
773 return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op));
774 }
775
776 /* Nonzero if OP is a floating point constant which can
777 be loaded into an integer register using a single
778 sethi instruction. */
779
780 int
781 fp_sethi_p (rtx op)
782 {
783 if (GET_CODE (op) == CONST_DOUBLE)
784 {
785 REAL_VALUE_TYPE r;
786 long i;
787
788 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
789 if (REAL_VALUES_EQUAL (r, dconst0) &&
790 ! REAL_VALUE_MINUS_ZERO (r))
791 return 0;
792 REAL_VALUE_TO_TARGET_SINGLE (r, i);
793 if (SPARC_SETHI_P (i))
794 return 1;
795 }
796
797 return 0;
798 }
799
800 /* Nonzero if OP is a floating point constant which can
801 be loaded into an integer register using a single
802 mov instruction. */
803
804 int
805 fp_mov_p (rtx op)
806 {
807 if (GET_CODE (op) == CONST_DOUBLE)
808 {
809 REAL_VALUE_TYPE r;
810 long i;
811
812 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
813 if (REAL_VALUES_EQUAL (r, dconst0) &&
814 ! REAL_VALUE_MINUS_ZERO (r))
815 return 0;
816 REAL_VALUE_TO_TARGET_SINGLE (r, i);
817 if (SPARC_SIMM13_P (i))
818 return 1;
819 }
820
821 return 0;
822 }
823
824 /* Nonzero if OP is a floating point constant which can
825 be loaded into an integer register using a high/losum
826 instruction sequence. */
827
828 int
829 fp_high_losum_p (rtx op)
830 {
831 /* The constraints calling this should only be in
832 SFmode move insns, so any constant which cannot
833 be moved using a single insn will do. */
834 if (GET_CODE (op) == CONST_DOUBLE)
835 {
836 REAL_VALUE_TYPE r;
837 long i;
838
839 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
840 if (REAL_VALUES_EQUAL (r, dconst0) &&
841 ! REAL_VALUE_MINUS_ZERO (r))
842 return 0;
843 REAL_VALUE_TO_TARGET_SINGLE (r, i);
844 if (! SPARC_SETHI_P (i)
845 && ! SPARC_SIMM13_P (i))
846 return 1;
847 }
848
849 return 0;
850 }
851
852 /* Nonzero if OP is an integer register. */
853
854 int
855 intreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
856 {
857 return (register_operand (op, SImode)
858 || (TARGET_ARCH64 && register_operand (op, DImode)));
859 }
860
861 /* Nonzero if OP is a floating point condition code register. */
862
863 int
864 fcc_reg_operand (rtx op, enum machine_mode mode)
865 {
866 /* This can happen when recog is called from combine. Op may be a MEM.
867 Fail instead of calling abort in this case. */
868 if (GET_CODE (op) != REG)
869 return 0;
870
871 if (mode != VOIDmode && mode != GET_MODE (op))
872 return 0;
873 if (mode == VOIDmode
874 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
875 return 0;
876
877 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
878 if (reg_renumber == 0)
879 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
880 return REGNO_OK_FOR_CCFP_P (REGNO (op));
881 #else
882 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
883 #endif
884 }
885
886 /* Nonzero if OP is a floating point condition code fcc0 register. */
887
888 int
889 fcc0_reg_operand (rtx op, enum machine_mode mode)
890 {
891 /* This can happen when recog is called from combine. Op may be a MEM.
892 Fail instead of calling abort in this case. */
893 if (GET_CODE (op) != REG)
894 return 0;
895
896 if (mode != VOIDmode && mode != GET_MODE (op))
897 return 0;
898 if (mode == VOIDmode
899 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
900 return 0;
901
902 return REGNO (op) == SPARC_FCC_REG;
903 }
904
905 /* Nonzero if OP is an integer or floating point condition code register. */
906
907 int
908 icc_or_fcc_reg_operand (rtx op, enum machine_mode mode)
909 {
910 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
911 {
912 if (mode != VOIDmode && mode != GET_MODE (op))
913 return 0;
914 if (mode == VOIDmode
915 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
916 return 0;
917 return 1;
918 }
919
920 return fcc_reg_operand (op, mode);
921 }
922
923 /* Call insn on SPARC can take a PC-relative constant address, or any regular
924 memory address. */
925
926 int
927 call_operand (rtx op, enum machine_mode mode)
928 {
929 if (GET_CODE (op) != MEM)
930 abort ();
931 op = XEXP (op, 0);
932 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
933 }
934
935 int
936 call_operand_address (rtx op, enum machine_mode mode)
937 {
938 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
939 }
940
941 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
942 otherwise return 0. */
943
944 int
945 tls_symbolic_operand (rtx op)
946 {
947 if (GET_CODE (op) != SYMBOL_REF)
948 return 0;
949 return SYMBOL_REF_TLS_MODEL (op);
950 }
951
952 int
953 tgd_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
954 {
955 return tls_symbolic_operand (op) == TLS_MODEL_GLOBAL_DYNAMIC;
956 }
957
958 int
959 tld_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
960 {
961 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_DYNAMIC;
962 }
963
964 int
965 tie_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
966 {
967 return tls_symbolic_operand (op) == TLS_MODEL_INITIAL_EXEC;
968 }
969
970 int
971 tle_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
972 {
973 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_EXEC;
974 }
975
976 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
977 reference and a constant. */
978
979 int
980 symbolic_operand (register rtx op, enum machine_mode mode)
981 {
982 enum machine_mode omode = GET_MODE (op);
983
984 if (omode != mode && omode != VOIDmode && mode != VOIDmode)
985 return 0;
986
987 switch (GET_CODE (op))
988 {
989 case SYMBOL_REF:
990 return !SYMBOL_REF_TLS_MODEL (op);
991
992 case LABEL_REF:
993 return 1;
994
995 case CONST:
996 op = XEXP (op, 0);
997 return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
998 && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
999 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1000 && GET_CODE (XEXP (op, 1)) == CONST_INT);
1001
1002 default:
1003 return 0;
1004 }
1005 }
1006
1007 /* Return truth value of statement that OP is a symbolic memory
1008 operand of mode MODE. */
1009
1010 int
1011 symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1012 {
1013 if (GET_CODE (op) == SUBREG)
1014 op = SUBREG_REG (op);
1015 if (GET_CODE (op) != MEM)
1016 return 0;
1017 op = XEXP (op, 0);
1018 return ((GET_CODE (op) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (op))
1019 || GET_CODE (op) == CONST || GET_CODE (op) == HIGH
1020 || GET_CODE (op) == LABEL_REF);
1021 }
1022
1023 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
1024
1025 int
1026 label_ref_operand (rtx op, enum machine_mode mode)
1027 {
1028 if (GET_CODE (op) != LABEL_REF)
1029 return 0;
1030 if (GET_MODE (op) != mode)
1031 return 0;
1032 return 1;
1033 }
1034
1035 /* Return 1 if the operand is an argument used in generating pic references
1036 in either the medium/low or medium/anywhere code models of sparc64. */
1037
1038 int
1039 sp64_medium_pic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1040 {
1041 /* Check for (const (minus (symbol_ref:GOT)
1042 (const (minus (label) (pc))))). */
1043 if (GET_CODE (op) != CONST)
1044 return 0;
1045 op = XEXP (op, 0);
1046 if (GET_CODE (op) != MINUS)
1047 return 0;
1048 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
1049 return 0;
1050 /* ??? Ensure symbol is GOT. */
1051 if (GET_CODE (XEXP (op, 1)) != CONST)
1052 return 0;
1053 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
1054 return 0;
1055 return 1;
1056 }
1057
1058 /* Return 1 if the operand is a data segment reference. This includes
1059 the readonly data segment, or in other words anything but the text segment.
1060 This is needed in the medium/anywhere code model on v9. These values
1061 are accessed with EMBMEDANY_BASE_REG. */
1062
1063 int
1064 data_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1065 {
1066 switch (GET_CODE (op))
1067 {
1068 case SYMBOL_REF :
1069 return ! SYMBOL_REF_FUNCTION_P (op);
1070 case PLUS :
1071 /* Assume canonical format of symbol + constant.
1072 Fall through. */
1073 case CONST :
1074 return data_segment_operand (XEXP (op, 0), VOIDmode);
1075 default :
1076 return 0;
1077 }
1078 }
1079
1080 /* Return 1 if the operand is a text segment reference.
1081 This is needed in the medium/anywhere code model on v9. */
1082
1083 int
1084 text_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1085 {
1086 switch (GET_CODE (op))
1087 {
1088 case LABEL_REF :
1089 return 1;
1090 case SYMBOL_REF :
1091 return SYMBOL_REF_FUNCTION_P (op);
1092 case PLUS :
1093 /* Assume canonical format of symbol + constant.
1094 Fall through. */
1095 case CONST :
1096 return text_segment_operand (XEXP (op, 0), VOIDmode);
1097 default :
1098 return 0;
1099 }
1100 }
1101
1102 /* Return 1 if the operand is either a register or a memory operand that is
1103 not symbolic. */
1104
1105 int
1106 reg_or_nonsymb_mem_operand (register rtx op, enum machine_mode mode)
1107 {
1108 if (register_operand (op, mode))
1109 return 1;
1110
1111 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
1112 return 1;
1113
1114 return 0;
1115 }
1116
1117 int
1118 splittable_symbolic_memory_operand (rtx op,
1119 enum machine_mode mode ATTRIBUTE_UNUSED)
1120 {
1121 if (GET_CODE (op) != MEM)
1122 return 0;
1123 if (! symbolic_operand (XEXP (op, 0), Pmode))
1124 return 0;
1125 return 1;
1126 }
1127
1128 int
1129 splittable_immediate_memory_operand (rtx op,
1130 enum machine_mode mode ATTRIBUTE_UNUSED)
1131 {
1132 if (GET_CODE (op) != MEM)
1133 return 0;
1134 if (! immediate_operand (XEXP (op, 0), Pmode))
1135 return 0;
1136 return 1;
1137 }
1138
1139 /* Return truth value of whether OP is EQ or NE. */
1140
1141 int
1142 eq_or_neq (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1143 {
1144 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
1145 }
1146
1147 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
1148 or LTU for non-floating-point. We handle those specially. */
1149
1150 int
1151 normal_comp_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1152 {
1153 enum rtx_code code;
1154
1155 if (!COMPARISON_P (op))
1156 return 0;
1157
1158 if (GET_MODE (XEXP (op, 0)) == CCFPmode
1159 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
1160 return 1;
1161
1162 code = GET_CODE (op);
1163 return (code != NE && code != EQ && code != GEU && code != LTU);
1164 }
1165
1166 /* Return 1 if this is a comparison operator. This allows the use of
1167 MATCH_OPERATOR to recognize all the branch insns. */
1168
1169 int
1170 noov_compare_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1171 {
1172 enum rtx_code code;
1173
1174 if (!COMPARISON_P (op))
1175 return 0;
1176
1177 code = GET_CODE (op);
1178 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode
1179 || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
1180 /* These are the only branches which work with CC_NOOVmode. */
1181 return (code == EQ || code == NE || code == GE || code == LT);
1182 return 1;
1183 }
1184
1185 /* Return 1 if this is a 64-bit comparison operator. This allows the use of
1186 MATCH_OPERATOR to recognize all the branch insns. */
1187
1188 int
1189 noov_compare64_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1190 {
1191 enum rtx_code code;
1192
1193 if (! TARGET_V9)
1194 return 0;
1195
1196 if (!COMPARISON_P (op))
1197 return 0;
1198
1199 code = GET_CODE (op);
1200 if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
1201 /* These are the only branches which work with CCX_NOOVmode. */
1202 return (code == EQ || code == NE || code == GE || code == LT);
1203 return (GET_MODE (XEXP (op, 0)) == CCXmode);
1204 }
1205
1206 /* Nonzero if OP is a comparison operator suitable for use in v9
1207 conditional move or branch on register contents instructions. */
1208
1209 int
1210 v9_regcmp_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1211 {
1212 enum rtx_code code;
1213
1214 if (!COMPARISON_P (op))
1215 return 0;
1216
1217 code = GET_CODE (op);
1218 return v9_regcmp_p (code);
1219 }
1220
1221 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
1222
1223 int
1224 extend_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1225 {
1226 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
1227 }
1228
1229 /* Return nonzero if OP is an operator of mode MODE which can set
1230 the condition codes explicitly. We do not include PLUS and MINUS
1231 because these require CC_NOOVmode, which we handle explicitly. */
1232
1233 int
1234 cc_arithop (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1235 {
1236 if (GET_CODE (op) == AND
1237 || GET_CODE (op) == IOR
1238 || GET_CODE (op) == XOR)
1239 return 1;
1240
1241 return 0;
1242 }
1243
1244 /* Return nonzero if OP is an operator of mode MODE which can bitwise
1245 complement its second operand and set the condition codes explicitly. */
1246
1247 int
1248 cc_arithopn (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1249 {
1250 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
1251 and (xor ... (not ...)) to (not (xor ...)). */
1252 return (GET_CODE (op) == AND
1253 || GET_CODE (op) == IOR);
1254 }
1255 \f
1256 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1257 signed 13 bit immediate field. This is an acceptable SImode operand for
1258 most 3 address instructions. */
1259
1260 int
1261 arith_operand (rtx op, enum machine_mode mode)
1262 {
1263 if (register_operand (op, mode))
1264 return 1;
1265 if (GET_CODE (op) != CONST_INT)
1266 return 0;
1267 return SMALL_INT32 (op);
1268 }
1269
1270 /* Return true if OP is a constant 4096 */
1271
1272 int
1273 arith_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1274 {
1275 if (GET_CODE (op) != CONST_INT)
1276 return 0;
1277 else
1278 return INTVAL (op) == 4096;
1279 }
1280
1281 /* Return true if OP is suitable as second operand for add/sub */
1282
1283 int
1284 arith_add_operand (rtx op, enum machine_mode mode)
1285 {
1286 return arith_operand (op, mode) || arith_4096_operand (op, mode);
1287 }
1288
1289 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
1290 immediate field of OR and XOR instructions. Used for 64-bit
1291 constant formation patterns. */
1292 int
1293 const64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1294 {
1295 return ((GET_CODE (op) == CONST_INT
1296 && SPARC_SIMM13_P (INTVAL (op)))
1297 #if HOST_BITS_PER_WIDE_INT != 64
1298 || (GET_CODE (op) == CONST_DOUBLE
1299 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1300 && (CONST_DOUBLE_HIGH (op) ==
1301 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
1302 (HOST_WIDE_INT)-1 : 0)))
1303 #endif
1304 );
1305 }
1306
1307 /* The same, but only for sethi instructions. */
1308 int
1309 const64_high_operand (rtx op, enum machine_mode mode)
1310 {
1311 return ((GET_CODE (op) == CONST_INT
1312 && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1313 && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1314 )
1315 || (GET_CODE (op) == CONST_DOUBLE
1316 && CONST_DOUBLE_HIGH (op) == 0
1317 && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1318 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
1319 }
1320
1321 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1322 signed 11 bit immediate field. This is an acceptable SImode operand for
1323 the movcc instructions. */
1324
1325 int
1326 arith11_operand (rtx op, enum machine_mode mode)
1327 {
1328 return (register_operand (op, mode)
1329 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
1330 }
1331
1332 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1333 signed 10 bit immediate field. This is an acceptable SImode operand for
1334 the movrcc instructions. */
1335
1336 int
1337 arith10_operand (rtx op, enum machine_mode mode)
1338 {
1339 return (register_operand (op, mode)
1340 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
1341 }
1342
1343 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
1344 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
1345 immediate field.
1346 ARCH64: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1347 can fit in a 13 bit immediate field. This is an acceptable DImode operand
1348 for most 3 address instructions. */
1349
1350 int
1351 arith_double_operand (rtx op, enum machine_mode mode)
1352 {
1353 return (register_operand (op, mode)
1354 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
1355 || (! TARGET_ARCH64
1356 && GET_CODE (op) == CONST_DOUBLE
1357 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1358 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
1359 || (TARGET_ARCH64
1360 && GET_CODE (op) == CONST_DOUBLE
1361 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1362 && ((CONST_DOUBLE_HIGH (op) == -1
1363 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
1364 || (CONST_DOUBLE_HIGH (op) == 0
1365 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
1366 }
1367
1368 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1369
1370 int
1371 arith_double_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1372 {
1373 return (TARGET_ARCH64 &&
1374 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
1375 (GET_CODE (op) == CONST_DOUBLE &&
1376 CONST_DOUBLE_LOW (op) == 4096 &&
1377 CONST_DOUBLE_HIGH (op) == 0)));
1378 }
1379
1380 /* Return true if OP is suitable as second operand for add/sub in DImode */
1381
1382 int
1383 arith_double_add_operand (rtx op, enum machine_mode mode)
1384 {
1385 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
1386 }
1387
1388 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1389 can fit in an 11 bit immediate field. This is an acceptable DImode
1390 operand for the movcc instructions. */
1391 /* ??? Replace with arith11_operand? */
1392
1393 int
1394 arith11_double_operand (rtx op, enum machine_mode mode)
1395 {
1396 return (register_operand (op, mode)
1397 || (GET_CODE (op) == CONST_DOUBLE
1398 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1399 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
1400 && ((CONST_DOUBLE_HIGH (op) == -1
1401 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
1402 || (CONST_DOUBLE_HIGH (op) == 0
1403 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
1404 || (GET_CODE (op) == CONST_INT
1405 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1406 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
1407 }
1408
1409 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1410 can fit in an 10 bit immediate field. This is an acceptable DImode
1411 operand for the movrcc instructions. */
1412 /* ??? Replace with arith10_operand? */
1413
1414 int
1415 arith10_double_operand (rtx op, enum machine_mode mode)
1416 {
1417 return (register_operand (op, mode)
1418 || (GET_CODE (op) == CONST_DOUBLE
1419 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1420 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
1421 && ((CONST_DOUBLE_HIGH (op) == -1
1422 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
1423 || (CONST_DOUBLE_HIGH (op) == 0
1424 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
1425 || (GET_CODE (op) == CONST_INT
1426 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1427 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
1428 }
1429
1430 /* Return truth value of whether OP is an integer which fits the
1431 range constraining immediate operands in most three-address insns,
1432 which have a 13 bit immediate field. */
1433
1434 int
1435 small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1436 {
1437 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1438 }
1439
1440 int
1441 small_int_or_double (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1442 {
1443 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1444 || (GET_CODE (op) == CONST_DOUBLE
1445 && CONST_DOUBLE_HIGH (op) == 0
1446 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))));
1447 }
1448
1449 /* Recognize operand values for the umul instruction. That instruction sign
1450 extends immediate values just like all other sparc instructions, but
1451 interprets the extended result as an unsigned number. */
1452
1453 int
1454 uns_small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1455 {
1456 #if HOST_BITS_PER_WIDE_INT > 32
1457 /* All allowed constants will fit a CONST_INT. */
1458 return (GET_CODE (op) == CONST_INT
1459 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
1460 || (INTVAL (op) >= 0xFFFFF000
1461 && INTVAL (op) <= 0xFFFFFFFF)));
1462 #else
1463 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1464 || (GET_CODE (op) == CONST_DOUBLE
1465 && CONST_DOUBLE_HIGH (op) == 0
1466 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
1467 #endif
1468 }
1469
1470 int
1471 uns_arith_operand (rtx op, enum machine_mode mode)
1472 {
1473 return register_operand (op, mode) || uns_small_int (op, mode);
1474 }
1475
1476 /* Return truth value of statement that OP is a call-clobbered register. */
1477 int
1478 clobbered_register (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1479 {
1480 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1481 }
1482
1483 /* Return 1 if OP is a valid operand for the source of a move insn. */
1484
1485 int
1486 input_operand (rtx op, enum machine_mode mode)
1487 {
1488 /* If both modes are non-void they must be the same. */
1489 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1490 return 0;
1491
1492 /* Allow any one instruction integer constant, and all CONST_INT
1493 variants when we are working in DImode and !arch64. */
1494 if (GET_MODE_CLASS (mode) == MODE_INT
1495 && ((GET_CODE (op) == CONST_INT
1496 && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1497 || SPARC_SIMM13_P (INTVAL (op))
1498 || (mode == DImode
1499 && ! TARGET_ARCH64)))
1500 || (TARGET_ARCH64
1501 && GET_CODE (op) == CONST_DOUBLE
1502 && ((CONST_DOUBLE_HIGH (op) == 0
1503 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1504 ||
1505 #if HOST_BITS_PER_WIDE_INT == 64
1506 (CONST_DOUBLE_HIGH (op) == 0
1507 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1508 #else
1509 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1510 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1511 && CONST_DOUBLE_HIGH (op) == 0)
1512 || (CONST_DOUBLE_HIGH (op) == -1
1513 && CONST_DOUBLE_LOW (op) & 0x80000000) != 0))
1514 #endif
1515 ))))
1516 return 1;
1517
1518 /* If !arch64 and this is a DImode const, allow it so that
1519 the splits can be generated. */
1520 if (! TARGET_ARCH64
1521 && mode == DImode
1522 && GET_CODE (op) == CONST_DOUBLE)
1523 return 1;
1524
1525 if (register_operand (op, mode))
1526 return 1;
1527
1528 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1529 && GET_CODE (op) == CONST_DOUBLE)
1530 return 1;
1531
1532 /* If this is a SUBREG, look inside so that we handle
1533 paradoxical ones. */
1534 if (GET_CODE (op) == SUBREG)
1535 op = SUBREG_REG (op);
1536
1537 /* Check for valid MEM forms. */
1538 if (GET_CODE (op) == MEM)
1539 {
1540 rtx inside = XEXP (op, 0);
1541
1542 if (GET_CODE (inside) == LO_SUM)
1543 {
1544 /* We can't allow these because all of the splits
1545 (eventually as they trickle down into DFmode
1546 splits) require offsettable memory references. */
1547 if (! TARGET_V9
1548 && GET_MODE (op) == TFmode)
1549 return 0;
1550
1551 return (register_operand (XEXP (inside, 0), Pmode)
1552 && CONSTANT_P (XEXP (inside, 1)));
1553 }
1554 return memory_address_p (mode, inside);
1555 }
1556
1557 return 0;
1558 }
1559
1560 /* Return 1 if OP is valid for the lhs of a compare insn. */
1561
1562 int
1563 compare_operand (rtx op, enum machine_mode mode)
1564 {
1565 if (GET_CODE (op) == ZERO_EXTRACT)
1566 return (register_operand (XEXP (op, 0), mode)
1567 && small_int_or_double (XEXP (op, 1), mode)
1568 && small_int_or_double (XEXP (op, 2), mode)
1569 /* This matches cmp_zero_extract. */
1570 && ((mode == SImode
1571 && ((GET_CODE (XEXP (op, 2)) == CONST_INT
1572 && INTVAL (XEXP (op, 2)) > 19)
1573 || (GET_CODE (XEXP (op, 2)) == CONST_DOUBLE
1574 && CONST_DOUBLE_LOW (XEXP (op, 2)) > 19)))
1575 /* This matches cmp_zero_extract_sp64. */
1576 || (mode == DImode
1577 && TARGET_ARCH64
1578 && ((GET_CODE (XEXP (op, 2)) == CONST_INT
1579 && INTVAL (XEXP (op, 2)) > 51)
1580 || (GET_CODE (XEXP (op, 2)) == CONST_DOUBLE
1581 && CONST_DOUBLE_LOW (XEXP (op, 2)) > 51)))));
1582 else
1583 return register_operand (op, mode);
1584 }
1585
1586 \f
1587 /* We know it can't be done in one insn when we get here,
1588 the movsi expander guarantees this. */
1589 void
1590 sparc_emit_set_const32 (rtx op0, rtx op1)
1591 {
1592 enum machine_mode mode = GET_MODE (op0);
1593 rtx temp;
1594
1595 if (GET_CODE (op1) == CONST_INT)
1596 {
1597 HOST_WIDE_INT value = INTVAL (op1);
1598
1599 if (SPARC_SETHI_P (value & GET_MODE_MASK (mode))
1600 || SPARC_SIMM13_P (value))
1601 abort ();
1602 }
1603
1604 /* Full 2-insn decomposition is needed. */
1605 if (reload_in_progress || reload_completed)
1606 temp = op0;
1607 else
1608 temp = gen_reg_rtx (mode);
1609
1610 if (GET_CODE (op1) == CONST_INT)
1611 {
1612 /* Emit them as real moves instead of a HIGH/LO_SUM,
1613 this way CSE can see everything and reuse intermediate
1614 values if it wants. */
1615 if (TARGET_ARCH64
1616 && HOST_BITS_PER_WIDE_INT != 64
1617 && (INTVAL (op1) & 0x80000000) != 0)
1618 emit_insn (gen_rtx_SET
1619 (VOIDmode, temp,
1620 immed_double_const (INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff,
1621 0, DImode)));
1622 else
1623 emit_insn (gen_rtx_SET (VOIDmode, temp,
1624 GEN_INT (INTVAL (op1)
1625 & ~(HOST_WIDE_INT)0x3ff)));
1626
1627 emit_insn (gen_rtx_SET (VOIDmode,
1628 op0,
1629 gen_rtx_IOR (mode, temp,
1630 GEN_INT (INTVAL (op1) & 0x3ff))));
1631 }
1632 else
1633 {
1634 /* A symbol, emit in the traditional way. */
1635 emit_insn (gen_rtx_SET (VOIDmode, temp,
1636 gen_rtx_HIGH (mode, op1)));
1637 emit_insn (gen_rtx_SET (VOIDmode,
1638 op0, gen_rtx_LO_SUM (mode, temp, op1)));
1639
1640 }
1641 }
1642
1643 \f
1644 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1645 If TEMP is non-zero, we are forbidden to use any other scratch
1646 registers. Otherwise, we are allowed to generate them as needed.
1647
1648 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1649 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1650 void
1651 sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp)
1652 {
1653 rtx temp1, temp2, temp3, temp4, temp5;
1654 rtx ti_temp = 0;
1655
1656 if (temp && GET_MODE (temp) == TImode)
1657 {
1658 ti_temp = temp;
1659 temp = gen_rtx_REG (DImode, REGNO (temp));
1660 }
1661
1662 /* SPARC-V9 code-model support. */
1663 switch (sparc_cmodel)
1664 {
1665 case CM_MEDLOW:
1666 /* The range spanned by all instructions in the object is less
1667 than 2^31 bytes (2GB) and the distance from any instruction
1668 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1669 than 2^31 bytes (2GB).
1670
1671 The executable must be in the low 4TB of the virtual address
1672 space.
1673
1674 sethi %hi(symbol), %temp1
1675 or %temp1, %lo(symbol), %reg */
1676 if (temp)
1677 temp1 = temp; /* op0 is allowed. */
1678 else
1679 temp1 = gen_reg_rtx (DImode);
1680
1681 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1682 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1683 break;
1684
1685 case CM_MEDMID:
1686 /* The range spanned by all instructions in the object is less
1687 than 2^31 bytes (2GB) and the distance from any instruction
1688 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1689 than 2^31 bytes (2GB).
1690
1691 The executable must be in the low 16TB of the virtual address
1692 space.
1693
1694 sethi %h44(symbol), %temp1
1695 or %temp1, %m44(symbol), %temp2
1696 sllx %temp2, 12, %temp3
1697 or %temp3, %l44(symbol), %reg */
1698 if (temp)
1699 {
1700 temp1 = op0;
1701 temp2 = op0;
1702 temp3 = temp; /* op0 is allowed. */
1703 }
1704 else
1705 {
1706 temp1 = gen_reg_rtx (DImode);
1707 temp2 = gen_reg_rtx (DImode);
1708 temp3 = gen_reg_rtx (DImode);
1709 }
1710
1711 emit_insn (gen_seth44 (temp1, op1));
1712 emit_insn (gen_setm44 (temp2, temp1, op1));
1713 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1714 gen_rtx_ASHIFT (DImode, temp2, GEN_INT (12))));
1715 emit_insn (gen_setl44 (op0, temp3, op1));
1716 break;
1717
1718 case CM_MEDANY:
1719 /* The range spanned by all instructions in the object is less
1720 than 2^31 bytes (2GB) and the distance from any instruction
1721 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1722 than 2^31 bytes (2GB).
1723
1724 The executable can be placed anywhere in the virtual address
1725 space.
1726
1727 sethi %hh(symbol), %temp1
1728 sethi %lm(symbol), %temp2
1729 or %temp1, %hm(symbol), %temp3
1730 sllx %temp3, 32, %temp4
1731 or %temp4, %temp2, %temp5
1732 or %temp5, %lo(symbol), %reg */
1733 if (temp)
1734 {
1735 /* It is possible that one of the registers we got for operands[2]
1736 might coincide with that of operands[0] (which is why we made
1737 it TImode). Pick the other one to use as our scratch. */
1738 if (rtx_equal_p (temp, op0))
1739 {
1740 if (ti_temp)
1741 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1742 else
1743 abort();
1744 }
1745 temp1 = op0;
1746 temp2 = temp; /* op0 is _not_ allowed, see above. */
1747 temp3 = op0;
1748 temp4 = op0;
1749 temp5 = op0;
1750 }
1751 else
1752 {
1753 temp1 = gen_reg_rtx (DImode);
1754 temp2 = gen_reg_rtx (DImode);
1755 temp3 = gen_reg_rtx (DImode);
1756 temp4 = gen_reg_rtx (DImode);
1757 temp5 = gen_reg_rtx (DImode);
1758 }
1759
1760 emit_insn (gen_sethh (temp1, op1));
1761 emit_insn (gen_setlm (temp2, op1));
1762 emit_insn (gen_sethm (temp3, temp1, op1));
1763 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1764 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1765 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1766 gen_rtx_PLUS (DImode, temp4, temp2)));
1767 emit_insn (gen_setlo (op0, temp5, op1));
1768 break;
1769
1770 case CM_EMBMEDANY:
1771 /* Old old old backwards compatibility kruft here.
1772 Essentially it is MEDLOW with a fixed 64-bit
1773 virtual base added to all data segment addresses.
1774 Text-segment stuff is computed like MEDANY, we can't
1775 reuse the code above because the relocation knobs
1776 look different.
1777
1778 Data segment: sethi %hi(symbol), %temp1
1779 add %temp1, EMBMEDANY_BASE_REG, %temp2
1780 or %temp2, %lo(symbol), %reg */
1781 if (data_segment_operand (op1, GET_MODE (op1)))
1782 {
1783 if (temp)
1784 {
1785 temp1 = temp; /* op0 is allowed. */
1786 temp2 = op0;
1787 }
1788 else
1789 {
1790 temp1 = gen_reg_rtx (DImode);
1791 temp2 = gen_reg_rtx (DImode);
1792 }
1793
1794 emit_insn (gen_embmedany_sethi (temp1, op1));
1795 emit_insn (gen_embmedany_brsum (temp2, temp1));
1796 emit_insn (gen_embmedany_losum (op0, temp2, op1));
1797 }
1798
1799 /* Text segment: sethi %uhi(symbol), %temp1
1800 sethi %hi(symbol), %temp2
1801 or %temp1, %ulo(symbol), %temp3
1802 sllx %temp3, 32, %temp4
1803 or %temp4, %temp2, %temp5
1804 or %temp5, %lo(symbol), %reg */
1805 else
1806 {
1807 if (temp)
1808 {
1809 /* It is possible that one of the registers we got for operands[2]
1810 might coincide with that of operands[0] (which is why we made
1811 it TImode). Pick the other one to use as our scratch. */
1812 if (rtx_equal_p (temp, op0))
1813 {
1814 if (ti_temp)
1815 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1816 else
1817 abort();
1818 }
1819 temp1 = op0;
1820 temp2 = temp; /* op0 is _not_ allowed, see above. */
1821 temp3 = op0;
1822 temp4 = op0;
1823 temp5 = op0;
1824 }
1825 else
1826 {
1827 temp1 = gen_reg_rtx (DImode);
1828 temp2 = gen_reg_rtx (DImode);
1829 temp3 = gen_reg_rtx (DImode);
1830 temp4 = gen_reg_rtx (DImode);
1831 temp5 = gen_reg_rtx (DImode);
1832 }
1833
1834 emit_insn (gen_embmedany_textuhi (temp1, op1));
1835 emit_insn (gen_embmedany_texthi (temp2, op1));
1836 emit_insn (gen_embmedany_textulo (temp3, temp1, op1));
1837 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1838 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1839 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1840 gen_rtx_PLUS (DImode, temp4, temp2)));
1841 emit_insn (gen_embmedany_textlo (op0, temp5, op1));
1842 }
1843 break;
1844
1845 default:
1846 abort();
1847 }
1848 }
1849
1850 /* These avoid problems when cross compiling. If we do not
1851 go through all this hair then the optimizer will see
1852 invalid REG_EQUAL notes or in some cases none at all. */
1853 static void sparc_emit_set_safe_HIGH64 (rtx, HOST_WIDE_INT);
1854 static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
1855 static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
1856 static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
1857
1858 #if HOST_BITS_PER_WIDE_INT == 64
1859 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
1860 #define GEN_INT64(__x) GEN_INT (__x)
1861 #else
1862 #define GEN_HIGHINT64(__x) \
1863 immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode)
1864 #define GEN_INT64(__x) \
1865 immed_double_const ((__x) & 0xffffffff, \
1866 ((__x) & 0x80000000 ? -1 : 0), DImode)
1867 #endif
1868
1869 /* The optimizer is not to assume anything about exactly
1870 which bits are set for a HIGH, they are unspecified.
1871 Unfortunately this leads to many missed optimizations
1872 during CSE. We mask out the non-HIGH bits, and matches
1873 a plain movdi, to alleviate this problem. */
1874 static void
1875 sparc_emit_set_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
1876 {
1877 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1878 }
1879
1880 static rtx
1881 gen_safe_SET64 (rtx dest, HOST_WIDE_INT val)
1882 {
1883 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1884 }
1885
1886 static rtx
1887 gen_safe_OR64 (rtx src, HOST_WIDE_INT val)
1888 {
1889 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1890 }
1891
1892 static rtx
1893 gen_safe_XOR64 (rtx src, HOST_WIDE_INT val)
1894 {
1895 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
1896 }
1897
1898 /* Worker routines for 64-bit constant formation on arch64.
1899 One of the key things to be doing in these emissions is
1900 to create as many temp REGs as possible. This makes it
1901 possible for half-built constants to be used later when
1902 such values are similar to something required later on.
1903 Without doing this, the optimizer cannot see such
1904 opportunities. */
1905
1906 static void sparc_emit_set_const64_quick1 (rtx, rtx,
1907 unsigned HOST_WIDE_INT, int);
1908
1909 static void
1910 sparc_emit_set_const64_quick1 (rtx op0, rtx temp,
1911 unsigned HOST_WIDE_INT low_bits, int is_neg)
1912 {
1913 unsigned HOST_WIDE_INT high_bits;
1914
1915 if (is_neg)
1916 high_bits = (~low_bits) & 0xffffffff;
1917 else
1918 high_bits = low_bits;
1919
1920 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1921 if (!is_neg)
1922 {
1923 emit_insn (gen_rtx_SET (VOIDmode, op0,
1924 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1925 }
1926 else
1927 {
1928 /* If we are XOR'ing with -1, then we should emit a one's complement
1929 instead. This way the combiner will notice logical operations
1930 such as ANDN later on and substitute. */
1931 if ((low_bits & 0x3ff) == 0x3ff)
1932 {
1933 emit_insn (gen_rtx_SET (VOIDmode, op0,
1934 gen_rtx_NOT (DImode, temp)));
1935 }
1936 else
1937 {
1938 emit_insn (gen_rtx_SET (VOIDmode, op0,
1939 gen_safe_XOR64 (temp,
1940 (-(HOST_WIDE_INT)0x400
1941 | (low_bits & 0x3ff)))));
1942 }
1943 }
1944 }
1945
1946 static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT,
1947 unsigned HOST_WIDE_INT, int);
1948
1949 static void
1950 sparc_emit_set_const64_quick2 (rtx op0, rtx temp,
1951 unsigned HOST_WIDE_INT high_bits,
1952 unsigned HOST_WIDE_INT low_immediate,
1953 int shift_count)
1954 {
1955 rtx temp2 = op0;
1956
1957 if ((high_bits & 0xfffffc00) != 0)
1958 {
1959 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1960 if ((high_bits & ~0xfffffc00) != 0)
1961 emit_insn (gen_rtx_SET (VOIDmode, op0,
1962 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1963 else
1964 temp2 = temp;
1965 }
1966 else
1967 {
1968 emit_insn (gen_safe_SET64 (temp, high_bits));
1969 temp2 = temp;
1970 }
1971
1972 /* Now shift it up into place. */
1973 emit_insn (gen_rtx_SET (VOIDmode, op0,
1974 gen_rtx_ASHIFT (DImode, temp2,
1975 GEN_INT (shift_count))));
1976
1977 /* If there is a low immediate part piece, finish up by
1978 putting that in as well. */
1979 if (low_immediate != 0)
1980 emit_insn (gen_rtx_SET (VOIDmode, op0,
1981 gen_safe_OR64 (op0, low_immediate)));
1982 }
1983
1984 static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT,
1985 unsigned HOST_WIDE_INT);
1986
1987 /* Full 64-bit constant decomposition. Even though this is the
1988 'worst' case, we still optimize a few things away. */
1989 static void
1990 sparc_emit_set_const64_longway (rtx op0, rtx temp,
1991 unsigned HOST_WIDE_INT high_bits,
1992 unsigned HOST_WIDE_INT low_bits)
1993 {
1994 rtx sub_temp;
1995
1996 if (reload_in_progress || reload_completed)
1997 sub_temp = op0;
1998 else
1999 sub_temp = gen_reg_rtx (DImode);
2000
2001 if ((high_bits & 0xfffffc00) != 0)
2002 {
2003 sparc_emit_set_safe_HIGH64 (temp, high_bits);
2004 if ((high_bits & ~0xfffffc00) != 0)
2005 emit_insn (gen_rtx_SET (VOIDmode,
2006 sub_temp,
2007 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
2008 else
2009 sub_temp = temp;
2010 }
2011 else
2012 {
2013 emit_insn (gen_safe_SET64 (temp, high_bits));
2014 sub_temp = temp;
2015 }
2016
2017 if (!reload_in_progress && !reload_completed)
2018 {
2019 rtx temp2 = gen_reg_rtx (DImode);
2020 rtx temp3 = gen_reg_rtx (DImode);
2021 rtx temp4 = gen_reg_rtx (DImode);
2022
2023 emit_insn (gen_rtx_SET (VOIDmode, temp4,
2024 gen_rtx_ASHIFT (DImode, sub_temp,
2025 GEN_INT (32))));
2026
2027 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
2028 if ((low_bits & ~0xfffffc00) != 0)
2029 {
2030 emit_insn (gen_rtx_SET (VOIDmode, temp3,
2031 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
2032 emit_insn (gen_rtx_SET (VOIDmode, op0,
2033 gen_rtx_PLUS (DImode, temp4, temp3)));
2034 }
2035 else
2036 {
2037 emit_insn (gen_rtx_SET (VOIDmode, op0,
2038 gen_rtx_PLUS (DImode, temp4, temp2)));
2039 }
2040 }
2041 else
2042 {
2043 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
2044 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
2045 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
2046 int to_shift = 12;
2047
2048 /* We are in the middle of reload, so this is really
2049 painful. However we do still make an attempt to
2050 avoid emitting truly stupid code. */
2051 if (low1 != const0_rtx)
2052 {
2053 emit_insn (gen_rtx_SET (VOIDmode, op0,
2054 gen_rtx_ASHIFT (DImode, sub_temp,
2055 GEN_INT (to_shift))));
2056 emit_insn (gen_rtx_SET (VOIDmode, op0,
2057 gen_rtx_IOR (DImode, op0, low1)));
2058 sub_temp = op0;
2059 to_shift = 12;
2060 }
2061 else
2062 {
2063 to_shift += 12;
2064 }
2065 if (low2 != const0_rtx)
2066 {
2067 emit_insn (gen_rtx_SET (VOIDmode, op0,
2068 gen_rtx_ASHIFT (DImode, sub_temp,
2069 GEN_INT (to_shift))));
2070 emit_insn (gen_rtx_SET (VOIDmode, op0,
2071 gen_rtx_IOR (DImode, op0, low2)));
2072 sub_temp = op0;
2073 to_shift = 8;
2074 }
2075 else
2076 {
2077 to_shift += 8;
2078 }
2079 emit_insn (gen_rtx_SET (VOIDmode, op0,
2080 gen_rtx_ASHIFT (DImode, sub_temp,
2081 GEN_INT (to_shift))));
2082 if (low3 != const0_rtx)
2083 emit_insn (gen_rtx_SET (VOIDmode, op0,
2084 gen_rtx_IOR (DImode, op0, low3)));
2085 /* phew... */
2086 }
2087 }
2088
2089 /* Analyze a 64-bit constant for certain properties. */
2090 static void analyze_64bit_constant (unsigned HOST_WIDE_INT,
2091 unsigned HOST_WIDE_INT,
2092 int *, int *, int *);
2093
2094 static void
2095 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits,
2096 unsigned HOST_WIDE_INT low_bits,
2097 int *hbsp, int *lbsp, int *abbasp)
2098 {
2099 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
2100 int i;
2101
2102 lowest_bit_set = highest_bit_set = -1;
2103 i = 0;
2104 do
2105 {
2106 if ((lowest_bit_set == -1)
2107 && ((low_bits >> i) & 1))
2108 lowest_bit_set = i;
2109 if ((highest_bit_set == -1)
2110 && ((high_bits >> (32 - i - 1)) & 1))
2111 highest_bit_set = (64 - i - 1);
2112 }
2113 while (++i < 32
2114 && ((highest_bit_set == -1)
2115 || (lowest_bit_set == -1)));
2116 if (i == 32)
2117 {
2118 i = 0;
2119 do
2120 {
2121 if ((lowest_bit_set == -1)
2122 && ((high_bits >> i) & 1))
2123 lowest_bit_set = i + 32;
2124 if ((highest_bit_set == -1)
2125 && ((low_bits >> (32 - i - 1)) & 1))
2126 highest_bit_set = 32 - i - 1;
2127 }
2128 while (++i < 32
2129 && ((highest_bit_set == -1)
2130 || (lowest_bit_set == -1)));
2131 }
2132 /* If there are no bits set this should have gone out
2133 as one instruction! */
2134 if (lowest_bit_set == -1
2135 || highest_bit_set == -1)
2136 abort ();
2137 all_bits_between_are_set = 1;
2138 for (i = lowest_bit_set; i <= highest_bit_set; i++)
2139 {
2140 if (i < 32)
2141 {
2142 if ((low_bits & (1 << i)) != 0)
2143 continue;
2144 }
2145 else
2146 {
2147 if ((high_bits & (1 << (i - 32))) != 0)
2148 continue;
2149 }
2150 all_bits_between_are_set = 0;
2151 break;
2152 }
2153 *hbsp = highest_bit_set;
2154 *lbsp = lowest_bit_set;
2155 *abbasp = all_bits_between_are_set;
2156 }
2157
2158 static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT);
2159
2160 static int
2161 const64_is_2insns (unsigned HOST_WIDE_INT high_bits,
2162 unsigned HOST_WIDE_INT low_bits)
2163 {
2164 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
2165
2166 if (high_bits == 0
2167 || high_bits == 0xffffffff)
2168 return 1;
2169
2170 analyze_64bit_constant (high_bits, low_bits,
2171 &highest_bit_set, &lowest_bit_set,
2172 &all_bits_between_are_set);
2173
2174 if ((highest_bit_set == 63
2175 || lowest_bit_set == 0)
2176 && all_bits_between_are_set != 0)
2177 return 1;
2178
2179 if ((highest_bit_set - lowest_bit_set) < 21)
2180 return 1;
2181
2182 return 0;
2183 }
2184
2185 static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT,
2186 unsigned HOST_WIDE_INT,
2187 int, int);
2188
2189 static unsigned HOST_WIDE_INT
2190 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits,
2191 unsigned HOST_WIDE_INT low_bits,
2192 int lowest_bit_set, int shift)
2193 {
2194 HOST_WIDE_INT hi, lo;
2195
2196 if (lowest_bit_set < 32)
2197 {
2198 lo = (low_bits >> lowest_bit_set) << shift;
2199 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
2200 }
2201 else
2202 {
2203 lo = 0;
2204 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
2205 }
2206 if (hi & lo)
2207 abort ();
2208 return (hi | lo);
2209 }
2210
2211 /* Here we are sure to be arch64 and this is an integer constant
2212 being loaded into a register. Emit the most efficient
2213 insn sequence possible. Detection of all the 1-insn cases
2214 has been done already. */
2215 void
2216 sparc_emit_set_const64 (rtx op0, rtx op1)
2217 {
2218 unsigned HOST_WIDE_INT high_bits, low_bits;
2219 int lowest_bit_set, highest_bit_set;
2220 int all_bits_between_are_set;
2221 rtx temp = 0;
2222
2223 /* Sanity check that we know what we are working with. */
2224 if (! TARGET_ARCH64)
2225 abort ();
2226
2227 if (GET_CODE (op0) != SUBREG)
2228 {
2229 if (GET_CODE (op0) != REG
2230 || (REGNO (op0) >= SPARC_FIRST_FP_REG
2231 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
2232 abort ();
2233 }
2234
2235 if (reload_in_progress || reload_completed)
2236 temp = op0;
2237
2238 if (GET_CODE (op1) != CONST_DOUBLE
2239 && GET_CODE (op1) != CONST_INT)
2240 {
2241 sparc_emit_set_symbolic_const64 (op0, op1, temp);
2242 return;
2243 }
2244
2245 if (! temp)
2246 temp = gen_reg_rtx (DImode);
2247
2248 if (GET_CODE (op1) == CONST_DOUBLE)
2249 {
2250 #if HOST_BITS_PER_WIDE_INT == 64
2251 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
2252 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
2253 #else
2254 high_bits = CONST_DOUBLE_HIGH (op1);
2255 low_bits = CONST_DOUBLE_LOW (op1);
2256 #endif
2257 }
2258 else
2259 {
2260 #if HOST_BITS_PER_WIDE_INT == 64
2261 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
2262 low_bits = (INTVAL (op1) & 0xffffffff);
2263 #else
2264 high_bits = ((INTVAL (op1) < 0) ?
2265 0xffffffff :
2266 0x00000000);
2267 low_bits = INTVAL (op1);
2268 #endif
2269 }
2270
2271 /* low_bits bits 0 --> 31
2272 high_bits bits 32 --> 63 */
2273
2274 analyze_64bit_constant (high_bits, low_bits,
2275 &highest_bit_set, &lowest_bit_set,
2276 &all_bits_between_are_set);
2277
2278 /* First try for a 2-insn sequence. */
2279
2280 /* These situations are preferred because the optimizer can
2281 * do more things with them:
2282 * 1) mov -1, %reg
2283 * sllx %reg, shift, %reg
2284 * 2) mov -1, %reg
2285 * srlx %reg, shift, %reg
2286 * 3) mov some_small_const, %reg
2287 * sllx %reg, shift, %reg
2288 */
2289 if (((highest_bit_set == 63
2290 || lowest_bit_set == 0)
2291 && all_bits_between_are_set != 0)
2292 || ((highest_bit_set - lowest_bit_set) < 12))
2293 {
2294 HOST_WIDE_INT the_const = -1;
2295 int shift = lowest_bit_set;
2296
2297 if ((highest_bit_set != 63
2298 && lowest_bit_set != 0)
2299 || all_bits_between_are_set == 0)
2300 {
2301 the_const =
2302 create_simple_focus_bits (high_bits, low_bits,
2303 lowest_bit_set, 0);
2304 }
2305 else if (lowest_bit_set == 0)
2306 shift = -(63 - highest_bit_set);
2307
2308 if (! SPARC_SIMM13_P (the_const))
2309 abort ();
2310
2311 emit_insn (gen_safe_SET64 (temp, the_const));
2312 if (shift > 0)
2313 emit_insn (gen_rtx_SET (VOIDmode,
2314 op0,
2315 gen_rtx_ASHIFT (DImode,
2316 temp,
2317 GEN_INT (shift))));
2318 else if (shift < 0)
2319 emit_insn (gen_rtx_SET (VOIDmode,
2320 op0,
2321 gen_rtx_LSHIFTRT (DImode,
2322 temp,
2323 GEN_INT (-shift))));
2324 else
2325 abort ();
2326 return;
2327 }
2328
2329 /* Now a range of 22 or less bits set somewhere.
2330 * 1) sethi %hi(focus_bits), %reg
2331 * sllx %reg, shift, %reg
2332 * 2) sethi %hi(focus_bits), %reg
2333 * srlx %reg, shift, %reg
2334 */
2335 if ((highest_bit_set - lowest_bit_set) < 21)
2336 {
2337 unsigned HOST_WIDE_INT focus_bits =
2338 create_simple_focus_bits (high_bits, low_bits,
2339 lowest_bit_set, 10);
2340
2341 if (! SPARC_SETHI_P (focus_bits))
2342 abort ();
2343
2344 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
2345
2346 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2347 if (lowest_bit_set < 10)
2348 emit_insn (gen_rtx_SET (VOIDmode,
2349 op0,
2350 gen_rtx_LSHIFTRT (DImode, temp,
2351 GEN_INT (10 - lowest_bit_set))));
2352 else if (lowest_bit_set > 10)
2353 emit_insn (gen_rtx_SET (VOIDmode,
2354 op0,
2355 gen_rtx_ASHIFT (DImode, temp,
2356 GEN_INT (lowest_bit_set - 10))));
2357 else
2358 abort ();
2359 return;
2360 }
2361
2362 /* 1) sethi %hi(low_bits), %reg
2363 * or %reg, %lo(low_bits), %reg
2364 * 2) sethi %hi(~low_bits), %reg
2365 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2366 */
2367 if (high_bits == 0
2368 || high_bits == 0xffffffff)
2369 {
2370 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
2371 (high_bits == 0xffffffff));
2372 return;
2373 }
2374
2375 /* Now, try 3-insn sequences. */
2376
2377 /* 1) sethi %hi(high_bits), %reg
2378 * or %reg, %lo(high_bits), %reg
2379 * sllx %reg, 32, %reg
2380 */
2381 if (low_bits == 0)
2382 {
2383 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
2384 return;
2385 }
2386
2387 /* We may be able to do something quick
2388 when the constant is negated, so try that. */
2389 if (const64_is_2insns ((~high_bits) & 0xffffffff,
2390 (~low_bits) & 0xfffffc00))
2391 {
2392 /* NOTE: The trailing bits get XOR'd so we need the
2393 non-negated bits, not the negated ones. */
2394 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
2395
2396 if ((((~high_bits) & 0xffffffff) == 0
2397 && ((~low_bits) & 0x80000000) == 0)
2398 || (((~high_bits) & 0xffffffff) == 0xffffffff
2399 && ((~low_bits) & 0x80000000) != 0))
2400 {
2401 int fast_int = (~low_bits & 0xffffffff);
2402
2403 if ((SPARC_SETHI_P (fast_int)
2404 && (~high_bits & 0xffffffff) == 0)
2405 || SPARC_SIMM13_P (fast_int))
2406 emit_insn (gen_safe_SET64 (temp, fast_int));
2407 else
2408 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
2409 }
2410 else
2411 {
2412 rtx negated_const;
2413 #if HOST_BITS_PER_WIDE_INT == 64
2414 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2415 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2416 #else
2417 negated_const = immed_double_const ((~low_bits) & 0xfffffc00,
2418 (~high_bits) & 0xffffffff,
2419 DImode);
2420 #endif
2421 sparc_emit_set_const64 (temp, negated_const);
2422 }
2423
2424 /* If we are XOR'ing with -1, then we should emit a one's complement
2425 instead. This way the combiner will notice logical operations
2426 such as ANDN later on and substitute. */
2427 if (trailing_bits == 0x3ff)
2428 {
2429 emit_insn (gen_rtx_SET (VOIDmode, op0,
2430 gen_rtx_NOT (DImode, temp)));
2431 }
2432 else
2433 {
2434 emit_insn (gen_rtx_SET (VOIDmode,
2435 op0,
2436 gen_safe_XOR64 (temp,
2437 (-0x400 | trailing_bits))));
2438 }
2439 return;
2440 }
2441
2442 /* 1) sethi %hi(xxx), %reg
2443 * or %reg, %lo(xxx), %reg
2444 * sllx %reg, yyy, %reg
2445 *
2446 * ??? This is just a generalized version of the low_bits==0
2447 * thing above, FIXME...
2448 */
2449 if ((highest_bit_set - lowest_bit_set) < 32)
2450 {
2451 unsigned HOST_WIDE_INT focus_bits =
2452 create_simple_focus_bits (high_bits, low_bits,
2453 lowest_bit_set, 0);
2454
2455 /* We can't get here in this state. */
2456 if (highest_bit_set < 32
2457 || lowest_bit_set >= 32)
2458 abort ();
2459
2460 /* So what we know is that the set bits straddle the
2461 middle of the 64-bit word. */
2462 sparc_emit_set_const64_quick2 (op0, temp,
2463 focus_bits, 0,
2464 lowest_bit_set);
2465 return;
2466 }
2467
2468 /* 1) sethi %hi(high_bits), %reg
2469 * or %reg, %lo(high_bits), %reg
2470 * sllx %reg, 32, %reg
2471 * or %reg, low_bits, %reg
2472 */
2473 if (SPARC_SIMM13_P(low_bits)
2474 && ((int)low_bits > 0))
2475 {
2476 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2477 return;
2478 }
2479
2480 /* The easiest way when all else fails, is full decomposition. */
2481 #if 0
2482 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2483 high_bits, low_bits, ~high_bits, ~low_bits);
2484 #endif
2485 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2486 }
2487
2488 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2489 return the mode to be used for the comparison. For floating-point,
2490 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2491 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2492 processing is needed. */
2493
2494 enum machine_mode
2495 select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED)
2496 {
2497 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2498 {
2499 switch (op)
2500 {
2501 case EQ:
2502 case NE:
2503 case UNORDERED:
2504 case ORDERED:
2505 case UNLT:
2506 case UNLE:
2507 case UNGT:
2508 case UNGE:
2509 case UNEQ:
2510 case LTGT:
2511 return CCFPmode;
2512
2513 case LT:
2514 case LE:
2515 case GT:
2516 case GE:
2517 return CCFPEmode;
2518
2519 default:
2520 abort ();
2521 }
2522 }
2523 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2524 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2525 {
2526 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2527 return CCX_NOOVmode;
2528 else
2529 return CC_NOOVmode;
2530 }
2531 else
2532 {
2533 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2534 return CCXmode;
2535 else
2536 return CCmode;
2537 }
2538 }
2539
2540 /* X and Y are two things to compare using CODE. Emit the compare insn and
2541 return the rtx for the cc reg in the proper mode. */
2542
2543 rtx
2544 gen_compare_reg (enum rtx_code code, rtx x, rtx y)
2545 {
2546 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
2547 rtx cc_reg;
2548
2549 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2550 fcc regs (cse can't tell they're really call clobbered regs and will
2551 remove a duplicate comparison even if there is an intervening function
2552 call - it will then try to reload the cc reg via an int reg which is why
2553 we need the movcc patterns). It is possible to provide the movcc
2554 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2555 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2556 to tell cse that CCFPE mode registers (even pseudos) are call
2557 clobbered. */
2558
2559 /* ??? This is an experiment. Rather than making changes to cse which may
2560 or may not be easy/clean, we do our own cse. This is possible because
2561 we will generate hard registers. Cse knows they're call clobbered (it
2562 doesn't know the same thing about pseudos). If we guess wrong, no big
2563 deal, but if we win, great! */
2564
2565 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2566 #if 1 /* experiment */
2567 {
2568 int reg;
2569 /* We cycle through the registers to ensure they're all exercised. */
2570 static int next_fcc_reg = 0;
2571 /* Previous x,y for each fcc reg. */
2572 static rtx prev_args[4][2];
2573
2574 /* Scan prev_args for x,y. */
2575 for (reg = 0; reg < 4; reg++)
2576 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2577 break;
2578 if (reg == 4)
2579 {
2580 reg = next_fcc_reg;
2581 prev_args[reg][0] = x;
2582 prev_args[reg][1] = y;
2583 next_fcc_reg = (next_fcc_reg + 1) & 3;
2584 }
2585 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2586 }
2587 #else
2588 cc_reg = gen_reg_rtx (mode);
2589 #endif /* ! experiment */
2590 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2591 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2592 else
2593 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2594
2595 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2596 gen_rtx_COMPARE (mode, x, y)));
2597
2598 return cc_reg;
2599 }
2600
2601 /* This function is used for v9 only.
2602 CODE is the code for an Scc's comparison.
2603 OPERANDS[0] is the target of the Scc insn.
2604 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2605 been generated yet).
2606
2607 This function is needed to turn
2608
2609 (set (reg:SI 110)
2610 (gt (reg:CCX 100 %icc)
2611 (const_int 0)))
2612 into
2613 (set (reg:SI 110)
2614 (gt:DI (reg:CCX 100 %icc)
2615 (const_int 0)))
2616
2617 IE: The instruction recognizer needs to see the mode of the comparison to
2618 find the right instruction. We could use "gt:DI" right in the
2619 define_expand, but leaving it out allows us to handle DI, SI, etc.
2620
2621 We refer to the global sparc compare operands sparc_compare_op0 and
2622 sparc_compare_op1. */
2623
2624 int
2625 gen_v9_scc (enum rtx_code compare_code, register rtx *operands)
2626 {
2627 rtx temp, op0, op1;
2628
2629 if (! TARGET_ARCH64
2630 && (GET_MODE (sparc_compare_op0) == DImode
2631 || GET_MODE (operands[0]) == DImode))
2632 return 0;
2633
2634 op0 = sparc_compare_op0;
2635 op1 = sparc_compare_op1;
2636
2637 /* Try to use the movrCC insns. */
2638 if (TARGET_ARCH64
2639 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2640 && op1 == const0_rtx
2641 && v9_regcmp_p (compare_code))
2642 {
2643 /* Special case for op0 != 0. This can be done with one instruction if
2644 operands[0] == sparc_compare_op0. */
2645
2646 if (compare_code == NE
2647 && GET_MODE (operands[0]) == DImode
2648 && rtx_equal_p (op0, operands[0]))
2649 {
2650 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2651 gen_rtx_IF_THEN_ELSE (DImode,
2652 gen_rtx_fmt_ee (compare_code, DImode,
2653 op0, const0_rtx),
2654 const1_rtx,
2655 operands[0])));
2656 return 1;
2657 }
2658
2659 if (reg_overlap_mentioned_p (operands[0], op0))
2660 {
2661 /* Handle the case where operands[0] == sparc_compare_op0.
2662 We "early clobber" the result. */
2663 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2664 emit_move_insn (op0, sparc_compare_op0);
2665 }
2666
2667 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2668 if (GET_MODE (op0) != DImode)
2669 {
2670 temp = gen_reg_rtx (DImode);
2671 convert_move (temp, op0, 0);
2672 }
2673 else
2674 temp = op0;
2675 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2676 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2677 gen_rtx_fmt_ee (compare_code, DImode,
2678 temp, const0_rtx),
2679 const1_rtx,
2680 operands[0])));
2681 return 1;
2682 }
2683 else
2684 {
2685 operands[1] = gen_compare_reg (compare_code, op0, op1);
2686
2687 switch (GET_MODE (operands[1]))
2688 {
2689 case CCmode :
2690 case CCXmode :
2691 case CCFPEmode :
2692 case CCFPmode :
2693 break;
2694 default :
2695 abort ();
2696 }
2697 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2698 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2699 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2700 gen_rtx_fmt_ee (compare_code,
2701 GET_MODE (operands[1]),
2702 operands[1], const0_rtx),
2703 const1_rtx, operands[0])));
2704 return 1;
2705 }
2706 }
2707
2708 /* Emit a conditional jump insn for the v9 architecture using comparison code
2709 CODE and jump target LABEL.
2710 This function exists to take advantage of the v9 brxx insns. */
2711
2712 void
2713 emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label)
2714 {
2715 emit_jump_insn (gen_rtx_SET (VOIDmode,
2716 pc_rtx,
2717 gen_rtx_IF_THEN_ELSE (VOIDmode,
2718 gen_rtx_fmt_ee (code, GET_MODE (op0),
2719 op0, const0_rtx),
2720 gen_rtx_LABEL_REF (VOIDmode, label),
2721 pc_rtx)));
2722 }
2723
2724 /* Generate a DFmode part of a hard TFmode register.
2725 REG is the TFmode hard register, LOW is 1 for the
2726 low 64bit of the register and 0 otherwise.
2727 */
2728 rtx
2729 gen_df_reg (rtx reg, int low)
2730 {
2731 int regno = REGNO (reg);
2732
2733 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2734 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
2735 return gen_rtx_REG (DFmode, regno);
2736 }
2737 \f
2738 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2739 Unlike normal calls, TFmode operands are passed by reference. It is
2740 assumed that no more than 3 operands are required. */
2741
2742 static void
2743 emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
2744 {
2745 rtx ret_slot = NULL, arg[3], func_sym;
2746 int i;
2747
2748 /* We only expect to be called for conversions, unary, and binary ops. */
2749 if (nargs < 2 || nargs > 3)
2750 abort ();
2751
2752 for (i = 0; i < nargs; ++i)
2753 {
2754 rtx this_arg = operands[i];
2755 rtx this_slot;
2756
2757 /* TFmode arguments and return values are passed by reference. */
2758 if (GET_MODE (this_arg) == TFmode)
2759 {
2760 int force_stack_temp;
2761
2762 force_stack_temp = 0;
2763 if (TARGET_BUGGY_QP_LIB && i == 0)
2764 force_stack_temp = 1;
2765
2766 if (GET_CODE (this_arg) == MEM
2767 && ! force_stack_temp)
2768 this_arg = XEXP (this_arg, 0);
2769 else if (CONSTANT_P (this_arg)
2770 && ! force_stack_temp)
2771 {
2772 this_slot = force_const_mem (TFmode, this_arg);
2773 this_arg = XEXP (this_slot, 0);
2774 }
2775 else
2776 {
2777 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2778
2779 /* Operand 0 is the return value. We'll copy it out later. */
2780 if (i > 0)
2781 emit_move_insn (this_slot, this_arg);
2782 else
2783 ret_slot = this_slot;
2784
2785 this_arg = XEXP (this_slot, 0);
2786 }
2787 }
2788
2789 arg[i] = this_arg;
2790 }
2791
2792 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2793
2794 if (GET_MODE (operands[0]) == TFmode)
2795 {
2796 if (nargs == 2)
2797 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2798 arg[0], GET_MODE (arg[0]),
2799 arg[1], GET_MODE (arg[1]));
2800 else
2801 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2802 arg[0], GET_MODE (arg[0]),
2803 arg[1], GET_MODE (arg[1]),
2804 arg[2], GET_MODE (arg[2]));
2805
2806 if (ret_slot)
2807 emit_move_insn (operands[0], ret_slot);
2808 }
2809 else
2810 {
2811 rtx ret;
2812
2813 if (nargs != 2)
2814 abort ();
2815
2816 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2817 GET_MODE (operands[0]), 1,
2818 arg[1], GET_MODE (arg[1]));
2819
2820 if (ret != operands[0])
2821 emit_move_insn (operands[0], ret);
2822 }
2823 }
2824
2825 /* Expand soft-float TFmode calls to sparc abi routines. */
2826
2827 static void
2828 emit_soft_tfmode_binop (enum rtx_code code, rtx *operands)
2829 {
2830 const char *func;
2831
2832 switch (code)
2833 {
2834 case PLUS:
2835 func = "_Qp_add";
2836 break;
2837 case MINUS:
2838 func = "_Qp_sub";
2839 break;
2840 case MULT:
2841 func = "_Qp_mul";
2842 break;
2843 case DIV:
2844 func = "_Qp_div";
2845 break;
2846 default:
2847 abort ();
2848 }
2849
2850 emit_soft_tfmode_libcall (func, 3, operands);
2851 }
2852
2853 static void
2854 emit_soft_tfmode_unop (enum rtx_code code, rtx *operands)
2855 {
2856 const char *func;
2857
2858 switch (code)
2859 {
2860 case SQRT:
2861 func = "_Qp_sqrt";
2862 break;
2863 default:
2864 abort ();
2865 }
2866
2867 emit_soft_tfmode_libcall (func, 2, operands);
2868 }
2869
2870 static void
2871 emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
2872 {
2873 const char *func;
2874
2875 switch (code)
2876 {
2877 case FLOAT_EXTEND:
2878 switch (GET_MODE (operands[1]))
2879 {
2880 case SFmode:
2881 func = "_Qp_stoq";
2882 break;
2883 case DFmode:
2884 func = "_Qp_dtoq";
2885 break;
2886 default:
2887 abort ();
2888 }
2889 break;
2890
2891 case FLOAT_TRUNCATE:
2892 switch (GET_MODE (operands[0]))
2893 {
2894 case SFmode:
2895 func = "_Qp_qtos";
2896 break;
2897 case DFmode:
2898 func = "_Qp_qtod";
2899 break;
2900 default:
2901 abort ();
2902 }
2903 break;
2904
2905 case FLOAT:
2906 switch (GET_MODE (operands[1]))
2907 {
2908 case SImode:
2909 func = "_Qp_itoq";
2910 break;
2911 case DImode:
2912 func = "_Qp_xtoq";
2913 break;
2914 default:
2915 abort ();
2916 }
2917 break;
2918
2919 case UNSIGNED_FLOAT:
2920 switch (GET_MODE (operands[1]))
2921 {
2922 case SImode:
2923 func = "_Qp_uitoq";
2924 break;
2925 case DImode:
2926 func = "_Qp_uxtoq";
2927 break;
2928 default:
2929 abort ();
2930 }
2931 break;
2932
2933 case FIX:
2934 switch (GET_MODE (operands[0]))
2935 {
2936 case SImode:
2937 func = "_Qp_qtoi";
2938 break;
2939 case DImode:
2940 func = "_Qp_qtox";
2941 break;
2942 default:
2943 abort ();
2944 }
2945 break;
2946
2947 case UNSIGNED_FIX:
2948 switch (GET_MODE (operands[0]))
2949 {
2950 case SImode:
2951 func = "_Qp_qtoui";
2952 break;
2953 case DImode:
2954 func = "_Qp_qtoux";
2955 break;
2956 default:
2957 abort ();
2958 }
2959 break;
2960
2961 default:
2962 abort ();
2963 }
2964
2965 emit_soft_tfmode_libcall (func, 2, operands);
2966 }
2967
2968 /* Expand a hard-float tfmode operation. All arguments must be in
2969 registers. */
2970
2971 static void
2972 emit_hard_tfmode_operation (enum rtx_code code, rtx *operands)
2973 {
2974 rtx op, dest;
2975
2976 if (GET_RTX_CLASS (code) == RTX_UNARY)
2977 {
2978 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2979 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2980 }
2981 else
2982 {
2983 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2984 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2985 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2986 operands[1], operands[2]);
2987 }
2988
2989 if (register_operand (operands[0], VOIDmode))
2990 dest = operands[0];
2991 else
2992 dest = gen_reg_rtx (GET_MODE (operands[0]));
2993
2994 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
2995
2996 if (dest != operands[0])
2997 emit_move_insn (operands[0], dest);
2998 }
2999
3000 void
3001 emit_tfmode_binop (enum rtx_code code, rtx *operands)
3002 {
3003 if (TARGET_HARD_QUAD)
3004 emit_hard_tfmode_operation (code, operands);
3005 else
3006 emit_soft_tfmode_binop (code, operands);
3007 }
3008
3009 void
3010 emit_tfmode_unop (enum rtx_code code, rtx *operands)
3011 {
3012 if (TARGET_HARD_QUAD)
3013 emit_hard_tfmode_operation (code, operands);
3014 else
3015 emit_soft_tfmode_unop (code, operands);
3016 }
3017
3018 void
3019 emit_tfmode_cvt (enum rtx_code code, rtx *operands)
3020 {
3021 if (TARGET_HARD_QUAD)
3022 emit_hard_tfmode_operation (code, operands);
3023 else
3024 emit_soft_tfmode_cvt (code, operands);
3025 }
3026 \f
3027 /* Return nonzero if a branch/jump/call instruction will be emitting
3028 nop into its delay slot. */
3029
3030 int
3031 empty_delay_slot (rtx insn)
3032 {
3033 rtx seq;
3034
3035 /* If no previous instruction (should not happen), return true. */
3036 if (PREV_INSN (insn) == NULL)
3037 return 1;
3038
3039 seq = NEXT_INSN (PREV_INSN (insn));
3040 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
3041 return 0;
3042
3043 return 1;
3044 }
3045
3046 /* Return nonzero if TRIAL can go into the call delay slot. */
3047
3048 int
3049 tls_call_delay (rtx trial)
3050 {
3051 rtx pat, unspec;
3052
3053 /* Binutils allows
3054 call __tls_get_addr, %tgd_call (foo)
3055 add %l7, %o0, %o0, %tgd_add (foo)
3056 while Sun as/ld does not. */
3057 if (TARGET_GNU_TLS || !TARGET_TLS)
3058 return 1;
3059
3060 pat = PATTERN (trial);
3061 if (GET_CODE (pat) != SET || GET_CODE (SET_DEST (pat)) != PLUS)
3062 return 1;
3063
3064 unspec = XEXP (SET_DEST (pat), 1);
3065 if (GET_CODE (unspec) != UNSPEC
3066 || (XINT (unspec, 1) != UNSPEC_TLSGD
3067 && XINT (unspec, 1) != UNSPEC_TLSLDM))
3068 return 1;
3069
3070 return 0;
3071 }
3072
3073 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
3074 instruction. RETURN_P is true if the v9 variant 'return' is to be
3075 considered in the test too.
3076
3077 TRIAL must be a SET whose destination is a REG appropriate for the
3078 'restore' instruction or, if RETURN_P is true, for the 'return'
3079 instruction. */
3080
3081 static int
3082 eligible_for_restore_insn (rtx trial, bool return_p)
3083 {
3084 rtx pat = PATTERN (trial);
3085 rtx src = SET_SRC (pat);
3086
3087 /* The 'restore src,%g0,dest' pattern for word mode and below. */
3088 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
3089 && arith_operand (src, GET_MODE (src)))
3090 {
3091 if (TARGET_ARCH64)
3092 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3093 else
3094 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
3095 }
3096
3097 /* The 'restore src,%g0,dest' pattern for double-word mode. */
3098 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
3099 && arith_double_operand (src, GET_MODE (src)))
3100 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3101
3102 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
3103 else if (! TARGET_FPU && register_operand (src, SFmode))
3104 return 1;
3105
3106 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
3107 else if (! TARGET_FPU && TARGET_ARCH64 && register_operand (src, DFmode))
3108 return 1;
3109
3110 /* If we have the 'return' instruction, anything that does not use
3111 local or output registers and can go into a delay slot wins. */
3112 else if (return_p && TARGET_V9 && ! epilogue_renumber (&pat, 1)
3113 && (get_attr_in_uncond_branch_delay (trial)
3114 == IN_UNCOND_BRANCH_DELAY_TRUE))
3115 return 1;
3116
3117 /* The 'restore src1,src2,dest' pattern for SImode. */
3118 else if (GET_CODE (src) == PLUS
3119 && register_operand (XEXP (src, 0), SImode)
3120 && arith_operand (XEXP (src, 1), SImode))
3121 return 1;
3122
3123 /* The 'restore src1,src2,dest' pattern for DImode. */
3124 else if (GET_CODE (src) == PLUS
3125 && register_operand (XEXP (src, 0), DImode)
3126 && arith_double_operand (XEXP (src, 1), DImode))
3127 return 1;
3128
3129 /* The 'restore src1,%lo(src2),dest' pattern. */
3130 else if (GET_CODE (src) == LO_SUM
3131 && ! TARGET_CM_MEDMID
3132 && ((register_operand (XEXP (src, 0), SImode)
3133 && immediate_operand (XEXP (src, 1), SImode))
3134 || (TARGET_ARCH64
3135 && register_operand (XEXP (src, 0), DImode)
3136 && immediate_operand (XEXP (src, 1), DImode))))
3137 return 1;
3138
3139 /* The 'restore src,src,dest' pattern. */
3140 else if (GET_CODE (src) == ASHIFT
3141 && (register_operand (XEXP (src, 0), SImode)
3142 || register_operand (XEXP (src, 0), DImode))
3143 && XEXP (src, 1) == const1_rtx)
3144 return 1;
3145
3146 return 0;
3147 }
3148
3149 /* Return nonzero if TRIAL can go into the function return's
3150 delay slot. */
3151
3152 int
3153 eligible_for_return_delay (rtx trial)
3154 {
3155 int leaf_function_p = current_function_uses_only_leaf_regs;
3156 rtx pat;
3157
3158 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
3159 return 0;
3160
3161 if (get_attr_length (trial) != 1)
3162 return 0;
3163
3164 /* If there are any call-saved registers, we should scan TRIAL if it
3165 does not reference them. For now just make it easy. */
3166 if (num_gfregs)
3167 return 0;
3168
3169 /* If the function uses __builtin_eh_return, the eh_return machinery
3170 occupies the delay slot. */
3171 if (current_function_calls_eh_return)
3172 return 0;
3173
3174 /* In the case of a true leaf function, anything can go into the slot. */
3175 if (leaf_function_p)
3176 return get_attr_in_uncond_branch_delay (trial)
3177 == IN_UNCOND_BRANCH_DELAY_TRUE;
3178
3179 pat = PATTERN (trial);
3180
3181 /* Otherwise, only operations which can be done in tandem with
3182 a `restore' or `return' insn can go into the delay slot. */
3183 if (GET_CODE (SET_DEST (pat)) != REG
3184 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24))
3185 return 0;
3186
3187 /* If this instruction sets up floating point register and we have a return
3188 instruction, it can probably go in. But restore will not work
3189 with FP_REGS. */
3190 if (REGNO (SET_DEST (pat)) >= 32)
3191 return (TARGET_V9
3192 && ! epilogue_renumber (&pat, 1)
3193 && (get_attr_in_uncond_branch_delay (trial)
3194 == IN_UNCOND_BRANCH_DELAY_TRUE));
3195
3196 return eligible_for_restore_insn (trial, true);
3197 }
3198
3199 /* Return nonzero if TRIAL can go into the sibling call's
3200 delay slot. */
3201
3202 int
3203 eligible_for_sibcall_delay (rtx trial)
3204 {
3205 int leaf_function_p = current_function_uses_only_leaf_regs;
3206 rtx pat;
3207
3208 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
3209 return 0;
3210
3211 if (get_attr_length (trial) != 1)
3212 return 0;
3213
3214 pat = PATTERN (trial);
3215
3216 if (leaf_function_p)
3217 {
3218 /* If the tail call is done using the call instruction,
3219 we have to restore %o7 in the delay slot. */
3220 if (LEAF_SIBCALL_SLOT_RESERVED_P)
3221 return 0;
3222
3223 /* %g1 is used to build the function address */
3224 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
3225 return 0;
3226
3227 return 1;
3228 }
3229
3230 /* Otherwise, only operations which can be done in tandem with
3231 a `restore' insn can go into the delay slot. */
3232 if (GET_CODE (SET_DEST (pat)) != REG
3233 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24)
3234 || REGNO (SET_DEST (pat)) >= 32)
3235 return 0;
3236
3237 /* If it mentions %o7, it can't go in, because sibcall will clobber it
3238 in most cases. */
3239 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
3240 return 0;
3241
3242 return eligible_for_restore_insn (trial, false);
3243 }
3244
3245 int
3246 short_branch (int uid1, int uid2)
3247 {
3248 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
3249
3250 /* Leave a few words of "slop". */
3251 if (delta >= -1023 && delta <= 1022)
3252 return 1;
3253
3254 return 0;
3255 }
3256
3257 /* Return nonzero if REG is not used after INSN.
3258 We assume REG is a reload reg, and therefore does
3259 not live past labels or calls or jumps. */
3260 int
3261 reg_unused_after (rtx reg, rtx insn)
3262 {
3263 enum rtx_code code, prev_code = UNKNOWN;
3264
3265 while ((insn = NEXT_INSN (insn)))
3266 {
3267 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
3268 return 1;
3269
3270 code = GET_CODE (insn);
3271 if (GET_CODE (insn) == CODE_LABEL)
3272 return 1;
3273
3274 if (INSN_P (insn))
3275 {
3276 rtx set = single_set (insn);
3277 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
3278 if (set && in_src)
3279 return 0;
3280 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
3281 return 1;
3282 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
3283 return 0;
3284 }
3285 prev_code = code;
3286 }
3287 return 1;
3288 }
3289 \f
3290 /* Determine if it's legal to put X into the constant pool. This
3291 is not possible if X contains the address of a symbol that is
3292 not constant (TLS) or not known at final link time (PIC). */
3293
3294 static bool
3295 sparc_cannot_force_const_mem (rtx x)
3296 {
3297 switch (GET_CODE (x))
3298 {
3299 case CONST_INT:
3300 case CONST_DOUBLE:
3301 /* Accept all non-symbolic constants. */
3302 return false;
3303
3304 case LABEL_REF:
3305 /* Labels are OK iff we are non-PIC. */
3306 return flag_pic != 0;
3307
3308 case SYMBOL_REF:
3309 /* 'Naked' TLS symbol references are never OK,
3310 non-TLS symbols are OK iff we are non-PIC. */
3311 if (SYMBOL_REF_TLS_MODEL (x))
3312 return true;
3313 else
3314 return flag_pic != 0;
3315
3316 case CONST:
3317 return sparc_cannot_force_const_mem (XEXP (x, 0));
3318 case PLUS:
3319 case MINUS:
3320 return sparc_cannot_force_const_mem (XEXP (x, 0))
3321 || sparc_cannot_force_const_mem (XEXP (x, 1));
3322 case UNSPEC:
3323 return true;
3324 default:
3325 abort ();
3326 }
3327 }
3328 \f
3329 /* The table we use to reference PIC data. */
3330 static GTY(()) rtx global_offset_table;
3331
3332 /* The function we use to get at it. */
3333 static GTY(()) rtx add_pc_to_pic_symbol;
3334 static GTY(()) char add_pc_to_pic_symbol_name[256];
3335
3336 /* Ensure that we are not using patterns that are not OK with PIC. */
3337
3338 int
3339 check_pic (int i)
3340 {
3341 switch (flag_pic)
3342 {
3343 case 1:
3344 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF
3345 || (GET_CODE (recog_data.operand[i]) == CONST
3346 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
3347 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
3348 == global_offset_table)
3349 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
3350 == CONST))))
3351 abort ();
3352 case 2:
3353 default:
3354 return 1;
3355 }
3356 }
3357
3358 /* Return true if X is an address which needs a temporary register when
3359 reloaded while generating PIC code. */
3360
3361 int
3362 pic_address_needs_scratch (rtx x)
3363 {
3364 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3365 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3366 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3367 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3368 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3369 return 1;
3370
3371 return 0;
3372 }
3373
3374 /* Determine if a given RTX is a valid constant. We already know this
3375 satisfies CONSTANT_P. */
3376
3377 bool
3378 legitimate_constant_p (rtx x)
3379 {
3380 rtx inner;
3381
3382 switch (GET_CODE (x))
3383 {
3384 case SYMBOL_REF:
3385 /* TLS symbols are not constant. */
3386 if (SYMBOL_REF_TLS_MODEL (x))
3387 return false;
3388 break;
3389
3390 case CONST:
3391 inner = XEXP (x, 0);
3392
3393 /* Offsets of TLS symbols are never valid.
3394 Discourage CSE from creating them. */
3395 if (GET_CODE (inner) == PLUS
3396 && tls_symbolic_operand (XEXP (inner, 0)))
3397 return false;
3398 break;
3399
3400 case CONST_DOUBLE:
3401 if (GET_MODE (x) == VOIDmode)
3402 return true;
3403
3404 /* Floating point constants are generally not ok.
3405 The only exception is 0.0 in VIS. */
3406 if (TARGET_VIS
3407 && (GET_MODE (x) == SFmode
3408 || GET_MODE (x) == DFmode
3409 || GET_MODE (x) == TFmode)
3410 && fp_zero_operand (x, GET_MODE (x)))
3411 return true;
3412
3413 return false;
3414
3415 default:
3416 break;
3417 }
3418
3419 return true;
3420 }
3421
3422 /* Determine if a given RTX is a valid constant address. */
3423
3424 bool
3425 constant_address_p (rtx x)
3426 {
3427 switch (GET_CODE (x))
3428 {
3429 case LABEL_REF:
3430 case CONST_INT:
3431 case HIGH:
3432 return true;
3433
3434 case CONST:
3435 if (flag_pic && pic_address_needs_scratch (x))
3436 return false;
3437 return legitimate_constant_p (x);
3438
3439 case SYMBOL_REF:
3440 return !flag_pic && legitimate_constant_p (x);
3441
3442 default:
3443 return false;
3444 }
3445 }
3446
3447 /* Nonzero if the constant value X is a legitimate general operand
3448 when generating PIC code. It is given that flag_pic is on and
3449 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3450
3451 bool
3452 legitimate_pic_operand_p (rtx x)
3453 {
3454 if (pic_address_needs_scratch (x))
3455 return false;
3456 if (tls_symbolic_operand (x)
3457 || (GET_CODE (x) == CONST
3458 && GET_CODE (XEXP (x, 0)) == PLUS
3459 && tls_symbolic_operand (XEXP (XEXP (x, 0), 0))))
3460 return false;
3461 return true;
3462 }
3463
3464 /* Return nonzero if ADDR is a valid memory address.
3465 STRICT specifies whether strict register checking applies. */
3466
3467 int
3468 legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
3469 {
3470 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL, imm2;
3471
3472 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
3473 rs1 = addr;
3474 else if (GET_CODE (addr) == PLUS)
3475 {
3476 rs1 = XEXP (addr, 0);
3477 rs2 = XEXP (addr, 1);
3478
3479 /* Canonicalize. REG comes first, if there are no regs,
3480 LO_SUM comes first. */
3481 if (!REG_P (rs1)
3482 && GET_CODE (rs1) != SUBREG
3483 && (REG_P (rs2)
3484 || GET_CODE (rs2) == SUBREG
3485 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
3486 {
3487 rs1 = XEXP (addr, 1);
3488 rs2 = XEXP (addr, 0);
3489 }
3490
3491 if ((flag_pic == 1
3492 && rs1 == pic_offset_table_rtx
3493 && !REG_P (rs2)
3494 && GET_CODE (rs2) != SUBREG
3495 && GET_CODE (rs2) != LO_SUM
3496 && GET_CODE (rs2) != MEM
3497 && !tls_symbolic_operand (rs2)
3498 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
3499 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
3500 || ((REG_P (rs1)
3501 || GET_CODE (rs1) == SUBREG)
3502 && RTX_OK_FOR_OFFSET_P (rs2)))
3503 {
3504 imm1 = rs2;
3505 rs2 = NULL;
3506 }
3507 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
3508 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
3509 {
3510 /* We prohibit REG + REG for TFmode when there are no instructions
3511 which accept REG+REG instructions. We do this because REG+REG
3512 is not an offsetable address. If we get the situation in reload
3513 where source and destination of a movtf pattern are both MEMs with
3514 REG+REG address, then only one of them gets converted to an
3515 offsetable address. */
3516 if (mode == TFmode
3517 && !(TARGET_FPU && TARGET_ARCH64 && TARGET_V9
3518 && TARGET_HARD_QUAD))
3519 return 0;
3520
3521 /* We prohibit REG + REG on ARCH32 if not optimizing for
3522 DFmode/DImode because then mem_min_alignment is likely to be zero
3523 after reload and the forced split would lack a matching splitter
3524 pattern. */
3525 if (TARGET_ARCH32 && !optimize
3526 && (mode == DFmode || mode == DImode))
3527 return 0;
3528 }
3529 else if (USE_AS_OFFSETABLE_LO10
3530 && GET_CODE (rs1) == LO_SUM
3531 && TARGET_ARCH64
3532 && ! TARGET_CM_MEDMID
3533 && RTX_OK_FOR_OLO10_P (rs2))
3534 {
3535 imm2 = rs2;
3536 rs2 = NULL;
3537 imm1 = XEXP (rs1, 1);
3538 rs1 = XEXP (rs1, 0);
3539 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3540 return 0;
3541 }
3542 }
3543 else if (GET_CODE (addr) == LO_SUM)
3544 {
3545 rs1 = XEXP (addr, 0);
3546 imm1 = XEXP (addr, 1);
3547
3548 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3549 return 0;
3550
3551 /* We can't allow TFmode, because an offset greater than or equal to the
3552 alignment (8) may cause the LO_SUM to overflow if !v9. */
3553 if (mode == TFmode && !TARGET_V9)
3554 return 0;
3555 }
3556 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
3557 return 1;
3558 else
3559 return 0;
3560
3561 if (GET_CODE (rs1) == SUBREG)
3562 rs1 = SUBREG_REG (rs1);
3563 if (!REG_P (rs1))
3564 return 0;
3565
3566 if (rs2)
3567 {
3568 if (GET_CODE (rs2) == SUBREG)
3569 rs2 = SUBREG_REG (rs2);
3570 if (!REG_P (rs2))
3571 return 0;
3572 }
3573
3574 if (strict)
3575 {
3576 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
3577 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
3578 return 0;
3579 }
3580 else
3581 {
3582 if ((REGNO (rs1) >= 32
3583 && REGNO (rs1) != FRAME_POINTER_REGNUM
3584 && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
3585 || (rs2
3586 && (REGNO (rs2) >= 32
3587 && REGNO (rs2) != FRAME_POINTER_REGNUM
3588 && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
3589 return 0;
3590 }
3591 return 1;
3592 }
3593
3594 /* Construct the SYMBOL_REF for the tls_get_offset function. */
3595
3596 static GTY(()) rtx sparc_tls_symbol;
3597 static rtx
3598 sparc_tls_get_addr (void)
3599 {
3600 if (!sparc_tls_symbol)
3601 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
3602
3603 return sparc_tls_symbol;
3604 }
3605
3606 static rtx
3607 sparc_tls_got (void)
3608 {
3609 rtx temp;
3610 if (flag_pic)
3611 {
3612 current_function_uses_pic_offset_table = 1;
3613 return pic_offset_table_rtx;
3614 }
3615
3616 if (!global_offset_table)
3617 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3618 temp = gen_reg_rtx (Pmode);
3619 emit_move_insn (temp, global_offset_table);
3620 return temp;
3621 }
3622
3623
3624 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3625 this (thread-local) address. */
3626
3627 rtx
3628 legitimize_tls_address (rtx addr)
3629 {
3630 rtx temp1, temp2, temp3, ret, o0, got, insn;
3631
3632 if (no_new_pseudos)
3633 abort ();
3634
3635 if (GET_CODE (addr) == SYMBOL_REF)
3636 switch (SYMBOL_REF_TLS_MODEL (addr))
3637 {
3638 case TLS_MODEL_GLOBAL_DYNAMIC:
3639 start_sequence ();
3640 temp1 = gen_reg_rtx (SImode);
3641 temp2 = gen_reg_rtx (SImode);
3642 ret = gen_reg_rtx (Pmode);
3643 o0 = gen_rtx_REG (Pmode, 8);
3644 got = sparc_tls_got ();
3645 emit_insn (gen_tgd_hi22 (temp1, addr));
3646 emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
3647 if (TARGET_ARCH32)
3648 {
3649 emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
3650 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (),
3651 addr, const1_rtx));
3652 }
3653 else
3654 {
3655 emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
3656 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (),
3657 addr, const1_rtx));
3658 }
3659 CALL_INSN_FUNCTION_USAGE (insn)
3660 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3661 CALL_INSN_FUNCTION_USAGE (insn));
3662 insn = get_insns ();
3663 end_sequence ();
3664 emit_libcall_block (insn, ret, o0, addr);
3665 break;
3666
3667 case TLS_MODEL_LOCAL_DYNAMIC:
3668 start_sequence ();
3669 temp1 = gen_reg_rtx (SImode);
3670 temp2 = gen_reg_rtx (SImode);
3671 temp3 = gen_reg_rtx (Pmode);
3672 ret = gen_reg_rtx (Pmode);
3673 o0 = gen_rtx_REG (Pmode, 8);
3674 got = sparc_tls_got ();
3675 emit_insn (gen_tldm_hi22 (temp1));
3676 emit_insn (gen_tldm_lo10 (temp2, temp1));
3677 if (TARGET_ARCH32)
3678 {
3679 emit_insn (gen_tldm_add32 (o0, got, temp2));
3680 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (),
3681 const1_rtx));
3682 }
3683 else
3684 {
3685 emit_insn (gen_tldm_add64 (o0, got, temp2));
3686 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (),
3687 const1_rtx));
3688 }
3689 CALL_INSN_FUNCTION_USAGE (insn)
3690 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3691 CALL_INSN_FUNCTION_USAGE (insn));
3692 insn = get_insns ();
3693 end_sequence ();
3694 emit_libcall_block (insn, temp3, o0,
3695 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3696 UNSPEC_TLSLD_BASE));
3697 temp1 = gen_reg_rtx (SImode);
3698 temp2 = gen_reg_rtx (SImode);
3699 emit_insn (gen_tldo_hix22 (temp1, addr));
3700 emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
3701 if (TARGET_ARCH32)
3702 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
3703 else
3704 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
3705 break;
3706
3707 case TLS_MODEL_INITIAL_EXEC:
3708 temp1 = gen_reg_rtx (SImode);
3709 temp2 = gen_reg_rtx (SImode);
3710 temp3 = gen_reg_rtx (Pmode);
3711 got = sparc_tls_got ();
3712 emit_insn (gen_tie_hi22 (temp1, addr));
3713 emit_insn (gen_tie_lo10 (temp2, temp1, addr));
3714 if (TARGET_ARCH32)
3715 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
3716 else
3717 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
3718 if (TARGET_SUN_TLS)
3719 {
3720 ret = gen_reg_rtx (Pmode);
3721 if (TARGET_ARCH32)
3722 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7),
3723 temp3, addr));
3724 else
3725 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7),
3726 temp3, addr));
3727 }
3728 else
3729 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
3730 break;
3731
3732 case TLS_MODEL_LOCAL_EXEC:
3733 temp1 = gen_reg_rtx (Pmode);
3734 temp2 = gen_reg_rtx (Pmode);
3735 if (TARGET_ARCH32)
3736 {
3737 emit_insn (gen_tle_hix22_sp32 (temp1, addr));
3738 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
3739 }
3740 else
3741 {
3742 emit_insn (gen_tle_hix22_sp64 (temp1, addr));
3743 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
3744 }
3745 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
3746 break;
3747
3748 default:
3749 abort ();
3750 }
3751
3752 else
3753 abort (); /* for now ... */
3754
3755 return ret;
3756 }
3757
3758
3759 /* Legitimize PIC addresses. If the address is already position-independent,
3760 we return ORIG. Newly generated position-independent addresses go into a
3761 reg. This is REG if nonzero, otherwise we allocate register(s) as
3762 necessary. */
3763
3764 rtx
3765 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
3766 rtx reg)
3767 {
3768 if (GET_CODE (orig) == SYMBOL_REF)
3769 {
3770 rtx pic_ref, address;
3771 rtx insn;
3772
3773 if (reg == 0)
3774 {
3775 if (reload_in_progress || reload_completed)
3776 abort ();
3777 else
3778 reg = gen_reg_rtx (Pmode);
3779 }
3780
3781 if (flag_pic == 2)
3782 {
3783 /* If not during reload, allocate another temp reg here for loading
3784 in the address, so that these instructions can be optimized
3785 properly. */
3786 rtx temp_reg = ((reload_in_progress || reload_completed)
3787 ? reg : gen_reg_rtx (Pmode));
3788
3789 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3790 won't get confused into thinking that these two instructions
3791 are loading in the true address of the symbol. If in the
3792 future a PIC rtx exists, that should be used instead. */
3793 if (Pmode == SImode)
3794 {
3795 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3796 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
3797 }
3798 else
3799 {
3800 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3801 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
3802 }
3803 address = temp_reg;
3804 }
3805 else
3806 address = orig;
3807
3808 pic_ref = gen_rtx_MEM (Pmode,
3809 gen_rtx_PLUS (Pmode,
3810 pic_offset_table_rtx, address));
3811 current_function_uses_pic_offset_table = 1;
3812 MEM_READONLY_P (pic_ref) = 1;
3813 insn = emit_move_insn (reg, pic_ref);
3814 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3815 by loop. */
3816 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
3817 REG_NOTES (insn));
3818 return reg;
3819 }
3820 else if (GET_CODE (orig) == CONST)
3821 {
3822 rtx base, offset;
3823
3824 if (GET_CODE (XEXP (orig, 0)) == PLUS
3825 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3826 return orig;
3827
3828 if (reg == 0)
3829 {
3830 if (reload_in_progress || reload_completed)
3831 abort ();
3832 else
3833 reg = gen_reg_rtx (Pmode);
3834 }
3835
3836 if (GET_CODE (XEXP (orig, 0)) == PLUS)
3837 {
3838 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3839 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3840 base == reg ? 0 : reg);
3841 }
3842 else
3843 abort ();
3844
3845 if (GET_CODE (offset) == CONST_INT)
3846 {
3847 if (SMALL_INT (offset))
3848 return plus_constant (base, INTVAL (offset));
3849 else if (! reload_in_progress && ! reload_completed)
3850 offset = force_reg (Pmode, offset);
3851 else
3852 /* If we reach here, then something is seriously wrong. */
3853 abort ();
3854 }
3855 return gen_rtx_PLUS (Pmode, base, offset);
3856 }
3857 else if (GET_CODE (orig) == LABEL_REF)
3858 /* ??? Why do we do this? */
3859 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3860 the register is live instead, in case it is eliminated. */
3861 current_function_uses_pic_offset_table = 1;
3862
3863 return orig;
3864 }
3865
3866 /* Try machine-dependent ways of modifying an illegitimate address X
3867 to be legitimate. If we find one, return the new, valid address.
3868
3869 OLDX is the address as it was before break_out_memory_refs was called.
3870 In some cases it is useful to look at this to decide what needs to be done.
3871
3872 MODE is the mode of the operand pointed to by X. */
3873
3874 rtx
3875 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
3876 {
3877 rtx orig_x = x;
3878
3879 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT)
3880 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3881 force_operand (XEXP (x, 0), NULL_RTX));
3882 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT)
3883 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3884 force_operand (XEXP (x, 1), NULL_RTX));
3885 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS)
3886 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX),
3887 XEXP (x, 1));
3888 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS)
3889 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3890 force_operand (XEXP (x, 1), NULL_RTX));
3891
3892 if (x != orig_x && legitimate_address_p (mode, x, FALSE))
3893 return x;
3894
3895 if (tls_symbolic_operand (x))
3896 x = legitimize_tls_address (x);
3897 else if (flag_pic)
3898 x = legitimize_pic_address (x, mode, 0);
3899 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1)))
3900 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3901 copy_to_mode_reg (Pmode, XEXP (x, 1)));
3902 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0)))
3903 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3904 copy_to_mode_reg (Pmode, XEXP (x, 0)));
3905 else if (GET_CODE (x) == SYMBOL_REF
3906 || GET_CODE (x) == CONST
3907 || GET_CODE (x) == LABEL_REF)
3908 x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
3909 return x;
3910 }
3911
3912 /* Emit the special PIC prologue. */
3913
3914 static void
3915 load_pic_register (void)
3916 {
3917 int orig_flag_pic = flag_pic;
3918
3919 /* If we haven't emitted the special helper function, do so now. */
3920 if (add_pc_to_pic_symbol_name[0] == 0)
3921 {
3922 const char *pic_name = reg_names[REGNO (pic_offset_table_rtx)];
3923 int align;
3924
3925 ASM_GENERATE_INTERNAL_LABEL (add_pc_to_pic_symbol_name, "LADDPC", 0);
3926 text_section ();
3927
3928 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
3929 if (align > 0)
3930 ASM_OUTPUT_ALIGN (asm_out_file, align);
3931 ASM_OUTPUT_LABEL (asm_out_file, add_pc_to_pic_symbol_name);
3932 if (flag_delayed_branch)
3933 fprintf (asm_out_file, "\tjmp %%o7+8\n\t add\t%%o7, %s, %s\n",
3934 pic_name, pic_name);
3935 else
3936 fprintf (asm_out_file, "\tadd\t%%o7, %s, %s\n\tjmp %%o7+8\n\t nop\n",
3937 pic_name, pic_name);
3938 }
3939
3940 /* Initialize every time through, since we can't easily
3941 know this to be permanent. */
3942 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3943 add_pc_to_pic_symbol = gen_rtx_SYMBOL_REF (Pmode, add_pc_to_pic_symbol_name);
3944
3945 flag_pic = 0;
3946 emit_insn (gen_load_pcrel_sym (pic_offset_table_rtx, global_offset_table,
3947 add_pc_to_pic_symbol));
3948 flag_pic = orig_flag_pic;
3949
3950 /* Need to emit this whether or not we obey regdecls,
3951 since setjmp/longjmp can cause life info to screw up.
3952 ??? In the case where we don't obey regdecls, this is not sufficient
3953 since we may not fall out the bottom. */
3954 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
3955 }
3956 \f
3957 /* Return 1 if RTX is a MEM which is known to be aligned to at
3958 least a DESIRED byte boundary. */
3959
3960 int
3961 mem_min_alignment (rtx mem, int desired)
3962 {
3963 rtx addr, base, offset;
3964
3965 /* If it's not a MEM we can't accept it. */
3966 if (GET_CODE (mem) != MEM)
3967 return 0;
3968
3969 addr = XEXP (mem, 0);
3970 base = offset = NULL_RTX;
3971 if (GET_CODE (addr) == PLUS)
3972 {
3973 if (GET_CODE (XEXP (addr, 0)) == REG)
3974 {
3975 base = XEXP (addr, 0);
3976
3977 /* What we are saying here is that if the base
3978 REG is aligned properly, the compiler will make
3979 sure any REG based index upon it will be so
3980 as well. */
3981 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3982 offset = XEXP (addr, 1);
3983 else
3984 offset = const0_rtx;
3985 }
3986 }
3987 else if (GET_CODE (addr) == REG)
3988 {
3989 base = addr;
3990 offset = const0_rtx;
3991 }
3992
3993 if (base != NULL_RTX)
3994 {
3995 int regno = REGNO (base);
3996
3997 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
3998 {
3999 /* Check if the compiler has recorded some information
4000 about the alignment of the base REG. If reload has
4001 completed, we already matched with proper alignments.
4002 If not running global_alloc, reload might give us
4003 unaligned pointer to local stack though. */
4004 if (((cfun != 0
4005 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
4006 || (optimize && reload_completed))
4007 && (INTVAL (offset) & (desired - 1)) == 0)
4008 return 1;
4009 }
4010 else
4011 {
4012 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
4013 return 1;
4014 }
4015 }
4016 else if (! TARGET_UNALIGNED_DOUBLES
4017 || CONSTANT_P (addr)
4018 || GET_CODE (addr) == LO_SUM)
4019 {
4020 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
4021 is true, in which case we can only assume that an access is aligned if
4022 it is to a constant address, or the address involves a LO_SUM. */
4023 return 1;
4024 }
4025
4026 /* An obviously unaligned address. */
4027 return 0;
4028 }
4029
4030 \f
4031 /* Vectors to keep interesting information about registers where it can easily
4032 be got. We used to use the actual mode value as the bit number, but there
4033 are more than 32 modes now. Instead we use two tables: one indexed by
4034 hard register number, and one indexed by mode. */
4035
4036 /* The purpose of sparc_mode_class is to shrink the range of modes so that
4037 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
4038 mapped into one sparc_mode_class mode. */
4039
4040 enum sparc_mode_class {
4041 S_MODE, D_MODE, T_MODE, O_MODE,
4042 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
4043 CC_MODE, CCFP_MODE
4044 };
4045
4046 /* Modes for single-word and smaller quantities. */
4047 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
4048
4049 /* Modes for double-word and smaller quantities. */
4050 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
4051
4052 /* Modes for quad-word and smaller quantities. */
4053 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
4054
4055 /* Modes for 8-word and smaller quantities. */
4056 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
4057
4058 /* Modes for single-float quantities. We must allow any single word or
4059 smaller quantity. This is because the fix/float conversion instructions
4060 take integer inputs/outputs from the float registers. */
4061 #define SF_MODES (S_MODES)
4062
4063 /* Modes for double-float and smaller quantities. */
4064 #define DF_MODES (S_MODES | D_MODES)
4065
4066 /* Modes for double-float only quantities. */
4067 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
4068
4069 /* Modes for quad-float only quantities. */
4070 #define TF_ONLY_MODES (1 << (int) TF_MODE)
4071
4072 /* Modes for quad-float and smaller quantities. */
4073 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
4074
4075 /* Modes for quad-float and double-float quantities. */
4076 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
4077
4078 /* Modes for quad-float pair only quantities. */
4079 #define OF_ONLY_MODES (1 << (int) OF_MODE)
4080
4081 /* Modes for quad-float pairs and smaller quantities. */
4082 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
4083
4084 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
4085
4086 /* Modes for condition codes. */
4087 #define CC_MODES (1 << (int) CC_MODE)
4088 #define CCFP_MODES (1 << (int) CCFP_MODE)
4089
4090 /* Value is 1 if register/mode pair is acceptable on sparc.
4091 The funny mixture of D and T modes is because integer operations
4092 do not specially operate on tetra quantities, so non-quad-aligned
4093 registers can hold quadword quantities (except %o4 and %i4 because
4094 they cross fixed registers). */
4095
4096 /* This points to either the 32 bit or the 64 bit version. */
4097 const int *hard_regno_mode_classes;
4098
4099 static const int hard_32bit_mode_classes[] = {
4100 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
4101 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
4102 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
4103 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
4104
4105 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4106 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4107 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4108 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
4109
4110 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4111 and none can hold SFmode/SImode values. */
4112 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4113 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4114 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4115 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4116
4117 /* %fcc[0123] */
4118 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
4119
4120 /* %icc */
4121 CC_MODES
4122 };
4123
4124 static const int hard_64bit_mode_classes[] = {
4125 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4126 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4127 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4128 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
4129
4130 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4131 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4132 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
4133 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
4134
4135 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4136 and none can hold SFmode/SImode values. */
4137 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4138 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4139 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4140 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4141
4142 /* %fcc[0123] */
4143 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
4144
4145 /* %icc */
4146 CC_MODES
4147 };
4148
4149 int sparc_mode_class [NUM_MACHINE_MODES];
4150
4151 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
4152
4153 static void
4154 sparc_init_modes (void)
4155 {
4156 int i;
4157
4158 for (i = 0; i < NUM_MACHINE_MODES; i++)
4159 {
4160 switch (GET_MODE_CLASS (i))
4161 {
4162 case MODE_INT:
4163 case MODE_PARTIAL_INT:
4164 case MODE_COMPLEX_INT:
4165 if (GET_MODE_SIZE (i) <= 4)
4166 sparc_mode_class[i] = 1 << (int) S_MODE;
4167 else if (GET_MODE_SIZE (i) == 8)
4168 sparc_mode_class[i] = 1 << (int) D_MODE;
4169 else if (GET_MODE_SIZE (i) == 16)
4170 sparc_mode_class[i] = 1 << (int) T_MODE;
4171 else if (GET_MODE_SIZE (i) == 32)
4172 sparc_mode_class[i] = 1 << (int) O_MODE;
4173 else
4174 sparc_mode_class[i] = 0;
4175 break;
4176 case MODE_FLOAT:
4177 case MODE_COMPLEX_FLOAT:
4178 if (GET_MODE_SIZE (i) <= 4)
4179 sparc_mode_class[i] = 1 << (int) SF_MODE;
4180 else if (GET_MODE_SIZE (i) == 8)
4181 sparc_mode_class[i] = 1 << (int) DF_MODE;
4182 else if (GET_MODE_SIZE (i) == 16)
4183 sparc_mode_class[i] = 1 << (int) TF_MODE;
4184 else if (GET_MODE_SIZE (i) == 32)
4185 sparc_mode_class[i] = 1 << (int) OF_MODE;
4186 else
4187 sparc_mode_class[i] = 0;
4188 break;
4189 case MODE_CC:
4190 if (i == (int) CCFPmode || i == (int) CCFPEmode)
4191 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
4192 else
4193 sparc_mode_class[i] = 1 << (int) CC_MODE;
4194 break;
4195 default:
4196 sparc_mode_class[i] = 0;
4197 break;
4198 }
4199 }
4200
4201 if (TARGET_ARCH64)
4202 hard_regno_mode_classes = hard_64bit_mode_classes;
4203 else
4204 hard_regno_mode_classes = hard_32bit_mode_classes;
4205
4206 /* Initialize the array used by REGNO_REG_CLASS. */
4207 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4208 {
4209 if (i < 16 && TARGET_V8PLUS)
4210 sparc_regno_reg_class[i] = I64_REGS;
4211 else if (i < 32 || i == FRAME_POINTER_REGNUM)
4212 sparc_regno_reg_class[i] = GENERAL_REGS;
4213 else if (i < 64)
4214 sparc_regno_reg_class[i] = FP_REGS;
4215 else if (i < 96)
4216 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
4217 else if (i < 100)
4218 sparc_regno_reg_class[i] = FPCC_REGS;
4219 else
4220 sparc_regno_reg_class[i] = NO_REGS;
4221 }
4222 }
4223 \f
4224 /* Compute the frame size required by the function. This function is called
4225 during the reload pass and also by sparc_expand_prologue. */
4226
4227 HOST_WIDE_INT
4228 sparc_compute_frame_size (HOST_WIDE_INT size, int leaf_function_p)
4229 {
4230 int outgoing_args_size = (current_function_outgoing_args_size
4231 + REG_PARM_STACK_SPACE (current_function_decl));
4232 int n_regs = 0; /* N_REGS is the number of 4-byte regs saved thus far. */
4233 int i;
4234
4235 if (TARGET_ARCH64)
4236 {
4237 for (i = 0; i < 8; i++)
4238 if (regs_ever_live[i] && ! call_used_regs[i])
4239 n_regs += 2;
4240 }
4241 else
4242 {
4243 for (i = 0; i < 8; i += 2)
4244 if ((regs_ever_live[i] && ! call_used_regs[i])
4245 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4246 n_regs += 2;
4247 }
4248
4249 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
4250 if ((regs_ever_live[i] && ! call_used_regs[i])
4251 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4252 n_regs += 2;
4253
4254 /* Set up values for use in prologue and epilogue. */
4255 num_gfregs = n_regs;
4256
4257 if (leaf_function_p
4258 && n_regs == 0
4259 && size == 0
4260 && current_function_outgoing_args_size == 0)
4261 actual_fsize = apparent_fsize = 0;
4262 else
4263 {
4264 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4265 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8;
4266 apparent_fsize += n_regs * 4;
4267 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
4268 }
4269
4270 /* Make sure nothing can clobber our register windows.
4271 If a SAVE must be done, or there is a stack-local variable,
4272 the register window area must be allocated.
4273 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
4274 if (! leaf_function_p || size > 0)
4275 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
4276
4277 return SPARC_STACK_ALIGN (actual_fsize);
4278 }
4279
4280 /* Output any necessary .register pseudo-ops. */
4281
4282 void
4283 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED)
4284 {
4285 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4286 int i;
4287
4288 if (TARGET_ARCH32)
4289 return;
4290
4291 /* Check if %g[2367] were used without
4292 .register being printed for them already. */
4293 for (i = 2; i < 8; i++)
4294 {
4295 if (regs_ever_live [i]
4296 && ! sparc_hard_reg_printed [i])
4297 {
4298 sparc_hard_reg_printed [i] = 1;
4299 fprintf (file, "\t.register\t%%g%d, #scratch\n", i);
4300 }
4301 if (i == 3) i = 5;
4302 }
4303 #endif
4304 }
4305
4306 /* Save/restore call-saved registers from LOW to HIGH at BASE+OFFSET
4307 as needed. LOW should be double-word aligned for 32-bit registers.
4308 Return the new OFFSET. */
4309
4310 #define SORR_SAVE 0
4311 #define SORR_RESTORE 1
4312
4313 static int
4314 save_or_restore_regs (int low, int high, rtx base, int offset, int action)
4315 {
4316 rtx mem, insn;
4317 int i;
4318
4319 if (TARGET_ARCH64 && high <= 32)
4320 {
4321 for (i = low; i < high; i++)
4322 {
4323 if (regs_ever_live[i] && ! call_used_regs[i])
4324 {
4325 mem = gen_rtx_MEM (DImode, plus_constant (base, offset));
4326 set_mem_alias_set (mem, sparc_sr_alias_set);
4327 if (action == SORR_SAVE)
4328 {
4329 insn = emit_move_insn (mem, gen_rtx_REG (DImode, i));
4330 RTX_FRAME_RELATED_P (insn) = 1;
4331 }
4332 else /* action == SORR_RESTORE */
4333 emit_move_insn (gen_rtx_REG (DImode, i), mem);
4334 offset += 8;
4335 }
4336 }
4337 }
4338 else
4339 {
4340 for (i = low; i < high; i += 2)
4341 {
4342 bool reg0 = regs_ever_live[i] && ! call_used_regs[i];
4343 bool reg1 = regs_ever_live[i+1] && ! call_used_regs[i+1];
4344 enum machine_mode mode;
4345 int regno;
4346
4347 if (reg0 && reg1)
4348 {
4349 mode = i < 32 ? DImode : DFmode;
4350 regno = i;
4351 }
4352 else if (reg0)
4353 {
4354 mode = i < 32 ? SImode : SFmode;
4355 regno = i;
4356 }
4357 else if (reg1)
4358 {
4359 mode = i < 32 ? SImode : SFmode;
4360 regno = i + 1;
4361 offset += 4;
4362 }
4363 else
4364 continue;
4365
4366 mem = gen_rtx_MEM (mode, plus_constant (base, offset));
4367 set_mem_alias_set (mem, sparc_sr_alias_set);
4368 if (action == SORR_SAVE)
4369 {
4370 insn = emit_move_insn (mem, gen_rtx_REG (mode, regno));
4371 RTX_FRAME_RELATED_P (insn) = 1;
4372 }
4373 else /* action == SORR_RESTORE */
4374 emit_move_insn (gen_rtx_REG (mode, regno), mem);
4375
4376 /* Always preserve double-word alignment. */
4377 offset = (offset + 7) & -8;
4378 }
4379 }
4380
4381 return offset;
4382 }
4383
4384 /* Emit code to save call-saved registers. */
4385
4386 static void
4387 emit_save_regs (void)
4388 {
4389 HOST_WIDE_INT offset;
4390 rtx base;
4391
4392 offset = frame_base_offset - apparent_fsize;
4393
4394 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
4395 {
4396 /* ??? This might be optimized a little as %g1 might already have a
4397 value close enough that a single add insn will do. */
4398 /* ??? Although, all of this is probably only a temporary fix
4399 because if %g1 can hold a function result, then
4400 sparc_expand_epilogue will lose (the result will be
4401 clobbered). */
4402 base = gen_rtx_REG (Pmode, 1);
4403 emit_move_insn (base, GEN_INT (offset));
4404 emit_insn (gen_rtx_SET (VOIDmode,
4405 base,
4406 gen_rtx_PLUS (Pmode, frame_base_reg, base)));
4407 offset = 0;
4408 }
4409 else
4410 base = frame_base_reg;
4411
4412 offset = save_or_restore_regs (0, 8, base, offset, SORR_SAVE);
4413 save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, SORR_SAVE);
4414 }
4415
4416 /* Emit code to restore call-saved registers. */
4417
4418 static void
4419 emit_restore_regs (void)
4420 {
4421 HOST_WIDE_INT offset;
4422 rtx base;
4423
4424 offset = frame_base_offset - apparent_fsize;
4425
4426 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
4427 {
4428 base = gen_rtx_REG (Pmode, 1);
4429 emit_move_insn (base, GEN_INT (offset));
4430 emit_insn (gen_rtx_SET (VOIDmode,
4431 base,
4432 gen_rtx_PLUS (Pmode, frame_base_reg, base)));
4433 offset = 0;
4434 }
4435 else
4436 base = frame_base_reg;
4437
4438 offset = save_or_restore_regs (0, 8, base, offset, SORR_RESTORE);
4439 save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, SORR_RESTORE);
4440 }
4441
4442 /* Emit an increment for the stack pointer. */
4443
4444 static void
4445 emit_stack_pointer_increment (rtx increment)
4446 {
4447 if (TARGET_ARCH64)
4448 emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, increment));
4449 else
4450 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, increment));
4451 }
4452
4453 /* Emit a decrement for the stack pointer. */
4454
4455 static void
4456 emit_stack_pointer_decrement (rtx decrement)
4457 {
4458 if (TARGET_ARCH64)
4459 emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, decrement));
4460 else
4461 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, decrement));
4462 }
4463
4464 /* Expand the function prologue. The prologue is responsible for reserving
4465 storage for the frame, saving the call-saved registers and loading the
4466 PIC register if needed. */
4467
4468 void
4469 sparc_expand_prologue (void)
4470 {
4471 int leaf_function_p = current_function_uses_only_leaf_regs;
4472
4473 /* Need to use actual_fsize, since we are also allocating
4474 space for our callee (and our own register save area). */
4475 actual_fsize = sparc_compute_frame_size (get_frame_size(), leaf_function_p);
4476
4477 if (leaf_function_p)
4478 {
4479 frame_base_reg = stack_pointer_rtx;
4480 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
4481 }
4482 else
4483 {
4484 frame_base_reg = hard_frame_pointer_rtx;
4485 frame_base_offset = SPARC_STACK_BIAS;
4486 }
4487
4488 if (actual_fsize == 0)
4489 /* do nothing. */ ;
4490 else if (leaf_function_p)
4491 {
4492 if (actual_fsize <= 4096)
4493 emit_stack_pointer_increment (GEN_INT (- actual_fsize));
4494 else if (actual_fsize <= 8192)
4495 {
4496 emit_stack_pointer_increment (GEN_INT (-4096));
4497 emit_stack_pointer_increment (GEN_INT (4096 - actual_fsize));
4498 }
4499 else
4500 {
4501 rtx reg = gen_rtx_REG (Pmode, 1);
4502 emit_move_insn (reg, GEN_INT (-actual_fsize));
4503 emit_stack_pointer_increment (reg);
4504 }
4505 }
4506 else
4507 {
4508 if (actual_fsize <= 4096)
4509 emit_insn (gen_save_register_window (GEN_INT (-actual_fsize)));
4510 else if (actual_fsize <= 8192)
4511 {
4512 emit_insn (gen_save_register_window (GEN_INT (-4096)));
4513 emit_stack_pointer_increment (GEN_INT (4096 - actual_fsize));
4514 }
4515 else
4516 {
4517 rtx reg = gen_rtx_REG (Pmode, 1);
4518 emit_move_insn (reg, GEN_INT (-actual_fsize));
4519 emit_insn (gen_save_register_window (reg));
4520 }
4521 }
4522
4523 /* Call-saved registers are saved just above the outgoing argument area. */
4524 if (num_gfregs)
4525 emit_save_regs ();
4526
4527 /* Load the PIC register if needed. */
4528 if (flag_pic && current_function_uses_pic_offset_table)
4529 load_pic_register ();
4530 }
4531
4532 /* This function generates the assembly code for function entry, which boils
4533 down to emitting the necessary .register directives. It also informs the
4534 DWARF-2 back-end on the layout of the frame.
4535
4536 ??? Historical cruft: "On SPARC, move-double insns between fpu and cpu need
4537 an 8-byte block of memory. If any fpu reg is used in the function, we
4538 allocate such a block here, at the bottom of the frame, just in case it's
4539 needed." Could this explain the -8 in emit_restore_regs? */
4540
4541 static void
4542 sparc_asm_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4543 {
4544 int leaf_function_p = current_function_uses_only_leaf_regs;
4545
4546 sparc_output_scratch_registers (file);
4547
4548 if (dwarf2out_do_frame () && actual_fsize)
4549 {
4550 char *label = dwarf2out_cfi_label ();
4551
4552 /* The canonical frame address refers to the top of the frame. */
4553 dwarf2out_def_cfa (label,
4554 leaf_function_p
4555 ? STACK_POINTER_REGNUM
4556 : HARD_FRAME_POINTER_REGNUM,
4557 frame_base_offset);
4558
4559 if (! leaf_function_p)
4560 {
4561 /* Note the register window save. This tells the unwinder that
4562 it needs to restore the window registers from the previous
4563 frame's window save area at 0(cfa). */
4564 dwarf2out_window_save (label);
4565
4566 /* The return address (-8) is now in %i7. */
4567 dwarf2out_return_reg (label, 31);
4568 }
4569 }
4570 }
4571
4572 /* Expand the function epilogue, either normal or part of a sibcall.
4573 We emit all the instructions except the return or the call. */
4574
4575 void
4576 sparc_expand_epilogue (void)
4577 {
4578 int leaf_function_p = current_function_uses_only_leaf_regs;
4579
4580 if (num_gfregs)
4581 emit_restore_regs ();
4582
4583 if (actual_fsize == 0)
4584 /* do nothing. */ ;
4585 else if (leaf_function_p)
4586 {
4587 if (actual_fsize <= 4096)
4588 emit_stack_pointer_decrement (GEN_INT (- actual_fsize));
4589 else if (actual_fsize <= 8192)
4590 {
4591 emit_stack_pointer_decrement (GEN_INT (-4096));
4592 emit_stack_pointer_decrement (GEN_INT (4096 - actual_fsize));
4593 }
4594 else
4595 {
4596 rtx reg = gen_rtx_REG (Pmode, 1);
4597 emit_move_insn (reg, GEN_INT (-actual_fsize));
4598 emit_stack_pointer_decrement (reg);
4599 }
4600 }
4601 }
4602
4603 /* This function generates the assembly code for function exit. */
4604
4605 static void
4606 sparc_asm_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4607 {
4608 /* If code does not drop into the epilogue, we have to still output
4609 a dummy nop for the sake of sane backtraces. Otherwise, if the
4610 last two instructions of a function were "call foo; dslot;" this
4611 can make the return PC of foo (ie. address of call instruction
4612 plus 8) point to the first instruction in the next function. */
4613
4614 rtx insn, last_real_insn;
4615
4616 insn = get_last_insn ();
4617
4618 last_real_insn = prev_real_insn (insn);
4619 if (last_real_insn
4620 && GET_CODE (last_real_insn) == INSN
4621 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE)
4622 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0);
4623
4624 if (last_real_insn && GET_CODE (last_real_insn) == CALL_INSN)
4625 fputs("\tnop\n", file);
4626
4627 sparc_output_deferred_case_vectors ();
4628 }
4629
4630 /* Output a 'restore' instruction. */
4631
4632 static void
4633 output_restore (rtx pat)
4634 {
4635 rtx operands[3];
4636
4637 if (! pat)
4638 {
4639 fputs ("\t restore\n", asm_out_file);
4640 return;
4641 }
4642
4643 if (GET_CODE (pat) != SET)
4644 abort ();
4645
4646 operands[0] = SET_DEST (pat);
4647 pat = SET_SRC (pat);
4648
4649 switch (GET_CODE (pat))
4650 {
4651 case PLUS:
4652 operands[1] = XEXP (pat, 0);
4653 operands[2] = XEXP (pat, 1);
4654 output_asm_insn (" restore %r1, %2, %Y0", operands);
4655 break;
4656 case LO_SUM:
4657 operands[1] = XEXP (pat, 0);
4658 operands[2] = XEXP (pat, 1);
4659 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
4660 break;
4661 case ASHIFT:
4662 operands[1] = XEXP (pat, 0);
4663 if (XEXP (pat, 1) != const1_rtx)
4664 abort();
4665 output_asm_insn (" restore %r1, %r1, %Y0", operands);
4666 break;
4667 default:
4668 operands[1] = pat;
4669 output_asm_insn (" restore %%g0, %1, %Y0", operands);
4670 break;
4671 }
4672 }
4673
4674 /* Output a return. */
4675
4676 const char *
4677 output_return (rtx insn)
4678 {
4679 int leaf_function_p = current_function_uses_only_leaf_regs;
4680 bool delay_slot_filled_p = dbr_sequence_length () > 0;
4681 /* True if the caller has placed an "unimp" insn immediately after the call.
4682 This insn is used in the 32-bit ABI when calling a function that returns
4683 a non zero-sized structure. The 64-bit ABI doesn't have it. Be careful
4684 to have this test be the same as that used on the call. */
4685 bool sparc_skip_caller_unimp
4686 = ! TARGET_ARCH64
4687 && current_function_returns_struct
4688 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl)))
4689 == INTEGER_CST)
4690 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl)));
4691
4692 if (leaf_function_p)
4693 {
4694 /* This is a leaf function so we don't have to bother restoring the
4695 register window, which frees us from dealing with the convoluted
4696 semantics of restore/return. We simply output the jump to the
4697 return address and the insn in the delay slot, which usually is
4698 the substraction restoring the stack pointer %sp. */
4699
4700 if (current_function_calls_eh_return)
4701 abort ();
4702
4703 fprintf (asm_out_file, "\tjmp\t%%o7+%d\n", sparc_skip_caller_unimp ? 12 : 8);
4704
4705 if (delay_slot_filled_p)
4706 {
4707 rtx delay = NEXT_INSN (insn);
4708 if (! delay)
4709 abort ();
4710
4711 final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL);
4712 PATTERN (delay) = gen_blockage ();
4713 INSN_CODE (delay) = -1;
4714 }
4715 else
4716 fputs ("\t nop\n", asm_out_file);
4717 }
4718 else
4719 {
4720 /* This is a regular function so we have to restore the register window.
4721 We may have a pending insn for the delay slot, which will be either
4722 combined with the 'restore' instruction or put in the delay slot of
4723 the 'return' instruction. */
4724
4725 if (current_function_calls_eh_return)
4726 {
4727 /* If the function uses __builtin_eh_return, the eh_return
4728 machinery occupies the delay slot. */
4729 if (delay_slot_filled_p || sparc_skip_caller_unimp)
4730 abort ();
4731
4732 if (! flag_delayed_branch)
4733 fputs ("\tadd\t%fp, %g1, %fp\n", asm_out_file);
4734
4735 if (TARGET_V9)
4736 fputs ("\treturn\t%i7+8\n", asm_out_file);
4737 else
4738 fputs ("\trestore\n\tjmp\t%o7+8\n", asm_out_file);
4739
4740 if (flag_delayed_branch)
4741 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file);
4742 else
4743 fputs ("\t nop\n", asm_out_file);
4744 }
4745 else if (delay_slot_filled_p)
4746 {
4747 rtx delay, pat;
4748
4749 delay = NEXT_INSN (insn);
4750 if (! delay)
4751 abort ();
4752
4753 pat = PATTERN (delay);
4754
4755 if (TARGET_V9 && ! epilogue_renumber (&pat, 1))
4756 {
4757 epilogue_renumber (&pat, 0);
4758 fprintf (asm_out_file, "\treturn\t%%i7+%d\n",
4759 sparc_skip_caller_unimp ? 12 : 8);
4760 final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL);
4761 }
4762 else
4763 {
4764 fprintf (asm_out_file, "\tjmp\t%%i7+%d\n",
4765 sparc_skip_caller_unimp ? 12 : 8);
4766 output_restore (pat);
4767 }
4768
4769 PATTERN (delay) = gen_blockage ();
4770 INSN_CODE (delay) = -1;
4771 }
4772 else
4773 {
4774 /* The delay slot is empty. */
4775 if (TARGET_V9)
4776 fprintf (asm_out_file, "\treturn\t%%i7+%d\n\t nop\n",
4777 sparc_skip_caller_unimp ? 12 : 8);
4778 else if (flag_delayed_branch)
4779 fprintf (asm_out_file, "\tjmp\t%%i7+%d\n\t restore\n",
4780 sparc_skip_caller_unimp ? 12 : 8);
4781 else
4782 fprintf (asm_out_file, "\trestore\n\tjmp\t%%o7+%d\n\t nop\n",
4783 sparc_skip_caller_unimp ? 12 : 8);
4784 }
4785 }
4786
4787 return "";
4788 }
4789
4790 /* Output a sibling call. */
4791
4792 const char *
4793 output_sibcall (rtx insn, rtx call_operand)
4794 {
4795 int leaf_function_p = current_function_uses_only_leaf_regs;
4796 bool delay_slot_filled_p = dbr_sequence_length () > 0;
4797 rtx operands[1];
4798
4799 if (! flag_delayed_branch)
4800 abort();
4801
4802 operands[0] = call_operand;
4803
4804 if (leaf_function_p)
4805 {
4806 /* This is a leaf function so we don't have to bother restoring the
4807 register window. We simply output the jump to the function and
4808 the insn in the delay slot (if any). */
4809
4810 if (LEAF_SIBCALL_SLOT_RESERVED_P && delay_slot_filled_p)
4811 abort();
4812
4813 if (delay_slot_filled_p)
4814 {
4815 rtx delay = NEXT_INSN (insn);
4816 if (! delay)
4817 abort ();
4818
4819 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands);
4820 output_asm_insn ("jmp\t%%g1 + %%lo(%a0)", operands);
4821 final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL);
4822
4823 PATTERN (delay) = gen_blockage ();
4824 INSN_CODE (delay) = -1;
4825 }
4826 else
4827 {
4828 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4829 it into branch if possible. */
4830 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands);
4831 output_asm_insn ("call\t%a0, 0", operands);
4832 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands);
4833 }
4834 }
4835 else
4836 {
4837 /* This is a regular function so we have to restore the register window.
4838 We may have a pending insn for the delay slot, which will be combined
4839 with the 'restore' instruction. */
4840
4841 output_asm_insn ("call\t%a0, 0", operands);
4842
4843 if (delay_slot_filled_p)
4844 {
4845 rtx delay = NEXT_INSN (insn);
4846 if (! delay)
4847 abort ();
4848
4849 output_restore (PATTERN (delay));
4850
4851 PATTERN (delay) = gen_blockage ();
4852 INSN_CODE (delay) = -1;
4853 }
4854 else
4855 output_restore (NULL_RTX);
4856 }
4857
4858 return "";
4859 }
4860 \f
4861 /* Functions for handling argument passing.
4862
4863 For 32-bit, the first 6 args are normally in registers and the rest are
4864 pushed. Any arg that starts within the first 6 words is at least
4865 partially passed in a register unless its data type forbids.
4866
4867 For 64-bit, the argument registers are laid out as an array of 16 elements
4868 and arguments are added sequentially. The first 6 int args and up to the
4869 first 16 fp args (depending on size) are passed in regs.
4870
4871 Slot Stack Integral Float Float in structure Double Long Double
4872 ---- ----- -------- ----- ------------------ ------ -----------
4873 15 [SP+248] %f31 %f30,%f31 %d30
4874 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4875 13 [SP+232] %f27 %f26,%f27 %d26
4876 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4877 11 [SP+216] %f23 %f22,%f23 %d22
4878 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4879 9 [SP+200] %f19 %f18,%f19 %d18
4880 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4881 7 [SP+184] %f15 %f14,%f15 %d14
4882 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4883 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4884 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4885 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4886 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4887 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4888 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4889
4890 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4891
4892 Integral arguments are always passed as 64-bit quantities appropriately
4893 extended.
4894
4895 Passing of floating point values is handled as follows.
4896 If a prototype is in scope:
4897 If the value is in a named argument (i.e. not a stdarg function or a
4898 value not part of the `...') then the value is passed in the appropriate
4899 fp reg.
4900 If the value is part of the `...' and is passed in one of the first 6
4901 slots then the value is passed in the appropriate int reg.
4902 If the value is part of the `...' and is not passed in one of the first 6
4903 slots then the value is passed in memory.
4904 If a prototype is not in scope:
4905 If the value is one of the first 6 arguments the value is passed in the
4906 appropriate integer reg and the appropriate fp reg.
4907 If the value is not one of the first 6 arguments the value is passed in
4908 the appropriate fp reg and in memory.
4909
4910
4911 Summary of the calling conventions implemented by GCC on SPARC:
4912
4913 32-bit ABI:
4914 size argument return value
4915
4916 small integer <4 int. reg. int. reg.
4917 word 4 int. reg. int. reg.
4918 double word 8 int. reg. int. reg.
4919
4920 _Complex small integer <8 int. reg. int. reg.
4921 _Complex word 8 int. reg. int. reg.
4922 _Complex double word 16 memory int. reg.
4923
4924 vector integer <=8 int. reg. FP reg.
4925 vector integer >8 memory memory
4926
4927 float 4 int. reg. FP reg.
4928 double 8 int. reg. FP reg.
4929 long double 16 memory memory
4930
4931 _Complex float 8 memory FP reg.
4932 _Complex double 16 memory FP reg.
4933 _Complex long double 32 memory FP reg.
4934
4935 vector float <=32 memory FP reg.
4936 vector float >32 memory memory
4937
4938 aggregate any memory memory
4939
4940
4941
4942 64-bit ABI:
4943 size argument return value
4944
4945 small integer <8 int. reg. int. reg.
4946 word 8 int. reg. int. reg.
4947 double word 16 int. reg. int. reg.
4948
4949 _Complex small integer <16 int. reg. int. reg.
4950 _Complex word 16 int. reg. int. reg.
4951 _Complex double word 32 memory int. reg.
4952
4953 vector integer <=16 FP reg. FP reg.
4954 vector integer 16<s<=32 memory FP reg.
4955 vector integer >32 memory memory
4956
4957 float 4 FP reg. FP reg.
4958 double 8 FP reg. FP reg.
4959 long double 16 FP reg. FP reg.
4960
4961 _Complex float 8 FP reg. FP reg.
4962 _Complex double 16 FP reg. FP reg.
4963 _Complex long double 32 memory FP reg.
4964
4965 vector float <=16 FP reg. FP reg.
4966 vector float 16<s<=32 memory FP reg.
4967 vector float >32 memory memory
4968
4969 aggregate <=16 reg. reg.
4970 aggregate 16<s<=32 memory reg.
4971 aggregate >32 memory memory
4972
4973
4974
4975 Note #1: complex floating-point types follow the extended SPARC ABIs as
4976 implemented by the Sun compiler.
4977
4978 Note #2: integral vector types follow the scalar floating-point types
4979 conventions to match what is implemented by the Sun VIS SDK.
4980
4981 Note #3: floating-point vector types follow the complex floating-point
4982 types conventions. */
4983
4984
4985 /* Maximum number of int regs for args. */
4986 #define SPARC_INT_ARG_MAX 6
4987 /* Maximum number of fp regs for args. */
4988 #define SPARC_FP_ARG_MAX 16
4989
4990 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4991
4992 /* Handle the INIT_CUMULATIVE_ARGS macro.
4993 Initialize a variable CUM of type CUMULATIVE_ARGS
4994 for a call to a function whose data type is FNTYPE.
4995 For a library call, FNTYPE is 0. */
4996
4997 void
4998 init_cumulative_args (struct sparc_args *cum, tree fntype,
4999 rtx libname ATTRIBUTE_UNUSED,
5000 tree fndecl ATTRIBUTE_UNUSED)
5001 {
5002 cum->words = 0;
5003 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
5004 cum->libcall_p = fntype == 0;
5005 }
5006
5007 /* Handle the TARGET_PROMOTE_PROTOTYPES target hook.
5008 When a prototype says `char' or `short', really pass an `int'. */
5009
5010 static bool
5011 sparc_promote_prototypes (tree fntype ATTRIBUTE_UNUSED)
5012 {
5013 return TARGET_ARCH32 ? true : false;
5014 }
5015
5016 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
5017
5018 static bool
5019 sparc_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
5020 {
5021 return TARGET_ARCH64 ? true : false;
5022 }
5023
5024 /* Scan the record type TYPE and return the following predicates:
5025 - INTREGS_P: the record contains at least one field or sub-field
5026 that is eligible for promotion in integer registers.
5027 - FP_REGS_P: the record contains at least one field or sub-field
5028 that is eligible for promotion in floating-point registers.
5029 - PACKED_P: the record contains at least one field that is packed.
5030
5031 Sub-fields are not taken into account for the PACKED_P predicate. */
5032
5033 static void
5034 scan_record_type (tree type, int *intregs_p, int *fpregs_p, int *packed_p)
5035 {
5036 tree field;
5037
5038 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5039 {
5040 if (TREE_CODE (field) == FIELD_DECL)
5041 {
5042 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5043 scan_record_type (TREE_TYPE (field), intregs_p, fpregs_p, 0);
5044 else if (FLOAT_TYPE_P (TREE_TYPE (field)) && TARGET_FPU)
5045 *fpregs_p = 1;
5046 else
5047 *intregs_p = 1;
5048
5049 if (packed_p && DECL_PACKED (field))
5050 *packed_p = 1;
5051 }
5052 }
5053 }
5054
5055 /* Compute the slot number to pass an argument in.
5056 Return the slot number or -1 if passing on the stack.
5057
5058 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5059 the preceding args and about the function being called.
5060 MODE is the argument's machine mode.
5061 TYPE is the data type of the argument (as a tree).
5062 This is null for libcalls where that information may
5063 not be available.
5064 NAMED is nonzero if this argument is a named parameter
5065 (otherwise it is an extra parameter matching an ellipsis).
5066 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
5067 *PREGNO records the register number to use if scalar type.
5068 *PPADDING records the amount of padding needed in words. */
5069
5070 static int
5071 function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode,
5072 tree type, int named, int incoming_p,
5073 int *pregno, int *ppadding)
5074 {
5075 int regbase = (incoming_p
5076 ? SPARC_INCOMING_INT_ARG_FIRST
5077 : SPARC_OUTGOING_INT_ARG_FIRST);
5078 int slotno = cum->words;
5079 int regno;
5080
5081 *ppadding = 0;
5082
5083 if (type && TREE_ADDRESSABLE (type))
5084 return -1;
5085
5086 if (TARGET_ARCH32
5087 && mode == BLKmode
5088 && type
5089 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
5090 return -1;
5091
5092 /* For SPARC64, objects requiring 16-byte alignment get it. */
5093 if (TARGET_ARCH64
5094 && GET_MODE_ALIGNMENT (mode) >= 2 * BITS_PER_WORD
5095 && (slotno & 1) != 0)
5096 slotno++, *ppadding = 1;
5097
5098 switch (GET_MODE_CLASS (mode))
5099 {
5100 case MODE_FLOAT:
5101 case MODE_COMPLEX_FLOAT:
5102 case MODE_VECTOR_INT:
5103 case MODE_VECTOR_FLOAT:
5104 if (TARGET_ARCH64 && TARGET_FPU && named)
5105 {
5106 if (slotno >= SPARC_FP_ARG_MAX)
5107 return -1;
5108 regno = SPARC_FP_ARG_FIRST + slotno * 2;
5109 /* Arguments filling only one single FP register are
5110 right-justified in the outer double FP register. */
5111 if (GET_MODE_SIZE (mode) <= 4)
5112 regno++;
5113 break;
5114 }
5115 /* fallthrough */
5116
5117 case MODE_INT:
5118 case MODE_COMPLEX_INT:
5119 if (slotno >= SPARC_INT_ARG_MAX)
5120 return -1;
5121 regno = regbase + slotno;
5122 break;
5123
5124 case MODE_RANDOM:
5125 if (mode == VOIDmode)
5126 /* MODE is VOIDmode when generating the actual call. */
5127 return -1;
5128
5129 if (mode != BLKmode)
5130 abort ();
5131
5132 /* For SPARC64, objects requiring 16-byte alignment get it. */
5133 if (TARGET_ARCH64
5134 && type
5135 && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5136 && (slotno & 1) != 0)
5137 slotno++, *ppadding = 1;
5138
5139 if (TARGET_ARCH32 || (type && TREE_CODE (type) == UNION_TYPE))
5140 {
5141 if (slotno >= SPARC_INT_ARG_MAX)
5142 return -1;
5143 regno = regbase + slotno;
5144 }
5145 else /* TARGET_ARCH64 && type && TREE_CODE (type) == RECORD_TYPE */
5146 {
5147 int intregs_p = 0, fpregs_p = 0, packed_p = 0;
5148
5149 /* First see what kinds of registers we would need. */
5150 scan_record_type (type, &intregs_p, &fpregs_p, &packed_p);
5151
5152 /* The ABI obviously doesn't specify how packed structures
5153 are passed. These are defined to be passed in int regs
5154 if possible, otherwise memory. */
5155 if (packed_p || !named)
5156 fpregs_p = 0, intregs_p = 1;
5157
5158 /* If all arg slots are filled, then must pass on stack. */
5159 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
5160 return -1;
5161
5162 /* If there are only int args and all int arg slots are filled,
5163 then must pass on stack. */
5164 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
5165 return -1;
5166
5167 /* Note that even if all int arg slots are filled, fp members may
5168 still be passed in regs if such regs are available.
5169 *PREGNO isn't set because there may be more than one, it's up
5170 to the caller to compute them. */
5171 return slotno;
5172 }
5173 break;
5174
5175 default :
5176 abort ();
5177 }
5178
5179 *pregno = regno;
5180 return slotno;
5181 }
5182
5183 /* Handle recursive register counting for structure field layout. */
5184
5185 struct function_arg_record_value_parms
5186 {
5187 rtx ret; /* return expression being built. */
5188 int slotno; /* slot number of the argument. */
5189 int named; /* whether the argument is named. */
5190 int regbase; /* regno of the base register. */
5191 int stack; /* 1 if part of the argument is on the stack. */
5192 int intoffset; /* offset of the first pending integer field. */
5193 unsigned int nregs; /* number of words passed in registers. */
5194 };
5195
5196 static void function_arg_record_value_3
5197 (HOST_WIDE_INT, struct function_arg_record_value_parms *);
5198 static void function_arg_record_value_2
5199 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5200 static void function_arg_record_value_1
5201 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5202 static rtx function_arg_record_value (tree, enum machine_mode, int, int, int);
5203 static rtx function_arg_union_value (int, enum machine_mode, int);
5204
5205 /* A subroutine of function_arg_record_value. Traverse the structure
5206 recursively and determine how many registers will be required. */
5207
5208 static void
5209 function_arg_record_value_1 (tree type, HOST_WIDE_INT startbitpos,
5210 struct function_arg_record_value_parms *parms,
5211 bool packed_p)
5212 {
5213 tree field;
5214
5215 /* We need to compute how many registers are needed so we can
5216 allocate the PARALLEL but before we can do that we need to know
5217 whether there are any packed fields. The ABI obviously doesn't
5218 specify how structures are passed in this case, so they are
5219 defined to be passed in int regs if possible, otherwise memory,
5220 regardless of whether there are fp values present. */
5221
5222 if (! packed_p)
5223 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5224 {
5225 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5226 {
5227 packed_p = true;
5228 break;
5229 }
5230 }
5231
5232 /* Compute how many registers we need. */
5233 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5234 {
5235 if (TREE_CODE (field) == FIELD_DECL)
5236 {
5237 HOST_WIDE_INT bitpos = startbitpos;
5238
5239 if (DECL_SIZE (field) != 0
5240 && host_integerp (bit_position (field), 1))
5241 bitpos += int_bit_position (field);
5242
5243 /* ??? FIXME: else assume zero offset. */
5244
5245 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5246 function_arg_record_value_1 (TREE_TYPE (field),
5247 bitpos,
5248 parms,
5249 packed_p);
5250 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5251 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5252 && TARGET_FPU
5253 && parms->named
5254 && ! packed_p)
5255 {
5256 if (parms->intoffset != -1)
5257 {
5258 unsigned int startbit, endbit;
5259 int intslots, this_slotno;
5260
5261 startbit = parms->intoffset & -BITS_PER_WORD;
5262 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5263
5264 intslots = (endbit - startbit) / BITS_PER_WORD;
5265 this_slotno = parms->slotno + parms->intoffset
5266 / BITS_PER_WORD;
5267
5268 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5269 {
5270 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5271 /* We need to pass this field on the stack. */
5272 parms->stack = 1;
5273 }
5274
5275 parms->nregs += intslots;
5276 parms->intoffset = -1;
5277 }
5278
5279 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
5280 If it wasn't true we wouldn't be here. */
5281 parms->nregs += 1;
5282 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5283 parms->nregs += 1;
5284 }
5285 else
5286 {
5287 if (parms->intoffset == -1)
5288 parms->intoffset = bitpos;
5289 }
5290 }
5291 }
5292 }
5293
5294 /* A subroutine of function_arg_record_value. Assign the bits of the
5295 structure between parms->intoffset and bitpos to integer registers. */
5296
5297 static void
5298 function_arg_record_value_3 (HOST_WIDE_INT bitpos,
5299 struct function_arg_record_value_parms *parms)
5300 {
5301 enum machine_mode mode;
5302 unsigned int regno;
5303 unsigned int startbit, endbit;
5304 int this_slotno, intslots, intoffset;
5305 rtx reg;
5306
5307 if (parms->intoffset == -1)
5308 return;
5309
5310 intoffset = parms->intoffset;
5311 parms->intoffset = -1;
5312
5313 startbit = intoffset & -BITS_PER_WORD;
5314 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5315 intslots = (endbit - startbit) / BITS_PER_WORD;
5316 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
5317
5318 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
5319 if (intslots <= 0)
5320 return;
5321
5322 /* If this is the trailing part of a word, only load that much into
5323 the register. Otherwise load the whole register. Note that in
5324 the latter case we may pick up unwanted bits. It's not a problem
5325 at the moment but may wish to revisit. */
5326
5327 if (intoffset % BITS_PER_WORD != 0)
5328 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5329 MODE_INT, 0);
5330 else
5331 mode = word_mode;
5332
5333 intoffset /= BITS_PER_UNIT;
5334 do
5335 {
5336 regno = parms->regbase + this_slotno;
5337 reg = gen_rtx_REG (mode, regno);
5338 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5339 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5340
5341 this_slotno += 1;
5342 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5343 mode = word_mode;
5344 parms->nregs += 1;
5345 intslots -= 1;
5346 }
5347 while (intslots > 0);
5348 }
5349
5350 /* A subroutine of function_arg_record_value. Traverse the structure
5351 recursively and assign bits to floating point registers. Track which
5352 bits in between need integer registers; invoke function_arg_record_value_3
5353 to make that happen. */
5354
5355 static void
5356 function_arg_record_value_2 (tree type, HOST_WIDE_INT startbitpos,
5357 struct function_arg_record_value_parms *parms,
5358 bool packed_p)
5359 {
5360 tree field;
5361
5362 if (! packed_p)
5363 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5364 {
5365 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5366 {
5367 packed_p = true;
5368 break;
5369 }
5370 }
5371
5372 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5373 {
5374 if (TREE_CODE (field) == FIELD_DECL)
5375 {
5376 HOST_WIDE_INT bitpos = startbitpos;
5377
5378 if (DECL_SIZE (field) != 0
5379 && host_integerp (bit_position (field), 1))
5380 bitpos += int_bit_position (field);
5381
5382 /* ??? FIXME: else assume zero offset. */
5383
5384 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5385 function_arg_record_value_2 (TREE_TYPE (field),
5386 bitpos,
5387 parms,
5388 packed_p);
5389 else if ((FLOAT_TYPE_P (TREE_TYPE (field))
5390 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
5391 && TARGET_FPU
5392 && parms->named
5393 && ! packed_p)
5394 {
5395 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
5396 int regno;
5397 enum machine_mode mode = DECL_MODE (field);
5398 rtx reg;
5399
5400 function_arg_record_value_3 (bitpos, parms);
5401 switch (mode)
5402 {
5403 case SCmode: mode = SFmode; break;
5404 case DCmode: mode = DFmode; break;
5405 case TCmode: mode = TFmode; break;
5406 default: break;
5407 }
5408 regno = SPARC_FP_ARG_FIRST + this_slotno * 2;
5409 if (GET_MODE_SIZE (mode) <= 4 && (bitpos & 32) != 0)
5410 regno++;
5411 reg = gen_rtx_REG (mode, regno);
5412 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5413 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5414 GEN_INT (bitpos / BITS_PER_UNIT));
5415 parms->nregs += 1;
5416 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5417 {
5418 regno += GET_MODE_SIZE (mode) / 4;
5419 reg = gen_rtx_REG (mode, regno);
5420 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5421 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5422 GEN_INT ((bitpos + GET_MODE_BITSIZE (mode))
5423 / BITS_PER_UNIT));
5424 parms->nregs += 1;
5425 }
5426 }
5427 else
5428 {
5429 if (parms->intoffset == -1)
5430 parms->intoffset = bitpos;
5431 }
5432 }
5433 }
5434 }
5435
5436 /* Used by function_arg and function_value to implement the complex
5437 conventions of the 64-bit ABI for passing and returning structures.
5438 Return an expression valid as a return value for the two macros
5439 FUNCTION_ARG and FUNCTION_VALUE.
5440
5441 TYPE is the data type of the argument (as a tree).
5442 This is null for libcalls where that information may
5443 not be available.
5444 MODE is the argument's machine mode.
5445 SLOTNO is the index number of the argument's slot in the parameter array.
5446 NAMED is nonzero if this argument is a named parameter
5447 (otherwise it is an extra parameter matching an ellipsis).
5448 REGBASE is the regno of the base register for the parameter array. */
5449
5450 static rtx
5451 function_arg_record_value (tree type, enum machine_mode mode,
5452 int slotno, int named, int regbase)
5453 {
5454 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5455 struct function_arg_record_value_parms parms;
5456 unsigned int nregs;
5457
5458 parms.ret = NULL_RTX;
5459 parms.slotno = slotno;
5460 parms.named = named;
5461 parms.regbase = regbase;
5462 parms.stack = 0;
5463
5464 /* Compute how many registers we need. */
5465 parms.nregs = 0;
5466 parms.intoffset = 0;
5467 function_arg_record_value_1 (type, 0, &parms, false);
5468
5469 /* Take into account pending integer fields. */
5470 if (parms.intoffset != -1)
5471 {
5472 unsigned int startbit, endbit;
5473 int intslots, this_slotno;
5474
5475 startbit = parms.intoffset & -BITS_PER_WORD;
5476 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5477 intslots = (endbit - startbit) / BITS_PER_WORD;
5478 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
5479
5480 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5481 {
5482 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5483 /* We need to pass this field on the stack. */
5484 parms.stack = 1;
5485 }
5486
5487 parms.nregs += intslots;
5488 }
5489 nregs = parms.nregs;
5490
5491 /* Allocate the vector and handle some annoying special cases. */
5492 if (nregs == 0)
5493 {
5494 /* ??? Empty structure has no value? Duh? */
5495 if (typesize <= 0)
5496 {
5497 /* Though there's nothing really to store, return a word register
5498 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
5499 leads to breakage due to the fact that there are zero bytes to
5500 load. */
5501 return gen_rtx_REG (mode, regbase);
5502 }
5503 else
5504 {
5505 /* ??? C++ has structures with no fields, and yet a size. Give up
5506 for now and pass everything back in integer registers. */
5507 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5508 }
5509 if (nregs + slotno > SPARC_INT_ARG_MAX)
5510 nregs = SPARC_INT_ARG_MAX - slotno;
5511 }
5512 if (nregs == 0)
5513 abort ();
5514
5515 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs));
5516
5517 /* If at least one field must be passed on the stack, generate
5518 (parallel [(expr_list (nil) ...) ...]) so that all fields will
5519 also be passed on the stack. We can't do much better because the
5520 semantics of FUNCTION_ARG_PARTIAL_NREGS doesn't handle the case
5521 of structures for which the fields passed exclusively in registers
5522 are not at the beginning of the structure. */
5523 if (parms.stack)
5524 XVECEXP (parms.ret, 0, 0)
5525 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5526
5527 /* Fill in the entries. */
5528 parms.nregs = 0;
5529 parms.intoffset = 0;
5530 function_arg_record_value_2 (type, 0, &parms, false);
5531 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
5532
5533 if (parms.nregs != nregs)
5534 abort ();
5535
5536 return parms.ret;
5537 }
5538
5539 /* Used by function_arg and function_value to implement the conventions
5540 of the 64-bit ABI for passing and returning unions.
5541 Return an expression valid as a return value for the two macros
5542 FUNCTION_ARG and FUNCTION_VALUE.
5543
5544 SIZE is the size in bytes of the union.
5545 MODE is the argument's machine mode.
5546 REGNO is the hard register the union will be passed in. */
5547
5548 static rtx
5549 function_arg_union_value (int size, enum machine_mode mode, int regno)
5550 {
5551 int nwords = ROUND_ADVANCE (size), i;
5552 rtx regs;
5553
5554 /* Unions are passed left-justified. */
5555 regs = gen_rtx_PARALLEL (mode, rtvec_alloc (nwords));
5556
5557 for (i = 0; i < nwords; i++)
5558 XVECEXP (regs, 0, i)
5559 = gen_rtx_EXPR_LIST (VOIDmode,
5560 gen_rtx_REG (word_mode, regno + i),
5561 GEN_INT (UNITS_PER_WORD * i));
5562
5563 return regs;
5564 }
5565
5566 /* Handle the FUNCTION_ARG macro.
5567 Determine where to put an argument to a function.
5568 Value is zero to push the argument on the stack,
5569 or a hard register in which to store the argument.
5570
5571 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5572 the preceding args and about the function being called.
5573 MODE is the argument's machine mode.
5574 TYPE is the data type of the argument (as a tree).
5575 This is null for libcalls where that information may
5576 not be available.
5577 NAMED is nonzero if this argument is a named parameter
5578 (otherwise it is an extra parameter matching an ellipsis).
5579 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
5580
5581 rtx
5582 function_arg (const struct sparc_args *cum, enum machine_mode mode,
5583 tree type, int named, int incoming_p)
5584 {
5585 int regbase = (incoming_p
5586 ? SPARC_INCOMING_INT_ARG_FIRST
5587 : SPARC_OUTGOING_INT_ARG_FIRST);
5588 int slotno, regno, padding;
5589 rtx reg;
5590
5591 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
5592 &regno, &padding);
5593
5594 if (slotno == -1)
5595 return 0;
5596
5597 if (TARGET_ARCH32)
5598 {
5599 reg = gen_rtx_REG (mode, regno);
5600 return reg;
5601 }
5602
5603 if (type && TREE_CODE (type) == RECORD_TYPE)
5604 {
5605 /* Structures up to 16 bytes in size are passed in arg slots on the
5606 stack and are promoted to registers where possible. */
5607
5608 if (int_size_in_bytes (type) > 16)
5609 abort (); /* shouldn't get here */
5610
5611 return function_arg_record_value (type, mode, slotno, named, regbase);
5612 }
5613 else if (type && TREE_CODE (type) == UNION_TYPE)
5614 {
5615 HOST_WIDE_INT size = int_size_in_bytes (type);
5616
5617 if (size > 16)
5618 abort (); /* shouldn't get here */
5619
5620 return function_arg_union_value (size, mode, regno);
5621 }
5622 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
5623 but also have the slot allocated for them.
5624 If no prototype is in scope fp values in register slots get passed
5625 in two places, either fp regs and int regs or fp regs and memory. */
5626 else if ((GET_MODE_CLASS (mode) == MODE_FLOAT
5627 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5628 || GET_MODE_CLASS (mode) == MODE_VECTOR_INT
5629 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
5630 && SPARC_FP_REG_P (regno))
5631 {
5632 reg = gen_rtx_REG (mode, regno);
5633 if (cum->prototype_p || cum->libcall_p)
5634 {
5635 /* "* 2" because fp reg numbers are recorded in 4 byte
5636 quantities. */
5637 #if 0
5638 /* ??? This will cause the value to be passed in the fp reg and
5639 in the stack. When a prototype exists we want to pass the
5640 value in the reg but reserve space on the stack. That's an
5641 optimization, and is deferred [for a bit]. */
5642 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
5643 return gen_rtx_PARALLEL (mode,
5644 gen_rtvec (2,
5645 gen_rtx_EXPR_LIST (VOIDmode,
5646 NULL_RTX, const0_rtx),
5647 gen_rtx_EXPR_LIST (VOIDmode,
5648 reg, const0_rtx)));
5649 else
5650 #else
5651 /* ??? It seems that passing back a register even when past
5652 the area declared by REG_PARM_STACK_SPACE will allocate
5653 space appropriately, and will not copy the data onto the
5654 stack, exactly as we desire.
5655
5656 This is due to locate_and_pad_parm being called in
5657 expand_call whenever reg_parm_stack_space > 0, which
5658 while beneficial to our example here, would seem to be
5659 in error from what had been intended. Ho hum... -- r~ */
5660 #endif
5661 return reg;
5662 }
5663 else
5664 {
5665 rtx v0, v1;
5666
5667 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
5668 {
5669 int intreg;
5670
5671 /* On incoming, we don't need to know that the value
5672 is passed in %f0 and %i0, and it confuses other parts
5673 causing needless spillage even on the simplest cases. */
5674 if (incoming_p)
5675 return reg;
5676
5677 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
5678 + (regno - SPARC_FP_ARG_FIRST) / 2);
5679
5680 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5681 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
5682 const0_rtx);
5683 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5684 }
5685 else
5686 {
5687 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5688 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5689 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5690 }
5691 }
5692 }
5693 else
5694 {
5695 /* Scalar or complex int. */
5696 reg = gen_rtx_REG (mode, regno);
5697 }
5698
5699 return reg;
5700 }
5701
5702 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
5703 For an arg passed partly in registers and partly in memory,
5704 this is the number of registers used.
5705 For args passed entirely in registers or entirely in memory, zero.
5706
5707 Any arg that starts in the first 6 regs but won't entirely fit in them
5708 needs partial registers on v8. On v9, structures with integer
5709 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
5710 values that begin in the last fp reg [where "last fp reg" varies with the
5711 mode] will be split between that reg and memory. */
5712
5713 int
5714 function_arg_partial_nregs (const struct sparc_args *cum,
5715 enum machine_mode mode, tree type, int named)
5716 {
5717 int slotno, regno, padding;
5718
5719 /* We pass 0 for incoming_p here, it doesn't matter. */
5720 slotno = function_arg_slotno (cum, mode, type, named, 0, &regno, &padding);
5721
5722 if (slotno == -1)
5723 return 0;
5724
5725 if (TARGET_ARCH32)
5726 {
5727 if ((slotno + (mode == BLKmode
5728 ? ROUND_ADVANCE (int_size_in_bytes (type))
5729 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
5730 > SPARC_INT_ARG_MAX)
5731 return SPARC_INT_ARG_MAX - slotno;
5732 }
5733 else
5734 {
5735 /* We are guaranteed by pass_by_reference that the size of the
5736 argument is not greater than 16 bytes, so we only need to
5737 return 1 if the argument is partially passed in registers. */
5738
5739 if (type && AGGREGATE_TYPE_P (type))
5740 {
5741 int size = int_size_in_bytes (type);
5742
5743 if (size > UNITS_PER_WORD
5744 && slotno == SPARC_INT_ARG_MAX - 1)
5745 return 1;
5746 }
5747 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
5748 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5749 && ! (TARGET_FPU && named)))
5750 {
5751 /* The complex types are passed as packed types. */
5752 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
5753 && slotno == SPARC_INT_ARG_MAX - 1)
5754 return 1;
5755 }
5756 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5757 {
5758 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
5759 > SPARC_FP_ARG_MAX)
5760 return 1;
5761 }
5762 }
5763
5764 return 0;
5765 }
5766
5767 /* Return true if the argument should be passed by reference.
5768 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
5769 quad-precision floats by invisible reference.
5770 v9: Aggregates greater than 16 bytes are passed by reference.
5771 For Pascal, also pass arrays by reference. */
5772
5773 static bool
5774 sparc_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5775 enum machine_mode mode, tree type,
5776 bool named ATTRIBUTE_UNUSED)
5777 {
5778 if (TARGET_ARCH32)
5779 {
5780 return ((type && AGGREGATE_TYPE_P (type))
5781 /* Extended ABI (as implemented by the Sun compiler) says
5782 that all complex floats are passed in memory. */
5783 || mode == SCmode
5784 /* Enforce the 2-word cap for passing arguments in registers.
5785 This affects CDImode, TFmode, DCmode, TCmode and large
5786 vector modes. */
5787 || GET_MODE_SIZE (mode) > 8);
5788 }
5789 else
5790 {
5791 return ((type && TREE_CODE (type) == ARRAY_TYPE)
5792 || (type
5793 && AGGREGATE_TYPE_P (type)
5794 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16)
5795 /* Enforce the 2-word cap for passing arguments in registers.
5796 This affects CTImode, TCmode and large vector modes. */
5797 || GET_MODE_SIZE (mode) > 16);
5798 }
5799 }
5800
5801 /* Handle the FUNCTION_ARG_ADVANCE macro.
5802 Update the data in CUM to advance over an argument
5803 of mode MODE and data type TYPE.
5804 TYPE is null for libcalls where that information may not be available. */
5805
5806 void
5807 function_arg_advance (struct sparc_args *cum, enum machine_mode mode,
5808 tree type, int named)
5809 {
5810 int slotno, regno, padding;
5811
5812 /* We pass 0 for incoming_p here, it doesn't matter. */
5813 slotno = function_arg_slotno (cum, mode, type, named, 0, &regno, &padding);
5814
5815 /* If register required leading padding, add it. */
5816 if (slotno != -1)
5817 cum->words += padding;
5818
5819 if (TARGET_ARCH32)
5820 {
5821 cum->words += (mode != BLKmode
5822 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5823 : ROUND_ADVANCE (int_size_in_bytes (type)));
5824 }
5825 else
5826 {
5827 if (type && AGGREGATE_TYPE_P (type))
5828 {
5829 int size = int_size_in_bytes (type);
5830
5831 if (size <= 8)
5832 ++cum->words;
5833 else if (size <= 16)
5834 cum->words += 2;
5835 else /* passed by reference */
5836 ++cum->words;
5837 }
5838 else
5839 {
5840 cum->words += (mode != BLKmode
5841 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5842 : ROUND_ADVANCE (int_size_in_bytes (type)));
5843 }
5844 }
5845 }
5846
5847 /* Handle the FUNCTION_ARG_PADDING macro.
5848 For the 64 bit ABI structs are always stored left shifted in their
5849 argument slot. */
5850
5851 enum direction
5852 function_arg_padding (enum machine_mode mode, tree type)
5853 {
5854 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
5855 return upward;
5856
5857 /* Fall back to the default. */
5858 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
5859 }
5860
5861 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
5862 Specify whether to return the return value in memory. */
5863
5864 static bool
5865 sparc_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
5866 {
5867 if (TARGET_ARCH32)
5868 /* Original SPARC 32-bit ABI says that quad-precision floats
5869 and all structures are returned in memory. Extended ABI
5870 (as implemented by the Sun compiler) says that all complex
5871 floats are returned in registers (8 FP registers at most
5872 for '_Complex long double'). Return all complex integers
5873 in registers (4 at most for '_Complex long long'). */
5874 return (TYPE_MODE (type) == BLKmode
5875 || TYPE_MODE (type) == TFmode
5876 /* Integral vector types follow the scalar FP types conventions. */
5877 || (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_VECTOR_INT
5878 && GET_MODE_SIZE (TYPE_MODE (type)) > 8)
5879 /* FP vector types follow the complex FP types conventions. */
5880 || (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_VECTOR_FLOAT
5881 && GET_MODE_SIZE (TYPE_MODE (type)) > 32));
5882 else
5883 /* Original SPARC 64-bit ABI says that structures and unions
5884 smaller than 32 bytes are returned in registers. Extended
5885 ABI (as implemented by the Sun compiler) says that all complex
5886 floats are returned in registers (8 FP registers at most
5887 for '_Complex long double'). Return all complex integers
5888 in registers (4 at most for '_Complex TItype'). */
5889 return ((TYPE_MODE (type) == BLKmode
5890 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 32)
5891 || GET_MODE_SIZE (TYPE_MODE (type)) > 32);
5892 }
5893
5894 /* Handle the TARGET_STRUCT_VALUE target hook.
5895 Return where to find the structure return value address. */
5896
5897 static rtx
5898 sparc_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED, int incoming)
5899 {
5900 if (TARGET_ARCH64)
5901 return 0;
5902 else
5903 {
5904 if (incoming)
5905 return gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx,
5906 STRUCT_VALUE_OFFSET));
5907 else
5908 return gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx,
5909 STRUCT_VALUE_OFFSET));
5910 }
5911 }
5912
5913 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5914 For v9, function return values are subject to the same rules as arguments,
5915 except that up to 32 bytes may be returned in registers. */
5916
5917 rtx
5918 function_value (tree type, enum machine_mode mode, int incoming_p)
5919 {
5920 /* Beware that the two values are swapped here wrt function_arg. */
5921 int regbase = (incoming_p
5922 ? SPARC_OUTGOING_INT_ARG_FIRST
5923 : SPARC_INCOMING_INT_ARG_FIRST);
5924 int regno;
5925
5926 if (TARGET_ARCH64 && type)
5927 {
5928 if (TREE_CODE (type) == RECORD_TYPE)
5929 {
5930 /* Structures up to 32 bytes in size are passed in registers,
5931 promoted to fp registers where possible. */
5932
5933 if (int_size_in_bytes (type) > 32)
5934 abort (); /* shouldn't get here */
5935
5936 return function_arg_record_value (type, mode, 0, 1, regbase);
5937 }
5938 else if (TREE_CODE (type) == UNION_TYPE)
5939 {
5940 HOST_WIDE_INT size = int_size_in_bytes (type);
5941
5942 if (size > 32)
5943 abort (); /* shouldn't get here */
5944
5945 return function_arg_union_value (size, mode, regbase);
5946 }
5947 else if (AGGREGATE_TYPE_P (type))
5948 {
5949 /* All other aggregate types are passed in an integer register
5950 in a mode corresponding to the size of the type. */
5951 HOST_WIDE_INT bytes = int_size_in_bytes (type);
5952
5953 if (bytes > 32)
5954 abort (); /* shouldn't get here */
5955
5956 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
5957
5958 /* ??? We probably should have made the same ABI change in
5959 3.4.0 as the one we made for unions. The latter was
5960 required by the SCD though, while the former is not
5961 specified, so we favored compatibility and efficiency.
5962
5963 Now we're stuck for aggregates larger than 16 bytes,
5964 because OImode vanished in the meantime. Let's not
5965 try to be unduly clever, and simply follow the ABI
5966 for unions in that case. */
5967 if (mode == BLKmode)
5968 return function_arg_union_value (bytes, mode, regbase);
5969 }
5970 else if (GET_MODE_CLASS (mode) == MODE_INT
5971 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
5972 mode = word_mode;
5973 }
5974
5975 if (TARGET_FPU && (FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode)))
5976 regno = SPARC_FP_ARG_FIRST;
5977 else
5978 regno = regbase;
5979
5980 return gen_rtx_REG (mode, regno);
5981 }
5982
5983 /* Do what is necessary for `va_start'. We look at the current function
5984 to determine if stdarg or varargs is used and return the address of
5985 the first unnamed parameter. */
5986
5987 static rtx
5988 sparc_builtin_saveregs (void)
5989 {
5990 int first_reg = current_function_args_info.words;
5991 rtx address;
5992 int regno;
5993
5994 for (regno = first_reg; regno < SPARC_INT_ARG_MAX; regno++)
5995 emit_move_insn (gen_rtx_MEM (word_mode,
5996 gen_rtx_PLUS (Pmode,
5997 frame_pointer_rtx,
5998 GEN_INT (FIRST_PARM_OFFSET (0)
5999 + (UNITS_PER_WORD
6000 * regno)))),
6001 gen_rtx_REG (word_mode,
6002 SPARC_INCOMING_INT_ARG_FIRST + regno));
6003
6004 address = gen_rtx_PLUS (Pmode,
6005 frame_pointer_rtx,
6006 GEN_INT (FIRST_PARM_OFFSET (0)
6007 + UNITS_PER_WORD * first_reg));
6008
6009 return address;
6010 }
6011
6012 /* Implement `va_start' for stdarg. */
6013
6014 void
6015 sparc_va_start (tree valist, rtx nextarg)
6016 {
6017 nextarg = expand_builtin_saveregs ();
6018 std_expand_builtin_va_start (valist, nextarg);
6019 }
6020
6021 /* Implement `va_arg' for stdarg. */
6022
6023 static tree
6024 sparc_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
6025 {
6026 HOST_WIDE_INT size, rsize, align;
6027 tree addr, incr;
6028 bool indirect;
6029 tree ptrtype = build_pointer_type (type);
6030
6031 if (pass_by_reference (NULL, TYPE_MODE (type), type, 0))
6032 {
6033 indirect = true;
6034 size = rsize = UNITS_PER_WORD;
6035 align = 0;
6036 }
6037 else
6038 {
6039 indirect = false;
6040 size = int_size_in_bytes (type);
6041 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
6042 align = 0;
6043
6044 if (TARGET_ARCH64)
6045 {
6046 /* For SPARC64, objects requiring 16-byte alignment get it. */
6047 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
6048 align = 2 * UNITS_PER_WORD;
6049
6050 /* SPARC-V9 ABI states that structures up to 16 bytes in size
6051 are given whole slots as needed. */
6052 if (AGGREGATE_TYPE_P (type))
6053 {
6054 if (size == 0)
6055 size = rsize = UNITS_PER_WORD;
6056 else
6057 size = rsize;
6058 }
6059 }
6060 }
6061
6062 incr = valist;
6063 if (align)
6064 {
6065 incr = fold (build2 (PLUS_EXPR, ptr_type_node, incr,
6066 ssize_int (align - 1)));
6067 incr = fold (build2 (BIT_AND_EXPR, ptr_type_node, incr,
6068 ssize_int (-align)));
6069 }
6070
6071 gimplify_expr (&incr, pre_p, post_p, is_gimple_val, fb_rvalue);
6072 addr = incr;
6073
6074 if (BYTES_BIG_ENDIAN && size < rsize)
6075 addr = fold (build2 (PLUS_EXPR, ptr_type_node, incr,
6076 ssize_int (rsize - size)));
6077
6078 if (indirect)
6079 {
6080 addr = fold_convert (build_pointer_type (ptrtype), addr);
6081 addr = build_fold_indirect_ref (addr);
6082 }
6083 /* If the address isn't aligned properly for the type,
6084 we may need to copy to a temporary.
6085 FIXME: This is inefficient. Usually we can do this
6086 in registers. */
6087 else if (align == 0
6088 && TYPE_ALIGN (type) > BITS_PER_WORD)
6089 {
6090 tree tmp = create_tmp_var (type, "va_arg_tmp");
6091 tree dest_addr = build_fold_addr_expr (tmp);
6092
6093 tree copy = build_function_call_expr
6094 (implicit_built_in_decls[BUILT_IN_MEMCPY],
6095 tree_cons (NULL_TREE, dest_addr,
6096 tree_cons (NULL_TREE, addr,
6097 tree_cons (NULL_TREE, size_int (rsize),
6098 NULL_TREE))));
6099
6100 gimplify_and_add (copy, pre_p);
6101 addr = dest_addr;
6102 }
6103 else
6104 addr = fold_convert (ptrtype, addr);
6105
6106 incr = fold (build2 (PLUS_EXPR, ptr_type_node, incr, ssize_int (rsize)));
6107 incr = build2 (MODIFY_EXPR, ptr_type_node, valist, incr);
6108 gimplify_and_add (incr, post_p);
6109
6110 return build_fold_indirect_ref (addr);
6111 }
6112 \f
6113 /* Return the string to output an unconditional branch to LABEL, which is
6114 the operand number of the label.
6115
6116 DEST is the destination insn (i.e. the label), INSN is the source. */
6117
6118 const char *
6119 output_ubranch (rtx dest, int label, rtx insn)
6120 {
6121 static char string[64];
6122 bool noop = false;
6123 char *p;
6124
6125 /* TurboSPARC is reported to have problems with
6126 with
6127 foo: b,a foo
6128 i.e. an empty loop with the annul bit set. The workaround is to use
6129 foo: b foo; nop
6130 instead. */
6131
6132 if (! TARGET_V9 && flag_delayed_branch
6133 && (INSN_ADDRESSES (INSN_UID (dest))
6134 == INSN_ADDRESSES (INSN_UID (insn))))
6135 {
6136 strcpy (string, "b\t");
6137 noop = true;
6138 }
6139 else
6140 {
6141 bool v9_form = false;
6142
6143 if (TARGET_V9 && INSN_ADDRESSES_SET_P ())
6144 {
6145 int delta = (INSN_ADDRESSES (INSN_UID (dest))
6146 - INSN_ADDRESSES (INSN_UID (insn)));
6147 /* Leave some instructions for "slop". */
6148 if (delta >= -260000 && delta < 260000)
6149 v9_form = true;
6150 }
6151
6152 if (v9_form)
6153 strcpy (string, "ba%*,pt\t%%xcc, ");
6154 else
6155 strcpy (string, "b%*\t");
6156 }
6157
6158 p = strchr (string, '\0');
6159 *p++ = '%';
6160 *p++ = 'l';
6161 *p++ = '0' + label;
6162 *p++ = '%';
6163 if (noop)
6164 *p++ = '#';
6165 else
6166 *p++ = '(';
6167 *p = '\0';
6168
6169 return string;
6170 }
6171
6172 /* Return the string to output a conditional branch to LABEL, which is
6173 the operand number of the label. OP is the conditional expression.
6174 XEXP (OP, 0) is assumed to be a condition code register (integer or
6175 floating point) and its mode specifies what kind of comparison we made.
6176
6177 DEST is the destination insn (i.e. the label), INSN is the source.
6178
6179 REVERSED is nonzero if we should reverse the sense of the comparison.
6180
6181 ANNUL is nonzero if we should generate an annulling branch.
6182
6183 NOOP is nonzero if we have to follow this branch by a noop. */
6184
6185 const char *
6186 output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
6187 int noop, rtx insn)
6188 {
6189 static char string[64];
6190 enum rtx_code code = GET_CODE (op);
6191 rtx cc_reg = XEXP (op, 0);
6192 enum machine_mode mode = GET_MODE (cc_reg);
6193 const char *labelno, *branch;
6194 int spaces = 8, far;
6195 char *p;
6196
6197 /* v9 branches are limited to +-1MB. If it is too far away,
6198 change
6199
6200 bne,pt %xcc, .LC30
6201
6202 to
6203
6204 be,pn %xcc, .+12
6205 nop
6206 ba .LC30
6207
6208 and
6209
6210 fbne,a,pn %fcc2, .LC29
6211
6212 to
6213
6214 fbe,pt %fcc2, .+16
6215 nop
6216 ba .LC29 */
6217
6218 far = TARGET_V9 && (get_attr_length (insn) >= 3);
6219 if (reversed ^ far)
6220 {
6221 /* Reversal of FP compares takes care -- an ordered compare
6222 becomes an unordered compare and vice versa. */
6223 if (mode == CCFPmode || mode == CCFPEmode)
6224 code = reverse_condition_maybe_unordered (code);
6225 else
6226 code = reverse_condition (code);
6227 }
6228
6229 /* Start by writing the branch condition. */
6230 if (mode == CCFPmode || mode == CCFPEmode)
6231 {
6232 switch (code)
6233 {
6234 case NE:
6235 branch = "fbne";
6236 break;
6237 case EQ:
6238 branch = "fbe";
6239 break;
6240 case GE:
6241 branch = "fbge";
6242 break;
6243 case GT:
6244 branch = "fbg";
6245 break;
6246 case LE:
6247 branch = "fble";
6248 break;
6249 case LT:
6250 branch = "fbl";
6251 break;
6252 case UNORDERED:
6253 branch = "fbu";
6254 break;
6255 case ORDERED:
6256 branch = "fbo";
6257 break;
6258 case UNGT:
6259 branch = "fbug";
6260 break;
6261 case UNLT:
6262 branch = "fbul";
6263 break;
6264 case UNEQ:
6265 branch = "fbue";
6266 break;
6267 case UNGE:
6268 branch = "fbuge";
6269 break;
6270 case UNLE:
6271 branch = "fbule";
6272 break;
6273 case LTGT:
6274 branch = "fblg";
6275 break;
6276
6277 default:
6278 abort ();
6279 }
6280
6281 /* ??? !v9: FP branches cannot be preceded by another floating point
6282 insn. Because there is currently no concept of pre-delay slots,
6283 we can fix this only by always emitting a nop before a floating
6284 point branch. */
6285
6286 string[0] = '\0';
6287 if (! TARGET_V9)
6288 strcpy (string, "nop\n\t");
6289 strcat (string, branch);
6290 }
6291 else
6292 {
6293 switch (code)
6294 {
6295 case NE:
6296 branch = "bne";
6297 break;
6298 case EQ:
6299 branch = "be";
6300 break;
6301 case GE:
6302 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
6303 branch = "bpos";
6304 else
6305 branch = "bge";
6306 break;
6307 case GT:
6308 branch = "bg";
6309 break;
6310 case LE:
6311 branch = "ble";
6312 break;
6313 case LT:
6314 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
6315 branch = "bneg";
6316 else
6317 branch = "bl";
6318 break;
6319 case GEU:
6320 branch = "bgeu";
6321 break;
6322 case GTU:
6323 branch = "bgu";
6324 break;
6325 case LEU:
6326 branch = "bleu";
6327 break;
6328 case LTU:
6329 branch = "blu";
6330 break;
6331
6332 default:
6333 abort ();
6334 }
6335 strcpy (string, branch);
6336 }
6337 spaces -= strlen (branch);
6338 p = strchr (string, '\0');
6339
6340 /* Now add the annulling, the label, and a possible noop. */
6341 if (annul && ! far)
6342 {
6343 strcpy (p, ",a");
6344 p += 2;
6345 spaces -= 2;
6346 }
6347
6348 if (TARGET_V9)
6349 {
6350 rtx note;
6351 int v8 = 0;
6352
6353 if (! far && insn && INSN_ADDRESSES_SET_P ())
6354 {
6355 int delta = (INSN_ADDRESSES (INSN_UID (dest))
6356 - INSN_ADDRESSES (INSN_UID (insn)));
6357 /* Leave some instructions for "slop". */
6358 if (delta < -260000 || delta >= 260000)
6359 v8 = 1;
6360 }
6361
6362 if (mode == CCFPmode || mode == CCFPEmode)
6363 {
6364 static char v9_fcc_labelno[] = "%%fccX, ";
6365 /* Set the char indicating the number of the fcc reg to use. */
6366 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
6367 labelno = v9_fcc_labelno;
6368 if (v8)
6369 {
6370 if (REGNO (cc_reg) == SPARC_FCC_REG)
6371 labelno = "";
6372 else
6373 abort ();
6374 }
6375 }
6376 else if (mode == CCXmode || mode == CCX_NOOVmode)
6377 {
6378 labelno = "%%xcc, ";
6379 if (v8)
6380 abort ();
6381 }
6382 else
6383 {
6384 labelno = "%%icc, ";
6385 if (v8)
6386 labelno = "";
6387 }
6388
6389 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6390 {
6391 strcpy (p,
6392 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6393 ? ",pt" : ",pn");
6394 p += 3;
6395 spaces -= 3;
6396 }
6397 }
6398 else
6399 labelno = "";
6400
6401 if (spaces > 0)
6402 *p++ = '\t';
6403 else
6404 *p++ = ' ';
6405 strcpy (p, labelno);
6406 p = strchr (p, '\0');
6407 if (far)
6408 {
6409 strcpy (p, ".+12\n\t nop\n\tb\t");
6410 if (annul || noop)
6411 p[3] = '6';
6412 p += 14;
6413 }
6414 *p++ = '%';
6415 *p++ = 'l';
6416 /* Set the char indicating the number of the operand containing the
6417 label_ref. */
6418 *p++ = label + '0';
6419 *p = '\0';
6420 if (noop)
6421 strcpy (p, "\n\t nop");
6422
6423 return string;
6424 }
6425
6426 /* Emit a library call comparison between floating point X and Y.
6427 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
6428 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
6429 values as arguments instead of the TFmode registers themselves,
6430 that's why we cannot call emit_float_lib_cmp. */
6431 void
6432 sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison)
6433 {
6434 const char *qpfunc;
6435 rtx slot0, slot1, result, tem, tem2;
6436 enum machine_mode mode;
6437
6438 switch (comparison)
6439 {
6440 case EQ:
6441 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq";
6442 break;
6443
6444 case NE:
6445 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne";
6446 break;
6447
6448 case GT:
6449 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt";
6450 break;
6451
6452 case GE:
6453 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge";
6454 break;
6455
6456 case LT:
6457 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt";
6458 break;
6459
6460 case LE:
6461 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle";
6462 break;
6463
6464 case ORDERED:
6465 case UNORDERED:
6466 case UNGT:
6467 case UNLT:
6468 case UNEQ:
6469 case UNGE:
6470 case UNLE:
6471 case LTGT:
6472 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp";
6473 break;
6474
6475 default:
6476 abort();
6477 break;
6478 }
6479
6480 if (TARGET_ARCH64)
6481 {
6482 if (GET_CODE (x) != MEM)
6483 {
6484 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6485 emit_insn (gen_rtx_SET (VOIDmode, slot0, x));
6486 }
6487 else
6488 slot0 = x;
6489
6490 if (GET_CODE (y) != MEM)
6491 {
6492 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6493 emit_insn (gen_rtx_SET (VOIDmode, slot1, y));
6494 }
6495 else
6496 slot1 = y;
6497
6498 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6499 DImode, 2,
6500 XEXP (slot0, 0), Pmode,
6501 XEXP (slot1, 0), Pmode);
6502
6503 mode = DImode;
6504 }
6505 else
6506 {
6507 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6508 SImode, 2,
6509 x, TFmode, y, TFmode);
6510
6511 mode = SImode;
6512 }
6513
6514
6515 /* Immediately move the result of the libcall into a pseudo
6516 register so reload doesn't clobber the value if it needs
6517 the return register for a spill reg. */
6518 result = gen_reg_rtx (mode);
6519 emit_move_insn (result, hard_libcall_value (mode));
6520
6521 switch (comparison)
6522 {
6523 default:
6524 emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0);
6525 break;
6526 case ORDERED:
6527 case UNORDERED:
6528 emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE,
6529 NULL_RTX, mode, 0);
6530 break;
6531 case UNGT:
6532 case UNGE:
6533 emit_cmp_insn (result, const1_rtx,
6534 comparison == UNGT ? GT : NE, NULL_RTX, mode, 0);
6535 break;
6536 case UNLE:
6537 emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0);
6538 break;
6539 case UNLT:
6540 tem = gen_reg_rtx (mode);
6541 if (TARGET_ARCH32)
6542 emit_insn (gen_andsi3 (tem, result, const1_rtx));
6543 else
6544 emit_insn (gen_anddi3 (tem, result, const1_rtx));
6545 emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0);
6546 break;
6547 case UNEQ:
6548 case LTGT:
6549 tem = gen_reg_rtx (mode);
6550 if (TARGET_ARCH32)
6551 emit_insn (gen_addsi3 (tem, result, const1_rtx));
6552 else
6553 emit_insn (gen_adddi3 (tem, result, const1_rtx));
6554 tem2 = gen_reg_rtx (mode);
6555 if (TARGET_ARCH32)
6556 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
6557 else
6558 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
6559 emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE,
6560 NULL_RTX, mode, 0);
6561 break;
6562 }
6563 }
6564
6565 /* Generate an unsigned DImode to FP conversion. This is the same code
6566 optabs would emit if we didn't have TFmode patterns. */
6567
6568 void
6569 sparc_emit_floatunsdi (rtx *operands, enum machine_mode mode)
6570 {
6571 rtx neglab, donelab, i0, i1, f0, in, out;
6572
6573 out = operands[0];
6574 in = force_reg (DImode, operands[1]);
6575 neglab = gen_label_rtx ();
6576 donelab = gen_label_rtx ();
6577 i0 = gen_reg_rtx (DImode);
6578 i1 = gen_reg_rtx (DImode);
6579 f0 = gen_reg_rtx (mode);
6580
6581 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
6582
6583 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
6584 emit_jump_insn (gen_jump (donelab));
6585 emit_barrier ();
6586
6587 emit_label (neglab);
6588
6589 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
6590 emit_insn (gen_anddi3 (i1, in, const1_rtx));
6591 emit_insn (gen_iordi3 (i0, i0, i1));
6592 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
6593 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
6594
6595 emit_label (donelab);
6596 }
6597
6598 /* Generate an FP to unsigned DImode conversion. This is the same code
6599 optabs would emit if we didn't have TFmode patterns. */
6600
6601 void
6602 sparc_emit_fixunsdi (rtx *operands, enum machine_mode mode)
6603 {
6604 rtx neglab, donelab, i0, i1, f0, in, out, limit;
6605
6606 out = operands[0];
6607 in = force_reg (mode, operands[1]);
6608 neglab = gen_label_rtx ();
6609 donelab = gen_label_rtx ();
6610 i0 = gen_reg_rtx (DImode);
6611 i1 = gen_reg_rtx (DImode);
6612 limit = gen_reg_rtx (mode);
6613 f0 = gen_reg_rtx (mode);
6614
6615 emit_move_insn (limit,
6616 CONST_DOUBLE_FROM_REAL_VALUE (
6617 REAL_VALUE_ATOF ("9223372036854775808.0", mode), mode));
6618 emit_cmp_and_jump_insns (in, limit, GE, NULL_RTX, mode, 0, neglab);
6619
6620 emit_insn (gen_rtx_SET (VOIDmode,
6621 out,
6622 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, in))));
6623 emit_jump_insn (gen_jump (donelab));
6624 emit_barrier ();
6625
6626 emit_label (neglab);
6627
6628 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_MINUS (mode, in, limit)));
6629 emit_insn (gen_rtx_SET (VOIDmode,
6630 i0,
6631 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, f0))));
6632 emit_insn (gen_movdi (i1, const1_rtx));
6633 emit_insn (gen_ashldi3 (i1, i1, GEN_INT (63)));
6634 emit_insn (gen_xordi3 (out, i0, i1));
6635
6636 emit_label (donelab);
6637 }
6638
6639 /* Return the string to output a conditional branch to LABEL, testing
6640 register REG. LABEL is the operand number of the label; REG is the
6641 operand number of the reg. OP is the conditional expression. The mode
6642 of REG says what kind of comparison we made.
6643
6644 DEST is the destination insn (i.e. the label), INSN is the source.
6645
6646 REVERSED is nonzero if we should reverse the sense of the comparison.
6647
6648 ANNUL is nonzero if we should generate an annulling branch.
6649
6650 NOOP is nonzero if we have to follow this branch by a noop. */
6651
6652 const char *
6653 output_v9branch (rtx op, rtx dest, int reg, int label, int reversed,
6654 int annul, int noop, rtx insn)
6655 {
6656 static char string[64];
6657 enum rtx_code code = GET_CODE (op);
6658 enum machine_mode mode = GET_MODE (XEXP (op, 0));
6659 rtx note;
6660 int far;
6661 char *p;
6662
6663 /* branch on register are limited to +-128KB. If it is too far away,
6664 change
6665
6666 brnz,pt %g1, .LC30
6667
6668 to
6669
6670 brz,pn %g1, .+12
6671 nop
6672 ba,pt %xcc, .LC30
6673
6674 and
6675
6676 brgez,a,pn %o1, .LC29
6677
6678 to
6679
6680 brlz,pt %o1, .+16
6681 nop
6682 ba,pt %xcc, .LC29 */
6683
6684 far = get_attr_length (insn) >= 3;
6685
6686 /* If not floating-point or if EQ or NE, we can just reverse the code. */
6687 if (reversed ^ far)
6688 code = reverse_condition (code);
6689
6690 /* Only 64 bit versions of these instructions exist. */
6691 if (mode != DImode)
6692 abort ();
6693
6694 /* Start by writing the branch condition. */
6695
6696 switch (code)
6697 {
6698 case NE:
6699 strcpy (string, "brnz");
6700 break;
6701
6702 case EQ:
6703 strcpy (string, "brz");
6704 break;
6705
6706 case GE:
6707 strcpy (string, "brgez");
6708 break;
6709
6710 case LT:
6711 strcpy (string, "brlz");
6712 break;
6713
6714 case LE:
6715 strcpy (string, "brlez");
6716 break;
6717
6718 case GT:
6719 strcpy (string, "brgz");
6720 break;
6721
6722 default:
6723 abort ();
6724 }
6725
6726 p = strchr (string, '\0');
6727
6728 /* Now add the annulling, reg, label, and nop. */
6729 if (annul && ! far)
6730 {
6731 strcpy (p, ",a");
6732 p += 2;
6733 }
6734
6735 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6736 {
6737 strcpy (p,
6738 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6739 ? ",pt" : ",pn");
6740 p += 3;
6741 }
6742
6743 *p = p < string + 8 ? '\t' : ' ';
6744 p++;
6745 *p++ = '%';
6746 *p++ = '0' + reg;
6747 *p++ = ',';
6748 *p++ = ' ';
6749 if (far)
6750 {
6751 int veryfar = 1, delta;
6752
6753 if (INSN_ADDRESSES_SET_P ())
6754 {
6755 delta = (INSN_ADDRESSES (INSN_UID (dest))
6756 - INSN_ADDRESSES (INSN_UID (insn)));
6757 /* Leave some instructions for "slop". */
6758 if (delta >= -260000 && delta < 260000)
6759 veryfar = 0;
6760 }
6761
6762 strcpy (p, ".+12\n\t nop\n\t");
6763 if (annul || noop)
6764 p[3] = '6';
6765 p += 12;
6766 if (veryfar)
6767 {
6768 strcpy (p, "b\t");
6769 p += 2;
6770 }
6771 else
6772 {
6773 strcpy (p, "ba,pt\t%%xcc, ");
6774 p += 13;
6775 }
6776 }
6777 *p++ = '%';
6778 *p++ = 'l';
6779 *p++ = '0' + label;
6780 *p = '\0';
6781
6782 if (noop)
6783 strcpy (p, "\n\t nop");
6784
6785 return string;
6786 }
6787
6788 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
6789 Such instructions cannot be used in the delay slot of return insn on v9.
6790 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
6791 */
6792
6793 static int
6794 epilogue_renumber (register rtx *where, int test)
6795 {
6796 register const char *fmt;
6797 register int i;
6798 register enum rtx_code code;
6799
6800 if (*where == 0)
6801 return 0;
6802
6803 code = GET_CODE (*where);
6804
6805 switch (code)
6806 {
6807 case REG:
6808 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
6809 return 1;
6810 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
6811 *where = gen_rtx_REG (GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
6812 case SCRATCH:
6813 case CC0:
6814 case PC:
6815 case CONST_INT:
6816 case CONST_DOUBLE:
6817 return 0;
6818
6819 /* Do not replace the frame pointer with the stack pointer because
6820 it can cause the delayed instruction to load below the stack.
6821 This occurs when instructions like:
6822
6823 (set (reg/i:SI 24 %i0)
6824 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
6825 (const_int -20 [0xffffffec])) 0))
6826
6827 are in the return delayed slot. */
6828 case PLUS:
6829 if (GET_CODE (XEXP (*where, 0)) == REG
6830 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
6831 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
6832 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
6833 return 1;
6834 break;
6835
6836 case MEM:
6837 if (SPARC_STACK_BIAS
6838 && GET_CODE (XEXP (*where, 0)) == REG
6839 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
6840 return 1;
6841 break;
6842
6843 default:
6844 break;
6845 }
6846
6847 fmt = GET_RTX_FORMAT (code);
6848
6849 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6850 {
6851 if (fmt[i] == 'E')
6852 {
6853 register int j;
6854 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
6855 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
6856 return 1;
6857 }
6858 else if (fmt[i] == 'e'
6859 && epilogue_renumber (&(XEXP (*where, i)), test))
6860 return 1;
6861 }
6862 return 0;
6863 }
6864 \f
6865 /* Leaf functions and non-leaf functions have different needs. */
6866
6867 static const int
6868 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
6869
6870 static const int
6871 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
6872
6873 static const int *const reg_alloc_orders[] = {
6874 reg_leaf_alloc_order,
6875 reg_nonleaf_alloc_order};
6876
6877 void
6878 order_regs_for_local_alloc (void)
6879 {
6880 static int last_order_nonleaf = 1;
6881
6882 if (regs_ever_live[15] != last_order_nonleaf)
6883 {
6884 last_order_nonleaf = !last_order_nonleaf;
6885 memcpy ((char *) reg_alloc_order,
6886 (const char *) reg_alloc_orders[last_order_nonleaf],
6887 FIRST_PSEUDO_REGISTER * sizeof (int));
6888 }
6889 }
6890 \f
6891 /* Return 1 if REG and MEM are legitimate enough to allow the various
6892 mem<-->reg splits to be run. */
6893
6894 int
6895 sparc_splitdi_legitimate (rtx reg, rtx mem)
6896 {
6897 /* Punt if we are here by mistake. */
6898 if (! reload_completed)
6899 abort ();
6900
6901 /* We must have an offsettable memory reference. */
6902 if (! offsettable_memref_p (mem))
6903 return 0;
6904
6905 /* If we have legitimate args for ldd/std, we do not want
6906 the split to happen. */
6907 if ((REGNO (reg) % 2) == 0
6908 && mem_min_alignment (mem, 8))
6909 return 0;
6910
6911 /* Success. */
6912 return 1;
6913 }
6914
6915 /* Return 1 if x and y are some kind of REG and they refer to
6916 different hard registers. This test is guaranteed to be
6917 run after reload. */
6918
6919 int
6920 sparc_absnegfloat_split_legitimate (rtx x, rtx y)
6921 {
6922 if (GET_CODE (x) != REG)
6923 return 0;
6924 if (GET_CODE (y) != REG)
6925 return 0;
6926 if (REGNO (x) == REGNO (y))
6927 return 0;
6928 return 1;
6929 }
6930
6931 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6932 This makes them candidates for using ldd and std insns.
6933
6934 Note reg1 and reg2 *must* be hard registers. */
6935
6936 int
6937 registers_ok_for_ldd_peep (rtx reg1, rtx reg2)
6938 {
6939 /* We might have been passed a SUBREG. */
6940 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
6941 return 0;
6942
6943 if (REGNO (reg1) % 2 != 0)
6944 return 0;
6945
6946 /* Integer ldd is deprecated in SPARC V9 */
6947 if (TARGET_V9 && REGNO (reg1) < 32)
6948 return 0;
6949
6950 return (REGNO (reg1) == REGNO (reg2) - 1);
6951 }
6952
6953 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
6954 an ldd or std insn.
6955
6956 This can only happen when addr1 and addr2, the addresses in mem1
6957 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
6958 addr1 must also be aligned on a 64-bit boundary.
6959
6960 Also iff dependent_reg_rtx is not null it should not be used to
6961 compute the address for mem1, i.e. we cannot optimize a sequence
6962 like:
6963 ld [%o0], %o0
6964 ld [%o0 + 4], %o1
6965 to
6966 ldd [%o0], %o0
6967 nor:
6968 ld [%g3 + 4], %g3
6969 ld [%g3], %g2
6970 to
6971 ldd [%g3], %g2
6972
6973 But, note that the transformation from:
6974 ld [%g2 + 4], %g3
6975 ld [%g2], %g2
6976 to
6977 ldd [%g2], %g2
6978 is perfectly fine. Thus, the peephole2 patterns always pass us
6979 the destination register of the first load, never the second one.
6980
6981 For stores we don't have a similar problem, so dependent_reg_rtx is
6982 NULL_RTX. */
6983
6984 int
6985 mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
6986 {
6987 rtx addr1, addr2;
6988 unsigned int reg1;
6989 HOST_WIDE_INT offset1;
6990
6991 /* The mems cannot be volatile. */
6992 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
6993 return 0;
6994
6995 /* MEM1 should be aligned on a 64-bit boundary. */
6996 if (MEM_ALIGN (mem1) < 64)
6997 return 0;
6998
6999 addr1 = XEXP (mem1, 0);
7000 addr2 = XEXP (mem2, 0);
7001
7002 /* Extract a register number and offset (if used) from the first addr. */
7003 if (GET_CODE (addr1) == PLUS)
7004 {
7005 /* If not a REG, return zero. */
7006 if (GET_CODE (XEXP (addr1, 0)) != REG)
7007 return 0;
7008 else
7009 {
7010 reg1 = REGNO (XEXP (addr1, 0));
7011 /* The offset must be constant! */
7012 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
7013 return 0;
7014 offset1 = INTVAL (XEXP (addr1, 1));
7015 }
7016 }
7017 else if (GET_CODE (addr1) != REG)
7018 return 0;
7019 else
7020 {
7021 reg1 = REGNO (addr1);
7022 /* This was a simple (mem (reg)) expression. Offset is 0. */
7023 offset1 = 0;
7024 }
7025
7026 /* Make sure the second address is a (mem (plus (reg) (const_int). */
7027 if (GET_CODE (addr2) != PLUS)
7028 return 0;
7029
7030 if (GET_CODE (XEXP (addr2, 0)) != REG
7031 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
7032 return 0;
7033
7034 if (reg1 != REGNO (XEXP (addr2, 0)))
7035 return 0;
7036
7037 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
7038 return 0;
7039
7040 /* The first offset must be evenly divisible by 8 to ensure the
7041 address is 64 bit aligned. */
7042 if (offset1 % 8 != 0)
7043 return 0;
7044
7045 /* The offset for the second addr must be 4 more than the first addr. */
7046 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
7047 return 0;
7048
7049 /* All the tests passed. addr1 and addr2 are valid for ldd and std
7050 instructions. */
7051 return 1;
7052 }
7053
7054 /* Return 1 if reg is a pseudo, or is the first register in
7055 a hard register pair. This makes it a candidate for use in
7056 ldd and std insns. */
7057
7058 int
7059 register_ok_for_ldd (rtx reg)
7060 {
7061 /* We might have been passed a SUBREG. */
7062 if (GET_CODE (reg) != REG)
7063 return 0;
7064
7065 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
7066 return (REGNO (reg) % 2 == 0);
7067 else
7068 return 1;
7069 }
7070 \f
7071 /* Print operand X (an rtx) in assembler syntax to file FILE.
7072 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
7073 For `%' followed by punctuation, CODE is the punctuation and X is null. */
7074
7075 void
7076 print_operand (FILE *file, rtx x, int code)
7077 {
7078 switch (code)
7079 {
7080 case '#':
7081 /* Output a 'nop' if there's nothing for the delay slot. */
7082 if (dbr_sequence_length () == 0)
7083 fputs ("\n\t nop", file);
7084 return;
7085 case '*':
7086 /* Output an annul flag if there's nothing for the delay slot and we
7087 are optimizing. This is always used with '(' below. */
7088 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
7089 this is a dbx bug. So, we only do this when optimizing. */
7090 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
7091 Always emit a nop in case the next instruction is a branch. */
7092 if (dbr_sequence_length () == 0
7093 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
7094 fputs (",a", file);
7095 return;
7096 case '(':
7097 /* Output a 'nop' if there's nothing for the delay slot and we are
7098 not optimizing. This is always used with '*' above. */
7099 if (dbr_sequence_length () == 0
7100 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
7101 fputs ("\n\t nop", file);
7102 return;
7103 case '_':
7104 /* Output the Embedded Medium/Anywhere code model base register. */
7105 fputs (EMBMEDANY_BASE_REG, file);
7106 return;
7107 case '@':
7108 /* Print out what we are using as the frame pointer. This might
7109 be %fp, or might be %sp+offset. */
7110 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
7111 fprintf (file, "%s+"HOST_WIDE_INT_PRINT_DEC,
7112 reg_names[REGNO (frame_base_reg)], frame_base_offset);
7113 return;
7114 case '&':
7115 /* Print some local dynamic TLS name. */
7116 assemble_name (file, get_some_local_dynamic_name ());
7117 return;
7118 case 'Y':
7119 /* Adjust the operand to take into account a RESTORE operation. */
7120 if (GET_CODE (x) == CONST_INT)
7121 break;
7122 else if (GET_CODE (x) != REG)
7123 output_operand_lossage ("invalid %%Y operand");
7124 else if (REGNO (x) < 8)
7125 fputs (reg_names[REGNO (x)], file);
7126 else if (REGNO (x) >= 24 && REGNO (x) < 32)
7127 fputs (reg_names[REGNO (x)-16], file);
7128 else
7129 output_operand_lossage ("invalid %%Y operand");
7130 return;
7131 case 'L':
7132 /* Print out the low order register name of a register pair. */
7133 if (WORDS_BIG_ENDIAN)
7134 fputs (reg_names[REGNO (x)+1], file);
7135 else
7136 fputs (reg_names[REGNO (x)], file);
7137 return;
7138 case 'H':
7139 /* Print out the high order register name of a register pair. */
7140 if (WORDS_BIG_ENDIAN)
7141 fputs (reg_names[REGNO (x)], file);
7142 else
7143 fputs (reg_names[REGNO (x)+1], file);
7144 return;
7145 case 'R':
7146 /* Print out the second register name of a register pair or quad.
7147 I.e., R (%o0) => %o1. */
7148 fputs (reg_names[REGNO (x)+1], file);
7149 return;
7150 case 'S':
7151 /* Print out the third register name of a register quad.
7152 I.e., S (%o0) => %o2. */
7153 fputs (reg_names[REGNO (x)+2], file);
7154 return;
7155 case 'T':
7156 /* Print out the fourth register name of a register quad.
7157 I.e., T (%o0) => %o3. */
7158 fputs (reg_names[REGNO (x)+3], file);
7159 return;
7160 case 'x':
7161 /* Print a condition code register. */
7162 if (REGNO (x) == SPARC_ICC_REG)
7163 {
7164 /* We don't handle CC[X]_NOOVmode because they're not supposed
7165 to occur here. */
7166 if (GET_MODE (x) == CCmode)
7167 fputs ("%icc", file);
7168 else if (GET_MODE (x) == CCXmode)
7169 fputs ("%xcc", file);
7170 else
7171 abort ();
7172 }
7173 else
7174 /* %fccN register */
7175 fputs (reg_names[REGNO (x)], file);
7176 return;
7177 case 'm':
7178 /* Print the operand's address only. */
7179 output_address (XEXP (x, 0));
7180 return;
7181 case 'r':
7182 /* In this case we need a register. Use %g0 if the
7183 operand is const0_rtx. */
7184 if (x == const0_rtx
7185 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
7186 {
7187 fputs ("%g0", file);
7188 return;
7189 }
7190 else
7191 break;
7192
7193 case 'A':
7194 switch (GET_CODE (x))
7195 {
7196 case IOR: fputs ("or", file); break;
7197 case AND: fputs ("and", file); break;
7198 case XOR: fputs ("xor", file); break;
7199 default: output_operand_lossage ("invalid %%A operand");
7200 }
7201 return;
7202
7203 case 'B':
7204 switch (GET_CODE (x))
7205 {
7206 case IOR: fputs ("orn", file); break;
7207 case AND: fputs ("andn", file); break;
7208 case XOR: fputs ("xnor", file); break;
7209 default: output_operand_lossage ("invalid %%B operand");
7210 }
7211 return;
7212
7213 /* These are used by the conditional move instructions. */
7214 case 'c' :
7215 case 'C':
7216 {
7217 enum rtx_code rc = GET_CODE (x);
7218
7219 if (code == 'c')
7220 {
7221 enum machine_mode mode = GET_MODE (XEXP (x, 0));
7222 if (mode == CCFPmode || mode == CCFPEmode)
7223 rc = reverse_condition_maybe_unordered (GET_CODE (x));
7224 else
7225 rc = reverse_condition (GET_CODE (x));
7226 }
7227 switch (rc)
7228 {
7229 case NE: fputs ("ne", file); break;
7230 case EQ: fputs ("e", file); break;
7231 case GE: fputs ("ge", file); break;
7232 case GT: fputs ("g", file); break;
7233 case LE: fputs ("le", file); break;
7234 case LT: fputs ("l", file); break;
7235 case GEU: fputs ("geu", file); break;
7236 case GTU: fputs ("gu", file); break;
7237 case LEU: fputs ("leu", file); break;
7238 case LTU: fputs ("lu", file); break;
7239 case LTGT: fputs ("lg", file); break;
7240 case UNORDERED: fputs ("u", file); break;
7241 case ORDERED: fputs ("o", file); break;
7242 case UNLT: fputs ("ul", file); break;
7243 case UNLE: fputs ("ule", file); break;
7244 case UNGT: fputs ("ug", file); break;
7245 case UNGE: fputs ("uge", file); break;
7246 case UNEQ: fputs ("ue", file); break;
7247 default: output_operand_lossage (code == 'c'
7248 ? "invalid %%c operand"
7249 : "invalid %%C operand");
7250 }
7251 return;
7252 }
7253
7254 /* These are used by the movr instruction pattern. */
7255 case 'd':
7256 case 'D':
7257 {
7258 enum rtx_code rc = (code == 'd'
7259 ? reverse_condition (GET_CODE (x))
7260 : GET_CODE (x));
7261 switch (rc)
7262 {
7263 case NE: fputs ("ne", file); break;
7264 case EQ: fputs ("e", file); break;
7265 case GE: fputs ("gez", file); break;
7266 case LT: fputs ("lz", file); break;
7267 case LE: fputs ("lez", file); break;
7268 case GT: fputs ("gz", file); break;
7269 default: output_operand_lossage (code == 'd'
7270 ? "invalid %%d operand"
7271 : "invalid %%D operand");
7272 }
7273 return;
7274 }
7275
7276 case 'b':
7277 {
7278 /* Print a sign-extended character. */
7279 int i = trunc_int_for_mode (INTVAL (x), QImode);
7280 fprintf (file, "%d", i);
7281 return;
7282 }
7283
7284 case 'f':
7285 /* Operand must be a MEM; write its address. */
7286 if (GET_CODE (x) != MEM)
7287 output_operand_lossage ("invalid %%f operand");
7288 output_address (XEXP (x, 0));
7289 return;
7290
7291 case 's':
7292 {
7293 /* Print a sign-extended 32-bit value. */
7294 HOST_WIDE_INT i;
7295 if (GET_CODE(x) == CONST_INT)
7296 i = INTVAL (x);
7297 else if (GET_CODE(x) == CONST_DOUBLE)
7298 i = CONST_DOUBLE_LOW (x);
7299 else
7300 {
7301 output_operand_lossage ("invalid %%s operand");
7302 return;
7303 }
7304 i = trunc_int_for_mode (i, SImode);
7305 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i);
7306 return;
7307 }
7308
7309 case 0:
7310 /* Do nothing special. */
7311 break;
7312
7313 default:
7314 /* Undocumented flag. */
7315 output_operand_lossage ("invalid operand output code");
7316 }
7317
7318 if (GET_CODE (x) == REG)
7319 fputs (reg_names[REGNO (x)], file);
7320 else if (GET_CODE (x) == MEM)
7321 {
7322 fputc ('[', file);
7323 /* Poor Sun assembler doesn't understand absolute addressing. */
7324 if (CONSTANT_P (XEXP (x, 0)))
7325 fputs ("%g0+", file);
7326 output_address (XEXP (x, 0));
7327 fputc (']', file);
7328 }
7329 else if (GET_CODE (x) == HIGH)
7330 {
7331 fputs ("%hi(", file);
7332 output_addr_const (file, XEXP (x, 0));
7333 fputc (')', file);
7334 }
7335 else if (GET_CODE (x) == LO_SUM)
7336 {
7337 print_operand (file, XEXP (x, 0), 0);
7338 if (TARGET_CM_MEDMID)
7339 fputs ("+%l44(", file);
7340 else
7341 fputs ("+%lo(", file);
7342 output_addr_const (file, XEXP (x, 1));
7343 fputc (')', file);
7344 }
7345 else if (GET_CODE (x) == CONST_DOUBLE
7346 && (GET_MODE (x) == VOIDmode
7347 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
7348 {
7349 if (CONST_DOUBLE_HIGH (x) == 0)
7350 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
7351 else if (CONST_DOUBLE_HIGH (x) == -1
7352 && CONST_DOUBLE_LOW (x) < 0)
7353 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
7354 else
7355 output_operand_lossage ("long long constant not a valid immediate operand");
7356 }
7357 else if (GET_CODE (x) == CONST_DOUBLE)
7358 output_operand_lossage ("floating point constant not a valid immediate operand");
7359 else { output_addr_const (file, x); }
7360 }
7361 \f
7362 /* Target hook for assembling integer objects. The sparc version has
7363 special handling for aligned DI-mode objects. */
7364
7365 static bool
7366 sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
7367 {
7368 /* ??? We only output .xword's for symbols and only then in environments
7369 where the assembler can handle them. */
7370 if (aligned_p && size == 8
7371 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
7372 {
7373 if (TARGET_V9)
7374 {
7375 assemble_integer_with_op ("\t.xword\t", x);
7376 return true;
7377 }
7378 else
7379 {
7380 assemble_aligned_integer (4, const0_rtx);
7381 assemble_aligned_integer (4, x);
7382 return true;
7383 }
7384 }
7385 return default_assemble_integer (x, size, aligned_p);
7386 }
7387 \f
7388 /* Return the value of a code used in the .proc pseudo-op that says
7389 what kind of result this function returns. For non-C types, we pick
7390 the closest C type. */
7391
7392 #ifndef SHORT_TYPE_SIZE
7393 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
7394 #endif
7395
7396 #ifndef INT_TYPE_SIZE
7397 #define INT_TYPE_SIZE BITS_PER_WORD
7398 #endif
7399
7400 #ifndef LONG_TYPE_SIZE
7401 #define LONG_TYPE_SIZE BITS_PER_WORD
7402 #endif
7403
7404 #ifndef LONG_LONG_TYPE_SIZE
7405 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
7406 #endif
7407
7408 #ifndef FLOAT_TYPE_SIZE
7409 #define FLOAT_TYPE_SIZE BITS_PER_WORD
7410 #endif
7411
7412 #ifndef DOUBLE_TYPE_SIZE
7413 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7414 #endif
7415
7416 #ifndef LONG_DOUBLE_TYPE_SIZE
7417 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7418 #endif
7419
7420 unsigned long
7421 sparc_type_code (register tree type)
7422 {
7423 register unsigned long qualifiers = 0;
7424 register unsigned shift;
7425
7426 /* Only the first 30 bits of the qualifier are valid. We must refrain from
7427 setting more, since some assemblers will give an error for this. Also,
7428 we must be careful to avoid shifts of 32 bits or more to avoid getting
7429 unpredictable results. */
7430
7431 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
7432 {
7433 switch (TREE_CODE (type))
7434 {
7435 case ERROR_MARK:
7436 return qualifiers;
7437
7438 case ARRAY_TYPE:
7439 qualifiers |= (3 << shift);
7440 break;
7441
7442 case FUNCTION_TYPE:
7443 case METHOD_TYPE:
7444 qualifiers |= (2 << shift);
7445 break;
7446
7447 case POINTER_TYPE:
7448 case REFERENCE_TYPE:
7449 case OFFSET_TYPE:
7450 qualifiers |= (1 << shift);
7451 break;
7452
7453 case RECORD_TYPE:
7454 return (qualifiers | 8);
7455
7456 case UNION_TYPE:
7457 case QUAL_UNION_TYPE:
7458 return (qualifiers | 9);
7459
7460 case ENUMERAL_TYPE:
7461 return (qualifiers | 10);
7462
7463 case VOID_TYPE:
7464 return (qualifiers | 16);
7465
7466 case INTEGER_TYPE:
7467 /* If this is a range type, consider it to be the underlying
7468 type. */
7469 if (TREE_TYPE (type) != 0)
7470 break;
7471
7472 /* Carefully distinguish all the standard types of C,
7473 without messing up if the language is not C. We do this by
7474 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
7475 look at both the names and the above fields, but that's redundant.
7476 Any type whose size is between two C types will be considered
7477 to be the wider of the two types. Also, we do not have a
7478 special code to use for "long long", so anything wider than
7479 long is treated the same. Note that we can't distinguish
7480 between "int" and "long" in this code if they are the same
7481 size, but that's fine, since neither can the assembler. */
7482
7483 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
7484 return (qualifiers | (TYPE_UNSIGNED (type) ? 12 : 2));
7485
7486 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
7487 return (qualifiers | (TYPE_UNSIGNED (type) ? 13 : 3));
7488
7489 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
7490 return (qualifiers | (TYPE_UNSIGNED (type) ? 14 : 4));
7491
7492 else
7493 return (qualifiers | (TYPE_UNSIGNED (type) ? 15 : 5));
7494
7495 case REAL_TYPE:
7496 /* If this is a range type, consider it to be the underlying
7497 type. */
7498 if (TREE_TYPE (type) != 0)
7499 break;
7500
7501 /* Carefully distinguish all the standard types of C,
7502 without messing up if the language is not C. */
7503
7504 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
7505 return (qualifiers | 6);
7506
7507 else
7508 return (qualifiers | 7);
7509
7510 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
7511 /* ??? We need to distinguish between double and float complex types,
7512 but I don't know how yet because I can't reach this code from
7513 existing front-ends. */
7514 return (qualifiers | 7); /* Who knows? */
7515
7516 case VECTOR_TYPE:
7517 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
7518 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
7519 case FILE_TYPE: /* GNU Pascal FILE type. */
7520 case SET_TYPE: /* GNU Pascal SET type. */
7521 case LANG_TYPE: /* ? */
7522 return qualifiers;
7523
7524 default:
7525 abort (); /* Not a type! */
7526 }
7527 }
7528
7529 return qualifiers;
7530 }
7531 \f
7532 /* Nested function support. */
7533
7534 /* Emit RTL insns to initialize the variable parts of a trampoline.
7535 FNADDR is an RTX for the address of the function's pure code.
7536 CXT is an RTX for the static chain value for the function.
7537
7538 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
7539 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
7540 (to store insns). This is a bit excessive. Perhaps a different
7541 mechanism would be better here.
7542
7543 Emit enough FLUSH insns to synchronize the data and instruction caches. */
7544
7545 void
7546 sparc_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7547 {
7548 /* SPARC 32-bit trampoline:
7549
7550 sethi %hi(fn), %g1
7551 sethi %hi(static), %g2
7552 jmp %g1+%lo(fn)
7553 or %g2, %lo(static), %g2
7554
7555 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
7556 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
7557 */
7558
7559 emit_move_insn
7560 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
7561 expand_binop (SImode, ior_optab,
7562 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
7563 size_int (10), 0, 1),
7564 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
7565 NULL_RTX, 1, OPTAB_DIRECT));
7566
7567 emit_move_insn
7568 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7569 expand_binop (SImode, ior_optab,
7570 expand_shift (RSHIFT_EXPR, SImode, cxt,
7571 size_int (10), 0, 1),
7572 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
7573 NULL_RTX, 1, OPTAB_DIRECT));
7574
7575 emit_move_insn
7576 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7577 expand_binop (SImode, ior_optab,
7578 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
7579 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
7580 NULL_RTX, 1, OPTAB_DIRECT));
7581
7582 emit_move_insn
7583 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7584 expand_binop (SImode, ior_optab,
7585 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
7586 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
7587 NULL_RTX, 1, OPTAB_DIRECT));
7588
7589 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
7590 aligned on a 16 byte boundary so one flush clears it all. */
7591 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
7592 if (sparc_cpu != PROCESSOR_ULTRASPARC
7593 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7594 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
7595 plus_constant (tramp, 8)))));
7596
7597 /* Call __enable_execute_stack after writing onto the stack to make sure
7598 the stack address is accessible. */
7599 #ifdef ENABLE_EXECUTE_STACK
7600 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
7601 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7602 #endif
7603
7604 }
7605
7606 /* The 64-bit version is simpler because it makes more sense to load the
7607 values as "immediate" data out of the trampoline. It's also easier since
7608 we can read the PC without clobbering a register. */
7609
7610 void
7611 sparc64_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7612 {
7613 /* SPARC 64-bit trampoline:
7614
7615 rd %pc, %g1
7616 ldx [%g1+24], %g5
7617 jmp %g5
7618 ldx [%g1+16], %g5
7619 +16 bytes data
7620 */
7621
7622 emit_move_insn (gen_rtx_MEM (SImode, tramp),
7623 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
7624 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7625 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
7626 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7627 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
7628 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7629 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
7630 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
7631 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
7632 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
7633
7634 if (sparc_cpu != PROCESSOR_ULTRASPARC
7635 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7636 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
7637
7638 /* Call __enable_execute_stack after writing onto the stack to make sure
7639 the stack address is accessible. */
7640 #ifdef ENABLE_EXECUTE_STACK
7641 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
7642 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7643 #endif
7644 }
7645 \f
7646 /* Adjust the cost of a scheduling dependency. Return the new cost of
7647 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7648
7649 static int
7650 supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
7651 {
7652 enum attr_type insn_type;
7653
7654 if (! recog_memoized (insn))
7655 return 0;
7656
7657 insn_type = get_attr_type (insn);
7658
7659 if (REG_NOTE_KIND (link) == 0)
7660 {
7661 /* Data dependency; DEP_INSN writes a register that INSN reads some
7662 cycles later. */
7663
7664 /* if a load, then the dependence must be on the memory address;
7665 add an extra "cycle". Note that the cost could be two cycles
7666 if the reg was written late in an instruction group; we ca not tell
7667 here. */
7668 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
7669 return cost + 3;
7670
7671 /* Get the delay only if the address of the store is the dependence. */
7672 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
7673 {
7674 rtx pat = PATTERN(insn);
7675 rtx dep_pat = PATTERN (dep_insn);
7676
7677 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7678 return cost; /* This should not happen! */
7679
7680 /* The dependency between the two instructions was on the data that
7681 is being stored. Assume that this implies that the address of the
7682 store is not dependent. */
7683 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7684 return cost;
7685
7686 return cost + 3; /* An approximation. */
7687 }
7688
7689 /* A shift instruction cannot receive its data from an instruction
7690 in the same cycle; add a one cycle penalty. */
7691 if (insn_type == TYPE_SHIFT)
7692 return cost + 3; /* Split before cascade into shift. */
7693 }
7694 else
7695 {
7696 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7697 INSN writes some cycles later. */
7698
7699 /* These are only significant for the fpu unit; writing a fp reg before
7700 the fpu has finished with it stalls the processor. */
7701
7702 /* Reusing an integer register causes no problems. */
7703 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7704 return 0;
7705 }
7706
7707 return cost;
7708 }
7709
7710 static int
7711 hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
7712 {
7713 enum attr_type insn_type, dep_type;
7714 rtx pat = PATTERN(insn);
7715 rtx dep_pat = PATTERN (dep_insn);
7716
7717 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
7718 return cost;
7719
7720 insn_type = get_attr_type (insn);
7721 dep_type = get_attr_type (dep_insn);
7722
7723 switch (REG_NOTE_KIND (link))
7724 {
7725 case 0:
7726 /* Data dependency; DEP_INSN writes a register that INSN reads some
7727 cycles later. */
7728
7729 switch (insn_type)
7730 {
7731 case TYPE_STORE:
7732 case TYPE_FPSTORE:
7733 /* Get the delay iff the address of the store is the dependence. */
7734 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
7735 return cost;
7736
7737 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
7738 return cost;
7739 return cost + 3;
7740
7741 case TYPE_LOAD:
7742 case TYPE_SLOAD:
7743 case TYPE_FPLOAD:
7744 /* If a load, then the dependence must be on the memory address. If
7745 the addresses aren't equal, then it might be a false dependency */
7746 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
7747 {
7748 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
7749 || GET_CODE (SET_DEST (dep_pat)) != MEM
7750 || GET_CODE (SET_SRC (pat)) != MEM
7751 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
7752 XEXP (SET_SRC (pat), 0)))
7753 return cost + 2;
7754
7755 return cost + 8;
7756 }
7757 break;
7758
7759 case TYPE_BRANCH:
7760 /* Compare to branch latency is 0. There is no benefit from
7761 separating compare and branch. */
7762 if (dep_type == TYPE_COMPARE)
7763 return 0;
7764 /* Floating point compare to branch latency is less than
7765 compare to conditional move. */
7766 if (dep_type == TYPE_FPCMP)
7767 return cost - 1;
7768 break;
7769 default:
7770 break;
7771 }
7772 break;
7773
7774 case REG_DEP_ANTI:
7775 /* Anti-dependencies only penalize the fpu unit. */
7776 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
7777 return 0;
7778 break;
7779
7780 default:
7781 break;
7782 }
7783
7784 return cost;
7785 }
7786
7787 static int
7788 sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost)
7789 {
7790 switch (sparc_cpu)
7791 {
7792 case PROCESSOR_SUPERSPARC:
7793 cost = supersparc_adjust_cost (insn, link, dep, cost);
7794 break;
7795 case PROCESSOR_HYPERSPARC:
7796 case PROCESSOR_SPARCLITE86X:
7797 cost = hypersparc_adjust_cost (insn, link, dep, cost);
7798 break;
7799 default:
7800 break;
7801 }
7802 return cost;
7803 }
7804
7805 static void
7806 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED,
7807 int sched_verbose ATTRIBUTE_UNUSED,
7808 int max_ready ATTRIBUTE_UNUSED)
7809 {
7810 }
7811
7812 static int
7813 sparc_use_sched_lookahead (void)
7814 {
7815 if (sparc_cpu == PROCESSOR_ULTRASPARC
7816 || sparc_cpu == PROCESSOR_ULTRASPARC3)
7817 return 4;
7818 if ((1 << sparc_cpu) &
7819 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
7820 (1 << PROCESSOR_SPARCLITE86X)))
7821 return 3;
7822 return 0;
7823 }
7824
7825 static int
7826 sparc_issue_rate (void)
7827 {
7828 switch (sparc_cpu)
7829 {
7830 default:
7831 return 1;
7832 case PROCESSOR_V9:
7833 /* Assume V9 processors are capable of at least dual-issue. */
7834 return 2;
7835 case PROCESSOR_SUPERSPARC:
7836 return 3;
7837 case PROCESSOR_HYPERSPARC:
7838 case PROCESSOR_SPARCLITE86X:
7839 return 2;
7840 case PROCESSOR_ULTRASPARC:
7841 case PROCESSOR_ULTRASPARC3:
7842 return 4;
7843 }
7844 }
7845
7846 static int
7847 set_extends (rtx insn)
7848 {
7849 register rtx pat = PATTERN (insn);
7850
7851 switch (GET_CODE (SET_SRC (pat)))
7852 {
7853 /* Load and some shift instructions zero extend. */
7854 case MEM:
7855 case ZERO_EXTEND:
7856 /* sethi clears the high bits */
7857 case HIGH:
7858 /* LO_SUM is used with sethi. sethi cleared the high
7859 bits and the values used with lo_sum are positive */
7860 case LO_SUM:
7861 /* Store flag stores 0 or 1 */
7862 case LT: case LTU:
7863 case GT: case GTU:
7864 case LE: case LEU:
7865 case GE: case GEU:
7866 case EQ:
7867 case NE:
7868 return 1;
7869 case AND:
7870 {
7871 rtx op0 = XEXP (SET_SRC (pat), 0);
7872 rtx op1 = XEXP (SET_SRC (pat), 1);
7873 if (GET_CODE (op1) == CONST_INT)
7874 return INTVAL (op1) >= 0;
7875 if (GET_CODE (op0) != REG)
7876 return 0;
7877 if (sparc_check_64 (op0, insn) == 1)
7878 return 1;
7879 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
7880 }
7881 case IOR:
7882 case XOR:
7883 {
7884 rtx op0 = XEXP (SET_SRC (pat), 0);
7885 rtx op1 = XEXP (SET_SRC (pat), 1);
7886 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
7887 return 0;
7888 if (GET_CODE (op1) == CONST_INT)
7889 return INTVAL (op1) >= 0;
7890 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
7891 }
7892 case LSHIFTRT:
7893 return GET_MODE (SET_SRC (pat)) == SImode;
7894 /* Positive integers leave the high bits zero. */
7895 case CONST_DOUBLE:
7896 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
7897 case CONST_INT:
7898 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
7899 case ASHIFTRT:
7900 case SIGN_EXTEND:
7901 return - (GET_MODE (SET_SRC (pat)) == SImode);
7902 case REG:
7903 return sparc_check_64 (SET_SRC (pat), insn);
7904 default:
7905 return 0;
7906 }
7907 }
7908
7909 /* We _ought_ to have only one kind per function, but... */
7910 static GTY(()) rtx sparc_addr_diff_list;
7911 static GTY(()) rtx sparc_addr_list;
7912
7913 void
7914 sparc_defer_case_vector (rtx lab, rtx vec, int diff)
7915 {
7916 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
7917 if (diff)
7918 sparc_addr_diff_list
7919 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
7920 else
7921 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
7922 }
7923
7924 static void
7925 sparc_output_addr_vec (rtx vec)
7926 {
7927 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7928 int idx, vlen = XVECLEN (body, 0);
7929
7930 #ifdef ASM_OUTPUT_ADDR_VEC_START
7931 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7932 #endif
7933
7934 #ifdef ASM_OUTPUT_CASE_LABEL
7935 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7936 NEXT_INSN (lab));
7937 #else
7938 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7939 #endif
7940
7941 for (idx = 0; idx < vlen; idx++)
7942 {
7943 ASM_OUTPUT_ADDR_VEC_ELT
7944 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
7945 }
7946
7947 #ifdef ASM_OUTPUT_ADDR_VEC_END
7948 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7949 #endif
7950 }
7951
7952 static void
7953 sparc_output_addr_diff_vec (rtx vec)
7954 {
7955 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
7956 rtx base = XEXP (XEXP (body, 0), 0);
7957 int idx, vlen = XVECLEN (body, 1);
7958
7959 #ifdef ASM_OUTPUT_ADDR_VEC_START
7960 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
7961 #endif
7962
7963 #ifdef ASM_OUTPUT_CASE_LABEL
7964 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
7965 NEXT_INSN (lab));
7966 #else
7967 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
7968 #endif
7969
7970 for (idx = 0; idx < vlen; idx++)
7971 {
7972 ASM_OUTPUT_ADDR_DIFF_ELT
7973 (asm_out_file,
7974 body,
7975 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
7976 CODE_LABEL_NUMBER (base));
7977 }
7978
7979 #ifdef ASM_OUTPUT_ADDR_VEC_END
7980 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
7981 #endif
7982 }
7983
7984 static void
7985 sparc_output_deferred_case_vectors (void)
7986 {
7987 rtx t;
7988 int align;
7989
7990 if (sparc_addr_list == NULL_RTX
7991 && sparc_addr_diff_list == NULL_RTX)
7992 return;
7993
7994 /* Align to cache line in the function's code section. */
7995 function_section (current_function_decl);
7996
7997 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
7998 if (align > 0)
7999 ASM_OUTPUT_ALIGN (asm_out_file, align);
8000
8001 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
8002 sparc_output_addr_vec (XEXP (t, 0));
8003 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
8004 sparc_output_addr_diff_vec (XEXP (t, 0));
8005
8006 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
8007 }
8008
8009 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
8010 unknown. Return 1 if the high bits are zero, -1 if the register is
8011 sign extended. */
8012 int
8013 sparc_check_64 (rtx x, rtx insn)
8014 {
8015 /* If a register is set only once it is safe to ignore insns this
8016 code does not know how to handle. The loop will either recognize
8017 the single set and return the correct value or fail to recognize
8018 it and return 0. */
8019 int set_once = 0;
8020 rtx y = x;
8021
8022 if (GET_CODE (x) != REG)
8023 abort ();
8024
8025 if (GET_MODE (x) == DImode)
8026 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
8027
8028 if (flag_expensive_optimizations
8029 && REG_N_SETS (REGNO (y)) == 1)
8030 set_once = 1;
8031
8032 if (insn == 0)
8033 {
8034 if (set_once)
8035 insn = get_last_insn_anywhere ();
8036 else
8037 return 0;
8038 }
8039
8040 while ((insn = PREV_INSN (insn)))
8041 {
8042 switch (GET_CODE (insn))
8043 {
8044 case JUMP_INSN:
8045 case NOTE:
8046 break;
8047 case CODE_LABEL:
8048 case CALL_INSN:
8049 default:
8050 if (! set_once)
8051 return 0;
8052 break;
8053 case INSN:
8054 {
8055 rtx pat = PATTERN (insn);
8056 if (GET_CODE (pat) != SET)
8057 return 0;
8058 if (rtx_equal_p (x, SET_DEST (pat)))
8059 return set_extends (insn);
8060 if (y && rtx_equal_p (y, SET_DEST (pat)))
8061 return set_extends (insn);
8062 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
8063 return 0;
8064 }
8065 }
8066 }
8067 return 0;
8068 }
8069
8070 /* Returns assembly code to perform a DImode shift using
8071 a 64-bit global or out register on SPARC-V8+. */
8072 const char *
8073 output_v8plus_shift (rtx *operands, rtx insn, const char *opcode)
8074 {
8075 static char asm_code[60];
8076
8077 /* The scratch register is only required when the destination
8078 register is not a 64-bit global or out register. */
8079 if (which_alternative != 2)
8080 operands[3] = operands[0];
8081
8082 /* We can only shift by constants <= 63. */
8083 if (GET_CODE (operands[2]) == CONST_INT)
8084 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
8085
8086 if (GET_CODE (operands[1]) == CONST_INT)
8087 {
8088 output_asm_insn ("mov\t%1, %3", operands);
8089 }
8090 else
8091 {
8092 output_asm_insn ("sllx\t%H1, 32, %3", operands);
8093 if (sparc_check_64 (operands[1], insn) <= 0)
8094 output_asm_insn ("srl\t%L1, 0, %L1", operands);
8095 output_asm_insn ("or\t%L1, %3, %3", operands);
8096 }
8097
8098 strcpy(asm_code, opcode);
8099
8100 if (which_alternative != 2)
8101 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
8102 else
8103 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
8104 }
8105 \f
8106 /* Output rtl to increment the profiler label LABELNO
8107 for profiling a function entry. */
8108
8109 void
8110 sparc_profile_hook (int labelno)
8111 {
8112 char buf[32];
8113 rtx lab, fun;
8114
8115 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
8116 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
8117 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
8118
8119 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
8120 }
8121 \f
8122 #ifdef OBJECT_FORMAT_ELF
8123 static void
8124 sparc_elf_asm_named_section (const char *name, unsigned int flags)
8125 {
8126 if (flags & SECTION_MERGE)
8127 {
8128 /* entsize cannot be expressed in this section attributes
8129 encoding style. */
8130 default_elf_asm_named_section (name, flags);
8131 return;
8132 }
8133
8134 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
8135
8136 if (!(flags & SECTION_DEBUG))
8137 fputs (",#alloc", asm_out_file);
8138 if (flags & SECTION_WRITE)
8139 fputs (",#write", asm_out_file);
8140 if (flags & SECTION_TLS)
8141 fputs (",#tls", asm_out_file);
8142 if (flags & SECTION_CODE)
8143 fputs (",#execinstr", asm_out_file);
8144
8145 /* ??? Handle SECTION_BSS. */
8146
8147 fputc ('\n', asm_out_file);
8148 }
8149 #endif /* OBJECT_FORMAT_ELF */
8150
8151 /* We do not allow indirect calls to be optimized into sibling calls.
8152
8153 We cannot use sibling calls when delayed branches are disabled
8154 because they will likely require the call delay slot to be filled.
8155
8156 Also, on SPARC 32-bit we cannot emit a sibling call when the
8157 current function returns a structure. This is because the "unimp
8158 after call" convention would cause the callee to return to the
8159 wrong place. The generic code already disallows cases where the
8160 function being called returns a structure.
8161
8162 It may seem strange how this last case could occur. Usually there
8163 is code after the call which jumps to epilogue code which dumps the
8164 return value into the struct return area. That ought to invalidate
8165 the sibling call right? Well, in the C++ case we can end up passing
8166 the pointer to the struct return area to a constructor (which returns
8167 void) and then nothing else happens. Such a sibling call would look
8168 valid without the added check here. */
8169 static bool
8170 sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8171 {
8172 return (decl
8173 && flag_delayed_branch
8174 && (TARGET_ARCH64 || ! current_function_returns_struct));
8175 }
8176 \f
8177 /* libfunc renaming. */
8178 #include "config/gofast.h"
8179
8180 static void
8181 sparc_init_libfuncs (void)
8182 {
8183 if (TARGET_ARCH32)
8184 {
8185 /* Use the subroutines that Sun's library provides for integer
8186 multiply and divide. The `*' prevents an underscore from
8187 being prepended by the compiler. .umul is a little faster
8188 than .mul. */
8189 set_optab_libfunc (smul_optab, SImode, "*.umul");
8190 set_optab_libfunc (sdiv_optab, SImode, "*.div");
8191 set_optab_libfunc (udiv_optab, SImode, "*.udiv");
8192 set_optab_libfunc (smod_optab, SImode, "*.rem");
8193 set_optab_libfunc (umod_optab, SImode, "*.urem");
8194
8195 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
8196 set_optab_libfunc (add_optab, TFmode, "_Q_add");
8197 set_optab_libfunc (sub_optab, TFmode, "_Q_sub");
8198 set_optab_libfunc (neg_optab, TFmode, "_Q_neg");
8199 set_optab_libfunc (smul_optab, TFmode, "_Q_mul");
8200 set_optab_libfunc (sdiv_optab, TFmode, "_Q_div");
8201
8202 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
8203 is because with soft-float, the SFmode and DFmode sqrt
8204 instructions will be absent, and the compiler will notice and
8205 try to use the TFmode sqrt instruction for calls to the
8206 builtin function sqrt, but this fails. */
8207 if (TARGET_FPU)
8208 set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt");
8209
8210 set_optab_libfunc (eq_optab, TFmode, "_Q_feq");
8211 set_optab_libfunc (ne_optab, TFmode, "_Q_fne");
8212 set_optab_libfunc (gt_optab, TFmode, "_Q_fgt");
8213 set_optab_libfunc (ge_optab, TFmode, "_Q_fge");
8214 set_optab_libfunc (lt_optab, TFmode, "_Q_flt");
8215 set_optab_libfunc (le_optab, TFmode, "_Q_fle");
8216
8217 set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq");
8218 set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq");
8219 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos");
8220 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod");
8221
8222 set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi");
8223 set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou");
8224 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq");
8225
8226 if (DITF_CONVERSION_LIBFUNCS)
8227 {
8228 set_conv_libfunc (sfix_optab, DImode, TFmode, "_Q_qtoll");
8229 set_conv_libfunc (ufix_optab, DImode, TFmode, "_Q_qtoull");
8230 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_Q_lltoq");
8231 }
8232
8233 if (SUN_CONVERSION_LIBFUNCS)
8234 {
8235 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8236 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8237 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8238 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8239 }
8240 }
8241 if (TARGET_ARCH64)
8242 {
8243 /* In the SPARC 64bit ABI, SImode multiply and divide functions
8244 do not exist in the library. Make sure the compiler does not
8245 emit calls to them by accident. (It should always use the
8246 hardware instructions.) */
8247 set_optab_libfunc (smul_optab, SImode, 0);
8248 set_optab_libfunc (sdiv_optab, SImode, 0);
8249 set_optab_libfunc (udiv_optab, SImode, 0);
8250 set_optab_libfunc (smod_optab, SImode, 0);
8251 set_optab_libfunc (umod_optab, SImode, 0);
8252
8253 if (SUN_INTEGER_MULTIPLY_64)
8254 {
8255 set_optab_libfunc (smul_optab, DImode, "__mul64");
8256 set_optab_libfunc (sdiv_optab, DImode, "__div64");
8257 set_optab_libfunc (udiv_optab, DImode, "__udiv64");
8258 set_optab_libfunc (smod_optab, DImode, "__rem64");
8259 set_optab_libfunc (umod_optab, DImode, "__urem64");
8260 }
8261
8262 if (SUN_CONVERSION_LIBFUNCS)
8263 {
8264 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol");
8265 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul");
8266 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol");
8267 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul");
8268 }
8269 }
8270
8271 gofast_maybe_init_libfuncs ();
8272 }
8273 \f
8274 int
8275 sparc_extra_constraint_check (rtx op, int c, int strict)
8276 {
8277 int reload_ok_mem;
8278
8279 if (TARGET_ARCH64
8280 && (c == 'T' || c == 'U'))
8281 return 0;
8282
8283 switch (c)
8284 {
8285 case 'Q':
8286 return fp_sethi_p (op);
8287
8288 case 'R':
8289 return fp_mov_p (op);
8290
8291 case 'S':
8292 return fp_high_losum_p (op);
8293
8294 case 'U':
8295 if (! strict
8296 || (GET_CODE (op) == REG
8297 && (REGNO (op) < FIRST_PSEUDO_REGISTER
8298 || reg_renumber[REGNO (op)] >= 0)))
8299 return register_ok_for_ldd (op);
8300
8301 return 0;
8302
8303 case 'W':
8304 case 'T':
8305 break;
8306
8307 default:
8308 return 0;
8309 }
8310
8311 /* Our memory extra constraints have to emulate the
8312 behavior of 'm' and 'o' in order for reload to work
8313 correctly. */
8314 if (GET_CODE (op) == MEM)
8315 {
8316 reload_ok_mem = 0;
8317 if ((TARGET_ARCH64 || mem_min_alignment (op, 8))
8318 && (! strict
8319 || strict_memory_address_p (Pmode, XEXP (op, 0))))
8320 reload_ok_mem = 1;
8321 }
8322 else
8323 {
8324 reload_ok_mem = (reload_in_progress
8325 && GET_CODE (op) == REG
8326 && REGNO (op) >= FIRST_PSEUDO_REGISTER
8327 && reg_renumber [REGNO (op)] < 0);
8328 }
8329
8330 return reload_ok_mem;
8331 }
8332
8333 /* ??? This duplicates information provided to the compiler by the
8334 ??? scheduler description. Some day, teach genautomata to output
8335 ??? the latencies and then CSE will just use that. */
8336
8337 static bool
8338 sparc_rtx_costs (rtx x, int code, int outer_code, int *total)
8339 {
8340 enum machine_mode mode = GET_MODE (x);
8341 bool float_mode_p = FLOAT_MODE_P (mode);
8342
8343 switch (code)
8344 {
8345 case CONST_INT:
8346 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
8347 {
8348 *total = 0;
8349 return true;
8350 }
8351 /* FALLTHRU */
8352
8353 case HIGH:
8354 *total = 2;
8355 return true;
8356
8357 case CONST:
8358 case LABEL_REF:
8359 case SYMBOL_REF:
8360 *total = 4;
8361 return true;
8362
8363 case CONST_DOUBLE:
8364 if (GET_MODE (x) == DImode
8365 && ((XINT (x, 3) == 0
8366 && (unsigned HOST_WIDE_INT) XINT (x, 2) < 0x1000)
8367 || (XINT (x, 3) == -1
8368 && XINT (x, 2) < 0
8369 && XINT (x, 2) >= -0x1000)))
8370 *total = 0;
8371 else
8372 *total = 8;
8373 return true;
8374
8375 case MEM:
8376 /* If outer-code was a sign or zero extension, a cost
8377 of COSTS_N_INSNS (1) was already added in. This is
8378 why we are subtracting it back out. */
8379 if (outer_code == ZERO_EXTEND)
8380 {
8381 *total = sparc_costs->int_zload - COSTS_N_INSNS (1);
8382 }
8383 else if (outer_code == SIGN_EXTEND)
8384 {
8385 *total = sparc_costs->int_sload - COSTS_N_INSNS (1);
8386 }
8387 else if (float_mode_p)
8388 {
8389 *total = sparc_costs->float_load;
8390 }
8391 else
8392 {
8393 *total = sparc_costs->int_load;
8394 }
8395
8396 return true;
8397
8398 case PLUS:
8399 case MINUS:
8400 if (float_mode_p)
8401 *total = sparc_costs->float_plusminus;
8402 else
8403 *total = COSTS_N_INSNS (1);
8404 return false;
8405
8406 case MULT:
8407 if (float_mode_p)
8408 *total = sparc_costs->float_mul;
8409 else if (! TARGET_HARD_MUL)
8410 *total = COSTS_N_INSNS (25);
8411 else
8412 {
8413 int bit_cost;
8414
8415 bit_cost = 0;
8416 if (sparc_costs->int_mul_bit_factor)
8417 {
8418 int nbits;
8419
8420 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8421 {
8422 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
8423 for (nbits = 0; value != 0; value &= value - 1)
8424 nbits++;
8425 }
8426 else if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
8427 && GET_MODE (XEXP (x, 1)) == DImode)
8428 {
8429 rtx x1 = XEXP (x, 1);
8430 unsigned HOST_WIDE_INT value1 = XINT (x1, 2);
8431 unsigned HOST_WIDE_INT value2 = XINT (x1, 3);
8432
8433 for (nbits = 0; value1 != 0; value1 &= value1 - 1)
8434 nbits++;
8435 for (; value2 != 0; value2 &= value2 - 1)
8436 nbits++;
8437 }
8438 else
8439 nbits = 7;
8440
8441 if (nbits < 3)
8442 nbits = 3;
8443 bit_cost = (nbits - 3) / sparc_costs->int_mul_bit_factor;
8444 bit_cost = COSTS_N_INSNS (bit_cost);
8445 }
8446
8447 if (mode == DImode)
8448 *total = sparc_costs->int_mulX + bit_cost;
8449 else
8450 *total = sparc_costs->int_mul + bit_cost;
8451 }
8452 return false;
8453
8454 case ASHIFT:
8455 case ASHIFTRT:
8456 case LSHIFTRT:
8457 *total = COSTS_N_INSNS (1) + sparc_costs->shift_penalty;
8458 return false;
8459
8460 case DIV:
8461 case UDIV:
8462 case MOD:
8463 case UMOD:
8464 if (float_mode_p)
8465 {
8466 if (mode == DFmode)
8467 *total = sparc_costs->float_div_df;
8468 else
8469 *total = sparc_costs->float_div_sf;
8470 }
8471 else
8472 {
8473 if (mode == DImode)
8474 *total = sparc_costs->int_divX;
8475 else
8476 *total = sparc_costs->int_div;
8477 }
8478 return false;
8479
8480 case NEG:
8481 if (! float_mode_p)
8482 {
8483 *total = COSTS_N_INSNS (1);
8484 return false;
8485 }
8486 /* FALLTHRU */
8487
8488 case ABS:
8489 case FLOAT:
8490 case UNSIGNED_FLOAT:
8491 case FIX:
8492 case UNSIGNED_FIX:
8493 case FLOAT_EXTEND:
8494 case FLOAT_TRUNCATE:
8495 *total = sparc_costs->float_move;
8496 return false;
8497
8498 case SQRT:
8499 if (mode == DFmode)
8500 *total = sparc_costs->float_sqrt_df;
8501 else
8502 *total = sparc_costs->float_sqrt_sf;
8503 return false;
8504
8505 case COMPARE:
8506 if (float_mode_p)
8507 *total = sparc_costs->float_cmp;
8508 else
8509 *total = COSTS_N_INSNS (1);
8510 return false;
8511
8512 case IF_THEN_ELSE:
8513 if (float_mode_p)
8514 *total = sparc_costs->float_cmove;
8515 else
8516 *total = sparc_costs->int_cmove;
8517 return false;
8518
8519 default:
8520 return false;
8521 }
8522 }
8523
8524 /* Emit the sequence of insns SEQ while preserving the register REG. */
8525
8526 static void
8527 emit_and_preserve (rtx seq, rtx reg)
8528 {
8529 rtx slot = gen_rtx_MEM (word_mode,
8530 plus_constant (stack_pointer_rtx, SPARC_STACK_BIAS));
8531
8532 emit_stack_pointer_decrement (GEN_INT (UNITS_PER_WORD));
8533 emit_insn (gen_rtx_SET (VOIDmode, slot, reg));
8534 emit_insn (seq);
8535 emit_insn (gen_rtx_SET (VOIDmode, reg, slot));
8536 emit_stack_pointer_increment (GEN_INT (UNITS_PER_WORD));
8537 }
8538
8539 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
8540 Used for C++ multiple inheritance. */
8541
8542 static void
8543 sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
8544 HOST_WIDE_INT delta,
8545 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
8546 tree function)
8547 {
8548 rtx this, insn, funexp, delta_rtx;
8549 unsigned int int_arg_first;
8550
8551 reload_completed = 1;
8552 epilogue_completed = 1;
8553 no_new_pseudos = 1;
8554 reset_block_changes ();
8555
8556 emit_note (NOTE_INSN_PROLOGUE_END);
8557
8558 if (flag_delayed_branch)
8559 {
8560 /* We will emit a regular sibcall below, so we need to instruct
8561 output_sibcall that we are in a leaf function. */
8562 current_function_uses_only_leaf_regs = 1;
8563
8564 /* This will cause final.c to invoke leaf_renumber_regs so we
8565 must behave as if we were in a not-yet-leafified function. */
8566 int_arg_first = SPARC_INCOMING_INT_ARG_FIRST;
8567 }
8568 else
8569 {
8570 /* We will emit the sibcall manually below, so we will need to
8571 manually spill non-leaf registers. */
8572 current_function_uses_only_leaf_regs = 0;
8573
8574 /* We really are in a leaf function. */
8575 int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST;
8576 }
8577
8578 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
8579 returns a structure, the structure return pointer is there instead. */
8580 if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8581 this = gen_rtx_REG (Pmode, int_arg_first + 1);
8582 else
8583 this = gen_rtx_REG (Pmode, int_arg_first);
8584
8585 /* Add DELTA. When possible use a plain add, otherwise load it into
8586 a register first. */
8587 delta_rtx = GEN_INT (delta);
8588 if (!SPARC_SIMM13_P (delta))
8589 {
8590 rtx scratch = gen_rtx_REG (Pmode, 1);
8591
8592 if (input_operand (delta_rtx, GET_MODE (scratch)))
8593 emit_insn (gen_rtx_SET (VOIDmode, scratch, delta_rtx));
8594 else
8595 {
8596 if (TARGET_ARCH64)
8597 sparc_emit_set_const64 (scratch, delta_rtx);
8598 else
8599 sparc_emit_set_const32 (scratch, delta_rtx);
8600 }
8601
8602 delta_rtx = scratch;
8603 }
8604
8605 emit_insn (gen_rtx_SET (VOIDmode,
8606 this,
8607 gen_rtx_PLUS (Pmode, this, delta_rtx)));
8608
8609 /* Generate a tail call to the target function. */
8610 if (! TREE_USED (function))
8611 {
8612 assemble_external (function);
8613 TREE_USED (function) = 1;
8614 }
8615 funexp = XEXP (DECL_RTL (function), 0);
8616
8617 if (flag_delayed_branch)
8618 {
8619 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
8620 insn = emit_call_insn (gen_sibcall (funexp));
8621 SIBLING_CALL_P (insn) = 1;
8622 }
8623 else
8624 {
8625 /* The hoops we have to jump through in order to generate a sibcall
8626 without using delay slots... */
8627 rtx spill_reg, seq, scratch = gen_rtx_REG (Pmode, 1);
8628
8629 if (flag_pic)
8630 {
8631 spill_reg = gen_rtx_REG (word_mode, 15); /* %o7 */
8632 start_sequence ();
8633 load_pic_register (); /* clobbers %o7 */
8634 scratch = legitimize_pic_address (funexp, Pmode, scratch);
8635 seq = get_insns ();
8636 end_sequence ();
8637 emit_and_preserve (seq, spill_reg);
8638 }
8639 else if (TARGET_ARCH32)
8640 {
8641 emit_insn (gen_rtx_SET (VOIDmode,
8642 scratch,
8643 gen_rtx_HIGH (SImode, funexp)));
8644 emit_insn (gen_rtx_SET (VOIDmode,
8645 scratch,
8646 gen_rtx_LO_SUM (SImode, scratch, funexp)));
8647 }
8648 else /* TARGET_ARCH64 */
8649 {
8650 switch (sparc_cmodel)
8651 {
8652 case CM_MEDLOW:
8653 case CM_MEDMID:
8654 /* The destination can serve as a temporary. */
8655 sparc_emit_set_symbolic_const64 (scratch, funexp, scratch);
8656 break;
8657
8658 case CM_MEDANY:
8659 case CM_EMBMEDANY:
8660 /* The destination cannot serve as a temporary. */
8661 spill_reg = gen_rtx_REG (DImode, 15); /* %o7 */
8662 start_sequence ();
8663 sparc_emit_set_symbolic_const64 (scratch, funexp, spill_reg);
8664 seq = get_insns ();
8665 end_sequence ();
8666 emit_and_preserve (seq, spill_reg);
8667 break;
8668
8669 default:
8670 abort();
8671 }
8672 }
8673
8674 emit_jump_insn (gen_indirect_jump (scratch));
8675 }
8676
8677 emit_barrier ();
8678
8679 /* Run just enough of rest_of_compilation to get the insns emitted.
8680 There's not really enough bulk here to make other passes such as
8681 instruction scheduling worth while. Note that use_thunk calls
8682 assemble_start_function and assemble_end_function. */
8683 insn = get_insns ();
8684 insn_locators_initialize ();
8685 shorten_branches (insn);
8686 final_start_function (insn, file, 1);
8687 final (insn, file, 1, 0);
8688 final_end_function ();
8689
8690 reload_completed = 0;
8691 epilogue_completed = 0;
8692 no_new_pseudos = 0;
8693 }
8694
8695 /* How to allocate a 'struct machine_function'. */
8696
8697 static struct machine_function *
8698 sparc_init_machine_status (void)
8699 {
8700 return ggc_alloc_cleared (sizeof (struct machine_function));
8701 }
8702
8703 /* Locate some local-dynamic symbol still in use by this function
8704 so that we can print its name in local-dynamic base patterns. */
8705
8706 static const char *
8707 get_some_local_dynamic_name (void)
8708 {
8709 rtx insn;
8710
8711 if (cfun->machine->some_ld_name)
8712 return cfun->machine->some_ld_name;
8713
8714 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
8715 if (INSN_P (insn)
8716 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
8717 return cfun->machine->some_ld_name;
8718
8719 abort ();
8720 }
8721
8722 static int
8723 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
8724 {
8725 rtx x = *px;
8726
8727 if (x
8728 && GET_CODE (x) == SYMBOL_REF
8729 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
8730 {
8731 cfun->machine->some_ld_name = XSTR (x, 0);
8732 return 1;
8733 }
8734
8735 return 0;
8736 }
8737
8738 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
8739 We need to emit DTP-relative relocations. */
8740
8741 void
8742 sparc_output_dwarf_dtprel (FILE *file, int size, rtx x)
8743 {
8744 switch (size)
8745 {
8746 case 4:
8747 fputs ("\t.word\t%r_tls_dtpoff32(", file);
8748 break;
8749 case 8:
8750 fputs ("\t.xword\t%r_tls_dtpoff64(", file);
8751 break;
8752 default:
8753 abort ();
8754 }
8755 output_addr_const (file, x);
8756 fputs (")", file);
8757 }
8758
8759 #include "gt-sparc.h"
Mirror of https://gcc.gnu.org/git/gcc.git