1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987-2017 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
4 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
34 #include "stringpool.h"
41 #include "diagnostic-core.h"
43 #include "fold-const.h"
44 #include "stor-layout.h"
48 #include "insn-attr.h"
52 #include "common/common-target.h"
54 #include "langhooks.h"
57 #include "tree-pass.h"
61 /* This file should be included last. */
62 #include "target-def.h"
66 struct processor_costs
{
70 /* Integer signed load */
73 /* Integer zeroed load */
79 /* fmov, fneg, fabs */
83 const int float_plusminus
;
89 const int float_cmove
;
95 const int float_div_sf
;
98 const int float_div_df
;
101 const int float_sqrt_sf
;
104 const int float_sqrt_df
;
112 /* integer multiply cost for each bit set past the most
113 significant 3, so the formula for multiply cost becomes:
116 highest_bit = highest_clear_bit(rs1);
118 highest_bit = highest_set_bit(rs1);
121 cost = int_mul{,X} + ((highest_bit - 3) / int_mul_bit_factor);
123 A value of zero indicates that the multiply costs is fixed,
125 const int int_mul_bit_factor
;
136 /* penalty for shifts, due to scheduling rules etc. */
137 const int shift_penalty
;
141 struct processor_costs cypress_costs
= {
142 COSTS_N_INSNS (2), /* int load */
143 COSTS_N_INSNS (2), /* int signed load */
144 COSTS_N_INSNS (2), /* int zeroed load */
145 COSTS_N_INSNS (2), /* float load */
146 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
147 COSTS_N_INSNS (5), /* fadd, fsub */
148 COSTS_N_INSNS (1), /* fcmp */
149 COSTS_N_INSNS (1), /* fmov, fmovr */
150 COSTS_N_INSNS (7), /* fmul */
151 COSTS_N_INSNS (37), /* fdivs */
152 COSTS_N_INSNS (37), /* fdivd */
153 COSTS_N_INSNS (63), /* fsqrts */
154 COSTS_N_INSNS (63), /* fsqrtd */
155 COSTS_N_INSNS (1), /* imul */
156 COSTS_N_INSNS (1), /* imulX */
157 0, /* imul bit factor */
158 COSTS_N_INSNS (1), /* idiv */
159 COSTS_N_INSNS (1), /* idivX */
160 COSTS_N_INSNS (1), /* movcc/movr */
161 0, /* shift penalty */
165 struct processor_costs supersparc_costs
= {
166 COSTS_N_INSNS (1), /* int load */
167 COSTS_N_INSNS (1), /* int signed load */
168 COSTS_N_INSNS (1), /* int zeroed load */
169 COSTS_N_INSNS (0), /* float load */
170 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
171 COSTS_N_INSNS (3), /* fadd, fsub */
172 COSTS_N_INSNS (3), /* fcmp */
173 COSTS_N_INSNS (1), /* fmov, fmovr */
174 COSTS_N_INSNS (3), /* fmul */
175 COSTS_N_INSNS (6), /* fdivs */
176 COSTS_N_INSNS (9), /* fdivd */
177 COSTS_N_INSNS (12), /* fsqrts */
178 COSTS_N_INSNS (12), /* fsqrtd */
179 COSTS_N_INSNS (4), /* imul */
180 COSTS_N_INSNS (4), /* imulX */
181 0, /* imul bit factor */
182 COSTS_N_INSNS (4), /* idiv */
183 COSTS_N_INSNS (4), /* idivX */
184 COSTS_N_INSNS (1), /* movcc/movr */
185 1, /* shift penalty */
189 struct processor_costs hypersparc_costs
= {
190 COSTS_N_INSNS (1), /* int load */
191 COSTS_N_INSNS (1), /* int signed load */
192 COSTS_N_INSNS (1), /* int zeroed load */
193 COSTS_N_INSNS (1), /* float load */
194 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
195 COSTS_N_INSNS (1), /* fadd, fsub */
196 COSTS_N_INSNS (1), /* fcmp */
197 COSTS_N_INSNS (1), /* fmov, fmovr */
198 COSTS_N_INSNS (1), /* fmul */
199 COSTS_N_INSNS (8), /* fdivs */
200 COSTS_N_INSNS (12), /* fdivd */
201 COSTS_N_INSNS (17), /* fsqrts */
202 COSTS_N_INSNS (17), /* fsqrtd */
203 COSTS_N_INSNS (17), /* imul */
204 COSTS_N_INSNS (17), /* imulX */
205 0, /* imul bit factor */
206 COSTS_N_INSNS (17), /* idiv */
207 COSTS_N_INSNS (17), /* idivX */
208 COSTS_N_INSNS (1), /* movcc/movr */
209 0, /* shift penalty */
213 struct processor_costs leon_costs
= {
214 COSTS_N_INSNS (1), /* int load */
215 COSTS_N_INSNS (1), /* int signed load */
216 COSTS_N_INSNS (1), /* int zeroed load */
217 COSTS_N_INSNS (1), /* float load */
218 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
219 COSTS_N_INSNS (1), /* fadd, fsub */
220 COSTS_N_INSNS (1), /* fcmp */
221 COSTS_N_INSNS (1), /* fmov, fmovr */
222 COSTS_N_INSNS (1), /* fmul */
223 COSTS_N_INSNS (15), /* fdivs */
224 COSTS_N_INSNS (15), /* fdivd */
225 COSTS_N_INSNS (23), /* fsqrts */
226 COSTS_N_INSNS (23), /* fsqrtd */
227 COSTS_N_INSNS (5), /* imul */
228 COSTS_N_INSNS (5), /* imulX */
229 0, /* imul bit factor */
230 COSTS_N_INSNS (5), /* idiv */
231 COSTS_N_INSNS (5), /* idivX */
232 COSTS_N_INSNS (1), /* movcc/movr */
233 0, /* shift penalty */
237 struct processor_costs leon3_costs
= {
238 COSTS_N_INSNS (1), /* int load */
239 COSTS_N_INSNS (1), /* int signed load */
240 COSTS_N_INSNS (1), /* int zeroed load */
241 COSTS_N_INSNS (1), /* float load */
242 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
243 COSTS_N_INSNS (1), /* fadd, fsub */
244 COSTS_N_INSNS (1), /* fcmp */
245 COSTS_N_INSNS (1), /* fmov, fmovr */
246 COSTS_N_INSNS (1), /* fmul */
247 COSTS_N_INSNS (14), /* fdivs */
248 COSTS_N_INSNS (15), /* fdivd */
249 COSTS_N_INSNS (22), /* fsqrts */
250 COSTS_N_INSNS (23), /* fsqrtd */
251 COSTS_N_INSNS (5), /* imul */
252 COSTS_N_INSNS (5), /* imulX */
253 0, /* imul bit factor */
254 COSTS_N_INSNS (35), /* idiv */
255 COSTS_N_INSNS (35), /* idivX */
256 COSTS_N_INSNS (1), /* movcc/movr */
257 0, /* shift penalty */
261 struct processor_costs sparclet_costs
= {
262 COSTS_N_INSNS (3), /* int load */
263 COSTS_N_INSNS (3), /* int signed load */
264 COSTS_N_INSNS (1), /* int zeroed load */
265 COSTS_N_INSNS (1), /* float load */
266 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
267 COSTS_N_INSNS (1), /* fadd, fsub */
268 COSTS_N_INSNS (1), /* fcmp */
269 COSTS_N_INSNS (1), /* fmov, fmovr */
270 COSTS_N_INSNS (1), /* fmul */
271 COSTS_N_INSNS (1), /* fdivs */
272 COSTS_N_INSNS (1), /* fdivd */
273 COSTS_N_INSNS (1), /* fsqrts */
274 COSTS_N_INSNS (1), /* fsqrtd */
275 COSTS_N_INSNS (5), /* imul */
276 COSTS_N_INSNS (5), /* imulX */
277 0, /* imul bit factor */
278 COSTS_N_INSNS (5), /* idiv */
279 COSTS_N_INSNS (5), /* idivX */
280 COSTS_N_INSNS (1), /* movcc/movr */
281 0, /* shift penalty */
285 struct processor_costs ultrasparc_costs
= {
286 COSTS_N_INSNS (2), /* int load */
287 COSTS_N_INSNS (3), /* int signed load */
288 COSTS_N_INSNS (2), /* int zeroed load */
289 COSTS_N_INSNS (2), /* float load */
290 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
291 COSTS_N_INSNS (4), /* fadd, fsub */
292 COSTS_N_INSNS (1), /* fcmp */
293 COSTS_N_INSNS (2), /* fmov, fmovr */
294 COSTS_N_INSNS (4), /* fmul */
295 COSTS_N_INSNS (13), /* fdivs */
296 COSTS_N_INSNS (23), /* fdivd */
297 COSTS_N_INSNS (13), /* fsqrts */
298 COSTS_N_INSNS (23), /* fsqrtd */
299 COSTS_N_INSNS (4), /* imul */
300 COSTS_N_INSNS (4), /* imulX */
301 2, /* imul bit factor */
302 COSTS_N_INSNS (37), /* idiv */
303 COSTS_N_INSNS (68), /* idivX */
304 COSTS_N_INSNS (2), /* movcc/movr */
305 2, /* shift penalty */
309 struct processor_costs ultrasparc3_costs
= {
310 COSTS_N_INSNS (2), /* int load */
311 COSTS_N_INSNS (3), /* int signed load */
312 COSTS_N_INSNS (3), /* int zeroed load */
313 COSTS_N_INSNS (2), /* float load */
314 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
315 COSTS_N_INSNS (4), /* fadd, fsub */
316 COSTS_N_INSNS (5), /* fcmp */
317 COSTS_N_INSNS (3), /* fmov, fmovr */
318 COSTS_N_INSNS (4), /* fmul */
319 COSTS_N_INSNS (17), /* fdivs */
320 COSTS_N_INSNS (20), /* fdivd */
321 COSTS_N_INSNS (20), /* fsqrts */
322 COSTS_N_INSNS (29), /* fsqrtd */
323 COSTS_N_INSNS (6), /* imul */
324 COSTS_N_INSNS (6), /* imulX */
325 0, /* imul bit factor */
326 COSTS_N_INSNS (40), /* idiv */
327 COSTS_N_INSNS (71), /* idivX */
328 COSTS_N_INSNS (2), /* movcc/movr */
329 0, /* shift penalty */
333 struct processor_costs niagara_costs
= {
334 COSTS_N_INSNS (3), /* int load */
335 COSTS_N_INSNS (3), /* int signed load */
336 COSTS_N_INSNS (3), /* int zeroed load */
337 COSTS_N_INSNS (9), /* float load */
338 COSTS_N_INSNS (8), /* fmov, fneg, fabs */
339 COSTS_N_INSNS (8), /* fadd, fsub */
340 COSTS_N_INSNS (26), /* fcmp */
341 COSTS_N_INSNS (8), /* fmov, fmovr */
342 COSTS_N_INSNS (29), /* fmul */
343 COSTS_N_INSNS (54), /* fdivs */
344 COSTS_N_INSNS (83), /* fdivd */
345 COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */
346 COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */
347 COSTS_N_INSNS (11), /* imul */
348 COSTS_N_INSNS (11), /* imulX */
349 0, /* imul bit factor */
350 COSTS_N_INSNS (72), /* idiv */
351 COSTS_N_INSNS (72), /* idivX */
352 COSTS_N_INSNS (1), /* movcc/movr */
353 0, /* shift penalty */
357 struct processor_costs niagara2_costs
= {
358 COSTS_N_INSNS (3), /* int load */
359 COSTS_N_INSNS (3), /* int signed load */
360 COSTS_N_INSNS (3), /* int zeroed load */
361 COSTS_N_INSNS (3), /* float load */
362 COSTS_N_INSNS (6), /* fmov, fneg, fabs */
363 COSTS_N_INSNS (6), /* fadd, fsub */
364 COSTS_N_INSNS (6), /* fcmp */
365 COSTS_N_INSNS (6), /* fmov, fmovr */
366 COSTS_N_INSNS (6), /* fmul */
367 COSTS_N_INSNS (19), /* fdivs */
368 COSTS_N_INSNS (33), /* fdivd */
369 COSTS_N_INSNS (19), /* fsqrts */
370 COSTS_N_INSNS (33), /* fsqrtd */
371 COSTS_N_INSNS (5), /* imul */
372 COSTS_N_INSNS (5), /* imulX */
373 0, /* imul bit factor */
374 COSTS_N_INSNS (26), /* idiv, average of 12 - 41 cycle range */
375 COSTS_N_INSNS (26), /* idivX, average of 12 - 41 cycle range */
376 COSTS_N_INSNS (1), /* movcc/movr */
377 0, /* shift penalty */
381 struct processor_costs niagara3_costs
= {
382 COSTS_N_INSNS (3), /* int load */
383 COSTS_N_INSNS (3), /* int signed load */
384 COSTS_N_INSNS (3), /* int zeroed load */
385 COSTS_N_INSNS (3), /* float load */
386 COSTS_N_INSNS (9), /* fmov, fneg, fabs */
387 COSTS_N_INSNS (9), /* fadd, fsub */
388 COSTS_N_INSNS (9), /* fcmp */
389 COSTS_N_INSNS (9), /* fmov, fmovr */
390 COSTS_N_INSNS (9), /* fmul */
391 COSTS_N_INSNS (23), /* fdivs */
392 COSTS_N_INSNS (37), /* fdivd */
393 COSTS_N_INSNS (23), /* fsqrts */
394 COSTS_N_INSNS (37), /* fsqrtd */
395 COSTS_N_INSNS (9), /* imul */
396 COSTS_N_INSNS (9), /* imulX */
397 0, /* imul bit factor */
398 COSTS_N_INSNS (31), /* idiv, average of 17 - 45 cycle range */
399 COSTS_N_INSNS (30), /* idivX, average of 16 - 44 cycle range */
400 COSTS_N_INSNS (1), /* movcc/movr */
401 0, /* shift penalty */
405 struct processor_costs niagara4_costs
= {
406 COSTS_N_INSNS (5), /* int load */
407 COSTS_N_INSNS (5), /* int signed load */
408 COSTS_N_INSNS (5), /* int zeroed load */
409 COSTS_N_INSNS (5), /* float load */
410 COSTS_N_INSNS (11), /* fmov, fneg, fabs */
411 COSTS_N_INSNS (11), /* fadd, fsub */
412 COSTS_N_INSNS (11), /* fcmp */
413 COSTS_N_INSNS (11), /* fmov, fmovr */
414 COSTS_N_INSNS (11), /* fmul */
415 COSTS_N_INSNS (24), /* fdivs */
416 COSTS_N_INSNS (37), /* fdivd */
417 COSTS_N_INSNS (24), /* fsqrts */
418 COSTS_N_INSNS (37), /* fsqrtd */
419 COSTS_N_INSNS (12), /* imul */
420 COSTS_N_INSNS (12), /* imulX */
421 0, /* imul bit factor */
422 COSTS_N_INSNS (50), /* idiv, average of 41 - 60 cycle range */
423 COSTS_N_INSNS (35), /* idivX, average of 26 - 44 cycle range */
424 COSTS_N_INSNS (1), /* movcc/movr */
425 0, /* shift penalty */
429 struct processor_costs niagara7_costs
= {
430 COSTS_N_INSNS (5), /* int load */
431 COSTS_N_INSNS (5), /* int signed load */
432 COSTS_N_INSNS (5), /* int zeroed load */
433 COSTS_N_INSNS (5), /* float load */
434 COSTS_N_INSNS (11), /* fmov, fneg, fabs */
435 COSTS_N_INSNS (11), /* fadd, fsub */
436 COSTS_N_INSNS (11), /* fcmp */
437 COSTS_N_INSNS (11), /* fmov, fmovr */
438 COSTS_N_INSNS (11), /* fmul */
439 COSTS_N_INSNS (24), /* fdivs */
440 COSTS_N_INSNS (37), /* fdivd */
441 COSTS_N_INSNS (24), /* fsqrts */
442 COSTS_N_INSNS (37), /* fsqrtd */
443 COSTS_N_INSNS (12), /* imul */
444 COSTS_N_INSNS (12), /* imulX */
445 0, /* imul bit factor */
446 COSTS_N_INSNS (51), /* idiv, average of 42 - 61 cycle range */
447 COSTS_N_INSNS (35), /* idivX, average of 26 - 44 cycle range */
448 COSTS_N_INSNS (1), /* movcc/movr */
449 0, /* shift penalty */
453 struct processor_costs m8_costs
= {
454 COSTS_N_INSNS (3), /* int load */
455 COSTS_N_INSNS (3), /* int signed load */
456 COSTS_N_INSNS (3), /* int zeroed load */
457 COSTS_N_INSNS (3), /* float load */
458 COSTS_N_INSNS (9), /* fmov, fneg, fabs */
459 COSTS_N_INSNS (9), /* fadd, fsub */
460 COSTS_N_INSNS (9), /* fcmp */
461 COSTS_N_INSNS (9), /* fmov, fmovr */
462 COSTS_N_INSNS (9), /* fmul */
463 COSTS_N_INSNS (26), /* fdivs */
464 COSTS_N_INSNS (30), /* fdivd */
465 COSTS_N_INSNS (33), /* fsqrts */
466 COSTS_N_INSNS (41), /* fsqrtd */
467 COSTS_N_INSNS (12), /* imul */
468 COSTS_N_INSNS (10), /* imulX */
469 0, /* imul bit factor */
470 COSTS_N_INSNS (57), /* udiv/sdiv */
471 COSTS_N_INSNS (30), /* udivx/sdivx */
472 COSTS_N_INSNS (1), /* movcc/movr */
473 0, /* shift penalty */
476 static const struct processor_costs
*sparc_costs
= &cypress_costs
;
478 #ifdef HAVE_AS_RELAX_OPTION
479 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
480 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
481 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
482 somebody does not branch between the sethi and jmp. */
483 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
485 #define LEAF_SIBCALL_SLOT_RESERVED_P \
486 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
489 /* Vector to say how input registers are mapped to output registers.
490 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
491 eliminate it. You must use -fomit-frame-pointer to get that. */
492 char leaf_reg_remap
[] =
493 { 0, 1, 2, 3, 4, 5, 6, 7,
494 -1, -1, -1, -1, -1, -1, 14, -1,
495 -1, -1, -1, -1, -1, -1, -1, -1,
496 8, 9, 10, 11, 12, 13, -1, 15,
498 32, 33, 34, 35, 36, 37, 38, 39,
499 40, 41, 42, 43, 44, 45, 46, 47,
500 48, 49, 50, 51, 52, 53, 54, 55,
501 56, 57, 58, 59, 60, 61, 62, 63,
502 64, 65, 66, 67, 68, 69, 70, 71,
503 72, 73, 74, 75, 76, 77, 78, 79,
504 80, 81, 82, 83, 84, 85, 86, 87,
505 88, 89, 90, 91, 92, 93, 94, 95,
506 96, 97, 98, 99, 100, 101, 102};
508 /* Vector, indexed by hard register number, which contains 1
509 for a register that is allowable in a candidate for leaf
510 function treatment. */
511 char sparc_leaf_regs
[] =
512 { 1, 1, 1, 1, 1, 1, 1, 1,
513 0, 0, 0, 0, 0, 0, 1, 0,
514 0, 0, 0, 0, 0, 0, 0, 0,
515 1, 1, 1, 1, 1, 1, 0, 1,
516 1, 1, 1, 1, 1, 1, 1, 1,
517 1, 1, 1, 1, 1, 1, 1, 1,
518 1, 1, 1, 1, 1, 1, 1, 1,
519 1, 1, 1, 1, 1, 1, 1, 1,
520 1, 1, 1, 1, 1, 1, 1, 1,
521 1, 1, 1, 1, 1, 1, 1, 1,
522 1, 1, 1, 1, 1, 1, 1, 1,
523 1, 1, 1, 1, 1, 1, 1, 1,
524 1, 1, 1, 1, 1, 1, 1};
526 struct GTY(()) machine_function
528 /* Size of the frame of the function. */
529 HOST_WIDE_INT frame_size
;
531 /* Size of the frame of the function minus the register window save area
532 and the outgoing argument area. */
533 HOST_WIDE_INT apparent_frame_size
;
535 /* Register we pretend the frame pointer is allocated to. Normally, this
536 is %fp, but if we are in a leaf procedure, this is (%sp + offset). We
537 record "offset" separately as it may be too big for (reg + disp). */
539 HOST_WIDE_INT frame_base_offset
;
541 /* Number of global or FP registers to be saved (as 4-byte quantities). */
542 int n_global_fp_regs
;
544 /* True if the current function is leaf and uses only leaf regs,
545 so that the SPARC leaf function optimization can be applied.
546 Private version of crtl->uses_only_leaf_regs, see
547 sparc_expand_prologue for the rationale. */
550 /* True if the prologue saves local or in registers. */
551 bool save_local_in_regs_p
;
553 /* True if the data calculated by sparc_expand_prologue are valid. */
554 bool prologue_data_valid_p
;
557 #define sparc_frame_size cfun->machine->frame_size
558 #define sparc_apparent_frame_size cfun->machine->apparent_frame_size
559 #define sparc_frame_base_reg cfun->machine->frame_base_reg
560 #define sparc_frame_base_offset cfun->machine->frame_base_offset
561 #define sparc_n_global_fp_regs cfun->machine->n_global_fp_regs
562 #define sparc_leaf_function_p cfun->machine->leaf_function_p
563 #define sparc_save_local_in_regs_p cfun->machine->save_local_in_regs_p
564 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
566 /* 1 if the next opcode is to be specially indented. */
567 int sparc_indent_opcode
= 0;
569 static void sparc_option_override (void);
570 static void sparc_init_modes (void);
571 static int function_arg_slotno (const CUMULATIVE_ARGS
*, machine_mode
,
572 const_tree
, bool, bool, int *, int *);
574 static int supersparc_adjust_cost (rtx_insn
*, int, rtx_insn
*, int);
575 static int hypersparc_adjust_cost (rtx_insn
*, int, rtx_insn
*, int);
577 static void sparc_emit_set_const32 (rtx
, rtx
);
578 static void sparc_emit_set_const64 (rtx
, rtx
);
579 static void sparc_output_addr_vec (rtx
);
580 static void sparc_output_addr_diff_vec (rtx
);
581 static void sparc_output_deferred_case_vectors (void);
582 static bool sparc_legitimate_address_p (machine_mode
, rtx
, bool);
583 static bool sparc_legitimate_constant_p (machine_mode
, rtx
);
584 static rtx
sparc_builtin_saveregs (void);
585 static int epilogue_renumber (rtx
*, int);
586 static bool sparc_assemble_integer (rtx
, unsigned int, int);
587 static int set_extends (rtx_insn
*);
588 static void sparc_asm_function_prologue (FILE *);
589 static void sparc_asm_function_epilogue (FILE *);
590 #ifdef TARGET_SOLARIS
591 static void sparc_solaris_elf_asm_named_section (const char *, unsigned int,
592 tree
) ATTRIBUTE_UNUSED
;
594 static int sparc_adjust_cost (rtx_insn
*, int, rtx_insn
*, int, unsigned int);
595 static int sparc_issue_rate (void);
596 static void sparc_sched_init (FILE *, int, int);
597 static int sparc_use_sched_lookahead (void);
599 static void emit_soft_tfmode_libcall (const char *, int, rtx
*);
600 static void emit_soft_tfmode_binop (enum rtx_code
, rtx
*);
601 static void emit_soft_tfmode_unop (enum rtx_code
, rtx
*);
602 static void emit_soft_tfmode_cvt (enum rtx_code
, rtx
*);
603 static void emit_hard_tfmode_operation (enum rtx_code
, rtx
*);
605 static bool sparc_function_ok_for_sibcall (tree
, tree
);
606 static void sparc_init_libfuncs (void);
607 static void sparc_init_builtins (void);
608 static void sparc_fpu_init_builtins (void);
609 static void sparc_vis_init_builtins (void);
610 static tree
sparc_builtin_decl (unsigned, bool);
611 static rtx
sparc_expand_builtin (tree
, rtx
, rtx
, machine_mode
, int);
612 static tree
sparc_fold_builtin (tree
, int, tree
*, bool);
613 static void sparc_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
614 HOST_WIDE_INT
, tree
);
615 static bool sparc_can_output_mi_thunk (const_tree
, HOST_WIDE_INT
,
616 HOST_WIDE_INT
, const_tree
);
617 static struct machine_function
* sparc_init_machine_status (void);
618 static bool sparc_cannot_force_const_mem (machine_mode
, rtx
);
619 static rtx
sparc_tls_get_addr (void);
620 static rtx
sparc_tls_got (void);
621 static int sparc_register_move_cost (machine_mode
,
622 reg_class_t
, reg_class_t
);
623 static bool sparc_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
624 static rtx
sparc_function_value (const_tree
, const_tree
, bool);
625 static rtx
sparc_libcall_value (machine_mode
, const_rtx
);
626 static bool sparc_function_value_regno_p (const unsigned int);
627 static rtx
sparc_struct_value_rtx (tree
, int);
628 static machine_mode
sparc_promote_function_mode (const_tree
, machine_mode
,
629 int *, const_tree
, int);
630 static bool sparc_return_in_memory (const_tree
, const_tree
);
631 static bool sparc_strict_argument_naming (cumulative_args_t
);
632 static void sparc_va_start (tree
, rtx
);
633 static tree
sparc_gimplify_va_arg (tree
, tree
, gimple_seq
*, gimple_seq
*);
634 static bool sparc_vector_mode_supported_p (machine_mode
);
635 static bool sparc_tls_referenced_p (rtx
);
636 static rtx
sparc_legitimize_tls_address (rtx
);
637 static rtx
sparc_legitimize_pic_address (rtx
, rtx
);
638 static rtx
sparc_legitimize_address (rtx
, rtx
, machine_mode
);
639 static rtx
sparc_delegitimize_address (rtx
);
640 static bool sparc_mode_dependent_address_p (const_rtx
, addr_space_t
);
641 static bool sparc_pass_by_reference (cumulative_args_t
,
642 machine_mode
, const_tree
, bool);
643 static void sparc_function_arg_advance (cumulative_args_t
,
644 machine_mode
, const_tree
, bool);
645 static rtx
sparc_function_arg_1 (cumulative_args_t
,
646 machine_mode
, const_tree
, bool, bool);
647 static rtx
sparc_function_arg (cumulative_args_t
,
648 machine_mode
, const_tree
, bool);
649 static rtx
sparc_function_incoming_arg (cumulative_args_t
,
650 machine_mode
, const_tree
, bool);
651 static pad_direction
sparc_function_arg_padding (machine_mode
, const_tree
);
652 static unsigned int sparc_function_arg_boundary (machine_mode
,
654 static int sparc_arg_partial_bytes (cumulative_args_t
,
655 machine_mode
, tree
, bool);
656 static void sparc_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
657 static void sparc_file_end (void);
658 static bool sparc_frame_pointer_required (void);
659 static bool sparc_can_eliminate (const int, const int);
660 static rtx
sparc_builtin_setjmp_frame_value (void);
661 static void sparc_conditional_register_usage (void);
662 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
663 static const char *sparc_mangle_type (const_tree
);
665 static void sparc_trampoline_init (rtx
, tree
, rtx
);
666 static machine_mode
sparc_preferred_simd_mode (scalar_mode
);
667 static reg_class_t
sparc_preferred_reload_class (rtx x
, reg_class_t rclass
);
668 static bool sparc_lra_p (void);
669 static bool sparc_print_operand_punct_valid_p (unsigned char);
670 static void sparc_print_operand (FILE *, rtx
, int);
671 static void sparc_print_operand_address (FILE *, machine_mode
, rtx
);
672 static reg_class_t
sparc_secondary_reload (bool, rtx
, reg_class_t
,
674 secondary_reload_info
*);
675 static bool sparc_secondary_memory_needed (machine_mode
, reg_class_t
,
677 static machine_mode
sparc_secondary_memory_needed_mode (machine_mode
);
678 static scalar_int_mode
sparc_cstore_mode (enum insn_code icode
);
679 static void sparc_atomic_assign_expand_fenv (tree
*, tree
*, tree
*);
680 static bool sparc_fixed_condition_code_regs (unsigned int *, unsigned int *);
681 static unsigned int sparc_min_arithmetic_precision (void);
682 static unsigned int sparc_hard_regno_nregs (unsigned int, machine_mode
);
683 static bool sparc_hard_regno_mode_ok (unsigned int, machine_mode
);
684 static bool sparc_modes_tieable_p (machine_mode
, machine_mode
);
685 static bool sparc_can_change_mode_class (machine_mode
, machine_mode
,
688 #ifdef SUBTARGET_ATTRIBUTE_TABLE
689 /* Table of valid machine attributes. */
690 static const struct attribute_spec sparc_attribute_table
[] =
692 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
694 SUBTARGET_ATTRIBUTE_TABLE
,
695 { NULL
, 0, 0, false, false, false, NULL
, false }
699 /* Option handling. */
702 enum cmodel sparc_cmodel
;
704 char sparc_hard_reg_printed
[8];
706 /* Initialize the GCC target structure. */
708 /* The default is to use .half rather than .short for aligned HI objects. */
709 #undef TARGET_ASM_ALIGNED_HI_OP
710 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
712 #undef TARGET_ASM_UNALIGNED_HI_OP
713 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
714 #undef TARGET_ASM_UNALIGNED_SI_OP
715 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
716 #undef TARGET_ASM_UNALIGNED_DI_OP
717 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
719 /* The target hook has to handle DI-mode values. */
720 #undef TARGET_ASM_INTEGER
721 #define TARGET_ASM_INTEGER sparc_assemble_integer
723 #undef TARGET_ASM_FUNCTION_PROLOGUE
724 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
725 #undef TARGET_ASM_FUNCTION_EPILOGUE
726 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
728 #undef TARGET_SCHED_ADJUST_COST
729 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
730 #undef TARGET_SCHED_ISSUE_RATE
731 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
732 #undef TARGET_SCHED_INIT
733 #define TARGET_SCHED_INIT sparc_sched_init
734 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
735 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
737 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
738 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
740 #undef TARGET_INIT_LIBFUNCS
741 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
743 #undef TARGET_LEGITIMIZE_ADDRESS
744 #define TARGET_LEGITIMIZE_ADDRESS sparc_legitimize_address
745 #undef TARGET_DELEGITIMIZE_ADDRESS
746 #define TARGET_DELEGITIMIZE_ADDRESS sparc_delegitimize_address
747 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
748 #define TARGET_MODE_DEPENDENT_ADDRESS_P sparc_mode_dependent_address_p
750 #undef TARGET_INIT_BUILTINS
751 #define TARGET_INIT_BUILTINS sparc_init_builtins
752 #undef TARGET_BUILTIN_DECL
753 #define TARGET_BUILTIN_DECL sparc_builtin_decl
754 #undef TARGET_EXPAND_BUILTIN
755 #define TARGET_EXPAND_BUILTIN sparc_expand_builtin
756 #undef TARGET_FOLD_BUILTIN
757 #define TARGET_FOLD_BUILTIN sparc_fold_builtin
760 #undef TARGET_HAVE_TLS
761 #define TARGET_HAVE_TLS true
764 #undef TARGET_CANNOT_FORCE_CONST_MEM
765 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
767 #undef TARGET_ASM_OUTPUT_MI_THUNK
768 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
769 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
770 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
772 #undef TARGET_RTX_COSTS
773 #define TARGET_RTX_COSTS sparc_rtx_costs
774 #undef TARGET_ADDRESS_COST
775 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
776 #undef TARGET_REGISTER_MOVE_COST
777 #define TARGET_REGISTER_MOVE_COST sparc_register_move_cost
779 #undef TARGET_PROMOTE_FUNCTION_MODE
780 #define TARGET_PROMOTE_FUNCTION_MODE sparc_promote_function_mode
782 #undef TARGET_FUNCTION_VALUE
783 #define TARGET_FUNCTION_VALUE sparc_function_value
784 #undef TARGET_LIBCALL_VALUE
785 #define TARGET_LIBCALL_VALUE sparc_libcall_value
786 #undef TARGET_FUNCTION_VALUE_REGNO_P
787 #define TARGET_FUNCTION_VALUE_REGNO_P sparc_function_value_regno_p
789 #undef TARGET_STRUCT_VALUE_RTX
790 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
791 #undef TARGET_RETURN_IN_MEMORY
792 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
793 #undef TARGET_MUST_PASS_IN_STACK
794 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
795 #undef TARGET_PASS_BY_REFERENCE
796 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
797 #undef TARGET_ARG_PARTIAL_BYTES
798 #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
799 #undef TARGET_FUNCTION_ARG_ADVANCE
800 #define TARGET_FUNCTION_ARG_ADVANCE sparc_function_arg_advance
801 #undef TARGET_FUNCTION_ARG
802 #define TARGET_FUNCTION_ARG sparc_function_arg
803 #undef TARGET_FUNCTION_INCOMING_ARG
804 #define TARGET_FUNCTION_INCOMING_ARG sparc_function_incoming_arg
805 #undef TARGET_FUNCTION_ARG_PADDING
806 #define TARGET_FUNCTION_ARG_PADDING sparc_function_arg_padding
807 #undef TARGET_FUNCTION_ARG_BOUNDARY
808 #define TARGET_FUNCTION_ARG_BOUNDARY sparc_function_arg_boundary
810 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
811 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
812 #undef TARGET_STRICT_ARGUMENT_NAMING
813 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
815 #undef TARGET_EXPAND_BUILTIN_VA_START
816 #define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start
817 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
818 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
820 #undef TARGET_VECTOR_MODE_SUPPORTED_P
821 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
823 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
824 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE sparc_preferred_simd_mode
826 #ifdef SUBTARGET_INSERT_ATTRIBUTES
827 #undef TARGET_INSERT_ATTRIBUTES
828 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
831 #ifdef SUBTARGET_ATTRIBUTE_TABLE
832 #undef TARGET_ATTRIBUTE_TABLE
833 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
836 #undef TARGET_OPTION_OVERRIDE
837 #define TARGET_OPTION_OVERRIDE sparc_option_override
839 #ifdef TARGET_THREAD_SSP_OFFSET
840 #undef TARGET_STACK_PROTECT_GUARD
841 #define TARGET_STACK_PROTECT_GUARD hook_tree_void_null
844 #if TARGET_GNU_TLS && defined(HAVE_AS_SPARC_UA_PCREL)
845 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
846 #define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel
849 #undef TARGET_ASM_FILE_END
850 #define TARGET_ASM_FILE_END sparc_file_end
852 #undef TARGET_FRAME_POINTER_REQUIRED
853 #define TARGET_FRAME_POINTER_REQUIRED sparc_frame_pointer_required
855 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
856 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE sparc_builtin_setjmp_frame_value
858 #undef TARGET_CAN_ELIMINATE
859 #define TARGET_CAN_ELIMINATE sparc_can_eliminate
861 #undef TARGET_PREFERRED_RELOAD_CLASS
862 #define TARGET_PREFERRED_RELOAD_CLASS sparc_preferred_reload_class
864 #undef TARGET_SECONDARY_RELOAD
865 #define TARGET_SECONDARY_RELOAD sparc_secondary_reload
866 #undef TARGET_SECONDARY_MEMORY_NEEDED
867 #define TARGET_SECONDARY_MEMORY_NEEDED sparc_secondary_memory_needed
868 #undef TARGET_SECONDARY_MEMORY_NEEDED_MODE
869 #define TARGET_SECONDARY_MEMORY_NEEDED_MODE sparc_secondary_memory_needed_mode
871 #undef TARGET_CONDITIONAL_REGISTER_USAGE
872 #define TARGET_CONDITIONAL_REGISTER_USAGE sparc_conditional_register_usage
874 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
875 #undef TARGET_MANGLE_TYPE
876 #define TARGET_MANGLE_TYPE sparc_mangle_type
880 #define TARGET_LRA_P sparc_lra_p
882 #undef TARGET_LEGITIMATE_ADDRESS_P
883 #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p
885 #undef TARGET_LEGITIMATE_CONSTANT_P
886 #define TARGET_LEGITIMATE_CONSTANT_P sparc_legitimate_constant_p
888 #undef TARGET_TRAMPOLINE_INIT
889 #define TARGET_TRAMPOLINE_INIT sparc_trampoline_init
891 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
892 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sparc_print_operand_punct_valid_p
893 #undef TARGET_PRINT_OPERAND
894 #define TARGET_PRINT_OPERAND sparc_print_operand
895 #undef TARGET_PRINT_OPERAND_ADDRESS
896 #define TARGET_PRINT_OPERAND_ADDRESS sparc_print_operand_address
898 /* The value stored by LDSTUB. */
899 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
900 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 0xff
902 #undef TARGET_CSTORE_MODE
903 #define TARGET_CSTORE_MODE sparc_cstore_mode
905 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
906 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV sparc_atomic_assign_expand_fenv
908 #undef TARGET_FIXED_CONDITION_CODE_REGS
909 #define TARGET_FIXED_CONDITION_CODE_REGS sparc_fixed_condition_code_regs
911 #undef TARGET_MIN_ARITHMETIC_PRECISION
912 #define TARGET_MIN_ARITHMETIC_PRECISION sparc_min_arithmetic_precision
914 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
915 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
917 #undef TARGET_HARD_REGNO_NREGS
918 #define TARGET_HARD_REGNO_NREGS sparc_hard_regno_nregs
919 #undef TARGET_HARD_REGNO_MODE_OK
920 #define TARGET_HARD_REGNO_MODE_OK sparc_hard_regno_mode_ok
922 #undef TARGET_MODES_TIEABLE_P
923 #define TARGET_MODES_TIEABLE_P sparc_modes_tieable_p
925 #undef TARGET_CAN_CHANGE_MODE_CLASS
926 #define TARGET_CAN_CHANGE_MODE_CLASS sparc_can_change_mode_class
928 struct gcc_target targetm
= TARGET_INITIALIZER
;
930 /* Return the memory reference contained in X if any, zero otherwise. */
935 if (GET_CODE (x
) == SIGN_EXTEND
|| GET_CODE (x
) == ZERO_EXTEND
)
944 /* We use a machine specific pass to enable workarounds for errata.
946 We need to have the (essentially) final form of the insn stream in order
947 to properly detect the various hazards. Therefore, this machine specific
948 pass runs as late as possible. */
950 /* True if INSN is a md pattern or asm statement. */
951 #define USEFUL_INSN_P(INSN) \
952 (NONDEBUG_INSN_P (INSN) \
953 && GET_CODE (PATTERN (INSN)) != USE \
954 && GET_CODE (PATTERN (INSN)) != CLOBBER)
957 sparc_do_work_around_errata (void)
959 rtx_insn
*insn
, *next
;
961 /* Force all instructions to be split into their final form. */
962 split_all_insns_noflow ();
964 /* Now look for specific patterns in the insn stream. */
965 for (insn
= get_insns (); insn
; insn
= next
)
967 bool insert_nop
= false;
970 /* Look into the instruction in a delay slot. */
971 if (NONJUMP_INSN_P (insn
))
972 if (rtx_sequence
*seq
= dyn_cast
<rtx_sequence
*> (PATTERN (insn
)))
973 insn
= seq
->insn (1);
975 /* Look for either of these two sequences:
978 1. store of word size or less (e.g. st / stb / sth / stf)
979 2. any single instruction that is not a load or store
980 3. any store instruction (e.g. st / stb / sth / stf / std / stdf)
983 1. store of double word size (e.g. std / stdf)
984 2. any store instruction (e.g. st / stb / sth / stf / std / stdf) */
986 && NONJUMP_INSN_P (insn
)
987 && (set
= single_set (insn
)) != NULL_RTX
988 && MEM_P (SET_DEST (set
)))
990 /* Sequence B begins with a double-word store. */
991 bool seq_b
= GET_MODE_SIZE (GET_MODE (SET_DEST (set
))) == 8;
995 next
= next_active_insn (insn
);
999 for (after
= next
, i
= 0; i
< 2; i
++)
1001 /* Skip empty assembly statements. */
1002 if ((GET_CODE (PATTERN (after
)) == UNSPEC_VOLATILE
)
1003 || (USEFUL_INSN_P (after
)
1004 && (asm_noperands (PATTERN (after
))>=0)
1005 && !strcmp (decode_asm_operands (PATTERN (after
),
1008 after
= next_active_insn (after
);
1012 /* If the insn is a branch, then it cannot be problematic. */
1013 if (!NONJUMP_INSN_P (after
)
1014 || GET_CODE (PATTERN (after
)) == SEQUENCE
)
1017 /* Sequence B is only two instructions long. */
1020 /* Add NOP if followed by a store. */
1021 if ((set
= single_set (after
)) != NULL_RTX
1022 && MEM_P (SET_DEST (set
)))
1025 /* Otherwise it is ok. */
1029 /* If the second instruction is a load or a store,
1030 then the sequence cannot be problematic. */
1033 if (((set
= single_set (after
)) != NULL_RTX
)
1034 && (MEM_P (SET_DEST (set
)) || MEM_P (SET_SRC (set
))))
1037 after
= next_active_insn (after
);
1042 /* Add NOP if third instruction is a store. */
1044 && ((set
= single_set (after
)) != NULL_RTX
)
1045 && MEM_P (SET_DEST (set
)))
1050 /* Look for a single-word load into an odd-numbered FP register. */
1051 if (sparc_fix_at697f
1052 && NONJUMP_INSN_P (insn
)
1053 && (set
= single_set (insn
)) != NULL_RTX
1054 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
1055 && MEM_P (SET_SRC (set
))
1056 && REG_P (SET_DEST (set
))
1057 && REGNO (SET_DEST (set
)) > 31
1058 && REGNO (SET_DEST (set
)) % 2 != 0)
1060 /* The wrong dependency is on the enclosing double register. */
1061 const unsigned int x
= REGNO (SET_DEST (set
)) - 1;
1062 unsigned int src1
, src2
, dest
;
1065 next
= next_active_insn (insn
);
1068 /* If the insn is a branch, then it cannot be problematic. */
1069 if (!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) == SEQUENCE
)
1072 extract_insn (next
);
1073 code
= INSN_CODE (next
);
1077 case CODE_FOR_adddf3
:
1078 case CODE_FOR_subdf3
:
1079 case CODE_FOR_muldf3
:
1080 case CODE_FOR_divdf3
:
1081 dest
= REGNO (recog_data
.operand
[0]);
1082 src1
= REGNO (recog_data
.operand
[1]);
1083 src2
= REGNO (recog_data
.operand
[2]);
1088 FPOPd %f{x,y}, %f{y,x}, %f{x,y} */
1089 if ((src1
== x
|| src2
== x
)
1090 && (dest
== src1
|| dest
== src2
))
1097 FPOPd %fx, %fx, %fx */
1100 && (code
== CODE_FOR_adddf3
|| code
== CODE_FOR_muldf3
))
1105 case CODE_FOR_sqrtdf2
:
1106 dest
= REGNO (recog_data
.operand
[0]);
1107 src1
= REGNO (recog_data
.operand
[1]);
1111 if (src1
== x
&& dest
== src1
)
1120 /* Look for a single-word load into an integer register. */
1121 else if (sparc_fix_ut699
1122 && NONJUMP_INSN_P (insn
)
1123 && (set
= single_set (insn
)) != NULL_RTX
1124 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) <= 4
1125 && mem_ref (SET_SRC (set
)) != NULL_RTX
1126 && REG_P (SET_DEST (set
))
1127 && REGNO (SET_DEST (set
)) < 32)
1129 /* There is no problem if the second memory access has a data
1130 dependency on the first single-cycle load. */
1131 rtx x
= SET_DEST (set
);
1133 next
= next_active_insn (insn
);
1136 /* If the insn is a branch, then it cannot be problematic. */
1137 if (!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) == SEQUENCE
)
1140 /* Look for a second memory access to/from an integer register. */
1141 if ((set
= single_set (next
)) != NULL_RTX
)
1143 rtx src
= SET_SRC (set
);
1144 rtx dest
= SET_DEST (set
);
1147 /* LDD is affected. */
1148 if ((mem
= mem_ref (src
)) != NULL_RTX
1150 && REGNO (dest
) < 32
1151 && !reg_mentioned_p (x
, XEXP (mem
, 0)))
1154 /* STD is *not* affected. */
1155 else if (MEM_P (dest
)
1156 && GET_MODE_SIZE (GET_MODE (dest
)) <= 4
1157 && (src
== CONST0_RTX (GET_MODE (dest
))
1160 && REGNO (src
) != REGNO (x
)))
1161 && !reg_mentioned_p (x
, XEXP (dest
, 0)))
1166 /* Look for a single-word load/operation into an FP register. */
1167 else if (sparc_fix_ut699
1168 && NONJUMP_INSN_P (insn
)
1169 && (set
= single_set (insn
)) != NULL_RTX
1170 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
1171 && REG_P (SET_DEST (set
))
1172 && REGNO (SET_DEST (set
)) > 31)
1174 /* Number of instructions in the problematic window. */
1175 const int n_insns
= 4;
1176 /* The problematic combination is with the sibling FP register. */
1177 const unsigned int x
= REGNO (SET_DEST (set
));
1178 const unsigned int y
= x
^ 1;
1182 next
= next_active_insn (insn
);
1185 /* If the insn is a branch, then it cannot be problematic. */
1186 if (!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) == SEQUENCE
)
1189 /* Look for a second load/operation into the sibling FP register. */
1190 if (!((set
= single_set (next
)) != NULL_RTX
1191 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
1192 && REG_P (SET_DEST (set
))
1193 && REGNO (SET_DEST (set
)) == y
))
1196 /* Look for a (possible) store from the FP register in the next N
1197 instructions, but bail out if it is again modified or if there
1198 is a store from the sibling FP register before this store. */
1199 for (after
= next
, i
= 0; i
< n_insns
; i
++)
1203 after
= next_active_insn (after
);
1207 /* This is a branch with an empty delay slot. */
1208 if (!NONJUMP_INSN_P (after
))
1215 /* This is a branch with a filled delay slot. */
1216 else if (rtx_sequence
*seq
=
1217 dyn_cast
<rtx_sequence
*> (PATTERN (after
)))
1222 after
= seq
->insn (1);
1224 /* This is a regular instruction. */
1228 if (after
&& (set
= single_set (after
)) != NULL_RTX
)
1230 const rtx src
= SET_SRC (set
);
1231 const rtx dest
= SET_DEST (set
);
1232 const unsigned int size
= GET_MODE_SIZE (GET_MODE (dest
));
1234 /* If the FP register is again modified before the store,
1235 then the store isn't affected. */
1237 && (REGNO (dest
) == x
1238 || (REGNO (dest
) == y
&& size
== 8)))
1241 if (MEM_P (dest
) && REG_P (src
))
1243 /* If there is a store from the sibling FP register
1244 before the store, then the store is not affected. */
1245 if (REGNO (src
) == y
|| (REGNO (src
) == x
&& size
== 8))
1248 /* Otherwise, the store is affected. */
1249 if (REGNO (src
) == x
&& size
== 4)
1257 /* If we have a branch in the first M instructions, then we
1258 cannot see the (M+2)th instruction so we play safe. */
1259 if (branch_p
&& i
<= (n_insns
- 2))
1268 next
= NEXT_INSN (insn
);
1271 emit_insn_before (gen_nop (), next
);
1279 const pass_data pass_data_work_around_errata
=
1281 RTL_PASS
, /* type */
1282 "errata", /* name */
1283 OPTGROUP_NONE
, /* optinfo_flags */
1284 TV_MACH_DEP
, /* tv_id */
1285 0, /* properties_required */
1286 0, /* properties_provided */
1287 0, /* properties_destroyed */
1288 0, /* todo_flags_start */
1289 0, /* todo_flags_finish */
1292 class pass_work_around_errata
: public rtl_opt_pass
1295 pass_work_around_errata(gcc::context
*ctxt
)
1296 : rtl_opt_pass(pass_data_work_around_errata
, ctxt
)
1299 /* opt_pass methods: */
1300 virtual bool gate (function
*)
1302 return sparc_fix_at697f
|| sparc_fix_ut699
|| sparc_fix_b2bst
;
1305 virtual unsigned int execute (function
*)
1307 return sparc_do_work_around_errata ();
1310 }; // class pass_work_around_errata
1315 make_pass_work_around_errata (gcc::context
*ctxt
)
1317 return new pass_work_around_errata (ctxt
);
1320 /* Helpers for TARGET_DEBUG_OPTIONS. */
1322 dump_target_flag_bits (const int flags
)
1324 if (flags
& MASK_64BIT
)
1325 fprintf (stderr
, "64BIT ");
1326 if (flags
& MASK_APP_REGS
)
1327 fprintf (stderr
, "APP_REGS ");
1328 if (flags
& MASK_FASTER_STRUCTS
)
1329 fprintf (stderr
, "FASTER_STRUCTS ");
1330 if (flags
& MASK_FLAT
)
1331 fprintf (stderr
, "FLAT ");
1332 if (flags
& MASK_FMAF
)
1333 fprintf (stderr
, "FMAF ");
1334 if (flags
& MASK_FSMULD
)
1335 fprintf (stderr
, "FSMULD ");
1336 if (flags
& MASK_FPU
)
1337 fprintf (stderr
, "FPU ");
1338 if (flags
& MASK_HARD_QUAD
)
1339 fprintf (stderr
, "HARD_QUAD ");
1340 if (flags
& MASK_POPC
)
1341 fprintf (stderr
, "POPC ");
1342 if (flags
& MASK_PTR64
)
1343 fprintf (stderr
, "PTR64 ");
1344 if (flags
& MASK_STACK_BIAS
)
1345 fprintf (stderr
, "STACK_BIAS ");
1346 if (flags
& MASK_UNALIGNED_DOUBLES
)
1347 fprintf (stderr
, "UNALIGNED_DOUBLES ");
1348 if (flags
& MASK_V8PLUS
)
1349 fprintf (stderr
, "V8PLUS ");
1350 if (flags
& MASK_VIS
)
1351 fprintf (stderr
, "VIS ");
1352 if (flags
& MASK_VIS2
)
1353 fprintf (stderr
, "VIS2 ");
1354 if (flags
& MASK_VIS3
)
1355 fprintf (stderr
, "VIS3 ");
1356 if (flags
& MASK_VIS4
)
1357 fprintf (stderr
, "VIS4 ");
1358 if (flags
& MASK_VIS4B
)
1359 fprintf (stderr
, "VIS4B ");
1360 if (flags
& MASK_CBCOND
)
1361 fprintf (stderr
, "CBCOND ");
1362 if (flags
& MASK_DEPRECATED_V8_INSNS
)
1363 fprintf (stderr
, "DEPRECATED_V8_INSNS ");
1364 if (flags
& MASK_SPARCLET
)
1365 fprintf (stderr
, "SPARCLET ");
1366 if (flags
& MASK_SPARCLITE
)
1367 fprintf (stderr
, "SPARCLITE ");
1368 if (flags
& MASK_V8
)
1369 fprintf (stderr
, "V8 ");
1370 if (flags
& MASK_V9
)
1371 fprintf (stderr
, "V9 ");
1375 dump_target_flags (const char *prefix
, const int flags
)
1377 fprintf (stderr
, "%s: (%08x) [ ", prefix
, flags
);
1378 dump_target_flag_bits (flags
);
1379 fprintf(stderr
, "]\n");
1382 /* Validate and override various options, and do some machine dependent
1386 sparc_option_override (void)
1388 static struct code_model
{
1389 const char *const name
;
1390 const enum cmodel value
;
1391 } const cmodels
[] = {
1393 { "medlow", CM_MEDLOW
},
1394 { "medmid", CM_MEDMID
},
1395 { "medany", CM_MEDANY
},
1396 { "embmedany", CM_EMBMEDANY
},
1397 { NULL
, (enum cmodel
) 0 }
1399 const struct code_model
*cmodel
;
1400 /* Map TARGET_CPU_DEFAULT to value for -m{cpu,tune}=. */
1401 static struct cpu_default
{
1403 const enum processor_type processor
;
1404 } const cpu_default
[] = {
1405 /* There must be one entry here for each TARGET_CPU value. */
1406 { TARGET_CPU_sparc
, PROCESSOR_CYPRESS
},
1407 { TARGET_CPU_v8
, PROCESSOR_V8
},
1408 { TARGET_CPU_supersparc
, PROCESSOR_SUPERSPARC
},
1409 { TARGET_CPU_hypersparc
, PROCESSOR_HYPERSPARC
},
1410 { TARGET_CPU_leon
, PROCESSOR_LEON
},
1411 { TARGET_CPU_leon3
, PROCESSOR_LEON3
},
1412 { TARGET_CPU_leon3v7
, PROCESSOR_LEON3V7
},
1413 { TARGET_CPU_sparclite
, PROCESSOR_F930
},
1414 { TARGET_CPU_sparclite86x
, PROCESSOR_SPARCLITE86X
},
1415 { TARGET_CPU_sparclet
, PROCESSOR_TSC701
},
1416 { TARGET_CPU_v9
, PROCESSOR_V9
},
1417 { TARGET_CPU_ultrasparc
, PROCESSOR_ULTRASPARC
},
1418 { TARGET_CPU_ultrasparc3
, PROCESSOR_ULTRASPARC3
},
1419 { TARGET_CPU_niagara
, PROCESSOR_NIAGARA
},
1420 { TARGET_CPU_niagara2
, PROCESSOR_NIAGARA2
},
1421 { TARGET_CPU_niagara3
, PROCESSOR_NIAGARA3
},
1422 { TARGET_CPU_niagara4
, PROCESSOR_NIAGARA4
},
1423 { TARGET_CPU_niagara7
, PROCESSOR_NIAGARA7
},
1424 { TARGET_CPU_m8
, PROCESSOR_M8
},
1425 { -1, PROCESSOR_V7
}
1427 const struct cpu_default
*def
;
1428 /* Table of values for -m{cpu,tune}=. This must match the order of
1429 the enum processor_type in sparc-opts.h. */
1430 static struct cpu_table
{
1431 const char *const name
;
1434 } const cpu_table
[] = {
1435 { "v7", MASK_ISA
|MASK_FSMULD
, 0 },
1436 { "cypress", MASK_ISA
|MASK_FSMULD
, 0 },
1437 { "v8", MASK_ISA
, MASK_V8
},
1438 /* TI TMS390Z55 supersparc */
1439 { "supersparc", MASK_ISA
, MASK_V8
},
1440 { "hypersparc", MASK_ISA
, MASK_V8
},
1441 { "leon", MASK_ISA
|MASK_FSMULD
, MASK_V8
|MASK_LEON
},
1442 { "leon3", MASK_ISA
, MASK_V8
|MASK_LEON3
},
1443 { "leon3v7", MASK_ISA
|MASK_FSMULD
, MASK_LEON3
},
1444 { "sparclite", MASK_ISA
|MASK_FSMULD
, MASK_SPARCLITE
},
1445 /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
1446 { "f930", MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
1447 /* The Fujitsu MB86934 is the recent sparclite chip, with an FPU. */
1448 { "f934", MASK_ISA
|MASK_FSMULD
, MASK_SPARCLITE
},
1449 { "sparclite86x", MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
1450 { "sparclet", MASK_ISA
|MASK_FSMULD
, MASK_SPARCLET
},
1451 /* TEMIC sparclet */
1452 { "tsc701", MASK_ISA
|MASK_FSMULD
, MASK_SPARCLET
},
1453 { "v9", MASK_ISA
, MASK_V9
},
1454 /* UltraSPARC I, II, IIi */
1455 { "ultrasparc", MASK_ISA
,
1456 /* Although insns using %y are deprecated, it is a clear win. */
1457 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
1458 /* UltraSPARC III */
1459 /* ??? Check if %y issue still holds true. */
1460 { "ultrasparc3", MASK_ISA
,
1461 MASK_V9
|MASK_DEPRECATED_V8_INSNS
|MASK_VIS2
},
1463 { "niagara", MASK_ISA
,
1464 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
1466 { "niagara2", MASK_ISA
,
1467 MASK_V9
|MASK_POPC
|MASK_VIS2
},
1469 { "niagara3", MASK_ISA
,
1470 MASK_V9
|MASK_POPC
|MASK_VIS3
|MASK_FMAF
},
1472 { "niagara4", MASK_ISA
,
1473 MASK_V9
|MASK_POPC
|MASK_VIS3
|MASK_FMAF
|MASK_CBCOND
},
1475 { "niagara7", MASK_ISA
,
1476 MASK_V9
|MASK_POPC
|MASK_VIS4
|MASK_FMAF
|MASK_CBCOND
|MASK_SUBXC
},
1479 MASK_V9
|MASK_POPC
|MASK_VIS4
|MASK_FMAF
|MASK_CBCOND
|MASK_SUBXC
|MASK_VIS4B
}
1481 const struct cpu_table
*cpu
;
1484 if (sparc_debug_string
!= NULL
)
1489 p
= ASTRDUP (sparc_debug_string
);
1490 while ((q
= strtok (p
, ",")) != NULL
)
1504 if (! strcmp (q
, "all"))
1505 mask
= MASK_DEBUG_ALL
;
1506 else if (! strcmp (q
, "options"))
1507 mask
= MASK_DEBUG_OPTIONS
;
1509 error ("unknown -mdebug-%s switch", q
);
1512 sparc_debug
&= ~mask
;
1514 sparc_debug
|= mask
;
1518 /* Enable the FsMULd instruction by default if not explicitly specified by
1519 the user. It may be later disabled by the CPU (explicitly or not). */
1520 if (TARGET_FPU
&& !(target_flags_explicit
& MASK_FSMULD
))
1521 target_flags
|= MASK_FSMULD
;
1523 if (TARGET_DEBUG_OPTIONS
)
1525 dump_target_flags("Initial target_flags", target_flags
);
1526 dump_target_flags("target_flags_explicit", target_flags_explicit
);
1529 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1530 SUBTARGET_OVERRIDE_OPTIONS
;
1533 #ifndef SPARC_BI_ARCH
1534 /* Check for unsupported architecture size. */
1535 if (!TARGET_64BIT
!= DEFAULT_ARCH32_P
)
1536 error ("%s is not supported by this configuration",
1537 DEFAULT_ARCH32_P
? "-m64" : "-m32");
1540 /* We force all 64bit archs to use 128 bit long double */
1541 if (TARGET_ARCH64
&& !TARGET_LONG_DOUBLE_128
)
1543 error ("-mlong-double-64 not allowed with -m64");
1544 target_flags
|= MASK_LONG_DOUBLE_128
;
1547 /* Code model selection. */
1548 sparc_cmodel
= SPARC_DEFAULT_CMODEL
;
1550 #ifdef SPARC_BI_ARCH
1552 sparc_cmodel
= CM_32
;
1555 if (sparc_cmodel_string
!= NULL
)
1559 for (cmodel
= &cmodels
[0]; cmodel
->name
; cmodel
++)
1560 if (strcmp (sparc_cmodel_string
, cmodel
->name
) == 0)
1562 if (cmodel
->name
== NULL
)
1563 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string
);
1565 sparc_cmodel
= cmodel
->value
;
1568 error ("-mcmodel= is not supported on 32-bit systems");
1571 /* Check that -fcall-saved-REG wasn't specified for out registers. */
1572 for (i
= 8; i
< 16; i
++)
1573 if (!call_used_regs
[i
])
1575 error ("-fcall-saved-REG is not supported for out registers");
1576 call_used_regs
[i
] = 1;
1579 /* Set the default CPU if no -mcpu option was specified. */
1580 if (!global_options_set
.x_sparc_cpu_and_features
)
1582 for (def
= &cpu_default
[0]; def
->cpu
!= -1; ++def
)
1583 if (def
->cpu
== TARGET_CPU_DEFAULT
)
1585 gcc_assert (def
->cpu
!= -1);
1586 sparc_cpu_and_features
= def
->processor
;
1589 /* Set the default CPU if no -mtune option was specified. */
1590 if (!global_options_set
.x_sparc_cpu
)
1591 sparc_cpu
= sparc_cpu_and_features
;
1593 cpu
= &cpu_table
[(int) sparc_cpu_and_features
];
1595 if (TARGET_DEBUG_OPTIONS
)
1597 fprintf (stderr
, "sparc_cpu_and_features: %s\n", cpu
->name
);
1598 dump_target_flags ("cpu->disable", cpu
->disable
);
1599 dump_target_flags ("cpu->enable", cpu
->enable
);
1602 target_flags
&= ~cpu
->disable
;
1603 target_flags
|= (cpu
->enable
1604 #ifndef HAVE_AS_FMAF_HPC_VIS3
1605 & ~(MASK_FMAF
| MASK_VIS3
)
1607 #ifndef HAVE_AS_SPARC4
1610 #ifndef HAVE_AS_SPARC5_VIS4
1611 & ~(MASK_VIS4
| MASK_SUBXC
)
1613 #ifndef HAVE_AS_SPARC6
1616 #ifndef HAVE_AS_LEON
1617 & ~(MASK_LEON
| MASK_LEON3
)
1619 & ~(target_flags_explicit
& MASK_FEATURES
)
1622 /* -mvis2 implies -mvis. */
1624 target_flags
|= MASK_VIS
;
1626 /* -mvis3 implies -mvis2 and -mvis. */
1628 target_flags
|= MASK_VIS2
| MASK_VIS
;
1630 /* -mvis4 implies -mvis3, -mvis2 and -mvis. */
1632 target_flags
|= MASK_VIS3
| MASK_VIS2
| MASK_VIS
;
1634 /* -mvis4b implies -mvis4, -mvis3, -mvis2 and -mvis */
1636 target_flags
|= MASK_VIS4
| MASK_VIS3
| MASK_VIS2
| MASK_VIS
;
1638 /* Don't allow -mvis, -mvis2, -mvis3, -mvis4, -mvis4b, -mfmaf and -mfsmuld if
1641 target_flags
&= ~(MASK_VIS
| MASK_VIS2
| MASK_VIS3
| MASK_VIS4
1642 | MASK_VIS4B
| MASK_FMAF
| MASK_FSMULD
);
1644 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
1645 are available; -m64 also implies v9. */
1646 if (TARGET_VIS
|| TARGET_ARCH64
)
1648 target_flags
|= MASK_V9
;
1649 target_flags
&= ~(MASK_V8
| MASK_SPARCLET
| MASK_SPARCLITE
);
1652 /* -mvis also implies -mv8plus on 32-bit. */
1653 if (TARGET_VIS
&& !TARGET_ARCH64
)
1654 target_flags
|= MASK_V8PLUS
;
1656 /* Use the deprecated v8 insns for sparc64 in 32-bit mode. */
1657 if (TARGET_V9
&& TARGET_ARCH32
)
1658 target_flags
|= MASK_DEPRECATED_V8_INSNS
;
1660 /* V8PLUS requires V9 and makes no sense in 64-bit mode. */
1661 if (!TARGET_V9
|| TARGET_ARCH64
)
1662 target_flags
&= ~MASK_V8PLUS
;
1664 /* Don't use stack biasing in 32-bit mode. */
1666 target_flags
&= ~MASK_STACK_BIAS
;
1668 /* Use LRA instead of reload, unless otherwise instructed. */
1669 if (!(target_flags_explicit
& MASK_LRA
))
1670 target_flags
|= MASK_LRA
;
1672 /* Enable the back-to-back store errata workaround for LEON3FT. */
1673 if (sparc_fix_ut699
|| sparc_fix_ut700
|| sparc_fix_gr712rc
)
1674 sparc_fix_b2bst
= 1;
1676 /* Disable FsMULd for the UT699 since it doesn't work correctly. */
1677 if (sparc_fix_ut699
)
1678 target_flags
&= ~MASK_FSMULD
;
1680 /* Supply a default value for align_functions. */
1681 if (align_functions
== 0)
1683 if (sparc_cpu
== PROCESSOR_ULTRASPARC
1684 || sparc_cpu
== PROCESSOR_ULTRASPARC3
1685 || sparc_cpu
== PROCESSOR_NIAGARA
1686 || sparc_cpu
== PROCESSOR_NIAGARA2
1687 || sparc_cpu
== PROCESSOR_NIAGARA3
1688 || sparc_cpu
== PROCESSOR_NIAGARA4
)
1689 align_functions
= 32;
1690 else if (sparc_cpu
== PROCESSOR_NIAGARA7
1691 || sparc_cpu
== PROCESSOR_M8
)
1692 align_functions
= 64;
1695 /* Validate PCC_STRUCT_RETURN. */
1696 if (flag_pcc_struct_return
== DEFAULT_PCC_STRUCT_RETURN
)
1697 flag_pcc_struct_return
= (TARGET_ARCH64
? 0 : 1);
1699 /* Only use .uaxword when compiling for a 64-bit target. */
1701 targetm
.asm_out
.unaligned_op
.di
= NULL
;
1703 /* Do various machine dependent initializations. */
1704 sparc_init_modes ();
1706 /* Set up function hooks. */
1707 init_machine_status
= sparc_init_machine_status
;
1712 case PROCESSOR_CYPRESS
:
1713 sparc_costs
= &cypress_costs
;
1716 case PROCESSOR_SPARCLITE
:
1717 case PROCESSOR_SUPERSPARC
:
1718 sparc_costs
= &supersparc_costs
;
1720 case PROCESSOR_F930
:
1721 case PROCESSOR_F934
:
1722 case PROCESSOR_HYPERSPARC
:
1723 case PROCESSOR_SPARCLITE86X
:
1724 sparc_costs
= &hypersparc_costs
;
1726 case PROCESSOR_LEON
:
1727 sparc_costs
= &leon_costs
;
1729 case PROCESSOR_LEON3
:
1730 case PROCESSOR_LEON3V7
:
1731 sparc_costs
= &leon3_costs
;
1733 case PROCESSOR_SPARCLET
:
1734 case PROCESSOR_TSC701
:
1735 sparc_costs
= &sparclet_costs
;
1738 case PROCESSOR_ULTRASPARC
:
1739 sparc_costs
= &ultrasparc_costs
;
1741 case PROCESSOR_ULTRASPARC3
:
1742 sparc_costs
= &ultrasparc3_costs
;
1744 case PROCESSOR_NIAGARA
:
1745 sparc_costs
= &niagara_costs
;
1747 case PROCESSOR_NIAGARA2
:
1748 sparc_costs
= &niagara2_costs
;
1750 case PROCESSOR_NIAGARA3
:
1751 sparc_costs
= &niagara3_costs
;
1753 case PROCESSOR_NIAGARA4
:
1754 sparc_costs
= &niagara4_costs
;
1756 case PROCESSOR_NIAGARA7
:
1757 sparc_costs
= &niagara7_costs
;
1760 sparc_costs
= &m8_costs
;
1762 case PROCESSOR_NATIVE
:
1766 if (sparc_memory_model
== SMM_DEFAULT
)
1768 /* Choose the memory model for the operating system. */
1769 enum sparc_memory_model_type os_default
= SUBTARGET_DEFAULT_MEMORY_MODEL
;
1770 if (os_default
!= SMM_DEFAULT
)
1771 sparc_memory_model
= os_default
;
1772 /* Choose the most relaxed model for the processor. */
1774 sparc_memory_model
= SMM_RMO
;
1775 else if (TARGET_LEON3
)
1776 sparc_memory_model
= SMM_TSO
;
1777 else if (TARGET_LEON
)
1778 sparc_memory_model
= SMM_SC
;
1780 sparc_memory_model
= SMM_PSO
;
1782 sparc_memory_model
= SMM_SC
;
1785 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1786 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
1787 target_flags
|= MASK_LONG_DOUBLE_128
;
1790 if (TARGET_DEBUG_OPTIONS
)
1791 dump_target_flags ("Final target_flags", target_flags
);
1793 /* PARAM_SIMULTANEOUS_PREFETCHES is the number of prefetches that
1794 can run at the same time. More important, it is the threshold
1795 defining when additional prefetches will be dropped by the
1798 The UltraSPARC-III features a documented prefetch queue with a
1799 size of 8. Additional prefetches issued in the cpu are
1802 Niagara processors are different. In these processors prefetches
1803 are handled much like regular loads. The L1 miss buffer is 32
1804 entries, but prefetches start getting affected when 30 entries
1805 become occupied. That occupation could be a mix of regular loads
1806 and prefetches though. And that buffer is shared by all threads.
1807 Once the threshold is reached, if the core is running a single
1808 thread the prefetch will retry. If more than one thread is
1809 running, the prefetch will be dropped.
1811 All this makes it very difficult to determine how many
1812 simultaneous prefetches can be issued simultaneously, even in a
1813 single-threaded program. Experimental results show that setting
1814 this parameter to 32 works well when the number of threads is not
1816 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
1817 ((sparc_cpu
== PROCESSOR_ULTRASPARC
1818 || sparc_cpu
== PROCESSOR_NIAGARA
1819 || sparc_cpu
== PROCESSOR_NIAGARA2
1820 || sparc_cpu
== PROCESSOR_NIAGARA3
1821 || sparc_cpu
== PROCESSOR_NIAGARA4
)
1823 : (sparc_cpu
== PROCESSOR_ULTRASPARC3
1824 ? 8 : ((sparc_cpu
== PROCESSOR_NIAGARA7
1825 || sparc_cpu
== PROCESSOR_M8
)
1827 global_options
.x_param_values
,
1828 global_options_set
.x_param_values
);
1830 /* PARAM_L1_CACHE_LINE_SIZE is the size of the L1 cache line, in
1833 The Oracle SPARC Architecture (previously the UltraSPARC
1834 Architecture) specification states that when a PREFETCH[A]
1835 instruction is executed an implementation-specific amount of data
1836 is prefetched, and that it is at least 64 bytes long (aligned to
1839 However, this is not correct. The M7 (and implementations prior
1840 to that) does not guarantee a 64B prefetch into a cache if the
1841 line size is smaller. A single cache line is all that is ever
1842 prefetched. So for the M7, where the L1D$ has 32B lines and the
1843 L2D$ and L3 have 64B lines, a prefetch will prefetch 64B into the
1844 L2 and L3, but only 32B are brought into the L1D$. (Assuming it
1845 is a read_n prefetch, which is the only type which allocates to
1847 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
1848 (sparc_cpu
== PROCESSOR_M8
1850 global_options
.x_param_values
,
1851 global_options_set
.x_param_values
);
1853 /* PARAM_L1_CACHE_SIZE is the size of the L1D$ (most SPARC chips use
1854 Hardvard level-1 caches) in kilobytes. Both UltraSPARC and
1855 Niagara processors feature a L1D$ of 16KB. */
1856 maybe_set_param_value (PARAM_L1_CACHE_SIZE
,
1857 ((sparc_cpu
== PROCESSOR_ULTRASPARC
1858 || sparc_cpu
== PROCESSOR_ULTRASPARC3
1859 || sparc_cpu
== PROCESSOR_NIAGARA
1860 || sparc_cpu
== PROCESSOR_NIAGARA2
1861 || sparc_cpu
== PROCESSOR_NIAGARA3
1862 || sparc_cpu
== PROCESSOR_NIAGARA4
1863 || sparc_cpu
== PROCESSOR_NIAGARA7
1864 || sparc_cpu
== PROCESSOR_M8
)
1866 global_options
.x_param_values
,
1867 global_options_set
.x_param_values
);
1870 /* PARAM_L2_CACHE_SIZE is the size fo the L2 in kilobytes. Note
1871 that 512 is the default in params.def. */
1872 maybe_set_param_value (PARAM_L2_CACHE_SIZE
,
1873 ((sparc_cpu
== PROCESSOR_NIAGARA4
1874 || sparc_cpu
== PROCESSOR_M8
)
1875 ? 128 : (sparc_cpu
== PROCESSOR_NIAGARA7
1877 global_options
.x_param_values
,
1878 global_options_set
.x_param_values
);
1881 /* Disable save slot sharing for call-clobbered registers by default.
1882 The IRA sharing algorithm works on single registers only and this
1883 pessimizes for double floating-point registers. */
1884 if (!global_options_set
.x_flag_ira_share_save_slots
)
1885 flag_ira_share_save_slots
= 0;
1887 /* Only enable REE by default in 64-bit mode where it helps to eliminate
1888 redundant 32-to-64-bit extensions. */
1889 if (!global_options_set
.x_flag_ree
&& TARGET_ARCH32
)
1893 /* Miscellaneous utilities. */
1895 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
1896 or branch on register contents instructions. */
1899 v9_regcmp_p (enum rtx_code code
)
1901 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
1902 || code
== LE
|| code
== GT
);
1905 /* Nonzero if OP is a floating point constant which can
1906 be loaded into an integer register using a single
1907 sethi instruction. */
1912 if (GET_CODE (op
) == CONST_DOUBLE
)
1916 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), i
);
1917 return !SPARC_SIMM13_P (i
) && SPARC_SETHI_P (i
);
1923 /* Nonzero if OP is a floating point constant which can
1924 be loaded into an integer register using a single
1930 if (GET_CODE (op
) == CONST_DOUBLE
)
1934 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), i
);
1935 return SPARC_SIMM13_P (i
);
1941 /* Nonzero if OP is a floating point constant which can
1942 be loaded into an integer register using a high/losum
1943 instruction sequence. */
1946 fp_high_losum_p (rtx op
)
1948 /* The constraints calling this should only be in
1949 SFmode move insns, so any constant which cannot
1950 be moved using a single insn will do. */
1951 if (GET_CODE (op
) == CONST_DOUBLE
)
1955 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), i
);
1956 return !SPARC_SIMM13_P (i
) && !SPARC_SETHI_P (i
);
1962 /* Return true if the address of LABEL can be loaded by means of the
1963 mov{si,di}_pic_label_ref patterns in PIC mode. */
1966 can_use_mov_pic_label_ref (rtx label
)
1968 /* VxWorks does not impose a fixed gap between segments; the run-time
1969 gap can be different from the object-file gap. We therefore can't
1970 assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
1971 are absolutely sure that X is in the same segment as the GOT.
1972 Unfortunately, the flexibility of linker scripts means that we
1973 can't be sure of that in general, so assume that GOT-relative
1974 accesses are never valid on VxWorks. */
1975 if (TARGET_VXWORKS_RTP
)
1978 /* Similarly, if the label is non-local, it might end up being placed
1979 in a different section than the current one; now mov_pic_label_ref
1980 requires the label and the code to be in the same section. */
1981 if (LABEL_REF_NONLOCAL_P (label
))
1984 /* Finally, if we are reordering basic blocks and partition into hot
1985 and cold sections, this might happen for any label. */
1986 if (flag_reorder_blocks_and_partition
)
1992 /* Expand a move instruction. Return true if all work is done. */
1995 sparc_expand_move (machine_mode mode
, rtx
*operands
)
1997 /* Handle sets of MEM first. */
1998 if (GET_CODE (operands
[0]) == MEM
)
2000 /* 0 is a register (or a pair of registers) on SPARC. */
2001 if (register_or_zero_operand (operands
[1], mode
))
2004 if (!reload_in_progress
)
2006 operands
[0] = validize_mem (operands
[0]);
2007 operands
[1] = force_reg (mode
, operands
[1]);
2011 /* Fixup TLS cases. */
2013 && CONSTANT_P (operands
[1])
2014 && sparc_tls_referenced_p (operands
[1]))
2016 operands
[1] = sparc_legitimize_tls_address (operands
[1]);
2020 /* Fixup PIC cases. */
2021 if (flag_pic
&& CONSTANT_P (operands
[1]))
2023 if (pic_address_needs_scratch (operands
[1]))
2024 operands
[1] = sparc_legitimize_pic_address (operands
[1], NULL_RTX
);
2026 /* We cannot use the mov{si,di}_pic_label_ref patterns in all cases. */
2027 if (GET_CODE (operands
[1]) == LABEL_REF
2028 && can_use_mov_pic_label_ref (operands
[1]))
2032 emit_insn (gen_movsi_pic_label_ref (operands
[0], operands
[1]));
2038 gcc_assert (TARGET_ARCH64
);
2039 emit_insn (gen_movdi_pic_label_ref (operands
[0], operands
[1]));
2044 if (symbolic_operand (operands
[1], mode
))
2047 = sparc_legitimize_pic_address (operands
[1],
2049 ? operands
[0] : NULL_RTX
);
2054 /* If we are trying to toss an integer constant into FP registers,
2055 or loading a FP or vector constant, force it into memory. */
2056 if (CONSTANT_P (operands
[1])
2057 && REG_P (operands
[0])
2058 && (SPARC_FP_REG_P (REGNO (operands
[0]))
2059 || SCALAR_FLOAT_MODE_P (mode
)
2060 || VECTOR_MODE_P (mode
)))
2062 /* emit_group_store will send such bogosity to us when it is
2063 not storing directly into memory. So fix this up to avoid
2064 crashes in output_constant_pool. */
2065 if (operands
[1] == const0_rtx
)
2066 operands
[1] = CONST0_RTX (mode
);
2068 /* We can clear or set to all-ones FP registers if TARGET_VIS, and
2069 always other regs. */
2070 if ((TARGET_VIS
|| REGNO (operands
[0]) < SPARC_FIRST_FP_REG
)
2071 && (const_zero_operand (operands
[1], mode
)
2072 || const_all_ones_operand (operands
[1], mode
)))
2075 if (REGNO (operands
[0]) < SPARC_FIRST_FP_REG
2076 /* We are able to build any SF constant in integer registers
2077 with at most 2 instructions. */
2079 /* And any DF constant in integer registers if needed. */
2080 || (mode
== DFmode
&& !can_create_pseudo_p ())))
2083 operands
[1] = force_const_mem (mode
, operands
[1]);
2084 if (!reload_in_progress
)
2085 operands
[1] = validize_mem (operands
[1]);
2089 /* Accept non-constants and valid constants unmodified. */
2090 if (!CONSTANT_P (operands
[1])
2091 || GET_CODE (operands
[1]) == HIGH
2092 || input_operand (operands
[1], mode
))
2098 /* All QImode constants require only one insn, so proceed. */
2103 sparc_emit_set_const32 (operands
[0], operands
[1]);
2107 /* input_operand should have filtered out 32-bit mode. */
2108 sparc_emit_set_const64 (operands
[0], operands
[1]);
2114 /* TImode isn't available in 32-bit mode. */
2115 split_double (operands
[1], &high
, &low
);
2116 emit_insn (gen_movdi (operand_subword (operands
[0], 0, 0, TImode
),
2118 emit_insn (gen_movdi (operand_subword (operands
[0], 1, 0, TImode
),
2130 /* Load OP1, a 32-bit constant, into OP0, a register.
2131 We know it can't be done in one insn when we get
2132 here, the move expander guarantees this. */
2135 sparc_emit_set_const32 (rtx op0
, rtx op1
)
2137 machine_mode mode
= GET_MODE (op0
);
2140 if (can_create_pseudo_p ())
2141 temp
= gen_reg_rtx (mode
);
2143 if (GET_CODE (op1
) == CONST_INT
)
2145 gcc_assert (!small_int_operand (op1
, mode
)
2146 && !const_high_operand (op1
, mode
));
2148 /* Emit them as real moves instead of a HIGH/LO_SUM,
2149 this way CSE can see everything and reuse intermediate
2150 values if it wants. */
2151 emit_insn (gen_rtx_SET (temp
, GEN_INT (INTVAL (op1
)
2152 & ~(HOST_WIDE_INT
) 0x3ff)));
2154 emit_insn (gen_rtx_SET (op0
,
2155 gen_rtx_IOR (mode
, temp
,
2156 GEN_INT (INTVAL (op1
) & 0x3ff))));
2160 /* A symbol, emit in the traditional way. */
2161 emit_insn (gen_rtx_SET (temp
, gen_rtx_HIGH (mode
, op1
)));
2162 emit_insn (gen_rtx_SET (op0
, gen_rtx_LO_SUM (mode
, temp
, op1
)));
2166 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
2167 If TEMP is nonzero, we are forbidden to use any other scratch
2168 registers. Otherwise, we are allowed to generate them as needed.
2170 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
2171 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
2174 sparc_emit_set_symbolic_const64 (rtx op0
, rtx op1
, rtx temp
)
2176 rtx cst
, temp1
, temp2
, temp3
, temp4
, temp5
;
2179 /* Deal with too large offsets. */
2180 if (GET_CODE (op1
) == CONST
2181 && GET_CODE (XEXP (op1
, 0)) == PLUS
2182 && CONST_INT_P (cst
= XEXP (XEXP (op1
, 0), 1))
2183 && trunc_int_for_mode (INTVAL (cst
), SImode
) != INTVAL (cst
))
2186 temp1
= gen_reg_rtx (DImode
);
2187 temp2
= gen_reg_rtx (DImode
);
2188 sparc_emit_set_const64 (temp2
, cst
);
2189 sparc_emit_set_symbolic_const64 (temp1
, XEXP (XEXP (op1
, 0), 0),
2191 emit_insn (gen_rtx_SET (op0
, gen_rtx_PLUS (DImode
, temp1
, temp2
)));
2195 if (temp
&& GET_MODE (temp
) == TImode
)
2198 temp
= gen_rtx_REG (DImode
, REGNO (temp
));
2201 /* SPARC-V9 code-model support. */
2202 switch (sparc_cmodel
)
2205 /* The range spanned by all instructions in the object is less
2206 than 2^31 bytes (2GB) and the distance from any instruction
2207 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
2208 than 2^31 bytes (2GB).
2210 The executable must be in the low 4TB of the virtual address
2213 sethi %hi(symbol), %temp1
2214 or %temp1, %lo(symbol), %reg */
2216 temp1
= temp
; /* op0 is allowed. */
2218 temp1
= gen_reg_rtx (DImode
);
2220 emit_insn (gen_rtx_SET (temp1
, gen_rtx_HIGH (DImode
, op1
)));
2221 emit_insn (gen_rtx_SET (op0
, gen_rtx_LO_SUM (DImode
, temp1
, op1
)));
2225 /* The range spanned by all instructions in the object is less
2226 than 2^31 bytes (2GB) and the distance from any instruction
2227 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
2228 than 2^31 bytes (2GB).
2230 The executable must be in the low 16TB of the virtual address
2233 sethi %h44(symbol), %temp1
2234 or %temp1, %m44(symbol), %temp2
2235 sllx %temp2, 12, %temp3
2236 or %temp3, %l44(symbol), %reg */
2241 temp3
= temp
; /* op0 is allowed. */
2245 temp1
= gen_reg_rtx (DImode
);
2246 temp2
= gen_reg_rtx (DImode
);
2247 temp3
= gen_reg_rtx (DImode
);
2250 emit_insn (gen_seth44 (temp1
, op1
));
2251 emit_insn (gen_setm44 (temp2
, temp1
, op1
));
2252 emit_insn (gen_rtx_SET (temp3
,
2253 gen_rtx_ASHIFT (DImode
, temp2
, GEN_INT (12))));
2254 emit_insn (gen_setl44 (op0
, temp3
, op1
));
2258 /* The range spanned by all instructions in the object is less
2259 than 2^31 bytes (2GB) and the distance from any instruction
2260 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
2261 than 2^31 bytes (2GB).
2263 The executable can be placed anywhere in the virtual address
2266 sethi %hh(symbol), %temp1
2267 sethi %lm(symbol), %temp2
2268 or %temp1, %hm(symbol), %temp3
2269 sllx %temp3, 32, %temp4
2270 or %temp4, %temp2, %temp5
2271 or %temp5, %lo(symbol), %reg */
2274 /* It is possible that one of the registers we got for operands[2]
2275 might coincide with that of operands[0] (which is why we made
2276 it TImode). Pick the other one to use as our scratch. */
2277 if (rtx_equal_p (temp
, op0
))
2279 gcc_assert (ti_temp
);
2280 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
2283 temp2
= temp
; /* op0 is _not_ allowed, see above. */
2290 temp1
= gen_reg_rtx (DImode
);
2291 temp2
= gen_reg_rtx (DImode
);
2292 temp3
= gen_reg_rtx (DImode
);
2293 temp4
= gen_reg_rtx (DImode
);
2294 temp5
= gen_reg_rtx (DImode
);
2297 emit_insn (gen_sethh (temp1
, op1
));
2298 emit_insn (gen_setlm (temp2
, op1
));
2299 emit_insn (gen_sethm (temp3
, temp1
, op1
));
2300 emit_insn (gen_rtx_SET (temp4
,
2301 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
2302 emit_insn (gen_rtx_SET (temp5
, gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2303 emit_insn (gen_setlo (op0
, temp5
, op1
));
2307 /* Old old old backwards compatibility kruft here.
2308 Essentially it is MEDLOW with a fixed 64-bit
2309 virtual base added to all data segment addresses.
2310 Text-segment stuff is computed like MEDANY, we can't
2311 reuse the code above because the relocation knobs
2314 Data segment: sethi %hi(symbol), %temp1
2315 add %temp1, EMBMEDANY_BASE_REG, %temp2
2316 or %temp2, %lo(symbol), %reg */
2317 if (data_segment_operand (op1
, GET_MODE (op1
)))
2321 temp1
= temp
; /* op0 is allowed. */
2326 temp1
= gen_reg_rtx (DImode
);
2327 temp2
= gen_reg_rtx (DImode
);
2330 emit_insn (gen_embmedany_sethi (temp1
, op1
));
2331 emit_insn (gen_embmedany_brsum (temp2
, temp1
));
2332 emit_insn (gen_embmedany_losum (op0
, temp2
, op1
));
2335 /* Text segment: sethi %uhi(symbol), %temp1
2336 sethi %hi(symbol), %temp2
2337 or %temp1, %ulo(symbol), %temp3
2338 sllx %temp3, 32, %temp4
2339 or %temp4, %temp2, %temp5
2340 or %temp5, %lo(symbol), %reg */
2345 /* It is possible that one of the registers we got for operands[2]
2346 might coincide with that of operands[0] (which is why we made
2347 it TImode). Pick the other one to use as our scratch. */
2348 if (rtx_equal_p (temp
, op0
))
2350 gcc_assert (ti_temp
);
2351 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
2354 temp2
= temp
; /* op0 is _not_ allowed, see above. */
2361 temp1
= gen_reg_rtx (DImode
);
2362 temp2
= gen_reg_rtx (DImode
);
2363 temp3
= gen_reg_rtx (DImode
);
2364 temp4
= gen_reg_rtx (DImode
);
2365 temp5
= gen_reg_rtx (DImode
);
2368 emit_insn (gen_embmedany_textuhi (temp1
, op1
));
2369 emit_insn (gen_embmedany_texthi (temp2
, op1
));
2370 emit_insn (gen_embmedany_textulo (temp3
, temp1
, op1
));
2371 emit_insn (gen_rtx_SET (temp4
,
2372 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
2373 emit_insn (gen_rtx_SET (temp5
, gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2374 emit_insn (gen_embmedany_textlo (op0
, temp5
, op1
));
2383 /* These avoid problems when cross compiling. If we do not
2384 go through all this hair then the optimizer will see
2385 invalid REG_EQUAL notes or in some cases none at all. */
2386 static rtx
gen_safe_HIGH64 (rtx
, HOST_WIDE_INT
);
2387 static rtx
gen_safe_SET64 (rtx
, HOST_WIDE_INT
);
2388 static rtx
gen_safe_OR64 (rtx
, HOST_WIDE_INT
);
2389 static rtx
gen_safe_XOR64 (rtx
, HOST_WIDE_INT
);
2391 /* The optimizer is not to assume anything about exactly
2392 which bits are set for a HIGH, they are unspecified.
2393 Unfortunately this leads to many missed optimizations
2394 during CSE. We mask out the non-HIGH bits, and matches
2395 a plain movdi, to alleviate this problem. */
2397 gen_safe_HIGH64 (rtx dest
, HOST_WIDE_INT val
)
2399 return gen_rtx_SET (dest
, GEN_INT (val
& ~(HOST_WIDE_INT
)0x3ff));
2403 gen_safe_SET64 (rtx dest
, HOST_WIDE_INT val
)
2405 return gen_rtx_SET (dest
, GEN_INT (val
));
2409 gen_safe_OR64 (rtx src
, HOST_WIDE_INT val
)
2411 return gen_rtx_IOR (DImode
, src
, GEN_INT (val
));
2415 gen_safe_XOR64 (rtx src
, HOST_WIDE_INT val
)
2417 return gen_rtx_XOR (DImode
, src
, GEN_INT (val
));
2420 /* Worker routines for 64-bit constant formation on arch64.
2421 One of the key things to be doing in these emissions is
2422 to create as many temp REGs as possible. This makes it
2423 possible for half-built constants to be used later when
2424 such values are similar to something required later on.
2425 Without doing this, the optimizer cannot see such
2428 static void sparc_emit_set_const64_quick1 (rtx
, rtx
,
2429 unsigned HOST_WIDE_INT
, int);
2432 sparc_emit_set_const64_quick1 (rtx op0
, rtx temp
,
2433 unsigned HOST_WIDE_INT low_bits
, int is_neg
)
2435 unsigned HOST_WIDE_INT high_bits
;
2438 high_bits
= (~low_bits
) & 0xffffffff;
2440 high_bits
= low_bits
;
2442 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
2445 emit_insn (gen_rtx_SET (op0
, gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2449 /* If we are XOR'ing with -1, then we should emit a one's complement
2450 instead. This way the combiner will notice logical operations
2451 such as ANDN later on and substitute. */
2452 if ((low_bits
& 0x3ff) == 0x3ff)
2454 emit_insn (gen_rtx_SET (op0
, gen_rtx_NOT (DImode
, temp
)));
2458 emit_insn (gen_rtx_SET (op0
,
2459 gen_safe_XOR64 (temp
,
2460 (-(HOST_WIDE_INT
)0x400
2461 | (low_bits
& 0x3ff)))));
2466 static void sparc_emit_set_const64_quick2 (rtx
, rtx
, unsigned HOST_WIDE_INT
,
2467 unsigned HOST_WIDE_INT
, int);
2470 sparc_emit_set_const64_quick2 (rtx op0
, rtx temp
,
2471 unsigned HOST_WIDE_INT high_bits
,
2472 unsigned HOST_WIDE_INT low_immediate
,
2477 if ((high_bits
& 0xfffffc00) != 0)
2479 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
2480 if ((high_bits
& ~0xfffffc00) != 0)
2481 emit_insn (gen_rtx_SET (op0
,
2482 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2488 emit_insn (gen_safe_SET64 (temp
, high_bits
));
2492 /* Now shift it up into place. */
2493 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, temp2
,
2494 GEN_INT (shift_count
))));
2496 /* If there is a low immediate part piece, finish up by
2497 putting that in as well. */
2498 if (low_immediate
!= 0)
2499 emit_insn (gen_rtx_SET (op0
, gen_safe_OR64 (op0
, low_immediate
)));
2502 static void sparc_emit_set_const64_longway (rtx
, rtx
, unsigned HOST_WIDE_INT
,
2503 unsigned HOST_WIDE_INT
);
2505 /* Full 64-bit constant decomposition. Even though this is the
2506 'worst' case, we still optimize a few things away. */
2508 sparc_emit_set_const64_longway (rtx op0
, rtx temp
,
2509 unsigned HOST_WIDE_INT high_bits
,
2510 unsigned HOST_WIDE_INT low_bits
)
2514 if (can_create_pseudo_p ())
2515 sub_temp
= gen_reg_rtx (DImode
);
2517 if ((high_bits
& 0xfffffc00) != 0)
2519 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
2520 if ((high_bits
& ~0xfffffc00) != 0)
2521 emit_insn (gen_rtx_SET (sub_temp
,
2522 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2528 emit_insn (gen_safe_SET64 (temp
, high_bits
));
2532 if (can_create_pseudo_p ())
2534 rtx temp2
= gen_reg_rtx (DImode
);
2535 rtx temp3
= gen_reg_rtx (DImode
);
2536 rtx temp4
= gen_reg_rtx (DImode
);
2538 emit_insn (gen_rtx_SET (temp4
, gen_rtx_ASHIFT (DImode
, sub_temp
,
2541 emit_insn (gen_safe_HIGH64 (temp2
, low_bits
));
2542 if ((low_bits
& ~0xfffffc00) != 0)
2544 emit_insn (gen_rtx_SET (temp3
,
2545 gen_safe_OR64 (temp2
, (low_bits
& 0x3ff))));
2546 emit_insn (gen_rtx_SET (op0
, gen_rtx_PLUS (DImode
, temp4
, temp3
)));
2550 emit_insn (gen_rtx_SET (op0
, gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2555 rtx low1
= GEN_INT ((low_bits
>> (32 - 12)) & 0xfff);
2556 rtx low2
= GEN_INT ((low_bits
>> (32 - 12 - 12)) & 0xfff);
2557 rtx low3
= GEN_INT ((low_bits
>> (32 - 12 - 12 - 8)) & 0x0ff);
2560 /* We are in the middle of reload, so this is really
2561 painful. However we do still make an attempt to
2562 avoid emitting truly stupid code. */
2563 if (low1
!= const0_rtx
)
2565 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, sub_temp
,
2566 GEN_INT (to_shift
))));
2567 emit_insn (gen_rtx_SET (op0
, gen_rtx_IOR (DImode
, op0
, low1
)));
2575 if (low2
!= const0_rtx
)
2577 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, sub_temp
,
2578 GEN_INT (to_shift
))));
2579 emit_insn (gen_rtx_SET (op0
, gen_rtx_IOR (DImode
, op0
, low2
)));
2587 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, sub_temp
,
2588 GEN_INT (to_shift
))));
2589 if (low3
!= const0_rtx
)
2590 emit_insn (gen_rtx_SET (op0
, gen_rtx_IOR (DImode
, op0
, low3
)));
2595 /* Analyze a 64-bit constant for certain properties. */
2596 static void analyze_64bit_constant (unsigned HOST_WIDE_INT
,
2597 unsigned HOST_WIDE_INT
,
2598 int *, int *, int *);
2601 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits
,
2602 unsigned HOST_WIDE_INT low_bits
,
2603 int *hbsp
, int *lbsp
, int *abbasp
)
2605 int lowest_bit_set
, highest_bit_set
, all_bits_between_are_set
;
2608 lowest_bit_set
= highest_bit_set
= -1;
2612 if ((lowest_bit_set
== -1)
2613 && ((low_bits
>> i
) & 1))
2615 if ((highest_bit_set
== -1)
2616 && ((high_bits
>> (32 - i
- 1)) & 1))
2617 highest_bit_set
= (64 - i
- 1);
2620 && ((highest_bit_set
== -1)
2621 || (lowest_bit_set
== -1)));
2627 if ((lowest_bit_set
== -1)
2628 && ((high_bits
>> i
) & 1))
2629 lowest_bit_set
= i
+ 32;
2630 if ((highest_bit_set
== -1)
2631 && ((low_bits
>> (32 - i
- 1)) & 1))
2632 highest_bit_set
= 32 - i
- 1;
2635 && ((highest_bit_set
== -1)
2636 || (lowest_bit_set
== -1)));
2638 /* If there are no bits set this should have gone out
2639 as one instruction! */
2640 gcc_assert (lowest_bit_set
!= -1 && highest_bit_set
!= -1);
2641 all_bits_between_are_set
= 1;
2642 for (i
= lowest_bit_set
; i
<= highest_bit_set
; i
++)
2646 if ((low_bits
& (1 << i
)) != 0)
2651 if ((high_bits
& (1 << (i
- 32))) != 0)
2654 all_bits_between_are_set
= 0;
2657 *hbsp
= highest_bit_set
;
2658 *lbsp
= lowest_bit_set
;
2659 *abbasp
= all_bits_between_are_set
;
2662 static int const64_is_2insns (unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
);
2665 const64_is_2insns (unsigned HOST_WIDE_INT high_bits
,
2666 unsigned HOST_WIDE_INT low_bits
)
2668 int highest_bit_set
, lowest_bit_set
, all_bits_between_are_set
;
2671 || high_bits
== 0xffffffff)
2674 analyze_64bit_constant (high_bits
, low_bits
,
2675 &highest_bit_set
, &lowest_bit_set
,
2676 &all_bits_between_are_set
);
2678 if ((highest_bit_set
== 63
2679 || lowest_bit_set
== 0)
2680 && all_bits_between_are_set
!= 0)
2683 if ((highest_bit_set
- lowest_bit_set
) < 21)
2689 static unsigned HOST_WIDE_INT
create_simple_focus_bits (unsigned HOST_WIDE_INT
,
2690 unsigned HOST_WIDE_INT
,
2693 static unsigned HOST_WIDE_INT
2694 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits
,
2695 unsigned HOST_WIDE_INT low_bits
,
2696 int lowest_bit_set
, int shift
)
2698 HOST_WIDE_INT hi
, lo
;
2700 if (lowest_bit_set
< 32)
2702 lo
= (low_bits
>> lowest_bit_set
) << shift
;
2703 hi
= ((high_bits
<< (32 - lowest_bit_set
)) << shift
);
2708 hi
= ((high_bits
>> (lowest_bit_set
- 32)) << shift
);
2710 gcc_assert (! (hi
& lo
));
2714 /* Here we are sure to be arch64 and this is an integer constant
2715 being loaded into a register. Emit the most efficient
2716 insn sequence possible. Detection of all the 1-insn cases
2717 has been done already. */
2719 sparc_emit_set_const64 (rtx op0
, rtx op1
)
2721 unsigned HOST_WIDE_INT high_bits
, low_bits
;
2722 int lowest_bit_set
, highest_bit_set
;
2723 int all_bits_between_are_set
;
2726 /* Sanity check that we know what we are working with. */
2727 gcc_assert (TARGET_ARCH64
2728 && (GET_CODE (op0
) == SUBREG
2729 || (REG_P (op0
) && ! SPARC_FP_REG_P (REGNO (op0
)))));
2731 if (! can_create_pseudo_p ())
2734 if (GET_CODE (op1
) != CONST_INT
)
2736 sparc_emit_set_symbolic_const64 (op0
, op1
, temp
);
2741 temp
= gen_reg_rtx (DImode
);
2743 high_bits
= ((INTVAL (op1
) >> 32) & 0xffffffff);
2744 low_bits
= (INTVAL (op1
) & 0xffffffff);
2746 /* low_bits bits 0 --> 31
2747 high_bits bits 32 --> 63 */
2749 analyze_64bit_constant (high_bits
, low_bits
,
2750 &highest_bit_set
, &lowest_bit_set
,
2751 &all_bits_between_are_set
);
2753 /* First try for a 2-insn sequence. */
2755 /* These situations are preferred because the optimizer can
2756 * do more things with them:
2758 * sllx %reg, shift, %reg
2760 * srlx %reg, shift, %reg
2761 * 3) mov some_small_const, %reg
2762 * sllx %reg, shift, %reg
2764 if (((highest_bit_set
== 63
2765 || lowest_bit_set
== 0)
2766 && all_bits_between_are_set
!= 0)
2767 || ((highest_bit_set
- lowest_bit_set
) < 12))
2769 HOST_WIDE_INT the_const
= -1;
2770 int shift
= lowest_bit_set
;
2772 if ((highest_bit_set
!= 63
2773 && lowest_bit_set
!= 0)
2774 || all_bits_between_are_set
== 0)
2777 create_simple_focus_bits (high_bits
, low_bits
,
2780 else if (lowest_bit_set
== 0)
2781 shift
= -(63 - highest_bit_set
);
2783 gcc_assert (SPARC_SIMM13_P (the_const
));
2784 gcc_assert (shift
!= 0);
2786 emit_insn (gen_safe_SET64 (temp
, the_const
));
2788 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, temp
,
2791 emit_insn (gen_rtx_SET (op0
, gen_rtx_LSHIFTRT (DImode
, temp
,
2792 GEN_INT (-shift
))));
2796 /* Now a range of 22 or less bits set somewhere.
2797 * 1) sethi %hi(focus_bits), %reg
2798 * sllx %reg, shift, %reg
2799 * 2) sethi %hi(focus_bits), %reg
2800 * srlx %reg, shift, %reg
2802 if ((highest_bit_set
- lowest_bit_set
) < 21)
2804 unsigned HOST_WIDE_INT focus_bits
=
2805 create_simple_focus_bits (high_bits
, low_bits
,
2806 lowest_bit_set
, 10);
2808 gcc_assert (SPARC_SETHI_P (focus_bits
));
2809 gcc_assert (lowest_bit_set
!= 10);
2811 emit_insn (gen_safe_HIGH64 (temp
, focus_bits
));
2813 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2814 if (lowest_bit_set
< 10)
2815 emit_insn (gen_rtx_SET (op0
,
2816 gen_rtx_LSHIFTRT (DImode
, temp
,
2817 GEN_INT (10 - lowest_bit_set
))));
2818 else if (lowest_bit_set
> 10)
2819 emit_insn (gen_rtx_SET (op0
,
2820 gen_rtx_ASHIFT (DImode
, temp
,
2821 GEN_INT (lowest_bit_set
- 10))));
2825 /* 1) sethi %hi(low_bits), %reg
2826 * or %reg, %lo(low_bits), %reg
2827 * 2) sethi %hi(~low_bits), %reg
2828 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2831 || high_bits
== 0xffffffff)
2833 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
,
2834 (high_bits
== 0xffffffff));
2838 /* Now, try 3-insn sequences. */
2840 /* 1) sethi %hi(high_bits), %reg
2841 * or %reg, %lo(high_bits), %reg
2842 * sllx %reg, 32, %reg
2846 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, 0, 32);
2850 /* We may be able to do something quick
2851 when the constant is negated, so try that. */
2852 if (const64_is_2insns ((~high_bits
) & 0xffffffff,
2853 (~low_bits
) & 0xfffffc00))
2855 /* NOTE: The trailing bits get XOR'd so we need the
2856 non-negated bits, not the negated ones. */
2857 unsigned HOST_WIDE_INT trailing_bits
= low_bits
& 0x3ff;
2859 if ((((~high_bits
) & 0xffffffff) == 0
2860 && ((~low_bits
) & 0x80000000) == 0)
2861 || (((~high_bits
) & 0xffffffff) == 0xffffffff
2862 && ((~low_bits
) & 0x80000000) != 0))
2864 unsigned HOST_WIDE_INT fast_int
= (~low_bits
& 0xffffffff);
2866 if ((SPARC_SETHI_P (fast_int
)
2867 && (~high_bits
& 0xffffffff) == 0)
2868 || SPARC_SIMM13_P (fast_int
))
2869 emit_insn (gen_safe_SET64 (temp
, fast_int
));
2871 sparc_emit_set_const64 (temp
, GEN_INT (fast_int
));
2876 negated_const
= GEN_INT (((~low_bits
) & 0xfffffc00) |
2877 (((HOST_WIDE_INT
)((~high_bits
) & 0xffffffff))<<32));
2878 sparc_emit_set_const64 (temp
, negated_const
);
2881 /* If we are XOR'ing with -1, then we should emit a one's complement
2882 instead. This way the combiner will notice logical operations
2883 such as ANDN later on and substitute. */
2884 if (trailing_bits
== 0x3ff)
2886 emit_insn (gen_rtx_SET (op0
, gen_rtx_NOT (DImode
, temp
)));
2890 emit_insn (gen_rtx_SET (op0
,
2891 gen_safe_XOR64 (temp
,
2892 (-0x400 | trailing_bits
))));
2897 /* 1) sethi %hi(xxx), %reg
2898 * or %reg, %lo(xxx), %reg
2899 * sllx %reg, yyy, %reg
2901 * ??? This is just a generalized version of the low_bits==0
2902 * thing above, FIXME...
2904 if ((highest_bit_set
- lowest_bit_set
) < 32)
2906 unsigned HOST_WIDE_INT focus_bits
=
2907 create_simple_focus_bits (high_bits
, low_bits
,
2910 /* We can't get here in this state. */
2911 gcc_assert (highest_bit_set
>= 32 && lowest_bit_set
< 32);
2913 /* So what we know is that the set bits straddle the
2914 middle of the 64-bit word. */
2915 sparc_emit_set_const64_quick2 (op0
, temp
,
2921 /* 1) sethi %hi(high_bits), %reg
2922 * or %reg, %lo(high_bits), %reg
2923 * sllx %reg, 32, %reg
2924 * or %reg, low_bits, %reg
2926 if (SPARC_SIMM13_P (low_bits
) && ((int)low_bits
> 0))
2928 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_bits
, 32);
2932 /* The easiest way when all else fails, is full decomposition. */
2933 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
);
2936 /* Implement TARGET_FIXED_CONDITION_CODE_REGS. */
2939 sparc_fixed_condition_code_regs (unsigned int *p1
, unsigned int *p2
)
2941 *p1
= SPARC_ICC_REG
;
2942 *p2
= SPARC_FCC_REG
;
2946 /* Implement TARGET_MIN_ARITHMETIC_PRECISION. */
2949 sparc_min_arithmetic_precision (void)
2954 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2955 return the mode to be used for the comparison. For floating-point,
2956 CCFP[E]mode is used. CCNZmode should be used when the first operand
2957 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2958 processing is needed. */
2961 select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
2963 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2989 else if ((GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
2990 || GET_CODE (x
) == NEG
|| GET_CODE (x
) == ASHIFT
)
2993 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
3000 /* This is for the cmp<mode>_sne pattern. */
3001 if (GET_CODE (x
) == NOT
&& y
== constm1_rtx
)
3003 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
3009 /* This is for the [u]addvdi4_sp32 and [u]subvdi4_sp32 patterns. */
3010 if (!TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
3012 if (GET_CODE (y
) == UNSPEC
3013 && (XINT (y
, 1) == UNSPEC_ADDV
3014 || XINT (y
, 1) == UNSPEC_SUBV
3015 || XINT (y
, 1) == UNSPEC_NEGV
))
3021 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
3028 /* Emit the compare insn and return the CC reg for a CODE comparison
3029 with operands X and Y. */
3032 gen_compare_reg_1 (enum rtx_code code
, rtx x
, rtx y
)
3037 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
3040 mode
= SELECT_CC_MODE (code
, x
, y
);
3042 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
3043 fcc regs (cse can't tell they're really call clobbered regs and will
3044 remove a duplicate comparison even if there is an intervening function
3045 call - it will then try to reload the cc reg via an int reg which is why
3046 we need the movcc patterns). It is possible to provide the movcc
3047 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
3048 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
3049 to tell cse that CCFPE mode registers (even pseudos) are call
3052 /* ??? This is an experiment. Rather than making changes to cse which may
3053 or may not be easy/clean, we do our own cse. This is possible because
3054 we will generate hard registers. Cse knows they're call clobbered (it
3055 doesn't know the same thing about pseudos). If we guess wrong, no big
3056 deal, but if we win, great! */
3058 if (TARGET_V9
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
3059 #if 1 /* experiment */
3062 /* We cycle through the registers to ensure they're all exercised. */
3063 static int next_fcc_reg
= 0;
3064 /* Previous x,y for each fcc reg. */
3065 static rtx prev_args
[4][2];
3067 /* Scan prev_args for x,y. */
3068 for (reg
= 0; reg
< 4; reg
++)
3069 if (prev_args
[reg
][0] == x
&& prev_args
[reg
][1] == y
)
3074 prev_args
[reg
][0] = x
;
3075 prev_args
[reg
][1] = y
;
3076 next_fcc_reg
= (next_fcc_reg
+ 1) & 3;
3078 cc_reg
= gen_rtx_REG (mode
, reg
+ SPARC_FIRST_V9_FCC_REG
);
3081 cc_reg
= gen_reg_rtx (mode
);
3082 #endif /* ! experiment */
3083 else if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
3084 cc_reg
= gen_rtx_REG (mode
, SPARC_FCC_REG
);
3086 cc_reg
= gen_rtx_REG (mode
, SPARC_ICC_REG
);
3088 /* We shouldn't get there for TFmode if !TARGET_HARD_QUAD. If we do, this
3089 will only result in an unrecognizable insn so no point in asserting. */
3090 emit_insn (gen_rtx_SET (cc_reg
, gen_rtx_COMPARE (mode
, x
, y
)));
3096 /* Emit the compare insn and return the CC reg for the comparison in CMP. */
3099 gen_compare_reg (rtx cmp
)
3101 return gen_compare_reg_1 (GET_CODE (cmp
), XEXP (cmp
, 0), XEXP (cmp
, 1));
3104 /* This function is used for v9 only.
3105 DEST is the target of the Scc insn.
3106 CODE is the code for an Scc's comparison.
3107 X and Y are the values we compare.
3109 This function is needed to turn
3112 (gt (reg:CCX 100 %icc)
3116 (gt:DI (reg:CCX 100 %icc)
3119 IE: The instruction recognizer needs to see the mode of the comparison to
3120 find the right instruction. We could use "gt:DI" right in the
3121 define_expand, but leaving it out allows us to handle DI, SI, etc. */
3124 gen_v9_scc (rtx dest
, enum rtx_code compare_code
, rtx x
, rtx y
)
3127 && (GET_MODE (x
) == DImode
3128 || GET_MODE (dest
) == DImode
))
3131 /* Try to use the movrCC insns. */
3133 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
3135 && v9_regcmp_p (compare_code
))
3140 /* Special case for op0 != 0. This can be done with one instruction if
3143 if (compare_code
== NE
3144 && GET_MODE (dest
) == DImode
3145 && rtx_equal_p (op0
, dest
))
3147 emit_insn (gen_rtx_SET (dest
,
3148 gen_rtx_IF_THEN_ELSE (DImode
,
3149 gen_rtx_fmt_ee (compare_code
, DImode
,
3156 if (reg_overlap_mentioned_p (dest
, op0
))
3158 /* Handle the case where dest == x.
3159 We "early clobber" the result. */
3160 op0
= gen_reg_rtx (GET_MODE (x
));
3161 emit_move_insn (op0
, x
);
3164 emit_insn (gen_rtx_SET (dest
, const0_rtx
));
3165 if (GET_MODE (op0
) != DImode
)
3167 temp
= gen_reg_rtx (DImode
);
3168 convert_move (temp
, op0
, 0);
3172 emit_insn (gen_rtx_SET (dest
,
3173 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
3174 gen_rtx_fmt_ee (compare_code
, DImode
,
3182 x
= gen_compare_reg_1 (compare_code
, x
, y
);
3185 emit_insn (gen_rtx_SET (dest
, const0_rtx
));
3186 emit_insn (gen_rtx_SET (dest
,
3187 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
3188 gen_rtx_fmt_ee (compare_code
,
3189 GET_MODE (x
), x
, y
),
3190 const1_rtx
, dest
)));
3196 /* Emit an scc insn. For seq, sne, sgeu, and sltu, we can do this
3197 without jumps using the addx/subx instructions. */
3200 emit_scc_insn (rtx operands
[])
3206 /* The quad-word fp compare library routines all return nonzero to indicate
3207 true, which is different from the equivalent libgcc routines, so we must
3208 handle them specially here. */
3209 if (GET_MODE (operands
[2]) == TFmode
&& ! TARGET_HARD_QUAD
)
3211 operands
[1] = sparc_emit_float_lib_cmp (operands
[2], operands
[3],
3212 GET_CODE (operands
[1]));
3213 operands
[2] = XEXP (operands
[1], 0);
3214 operands
[3] = XEXP (operands
[1], 1);
3217 code
= GET_CODE (operands
[1]);
3220 mode
= GET_MODE (x
);
3222 /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has
3223 more applications). The exception to this is "reg != 0" which can
3224 be done in one instruction on v9 (so we do it). */
3225 if ((code
== EQ
|| code
== NE
) && (mode
== SImode
|| mode
== DImode
))
3227 if (y
!= const0_rtx
)
3228 x
= force_reg (mode
, gen_rtx_XOR (mode
, x
, y
));
3230 rtx pat
= gen_rtx_SET (operands
[0],
3231 gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
3234 /* If we can use addx/subx or addxc, add a clobber for CC. */
3235 if (mode
== SImode
|| (code
== NE
&& TARGET_VIS3
))
3238 = gen_rtx_CLOBBER (VOIDmode
,
3239 gen_rtx_REG (mode
== SImode
? CCmode
: CCXmode
,
3241 pat
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, pat
, clobber
));
3248 /* We can do LTU in DImode using the addxc instruction with VIS3. */
3251 && !((code
== LTU
|| code
== GTU
) && TARGET_VIS3
)
3252 && gen_v9_scc (operands
[0], code
, x
, y
))
3255 /* We can do LTU and GEU using the addx/subx instructions too. And
3256 for GTU/LEU, if both operands are registers swap them and fall
3257 back to the easy case. */
3258 if (code
== GTU
|| code
== LEU
)
3260 if ((GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
3261 && (GET_CODE (y
) == REG
|| GET_CODE (y
) == SUBREG
))
3266 code
= swap_condition (code
);
3270 if (code
== LTU
|| code
== GEU
)
3272 emit_insn (gen_rtx_SET (operands
[0],
3273 gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
3274 gen_compare_reg_1 (code
, x
, y
),
3279 /* All the posibilities to use addx/subx based sequences has been
3280 exhausted, try for a 3 instruction sequence using v9 conditional
3282 if (TARGET_V9
&& gen_v9_scc (operands
[0], code
, x
, y
))
3285 /* Nope, do branches. */
3289 /* Emit a conditional jump insn for the v9 architecture using comparison code
3290 CODE and jump target LABEL.
3291 This function exists to take advantage of the v9 brxx insns. */
3294 emit_v9_brxx_insn (enum rtx_code code
, rtx op0
, rtx label
)
3296 emit_jump_insn (gen_rtx_SET (pc_rtx
,
3297 gen_rtx_IF_THEN_ELSE (VOIDmode
,
3298 gen_rtx_fmt_ee (code
, GET_MODE (op0
),
3300 gen_rtx_LABEL_REF (VOIDmode
, label
),
3304 /* Emit a conditional jump insn for the UA2011 architecture using
3305 comparison code CODE and jump target LABEL. This function exists
3306 to take advantage of the UA2011 Compare and Branch insns. */
3309 emit_cbcond_insn (enum rtx_code code
, rtx op0
, rtx op1
, rtx label
)
3313 if_then_else
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
3314 gen_rtx_fmt_ee(code
, GET_MODE(op0
),
3316 gen_rtx_LABEL_REF (VOIDmode
, label
),
3319 emit_jump_insn (gen_rtx_SET (pc_rtx
, if_then_else
));
3323 emit_conditional_branch_insn (rtx operands
[])
3325 /* The quad-word fp compare library routines all return nonzero to indicate
3326 true, which is different from the equivalent libgcc routines, so we must
3327 handle them specially here. */
3328 if (GET_MODE (operands
[1]) == TFmode
&& ! TARGET_HARD_QUAD
)
3330 operands
[0] = sparc_emit_float_lib_cmp (operands
[1], operands
[2],
3331 GET_CODE (operands
[0]));
3332 operands
[1] = XEXP (operands
[0], 0);
3333 operands
[2] = XEXP (operands
[0], 1);
3336 /* If we can tell early on that the comparison is against a constant
3337 that won't fit in the 5-bit signed immediate field of a cbcond,
3338 use one of the other v9 conditional branch sequences. */
3340 && GET_CODE (operands
[1]) == REG
3341 && (GET_MODE (operands
[1]) == SImode
3342 || (TARGET_ARCH64
&& GET_MODE (operands
[1]) == DImode
))
3343 && (GET_CODE (operands
[2]) != CONST_INT
3344 || SPARC_SIMM5_P (INTVAL (operands
[2]))))
3346 emit_cbcond_insn (GET_CODE (operands
[0]), operands
[1], operands
[2], operands
[3]);
3350 if (TARGET_ARCH64
&& operands
[2] == const0_rtx
3351 && GET_CODE (operands
[1]) == REG
3352 && GET_MODE (operands
[1]) == DImode
)
3354 emit_v9_brxx_insn (GET_CODE (operands
[0]), operands
[1], operands
[3]);
3358 operands
[1] = gen_compare_reg (operands
[0]);
3359 operands
[2] = const0_rtx
;
3360 operands
[0] = gen_rtx_fmt_ee (GET_CODE (operands
[0]), VOIDmode
,
3361 operands
[1], operands
[2]);
3362 emit_jump_insn (gen_cbranchcc4 (operands
[0], operands
[1], operands
[2],
3367 /* Generate a DFmode part of a hard TFmode register.
3368 REG is the TFmode hard register, LOW is 1 for the
3369 low 64bit of the register and 0 otherwise.
3372 gen_df_reg (rtx reg
, int low
)
3374 int regno
= REGNO (reg
);
3376 if ((WORDS_BIG_ENDIAN
== 0) ^ (low
!= 0))
3377 regno
+= (TARGET_ARCH64
&& SPARC_INT_REG_P (regno
)) ? 1 : 2;
3378 return gen_rtx_REG (DFmode
, regno
);
3381 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
3382 Unlike normal calls, TFmode operands are passed by reference. It is
3383 assumed that no more than 3 operands are required. */
3386 emit_soft_tfmode_libcall (const char *func_name
, int nargs
, rtx
*operands
)
3388 rtx ret_slot
= NULL
, arg
[3], func_sym
;
3391 /* We only expect to be called for conversions, unary, and binary ops. */
3392 gcc_assert (nargs
== 2 || nargs
== 3);
3394 for (i
= 0; i
< nargs
; ++i
)
3396 rtx this_arg
= operands
[i
];
3399 /* TFmode arguments and return values are passed by reference. */
3400 if (GET_MODE (this_arg
) == TFmode
)
3402 int force_stack_temp
;
3404 force_stack_temp
= 0;
3405 if (TARGET_BUGGY_QP_LIB
&& i
== 0)
3406 force_stack_temp
= 1;
3408 if (GET_CODE (this_arg
) == MEM
3409 && ! force_stack_temp
)
3411 tree expr
= MEM_EXPR (this_arg
);
3413 mark_addressable (expr
);
3414 this_arg
= XEXP (this_arg
, 0);
3416 else if (CONSTANT_P (this_arg
)
3417 && ! force_stack_temp
)
3419 this_slot
= force_const_mem (TFmode
, this_arg
);
3420 this_arg
= XEXP (this_slot
, 0);
3424 this_slot
= assign_stack_temp (TFmode
, GET_MODE_SIZE (TFmode
));
3426 /* Operand 0 is the return value. We'll copy it out later. */
3428 emit_move_insn (this_slot
, this_arg
);
3430 ret_slot
= this_slot
;
3432 this_arg
= XEXP (this_slot
, 0);
3439 func_sym
= gen_rtx_SYMBOL_REF (Pmode
, func_name
);
3441 if (GET_MODE (operands
[0]) == TFmode
)
3444 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
,
3445 arg
[0], GET_MODE (arg
[0]),
3446 arg
[1], GET_MODE (arg
[1]));
3448 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
,
3449 arg
[0], GET_MODE (arg
[0]),
3450 arg
[1], GET_MODE (arg
[1]),
3451 arg
[2], GET_MODE (arg
[2]));
3454 emit_move_insn (operands
[0], ret_slot
);
3460 gcc_assert (nargs
== 2);
3462 ret
= emit_library_call_value (func_sym
, operands
[0], LCT_NORMAL
,
3463 GET_MODE (operands
[0]),
3464 arg
[1], GET_MODE (arg
[1]));
3466 if (ret
!= operands
[0])
3467 emit_move_insn (operands
[0], ret
);
3471 /* Expand soft-float TFmode calls to sparc abi routines. */
3474 emit_soft_tfmode_binop (enum rtx_code code
, rtx
*operands
)
3496 emit_soft_tfmode_libcall (func
, 3, operands
);
3500 emit_soft_tfmode_unop (enum rtx_code code
, rtx
*operands
)
3504 gcc_assert (code
== SQRT
);
3507 emit_soft_tfmode_libcall (func
, 2, operands
);
3511 emit_soft_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
3518 switch (GET_MODE (operands
[1]))
3531 case FLOAT_TRUNCATE
:
3532 switch (GET_MODE (operands
[0]))
3546 switch (GET_MODE (operands
[1]))
3551 operands
[1] = gen_rtx_SIGN_EXTEND (DImode
, operands
[1]);
3561 case UNSIGNED_FLOAT
:
3562 switch (GET_MODE (operands
[1]))
3567 operands
[1] = gen_rtx_ZERO_EXTEND (DImode
, operands
[1]);
3578 switch (GET_MODE (operands
[0]))
3592 switch (GET_MODE (operands
[0]))
3609 emit_soft_tfmode_libcall (func
, 2, operands
);
3612 /* Expand a hard-float tfmode operation. All arguments must be in
3616 emit_hard_tfmode_operation (enum rtx_code code
, rtx
*operands
)
3620 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
3622 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
3623 op
= gen_rtx_fmt_e (code
, GET_MODE (operands
[0]), operands
[1]);
3627 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
3628 operands
[2] = force_reg (GET_MODE (operands
[2]), operands
[2]);
3629 op
= gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
3630 operands
[1], operands
[2]);
3633 if (register_operand (operands
[0], VOIDmode
))
3636 dest
= gen_reg_rtx (GET_MODE (operands
[0]));
3638 emit_insn (gen_rtx_SET (dest
, op
));
3640 if (dest
!= operands
[0])
3641 emit_move_insn (operands
[0], dest
);
3645 emit_tfmode_binop (enum rtx_code code
, rtx
*operands
)
3647 if (TARGET_HARD_QUAD
)
3648 emit_hard_tfmode_operation (code
, operands
);
3650 emit_soft_tfmode_binop (code
, operands
);
3654 emit_tfmode_unop (enum rtx_code code
, rtx
*operands
)
3656 if (TARGET_HARD_QUAD
)
3657 emit_hard_tfmode_operation (code
, operands
);
3659 emit_soft_tfmode_unop (code
, operands
);
3663 emit_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
3665 if (TARGET_HARD_QUAD
)
3666 emit_hard_tfmode_operation (code
, operands
);
3668 emit_soft_tfmode_cvt (code
, operands
);
3671 /* Return nonzero if a branch/jump/call instruction will be emitting
3672 nop into its delay slot. */
3675 empty_delay_slot (rtx_insn
*insn
)
3679 /* If no previous instruction (should not happen), return true. */
3680 if (PREV_INSN (insn
) == NULL
)
3683 seq
= NEXT_INSN (PREV_INSN (insn
));
3684 if (GET_CODE (PATTERN (seq
)) == SEQUENCE
)
3690 /* Return nonzero if we should emit a nop after a cbcond instruction.
3691 The cbcond instruction does not have a delay slot, however there is
3692 a severe performance penalty if a control transfer appears right
3693 after a cbcond. Therefore we emit a nop when we detect this
3697 emit_cbcond_nop (rtx_insn
*insn
)
3699 rtx next
= next_active_insn (insn
);
3704 if (NONJUMP_INSN_P (next
)
3705 && GET_CODE (PATTERN (next
)) == SEQUENCE
)
3706 next
= XVECEXP (PATTERN (next
), 0, 0);
3707 else if (CALL_P (next
)
3708 && GET_CODE (PATTERN (next
)) == PARALLEL
)
3710 rtx delay
= XVECEXP (PATTERN (next
), 0, 1);
3712 if (GET_CODE (delay
) == RETURN
)
3714 /* It's a sibling call. Do not emit the nop if we're going
3715 to emit something other than the jump itself as the first
3716 instruction of the sibcall sequence. */
3717 if (sparc_leaf_function_p
|| TARGET_FLAT
)
3722 if (NONJUMP_INSN_P (next
))
3728 /* Return nonzero if TRIAL can go into the call delay slot. */
3731 eligible_for_call_delay (rtx_insn
*trial
)
3735 if (get_attr_in_branch_delay (trial
) == IN_BRANCH_DELAY_FALSE
)
3739 call __tls_get_addr, %tgd_call (foo)
3740 add %l7, %o0, %o0, %tgd_add (foo)
3741 while Sun as/ld does not. */
3742 if (TARGET_GNU_TLS
|| !TARGET_TLS
)
3745 pat
= PATTERN (trial
);
3747 /* We must reject tgd_add{32|64}, i.e.
3748 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD)))
3749 and tldm_add{32|64}, i.e.
3750 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM)))
3752 if (GET_CODE (pat
) == SET
3753 && GET_CODE (SET_SRC (pat
)) == PLUS
)
3755 rtx unspec
= XEXP (SET_SRC (pat
), 1);
3757 if (GET_CODE (unspec
) == UNSPEC
3758 && (XINT (unspec
, 1) == UNSPEC_TLSGD
3759 || XINT (unspec
, 1) == UNSPEC_TLSLDM
))
3766 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
3767 instruction. RETURN_P is true if the v9 variant 'return' is to be
3768 considered in the test too.
3770 TRIAL must be a SET whose destination is a REG appropriate for the
3771 'restore' instruction or, if RETURN_P is true, for the 'return'
3775 eligible_for_restore_insn (rtx trial
, bool return_p
)
3777 rtx pat
= PATTERN (trial
);
3778 rtx src
= SET_SRC (pat
);
3779 bool src_is_freg
= false;
3782 /* Since we now can do moves between float and integer registers when
3783 VIS3 is enabled, we have to catch this case. We can allow such
3784 moves when doing a 'return' however. */
3786 if (GET_CODE (src_reg
) == SUBREG
)
3787 src_reg
= SUBREG_REG (src_reg
);
3788 if (GET_CODE (src_reg
) == REG
3789 && SPARC_FP_REG_P (REGNO (src_reg
)))
3792 /* The 'restore src,%g0,dest' pattern for word mode and below. */
3793 if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
3794 && arith_operand (src
, GET_MODE (src
))
3798 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
3800 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
3803 /* The 'restore src,%g0,dest' pattern for double-word mode. */
3804 else if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
3805 && arith_double_operand (src
, GET_MODE (src
))
3807 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
3809 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
3810 else if (! TARGET_FPU
&& register_operand (src
, SFmode
))
3813 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
3814 else if (! TARGET_FPU
&& TARGET_ARCH64
&& register_operand (src
, DFmode
))
3817 /* If we have the 'return' instruction, anything that does not use
3818 local or output registers and can go into a delay slot wins. */
3819 else if (return_p
&& TARGET_V9
&& !epilogue_renumber (&pat
, 1))
3822 /* The 'restore src1,src2,dest' pattern for SImode. */
3823 else if (GET_CODE (src
) == PLUS
3824 && register_operand (XEXP (src
, 0), SImode
)
3825 && arith_operand (XEXP (src
, 1), SImode
))
3828 /* The 'restore src1,src2,dest' pattern for DImode. */
3829 else if (GET_CODE (src
) == PLUS
3830 && register_operand (XEXP (src
, 0), DImode
)
3831 && arith_double_operand (XEXP (src
, 1), DImode
))
3834 /* The 'restore src1,%lo(src2),dest' pattern. */
3835 else if (GET_CODE (src
) == LO_SUM
3836 && ! TARGET_CM_MEDMID
3837 && ((register_operand (XEXP (src
, 0), SImode
)
3838 && immediate_operand (XEXP (src
, 1), SImode
))
3840 && register_operand (XEXP (src
, 0), DImode
)
3841 && immediate_operand (XEXP (src
, 1), DImode
))))
3844 /* The 'restore src,src,dest' pattern. */
3845 else if (GET_CODE (src
) == ASHIFT
3846 && (register_operand (XEXP (src
, 0), SImode
)
3847 || register_operand (XEXP (src
, 0), DImode
))
3848 && XEXP (src
, 1) == const1_rtx
)
3854 /* Return nonzero if TRIAL can go into the function return's delay slot. */
3857 eligible_for_return_delay (rtx_insn
*trial
)
3862 /* If the function uses __builtin_eh_return, the eh_return machinery
3863 occupies the delay slot. */
3864 if (crtl
->calls_eh_return
)
3867 if (get_attr_in_branch_delay (trial
) == IN_BRANCH_DELAY_FALSE
)
3870 /* In the case of a leaf or flat function, anything can go into the slot. */
3871 if (sparc_leaf_function_p
|| TARGET_FLAT
)
3874 if (!NONJUMP_INSN_P (trial
))
3877 pat
= PATTERN (trial
);
3878 if (GET_CODE (pat
) == PARALLEL
)
3884 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
3886 rtx expr
= XVECEXP (pat
, 0, i
);
3887 if (GET_CODE (expr
) != SET
)
3889 if (GET_CODE (SET_DEST (expr
)) != REG
)
3891 regno
= REGNO (SET_DEST (expr
));
3892 if (regno
>= 8 && regno
< 24)
3895 return !epilogue_renumber (&pat
, 1);
3898 if (GET_CODE (pat
) != SET
)
3901 if (GET_CODE (SET_DEST (pat
)) != REG
)
3904 regno
= REGNO (SET_DEST (pat
));
3906 /* Otherwise, only operations which can be done in tandem with
3907 a `restore' or `return' insn can go into the delay slot. */
3908 if (regno
>= 8 && regno
< 24)
3911 /* If this instruction sets up floating point register and we have a return
3912 instruction, it can probably go in. But restore will not work
3914 if (! SPARC_INT_REG_P (regno
))
3915 return TARGET_V9
&& !epilogue_renumber (&pat
, 1);
3917 return eligible_for_restore_insn (trial
, true);
3920 /* Return nonzero if TRIAL can go into the sibling call's delay slot. */
3923 eligible_for_sibcall_delay (rtx_insn
*trial
)
3927 if (get_attr_in_branch_delay (trial
) == IN_BRANCH_DELAY_FALSE
)
3930 if (!NONJUMP_INSN_P (trial
))
3933 pat
= PATTERN (trial
);
3935 if (sparc_leaf_function_p
|| TARGET_FLAT
)
3937 /* If the tail call is done using the call instruction,
3938 we have to restore %o7 in the delay slot. */
3939 if (LEAF_SIBCALL_SLOT_RESERVED_P
)
3942 /* %g1 is used to build the function address */
3943 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 1), pat
))
3949 if (GET_CODE (pat
) != SET
)
3952 /* Otherwise, only operations which can be done in tandem with
3953 a `restore' insn can go into the delay slot. */
3954 if (GET_CODE (SET_DEST (pat
)) != REG
3955 || (REGNO (SET_DEST (pat
)) >= 8 && REGNO (SET_DEST (pat
)) < 24)
3956 || ! SPARC_INT_REG_P (REGNO (SET_DEST (pat
))))
3959 /* If it mentions %o7, it can't go in, because sibcall will clobber it
3961 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 15), pat
))
3964 return eligible_for_restore_insn (trial
, false);
3967 /* Determine if it's legal to put X into the constant pool. This
3968 is not possible if X contains the address of a symbol that is
3969 not constant (TLS) or not known at final link time (PIC). */
3972 sparc_cannot_force_const_mem (machine_mode mode
, rtx x
)
3974 switch (GET_CODE (x
))
3977 case CONST_WIDE_INT
:
3980 /* Accept all non-symbolic constants. */
3984 /* Labels are OK iff we are non-PIC. */
3985 return flag_pic
!= 0;
3988 /* 'Naked' TLS symbol references are never OK,
3989 non-TLS symbols are OK iff we are non-PIC. */
3990 if (SYMBOL_REF_TLS_MODEL (x
))
3993 return flag_pic
!= 0;
3996 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0));
3999 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0))
4000 || sparc_cannot_force_const_mem (mode
, XEXP (x
, 1));
4008 /* Global Offset Table support. */
4009 static GTY(()) rtx got_helper_rtx
= NULL_RTX
;
4010 static GTY(()) rtx global_offset_table_rtx
= NULL_RTX
;
4012 /* Return the SYMBOL_REF for the Global Offset Table. */
4014 static GTY(()) rtx sparc_got_symbol
= NULL_RTX
;
4019 if (!sparc_got_symbol
)
4020 sparc_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
4022 return sparc_got_symbol
;
4025 /* Ensure that we are not using patterns that are not OK with PIC. */
4035 op
= recog_data
.operand
[i
];
4036 gcc_assert (GET_CODE (op
) != SYMBOL_REF
4037 && (GET_CODE (op
) != CONST
4038 || (GET_CODE (XEXP (op
, 0)) == MINUS
4039 && XEXP (XEXP (op
, 0), 0) == sparc_got ()
4040 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST
)));
4048 /* Return true if X is an address which needs a temporary register when
4049 reloaded while generating PIC code. */
4052 pic_address_needs_scratch (rtx x
)
4054 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
4055 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
4056 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
4057 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4058 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
4064 /* Determine if a given RTX is a valid constant. We already know this
4065 satisfies CONSTANT_P. */
4068 sparc_legitimate_constant_p (machine_mode mode
, rtx x
)
4070 switch (GET_CODE (x
))
4074 if (sparc_tls_referenced_p (x
))
4079 /* Floating point constants are generally not ok.
4080 The only exception is 0.0 and all-ones in VIS. */
4082 && SCALAR_FLOAT_MODE_P (mode
)
4083 && (const_zero_operand (x
, mode
)
4084 || const_all_ones_operand (x
, mode
)))
4090 /* Vector constants are generally not ok.
4091 The only exception is 0 or -1 in VIS. */
4093 && (const_zero_operand (x
, mode
)
4094 || const_all_ones_operand (x
, mode
)))
4106 /* Determine if a given RTX is a valid constant address. */
4109 constant_address_p (rtx x
)
4111 switch (GET_CODE (x
))
4119 if (flag_pic
&& pic_address_needs_scratch (x
))
4121 return sparc_legitimate_constant_p (Pmode
, x
);
4124 return !flag_pic
&& sparc_legitimate_constant_p (Pmode
, x
);
4131 /* Nonzero if the constant value X is a legitimate general operand
4132 when generating PIC code. It is given that flag_pic is on and
4133 that X satisfies CONSTANT_P. */
4136 legitimate_pic_operand_p (rtx x
)
4138 if (pic_address_needs_scratch (x
))
4140 if (sparc_tls_referenced_p (x
))
4145 #define RTX_OK_FOR_OFFSET_P(X, MODE) \
4147 && INTVAL (X) >= -0x1000 \
4148 && INTVAL (X) <= (0x1000 - GET_MODE_SIZE (MODE)))
4150 #define RTX_OK_FOR_OLO10_P(X, MODE) \
4152 && INTVAL (X) >= -0x1000 \
4153 && INTVAL (X) <= (0xc00 - GET_MODE_SIZE (MODE)))
4155 /* Handle the TARGET_LEGITIMATE_ADDRESS_P target hook.
4157 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
4158 ordinarily. This changes a bit when generating PIC. */
4161 sparc_legitimate_address_p (machine_mode mode
, rtx addr
, bool strict
)
4163 rtx rs1
= NULL
, rs2
= NULL
, imm1
= NULL
;
4165 if (REG_P (addr
) || GET_CODE (addr
) == SUBREG
)
4167 else if (GET_CODE (addr
) == PLUS
)
4169 rs1
= XEXP (addr
, 0);
4170 rs2
= XEXP (addr
, 1);
4172 /* Canonicalize. REG comes first, if there are no regs,
4173 LO_SUM comes first. */
4175 && GET_CODE (rs1
) != SUBREG
4177 || GET_CODE (rs2
) == SUBREG
4178 || (GET_CODE (rs2
) == LO_SUM
&& GET_CODE (rs1
) != LO_SUM
)))
4180 rs1
= XEXP (addr
, 1);
4181 rs2
= XEXP (addr
, 0);
4185 && rs1
== pic_offset_table_rtx
4187 && GET_CODE (rs2
) != SUBREG
4188 && GET_CODE (rs2
) != LO_SUM
4189 && GET_CODE (rs2
) != MEM
4190 && !(GET_CODE (rs2
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs2
))
4191 && (! symbolic_operand (rs2
, VOIDmode
) || mode
== Pmode
)
4192 && (GET_CODE (rs2
) != CONST_INT
|| SMALL_INT (rs2
)))
4194 || GET_CODE (rs1
) == SUBREG
)
4195 && RTX_OK_FOR_OFFSET_P (rs2
, mode
)))
4200 else if ((REG_P (rs1
) || GET_CODE (rs1
) == SUBREG
)
4201 && (REG_P (rs2
) || GET_CODE (rs2
) == SUBREG
))
4203 /* We prohibit REG + REG for TFmode when there are no quad move insns
4204 and we consequently need to split. We do this because REG+REG
4205 is not an offsettable address. If we get the situation in reload
4206 where source and destination of a movtf pattern are both MEMs with
4207 REG+REG address, then only one of them gets converted to an
4208 offsettable address. */
4210 && ! (TARGET_ARCH64
&& TARGET_HARD_QUAD
))
4213 /* Likewise for TImode, but in all cases. */
4217 /* We prohibit REG + REG on ARCH32 if not optimizing for
4218 DFmode/DImode because then mem_min_alignment is likely to be zero
4219 after reload and the forced split would lack a matching splitter
4221 if (TARGET_ARCH32
&& !optimize
4222 && (mode
== DFmode
|| mode
== DImode
))
4225 else if (USE_AS_OFFSETABLE_LO10
4226 && GET_CODE (rs1
) == LO_SUM
4228 && ! TARGET_CM_MEDMID
4229 && RTX_OK_FOR_OLO10_P (rs2
, mode
))
4232 imm1
= XEXP (rs1
, 1);
4233 rs1
= XEXP (rs1
, 0);
4234 if (!CONSTANT_P (imm1
)
4235 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
4239 else if (GET_CODE (addr
) == LO_SUM
)
4241 rs1
= XEXP (addr
, 0);
4242 imm1
= XEXP (addr
, 1);
4244 if (!CONSTANT_P (imm1
)
4245 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
4248 /* We can't allow TFmode in 32-bit mode, because an offset greater
4249 than the alignment (8) may cause the LO_SUM to overflow. */
4250 if (mode
== TFmode
&& TARGET_ARCH32
)
4253 /* During reload, accept the HIGH+LO_SUM construct generated by
4254 sparc_legitimize_reload_address. */
4255 if (reload_in_progress
4256 && GET_CODE (rs1
) == HIGH
4257 && XEXP (rs1
, 0) == imm1
)
4260 else if (GET_CODE (addr
) == CONST_INT
&& SMALL_INT (addr
))
4265 if (GET_CODE (rs1
) == SUBREG
)
4266 rs1
= SUBREG_REG (rs1
);
4272 if (GET_CODE (rs2
) == SUBREG
)
4273 rs2
= SUBREG_REG (rs2
);
4280 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1
))
4281 || (rs2
&& !REGNO_OK_FOR_BASE_P (REGNO (rs2
))))
4286 if ((! SPARC_INT_REG_P (REGNO (rs1
))
4287 && REGNO (rs1
) != FRAME_POINTER_REGNUM
4288 && REGNO (rs1
) < FIRST_PSEUDO_REGISTER
)
4290 && (! SPARC_INT_REG_P (REGNO (rs2
))
4291 && REGNO (rs2
) != FRAME_POINTER_REGNUM
4292 && REGNO (rs2
) < FIRST_PSEUDO_REGISTER
)))
4298 /* Return the SYMBOL_REF for the tls_get_addr function. */
4300 static GTY(()) rtx sparc_tls_symbol
= NULL_RTX
;
4303 sparc_tls_get_addr (void)
4305 if (!sparc_tls_symbol
)
4306 sparc_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
4308 return sparc_tls_symbol
;
4311 /* Return the Global Offset Table to be used in TLS mode. */
4314 sparc_tls_got (void)
4316 /* In PIC mode, this is just the PIC offset table. */
4319 crtl
->uses_pic_offset_table
= 1;
4320 return pic_offset_table_rtx
;
4323 /* In non-PIC mode, Sun as (unlike GNU as) emits PC-relative relocations for
4324 the GOT symbol with the 32-bit ABI, so we reload the GOT register. */
4325 if (TARGET_SUN_TLS
&& TARGET_ARCH32
)
4327 load_got_register ();
4328 return global_offset_table_rtx
;
4331 /* In all other cases, we load a new pseudo with the GOT symbol. */
4332 return copy_to_reg (sparc_got ());
4335 /* Return true if X contains a thread-local symbol. */
4338 sparc_tls_referenced_p (rtx x
)
4340 if (!TARGET_HAVE_TLS
)
4343 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
4344 x
= XEXP (XEXP (x
, 0), 0);
4346 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
))
4349 /* That's all we handle in sparc_legitimize_tls_address for now. */
4353 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
4354 this (thread-local) address. */
4357 sparc_legitimize_tls_address (rtx addr
)
4359 rtx temp1
, temp2
, temp3
, ret
, o0
, got
;
4362 gcc_assert (can_create_pseudo_p ());
4364 if (GET_CODE (addr
) == SYMBOL_REF
)
4365 switch (SYMBOL_REF_TLS_MODEL (addr
))
4367 case TLS_MODEL_GLOBAL_DYNAMIC
:
4369 temp1
= gen_reg_rtx (SImode
);
4370 temp2
= gen_reg_rtx (SImode
);
4371 ret
= gen_reg_rtx (Pmode
);
4372 o0
= gen_rtx_REG (Pmode
, 8);
4373 got
= sparc_tls_got ();
4374 emit_insn (gen_tgd_hi22 (temp1
, addr
));
4375 emit_insn (gen_tgd_lo10 (temp2
, temp1
, addr
));
4378 emit_insn (gen_tgd_add32 (o0
, got
, temp2
, addr
));
4379 insn
= emit_call_insn (gen_tgd_call32 (o0
, sparc_tls_get_addr (),
4384 emit_insn (gen_tgd_add64 (o0
, got
, temp2
, addr
));
4385 insn
= emit_call_insn (gen_tgd_call64 (o0
, sparc_tls_get_addr (),
4388 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
4389 insn
= get_insns ();
4391 emit_libcall_block (insn
, ret
, o0
, addr
);
4394 case TLS_MODEL_LOCAL_DYNAMIC
:
4396 temp1
= gen_reg_rtx (SImode
);
4397 temp2
= gen_reg_rtx (SImode
);
4398 temp3
= gen_reg_rtx (Pmode
);
4399 ret
= gen_reg_rtx (Pmode
);
4400 o0
= gen_rtx_REG (Pmode
, 8);
4401 got
= sparc_tls_got ();
4402 emit_insn (gen_tldm_hi22 (temp1
));
4403 emit_insn (gen_tldm_lo10 (temp2
, temp1
));
4406 emit_insn (gen_tldm_add32 (o0
, got
, temp2
));
4407 insn
= emit_call_insn (gen_tldm_call32 (o0
, sparc_tls_get_addr (),
4412 emit_insn (gen_tldm_add64 (o0
, got
, temp2
));
4413 insn
= emit_call_insn (gen_tldm_call64 (o0
, sparc_tls_get_addr (),
4416 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
4417 insn
= get_insns ();
4419 emit_libcall_block (insn
, temp3
, o0
,
4420 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
4421 UNSPEC_TLSLD_BASE
));
4422 temp1
= gen_reg_rtx (SImode
);
4423 temp2
= gen_reg_rtx (SImode
);
4424 emit_insn (gen_tldo_hix22 (temp1
, addr
));
4425 emit_insn (gen_tldo_lox10 (temp2
, temp1
, addr
));
4427 emit_insn (gen_tldo_add32 (ret
, temp3
, temp2
, addr
));
4429 emit_insn (gen_tldo_add64 (ret
, temp3
, temp2
, addr
));
4432 case TLS_MODEL_INITIAL_EXEC
:
4433 temp1
= gen_reg_rtx (SImode
);
4434 temp2
= gen_reg_rtx (SImode
);
4435 temp3
= gen_reg_rtx (Pmode
);
4436 got
= sparc_tls_got ();
4437 emit_insn (gen_tie_hi22 (temp1
, addr
));
4438 emit_insn (gen_tie_lo10 (temp2
, temp1
, addr
));
4440 emit_insn (gen_tie_ld32 (temp3
, got
, temp2
, addr
));
4442 emit_insn (gen_tie_ld64 (temp3
, got
, temp2
, addr
));
4445 ret
= gen_reg_rtx (Pmode
);
4447 emit_insn (gen_tie_add32 (ret
, gen_rtx_REG (Pmode
, 7),
4450 emit_insn (gen_tie_add64 (ret
, gen_rtx_REG (Pmode
, 7),
4454 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp3
);
4457 case TLS_MODEL_LOCAL_EXEC
:
4458 temp1
= gen_reg_rtx (Pmode
);
4459 temp2
= gen_reg_rtx (Pmode
);
4462 emit_insn (gen_tle_hix22_sp32 (temp1
, addr
));
4463 emit_insn (gen_tle_lox10_sp32 (temp2
, temp1
, addr
));
4467 emit_insn (gen_tle_hix22_sp64 (temp1
, addr
));
4468 emit_insn (gen_tle_lox10_sp64 (temp2
, temp1
, addr
));
4470 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp2
);
4477 else if (GET_CODE (addr
) == CONST
)
4481 gcc_assert (GET_CODE (XEXP (addr
, 0)) == PLUS
);
4483 base
= sparc_legitimize_tls_address (XEXP (XEXP (addr
, 0), 0));
4484 offset
= XEXP (XEXP (addr
, 0), 1);
4486 base
= force_operand (base
, NULL_RTX
);
4487 if (!(GET_CODE (offset
) == CONST_INT
&& SMALL_INT (offset
)))
4488 offset
= force_reg (Pmode
, offset
);
4489 ret
= gen_rtx_PLUS (Pmode
, base
, offset
);
4493 gcc_unreachable (); /* for now ... */
4498 /* Legitimize PIC addresses. If the address is already position-independent,
4499 we return ORIG. Newly generated position-independent addresses go into a
4500 reg. This is REG if nonzero, otherwise we allocate register(s) as
4504 sparc_legitimize_pic_address (rtx orig
, rtx reg
)
4506 bool gotdata_op
= false;
4508 if (GET_CODE (orig
) == SYMBOL_REF
4509 /* See the comment in sparc_expand_move. */
4510 || (GET_CODE (orig
) == LABEL_REF
&& !can_use_mov_pic_label_ref (orig
)))
4512 rtx pic_ref
, address
;
4517 gcc_assert (can_create_pseudo_p ());
4518 reg
= gen_reg_rtx (Pmode
);
4523 /* If not during reload, allocate another temp reg here for loading
4524 in the address, so that these instructions can be optimized
4526 rtx temp_reg
= (! can_create_pseudo_p ()
4527 ? reg
: gen_reg_rtx (Pmode
));
4529 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
4530 won't get confused into thinking that these two instructions
4531 are loading in the true address of the symbol. If in the
4532 future a PIC rtx exists, that should be used instead. */
4535 emit_insn (gen_movdi_high_pic (temp_reg
, orig
));
4536 emit_insn (gen_movdi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
4540 emit_insn (gen_movsi_high_pic (temp_reg
, orig
));
4541 emit_insn (gen_movsi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
4549 crtl
->uses_pic_offset_table
= 1;
4553 insn
= emit_insn (gen_movdi_pic_gotdata_op (reg
,
4554 pic_offset_table_rtx
,
4557 insn
= emit_insn (gen_movsi_pic_gotdata_op (reg
,
4558 pic_offset_table_rtx
,
4564 = gen_const_mem (Pmode
,
4565 gen_rtx_PLUS (Pmode
,
4566 pic_offset_table_rtx
, address
));
4567 insn
= emit_move_insn (reg
, pic_ref
);
4570 /* Put a REG_EQUAL note on this insn, so that it can be optimized
4572 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
4575 else if (GET_CODE (orig
) == CONST
)
4579 if (GET_CODE (XEXP (orig
, 0)) == PLUS
4580 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
4585 gcc_assert (can_create_pseudo_p ());
4586 reg
= gen_reg_rtx (Pmode
);
4589 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
4590 base
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), reg
);
4591 offset
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
4592 base
== reg
? NULL_RTX
: reg
);
4594 if (GET_CODE (offset
) == CONST_INT
)
4596 if (SMALL_INT (offset
))
4597 return plus_constant (Pmode
, base
, INTVAL (offset
));
4598 else if (can_create_pseudo_p ())
4599 offset
= force_reg (Pmode
, offset
);
4601 /* If we reach here, then something is seriously wrong. */
4604 return gen_rtx_PLUS (Pmode
, base
, offset
);
4606 else if (GET_CODE (orig
) == LABEL_REF
)
4607 /* ??? We ought to be checking that the register is live instead, in case
4608 it is eliminated. */
4609 crtl
->uses_pic_offset_table
= 1;
4614 /* Try machine-dependent ways of modifying an illegitimate address X
4615 to be legitimate. If we find one, return the new, valid address.
4617 OLDX is the address as it was before break_out_memory_refs was called.
4618 In some cases it is useful to look at this to decide what needs to be done.
4620 MODE is the mode of the operand pointed to by X.
4622 On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
4625 sparc_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
4630 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
)
4631 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
4632 force_operand (XEXP (x
, 0), NULL_RTX
));
4633 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == MULT
)
4634 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4635 force_operand (XEXP (x
, 1), NULL_RTX
));
4636 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
4637 x
= gen_rtx_PLUS (Pmode
, force_operand (XEXP (x
, 0), NULL_RTX
),
4639 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == PLUS
)
4640 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4641 force_operand (XEXP (x
, 1), NULL_RTX
));
4643 if (x
!= orig_x
&& sparc_legitimate_address_p (mode
, x
, FALSE
))
4646 if (sparc_tls_referenced_p (x
))
4647 x
= sparc_legitimize_tls_address (x
);
4649 x
= sparc_legitimize_pic_address (x
, NULL_RTX
);
4650 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 1)))
4651 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4652 copy_to_mode_reg (Pmode
, XEXP (x
, 1)));
4653 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 0)))
4654 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
4655 copy_to_mode_reg (Pmode
, XEXP (x
, 0)));
4656 else if (GET_CODE (x
) == SYMBOL_REF
4657 || GET_CODE (x
) == CONST
4658 || GET_CODE (x
) == LABEL_REF
)
4659 x
= copy_to_suggested_reg (x
, NULL_RTX
, Pmode
);
4664 /* Delegitimize an address that was legitimized by the above function. */
4667 sparc_delegitimize_address (rtx x
)
4669 x
= delegitimize_mem_from_attrs (x
);
4671 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 1)) == UNSPEC
)
4672 switch (XINT (XEXP (x
, 1), 1))
4674 case UNSPEC_MOVE_PIC
:
4676 x
= XVECEXP (XEXP (x
, 1), 0, 0);
4677 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
4683 /* This is generated by mov{si,di}_pic_label_ref in PIC mode. */
4684 if (GET_CODE (x
) == MINUS
4685 && REG_P (XEXP (x
, 0))
4686 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
4687 && GET_CODE (XEXP (x
, 1)) == LO_SUM
4688 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == UNSPEC
4689 && XINT (XEXP (XEXP (x
, 1), 1), 1) == UNSPEC_MOVE_PIC_LABEL
)
4691 x
= XVECEXP (XEXP (XEXP (x
, 1), 1), 0, 0);
4692 gcc_assert (GET_CODE (x
) == LABEL_REF
);
4698 /* SPARC implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
4699 replace the input X, or the original X if no replacement is called for.
4700 The output parameter *WIN is 1 if the calling macro should goto WIN,
4703 For SPARC, we wish to handle addresses by splitting them into
4704 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
4705 This cuts the number of extra insns by one.
4707 Do nothing when generating PIC code and the address is a symbolic
4708 operand or requires a scratch register. */
4711 sparc_legitimize_reload_address (rtx x
, machine_mode mode
,
4712 int opnum
, int type
,
4713 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
4715 /* Decompose SImode constants into HIGH+LO_SUM. */
4717 && (mode
!= TFmode
|| TARGET_ARCH64
)
4718 && GET_MODE (x
) == SImode
4719 && GET_CODE (x
) != LO_SUM
4720 && GET_CODE (x
) != HIGH
4721 && sparc_cmodel
<= CM_MEDLOW
4723 && (symbolic_operand (x
, Pmode
) || pic_address_needs_scratch (x
))))
4725 x
= gen_rtx_LO_SUM (GET_MODE (x
), gen_rtx_HIGH (GET_MODE (x
), x
), x
);
4726 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4727 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
4728 opnum
, (enum reload_type
)type
);
4733 /* We have to recognize what we have already generated above. */
4734 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == HIGH
)
4736 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4737 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
4738 opnum
, (enum reload_type
)type
);
4747 /* Return true if ADDR (a legitimate address expression)
4748 has an effect that depends on the machine mode it is used for.
4754 is not equivalent to
4756 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
4758 because [%l7+a+1] is interpreted as the address of (a+1). */
4762 sparc_mode_dependent_address_p (const_rtx addr
,
4763 addr_space_t as ATTRIBUTE_UNUSED
)
4765 if (flag_pic
&& GET_CODE (addr
) == PLUS
)
4767 rtx op0
= XEXP (addr
, 0);
4768 rtx op1
= XEXP (addr
, 1);
4769 if (op0
== pic_offset_table_rtx
4770 && symbolic_operand (op1
, VOIDmode
))
4777 #ifdef HAVE_GAS_HIDDEN
4778 # define USE_HIDDEN_LINKONCE 1
4780 # define USE_HIDDEN_LINKONCE 0
4784 get_pc_thunk_name (char name
[32], unsigned int regno
)
4786 const char *reg_name
= reg_names
[regno
];
4788 /* Skip the leading '%' as that cannot be used in a
4792 if (USE_HIDDEN_LINKONCE
)
4793 sprintf (name
, "__sparc_get_pc_thunk.%s", reg_name
);
4795 ASM_GENERATE_INTERNAL_LABEL (name
, "LADDPC", regno
);
4798 /* Wrapper around the load_pcrel_sym{si,di} patterns. */
4801 gen_load_pcrel_sym (rtx op0
, rtx op1
, rtx op2
, rtx op3
)
4803 int orig_flag_pic
= flag_pic
;
4806 /* The load_pcrel_sym{si,di} patterns require absolute addressing. */
4809 insn
= gen_load_pcrel_symdi (op0
, op1
, op2
, op3
);
4811 insn
= gen_load_pcrel_symsi (op0
, op1
, op2
, op3
);
4812 flag_pic
= orig_flag_pic
;
4817 /* Emit code to load the GOT register. */
4820 load_got_register (void)
4822 /* In PIC mode, this will retrieve pic_offset_table_rtx. */
4823 if (!global_offset_table_rtx
)
4824 global_offset_table_rtx
= gen_rtx_REG (Pmode
, GLOBAL_OFFSET_TABLE_REGNUM
);
4826 if (TARGET_VXWORKS_RTP
)
4827 emit_insn (gen_vxworks_load_got ());
4830 /* The GOT symbol is subject to a PC-relative relocation so we need a
4831 helper function to add the PC value and thus get the final value. */
4832 if (!got_helper_rtx
)
4835 get_pc_thunk_name (name
, GLOBAL_OFFSET_TABLE_REGNUM
);
4836 got_helper_rtx
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
4839 emit_insn (gen_load_pcrel_sym (global_offset_table_rtx
, sparc_got (),
4841 GEN_INT (GLOBAL_OFFSET_TABLE_REGNUM
)));
4844 /* Need to emit this whether or not we obey regdecls,
4845 since setjmp/longjmp can cause life info to screw up.
4846 ??? In the case where we don't obey regdecls, this is not sufficient
4847 since we may not fall out the bottom. */
4848 emit_use (global_offset_table_rtx
);
4851 /* Emit a call instruction with the pattern given by PAT. ADDR is the
4852 address of the call target. */
4855 sparc_emit_call_insn (rtx pat
, rtx addr
)
4859 insn
= emit_call_insn (pat
);
4861 /* The PIC register is live on entry to VxWorks PIC PLT entries. */
4862 if (TARGET_VXWORKS_RTP
4864 && GET_CODE (addr
) == SYMBOL_REF
4865 && (SYMBOL_REF_DECL (addr
)
4866 ? !targetm
.binds_local_p (SYMBOL_REF_DECL (addr
))
4867 : !SYMBOL_REF_LOCAL_P (addr
)))
4869 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
4870 crtl
->uses_pic_offset_table
= 1;
4874 /* Return 1 if RTX is a MEM which is known to be aligned to at
4875 least a DESIRED byte boundary. */
4878 mem_min_alignment (rtx mem
, int desired
)
4880 rtx addr
, base
, offset
;
4882 /* If it's not a MEM we can't accept it. */
4883 if (GET_CODE (mem
) != MEM
)
4887 if (!TARGET_UNALIGNED_DOUBLES
4888 && MEM_ALIGN (mem
) / BITS_PER_UNIT
>= (unsigned)desired
)
4891 /* ??? The rest of the function predates MEM_ALIGN so
4892 there is probably a bit of redundancy. */
4893 addr
= XEXP (mem
, 0);
4894 base
= offset
= NULL_RTX
;
4895 if (GET_CODE (addr
) == PLUS
)
4897 if (GET_CODE (XEXP (addr
, 0)) == REG
)
4899 base
= XEXP (addr
, 0);
4901 /* What we are saying here is that if the base
4902 REG is aligned properly, the compiler will make
4903 sure any REG based index upon it will be so
4905 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
4906 offset
= XEXP (addr
, 1);
4908 offset
= const0_rtx
;
4911 else if (GET_CODE (addr
) == REG
)
4914 offset
= const0_rtx
;
4917 if (base
!= NULL_RTX
)
4919 int regno
= REGNO (base
);
4921 if (regno
!= HARD_FRAME_POINTER_REGNUM
&& regno
!= STACK_POINTER_REGNUM
)
4923 /* Check if the compiler has recorded some information
4924 about the alignment of the base REG. If reload has
4925 completed, we already matched with proper alignments.
4926 If not running global_alloc, reload might give us
4927 unaligned pointer to local stack though. */
4929 && REGNO_POINTER_ALIGN (regno
) >= desired
* BITS_PER_UNIT
)
4930 || (optimize
&& reload_completed
))
4931 && (INTVAL (offset
) & (desired
- 1)) == 0)
4936 if (((INTVAL (offset
) - SPARC_STACK_BIAS
) & (desired
- 1)) == 0)
4940 else if (! TARGET_UNALIGNED_DOUBLES
4941 || CONSTANT_P (addr
)
4942 || GET_CODE (addr
) == LO_SUM
)
4944 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
4945 is true, in which case we can only assume that an access is aligned if
4946 it is to a constant address, or the address involves a LO_SUM. */
4950 /* An obviously unaligned address. */
4955 /* Vectors to keep interesting information about registers where it can easily
4956 be got. We used to use the actual mode value as the bit number, but there
4957 are more than 32 modes now. Instead we use two tables: one indexed by
4958 hard register number, and one indexed by mode. */
4960 /* The purpose of sparc_mode_class is to shrink the range of modes so that
4961 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
4962 mapped into one sparc_mode_class mode. */
4964 enum sparc_mode_class
{
4965 H_MODE
, S_MODE
, D_MODE
, T_MODE
, O_MODE
,
4966 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
4970 /* Modes for single-word and smaller quantities. */
4972 ((1 << (int) H_MODE) | (1 << (int) S_MODE) | (1 << (int) SF_MODE))
4974 /* Modes for double-word and smaller quantities. */
4975 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << (int) DF_MODE))
4977 /* Modes for quad-word and smaller quantities. */
4978 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
4980 /* Modes for 8-word and smaller quantities. */
4981 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
4983 /* Modes for single-float quantities. */
4984 #define SF_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
4986 /* Modes for double-float and smaller quantities. */
4987 #define DF_MODES (SF_MODES | (1 << (int) D_MODE) | (1 << (int) DF_MODE))
4989 /* Modes for quad-float and smaller quantities. */
4990 #define TF_MODES (DF_MODES | (1 << (int) TF_MODE))
4992 /* Modes for quad-float pairs and smaller quantities. */
4993 #define OF_MODES (TF_MODES | (1 << (int) OF_MODE))
4995 /* Modes for double-float only quantities. */
4996 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
4998 /* Modes for quad-float and double-float only quantities. */
4999 #define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE))
5001 /* Modes for quad-float pairs and double-float only quantities. */
5002 #define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE))
5004 /* Modes for condition codes. */
5005 #define CC_MODES (1 << (int) CC_MODE)
5006 #define CCFP_MODES (1 << (int) CCFP_MODE)
5008 /* Value is 1 if register/mode pair is acceptable on sparc.
5010 The funny mixture of D and T modes is because integer operations
5011 do not specially operate on tetra quantities, so non-quad-aligned
5012 registers can hold quadword quantities (except %o4 and %i4 because
5013 they cross fixed registers).
5015 ??? Note that, despite the settings, non-double-aligned parameter
5016 registers can hold double-word quantities in 32-bit mode. */
5018 /* This points to either the 32-bit or the 64-bit version. */
5019 static const int *hard_regno_mode_classes
;
5021 static const int hard_32bit_mode_classes
[] = {
5022 S_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
5023 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
5024 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
5025 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
5027 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5028 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5029 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5030 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5032 /* FP regs f32 to f63. Only the even numbered registers actually exist,
5033 and none can hold SFmode/SImode values. */
5034 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5035 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5036 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5037 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5040 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
5042 /* %icc, %sfp, %gsr */
5043 CC_MODES
, 0, D_MODES
5046 static const int hard_64bit_mode_classes
[] = {
5047 D_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
5048 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
5049 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
5050 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
5052 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5053 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5054 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5055 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5057 /* FP regs f32 to f63. Only the even numbered registers actually exist,
5058 and none can hold SFmode/SImode values. */
5059 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5060 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5061 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5062 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5065 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
5067 /* %icc, %sfp, %gsr */
5068 CC_MODES
, 0, D_MODES
5071 static int sparc_mode_class
[NUM_MACHINE_MODES
];
5073 enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
5076 sparc_init_modes (void)
5080 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
5082 machine_mode m
= (machine_mode
) i
;
5083 unsigned int size
= GET_MODE_SIZE (m
);
5085 switch (GET_MODE_CLASS (m
))
5088 case MODE_PARTIAL_INT
:
5089 case MODE_COMPLEX_INT
:
5091 sparc_mode_class
[i
] = 1 << (int) H_MODE
;
5093 sparc_mode_class
[i
] = 1 << (int) S_MODE
;
5095 sparc_mode_class
[i
] = 1 << (int) D_MODE
;
5096 else if (size
== 16)
5097 sparc_mode_class
[i
] = 1 << (int) T_MODE
;
5098 else if (size
== 32)
5099 sparc_mode_class
[i
] = 1 << (int) O_MODE
;
5101 sparc_mode_class
[i
] = 0;
5103 case MODE_VECTOR_INT
:
5105 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
5107 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
5109 sparc_mode_class
[i
] = 0;
5112 case MODE_COMPLEX_FLOAT
:
5114 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
5116 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
5117 else if (size
== 16)
5118 sparc_mode_class
[i
] = 1 << (int) TF_MODE
;
5119 else if (size
== 32)
5120 sparc_mode_class
[i
] = 1 << (int) OF_MODE
;
5122 sparc_mode_class
[i
] = 0;
5125 if (m
== CCFPmode
|| m
== CCFPEmode
)
5126 sparc_mode_class
[i
] = 1 << (int) CCFP_MODE
;
5128 sparc_mode_class
[i
] = 1 << (int) CC_MODE
;
5131 sparc_mode_class
[i
] = 0;
5137 hard_regno_mode_classes
= hard_64bit_mode_classes
;
5139 hard_regno_mode_classes
= hard_32bit_mode_classes
;
5141 /* Initialize the array used by REGNO_REG_CLASS. */
5142 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
5144 if (i
< 16 && TARGET_V8PLUS
)
5145 sparc_regno_reg_class
[i
] = I64_REGS
;
5146 else if (i
< 32 || i
== FRAME_POINTER_REGNUM
)
5147 sparc_regno_reg_class
[i
] = GENERAL_REGS
;
5149 sparc_regno_reg_class
[i
] = FP_REGS
;
5151 sparc_regno_reg_class
[i
] = EXTRA_FP_REGS
;
5153 sparc_regno_reg_class
[i
] = FPCC_REGS
;
5155 sparc_regno_reg_class
[i
] = NO_REGS
;
5159 /* Return whether REGNO, a global or FP register, must be saved/restored. */
5162 save_global_or_fp_reg_p (unsigned int regno
,
5163 int leaf_function ATTRIBUTE_UNUSED
)
5165 return !call_used_regs
[regno
] && df_regs_ever_live_p (regno
);
5168 /* Return whether the return address register (%i7) is needed. */
5171 return_addr_reg_needed_p (int leaf_function
)
5173 /* If it is live, for example because of __builtin_return_address (0). */
5174 if (df_regs_ever_live_p (RETURN_ADDR_REGNUM
))
5177 /* Otherwise, it is needed as save register if %o7 is clobbered. */
5179 /* Loading the GOT register clobbers %o7. */
5180 || crtl
->uses_pic_offset_table
5181 || df_regs_ever_live_p (INCOMING_RETURN_ADDR_REGNUM
))
5187 /* Return whether REGNO, a local or in register, must be saved/restored. */
5190 save_local_or_in_reg_p (unsigned int regno
, int leaf_function
)
5192 /* General case: call-saved registers live at some point. */
5193 if (!call_used_regs
[regno
] && df_regs_ever_live_p (regno
))
5196 /* Frame pointer register (%fp) if needed. */
5197 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
5200 /* Return address register (%i7) if needed. */
5201 if (regno
== RETURN_ADDR_REGNUM
&& return_addr_reg_needed_p (leaf_function
))
5204 /* GOT register (%l7) if needed. */
5205 if (regno
== PIC_OFFSET_TABLE_REGNUM
&& crtl
->uses_pic_offset_table
)
5208 /* If the function accesses prior frames, the frame pointer and the return
5209 address of the previous frame must be saved on the stack. */
5210 if (crtl
->accesses_prior_frames
5211 && (regno
== HARD_FRAME_POINTER_REGNUM
|| regno
== RETURN_ADDR_REGNUM
))
5217 /* Compute the frame size required by the function. This function is called
5218 during the reload pass and also by sparc_expand_prologue. */
5221 sparc_compute_frame_size (HOST_WIDE_INT size
, int leaf_function
)
5223 HOST_WIDE_INT frame_size
, apparent_frame_size
;
5224 int args_size
, n_global_fp_regs
= 0;
5225 bool save_local_in_regs_p
= false;
5228 /* If the function allocates dynamic stack space, the dynamic offset is
5229 computed early and contains REG_PARM_STACK_SPACE, so we need to cope. */
5230 if (leaf_function
&& !cfun
->calls_alloca
)
5233 args_size
= crtl
->outgoing_args_size
+ REG_PARM_STACK_SPACE (cfun
->decl
);
5235 /* Calculate space needed for global registers. */
5238 for (i
= 0; i
< 8; i
++)
5239 if (save_global_or_fp_reg_p (i
, 0))
5240 n_global_fp_regs
+= 2;
5244 for (i
= 0; i
< 8; i
+= 2)
5245 if (save_global_or_fp_reg_p (i
, 0)
5246 || save_global_or_fp_reg_p (i
+ 1, 0))
5247 n_global_fp_regs
+= 2;
5250 /* In the flat window model, find out which local and in registers need to
5251 be saved. We don't reserve space in the current frame for them as they
5252 will be spilled into the register window save area of the caller's frame.
5253 However, as soon as we use this register window save area, we must create
5254 that of the current frame to make it the live one. */
5256 for (i
= 16; i
< 32; i
++)
5257 if (save_local_or_in_reg_p (i
, leaf_function
))
5259 save_local_in_regs_p
= true;
5263 /* Calculate space needed for FP registers. */
5264 for (i
= 32; i
< (TARGET_V9
? 96 : 64); i
+= 2)
5265 if (save_global_or_fp_reg_p (i
, 0) || save_global_or_fp_reg_p (i
+ 1, 0))
5266 n_global_fp_regs
+= 2;
5269 && n_global_fp_regs
== 0
5271 && !save_local_in_regs_p
)
5272 frame_size
= apparent_frame_size
= 0;
5275 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
5276 apparent_frame_size
= ROUND_UP (size
- STARTING_FRAME_OFFSET
, 8);
5277 apparent_frame_size
+= n_global_fp_regs
* 4;
5279 /* We need to add the size of the outgoing argument area. */
5280 frame_size
= apparent_frame_size
+ ROUND_UP (args_size
, 8);
5282 /* And that of the register window save area. */
5283 frame_size
+= FIRST_PARM_OFFSET (cfun
->decl
);
5285 /* Finally, bump to the appropriate alignment. */
5286 frame_size
= SPARC_STACK_ALIGN (frame_size
);
5289 /* Set up values for use in prologue and epilogue. */
5290 sparc_frame_size
= frame_size
;
5291 sparc_apparent_frame_size
= apparent_frame_size
;
5292 sparc_n_global_fp_regs
= n_global_fp_regs
;
5293 sparc_save_local_in_regs_p
= save_local_in_regs_p
;
5298 /* Implement the macro INITIAL_ELIMINATION_OFFSET, return the OFFSET. */
5301 sparc_initial_elimination_offset (int to
)
5305 if (to
== STACK_POINTER_REGNUM
)
5306 offset
= sparc_compute_frame_size (get_frame_size (), crtl
->is_leaf
);
5310 offset
+= SPARC_STACK_BIAS
;
5314 /* Output any necessary .register pseudo-ops. */
5317 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED
)
5319 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
5325 /* Check if %g[2367] were used without
5326 .register being printed for them already. */
5327 for (i
= 2; i
< 8; i
++)
5329 if (df_regs_ever_live_p (i
)
5330 && ! sparc_hard_reg_printed
[i
])
5332 sparc_hard_reg_printed
[i
] = 1;
5333 /* %g7 is used as TLS base register, use #ignore
5334 for it instead of #scratch. */
5335 fprintf (file
, "\t.register\t%%g%d, #%s\n", i
,
5336 i
== 7 ? "ignore" : "scratch");
5343 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
5345 #if PROBE_INTERVAL > 4096
5346 #error Cannot use indexed addressing mode for stack probing
5349 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
5350 inclusive. These are offsets from the current stack pointer.
5352 Note that we don't use the REG+REG addressing mode for the probes because
5353 of the stack bias in 64-bit mode. And it doesn't really buy us anything
5354 so the advantages of having a single code win here. */
5357 sparc_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
5359 rtx g1
= gen_rtx_REG (Pmode
, 1);
5361 /* See if we have a constant small number of probes to generate. If so,
5362 that's the easy case. */
5363 if (size
<= PROBE_INTERVAL
)
5365 emit_move_insn (g1
, GEN_INT (first
));
5366 emit_insn (gen_rtx_SET (g1
,
5367 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
5368 emit_stack_probe (plus_constant (Pmode
, g1
, -size
));
5371 /* The run-time loop is made up of 9 insns in the generic case while the
5372 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
5373 else if (size
<= 4 * PROBE_INTERVAL
)
5377 emit_move_insn (g1
, GEN_INT (first
+ PROBE_INTERVAL
));
5378 emit_insn (gen_rtx_SET (g1
,
5379 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
5380 emit_stack_probe (g1
);
5382 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
5383 it exceeds SIZE. If only two probes are needed, this will not
5384 generate any code. Then probe at FIRST + SIZE. */
5385 for (i
= 2 * PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
5387 emit_insn (gen_rtx_SET (g1
,
5388 plus_constant (Pmode
, g1
, -PROBE_INTERVAL
)));
5389 emit_stack_probe (g1
);
5392 emit_stack_probe (plus_constant (Pmode
, g1
,
5393 (i
- PROBE_INTERVAL
) - size
));
5396 /* Otherwise, do the same as above, but in a loop. Note that we must be
5397 extra careful with variables wrapping around because we might be at
5398 the very top (or the very bottom) of the address space and we have
5399 to be able to handle this case properly; in particular, we use an
5400 equality test for the loop condition. */
5403 HOST_WIDE_INT rounded_size
;
5404 rtx g4
= gen_rtx_REG (Pmode
, 4);
5406 emit_move_insn (g1
, GEN_INT (first
));
5409 /* Step 1: round SIZE to the previous multiple of the interval. */
5411 rounded_size
= ROUND_DOWN (size
, PROBE_INTERVAL
);
5412 emit_move_insn (g4
, GEN_INT (rounded_size
));
5415 /* Step 2: compute initial and final value of the loop counter. */
5417 /* TEST_ADDR = SP + FIRST. */
5418 emit_insn (gen_rtx_SET (g1
,
5419 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
5421 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
5422 emit_insn (gen_rtx_SET (g4
, gen_rtx_MINUS (Pmode
, g1
, g4
)));
5427 while (TEST_ADDR != LAST_ADDR)
5429 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
5433 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
5434 until it is equal to ROUNDED_SIZE. */
5437 emit_insn (gen_probe_stack_rangedi (g1
, g1
, g4
));
5439 emit_insn (gen_probe_stack_rangesi (g1
, g1
, g4
));
5442 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
5443 that SIZE is equal to ROUNDED_SIZE. */
5445 if (size
!= rounded_size
)
5446 emit_stack_probe (plus_constant (Pmode
, g4
, rounded_size
- size
));
5449 /* Make sure nothing is scheduled before we are done. */
5450 emit_insn (gen_blockage ());
5453 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
5454 absolute addresses. */
5457 output_probe_stack_range (rtx reg1
, rtx reg2
)
5459 static int labelno
= 0;
5463 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
++);
5466 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
5468 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
5470 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
5471 output_asm_insn ("add\t%0, %1, %0", xops
);
5473 /* Test if TEST_ADDR == LAST_ADDR. */
5475 output_asm_insn ("cmp\t%0, %1", xops
);
5477 /* Probe at TEST_ADDR and branch. */
5479 fputs ("\tbne,pt\t%xcc,", asm_out_file
);
5481 fputs ("\tbne\t", asm_out_file
);
5482 assemble_name_raw (asm_out_file
, loop_lab
);
5483 fputc ('\n', asm_out_file
);
5484 xops
[1] = GEN_INT (SPARC_STACK_BIAS
);
5485 output_asm_insn (" st\t%%g0, [%0+%1]", xops
);
5490 /* Emit code to save/restore registers from LOW to HIGH at BASE+OFFSET as
5491 needed. LOW is supposed to be double-word aligned for 32-bit registers.
5492 SAVE_P decides whether a register must be saved/restored. ACTION_TRUE
5493 is the action to be performed if SAVE_P returns true and ACTION_FALSE
5494 the action to be performed if it returns false. Return the new offset. */
5496 typedef bool (*sorr_pred_t
) (unsigned int, int);
5497 typedef enum { SORR_NONE
, SORR_ADVANCE
, SORR_SAVE
, SORR_RESTORE
} sorr_act_t
;
5500 emit_save_or_restore_regs (unsigned int low
, unsigned int high
, rtx base
,
5501 int offset
, int leaf_function
, sorr_pred_t save_p
,
5502 sorr_act_t action_true
, sorr_act_t action_false
)
5508 if (TARGET_ARCH64
&& high
<= 32)
5512 for (i
= low
; i
< high
; i
++)
5514 if (save_p (i
, leaf_function
))
5516 mem
= gen_frame_mem (DImode
, plus_constant (Pmode
,
5518 if (action_true
== SORR_SAVE
)
5520 insn
= emit_move_insn (mem
, gen_rtx_REG (DImode
, i
));
5521 RTX_FRAME_RELATED_P (insn
) = 1;
5523 else /* action_true == SORR_RESTORE */
5525 /* The frame pointer must be restored last since its old
5526 value may be used as base address for the frame. This
5527 is problematic in 64-bit mode only because of the lack
5528 of double-word load instruction. */
5529 if (i
== HARD_FRAME_POINTER_REGNUM
)
5532 emit_move_insn (gen_rtx_REG (DImode
, i
), mem
);
5536 else if (action_false
== SORR_ADVANCE
)
5542 mem
= gen_frame_mem (DImode
, plus_constant (Pmode
, base
, fp_offset
));
5543 emit_move_insn (hard_frame_pointer_rtx
, mem
);
5548 for (i
= low
; i
< high
; i
+= 2)
5550 bool reg0
= save_p (i
, leaf_function
);
5551 bool reg1
= save_p (i
+ 1, leaf_function
);
5557 mode
= SPARC_INT_REG_P (i
) ? E_DImode
: E_DFmode
;
5562 mode
= SPARC_INT_REG_P (i
) ? E_SImode
: E_SFmode
;
5567 mode
= SPARC_INT_REG_P (i
) ? E_SImode
: E_SFmode
;
5573 if (action_false
== SORR_ADVANCE
)
5578 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, base
, offset
));
5579 if (action_true
== SORR_SAVE
)
5581 insn
= emit_move_insn (mem
, gen_rtx_REG (mode
, regno
));
5582 RTX_FRAME_RELATED_P (insn
) = 1;
5586 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, base
,
5588 set1
= gen_rtx_SET (mem
, gen_rtx_REG (SImode
, regno
));
5589 RTX_FRAME_RELATED_P (set1
) = 1;
5591 = gen_frame_mem (SImode
, plus_constant (Pmode
, base
,
5593 set2
= gen_rtx_SET (mem
, gen_rtx_REG (SImode
, regno
+ 1));
5594 RTX_FRAME_RELATED_P (set2
) = 1;
5595 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
5596 gen_rtx_PARALLEL (VOIDmode
,
5597 gen_rtvec (2, set1
, set2
)));
5600 else /* action_true == SORR_RESTORE */
5601 emit_move_insn (gen_rtx_REG (mode
, regno
), mem
);
5603 /* Bump and round down to double word
5604 in case we already bumped by 4. */
5605 offset
= ROUND_DOWN (offset
+ 8, 8);
5612 /* Emit code to adjust BASE to OFFSET. Return the new base. */
5615 emit_adjust_base_to_offset (rtx base
, int offset
)
5617 /* ??? This might be optimized a little as %g1 might already have a
5618 value close enough that a single add insn will do. */
5619 /* ??? Although, all of this is probably only a temporary fix because
5620 if %g1 can hold a function result, then sparc_expand_epilogue will
5621 lose (the result will be clobbered). */
5622 rtx new_base
= gen_rtx_REG (Pmode
, 1);
5623 emit_move_insn (new_base
, GEN_INT (offset
));
5624 emit_insn (gen_rtx_SET (new_base
, gen_rtx_PLUS (Pmode
, base
, new_base
)));
5628 /* Emit code to save/restore call-saved global and FP registers. */
5631 emit_save_or_restore_global_fp_regs (rtx base
, int offset
, sorr_act_t action
)
5633 if (offset
< -4096 || offset
+ sparc_n_global_fp_regs
* 4 > 4095)
5635 base
= emit_adjust_base_to_offset (base
, offset
);
5640 = emit_save_or_restore_regs (0, 8, base
, offset
, 0,
5641 save_global_or_fp_reg_p
, action
, SORR_NONE
);
5642 emit_save_or_restore_regs (32, TARGET_V9
? 96 : 64, base
, offset
, 0,
5643 save_global_or_fp_reg_p
, action
, SORR_NONE
);
5646 /* Emit code to save/restore call-saved local and in registers. */
5649 emit_save_or_restore_local_in_regs (rtx base
, int offset
, sorr_act_t action
)
5651 if (offset
< -4096 || offset
+ 16 * UNITS_PER_WORD
> 4095)
5653 base
= emit_adjust_base_to_offset (base
, offset
);
5657 emit_save_or_restore_regs (16, 32, base
, offset
, sparc_leaf_function_p
,
5658 save_local_or_in_reg_p
, action
, SORR_ADVANCE
);
5661 /* Emit a window_save insn. */
5664 emit_window_save (rtx increment
)
5666 rtx_insn
*insn
= emit_insn (gen_window_save (increment
));
5667 RTX_FRAME_RELATED_P (insn
) = 1;
5669 /* The incoming return address (%o7) is saved in %i7. */
5670 add_reg_note (insn
, REG_CFA_REGISTER
,
5671 gen_rtx_SET (gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
),
5673 INCOMING_RETURN_ADDR_REGNUM
)));
5675 /* The window save event. */
5676 add_reg_note (insn
, REG_CFA_WINDOW_SAVE
, const0_rtx
);
5678 /* The CFA is %fp, the hard frame pointer. */
5679 add_reg_note (insn
, REG_CFA_DEF_CFA
,
5680 plus_constant (Pmode
, hard_frame_pointer_rtx
,
5681 INCOMING_FRAME_SP_OFFSET
));
5686 /* Generate an increment for the stack pointer. */
5689 gen_stack_pointer_inc (rtx increment
)
5691 return gen_rtx_SET (stack_pointer_rtx
,
5692 gen_rtx_PLUS (Pmode
,
5697 /* Expand the function prologue. The prologue is responsible for reserving
5698 storage for the frame, saving the call-saved registers and loading the
5699 GOT register if needed. */
5702 sparc_expand_prologue (void)
5707 /* Compute a snapshot of crtl->uses_only_leaf_regs. Relying
5708 on the final value of the flag means deferring the prologue/epilogue
5709 expansion until just before the second scheduling pass, which is too
5710 late to emit multiple epilogues or return insns.
5712 Of course we are making the assumption that the value of the flag
5713 will not change between now and its final value. Of the three parts
5714 of the formula, only the last one can reasonably vary. Let's take a
5715 closer look, after assuming that the first two ones are set to true
5716 (otherwise the last value is effectively silenced).
5718 If only_leaf_regs_used returns false, the global predicate will also
5719 be false so the actual frame size calculated below will be positive.
5720 As a consequence, the save_register_window insn will be emitted in
5721 the instruction stream; now this insn explicitly references %fp
5722 which is not a leaf register so only_leaf_regs_used will always
5723 return false subsequently.
5725 If only_leaf_regs_used returns true, we hope that the subsequent
5726 optimization passes won't cause non-leaf registers to pop up. For
5727 example, the regrename pass has special provisions to not rename to
5728 non-leaf registers in a leaf function. */
5729 sparc_leaf_function_p
5730 = optimize
> 0 && crtl
->is_leaf
&& only_leaf_regs_used ();
5732 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
5734 if (flag_stack_usage_info
)
5735 current_function_static_stack_size
= size
;
5737 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
5738 || flag_stack_clash_protection
)
5740 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
5742 if (size
> PROBE_INTERVAL
&& size
> get_stack_check_protect ())
5743 sparc_emit_probe_stack_range (get_stack_check_protect (),
5744 size
- get_stack_check_protect ());
5747 sparc_emit_probe_stack_range (get_stack_check_protect (), size
);
5752 else if (sparc_leaf_function_p
)
5754 rtx size_int_rtx
= GEN_INT (-size
);
5757 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
5758 else if (size
<= 8192)
5760 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
5761 RTX_FRAME_RELATED_P (insn
) = 1;
5763 /* %sp is still the CFA register. */
5764 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
5768 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
5769 emit_move_insn (size_rtx
, size_int_rtx
);
5770 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
5771 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
5772 gen_stack_pointer_inc (size_int_rtx
));
5775 RTX_FRAME_RELATED_P (insn
) = 1;
5779 rtx size_int_rtx
= GEN_INT (-size
);
5782 emit_window_save (size_int_rtx
);
5783 else if (size
<= 8192)
5785 emit_window_save (GEN_INT (-4096));
5787 /* %sp is not the CFA register anymore. */
5788 emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
5790 /* Make sure no %fp-based store is issued until after the frame is
5791 established. The offset between the frame pointer and the stack
5792 pointer is calculated relative to the value of the stack pointer
5793 at the end of the function prologue, and moving instructions that
5794 access the stack via the frame pointer between the instructions
5795 that decrement the stack pointer could result in accessing the
5796 register window save area, which is volatile. */
5797 emit_insn (gen_frame_blockage ());
5801 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
5802 emit_move_insn (size_rtx
, size_int_rtx
);
5803 emit_window_save (size_rtx
);
5807 if (sparc_leaf_function_p
)
5809 sparc_frame_base_reg
= stack_pointer_rtx
;
5810 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
5814 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
5815 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
5818 if (sparc_n_global_fp_regs
> 0)
5819 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5820 sparc_frame_base_offset
5821 - sparc_apparent_frame_size
,
5824 /* Load the GOT register if needed. */
5825 if (crtl
->uses_pic_offset_table
)
5826 load_got_register ();
5828 /* Advertise that the data calculated just above are now valid. */
5829 sparc_prologue_data_valid_p
= true;
5832 /* Expand the function prologue. The prologue is responsible for reserving
5833 storage for the frame, saving the call-saved registers and loading the
5834 GOT register if needed. */
5837 sparc_flat_expand_prologue (void)
5842 sparc_leaf_function_p
= optimize
> 0 && crtl
->is_leaf
;
5844 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
5846 if (flag_stack_usage_info
)
5847 current_function_static_stack_size
= size
;
5849 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
5850 || flag_stack_clash_protection
)
5852 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
5854 if (size
> PROBE_INTERVAL
&& size
> get_stack_check_protect ())
5855 sparc_emit_probe_stack_range (get_stack_check_protect (),
5856 size
- get_stack_check_protect ());
5859 sparc_emit_probe_stack_range (get_stack_check_protect (), size
);
5862 if (sparc_save_local_in_regs_p
)
5863 emit_save_or_restore_local_in_regs (stack_pointer_rtx
, SPARC_STACK_BIAS
,
5870 rtx size_int_rtx
, size_rtx
;
5872 size_rtx
= size_int_rtx
= GEN_INT (-size
);
5874 /* We establish the frame (i.e. decrement the stack pointer) first, even
5875 if we use a frame pointer, because we cannot clobber any call-saved
5876 registers, including the frame pointer, if we haven't created a new
5877 register save area, for the sake of compatibility with the ABI. */
5879 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
5880 else if (size
<= 8192 && !frame_pointer_needed
)
5882 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
5883 RTX_FRAME_RELATED_P (insn
) = 1;
5884 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
5888 size_rtx
= gen_rtx_REG (Pmode
, 1);
5889 emit_move_insn (size_rtx
, size_int_rtx
);
5890 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
5891 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
5892 gen_stack_pointer_inc (size_int_rtx
));
5894 RTX_FRAME_RELATED_P (insn
) = 1;
5896 /* Ensure nothing is scheduled until after the frame is established. */
5897 emit_insn (gen_blockage ());
5899 if (frame_pointer_needed
)
5901 insn
= emit_insn (gen_rtx_SET (hard_frame_pointer_rtx
,
5902 gen_rtx_MINUS (Pmode
,
5905 RTX_FRAME_RELATED_P (insn
) = 1;
5907 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
5908 gen_rtx_SET (hard_frame_pointer_rtx
,
5909 plus_constant (Pmode
, stack_pointer_rtx
,
5913 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
5915 rtx o7
= gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
);
5916 rtx i7
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
5918 insn
= emit_move_insn (i7
, o7
);
5919 RTX_FRAME_RELATED_P (insn
) = 1;
5921 add_reg_note (insn
, REG_CFA_REGISTER
, gen_rtx_SET (i7
, o7
));
5923 /* Prevent this instruction from ever being considered dead,
5924 even if this function has no epilogue. */
5929 if (frame_pointer_needed
)
5931 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
5932 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
5936 sparc_frame_base_reg
= stack_pointer_rtx
;
5937 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
5940 if (sparc_n_global_fp_regs
> 0)
5941 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5942 sparc_frame_base_offset
5943 - sparc_apparent_frame_size
,
5946 /* Load the GOT register if needed. */
5947 if (crtl
->uses_pic_offset_table
)
5948 load_got_register ();
5950 /* Advertise that the data calculated just above are now valid. */
5951 sparc_prologue_data_valid_p
= true;
5954 /* This function generates the assembly code for function entry, which boils
5955 down to emitting the necessary .register directives. */
5958 sparc_asm_function_prologue (FILE *file
)
5960 /* Check that the assumption we made in sparc_expand_prologue is valid. */
5962 gcc_assert (sparc_leaf_function_p
== crtl
->uses_only_leaf_regs
);
5964 sparc_output_scratch_registers (file
);
5967 /* Expand the function epilogue, either normal or part of a sibcall.
5968 We emit all the instructions except the return or the call. */
5971 sparc_expand_epilogue (bool for_eh
)
5973 HOST_WIDE_INT size
= sparc_frame_size
;
5975 if (cfun
->calls_alloca
)
5976 emit_insn (gen_frame_blockage ());
5978 if (sparc_n_global_fp_regs
> 0)
5979 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5980 sparc_frame_base_offset
5981 - sparc_apparent_frame_size
,
5984 if (size
== 0 || for_eh
)
5986 else if (sparc_leaf_function_p
)
5989 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
5990 else if (size
<= 8192)
5992 emit_insn (gen_stack_pointer_inc (GEN_INT (4096)));
5993 emit_insn (gen_stack_pointer_inc (GEN_INT (size
- 4096)));
5997 rtx reg
= gen_rtx_REG (Pmode
, 1);
5998 emit_move_insn (reg
, GEN_INT (size
));
5999 emit_insn (gen_stack_pointer_inc (reg
));
6004 /* Expand the function epilogue, either normal or part of a sibcall.
6005 We emit all the instructions except the return or the call. */
6008 sparc_flat_expand_epilogue (bool for_eh
)
6010 HOST_WIDE_INT size
= sparc_frame_size
;
6012 if (sparc_n_global_fp_regs
> 0)
6013 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
6014 sparc_frame_base_offset
6015 - sparc_apparent_frame_size
,
6018 /* If we have a frame pointer, we'll need both to restore it before the
6019 frame is destroyed and use its current value in destroying the frame.
6020 Since we don't have an atomic way to do that in the flat window model,
6021 we save the current value into a temporary register (%g1). */
6022 if (frame_pointer_needed
&& !for_eh
)
6023 emit_move_insn (gen_rtx_REG (Pmode
, 1), hard_frame_pointer_rtx
);
6025 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
6026 emit_move_insn (gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
),
6027 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
));
6029 if (sparc_save_local_in_regs_p
)
6030 emit_save_or_restore_local_in_regs (sparc_frame_base_reg
,
6031 sparc_frame_base_offset
,
6034 if (size
== 0 || for_eh
)
6036 else if (frame_pointer_needed
)
6038 /* Make sure the frame is destroyed after everything else is done. */
6039 emit_insn (gen_blockage ());
6041 emit_move_insn (stack_pointer_rtx
, gen_rtx_REG (Pmode
, 1));
6046 emit_insn (gen_blockage ());
6049 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
6050 else if (size
<= 8192)
6052 emit_insn (gen_stack_pointer_inc (GEN_INT (4096)));
6053 emit_insn (gen_stack_pointer_inc (GEN_INT (size
- 4096)));
6057 rtx reg
= gen_rtx_REG (Pmode
, 1);
6058 emit_move_insn (reg
, GEN_INT (size
));
6059 emit_insn (gen_stack_pointer_inc (reg
));
6064 /* Return true if it is appropriate to emit `return' instructions in the
6065 body of a function. */
6068 sparc_can_use_return_insn_p (void)
6070 return sparc_prologue_data_valid_p
6071 && sparc_n_global_fp_regs
== 0
6073 ? (sparc_frame_size
== 0 && !sparc_save_local_in_regs_p
)
6074 : (sparc_frame_size
== 0 || !sparc_leaf_function_p
);
6077 /* This function generates the assembly code for function exit. */
6080 sparc_asm_function_epilogue (FILE *file
)
6082 /* If the last two instructions of a function are "call foo; dslot;"
6083 the return address might point to the first instruction in the next
6084 function and we have to output a dummy nop for the sake of sane
6085 backtraces in such cases. This is pointless for sibling calls since
6086 the return address is explicitly adjusted. */
6088 rtx_insn
*insn
= get_last_insn ();
6090 rtx last_real_insn
= prev_real_insn (insn
);
6092 && NONJUMP_INSN_P (last_real_insn
)
6093 && GET_CODE (PATTERN (last_real_insn
)) == SEQUENCE
)
6094 last_real_insn
= XVECEXP (PATTERN (last_real_insn
), 0, 0);
6097 && CALL_P (last_real_insn
)
6098 && !SIBLING_CALL_P (last_real_insn
))
6099 fputs("\tnop\n", file
);
6101 sparc_output_deferred_case_vectors ();
6104 /* Output a 'restore' instruction. */
6107 output_restore (rtx pat
)
6113 fputs ("\t restore\n", asm_out_file
);
6117 gcc_assert (GET_CODE (pat
) == SET
);
6119 operands
[0] = SET_DEST (pat
);
6120 pat
= SET_SRC (pat
);
6122 switch (GET_CODE (pat
))
6125 operands
[1] = XEXP (pat
, 0);
6126 operands
[2] = XEXP (pat
, 1);
6127 output_asm_insn (" restore %r1, %2, %Y0", operands
);
6130 operands
[1] = XEXP (pat
, 0);
6131 operands
[2] = XEXP (pat
, 1);
6132 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands
);
6135 operands
[1] = XEXP (pat
, 0);
6136 gcc_assert (XEXP (pat
, 1) == const1_rtx
);
6137 output_asm_insn (" restore %r1, %r1, %Y0", operands
);
6141 output_asm_insn (" restore %%g0, %1, %Y0", operands
);
6146 /* Output a return. */
6149 output_return (rtx_insn
*insn
)
6151 if (crtl
->calls_eh_return
)
6153 /* If the function uses __builtin_eh_return, the eh_return
6154 machinery occupies the delay slot. */
6155 gcc_assert (!final_sequence
);
6157 if (flag_delayed_branch
)
6159 if (!TARGET_FLAT
&& TARGET_V9
)
6160 fputs ("\treturn\t%i7+8\n", asm_out_file
);
6164 fputs ("\trestore\n", asm_out_file
);
6166 fputs ("\tjmp\t%o7+8\n", asm_out_file
);
6169 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file
);
6174 fputs ("\trestore\n", asm_out_file
);
6176 fputs ("\tadd\t%sp, %g1, %sp\n", asm_out_file
);
6177 fputs ("\tjmp\t%o7+8\n\t nop\n", asm_out_file
);
6180 else if (sparc_leaf_function_p
|| TARGET_FLAT
)
6182 /* This is a leaf or flat function so we don't have to bother restoring
6183 the register window, which frees us from dealing with the convoluted
6184 semantics of restore/return. We simply output the jump to the
6185 return address and the insn in the delay slot (if any). */
6187 return "jmp\t%%o7+%)%#";
6191 /* This is a regular function so we have to restore the register window.
6192 We may have a pending insn for the delay slot, which will be either
6193 combined with the 'restore' instruction or put in the delay slot of
6194 the 'return' instruction. */
6202 delay
= NEXT_INSN (insn
);
6205 pat
= PATTERN (delay
);
6207 if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1))
6209 epilogue_renumber (&pat
, 0);
6210 return "return\t%%i7+%)%#";
6214 output_asm_insn ("jmp\t%%i7+%)", NULL
);
6216 /* We're going to output the insn in the delay slot manually.
6217 Make sure to output its source location first. */
6218 PATTERN (delay
) = gen_blockage ();
6219 INSN_CODE (delay
) = -1;
6220 final_scan_insn (delay
, asm_out_file
, optimize
, 0, &seen
);
6221 INSN_LOCATION (delay
) = UNKNOWN_LOCATION
;
6223 output_restore (pat
);
6228 /* The delay slot is empty. */
6230 return "return\t%%i7+%)\n\t nop";
6231 else if (flag_delayed_branch
)
6232 return "jmp\t%%i7+%)\n\t restore";
6234 return "restore\n\tjmp\t%%o7+%)\n\t nop";
6241 /* Output a sibling call. */
6244 output_sibcall (rtx_insn
*insn
, rtx call_operand
)
6248 gcc_assert (flag_delayed_branch
);
6250 operands
[0] = call_operand
;
6252 if (sparc_leaf_function_p
|| TARGET_FLAT
)
6254 /* This is a leaf or flat function so we don't have to bother restoring
6255 the register window. We simply output the jump to the function and
6256 the insn in the delay slot (if any). */
6258 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P
&& final_sequence
));
6261 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
6264 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
6265 it into branch if possible. */
6266 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
6271 /* This is a regular function so we have to restore the register window.
6272 We may have a pending insn for the delay slot, which will be combined
6273 with the 'restore' instruction. */
6275 output_asm_insn ("call\t%a0, 0", operands
);
6283 delay
= NEXT_INSN (insn
);
6286 pat
= PATTERN (delay
);
6288 /* We're going to output the insn in the delay slot manually.
6289 Make sure to output its source location first. */
6290 PATTERN (delay
) = gen_blockage ();
6291 INSN_CODE (delay
) = -1;
6292 final_scan_insn (delay
, asm_out_file
, optimize
, 0, &seen
);
6293 INSN_LOCATION (delay
) = UNKNOWN_LOCATION
;
6295 output_restore (pat
);
6298 output_restore (NULL_RTX
);
6304 /* Functions for handling argument passing.
6306 For 32-bit, the first 6 args are normally in registers and the rest are
6307 pushed. Any arg that starts within the first 6 words is at least
6308 partially passed in a register unless its data type forbids.
6310 For 64-bit, the argument registers are laid out as an array of 16 elements
6311 and arguments are added sequentially. The first 6 int args and up to the
6312 first 16 fp args (depending on size) are passed in regs.
6314 Slot Stack Integral Float Float in structure Double Long Double
6315 ---- ----- -------- ----- ------------------ ------ -----------
6316 15 [SP+248] %f31 %f30,%f31 %d30
6317 14 [SP+240] %f29 %f28,%f29 %d28 %q28
6318 13 [SP+232] %f27 %f26,%f27 %d26
6319 12 [SP+224] %f25 %f24,%f25 %d24 %q24
6320 11 [SP+216] %f23 %f22,%f23 %d22
6321 10 [SP+208] %f21 %f20,%f21 %d20 %q20
6322 9 [SP+200] %f19 %f18,%f19 %d18
6323 8 [SP+192] %f17 %f16,%f17 %d16 %q16
6324 7 [SP+184] %f15 %f14,%f15 %d14
6325 6 [SP+176] %f13 %f12,%f13 %d12 %q12
6326 5 [SP+168] %o5 %f11 %f10,%f11 %d10
6327 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
6328 3 [SP+152] %o3 %f7 %f6,%f7 %d6
6329 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
6330 1 [SP+136] %o1 %f3 %f2,%f3 %d2
6331 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
6333 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
6335 Integral arguments are always passed as 64-bit quantities appropriately
6338 Passing of floating point values is handled as follows.
6339 If a prototype is in scope:
6340 If the value is in a named argument (i.e. not a stdarg function or a
6341 value not part of the `...') then the value is passed in the appropriate
6343 If the value is part of the `...' and is passed in one of the first 6
6344 slots then the value is passed in the appropriate int reg.
6345 If the value is part of the `...' and is not passed in one of the first 6
6346 slots then the value is passed in memory.
6347 If a prototype is not in scope:
6348 If the value is one of the first 6 arguments the value is passed in the
6349 appropriate integer reg and the appropriate fp reg.
6350 If the value is not one of the first 6 arguments the value is passed in
6351 the appropriate fp reg and in memory.
6354 Summary of the calling conventions implemented by GCC on the SPARC:
6357 size argument return value
6359 small integer <4 int. reg. int. reg.
6360 word 4 int. reg. int. reg.
6361 double word 8 int. reg. int. reg.
6363 _Complex small integer <8 int. reg. int. reg.
6364 _Complex word 8 int. reg. int. reg.
6365 _Complex double word 16 memory int. reg.
6367 vector integer <=8 int. reg. FP reg.
6368 vector integer >8 memory memory
6370 float 4 int. reg. FP reg.
6371 double 8 int. reg. FP reg.
6372 long double 16 memory memory
6374 _Complex float 8 memory FP reg.
6375 _Complex double 16 memory FP reg.
6376 _Complex long double 32 memory FP reg.
6378 vector float any memory memory
6380 aggregate any memory memory
6385 size argument return value
6387 small integer <8 int. reg. int. reg.
6388 word 8 int. reg. int. reg.
6389 double word 16 int. reg. int. reg.
6391 _Complex small integer <16 int. reg. int. reg.
6392 _Complex word 16 int. reg. int. reg.
6393 _Complex double word 32 memory int. reg.
6395 vector integer <=16 FP reg. FP reg.
6396 vector integer 16<s<=32 memory FP reg.
6397 vector integer >32 memory memory
6399 float 4 FP reg. FP reg.
6400 double 8 FP reg. FP reg.
6401 long double 16 FP reg. FP reg.
6403 _Complex float 8 FP reg. FP reg.
6404 _Complex double 16 FP reg. FP reg.
6405 _Complex long double 32 memory FP reg.
6407 vector float <=16 FP reg. FP reg.
6408 vector float 16<s<=32 memory FP reg.
6409 vector float >32 memory memory
6411 aggregate <=16 reg. reg.
6412 aggregate 16<s<=32 memory reg.
6413 aggregate >32 memory memory
6417 Note #1: complex floating-point types follow the extended SPARC ABIs as
6418 implemented by the Sun compiler.
6420 Note #2: integral vector types follow the scalar floating-point types
6421 conventions to match what is implemented by the Sun VIS SDK.
6423 Note #3: floating-point vector types follow the aggregate types
6427 /* Maximum number of int regs for args. */
6428 #define SPARC_INT_ARG_MAX 6
6429 /* Maximum number of fp regs for args. */
6430 #define SPARC_FP_ARG_MAX 16
6431 /* Number of words (partially) occupied for a given size in units. */
6432 #define CEIL_NWORDS(SIZE) CEIL((SIZE), UNITS_PER_WORD)
6434 /* Handle the INIT_CUMULATIVE_ARGS macro.
6435 Initialize a variable CUM of type CUMULATIVE_ARGS
6436 for a call to a function whose data type is FNTYPE.
6437 For a library call, FNTYPE is 0. */
6440 init_cumulative_args (struct sparc_args
*cum
, tree fntype
, rtx
, tree
)
6443 cum
->prototype_p
= fntype
&& prototype_p (fntype
);
6444 cum
->libcall_p
= !fntype
;
6447 /* Handle promotion of pointer and integer arguments. */
6450 sparc_promote_function_mode (const_tree type
, machine_mode mode
,
6451 int *punsignedp
, const_tree
, int)
6453 if (type
&& POINTER_TYPE_P (type
))
6455 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
6459 /* Integral arguments are passed as full words, as per the ABI. */
6460 if (GET_MODE_CLASS (mode
) == MODE_INT
6461 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
6467 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
6470 sparc_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
6472 return TARGET_ARCH64
? true : false;
6475 /* Traverse the record TYPE recursively and call FUNC on its fields.
6476 NAMED is true if this is for a named parameter. DATA is passed
6477 to FUNC for each field. OFFSET is the starting position and
6478 PACKED is true if we are inside a packed record. */
6480 template <typename T
, void Func (const_tree
, HOST_WIDE_INT
, bool, T
*)>
6482 traverse_record_type (const_tree type
, bool named
, T
*data
,
6483 HOST_WIDE_INT offset
= 0, bool packed
= false)
6485 /* The ABI obviously doesn't specify how packed structures are passed.
6486 These are passed in integer regs if possible, otherwise memory. */
6488 for (tree field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
6489 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
6495 /* Walk the real fields, but skip those with no size or a zero size.
6496 ??? Fields with variable offset are handled as having zero offset. */
6497 for (tree field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
6498 if (TREE_CODE (field
) == FIELD_DECL
)
6500 if (!DECL_SIZE (field
) || integer_zerop (DECL_SIZE (field
)))
6503 HOST_WIDE_INT bitpos
= offset
;
6504 if (TREE_CODE (DECL_FIELD_OFFSET (field
)) == INTEGER_CST
)
6505 bitpos
+= int_bit_position (field
);
6507 tree field_type
= TREE_TYPE (field
);
6508 if (TREE_CODE (field_type
) == RECORD_TYPE
)
6509 traverse_record_type
<T
, Func
> (field_type
, named
, data
, bitpos
,
6514 = FLOAT_TYPE_P (field_type
) || VECTOR_TYPE_P (field_type
);
6515 Func (field
, bitpos
, fp_type
&& named
&& !packed
&& TARGET_FPU
,
6521 /* Handle recursive register classifying for structure layout. */
6525 bool fp_regs
; /* true if field eligible to FP registers. */
6526 bool fp_regs_in_first_word
; /* true if such field in first word. */
6529 /* A subroutine of function_arg_slotno. Classify the field. */
6532 classify_registers (const_tree
, HOST_WIDE_INT bitpos
, bool fp
,
6533 classify_data_t
*data
)
6537 data
->fp_regs
= true;
6538 if (bitpos
< BITS_PER_WORD
)
6539 data
->fp_regs_in_first_word
= true;
6543 /* Compute the slot number to pass an argument in.
6544 Return the slot number or -1 if passing on the stack.
6546 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6547 the preceding args and about the function being called.
6548 MODE is the argument's machine mode.
6549 TYPE is the data type of the argument (as a tree).
6550 This is null for libcalls where that information may
6552 NAMED is nonzero if this argument is a named parameter
6553 (otherwise it is an extra parameter matching an ellipsis).
6554 INCOMING is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
6555 *PREGNO records the register number to use if scalar type.
6556 *PPADDING records the amount of padding needed in words. */
6559 function_arg_slotno (const struct sparc_args
*cum
, machine_mode mode
,
6560 const_tree type
, bool named
, bool incoming
,
6561 int *pregno
, int *ppadding
)
6563 int regbase
= (incoming
6564 ? SPARC_INCOMING_INT_ARG_FIRST
6565 : SPARC_OUTGOING_INT_ARG_FIRST
);
6566 int slotno
= cum
->words
;
6567 enum mode_class mclass
;
6572 if (type
&& TREE_ADDRESSABLE (type
))
6578 && TYPE_ALIGN (type
) % PARM_BOUNDARY
!= 0)
6581 /* For SPARC64, objects requiring 16-byte alignment get it. */
6583 && (type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
)) >= 128
6584 && (slotno
& 1) != 0)
6585 slotno
++, *ppadding
= 1;
6587 mclass
= GET_MODE_CLASS (mode
);
6588 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
6590 /* Vector types deserve special treatment because they are
6591 polymorphic wrt their mode, depending upon whether VIS
6592 instructions are enabled. */
6593 if (TREE_CODE (TREE_TYPE (type
)) == REAL_TYPE
)
6595 /* The SPARC port defines no floating-point vector modes. */
6596 gcc_assert (mode
== BLKmode
);
6600 /* Integral vector types should either have a vector
6601 mode or an integral mode, because we are guaranteed
6602 by pass_by_reference that their size is not greater
6603 than 16 bytes and TImode is 16-byte wide. */
6604 gcc_assert (mode
!= BLKmode
);
6606 /* Vector integers are handled like floats according to
6608 mclass
= MODE_FLOAT
;
6615 case MODE_COMPLEX_FLOAT
:
6616 case MODE_VECTOR_INT
:
6617 if (TARGET_ARCH64
&& TARGET_FPU
&& named
)
6619 /* If all arg slots are filled, then must pass on stack. */
6620 if (slotno
>= SPARC_FP_ARG_MAX
)
6623 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
6624 /* Arguments filling only one single FP register are
6625 right-justified in the outer double FP register. */
6626 if (GET_MODE_SIZE (mode
) <= 4)
6633 case MODE_COMPLEX_INT
:
6634 /* If all arg slots are filled, then must pass on stack. */
6635 if (slotno
>= SPARC_INT_ARG_MAX
)
6638 regno
= regbase
+ slotno
;
6642 if (mode
== VOIDmode
)
6643 /* MODE is VOIDmode when generating the actual call. */
6646 gcc_assert (mode
== BLKmode
);
6650 || (TREE_CODE (type
) != RECORD_TYPE
6651 && TREE_CODE (type
) != VECTOR_TYPE
))
6653 /* If all arg slots are filled, then must pass on stack. */
6654 if (slotno
>= SPARC_INT_ARG_MAX
)
6657 regno
= regbase
+ slotno
;
6659 else /* TARGET_ARCH64 && type */
6661 /* If all arg slots are filled, then must pass on stack. */
6662 if (slotno
>= SPARC_FP_ARG_MAX
)
6665 if (TREE_CODE (type
) == RECORD_TYPE
)
6667 classify_data_t data
= { false, false };
6668 traverse_record_type
<classify_data_t
, classify_registers
>
6669 (type
, named
, &data
);
6673 /* If all FP slots are filled except for the last one and
6674 there is no FP field in the first word, then must pass
6676 if (slotno
>= SPARC_FP_ARG_MAX
- 1
6677 && !data
.fp_regs_in_first_word
)
6682 /* If all int slots are filled, then must pass on stack. */
6683 if (slotno
>= SPARC_INT_ARG_MAX
)
6688 /* PREGNO isn't set since both int and FP regs can be used. */
6701 /* Handle recursive register counting/assigning for structure layout. */
6705 int slotno
; /* slot number of the argument. */
6706 int regbase
; /* regno of the base register. */
6707 int intoffset
; /* offset of the first pending integer field. */
6708 int nregs
; /* number of words passed in registers. */
6709 bool stack
; /* true if part of the argument is on the stack. */
6710 rtx ret
; /* return expression being built. */
6713 /* A subroutine of function_arg_record_value. Compute the number of integer
6714 registers to be assigned between PARMS->intoffset and BITPOS. Return
6715 true if at least one integer register is assigned or false otherwise. */
6718 compute_int_layout (HOST_WIDE_INT bitpos
, assign_data_t
*data
, int *pnregs
)
6720 if (data
->intoffset
< 0)
6723 const int intoffset
= data
->intoffset
;
6724 data
->intoffset
= -1;
6726 const int this_slotno
= data
->slotno
+ intoffset
/ BITS_PER_WORD
;
6727 const unsigned int startbit
= ROUND_DOWN (intoffset
, BITS_PER_WORD
);
6728 const unsigned int endbit
= ROUND_UP (bitpos
, BITS_PER_WORD
);
6729 int nregs
= (endbit
- startbit
) / BITS_PER_WORD
;
6731 if (nregs
> 0 && nregs
> SPARC_INT_ARG_MAX
- this_slotno
)
6733 nregs
= SPARC_INT_ARG_MAX
- this_slotno
;
6735 /* We need to pass this field (partly) on the stack. */
6746 /* A subroutine of function_arg_record_value. Compute the number and the mode
6747 of the FP registers to be assigned for FIELD. Return true if at least one
6748 FP register is assigned or false otherwise. */
6751 compute_fp_layout (const_tree field
, HOST_WIDE_INT bitpos
,
6752 assign_data_t
*data
,
6753 int *pnregs
, machine_mode
*pmode
)
6755 const int this_slotno
= data
->slotno
+ bitpos
/ BITS_PER_WORD
;
6756 machine_mode mode
= DECL_MODE (field
);
6759 /* Slots are counted as words while regs are counted as having the size of
6760 the (inner) mode. */
6761 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
&& mode
== BLKmode
)
6763 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
6764 nregs
= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
6766 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
6768 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
6774 nslots
= CEIL_NWORDS (nregs
* GET_MODE_SIZE (mode
));
6776 if (nslots
> SPARC_FP_ARG_MAX
- this_slotno
)
6778 nslots
= SPARC_FP_ARG_MAX
- this_slotno
;
6779 nregs
= (nslots
* UNITS_PER_WORD
) / GET_MODE_SIZE (mode
);
6781 /* We need to pass this field (partly) on the stack. */
6793 /* A subroutine of function_arg_record_value. Count the number of registers
6794 to be assigned for FIELD and between PARMS->intoffset and BITPOS. */
6797 count_registers (const_tree field
, HOST_WIDE_INT bitpos
, bool fp
,
6798 assign_data_t
*data
)
6805 if (compute_int_layout (bitpos
, data
, &nregs
))
6806 data
->nregs
+= nregs
;
6808 if (compute_fp_layout (field
, bitpos
, data
, &nregs
, &mode
))
6809 data
->nregs
+= nregs
;
6813 if (data
->intoffset
< 0)
6814 data
->intoffset
= bitpos
;
6818 /* A subroutine of function_arg_record_value. Assign the bits of the
6819 structure between PARMS->intoffset and BITPOS to integer registers. */
6822 assign_int_registers (HOST_WIDE_INT bitpos
, assign_data_t
*data
)
6824 int intoffset
= data
->intoffset
;
6828 if (!compute_int_layout (bitpos
, data
, &nregs
))
6831 /* If this is the trailing part of a word, only load that much into
6832 the register. Otherwise load the whole register. Note that in
6833 the latter case we may pick up unwanted bits. It's not a problem
6834 at the moment but may wish to revisit. */
6835 if (intoffset
% BITS_PER_WORD
!= 0)
6836 mode
= smallest_int_mode_for_size (BITS_PER_WORD
6837 - intoffset
% BITS_PER_WORD
);
6841 const int this_slotno
= data
->slotno
+ intoffset
/ BITS_PER_WORD
;
6842 unsigned int regno
= data
->regbase
+ this_slotno
;
6843 intoffset
/= BITS_PER_UNIT
;
6847 rtx reg
= gen_rtx_REG (mode
, regno
);
6848 XVECEXP (data
->ret
, 0, data
->stack
+ data
->nregs
)
6849 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
6853 intoffset
= (intoffset
| (UNITS_PER_WORD
- 1)) + 1;
6855 while (--nregs
> 0);
6858 /* A subroutine of function_arg_record_value. Assign FIELD at position
6859 BITPOS to FP registers. */
6862 assign_fp_registers (const_tree field
, HOST_WIDE_INT bitpos
,
6863 assign_data_t
*data
)
6868 if (!compute_fp_layout (field
, bitpos
, data
, &nregs
, &mode
))
6871 const int this_slotno
= data
->slotno
+ bitpos
/ BITS_PER_WORD
;
6872 int regno
= SPARC_FP_ARG_FIRST
+ this_slotno
* 2;
6873 if (GET_MODE_SIZE (mode
) <= 4 && (bitpos
& 32) != 0)
6875 int pos
= bitpos
/ BITS_PER_UNIT
;
6879 rtx reg
= gen_rtx_REG (mode
, regno
);
6880 XVECEXP (data
->ret
, 0, data
->stack
+ data
->nregs
)
6881 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
6883 regno
+= GET_MODE_SIZE (mode
) / 4;
6884 pos
+= GET_MODE_SIZE (mode
);
6886 while (--nregs
> 0);
6889 /* A subroutine of function_arg_record_value. Assign FIELD and the bits of
6890 the structure between PARMS->intoffset and BITPOS to registers. */
6893 assign_registers (const_tree field
, HOST_WIDE_INT bitpos
, bool fp
,
6894 assign_data_t
*data
)
6898 assign_int_registers (bitpos
, data
);
6900 assign_fp_registers (field
, bitpos
, data
);
6904 if (data
->intoffset
< 0)
6905 data
->intoffset
= bitpos
;
6909 /* Used by function_arg and sparc_function_value_1 to implement the complex
6910 conventions of the 64-bit ABI for passing and returning structures.
6911 Return an expression valid as a return value for the FUNCTION_ARG
6912 and TARGET_FUNCTION_VALUE.
6914 TYPE is the data type of the argument (as a tree).
6915 This is null for libcalls where that information may
6917 MODE is the argument's machine mode.
6918 SLOTNO is the index number of the argument's slot in the parameter array.
6919 NAMED is true if this argument is a named parameter
6920 (otherwise it is an extra parameter matching an ellipsis).
6921 REGBASE is the regno of the base register for the parameter array. */
6924 function_arg_record_value (const_tree type
, machine_mode mode
,
6925 int slotno
, bool named
, int regbase
)
6927 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
6931 data
.slotno
= slotno
;
6932 data
.regbase
= regbase
;
6934 /* Count how many registers we need. */
6938 traverse_record_type
<assign_data_t
, count_registers
> (type
, named
, &data
);
6940 /* Take into account pending integer fields. */
6941 if (compute_int_layout (typesize
* BITS_PER_UNIT
, &data
, &nregs
))
6942 data
.nregs
+= nregs
;
6944 /* Allocate the vector and handle some annoying special cases. */
6949 /* ??? Empty structure has no value? Duh? */
6952 /* Though there's nothing really to store, return a word register
6953 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
6954 leads to breakage due to the fact that there are zero bytes to
6956 return gen_rtx_REG (mode
, regbase
);
6959 /* ??? C++ has structures with no fields, and yet a size. Give up
6960 for now and pass everything back in integer registers. */
6961 nregs
= (typesize
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6962 if (nregs
+ slotno
> SPARC_INT_ARG_MAX
)
6963 nregs
= SPARC_INT_ARG_MAX
- slotno
;
6966 gcc_assert (nregs
> 0);
6968 data
.ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (data
.stack
+ nregs
));
6970 /* If at least one field must be passed on the stack, generate
6971 (parallel [(expr_list (nil) ...) ...]) so that all fields will
6972 also be passed on the stack. We can't do much better because the
6973 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
6974 of structures for which the fields passed exclusively in registers
6975 are not at the beginning of the structure. */
6977 XVECEXP (data
.ret
, 0, 0)
6978 = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
6980 /* Assign the registers. */
6983 traverse_record_type
<assign_data_t
, assign_registers
> (type
, named
, &data
);
6985 /* Assign pending integer fields. */
6986 assign_int_registers (typesize
* BITS_PER_UNIT
, &data
);
6988 gcc_assert (data
.nregs
== nregs
);
6993 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6994 of the 64-bit ABI for passing and returning unions.
6995 Return an expression valid as a return value for the FUNCTION_ARG
6996 and TARGET_FUNCTION_VALUE.
6998 SIZE is the size in bytes of the union.
6999 MODE is the argument's machine mode.
7000 REGNO is the hard register the union will be passed in. */
7003 function_arg_union_value (int size
, machine_mode mode
, int slotno
,
7006 int nwords
= CEIL_NWORDS (size
), i
;
7009 /* See comment in previous function for empty structures. */
7011 return gen_rtx_REG (mode
, regno
);
7013 if (slotno
== SPARC_INT_ARG_MAX
- 1)
7016 regs
= gen_rtx_PARALLEL (mode
, rtvec_alloc (nwords
));
7018 for (i
= 0; i
< nwords
; i
++)
7020 /* Unions are passed left-justified. */
7021 XVECEXP (regs
, 0, i
)
7022 = gen_rtx_EXPR_LIST (VOIDmode
,
7023 gen_rtx_REG (word_mode
, regno
),
7024 GEN_INT (UNITS_PER_WORD
* i
));
7031 /* Used by function_arg and sparc_function_value_1 to implement the conventions
7032 for passing and returning BLKmode vectors.
7033 Return an expression valid as a return value for the FUNCTION_ARG
7034 and TARGET_FUNCTION_VALUE.
7036 SIZE is the size in bytes of the vector.
7037 REGNO is the FP hard register the vector will be passed in. */
7040 function_arg_vector_value (int size
, int regno
)
7042 const int nregs
= MAX (1, size
/ 8);
7043 rtx regs
= gen_rtx_PARALLEL (BLKmode
, rtvec_alloc (nregs
));
7046 XVECEXP (regs
, 0, 0)
7047 = gen_rtx_EXPR_LIST (VOIDmode
,
7048 gen_rtx_REG (SImode
, regno
),
7051 for (int i
= 0; i
< nregs
; i
++)
7052 XVECEXP (regs
, 0, i
)
7053 = gen_rtx_EXPR_LIST (VOIDmode
,
7054 gen_rtx_REG (DImode
, regno
+ 2*i
),
7060 /* Determine where to put an argument to a function.
7061 Value is zero to push the argument on the stack,
7062 or a hard register in which to store the argument.
7064 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7065 the preceding args and about the function being called.
7066 MODE is the argument's machine mode.
7067 TYPE is the data type of the argument (as a tree).
7068 This is null for libcalls where that information may
7070 NAMED is true if this argument is a named parameter
7071 (otherwise it is an extra parameter matching an ellipsis).
7072 INCOMING_P is false for TARGET_FUNCTION_ARG, true for
7073 TARGET_FUNCTION_INCOMING_ARG. */
7076 sparc_function_arg_1 (cumulative_args_t cum_v
, machine_mode mode
,
7077 const_tree type
, bool named
, bool incoming
)
7079 const CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
7081 int regbase
= (incoming
7082 ? SPARC_INCOMING_INT_ARG_FIRST
7083 : SPARC_OUTGOING_INT_ARG_FIRST
);
7084 int slotno
, regno
, padding
;
7085 enum mode_class mclass
= GET_MODE_CLASS (mode
);
7087 slotno
= function_arg_slotno (cum
, mode
, type
, named
, incoming
,
7092 /* Vector types deserve special treatment because they are polymorphic wrt
7093 their mode, depending upon whether VIS instructions are enabled. */
7094 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
7096 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7097 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
7098 || (TARGET_ARCH64
&& size
<= 16));
7100 if (mode
== BLKmode
)
7101 return function_arg_vector_value (size
, SPARC_FP_ARG_FIRST
+ 2*slotno
);
7103 mclass
= MODE_FLOAT
;
7107 return gen_rtx_REG (mode
, regno
);
7109 /* Structures up to 16 bytes in size are passed in arg slots on the stack
7110 and are promoted to registers if possible. */
7111 if (type
&& TREE_CODE (type
) == RECORD_TYPE
)
7113 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7114 gcc_assert (size
<= 16);
7116 return function_arg_record_value (type
, mode
, slotno
, named
, regbase
);
7119 /* Unions up to 16 bytes in size are passed in integer registers. */
7120 else if (type
&& TREE_CODE (type
) == UNION_TYPE
)
7122 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7123 gcc_assert (size
<= 16);
7125 return function_arg_union_value (size
, mode
, slotno
, regno
);
7128 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
7129 but also have the slot allocated for them.
7130 If no prototype is in scope fp values in register slots get passed
7131 in two places, either fp regs and int regs or fp regs and memory. */
7132 else if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
7133 && SPARC_FP_REG_P (regno
))
7135 rtx reg
= gen_rtx_REG (mode
, regno
);
7136 if (cum
->prototype_p
|| cum
->libcall_p
)
7142 if ((regno
- SPARC_FP_ARG_FIRST
) < SPARC_INT_ARG_MAX
* 2)
7146 /* On incoming, we don't need to know that the value
7147 is passed in %f0 and %i0, and it confuses other parts
7148 causing needless spillage even on the simplest cases. */
7152 intreg
= (SPARC_OUTGOING_INT_ARG_FIRST
7153 + (regno
- SPARC_FP_ARG_FIRST
) / 2);
7155 v0
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
7156 v1
= gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (mode
, intreg
),
7158 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
7162 v0
= gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
7163 v1
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
7164 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
7169 /* All other aggregate types are passed in an integer register in a mode
7170 corresponding to the size of the type. */
7171 else if (type
&& AGGREGATE_TYPE_P (type
))
7173 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7174 gcc_assert (size
<= 16);
7176 mode
= int_mode_for_size (size
* BITS_PER_UNIT
, 0).else_blk ();
7179 return gen_rtx_REG (mode
, regno
);
7182 /* Handle the TARGET_FUNCTION_ARG target hook. */
7185 sparc_function_arg (cumulative_args_t cum
, machine_mode mode
,
7186 const_tree type
, bool named
)
7188 return sparc_function_arg_1 (cum
, mode
, type
, named
, false);
7191 /* Handle the TARGET_FUNCTION_INCOMING_ARG target hook. */
7194 sparc_function_incoming_arg (cumulative_args_t cum
, machine_mode mode
,
7195 const_tree type
, bool named
)
7197 return sparc_function_arg_1 (cum
, mode
, type
, named
, true);
7200 /* For sparc64, objects requiring 16 byte alignment are passed that way. */
7203 sparc_function_arg_boundary (machine_mode mode
, const_tree type
)
7205 return ((TARGET_ARCH64
7206 && (GET_MODE_ALIGNMENT (mode
) == 128
7207 || (type
&& TYPE_ALIGN (type
) == 128)))
7212 /* For an arg passed partly in registers and partly in memory,
7213 this is the number of bytes of registers used.
7214 For args passed entirely in registers or entirely in memory, zero.
7216 Any arg that starts in the first 6 regs but won't entirely fit in them
7217 needs partial registers on v8. On v9, structures with integer
7218 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
7219 values that begin in the last fp reg [where "last fp reg" varies with the
7220 mode] will be split between that reg and memory. */
7223 sparc_arg_partial_bytes (cumulative_args_t cum
, machine_mode mode
,
7224 tree type
, bool named
)
7226 int slotno
, regno
, padding
;
7228 /* We pass false for incoming here, it doesn't matter. */
7229 slotno
= function_arg_slotno (get_cumulative_args (cum
), mode
, type
, named
,
7230 false, ®no
, &padding
);
7237 if ((slotno
+ (mode
== BLKmode
7238 ? CEIL_NWORDS (int_size_in_bytes (type
))
7239 : CEIL_NWORDS (GET_MODE_SIZE (mode
))))
7240 > SPARC_INT_ARG_MAX
)
7241 return (SPARC_INT_ARG_MAX
- slotno
) * UNITS_PER_WORD
;
7245 /* We are guaranteed by pass_by_reference that the size of the
7246 argument is not greater than 16 bytes, so we only need to return
7247 one word if the argument is partially passed in registers. */
7249 if (type
&& AGGREGATE_TYPE_P (type
))
7251 int size
= int_size_in_bytes (type
);
7253 if (size
> UNITS_PER_WORD
7254 && (slotno
== SPARC_INT_ARG_MAX
- 1
7255 || slotno
== SPARC_FP_ARG_MAX
- 1))
7256 return UNITS_PER_WORD
;
7258 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
7259 || (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
7260 && ! (TARGET_FPU
&& named
)))
7262 /* The complex types are passed as packed types. */
7263 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
7264 && slotno
== SPARC_INT_ARG_MAX
- 1)
7265 return UNITS_PER_WORD
;
7267 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
7269 if ((slotno
+ GET_MODE_SIZE (mode
) / UNITS_PER_WORD
)
7271 return UNITS_PER_WORD
;
7278 /* Handle the TARGET_PASS_BY_REFERENCE target hook.
7279 Specify whether to pass the argument by reference. */
7282 sparc_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
7283 machine_mode mode
, const_tree type
,
7284 bool named ATTRIBUTE_UNUSED
)
7287 /* Original SPARC 32-bit ABI says that structures and unions,
7288 and quad-precision floats are passed by reference. For Pascal,
7289 also pass arrays by reference. All other base types are passed
7292 Extended ABI (as implemented by the Sun compiler) says that all
7293 complex floats are passed by reference. Pass complex integers
7294 in registers up to 8 bytes. More generally, enforce the 2-word
7295 cap for passing arguments in registers.
7297 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7298 integers are passed like floats of the same size, that is in
7299 registers up to 8 bytes. Pass all vector floats by reference
7300 like structure and unions. */
7301 return ((type
&& (AGGREGATE_TYPE_P (type
) || VECTOR_FLOAT_TYPE_P (type
)))
7303 /* Catch CDImode, TFmode, DCmode and TCmode. */
7304 || GET_MODE_SIZE (mode
) > 8
7306 && TREE_CODE (type
) == VECTOR_TYPE
7307 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
7309 /* Original SPARC 64-bit ABI says that structures and unions
7310 smaller than 16 bytes are passed in registers, as well as
7311 all other base types.
7313 Extended ABI (as implemented by the Sun compiler) says that
7314 complex floats are passed in registers up to 16 bytes. Pass
7315 all complex integers in registers up to 16 bytes. More generally,
7316 enforce the 2-word cap for passing arguments in registers.
7318 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7319 integers are passed like floats of the same size, that is in
7320 registers (up to 16 bytes). Pass all vector floats like structure
7323 && (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == VECTOR_TYPE
)
7324 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 16)
7325 /* Catch CTImode and TCmode. */
7326 || GET_MODE_SIZE (mode
) > 16);
7329 /* Handle the TARGET_FUNCTION_ARG_ADVANCE hook.
7330 Update the data in CUM to advance over an argument
7331 of mode MODE and data type TYPE.
7332 TYPE is null for libcalls where that information may not be available. */
7335 sparc_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
7336 const_tree type
, bool named
)
7338 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
7341 /* We pass false for incoming here, it doesn't matter. */
7342 function_arg_slotno (cum
, mode
, type
, named
, false, ®no
, &padding
);
7344 /* If argument requires leading padding, add it. */
7345 cum
->words
+= padding
;
7348 cum
->words
+= (mode
== BLKmode
7349 ? CEIL_NWORDS (int_size_in_bytes (type
))
7350 : CEIL_NWORDS (GET_MODE_SIZE (mode
)));
7353 if (type
&& AGGREGATE_TYPE_P (type
))
7355 int size
= int_size_in_bytes (type
);
7359 else if (size
<= 16)
7361 else /* passed by reference */
7365 cum
->words
+= (mode
== BLKmode
7366 ? CEIL_NWORDS (int_size_in_bytes (type
))
7367 : CEIL_NWORDS (GET_MODE_SIZE (mode
)));
7371 /* Implement TARGET_FUNCTION_ARG_PADDING. For the 64-bit ABI structs
7372 are always stored left shifted in their argument slot. */
7374 static pad_direction
7375 sparc_function_arg_padding (machine_mode mode
, const_tree type
)
7377 if (TARGET_ARCH64
&& type
&& AGGREGATE_TYPE_P (type
))
7380 /* Fall back to the default. */
7381 return default_function_arg_padding (mode
, type
);
7384 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
7385 Specify whether to return the return value in memory. */
7388 sparc_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
7391 /* Original SPARC 32-bit ABI says that structures and unions,
7392 and quad-precision floats are returned in memory. All other
7393 base types are returned in registers.
7395 Extended ABI (as implemented by the Sun compiler) says that
7396 all complex floats are returned in registers (8 FP registers
7397 at most for '_Complex long double'). Return all complex integers
7398 in registers (4 at most for '_Complex long long').
7400 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7401 integers are returned like floats of the same size, that is in
7402 registers up to 8 bytes and in memory otherwise. Return all
7403 vector floats in memory like structure and unions; note that
7404 they always have BLKmode like the latter. */
7405 return (TYPE_MODE (type
) == BLKmode
7406 || TYPE_MODE (type
) == TFmode
7407 || (TREE_CODE (type
) == VECTOR_TYPE
7408 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
7410 /* Original SPARC 64-bit ABI says that structures and unions
7411 smaller than 32 bytes are returned in registers, as well as
7412 all other base types.
7414 Extended ABI (as implemented by the Sun compiler) says that all
7415 complex floats are returned in registers (8 FP registers at most
7416 for '_Complex long double'). Return all complex integers in
7417 registers (4 at most for '_Complex TItype').
7419 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7420 integers are returned like floats of the same size, that is in
7421 registers. Return all vector floats like structure and unions;
7422 note that they always have BLKmode like the latter. */
7423 return (TYPE_MODE (type
) == BLKmode
7424 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 32);
7427 /* Handle the TARGET_STRUCT_VALUE target hook.
7428 Return where to find the structure return value address. */
7431 sparc_struct_value_rtx (tree fndecl
, int incoming
)
7440 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, frame_pointer_rtx
,
7441 STRUCT_VALUE_OFFSET
));
7443 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, stack_pointer_rtx
,
7444 STRUCT_VALUE_OFFSET
));
7446 /* Only follow the SPARC ABI for fixed-size structure returns.
7447 Variable size structure returns are handled per the normal
7448 procedures in GCC. This is enabled by -mstd-struct-return */
7450 && sparc_std_struct_return
7451 && TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))
7452 && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))) == INTEGER_CST
)
7454 /* We must check and adjust the return address, as it is optional
7455 as to whether the return object is really provided. */
7456 rtx ret_reg
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
7457 rtx scratch
= gen_reg_rtx (SImode
);
7458 rtx_code_label
*endlab
= gen_label_rtx ();
7460 /* Calculate the return object size. */
7461 tree size
= TYPE_SIZE_UNIT (TREE_TYPE (fndecl
));
7462 rtx size_rtx
= GEN_INT (TREE_INT_CST_LOW (size
) & 0xfff);
7463 /* Construct a temporary return value. */
7465 = assign_stack_local (Pmode
, TREE_INT_CST_LOW (size
), 0);
7467 /* Implement SPARC 32-bit psABI callee return struct checking:
7469 Fetch the instruction where we will return to and see if
7470 it's an unimp instruction (the most significant 10 bits
7472 emit_move_insn (scratch
, gen_rtx_MEM (SImode
,
7473 plus_constant (Pmode
,
7475 /* Assume the size is valid and pre-adjust. */
7476 emit_insn (gen_add3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
7477 emit_cmp_and_jump_insns (scratch
, size_rtx
, EQ
, const0_rtx
, SImode
,
7479 emit_insn (gen_sub3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
7480 /* Write the address of the memory pointed to by temp_val into
7481 the memory pointed to by mem. */
7482 emit_move_insn (mem
, XEXP (temp_val
, 0));
7483 emit_label (endlab
);
7490 /* Handle TARGET_FUNCTION_VALUE, and TARGET_LIBCALL_VALUE target hook.
7491 For v9, function return values are subject to the same rules as arguments,
7492 except that up to 32 bytes may be returned in registers. */
7495 sparc_function_value_1 (const_tree type
, machine_mode mode
,
7498 /* Beware that the two values are swapped here wrt function_arg. */
7499 int regbase
= (outgoing
7500 ? SPARC_INCOMING_INT_ARG_FIRST
7501 : SPARC_OUTGOING_INT_ARG_FIRST
);
7502 enum mode_class mclass
= GET_MODE_CLASS (mode
);
7505 /* Vector types deserve special treatment because they are polymorphic wrt
7506 their mode, depending upon whether VIS instructions are enabled. */
7507 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
7509 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7510 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
7511 || (TARGET_ARCH64
&& size
<= 32));
7513 if (mode
== BLKmode
)
7514 return function_arg_vector_value (size
, SPARC_FP_ARG_FIRST
);
7516 mclass
= MODE_FLOAT
;
7519 if (TARGET_ARCH64
&& type
)
7521 /* Structures up to 32 bytes in size are returned in registers. */
7522 if (TREE_CODE (type
) == RECORD_TYPE
)
7524 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7525 gcc_assert (size
<= 32);
7527 return function_arg_record_value (type
, mode
, 0, 1, regbase
);
7530 /* Unions up to 32 bytes in size are returned in integer registers. */
7531 else if (TREE_CODE (type
) == UNION_TYPE
)
7533 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7534 gcc_assert (size
<= 32);
7536 return function_arg_union_value (size
, mode
, 0, regbase
);
7539 /* Objects that require it are returned in FP registers. */
7540 else if (mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
7543 /* All other aggregate types are returned in an integer register in a
7544 mode corresponding to the size of the type. */
7545 else if (AGGREGATE_TYPE_P (type
))
7547 /* All other aggregate types are passed in an integer register
7548 in a mode corresponding to the size of the type. */
7549 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7550 gcc_assert (size
<= 32);
7552 mode
= int_mode_for_size (size
* BITS_PER_UNIT
, 0).else_blk ();
7554 /* ??? We probably should have made the same ABI change in
7555 3.4.0 as the one we made for unions. The latter was
7556 required by the SCD though, while the former is not
7557 specified, so we favored compatibility and efficiency.
7559 Now we're stuck for aggregates larger than 16 bytes,
7560 because OImode vanished in the meantime. Let's not
7561 try to be unduly clever, and simply follow the ABI
7562 for unions in that case. */
7563 if (mode
== BLKmode
)
7564 return function_arg_union_value (size
, mode
, 0, regbase
);
7569 /* We should only have pointer and integer types at this point. This
7570 must match sparc_promote_function_mode. */
7571 else if (mclass
== MODE_INT
&& GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
7575 /* We should only have pointer and integer types at this point, except with
7576 -freg-struct-return. This must match sparc_promote_function_mode. */
7577 else if (TARGET_ARCH32
7578 && !(type
&& AGGREGATE_TYPE_P (type
))
7579 && mclass
== MODE_INT
7580 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
7583 if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
) && TARGET_FPU
)
7584 regno
= SPARC_FP_ARG_FIRST
;
7588 return gen_rtx_REG (mode
, regno
);
7591 /* Handle TARGET_FUNCTION_VALUE.
7592 On the SPARC, the value is found in the first "output" register, but the
7593 called function leaves it in the first "input" register. */
7596 sparc_function_value (const_tree valtype
,
7597 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
7600 return sparc_function_value_1 (valtype
, TYPE_MODE (valtype
), outgoing
);
7603 /* Handle TARGET_LIBCALL_VALUE. */
7606 sparc_libcall_value (machine_mode mode
,
7607 const_rtx fun ATTRIBUTE_UNUSED
)
7609 return sparc_function_value_1 (NULL_TREE
, mode
, false);
7612 /* Handle FUNCTION_VALUE_REGNO_P.
7613 On the SPARC, the first "output" reg is used for integer values, and the
7614 first floating point register is used for floating point values. */
7617 sparc_function_value_regno_p (const unsigned int regno
)
7619 return (regno
== 8 || (TARGET_FPU
&& regno
== 32));
7622 /* Do what is necessary for `va_start'. We look at the current function
7623 to determine if stdarg or varargs is used and return the address of
7624 the first unnamed parameter. */
7627 sparc_builtin_saveregs (void)
7629 int first_reg
= crtl
->args
.info
.words
;
7633 for (regno
= first_reg
; regno
< SPARC_INT_ARG_MAX
; regno
++)
7634 emit_move_insn (gen_rtx_MEM (word_mode
,
7635 gen_rtx_PLUS (Pmode
,
7637 GEN_INT (FIRST_PARM_OFFSET (0)
7640 gen_rtx_REG (word_mode
,
7641 SPARC_INCOMING_INT_ARG_FIRST
+ regno
));
7643 address
= gen_rtx_PLUS (Pmode
,
7645 GEN_INT (FIRST_PARM_OFFSET (0)
7646 + UNITS_PER_WORD
* first_reg
));
7651 /* Implement `va_start' for stdarg. */
7654 sparc_va_start (tree valist
, rtx nextarg
)
7656 nextarg
= expand_builtin_saveregs ();
7657 std_expand_builtin_va_start (valist
, nextarg
);
7660 /* Implement `va_arg' for stdarg. */
7663 sparc_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
7666 HOST_WIDE_INT size
, rsize
, align
;
7669 tree ptrtype
= build_pointer_type (type
);
7671 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
7674 size
= rsize
= UNITS_PER_WORD
;
7680 size
= int_size_in_bytes (type
);
7681 rsize
= ROUND_UP (size
, UNITS_PER_WORD
);
7686 /* For SPARC64, objects requiring 16-byte alignment get it. */
7687 if (TYPE_ALIGN (type
) >= 2 * (unsigned) BITS_PER_WORD
)
7688 align
= 2 * UNITS_PER_WORD
;
7690 /* SPARC-V9 ABI states that structures up to 16 bytes in size
7691 are left-justified in their slots. */
7692 if (AGGREGATE_TYPE_P (type
))
7695 size
= rsize
= UNITS_PER_WORD
;
7705 incr
= fold_build_pointer_plus_hwi (incr
, align
- 1);
7706 incr
= fold_convert (sizetype
, incr
);
7707 incr
= fold_build2 (BIT_AND_EXPR
, sizetype
, incr
,
7709 incr
= fold_convert (ptr_type_node
, incr
);
7712 gimplify_expr (&incr
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
7715 if (BYTES_BIG_ENDIAN
&& size
< rsize
)
7716 addr
= fold_build_pointer_plus_hwi (incr
, rsize
- size
);
7720 addr
= fold_convert (build_pointer_type (ptrtype
), addr
);
7721 addr
= build_va_arg_indirect_ref (addr
);
7724 /* If the address isn't aligned properly for the type, we need a temporary.
7725 FIXME: This is inefficient, usually we can do this in registers. */
7726 else if (align
== 0 && TYPE_ALIGN (type
) > BITS_PER_WORD
)
7728 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
7729 tree dest_addr
= build_fold_addr_expr (tmp
);
7730 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
7731 3, dest_addr
, addr
, size_int (rsize
));
7732 TREE_ADDRESSABLE (tmp
) = 1;
7733 gimplify_and_add (copy
, pre_p
);
7738 addr
= fold_convert (ptrtype
, addr
);
7740 incr
= fold_build_pointer_plus_hwi (incr
, rsize
);
7741 gimplify_assign (valist
, incr
, post_p
);
7743 return build_va_arg_indirect_ref (addr
);
7746 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
7747 Specify whether the vector mode is supported by the hardware. */
7750 sparc_vector_mode_supported_p (machine_mode mode
)
7752 return TARGET_VIS
&& VECTOR_MODE_P (mode
) ? true : false;
7755 /* Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook. */
7758 sparc_preferred_simd_mode (scalar_mode mode
)
7776 /* Return the string to output an unconditional branch to LABEL, which is
7777 the operand number of the label.
7779 DEST is the destination insn (i.e. the label), INSN is the source. */
7782 output_ubranch (rtx dest
, rtx_insn
*insn
)
7784 static char string
[64];
7785 bool v9_form
= false;
7789 /* Even if we are trying to use cbcond for this, evaluate
7790 whether we can use V9 branches as our backup plan. */
7793 if (INSN_ADDRESSES_SET_P ())
7794 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
7795 - INSN_ADDRESSES (INSN_UID (insn
)));
7797 /* Leave some instructions for "slop". */
7798 if (TARGET_V9
&& delta
>= -260000 && delta
< 260000)
7803 bool emit_nop
= emit_cbcond_nop (insn
);
7807 if (delta
< -500 || delta
> 500)
7813 rval
= "ba,a,pt\t%%xcc, %l0";
7820 rval
= "cwbe\t%%g0, %%g0, %l0\n\tnop";
7822 rval
= "cwbe\t%%g0, %%g0, %l0";
7828 strcpy (string
, "ba%*,pt\t%%xcc, ");
7830 strcpy (string
, "b%*\t");
7832 p
= strchr (string
, '\0');
7843 /* Return the string to output a conditional branch to LABEL, which is
7844 the operand number of the label. OP is the conditional expression.
7845 XEXP (OP, 0) is assumed to be a condition code register (integer or
7846 floating point) and its mode specifies what kind of comparison we made.
7848 DEST is the destination insn (i.e. the label), INSN is the source.
7850 REVERSED is nonzero if we should reverse the sense of the comparison.
7852 ANNUL is nonzero if we should generate an annulling branch. */
7855 output_cbranch (rtx op
, rtx dest
, int label
, int reversed
, int annul
,
7858 static char string
[64];
7859 enum rtx_code code
= GET_CODE (op
);
7860 rtx cc_reg
= XEXP (op
, 0);
7861 machine_mode mode
= GET_MODE (cc_reg
);
7862 const char *labelno
, *branch
;
7863 int spaces
= 8, far
;
7866 /* v9 branches are limited to +-1MB. If it is too far away,
7879 fbne,a,pn %fcc2, .LC29
7887 far
= TARGET_V9
&& (get_attr_length (insn
) >= 3);
7890 /* Reversal of FP compares takes care -- an ordered compare
7891 becomes an unordered compare and vice versa. */
7892 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7893 code
= reverse_condition_maybe_unordered (code
);
7895 code
= reverse_condition (code
);
7898 /* Start by writing the branch condition. */
7899 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7949 /* ??? !v9: FP branches cannot be preceded by another floating point
7950 insn. Because there is currently no concept of pre-delay slots,
7951 we can fix this only by always emitting a nop before a floating
7956 strcpy (string
, "nop\n\t");
7957 strcat (string
, branch
);
7964 if (mode
== CCVmode
|| mode
== CCXVmode
)
7970 if (mode
== CCVmode
|| mode
== CCXVmode
)
7976 if (mode
== CCNZmode
|| mode
== CCXNZmode
)
7988 if (mode
== CCNZmode
|| mode
== CCXNZmode
)
8008 strcpy (string
, branch
);
8010 spaces
-= strlen (branch
);
8011 p
= strchr (string
, '\0');
8013 /* Now add the annulling, the label, and a possible noop. */
8026 if (! far
&& insn
&& INSN_ADDRESSES_SET_P ())
8028 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
8029 - INSN_ADDRESSES (INSN_UID (insn
)));
8030 /* Leave some instructions for "slop". */
8031 if (delta
< -260000 || delta
>= 260000)
8041 labelno
= "%%icc, ";
8049 labelno
= "%%xcc, ";
8055 static char v9_fcc_labelno
[] = "%%fccX, ";
8056 /* Set the char indicating the number of the fcc reg to use. */
8057 v9_fcc_labelno
[5] = REGNO (cc_reg
) - SPARC_FIRST_V9_FCC_REG
+ '0';
8058 labelno
= v9_fcc_labelno
;
8061 gcc_assert (REGNO (cc_reg
) == SPARC_FCC_REG
);
8070 if (*labelno
&& insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
8073 ((profile_probability::from_reg_br_prob_note (XINT (note
, 0))
8074 >= profile_probability::even ()) ^ far
)
8087 strcpy (p
, labelno
);
8088 p
= strchr (p
, '\0');
8091 strcpy (p
, ".+12\n\t nop\n\tb\t");
8092 /* Skip the next insn if requested or
8093 if we know that it will be a nop. */
8094 if (annul
|| ! final_sequence
)
8108 /* Emit a library call comparison between floating point X and Y.
8109 COMPARISON is the operator to compare with (EQ, NE, GT, etc).
8110 Return the new operator to be used in the comparison sequence.
8112 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
8113 values as arguments instead of the TFmode registers themselves,
8114 that's why we cannot call emit_float_lib_cmp. */
8117 sparc_emit_float_lib_cmp (rtx x
, rtx y
, enum rtx_code comparison
)
8120 rtx slot0
, slot1
, result
, tem
, tem2
, libfunc
;
8122 enum rtx_code new_comparison
;
8127 qpfunc
= (TARGET_ARCH64
? "_Qp_feq" : "_Q_feq");
8131 qpfunc
= (TARGET_ARCH64
? "_Qp_fne" : "_Q_fne");
8135 qpfunc
= (TARGET_ARCH64
? "_Qp_fgt" : "_Q_fgt");
8139 qpfunc
= (TARGET_ARCH64
? "_Qp_fge" : "_Q_fge");
8143 qpfunc
= (TARGET_ARCH64
? "_Qp_flt" : "_Q_flt");
8147 qpfunc
= (TARGET_ARCH64
? "_Qp_fle" : "_Q_fle");
8158 qpfunc
= (TARGET_ARCH64
? "_Qp_cmp" : "_Q_cmp");
8169 tree expr
= MEM_EXPR (x
);
8171 mark_addressable (expr
);
8176 slot0
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
));
8177 emit_move_insn (slot0
, x
);
8182 tree expr
= MEM_EXPR (y
);
8184 mark_addressable (expr
);
8189 slot1
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
));
8190 emit_move_insn (slot1
, y
);
8193 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
8194 emit_library_call (libfunc
, LCT_NORMAL
,
8196 XEXP (slot0
, 0), Pmode
,
8197 XEXP (slot1
, 0), Pmode
);
8202 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
8203 emit_library_call (libfunc
, LCT_NORMAL
,
8205 x
, TFmode
, y
, TFmode
);
8210 /* Immediately move the result of the libcall into a pseudo
8211 register so reload doesn't clobber the value if it needs
8212 the return register for a spill reg. */
8213 result
= gen_reg_rtx (mode
);
8214 emit_move_insn (result
, hard_libcall_value (mode
, libfunc
));
8219 return gen_rtx_NE (VOIDmode
, result
, const0_rtx
);
8222 new_comparison
= (comparison
== UNORDERED
? EQ
: NE
);
8223 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, GEN_INT(3));
8226 new_comparison
= (comparison
== UNGT
? GT
: NE
);
8227 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, const1_rtx
);
8229 return gen_rtx_NE (VOIDmode
, result
, const2_rtx
);
8231 tem
= gen_reg_rtx (mode
);
8233 emit_insn (gen_andsi3 (tem
, result
, const1_rtx
));
8235 emit_insn (gen_anddi3 (tem
, result
, const1_rtx
));
8236 return gen_rtx_NE (VOIDmode
, tem
, const0_rtx
);
8239 tem
= gen_reg_rtx (mode
);
8241 emit_insn (gen_addsi3 (tem
, result
, const1_rtx
));
8243 emit_insn (gen_adddi3 (tem
, result
, const1_rtx
));
8244 tem2
= gen_reg_rtx (mode
);
8246 emit_insn (gen_andsi3 (tem2
, tem
, const2_rtx
));
8248 emit_insn (gen_anddi3 (tem2
, tem
, const2_rtx
));
8249 new_comparison
= (comparison
== UNEQ
? EQ
: NE
);
8250 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, tem2
, const0_rtx
);
8256 /* Generate an unsigned DImode to FP conversion. This is the same code
8257 optabs would emit if we didn't have TFmode patterns. */
8260 sparc_emit_floatunsdi (rtx
*operands
, machine_mode mode
)
8262 rtx i0
, i1
, f0
, in
, out
;
8265 in
= force_reg (DImode
, operands
[1]);
8266 rtx_code_label
*neglab
= gen_label_rtx ();
8267 rtx_code_label
*donelab
= gen_label_rtx ();
8268 i0
= gen_reg_rtx (DImode
);
8269 i1
= gen_reg_rtx (DImode
);
8270 f0
= gen_reg_rtx (mode
);
8272 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
8274 emit_insn (gen_rtx_SET (out
, gen_rtx_FLOAT (mode
, in
)));
8275 emit_jump_insn (gen_jump (donelab
));
8278 emit_label (neglab
);
8280 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
8281 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
8282 emit_insn (gen_iordi3 (i0
, i0
, i1
));
8283 emit_insn (gen_rtx_SET (f0
, gen_rtx_FLOAT (mode
, i0
)));
8284 emit_insn (gen_rtx_SET (out
, gen_rtx_PLUS (mode
, f0
, f0
)));
8286 emit_label (donelab
);
8289 /* Generate an FP to unsigned DImode conversion. This is the same code
8290 optabs would emit if we didn't have TFmode patterns. */
8293 sparc_emit_fixunsdi (rtx
*operands
, machine_mode mode
)
8295 rtx i0
, i1
, f0
, in
, out
, limit
;
8298 in
= force_reg (mode
, operands
[1]);
8299 rtx_code_label
*neglab
= gen_label_rtx ();
8300 rtx_code_label
*donelab
= gen_label_rtx ();
8301 i0
= gen_reg_rtx (DImode
);
8302 i1
= gen_reg_rtx (DImode
);
8303 limit
= gen_reg_rtx (mode
);
8304 f0
= gen_reg_rtx (mode
);
8306 emit_move_insn (limit
,
8307 const_double_from_real_value (
8308 REAL_VALUE_ATOF ("9223372036854775808.0", mode
), mode
));
8309 emit_cmp_and_jump_insns (in
, limit
, GE
, NULL_RTX
, mode
, 0, neglab
);
8311 emit_insn (gen_rtx_SET (out
,
8312 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, in
))));
8313 emit_jump_insn (gen_jump (donelab
));
8316 emit_label (neglab
);
8318 emit_insn (gen_rtx_SET (f0
, gen_rtx_MINUS (mode
, in
, limit
)));
8319 emit_insn (gen_rtx_SET (i0
,
8320 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, f0
))));
8321 emit_insn (gen_movdi (i1
, const1_rtx
));
8322 emit_insn (gen_ashldi3 (i1
, i1
, GEN_INT (63)));
8323 emit_insn (gen_xordi3 (out
, i0
, i1
));
8325 emit_label (donelab
);
8328 /* Return the string to output a compare and branch instruction to DEST.
8329 DEST is the destination insn (i.e. the label), INSN is the source,
8330 and OP is the conditional expression. */
8333 output_cbcond (rtx op
, rtx dest
, rtx_insn
*insn
)
8335 machine_mode mode
= GET_MODE (XEXP (op
, 0));
8336 enum rtx_code code
= GET_CODE (op
);
8337 const char *cond_str
, *tmpl
;
8338 int far
, emit_nop
, len
;
8339 static char string
[64];
8342 /* Compare and Branch is limited to +-2KB. If it is too far away,
8354 len
= get_attr_length (insn
);
8357 emit_nop
= len
== 2;
8360 code
= reverse_condition (code
);
8362 size_char
= ((mode
== SImode
) ? 'w' : 'x');
8412 int veryfar
= 1, delta
;
8414 if (INSN_ADDRESSES_SET_P ())
8416 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
8417 - INSN_ADDRESSES (INSN_UID (insn
)));
8418 /* Leave some instructions for "slop". */
8419 if (delta
>= -260000 && delta
< 260000)
8424 tmpl
= "c%cb%s\t%%1, %%2, .+16\n\tnop\n\tb\t%%3\n\tnop";
8426 tmpl
= "c%cb%s\t%%1, %%2, .+16\n\tnop\n\tba,pt\t%%%%xcc, %%3\n\tnop";
8431 tmpl
= "c%cb%s\t%%1, %%2, %%3\n\tnop";
8433 tmpl
= "c%cb%s\t%%1, %%2, %%3";
8436 snprintf (string
, sizeof(string
), tmpl
, size_char
, cond_str
);
8441 /* Return the string to output a conditional branch to LABEL, testing
8442 register REG. LABEL is the operand number of the label; REG is the
8443 operand number of the reg. OP is the conditional expression. The mode
8444 of REG says what kind of comparison we made.
8446 DEST is the destination insn (i.e. the label), INSN is the source.
8448 REVERSED is nonzero if we should reverse the sense of the comparison.
8450 ANNUL is nonzero if we should generate an annulling branch. */
8453 output_v9branch (rtx op
, rtx dest
, int reg
, int label
, int reversed
,
8454 int annul
, rtx_insn
*insn
)
8456 static char string
[64];
8457 enum rtx_code code
= GET_CODE (op
);
8458 machine_mode mode
= GET_MODE (XEXP (op
, 0));
8463 /* branch on register are limited to +-128KB. If it is too far away,
8476 brgez,a,pn %o1, .LC29
8482 ba,pt %xcc, .LC29 */
8484 far
= get_attr_length (insn
) >= 3;
8486 /* If not floating-point or if EQ or NE, we can just reverse the code. */
8488 code
= reverse_condition (code
);
8490 /* Only 64-bit versions of these instructions exist. */
8491 gcc_assert (mode
== DImode
);
8493 /* Start by writing the branch condition. */
8498 strcpy (string
, "brnz");
8502 strcpy (string
, "brz");
8506 strcpy (string
, "brgez");
8510 strcpy (string
, "brlz");
8514 strcpy (string
, "brlez");
8518 strcpy (string
, "brgz");
8525 p
= strchr (string
, '\0');
8527 /* Now add the annulling, reg, label, and nop. */
8534 if (insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
8537 ((profile_probability::from_reg_br_prob_note (XINT (note
, 0))
8538 >= profile_probability::even ()) ^ far
)
8543 *p
= p
< string
+ 8 ? '\t' : ' ';
8551 int veryfar
= 1, delta
;
8553 if (INSN_ADDRESSES_SET_P ())
8555 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
8556 - INSN_ADDRESSES (INSN_UID (insn
)));
8557 /* Leave some instructions for "slop". */
8558 if (delta
>= -260000 && delta
< 260000)
8562 strcpy (p
, ".+12\n\t nop\n\t");
8563 /* Skip the next insn if requested or
8564 if we know that it will be a nop. */
8565 if (annul
|| ! final_sequence
)
8575 strcpy (p
, "ba,pt\t%%xcc, ");
8589 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
8590 Such instructions cannot be used in the delay slot of return insn on v9.
8591 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
8595 epilogue_renumber (register rtx
*where
, int test
)
8597 register const char *fmt
;
8599 register enum rtx_code code
;
8604 code
= GET_CODE (*where
);
8609 if (REGNO (*where
) >= 8 && REGNO (*where
) < 24) /* oX or lX */
8611 if (! test
&& REGNO (*where
) >= 24 && REGNO (*where
) < 32)
8612 *where
= gen_rtx_REG (GET_MODE (*where
), OUTGOING_REGNO (REGNO(*where
)));
8618 case CONST_WIDE_INT
:
8622 /* Do not replace the frame pointer with the stack pointer because
8623 it can cause the delayed instruction to load below the stack.
8624 This occurs when instructions like:
8626 (set (reg/i:SI 24 %i0)
8627 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
8628 (const_int -20 [0xffffffec])) 0))
8630 are in the return delayed slot. */
8632 if (GET_CODE (XEXP (*where
, 0)) == REG
8633 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
8634 && (GET_CODE (XEXP (*where
, 1)) != CONST_INT
8635 || INTVAL (XEXP (*where
, 1)) < SPARC_STACK_BIAS
))
8640 if (SPARC_STACK_BIAS
8641 && GET_CODE (XEXP (*where
, 0)) == REG
8642 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
)
8650 fmt
= GET_RTX_FORMAT (code
);
8652 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8657 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
8658 if (epilogue_renumber (&(XVECEXP (*where
, i
, j
)), test
))
8661 else if (fmt
[i
] == 'e'
8662 && epilogue_renumber (&(XEXP (*where
, i
)), test
))
8668 /* Leaf functions and non-leaf functions have different needs. */
8671 reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
8674 reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
8676 static const int *const reg_alloc_orders
[] = {
8677 reg_leaf_alloc_order
,
8678 reg_nonleaf_alloc_order
};
8681 order_regs_for_local_alloc (void)
8683 static int last_order_nonleaf
= 1;
8685 if (df_regs_ever_live_p (15) != last_order_nonleaf
)
8687 last_order_nonleaf
= !last_order_nonleaf
;
8688 memcpy ((char *) reg_alloc_order
,
8689 (const char *) reg_alloc_orders
[last_order_nonleaf
],
8690 FIRST_PSEUDO_REGISTER
* sizeof (int));
8694 /* Return 1 if REG and MEM are legitimate enough to allow the various
8695 MEM<-->REG splits to be run. */
8698 sparc_split_reg_mem_legitimate (rtx reg
, rtx mem
)
8700 /* Punt if we are here by mistake. */
8701 gcc_assert (reload_completed
);
8703 /* We must have an offsettable memory reference. */
8704 if (!offsettable_memref_p (mem
))
8707 /* If we have legitimate args for ldd/std, we do not want
8708 the split to happen. */
8709 if ((REGNO (reg
) % 2) == 0 && mem_min_alignment (mem
, 8))
8716 /* Split a REG <-- MEM move into a pair of moves in MODE. */
8719 sparc_split_reg_mem (rtx dest
, rtx src
, machine_mode mode
)
8721 rtx high_part
= gen_highpart (mode
, dest
);
8722 rtx low_part
= gen_lowpart (mode
, dest
);
8723 rtx word0
= adjust_address (src
, mode
, 0);
8724 rtx word1
= adjust_address (src
, mode
, 4);
8726 if (reg_overlap_mentioned_p (high_part
, word1
))
8728 emit_move_insn_1 (low_part
, word1
);
8729 emit_move_insn_1 (high_part
, word0
);
8733 emit_move_insn_1 (high_part
, word0
);
8734 emit_move_insn_1 (low_part
, word1
);
8738 /* Split a MEM <-- REG move into a pair of moves in MODE. */
8741 sparc_split_mem_reg (rtx dest
, rtx src
, machine_mode mode
)
8743 rtx word0
= adjust_address (dest
, mode
, 0);
8744 rtx word1
= adjust_address (dest
, mode
, 4);
8745 rtx high_part
= gen_highpart (mode
, src
);
8746 rtx low_part
= gen_lowpart (mode
, src
);
8748 emit_move_insn_1 (word0
, high_part
);
8749 emit_move_insn_1 (word1
, low_part
);
8752 /* Like sparc_split_reg_mem_legitimate but for REG <--> REG moves. */
8755 sparc_split_reg_reg_legitimate (rtx reg1
, rtx reg2
)
8757 /* Punt if we are here by mistake. */
8758 gcc_assert (reload_completed
);
8760 if (GET_CODE (reg1
) == SUBREG
)
8761 reg1
= SUBREG_REG (reg1
);
8762 if (GET_CODE (reg1
) != REG
)
8764 const int regno1
= REGNO (reg1
);
8766 if (GET_CODE (reg2
) == SUBREG
)
8767 reg2
= SUBREG_REG (reg2
);
8768 if (GET_CODE (reg2
) != REG
)
8770 const int regno2
= REGNO (reg2
);
8772 if (SPARC_INT_REG_P (regno1
) && SPARC_INT_REG_P (regno2
))
8777 if ((SPARC_INT_REG_P (regno1
) && SPARC_FP_REG_P (regno2
))
8778 || (SPARC_FP_REG_P (regno1
) && SPARC_INT_REG_P (regno2
)))
8785 /* Split a REG <--> REG move into a pair of moves in MODE. */
8788 sparc_split_reg_reg (rtx dest
, rtx src
, machine_mode mode
)
8790 rtx dest1
= gen_highpart (mode
, dest
);
8791 rtx dest2
= gen_lowpart (mode
, dest
);
8792 rtx src1
= gen_highpart (mode
, src
);
8793 rtx src2
= gen_lowpart (mode
, src
);
8795 /* Now emit using the real source and destination we found, swapping
8796 the order if we detect overlap. */
8797 if (reg_overlap_mentioned_p (dest1
, src2
))
8799 emit_move_insn_1 (dest2
, src2
);
8800 emit_move_insn_1 (dest1
, src1
);
8804 emit_move_insn_1 (dest1
, src1
);
8805 emit_move_insn_1 (dest2
, src2
);
8809 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
8810 This makes them candidates for using ldd and std insns.
8812 Note reg1 and reg2 *must* be hard registers. */
8815 registers_ok_for_ldd_peep (rtx reg1
, rtx reg2
)
8817 /* We might have been passed a SUBREG. */
8818 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
8821 if (REGNO (reg1
) % 2 != 0)
8824 /* Integer ldd is deprecated in SPARC V9 */
8825 if (TARGET_V9
&& SPARC_INT_REG_P (REGNO (reg1
)))
8828 return (REGNO (reg1
) == REGNO (reg2
) - 1);
8831 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
8834 This can only happen when addr1 and addr2, the addresses in mem1
8835 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
8836 addr1 must also be aligned on a 64-bit boundary.
8838 Also iff dependent_reg_rtx is not null it should not be used to
8839 compute the address for mem1, i.e. we cannot optimize a sequence
8851 But, note that the transformation from:
8856 is perfectly fine. Thus, the peephole2 patterns always pass us
8857 the destination register of the first load, never the second one.
8859 For stores we don't have a similar problem, so dependent_reg_rtx is
8863 mems_ok_for_ldd_peep (rtx mem1
, rtx mem2
, rtx dependent_reg_rtx
)
8867 HOST_WIDE_INT offset1
;
8869 /* The mems cannot be volatile. */
8870 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
8873 /* MEM1 should be aligned on a 64-bit boundary. */
8874 if (MEM_ALIGN (mem1
) < 64)
8877 addr1
= XEXP (mem1
, 0);
8878 addr2
= XEXP (mem2
, 0);
8880 /* Extract a register number and offset (if used) from the first addr. */
8881 if (GET_CODE (addr1
) == PLUS
)
8883 /* If not a REG, return zero. */
8884 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
8888 reg1
= REGNO (XEXP (addr1
, 0));
8889 /* The offset must be constant! */
8890 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
8892 offset1
= INTVAL (XEXP (addr1
, 1));
8895 else if (GET_CODE (addr1
) != REG
)
8899 reg1
= REGNO (addr1
);
8900 /* This was a simple (mem (reg)) expression. Offset is 0. */
8904 /* Make sure the second address is a (mem (plus (reg) (const_int). */
8905 if (GET_CODE (addr2
) != PLUS
)
8908 if (GET_CODE (XEXP (addr2
, 0)) != REG
8909 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
8912 if (reg1
!= REGNO (XEXP (addr2
, 0)))
8915 if (dependent_reg_rtx
!= NULL_RTX
&& reg1
== REGNO (dependent_reg_rtx
))
8918 /* The first offset must be evenly divisible by 8 to ensure the
8919 address is 64-bit aligned. */
8920 if (offset1
% 8 != 0)
8923 /* The offset for the second addr must be 4 more than the first addr. */
8924 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
8927 /* All the tests passed. addr1 and addr2 are valid for ldd and std
8932 /* Return the widened memory access made of MEM1 and MEM2 in MODE. */
8935 widen_mem_for_ldd_peep (rtx mem1
, rtx mem2
, machine_mode mode
)
8937 rtx x
= widen_memory_access (mem1
, mode
, 0);
8938 MEM_NOTRAP_P (x
) = MEM_NOTRAP_P (mem1
) && MEM_NOTRAP_P (mem2
);
8942 /* Return 1 if reg is a pseudo, or is the first register in
8943 a hard register pair. This makes it suitable for use in
8944 ldd and std insns. */
8947 register_ok_for_ldd (rtx reg
)
8949 /* We might have been passed a SUBREG. */
8953 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
8954 return (REGNO (reg
) % 2 == 0);
8959 /* Return 1 if OP, a MEM, has an address which is known to be
8960 aligned to an 8-byte boundary. */
8963 memory_ok_for_ldd (rtx op
)
8965 /* In 64-bit mode, we assume that the address is word-aligned. */
8966 if (TARGET_ARCH32
&& !mem_min_alignment (op
, 8))
8969 if (! can_create_pseudo_p ()
8970 && !strict_memory_address_p (Pmode
, XEXP (op
, 0)))
8976 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8979 sparc_print_operand_punct_valid_p (unsigned char code
)
8992 /* Implement TARGET_PRINT_OPERAND.
8993 Print operand X (an rtx) in assembler syntax to file FILE.
8994 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
8995 For `%' followed by punctuation, CODE is the punctuation and X is null. */
8998 sparc_print_operand (FILE *file
, rtx x
, int code
)
9005 /* Output an insn in a delay slot. */
9007 sparc_indent_opcode
= 1;
9009 fputs ("\n\t nop", file
);
9012 /* Output an annul flag if there's nothing for the delay slot and we
9013 are optimizing. This is always used with '(' below.
9014 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
9015 this is a dbx bug. So, we only do this when optimizing.
9016 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
9017 Always emit a nop in case the next instruction is a branch. */
9018 if (! final_sequence
&& (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
9022 /* Output a 'nop' if there's nothing for the delay slot and we are
9023 not optimizing. This is always used with '*' above. */
9024 if (! final_sequence
&& ! (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
9025 fputs ("\n\t nop", file
);
9026 else if (final_sequence
)
9027 sparc_indent_opcode
= 1;
9030 /* Output the right displacement from the saved PC on function return.
9031 The caller may have placed an "unimp" insn immediately after the call
9032 so we have to account for it. This insn is used in the 32-bit ABI
9033 when calling a function that returns a non zero-sized structure. The
9034 64-bit ABI doesn't have it. Be careful to have this test be the same
9035 as that for the call. The exception is when sparc_std_struct_return
9036 is enabled, the psABI is followed exactly and the adjustment is made
9037 by the code in sparc_struct_value_rtx. The call emitted is the same
9038 when sparc_std_struct_return is enabled. */
9040 && cfun
->returns_struct
9041 && !sparc_std_struct_return
9042 && DECL_SIZE (DECL_RESULT (current_function_decl
))
9043 && TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl
)))
9045 && !integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl
))))
9051 /* Output the Embedded Medium/Anywhere code model base register. */
9052 fputs (EMBMEDANY_BASE_REG
, file
);
9055 /* Print some local dynamic TLS name. */
9056 if (const char *name
= get_some_local_dynamic_name ())
9057 assemble_name (file
, name
);
9059 output_operand_lossage ("'%%&' used without any "
9060 "local dynamic TLS references");
9064 /* Adjust the operand to take into account a RESTORE operation. */
9065 if (GET_CODE (x
) == CONST_INT
)
9067 else if (GET_CODE (x
) != REG
)
9068 output_operand_lossage ("invalid %%Y operand");
9069 else if (REGNO (x
) < 8)
9070 fputs (reg_names
[REGNO (x
)], file
);
9071 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
9072 fputs (reg_names
[REGNO (x
)-16], file
);
9074 output_operand_lossage ("invalid %%Y operand");
9077 /* Print out the low order register name of a register pair. */
9078 if (WORDS_BIG_ENDIAN
)
9079 fputs (reg_names
[REGNO (x
)+1], file
);
9081 fputs (reg_names
[REGNO (x
)], file
);
9084 /* Print out the high order register name of a register pair. */
9085 if (WORDS_BIG_ENDIAN
)
9086 fputs (reg_names
[REGNO (x
)], file
);
9088 fputs (reg_names
[REGNO (x
)+1], file
);
9091 /* Print out the second register name of a register pair or quad.
9092 I.e., R (%o0) => %o1. */
9093 fputs (reg_names
[REGNO (x
)+1], file
);
9096 /* Print out the third register name of a register quad.
9097 I.e., S (%o0) => %o2. */
9098 fputs (reg_names
[REGNO (x
)+2], file
);
9101 /* Print out the fourth register name of a register quad.
9102 I.e., T (%o0) => %o3. */
9103 fputs (reg_names
[REGNO (x
)+3], file
);
9106 /* Print a condition code register. */
9107 if (REGNO (x
) == SPARC_ICC_REG
)
9109 switch (GET_MODE (x
))
9129 /* %fccN register */
9130 fputs (reg_names
[REGNO (x
)], file
);
9133 /* Print the operand's address only. */
9134 output_address (GET_MODE (x
), XEXP (x
, 0));
9137 /* In this case we need a register. Use %g0 if the
9138 operand is const0_rtx. */
9140 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
9142 fputs ("%g0", file
);
9149 switch (GET_CODE (x
))
9161 output_operand_lossage ("invalid %%A operand");
9169 switch (GET_CODE (x
))
9181 output_operand_lossage ("invalid %%B operand");
9188 /* This is used by the conditional move instructions. */
9191 machine_mode mode
= GET_MODE (XEXP (x
, 0));
9192 switch (GET_CODE (x
))
9195 if (mode
== CCVmode
|| mode
== CCXVmode
)
9201 if (mode
== CCVmode
|| mode
== CCXVmode
)
9207 if (mode
== CCNZmode
|| mode
== CCXNZmode
)
9219 if (mode
== CCNZmode
|| mode
== CCXNZmode
)
9261 output_operand_lossage ("invalid %%C operand");
9269 /* This are used by the movr instruction pattern. */
9272 switch (GET_CODE (x
))
9293 output_operand_lossage ("invalid %%D operand");
9303 /* Print a sign-extended character. */
9304 int i
= trunc_int_for_mode (INTVAL (x
), QImode
);
9305 fprintf (file
, "%d", i
);
9310 /* Operand must be a MEM; write its address. */
9311 if (GET_CODE (x
) != MEM
)
9312 output_operand_lossage ("invalid %%f operand");
9313 output_address (GET_MODE (x
), XEXP (x
, 0));
9318 /* Print a sign-extended 32-bit value. */
9320 if (GET_CODE(x
) == CONST_INT
)
9324 output_operand_lossage ("invalid %%s operand");
9327 i
= trunc_int_for_mode (i
, SImode
);
9328 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, i
);
9333 /* Do nothing special. */
9337 /* Undocumented flag. */
9338 output_operand_lossage ("invalid operand output code");
9341 if (GET_CODE (x
) == REG
)
9342 fputs (reg_names
[REGNO (x
)], file
);
9343 else if (GET_CODE (x
) == MEM
)
9346 /* Poor Sun assembler doesn't understand absolute addressing. */
9347 if (CONSTANT_P (XEXP (x
, 0)))
9348 fputs ("%g0+", file
);
9349 output_address (GET_MODE (x
), XEXP (x
, 0));
9352 else if (GET_CODE (x
) == HIGH
)
9354 fputs ("%hi(", file
);
9355 output_addr_const (file
, XEXP (x
, 0));
9358 else if (GET_CODE (x
) == LO_SUM
)
9360 sparc_print_operand (file
, XEXP (x
, 0), 0);
9361 if (TARGET_CM_MEDMID
)
9362 fputs ("+%l44(", file
);
9364 fputs ("+%lo(", file
);
9365 output_addr_const (file
, XEXP (x
, 1));
9368 else if (GET_CODE (x
) == CONST_DOUBLE
)
9369 output_operand_lossage ("floating-point constant not a valid immediate operand");
9371 output_addr_const (file
, x
);
9374 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
9377 sparc_print_operand_address (FILE *file
, machine_mode
/*mode*/, rtx x
)
9379 register rtx base
, index
= 0;
9381 register rtx addr
= x
;
9384 fputs (reg_names
[REGNO (addr
)], file
);
9385 else if (GET_CODE (addr
) == PLUS
)
9387 if (CONST_INT_P (XEXP (addr
, 0)))
9388 offset
= INTVAL (XEXP (addr
, 0)), base
= XEXP (addr
, 1);
9389 else if (CONST_INT_P (XEXP (addr
, 1)))
9390 offset
= INTVAL (XEXP (addr
, 1)), base
= XEXP (addr
, 0);
9392 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
9393 if (GET_CODE (base
) == LO_SUM
)
9395 gcc_assert (USE_AS_OFFSETABLE_LO10
9397 && ! TARGET_CM_MEDMID
);
9398 output_operand (XEXP (base
, 0), 0);
9399 fputs ("+%lo(", file
);
9400 output_address (VOIDmode
, XEXP (base
, 1));
9401 fprintf (file
, ")+%d", offset
);
9405 fputs (reg_names
[REGNO (base
)], file
);
9407 fprintf (file
, "%+d", offset
);
9408 else if (REG_P (index
))
9409 fprintf (file
, "+%s", reg_names
[REGNO (index
)]);
9410 else if (GET_CODE (index
) == SYMBOL_REF
9411 || GET_CODE (index
) == LABEL_REF
9412 || GET_CODE (index
) == CONST
)
9413 fputc ('+', file
), output_addr_const (file
, index
);
9414 else gcc_unreachable ();
9417 else if (GET_CODE (addr
) == MINUS
9418 && GET_CODE (XEXP (addr
, 1)) == LABEL_REF
)
9420 output_addr_const (file
, XEXP (addr
, 0));
9422 output_addr_const (file
, XEXP (addr
, 1));
9423 fputs ("-.)", file
);
9425 else if (GET_CODE (addr
) == LO_SUM
)
9427 output_operand (XEXP (addr
, 0), 0);
9428 if (TARGET_CM_MEDMID
)
9429 fputs ("+%l44(", file
);
9431 fputs ("+%lo(", file
);
9432 output_address (VOIDmode
, XEXP (addr
, 1));
9436 && GET_CODE (addr
) == CONST
9437 && GET_CODE (XEXP (addr
, 0)) == MINUS
9438 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST
9439 && GET_CODE (XEXP (XEXP (XEXP (addr
, 0), 1), 0)) == MINUS
9440 && XEXP (XEXP (XEXP (XEXP (addr
, 0), 1), 0), 1) == pc_rtx
)
9442 addr
= XEXP (addr
, 0);
9443 output_addr_const (file
, XEXP (addr
, 0));
9444 /* Group the args of the second CONST in parenthesis. */
9446 /* Skip past the second CONST--it does nothing for us. */
9447 output_addr_const (file
, XEXP (XEXP (addr
, 1), 0));
9448 /* Close the parenthesis. */
9453 output_addr_const (file
, addr
);
9457 /* Target hook for assembling integer objects. The sparc version has
9458 special handling for aligned DI-mode objects. */
9461 sparc_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
9463 /* ??? We only output .xword's for symbols and only then in environments
9464 where the assembler can handle them. */
9465 if (aligned_p
&& size
== 8 && GET_CODE (x
) != CONST_INT
)
9469 assemble_integer_with_op ("\t.xword\t", x
);
9474 assemble_aligned_integer (4, const0_rtx
);
9475 assemble_aligned_integer (4, x
);
9479 return default_assemble_integer (x
, size
, aligned_p
);
9482 /* Return the value of a code used in the .proc pseudo-op that says
9483 what kind of result this function returns. For non-C types, we pick
9484 the closest C type. */
9486 #ifndef SHORT_TYPE_SIZE
9487 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
9490 #ifndef INT_TYPE_SIZE
9491 #define INT_TYPE_SIZE BITS_PER_WORD
9494 #ifndef LONG_TYPE_SIZE
9495 #define LONG_TYPE_SIZE BITS_PER_WORD
9498 #ifndef LONG_LONG_TYPE_SIZE
9499 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
9502 #ifndef FLOAT_TYPE_SIZE
9503 #define FLOAT_TYPE_SIZE BITS_PER_WORD
9506 #ifndef DOUBLE_TYPE_SIZE
9507 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
9510 #ifndef LONG_DOUBLE_TYPE_SIZE
9511 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
9515 sparc_type_code (register tree type
)
9517 register unsigned long qualifiers
= 0;
9518 register unsigned shift
;
9520 /* Only the first 30 bits of the qualifier are valid. We must refrain from
9521 setting more, since some assemblers will give an error for this. Also,
9522 we must be careful to avoid shifts of 32 bits or more to avoid getting
9523 unpredictable results. */
9525 for (shift
= 6; shift
< 30; shift
+= 2, type
= TREE_TYPE (type
))
9527 switch (TREE_CODE (type
))
9533 qualifiers
|= (3 << shift
);
9538 qualifiers
|= (2 << shift
);
9542 case REFERENCE_TYPE
:
9544 qualifiers
|= (1 << shift
);
9548 return (qualifiers
| 8);
9551 case QUAL_UNION_TYPE
:
9552 return (qualifiers
| 9);
9555 return (qualifiers
| 10);
9558 return (qualifiers
| 16);
9561 /* If this is a range type, consider it to be the underlying
9563 if (TREE_TYPE (type
) != 0)
9566 /* Carefully distinguish all the standard types of C,
9567 without messing up if the language is not C. We do this by
9568 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
9569 look at both the names and the above fields, but that's redundant.
9570 Any type whose size is between two C types will be considered
9571 to be the wider of the two types. Also, we do not have a
9572 special code to use for "long long", so anything wider than
9573 long is treated the same. Note that we can't distinguish
9574 between "int" and "long" in this code if they are the same
9575 size, but that's fine, since neither can the assembler. */
9577 if (TYPE_PRECISION (type
) <= CHAR_TYPE_SIZE
)
9578 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 12 : 2));
9580 else if (TYPE_PRECISION (type
) <= SHORT_TYPE_SIZE
)
9581 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 13 : 3));
9583 else if (TYPE_PRECISION (type
) <= INT_TYPE_SIZE
)
9584 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 14 : 4));
9587 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 15 : 5));
9590 /* If this is a range type, consider it to be the underlying
9592 if (TREE_TYPE (type
) != 0)
9595 /* Carefully distinguish all the standard types of C,
9596 without messing up if the language is not C. */
9598 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
9599 return (qualifiers
| 6);
9602 return (qualifiers
| 7);
9604 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
9605 /* ??? We need to distinguish between double and float complex types,
9606 but I don't know how yet because I can't reach this code from
9607 existing front-ends. */
9608 return (qualifiers
| 7); /* Who knows? */
9611 case BOOLEAN_TYPE
: /* Boolean truth value type. */
9617 gcc_unreachable (); /* Not a type! */
9624 /* Nested function support. */
9626 /* Emit RTL insns to initialize the variable parts of a trampoline.
9627 FNADDR is an RTX for the address of the function's pure code.
9628 CXT is an RTX for the static chain value for the function.
9630 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
9631 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
9632 (to store insns). This is a bit excessive. Perhaps a different
9633 mechanism would be better here.
9635 Emit enough FLUSH insns to synchronize the data and instruction caches. */
9638 sparc32_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
9640 /* SPARC 32-bit trampoline:
9643 sethi %hi(static), %g2
9645 or %g2, %lo(static), %g2
9647 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
9648 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
9652 (adjust_address (m_tramp
, SImode
, 0),
9653 expand_binop (SImode
, ior_optab
,
9654 expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
, 10, 0, 1),
9655 GEN_INT (trunc_int_for_mode (0x03000000, SImode
)),
9656 NULL_RTX
, 1, OPTAB_DIRECT
));
9659 (adjust_address (m_tramp
, SImode
, 4),
9660 expand_binop (SImode
, ior_optab
,
9661 expand_shift (RSHIFT_EXPR
, SImode
, cxt
, 10, 0, 1),
9662 GEN_INT (trunc_int_for_mode (0x05000000, SImode
)),
9663 NULL_RTX
, 1, OPTAB_DIRECT
));
9666 (adjust_address (m_tramp
, SImode
, 8),
9667 expand_binop (SImode
, ior_optab
,
9668 expand_and (SImode
, fnaddr
, GEN_INT (0x3ff), NULL_RTX
),
9669 GEN_INT (trunc_int_for_mode (0x81c06000, SImode
)),
9670 NULL_RTX
, 1, OPTAB_DIRECT
));
9673 (adjust_address (m_tramp
, SImode
, 12),
9674 expand_binop (SImode
, ior_optab
,
9675 expand_and (SImode
, cxt
, GEN_INT (0x3ff), NULL_RTX
),
9676 GEN_INT (trunc_int_for_mode (0x8410a000, SImode
)),
9677 NULL_RTX
, 1, OPTAB_DIRECT
));
9679 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
9680 aligned on a 16 byte boundary so one flush clears it all. */
9681 emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp
, SImode
, 0))));
9682 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
9683 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
9684 && sparc_cpu
!= PROCESSOR_NIAGARA
9685 && sparc_cpu
!= PROCESSOR_NIAGARA2
9686 && sparc_cpu
!= PROCESSOR_NIAGARA3
9687 && sparc_cpu
!= PROCESSOR_NIAGARA4
9688 && sparc_cpu
!= PROCESSOR_NIAGARA7
9689 && sparc_cpu
!= PROCESSOR_M8
)
9690 emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp
, SImode
, 8))));
9692 /* Call __enable_execute_stack after writing onto the stack to make sure
9693 the stack address is accessible. */
9694 #ifdef HAVE_ENABLE_EXECUTE_STACK
9695 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
9696 LCT_NORMAL
, VOIDmode
, XEXP (m_tramp
, 0), Pmode
);
9701 /* The 64-bit version is simpler because it makes more sense to load the
9702 values as "immediate" data out of the trampoline. It's also easier since
9703 we can read the PC without clobbering a register. */
9706 sparc64_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
9708 /* SPARC 64-bit trampoline:
9717 emit_move_insn (adjust_address (m_tramp
, SImode
, 0),
9718 GEN_INT (trunc_int_for_mode (0x83414000, SImode
)));
9719 emit_move_insn (adjust_address (m_tramp
, SImode
, 4),
9720 GEN_INT (trunc_int_for_mode (0xca586018, SImode
)));
9721 emit_move_insn (adjust_address (m_tramp
, SImode
, 8),
9722 GEN_INT (trunc_int_for_mode (0x81c14000, SImode
)));
9723 emit_move_insn (adjust_address (m_tramp
, SImode
, 12),
9724 GEN_INT (trunc_int_for_mode (0xca586010, SImode
)));
9725 emit_move_insn (adjust_address (m_tramp
, DImode
, 16), cxt
);
9726 emit_move_insn (adjust_address (m_tramp
, DImode
, 24), fnaddr
);
9727 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 0))));
9729 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
9730 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
9731 && sparc_cpu
!= PROCESSOR_NIAGARA
9732 && sparc_cpu
!= PROCESSOR_NIAGARA2
9733 && sparc_cpu
!= PROCESSOR_NIAGARA3
9734 && sparc_cpu
!= PROCESSOR_NIAGARA4
9735 && sparc_cpu
!= PROCESSOR_NIAGARA7
9736 && sparc_cpu
!= PROCESSOR_M8
)
9737 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 8))));
9739 /* Call __enable_execute_stack after writing onto the stack to make sure
9740 the stack address is accessible. */
9741 #ifdef HAVE_ENABLE_EXECUTE_STACK
9742 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
9743 LCT_NORMAL
, VOIDmode
, XEXP (m_tramp
, 0), Pmode
);
9747 /* Worker for TARGET_TRAMPOLINE_INIT. */
9750 sparc_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
9752 rtx fnaddr
= force_reg (Pmode
, XEXP (DECL_RTL (fndecl
), 0));
9753 cxt
= force_reg (Pmode
, cxt
);
9755 sparc64_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
9757 sparc32_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
9760 /* Adjust the cost of a scheduling dependency. Return the new cost of
9761 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
9764 supersparc_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep_insn
,
9767 enum attr_type insn_type
;
9769 if (recog_memoized (insn
) < 0)
9772 insn_type
= get_attr_type (insn
);
9776 /* Data dependency; DEP_INSN writes a register that INSN reads some
9779 /* if a load, then the dependence must be on the memory address;
9780 add an extra "cycle". Note that the cost could be two cycles
9781 if the reg was written late in an instruction group; we ca not tell
9783 if (insn_type
== TYPE_LOAD
|| insn_type
== TYPE_FPLOAD
)
9786 /* Get the delay only if the address of the store is the dependence. */
9787 if (insn_type
== TYPE_STORE
|| insn_type
== TYPE_FPSTORE
)
9789 rtx pat
= PATTERN(insn
);
9790 rtx dep_pat
= PATTERN (dep_insn
);
9792 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
9793 return cost
; /* This should not happen! */
9795 /* The dependency between the two instructions was on the data that
9796 is being stored. Assume that this implies that the address of the
9797 store is not dependent. */
9798 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
9801 return cost
+ 3; /* An approximation. */
9804 /* A shift instruction cannot receive its data from an instruction
9805 in the same cycle; add a one cycle penalty. */
9806 if (insn_type
== TYPE_SHIFT
)
9807 return cost
+ 3; /* Split before cascade into shift. */
9811 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
9812 INSN writes some cycles later. */
9814 /* These are only significant for the fpu unit; writing a fp reg before
9815 the fpu has finished with it stalls the processor. */
9817 /* Reusing an integer register causes no problems. */
9818 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
9826 hypersparc_adjust_cost (rtx_insn
*insn
, int dtype
, rtx_insn
*dep_insn
,
9829 enum attr_type insn_type
, dep_type
;
9830 rtx pat
= PATTERN(insn
);
9831 rtx dep_pat
= PATTERN (dep_insn
);
9833 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
9836 insn_type
= get_attr_type (insn
);
9837 dep_type
= get_attr_type (dep_insn
);
9842 /* Data dependency; DEP_INSN writes a register that INSN reads some
9849 /* Get the delay iff the address of the store is the dependence. */
9850 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
9853 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
9860 /* If a load, then the dependence must be on the memory address. If
9861 the addresses aren't equal, then it might be a false dependency */
9862 if (dep_type
== TYPE_STORE
|| dep_type
== TYPE_FPSTORE
)
9864 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
9865 || GET_CODE (SET_DEST (dep_pat
)) != MEM
9866 || GET_CODE (SET_SRC (pat
)) != MEM
9867 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat
), 0),
9868 XEXP (SET_SRC (pat
), 0)))
9876 /* Compare to branch latency is 0. There is no benefit from
9877 separating compare and branch. */
9878 if (dep_type
== TYPE_COMPARE
)
9880 /* Floating point compare to branch latency is less than
9881 compare to conditional move. */
9882 if (dep_type
== TYPE_FPCMP
)
9891 /* Anti-dependencies only penalize the fpu unit. */
9892 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
9904 sparc_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep
, int cost
,
9909 case PROCESSOR_SUPERSPARC
:
9910 cost
= supersparc_adjust_cost (insn
, dep_type
, dep
, cost
);
9912 case PROCESSOR_HYPERSPARC
:
9913 case PROCESSOR_SPARCLITE86X
:
9914 cost
= hypersparc_adjust_cost (insn
, dep_type
, dep
, cost
);
9923 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
9924 int sched_verbose ATTRIBUTE_UNUSED
,
9925 int max_ready ATTRIBUTE_UNUSED
)
9929 sparc_use_sched_lookahead (void)
9931 if (sparc_cpu
== PROCESSOR_NIAGARA
9932 || sparc_cpu
== PROCESSOR_NIAGARA2
9933 || sparc_cpu
== PROCESSOR_NIAGARA3
)
9935 if (sparc_cpu
== PROCESSOR_NIAGARA4
9936 || sparc_cpu
== PROCESSOR_NIAGARA7
9937 || sparc_cpu
== PROCESSOR_M8
)
9939 if (sparc_cpu
== PROCESSOR_ULTRASPARC
9940 || sparc_cpu
== PROCESSOR_ULTRASPARC3
)
9942 if ((1 << sparc_cpu
) &
9943 ((1 << PROCESSOR_SUPERSPARC
) | (1 << PROCESSOR_HYPERSPARC
) |
9944 (1 << PROCESSOR_SPARCLITE86X
)))
9950 sparc_issue_rate (void)
9954 case PROCESSOR_NIAGARA
:
9955 case PROCESSOR_NIAGARA2
:
9956 case PROCESSOR_NIAGARA3
:
9959 case PROCESSOR_NIAGARA4
:
9960 case PROCESSOR_NIAGARA7
:
9962 /* Assume V9 processors are capable of at least dual-issue. */
9964 case PROCESSOR_SUPERSPARC
:
9966 case PROCESSOR_HYPERSPARC
:
9967 case PROCESSOR_SPARCLITE86X
:
9969 case PROCESSOR_ULTRASPARC
:
9970 case PROCESSOR_ULTRASPARC3
:
9977 set_extends (rtx_insn
*insn
)
9979 register rtx pat
= PATTERN (insn
);
9981 switch (GET_CODE (SET_SRC (pat
)))
9983 /* Load and some shift instructions zero extend. */
9986 /* sethi clears the high bits */
9988 /* LO_SUM is used with sethi. sethi cleared the high
9989 bits and the values used with lo_sum are positive */
9991 /* Store flag stores 0 or 1 */
10001 rtx op0
= XEXP (SET_SRC (pat
), 0);
10002 rtx op1
= XEXP (SET_SRC (pat
), 1);
10003 if (GET_CODE (op1
) == CONST_INT
)
10004 return INTVAL (op1
) >= 0;
10005 if (GET_CODE (op0
) != REG
)
10007 if (sparc_check_64 (op0
, insn
) == 1)
10009 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
10014 rtx op0
= XEXP (SET_SRC (pat
), 0);
10015 rtx op1
= XEXP (SET_SRC (pat
), 1);
10016 if (GET_CODE (op0
) != REG
|| sparc_check_64 (op0
, insn
) <= 0)
10018 if (GET_CODE (op1
) == CONST_INT
)
10019 return INTVAL (op1
) >= 0;
10020 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
10023 return GET_MODE (SET_SRC (pat
)) == SImode
;
10024 /* Positive integers leave the high bits zero. */
10026 return !(INTVAL (SET_SRC (pat
)) & 0x80000000);
10029 return - (GET_MODE (SET_SRC (pat
)) == SImode
);
10031 return sparc_check_64 (SET_SRC (pat
), insn
);
10037 /* We _ought_ to have only one kind per function, but... */
10038 static GTY(()) rtx sparc_addr_diff_list
;
10039 static GTY(()) rtx sparc_addr_list
;
10042 sparc_defer_case_vector (rtx lab
, rtx vec
, int diff
)
10044 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
10046 sparc_addr_diff_list
10047 = gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_diff_list
);
10049 sparc_addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_list
);
10053 sparc_output_addr_vec (rtx vec
)
10055 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
10056 int idx
, vlen
= XVECLEN (body
, 0);
10058 #ifdef ASM_OUTPUT_ADDR_VEC_START
10059 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
10062 #ifdef ASM_OUTPUT_CASE_LABEL
10063 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
10066 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
10069 for (idx
= 0; idx
< vlen
; idx
++)
10071 ASM_OUTPUT_ADDR_VEC_ELT
10072 (asm_out_file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
10075 #ifdef ASM_OUTPUT_ADDR_VEC_END
10076 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
10081 sparc_output_addr_diff_vec (rtx vec
)
10083 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
10084 rtx base
= XEXP (XEXP (body
, 0), 0);
10085 int idx
, vlen
= XVECLEN (body
, 1);
10087 #ifdef ASM_OUTPUT_ADDR_VEC_START
10088 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
10091 #ifdef ASM_OUTPUT_CASE_LABEL
10092 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
10095 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
10098 for (idx
= 0; idx
< vlen
; idx
++)
10100 ASM_OUTPUT_ADDR_DIFF_ELT
10103 CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 1, idx
), 0)),
10104 CODE_LABEL_NUMBER (base
));
10107 #ifdef ASM_OUTPUT_ADDR_VEC_END
10108 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
10113 sparc_output_deferred_case_vectors (void)
10118 if (sparc_addr_list
== NULL_RTX
10119 && sparc_addr_diff_list
== NULL_RTX
)
10122 /* Align to cache line in the function's code section. */
10123 switch_to_section (current_function_section ());
10125 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
10127 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
10129 for (t
= sparc_addr_list
; t
; t
= XEXP (t
, 1))
10130 sparc_output_addr_vec (XEXP (t
, 0));
10131 for (t
= sparc_addr_diff_list
; t
; t
= XEXP (t
, 1))
10132 sparc_output_addr_diff_vec (XEXP (t
, 0));
10134 sparc_addr_list
= sparc_addr_diff_list
= NULL_RTX
;
10137 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
10138 unknown. Return 1 if the high bits are zero, -1 if the register is
10141 sparc_check_64 (rtx x
, rtx_insn
*insn
)
10143 /* If a register is set only once it is safe to ignore insns this
10144 code does not know how to handle. The loop will either recognize
10145 the single set and return the correct value or fail to recognize
10146 it and return 0. */
10150 gcc_assert (GET_CODE (x
) == REG
);
10152 if (GET_MODE (x
) == DImode
)
10153 y
= gen_rtx_REG (SImode
, REGNO (x
) + WORDS_BIG_ENDIAN
);
10155 if (flag_expensive_optimizations
10156 && df
&& DF_REG_DEF_COUNT (REGNO (y
)) == 1)
10162 insn
= get_last_insn_anywhere ();
10167 while ((insn
= PREV_INSN (insn
)))
10169 switch (GET_CODE (insn
))
10182 rtx pat
= PATTERN (insn
);
10183 if (GET_CODE (pat
) != SET
)
10185 if (rtx_equal_p (x
, SET_DEST (pat
)))
10186 return set_extends (insn
);
10187 if (y
&& rtx_equal_p (y
, SET_DEST (pat
)))
10188 return set_extends (insn
);
10189 if (reg_overlap_mentioned_p (SET_DEST (pat
), y
))
10197 /* Output a wide shift instruction in V8+ mode. INSN is the instruction,
10198 OPERANDS are its operands and OPCODE is the mnemonic to be used. */
10201 output_v8plus_shift (rtx_insn
*insn
, rtx
*operands
, const char *opcode
)
10203 static char asm_code
[60];
10205 /* The scratch register is only required when the destination
10206 register is not a 64-bit global or out register. */
10207 if (which_alternative
!= 2)
10208 operands
[3] = operands
[0];
10210 /* We can only shift by constants <= 63. */
10211 if (GET_CODE (operands
[2]) == CONST_INT
)
10212 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0x3f);
10214 if (GET_CODE (operands
[1]) == CONST_INT
)
10216 output_asm_insn ("mov\t%1, %3", operands
);
10220 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
10221 if (sparc_check_64 (operands
[1], insn
) <= 0)
10222 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
10223 output_asm_insn ("or\t%L1, %3, %3", operands
);
10226 strcpy (asm_code
, opcode
);
10228 if (which_alternative
!= 2)
10229 return strcat (asm_code
, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
10232 strcat (asm_code
, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
10235 /* Output rtl to increment the profiler label LABELNO
10236 for profiling a function entry. */
10239 sparc_profile_hook (int labelno
)
10244 fun
= gen_rtx_SYMBOL_REF (Pmode
, MCOUNT_FUNCTION
);
10245 if (NO_PROFILE_COUNTERS
)
10247 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
);
10251 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
10252 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
10253 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, lab
, Pmode
);
10257 #ifdef TARGET_SOLARIS
10258 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
10261 sparc_solaris_elf_asm_named_section (const char *name
, unsigned int flags
,
10262 tree decl ATTRIBUTE_UNUSED
)
10264 if (HAVE_COMDAT_GROUP
&& flags
& SECTION_LINKONCE
)
10266 solaris_elf_asm_comdat_section (name
, flags
, decl
);
10270 fprintf (asm_out_file
, "\t.section\t\"%s\"", name
);
10272 if (!(flags
& SECTION_DEBUG
))
10273 fputs (",#alloc", asm_out_file
);
10274 if (flags
& SECTION_WRITE
)
10275 fputs (",#write", asm_out_file
);
10276 if (flags
& SECTION_TLS
)
10277 fputs (",#tls", asm_out_file
);
10278 if (flags
& SECTION_CODE
)
10279 fputs (",#execinstr", asm_out_file
);
10281 if (flags
& SECTION_NOTYPE
)
10283 else if (flags
& SECTION_BSS
)
10284 fputs (",#nobits", asm_out_file
);
10286 fputs (",#progbits", asm_out_file
);
10288 fputc ('\n', asm_out_file
);
10290 #endif /* TARGET_SOLARIS */
10292 /* We do not allow indirect calls to be optimized into sibling calls.
10294 We cannot use sibling calls when delayed branches are disabled
10295 because they will likely require the call delay slot to be filled.
10297 Also, on SPARC 32-bit we cannot emit a sibling call when the
10298 current function returns a structure. This is because the "unimp
10299 after call" convention would cause the callee to return to the
10300 wrong place. The generic code already disallows cases where the
10301 function being called returns a structure.
10303 It may seem strange how this last case could occur. Usually there
10304 is code after the call which jumps to epilogue code which dumps the
10305 return value into the struct return area. That ought to invalidate
10306 the sibling call right? Well, in the C++ case we can end up passing
10307 the pointer to the struct return area to a constructor (which returns
10308 void) and then nothing else happens. Such a sibling call would look
10309 valid without the added check here.
10311 VxWorks PIC PLT entries require the global pointer to be initialized
10312 on entry. We therefore can't emit sibling calls to them. */
10314 sparc_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
10317 && flag_delayed_branch
10318 && (TARGET_ARCH64
|| ! cfun
->returns_struct
)
10319 && !(TARGET_VXWORKS_RTP
10321 && !targetm
.binds_local_p (decl
)));
10324 /* libfunc renaming. */
10327 sparc_init_libfuncs (void)
10331 /* Use the subroutines that Sun's library provides for integer
10332 multiply and divide. The `*' prevents an underscore from
10333 being prepended by the compiler. .umul is a little faster
10335 set_optab_libfunc (smul_optab
, SImode
, "*.umul");
10336 set_optab_libfunc (sdiv_optab
, SImode
, "*.div");
10337 set_optab_libfunc (udiv_optab
, SImode
, "*.udiv");
10338 set_optab_libfunc (smod_optab
, SImode
, "*.rem");
10339 set_optab_libfunc (umod_optab
, SImode
, "*.urem");
10341 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
10342 set_optab_libfunc (add_optab
, TFmode
, "_Q_add");
10343 set_optab_libfunc (sub_optab
, TFmode
, "_Q_sub");
10344 set_optab_libfunc (neg_optab
, TFmode
, "_Q_neg");
10345 set_optab_libfunc (smul_optab
, TFmode
, "_Q_mul");
10346 set_optab_libfunc (sdiv_optab
, TFmode
, "_Q_div");
10348 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
10349 is because with soft-float, the SFmode and DFmode sqrt
10350 instructions will be absent, and the compiler will notice and
10351 try to use the TFmode sqrt instruction for calls to the
10352 builtin function sqrt, but this fails. */
10354 set_optab_libfunc (sqrt_optab
, TFmode
, "_Q_sqrt");
10356 set_optab_libfunc (eq_optab
, TFmode
, "_Q_feq");
10357 set_optab_libfunc (ne_optab
, TFmode
, "_Q_fne");
10358 set_optab_libfunc (gt_optab
, TFmode
, "_Q_fgt");
10359 set_optab_libfunc (ge_optab
, TFmode
, "_Q_fge");
10360 set_optab_libfunc (lt_optab
, TFmode
, "_Q_flt");
10361 set_optab_libfunc (le_optab
, TFmode
, "_Q_fle");
10363 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_Q_stoq");
10364 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_Q_dtoq");
10365 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_Q_qtos");
10366 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_Q_qtod");
10368 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_Q_qtoi");
10369 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_Q_qtou");
10370 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_Q_itoq");
10371 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_Q_utoq");
10373 if (DITF_CONVERSION_LIBFUNCS
)
10375 set_conv_libfunc (sfix_optab
, DImode
, TFmode
, "_Q_qtoll");
10376 set_conv_libfunc (ufix_optab
, DImode
, TFmode
, "_Q_qtoull");
10377 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
, "_Q_lltoq");
10378 set_conv_libfunc (ufloat_optab
, TFmode
, DImode
, "_Q_ulltoq");
10381 if (SUN_CONVERSION_LIBFUNCS
)
10383 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
10384 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
10385 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
10386 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
10391 /* In the SPARC 64bit ABI, SImode multiply and divide functions
10392 do not exist in the library. Make sure the compiler does not
10393 emit calls to them by accident. (It should always use the
10394 hardware instructions.) */
10395 set_optab_libfunc (smul_optab
, SImode
, 0);
10396 set_optab_libfunc (sdiv_optab
, SImode
, 0);
10397 set_optab_libfunc (udiv_optab
, SImode
, 0);
10398 set_optab_libfunc (smod_optab
, SImode
, 0);
10399 set_optab_libfunc (umod_optab
, SImode
, 0);
10401 if (SUN_INTEGER_MULTIPLY_64
)
10403 set_optab_libfunc (smul_optab
, DImode
, "__mul64");
10404 set_optab_libfunc (sdiv_optab
, DImode
, "__div64");
10405 set_optab_libfunc (udiv_optab
, DImode
, "__udiv64");
10406 set_optab_libfunc (smod_optab
, DImode
, "__rem64");
10407 set_optab_libfunc (umod_optab
, DImode
, "__urem64");
10410 if (SUN_CONVERSION_LIBFUNCS
)
10412 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftol");
10413 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoul");
10414 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtol");
10415 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoul");
10420 /* SPARC builtins. */
10421 enum sparc_builtins
10423 /* FPU builtins. */
10424 SPARC_BUILTIN_LDFSR
,
10425 SPARC_BUILTIN_STFSR
,
10427 /* VIS 1.0 builtins. */
10428 SPARC_BUILTIN_FPACK16
,
10429 SPARC_BUILTIN_FPACK32
,
10430 SPARC_BUILTIN_FPACKFIX
,
10431 SPARC_BUILTIN_FEXPAND
,
10432 SPARC_BUILTIN_FPMERGE
,
10433 SPARC_BUILTIN_FMUL8X16
,
10434 SPARC_BUILTIN_FMUL8X16AU
,
10435 SPARC_BUILTIN_FMUL8X16AL
,
10436 SPARC_BUILTIN_FMUL8SUX16
,
10437 SPARC_BUILTIN_FMUL8ULX16
,
10438 SPARC_BUILTIN_FMULD8SUX16
,
10439 SPARC_BUILTIN_FMULD8ULX16
,
10440 SPARC_BUILTIN_FALIGNDATAV4HI
,
10441 SPARC_BUILTIN_FALIGNDATAV8QI
,
10442 SPARC_BUILTIN_FALIGNDATAV2SI
,
10443 SPARC_BUILTIN_FALIGNDATADI
,
10444 SPARC_BUILTIN_WRGSR
,
10445 SPARC_BUILTIN_RDGSR
,
10446 SPARC_BUILTIN_ALIGNADDR
,
10447 SPARC_BUILTIN_ALIGNADDRL
,
10448 SPARC_BUILTIN_PDIST
,
10449 SPARC_BUILTIN_EDGE8
,
10450 SPARC_BUILTIN_EDGE8L
,
10451 SPARC_BUILTIN_EDGE16
,
10452 SPARC_BUILTIN_EDGE16L
,
10453 SPARC_BUILTIN_EDGE32
,
10454 SPARC_BUILTIN_EDGE32L
,
10455 SPARC_BUILTIN_FCMPLE16
,
10456 SPARC_BUILTIN_FCMPLE32
,
10457 SPARC_BUILTIN_FCMPNE16
,
10458 SPARC_BUILTIN_FCMPNE32
,
10459 SPARC_BUILTIN_FCMPGT16
,
10460 SPARC_BUILTIN_FCMPGT32
,
10461 SPARC_BUILTIN_FCMPEQ16
,
10462 SPARC_BUILTIN_FCMPEQ32
,
10463 SPARC_BUILTIN_FPADD16
,
10464 SPARC_BUILTIN_FPADD16S
,
10465 SPARC_BUILTIN_FPADD32
,
10466 SPARC_BUILTIN_FPADD32S
,
10467 SPARC_BUILTIN_FPSUB16
,
10468 SPARC_BUILTIN_FPSUB16S
,
10469 SPARC_BUILTIN_FPSUB32
,
10470 SPARC_BUILTIN_FPSUB32S
,
10471 SPARC_BUILTIN_ARRAY8
,
10472 SPARC_BUILTIN_ARRAY16
,
10473 SPARC_BUILTIN_ARRAY32
,
10475 /* VIS 2.0 builtins. */
10476 SPARC_BUILTIN_EDGE8N
,
10477 SPARC_BUILTIN_EDGE8LN
,
10478 SPARC_BUILTIN_EDGE16N
,
10479 SPARC_BUILTIN_EDGE16LN
,
10480 SPARC_BUILTIN_EDGE32N
,
10481 SPARC_BUILTIN_EDGE32LN
,
10482 SPARC_BUILTIN_BMASK
,
10483 SPARC_BUILTIN_BSHUFFLEV4HI
,
10484 SPARC_BUILTIN_BSHUFFLEV8QI
,
10485 SPARC_BUILTIN_BSHUFFLEV2SI
,
10486 SPARC_BUILTIN_BSHUFFLEDI
,
10488 /* VIS 3.0 builtins. */
10489 SPARC_BUILTIN_CMASK8
,
10490 SPARC_BUILTIN_CMASK16
,
10491 SPARC_BUILTIN_CMASK32
,
10492 SPARC_BUILTIN_FCHKSM16
,
10493 SPARC_BUILTIN_FSLL16
,
10494 SPARC_BUILTIN_FSLAS16
,
10495 SPARC_BUILTIN_FSRL16
,
10496 SPARC_BUILTIN_FSRA16
,
10497 SPARC_BUILTIN_FSLL32
,
10498 SPARC_BUILTIN_FSLAS32
,
10499 SPARC_BUILTIN_FSRL32
,
10500 SPARC_BUILTIN_FSRA32
,
10501 SPARC_BUILTIN_PDISTN
,
10502 SPARC_BUILTIN_FMEAN16
,
10503 SPARC_BUILTIN_FPADD64
,
10504 SPARC_BUILTIN_FPSUB64
,
10505 SPARC_BUILTIN_FPADDS16
,
10506 SPARC_BUILTIN_FPADDS16S
,
10507 SPARC_BUILTIN_FPSUBS16
,
10508 SPARC_BUILTIN_FPSUBS16S
,
10509 SPARC_BUILTIN_FPADDS32
,
10510 SPARC_BUILTIN_FPADDS32S
,
10511 SPARC_BUILTIN_FPSUBS32
,
10512 SPARC_BUILTIN_FPSUBS32S
,
10513 SPARC_BUILTIN_FUCMPLE8
,
10514 SPARC_BUILTIN_FUCMPNE8
,
10515 SPARC_BUILTIN_FUCMPGT8
,
10516 SPARC_BUILTIN_FUCMPEQ8
,
10517 SPARC_BUILTIN_FHADDS
,
10518 SPARC_BUILTIN_FHADDD
,
10519 SPARC_BUILTIN_FHSUBS
,
10520 SPARC_BUILTIN_FHSUBD
,
10521 SPARC_BUILTIN_FNHADDS
,
10522 SPARC_BUILTIN_FNHADDD
,
10523 SPARC_BUILTIN_UMULXHI
,
10524 SPARC_BUILTIN_XMULX
,
10525 SPARC_BUILTIN_XMULXHI
,
10527 /* VIS 4.0 builtins. */
10528 SPARC_BUILTIN_FPADD8
,
10529 SPARC_BUILTIN_FPADDS8
,
10530 SPARC_BUILTIN_FPADDUS8
,
10531 SPARC_BUILTIN_FPADDUS16
,
10532 SPARC_BUILTIN_FPCMPLE8
,
10533 SPARC_BUILTIN_FPCMPGT8
,
10534 SPARC_BUILTIN_FPCMPULE16
,
10535 SPARC_BUILTIN_FPCMPUGT16
,
10536 SPARC_BUILTIN_FPCMPULE32
,
10537 SPARC_BUILTIN_FPCMPUGT32
,
10538 SPARC_BUILTIN_FPMAX8
,
10539 SPARC_BUILTIN_FPMAX16
,
10540 SPARC_BUILTIN_FPMAX32
,
10541 SPARC_BUILTIN_FPMAXU8
,
10542 SPARC_BUILTIN_FPMAXU16
,
10543 SPARC_BUILTIN_FPMAXU32
,
10544 SPARC_BUILTIN_FPMIN8
,
10545 SPARC_BUILTIN_FPMIN16
,
10546 SPARC_BUILTIN_FPMIN32
,
10547 SPARC_BUILTIN_FPMINU8
,
10548 SPARC_BUILTIN_FPMINU16
,
10549 SPARC_BUILTIN_FPMINU32
,
10550 SPARC_BUILTIN_FPSUB8
,
10551 SPARC_BUILTIN_FPSUBS8
,
10552 SPARC_BUILTIN_FPSUBUS8
,
10553 SPARC_BUILTIN_FPSUBUS16
,
10555 /* VIS 4.0B builtins. */
10557 /* Note that all the DICTUNPACK* entries should be kept
10559 SPARC_BUILTIN_FIRST_DICTUNPACK
,
10560 SPARC_BUILTIN_DICTUNPACK8
= SPARC_BUILTIN_FIRST_DICTUNPACK
,
10561 SPARC_BUILTIN_DICTUNPACK16
,
10562 SPARC_BUILTIN_DICTUNPACK32
,
10563 SPARC_BUILTIN_LAST_DICTUNPACK
= SPARC_BUILTIN_DICTUNPACK32
,
10565 /* Note that all the FPCMP*SHL entries should be kept
10567 SPARC_BUILTIN_FIRST_FPCMPSHL
,
10568 SPARC_BUILTIN_FPCMPLE8SHL
= SPARC_BUILTIN_FIRST_FPCMPSHL
,
10569 SPARC_BUILTIN_FPCMPGT8SHL
,
10570 SPARC_BUILTIN_FPCMPEQ8SHL
,
10571 SPARC_BUILTIN_FPCMPNE8SHL
,
10572 SPARC_BUILTIN_FPCMPLE16SHL
,
10573 SPARC_BUILTIN_FPCMPGT16SHL
,
10574 SPARC_BUILTIN_FPCMPEQ16SHL
,
10575 SPARC_BUILTIN_FPCMPNE16SHL
,
10576 SPARC_BUILTIN_FPCMPLE32SHL
,
10577 SPARC_BUILTIN_FPCMPGT32SHL
,
10578 SPARC_BUILTIN_FPCMPEQ32SHL
,
10579 SPARC_BUILTIN_FPCMPNE32SHL
,
10580 SPARC_BUILTIN_FPCMPULE8SHL
,
10581 SPARC_BUILTIN_FPCMPUGT8SHL
,
10582 SPARC_BUILTIN_FPCMPULE16SHL
,
10583 SPARC_BUILTIN_FPCMPUGT16SHL
,
10584 SPARC_BUILTIN_FPCMPULE32SHL
,
10585 SPARC_BUILTIN_FPCMPUGT32SHL
,
10586 SPARC_BUILTIN_FPCMPDE8SHL
,
10587 SPARC_BUILTIN_FPCMPDE16SHL
,
10588 SPARC_BUILTIN_FPCMPDE32SHL
,
10589 SPARC_BUILTIN_FPCMPUR8SHL
,
10590 SPARC_BUILTIN_FPCMPUR16SHL
,
10591 SPARC_BUILTIN_FPCMPUR32SHL
,
10592 SPARC_BUILTIN_LAST_FPCMPSHL
= SPARC_BUILTIN_FPCMPUR32SHL
,
10597 static GTY (()) tree sparc_builtins
[(int) SPARC_BUILTIN_MAX
];
10598 static enum insn_code sparc_builtins_icode
[(int) SPARC_BUILTIN_MAX
];
10600 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
10601 The instruction should require a constant operand of some sort. The
10602 function prints an error if OPVAL is not valid. */
10605 check_constant_argument (enum insn_code icode
, int opnum
, rtx opval
)
10607 if (GET_CODE (opval
) != CONST_INT
)
10609 error ("%qs expects a constant argument", insn_data
[icode
].name
);
10613 if (!(*insn_data
[icode
].operand
[opnum
].predicate
) (opval
, VOIDmode
))
10615 error ("constant argument out of range for %qs", insn_data
[icode
].name
);
10621 /* Add a SPARC builtin function with NAME, ICODE, CODE and TYPE. Return the
10622 function decl or NULL_TREE if the builtin was not added. */
10625 def_builtin (const char *name
, enum insn_code icode
, enum sparc_builtins code
,
10629 = add_builtin_function (name
, type
, code
, BUILT_IN_MD
, NULL
, NULL_TREE
);
10633 sparc_builtins
[code
] = t
;
10634 sparc_builtins_icode
[code
] = icode
;
10640 /* Likewise, but also marks the function as "const". */
10643 def_builtin_const (const char *name
, enum insn_code icode
,
10644 enum sparc_builtins code
, tree type
)
10646 tree t
= def_builtin (name
, icode
, code
, type
);
10649 TREE_READONLY (t
) = 1;
10654 /* Implement the TARGET_INIT_BUILTINS target hook.
10655 Create builtin functions for special SPARC instructions. */
10658 sparc_init_builtins (void)
10661 sparc_fpu_init_builtins ();
10664 sparc_vis_init_builtins ();
10667 /* Create builtin functions for FPU instructions. */
10670 sparc_fpu_init_builtins (void)
10673 = build_function_type_list (void_type_node
,
10674 build_pointer_type (unsigned_type_node
), 0);
10675 def_builtin ("__builtin_load_fsr", CODE_FOR_ldfsr
,
10676 SPARC_BUILTIN_LDFSR
, ftype
);
10677 def_builtin ("__builtin_store_fsr", CODE_FOR_stfsr
,
10678 SPARC_BUILTIN_STFSR
, ftype
);
10681 /* Create builtin functions for VIS instructions. */
10684 sparc_vis_init_builtins (void)
10686 tree v4qi
= build_vector_type (unsigned_intQI_type_node
, 4);
10687 tree v8qi
= build_vector_type (unsigned_intQI_type_node
, 8);
10688 tree v4hi
= build_vector_type (intHI_type_node
, 4);
10689 tree v2hi
= build_vector_type (intHI_type_node
, 2);
10690 tree v2si
= build_vector_type (intSI_type_node
, 2);
10691 tree v1si
= build_vector_type (intSI_type_node
, 1);
10693 tree v4qi_ftype_v4hi
= build_function_type_list (v4qi
, v4hi
, 0);
10694 tree v8qi_ftype_v2si_v8qi
= build_function_type_list (v8qi
, v2si
, v8qi
, 0);
10695 tree v2hi_ftype_v2si
= build_function_type_list (v2hi
, v2si
, 0);
10696 tree v4hi_ftype_v4qi
= build_function_type_list (v4hi
, v4qi
, 0);
10697 tree v8qi_ftype_v4qi_v4qi
= build_function_type_list (v8qi
, v4qi
, v4qi
, 0);
10698 tree v4hi_ftype_v4qi_v4hi
= build_function_type_list (v4hi
, v4qi
, v4hi
, 0);
10699 tree v4hi_ftype_v4qi_v2hi
= build_function_type_list (v4hi
, v4qi
, v2hi
, 0);
10700 tree v2si_ftype_v4qi_v2hi
= build_function_type_list (v2si
, v4qi
, v2hi
, 0);
10701 tree v4hi_ftype_v8qi_v4hi
= build_function_type_list (v4hi
, v8qi
, v4hi
, 0);
10702 tree v4hi_ftype_v4hi_v4hi
= build_function_type_list (v4hi
, v4hi
, v4hi
, 0);
10703 tree v2si_ftype_v2si_v2si
= build_function_type_list (v2si
, v2si
, v2si
, 0);
10704 tree v8qi_ftype_v8qi_v8qi
= build_function_type_list (v8qi
, v8qi
, v8qi
, 0);
10705 tree v2hi_ftype_v2hi_v2hi
= build_function_type_list (v2hi
, v2hi
, v2hi
, 0);
10706 tree v1si_ftype_v1si_v1si
= build_function_type_list (v1si
, v1si
, v1si
, 0);
10707 tree di_ftype_v8qi_v8qi_di
= build_function_type_list (intDI_type_node
,
10709 intDI_type_node
, 0);
10710 tree di_ftype_v8qi_v8qi
= build_function_type_list (intDI_type_node
,
10712 tree si_ftype_v8qi_v8qi
= build_function_type_list (intSI_type_node
,
10714 tree v8qi_ftype_df_si
= build_function_type_list (v8qi
, double_type_node
,
10715 intSI_type_node
, 0);
10716 tree v4hi_ftype_df_si
= build_function_type_list (v4hi
, double_type_node
,
10717 intSI_type_node
, 0);
10718 tree v2si_ftype_df_si
= build_function_type_list (v2si
, double_type_node
,
10719 intDI_type_node
, 0);
10720 tree di_ftype_di_di
= build_function_type_list (intDI_type_node
,
10722 intDI_type_node
, 0);
10723 tree si_ftype_si_si
= build_function_type_list (intSI_type_node
,
10725 intSI_type_node
, 0);
10726 tree ptr_ftype_ptr_si
= build_function_type_list (ptr_type_node
,
10728 intSI_type_node
, 0);
10729 tree ptr_ftype_ptr_di
= build_function_type_list (ptr_type_node
,
10731 intDI_type_node
, 0);
10732 tree si_ftype_ptr_ptr
= build_function_type_list (intSI_type_node
,
10735 tree di_ftype_ptr_ptr
= build_function_type_list (intDI_type_node
,
10738 tree si_ftype_v4hi_v4hi
= build_function_type_list (intSI_type_node
,
10740 tree si_ftype_v2si_v2si
= build_function_type_list (intSI_type_node
,
10742 tree di_ftype_v4hi_v4hi
= build_function_type_list (intDI_type_node
,
10744 tree di_ftype_v2si_v2si
= build_function_type_list (intDI_type_node
,
10746 tree void_ftype_di
= build_function_type_list (void_type_node
,
10747 intDI_type_node
, 0);
10748 tree di_ftype_void
= build_function_type_list (intDI_type_node
,
10749 void_type_node
, 0);
10750 tree void_ftype_si
= build_function_type_list (void_type_node
,
10751 intSI_type_node
, 0);
10752 tree sf_ftype_sf_sf
= build_function_type_list (float_type_node
,
10754 float_type_node
, 0);
10755 tree df_ftype_df_df
= build_function_type_list (double_type_node
,
10757 double_type_node
, 0);
10759 /* Packing and expanding vectors. */
10760 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis
,
10761 SPARC_BUILTIN_FPACK16
, v4qi_ftype_v4hi
);
10762 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis
,
10763 SPARC_BUILTIN_FPACK32
, v8qi_ftype_v2si_v8qi
);
10764 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis
,
10765 SPARC_BUILTIN_FPACKFIX
, v2hi_ftype_v2si
);
10766 def_builtin_const ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis
,
10767 SPARC_BUILTIN_FEXPAND
, v4hi_ftype_v4qi
);
10768 def_builtin_const ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis
,
10769 SPARC_BUILTIN_FPMERGE
, v8qi_ftype_v4qi_v4qi
);
10771 /* Multiplications. */
10772 def_builtin_const ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis
,
10773 SPARC_BUILTIN_FMUL8X16
, v4hi_ftype_v4qi_v4hi
);
10774 def_builtin_const ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis
,
10775 SPARC_BUILTIN_FMUL8X16AU
, v4hi_ftype_v4qi_v2hi
);
10776 def_builtin_const ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis
,
10777 SPARC_BUILTIN_FMUL8X16AL
, v4hi_ftype_v4qi_v2hi
);
10778 def_builtin_const ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis
,
10779 SPARC_BUILTIN_FMUL8SUX16
, v4hi_ftype_v8qi_v4hi
);
10780 def_builtin_const ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis
,
10781 SPARC_BUILTIN_FMUL8ULX16
, v4hi_ftype_v8qi_v4hi
);
10782 def_builtin_const ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis
,
10783 SPARC_BUILTIN_FMULD8SUX16
, v2si_ftype_v4qi_v2hi
);
10784 def_builtin_const ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis
,
10785 SPARC_BUILTIN_FMULD8ULX16
, v2si_ftype_v4qi_v2hi
);
10787 /* Data aligning. */
10788 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis
,
10789 SPARC_BUILTIN_FALIGNDATAV4HI
, v4hi_ftype_v4hi_v4hi
);
10790 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis
,
10791 SPARC_BUILTIN_FALIGNDATAV8QI
, v8qi_ftype_v8qi_v8qi
);
10792 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis
,
10793 SPARC_BUILTIN_FALIGNDATAV2SI
, v2si_ftype_v2si_v2si
);
10794 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatav1di_vis
,
10795 SPARC_BUILTIN_FALIGNDATADI
, di_ftype_di_di
);
10797 def_builtin ("__builtin_vis_write_gsr", CODE_FOR_wrgsr_vis
,
10798 SPARC_BUILTIN_WRGSR
, void_ftype_di
);
10799 def_builtin ("__builtin_vis_read_gsr", CODE_FOR_rdgsr_vis
,
10800 SPARC_BUILTIN_RDGSR
, di_ftype_void
);
10804 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis
,
10805 SPARC_BUILTIN_ALIGNADDR
, ptr_ftype_ptr_di
);
10806 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrldi_vis
,
10807 SPARC_BUILTIN_ALIGNADDRL
, ptr_ftype_ptr_di
);
10811 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis
,
10812 SPARC_BUILTIN_ALIGNADDR
, ptr_ftype_ptr_si
);
10813 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrlsi_vis
,
10814 SPARC_BUILTIN_ALIGNADDRL
, ptr_ftype_ptr_si
);
10817 /* Pixel distance. */
10818 def_builtin_const ("__builtin_vis_pdist", CODE_FOR_pdist_vis
,
10819 SPARC_BUILTIN_PDIST
, di_ftype_v8qi_v8qi_di
);
10821 /* Edge handling. */
10824 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8di_vis
,
10825 SPARC_BUILTIN_EDGE8
, di_ftype_ptr_ptr
);
10826 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8ldi_vis
,
10827 SPARC_BUILTIN_EDGE8L
, di_ftype_ptr_ptr
);
10828 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16di_vis
,
10829 SPARC_BUILTIN_EDGE16
, di_ftype_ptr_ptr
);
10830 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16ldi_vis
,
10831 SPARC_BUILTIN_EDGE16L
, di_ftype_ptr_ptr
);
10832 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32di_vis
,
10833 SPARC_BUILTIN_EDGE32
, di_ftype_ptr_ptr
);
10834 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32ldi_vis
,
10835 SPARC_BUILTIN_EDGE32L
, di_ftype_ptr_ptr
);
10839 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8si_vis
,
10840 SPARC_BUILTIN_EDGE8
, si_ftype_ptr_ptr
);
10841 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8lsi_vis
,
10842 SPARC_BUILTIN_EDGE8L
, si_ftype_ptr_ptr
);
10843 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16si_vis
,
10844 SPARC_BUILTIN_EDGE16
, si_ftype_ptr_ptr
);
10845 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16lsi_vis
,
10846 SPARC_BUILTIN_EDGE16L
, si_ftype_ptr_ptr
);
10847 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32si_vis
,
10848 SPARC_BUILTIN_EDGE32
, si_ftype_ptr_ptr
);
10849 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32lsi_vis
,
10850 SPARC_BUILTIN_EDGE32L
, si_ftype_ptr_ptr
);
10853 /* Pixel compare. */
10856 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16di_vis
,
10857 SPARC_BUILTIN_FCMPLE16
, di_ftype_v4hi_v4hi
);
10858 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32di_vis
,
10859 SPARC_BUILTIN_FCMPLE32
, di_ftype_v2si_v2si
);
10860 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16di_vis
,
10861 SPARC_BUILTIN_FCMPNE16
, di_ftype_v4hi_v4hi
);
10862 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32di_vis
,
10863 SPARC_BUILTIN_FCMPNE32
, di_ftype_v2si_v2si
);
10864 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16di_vis
,
10865 SPARC_BUILTIN_FCMPGT16
, di_ftype_v4hi_v4hi
);
10866 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32di_vis
,
10867 SPARC_BUILTIN_FCMPGT32
, di_ftype_v2si_v2si
);
10868 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16di_vis
,
10869 SPARC_BUILTIN_FCMPEQ16
, di_ftype_v4hi_v4hi
);
10870 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32di_vis
,
10871 SPARC_BUILTIN_FCMPEQ32
, di_ftype_v2si_v2si
);
10875 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16si_vis
,
10876 SPARC_BUILTIN_FCMPLE16
, si_ftype_v4hi_v4hi
);
10877 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32si_vis
,
10878 SPARC_BUILTIN_FCMPLE32
, si_ftype_v2si_v2si
);
10879 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16si_vis
,
10880 SPARC_BUILTIN_FCMPNE16
, si_ftype_v4hi_v4hi
);
10881 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32si_vis
,
10882 SPARC_BUILTIN_FCMPNE32
, si_ftype_v2si_v2si
);
10883 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16si_vis
,
10884 SPARC_BUILTIN_FCMPGT16
, si_ftype_v4hi_v4hi
);
10885 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32si_vis
,
10886 SPARC_BUILTIN_FCMPGT32
, si_ftype_v2si_v2si
);
10887 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16si_vis
,
10888 SPARC_BUILTIN_FCMPEQ16
, si_ftype_v4hi_v4hi
);
10889 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32si_vis
,
10890 SPARC_BUILTIN_FCMPEQ32
, si_ftype_v2si_v2si
);
10893 /* Addition and subtraction. */
10894 def_builtin_const ("__builtin_vis_fpadd16", CODE_FOR_addv4hi3
,
10895 SPARC_BUILTIN_FPADD16
, v4hi_ftype_v4hi_v4hi
);
10896 def_builtin_const ("__builtin_vis_fpadd16s", CODE_FOR_addv2hi3
,
10897 SPARC_BUILTIN_FPADD16S
, v2hi_ftype_v2hi_v2hi
);
10898 def_builtin_const ("__builtin_vis_fpadd32", CODE_FOR_addv2si3
,
10899 SPARC_BUILTIN_FPADD32
, v2si_ftype_v2si_v2si
);
10900 def_builtin_const ("__builtin_vis_fpadd32s", CODE_FOR_addv1si3
,
10901 SPARC_BUILTIN_FPADD32S
, v1si_ftype_v1si_v1si
);
10902 def_builtin_const ("__builtin_vis_fpsub16", CODE_FOR_subv4hi3
,
10903 SPARC_BUILTIN_FPSUB16
, v4hi_ftype_v4hi_v4hi
);
10904 def_builtin_const ("__builtin_vis_fpsub16s", CODE_FOR_subv2hi3
,
10905 SPARC_BUILTIN_FPSUB16S
, v2hi_ftype_v2hi_v2hi
);
10906 def_builtin_const ("__builtin_vis_fpsub32", CODE_FOR_subv2si3
,
10907 SPARC_BUILTIN_FPSUB32
, v2si_ftype_v2si_v2si
);
10908 def_builtin_const ("__builtin_vis_fpsub32s", CODE_FOR_subv1si3
,
10909 SPARC_BUILTIN_FPSUB32S
, v1si_ftype_v1si_v1si
);
10911 /* Three-dimensional array addressing. */
10914 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8di_vis
,
10915 SPARC_BUILTIN_ARRAY8
, di_ftype_di_di
);
10916 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16di_vis
,
10917 SPARC_BUILTIN_ARRAY16
, di_ftype_di_di
);
10918 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32di_vis
,
10919 SPARC_BUILTIN_ARRAY32
, di_ftype_di_di
);
10923 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8si_vis
,
10924 SPARC_BUILTIN_ARRAY8
, si_ftype_si_si
);
10925 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16si_vis
,
10926 SPARC_BUILTIN_ARRAY16
, si_ftype_si_si
);
10927 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32si_vis
,
10928 SPARC_BUILTIN_ARRAY32
, si_ftype_si_si
);
10933 /* Edge handling. */
10936 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8ndi_vis
,
10937 SPARC_BUILTIN_EDGE8N
, di_ftype_ptr_ptr
);
10938 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lndi_vis
,
10939 SPARC_BUILTIN_EDGE8LN
, di_ftype_ptr_ptr
);
10940 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16ndi_vis
,
10941 SPARC_BUILTIN_EDGE16N
, di_ftype_ptr_ptr
);
10942 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lndi_vis
,
10943 SPARC_BUILTIN_EDGE16LN
, di_ftype_ptr_ptr
);
10944 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32ndi_vis
,
10945 SPARC_BUILTIN_EDGE32N
, di_ftype_ptr_ptr
);
10946 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lndi_vis
,
10947 SPARC_BUILTIN_EDGE32LN
, di_ftype_ptr_ptr
);
10951 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8nsi_vis
,
10952 SPARC_BUILTIN_EDGE8N
, si_ftype_ptr_ptr
);
10953 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lnsi_vis
,
10954 SPARC_BUILTIN_EDGE8LN
, si_ftype_ptr_ptr
);
10955 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16nsi_vis
,
10956 SPARC_BUILTIN_EDGE16N
, si_ftype_ptr_ptr
);
10957 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lnsi_vis
,
10958 SPARC_BUILTIN_EDGE16LN
, si_ftype_ptr_ptr
);
10959 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32nsi_vis
,
10960 SPARC_BUILTIN_EDGE32N
, si_ftype_ptr_ptr
);
10961 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lnsi_vis
,
10962 SPARC_BUILTIN_EDGE32LN
, si_ftype_ptr_ptr
);
10965 /* Byte mask and shuffle. */
10967 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmaskdi_vis
,
10968 SPARC_BUILTIN_BMASK
, di_ftype_di_di
);
10970 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmasksi_vis
,
10971 SPARC_BUILTIN_BMASK
, si_ftype_si_si
);
10972 def_builtin ("__builtin_vis_bshufflev4hi", CODE_FOR_bshufflev4hi_vis
,
10973 SPARC_BUILTIN_BSHUFFLEV4HI
, v4hi_ftype_v4hi_v4hi
);
10974 def_builtin ("__builtin_vis_bshufflev8qi", CODE_FOR_bshufflev8qi_vis
,
10975 SPARC_BUILTIN_BSHUFFLEV8QI
, v8qi_ftype_v8qi_v8qi
);
10976 def_builtin ("__builtin_vis_bshufflev2si", CODE_FOR_bshufflev2si_vis
,
10977 SPARC_BUILTIN_BSHUFFLEV2SI
, v2si_ftype_v2si_v2si
);
10978 def_builtin ("__builtin_vis_bshuffledi", CODE_FOR_bshufflev1di_vis
,
10979 SPARC_BUILTIN_BSHUFFLEDI
, di_ftype_di_di
);
10986 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8di_vis
,
10987 SPARC_BUILTIN_CMASK8
, void_ftype_di
);
10988 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16di_vis
,
10989 SPARC_BUILTIN_CMASK16
, void_ftype_di
);
10990 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32di_vis
,
10991 SPARC_BUILTIN_CMASK32
, void_ftype_di
);
10995 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8si_vis
,
10996 SPARC_BUILTIN_CMASK8
, void_ftype_si
);
10997 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16si_vis
,
10998 SPARC_BUILTIN_CMASK16
, void_ftype_si
);
10999 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32si_vis
,
11000 SPARC_BUILTIN_CMASK32
, void_ftype_si
);
11003 def_builtin_const ("__builtin_vis_fchksm16", CODE_FOR_fchksm16_vis
,
11004 SPARC_BUILTIN_FCHKSM16
, v4hi_ftype_v4hi_v4hi
);
11006 def_builtin_const ("__builtin_vis_fsll16", CODE_FOR_vashlv4hi3
,
11007 SPARC_BUILTIN_FSLL16
, v4hi_ftype_v4hi_v4hi
);
11008 def_builtin_const ("__builtin_vis_fslas16", CODE_FOR_vssashlv4hi3
,
11009 SPARC_BUILTIN_FSLAS16
, v4hi_ftype_v4hi_v4hi
);
11010 def_builtin_const ("__builtin_vis_fsrl16", CODE_FOR_vlshrv4hi3
,
11011 SPARC_BUILTIN_FSRL16
, v4hi_ftype_v4hi_v4hi
);
11012 def_builtin_const ("__builtin_vis_fsra16", CODE_FOR_vashrv4hi3
,
11013 SPARC_BUILTIN_FSRA16
, v4hi_ftype_v4hi_v4hi
);
11014 def_builtin_const ("__builtin_vis_fsll32", CODE_FOR_vashlv2si3
,
11015 SPARC_BUILTIN_FSLL32
, v2si_ftype_v2si_v2si
);
11016 def_builtin_const ("__builtin_vis_fslas32", CODE_FOR_vssashlv2si3
,
11017 SPARC_BUILTIN_FSLAS32
, v2si_ftype_v2si_v2si
);
11018 def_builtin_const ("__builtin_vis_fsrl32", CODE_FOR_vlshrv2si3
,
11019 SPARC_BUILTIN_FSRL32
, v2si_ftype_v2si_v2si
);
11020 def_builtin_const ("__builtin_vis_fsra32", CODE_FOR_vashrv2si3
,
11021 SPARC_BUILTIN_FSRA32
, v2si_ftype_v2si_v2si
);
11024 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistndi_vis
,
11025 SPARC_BUILTIN_PDISTN
, di_ftype_v8qi_v8qi
);
11027 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistnsi_vis
,
11028 SPARC_BUILTIN_PDISTN
, si_ftype_v8qi_v8qi
);
11030 def_builtin_const ("__builtin_vis_fmean16", CODE_FOR_fmean16_vis
,
11031 SPARC_BUILTIN_FMEAN16
, v4hi_ftype_v4hi_v4hi
);
11032 def_builtin_const ("__builtin_vis_fpadd64", CODE_FOR_fpadd64_vis
,
11033 SPARC_BUILTIN_FPADD64
, di_ftype_di_di
);
11034 def_builtin_const ("__builtin_vis_fpsub64", CODE_FOR_fpsub64_vis
,
11035 SPARC_BUILTIN_FPSUB64
, di_ftype_di_di
);
11037 def_builtin_const ("__builtin_vis_fpadds16", CODE_FOR_ssaddv4hi3
,
11038 SPARC_BUILTIN_FPADDS16
, v4hi_ftype_v4hi_v4hi
);
11039 def_builtin_const ("__builtin_vis_fpadds16s", CODE_FOR_ssaddv2hi3
,
11040 SPARC_BUILTIN_FPADDS16S
, v2hi_ftype_v2hi_v2hi
);
11041 def_builtin_const ("__builtin_vis_fpsubs16", CODE_FOR_sssubv4hi3
,
11042 SPARC_BUILTIN_FPSUBS16
, v4hi_ftype_v4hi_v4hi
);
11043 def_builtin_const ("__builtin_vis_fpsubs16s", CODE_FOR_sssubv2hi3
,
11044 SPARC_BUILTIN_FPSUBS16S
, v2hi_ftype_v2hi_v2hi
);
11045 def_builtin_const ("__builtin_vis_fpadds32", CODE_FOR_ssaddv2si3
,
11046 SPARC_BUILTIN_FPADDS32
, v2si_ftype_v2si_v2si
);
11047 def_builtin_const ("__builtin_vis_fpadds32s", CODE_FOR_ssaddv1si3
,
11048 SPARC_BUILTIN_FPADDS32S
, v1si_ftype_v1si_v1si
);
11049 def_builtin_const ("__builtin_vis_fpsubs32", CODE_FOR_sssubv2si3
,
11050 SPARC_BUILTIN_FPSUBS32
, v2si_ftype_v2si_v2si
);
11051 def_builtin_const ("__builtin_vis_fpsubs32s", CODE_FOR_sssubv1si3
,
11052 SPARC_BUILTIN_FPSUBS32S
, v1si_ftype_v1si_v1si
);
11056 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8di_vis
,
11057 SPARC_BUILTIN_FUCMPLE8
, di_ftype_v8qi_v8qi
);
11058 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8di_vis
,
11059 SPARC_BUILTIN_FUCMPNE8
, di_ftype_v8qi_v8qi
);
11060 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8di_vis
,
11061 SPARC_BUILTIN_FUCMPGT8
, di_ftype_v8qi_v8qi
);
11062 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8di_vis
,
11063 SPARC_BUILTIN_FUCMPEQ8
, di_ftype_v8qi_v8qi
);
11067 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8si_vis
,
11068 SPARC_BUILTIN_FUCMPLE8
, si_ftype_v8qi_v8qi
);
11069 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8si_vis
,
11070 SPARC_BUILTIN_FUCMPNE8
, si_ftype_v8qi_v8qi
);
11071 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8si_vis
,
11072 SPARC_BUILTIN_FUCMPGT8
, si_ftype_v8qi_v8qi
);
11073 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8si_vis
,
11074 SPARC_BUILTIN_FUCMPEQ8
, si_ftype_v8qi_v8qi
);
11077 def_builtin_const ("__builtin_vis_fhadds", CODE_FOR_fhaddsf_vis
,
11078 SPARC_BUILTIN_FHADDS
, sf_ftype_sf_sf
);
11079 def_builtin_const ("__builtin_vis_fhaddd", CODE_FOR_fhadddf_vis
,
11080 SPARC_BUILTIN_FHADDD
, df_ftype_df_df
);
11081 def_builtin_const ("__builtin_vis_fhsubs", CODE_FOR_fhsubsf_vis
,
11082 SPARC_BUILTIN_FHSUBS
, sf_ftype_sf_sf
);
11083 def_builtin_const ("__builtin_vis_fhsubd", CODE_FOR_fhsubdf_vis
,
11084 SPARC_BUILTIN_FHSUBD
, df_ftype_df_df
);
11085 def_builtin_const ("__builtin_vis_fnhadds", CODE_FOR_fnhaddsf_vis
,
11086 SPARC_BUILTIN_FNHADDS
, sf_ftype_sf_sf
);
11087 def_builtin_const ("__builtin_vis_fnhaddd", CODE_FOR_fnhadddf_vis
,
11088 SPARC_BUILTIN_FNHADDD
, df_ftype_df_df
);
11090 def_builtin_const ("__builtin_vis_umulxhi", CODE_FOR_umulxhi_vis
,
11091 SPARC_BUILTIN_UMULXHI
, di_ftype_di_di
);
11092 def_builtin_const ("__builtin_vis_xmulx", CODE_FOR_xmulx_vis
,
11093 SPARC_BUILTIN_XMULX
, di_ftype_di_di
);
11094 def_builtin_const ("__builtin_vis_xmulxhi", CODE_FOR_xmulxhi_vis
,
11095 SPARC_BUILTIN_XMULXHI
, di_ftype_di_di
);
11100 def_builtin_const ("__builtin_vis_fpadd8", CODE_FOR_addv8qi3
,
11101 SPARC_BUILTIN_FPADD8
, v8qi_ftype_v8qi_v8qi
);
11102 def_builtin_const ("__builtin_vis_fpadds8", CODE_FOR_ssaddv8qi3
,
11103 SPARC_BUILTIN_FPADDS8
, v8qi_ftype_v8qi_v8qi
);
11104 def_builtin_const ("__builtin_vis_fpaddus8", CODE_FOR_usaddv8qi3
,
11105 SPARC_BUILTIN_FPADDUS8
, v8qi_ftype_v8qi_v8qi
);
11106 def_builtin_const ("__builtin_vis_fpaddus16", CODE_FOR_usaddv4hi3
,
11107 SPARC_BUILTIN_FPADDUS16
, v4hi_ftype_v4hi_v4hi
);
11112 def_builtin_const ("__builtin_vis_fpcmple8", CODE_FOR_fpcmple8di_vis
,
11113 SPARC_BUILTIN_FPCMPLE8
, di_ftype_v8qi_v8qi
);
11114 def_builtin_const ("__builtin_vis_fpcmpgt8", CODE_FOR_fpcmpgt8di_vis
,
11115 SPARC_BUILTIN_FPCMPGT8
, di_ftype_v8qi_v8qi
);
11116 def_builtin_const ("__builtin_vis_fpcmpule16", CODE_FOR_fpcmpule16di_vis
,
11117 SPARC_BUILTIN_FPCMPULE16
, di_ftype_v4hi_v4hi
);
11118 def_builtin_const ("__builtin_vis_fpcmpugt16", CODE_FOR_fpcmpugt16di_vis
,
11119 SPARC_BUILTIN_FPCMPUGT16
, di_ftype_v4hi_v4hi
);
11120 def_builtin_const ("__builtin_vis_fpcmpule32", CODE_FOR_fpcmpule32di_vis
,
11121 SPARC_BUILTIN_FPCMPULE32
, di_ftype_v2si_v2si
);
11122 def_builtin_const ("__builtin_vis_fpcmpugt32", CODE_FOR_fpcmpugt32di_vis
,
11123 SPARC_BUILTIN_FPCMPUGT32
, di_ftype_v2si_v2si
);
11127 def_builtin_const ("__builtin_vis_fpcmple8", CODE_FOR_fpcmple8si_vis
,
11128 SPARC_BUILTIN_FPCMPLE8
, si_ftype_v8qi_v8qi
);
11129 def_builtin_const ("__builtin_vis_fpcmpgt8", CODE_FOR_fpcmpgt8si_vis
,
11130 SPARC_BUILTIN_FPCMPGT8
, si_ftype_v8qi_v8qi
);
11131 def_builtin_const ("__builtin_vis_fpcmpule16", CODE_FOR_fpcmpule16si_vis
,
11132 SPARC_BUILTIN_FPCMPULE16
, si_ftype_v4hi_v4hi
);
11133 def_builtin_const ("__builtin_vis_fpcmpugt16", CODE_FOR_fpcmpugt16si_vis
,
11134 SPARC_BUILTIN_FPCMPUGT16
, si_ftype_v4hi_v4hi
);
11135 def_builtin_const ("__builtin_vis_fpcmpule32", CODE_FOR_fpcmpule32si_vis
,
11136 SPARC_BUILTIN_FPCMPULE32
, di_ftype_v2si_v2si
);
11137 def_builtin_const ("__builtin_vis_fpcmpugt32", CODE_FOR_fpcmpugt32si_vis
,
11138 SPARC_BUILTIN_FPCMPUGT32
, di_ftype_v2si_v2si
);
11141 def_builtin_const ("__builtin_vis_fpmax8", CODE_FOR_maxv8qi3
,
11142 SPARC_BUILTIN_FPMAX8
, v8qi_ftype_v8qi_v8qi
);
11143 def_builtin_const ("__builtin_vis_fpmax16", CODE_FOR_maxv4hi3
,
11144 SPARC_BUILTIN_FPMAX16
, v4hi_ftype_v4hi_v4hi
);
11145 def_builtin_const ("__builtin_vis_fpmax32", CODE_FOR_maxv2si3
,
11146 SPARC_BUILTIN_FPMAX32
, v2si_ftype_v2si_v2si
);
11147 def_builtin_const ("__builtin_vis_fpmaxu8", CODE_FOR_maxuv8qi3
,
11148 SPARC_BUILTIN_FPMAXU8
, v8qi_ftype_v8qi_v8qi
);
11149 def_builtin_const ("__builtin_vis_fpmaxu16", CODE_FOR_maxuv4hi3
,
11150 SPARC_BUILTIN_FPMAXU16
, v4hi_ftype_v4hi_v4hi
);
11151 def_builtin_const ("__builtin_vis_fpmaxu32", CODE_FOR_maxuv2si3
,
11152 SPARC_BUILTIN_FPMAXU32
, v2si_ftype_v2si_v2si
);
11153 def_builtin_const ("__builtin_vis_fpmin8", CODE_FOR_minv8qi3
,
11154 SPARC_BUILTIN_FPMIN8
, v8qi_ftype_v8qi_v8qi
);
11155 def_builtin_const ("__builtin_vis_fpmin16", CODE_FOR_minv4hi3
,
11156 SPARC_BUILTIN_FPMIN16
, v4hi_ftype_v4hi_v4hi
);
11157 def_builtin_const ("__builtin_vis_fpmin32", CODE_FOR_minv2si3
,
11158 SPARC_BUILTIN_FPMIN32
, v2si_ftype_v2si_v2si
);
11159 def_builtin_const ("__builtin_vis_fpminu8", CODE_FOR_minuv8qi3
,
11160 SPARC_BUILTIN_FPMINU8
, v8qi_ftype_v8qi_v8qi
);
11161 def_builtin_const ("__builtin_vis_fpminu16", CODE_FOR_minuv4hi3
,
11162 SPARC_BUILTIN_FPMINU16
, v4hi_ftype_v4hi_v4hi
);
11163 def_builtin_const ("__builtin_vis_fpminu32", CODE_FOR_minuv2si3
,
11164 SPARC_BUILTIN_FPMINU32
, v2si_ftype_v2si_v2si
);
11165 def_builtin_const ("__builtin_vis_fpsub8", CODE_FOR_subv8qi3
,
11166 SPARC_BUILTIN_FPSUB8
, v8qi_ftype_v8qi_v8qi
);
11167 def_builtin_const ("__builtin_vis_fpsubs8", CODE_FOR_sssubv8qi3
,
11168 SPARC_BUILTIN_FPSUBS8
, v8qi_ftype_v8qi_v8qi
);
11169 def_builtin_const ("__builtin_vis_fpsubus8", CODE_FOR_ussubv8qi3
,
11170 SPARC_BUILTIN_FPSUBUS8
, v8qi_ftype_v8qi_v8qi
);
11171 def_builtin_const ("__builtin_vis_fpsubus16", CODE_FOR_ussubv4hi3
,
11172 SPARC_BUILTIN_FPSUBUS16
, v4hi_ftype_v4hi_v4hi
);
11177 def_builtin_const ("__builtin_vis_dictunpack8", CODE_FOR_dictunpack8
,
11178 SPARC_BUILTIN_DICTUNPACK8
, v8qi_ftype_df_si
);
11179 def_builtin_const ("__builtin_vis_dictunpack16", CODE_FOR_dictunpack16
,
11180 SPARC_BUILTIN_DICTUNPACK16
, v4hi_ftype_df_si
);
11181 def_builtin_const ("__builtin_vis_dictunpack32", CODE_FOR_dictunpack32
,
11182 SPARC_BUILTIN_DICTUNPACK32
, v2si_ftype_df_si
);
11186 tree di_ftype_v8qi_v8qi_si
= build_function_type_list (intDI_type_node
,
11188 intSI_type_node
, 0);
11189 tree di_ftype_v4hi_v4hi_si
= build_function_type_list (intDI_type_node
,
11191 intSI_type_node
, 0);
11192 tree di_ftype_v2si_v2si_si
= build_function_type_list (intDI_type_node
,
11194 intSI_type_node
, 0);
11196 def_builtin_const ("__builtin_vis_fpcmple8shl", CODE_FOR_fpcmple8dishl
,
11197 SPARC_BUILTIN_FPCMPLE8SHL
, di_ftype_v8qi_v8qi_si
);
11198 def_builtin_const ("__builtin_vis_fpcmpgt8shl", CODE_FOR_fpcmpgt8dishl
,
11199 SPARC_BUILTIN_FPCMPGT8SHL
, di_ftype_v8qi_v8qi_si
);
11200 def_builtin_const ("__builtin_vis_fpcmpeq8shl", CODE_FOR_fpcmpeq8dishl
,
11201 SPARC_BUILTIN_FPCMPEQ8SHL
, di_ftype_v8qi_v8qi_si
);
11202 def_builtin_const ("__builtin_vis_fpcmpne8shl", CODE_FOR_fpcmpne8dishl
,
11203 SPARC_BUILTIN_FPCMPNE8SHL
, di_ftype_v8qi_v8qi_si
);
11205 def_builtin_const ("__builtin_vis_fpcmple16shl", CODE_FOR_fpcmple16dishl
,
11206 SPARC_BUILTIN_FPCMPLE16SHL
, di_ftype_v4hi_v4hi_si
);
11207 def_builtin_const ("__builtin_vis_fpcmpgt16shl", CODE_FOR_fpcmpgt16dishl
,
11208 SPARC_BUILTIN_FPCMPGT16SHL
, di_ftype_v4hi_v4hi_si
);
11209 def_builtin_const ("__builtin_vis_fpcmpeq16shl", CODE_FOR_fpcmpeq16dishl
,
11210 SPARC_BUILTIN_FPCMPEQ16SHL
, di_ftype_v4hi_v4hi_si
);
11211 def_builtin_const ("__builtin_vis_fpcmpne16shl", CODE_FOR_fpcmpne16dishl
,
11212 SPARC_BUILTIN_FPCMPNE16SHL
, di_ftype_v4hi_v4hi_si
);
11214 def_builtin_const ("__builtin_vis_fpcmple32shl", CODE_FOR_fpcmple32dishl
,
11215 SPARC_BUILTIN_FPCMPLE32SHL
, di_ftype_v2si_v2si_si
);
11216 def_builtin_const ("__builtin_vis_fpcmpgt32shl", CODE_FOR_fpcmpgt32dishl
,
11217 SPARC_BUILTIN_FPCMPGT32SHL
, di_ftype_v2si_v2si_si
);
11218 def_builtin_const ("__builtin_vis_fpcmpeq32shl", CODE_FOR_fpcmpeq32dishl
,
11219 SPARC_BUILTIN_FPCMPEQ32SHL
, di_ftype_v2si_v2si_si
);
11220 def_builtin_const ("__builtin_vis_fpcmpne32shl", CODE_FOR_fpcmpne32dishl
,
11221 SPARC_BUILTIN_FPCMPNE32SHL
, di_ftype_v2si_v2si_si
);
11224 def_builtin_const ("__builtin_vis_fpcmpule8shl", CODE_FOR_fpcmpule8dishl
,
11225 SPARC_BUILTIN_FPCMPULE8SHL
, di_ftype_v8qi_v8qi_si
);
11226 def_builtin_const ("__builtin_vis_fpcmpugt8shl", CODE_FOR_fpcmpugt8dishl
,
11227 SPARC_BUILTIN_FPCMPUGT8SHL
, di_ftype_v8qi_v8qi_si
);
11229 def_builtin_const ("__builtin_vis_fpcmpule16shl", CODE_FOR_fpcmpule16dishl
,
11230 SPARC_BUILTIN_FPCMPULE16SHL
, di_ftype_v4hi_v4hi_si
);
11231 def_builtin_const ("__builtin_vis_fpcmpugt16shl", CODE_FOR_fpcmpugt16dishl
,
11232 SPARC_BUILTIN_FPCMPUGT16SHL
, di_ftype_v4hi_v4hi_si
);
11234 def_builtin_const ("__builtin_vis_fpcmpule32shl", CODE_FOR_fpcmpule32dishl
,
11235 SPARC_BUILTIN_FPCMPULE32SHL
, di_ftype_v2si_v2si_si
);
11236 def_builtin_const ("__builtin_vis_fpcmpugt32shl", CODE_FOR_fpcmpugt32dishl
,
11237 SPARC_BUILTIN_FPCMPUGT32SHL
, di_ftype_v2si_v2si_si
);
11239 def_builtin_const ("__builtin_vis_fpcmpde8shl", CODE_FOR_fpcmpde8dishl
,
11240 SPARC_BUILTIN_FPCMPDE8SHL
, di_ftype_v8qi_v8qi_si
);
11241 def_builtin_const ("__builtin_vis_fpcmpde16shl", CODE_FOR_fpcmpde16dishl
,
11242 SPARC_BUILTIN_FPCMPDE16SHL
, di_ftype_v4hi_v4hi_si
);
11243 def_builtin_const ("__builtin_vis_fpcmpde32shl", CODE_FOR_fpcmpde32dishl
,
11244 SPARC_BUILTIN_FPCMPDE32SHL
, di_ftype_v2si_v2si_si
);
11246 def_builtin_const ("__builtin_vis_fpcmpur8shl", CODE_FOR_fpcmpur8dishl
,
11247 SPARC_BUILTIN_FPCMPUR8SHL
, di_ftype_v8qi_v8qi_si
);
11248 def_builtin_const ("__builtin_vis_fpcmpur16shl", CODE_FOR_fpcmpur16dishl
,
11249 SPARC_BUILTIN_FPCMPUR16SHL
, di_ftype_v4hi_v4hi_si
);
11250 def_builtin_const ("__builtin_vis_fpcmpur32shl", CODE_FOR_fpcmpur32dishl
,
11251 SPARC_BUILTIN_FPCMPUR32SHL
, di_ftype_v2si_v2si_si
);
11256 tree si_ftype_v8qi_v8qi_si
= build_function_type_list (intSI_type_node
,
11258 intSI_type_node
, 0);
11259 tree si_ftype_v4hi_v4hi_si
= build_function_type_list (intSI_type_node
,
11261 intSI_type_node
, 0);
11262 tree si_ftype_v2si_v2si_si
= build_function_type_list (intSI_type_node
,
11264 intSI_type_node
, 0);
11266 def_builtin_const ("__builtin_vis_fpcmple8shl", CODE_FOR_fpcmple8sishl
,
11267 SPARC_BUILTIN_FPCMPLE8SHL
, si_ftype_v8qi_v8qi_si
);
11268 def_builtin_const ("__builtin_vis_fpcmpgt8shl", CODE_FOR_fpcmpgt8sishl
,
11269 SPARC_BUILTIN_FPCMPGT8SHL
, si_ftype_v8qi_v8qi_si
);
11270 def_builtin_const ("__builtin_vis_fpcmpeq8shl", CODE_FOR_fpcmpeq8sishl
,
11271 SPARC_BUILTIN_FPCMPEQ8SHL
, si_ftype_v8qi_v8qi_si
);
11272 def_builtin_const ("__builtin_vis_fpcmpne8shl", CODE_FOR_fpcmpne8sishl
,
11273 SPARC_BUILTIN_FPCMPNE8SHL
, si_ftype_v8qi_v8qi_si
);
11275 def_builtin_const ("__builtin_vis_fpcmple16shl", CODE_FOR_fpcmple16sishl
,
11276 SPARC_BUILTIN_FPCMPLE16SHL
, si_ftype_v4hi_v4hi_si
);
11277 def_builtin_const ("__builtin_vis_fpcmpgt16shl", CODE_FOR_fpcmpgt16sishl
,
11278 SPARC_BUILTIN_FPCMPGT16SHL
, si_ftype_v4hi_v4hi_si
);
11279 def_builtin_const ("__builtin_vis_fpcmpeq16shl", CODE_FOR_fpcmpeq16sishl
,
11280 SPARC_BUILTIN_FPCMPEQ16SHL
, si_ftype_v4hi_v4hi_si
);
11281 def_builtin_const ("__builtin_vis_fpcmpne16shl", CODE_FOR_fpcmpne16sishl
,
11282 SPARC_BUILTIN_FPCMPNE16SHL
, si_ftype_v4hi_v4hi_si
);
11284 def_builtin_const ("__builtin_vis_fpcmple32shl", CODE_FOR_fpcmple32sishl
,
11285 SPARC_BUILTIN_FPCMPLE32SHL
, si_ftype_v2si_v2si_si
);
11286 def_builtin_const ("__builtin_vis_fpcmpgt32shl", CODE_FOR_fpcmpgt32sishl
,
11287 SPARC_BUILTIN_FPCMPGT32SHL
, si_ftype_v2si_v2si_si
);
11288 def_builtin_const ("__builtin_vis_fpcmpeq32shl", CODE_FOR_fpcmpeq32sishl
,
11289 SPARC_BUILTIN_FPCMPEQ32SHL
, si_ftype_v2si_v2si_si
);
11290 def_builtin_const ("__builtin_vis_fpcmpne32shl", CODE_FOR_fpcmpne32sishl
,
11291 SPARC_BUILTIN_FPCMPNE32SHL
, si_ftype_v2si_v2si_si
);
11294 def_builtin_const ("__builtin_vis_fpcmpule8shl", CODE_FOR_fpcmpule8sishl
,
11295 SPARC_BUILTIN_FPCMPULE8SHL
, si_ftype_v8qi_v8qi_si
);
11296 def_builtin_const ("__builtin_vis_fpcmpugt8shl", CODE_FOR_fpcmpugt8sishl
,
11297 SPARC_BUILTIN_FPCMPUGT8SHL
, si_ftype_v8qi_v8qi_si
);
11299 def_builtin_const ("__builtin_vis_fpcmpule16shl", CODE_FOR_fpcmpule16sishl
,
11300 SPARC_BUILTIN_FPCMPULE16SHL
, si_ftype_v4hi_v4hi_si
);
11301 def_builtin_const ("__builtin_vis_fpcmpugt16shl", CODE_FOR_fpcmpugt16sishl
,
11302 SPARC_BUILTIN_FPCMPUGT16SHL
, si_ftype_v4hi_v4hi_si
);
11304 def_builtin_const ("__builtin_vis_fpcmpule32shl", CODE_FOR_fpcmpule32sishl
,
11305 SPARC_BUILTIN_FPCMPULE32SHL
, si_ftype_v2si_v2si_si
);
11306 def_builtin_const ("__builtin_vis_fpcmpugt32shl", CODE_FOR_fpcmpugt32sishl
,
11307 SPARC_BUILTIN_FPCMPUGT32SHL
, si_ftype_v2si_v2si_si
);
11309 def_builtin_const ("__builtin_vis_fpcmpde8shl", CODE_FOR_fpcmpde8sishl
,
11310 SPARC_BUILTIN_FPCMPDE8SHL
, si_ftype_v8qi_v8qi_si
);
11311 def_builtin_const ("__builtin_vis_fpcmpde16shl", CODE_FOR_fpcmpde16sishl
,
11312 SPARC_BUILTIN_FPCMPDE16SHL
, si_ftype_v4hi_v4hi_si
);
11313 def_builtin_const ("__builtin_vis_fpcmpde32shl", CODE_FOR_fpcmpde32sishl
,
11314 SPARC_BUILTIN_FPCMPDE32SHL
, si_ftype_v2si_v2si_si
);
11316 def_builtin_const ("__builtin_vis_fpcmpur8shl", CODE_FOR_fpcmpur8sishl
,
11317 SPARC_BUILTIN_FPCMPUR8SHL
, si_ftype_v8qi_v8qi_si
);
11318 def_builtin_const ("__builtin_vis_fpcmpur16shl", CODE_FOR_fpcmpur16sishl
,
11319 SPARC_BUILTIN_FPCMPUR16SHL
, si_ftype_v4hi_v4hi_si
);
11320 def_builtin_const ("__builtin_vis_fpcmpur32shl", CODE_FOR_fpcmpur32sishl
,
11321 SPARC_BUILTIN_FPCMPUR32SHL
, si_ftype_v2si_v2si_si
);
11326 /* Implement TARGET_BUILTIN_DECL hook. */
11329 sparc_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
11331 if (code
>= SPARC_BUILTIN_MAX
)
11332 return error_mark_node
;
11334 return sparc_builtins
[code
];
11337 /* Implemented TARGET_EXPAND_BUILTIN hook. */
11340 sparc_expand_builtin (tree exp
, rtx target
,
11341 rtx subtarget ATTRIBUTE_UNUSED
,
11342 machine_mode tmode ATTRIBUTE_UNUSED
,
11343 int ignore ATTRIBUTE_UNUSED
)
11345 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
11346 enum sparc_builtins code
= (enum sparc_builtins
) DECL_FUNCTION_CODE (fndecl
);
11347 enum insn_code icode
= sparc_builtins_icode
[code
];
11348 bool nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
11349 call_expr_arg_iterator iter
;
11356 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11358 || GET_MODE (target
) != tmode
11359 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11360 op
[0] = gen_reg_rtx (tmode
);
11365 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
11367 const struct insn_operand_data
*insn_op
;
11370 if (arg
== error_mark_node
)
11374 idx
= arg_count
- !nonvoid
;
11375 insn_op
= &insn_data
[icode
].operand
[idx
];
11376 op
[arg_count
] = expand_normal (arg
);
11378 /* Some of the builtins require constant arguments. We check
11380 if ((code
>= SPARC_BUILTIN_FIRST_FPCMPSHL
11381 && code
<= SPARC_BUILTIN_LAST_FPCMPSHL
11383 || (code
>= SPARC_BUILTIN_FIRST_DICTUNPACK
11384 && code
<= SPARC_BUILTIN_LAST_DICTUNPACK
11385 && arg_count
== 2))
11387 if (!check_constant_argument (icode
, idx
, op
[arg_count
]))
11391 if (code
== SPARC_BUILTIN_LDFSR
|| code
== SPARC_BUILTIN_STFSR
)
11393 if (!address_operand (op
[arg_count
], SImode
))
11395 op
[arg_count
] = convert_memory_address (Pmode
, op
[arg_count
]);
11396 op
[arg_count
] = copy_addr_to_reg (op
[arg_count
]);
11398 op
[arg_count
] = gen_rtx_MEM (SImode
, op
[arg_count
]);
11401 else if (insn_op
->mode
== V1DImode
11402 && GET_MODE (op
[arg_count
]) == DImode
)
11403 op
[arg_count
] = gen_lowpart (V1DImode
, op
[arg_count
]);
11405 else if (insn_op
->mode
== V1SImode
11406 && GET_MODE (op
[arg_count
]) == SImode
)
11407 op
[arg_count
] = gen_lowpart (V1SImode
, op
[arg_count
]);
11409 if (! (*insn_data
[icode
].operand
[idx
].predicate
) (op
[arg_count
],
11411 op
[arg_count
] = copy_to_mode_reg (insn_op
->mode
, op
[arg_count
]);
11417 pat
= GEN_FCN (icode
) (op
[0]);
11421 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
11423 pat
= GEN_FCN (icode
) (op
[1]);
11426 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
11429 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
11432 gcc_unreachable ();
11440 return (nonvoid
? op
[0] : const0_rtx
);
11443 /* Return the upper 16 bits of the 8x16 multiplication. */
11446 sparc_vis_mul8x16 (int e8
, int e16
)
11448 return (e8
* e16
+ 128) / 256;
11451 /* Multiply the VECTOR_CSTs CST0 and CST1 as specified by FNCODE and put
11452 the result into the array N_ELTS, whose elements are of INNER_TYPE. */
11455 sparc_handle_vis_mul8x16 (vec
<tree
> *n_elts
, enum sparc_builtins fncode
,
11456 tree inner_type
, tree cst0
, tree cst1
)
11458 unsigned i
, num
= VECTOR_CST_NELTS (cst0
);
11463 case SPARC_BUILTIN_FMUL8X16
:
11464 for (i
= 0; i
< num
; ++i
)
11467 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
11468 TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, i
)));
11469 n_elts
->quick_push (build_int_cst (inner_type
, val
));
11473 case SPARC_BUILTIN_FMUL8X16AU
:
11474 scale
= TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, 0));
11476 for (i
= 0; i
< num
; ++i
)
11479 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
11481 n_elts
->quick_push (build_int_cst (inner_type
, val
));
11485 case SPARC_BUILTIN_FMUL8X16AL
:
11486 scale
= TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, 1));
11488 for (i
= 0; i
< num
; ++i
)
11491 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
11493 n_elts
->quick_push (build_int_cst (inner_type
, val
));
11498 gcc_unreachable ();
11502 /* Implement TARGET_FOLD_BUILTIN hook.
11504 Fold builtin functions for SPARC intrinsics. If IGNORE is true the
11505 result of the function call is ignored. NULL_TREE is returned if the
11506 function could not be folded. */
11509 sparc_fold_builtin (tree fndecl
, int n_args ATTRIBUTE_UNUSED
,
11510 tree
*args
, bool ignore
)
11512 enum sparc_builtins code
= (enum sparc_builtins
) DECL_FUNCTION_CODE (fndecl
);
11513 tree rtype
= TREE_TYPE (TREE_TYPE (fndecl
));
11514 tree arg0
, arg1
, arg2
;
11519 case SPARC_BUILTIN_LDFSR
:
11520 case SPARC_BUILTIN_STFSR
:
11521 case SPARC_BUILTIN_ALIGNADDR
:
11522 case SPARC_BUILTIN_WRGSR
:
11523 case SPARC_BUILTIN_BMASK
:
11524 case SPARC_BUILTIN_CMASK8
:
11525 case SPARC_BUILTIN_CMASK16
:
11526 case SPARC_BUILTIN_CMASK32
:
11530 return build_zero_cst (rtype
);
11535 case SPARC_BUILTIN_FEXPAND
:
11539 if (TREE_CODE (arg0
) == VECTOR_CST
)
11541 tree inner_type
= TREE_TYPE (rtype
);
11544 auto_vec
<tree
, 32> n_elts (VECTOR_CST_NELTS (arg0
));
11545 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
11547 unsigned HOST_WIDE_INT val
11548 = TREE_INT_CST_LOW (VECTOR_CST_ELT (arg0
, i
));
11549 n_elts
.quick_push (build_int_cst (inner_type
, val
<< 4));
11551 return build_vector (rtype
, n_elts
);
11555 case SPARC_BUILTIN_FMUL8X16
:
11556 case SPARC_BUILTIN_FMUL8X16AU
:
11557 case SPARC_BUILTIN_FMUL8X16AL
:
11563 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
11565 tree inner_type
= TREE_TYPE (rtype
);
11566 auto_vec
<tree
, 32> n_elts (VECTOR_CST_NELTS (arg0
));
11567 sparc_handle_vis_mul8x16 (&n_elts
, code
, inner_type
, arg0
, arg1
);
11568 return build_vector (rtype
, n_elts
);
11572 case SPARC_BUILTIN_FPMERGE
:
11578 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
11580 auto_vec
<tree
, 32> n_elts (2 * VECTOR_CST_NELTS (arg0
));
11582 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
11584 n_elts
.quick_push (VECTOR_CST_ELT (arg0
, i
));
11585 n_elts
.quick_push (VECTOR_CST_ELT (arg1
, i
));
11588 return build_vector (rtype
, n_elts
);
11592 case SPARC_BUILTIN_PDIST
:
11593 case SPARC_BUILTIN_PDISTN
:
11598 if (code
== SPARC_BUILTIN_PDIST
)
11604 arg2
= integer_zero_node
;
11606 if (TREE_CODE (arg0
) == VECTOR_CST
11607 && TREE_CODE (arg1
) == VECTOR_CST
11608 && TREE_CODE (arg2
) == INTEGER_CST
)
11610 bool overflow
= false;
11611 widest_int result
= wi::to_widest (arg2
);
11615 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
11617 tree e0
= VECTOR_CST_ELT (arg0
, i
);
11618 tree e1
= VECTOR_CST_ELT (arg1
, i
);
11620 bool neg1_ovf
, neg2_ovf
, add1_ovf
, add2_ovf
;
11622 tmp
= wi::neg (wi::to_widest (e1
), &neg1_ovf
);
11623 tmp
= wi::add (wi::to_widest (e0
), tmp
, SIGNED
, &add1_ovf
);
11624 if (wi::neg_p (tmp
))
11625 tmp
= wi::neg (tmp
, &neg2_ovf
);
11628 result
= wi::add (result
, tmp
, SIGNED
, &add2_ovf
);
11629 overflow
|= neg1_ovf
| neg2_ovf
| add1_ovf
| add2_ovf
;
11632 gcc_assert (!overflow
);
11634 return wide_int_to_tree (rtype
, result
);
11644 /* ??? This duplicates information provided to the compiler by the
11645 ??? scheduler description. Some day, teach genautomata to output
11646 ??? the latencies and then CSE will just use that. */
11649 sparc_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
11650 int opno ATTRIBUTE_UNUSED
,
11651 int *total
, bool speed ATTRIBUTE_UNUSED
)
11653 int code
= GET_CODE (x
);
11654 bool float_mode_p
= FLOAT_MODE_P (mode
);
11665 case CONST_WIDE_INT
:
11667 if (!SPARC_SIMM13_P (CONST_WIDE_INT_ELT (x
, 0)))
11669 if (!SPARC_SIMM13_P (CONST_WIDE_INT_ELT (x
, 1)))
11688 /* If outer-code was a sign or zero extension, a cost
11689 of COSTS_N_INSNS (1) was already added in. This is
11690 why we are subtracting it back out. */
11691 if (outer_code
== ZERO_EXTEND
)
11693 *total
= sparc_costs
->int_zload
- COSTS_N_INSNS (1);
11695 else if (outer_code
== SIGN_EXTEND
)
11697 *total
= sparc_costs
->int_sload
- COSTS_N_INSNS (1);
11699 else if (float_mode_p
)
11701 *total
= sparc_costs
->float_load
;
11705 *total
= sparc_costs
->int_load
;
11713 *total
= sparc_costs
->float_plusminus
;
11715 *total
= COSTS_N_INSNS (1);
11722 gcc_assert (float_mode_p
);
11723 *total
= sparc_costs
->float_mul
;
11726 if (GET_CODE (sub
) == NEG
)
11727 sub
= XEXP (sub
, 0);
11728 *total
+= rtx_cost (sub
, mode
, FMA
, 0, speed
);
11731 if (GET_CODE (sub
) == NEG
)
11732 sub
= XEXP (sub
, 0);
11733 *total
+= rtx_cost (sub
, mode
, FMA
, 2, speed
);
11739 *total
= sparc_costs
->float_mul
;
11740 else if (TARGET_ARCH32
&& !TARGET_HARD_MUL
)
11741 *total
= COSTS_N_INSNS (25);
11747 if (sparc_costs
->int_mul_bit_factor
)
11751 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
11753 unsigned HOST_WIDE_INT value
= INTVAL (XEXP (x
, 1));
11754 for (nbits
= 0; value
!= 0; value
&= value
- 1)
11762 bit_cost
= (nbits
- 3) / sparc_costs
->int_mul_bit_factor
;
11763 bit_cost
= COSTS_N_INSNS (bit_cost
);
11766 if (mode
== DImode
|| !TARGET_HARD_MUL
)
11767 *total
= sparc_costs
->int_mulX
+ bit_cost
;
11769 *total
= sparc_costs
->int_mul
+ bit_cost
;
11776 *total
= COSTS_N_INSNS (1) + sparc_costs
->shift_penalty
;
11785 if (mode
== DFmode
)
11786 *total
= sparc_costs
->float_div_df
;
11788 *total
= sparc_costs
->float_div_sf
;
11792 if (mode
== DImode
)
11793 *total
= sparc_costs
->int_divX
;
11795 *total
= sparc_costs
->int_div
;
11800 if (! float_mode_p
)
11802 *total
= COSTS_N_INSNS (1);
11809 case UNSIGNED_FLOAT
:
11813 case FLOAT_TRUNCATE
:
11814 *total
= sparc_costs
->float_move
;
11818 if (mode
== DFmode
)
11819 *total
= sparc_costs
->float_sqrt_df
;
11821 *total
= sparc_costs
->float_sqrt_sf
;
11826 *total
= sparc_costs
->float_cmp
;
11828 *total
= COSTS_N_INSNS (1);
11833 *total
= sparc_costs
->float_cmove
;
11835 *total
= sparc_costs
->int_cmove
;
11839 /* Handle the NAND vector patterns. */
11840 if (sparc_vector_mode_supported_p (mode
)
11841 && GET_CODE (XEXP (x
, 0)) == NOT
11842 && GET_CODE (XEXP (x
, 1)) == NOT
)
11844 *total
= COSTS_N_INSNS (1);
11855 /* Return true if CLASS is either GENERAL_REGS or I64_REGS. */
11858 general_or_i64_p (reg_class_t rclass
)
11860 return (rclass
== GENERAL_REGS
|| rclass
== I64_REGS
);
11863 /* Implement TARGET_REGISTER_MOVE_COST. */
11866 sparc_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
11867 reg_class_t from
, reg_class_t to
)
11869 bool need_memory
= false;
11871 /* This helps postreload CSE to eliminate redundant comparisons. */
11872 if (from
== NO_REGS
|| to
== NO_REGS
)
11875 if (from
== FPCC_REGS
|| to
== FPCC_REGS
)
11876 need_memory
= true;
11877 else if ((FP_REG_CLASS_P (from
) && general_or_i64_p (to
))
11878 || (general_or_i64_p (from
) && FP_REG_CLASS_P (to
)))
11882 int size
= GET_MODE_SIZE (mode
);
11883 if (size
== 8 || size
== 4)
11885 if (! TARGET_ARCH32
|| size
== 4)
11891 need_memory
= true;
11896 if (sparc_cpu
== PROCESSOR_ULTRASPARC
11897 || sparc_cpu
== PROCESSOR_ULTRASPARC3
11898 || sparc_cpu
== PROCESSOR_NIAGARA
11899 || sparc_cpu
== PROCESSOR_NIAGARA2
11900 || sparc_cpu
== PROCESSOR_NIAGARA3
11901 || sparc_cpu
== PROCESSOR_NIAGARA4
11902 || sparc_cpu
== PROCESSOR_NIAGARA7
11903 || sparc_cpu
== PROCESSOR_M8
)
11912 /* Emit the sequence of insns SEQ while preserving the registers REG and REG2.
11913 This is achieved by means of a manual dynamic stack space allocation in
11914 the current frame. We make the assumption that SEQ doesn't contain any
11915 function calls, with the possible exception of calls to the GOT helper. */
11918 emit_and_preserve (rtx seq
, rtx reg
, rtx reg2
)
11920 /* We must preserve the lowest 16 words for the register save area. */
11921 HOST_WIDE_INT offset
= 16*UNITS_PER_WORD
;
11922 /* We really need only 2 words of fresh stack space. */
11923 HOST_WIDE_INT size
= SPARC_STACK_ALIGN (offset
+ 2*UNITS_PER_WORD
);
11926 = gen_rtx_MEM (word_mode
, plus_constant (Pmode
, stack_pointer_rtx
,
11927 SPARC_STACK_BIAS
+ offset
));
11929 emit_insn (gen_stack_pointer_inc (GEN_INT (-size
)));
11930 emit_insn (gen_rtx_SET (slot
, reg
));
11932 emit_insn (gen_rtx_SET (adjust_address (slot
, word_mode
, UNITS_PER_WORD
),
11936 emit_insn (gen_rtx_SET (reg2
,
11937 adjust_address (slot
, word_mode
, UNITS_PER_WORD
)));
11938 emit_insn (gen_rtx_SET (reg
, slot
));
11939 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
11942 /* Output the assembler code for a thunk function. THUNK_DECL is the
11943 declaration for the thunk function itself, FUNCTION is the decl for
11944 the target function. DELTA is an immediate constant offset to be
11945 added to THIS. If VCALL_OFFSET is nonzero, the word at address
11946 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
11949 sparc_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
11950 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
11953 rtx this_rtx
, funexp
;
11955 unsigned int int_arg_first
;
11957 reload_completed
= 1;
11958 epilogue_completed
= 1;
11960 emit_note (NOTE_INSN_PROLOGUE_END
);
11964 sparc_leaf_function_p
= 1;
11966 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
11968 else if (flag_delayed_branch
)
11970 /* We will emit a regular sibcall below, so we need to instruct
11971 output_sibcall that we are in a leaf function. */
11972 sparc_leaf_function_p
= crtl
->uses_only_leaf_regs
= 1;
11974 /* This will cause final.c to invoke leaf_renumber_regs so we
11975 must behave as if we were in a not-yet-leafified function. */
11976 int_arg_first
= SPARC_INCOMING_INT_ARG_FIRST
;
11980 /* We will emit the sibcall manually below, so we will need to
11981 manually spill non-leaf registers. */
11982 sparc_leaf_function_p
= crtl
->uses_only_leaf_regs
= 0;
11984 /* We really are in a leaf function. */
11985 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
11988 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
11989 returns a structure, the structure return pointer is there instead. */
11991 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
11992 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
+ 1);
11994 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
);
11996 /* Add DELTA. When possible use a plain add, otherwise load it into
11997 a register first. */
12000 rtx delta_rtx
= GEN_INT (delta
);
12002 if (! SPARC_SIMM13_P (delta
))
12004 rtx scratch
= gen_rtx_REG (Pmode
, 1);
12005 emit_move_insn (scratch
, delta_rtx
);
12006 delta_rtx
= scratch
;
12009 /* THIS_RTX += DELTA. */
12010 emit_insn (gen_add2_insn (this_rtx
, delta_rtx
));
12013 /* Add the word at address (*THIS_RTX + VCALL_OFFSET). */
12016 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
12017 rtx scratch
= gen_rtx_REG (Pmode
, 1);
12019 gcc_assert (vcall_offset
< 0);
12021 /* SCRATCH = *THIS_RTX. */
12022 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
, this_rtx
));
12024 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
12025 may not have any available scratch register at this point. */
12026 if (SPARC_SIMM13_P (vcall_offset
))
12028 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
12029 else if (! fixed_regs
[5]
12030 /* The below sequence is made up of at least 2 insns,
12031 while the default method may need only one. */
12032 && vcall_offset
< -8192)
12034 rtx scratch2
= gen_rtx_REG (Pmode
, 5);
12035 emit_move_insn (scratch2
, vcall_offset_rtx
);
12036 vcall_offset_rtx
= scratch2
;
12040 rtx increment
= GEN_INT (-4096);
12042 /* VCALL_OFFSET is a negative number whose typical range can be
12043 estimated as -32768..0 in 32-bit mode. In almost all cases
12044 it is therefore cheaper to emit multiple add insns than
12045 spilling and loading the constant into a register (at least
12047 while (! SPARC_SIMM13_P (vcall_offset
))
12049 emit_insn (gen_add2_insn (scratch
, increment
));
12050 vcall_offset
+= 4096;
12052 vcall_offset_rtx
= GEN_INT (vcall_offset
); /* cannot be 0 */
12055 /* SCRATCH = *(*THIS_RTX + VCALL_OFFSET). */
12056 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
,
12057 gen_rtx_PLUS (Pmode
,
12059 vcall_offset_rtx
)));
12061 /* THIS_RTX += *(*THIS_RTX + VCALL_OFFSET). */
12062 emit_insn (gen_add2_insn (this_rtx
, scratch
));
12065 /* Generate a tail call to the target function. */
12066 if (! TREE_USED (function
))
12068 assemble_external (function
);
12069 TREE_USED (function
) = 1;
12071 funexp
= XEXP (DECL_RTL (function
), 0);
12073 if (flag_delayed_branch
)
12075 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
12076 insn
= emit_call_insn (gen_sibcall (funexp
));
12077 SIBLING_CALL_P (insn
) = 1;
12081 /* The hoops we have to jump through in order to generate a sibcall
12082 without using delay slots... */
12083 rtx spill_reg
, seq
, scratch
= gen_rtx_REG (Pmode
, 1);
12087 spill_reg
= gen_rtx_REG (word_mode
, 15); /* %o7 */
12089 load_got_register (); /* clobbers %o7 */
12090 scratch
= sparc_legitimize_pic_address (funexp
, scratch
);
12091 seq
= get_insns ();
12093 emit_and_preserve (seq
, spill_reg
, pic_offset_table_rtx
);
12095 else if (TARGET_ARCH32
)
12097 emit_insn (gen_rtx_SET (scratch
,
12098 gen_rtx_HIGH (SImode
, funexp
)));
12099 emit_insn (gen_rtx_SET (scratch
,
12100 gen_rtx_LO_SUM (SImode
, scratch
, funexp
)));
12102 else /* TARGET_ARCH64 */
12104 switch (sparc_cmodel
)
12108 /* The destination can serve as a temporary. */
12109 sparc_emit_set_symbolic_const64 (scratch
, funexp
, scratch
);
12114 /* The destination cannot serve as a temporary. */
12115 spill_reg
= gen_rtx_REG (DImode
, 15); /* %o7 */
12117 sparc_emit_set_symbolic_const64 (scratch
, funexp
, spill_reg
);
12118 seq
= get_insns ();
12120 emit_and_preserve (seq
, spill_reg
, 0);
12124 gcc_unreachable ();
12128 emit_jump_insn (gen_indirect_jump (scratch
));
12133 /* Run just enough of rest_of_compilation to get the insns emitted.
12134 There's not really enough bulk here to make other passes such as
12135 instruction scheduling worth while. Note that use_thunk calls
12136 assemble_start_function and assemble_end_function. */
12137 insn
= get_insns ();
12138 shorten_branches (insn
);
12139 final_start_function (insn
, file
, 1);
12140 final (insn
, file
, 1);
12141 final_end_function ();
12143 reload_completed
= 0;
12144 epilogue_completed
= 0;
12147 /* Return true if sparc_output_mi_thunk would be able to output the
12148 assembler code for the thunk function specified by the arguments
12149 it is passed, and false otherwise. */
12151 sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED
,
12152 HOST_WIDE_INT delta ATTRIBUTE_UNUSED
,
12153 HOST_WIDE_INT vcall_offset
,
12154 const_tree function ATTRIBUTE_UNUSED
)
12156 /* Bound the loop used in the default method above. */
12157 return (vcall_offset
>= -32768 || ! fixed_regs
[5]);
12160 /* How to allocate a 'struct machine_function'. */
12162 static struct machine_function
*
12163 sparc_init_machine_status (void)
12165 return ggc_cleared_alloc
<machine_function
> ();
12168 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
12169 We need to emit DTP-relative relocations. */
12172 sparc_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
12177 fputs ("\t.word\t%r_tls_dtpoff32(", file
);
12180 fputs ("\t.xword\t%r_tls_dtpoff64(", file
);
12183 gcc_unreachable ();
12185 output_addr_const (file
, x
);
12189 /* Do whatever processing is required at the end of a file. */
12192 sparc_file_end (void)
12194 /* If we need to emit the special GOT helper function, do so now. */
12195 if (got_helper_rtx
)
12197 const char *name
= XSTR (got_helper_rtx
, 0);
12198 const char *reg_name
= reg_names
[GLOBAL_OFFSET_TABLE_REGNUM
];
12199 #ifdef DWARF2_UNWIND_INFO
12203 if (USE_HIDDEN_LINKONCE
)
12205 tree decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
12206 get_identifier (name
),
12207 build_function_type_list (void_type_node
,
12209 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
12210 NULL_TREE
, void_type_node
);
12211 TREE_PUBLIC (decl
) = 1;
12212 TREE_STATIC (decl
) = 1;
12213 make_decl_one_only (decl
, DECL_ASSEMBLER_NAME (decl
));
12214 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
12215 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
12216 resolve_unique_section (decl
, 0, flag_function_sections
);
12217 allocate_struct_function (decl
, true);
12218 cfun
->is_thunk
= 1;
12219 current_function_decl
= decl
;
12220 init_varasm_status ();
12221 assemble_start_function (decl
, name
);
12225 const int align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
12226 switch_to_section (text_section
);
12228 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
12229 ASM_OUTPUT_LABEL (asm_out_file
, name
);
12232 #ifdef DWARF2_UNWIND_INFO
12233 do_cfi
= dwarf2out_do_cfi_asm ();
12235 fprintf (asm_out_file
, "\t.cfi_startproc\n");
12237 if (flag_delayed_branch
)
12238 fprintf (asm_out_file
, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
12239 reg_name
, reg_name
);
12241 fprintf (asm_out_file
, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
12242 reg_name
, reg_name
);
12243 #ifdef DWARF2_UNWIND_INFO
12245 fprintf (asm_out_file
, "\t.cfi_endproc\n");
12249 if (NEED_INDICATE_EXEC_STACK
)
12250 file_end_indicate_exec_stack ();
12252 #ifdef TARGET_SOLARIS
12253 solaris_file_end ();
12257 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
12258 /* Implement TARGET_MANGLE_TYPE. */
12260 static const char *
12261 sparc_mangle_type (const_tree type
)
12264 && TYPE_MAIN_VARIANT (type
) == long_double_type_node
12265 && TARGET_LONG_DOUBLE_128
)
12268 /* For all other types, use normal C++ mangling. */
12273 /* Expand a membar instruction for various use cases. Both the LOAD_STORE
12274 and BEFORE_AFTER arguments of the form X_Y. They are two-bit masks where
12275 bit 0 indicates that X is true, and bit 1 indicates Y is true. */
12278 sparc_emit_membar_for_model (enum memmodel model
,
12279 int load_store
, int before_after
)
12281 /* Bits for the MEMBAR mmask field. */
12282 const int LoadLoad
= 1;
12283 const int StoreLoad
= 2;
12284 const int LoadStore
= 4;
12285 const int StoreStore
= 8;
12287 int mm
= 0, implied
= 0;
12289 switch (sparc_memory_model
)
12292 /* Sequential Consistency. All memory transactions are immediately
12293 visible in sequential execution order. No barriers needed. */
12294 implied
= LoadLoad
| StoreLoad
| LoadStore
| StoreStore
;
12298 /* Total Store Ordering: all memory transactions with store semantics
12299 are followed by an implied StoreStore. */
12300 implied
|= StoreStore
;
12302 /* If we're not looking for a raw barrer (before+after), then atomic
12303 operations get the benefit of being both load and store. */
12304 if (load_store
== 3 && before_after
== 1)
12305 implied
|= StoreLoad
;
12309 /* Partial Store Ordering: all memory transactions with load semantics
12310 are followed by an implied LoadLoad | LoadStore. */
12311 implied
|= LoadLoad
| LoadStore
;
12313 /* If we're not looking for a raw barrer (before+after), then atomic
12314 operations get the benefit of being both load and store. */
12315 if (load_store
== 3 && before_after
== 2)
12316 implied
|= StoreLoad
| StoreStore
;
12320 /* Relaxed Memory Ordering: no implicit bits. */
12324 gcc_unreachable ();
12327 if (before_after
& 1)
12329 if (is_mm_release (model
) || is_mm_acq_rel (model
)
12330 || is_mm_seq_cst (model
))
12332 if (load_store
& 1)
12333 mm
|= LoadLoad
| StoreLoad
;
12334 if (load_store
& 2)
12335 mm
|= LoadStore
| StoreStore
;
12338 if (before_after
& 2)
12340 if (is_mm_acquire (model
) || is_mm_acq_rel (model
)
12341 || is_mm_seq_cst (model
))
12343 if (load_store
& 1)
12344 mm
|= LoadLoad
| LoadStore
;
12345 if (load_store
& 2)
12346 mm
|= StoreLoad
| StoreStore
;
12350 /* Remove the bits implied by the system memory model. */
12353 /* For raw barriers (before+after), always emit a barrier.
12354 This will become a compile-time barrier if needed. */
12355 if (mm
|| before_after
== 3)
12356 emit_insn (gen_membar (GEN_INT (mm
)));
12359 /* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit
12360 compare and swap on the word containing the byte or half-word. */
12363 sparc_expand_compare_and_swap_12 (rtx bool_result
, rtx result
, rtx mem
,
12364 rtx oldval
, rtx newval
)
12366 rtx addr1
= force_reg (Pmode
, XEXP (mem
, 0));
12367 rtx addr
= gen_reg_rtx (Pmode
);
12368 rtx off
= gen_reg_rtx (SImode
);
12369 rtx oldv
= gen_reg_rtx (SImode
);
12370 rtx newv
= gen_reg_rtx (SImode
);
12371 rtx oldvalue
= gen_reg_rtx (SImode
);
12372 rtx newvalue
= gen_reg_rtx (SImode
);
12373 rtx res
= gen_reg_rtx (SImode
);
12374 rtx resv
= gen_reg_rtx (SImode
);
12375 rtx memsi
, val
, mask
, cc
;
12377 emit_insn (gen_rtx_SET (addr
, gen_rtx_AND (Pmode
, addr1
, GEN_INT (-4))));
12379 if (Pmode
!= SImode
)
12380 addr1
= gen_lowpart (SImode
, addr1
);
12381 emit_insn (gen_rtx_SET (off
, gen_rtx_AND (SImode
, addr1
, GEN_INT (3))));
12383 memsi
= gen_rtx_MEM (SImode
, addr
);
12384 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
12385 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
12387 val
= copy_to_reg (memsi
);
12389 emit_insn (gen_rtx_SET (off
,
12390 gen_rtx_XOR (SImode
, off
,
12391 GEN_INT (GET_MODE (mem
) == QImode
12394 emit_insn (gen_rtx_SET (off
, gen_rtx_ASHIFT (SImode
, off
, GEN_INT (3))));
12396 if (GET_MODE (mem
) == QImode
)
12397 mask
= force_reg (SImode
, GEN_INT (0xff));
12399 mask
= force_reg (SImode
, GEN_INT (0xffff));
12401 emit_insn (gen_rtx_SET (mask
, gen_rtx_ASHIFT (SImode
, mask
, off
)));
12403 emit_insn (gen_rtx_SET (val
,
12404 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
12407 oldval
= gen_lowpart (SImode
, oldval
);
12408 emit_insn (gen_rtx_SET (oldv
, gen_rtx_ASHIFT (SImode
, oldval
, off
)));
12410 newval
= gen_lowpart_common (SImode
, newval
);
12411 emit_insn (gen_rtx_SET (newv
, gen_rtx_ASHIFT (SImode
, newval
, off
)));
12413 emit_insn (gen_rtx_SET (oldv
, gen_rtx_AND (SImode
, oldv
, mask
)));
12415 emit_insn (gen_rtx_SET (newv
, gen_rtx_AND (SImode
, newv
, mask
)));
12417 rtx_code_label
*end_label
= gen_label_rtx ();
12418 rtx_code_label
*loop_label
= gen_label_rtx ();
12419 emit_label (loop_label
);
12421 emit_insn (gen_rtx_SET (oldvalue
, gen_rtx_IOR (SImode
, oldv
, val
)));
12423 emit_insn (gen_rtx_SET (newvalue
, gen_rtx_IOR (SImode
, newv
, val
)));
12425 emit_move_insn (bool_result
, const1_rtx
);
12427 emit_insn (gen_atomic_compare_and_swapsi_1 (res
, memsi
, oldvalue
, newvalue
));
12429 emit_cmp_and_jump_insns (res
, oldvalue
, EQ
, NULL
, SImode
, 0, end_label
);
12431 emit_insn (gen_rtx_SET (resv
,
12432 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
12435 emit_move_insn (bool_result
, const0_rtx
);
12437 cc
= gen_compare_reg_1 (NE
, resv
, val
);
12438 emit_insn (gen_rtx_SET (val
, resv
));
12440 /* Use cbranchcc4 to separate the compare and branch! */
12441 emit_jump_insn (gen_cbranchcc4 (gen_rtx_NE (VOIDmode
, cc
, const0_rtx
),
12442 cc
, const0_rtx
, loop_label
));
12444 emit_label (end_label
);
12446 emit_insn (gen_rtx_SET (res
, gen_rtx_AND (SImode
, res
, mask
)));
12448 emit_insn (gen_rtx_SET (res
, gen_rtx_LSHIFTRT (SImode
, res
, off
)));
12450 emit_move_insn (result
, gen_lowpart (GET_MODE (result
), res
));
12453 /* Expand code to perform a compare-and-swap. */
12456 sparc_expand_compare_and_swap (rtx operands
[])
12458 rtx bval
, retval
, mem
, oldval
, newval
;
12460 enum memmodel model
;
12462 bval
= operands
[0];
12463 retval
= operands
[1];
12465 oldval
= operands
[3];
12466 newval
= operands
[4];
12467 model
= (enum memmodel
) INTVAL (operands
[6]);
12468 mode
= GET_MODE (mem
);
12470 sparc_emit_membar_for_model (model
, 3, 1);
12472 if (reg_overlap_mentioned_p (retval
, oldval
))
12473 oldval
= copy_to_reg (oldval
);
12475 if (mode
== QImode
|| mode
== HImode
)
12476 sparc_expand_compare_and_swap_12 (bval
, retval
, mem
, oldval
, newval
);
12479 rtx (*gen
) (rtx
, rtx
, rtx
, rtx
);
12482 if (mode
== SImode
)
12483 gen
= gen_atomic_compare_and_swapsi_1
;
12485 gen
= gen_atomic_compare_and_swapdi_1
;
12486 emit_insn (gen (retval
, mem
, oldval
, newval
));
12488 x
= emit_store_flag (bval
, EQ
, retval
, oldval
, mode
, 1, 1);
12490 convert_move (bval
, x
, 1);
12493 sparc_emit_membar_for_model (model
, 3, 2);
12497 sparc_expand_vec_perm_bmask (machine_mode vmode
, rtx sel
)
12501 sel
= gen_lowpart (DImode
, sel
);
12505 /* inp = xxxxxxxAxxxxxxxB */
12506 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
12507 NULL_RTX
, 1, OPTAB_DIRECT
);
12508 /* t_1 = ....xxxxxxxAxxx. */
12509 sel
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, sel
),
12510 GEN_INT (3), NULL_RTX
, 1, OPTAB_DIRECT
);
12511 t_1
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_1
),
12512 GEN_INT (0x30000), NULL_RTX
, 1, OPTAB_DIRECT
);
12513 /* sel = .......B */
12514 /* t_1 = ...A.... */
12515 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_1
, sel
, 1, OPTAB_DIRECT
);
12516 /* sel = ...A...B */
12517 sel
= expand_mult (SImode
, sel
, GEN_INT (0x4444), sel
, 1);
12518 /* sel = AAAABBBB * 4 */
12519 t_1
= force_reg (SImode
, GEN_INT (0x01230123));
12520 /* sel = { A*4, A*4+1, A*4+2, ... } */
12524 /* inp = xxxAxxxBxxxCxxxD */
12525 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (8),
12526 NULL_RTX
, 1, OPTAB_DIRECT
);
12527 t_2
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
12528 NULL_RTX
, 1, OPTAB_DIRECT
);
12529 t_3
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (24),
12530 NULL_RTX
, 1, OPTAB_DIRECT
);
12531 /* t_1 = ..xxxAxxxBxxxCxx */
12532 /* t_2 = ....xxxAxxxBxxxC */
12533 /* t_3 = ......xxxAxxxBxx */
12534 sel
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, sel
),
12536 NULL_RTX
, 1, OPTAB_DIRECT
);
12537 t_1
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_1
),
12539 NULL_RTX
, 1, OPTAB_DIRECT
);
12540 t_2
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_2
),
12541 GEN_INT (0x070000),
12542 NULL_RTX
, 1, OPTAB_DIRECT
);
12543 t_3
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_3
),
12544 GEN_INT (0x07000000),
12545 NULL_RTX
, 1, OPTAB_DIRECT
);
12546 /* sel = .......D */
12547 /* t_1 = .....C.. */
12548 /* t_2 = ...B.... */
12549 /* t_3 = .A...... */
12550 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_1
, sel
, 1, OPTAB_DIRECT
);
12551 t_2
= expand_simple_binop (SImode
, IOR
, t_2
, t_3
, t_2
, 1, OPTAB_DIRECT
);
12552 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_2
, sel
, 1, OPTAB_DIRECT
);
12553 /* sel = .A.B.C.D */
12554 sel
= expand_mult (SImode
, sel
, GEN_INT (0x22), sel
, 1);
12555 /* sel = AABBCCDD * 2 */
12556 t_1
= force_reg (SImode
, GEN_INT (0x01010101));
12557 /* sel = { A*2, A*2+1, B*2, B*2+1, ... } */
12561 /* input = xAxBxCxDxExFxGxH */
12562 sel
= expand_simple_binop (DImode
, AND
, sel
,
12563 GEN_INT ((HOST_WIDE_INT
)0x0f0f0f0f << 32
12565 NULL_RTX
, 1, OPTAB_DIRECT
);
12566 /* sel = .A.B.C.D.E.F.G.H */
12567 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (4),
12568 NULL_RTX
, 1, OPTAB_DIRECT
);
12569 /* t_1 = ..A.B.C.D.E.F.G. */
12570 sel
= expand_simple_binop (DImode
, IOR
, sel
, t_1
,
12571 NULL_RTX
, 1, OPTAB_DIRECT
);
12572 /* sel = .AABBCCDDEEFFGGH */
12573 sel
= expand_simple_binop (DImode
, AND
, sel
,
12574 GEN_INT ((HOST_WIDE_INT
)0xff00ff << 32
12576 NULL_RTX
, 1, OPTAB_DIRECT
);
12577 /* sel = ..AB..CD..EF..GH */
12578 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (8),
12579 NULL_RTX
, 1, OPTAB_DIRECT
);
12580 /* t_1 = ....AB..CD..EF.. */
12581 sel
= expand_simple_binop (DImode
, IOR
, sel
, t_1
,
12582 NULL_RTX
, 1, OPTAB_DIRECT
);
12583 /* sel = ..ABABCDCDEFEFGH */
12584 sel
= expand_simple_binop (DImode
, AND
, sel
,
12585 GEN_INT ((HOST_WIDE_INT
)0xffff << 32 | 0xffff),
12586 NULL_RTX
, 1, OPTAB_DIRECT
);
12587 /* sel = ....ABCD....EFGH */
12588 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
12589 NULL_RTX
, 1, OPTAB_DIRECT
);
12590 /* t_1 = ........ABCD.... */
12591 sel
= gen_lowpart (SImode
, sel
);
12592 t_1
= gen_lowpart (SImode
, t_1
);
12596 gcc_unreachable ();
12599 /* Always perform the final addition/merge within the bmask insn. */
12600 emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode
), sel
, t_1
));
12603 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
12606 sparc_frame_pointer_required (void)
12608 /* If the stack pointer is dynamically modified in the function, it cannot
12609 serve as the frame pointer. */
12610 if (cfun
->calls_alloca
)
12613 /* If the function receives nonlocal gotos, it needs to save the frame
12614 pointer in the nonlocal_goto_save_area object. */
12615 if (cfun
->has_nonlocal_label
)
12618 /* In flat mode, that's it. */
12622 /* Otherwise, the frame pointer is required if the function isn't leaf, but
12623 we cannot use sparc_leaf_function_p since it hasn't been computed yet. */
12624 return !(optimize
> 0 && crtl
->is_leaf
&& only_leaf_regs_used ());
12627 /* The way this is structured, we can't eliminate SFP in favor of SP
12628 if the frame pointer is required: we want to use the SFP->HFP elimination
12629 in that case. But the test in update_eliminables doesn't know we are
12630 assuming below that we only do the former elimination. */
12633 sparc_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
12635 return to
== HARD_FRAME_POINTER_REGNUM
|| !sparc_frame_pointer_required ();
12638 /* Return the hard frame pointer directly to bypass the stack bias. */
12641 sparc_builtin_setjmp_frame_value (void)
12643 return hard_frame_pointer_rtx
;
12646 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
12647 they won't be allocated. */
12650 sparc_conditional_register_usage (void)
12652 if (PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
12654 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
12655 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
12657 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */
12658 /* then honor it. */
12659 if (TARGET_ARCH32
&& fixed_regs
[5])
12661 else if (TARGET_ARCH64
&& fixed_regs
[5] == 2)
12666 for (regno
= SPARC_FIRST_V9_FP_REG
;
12667 regno
<= SPARC_LAST_V9_FP_REG
;
12669 fixed_regs
[regno
] = 1;
12670 /* %fcc0 is used by v8 and v9. */
12671 for (regno
= SPARC_FIRST_V9_FCC_REG
+ 1;
12672 regno
<= SPARC_LAST_V9_FCC_REG
;
12674 fixed_regs
[regno
] = 1;
12679 for (regno
= 32; regno
< SPARC_LAST_V9_FCC_REG
; regno
++)
12680 fixed_regs
[regno
] = 1;
12682 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */
12683 /* then honor it. Likewise with g3 and g4. */
12684 if (fixed_regs
[2] == 2)
12685 fixed_regs
[2] = ! TARGET_APP_REGS
;
12686 if (fixed_regs
[3] == 2)
12687 fixed_regs
[3] = ! TARGET_APP_REGS
;
12688 if (TARGET_ARCH32
&& fixed_regs
[4] == 2)
12689 fixed_regs
[4] = ! TARGET_APP_REGS
;
12690 else if (TARGET_CM_EMBMEDANY
)
12692 else if (fixed_regs
[4] == 2)
12697 /* Disable leaf functions. */
12698 memset (sparc_leaf_regs
, 0, FIRST_PSEUDO_REGISTER
);
12699 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
12700 leaf_reg_remap
[regno
] = regno
;
12703 global_regs
[SPARC_GSR_REG
] = 1;
12706 /* Implement TARGET_PREFERRED_RELOAD_CLASS:
12708 - We can't load constants into FP registers.
12709 - We can't load FP constants into integer registers when soft-float,
12710 because there is no soft-float pattern with a r/F constraint.
12711 - We can't load FP constants into integer registers for TFmode unless
12712 it is 0.0L, because there is no movtf pattern with a r/F constraint.
12713 - Try and reload integer constants (symbolic or otherwise) back into
12714 registers directly, rather than having them dumped to memory. */
12717 sparc_preferred_reload_class (rtx x
, reg_class_t rclass
)
12719 machine_mode mode
= GET_MODE (x
);
12720 if (CONSTANT_P (x
))
12722 if (FP_REG_CLASS_P (rclass
)
12723 || rclass
== GENERAL_OR_FP_REGS
12724 || rclass
== GENERAL_OR_EXTRA_FP_REGS
12725 || (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& ! TARGET_FPU
)
12726 || (mode
== TFmode
&& ! const_zero_operand (x
, mode
)))
12729 if (GET_MODE_CLASS (mode
) == MODE_INT
)
12730 return GENERAL_REGS
;
12732 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
12734 if (! FP_REG_CLASS_P (rclass
)
12735 || !(const_zero_operand (x
, mode
)
12736 || const_all_ones_operand (x
, mode
)))
12743 && (rclass
== EXTRA_FP_REGS
12744 || rclass
== GENERAL_OR_EXTRA_FP_REGS
))
12746 int regno
= true_regnum (x
);
12748 if (SPARC_INT_REG_P (regno
))
12749 return (rclass
== EXTRA_FP_REGS
12750 ? FP_REGS
: GENERAL_OR_FP_REGS
);
12756 /* Return true if we use LRA instead of reload pass. */
12764 /* Output a wide multiply instruction in V8+ mode. INSN is the instruction,
12765 OPERANDS are its operands and OPCODE is the mnemonic to be used. */
12768 output_v8plus_mult (rtx_insn
*insn
, rtx
*operands
, const char *opcode
)
12772 gcc_assert (! TARGET_ARCH64
);
12774 if (sparc_check_64 (operands
[1], insn
) <= 0)
12775 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
12776 if (which_alternative
== 1)
12777 output_asm_insn ("sllx\t%H1, 32, %H1", operands
);
12778 if (GET_CODE (operands
[2]) == CONST_INT
)
12780 if (which_alternative
== 1)
12782 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
12783 sprintf (mulstr
, "%s\t%%H1, %%2, %%L0", opcode
);
12784 output_asm_insn (mulstr
, operands
);
12785 return "srlx\t%L0, 32, %H0";
12789 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
12790 output_asm_insn ("or\t%L1, %3, %3", operands
);
12791 sprintf (mulstr
, "%s\t%%3, %%2, %%3", opcode
);
12792 output_asm_insn (mulstr
, operands
);
12793 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
12794 return "mov\t%3, %L0";
12797 else if (rtx_equal_p (operands
[1], operands
[2]))
12799 if (which_alternative
== 1)
12801 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
12802 sprintf (mulstr
, "%s\t%%H1, %%H1, %%L0", opcode
);
12803 output_asm_insn (mulstr
, operands
);
12804 return "srlx\t%L0, 32, %H0";
12808 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
12809 output_asm_insn ("or\t%L1, %3, %3", operands
);
12810 sprintf (mulstr
, "%s\t%%3, %%3, %%3", opcode
);
12811 output_asm_insn (mulstr
, operands
);
12812 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
12813 return "mov\t%3, %L0";
12816 if (sparc_check_64 (operands
[2], insn
) <= 0)
12817 output_asm_insn ("srl\t%L2, 0, %L2", operands
);
12818 if (which_alternative
== 1)
12820 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
12821 output_asm_insn ("sllx\t%H2, 32, %L1", operands
);
12822 output_asm_insn ("or\t%L2, %L1, %L1", operands
);
12823 sprintf (mulstr
, "%s\t%%H1, %%L1, %%L0", opcode
);
12824 output_asm_insn (mulstr
, operands
);
12825 return "srlx\t%L0, 32, %H0";
12829 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
12830 output_asm_insn ("sllx\t%H2, 32, %4", operands
);
12831 output_asm_insn ("or\t%L1, %3, %3", operands
);
12832 output_asm_insn ("or\t%L2, %4, %4", operands
);
12833 sprintf (mulstr
, "%s\t%%3, %%4, %%3", opcode
);
12834 output_asm_insn (mulstr
, operands
);
12835 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
12836 return "mov\t%3, %L0";
12840 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
12841 all fields of TARGET to ELT by means of VIS2 BSHUFFLE insn. MODE
12842 and INNER_MODE are the modes describing TARGET. */
12845 vector_init_bshuffle (rtx target
, rtx elt
, machine_mode mode
,
12846 machine_mode inner_mode
)
12848 rtx t1
, final_insn
, sel
;
12851 t1
= gen_reg_rtx (mode
);
12853 elt
= convert_modes (SImode
, inner_mode
, elt
, true);
12854 emit_move_insn (gen_lowpart(SImode
, t1
), elt
);
12859 final_insn
= gen_bshufflev2si_vis (target
, t1
, t1
);
12860 bmask
= 0x45674567;
12863 final_insn
= gen_bshufflev4hi_vis (target
, t1
, t1
);
12864 bmask
= 0x67676767;
12867 final_insn
= gen_bshufflev8qi_vis (target
, t1
, t1
);
12868 bmask
= 0x77777777;
12871 gcc_unreachable ();
12874 sel
= force_reg (SImode
, GEN_INT (bmask
));
12875 emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode
), sel
, const0_rtx
));
12876 emit_insn (final_insn
);
12879 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
12880 all fields of TARGET to ELT in V8QI by means of VIS FPMERGE insn. */
12883 vector_init_fpmerge (rtx target
, rtx elt
)
12885 rtx t1
, t2
, t2_low
, t3
, t3_low
;
12887 t1
= gen_reg_rtx (V4QImode
);
12888 elt
= convert_modes (SImode
, QImode
, elt
, true);
12889 emit_move_insn (gen_lowpart (SImode
, t1
), elt
);
12891 t2
= gen_reg_rtx (V8QImode
);
12892 t2_low
= gen_lowpart (V4QImode
, t2
);
12893 emit_insn (gen_fpmerge_vis (t2
, t1
, t1
));
12895 t3
= gen_reg_rtx (V8QImode
);
12896 t3_low
= gen_lowpart (V4QImode
, t3
);
12897 emit_insn (gen_fpmerge_vis (t3
, t2_low
, t2_low
));
12899 emit_insn (gen_fpmerge_vis (target
, t3_low
, t3_low
));
12902 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
12903 all fields of TARGET to ELT in V4HI by means of VIS FALIGNDATA insn. */
12906 vector_init_faligndata (rtx target
, rtx elt
)
12908 rtx t1
= gen_reg_rtx (V4HImode
);
12911 elt
= convert_modes (SImode
, HImode
, elt
, true);
12912 emit_move_insn (gen_lowpart (SImode
, t1
), elt
);
12914 emit_insn (gen_alignaddrsi_vis (gen_reg_rtx (SImode
),
12915 force_reg (SImode
, GEN_INT (6)),
12918 for (i
= 0; i
< 4; i
++)
12919 emit_insn (gen_faligndatav4hi_vis (target
, t1
, target
));
12922 /* Emit code to initialize TARGET to values for individual fields VALS. */
12925 sparc_expand_vector_init (rtx target
, rtx vals
)
12927 const machine_mode mode
= GET_MODE (target
);
12928 const machine_mode inner_mode
= GET_MODE_INNER (mode
);
12929 const int n_elts
= GET_MODE_NUNITS (mode
);
12931 bool all_same
= true;
12934 for (i
= 0; i
< n_elts
; i
++)
12936 rtx x
= XVECEXP (vals
, 0, i
);
12937 if (!(CONST_SCALAR_INT_P (x
) || CONST_DOUBLE_P (x
) || CONST_FIXED_P (x
)))
12940 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
12946 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
12950 if (GET_MODE_SIZE (inner_mode
) == GET_MODE_SIZE (mode
))
12952 if (GET_MODE_SIZE (inner_mode
) == 4)
12954 emit_move_insn (gen_lowpart (SImode
, target
),
12955 gen_lowpart (SImode
, XVECEXP (vals
, 0, 0)));
12958 else if (GET_MODE_SIZE (inner_mode
) == 8)
12960 emit_move_insn (gen_lowpart (DImode
, target
),
12961 gen_lowpart (DImode
, XVECEXP (vals
, 0, 0)));
12965 else if (GET_MODE_SIZE (inner_mode
) == GET_MODE_SIZE (word_mode
)
12966 && GET_MODE_SIZE (mode
) == 2 * GET_MODE_SIZE (word_mode
))
12968 emit_move_insn (gen_highpart (word_mode
, target
),
12969 gen_lowpart (word_mode
, XVECEXP (vals
, 0, 0)));
12970 emit_move_insn (gen_lowpart (word_mode
, target
),
12971 gen_lowpart (word_mode
, XVECEXP (vals
, 0, 1)));
12975 if (all_same
&& GET_MODE_SIZE (mode
) == 8)
12979 vector_init_bshuffle (target
, XVECEXP (vals
, 0, 0), mode
, inner_mode
);
12982 if (mode
== V8QImode
)
12984 vector_init_fpmerge (target
, XVECEXP (vals
, 0, 0));
12987 if (mode
== V4HImode
)
12989 vector_init_faligndata (target
, XVECEXP (vals
, 0, 0));
12994 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
12995 for (i
= 0; i
< n_elts
; i
++)
12996 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
12997 i
* GET_MODE_SIZE (inner_mode
)),
12998 XVECEXP (vals
, 0, i
));
12999 emit_move_insn (target
, mem
);
13002 /* Implement TARGET_SECONDARY_RELOAD. */
13005 sparc_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
13006 machine_mode mode
, secondary_reload_info
*sri
)
13008 enum reg_class rclass
= (enum reg_class
) rclass_i
;
13010 sri
->icode
= CODE_FOR_nothing
;
13011 sri
->extra_cost
= 0;
13013 /* We need a temporary when loading/storing a HImode/QImode value
13014 between memory and the FPU registers. This can happen when combine puts
13015 a paradoxical subreg in a float/fix conversion insn. */
13016 if (FP_REG_CLASS_P (rclass
)
13017 && (mode
== HImode
|| mode
== QImode
)
13018 && (GET_CODE (x
) == MEM
13019 || ((GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
13020 && true_regnum (x
) == -1)))
13021 return GENERAL_REGS
;
13023 /* On 32-bit we need a temporary when loading/storing a DFmode value
13024 between unaligned memory and the upper FPU registers. */
13026 && rclass
== EXTRA_FP_REGS
13028 && GET_CODE (x
) == MEM
13029 && ! mem_min_alignment (x
, 8))
13032 if (((TARGET_CM_MEDANY
13033 && symbolic_operand (x
, mode
))
13034 || (TARGET_CM_EMBMEDANY
13035 && text_segment_operand (x
, mode
)))
13039 sri
->icode
= direct_optab_handler (reload_in_optab
, mode
);
13041 sri
->icode
= direct_optab_handler (reload_out_optab
, mode
);
13045 if (TARGET_VIS3
&& TARGET_ARCH32
)
13047 int regno
= true_regnum (x
);
13049 /* When using VIS3 fp<-->int register moves, on 32-bit we have
13050 to move 8-byte values in 4-byte pieces. This only works via
13051 FP_REGS, and not via EXTRA_FP_REGS. Therefore if we try to
13052 move between EXTRA_FP_REGS and GENERAL_REGS, we will need
13053 an FP_REGS intermediate move. */
13054 if ((rclass
== EXTRA_FP_REGS
&& SPARC_INT_REG_P (regno
))
13055 || ((general_or_i64_p (rclass
)
13056 || rclass
== GENERAL_OR_FP_REGS
)
13057 && SPARC_FP_REG_P (regno
)))
13059 sri
->extra_cost
= 2;
13067 /* Implement TARGET_SECONDARY_MEMORY_NEEDED.
13069 On SPARC when not VIS3 it is not possible to directly move data
13070 between GENERAL_REGS and FP_REGS. */
13073 sparc_secondary_memory_needed (machine_mode mode
, reg_class_t class1
,
13074 reg_class_t class2
)
13076 return ((FP_REG_CLASS_P (class1
) != FP_REG_CLASS_P (class2
))
13078 || GET_MODE_SIZE (mode
) > 8
13079 || GET_MODE_SIZE (mode
) < 4));
13082 /* Implement TARGET_SECONDARY_MEMORY_NEEDED_MODE.
13084 get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9
13085 because the movsi and movsf patterns don't handle r/f moves.
13086 For v8 we copy the default definition. */
13088 static machine_mode
13089 sparc_secondary_memory_needed_mode (machine_mode mode
)
13093 if (GET_MODE_BITSIZE (mode
) < 32)
13094 return mode_for_size (32, GET_MODE_CLASS (mode
), 0).require ();
13099 if (GET_MODE_BITSIZE (mode
) < BITS_PER_WORD
)
13100 return mode_for_size (BITS_PER_WORD
,
13101 GET_MODE_CLASS (mode
), 0).require ();
13106 /* Emit code to conditionally move either OPERANDS[2] or OPERANDS[3] into
13107 OPERANDS[0] in MODE. OPERANDS[1] is the operator of the condition. */
13110 sparc_expand_conditional_move (machine_mode mode
, rtx
*operands
)
13112 enum rtx_code rc
= GET_CODE (operands
[1]);
13113 machine_mode cmp_mode
;
13114 rtx cc_reg
, dst
, cmp
;
13117 if (GET_MODE (XEXP (cmp
, 0)) == DImode
&& !TARGET_ARCH64
)
13120 if (GET_MODE (XEXP (cmp
, 0)) == TFmode
&& !TARGET_HARD_QUAD
)
13121 cmp
= sparc_emit_float_lib_cmp (XEXP (cmp
, 0), XEXP (cmp
, 1), rc
);
13123 cmp_mode
= GET_MODE (XEXP (cmp
, 0));
13124 rc
= GET_CODE (cmp
);
13127 if (! rtx_equal_p (operands
[2], dst
)
13128 && ! rtx_equal_p (operands
[3], dst
))
13130 if (reg_overlap_mentioned_p (dst
, cmp
))
13131 dst
= gen_reg_rtx (mode
);
13133 emit_move_insn (dst
, operands
[3]);
13135 else if (operands
[2] == dst
)
13137 operands
[2] = operands
[3];
13139 if (GET_MODE_CLASS (cmp_mode
) == MODE_FLOAT
)
13140 rc
= reverse_condition_maybe_unordered (rc
);
13142 rc
= reverse_condition (rc
);
13145 if (XEXP (cmp
, 1) == const0_rtx
13146 && GET_CODE (XEXP (cmp
, 0)) == REG
13147 && cmp_mode
== DImode
13148 && v9_regcmp_p (rc
))
13149 cc_reg
= XEXP (cmp
, 0);
13151 cc_reg
= gen_compare_reg_1 (rc
, XEXP (cmp
, 0), XEXP (cmp
, 1));
13153 cmp
= gen_rtx_fmt_ee (rc
, GET_MODE (cc_reg
), cc_reg
, const0_rtx
);
13155 emit_insn (gen_rtx_SET (dst
,
13156 gen_rtx_IF_THEN_ELSE (mode
, cmp
, operands
[2], dst
)));
13158 if (dst
!= operands
[0])
13159 emit_move_insn (operands
[0], dst
);
13164 /* Emit code to conditionally move a combination of OPERANDS[1] and OPERANDS[2]
13165 into OPERANDS[0] in MODE, depending on the outcome of the comparison of
13166 OPERANDS[4] and OPERANDS[5]. OPERANDS[3] is the operator of the condition.
13167 FCODE is the machine code to be used for OPERANDS[3] and CCODE the machine
13168 code to be used for the condition mask. */
13171 sparc_expand_vcond (machine_mode mode
, rtx
*operands
, int ccode
, int fcode
)
13173 rtx mask
, cop0
, cop1
, fcmp
, cmask
, bshuf
, gsr
;
13174 enum rtx_code code
= GET_CODE (operands
[3]);
13176 mask
= gen_reg_rtx (Pmode
);
13177 cop0
= operands
[4];
13178 cop1
= operands
[5];
13179 if (code
== LT
|| code
== GE
)
13183 code
= swap_condition (code
);
13184 t
= cop0
; cop0
= cop1
; cop1
= t
;
13187 gsr
= gen_rtx_REG (DImode
, SPARC_GSR_REG
);
13189 fcmp
= gen_rtx_UNSPEC (Pmode
,
13190 gen_rtvec (1, gen_rtx_fmt_ee (code
, mode
, cop0
, cop1
)),
13193 cmask
= gen_rtx_UNSPEC (DImode
,
13194 gen_rtvec (2, mask
, gsr
),
13197 bshuf
= gen_rtx_UNSPEC (mode
,
13198 gen_rtvec (3, operands
[1], operands
[2], gsr
),
13201 emit_insn (gen_rtx_SET (mask
, fcmp
));
13202 emit_insn (gen_rtx_SET (gsr
, cmask
));
13204 emit_insn (gen_rtx_SET (operands
[0], bshuf
));
13207 /* On sparc, any mode which naturally allocates into the float
13208 registers should return 4 here. */
13211 sparc_regmode_natural_size (machine_mode mode
)
13213 int size
= UNITS_PER_WORD
;
13217 enum mode_class mclass
= GET_MODE_CLASS (mode
);
13219 if (mclass
== MODE_FLOAT
|| mclass
== MODE_VECTOR_INT
)
13226 /* Implement TARGET_HARD_REGNO_NREGS.
13228 On SPARC, ordinary registers hold 32 bits worth; this means both
13229 integer and floating point registers. On v9, integer regs hold 64
13230 bits worth; floating point regs hold 32 bits worth (this includes the
13231 new fp regs as even the odd ones are included in the hard register
13234 static unsigned int
13235 sparc_hard_regno_nregs (unsigned int regno
, machine_mode mode
)
13237 if (regno
== SPARC_GSR_REG
)
13241 if (SPARC_INT_REG_P (regno
) || regno
== FRAME_POINTER_REGNUM
)
13242 return CEIL (GET_MODE_SIZE (mode
), UNITS_PER_WORD
);
13243 return CEIL (GET_MODE_SIZE (mode
), 4);
13245 return CEIL (GET_MODE_SIZE (mode
), UNITS_PER_WORD
);
13248 /* Implement TARGET_HARD_REGNO_MODE_OK.
13250 ??? Because of the funny way we pass parameters we should allow certain
13251 ??? types of float/complex values to be in integer registers during
13252 ??? RTL generation. This only matters on arch32. */
13255 sparc_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
13257 return (hard_regno_mode_classes
[regno
] & sparc_mode_class
[mode
]) != 0;
13260 /* Implement TARGET_MODES_TIEABLE_P.
13262 For V9 we have to deal with the fact that only the lower 32 floating
13263 point registers are 32-bit addressable. */
13266 sparc_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
13268 enum mode_class mclass1
, mclass2
;
13269 unsigned short size1
, size2
;
13271 if (mode1
== mode2
)
13274 mclass1
= GET_MODE_CLASS (mode1
);
13275 mclass2
= GET_MODE_CLASS (mode2
);
13276 if (mclass1
!= mclass2
)
13282 /* Classes are the same and we are V9 so we have to deal with upper
13283 vs. lower floating point registers. If one of the modes is a
13284 4-byte mode, and the other is not, we have to mark them as not
13285 tieable because only the lower 32 floating point register are
13286 addressable 32-bits at a time.
13288 We can't just test explicitly for SFmode, otherwise we won't
13289 cover the vector mode cases properly. */
13291 if (mclass1
!= MODE_FLOAT
&& mclass1
!= MODE_VECTOR_INT
)
13294 size1
= GET_MODE_SIZE (mode1
);
13295 size2
= GET_MODE_SIZE (mode2
);
13296 if ((size1
> 4 && size2
== 4)
13297 || (size2
> 4 && size1
== 4))
13303 /* Implement TARGET_CSTORE_MODE. */
13305 static scalar_int_mode
13306 sparc_cstore_mode (enum insn_code icode ATTRIBUTE_UNUSED
)
13308 return (TARGET_ARCH64
? DImode
: SImode
);
13311 /* Return the compound expression made of T1 and T2. */
13314 compound_expr (tree t1
, tree t2
)
13316 return build2 (COMPOUND_EXPR
, void_type_node
, t1
, t2
);
13319 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
13322 sparc_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
13327 const unsigned HOST_WIDE_INT accrued_exception_mask
= 0x1f << 5;
13328 const unsigned HOST_WIDE_INT trap_enable_mask
= 0x1f << 23;
13330 /* We generate the equivalent of feholdexcept (&fenv_var):
13332 unsigned int fenv_var;
13333 __builtin_store_fsr (&fenv_var);
13335 unsigned int tmp1_var;
13336 tmp1_var = fenv_var & ~(accrued_exception_mask | trap_enable_mask);
13338 __builtin_load_fsr (&tmp1_var); */
13340 tree fenv_var
= create_tmp_var_raw (unsigned_type_node
);
13341 TREE_ADDRESSABLE (fenv_var
) = 1;
13342 tree fenv_addr
= build_fold_addr_expr (fenv_var
);
13343 tree stfsr
= sparc_builtins
[SPARC_BUILTIN_STFSR
];
13345 = build4 (TARGET_EXPR
, unsigned_type_node
, fenv_var
,
13346 build_call_expr (stfsr
, 1, fenv_addr
), NULL_TREE
, NULL_TREE
);
13348 tree tmp1_var
= create_tmp_var_raw (unsigned_type_node
);
13349 TREE_ADDRESSABLE (tmp1_var
) = 1;
13350 tree masked_fenv_var
13351 = build2 (BIT_AND_EXPR
, unsigned_type_node
, fenv_var
,
13352 build_int_cst (unsigned_type_node
,
13353 ~(accrued_exception_mask
| trap_enable_mask
)));
13355 = build4 (TARGET_EXPR
, unsigned_type_node
, tmp1_var
, masked_fenv_var
,
13356 NULL_TREE
, NULL_TREE
);
13358 tree tmp1_addr
= build_fold_addr_expr (tmp1_var
);
13359 tree ldfsr
= sparc_builtins
[SPARC_BUILTIN_LDFSR
];
13360 tree hold_ldfsr
= build_call_expr (ldfsr
, 1, tmp1_addr
);
13362 *hold
= compound_expr (compound_expr (hold_stfsr
, hold_mask
), hold_ldfsr
);
13364 /* We reload the value of tmp1_var to clear the exceptions:
13366 __builtin_load_fsr (&tmp1_var); */
13368 *clear
= build_call_expr (ldfsr
, 1, tmp1_addr
);
13370 /* We generate the equivalent of feupdateenv (&fenv_var):
13372 unsigned int tmp2_var;
13373 __builtin_store_fsr (&tmp2_var);
13375 __builtin_load_fsr (&fenv_var);
13377 if (SPARC_LOW_FE_EXCEPT_VALUES)
13379 __atomic_feraiseexcept ((int) tmp2_var); */
13381 tree tmp2_var
= create_tmp_var_raw (unsigned_type_node
);
13382 TREE_ADDRESSABLE (tmp2_var
) = 1;
13383 tree tmp2_addr
= build_fold_addr_expr (tmp2_var
);
13385 = build4 (TARGET_EXPR
, unsigned_type_node
, tmp2_var
,
13386 build_call_expr (stfsr
, 1, tmp2_addr
), NULL_TREE
, NULL_TREE
);
13388 tree update_ldfsr
= build_call_expr (ldfsr
, 1, fenv_addr
);
13390 tree atomic_feraiseexcept
13391 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT
);
13393 = build_call_expr (atomic_feraiseexcept
, 1,
13394 fold_convert (integer_type_node
, tmp2_var
));
13396 if (SPARC_LOW_FE_EXCEPT_VALUES
)
13398 tree shifted_tmp2_var
13399 = build2 (RSHIFT_EXPR
, unsigned_type_node
, tmp2_var
,
13400 build_int_cst (unsigned_type_node
, 5));
13402 = build2 (MODIFY_EXPR
, void_type_node
, tmp2_var
, shifted_tmp2_var
);
13403 update_call
= compound_expr (update_shift
, update_call
);
13407 = compound_expr (compound_expr (update_stfsr
, update_ldfsr
), update_call
);
13410 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. Borrowed from the PA port.
13412 SImode loads to floating-point registers are not zero-extended.
13413 The definition for LOAD_EXTEND_OP specifies that integer loads
13414 narrower than BITS_PER_WORD will be zero-extended. As a result,
13415 we inhibit changes from SImode unless they are to a mode that is
13418 Likewise for SFmode, since word-mode paradoxical subregs are
13419 problematic on big-endian architectures. */
13422 sparc_can_change_mode_class (machine_mode from
, machine_mode to
,
13423 reg_class_t rclass
)
13426 && GET_MODE_SIZE (from
) == 4
13427 && GET_MODE_SIZE (to
) != 4)
13428 return !reg_classes_intersect_p (rclass
, FP_REGS
);
13432 #include "gt-sparc.h"