1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987-2019 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
4 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
23 #define IN_TARGET_CODE 1
27 #include "coretypes.h"
36 #include "stringpool.h"
43 #include "diagnostic-core.h"
45 #include "fold-const.h"
46 #include "stor-layout.h"
50 #include "insn-attr.h"
55 #include "common/common-target.h"
57 #include "langhooks.h"
60 #include "tree-pass.h"
63 #include "tree-vector-builder.h"
65 /* This file should be included last. */
66 #include "target-def.h"
70 struct processor_costs
{
74 /* Integer signed load */
77 /* Integer zeroed load */
83 /* fmov, fneg, fabs */
87 const int float_plusminus
;
93 const int float_cmove
;
99 const int float_div_sf
;
102 const int float_div_df
;
105 const int float_sqrt_sf
;
108 const int float_sqrt_df
;
116 /* integer multiply cost for each bit set past the most
117 significant 3, so the formula for multiply cost becomes:
120 highest_bit = highest_clear_bit(rs1);
122 highest_bit = highest_set_bit(rs1);
125 cost = int_mul{,X} + ((highest_bit - 3) / int_mul_bit_factor);
127 A value of zero indicates that the multiply costs is fixed,
129 const int int_mul_bit_factor
;
140 /* penalty for shifts, due to scheduling rules etc. */
141 const int shift_penalty
;
143 /* cost of a (predictable) branch. */
144 const int branch_cost
;
148 struct processor_costs cypress_costs
= {
149 COSTS_N_INSNS (2), /* int load */
150 COSTS_N_INSNS (2), /* int signed load */
151 COSTS_N_INSNS (2), /* int zeroed load */
152 COSTS_N_INSNS (2), /* float load */
153 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
154 COSTS_N_INSNS (5), /* fadd, fsub */
155 COSTS_N_INSNS (1), /* fcmp */
156 COSTS_N_INSNS (1), /* fmov, fmovr */
157 COSTS_N_INSNS (7), /* fmul */
158 COSTS_N_INSNS (37), /* fdivs */
159 COSTS_N_INSNS (37), /* fdivd */
160 COSTS_N_INSNS (63), /* fsqrts */
161 COSTS_N_INSNS (63), /* fsqrtd */
162 COSTS_N_INSNS (1), /* imul */
163 COSTS_N_INSNS (1), /* imulX */
164 0, /* imul bit factor */
165 COSTS_N_INSNS (1), /* idiv */
166 COSTS_N_INSNS (1), /* idivX */
167 COSTS_N_INSNS (1), /* movcc/movr */
168 0, /* shift penalty */
173 struct processor_costs supersparc_costs
= {
174 COSTS_N_INSNS (1), /* int load */
175 COSTS_N_INSNS (1), /* int signed load */
176 COSTS_N_INSNS (1), /* int zeroed load */
177 COSTS_N_INSNS (0), /* float load */
178 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
179 COSTS_N_INSNS (3), /* fadd, fsub */
180 COSTS_N_INSNS (3), /* fcmp */
181 COSTS_N_INSNS (1), /* fmov, fmovr */
182 COSTS_N_INSNS (3), /* fmul */
183 COSTS_N_INSNS (6), /* fdivs */
184 COSTS_N_INSNS (9), /* fdivd */
185 COSTS_N_INSNS (12), /* fsqrts */
186 COSTS_N_INSNS (12), /* fsqrtd */
187 COSTS_N_INSNS (4), /* imul */
188 COSTS_N_INSNS (4), /* imulX */
189 0, /* imul bit factor */
190 COSTS_N_INSNS (4), /* idiv */
191 COSTS_N_INSNS (4), /* idivX */
192 COSTS_N_INSNS (1), /* movcc/movr */
193 1, /* shift penalty */
198 struct processor_costs hypersparc_costs
= {
199 COSTS_N_INSNS (1), /* int load */
200 COSTS_N_INSNS (1), /* int signed load */
201 COSTS_N_INSNS (1), /* int zeroed load */
202 COSTS_N_INSNS (1), /* float load */
203 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
204 COSTS_N_INSNS (1), /* fadd, fsub */
205 COSTS_N_INSNS (1), /* fcmp */
206 COSTS_N_INSNS (1), /* fmov, fmovr */
207 COSTS_N_INSNS (1), /* fmul */
208 COSTS_N_INSNS (8), /* fdivs */
209 COSTS_N_INSNS (12), /* fdivd */
210 COSTS_N_INSNS (17), /* fsqrts */
211 COSTS_N_INSNS (17), /* fsqrtd */
212 COSTS_N_INSNS (17), /* imul */
213 COSTS_N_INSNS (17), /* imulX */
214 0, /* imul bit factor */
215 COSTS_N_INSNS (17), /* idiv */
216 COSTS_N_INSNS (17), /* idivX */
217 COSTS_N_INSNS (1), /* movcc/movr */
218 0, /* shift penalty */
223 struct processor_costs leon_costs
= {
224 COSTS_N_INSNS (1), /* int load */
225 COSTS_N_INSNS (1), /* int signed load */
226 COSTS_N_INSNS (1), /* int zeroed load */
227 COSTS_N_INSNS (1), /* float load */
228 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
229 COSTS_N_INSNS (1), /* fadd, fsub */
230 COSTS_N_INSNS (1), /* fcmp */
231 COSTS_N_INSNS (1), /* fmov, fmovr */
232 COSTS_N_INSNS (1), /* fmul */
233 COSTS_N_INSNS (15), /* fdivs */
234 COSTS_N_INSNS (15), /* fdivd */
235 COSTS_N_INSNS (23), /* fsqrts */
236 COSTS_N_INSNS (23), /* fsqrtd */
237 COSTS_N_INSNS (5), /* imul */
238 COSTS_N_INSNS (5), /* imulX */
239 0, /* imul bit factor */
240 COSTS_N_INSNS (5), /* idiv */
241 COSTS_N_INSNS (5), /* idivX */
242 COSTS_N_INSNS (1), /* movcc/movr */
243 0, /* shift penalty */
248 struct processor_costs leon3_costs
= {
249 COSTS_N_INSNS (1), /* int load */
250 COSTS_N_INSNS (1), /* int signed load */
251 COSTS_N_INSNS (1), /* int zeroed load */
252 COSTS_N_INSNS (1), /* float load */
253 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
254 COSTS_N_INSNS (1), /* fadd, fsub */
255 COSTS_N_INSNS (1), /* fcmp */
256 COSTS_N_INSNS (1), /* fmov, fmovr */
257 COSTS_N_INSNS (1), /* fmul */
258 COSTS_N_INSNS (14), /* fdivs */
259 COSTS_N_INSNS (15), /* fdivd */
260 COSTS_N_INSNS (22), /* fsqrts */
261 COSTS_N_INSNS (23), /* fsqrtd */
262 COSTS_N_INSNS (5), /* imul */
263 COSTS_N_INSNS (5), /* imulX */
264 0, /* imul bit factor */
265 COSTS_N_INSNS (35), /* idiv */
266 COSTS_N_INSNS (35), /* idivX */
267 COSTS_N_INSNS (1), /* movcc/movr */
268 0, /* shift penalty */
273 struct processor_costs sparclet_costs
= {
274 COSTS_N_INSNS (3), /* int load */
275 COSTS_N_INSNS (3), /* int signed load */
276 COSTS_N_INSNS (1), /* int zeroed load */
277 COSTS_N_INSNS (1), /* float load */
278 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
279 COSTS_N_INSNS (1), /* fadd, fsub */
280 COSTS_N_INSNS (1), /* fcmp */
281 COSTS_N_INSNS (1), /* fmov, fmovr */
282 COSTS_N_INSNS (1), /* fmul */
283 COSTS_N_INSNS (1), /* fdivs */
284 COSTS_N_INSNS (1), /* fdivd */
285 COSTS_N_INSNS (1), /* fsqrts */
286 COSTS_N_INSNS (1), /* fsqrtd */
287 COSTS_N_INSNS (5), /* imul */
288 COSTS_N_INSNS (5), /* imulX */
289 0, /* imul bit factor */
290 COSTS_N_INSNS (5), /* idiv */
291 COSTS_N_INSNS (5), /* idivX */
292 COSTS_N_INSNS (1), /* movcc/movr */
293 0, /* shift penalty */
298 struct processor_costs ultrasparc_costs
= {
299 COSTS_N_INSNS (2), /* int load */
300 COSTS_N_INSNS (3), /* int signed load */
301 COSTS_N_INSNS (2), /* int zeroed load */
302 COSTS_N_INSNS (2), /* float load */
303 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
304 COSTS_N_INSNS (4), /* fadd, fsub */
305 COSTS_N_INSNS (1), /* fcmp */
306 COSTS_N_INSNS (2), /* fmov, fmovr */
307 COSTS_N_INSNS (4), /* fmul */
308 COSTS_N_INSNS (13), /* fdivs */
309 COSTS_N_INSNS (23), /* fdivd */
310 COSTS_N_INSNS (13), /* fsqrts */
311 COSTS_N_INSNS (23), /* fsqrtd */
312 COSTS_N_INSNS (4), /* imul */
313 COSTS_N_INSNS (4), /* imulX */
314 2, /* imul bit factor */
315 COSTS_N_INSNS (37), /* idiv */
316 COSTS_N_INSNS (68), /* idivX */
317 COSTS_N_INSNS (2), /* movcc/movr */
318 2, /* shift penalty */
323 struct processor_costs ultrasparc3_costs
= {
324 COSTS_N_INSNS (2), /* int load */
325 COSTS_N_INSNS (3), /* int signed load */
326 COSTS_N_INSNS (3), /* int zeroed load */
327 COSTS_N_INSNS (2), /* float load */
328 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
329 COSTS_N_INSNS (4), /* fadd, fsub */
330 COSTS_N_INSNS (5), /* fcmp */
331 COSTS_N_INSNS (3), /* fmov, fmovr */
332 COSTS_N_INSNS (4), /* fmul */
333 COSTS_N_INSNS (17), /* fdivs */
334 COSTS_N_INSNS (20), /* fdivd */
335 COSTS_N_INSNS (20), /* fsqrts */
336 COSTS_N_INSNS (29), /* fsqrtd */
337 COSTS_N_INSNS (6), /* imul */
338 COSTS_N_INSNS (6), /* imulX */
339 0, /* imul bit factor */
340 COSTS_N_INSNS (40), /* idiv */
341 COSTS_N_INSNS (71), /* idivX */
342 COSTS_N_INSNS (2), /* movcc/movr */
343 0, /* shift penalty */
348 struct processor_costs niagara_costs
= {
349 COSTS_N_INSNS (3), /* int load */
350 COSTS_N_INSNS (3), /* int signed load */
351 COSTS_N_INSNS (3), /* int zeroed load */
352 COSTS_N_INSNS (9), /* float load */
353 COSTS_N_INSNS (8), /* fmov, fneg, fabs */
354 COSTS_N_INSNS (8), /* fadd, fsub */
355 COSTS_N_INSNS (26), /* fcmp */
356 COSTS_N_INSNS (8), /* fmov, fmovr */
357 COSTS_N_INSNS (29), /* fmul */
358 COSTS_N_INSNS (54), /* fdivs */
359 COSTS_N_INSNS (83), /* fdivd */
360 COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */
361 COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */
362 COSTS_N_INSNS (11), /* imul */
363 COSTS_N_INSNS (11), /* imulX */
364 0, /* imul bit factor */
365 COSTS_N_INSNS (72), /* idiv */
366 COSTS_N_INSNS (72), /* idivX */
367 COSTS_N_INSNS (1), /* movcc/movr */
368 0, /* shift penalty */
373 struct processor_costs niagara2_costs
= {
374 COSTS_N_INSNS (3), /* int load */
375 COSTS_N_INSNS (3), /* int signed load */
376 COSTS_N_INSNS (3), /* int zeroed load */
377 COSTS_N_INSNS (3), /* float load */
378 COSTS_N_INSNS (6), /* fmov, fneg, fabs */
379 COSTS_N_INSNS (6), /* fadd, fsub */
380 COSTS_N_INSNS (6), /* fcmp */
381 COSTS_N_INSNS (6), /* fmov, fmovr */
382 COSTS_N_INSNS (6), /* fmul */
383 COSTS_N_INSNS (19), /* fdivs */
384 COSTS_N_INSNS (33), /* fdivd */
385 COSTS_N_INSNS (19), /* fsqrts */
386 COSTS_N_INSNS (33), /* fsqrtd */
387 COSTS_N_INSNS (5), /* imul */
388 COSTS_N_INSNS (5), /* imulX */
389 0, /* imul bit factor */
390 COSTS_N_INSNS (26), /* idiv, average of 12 - 41 cycle range */
391 COSTS_N_INSNS (26), /* idivX, average of 12 - 41 cycle range */
392 COSTS_N_INSNS (1), /* movcc/movr */
393 0, /* shift penalty */
398 struct processor_costs niagara3_costs
= {
399 COSTS_N_INSNS (3), /* int load */
400 COSTS_N_INSNS (3), /* int signed load */
401 COSTS_N_INSNS (3), /* int zeroed load */
402 COSTS_N_INSNS (3), /* float load */
403 COSTS_N_INSNS (9), /* fmov, fneg, fabs */
404 COSTS_N_INSNS (9), /* fadd, fsub */
405 COSTS_N_INSNS (9), /* fcmp */
406 COSTS_N_INSNS (9), /* fmov, fmovr */
407 COSTS_N_INSNS (9), /* fmul */
408 COSTS_N_INSNS (23), /* fdivs */
409 COSTS_N_INSNS (37), /* fdivd */
410 COSTS_N_INSNS (23), /* fsqrts */
411 COSTS_N_INSNS (37), /* fsqrtd */
412 COSTS_N_INSNS (9), /* imul */
413 COSTS_N_INSNS (9), /* imulX */
414 0, /* imul bit factor */
415 COSTS_N_INSNS (31), /* idiv, average of 17 - 45 cycle range */
416 COSTS_N_INSNS (30), /* idivX, average of 16 - 44 cycle range */
417 COSTS_N_INSNS (1), /* movcc/movr */
418 0, /* shift penalty */
423 struct processor_costs niagara4_costs
= {
424 COSTS_N_INSNS (5), /* int load */
425 COSTS_N_INSNS (5), /* int signed load */
426 COSTS_N_INSNS (5), /* int zeroed load */
427 COSTS_N_INSNS (5), /* float load */
428 COSTS_N_INSNS (11), /* fmov, fneg, fabs */
429 COSTS_N_INSNS (11), /* fadd, fsub */
430 COSTS_N_INSNS (11), /* fcmp */
431 COSTS_N_INSNS (11), /* fmov, fmovr */
432 COSTS_N_INSNS (11), /* fmul */
433 COSTS_N_INSNS (24), /* fdivs */
434 COSTS_N_INSNS (37), /* fdivd */
435 COSTS_N_INSNS (24), /* fsqrts */
436 COSTS_N_INSNS (37), /* fsqrtd */
437 COSTS_N_INSNS (12), /* imul */
438 COSTS_N_INSNS (12), /* imulX */
439 0, /* imul bit factor */
440 COSTS_N_INSNS (50), /* idiv, average of 41 - 60 cycle range */
441 COSTS_N_INSNS (35), /* idivX, average of 26 - 44 cycle range */
442 COSTS_N_INSNS (1), /* movcc/movr */
443 0, /* shift penalty */
448 struct processor_costs niagara7_costs
= {
449 COSTS_N_INSNS (5), /* int load */
450 COSTS_N_INSNS (5), /* int signed load */
451 COSTS_N_INSNS (5), /* int zeroed load */
452 COSTS_N_INSNS (5), /* float load */
453 COSTS_N_INSNS (11), /* fmov, fneg, fabs */
454 COSTS_N_INSNS (11), /* fadd, fsub */
455 COSTS_N_INSNS (11), /* fcmp */
456 COSTS_N_INSNS (11), /* fmov, fmovr */
457 COSTS_N_INSNS (11), /* fmul */
458 COSTS_N_INSNS (24), /* fdivs */
459 COSTS_N_INSNS (37), /* fdivd */
460 COSTS_N_INSNS (24), /* fsqrts */
461 COSTS_N_INSNS (37), /* fsqrtd */
462 COSTS_N_INSNS (12), /* imul */
463 COSTS_N_INSNS (12), /* imulX */
464 0, /* imul bit factor */
465 COSTS_N_INSNS (51), /* idiv, average of 42 - 61 cycle range */
466 COSTS_N_INSNS (35), /* idivX, average of 26 - 44 cycle range */
467 COSTS_N_INSNS (1), /* movcc/movr */
468 0, /* shift penalty */
473 struct processor_costs m8_costs
= {
474 COSTS_N_INSNS (3), /* int load */
475 COSTS_N_INSNS (3), /* int signed load */
476 COSTS_N_INSNS (3), /* int zeroed load */
477 COSTS_N_INSNS (3), /* float load */
478 COSTS_N_INSNS (9), /* fmov, fneg, fabs */
479 COSTS_N_INSNS (9), /* fadd, fsub */
480 COSTS_N_INSNS (9), /* fcmp */
481 COSTS_N_INSNS (9), /* fmov, fmovr */
482 COSTS_N_INSNS (9), /* fmul */
483 COSTS_N_INSNS (26), /* fdivs */
484 COSTS_N_INSNS (30), /* fdivd */
485 COSTS_N_INSNS (33), /* fsqrts */
486 COSTS_N_INSNS (41), /* fsqrtd */
487 COSTS_N_INSNS (12), /* imul */
488 COSTS_N_INSNS (10), /* imulX */
489 0, /* imul bit factor */
490 COSTS_N_INSNS (57), /* udiv/sdiv */
491 COSTS_N_INSNS (30), /* udivx/sdivx */
492 COSTS_N_INSNS (1), /* movcc/movr */
493 0, /* shift penalty */
497 static const struct processor_costs
*sparc_costs
= &cypress_costs
;
499 #ifdef HAVE_AS_RELAX_OPTION
500 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
501 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
502 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
503 somebody does not branch between the sethi and jmp. */
504 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
506 #define LEAF_SIBCALL_SLOT_RESERVED_P \
507 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
510 /* Vector to say how input registers are mapped to output registers.
511 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
512 eliminate it. You must use -fomit-frame-pointer to get that. */
513 char leaf_reg_remap
[] =
514 { 0, 1, 2, 3, 4, 5, 6, 7,
515 -1, -1, -1, -1, -1, -1, 14, -1,
516 -1, -1, -1, -1, -1, -1, -1, -1,
517 8, 9, 10, 11, 12, 13, -1, 15,
519 32, 33, 34, 35, 36, 37, 38, 39,
520 40, 41, 42, 43, 44, 45, 46, 47,
521 48, 49, 50, 51, 52, 53, 54, 55,
522 56, 57, 58, 59, 60, 61, 62, 63,
523 64, 65, 66, 67, 68, 69, 70, 71,
524 72, 73, 74, 75, 76, 77, 78, 79,
525 80, 81, 82, 83, 84, 85, 86, 87,
526 88, 89, 90, 91, 92, 93, 94, 95,
527 96, 97, 98, 99, 100, 101, 102};
529 /* Vector, indexed by hard register number, which contains 1
530 for a register that is allowable in a candidate for leaf
531 function treatment. */
532 char sparc_leaf_regs
[] =
533 { 1, 1, 1, 1, 1, 1, 1, 1,
534 0, 0, 0, 0, 0, 0, 1, 0,
535 0, 0, 0, 0, 0, 0, 0, 0,
536 1, 1, 1, 1, 1, 1, 0, 1,
537 1, 1, 1, 1, 1, 1, 1, 1,
538 1, 1, 1, 1, 1, 1, 1, 1,
539 1, 1, 1, 1, 1, 1, 1, 1,
540 1, 1, 1, 1, 1, 1, 1, 1,
541 1, 1, 1, 1, 1, 1, 1, 1,
542 1, 1, 1, 1, 1, 1, 1, 1,
543 1, 1, 1, 1, 1, 1, 1, 1,
544 1, 1, 1, 1, 1, 1, 1, 1,
545 1, 1, 1, 1, 1, 1, 1};
547 struct GTY(()) machine_function
549 /* Size of the frame of the function. */
550 HOST_WIDE_INT frame_size
;
552 /* Size of the frame of the function minus the register window save area
553 and the outgoing argument area. */
554 HOST_WIDE_INT apparent_frame_size
;
556 /* Register we pretend the frame pointer is allocated to. Normally, this
557 is %fp, but if we are in a leaf procedure, this is (%sp + offset). We
558 record "offset" separately as it may be too big for (reg + disp). */
560 HOST_WIDE_INT frame_base_offset
;
562 /* Number of global or FP registers to be saved (as 4-byte quantities). */
563 int n_global_fp_regs
;
565 /* True if the current function is leaf and uses only leaf regs,
566 so that the SPARC leaf function optimization can be applied.
567 Private version of crtl->uses_only_leaf_regs, see
568 sparc_expand_prologue for the rationale. */
571 /* True if the prologue saves local or in registers. */
572 bool save_local_in_regs_p
;
574 /* True if the data calculated by sparc_expand_prologue are valid. */
575 bool prologue_data_valid_p
;
578 #define sparc_frame_size cfun->machine->frame_size
579 #define sparc_apparent_frame_size cfun->machine->apparent_frame_size
580 #define sparc_frame_base_reg cfun->machine->frame_base_reg
581 #define sparc_frame_base_offset cfun->machine->frame_base_offset
582 #define sparc_n_global_fp_regs cfun->machine->n_global_fp_regs
583 #define sparc_leaf_function_p cfun->machine->leaf_function_p
584 #define sparc_save_local_in_regs_p cfun->machine->save_local_in_regs_p
585 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
587 /* 1 if the next opcode is to be specially indented. */
588 int sparc_indent_opcode
= 0;
590 static void sparc_option_override (void);
591 static void sparc_init_modes (void);
592 static int function_arg_slotno (const CUMULATIVE_ARGS
*, machine_mode
,
593 const_tree
, bool, bool, int *, int *);
595 static int supersparc_adjust_cost (rtx_insn
*, int, rtx_insn
*, int);
596 static int hypersparc_adjust_cost (rtx_insn
*, int, rtx_insn
*, int);
598 static void sparc_emit_set_const32 (rtx
, rtx
);
599 static void sparc_emit_set_const64 (rtx
, rtx
);
600 static void sparc_output_addr_vec (rtx
);
601 static void sparc_output_addr_diff_vec (rtx
);
602 static void sparc_output_deferred_case_vectors (void);
603 static bool sparc_legitimate_address_p (machine_mode
, rtx
, bool);
604 static bool sparc_legitimate_constant_p (machine_mode
, rtx
);
605 static rtx
sparc_builtin_saveregs (void);
606 static int epilogue_renumber (rtx
*, int);
607 static bool sparc_assemble_integer (rtx
, unsigned int, int);
608 static int set_extends (rtx_insn
*);
609 static void sparc_asm_function_prologue (FILE *);
610 static void sparc_asm_function_epilogue (FILE *);
611 #ifdef TARGET_SOLARIS
612 static void sparc_solaris_elf_asm_named_section (const char *, unsigned int,
613 tree
) ATTRIBUTE_UNUSED
;
615 static int sparc_adjust_cost (rtx_insn
*, int, rtx_insn
*, int, unsigned int);
616 static int sparc_issue_rate (void);
617 static void sparc_sched_init (FILE *, int, int);
618 static int sparc_use_sched_lookahead (void);
620 static void emit_soft_tfmode_libcall (const char *, int, rtx
*);
621 static void emit_soft_tfmode_binop (enum rtx_code
, rtx
*);
622 static void emit_soft_tfmode_unop (enum rtx_code
, rtx
*);
623 static void emit_soft_tfmode_cvt (enum rtx_code
, rtx
*);
624 static void emit_hard_tfmode_operation (enum rtx_code
, rtx
*);
626 static bool sparc_function_ok_for_sibcall (tree
, tree
);
627 static void sparc_init_libfuncs (void);
628 static void sparc_init_builtins (void);
629 static void sparc_fpu_init_builtins (void);
630 static void sparc_vis_init_builtins (void);
631 static tree
sparc_builtin_decl (unsigned, bool);
632 static rtx
sparc_expand_builtin (tree
, rtx
, rtx
, machine_mode
, int);
633 static tree
sparc_fold_builtin (tree
, int, tree
*, bool);
634 static void sparc_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
635 HOST_WIDE_INT
, tree
);
636 static bool sparc_can_output_mi_thunk (const_tree
, HOST_WIDE_INT
,
637 HOST_WIDE_INT
, const_tree
);
638 static struct machine_function
* sparc_init_machine_status (void);
639 static bool sparc_cannot_force_const_mem (machine_mode
, rtx
);
640 static rtx
sparc_tls_get_addr (void);
641 static rtx
sparc_tls_got (void);
642 static int sparc_register_move_cost (machine_mode
,
643 reg_class_t
, reg_class_t
);
644 static bool sparc_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
645 static machine_mode
sparc_promote_function_mode (const_tree
, machine_mode
,
646 int *, const_tree
, int);
647 static bool sparc_strict_argument_naming (cumulative_args_t
);
648 static void sparc_va_start (tree
, rtx
);
649 static tree
sparc_gimplify_va_arg (tree
, tree
, gimple_seq
*, gimple_seq
*);
650 static bool sparc_vector_mode_supported_p (machine_mode
);
651 static bool sparc_tls_referenced_p (rtx
);
652 static rtx
sparc_legitimize_tls_address (rtx
);
653 static rtx
sparc_legitimize_pic_address (rtx
, rtx
);
654 static rtx
sparc_legitimize_address (rtx
, rtx
, machine_mode
);
655 static rtx
sparc_delegitimize_address (rtx
);
656 static bool sparc_mode_dependent_address_p (const_rtx
, addr_space_t
);
657 static bool sparc_pass_by_reference (cumulative_args_t
,
658 machine_mode
, const_tree
, bool);
659 static void sparc_function_arg_advance (cumulative_args_t
,
660 machine_mode
, const_tree
, bool);
661 static rtx
sparc_function_arg_1 (cumulative_args_t
,
662 machine_mode
, const_tree
, bool, bool);
663 static rtx
sparc_function_arg (cumulative_args_t
,
664 machine_mode
, const_tree
, bool);
665 static rtx
sparc_function_incoming_arg (cumulative_args_t
,
666 machine_mode
, const_tree
, bool);
667 static pad_direction
sparc_function_arg_padding (machine_mode
, const_tree
);
668 static unsigned int sparc_function_arg_boundary (machine_mode
,
670 static int sparc_arg_partial_bytes (cumulative_args_t
,
671 machine_mode
, tree
, bool);
672 static bool sparc_return_in_memory (const_tree
, const_tree
);
673 static rtx
sparc_struct_value_rtx (tree
, int);
674 static rtx
sparc_function_value (const_tree
, const_tree
, bool);
675 static rtx
sparc_libcall_value (machine_mode
, const_rtx
);
676 static bool sparc_function_value_regno_p (const unsigned int);
677 static unsigned HOST_WIDE_INT
sparc_asan_shadow_offset (void);
678 static void sparc_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
679 static void sparc_file_end (void);
680 static bool sparc_frame_pointer_required (void);
681 static bool sparc_can_eliminate (const int, const int);
682 static void sparc_conditional_register_usage (void);
683 static bool sparc_use_pseudo_pic_reg (void);
684 static void sparc_init_pic_reg (void);
685 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
686 static const char *sparc_mangle_type (const_tree
);
688 static void sparc_trampoline_init (rtx
, tree
, rtx
);
689 static machine_mode
sparc_preferred_simd_mode (scalar_mode
);
690 static reg_class_t
sparc_preferred_reload_class (rtx x
, reg_class_t rclass
);
691 static bool sparc_lra_p (void);
692 static bool sparc_print_operand_punct_valid_p (unsigned char);
693 static void sparc_print_operand (FILE *, rtx
, int);
694 static void sparc_print_operand_address (FILE *, machine_mode
, rtx
);
695 static reg_class_t
sparc_secondary_reload (bool, rtx
, reg_class_t
,
697 secondary_reload_info
*);
698 static bool sparc_secondary_memory_needed (machine_mode
, reg_class_t
,
700 static machine_mode
sparc_secondary_memory_needed_mode (machine_mode
);
701 static scalar_int_mode
sparc_cstore_mode (enum insn_code icode
);
702 static void sparc_atomic_assign_expand_fenv (tree
*, tree
*, tree
*);
703 static bool sparc_fixed_condition_code_regs (unsigned int *, unsigned int *);
704 static unsigned int sparc_min_arithmetic_precision (void);
705 static unsigned int sparc_hard_regno_nregs (unsigned int, machine_mode
);
706 static bool sparc_hard_regno_mode_ok (unsigned int, machine_mode
);
707 static bool sparc_modes_tieable_p (machine_mode
, machine_mode
);
708 static bool sparc_can_change_mode_class (machine_mode
, machine_mode
,
710 static HOST_WIDE_INT
sparc_constant_alignment (const_tree
, HOST_WIDE_INT
);
711 static bool sparc_vectorize_vec_perm_const (machine_mode
, rtx
, rtx
, rtx
,
712 const vec_perm_indices
&);
713 static bool sparc_can_follow_jump (const rtx_insn
*, const rtx_insn
*);
715 #ifdef SUBTARGET_ATTRIBUTE_TABLE
716 /* Table of valid machine attributes. */
717 static const struct attribute_spec sparc_attribute_table
[] =
719 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
720 do_diagnostic, handler, exclude } */
721 SUBTARGET_ATTRIBUTE_TABLE
,
722 { NULL
, 0, 0, false, false, false, false, NULL
, NULL
}
726 char sparc_hard_reg_printed
[8];
728 /* Initialize the GCC target structure. */
730 /* The default is to use .half rather than .short for aligned HI objects. */
731 #undef TARGET_ASM_ALIGNED_HI_OP
732 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
734 #undef TARGET_ASM_UNALIGNED_HI_OP
735 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
736 #undef TARGET_ASM_UNALIGNED_SI_OP
737 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
738 #undef TARGET_ASM_UNALIGNED_DI_OP
739 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
741 /* The target hook has to handle DI-mode values. */
742 #undef TARGET_ASM_INTEGER
743 #define TARGET_ASM_INTEGER sparc_assemble_integer
745 #undef TARGET_ASM_FUNCTION_PROLOGUE
746 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
747 #undef TARGET_ASM_FUNCTION_EPILOGUE
748 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
750 #undef TARGET_SCHED_ADJUST_COST
751 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
752 #undef TARGET_SCHED_ISSUE_RATE
753 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
754 #undef TARGET_SCHED_INIT
755 #define TARGET_SCHED_INIT sparc_sched_init
756 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
757 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
759 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
760 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
762 #undef TARGET_INIT_LIBFUNCS
763 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
765 #undef TARGET_LEGITIMIZE_ADDRESS
766 #define TARGET_LEGITIMIZE_ADDRESS sparc_legitimize_address
767 #undef TARGET_DELEGITIMIZE_ADDRESS
768 #define TARGET_DELEGITIMIZE_ADDRESS sparc_delegitimize_address
769 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
770 #define TARGET_MODE_DEPENDENT_ADDRESS_P sparc_mode_dependent_address_p
772 #undef TARGET_INIT_BUILTINS
773 #define TARGET_INIT_BUILTINS sparc_init_builtins
774 #undef TARGET_BUILTIN_DECL
775 #define TARGET_BUILTIN_DECL sparc_builtin_decl
776 #undef TARGET_EXPAND_BUILTIN
777 #define TARGET_EXPAND_BUILTIN sparc_expand_builtin
778 #undef TARGET_FOLD_BUILTIN
779 #define TARGET_FOLD_BUILTIN sparc_fold_builtin
782 #undef TARGET_HAVE_TLS
783 #define TARGET_HAVE_TLS true
786 #undef TARGET_CANNOT_FORCE_CONST_MEM
787 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
789 #undef TARGET_ASM_OUTPUT_MI_THUNK
790 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
791 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
792 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
794 #undef TARGET_RTX_COSTS
795 #define TARGET_RTX_COSTS sparc_rtx_costs
796 #undef TARGET_ADDRESS_COST
797 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
798 #undef TARGET_REGISTER_MOVE_COST
799 #define TARGET_REGISTER_MOVE_COST sparc_register_move_cost
801 #undef TARGET_PROMOTE_FUNCTION_MODE
802 #define TARGET_PROMOTE_FUNCTION_MODE sparc_promote_function_mode
803 #undef TARGET_STRICT_ARGUMENT_NAMING
804 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
806 #undef TARGET_MUST_PASS_IN_STACK
807 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
808 #undef TARGET_PASS_BY_REFERENCE
809 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
810 #undef TARGET_ARG_PARTIAL_BYTES
811 #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
812 #undef TARGET_FUNCTION_ARG_ADVANCE
813 #define TARGET_FUNCTION_ARG_ADVANCE sparc_function_arg_advance
814 #undef TARGET_FUNCTION_ARG
815 #define TARGET_FUNCTION_ARG sparc_function_arg
816 #undef TARGET_FUNCTION_INCOMING_ARG
817 #define TARGET_FUNCTION_INCOMING_ARG sparc_function_incoming_arg
818 #undef TARGET_FUNCTION_ARG_PADDING
819 #define TARGET_FUNCTION_ARG_PADDING sparc_function_arg_padding
820 #undef TARGET_FUNCTION_ARG_BOUNDARY
821 #define TARGET_FUNCTION_ARG_BOUNDARY sparc_function_arg_boundary
823 #undef TARGET_RETURN_IN_MEMORY
824 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
825 #undef TARGET_STRUCT_VALUE_RTX
826 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
827 #undef TARGET_FUNCTION_VALUE
828 #define TARGET_FUNCTION_VALUE sparc_function_value
829 #undef TARGET_LIBCALL_VALUE
830 #define TARGET_LIBCALL_VALUE sparc_libcall_value
831 #undef TARGET_FUNCTION_VALUE_REGNO_P
832 #define TARGET_FUNCTION_VALUE_REGNO_P sparc_function_value_regno_p
834 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
835 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
837 #undef TARGET_ASAN_SHADOW_OFFSET
838 #define TARGET_ASAN_SHADOW_OFFSET sparc_asan_shadow_offset
840 #undef TARGET_EXPAND_BUILTIN_VA_START
841 #define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start
842 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
843 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
845 #undef TARGET_VECTOR_MODE_SUPPORTED_P
846 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
848 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
849 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE sparc_preferred_simd_mode
851 #ifdef SUBTARGET_INSERT_ATTRIBUTES
852 #undef TARGET_INSERT_ATTRIBUTES
853 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
856 #ifdef SUBTARGET_ATTRIBUTE_TABLE
857 #undef TARGET_ATTRIBUTE_TABLE
858 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
861 #undef TARGET_OPTION_OVERRIDE
862 #define TARGET_OPTION_OVERRIDE sparc_option_override
864 #ifdef TARGET_THREAD_SSP_OFFSET
865 #undef TARGET_STACK_PROTECT_GUARD
866 #define TARGET_STACK_PROTECT_GUARD hook_tree_void_null
869 #if TARGET_GNU_TLS && defined(HAVE_AS_SPARC_UA_PCREL)
870 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
871 #define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel
874 #undef TARGET_ASM_FILE_END
875 #define TARGET_ASM_FILE_END sparc_file_end
877 #undef TARGET_FRAME_POINTER_REQUIRED
878 #define TARGET_FRAME_POINTER_REQUIRED sparc_frame_pointer_required
880 #undef TARGET_CAN_ELIMINATE
881 #define TARGET_CAN_ELIMINATE sparc_can_eliminate
883 #undef TARGET_PREFERRED_RELOAD_CLASS
884 #define TARGET_PREFERRED_RELOAD_CLASS sparc_preferred_reload_class
886 #undef TARGET_SECONDARY_RELOAD
887 #define TARGET_SECONDARY_RELOAD sparc_secondary_reload
888 #undef TARGET_SECONDARY_MEMORY_NEEDED
889 #define TARGET_SECONDARY_MEMORY_NEEDED sparc_secondary_memory_needed
890 #undef TARGET_SECONDARY_MEMORY_NEEDED_MODE
891 #define TARGET_SECONDARY_MEMORY_NEEDED_MODE sparc_secondary_memory_needed_mode
893 #undef TARGET_CONDITIONAL_REGISTER_USAGE
894 #define TARGET_CONDITIONAL_REGISTER_USAGE sparc_conditional_register_usage
896 #undef TARGET_INIT_PIC_REG
897 #define TARGET_INIT_PIC_REG sparc_init_pic_reg
899 #undef TARGET_USE_PSEUDO_PIC_REG
900 #define TARGET_USE_PSEUDO_PIC_REG sparc_use_pseudo_pic_reg
902 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
903 #undef TARGET_MANGLE_TYPE
904 #define TARGET_MANGLE_TYPE sparc_mangle_type
908 #define TARGET_LRA_P sparc_lra_p
910 #undef TARGET_LEGITIMATE_ADDRESS_P
911 #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p
913 #undef TARGET_LEGITIMATE_CONSTANT_P
914 #define TARGET_LEGITIMATE_CONSTANT_P sparc_legitimate_constant_p
916 #undef TARGET_TRAMPOLINE_INIT
917 #define TARGET_TRAMPOLINE_INIT sparc_trampoline_init
919 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
920 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sparc_print_operand_punct_valid_p
921 #undef TARGET_PRINT_OPERAND
922 #define TARGET_PRINT_OPERAND sparc_print_operand
923 #undef TARGET_PRINT_OPERAND_ADDRESS
924 #define TARGET_PRINT_OPERAND_ADDRESS sparc_print_operand_address
926 /* The value stored by LDSTUB. */
927 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
928 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 0xff
930 #undef TARGET_CSTORE_MODE
931 #define TARGET_CSTORE_MODE sparc_cstore_mode
933 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
934 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV sparc_atomic_assign_expand_fenv
936 #undef TARGET_FIXED_CONDITION_CODE_REGS
937 #define TARGET_FIXED_CONDITION_CODE_REGS sparc_fixed_condition_code_regs
939 #undef TARGET_MIN_ARITHMETIC_PRECISION
940 #define TARGET_MIN_ARITHMETIC_PRECISION sparc_min_arithmetic_precision
942 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
943 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
945 #undef TARGET_HARD_REGNO_NREGS
946 #define TARGET_HARD_REGNO_NREGS sparc_hard_regno_nregs
947 #undef TARGET_HARD_REGNO_MODE_OK
948 #define TARGET_HARD_REGNO_MODE_OK sparc_hard_regno_mode_ok
950 #undef TARGET_MODES_TIEABLE_P
951 #define TARGET_MODES_TIEABLE_P sparc_modes_tieable_p
953 #undef TARGET_CAN_CHANGE_MODE_CLASS
954 #define TARGET_CAN_CHANGE_MODE_CLASS sparc_can_change_mode_class
956 #undef TARGET_CONSTANT_ALIGNMENT
957 #define TARGET_CONSTANT_ALIGNMENT sparc_constant_alignment
959 #undef TARGET_VECTORIZE_VEC_PERM_CONST
960 #define TARGET_VECTORIZE_VEC_PERM_CONST sparc_vectorize_vec_perm_const
962 #undef TARGET_CAN_FOLLOW_JUMP
963 #define TARGET_CAN_FOLLOW_JUMP sparc_can_follow_jump
965 struct gcc_target targetm
= TARGET_INITIALIZER
;
967 /* Return the memory reference contained in X if any, zero otherwise. */
972 if (GET_CODE (x
) == SIGN_EXTEND
|| GET_CODE (x
) == ZERO_EXTEND
)
981 /* True if any of INSN's source register(s) is REG. */
984 insn_uses_reg_p (rtx_insn
*insn
, unsigned int reg
)
987 return ((REG_P (recog_data
.operand
[1])
988 && REGNO (recog_data
.operand
[1]) == reg
)
989 || (recog_data
.n_operands
== 3
990 && REG_P (recog_data
.operand
[2])
991 && REGNO (recog_data
.operand
[2]) == reg
));
994 /* True if INSN is a floating-point division or square-root. */
997 div_sqrt_insn_p (rtx_insn
*insn
)
999 if (GET_CODE (PATTERN (insn
)) != SET
)
1002 switch (get_attr_type (insn
))
1014 /* True if INSN is a floating-point instruction. */
1017 fpop_insn_p (rtx_insn
*insn
)
1019 if (GET_CODE (PATTERN (insn
)) != SET
)
1022 switch (get_attr_type (insn
))
1039 /* True if INSN is an atomic instruction. */
1042 atomic_insn_for_leon3_p (rtx_insn
*insn
)
1044 switch (INSN_CODE (insn
))
1046 case CODE_FOR_swapsi
:
1047 case CODE_FOR_ldstub
:
1048 case CODE_FOR_atomic_compare_and_swap_leon3_1
:
1055 /* We use a machine specific pass to enable workarounds for errata.
1057 We need to have the (essentially) final form of the insn stream in order
1058 to properly detect the various hazards. Therefore, this machine specific
1059 pass runs as late as possible. */
1061 /* True if INSN is a md pattern or asm statement. */
1062 #define USEFUL_INSN_P(INSN) \
1063 (NONDEBUG_INSN_P (INSN) \
1064 && GET_CODE (PATTERN (INSN)) != USE \
1065 && GET_CODE (PATTERN (INSN)) != CLOBBER)
1068 sparc_do_work_around_errata (void)
1070 rtx_insn
*insn
, *next
;
1072 /* Force all instructions to be split into their final form. */
1073 split_all_insns_noflow ();
1075 /* Now look for specific patterns in the insn stream. */
1076 for (insn
= get_insns (); insn
; insn
= next
)
1078 bool insert_nop
= false;
1083 /* Look into the instruction in a delay slot. */
1084 if (NONJUMP_INSN_P (insn
)
1085 && (seq
= dyn_cast
<rtx_sequence
*> (PATTERN (insn
))))
1087 jump
= seq
->insn (0);
1088 insn
= seq
->insn (1);
1090 else if (JUMP_P (insn
))
1095 /* Place a NOP at the branch target of an integer branch if it is a
1096 floating-point operation or a floating-point branch. */
1097 if (sparc_fix_gr712rc
1099 && jump_to_label_p (jump
)
1100 && get_attr_branch_type (jump
) == BRANCH_TYPE_ICC
)
1102 rtx_insn
*target
= next_active_insn (JUMP_LABEL_AS_INSN (jump
));
1104 && (fpop_insn_p (target
)
1106 && get_attr_branch_type (target
) == BRANCH_TYPE_FCC
)))
1107 emit_insn_before (gen_nop (), target
);
1110 /* Insert a NOP between load instruction and atomic instruction. Insert
1111 a NOP at branch target if there is a load in delay slot and an atomic
1112 instruction at branch target. */
1114 && NONJUMP_INSN_P (insn
)
1115 && (set
= single_set (insn
)) != NULL_RTX
1116 && mem_ref (SET_SRC (set
))
1117 && REG_P (SET_DEST (set
)))
1119 if (jump
&& jump_to_label_p (jump
))
1121 rtx_insn
*target
= next_active_insn (JUMP_LABEL_AS_INSN (jump
));
1122 if (target
&& atomic_insn_for_leon3_p (target
))
1123 emit_insn_before (gen_nop (), target
);
1126 next
= next_active_insn (insn
);
1130 if (atomic_insn_for_leon3_p (next
))
1134 /* Look for a sequence that starts with a fdiv or fsqrt instruction and
1135 ends with another fdiv or fsqrt instruction with no dependencies on
1136 the former, along with an appropriate pattern in between. */
1137 if (sparc_fix_lost_divsqrt
1138 && NONJUMP_INSN_P (insn
)
1139 && div_sqrt_insn_p (insn
))
1145 const unsigned int dest_reg
= REGNO (SET_DEST (single_set (insn
)));
1147 next
= next_active_insn (insn
);
1151 for (after
= next
, i
= 0; i
< 4; i
++)
1153 /* Count floating-point operations. */
1154 if (i
!= 3 && fpop_insn_p (after
))
1156 /* If the insn uses the destination register of
1157 the div/sqrt, then it cannot be problematic. */
1158 if (insn_uses_reg_p (after
, dest_reg
))
1163 /* Count floating-point loads. */
1165 && (set
= single_set (after
)) != NULL_RTX
1166 && REG_P (SET_DEST (set
))
1167 && REGNO (SET_DEST (set
)) > 31)
1169 /* If the insn uses the destination register of
1170 the div/sqrt, then it cannot be problematic. */
1171 if (REGNO (SET_DEST (set
)) == dest_reg
)
1176 /* Check if this is a problematic sequence. */
1179 && div_sqrt_insn_p (after
))
1181 /* If this is the short version of the problematic
1182 sequence we add two NOPs in a row to also prevent
1183 the long version. */
1185 emit_insn_before (gen_nop (), next
);
1190 /* No need to scan past a second div/sqrt. */
1191 if (div_sqrt_insn_p (after
))
1194 /* Insert NOP before branch. */
1196 && (!NONJUMP_INSN_P (after
)
1197 || GET_CODE (PATTERN (after
)) == SEQUENCE
))
1203 after
= next_active_insn (after
);
1209 /* Look for either of these two sequences:
1212 1. store of word size or less (e.g. st / stb / sth / stf)
1213 2. any single instruction that is not a load or store
1214 3. any store instruction (e.g. st / stb / sth / stf / std / stdf)
1217 1. store of double word size (e.g. std / stdf)
1218 2. any store instruction (e.g. st / stb / sth / stf / std / stdf) */
1220 && NONJUMP_INSN_P (insn
)
1221 && (set
= single_set (insn
)) != NULL_RTX
1222 && MEM_P (SET_DEST (set
)))
1224 /* Sequence B begins with a double-word store. */
1225 bool seq_b
= GET_MODE_SIZE (GET_MODE (SET_DEST (set
))) == 8;
1229 next
= next_active_insn (insn
);
1233 for (after
= next
, i
= 0; i
< 2; i
++)
1235 /* Skip empty assembly statements. */
1236 if ((GET_CODE (PATTERN (after
)) == UNSPEC_VOLATILE
)
1237 || (USEFUL_INSN_P (after
)
1238 && (asm_noperands (PATTERN (after
))>=0)
1239 && !strcmp (decode_asm_operands (PATTERN (after
),
1242 after
= next_active_insn (after
);
1246 /* If the insn is a branch, then it cannot be problematic. */
1247 if (!NONJUMP_INSN_P (after
)
1248 || GET_CODE (PATTERN (after
)) == SEQUENCE
)
1251 /* Sequence B is only two instructions long. */
1254 /* Add NOP if followed by a store. */
1255 if ((set
= single_set (after
)) != NULL_RTX
1256 && MEM_P (SET_DEST (set
)))
1259 /* Otherwise it is ok. */
1263 /* If the second instruction is a load or a store,
1264 then the sequence cannot be problematic. */
1267 if ((set
= single_set (after
)) != NULL_RTX
1268 && (MEM_P (SET_DEST (set
)) || mem_ref (SET_SRC (set
))))
1271 after
= next_active_insn (after
);
1276 /* Add NOP if third instruction is a store. */
1278 && (set
= single_set (after
)) != NULL_RTX
1279 && MEM_P (SET_DEST (set
)))
1284 /* Look for a single-word load into an odd-numbered FP register. */
1285 else if (sparc_fix_at697f
1286 && NONJUMP_INSN_P (insn
)
1287 && (set
= single_set (insn
)) != NULL_RTX
1288 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
1289 && mem_ref (SET_SRC (set
))
1290 && REG_P (SET_DEST (set
))
1291 && REGNO (SET_DEST (set
)) > 31
1292 && REGNO (SET_DEST (set
)) % 2 != 0)
1294 /* The wrong dependency is on the enclosing double register. */
1295 const unsigned int x
= REGNO (SET_DEST (set
)) - 1;
1296 unsigned int src1
, src2
, dest
;
1299 next
= next_active_insn (insn
);
1302 /* If the insn is a branch, then it cannot be problematic. */
1303 if (!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) == SEQUENCE
)
1306 extract_insn (next
);
1307 code
= INSN_CODE (next
);
1311 case CODE_FOR_adddf3
:
1312 case CODE_FOR_subdf3
:
1313 case CODE_FOR_muldf3
:
1314 case CODE_FOR_divdf3
:
1315 dest
= REGNO (recog_data
.operand
[0]);
1316 src1
= REGNO (recog_data
.operand
[1]);
1317 src2
= REGNO (recog_data
.operand
[2]);
1322 FPOPd %f{x,y}, %f{y,x}, %f{x,y} */
1323 if ((src1
== x
|| src2
== x
)
1324 && (dest
== src1
|| dest
== src2
))
1331 FPOPd %fx, %fx, %fx */
1334 && (code
== CODE_FOR_adddf3
|| code
== CODE_FOR_muldf3
))
1339 case CODE_FOR_sqrtdf2
:
1340 dest
= REGNO (recog_data
.operand
[0]);
1341 src1
= REGNO (recog_data
.operand
[1]);
1345 if (src1
== x
&& dest
== src1
)
1354 /* Look for a single-word load into an integer register. */
1355 else if (sparc_fix_ut699
1356 && NONJUMP_INSN_P (insn
)
1357 && (set
= single_set (insn
)) != NULL_RTX
1358 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) <= 4
1359 && (mem_ref (SET_SRC (set
)) != NULL_RTX
1360 || INSN_CODE (insn
) == CODE_FOR_movsi_pic_gotdata_op
)
1361 && REG_P (SET_DEST (set
))
1362 && REGNO (SET_DEST (set
)) < 32)
1364 /* There is no problem if the second memory access has a data
1365 dependency on the first single-cycle load. */
1366 rtx x
= SET_DEST (set
);
1368 next
= next_active_insn (insn
);
1371 /* If the insn is a branch, then it cannot be problematic. */
1372 if (!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) == SEQUENCE
)
1375 /* Look for a second memory access to/from an integer register. */
1376 if ((set
= single_set (next
)) != NULL_RTX
)
1378 rtx src
= SET_SRC (set
);
1379 rtx dest
= SET_DEST (set
);
1382 /* LDD is affected. */
1383 if ((mem
= mem_ref (src
)) != NULL_RTX
1385 && REGNO (dest
) < 32
1386 && !reg_mentioned_p (x
, XEXP (mem
, 0)))
1389 /* STD is *not* affected. */
1390 else if (MEM_P (dest
)
1391 && GET_MODE_SIZE (GET_MODE (dest
)) <= 4
1392 && (src
== CONST0_RTX (GET_MODE (dest
))
1395 && REGNO (src
) != REGNO (x
)))
1396 && !reg_mentioned_p (x
, XEXP (dest
, 0)))
1399 /* GOT accesses uses LD. */
1400 else if (INSN_CODE (next
) == CODE_FOR_movsi_pic_gotdata_op
1401 && !reg_mentioned_p (x
, XEXP (XEXP (src
, 0), 1)))
1406 /* Look for a single-word load/operation into an FP register. */
1407 else if (sparc_fix_ut699
1408 && NONJUMP_INSN_P (insn
)
1409 && (set
= single_set (insn
)) != NULL_RTX
1410 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
1411 && REG_P (SET_DEST (set
))
1412 && REGNO (SET_DEST (set
)) > 31)
1414 /* Number of instructions in the problematic window. */
1415 const int n_insns
= 4;
1416 /* The problematic combination is with the sibling FP register. */
1417 const unsigned int x
= REGNO (SET_DEST (set
));
1418 const unsigned int y
= x
^ 1;
1422 next
= next_active_insn (insn
);
1425 /* If the insn is a branch, then it cannot be problematic. */
1426 if (!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) == SEQUENCE
)
1429 /* Look for a second load/operation into the sibling FP register. */
1430 if (!((set
= single_set (next
)) != NULL_RTX
1431 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
1432 && REG_P (SET_DEST (set
))
1433 && REGNO (SET_DEST (set
)) == y
))
1436 /* Look for a (possible) store from the FP register in the next N
1437 instructions, but bail out if it is again modified or if there
1438 is a store from the sibling FP register before this store. */
1439 for (after
= next
, i
= 0; i
< n_insns
; i
++)
1443 after
= next_active_insn (after
);
1447 /* This is a branch with an empty delay slot. */
1448 if (!NONJUMP_INSN_P (after
))
1455 /* This is a branch with a filled delay slot. */
1456 else if (rtx_sequence
*seq
=
1457 dyn_cast
<rtx_sequence
*> (PATTERN (after
)))
1462 after
= seq
->insn (1);
1464 /* This is a regular instruction. */
1468 if (after
&& (set
= single_set (after
)) != NULL_RTX
)
1470 const rtx src
= SET_SRC (set
);
1471 const rtx dest
= SET_DEST (set
);
1472 const unsigned int size
= GET_MODE_SIZE (GET_MODE (dest
));
1474 /* If the FP register is again modified before the store,
1475 then the store isn't affected. */
1477 && (REGNO (dest
) == x
1478 || (REGNO (dest
) == y
&& size
== 8)))
1481 if (MEM_P (dest
) && REG_P (src
))
1483 /* If there is a store from the sibling FP register
1484 before the store, then the store is not affected. */
1485 if (REGNO (src
) == y
|| (REGNO (src
) == x
&& size
== 8))
1488 /* Otherwise, the store is affected. */
1489 if (REGNO (src
) == x
&& size
== 4)
1497 /* If we have a branch in the first M instructions, then we
1498 cannot see the (M+2)th instruction so we play safe. */
1499 if (branch_p
&& i
<= (n_insns
- 2))
1508 next
= NEXT_INSN (insn
);
1511 emit_insn_before (gen_nop (), next
);
1519 const pass_data pass_data_work_around_errata
=
1521 RTL_PASS
, /* type */
1522 "errata", /* name */
1523 OPTGROUP_NONE
, /* optinfo_flags */
1524 TV_MACH_DEP
, /* tv_id */
1525 0, /* properties_required */
1526 0, /* properties_provided */
1527 0, /* properties_destroyed */
1528 0, /* todo_flags_start */
1529 0, /* todo_flags_finish */
1532 class pass_work_around_errata
: public rtl_opt_pass
1535 pass_work_around_errata(gcc::context
*ctxt
)
1536 : rtl_opt_pass(pass_data_work_around_errata
, ctxt
)
1539 /* opt_pass methods: */
1540 virtual bool gate (function
*)
1542 return sparc_fix_at697f
1543 || sparc_fix_ut699
|| sparc_fix_ut700
|| sparc_fix_gr712rc
1544 || sparc_fix_b2bst
|| sparc_fix_lost_divsqrt
;
1547 virtual unsigned int execute (function
*)
1549 return sparc_do_work_around_errata ();
1552 }; // class pass_work_around_errata
1557 make_pass_work_around_errata (gcc::context
*ctxt
)
1559 return new pass_work_around_errata (ctxt
);
1562 /* Helpers for TARGET_DEBUG_OPTIONS. */
1564 dump_target_flag_bits (const int flags
)
1566 if (flags
& MASK_64BIT
)
1567 fprintf (stderr
, "64BIT ");
1568 if (flags
& MASK_APP_REGS
)
1569 fprintf (stderr
, "APP_REGS ");
1570 if (flags
& MASK_FASTER_STRUCTS
)
1571 fprintf (stderr
, "FASTER_STRUCTS ");
1572 if (flags
& MASK_FLAT
)
1573 fprintf (stderr
, "FLAT ");
1574 if (flags
& MASK_FMAF
)
1575 fprintf (stderr
, "FMAF ");
1576 if (flags
& MASK_FSMULD
)
1577 fprintf (stderr
, "FSMULD ");
1578 if (flags
& MASK_FPU
)
1579 fprintf (stderr
, "FPU ");
1580 if (flags
& MASK_HARD_QUAD
)
1581 fprintf (stderr
, "HARD_QUAD ");
1582 if (flags
& MASK_POPC
)
1583 fprintf (stderr
, "POPC ");
1584 if (flags
& MASK_PTR64
)
1585 fprintf (stderr
, "PTR64 ");
1586 if (flags
& MASK_STACK_BIAS
)
1587 fprintf (stderr
, "STACK_BIAS ");
1588 if (flags
& MASK_UNALIGNED_DOUBLES
)
1589 fprintf (stderr
, "UNALIGNED_DOUBLES ");
1590 if (flags
& MASK_V8PLUS
)
1591 fprintf (stderr
, "V8PLUS ");
1592 if (flags
& MASK_VIS
)
1593 fprintf (stderr
, "VIS ");
1594 if (flags
& MASK_VIS2
)
1595 fprintf (stderr
, "VIS2 ");
1596 if (flags
& MASK_VIS3
)
1597 fprintf (stderr
, "VIS3 ");
1598 if (flags
& MASK_VIS4
)
1599 fprintf (stderr
, "VIS4 ");
1600 if (flags
& MASK_VIS4B
)
1601 fprintf (stderr
, "VIS4B ");
1602 if (flags
& MASK_CBCOND
)
1603 fprintf (stderr
, "CBCOND ");
1604 if (flags
& MASK_DEPRECATED_V8_INSNS
)
1605 fprintf (stderr
, "DEPRECATED_V8_INSNS ");
1606 if (flags
& MASK_SPARCLET
)
1607 fprintf (stderr
, "SPARCLET ");
1608 if (flags
& MASK_SPARCLITE
)
1609 fprintf (stderr
, "SPARCLITE ");
1610 if (flags
& MASK_V8
)
1611 fprintf (stderr
, "V8 ");
1612 if (flags
& MASK_V9
)
1613 fprintf (stderr
, "V9 ");
1617 dump_target_flags (const char *prefix
, const int flags
)
1619 fprintf (stderr
, "%s: (%08x) [ ", prefix
, flags
);
1620 dump_target_flag_bits (flags
);
1621 fprintf(stderr
, "]\n");
1624 /* Validate and override various options, and do some machine dependent
1628 sparc_option_override (void)
1630 /* Map TARGET_CPU_DEFAULT to value for -m{cpu,tune}=. */
1631 static struct cpu_default
{
1633 const enum sparc_processor_type processor
;
1634 } const cpu_default
[] = {
1635 /* There must be one entry here for each TARGET_CPU value. */
1636 { TARGET_CPU_sparc
, PROCESSOR_CYPRESS
},
1637 { TARGET_CPU_v8
, PROCESSOR_V8
},
1638 { TARGET_CPU_supersparc
, PROCESSOR_SUPERSPARC
},
1639 { TARGET_CPU_hypersparc
, PROCESSOR_HYPERSPARC
},
1640 { TARGET_CPU_leon
, PROCESSOR_LEON
},
1641 { TARGET_CPU_leon3
, PROCESSOR_LEON3
},
1642 { TARGET_CPU_leon3v7
, PROCESSOR_LEON3V7
},
1643 { TARGET_CPU_sparclite
, PROCESSOR_F930
},
1644 { TARGET_CPU_sparclite86x
, PROCESSOR_SPARCLITE86X
},
1645 { TARGET_CPU_sparclet
, PROCESSOR_TSC701
},
1646 { TARGET_CPU_v9
, PROCESSOR_V9
},
1647 { TARGET_CPU_ultrasparc
, PROCESSOR_ULTRASPARC
},
1648 { TARGET_CPU_ultrasparc3
, PROCESSOR_ULTRASPARC3
},
1649 { TARGET_CPU_niagara
, PROCESSOR_NIAGARA
},
1650 { TARGET_CPU_niagara2
, PROCESSOR_NIAGARA2
},
1651 { TARGET_CPU_niagara3
, PROCESSOR_NIAGARA3
},
1652 { TARGET_CPU_niagara4
, PROCESSOR_NIAGARA4
},
1653 { TARGET_CPU_niagara7
, PROCESSOR_NIAGARA7
},
1654 { TARGET_CPU_m8
, PROCESSOR_M8
},
1655 { -1, PROCESSOR_V7
}
1657 const struct cpu_default
*def
;
1658 /* Table of values for -m{cpu,tune}=. This must match the order of
1659 the enum processor_type in sparc-opts.h. */
1660 static struct cpu_table
{
1661 const char *const name
;
1664 } const cpu_table
[] = {
1665 { "v7", MASK_ISA
, 0 },
1666 { "cypress", MASK_ISA
, 0 },
1667 { "v8", MASK_ISA
, MASK_V8
},
1668 /* TI TMS390Z55 supersparc */
1669 { "supersparc", MASK_ISA
, MASK_V8
},
1670 { "hypersparc", MASK_ISA
, MASK_V8
},
1671 { "leon", MASK_ISA
|MASK_FSMULD
, MASK_V8
|MASK_LEON
},
1672 { "leon3", MASK_ISA
, MASK_V8
|MASK_LEON3
},
1673 { "leon3v7", MASK_ISA
, MASK_LEON3
},
1674 { "sparclite", MASK_ISA
, MASK_SPARCLITE
},
1675 /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
1676 { "f930", MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
1677 /* The Fujitsu MB86934 is the recent sparclite chip, with an FPU. */
1678 { "f934", MASK_ISA
, MASK_SPARCLITE
},
1679 { "sparclite86x", MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
1680 { "sparclet", MASK_ISA
, MASK_SPARCLET
},
1681 /* TEMIC sparclet */
1682 { "tsc701", MASK_ISA
, MASK_SPARCLET
},
1683 { "v9", MASK_ISA
, MASK_V9
},
1684 /* UltraSPARC I, II, IIi */
1685 { "ultrasparc", MASK_ISA
,
1686 /* Although insns using %y are deprecated, it is a clear win. */
1687 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
1688 /* UltraSPARC III */
1689 /* ??? Check if %y issue still holds true. */
1690 { "ultrasparc3", MASK_ISA
,
1691 MASK_V9
|MASK_DEPRECATED_V8_INSNS
|MASK_VIS2
},
1693 { "niagara", MASK_ISA
,
1694 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
1696 { "niagara2", MASK_ISA
,
1697 MASK_V9
|MASK_POPC
|MASK_VIS2
},
1699 { "niagara3", MASK_ISA
,
1700 MASK_V9
|MASK_POPC
|MASK_VIS3
|MASK_FMAF
},
1702 { "niagara4", MASK_ISA
,
1703 MASK_V9
|MASK_POPC
|MASK_VIS3
|MASK_FMAF
|MASK_CBCOND
},
1705 { "niagara7", MASK_ISA
,
1706 MASK_V9
|MASK_POPC
|MASK_VIS4
|MASK_FMAF
|MASK_CBCOND
|MASK_SUBXC
},
1709 MASK_V9
|MASK_POPC
|MASK_VIS4B
|MASK_FMAF
|MASK_CBCOND
|MASK_SUBXC
}
1711 const struct cpu_table
*cpu
;
1714 if (sparc_debug_string
!= NULL
)
1719 p
= ASTRDUP (sparc_debug_string
);
1720 while ((q
= strtok (p
, ",")) != NULL
)
1734 if (! strcmp (q
, "all"))
1735 mask
= MASK_DEBUG_ALL
;
1736 else if (! strcmp (q
, "options"))
1737 mask
= MASK_DEBUG_OPTIONS
;
1739 error ("unknown %<-mdebug-%s%> switch", q
);
1742 sparc_debug
&= ~mask
;
1744 sparc_debug
|= mask
;
1748 /* Enable the FsMULd instruction by default if not explicitly specified by
1749 the user. It may be later disabled by the CPU (explicitly or not). */
1750 if (TARGET_FPU
&& !(target_flags_explicit
& MASK_FSMULD
))
1751 target_flags
|= MASK_FSMULD
;
1753 if (TARGET_DEBUG_OPTIONS
)
1755 dump_target_flags("Initial target_flags", target_flags
);
1756 dump_target_flags("target_flags_explicit", target_flags_explicit
);
1759 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1760 SUBTARGET_OVERRIDE_OPTIONS
;
1763 #ifndef SPARC_BI_ARCH
1764 /* Check for unsupported architecture size. */
1765 if (!TARGET_64BIT
!= DEFAULT_ARCH32_P
)
1766 error ("%s is not supported by this configuration",
1767 DEFAULT_ARCH32_P
? "-m64" : "-m32");
1770 /* We force all 64bit archs to use 128 bit long double */
1771 if (TARGET_ARCH64
&& !TARGET_LONG_DOUBLE_128
)
1773 error ("%<-mlong-double-64%> not allowed with %<-m64%>");
1774 target_flags
|= MASK_LONG_DOUBLE_128
;
1777 /* Check that -fcall-saved-REG wasn't specified for out registers. */
1778 for (i
= 8; i
< 16; i
++)
1779 if (!call_used_regs
[i
])
1781 error ("%<-fcall-saved-REG%> is not supported for out registers");
1782 call_used_regs
[i
] = 1;
1785 /* Set the default CPU if no -mcpu option was specified. */
1786 if (!global_options_set
.x_sparc_cpu_and_features
)
1788 for (def
= &cpu_default
[0]; def
->cpu
!= -1; ++def
)
1789 if (def
->cpu
== TARGET_CPU_DEFAULT
)
1791 gcc_assert (def
->cpu
!= -1);
1792 sparc_cpu_and_features
= def
->processor
;
1795 /* Set the default CPU if no -mtune option was specified. */
1796 if (!global_options_set
.x_sparc_cpu
)
1797 sparc_cpu
= sparc_cpu_and_features
;
1799 cpu
= &cpu_table
[(int) sparc_cpu_and_features
];
1801 if (TARGET_DEBUG_OPTIONS
)
1803 fprintf (stderr
, "sparc_cpu_and_features: %s\n", cpu
->name
);
1804 dump_target_flags ("cpu->disable", cpu
->disable
);
1805 dump_target_flags ("cpu->enable", cpu
->enable
);
1808 target_flags
&= ~cpu
->disable
;
1809 target_flags
|= (cpu
->enable
1810 #ifndef HAVE_AS_FMAF_HPC_VIS3
1811 & ~(MASK_FMAF
| MASK_VIS3
)
1813 #ifndef HAVE_AS_SPARC4
1816 #ifndef HAVE_AS_SPARC5_VIS4
1817 & ~(MASK_VIS4
| MASK_SUBXC
)
1819 #ifndef HAVE_AS_SPARC6
1822 #ifndef HAVE_AS_LEON
1823 & ~(MASK_LEON
| MASK_LEON3
)
1825 & ~(target_flags_explicit
& MASK_FEATURES
)
1828 /* FsMULd is a V8 instruction. */
1829 if (!TARGET_V8
&& !TARGET_V9
)
1830 target_flags
&= ~MASK_FSMULD
;
1832 /* -mvis2 implies -mvis. */
1834 target_flags
|= MASK_VIS
;
1836 /* -mvis3 implies -mvis2 and -mvis. */
1838 target_flags
|= MASK_VIS2
| MASK_VIS
;
1840 /* -mvis4 implies -mvis3, -mvis2 and -mvis. */
1842 target_flags
|= MASK_VIS3
| MASK_VIS2
| MASK_VIS
;
1844 /* -mvis4b implies -mvis4, -mvis3, -mvis2 and -mvis */
1846 target_flags
|= MASK_VIS4
| MASK_VIS3
| MASK_VIS2
| MASK_VIS
;
1848 /* Don't allow -mvis, -mvis2, -mvis3, -mvis4, -mvis4b, -mfmaf and -mfsmuld if
1851 target_flags
&= ~(MASK_VIS
| MASK_VIS2
| MASK_VIS3
| MASK_VIS4
1852 | MASK_VIS4B
| MASK_FMAF
| MASK_FSMULD
);
1854 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
1855 are available; -m64 also implies v9. */
1856 if (TARGET_VIS
|| TARGET_ARCH64
)
1858 target_flags
|= MASK_V9
;
1859 target_flags
&= ~(MASK_V8
| MASK_SPARCLET
| MASK_SPARCLITE
);
1862 /* -mvis also implies -mv8plus on 32-bit. */
1863 if (TARGET_VIS
&& !TARGET_ARCH64
)
1864 target_flags
|= MASK_V8PLUS
;
1866 /* Use the deprecated v8 insns for sparc64 in 32-bit mode. */
1867 if (TARGET_V9
&& TARGET_ARCH32
)
1868 target_flags
|= MASK_DEPRECATED_V8_INSNS
;
1870 /* V8PLUS requires V9 and makes no sense in 64-bit mode. */
1871 if (!TARGET_V9
|| TARGET_ARCH64
)
1872 target_flags
&= ~MASK_V8PLUS
;
1874 /* Don't use stack biasing in 32-bit mode. */
1876 target_flags
&= ~MASK_STACK_BIAS
;
1878 /* Use LRA instead of reload, unless otherwise instructed. */
1879 if (!(target_flags_explicit
& MASK_LRA
))
1880 target_flags
|= MASK_LRA
;
1882 /* Enable applicable errata workarounds for LEON3FT. */
1883 if (sparc_fix_ut699
|| sparc_fix_ut700
|| sparc_fix_gr712rc
)
1885 sparc_fix_b2bst
= 1;
1886 sparc_fix_lost_divsqrt
= 1;
1889 /* Disable FsMULd for the UT699 since it doesn't work correctly. */
1890 if (sparc_fix_ut699
)
1891 target_flags
&= ~MASK_FSMULD
;
1893 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1894 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
1895 target_flags
|= MASK_LONG_DOUBLE_128
;
1898 if (TARGET_DEBUG_OPTIONS
)
1899 dump_target_flags ("Final target_flags", target_flags
);
1901 /* Set the code model if no -mcmodel option was specified. */
1902 if (global_options_set
.x_sparc_code_model
)
1905 error ("%<-mcmodel=%> is not supported in 32-bit mode");
1910 sparc_code_model
= CM_32
;
1912 sparc_code_model
= SPARC_DEFAULT_CMODEL
;
1915 /* Set the memory model if no -mmemory-model option was specified. */
1916 if (!global_options_set
.x_sparc_memory_model
)
1918 /* Choose the memory model for the operating system. */
1919 enum sparc_memory_model_type os_default
= SUBTARGET_DEFAULT_MEMORY_MODEL
;
1920 if (os_default
!= SMM_DEFAULT
)
1921 sparc_memory_model
= os_default
;
1922 /* Choose the most relaxed model for the processor. */
1924 sparc_memory_model
= SMM_RMO
;
1925 else if (TARGET_LEON3
)
1926 sparc_memory_model
= SMM_TSO
;
1927 else if (TARGET_LEON
)
1928 sparc_memory_model
= SMM_SC
;
1930 sparc_memory_model
= SMM_PSO
;
1932 sparc_memory_model
= SMM_SC
;
1935 /* Supply a default value for align_functions. */
1936 if (flag_align_functions
&& !str_align_functions
)
1938 if (sparc_cpu
== PROCESSOR_ULTRASPARC
1939 || sparc_cpu
== PROCESSOR_ULTRASPARC3
1940 || sparc_cpu
== PROCESSOR_NIAGARA
1941 || sparc_cpu
== PROCESSOR_NIAGARA2
1942 || sparc_cpu
== PROCESSOR_NIAGARA3
1943 || sparc_cpu
== PROCESSOR_NIAGARA4
)
1944 str_align_functions
= "32";
1945 else if (sparc_cpu
== PROCESSOR_NIAGARA7
1946 || sparc_cpu
== PROCESSOR_M8
)
1947 str_align_functions
= "64";
1950 /* Validate PCC_STRUCT_RETURN. */
1951 if (flag_pcc_struct_return
== DEFAULT_PCC_STRUCT_RETURN
)
1952 flag_pcc_struct_return
= (TARGET_ARCH64
? 0 : 1);
1954 /* Only use .uaxword when compiling for a 64-bit target. */
1956 targetm
.asm_out
.unaligned_op
.di
= NULL
;
1958 /* Set the processor costs. */
1962 case PROCESSOR_CYPRESS
:
1963 sparc_costs
= &cypress_costs
;
1966 case PROCESSOR_SPARCLITE
:
1967 case PROCESSOR_SUPERSPARC
:
1968 sparc_costs
= &supersparc_costs
;
1970 case PROCESSOR_F930
:
1971 case PROCESSOR_F934
:
1972 case PROCESSOR_HYPERSPARC
:
1973 case PROCESSOR_SPARCLITE86X
:
1974 sparc_costs
= &hypersparc_costs
;
1976 case PROCESSOR_LEON
:
1977 sparc_costs
= &leon_costs
;
1979 case PROCESSOR_LEON3
:
1980 case PROCESSOR_LEON3V7
:
1981 sparc_costs
= &leon3_costs
;
1983 case PROCESSOR_SPARCLET
:
1984 case PROCESSOR_TSC701
:
1985 sparc_costs
= &sparclet_costs
;
1988 case PROCESSOR_ULTRASPARC
:
1989 sparc_costs
= &ultrasparc_costs
;
1991 case PROCESSOR_ULTRASPARC3
:
1992 sparc_costs
= &ultrasparc3_costs
;
1994 case PROCESSOR_NIAGARA
:
1995 sparc_costs
= &niagara_costs
;
1997 case PROCESSOR_NIAGARA2
:
1998 sparc_costs
= &niagara2_costs
;
2000 case PROCESSOR_NIAGARA3
:
2001 sparc_costs
= &niagara3_costs
;
2003 case PROCESSOR_NIAGARA4
:
2004 sparc_costs
= &niagara4_costs
;
2006 case PROCESSOR_NIAGARA7
:
2007 sparc_costs
= &niagara7_costs
;
2010 sparc_costs
= &m8_costs
;
2012 case PROCESSOR_NATIVE
:
2016 /* PARAM_SIMULTANEOUS_PREFETCHES is the number of prefetches that
2017 can run at the same time. More important, it is the threshold
2018 defining when additional prefetches will be dropped by the
2021 The UltraSPARC-III features a documented prefetch queue with a
2022 size of 8. Additional prefetches issued in the cpu are
2025 Niagara processors are different. In these processors prefetches
2026 are handled much like regular loads. The L1 miss buffer is 32
2027 entries, but prefetches start getting affected when 30 entries
2028 become occupied. That occupation could be a mix of regular loads
2029 and prefetches though. And that buffer is shared by all threads.
2030 Once the threshold is reached, if the core is running a single
2031 thread the prefetch will retry. If more than one thread is
2032 running, the prefetch will be dropped.
2034 All this makes it very difficult to determine how many
2035 simultaneous prefetches can be issued simultaneously, even in a
2036 single-threaded program. Experimental results show that setting
2037 this parameter to 32 works well when the number of threads is not
2039 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
2040 ((sparc_cpu
== PROCESSOR_ULTRASPARC
2041 || sparc_cpu
== PROCESSOR_NIAGARA
2042 || sparc_cpu
== PROCESSOR_NIAGARA2
2043 || sparc_cpu
== PROCESSOR_NIAGARA3
2044 || sparc_cpu
== PROCESSOR_NIAGARA4
)
2046 : (sparc_cpu
== PROCESSOR_ULTRASPARC3
2047 ? 8 : ((sparc_cpu
== PROCESSOR_NIAGARA7
2048 || sparc_cpu
== PROCESSOR_M8
)
2050 global_options
.x_param_values
,
2051 global_options_set
.x_param_values
);
2053 /* PARAM_L1_CACHE_LINE_SIZE is the size of the L1 cache line, in
2056 The Oracle SPARC Architecture (previously the UltraSPARC
2057 Architecture) specification states that when a PREFETCH[A]
2058 instruction is executed an implementation-specific amount of data
2059 is prefetched, and that it is at least 64 bytes long (aligned to
2062 However, this is not correct. The M7 (and implementations prior
2063 to that) does not guarantee a 64B prefetch into a cache if the
2064 line size is smaller. A single cache line is all that is ever
2065 prefetched. So for the M7, where the L1D$ has 32B lines and the
2066 L2D$ and L3 have 64B lines, a prefetch will prefetch 64B into the
2067 L2 and L3, but only 32B are brought into the L1D$. (Assuming it
2068 is a read_n prefetch, which is the only type which allocates to
2070 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
2071 (sparc_cpu
== PROCESSOR_M8
2073 global_options
.x_param_values
,
2074 global_options_set
.x_param_values
);
2076 /* PARAM_L1_CACHE_SIZE is the size of the L1D$ (most SPARC chips use
2077 Hardvard level-1 caches) in kilobytes. Both UltraSPARC and
2078 Niagara processors feature a L1D$ of 16KB. */
2079 maybe_set_param_value (PARAM_L1_CACHE_SIZE
,
2080 ((sparc_cpu
== PROCESSOR_ULTRASPARC
2081 || sparc_cpu
== PROCESSOR_ULTRASPARC3
2082 || sparc_cpu
== PROCESSOR_NIAGARA
2083 || sparc_cpu
== PROCESSOR_NIAGARA2
2084 || sparc_cpu
== PROCESSOR_NIAGARA3
2085 || sparc_cpu
== PROCESSOR_NIAGARA4
2086 || sparc_cpu
== PROCESSOR_NIAGARA7
2087 || sparc_cpu
== PROCESSOR_M8
)
2089 global_options
.x_param_values
,
2090 global_options_set
.x_param_values
);
2093 /* PARAM_L2_CACHE_SIZE is the size fo the L2 in kilobytes. Note
2094 that 512 is the default in params.def. */
2095 maybe_set_param_value (PARAM_L2_CACHE_SIZE
,
2096 ((sparc_cpu
== PROCESSOR_NIAGARA4
2097 || sparc_cpu
== PROCESSOR_M8
)
2098 ? 128 : (sparc_cpu
== PROCESSOR_NIAGARA7
2100 global_options
.x_param_values
,
2101 global_options_set
.x_param_values
);
2104 /* Disable save slot sharing for call-clobbered registers by default.
2105 The IRA sharing algorithm works on single registers only and this
2106 pessimizes for double floating-point registers. */
2107 if (!global_options_set
.x_flag_ira_share_save_slots
)
2108 flag_ira_share_save_slots
= 0;
2110 /* Only enable REE by default in 64-bit mode where it helps to eliminate
2111 redundant 32-to-64-bit extensions. */
2112 if (!global_options_set
.x_flag_ree
&& TARGET_ARCH32
)
2115 /* Do various machine dependent initializations. */
2116 sparc_init_modes ();
2118 /* Set up function hooks. */
2119 init_machine_status
= sparc_init_machine_status
;
2122 /* Miscellaneous utilities. */
2124 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
2125 or branch on register contents instructions. */
2128 v9_regcmp_p (enum rtx_code code
)
2130 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
2131 || code
== LE
|| code
== GT
);
2134 /* Nonzero if OP is a floating point constant which can
2135 be loaded into an integer register using a single
2136 sethi instruction. */
2141 if (GET_CODE (op
) == CONST_DOUBLE
)
2145 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), i
);
2146 return !SPARC_SIMM13_P (i
) && SPARC_SETHI_P (i
);
2152 /* Nonzero if OP is a floating point constant which can
2153 be loaded into an integer register using a single
2159 if (GET_CODE (op
) == CONST_DOUBLE
)
2163 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), i
);
2164 return SPARC_SIMM13_P (i
);
2170 /* Nonzero if OP is a floating point constant which can
2171 be loaded into an integer register using a high/losum
2172 instruction sequence. */
2175 fp_high_losum_p (rtx op
)
2177 /* The constraints calling this should only be in
2178 SFmode move insns, so any constant which cannot
2179 be moved using a single insn will do. */
2180 if (GET_CODE (op
) == CONST_DOUBLE
)
2184 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), i
);
2185 return !SPARC_SIMM13_P (i
) && !SPARC_SETHI_P (i
);
2191 /* Return true if the address of LABEL can be loaded by means of the
2192 mov{si,di}_pic_label_ref patterns in PIC mode. */
2195 can_use_mov_pic_label_ref (rtx label
)
2197 /* VxWorks does not impose a fixed gap between segments; the run-time
2198 gap can be different from the object-file gap. We therefore can't
2199 assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
2200 are absolutely sure that X is in the same segment as the GOT.
2201 Unfortunately, the flexibility of linker scripts means that we
2202 can't be sure of that in general, so assume that GOT-relative
2203 accesses are never valid on VxWorks. */
2204 if (TARGET_VXWORKS_RTP
)
2207 /* Similarly, if the label is non-local, it might end up being placed
2208 in a different section than the current one; now mov_pic_label_ref
2209 requires the label and the code to be in the same section. */
2210 if (LABEL_REF_NONLOCAL_P (label
))
2213 /* Finally, if we are reordering basic blocks and partition into hot
2214 and cold sections, this might happen for any label. */
2215 if (flag_reorder_blocks_and_partition
)
2221 /* Expand a move instruction. Return true if all work is done. */
2224 sparc_expand_move (machine_mode mode
, rtx
*operands
)
2226 /* Handle sets of MEM first. */
2227 if (GET_CODE (operands
[0]) == MEM
)
2229 /* 0 is a register (or a pair of registers) on SPARC. */
2230 if (register_or_zero_operand (operands
[1], mode
))
2233 if (!reload_in_progress
)
2235 operands
[0] = validize_mem (operands
[0]);
2236 operands
[1] = force_reg (mode
, operands
[1]);
2240 /* Fix up TLS cases. */
2242 && CONSTANT_P (operands
[1])
2243 && sparc_tls_referenced_p (operands
[1]))
2245 operands
[1] = sparc_legitimize_tls_address (operands
[1]);
2249 /* Fix up PIC cases. */
2250 if (flag_pic
&& CONSTANT_P (operands
[1]))
2252 if (pic_address_needs_scratch (operands
[1]))
2253 operands
[1] = sparc_legitimize_pic_address (operands
[1], NULL_RTX
);
2255 /* We cannot use the mov{si,di}_pic_label_ref patterns in all cases. */
2256 if ((GET_CODE (operands
[1]) == LABEL_REF
2257 && can_use_mov_pic_label_ref (operands
[1]))
2258 || (GET_CODE (operands
[1]) == CONST
2259 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
2260 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
2261 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == CONST_INT
2262 && can_use_mov_pic_label_ref (XEXP (XEXP (operands
[1], 0), 0))))
2266 emit_insn (gen_movsi_pic_label_ref (operands
[0], operands
[1]));
2272 emit_insn (gen_movdi_pic_label_ref (operands
[0], operands
[1]));
2277 if (symbolic_operand (operands
[1], mode
))
2280 = sparc_legitimize_pic_address (operands
[1],
2282 ? operands
[0] : NULL_RTX
);
2287 /* If we are trying to toss an integer constant into FP registers,
2288 or loading a FP or vector constant, force it into memory. */
2289 if (CONSTANT_P (operands
[1])
2290 && REG_P (operands
[0])
2291 && (SPARC_FP_REG_P (REGNO (operands
[0]))
2292 || SCALAR_FLOAT_MODE_P (mode
)
2293 || VECTOR_MODE_P (mode
)))
2295 /* emit_group_store will send such bogosity to us when it is
2296 not storing directly into memory. So fix this up to avoid
2297 crashes in output_constant_pool. */
2298 if (operands
[1] == const0_rtx
)
2299 operands
[1] = CONST0_RTX (mode
);
2301 /* We can clear or set to all-ones FP registers if TARGET_VIS, and
2302 always other regs. */
2303 if ((TARGET_VIS
|| REGNO (operands
[0]) < SPARC_FIRST_FP_REG
)
2304 && (const_zero_operand (operands
[1], mode
)
2305 || const_all_ones_operand (operands
[1], mode
)))
2308 if (REGNO (operands
[0]) < SPARC_FIRST_FP_REG
2309 /* We are able to build any SF constant in integer registers
2310 with at most 2 instructions. */
2312 /* And any DF constant in integer registers if needed. */
2313 || (mode
== DFmode
&& !can_create_pseudo_p ())))
2316 operands
[1] = force_const_mem (mode
, operands
[1]);
2317 if (!reload_in_progress
)
2318 operands
[1] = validize_mem (operands
[1]);
2322 /* Accept non-constants and valid constants unmodified. */
2323 if (!CONSTANT_P (operands
[1])
2324 || GET_CODE (operands
[1]) == HIGH
2325 || input_operand (operands
[1], mode
))
2331 /* All QImode constants require only one insn, so proceed. */
2336 sparc_emit_set_const32 (operands
[0], operands
[1]);
2340 /* input_operand should have filtered out 32-bit mode. */
2341 sparc_emit_set_const64 (operands
[0], operands
[1]);
2347 /* TImode isn't available in 32-bit mode. */
2348 split_double (operands
[1], &high
, &low
);
2349 emit_insn (gen_movdi (operand_subword (operands
[0], 0, 0, TImode
),
2351 emit_insn (gen_movdi (operand_subword (operands
[0], 1, 0, TImode
),
2363 /* Load OP1, a 32-bit constant, into OP0, a register.
2364 We know it can't be done in one insn when we get
2365 here, the move expander guarantees this. */
2368 sparc_emit_set_const32 (rtx op0
, rtx op1
)
2370 machine_mode mode
= GET_MODE (op0
);
2373 if (can_create_pseudo_p ())
2374 temp
= gen_reg_rtx (mode
);
2376 if (GET_CODE (op1
) == CONST_INT
)
2378 gcc_assert (!small_int_operand (op1
, mode
)
2379 && !const_high_operand (op1
, mode
));
2381 /* Emit them as real moves instead of a HIGH/LO_SUM,
2382 this way CSE can see everything and reuse intermediate
2383 values if it wants. */
2384 emit_insn (gen_rtx_SET (temp
, GEN_INT (INTVAL (op1
)
2385 & ~(HOST_WIDE_INT
) 0x3ff)));
2387 emit_insn (gen_rtx_SET (op0
,
2388 gen_rtx_IOR (mode
, temp
,
2389 GEN_INT (INTVAL (op1
) & 0x3ff))));
2393 /* A symbol, emit in the traditional way. */
2394 emit_insn (gen_rtx_SET (temp
, gen_rtx_HIGH (mode
, op1
)));
2395 emit_insn (gen_rtx_SET (op0
, gen_rtx_LO_SUM (mode
, temp
, op1
)));
2399 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
2400 If TEMP is nonzero, we are forbidden to use any other scratch
2401 registers. Otherwise, we are allowed to generate them as needed.
2403 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
2404 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
2407 sparc_emit_set_symbolic_const64 (rtx op0
, rtx op1
, rtx temp
)
2409 rtx cst
, temp1
, temp2
, temp3
, temp4
, temp5
;
2412 /* Deal with too large offsets. */
2413 if (GET_CODE (op1
) == CONST
2414 && GET_CODE (XEXP (op1
, 0)) == PLUS
2415 && CONST_INT_P (cst
= XEXP (XEXP (op1
, 0), 1))
2416 && trunc_int_for_mode (INTVAL (cst
), SImode
) != INTVAL (cst
))
2419 temp1
= gen_reg_rtx (DImode
);
2420 temp2
= gen_reg_rtx (DImode
);
2421 sparc_emit_set_const64 (temp2
, cst
);
2422 sparc_emit_set_symbolic_const64 (temp1
, XEXP (XEXP (op1
, 0), 0),
2424 emit_insn (gen_rtx_SET (op0
, gen_rtx_PLUS (DImode
, temp1
, temp2
)));
2428 if (temp
&& GET_MODE (temp
) == TImode
)
2431 temp
= gen_rtx_REG (DImode
, REGNO (temp
));
2434 /* SPARC-V9 code model support. */
2435 switch (sparc_code_model
)
2438 /* The range spanned by all instructions in the object is less
2439 than 2^31 bytes (2GB) and the distance from any instruction
2440 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
2441 than 2^31 bytes (2GB).
2443 The executable must be in the low 4TB of the virtual address
2446 sethi %hi(symbol), %temp1
2447 or %temp1, %lo(symbol), %reg */
2449 temp1
= temp
; /* op0 is allowed. */
2451 temp1
= gen_reg_rtx (DImode
);
2453 emit_insn (gen_rtx_SET (temp1
, gen_rtx_HIGH (DImode
, op1
)));
2454 emit_insn (gen_rtx_SET (op0
, gen_rtx_LO_SUM (DImode
, temp1
, op1
)));
2458 /* The range spanned by all instructions in the object is less
2459 than 2^31 bytes (2GB) and the distance from any instruction
2460 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
2461 than 2^31 bytes (2GB).
2463 The executable must be in the low 16TB of the virtual address
2466 sethi %h44(symbol), %temp1
2467 or %temp1, %m44(symbol), %temp2
2468 sllx %temp2, 12, %temp3
2469 or %temp3, %l44(symbol), %reg */
2474 temp3
= temp
; /* op0 is allowed. */
2478 temp1
= gen_reg_rtx (DImode
);
2479 temp2
= gen_reg_rtx (DImode
);
2480 temp3
= gen_reg_rtx (DImode
);
2483 emit_insn (gen_seth44 (temp1
, op1
));
2484 emit_insn (gen_setm44 (temp2
, temp1
, op1
));
2485 emit_insn (gen_rtx_SET (temp3
,
2486 gen_rtx_ASHIFT (DImode
, temp2
, GEN_INT (12))));
2487 emit_insn (gen_setl44 (op0
, temp3
, op1
));
2491 /* The range spanned by all instructions in the object is less
2492 than 2^31 bytes (2GB) and the distance from any instruction
2493 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
2494 than 2^31 bytes (2GB).
2496 The executable can be placed anywhere in the virtual address
2499 sethi %hh(symbol), %temp1
2500 sethi %lm(symbol), %temp2
2501 or %temp1, %hm(symbol), %temp3
2502 sllx %temp3, 32, %temp4
2503 or %temp4, %temp2, %temp5
2504 or %temp5, %lo(symbol), %reg */
2507 /* It is possible that one of the registers we got for operands[2]
2508 might coincide with that of operands[0] (which is why we made
2509 it TImode). Pick the other one to use as our scratch. */
2510 if (rtx_equal_p (temp
, op0
))
2512 gcc_assert (ti_temp
);
2513 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
2516 temp2
= temp
; /* op0 is _not_ allowed, see above. */
2523 temp1
= gen_reg_rtx (DImode
);
2524 temp2
= gen_reg_rtx (DImode
);
2525 temp3
= gen_reg_rtx (DImode
);
2526 temp4
= gen_reg_rtx (DImode
);
2527 temp5
= gen_reg_rtx (DImode
);
2530 emit_insn (gen_sethh (temp1
, op1
));
2531 emit_insn (gen_setlm (temp2
, op1
));
2532 emit_insn (gen_sethm (temp3
, temp1
, op1
));
2533 emit_insn (gen_rtx_SET (temp4
,
2534 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
2535 emit_insn (gen_rtx_SET (temp5
, gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2536 emit_insn (gen_setlo (op0
, temp5
, op1
));
2540 /* Old old old backwards compatibility kruft here.
2541 Essentially it is MEDLOW with a fixed 64-bit
2542 virtual base added to all data segment addresses.
2543 Text-segment stuff is computed like MEDANY, we can't
2544 reuse the code above because the relocation knobs
2547 Data segment: sethi %hi(symbol), %temp1
2548 add %temp1, EMBMEDANY_BASE_REG, %temp2
2549 or %temp2, %lo(symbol), %reg */
2550 if (data_segment_operand (op1
, GET_MODE (op1
)))
2554 temp1
= temp
; /* op0 is allowed. */
2559 temp1
= gen_reg_rtx (DImode
);
2560 temp2
= gen_reg_rtx (DImode
);
2563 emit_insn (gen_embmedany_sethi (temp1
, op1
));
2564 emit_insn (gen_embmedany_brsum (temp2
, temp1
));
2565 emit_insn (gen_embmedany_losum (op0
, temp2
, op1
));
2568 /* Text segment: sethi %uhi(symbol), %temp1
2569 sethi %hi(symbol), %temp2
2570 or %temp1, %ulo(symbol), %temp3
2571 sllx %temp3, 32, %temp4
2572 or %temp4, %temp2, %temp5
2573 or %temp5, %lo(symbol), %reg */
2578 /* It is possible that one of the registers we got for operands[2]
2579 might coincide with that of operands[0] (which is why we made
2580 it TImode). Pick the other one to use as our scratch. */
2581 if (rtx_equal_p (temp
, op0
))
2583 gcc_assert (ti_temp
);
2584 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
2587 temp2
= temp
; /* op0 is _not_ allowed, see above. */
2594 temp1
= gen_reg_rtx (DImode
);
2595 temp2
= gen_reg_rtx (DImode
);
2596 temp3
= gen_reg_rtx (DImode
);
2597 temp4
= gen_reg_rtx (DImode
);
2598 temp5
= gen_reg_rtx (DImode
);
2601 emit_insn (gen_embmedany_textuhi (temp1
, op1
));
2602 emit_insn (gen_embmedany_texthi (temp2
, op1
));
2603 emit_insn (gen_embmedany_textulo (temp3
, temp1
, op1
));
2604 emit_insn (gen_rtx_SET (temp4
,
2605 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
2606 emit_insn (gen_rtx_SET (temp5
, gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2607 emit_insn (gen_embmedany_textlo (op0
, temp5
, op1
));
2616 /* These avoid problems when cross compiling. If we do not
2617 go through all this hair then the optimizer will see
2618 invalid REG_EQUAL notes or in some cases none at all. */
2619 static rtx
gen_safe_HIGH64 (rtx
, HOST_WIDE_INT
);
2620 static rtx
gen_safe_SET64 (rtx
, HOST_WIDE_INT
);
2621 static rtx
gen_safe_OR64 (rtx
, HOST_WIDE_INT
);
2622 static rtx
gen_safe_XOR64 (rtx
, HOST_WIDE_INT
);
2624 /* The optimizer is not to assume anything about exactly
2625 which bits are set for a HIGH, they are unspecified.
2626 Unfortunately this leads to many missed optimizations
2627 during CSE. We mask out the non-HIGH bits, and matches
2628 a plain movdi, to alleviate this problem. */
2630 gen_safe_HIGH64 (rtx dest
, HOST_WIDE_INT val
)
2632 return gen_rtx_SET (dest
, GEN_INT (val
& ~(HOST_WIDE_INT
)0x3ff));
2636 gen_safe_SET64 (rtx dest
, HOST_WIDE_INT val
)
2638 return gen_rtx_SET (dest
, GEN_INT (val
));
2642 gen_safe_OR64 (rtx src
, HOST_WIDE_INT val
)
2644 return gen_rtx_IOR (DImode
, src
, GEN_INT (val
));
2648 gen_safe_XOR64 (rtx src
, HOST_WIDE_INT val
)
2650 return gen_rtx_XOR (DImode
, src
, GEN_INT (val
));
2653 /* Worker routines for 64-bit constant formation on arch64.
2654 One of the key things to be doing in these emissions is
2655 to create as many temp REGs as possible. This makes it
2656 possible for half-built constants to be used later when
2657 such values are similar to something required later on.
2658 Without doing this, the optimizer cannot see such
2661 static void sparc_emit_set_const64_quick1 (rtx
, rtx
,
2662 unsigned HOST_WIDE_INT
, int);
2665 sparc_emit_set_const64_quick1 (rtx op0
, rtx temp
,
2666 unsigned HOST_WIDE_INT low_bits
, int is_neg
)
2668 unsigned HOST_WIDE_INT high_bits
;
2671 high_bits
= (~low_bits
) & 0xffffffff;
2673 high_bits
= low_bits
;
2675 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
2678 emit_insn (gen_rtx_SET (op0
, gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2682 /* If we are XOR'ing with -1, then we should emit a one's complement
2683 instead. This way the combiner will notice logical operations
2684 such as ANDN later on and substitute. */
2685 if ((low_bits
& 0x3ff) == 0x3ff)
2687 emit_insn (gen_rtx_SET (op0
, gen_rtx_NOT (DImode
, temp
)));
2691 emit_insn (gen_rtx_SET (op0
,
2692 gen_safe_XOR64 (temp
,
2693 (-(HOST_WIDE_INT
)0x400
2694 | (low_bits
& 0x3ff)))));
2699 static void sparc_emit_set_const64_quick2 (rtx
, rtx
, unsigned HOST_WIDE_INT
,
2700 unsigned HOST_WIDE_INT
, int);
2703 sparc_emit_set_const64_quick2 (rtx op0
, rtx temp
,
2704 unsigned HOST_WIDE_INT high_bits
,
2705 unsigned HOST_WIDE_INT low_immediate
,
2710 if ((high_bits
& 0xfffffc00) != 0)
2712 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
2713 if ((high_bits
& ~0xfffffc00) != 0)
2714 emit_insn (gen_rtx_SET (op0
,
2715 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2721 emit_insn (gen_safe_SET64 (temp
, high_bits
));
2725 /* Now shift it up into place. */
2726 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, temp2
,
2727 GEN_INT (shift_count
))));
2729 /* If there is a low immediate part piece, finish up by
2730 putting that in as well. */
2731 if (low_immediate
!= 0)
2732 emit_insn (gen_rtx_SET (op0
, gen_safe_OR64 (op0
, low_immediate
)));
2735 static void sparc_emit_set_const64_longway (rtx
, rtx
, unsigned HOST_WIDE_INT
,
2736 unsigned HOST_WIDE_INT
);
2738 /* Full 64-bit constant decomposition. Even though this is the
2739 'worst' case, we still optimize a few things away. */
2741 sparc_emit_set_const64_longway (rtx op0
, rtx temp
,
2742 unsigned HOST_WIDE_INT high_bits
,
2743 unsigned HOST_WIDE_INT low_bits
)
2747 if (can_create_pseudo_p ())
2748 sub_temp
= gen_reg_rtx (DImode
);
2750 if ((high_bits
& 0xfffffc00) != 0)
2752 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
2753 if ((high_bits
& ~0xfffffc00) != 0)
2754 emit_insn (gen_rtx_SET (sub_temp
,
2755 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2761 emit_insn (gen_safe_SET64 (temp
, high_bits
));
2765 if (can_create_pseudo_p ())
2767 rtx temp2
= gen_reg_rtx (DImode
);
2768 rtx temp3
= gen_reg_rtx (DImode
);
2769 rtx temp4
= gen_reg_rtx (DImode
);
2771 emit_insn (gen_rtx_SET (temp4
, gen_rtx_ASHIFT (DImode
, sub_temp
,
2774 emit_insn (gen_safe_HIGH64 (temp2
, low_bits
));
2775 if ((low_bits
& ~0xfffffc00) != 0)
2777 emit_insn (gen_rtx_SET (temp3
,
2778 gen_safe_OR64 (temp2
, (low_bits
& 0x3ff))));
2779 emit_insn (gen_rtx_SET (op0
, gen_rtx_PLUS (DImode
, temp4
, temp3
)));
2783 emit_insn (gen_rtx_SET (op0
, gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2788 rtx low1
= GEN_INT ((low_bits
>> (32 - 12)) & 0xfff);
2789 rtx low2
= GEN_INT ((low_bits
>> (32 - 12 - 12)) & 0xfff);
2790 rtx low3
= GEN_INT ((low_bits
>> (32 - 12 - 12 - 8)) & 0x0ff);
2793 /* We are in the middle of reload, so this is really
2794 painful. However we do still make an attempt to
2795 avoid emitting truly stupid code. */
2796 if (low1
!= const0_rtx
)
2798 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, sub_temp
,
2799 GEN_INT (to_shift
))));
2800 emit_insn (gen_rtx_SET (op0
, gen_rtx_IOR (DImode
, op0
, low1
)));
2808 if (low2
!= const0_rtx
)
2810 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, sub_temp
,
2811 GEN_INT (to_shift
))));
2812 emit_insn (gen_rtx_SET (op0
, gen_rtx_IOR (DImode
, op0
, low2
)));
2820 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, sub_temp
,
2821 GEN_INT (to_shift
))));
2822 if (low3
!= const0_rtx
)
2823 emit_insn (gen_rtx_SET (op0
, gen_rtx_IOR (DImode
, op0
, low3
)));
2828 /* Analyze a 64-bit constant for certain properties. */
2829 static void analyze_64bit_constant (unsigned HOST_WIDE_INT
,
2830 unsigned HOST_WIDE_INT
,
2831 int *, int *, int *);
2834 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits
,
2835 unsigned HOST_WIDE_INT low_bits
,
2836 int *hbsp
, int *lbsp
, int *abbasp
)
2838 int lowest_bit_set
, highest_bit_set
, all_bits_between_are_set
;
2841 lowest_bit_set
= highest_bit_set
= -1;
2845 if ((lowest_bit_set
== -1)
2846 && ((low_bits
>> i
) & 1))
2848 if ((highest_bit_set
== -1)
2849 && ((high_bits
>> (32 - i
- 1)) & 1))
2850 highest_bit_set
= (64 - i
- 1);
2853 && ((highest_bit_set
== -1)
2854 || (lowest_bit_set
== -1)));
2860 if ((lowest_bit_set
== -1)
2861 && ((high_bits
>> i
) & 1))
2862 lowest_bit_set
= i
+ 32;
2863 if ((highest_bit_set
== -1)
2864 && ((low_bits
>> (32 - i
- 1)) & 1))
2865 highest_bit_set
= 32 - i
- 1;
2868 && ((highest_bit_set
== -1)
2869 || (lowest_bit_set
== -1)));
2871 /* If there are no bits set this should have gone out
2872 as one instruction! */
2873 gcc_assert (lowest_bit_set
!= -1 && highest_bit_set
!= -1);
2874 all_bits_between_are_set
= 1;
2875 for (i
= lowest_bit_set
; i
<= highest_bit_set
; i
++)
2879 if ((low_bits
& (1 << i
)) != 0)
2884 if ((high_bits
& (1 << (i
- 32))) != 0)
2887 all_bits_between_are_set
= 0;
2890 *hbsp
= highest_bit_set
;
2891 *lbsp
= lowest_bit_set
;
2892 *abbasp
= all_bits_between_are_set
;
2895 static int const64_is_2insns (unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
);
2898 const64_is_2insns (unsigned HOST_WIDE_INT high_bits
,
2899 unsigned HOST_WIDE_INT low_bits
)
2901 int highest_bit_set
, lowest_bit_set
, all_bits_between_are_set
;
2904 || high_bits
== 0xffffffff)
2907 analyze_64bit_constant (high_bits
, low_bits
,
2908 &highest_bit_set
, &lowest_bit_set
,
2909 &all_bits_between_are_set
);
2911 if ((highest_bit_set
== 63
2912 || lowest_bit_set
== 0)
2913 && all_bits_between_are_set
!= 0)
2916 if ((highest_bit_set
- lowest_bit_set
) < 21)
2922 static unsigned HOST_WIDE_INT
create_simple_focus_bits (unsigned HOST_WIDE_INT
,
2923 unsigned HOST_WIDE_INT
,
2926 static unsigned HOST_WIDE_INT
2927 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits
,
2928 unsigned HOST_WIDE_INT low_bits
,
2929 int lowest_bit_set
, int shift
)
2931 HOST_WIDE_INT hi
, lo
;
2933 if (lowest_bit_set
< 32)
2935 lo
= (low_bits
>> lowest_bit_set
) << shift
;
2936 hi
= ((high_bits
<< (32 - lowest_bit_set
)) << shift
);
2941 hi
= ((high_bits
>> (lowest_bit_set
- 32)) << shift
);
2943 gcc_assert (! (hi
& lo
));
2947 /* Here we are sure to be arch64 and this is an integer constant
2948 being loaded into a register. Emit the most efficient
2949 insn sequence possible. Detection of all the 1-insn cases
2950 has been done already. */
2952 sparc_emit_set_const64 (rtx op0
, rtx op1
)
2954 unsigned HOST_WIDE_INT high_bits
, low_bits
;
2955 int lowest_bit_set
, highest_bit_set
;
2956 int all_bits_between_are_set
;
2959 /* Sanity check that we know what we are working with. */
2960 gcc_assert (TARGET_ARCH64
2961 && (GET_CODE (op0
) == SUBREG
2962 || (REG_P (op0
) && ! SPARC_FP_REG_P (REGNO (op0
)))));
2964 if (! can_create_pseudo_p ())
2967 if (GET_CODE (op1
) != CONST_INT
)
2969 sparc_emit_set_symbolic_const64 (op0
, op1
, temp
);
2974 temp
= gen_reg_rtx (DImode
);
2976 high_bits
= ((INTVAL (op1
) >> 32) & 0xffffffff);
2977 low_bits
= (INTVAL (op1
) & 0xffffffff);
2979 /* low_bits bits 0 --> 31
2980 high_bits bits 32 --> 63 */
2982 analyze_64bit_constant (high_bits
, low_bits
,
2983 &highest_bit_set
, &lowest_bit_set
,
2984 &all_bits_between_are_set
);
2986 /* First try for a 2-insn sequence. */
2988 /* These situations are preferred because the optimizer can
2989 * do more things with them:
2991 * sllx %reg, shift, %reg
2993 * srlx %reg, shift, %reg
2994 * 3) mov some_small_const, %reg
2995 * sllx %reg, shift, %reg
2997 if (((highest_bit_set
== 63
2998 || lowest_bit_set
== 0)
2999 && all_bits_between_are_set
!= 0)
3000 || ((highest_bit_set
- lowest_bit_set
) < 12))
3002 HOST_WIDE_INT the_const
= -1;
3003 int shift
= lowest_bit_set
;
3005 if ((highest_bit_set
!= 63
3006 && lowest_bit_set
!= 0)
3007 || all_bits_between_are_set
== 0)
3010 create_simple_focus_bits (high_bits
, low_bits
,
3013 else if (lowest_bit_set
== 0)
3014 shift
= -(63 - highest_bit_set
);
3016 gcc_assert (SPARC_SIMM13_P (the_const
));
3017 gcc_assert (shift
!= 0);
3019 emit_insn (gen_safe_SET64 (temp
, the_const
));
3021 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, temp
,
3024 emit_insn (gen_rtx_SET (op0
, gen_rtx_LSHIFTRT (DImode
, temp
,
3025 GEN_INT (-shift
))));
3029 /* Now a range of 22 or less bits set somewhere.
3030 * 1) sethi %hi(focus_bits), %reg
3031 * sllx %reg, shift, %reg
3032 * 2) sethi %hi(focus_bits), %reg
3033 * srlx %reg, shift, %reg
3035 if ((highest_bit_set
- lowest_bit_set
) < 21)
3037 unsigned HOST_WIDE_INT focus_bits
=
3038 create_simple_focus_bits (high_bits
, low_bits
,
3039 lowest_bit_set
, 10);
3041 gcc_assert (SPARC_SETHI_P (focus_bits
));
3042 gcc_assert (lowest_bit_set
!= 10);
3044 emit_insn (gen_safe_HIGH64 (temp
, focus_bits
));
3046 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
3047 if (lowest_bit_set
< 10)
3048 emit_insn (gen_rtx_SET (op0
,
3049 gen_rtx_LSHIFTRT (DImode
, temp
,
3050 GEN_INT (10 - lowest_bit_set
))));
3051 else if (lowest_bit_set
> 10)
3052 emit_insn (gen_rtx_SET (op0
,
3053 gen_rtx_ASHIFT (DImode
, temp
,
3054 GEN_INT (lowest_bit_set
- 10))));
3058 /* 1) sethi %hi(low_bits), %reg
3059 * or %reg, %lo(low_bits), %reg
3060 * 2) sethi %hi(~low_bits), %reg
3061 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
3064 || high_bits
== 0xffffffff)
3066 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
,
3067 (high_bits
== 0xffffffff));
3071 /* Now, try 3-insn sequences. */
3073 /* 1) sethi %hi(high_bits), %reg
3074 * or %reg, %lo(high_bits), %reg
3075 * sllx %reg, 32, %reg
3079 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, 0, 32);
3083 /* We may be able to do something quick
3084 when the constant is negated, so try that. */
3085 if (const64_is_2insns ((~high_bits
) & 0xffffffff,
3086 (~low_bits
) & 0xfffffc00))
3088 /* NOTE: The trailing bits get XOR'd so we need the
3089 non-negated bits, not the negated ones. */
3090 unsigned HOST_WIDE_INT trailing_bits
= low_bits
& 0x3ff;
3092 if ((((~high_bits
) & 0xffffffff) == 0
3093 && ((~low_bits
) & 0x80000000) == 0)
3094 || (((~high_bits
) & 0xffffffff) == 0xffffffff
3095 && ((~low_bits
) & 0x80000000) != 0))
3097 unsigned HOST_WIDE_INT fast_int
= (~low_bits
& 0xffffffff);
3099 if ((SPARC_SETHI_P (fast_int
)
3100 && (~high_bits
& 0xffffffff) == 0)
3101 || SPARC_SIMM13_P (fast_int
))
3102 emit_insn (gen_safe_SET64 (temp
, fast_int
));
3104 sparc_emit_set_const64 (temp
, GEN_INT (fast_int
));
3109 negated_const
= GEN_INT (((~low_bits
) & 0xfffffc00) |
3110 (((HOST_WIDE_INT
)((~high_bits
) & 0xffffffff))<<32));
3111 sparc_emit_set_const64 (temp
, negated_const
);
3114 /* If we are XOR'ing with -1, then we should emit a one's complement
3115 instead. This way the combiner will notice logical operations
3116 such as ANDN later on and substitute. */
3117 if (trailing_bits
== 0x3ff)
3119 emit_insn (gen_rtx_SET (op0
, gen_rtx_NOT (DImode
, temp
)));
3123 emit_insn (gen_rtx_SET (op0
,
3124 gen_safe_XOR64 (temp
,
3125 (-0x400 | trailing_bits
))));
3130 /* 1) sethi %hi(xxx), %reg
3131 * or %reg, %lo(xxx), %reg
3132 * sllx %reg, yyy, %reg
3134 * ??? This is just a generalized version of the low_bits==0
3135 * thing above, FIXME...
3137 if ((highest_bit_set
- lowest_bit_set
) < 32)
3139 unsigned HOST_WIDE_INT focus_bits
=
3140 create_simple_focus_bits (high_bits
, low_bits
,
3143 /* We can't get here in this state. */
3144 gcc_assert (highest_bit_set
>= 32 && lowest_bit_set
< 32);
3146 /* So what we know is that the set bits straddle the
3147 middle of the 64-bit word. */
3148 sparc_emit_set_const64_quick2 (op0
, temp
,
3154 /* 1) sethi %hi(high_bits), %reg
3155 * or %reg, %lo(high_bits), %reg
3156 * sllx %reg, 32, %reg
3157 * or %reg, low_bits, %reg
3159 if (SPARC_SIMM13_P (low_bits
) && ((int)low_bits
> 0))
3161 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_bits
, 32);
3165 /* The easiest way when all else fails, is full decomposition. */
3166 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
);
3169 /* Implement TARGET_FIXED_CONDITION_CODE_REGS. */
3172 sparc_fixed_condition_code_regs (unsigned int *p1
, unsigned int *p2
)
3174 *p1
= SPARC_ICC_REG
;
3175 *p2
= SPARC_FCC_REG
;
3179 /* Implement TARGET_MIN_ARITHMETIC_PRECISION. */
3182 sparc_min_arithmetic_precision (void)
3187 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
3188 return the mode to be used for the comparison. For floating-point,
3189 CCFP[E]mode is used. CCNZmode should be used when the first operand
3190 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
3191 processing is needed. */
3194 select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
3196 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
3222 else if ((GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
3223 || GET_CODE (x
) == NEG
|| GET_CODE (x
) == ASHIFT
)
3226 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
3233 /* This is for the cmp<mode>_sne pattern. */
3234 if (GET_CODE (x
) == NOT
&& y
== constm1_rtx
)
3236 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
3242 /* This is for the [u]addvdi4_sp32 and [u]subvdi4_sp32 patterns. */
3243 if (!TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
3245 if (GET_CODE (y
) == UNSPEC
3246 && (XINT (y
, 1) == UNSPEC_ADDV
3247 || XINT (y
, 1) == UNSPEC_SUBV
3248 || XINT (y
, 1) == UNSPEC_NEGV
))
3254 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
3261 /* Emit the compare insn and return the CC reg for a CODE comparison
3262 with operands X and Y. */
3265 gen_compare_reg_1 (enum rtx_code code
, rtx x
, rtx y
)
3270 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
3273 mode
= SELECT_CC_MODE (code
, x
, y
);
3275 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
3276 fcc regs (cse can't tell they're really call clobbered regs and will
3277 remove a duplicate comparison even if there is an intervening function
3278 call - it will then try to reload the cc reg via an int reg which is why
3279 we need the movcc patterns). It is possible to provide the movcc
3280 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
3281 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
3282 to tell cse that CCFPE mode registers (even pseudos) are call
3285 /* ??? This is an experiment. Rather than making changes to cse which may
3286 or may not be easy/clean, we do our own cse. This is possible because
3287 we will generate hard registers. Cse knows they're call clobbered (it
3288 doesn't know the same thing about pseudos). If we guess wrong, no big
3289 deal, but if we win, great! */
3291 if (TARGET_V9
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
3292 #if 1 /* experiment */
3295 /* We cycle through the registers to ensure they're all exercised. */
3296 static int next_fcc_reg
= 0;
3297 /* Previous x,y for each fcc reg. */
3298 static rtx prev_args
[4][2];
3300 /* Scan prev_args for x,y. */
3301 for (reg
= 0; reg
< 4; reg
++)
3302 if (prev_args
[reg
][0] == x
&& prev_args
[reg
][1] == y
)
3307 prev_args
[reg
][0] = x
;
3308 prev_args
[reg
][1] = y
;
3309 next_fcc_reg
= (next_fcc_reg
+ 1) & 3;
3311 cc_reg
= gen_rtx_REG (mode
, reg
+ SPARC_FIRST_V9_FCC_REG
);
3314 cc_reg
= gen_reg_rtx (mode
);
3315 #endif /* ! experiment */
3316 else if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
3317 cc_reg
= gen_rtx_REG (mode
, SPARC_FCC_REG
);
3319 cc_reg
= gen_rtx_REG (mode
, SPARC_ICC_REG
);
3321 /* We shouldn't get there for TFmode if !TARGET_HARD_QUAD. If we do, this
3322 will only result in an unrecognizable insn so no point in asserting. */
3323 emit_insn (gen_rtx_SET (cc_reg
, gen_rtx_COMPARE (mode
, x
, y
)));
3329 /* Emit the compare insn and return the CC reg for the comparison in CMP. */
3332 gen_compare_reg (rtx cmp
)
3334 return gen_compare_reg_1 (GET_CODE (cmp
), XEXP (cmp
, 0), XEXP (cmp
, 1));
3337 /* This function is used for v9 only.
3338 DEST is the target of the Scc insn.
3339 CODE is the code for an Scc's comparison.
3340 X and Y are the values we compare.
3342 This function is needed to turn
3345 (gt (reg:CCX 100 %icc)
3349 (gt:DI (reg:CCX 100 %icc)
3352 IE: The instruction recognizer needs to see the mode of the comparison to
3353 find the right instruction. We could use "gt:DI" right in the
3354 define_expand, but leaving it out allows us to handle DI, SI, etc. */
3357 gen_v9_scc (rtx dest
, enum rtx_code compare_code
, rtx x
, rtx y
)
3360 && (GET_MODE (x
) == DImode
3361 || GET_MODE (dest
) == DImode
))
3364 /* Try to use the movrCC insns. */
3366 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
3368 && v9_regcmp_p (compare_code
))
3373 /* Special case for op0 != 0. This can be done with one instruction if
3376 if (compare_code
== NE
3377 && GET_MODE (dest
) == DImode
3378 && rtx_equal_p (op0
, dest
))
3380 emit_insn (gen_rtx_SET (dest
,
3381 gen_rtx_IF_THEN_ELSE (DImode
,
3382 gen_rtx_fmt_ee (compare_code
, DImode
,
3389 if (reg_overlap_mentioned_p (dest
, op0
))
3391 /* Handle the case where dest == x.
3392 We "early clobber" the result. */
3393 op0
= gen_reg_rtx (GET_MODE (x
));
3394 emit_move_insn (op0
, x
);
3397 emit_insn (gen_rtx_SET (dest
, const0_rtx
));
3398 if (GET_MODE (op0
) != DImode
)
3400 temp
= gen_reg_rtx (DImode
);
3401 convert_move (temp
, op0
, 0);
3405 emit_insn (gen_rtx_SET (dest
,
3406 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
3407 gen_rtx_fmt_ee (compare_code
, DImode
,
3415 x
= gen_compare_reg_1 (compare_code
, x
, y
);
3418 emit_insn (gen_rtx_SET (dest
, const0_rtx
));
3419 emit_insn (gen_rtx_SET (dest
,
3420 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
3421 gen_rtx_fmt_ee (compare_code
,
3422 GET_MODE (x
), x
, y
),
3423 const1_rtx
, dest
)));
3429 /* Emit an scc insn. For seq, sne, sgeu, and sltu, we can do this
3430 without jumps using the addx/subx instructions. */
3433 emit_scc_insn (rtx operands
[])
3439 /* The quad-word fp compare library routines all return nonzero to indicate
3440 true, which is different from the equivalent libgcc routines, so we must
3441 handle them specially here. */
3442 if (GET_MODE (operands
[2]) == TFmode
&& ! TARGET_HARD_QUAD
)
3444 operands
[1] = sparc_emit_float_lib_cmp (operands
[2], operands
[3],
3445 GET_CODE (operands
[1]));
3446 operands
[2] = XEXP (operands
[1], 0);
3447 operands
[3] = XEXP (operands
[1], 1);
3450 code
= GET_CODE (operands
[1]);
3453 mode
= GET_MODE (x
);
3455 /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has
3456 more applications). The exception to this is "reg != 0" which can
3457 be done in one instruction on v9 (so we do it). */
3458 if ((code
== EQ
|| code
== NE
) && (mode
== SImode
|| mode
== DImode
))
3460 if (y
!= const0_rtx
)
3461 x
= force_reg (mode
, gen_rtx_XOR (mode
, x
, y
));
3463 rtx pat
= gen_rtx_SET (operands
[0],
3464 gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
3467 /* If we can use addx/subx or addxc, add a clobber for CC. */
3468 if (mode
== SImode
|| (code
== NE
&& TARGET_VIS3
))
3471 = gen_rtx_CLOBBER (VOIDmode
,
3472 gen_rtx_REG (mode
== SImode
? CCmode
: CCXmode
,
3474 pat
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, pat
, clobber
));
3481 /* We can do LTU in DImode using the addxc instruction with VIS3. */
3484 && !((code
== LTU
|| code
== GTU
) && TARGET_VIS3
)
3485 && gen_v9_scc (operands
[0], code
, x
, y
))
3488 /* We can do LTU and GEU using the addx/subx instructions too. And
3489 for GTU/LEU, if both operands are registers swap them and fall
3490 back to the easy case. */
3491 if (code
== GTU
|| code
== LEU
)
3493 if ((GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
3494 && (GET_CODE (y
) == REG
|| GET_CODE (y
) == SUBREG
))
3499 code
= swap_condition (code
);
3503 if (code
== LTU
|| code
== GEU
)
3505 emit_insn (gen_rtx_SET (operands
[0],
3506 gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
3507 gen_compare_reg_1 (code
, x
, y
),
3512 /* All the posibilities to use addx/subx based sequences has been
3513 exhausted, try for a 3 instruction sequence using v9 conditional
3515 if (TARGET_V9
&& gen_v9_scc (operands
[0], code
, x
, y
))
3518 /* Nope, do branches. */
3522 /* Emit a conditional jump insn for the v9 architecture using comparison code
3523 CODE and jump target LABEL.
3524 This function exists to take advantage of the v9 brxx insns. */
3527 emit_v9_brxx_insn (enum rtx_code code
, rtx op0
, rtx label
)
3529 emit_jump_insn (gen_rtx_SET (pc_rtx
,
3530 gen_rtx_IF_THEN_ELSE (VOIDmode
,
3531 gen_rtx_fmt_ee (code
, GET_MODE (op0
),
3533 gen_rtx_LABEL_REF (VOIDmode
, label
),
3537 /* Emit a conditional jump insn for the UA2011 architecture using
3538 comparison code CODE and jump target LABEL. This function exists
3539 to take advantage of the UA2011 Compare and Branch insns. */
3542 emit_cbcond_insn (enum rtx_code code
, rtx op0
, rtx op1
, rtx label
)
3546 if_then_else
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
3547 gen_rtx_fmt_ee(code
, GET_MODE(op0
),
3549 gen_rtx_LABEL_REF (VOIDmode
, label
),
3552 emit_jump_insn (gen_rtx_SET (pc_rtx
, if_then_else
));
3556 emit_conditional_branch_insn (rtx operands
[])
3558 /* The quad-word fp compare library routines all return nonzero to indicate
3559 true, which is different from the equivalent libgcc routines, so we must
3560 handle them specially here. */
3561 if (GET_MODE (operands
[1]) == TFmode
&& ! TARGET_HARD_QUAD
)
3563 operands
[0] = sparc_emit_float_lib_cmp (operands
[1], operands
[2],
3564 GET_CODE (operands
[0]));
3565 operands
[1] = XEXP (operands
[0], 0);
3566 operands
[2] = XEXP (operands
[0], 1);
3569 /* If we can tell early on that the comparison is against a constant
3570 that won't fit in the 5-bit signed immediate field of a cbcond,
3571 use one of the other v9 conditional branch sequences. */
3573 && GET_CODE (operands
[1]) == REG
3574 && (GET_MODE (operands
[1]) == SImode
3575 || (TARGET_ARCH64
&& GET_MODE (operands
[1]) == DImode
))
3576 && (GET_CODE (operands
[2]) != CONST_INT
3577 || SPARC_SIMM5_P (INTVAL (operands
[2]))))
3579 emit_cbcond_insn (GET_CODE (operands
[0]), operands
[1], operands
[2], operands
[3]);
3583 if (TARGET_ARCH64
&& operands
[2] == const0_rtx
3584 && GET_CODE (operands
[1]) == REG
3585 && GET_MODE (operands
[1]) == DImode
)
3587 emit_v9_brxx_insn (GET_CODE (operands
[0]), operands
[1], operands
[3]);
3591 operands
[1] = gen_compare_reg (operands
[0]);
3592 operands
[2] = const0_rtx
;
3593 operands
[0] = gen_rtx_fmt_ee (GET_CODE (operands
[0]), VOIDmode
,
3594 operands
[1], operands
[2]);
3595 emit_jump_insn (gen_cbranchcc4 (operands
[0], operands
[1], operands
[2],
3600 /* Generate a DFmode part of a hard TFmode register.
3601 REG is the TFmode hard register, LOW is 1 for the
3602 low 64bit of the register and 0 otherwise.
3605 gen_df_reg (rtx reg
, int low
)
3607 int regno
= REGNO (reg
);
3609 if ((WORDS_BIG_ENDIAN
== 0) ^ (low
!= 0))
3610 regno
+= (TARGET_ARCH64
&& SPARC_INT_REG_P (regno
)) ? 1 : 2;
3611 return gen_rtx_REG (DFmode
, regno
);
3614 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
3615 Unlike normal calls, TFmode operands are passed by reference. It is
3616 assumed that no more than 3 operands are required. */
3619 emit_soft_tfmode_libcall (const char *func_name
, int nargs
, rtx
*operands
)
3621 rtx ret_slot
= NULL
, arg
[3], func_sym
;
3624 /* We only expect to be called for conversions, unary, and binary ops. */
3625 gcc_assert (nargs
== 2 || nargs
== 3);
3627 for (i
= 0; i
< nargs
; ++i
)
3629 rtx this_arg
= operands
[i
];
3632 /* TFmode arguments and return values are passed by reference. */
3633 if (GET_MODE (this_arg
) == TFmode
)
3635 int force_stack_temp
;
3637 force_stack_temp
= 0;
3638 if (TARGET_BUGGY_QP_LIB
&& i
== 0)
3639 force_stack_temp
= 1;
3641 if (GET_CODE (this_arg
) == MEM
3642 && ! force_stack_temp
)
3644 tree expr
= MEM_EXPR (this_arg
);
3646 mark_addressable (expr
);
3647 this_arg
= XEXP (this_arg
, 0);
3649 else if (CONSTANT_P (this_arg
)
3650 && ! force_stack_temp
)
3652 this_slot
= force_const_mem (TFmode
, this_arg
);
3653 this_arg
= XEXP (this_slot
, 0);
3657 this_slot
= assign_stack_temp (TFmode
, GET_MODE_SIZE (TFmode
));
3659 /* Operand 0 is the return value. We'll copy it out later. */
3661 emit_move_insn (this_slot
, this_arg
);
3663 ret_slot
= this_slot
;
3665 this_arg
= XEXP (this_slot
, 0);
3672 func_sym
= gen_rtx_SYMBOL_REF (Pmode
, func_name
);
3674 if (GET_MODE (operands
[0]) == TFmode
)
3677 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
,
3678 arg
[0], GET_MODE (arg
[0]),
3679 arg
[1], GET_MODE (arg
[1]));
3681 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
,
3682 arg
[0], GET_MODE (arg
[0]),
3683 arg
[1], GET_MODE (arg
[1]),
3684 arg
[2], GET_MODE (arg
[2]));
3687 emit_move_insn (operands
[0], ret_slot
);
3693 gcc_assert (nargs
== 2);
3695 ret
= emit_library_call_value (func_sym
, operands
[0], LCT_NORMAL
,
3696 GET_MODE (operands
[0]),
3697 arg
[1], GET_MODE (arg
[1]));
3699 if (ret
!= operands
[0])
3700 emit_move_insn (operands
[0], ret
);
3704 /* Expand soft-float TFmode calls to sparc abi routines. */
3707 emit_soft_tfmode_binop (enum rtx_code code
, rtx
*operands
)
3729 emit_soft_tfmode_libcall (func
, 3, operands
);
3733 emit_soft_tfmode_unop (enum rtx_code code
, rtx
*operands
)
3737 gcc_assert (code
== SQRT
);
3740 emit_soft_tfmode_libcall (func
, 2, operands
);
3744 emit_soft_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
3751 switch (GET_MODE (operands
[1]))
3764 case FLOAT_TRUNCATE
:
3765 switch (GET_MODE (operands
[0]))
3779 switch (GET_MODE (operands
[1]))
3784 operands
[1] = gen_rtx_SIGN_EXTEND (DImode
, operands
[1]);
3794 case UNSIGNED_FLOAT
:
3795 switch (GET_MODE (operands
[1]))
3800 operands
[1] = gen_rtx_ZERO_EXTEND (DImode
, operands
[1]);
3811 switch (GET_MODE (operands
[0]))
3825 switch (GET_MODE (operands
[0]))
3842 emit_soft_tfmode_libcall (func
, 2, operands
);
3845 /* Expand a hard-float tfmode operation. All arguments must be in
3849 emit_hard_tfmode_operation (enum rtx_code code
, rtx
*operands
)
3853 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
3855 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
3856 op
= gen_rtx_fmt_e (code
, GET_MODE (operands
[0]), operands
[1]);
3860 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
3861 operands
[2] = force_reg (GET_MODE (operands
[2]), operands
[2]);
3862 op
= gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
3863 operands
[1], operands
[2]);
3866 if (register_operand (operands
[0], VOIDmode
))
3869 dest
= gen_reg_rtx (GET_MODE (operands
[0]));
3871 emit_insn (gen_rtx_SET (dest
, op
));
3873 if (dest
!= operands
[0])
3874 emit_move_insn (operands
[0], dest
);
3878 emit_tfmode_binop (enum rtx_code code
, rtx
*operands
)
3880 if (TARGET_HARD_QUAD
)
3881 emit_hard_tfmode_operation (code
, operands
);
3883 emit_soft_tfmode_binop (code
, operands
);
3887 emit_tfmode_unop (enum rtx_code code
, rtx
*operands
)
3889 if (TARGET_HARD_QUAD
)
3890 emit_hard_tfmode_operation (code
, operands
);
3892 emit_soft_tfmode_unop (code
, operands
);
3896 emit_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
3898 if (TARGET_HARD_QUAD
)
3899 emit_hard_tfmode_operation (code
, operands
);
3901 emit_soft_tfmode_cvt (code
, operands
);
3904 /* Return nonzero if a branch/jump/call instruction will be emitting
3905 nop into its delay slot. */
3908 empty_delay_slot (rtx_insn
*insn
)
3912 /* If no previous instruction (should not happen), return true. */
3913 if (PREV_INSN (insn
) == NULL
)
3916 seq
= NEXT_INSN (PREV_INSN (insn
));
3917 if (GET_CODE (PATTERN (seq
)) == SEQUENCE
)
3923 /* Return nonzero if we should emit a nop after a cbcond instruction.
3924 The cbcond instruction does not have a delay slot, however there is
3925 a severe performance penalty if a control transfer appears right
3926 after a cbcond. Therefore we emit a nop when we detect this
3930 emit_cbcond_nop (rtx_insn
*insn
)
3932 rtx next
= next_active_insn (insn
);
3937 if (NONJUMP_INSN_P (next
)
3938 && GET_CODE (PATTERN (next
)) == SEQUENCE
)
3939 next
= XVECEXP (PATTERN (next
), 0, 0);
3940 else if (CALL_P (next
)
3941 && GET_CODE (PATTERN (next
)) == PARALLEL
)
3943 rtx delay
= XVECEXP (PATTERN (next
), 0, 1);
3945 if (GET_CODE (delay
) == RETURN
)
3947 /* It's a sibling call. Do not emit the nop if we're going
3948 to emit something other than the jump itself as the first
3949 instruction of the sibcall sequence. */
3950 if (sparc_leaf_function_p
|| TARGET_FLAT
)
3955 if (NONJUMP_INSN_P (next
))
3961 /* Return nonzero if TRIAL can go into the call delay slot. */
3964 eligible_for_call_delay (rtx_insn
*trial
)
3968 if (get_attr_in_branch_delay (trial
) == IN_BRANCH_DELAY_FALSE
)
3972 call __tls_get_addr, %tgd_call (foo)
3973 add %l7, %o0, %o0, %tgd_add (foo)
3974 while Sun as/ld does not. */
3975 if (TARGET_GNU_TLS
|| !TARGET_TLS
)
3978 pat
= PATTERN (trial
);
3980 /* We must reject tgd_add{32|64}, i.e.
3981 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD)))
3982 and tldm_add{32|64}, i.e.
3983 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM)))
3985 if (GET_CODE (pat
) == SET
3986 && GET_CODE (SET_SRC (pat
)) == PLUS
)
3988 rtx unspec
= XEXP (SET_SRC (pat
), 1);
3990 if (GET_CODE (unspec
) == UNSPEC
3991 && (XINT (unspec
, 1) == UNSPEC_TLSGD
3992 || XINT (unspec
, 1) == UNSPEC_TLSLDM
))
3999 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
4000 instruction. RETURN_P is true if the v9 variant 'return' is to be
4001 considered in the test too.
4003 TRIAL must be a SET whose destination is a REG appropriate for the
4004 'restore' instruction or, if RETURN_P is true, for the 'return'
4008 eligible_for_restore_insn (rtx trial
, bool return_p
)
4010 rtx pat
= PATTERN (trial
);
4011 rtx src
= SET_SRC (pat
);
4012 bool src_is_freg
= false;
4015 /* Since we now can do moves between float and integer registers when
4016 VIS3 is enabled, we have to catch this case. We can allow such
4017 moves when doing a 'return' however. */
4019 if (GET_CODE (src_reg
) == SUBREG
)
4020 src_reg
= SUBREG_REG (src_reg
);
4021 if (GET_CODE (src_reg
) == REG
4022 && SPARC_FP_REG_P (REGNO (src_reg
)))
4025 /* The 'restore src,%g0,dest' pattern for word mode and below. */
4026 if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
4027 && arith_operand (src
, GET_MODE (src
))
4031 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
4033 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
4036 /* The 'restore src,%g0,dest' pattern for double-word mode. */
4037 else if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
4038 && arith_double_operand (src
, GET_MODE (src
))
4040 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
4042 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
4043 else if (! TARGET_FPU
&& register_operand (src
, SFmode
))
4046 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
4047 else if (! TARGET_FPU
&& TARGET_ARCH64
&& register_operand (src
, DFmode
))
4050 /* If we have the 'return' instruction, anything that does not use
4051 local or output registers and can go into a delay slot wins. */
4052 else if (return_p
&& TARGET_V9
&& !epilogue_renumber (&pat
, 1))
4055 /* The 'restore src1,src2,dest' pattern for SImode. */
4056 else if (GET_CODE (src
) == PLUS
4057 && register_operand (XEXP (src
, 0), SImode
)
4058 && arith_operand (XEXP (src
, 1), SImode
))
4061 /* The 'restore src1,src2,dest' pattern for DImode. */
4062 else if (GET_CODE (src
) == PLUS
4063 && register_operand (XEXP (src
, 0), DImode
)
4064 && arith_double_operand (XEXP (src
, 1), DImode
))
4067 /* The 'restore src1,%lo(src2),dest' pattern. */
4068 else if (GET_CODE (src
) == LO_SUM
4069 && ! TARGET_CM_MEDMID
4070 && ((register_operand (XEXP (src
, 0), SImode
)
4071 && immediate_operand (XEXP (src
, 1), SImode
))
4073 && register_operand (XEXP (src
, 0), DImode
)
4074 && immediate_operand (XEXP (src
, 1), DImode
))))
4077 /* The 'restore src,src,dest' pattern. */
4078 else if (GET_CODE (src
) == ASHIFT
4079 && (register_operand (XEXP (src
, 0), SImode
)
4080 || register_operand (XEXP (src
, 0), DImode
))
4081 && XEXP (src
, 1) == const1_rtx
)
4087 /* Return nonzero if TRIAL can go into the function return's delay slot. */
4090 eligible_for_return_delay (rtx_insn
*trial
)
4095 /* If the function uses __builtin_eh_return, the eh_return machinery
4096 occupies the delay slot. */
4097 if (crtl
->calls_eh_return
)
4100 if (get_attr_in_branch_delay (trial
) == IN_BRANCH_DELAY_FALSE
)
4103 /* In the case of a leaf or flat function, anything can go into the slot. */
4104 if (sparc_leaf_function_p
|| TARGET_FLAT
)
4107 if (!NONJUMP_INSN_P (trial
))
4110 pat
= PATTERN (trial
);
4111 if (GET_CODE (pat
) == PARALLEL
)
4117 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
4119 rtx expr
= XVECEXP (pat
, 0, i
);
4120 if (GET_CODE (expr
) != SET
)
4122 if (GET_CODE (SET_DEST (expr
)) != REG
)
4124 regno
= REGNO (SET_DEST (expr
));
4125 if (regno
>= 8 && regno
< 24)
4128 return !epilogue_renumber (&pat
, 1);
4131 if (GET_CODE (pat
) != SET
)
4134 if (GET_CODE (SET_DEST (pat
)) != REG
)
4137 regno
= REGNO (SET_DEST (pat
));
4139 /* Otherwise, only operations which can be done in tandem with
4140 a `restore' or `return' insn can go into the delay slot. */
4141 if (regno
>= 8 && regno
< 24)
4144 /* If this instruction sets up floating point register and we have a return
4145 instruction, it can probably go in. But restore will not work
4147 if (! SPARC_INT_REG_P (regno
))
4148 return TARGET_V9
&& !epilogue_renumber (&pat
, 1);
4150 return eligible_for_restore_insn (trial
, true);
4153 /* Return nonzero if TRIAL can go into the sibling call's delay slot. */
4156 eligible_for_sibcall_delay (rtx_insn
*trial
)
4160 if (get_attr_in_branch_delay (trial
) == IN_BRANCH_DELAY_FALSE
)
4163 if (!NONJUMP_INSN_P (trial
))
4166 pat
= PATTERN (trial
);
4168 if (sparc_leaf_function_p
|| TARGET_FLAT
)
4170 /* If the tail call is done using the call instruction,
4171 we have to restore %o7 in the delay slot. */
4172 if (LEAF_SIBCALL_SLOT_RESERVED_P
)
4175 /* %g1 is used to build the function address */
4176 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 1), pat
))
4182 if (GET_CODE (pat
) != SET
)
4185 /* Otherwise, only operations which can be done in tandem with
4186 a `restore' insn can go into the delay slot. */
4187 if (GET_CODE (SET_DEST (pat
)) != REG
4188 || (REGNO (SET_DEST (pat
)) >= 8 && REGNO (SET_DEST (pat
)) < 24)
4189 || ! SPARC_INT_REG_P (REGNO (SET_DEST (pat
))))
4192 /* If it mentions %o7, it can't go in, because sibcall will clobber it
4194 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 15), pat
))
4197 return eligible_for_restore_insn (trial
, false);
4200 /* Determine if it's legal to put X into the constant pool. This
4201 is not possible if X contains the address of a symbol that is
4202 not constant (TLS) or not known at final link time (PIC). */
4205 sparc_cannot_force_const_mem (machine_mode mode
, rtx x
)
4207 switch (GET_CODE (x
))
4210 case CONST_WIDE_INT
:
4213 /* Accept all non-symbolic constants. */
4217 /* Labels are OK iff we are non-PIC. */
4218 return flag_pic
!= 0;
4221 /* 'Naked' TLS symbol references are never OK,
4222 non-TLS symbols are OK iff we are non-PIC. */
4223 if (SYMBOL_REF_TLS_MODEL (x
))
4226 return flag_pic
!= 0;
4229 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0));
4232 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0))
4233 || sparc_cannot_force_const_mem (mode
, XEXP (x
, 1));
4241 /* Global Offset Table support. */
4242 static GTY(()) rtx got_helper_rtx
= NULL_RTX
;
4243 static GTY(()) rtx got_register_rtx
= NULL_RTX
;
4244 static GTY(()) rtx got_symbol_rtx
= NULL_RTX
;
4246 /* Return the SYMBOL_REF for the Global Offset Table. */
4251 if (!got_symbol_rtx
)
4252 got_symbol_rtx
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
4254 return got_symbol_rtx
;
4257 #ifdef HAVE_GAS_HIDDEN
4258 # define USE_HIDDEN_LINKONCE 1
4260 # define USE_HIDDEN_LINKONCE 0
4264 get_pc_thunk_name (char name
[32], unsigned int regno
)
4266 const char *reg_name
= reg_names
[regno
];
4268 /* Skip the leading '%' as that cannot be used in a
4272 if (USE_HIDDEN_LINKONCE
)
4273 sprintf (name
, "__sparc_get_pc_thunk.%s", reg_name
);
4275 ASM_GENERATE_INTERNAL_LABEL (name
, "LADDPC", regno
);
4278 /* Wrapper around the load_pcrel_sym{si,di} patterns. */
4281 gen_load_pcrel_sym (rtx op0
, rtx op1
, rtx op2
)
4283 int orig_flag_pic
= flag_pic
;
4286 /* The load_pcrel_sym{si,di} patterns require absolute addressing. */
4289 insn
= gen_load_pcrel_symdi (op0
, op1
, op2
, GEN_INT (REGNO (op0
)));
4291 insn
= gen_load_pcrel_symsi (op0
, op1
, op2
, GEN_INT (REGNO (op0
)));
4292 flag_pic
= orig_flag_pic
;
4297 /* Emit code to load the GOT register. */
4300 load_got_register (void)
4302 if (!got_register_rtx
)
4303 got_register_rtx
= gen_rtx_REG (Pmode
, GLOBAL_OFFSET_TABLE_REGNUM
);
4305 if (TARGET_VXWORKS_RTP
)
4306 emit_insn (gen_vxworks_load_got ());
4309 /* The GOT symbol is subject to a PC-relative relocation so we need a
4310 helper function to add the PC value and thus get the final value. */
4311 if (!got_helper_rtx
)
4314 get_pc_thunk_name (name
, GLOBAL_OFFSET_TABLE_REGNUM
);
4315 got_helper_rtx
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
4318 emit_insn (gen_load_pcrel_sym (got_register_rtx
, sparc_got (),
4323 /* Ensure that we are not using patterns that are not OK with PIC. */
4333 op
= recog_data
.operand
[i
];
4334 gcc_assert (GET_CODE (op
) != SYMBOL_REF
4335 && (GET_CODE (op
) != CONST
4336 || (GET_CODE (XEXP (op
, 0)) == MINUS
4337 && XEXP (XEXP (op
, 0), 0) == sparc_got ()
4338 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST
)));
4346 /* Return true if X is an address which needs a temporary register when
4347 reloaded while generating PIC code. */
4350 pic_address_needs_scratch (rtx x
)
4352 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
4353 if (GET_CODE (x
) == CONST
4354 && GET_CODE (XEXP (x
, 0)) == PLUS
4355 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
4356 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4357 && !SMALL_INT (XEXP (XEXP (x
, 0), 1)))
4363 /* Determine if a given RTX is a valid constant. We already know this
4364 satisfies CONSTANT_P. */
4367 sparc_legitimate_constant_p (machine_mode mode
, rtx x
)
4369 switch (GET_CODE (x
))
4373 if (sparc_tls_referenced_p (x
))
4378 /* Floating point constants are generally not ok.
4379 The only exception is 0.0 and all-ones in VIS. */
4381 && SCALAR_FLOAT_MODE_P (mode
)
4382 && (const_zero_operand (x
, mode
)
4383 || const_all_ones_operand (x
, mode
)))
4389 /* Vector constants are generally not ok.
4390 The only exception is 0 or -1 in VIS. */
4392 && (const_zero_operand (x
, mode
)
4393 || const_all_ones_operand (x
, mode
)))
4405 /* Determine if a given RTX is a valid constant address. */
4408 constant_address_p (rtx x
)
4410 switch (GET_CODE (x
))
4418 if (flag_pic
&& pic_address_needs_scratch (x
))
4420 return sparc_legitimate_constant_p (Pmode
, x
);
4423 return !flag_pic
&& sparc_legitimate_constant_p (Pmode
, x
);
4430 /* Nonzero if the constant value X is a legitimate general operand
4431 when generating PIC code. It is given that flag_pic is on and
4432 that X satisfies CONSTANT_P. */
4435 legitimate_pic_operand_p (rtx x
)
4437 if (pic_address_needs_scratch (x
))
4439 if (sparc_tls_referenced_p (x
))
4444 /* Return true if X is a representation of the PIC register. */
4447 sparc_pic_register_p (rtx x
)
4449 if (!REG_P (x
) || !pic_offset_table_rtx
)
4452 if (x
== pic_offset_table_rtx
)
4455 if (!HARD_REGISTER_P (pic_offset_table_rtx
)
4456 && (HARD_REGISTER_P (x
) || lra_in_progress
)
4457 && ORIGINAL_REGNO (x
) == REGNO (pic_offset_table_rtx
))
4463 #define RTX_OK_FOR_OFFSET_P(X, MODE) \
4465 && INTVAL (X) >= -0x1000 \
4466 && INTVAL (X) <= (0x1000 - GET_MODE_SIZE (MODE)))
4468 #define RTX_OK_FOR_OLO10_P(X, MODE) \
4470 && INTVAL (X) >= -0x1000 \
4471 && INTVAL (X) <= (0xc00 - GET_MODE_SIZE (MODE)))
4473 /* Handle the TARGET_LEGITIMATE_ADDRESS_P target hook.
4475 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
4476 ordinarily. This changes a bit when generating PIC. */
4479 sparc_legitimate_address_p (machine_mode mode
, rtx addr
, bool strict
)
4481 rtx rs1
= NULL
, rs2
= NULL
, imm1
= NULL
;
4483 if (REG_P (addr
) || GET_CODE (addr
) == SUBREG
)
4485 else if (GET_CODE (addr
) == PLUS
)
4487 rs1
= XEXP (addr
, 0);
4488 rs2
= XEXP (addr
, 1);
4490 /* Canonicalize. REG comes first, if there are no regs,
4491 LO_SUM comes first. */
4493 && GET_CODE (rs1
) != SUBREG
4495 || GET_CODE (rs2
) == SUBREG
4496 || (GET_CODE (rs2
) == LO_SUM
&& GET_CODE (rs1
) != LO_SUM
)))
4498 rs1
= XEXP (addr
, 1);
4499 rs2
= XEXP (addr
, 0);
4503 && sparc_pic_register_p (rs1
)
4505 && GET_CODE (rs2
) != SUBREG
4506 && GET_CODE (rs2
) != LO_SUM
4507 && GET_CODE (rs2
) != MEM
4508 && !(GET_CODE (rs2
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs2
))
4509 && (! symbolic_operand (rs2
, VOIDmode
) || mode
== Pmode
)
4510 && (GET_CODE (rs2
) != CONST_INT
|| SMALL_INT (rs2
)))
4512 || GET_CODE (rs1
) == SUBREG
)
4513 && RTX_OK_FOR_OFFSET_P (rs2
, mode
)))
4518 else if ((REG_P (rs1
) || GET_CODE (rs1
) == SUBREG
)
4519 && (REG_P (rs2
) || GET_CODE (rs2
) == SUBREG
))
4521 /* We prohibit REG + REG for TFmode when there are no quad move insns
4522 and we consequently need to split. We do this because REG+REG
4523 is not an offsettable address. If we get the situation in reload
4524 where source and destination of a movtf pattern are both MEMs with
4525 REG+REG address, then only one of them gets converted to an
4526 offsettable address. */
4528 && ! (TARGET_ARCH64
&& TARGET_HARD_QUAD
))
4531 /* Likewise for TImode, but in all cases. */
4535 /* We prohibit REG + REG on ARCH32 if not optimizing for
4536 DFmode/DImode because then mem_min_alignment is likely to be zero
4537 after reload and the forced split would lack a matching splitter
4539 if (TARGET_ARCH32
&& !optimize
4540 && (mode
== DFmode
|| mode
== DImode
))
4543 else if (USE_AS_OFFSETABLE_LO10
4544 && GET_CODE (rs1
) == LO_SUM
4546 && ! TARGET_CM_MEDMID
4547 && RTX_OK_FOR_OLO10_P (rs2
, mode
))
4550 imm1
= XEXP (rs1
, 1);
4551 rs1
= XEXP (rs1
, 0);
4552 if (!CONSTANT_P (imm1
)
4553 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
4557 else if (GET_CODE (addr
) == LO_SUM
)
4559 rs1
= XEXP (addr
, 0);
4560 imm1
= XEXP (addr
, 1);
4562 if (!CONSTANT_P (imm1
)
4563 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
4566 /* We can't allow TFmode in 32-bit mode, because an offset greater
4567 than the alignment (8) may cause the LO_SUM to overflow. */
4568 if (mode
== TFmode
&& TARGET_ARCH32
)
4571 /* During reload, accept the HIGH+LO_SUM construct generated by
4572 sparc_legitimize_reload_address. */
4573 if (reload_in_progress
4574 && GET_CODE (rs1
) == HIGH
4575 && XEXP (rs1
, 0) == imm1
)
4578 else if (GET_CODE (addr
) == CONST_INT
&& SMALL_INT (addr
))
4583 if (GET_CODE (rs1
) == SUBREG
)
4584 rs1
= SUBREG_REG (rs1
);
4590 if (GET_CODE (rs2
) == SUBREG
)
4591 rs2
= SUBREG_REG (rs2
);
4598 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1
))
4599 || (rs2
&& !REGNO_OK_FOR_BASE_P (REGNO (rs2
))))
4604 if ((! SPARC_INT_REG_P (REGNO (rs1
))
4605 && REGNO (rs1
) != FRAME_POINTER_REGNUM
4606 && REGNO (rs1
) < FIRST_PSEUDO_REGISTER
)
4608 && (! SPARC_INT_REG_P (REGNO (rs2
))
4609 && REGNO (rs2
) != FRAME_POINTER_REGNUM
4610 && REGNO (rs2
) < FIRST_PSEUDO_REGISTER
)))
4616 /* Return the SYMBOL_REF for the tls_get_addr function. */
4618 static GTY(()) rtx sparc_tls_symbol
= NULL_RTX
;
4621 sparc_tls_get_addr (void)
4623 if (!sparc_tls_symbol
)
4624 sparc_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
4626 return sparc_tls_symbol
;
4629 /* Return the Global Offset Table to be used in TLS mode. */
4632 sparc_tls_got (void)
4634 /* In PIC mode, this is just the PIC offset table. */
4637 crtl
->uses_pic_offset_table
= 1;
4638 return pic_offset_table_rtx
;
4641 /* In non-PIC mode, Sun as (unlike GNU as) emits PC-relative relocations for
4642 the GOT symbol with the 32-bit ABI, so we reload the GOT register. */
4643 if (TARGET_SUN_TLS
&& TARGET_ARCH32
)
4645 load_got_register ();
4646 return got_register_rtx
;
4649 /* In all other cases, we load a new pseudo with the GOT symbol. */
4650 return copy_to_reg (sparc_got ());
4653 /* Return true if X contains a thread-local symbol. */
4656 sparc_tls_referenced_p (rtx x
)
4658 if (!TARGET_HAVE_TLS
)
4661 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
4662 x
= XEXP (XEXP (x
, 0), 0);
4664 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
))
4667 /* That's all we handle in sparc_legitimize_tls_address for now. */
4671 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
4672 this (thread-local) address. */
4675 sparc_legitimize_tls_address (rtx addr
)
4677 rtx temp1
, temp2
, temp3
, ret
, o0
, got
;
4680 gcc_assert (can_create_pseudo_p ());
4682 if (GET_CODE (addr
) == SYMBOL_REF
)
4683 /* Although the various sethi/or sequences generate SImode values, many of
4684 them can be transformed by the linker when relaxing and, if relaxing to
4685 local-exec, will become a sethi/xor pair, which is signed and therefore
4686 a full DImode value in 64-bit mode. Thus we must use Pmode, lest these
4687 values be spilled onto the stack in 64-bit mode. */
4688 switch (SYMBOL_REF_TLS_MODEL (addr
))
4690 case TLS_MODEL_GLOBAL_DYNAMIC
:
4692 temp1
= gen_reg_rtx (Pmode
);
4693 temp2
= gen_reg_rtx (Pmode
);
4694 ret
= gen_reg_rtx (Pmode
);
4695 o0
= gen_rtx_REG (Pmode
, 8);
4696 got
= sparc_tls_got ();
4699 emit_insn (gen_tgd_hi22si (temp1
, addr
));
4700 emit_insn (gen_tgd_lo10si (temp2
, temp1
, addr
));
4701 emit_insn (gen_tgd_addsi (o0
, got
, temp2
, addr
));
4702 insn
= emit_call_insn (gen_tgd_callsi (o0
, sparc_tls_get_addr (),
4707 emit_insn (gen_tgd_hi22di (temp1
, addr
));
4708 emit_insn (gen_tgd_lo10di (temp2
, temp1
, addr
));
4709 emit_insn (gen_tgd_adddi (o0
, got
, temp2
, addr
));
4710 insn
= emit_call_insn (gen_tgd_calldi (o0
, sparc_tls_get_addr (),
4713 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
4714 RTL_CONST_CALL_P (insn
) = 1;
4715 insn
= get_insns ();
4717 emit_libcall_block (insn
, ret
, o0
, addr
);
4720 case TLS_MODEL_LOCAL_DYNAMIC
:
4722 temp1
= gen_reg_rtx (Pmode
);
4723 temp2
= gen_reg_rtx (Pmode
);
4724 temp3
= gen_reg_rtx (Pmode
);
4725 ret
= gen_reg_rtx (Pmode
);
4726 o0
= gen_rtx_REG (Pmode
, 8);
4727 got
= sparc_tls_got ();
4730 emit_insn (gen_tldm_hi22si (temp1
));
4731 emit_insn (gen_tldm_lo10si (temp2
, temp1
));
4732 emit_insn (gen_tldm_addsi (o0
, got
, temp2
));
4733 insn
= emit_call_insn (gen_tldm_callsi (o0
, sparc_tls_get_addr (),
4738 emit_insn (gen_tldm_hi22di (temp1
));
4739 emit_insn (gen_tldm_lo10di (temp2
, temp1
));
4740 emit_insn (gen_tldm_adddi (o0
, got
, temp2
));
4741 insn
= emit_call_insn (gen_tldm_calldi (o0
, sparc_tls_get_addr (),
4744 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
4745 RTL_CONST_CALL_P (insn
) = 1;
4746 insn
= get_insns ();
4748 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
4749 share the LD_BASE result with other LD model accesses. */
4750 emit_libcall_block (insn
, temp3
, o0
,
4751 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
4752 UNSPEC_TLSLD_BASE
));
4753 temp1
= gen_reg_rtx (Pmode
);
4754 temp2
= gen_reg_rtx (Pmode
);
4757 emit_insn (gen_tldo_hix22si (temp1
, addr
));
4758 emit_insn (gen_tldo_lox10si (temp2
, temp1
, addr
));
4759 emit_insn (gen_tldo_addsi (ret
, temp3
, temp2
, addr
));
4763 emit_insn (gen_tldo_hix22di (temp1
, addr
));
4764 emit_insn (gen_tldo_lox10di (temp2
, temp1
, addr
));
4765 emit_insn (gen_tldo_adddi (ret
, temp3
, temp2
, addr
));
4769 case TLS_MODEL_INITIAL_EXEC
:
4770 temp1
= gen_reg_rtx (Pmode
);
4771 temp2
= gen_reg_rtx (Pmode
);
4772 temp3
= gen_reg_rtx (Pmode
);
4773 got
= sparc_tls_got ();
4776 emit_insn (gen_tie_hi22si (temp1
, addr
));
4777 emit_insn (gen_tie_lo10si (temp2
, temp1
, addr
));
4778 emit_insn (gen_tie_ld32 (temp3
, got
, temp2
, addr
));
4782 emit_insn (gen_tie_hi22di (temp1
, addr
));
4783 emit_insn (gen_tie_lo10di (temp2
, temp1
, addr
));
4784 emit_insn (gen_tie_ld64 (temp3
, got
, temp2
, addr
));
4788 ret
= gen_reg_rtx (Pmode
);
4790 emit_insn (gen_tie_addsi (ret
, gen_rtx_REG (Pmode
, 7),
4793 emit_insn (gen_tie_adddi (ret
, gen_rtx_REG (Pmode
, 7),
4797 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp3
);
4800 case TLS_MODEL_LOCAL_EXEC
:
4801 temp1
= gen_reg_rtx (Pmode
);
4802 temp2
= gen_reg_rtx (Pmode
);
4805 emit_insn (gen_tle_hix22si (temp1
, addr
));
4806 emit_insn (gen_tle_lox10si (temp2
, temp1
, addr
));
4810 emit_insn (gen_tle_hix22di (temp1
, addr
));
4811 emit_insn (gen_tle_lox10di (temp2
, temp1
, addr
));
4813 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp2
);
4820 else if (GET_CODE (addr
) == CONST
)
4824 gcc_assert (GET_CODE (XEXP (addr
, 0)) == PLUS
);
4826 base
= sparc_legitimize_tls_address (XEXP (XEXP (addr
, 0), 0));
4827 offset
= XEXP (XEXP (addr
, 0), 1);
4829 base
= force_operand (base
, NULL_RTX
);
4830 if (!(GET_CODE (offset
) == CONST_INT
&& SMALL_INT (offset
)))
4831 offset
= force_reg (Pmode
, offset
);
4832 ret
= gen_rtx_PLUS (Pmode
, base
, offset
);
4836 gcc_unreachable (); /* for now ... */
4841 /* Legitimize PIC addresses. If the address is already position-independent,
4842 we return ORIG. Newly generated position-independent addresses go into a
4843 reg. This is REG if nonzero, otherwise we allocate register(s) as
4847 sparc_legitimize_pic_address (rtx orig
, rtx reg
)
4849 if (GET_CODE (orig
) == SYMBOL_REF
4850 /* See the comment in sparc_expand_move. */
4851 || (GET_CODE (orig
) == LABEL_REF
&& !can_use_mov_pic_label_ref (orig
)))
4853 bool gotdata_op
= false;
4854 rtx pic_ref
, address
;
4859 gcc_assert (can_create_pseudo_p ());
4860 reg
= gen_reg_rtx (Pmode
);
4865 /* If not during reload, allocate another temp reg here for loading
4866 in the address, so that these instructions can be optimized
4868 rtx temp_reg
= can_create_pseudo_p () ? gen_reg_rtx (Pmode
) : reg
;
4870 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
4871 won't get confused into thinking that these two instructions
4872 are loading in the true address of the symbol. If in the
4873 future a PIC rtx exists, that should be used instead. */
4876 emit_insn (gen_movdi_high_pic (temp_reg
, orig
));
4877 emit_insn (gen_movdi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
4881 emit_insn (gen_movsi_high_pic (temp_reg
, orig
));
4882 emit_insn (gen_movsi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
4891 crtl
->uses_pic_offset_table
= 1;
4895 insn
= emit_insn (gen_movdi_pic_gotdata_op (reg
,
4896 pic_offset_table_rtx
,
4899 insn
= emit_insn (gen_movsi_pic_gotdata_op (reg
,
4900 pic_offset_table_rtx
,
4906 = gen_const_mem (Pmode
,
4907 gen_rtx_PLUS (Pmode
,
4908 pic_offset_table_rtx
, address
));
4909 insn
= emit_move_insn (reg
, pic_ref
);
4912 /* Put a REG_EQUAL note on this insn, so that it can be optimized
4914 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
4917 else if (GET_CODE (orig
) == CONST
)
4921 if (GET_CODE (XEXP (orig
, 0)) == PLUS
4922 && sparc_pic_register_p (XEXP (XEXP (orig
, 0), 0)))
4927 gcc_assert (can_create_pseudo_p ());
4928 reg
= gen_reg_rtx (Pmode
);
4931 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
4932 base
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), reg
);
4933 offset
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
4934 base
== reg
? NULL_RTX
: reg
);
4936 if (GET_CODE (offset
) == CONST_INT
)
4938 if (SMALL_INT (offset
))
4939 return plus_constant (Pmode
, base
, INTVAL (offset
));
4940 else if (can_create_pseudo_p ())
4941 offset
= force_reg (Pmode
, offset
);
4943 /* If we reach here, then something is seriously wrong. */
4946 return gen_rtx_PLUS (Pmode
, base
, offset
);
4948 else if (GET_CODE (orig
) == LABEL_REF
)
4949 /* ??? We ought to be checking that the register is live instead, in case
4950 it is eliminated. */
4951 crtl
->uses_pic_offset_table
= 1;
4956 /* Try machine-dependent ways of modifying an illegitimate address X
4957 to be legitimate. If we find one, return the new, valid address.
4959 OLDX is the address as it was before break_out_memory_refs was called.
4960 In some cases it is useful to look at this to decide what needs to be done.
4962 MODE is the mode of the operand pointed to by X.
4964 On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
4967 sparc_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
4972 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
)
4973 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
4974 force_operand (XEXP (x
, 0), NULL_RTX
));
4975 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == MULT
)
4976 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4977 force_operand (XEXP (x
, 1), NULL_RTX
));
4978 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
4979 x
= gen_rtx_PLUS (Pmode
, force_operand (XEXP (x
, 0), NULL_RTX
),
4981 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == PLUS
)
4982 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4983 force_operand (XEXP (x
, 1), NULL_RTX
));
4985 if (x
!= orig_x
&& sparc_legitimate_address_p (mode
, x
, FALSE
))
4988 if (sparc_tls_referenced_p (x
))
4989 x
= sparc_legitimize_tls_address (x
);
4991 x
= sparc_legitimize_pic_address (x
, NULL_RTX
);
4992 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 1)))
4993 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4994 copy_to_mode_reg (Pmode
, XEXP (x
, 1)));
4995 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 0)))
4996 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
4997 copy_to_mode_reg (Pmode
, XEXP (x
, 0)));
4998 else if (GET_CODE (x
) == SYMBOL_REF
4999 || GET_CODE (x
) == CONST
5000 || GET_CODE (x
) == LABEL_REF
)
5001 x
= copy_to_suggested_reg (x
, NULL_RTX
, Pmode
);
5006 /* Delegitimize an address that was legitimized by the above function. */
5009 sparc_delegitimize_address (rtx x
)
5011 x
= delegitimize_mem_from_attrs (x
);
5013 if (GET_CODE (x
) == LO_SUM
)
5016 if (GET_CODE (x
) == UNSPEC
)
5017 switch (XINT (x
, 1))
5019 case UNSPEC_MOVE_PIC
:
5021 x
= XVECEXP (x
, 0, 0);
5022 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
5024 case UNSPEC_MOVE_GOTDATA
:
5025 x
= XVECEXP (x
, 0, 2);
5026 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
5032 /* This is generated by mov{si,di}_pic_label_ref in PIC mode. */
5033 if (GET_CODE (x
) == MINUS
5034 && (XEXP (x
, 0) == got_register_rtx
5035 || sparc_pic_register_p (XEXP (x
, 0))))
5037 rtx y
= XEXP (x
, 1);
5039 if (GET_CODE (y
) == LO_SUM
)
5042 if (GET_CODE (y
) == UNSPEC
&& XINT (y
, 1) == UNSPEC_MOVE_PIC_LABEL
)
5044 x
= XVECEXP (y
, 0, 0);
5045 gcc_assert (GET_CODE (x
) == LABEL_REF
5046 || (GET_CODE (x
) == CONST
5047 && GET_CODE (XEXP (x
, 0)) == PLUS
5048 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
5049 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
));
5056 /* SPARC implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
5057 replace the input X, or the original X if no replacement is called for.
5058 The output parameter *WIN is 1 if the calling macro should goto WIN,
5061 For SPARC, we wish to handle addresses by splitting them into
5062 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
5063 This cuts the number of extra insns by one.
5065 Do nothing when generating PIC code and the address is a symbolic
5066 operand or requires a scratch register. */
5069 sparc_legitimize_reload_address (rtx x
, machine_mode mode
,
5070 int opnum
, int type
,
5071 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
5073 /* Decompose SImode constants into HIGH+LO_SUM. */
5075 && (mode
!= TFmode
|| TARGET_ARCH64
)
5076 && GET_MODE (x
) == SImode
5077 && GET_CODE (x
) != LO_SUM
5078 && GET_CODE (x
) != HIGH
5079 && sparc_code_model
<= CM_MEDLOW
5081 && (symbolic_operand (x
, Pmode
) || pic_address_needs_scratch (x
))))
5083 x
= gen_rtx_LO_SUM (GET_MODE (x
), gen_rtx_HIGH (GET_MODE (x
), x
), x
);
5084 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
5085 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
5086 opnum
, (enum reload_type
)type
);
5091 /* We have to recognize what we have already generated above. */
5092 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == HIGH
)
5094 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
5095 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
5096 opnum
, (enum reload_type
)type
);
5105 /* Return true if ADDR (a legitimate address expression)
5106 has an effect that depends on the machine mode it is used for.
5112 is not equivalent to
5114 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
5116 because [%l7+a+1] is interpreted as the address of (a+1). */
5120 sparc_mode_dependent_address_p (const_rtx addr
,
5121 addr_space_t as ATTRIBUTE_UNUSED
)
5123 if (GET_CODE (addr
) == PLUS
5124 && sparc_pic_register_p (XEXP (addr
, 0))
5125 && symbolic_operand (XEXP (addr
, 1), VOIDmode
))
5131 /* Emit a call instruction with the pattern given by PAT. ADDR is the
5132 address of the call target. */
5135 sparc_emit_call_insn (rtx pat
, rtx addr
)
5139 insn
= emit_call_insn (pat
);
5141 /* The PIC register is live on entry to VxWorks PIC PLT entries. */
5142 if (TARGET_VXWORKS_RTP
5144 && GET_CODE (addr
) == SYMBOL_REF
5145 && (SYMBOL_REF_DECL (addr
)
5146 ? !targetm
.binds_local_p (SYMBOL_REF_DECL (addr
))
5147 : !SYMBOL_REF_LOCAL_P (addr
)))
5149 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
5150 crtl
->uses_pic_offset_table
= 1;
5154 /* Return 1 if RTX is a MEM which is known to be aligned to at
5155 least a DESIRED byte boundary. */
5158 mem_min_alignment (rtx mem
, int desired
)
5160 rtx addr
, base
, offset
;
5162 /* If it's not a MEM we can't accept it. */
5163 if (GET_CODE (mem
) != MEM
)
5167 if (!TARGET_UNALIGNED_DOUBLES
5168 && MEM_ALIGN (mem
) / BITS_PER_UNIT
>= (unsigned)desired
)
5171 /* ??? The rest of the function predates MEM_ALIGN so
5172 there is probably a bit of redundancy. */
5173 addr
= XEXP (mem
, 0);
5174 base
= offset
= NULL_RTX
;
5175 if (GET_CODE (addr
) == PLUS
)
5177 if (GET_CODE (XEXP (addr
, 0)) == REG
)
5179 base
= XEXP (addr
, 0);
5181 /* What we are saying here is that if the base
5182 REG is aligned properly, the compiler will make
5183 sure any REG based index upon it will be so
5185 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
5186 offset
= XEXP (addr
, 1);
5188 offset
= const0_rtx
;
5191 else if (GET_CODE (addr
) == REG
)
5194 offset
= const0_rtx
;
5197 if (base
!= NULL_RTX
)
5199 int regno
= REGNO (base
);
5201 if (regno
!= HARD_FRAME_POINTER_REGNUM
&& regno
!= STACK_POINTER_REGNUM
)
5203 /* Check if the compiler has recorded some information
5204 about the alignment of the base REG. If reload has
5205 completed, we already matched with proper alignments.
5206 If not running global_alloc, reload might give us
5207 unaligned pointer to local stack though. */
5209 && REGNO_POINTER_ALIGN (regno
) >= desired
* BITS_PER_UNIT
)
5210 || (optimize
&& reload_completed
))
5211 && (INTVAL (offset
) & (desired
- 1)) == 0)
5216 if (((INTVAL (offset
) - SPARC_STACK_BIAS
) & (desired
- 1)) == 0)
5220 else if (! TARGET_UNALIGNED_DOUBLES
5221 || CONSTANT_P (addr
)
5222 || GET_CODE (addr
) == LO_SUM
)
5224 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
5225 is true, in which case we can only assume that an access is aligned if
5226 it is to a constant address, or the address involves a LO_SUM. */
5230 /* An obviously unaligned address. */
5235 /* Vectors to keep interesting information about registers where it can easily
5236 be got. We used to use the actual mode value as the bit number, but there
5237 are more than 32 modes now. Instead we use two tables: one indexed by
5238 hard register number, and one indexed by mode. */
5240 /* The purpose of sparc_mode_class is to shrink the range of modes so that
5241 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
5242 mapped into one sparc_mode_class mode. */
5244 enum sparc_mode_class
{
5245 H_MODE
, S_MODE
, D_MODE
, T_MODE
, O_MODE
,
5246 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
5250 /* Modes for single-word and smaller quantities. */
5252 ((1 << (int) H_MODE) | (1 << (int) S_MODE) | (1 << (int) SF_MODE))
5254 /* Modes for double-word and smaller quantities. */
5255 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << (int) DF_MODE))
5257 /* Modes for quad-word and smaller quantities. */
5258 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
5260 /* Modes for 8-word and smaller quantities. */
5261 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
5263 /* Modes for single-float quantities. */
5264 #define SF_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
5266 /* Modes for double-float and smaller quantities. */
5267 #define DF_MODES (SF_MODES | (1 << (int) D_MODE) | (1 << (int) DF_MODE))
5269 /* Modes for quad-float and smaller quantities. */
5270 #define TF_MODES (DF_MODES | (1 << (int) TF_MODE))
5272 /* Modes for quad-float pairs and smaller quantities. */
5273 #define OF_MODES (TF_MODES | (1 << (int) OF_MODE))
5275 /* Modes for double-float only quantities. */
5276 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
5278 /* Modes for quad-float and double-float only quantities. */
5279 #define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE))
5281 /* Modes for quad-float pairs and double-float only quantities. */
5282 #define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE))
5284 /* Modes for condition codes. */
5285 #define CC_MODES (1 << (int) CC_MODE)
5286 #define CCFP_MODES (1 << (int) CCFP_MODE)
5288 /* Value is 1 if register/mode pair is acceptable on sparc.
5290 The funny mixture of D and T modes is because integer operations
5291 do not specially operate on tetra quantities, so non-quad-aligned
5292 registers can hold quadword quantities (except %o4 and %i4 because
5293 they cross fixed registers).
5295 ??? Note that, despite the settings, non-double-aligned parameter
5296 registers can hold double-word quantities in 32-bit mode. */
5298 /* This points to either the 32-bit or the 64-bit version. */
5299 static const int *hard_regno_mode_classes
;
5301 static const int hard_32bit_mode_classes
[] = {
5302 S_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
5303 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
5304 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
5305 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
5307 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5308 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5309 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5310 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5312 /* FP regs f32 to f63. Only the even numbered registers actually exist,
5313 and none can hold SFmode/SImode values. */
5314 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5315 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5316 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5317 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5320 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
5322 /* %icc, %sfp, %gsr */
5323 CC_MODES
, 0, D_MODES
5326 static const int hard_64bit_mode_classes
[] = {
5327 D_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
5328 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
5329 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
5330 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
5332 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5333 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5334 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5335 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5337 /* FP regs f32 to f63. Only the even numbered registers actually exist,
5338 and none can hold SFmode/SImode values. */
5339 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5340 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5341 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5342 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5345 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
5347 /* %icc, %sfp, %gsr */
5348 CC_MODES
, 0, D_MODES
5351 static int sparc_mode_class
[NUM_MACHINE_MODES
];
5353 enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
5356 sparc_init_modes (void)
5360 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
5362 machine_mode m
= (machine_mode
) i
;
5363 unsigned int size
= GET_MODE_SIZE (m
);
5365 switch (GET_MODE_CLASS (m
))
5368 case MODE_PARTIAL_INT
:
5369 case MODE_COMPLEX_INT
:
5371 sparc_mode_class
[i
] = 1 << (int) H_MODE
;
5373 sparc_mode_class
[i
] = 1 << (int) S_MODE
;
5375 sparc_mode_class
[i
] = 1 << (int) D_MODE
;
5376 else if (size
== 16)
5377 sparc_mode_class
[i
] = 1 << (int) T_MODE
;
5378 else if (size
== 32)
5379 sparc_mode_class
[i
] = 1 << (int) O_MODE
;
5381 sparc_mode_class
[i
] = 0;
5383 case MODE_VECTOR_INT
:
5385 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
5387 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
5389 sparc_mode_class
[i
] = 0;
5392 case MODE_COMPLEX_FLOAT
:
5394 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
5396 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
5397 else if (size
== 16)
5398 sparc_mode_class
[i
] = 1 << (int) TF_MODE
;
5399 else if (size
== 32)
5400 sparc_mode_class
[i
] = 1 << (int) OF_MODE
;
5402 sparc_mode_class
[i
] = 0;
5405 if (m
== CCFPmode
|| m
== CCFPEmode
)
5406 sparc_mode_class
[i
] = 1 << (int) CCFP_MODE
;
5408 sparc_mode_class
[i
] = 1 << (int) CC_MODE
;
5411 sparc_mode_class
[i
] = 0;
5417 hard_regno_mode_classes
= hard_64bit_mode_classes
;
5419 hard_regno_mode_classes
= hard_32bit_mode_classes
;
5421 /* Initialize the array used by REGNO_REG_CLASS. */
5422 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
5424 if (i
< 16 && TARGET_V8PLUS
)
5425 sparc_regno_reg_class
[i
] = I64_REGS
;
5426 else if (i
< 32 || i
== FRAME_POINTER_REGNUM
)
5427 sparc_regno_reg_class
[i
] = GENERAL_REGS
;
5429 sparc_regno_reg_class
[i
] = FP_REGS
;
5431 sparc_regno_reg_class
[i
] = EXTRA_FP_REGS
;
5433 sparc_regno_reg_class
[i
] = FPCC_REGS
;
5435 sparc_regno_reg_class
[i
] = NO_REGS
;
5439 /* Return whether REGNO, a global or FP register, must be saved/restored. */
5442 save_global_or_fp_reg_p (unsigned int regno
,
5443 int leaf_function ATTRIBUTE_UNUSED
)
5445 return !call_used_regs
[regno
] && df_regs_ever_live_p (regno
);
5448 /* Return whether the return address register (%i7) is needed. */
5451 return_addr_reg_needed_p (int leaf_function
)
5453 /* If it is live, for example because of __builtin_return_address (0). */
5454 if (df_regs_ever_live_p (RETURN_ADDR_REGNUM
))
5457 /* Otherwise, it is needed as save register if %o7 is clobbered. */
5459 /* Loading the GOT register clobbers %o7. */
5460 || crtl
->uses_pic_offset_table
5461 || df_regs_ever_live_p (INCOMING_RETURN_ADDR_REGNUM
))
5467 /* Return whether REGNO, a local or in register, must be saved/restored. */
5470 save_local_or_in_reg_p (unsigned int regno
, int leaf_function
)
5472 /* General case: call-saved registers live at some point. */
5473 if (!call_used_regs
[regno
] && df_regs_ever_live_p (regno
))
5476 /* Frame pointer register (%fp) if needed. */
5477 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
5480 /* Return address register (%i7) if needed. */
5481 if (regno
== RETURN_ADDR_REGNUM
&& return_addr_reg_needed_p (leaf_function
))
5484 /* GOT register (%l7) if needed. */
5485 if (regno
== GLOBAL_OFFSET_TABLE_REGNUM
&& got_register_rtx
)
5488 /* If the function accesses prior frames, the frame pointer and the return
5489 address of the previous frame must be saved on the stack. */
5490 if (crtl
->accesses_prior_frames
5491 && (regno
== HARD_FRAME_POINTER_REGNUM
|| regno
== RETURN_ADDR_REGNUM
))
5497 /* Compute the frame size required by the function. This function is called
5498 during the reload pass and also by sparc_expand_prologue. */
5500 static HOST_WIDE_INT
5501 sparc_compute_frame_size (HOST_WIDE_INT size
, int leaf_function
)
5503 HOST_WIDE_INT frame_size
, apparent_frame_size
;
5504 int args_size
, n_global_fp_regs
= 0;
5505 bool save_local_in_regs_p
= false;
5508 /* If the function allocates dynamic stack space, the dynamic offset is
5509 computed early and contains REG_PARM_STACK_SPACE, so we need to cope. */
5510 if (leaf_function
&& !cfun
->calls_alloca
)
5513 args_size
= crtl
->outgoing_args_size
+ REG_PARM_STACK_SPACE (cfun
->decl
);
5515 /* Calculate space needed for global registers. */
5518 for (i
= 0; i
< 8; i
++)
5519 if (save_global_or_fp_reg_p (i
, 0))
5520 n_global_fp_regs
+= 2;
5524 for (i
= 0; i
< 8; i
+= 2)
5525 if (save_global_or_fp_reg_p (i
, 0)
5526 || save_global_or_fp_reg_p (i
+ 1, 0))
5527 n_global_fp_regs
+= 2;
5530 /* In the flat window model, find out which local and in registers need to
5531 be saved. We don't reserve space in the current frame for them as they
5532 will be spilled into the register window save area of the caller's frame.
5533 However, as soon as we use this register window save area, we must create
5534 that of the current frame to make it the live one. */
5536 for (i
= 16; i
< 32; i
++)
5537 if (save_local_or_in_reg_p (i
, leaf_function
))
5539 save_local_in_regs_p
= true;
5543 /* Calculate space needed for FP registers. */
5544 for (i
= 32; i
< (TARGET_V9
? 96 : 64); i
+= 2)
5545 if (save_global_or_fp_reg_p (i
, 0) || save_global_or_fp_reg_p (i
+ 1, 0))
5546 n_global_fp_regs
+= 2;
5549 && n_global_fp_regs
== 0
5551 && !save_local_in_regs_p
)
5552 frame_size
= apparent_frame_size
= 0;
5555 /* Start from the apparent frame size. */
5556 apparent_frame_size
= ROUND_UP (size
, 8) + n_global_fp_regs
* 4;
5558 /* We need to add the size of the outgoing argument area. */
5559 frame_size
= apparent_frame_size
+ ROUND_UP (args_size
, 8);
5561 /* And that of the register window save area. */
5562 frame_size
+= FIRST_PARM_OFFSET (cfun
->decl
);
5564 /* Finally, bump to the appropriate alignment. */
5565 frame_size
= SPARC_STACK_ALIGN (frame_size
);
5568 /* Set up values for use in prologue and epilogue. */
5569 sparc_frame_size
= frame_size
;
5570 sparc_apparent_frame_size
= apparent_frame_size
;
5571 sparc_n_global_fp_regs
= n_global_fp_regs
;
5572 sparc_save_local_in_regs_p
= save_local_in_regs_p
;
5577 /* Implement the macro INITIAL_ELIMINATION_OFFSET, return the OFFSET. */
5580 sparc_initial_elimination_offset (int to
)
5584 if (to
== STACK_POINTER_REGNUM
)
5585 offset
= sparc_compute_frame_size (get_frame_size (), crtl
->is_leaf
);
5589 offset
+= SPARC_STACK_BIAS
;
5593 /* Output any necessary .register pseudo-ops. */
5596 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED
)
5603 /* Check if %g[2367] were used without
5604 .register being printed for them already. */
5605 for (i
= 2; i
< 8; i
++)
5607 if (df_regs_ever_live_p (i
)
5608 && ! sparc_hard_reg_printed
[i
])
5610 sparc_hard_reg_printed
[i
] = 1;
5611 /* %g7 is used as TLS base register, use #ignore
5612 for it instead of #scratch. */
5613 fprintf (file
, "\t.register\t%%g%d, #%s\n", i
,
5614 i
== 7 ? "ignore" : "scratch");
5620 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
5622 #if PROBE_INTERVAL > 4096
5623 #error Cannot use indexed addressing mode for stack probing
5626 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
5627 inclusive. These are offsets from the current stack pointer.
5629 Note that we don't use the REG+REG addressing mode for the probes because
5630 of the stack bias in 64-bit mode. And it doesn't really buy us anything
5631 so the advantages of having a single code win here. */
5634 sparc_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
5636 rtx g1
= gen_rtx_REG (Pmode
, 1);
5638 /* See if we have a constant small number of probes to generate. If so,
5639 that's the easy case. */
5640 if (size
<= PROBE_INTERVAL
)
5642 emit_move_insn (g1
, GEN_INT (first
));
5643 emit_insn (gen_rtx_SET (g1
,
5644 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
5645 emit_stack_probe (plus_constant (Pmode
, g1
, -size
));
5648 /* The run-time loop is made up of 9 insns in the generic case while the
5649 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
5650 else if (size
<= 4 * PROBE_INTERVAL
)
5654 emit_move_insn (g1
, GEN_INT (first
+ PROBE_INTERVAL
));
5655 emit_insn (gen_rtx_SET (g1
,
5656 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
5657 emit_stack_probe (g1
);
5659 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
5660 it exceeds SIZE. If only two probes are needed, this will not
5661 generate any code. Then probe at FIRST + SIZE. */
5662 for (i
= 2 * PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
5664 emit_insn (gen_rtx_SET (g1
,
5665 plus_constant (Pmode
, g1
, -PROBE_INTERVAL
)));
5666 emit_stack_probe (g1
);
5669 emit_stack_probe (plus_constant (Pmode
, g1
,
5670 (i
- PROBE_INTERVAL
) - size
));
5673 /* Otherwise, do the same as above, but in a loop. Note that we must be
5674 extra careful with variables wrapping around because we might be at
5675 the very top (or the very bottom) of the address space and we have
5676 to be able to handle this case properly; in particular, we use an
5677 equality test for the loop condition. */
5680 HOST_WIDE_INT rounded_size
;
5681 rtx g4
= gen_rtx_REG (Pmode
, 4);
5683 emit_move_insn (g1
, GEN_INT (first
));
5686 /* Step 1: round SIZE to the previous multiple of the interval. */
5688 rounded_size
= ROUND_DOWN (size
, PROBE_INTERVAL
);
5689 emit_move_insn (g4
, GEN_INT (rounded_size
));
5692 /* Step 2: compute initial and final value of the loop counter. */
5694 /* TEST_ADDR = SP + FIRST. */
5695 emit_insn (gen_rtx_SET (g1
,
5696 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
5698 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
5699 emit_insn (gen_rtx_SET (g4
, gen_rtx_MINUS (Pmode
, g1
, g4
)));
5704 while (TEST_ADDR != LAST_ADDR)
5706 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
5710 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
5711 until it is equal to ROUNDED_SIZE. */
5714 emit_insn (gen_probe_stack_rangedi (g1
, g1
, g4
));
5716 emit_insn (gen_probe_stack_rangesi (g1
, g1
, g4
));
5719 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
5720 that SIZE is equal to ROUNDED_SIZE. */
5722 if (size
!= rounded_size
)
5723 emit_stack_probe (plus_constant (Pmode
, g4
, rounded_size
- size
));
5726 /* Make sure nothing is scheduled before we are done. */
5727 emit_insn (gen_blockage ());
5730 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
5731 absolute addresses. */
5734 output_probe_stack_range (rtx reg1
, rtx reg2
)
5736 static int labelno
= 0;
5740 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
++);
5743 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
5745 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
5747 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
5748 output_asm_insn ("add\t%0, %1, %0", xops
);
5750 /* Test if TEST_ADDR == LAST_ADDR. */
5752 output_asm_insn ("cmp\t%0, %1", xops
);
5754 /* Probe at TEST_ADDR and branch. */
5756 fputs ("\tbne,pt\t%xcc,", asm_out_file
);
5758 fputs ("\tbne\t", asm_out_file
);
5759 assemble_name_raw (asm_out_file
, loop_lab
);
5760 fputc ('\n', asm_out_file
);
5761 xops
[1] = GEN_INT (SPARC_STACK_BIAS
);
5762 output_asm_insn (" st\t%%g0, [%0+%1]", xops
);
5767 /* Emit code to save/restore registers from LOW to HIGH at BASE+OFFSET as
5768 needed. LOW is supposed to be double-word aligned for 32-bit registers.
5769 SAVE_P decides whether a register must be saved/restored. ACTION_TRUE
5770 is the action to be performed if SAVE_P returns true and ACTION_FALSE
5771 the action to be performed if it returns false. Return the new offset. */
5773 typedef bool (*sorr_pred_t
) (unsigned int, int);
5774 typedef enum { SORR_NONE
, SORR_ADVANCE
, SORR_SAVE
, SORR_RESTORE
} sorr_act_t
;
5777 emit_save_or_restore_regs (unsigned int low
, unsigned int high
, rtx base
,
5778 int offset
, int leaf_function
, sorr_pred_t save_p
,
5779 sorr_act_t action_true
, sorr_act_t action_false
)
5785 if (TARGET_ARCH64
&& high
<= 32)
5789 for (i
= low
; i
< high
; i
++)
5791 if (save_p (i
, leaf_function
))
5793 mem
= gen_frame_mem (DImode
, plus_constant (Pmode
,
5795 if (action_true
== SORR_SAVE
)
5797 insn
= emit_move_insn (mem
, gen_rtx_REG (DImode
, i
));
5798 RTX_FRAME_RELATED_P (insn
) = 1;
5800 else /* action_true == SORR_RESTORE */
5802 /* The frame pointer must be restored last since its old
5803 value may be used as base address for the frame. This
5804 is problematic in 64-bit mode only because of the lack
5805 of double-word load instruction. */
5806 if (i
== HARD_FRAME_POINTER_REGNUM
)
5809 emit_move_insn (gen_rtx_REG (DImode
, i
), mem
);
5813 else if (action_false
== SORR_ADVANCE
)
5819 mem
= gen_frame_mem (DImode
, plus_constant (Pmode
, base
, fp_offset
));
5820 emit_move_insn (hard_frame_pointer_rtx
, mem
);
5825 for (i
= low
; i
< high
; i
+= 2)
5827 bool reg0
= save_p (i
, leaf_function
);
5828 bool reg1
= save_p (i
+ 1, leaf_function
);
5834 mode
= SPARC_INT_REG_P (i
) ? E_DImode
: E_DFmode
;
5839 mode
= SPARC_INT_REG_P (i
) ? E_SImode
: E_SFmode
;
5844 mode
= SPARC_INT_REG_P (i
) ? E_SImode
: E_SFmode
;
5850 if (action_false
== SORR_ADVANCE
)
5855 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, base
, offset
));
5856 if (action_true
== SORR_SAVE
)
5858 insn
= emit_move_insn (mem
, gen_rtx_REG (mode
, regno
));
5859 RTX_FRAME_RELATED_P (insn
) = 1;
5863 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, base
,
5865 set1
= gen_rtx_SET (mem
, gen_rtx_REG (SImode
, regno
));
5866 RTX_FRAME_RELATED_P (set1
) = 1;
5868 = gen_frame_mem (SImode
, plus_constant (Pmode
, base
,
5870 set2
= gen_rtx_SET (mem
, gen_rtx_REG (SImode
, regno
+ 1));
5871 RTX_FRAME_RELATED_P (set2
) = 1;
5872 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
5873 gen_rtx_PARALLEL (VOIDmode
,
5874 gen_rtvec (2, set1
, set2
)));
5877 else /* action_true == SORR_RESTORE */
5878 emit_move_insn (gen_rtx_REG (mode
, regno
), mem
);
5880 /* Bump and round down to double word
5881 in case we already bumped by 4. */
5882 offset
= ROUND_DOWN (offset
+ 8, 8);
5889 /* Emit code to adjust BASE to OFFSET. Return the new base. */
5892 emit_adjust_base_to_offset (rtx base
, int offset
)
5894 /* ??? This might be optimized a little as %g1 might already have a
5895 value close enough that a single add insn will do. */
5896 /* ??? Although, all of this is probably only a temporary fix because
5897 if %g1 can hold a function result, then sparc_expand_epilogue will
5898 lose (the result will be clobbered). */
5899 rtx new_base
= gen_rtx_REG (Pmode
, 1);
5900 emit_move_insn (new_base
, GEN_INT (offset
));
5901 emit_insn (gen_rtx_SET (new_base
, gen_rtx_PLUS (Pmode
, base
, new_base
)));
5905 /* Emit code to save/restore call-saved global and FP registers. */
5908 emit_save_or_restore_global_fp_regs (rtx base
, int offset
, sorr_act_t action
)
5910 if (offset
< -4096 || offset
+ sparc_n_global_fp_regs
* 4 > 4095)
5912 base
= emit_adjust_base_to_offset (base
, offset
);
5917 = emit_save_or_restore_regs (0, 8, base
, offset
, 0,
5918 save_global_or_fp_reg_p
, action
, SORR_NONE
);
5919 emit_save_or_restore_regs (32, TARGET_V9
? 96 : 64, base
, offset
, 0,
5920 save_global_or_fp_reg_p
, action
, SORR_NONE
);
5923 /* Emit code to save/restore call-saved local and in registers. */
5926 emit_save_or_restore_local_in_regs (rtx base
, int offset
, sorr_act_t action
)
5928 if (offset
< -4096 || offset
+ 16 * UNITS_PER_WORD
> 4095)
5930 base
= emit_adjust_base_to_offset (base
, offset
);
5934 emit_save_or_restore_regs (16, 32, base
, offset
, sparc_leaf_function_p
,
5935 save_local_or_in_reg_p
, action
, SORR_ADVANCE
);
5938 /* Emit a window_save insn. */
5941 emit_window_save (rtx increment
)
5943 rtx_insn
*insn
= emit_insn (gen_window_save (increment
));
5944 RTX_FRAME_RELATED_P (insn
) = 1;
5946 /* The incoming return address (%o7) is saved in %i7. */
5947 add_reg_note (insn
, REG_CFA_REGISTER
,
5948 gen_rtx_SET (gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
),
5950 INCOMING_RETURN_ADDR_REGNUM
)));
5952 /* The window save event. */
5953 add_reg_note (insn
, REG_CFA_WINDOW_SAVE
, const0_rtx
);
5955 /* The CFA is %fp, the hard frame pointer. */
5956 add_reg_note (insn
, REG_CFA_DEF_CFA
,
5957 plus_constant (Pmode
, hard_frame_pointer_rtx
,
5958 INCOMING_FRAME_SP_OFFSET
));
5963 /* Generate an increment for the stack pointer. */
5966 gen_stack_pointer_inc (rtx increment
)
5968 return gen_rtx_SET (stack_pointer_rtx
,
5969 gen_rtx_PLUS (Pmode
,
5974 /* Expand the function prologue. The prologue is responsible for reserving
5975 storage for the frame, saving the call-saved registers and loading the
5976 GOT register if needed. */
5979 sparc_expand_prologue (void)
5984 /* Compute a snapshot of crtl->uses_only_leaf_regs. Relying
5985 on the final value of the flag means deferring the prologue/epilogue
5986 expansion until just before the second scheduling pass, which is too
5987 late to emit multiple epilogues or return insns.
5989 Of course we are making the assumption that the value of the flag
5990 will not change between now and its final value. Of the three parts
5991 of the formula, only the last one can reasonably vary. Let's take a
5992 closer look, after assuming that the first two ones are set to true
5993 (otherwise the last value is effectively silenced).
5995 If only_leaf_regs_used returns false, the global predicate will also
5996 be false so the actual frame size calculated below will be positive.
5997 As a consequence, the save_register_window insn will be emitted in
5998 the instruction stream; now this insn explicitly references %fp
5999 which is not a leaf register so only_leaf_regs_used will always
6000 return false subsequently.
6002 If only_leaf_regs_used returns true, we hope that the subsequent
6003 optimization passes won't cause non-leaf registers to pop up. For
6004 example, the regrename pass has special provisions to not rename to
6005 non-leaf registers in a leaf function. */
6006 sparc_leaf_function_p
6007 = optimize
> 0 && crtl
->is_leaf
&& only_leaf_regs_used ();
6009 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
6011 if (flag_stack_usage_info
)
6012 current_function_static_stack_size
= size
;
6014 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
6015 || flag_stack_clash_protection
)
6017 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
6019 if (size
> PROBE_INTERVAL
&& size
> get_stack_check_protect ())
6020 sparc_emit_probe_stack_range (get_stack_check_protect (),
6021 size
- get_stack_check_protect ());
6024 sparc_emit_probe_stack_range (get_stack_check_protect (), size
);
6029 else if (sparc_leaf_function_p
)
6031 rtx size_int_rtx
= GEN_INT (-size
);
6034 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
6035 else if (size
<= 8192)
6037 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
6038 RTX_FRAME_RELATED_P (insn
) = 1;
6040 /* %sp is still the CFA register. */
6041 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
6045 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
6046 emit_move_insn (size_rtx
, size_int_rtx
);
6047 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
6048 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
6049 gen_stack_pointer_inc (size_int_rtx
));
6052 RTX_FRAME_RELATED_P (insn
) = 1;
6056 rtx size_int_rtx
= GEN_INT (-size
);
6059 emit_window_save (size_int_rtx
);
6060 else if (size
<= 8192)
6062 emit_window_save (GEN_INT (-4096));
6064 /* %sp is not the CFA register anymore. */
6065 emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
6067 /* Make sure no %fp-based store is issued until after the frame is
6068 established. The offset between the frame pointer and the stack
6069 pointer is calculated relative to the value of the stack pointer
6070 at the end of the function prologue, and moving instructions that
6071 access the stack via the frame pointer between the instructions
6072 that decrement the stack pointer could result in accessing the
6073 register window save area, which is volatile. */
6074 emit_insn (gen_frame_blockage ());
6078 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
6079 emit_move_insn (size_rtx
, size_int_rtx
);
6080 emit_window_save (size_rtx
);
6084 if (sparc_leaf_function_p
)
6086 sparc_frame_base_reg
= stack_pointer_rtx
;
6087 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
6091 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
6092 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
6095 if (sparc_n_global_fp_regs
> 0)
6096 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
6097 sparc_frame_base_offset
6098 - sparc_apparent_frame_size
,
6101 /* Advertise that the data calculated just above are now valid. */
6102 sparc_prologue_data_valid_p
= true;
6105 /* Expand the function prologue. The prologue is responsible for reserving
6106 storage for the frame, saving the call-saved registers and loading the
6107 GOT register if needed. */
6110 sparc_flat_expand_prologue (void)
6115 sparc_leaf_function_p
= optimize
> 0 && crtl
->is_leaf
;
6117 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
6119 if (flag_stack_usage_info
)
6120 current_function_static_stack_size
= size
;
6122 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
6123 || flag_stack_clash_protection
)
6125 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
6127 if (size
> PROBE_INTERVAL
&& size
> get_stack_check_protect ())
6128 sparc_emit_probe_stack_range (get_stack_check_protect (),
6129 size
- get_stack_check_protect ());
6132 sparc_emit_probe_stack_range (get_stack_check_protect (), size
);
6135 if (sparc_save_local_in_regs_p
)
6136 emit_save_or_restore_local_in_regs (stack_pointer_rtx
, SPARC_STACK_BIAS
,
6143 rtx size_int_rtx
, size_rtx
;
6145 size_rtx
= size_int_rtx
= GEN_INT (-size
);
6147 /* We establish the frame (i.e. decrement the stack pointer) first, even
6148 if we use a frame pointer, because we cannot clobber any call-saved
6149 registers, including the frame pointer, if we haven't created a new
6150 register save area, for the sake of compatibility with the ABI. */
6152 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
6153 else if (size
<= 8192 && !frame_pointer_needed
)
6155 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
6156 RTX_FRAME_RELATED_P (insn
) = 1;
6157 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
6161 size_rtx
= gen_rtx_REG (Pmode
, 1);
6162 emit_move_insn (size_rtx
, size_int_rtx
);
6163 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
6164 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
6165 gen_stack_pointer_inc (size_int_rtx
));
6167 RTX_FRAME_RELATED_P (insn
) = 1;
6169 /* Ensure nothing is scheduled until after the frame is established. */
6170 emit_insn (gen_blockage ());
6172 if (frame_pointer_needed
)
6174 insn
= emit_insn (gen_rtx_SET (hard_frame_pointer_rtx
,
6175 gen_rtx_MINUS (Pmode
,
6178 RTX_FRAME_RELATED_P (insn
) = 1;
6180 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
6181 gen_rtx_SET (hard_frame_pointer_rtx
,
6182 plus_constant (Pmode
, stack_pointer_rtx
,
6186 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
6188 rtx o7
= gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
);
6189 rtx i7
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
6191 insn
= emit_move_insn (i7
, o7
);
6192 RTX_FRAME_RELATED_P (insn
) = 1;
6194 add_reg_note (insn
, REG_CFA_REGISTER
, gen_rtx_SET (i7
, o7
));
6196 /* Prevent this instruction from ever being considered dead,
6197 even if this function has no epilogue. */
6202 if (frame_pointer_needed
)
6204 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
6205 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
6209 sparc_frame_base_reg
= stack_pointer_rtx
;
6210 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
6213 if (sparc_n_global_fp_regs
> 0)
6214 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
6215 sparc_frame_base_offset
6216 - sparc_apparent_frame_size
,
6219 /* Advertise that the data calculated just above are now valid. */
6220 sparc_prologue_data_valid_p
= true;
6223 /* This function generates the assembly code for function entry, which boils
6224 down to emitting the necessary .register directives. */
6227 sparc_asm_function_prologue (FILE *file
)
6229 /* Check that the assumption we made in sparc_expand_prologue is valid. */
6231 gcc_assert (sparc_leaf_function_p
== crtl
->uses_only_leaf_regs
);
6233 sparc_output_scratch_registers (file
);
6236 /* Expand the function epilogue, either normal or part of a sibcall.
6237 We emit all the instructions except the return or the call. */
6240 sparc_expand_epilogue (bool for_eh
)
6242 HOST_WIDE_INT size
= sparc_frame_size
;
6244 if (cfun
->calls_alloca
)
6245 emit_insn (gen_frame_blockage ());
6247 if (sparc_n_global_fp_regs
> 0)
6248 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
6249 sparc_frame_base_offset
6250 - sparc_apparent_frame_size
,
6253 if (size
== 0 || for_eh
)
6255 else if (sparc_leaf_function_p
)
6258 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
6259 else if (size
<= 8192)
6261 emit_insn (gen_stack_pointer_inc (GEN_INT (4096)));
6262 emit_insn (gen_stack_pointer_inc (GEN_INT (size
- 4096)));
6266 rtx reg
= gen_rtx_REG (Pmode
, 1);
6267 emit_move_insn (reg
, GEN_INT (size
));
6268 emit_insn (gen_stack_pointer_inc (reg
));
6273 /* Expand the function epilogue, either normal or part of a sibcall.
6274 We emit all the instructions except the return or the call. */
6277 sparc_flat_expand_epilogue (bool for_eh
)
6279 HOST_WIDE_INT size
= sparc_frame_size
;
6281 if (sparc_n_global_fp_regs
> 0)
6282 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
6283 sparc_frame_base_offset
6284 - sparc_apparent_frame_size
,
6287 /* If we have a frame pointer, we'll need both to restore it before the
6288 frame is destroyed and use its current value in destroying the frame.
6289 Since we don't have an atomic way to do that in the flat window model,
6290 we save the current value into a temporary register (%g1). */
6291 if (frame_pointer_needed
&& !for_eh
)
6292 emit_move_insn (gen_rtx_REG (Pmode
, 1), hard_frame_pointer_rtx
);
6294 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
6295 emit_move_insn (gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
),
6296 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
));
6298 if (sparc_save_local_in_regs_p
)
6299 emit_save_or_restore_local_in_regs (sparc_frame_base_reg
,
6300 sparc_frame_base_offset
,
6303 if (size
== 0 || for_eh
)
6305 else if (frame_pointer_needed
)
6307 /* Make sure the frame is destroyed after everything else is done. */
6308 emit_insn (gen_blockage ());
6310 emit_move_insn (stack_pointer_rtx
, gen_rtx_REG (Pmode
, 1));
6315 emit_insn (gen_blockage ());
6318 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
6319 else if (size
<= 8192)
6321 emit_insn (gen_stack_pointer_inc (GEN_INT (4096)));
6322 emit_insn (gen_stack_pointer_inc (GEN_INT (size
- 4096)));
6326 rtx reg
= gen_rtx_REG (Pmode
, 1);
6327 emit_move_insn (reg
, GEN_INT (size
));
6328 emit_insn (gen_stack_pointer_inc (reg
));
6333 /* Return true if it is appropriate to emit `return' instructions in the
6334 body of a function. */
6337 sparc_can_use_return_insn_p (void)
6339 return sparc_prologue_data_valid_p
6340 && sparc_n_global_fp_regs
== 0
6342 ? (sparc_frame_size
== 0 && !sparc_save_local_in_regs_p
)
6343 : (sparc_frame_size
== 0 || !sparc_leaf_function_p
);
6346 /* This function generates the assembly code for function exit. */
6349 sparc_asm_function_epilogue (FILE *file
)
6351 /* If the last two instructions of a function are "call foo; dslot;"
6352 the return address might point to the first instruction in the next
6353 function and we have to output a dummy nop for the sake of sane
6354 backtraces in such cases. This is pointless for sibling calls since
6355 the return address is explicitly adjusted. */
6357 rtx_insn
*insn
= get_last_insn ();
6359 rtx last_real_insn
= prev_real_insn (insn
);
6361 && NONJUMP_INSN_P (last_real_insn
)
6362 && GET_CODE (PATTERN (last_real_insn
)) == SEQUENCE
)
6363 last_real_insn
= XVECEXP (PATTERN (last_real_insn
), 0, 0);
6366 && CALL_P (last_real_insn
)
6367 && !SIBLING_CALL_P (last_real_insn
))
6368 fputs("\tnop\n", file
);
6370 sparc_output_deferred_case_vectors ();
6373 /* Output a 'restore' instruction. */
6376 output_restore (rtx pat
)
6382 fputs ("\t restore\n", asm_out_file
);
6386 gcc_assert (GET_CODE (pat
) == SET
);
6388 operands
[0] = SET_DEST (pat
);
6389 pat
= SET_SRC (pat
);
6391 switch (GET_CODE (pat
))
6394 operands
[1] = XEXP (pat
, 0);
6395 operands
[2] = XEXP (pat
, 1);
6396 output_asm_insn (" restore %r1, %2, %Y0", operands
);
6399 operands
[1] = XEXP (pat
, 0);
6400 operands
[2] = XEXP (pat
, 1);
6401 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands
);
6404 operands
[1] = XEXP (pat
, 0);
6405 gcc_assert (XEXP (pat
, 1) == const1_rtx
);
6406 output_asm_insn (" restore %r1, %r1, %Y0", operands
);
6410 output_asm_insn (" restore %%g0, %1, %Y0", operands
);
6415 /* Output a return. */
6418 output_return (rtx_insn
*insn
)
6420 if (crtl
->calls_eh_return
)
6422 /* If the function uses __builtin_eh_return, the eh_return
6423 machinery occupies the delay slot. */
6424 gcc_assert (!final_sequence
);
6426 if (flag_delayed_branch
)
6428 if (!TARGET_FLAT
&& TARGET_V9
)
6429 fputs ("\treturn\t%i7+8\n", asm_out_file
);
6433 fputs ("\trestore\n", asm_out_file
);
6435 fputs ("\tjmp\t%o7+8\n", asm_out_file
);
6438 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file
);
6443 fputs ("\trestore\n", asm_out_file
);
6445 fputs ("\tadd\t%sp, %g1, %sp\n", asm_out_file
);
6446 fputs ("\tjmp\t%o7+8\n\t nop\n", asm_out_file
);
6449 else if (sparc_leaf_function_p
|| TARGET_FLAT
)
6451 /* This is a leaf or flat function so we don't have to bother restoring
6452 the register window, which frees us from dealing with the convoluted
6453 semantics of restore/return. We simply output the jump to the
6454 return address and the insn in the delay slot (if any). */
6456 return "jmp\t%%o7+%)%#";
6460 /* This is a regular function so we have to restore the register window.
6461 We may have a pending insn for the delay slot, which will be either
6462 combined with the 'restore' instruction or put in the delay slot of
6463 the 'return' instruction. */
6470 delay
= NEXT_INSN (insn
);
6473 pat
= PATTERN (delay
);
6475 if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1))
6477 epilogue_renumber (&pat
, 0);
6478 return "return\t%%i7+%)%#";
6482 output_asm_insn ("jmp\t%%i7+%)", NULL
);
6484 /* We're going to output the insn in the delay slot manually.
6485 Make sure to output its source location first. */
6486 PATTERN (delay
) = gen_blockage ();
6487 INSN_CODE (delay
) = -1;
6488 final_scan_insn (delay
, asm_out_file
, optimize
, 0, NULL
);
6489 INSN_LOCATION (delay
) = UNKNOWN_LOCATION
;
6491 output_restore (pat
);
6496 /* The delay slot is empty. */
6498 return "return\t%%i7+%)\n\t nop";
6499 else if (flag_delayed_branch
)
6500 return "jmp\t%%i7+%)\n\t restore";
6502 return "restore\n\tjmp\t%%o7+%)\n\t nop";
6509 /* Output a sibling call. */
6512 output_sibcall (rtx_insn
*insn
, rtx call_operand
)
6516 gcc_assert (flag_delayed_branch
);
6518 operands
[0] = call_operand
;
6520 if (sparc_leaf_function_p
|| TARGET_FLAT
)
6522 /* This is a leaf or flat function so we don't have to bother restoring
6523 the register window. We simply output the jump to the function and
6524 the insn in the delay slot (if any). */
6526 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P
&& final_sequence
));
6529 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
6532 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
6533 it into branch if possible. */
6534 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
6539 /* This is a regular function so we have to restore the register window.
6540 We may have a pending insn for the delay slot, which will be combined
6541 with the 'restore' instruction. */
6543 output_asm_insn ("call\t%a0, 0", operands
);
6550 delay
= NEXT_INSN (insn
);
6553 pat
= PATTERN (delay
);
6555 /* We're going to output the insn in the delay slot manually.
6556 Make sure to output its source location first. */
6557 PATTERN (delay
) = gen_blockage ();
6558 INSN_CODE (delay
) = -1;
6559 final_scan_insn (delay
, asm_out_file
, optimize
, 0, NULL
);
6560 INSN_LOCATION (delay
) = UNKNOWN_LOCATION
;
6562 output_restore (pat
);
6565 output_restore (NULL_RTX
);
6571 /* Functions for handling argument passing.
6573 For 32-bit, the first 6 args are normally in registers and the rest are
6574 pushed. Any arg that starts within the first 6 words is at least
6575 partially passed in a register unless its data type forbids.
6577 For 64-bit, the argument registers are laid out as an array of 16 elements
6578 and arguments are added sequentially. The first 6 int args and up to the
6579 first 16 fp args (depending on size) are passed in regs.
6581 Slot Stack Integral Float Float in structure Double Long Double
6582 ---- ----- -------- ----- ------------------ ------ -----------
6583 15 [SP+248] %f31 %f30,%f31 %d30
6584 14 [SP+240] %f29 %f28,%f29 %d28 %q28
6585 13 [SP+232] %f27 %f26,%f27 %d26
6586 12 [SP+224] %f25 %f24,%f25 %d24 %q24
6587 11 [SP+216] %f23 %f22,%f23 %d22
6588 10 [SP+208] %f21 %f20,%f21 %d20 %q20
6589 9 [SP+200] %f19 %f18,%f19 %d18
6590 8 [SP+192] %f17 %f16,%f17 %d16 %q16
6591 7 [SP+184] %f15 %f14,%f15 %d14
6592 6 [SP+176] %f13 %f12,%f13 %d12 %q12
6593 5 [SP+168] %o5 %f11 %f10,%f11 %d10
6594 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
6595 3 [SP+152] %o3 %f7 %f6,%f7 %d6
6596 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
6597 1 [SP+136] %o1 %f3 %f2,%f3 %d2
6598 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
6600 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
6602 Integral arguments are always passed as 64-bit quantities appropriately
6605 Passing of floating point values is handled as follows.
6606 If a prototype is in scope:
6607 If the value is in a named argument (i.e. not a stdarg function or a
6608 value not part of the `...') then the value is passed in the appropriate
6610 If the value is part of the `...' and is passed in one of the first 6
6611 slots then the value is passed in the appropriate int reg.
6612 If the value is part of the `...' and is not passed in one of the first 6
6613 slots then the value is passed in memory.
6614 If a prototype is not in scope:
6615 If the value is one of the first 6 arguments the value is passed in the
6616 appropriate integer reg and the appropriate fp reg.
6617 If the value is not one of the first 6 arguments the value is passed in
6618 the appropriate fp reg and in memory.
6621 Summary of the calling conventions implemented by GCC on the SPARC:
6624 size argument return value
6626 small integer <4 int. reg. int. reg.
6627 word 4 int. reg. int. reg.
6628 double word 8 int. reg. int. reg.
6630 _Complex small integer <8 int. reg. int. reg.
6631 _Complex word 8 int. reg. int. reg.
6632 _Complex double word 16 memory int. reg.
6634 vector integer <=8 int. reg. FP reg.
6635 vector integer >8 memory memory
6637 float 4 int. reg. FP reg.
6638 double 8 int. reg. FP reg.
6639 long double 16 memory memory
6641 _Complex float 8 memory FP reg.
6642 _Complex double 16 memory FP reg.
6643 _Complex long double 32 memory FP reg.
6645 vector float any memory memory
6647 aggregate any memory memory
6652 size argument return value
6654 small integer <8 int. reg. int. reg.
6655 word 8 int. reg. int. reg.
6656 double word 16 int. reg. int. reg.
6658 _Complex small integer <16 int. reg. int. reg.
6659 _Complex word 16 int. reg. int. reg.
6660 _Complex double word 32 memory int. reg.
6662 vector integer <=16 FP reg. FP reg.
6663 vector integer 16<s<=32 memory FP reg.
6664 vector integer >32 memory memory
6666 float 4 FP reg. FP reg.
6667 double 8 FP reg. FP reg.
6668 long double 16 FP reg. FP reg.
6670 _Complex float 8 FP reg. FP reg.
6671 _Complex double 16 FP reg. FP reg.
6672 _Complex long double 32 memory FP reg.
6674 vector float <=16 FP reg. FP reg.
6675 vector float 16<s<=32 memory FP reg.
6676 vector float >32 memory memory
6678 aggregate <=16 reg. reg.
6679 aggregate 16<s<=32 memory reg.
6680 aggregate >32 memory memory
6684 Note #1: complex floating-point types follow the extended SPARC ABIs as
6685 implemented by the Sun compiler.
6687 Note #2: integer vector types follow the scalar floating-point types
6688 conventions to match what is implemented by the Sun VIS SDK.
6690 Note #3: floating-point vector types follow the aggregate types
6694 /* Maximum number of int regs for args. */
6695 #define SPARC_INT_ARG_MAX 6
6696 /* Maximum number of fp regs for args. */
6697 #define SPARC_FP_ARG_MAX 16
6698 /* Number of words (partially) occupied for a given size in units. */
6699 #define CEIL_NWORDS(SIZE) CEIL((SIZE), UNITS_PER_WORD)
6701 /* Handle the INIT_CUMULATIVE_ARGS macro.
6702 Initialize a variable CUM of type CUMULATIVE_ARGS
6703 for a call to a function whose data type is FNTYPE.
6704 For a library call, FNTYPE is 0. */
6707 init_cumulative_args (struct sparc_args
*cum
, tree fntype
, rtx
, tree
)
6710 cum
->prototype_p
= fntype
&& prototype_p (fntype
);
6711 cum
->libcall_p
= !fntype
;
6714 /* Handle promotion of pointer and integer arguments. */
6717 sparc_promote_function_mode (const_tree type
, machine_mode mode
,
6718 int *punsignedp
, const_tree
, int)
6720 if (type
&& POINTER_TYPE_P (type
))
6722 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
6726 /* Integral arguments are passed as full words, as per the ABI. */
6727 if (GET_MODE_CLASS (mode
) == MODE_INT
6728 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
6734 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
6737 sparc_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
6739 return TARGET_ARCH64
? true : false;
6742 /* Handle the TARGET_PASS_BY_REFERENCE target hook.
6743 Specify whether to pass the argument by reference. */
6746 sparc_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
6747 machine_mode mode
, const_tree type
,
6748 bool named ATTRIBUTE_UNUSED
)
6751 /* Original SPARC 32-bit ABI says that structures and unions,
6752 and quad-precision floats are passed by reference.
6753 All other base types are passed in registers.
6755 Extended ABI (as implemented by the Sun compiler) says that all
6756 complex floats are passed by reference. Pass complex integers
6757 in registers up to 8 bytes. More generally, enforce the 2-word
6758 cap for passing arguments in registers.
6760 Vector ABI (as implemented by the Sun VIS SDK) says that integer
6761 vectors are passed like floats of the same size, that is in
6762 registers up to 8 bytes. Pass all vector floats by reference
6763 like structure and unions. */
6764 return ((type
&& (AGGREGATE_TYPE_P (type
) || VECTOR_FLOAT_TYPE_P (type
)))
6766 /* Catch CDImode, TFmode, DCmode and TCmode. */
6767 || GET_MODE_SIZE (mode
) > 8
6769 && VECTOR_TYPE_P (type
)
6770 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
6772 /* Original SPARC 64-bit ABI says that structures and unions
6773 smaller than 16 bytes are passed in registers, as well as
6774 all other base types.
6776 Extended ABI (as implemented by the Sun compiler) says that
6777 complex floats are passed in registers up to 16 bytes. Pass
6778 all complex integers in registers up to 16 bytes. More generally,
6779 enforce the 2-word cap for passing arguments in registers.
6781 Vector ABI (as implemented by the Sun VIS SDK) says that integer
6782 vectors are passed like floats of the same size, that is in
6783 registers (up to 16 bytes). Pass all vector floats like structure
6786 && (AGGREGATE_TYPE_P (type
) || VECTOR_TYPE_P (type
))
6787 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 16)
6788 /* Catch CTImode and TCmode. */
6789 || GET_MODE_SIZE (mode
) > 16);
6792 /* Traverse the record TYPE recursively and call FUNC on its fields.
6793 NAMED is true if this is for a named parameter. DATA is passed
6794 to FUNC for each field. OFFSET is the starting position and
6795 PACKED is true if we are inside a packed record. */
6797 template <typename T
, void Func (const_tree
, int, bool, T
*)>
6799 traverse_record_type (const_tree type
, bool named
, T
*data
,
6800 int offset
= 0, bool packed
= false)
6802 /* The ABI obviously doesn't specify how packed structures are passed.
6803 These are passed in integer regs if possible, otherwise memory. */
6805 for (tree field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
6806 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
6812 /* Walk the real fields, but skip those with no size or a zero size.
6813 ??? Fields with variable offset are handled as having zero offset. */
6814 for (tree field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
6815 if (TREE_CODE (field
) == FIELD_DECL
)
6817 if (!DECL_SIZE (field
) || integer_zerop (DECL_SIZE (field
)))
6820 int bitpos
= offset
;
6821 if (TREE_CODE (DECL_FIELD_OFFSET (field
)) == INTEGER_CST
)
6822 bitpos
+= int_bit_position (field
);
6824 tree field_type
= TREE_TYPE (field
);
6825 if (TREE_CODE (field_type
) == RECORD_TYPE
)
6826 traverse_record_type
<T
, Func
> (field_type
, named
, data
, bitpos
,
6831 = FLOAT_TYPE_P (field_type
) || VECTOR_TYPE_P (field_type
);
6832 Func (field
, bitpos
, fp_type
&& named
&& !packed
&& TARGET_FPU
,
6838 /* Handle recursive register classifying for structure layout. */
6842 bool fp_regs
; /* true if field eligible to FP registers. */
6843 bool fp_regs_in_first_word
; /* true if such field in first word. */
6846 /* A subroutine of function_arg_slotno. Classify the field. */
6849 classify_registers (const_tree
, int bitpos
, bool fp
, classify_data_t
*data
)
6853 data
->fp_regs
= true;
6854 if (bitpos
< BITS_PER_WORD
)
6855 data
->fp_regs_in_first_word
= true;
6859 /* Compute the slot number to pass an argument in.
6860 Return the slot number or -1 if passing on the stack.
6862 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6863 the preceding args and about the function being called.
6864 MODE is the argument's machine mode.
6865 TYPE is the data type of the argument (as a tree).
6866 This is null for libcalls where that information may
6868 NAMED is nonzero if this argument is a named parameter
6869 (otherwise it is an extra parameter matching an ellipsis).
6870 INCOMING is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
6871 *PREGNO records the register number to use if scalar type.
6872 *PPADDING records the amount of padding needed in words. */
6875 function_arg_slotno (const struct sparc_args
*cum
, machine_mode mode
,
6876 const_tree type
, bool named
, bool incoming
,
6877 int *pregno
, int *ppadding
)
6880 = incoming
? SPARC_INCOMING_INT_ARG_FIRST
: SPARC_OUTGOING_INT_ARG_FIRST
;
6881 int slotno
= cum
->words
, regno
;
6882 enum mode_class mclass
= GET_MODE_CLASS (mode
);
6884 /* Silence warnings in the callers. */
6888 if (type
&& TREE_ADDRESSABLE (type
))
6891 /* In 64-bit mode, objects requiring 16-byte alignment get it. */
6893 && (type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
)) >= 128
6894 && (slotno
& 1) != 0)
6902 /* Vector types deserve special treatment because they are polymorphic wrt
6903 their mode, depending upon whether VIS instructions are enabled. */
6904 if (type
&& VECTOR_TYPE_P (type
))
6906 if (TREE_CODE (TREE_TYPE (type
)) == REAL_TYPE
)
6908 /* The SPARC port defines no floating-point vector modes. */
6909 gcc_assert (mode
== BLKmode
);
6913 /* Integer vector types should either have a vector
6914 mode or an integral mode, because we are guaranteed
6915 by pass_by_reference that their size is not greater
6916 than 16 bytes and TImode is 16-byte wide. */
6917 gcc_assert (mode
!= BLKmode
);
6919 /* Integer vectors are handled like floats as per
6921 mclass
= MODE_FLOAT
;
6928 case MODE_COMPLEX_FLOAT
:
6929 case MODE_VECTOR_INT
:
6930 if (TARGET_ARCH64
&& TARGET_FPU
&& named
)
6932 /* If all arg slots are filled, then must pass on stack. */
6933 if (slotno
>= SPARC_FP_ARG_MAX
)
6936 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
6937 /* Arguments filling only one single FP register are
6938 right-justified in the outer double FP register. */
6939 if (GET_MODE_SIZE (mode
) <= 4)
6946 case MODE_COMPLEX_INT
:
6947 /* If all arg slots are filled, then must pass on stack. */
6948 if (slotno
>= SPARC_INT_ARG_MAX
)
6951 regno
= regbase
+ slotno
;
6955 /* MODE is VOIDmode when generating the actual call. */
6956 if (mode
== VOIDmode
)
6959 if (TARGET_64BIT
&& TARGET_FPU
&& named
6961 && (TREE_CODE (type
) == RECORD_TYPE
|| VECTOR_TYPE_P (type
)))
6963 /* If all arg slots are filled, then must pass on stack. */
6964 if (slotno
>= SPARC_FP_ARG_MAX
)
6967 if (TREE_CODE (type
) == RECORD_TYPE
)
6969 classify_data_t data
= { false, false };
6970 traverse_record_type
<classify_data_t
, classify_registers
>
6971 (type
, named
, &data
);
6975 /* If all FP slots are filled except for the last one and
6976 there is no FP field in the first word, then must pass
6978 if (slotno
>= SPARC_FP_ARG_MAX
- 1
6979 && !data
.fp_regs_in_first_word
)
6984 /* If all int slots are filled, then must pass on stack. */
6985 if (slotno
>= SPARC_INT_ARG_MAX
)
6989 /* PREGNO isn't set since both int and FP regs can be used. */
6993 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
6997 /* If all arg slots are filled, then must pass on stack. */
6998 if (slotno
>= SPARC_INT_ARG_MAX
)
7001 regno
= regbase
+ slotno
;
7013 /* Handle recursive register counting/assigning for structure layout. */
7017 int slotno
; /* slot number of the argument. */
7018 int regbase
; /* regno of the base register. */
7019 int intoffset
; /* offset of the first pending integer field. */
7020 int nregs
; /* number of words passed in registers. */
7021 bool stack
; /* true if part of the argument is on the stack. */
7022 rtx ret
; /* return expression being built. */
7025 /* A subroutine of function_arg_record_value. Compute the number of integer
7026 registers to be assigned between PARMS->intoffset and BITPOS. Return
7027 true if at least one integer register is assigned or false otherwise. */
7030 compute_int_layout (int bitpos
, assign_data_t
*data
, int *pnregs
)
7032 if (data
->intoffset
< 0)
7035 const int intoffset
= data
->intoffset
;
7036 data
->intoffset
= -1;
7038 const int this_slotno
= data
->slotno
+ intoffset
/ BITS_PER_WORD
;
7039 const unsigned int startbit
= ROUND_DOWN (intoffset
, BITS_PER_WORD
);
7040 const unsigned int endbit
= ROUND_UP (bitpos
, BITS_PER_WORD
);
7041 int nregs
= (endbit
- startbit
) / BITS_PER_WORD
;
7043 if (nregs
> 0 && nregs
> SPARC_INT_ARG_MAX
- this_slotno
)
7045 nregs
= SPARC_INT_ARG_MAX
- this_slotno
;
7047 /* We need to pass this field (partly) on the stack. */
7058 /* A subroutine of function_arg_record_value. Compute the number and the mode
7059 of the FP registers to be assigned for FIELD. Return true if at least one
7060 FP register is assigned or false otherwise. */
7063 compute_fp_layout (const_tree field
, int bitpos
, assign_data_t
*data
,
7064 int *pnregs
, machine_mode
*pmode
)
7066 const int this_slotno
= data
->slotno
+ bitpos
/ BITS_PER_WORD
;
7067 machine_mode mode
= DECL_MODE (field
);
7070 /* Slots are counted as words while regs are counted as having the size of
7071 the (inner) mode. */
7072 if (VECTOR_TYPE_P (TREE_TYPE (field
)) && mode
== BLKmode
)
7074 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
7075 nregs
= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
7077 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
7079 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
7085 nslots
= CEIL_NWORDS (nregs
* GET_MODE_SIZE (mode
));
7087 if (nslots
> SPARC_FP_ARG_MAX
- this_slotno
)
7089 nslots
= SPARC_FP_ARG_MAX
- this_slotno
;
7090 nregs
= (nslots
* UNITS_PER_WORD
) / GET_MODE_SIZE (mode
);
7092 /* We need to pass this field (partly) on the stack. */
7104 /* A subroutine of function_arg_record_value. Count the number of registers
7105 to be assigned for FIELD and between PARMS->intoffset and BITPOS. */
7108 count_registers (const_tree field
, int bitpos
, bool fp
, assign_data_t
*data
)
7115 if (compute_int_layout (bitpos
, data
, &nregs
))
7116 data
->nregs
+= nregs
;
7118 if (compute_fp_layout (field
, bitpos
, data
, &nregs
, &mode
))
7119 data
->nregs
+= nregs
;
7123 if (data
->intoffset
< 0)
7124 data
->intoffset
= bitpos
;
7128 /* A subroutine of function_arg_record_value. Assign the bits of the
7129 structure between PARMS->intoffset and BITPOS to integer registers. */
7132 assign_int_registers (int bitpos
, assign_data_t
*data
)
7134 int intoffset
= data
->intoffset
;
7138 if (!compute_int_layout (bitpos
, data
, &nregs
))
7141 /* If this is the trailing part of a word, only load that much into
7142 the register. Otherwise load the whole register. Note that in
7143 the latter case we may pick up unwanted bits. It's not a problem
7144 at the moment but may wish to revisit. */
7145 if (intoffset
% BITS_PER_WORD
!= 0)
7146 mode
= smallest_int_mode_for_size (BITS_PER_WORD
7147 - intoffset
% BITS_PER_WORD
);
7151 const int this_slotno
= data
->slotno
+ intoffset
/ BITS_PER_WORD
;
7152 unsigned int regno
= data
->regbase
+ this_slotno
;
7153 intoffset
/= BITS_PER_UNIT
;
7157 rtx reg
= gen_rtx_REG (mode
, regno
);
7158 XVECEXP (data
->ret
, 0, data
->stack
+ data
->nregs
)
7159 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
7163 intoffset
= (intoffset
| (UNITS_PER_WORD
- 1)) + 1;
7165 while (--nregs
> 0);
7168 /* A subroutine of function_arg_record_value. Assign FIELD at position
7169 BITPOS to FP registers. */
7172 assign_fp_registers (const_tree field
, int bitpos
, assign_data_t
*data
)
7177 if (!compute_fp_layout (field
, bitpos
, data
, &nregs
, &mode
))
7180 const int this_slotno
= data
->slotno
+ bitpos
/ BITS_PER_WORD
;
7181 int regno
= SPARC_FP_ARG_FIRST
+ this_slotno
* 2;
7182 if (GET_MODE_SIZE (mode
) <= 4 && (bitpos
& 32) != 0)
7184 int pos
= bitpos
/ BITS_PER_UNIT
;
7188 rtx reg
= gen_rtx_REG (mode
, regno
);
7189 XVECEXP (data
->ret
, 0, data
->stack
+ data
->nregs
)
7190 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
7192 regno
+= GET_MODE_SIZE (mode
) / 4;
7193 pos
+= GET_MODE_SIZE (mode
);
7195 while (--nregs
> 0);
7198 /* A subroutine of function_arg_record_value. Assign FIELD and the bits of
7199 the structure between PARMS->intoffset and BITPOS to registers. */
7202 assign_registers (const_tree field
, int bitpos
, bool fp
, assign_data_t
*data
)
7206 assign_int_registers (bitpos
, data
);
7208 assign_fp_registers (field
, bitpos
, data
);
7212 if (data
->intoffset
< 0)
7213 data
->intoffset
= bitpos
;
7217 /* Used by function_arg and function_value to implement the complex
7218 conventions of the 64-bit ABI for passing and returning structures.
7219 Return an expression valid as a return value for the FUNCTION_ARG
7220 and TARGET_FUNCTION_VALUE.
7222 TYPE is the data type of the argument (as a tree).
7223 This is null for libcalls where that information may
7225 MODE is the argument's machine mode.
7226 SLOTNO is the index number of the argument's slot in the parameter array.
7227 NAMED is true if this argument is a named parameter
7228 (otherwise it is an extra parameter matching an ellipsis).
7229 REGBASE is the regno of the base register for the parameter array. */
7232 function_arg_record_value (const_tree type
, machine_mode mode
,
7233 int slotno
, bool named
, int regbase
)
7235 const int size
= int_size_in_bytes (type
);
7239 data
.slotno
= slotno
;
7240 data
.regbase
= regbase
;
7242 /* Count how many registers we need. */
7246 traverse_record_type
<assign_data_t
, count_registers
> (type
, named
, &data
);
7248 /* Take into account pending integer fields. */
7249 if (compute_int_layout (size
* BITS_PER_UNIT
, &data
, &nregs
))
7250 data
.nregs
+= nregs
;
7252 /* Allocate the vector and handle some annoying special cases. */
7257 /* ??? Empty structure has no value? Duh? */
7260 /* Though there's nothing really to store, return a word register
7261 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
7262 leads to breakage due to the fact that there are zero bytes to
7264 return gen_rtx_REG (mode
, regbase
);
7267 /* ??? C++ has structures with no fields, and yet a size. Give up
7268 for now and pass everything back in integer registers. */
7269 nregs
= CEIL_NWORDS (size
);
7270 if (nregs
+ slotno
> SPARC_INT_ARG_MAX
)
7271 nregs
= SPARC_INT_ARG_MAX
- slotno
;
7274 gcc_assert (nregs
> 0);
7276 data
.ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (data
.stack
+ nregs
));
7278 /* If at least one field must be passed on the stack, generate
7279 (parallel [(expr_list (nil) ...) ...]) so that all fields will
7280 also be passed on the stack. We can't do much better because the
7281 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
7282 of structures for which the fields passed exclusively in registers
7283 are not at the beginning of the structure. */
7285 XVECEXP (data
.ret
, 0, 0)
7286 = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
7288 /* Assign the registers. */
7291 traverse_record_type
<assign_data_t
, assign_registers
> (type
, named
, &data
);
7293 /* Assign pending integer fields. */
7294 assign_int_registers (size
* BITS_PER_UNIT
, &data
);
7296 gcc_assert (data
.nregs
== nregs
);
7301 /* Used by function_arg and function_value to implement the conventions
7302 of the 64-bit ABI for passing and returning unions.
7303 Return an expression valid as a return value for the FUNCTION_ARG
7304 and TARGET_FUNCTION_VALUE.
7306 SIZE is the size in bytes of the union.
7307 MODE is the argument's machine mode.
7308 SLOTNO is the index number of the argument's slot in the parameter array.
7309 REGNO is the hard register the union will be passed in. */
7312 function_arg_union_value (int size
, machine_mode mode
, int slotno
, int regno
)
7314 unsigned int nwords
;
7316 /* See comment in function_arg_record_value for empty structures. */
7318 return gen_rtx_REG (mode
, regno
);
7320 if (slotno
== SPARC_INT_ARG_MAX
- 1)
7323 nwords
= CEIL_NWORDS (size
);
7325 rtx regs
= gen_rtx_PARALLEL (mode
, rtvec_alloc (nwords
));
7327 /* Unions are passed left-justified. */
7328 for (unsigned int i
= 0; i
< nwords
; i
++)
7329 XVECEXP (regs
, 0, i
)
7330 = gen_rtx_EXPR_LIST (VOIDmode
,
7331 gen_rtx_REG (word_mode
, regno
+ i
),
7332 GEN_INT (UNITS_PER_WORD
* i
));
7337 /* Used by function_arg and function_value to implement the conventions
7338 of the 64-bit ABI for passing and returning BLKmode vectors.
7339 Return an expression valid as a return value for the FUNCTION_ARG
7340 and TARGET_FUNCTION_VALUE.
7342 SIZE is the size in bytes of the vector.
7343 SLOTNO is the index number of the argument's slot in the parameter array.
7344 NAMED is true if this argument is a named parameter
7345 (otherwise it is an extra parameter matching an ellipsis).
7346 REGNO is the hard register the vector will be passed in. */
7349 function_arg_vector_value (int size
, int slotno
, bool named
, int regno
)
7351 const int mult
= (named
? 2 : 1);
7352 unsigned int nwords
;
7354 if (slotno
== (named
? SPARC_FP_ARG_MAX
: SPARC_INT_ARG_MAX
) - 1)
7357 nwords
= CEIL_NWORDS (size
);
7359 rtx regs
= gen_rtx_PARALLEL (BLKmode
, rtvec_alloc (nwords
));
7361 if (size
< UNITS_PER_WORD
)
7362 XVECEXP (regs
, 0, 0)
7363 = gen_rtx_EXPR_LIST (VOIDmode
,
7364 gen_rtx_REG (SImode
, regno
),
7367 for (unsigned int i
= 0; i
< nwords
; i
++)
7368 XVECEXP (regs
, 0, i
)
7369 = gen_rtx_EXPR_LIST (VOIDmode
,
7370 gen_rtx_REG (word_mode
, regno
+ i
* mult
),
7371 GEN_INT (i
* UNITS_PER_WORD
));
7376 /* Determine where to put an argument to a function.
7377 Value is zero to push the argument on the stack,
7378 or a hard register in which to store the argument.
7380 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7381 the preceding args and about the function being called.
7382 MODE is the argument's machine mode.
7383 TYPE is the data type of the argument (as a tree).
7384 This is null for libcalls where that information may
7386 NAMED is true if this argument is a named parameter
7387 (otherwise it is an extra parameter matching an ellipsis).
7388 INCOMING_P is false for TARGET_FUNCTION_ARG, true for
7389 TARGET_FUNCTION_INCOMING_ARG. */
7392 sparc_function_arg_1 (cumulative_args_t cum_v
, machine_mode mode
,
7393 const_tree type
, bool named
, bool incoming
)
7395 const CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
7397 = incoming
? SPARC_INCOMING_INT_ARG_FIRST
: SPARC_OUTGOING_INT_ARG_FIRST
;
7398 int slotno
, regno
, padding
;
7399 enum mode_class mclass
= GET_MODE_CLASS (mode
);
7402 = function_arg_slotno (cum
, mode
, type
, named
, incoming
, ®no
, &padding
);
7406 /* Integer vectors are handled like floats as per the Sun VIS SDK. */
7407 if (type
&& VECTOR_INTEGER_TYPE_P (type
))
7408 mclass
= MODE_FLOAT
;
7411 return gen_rtx_REG (mode
, regno
);
7413 /* Structures up to 16 bytes in size are passed in arg slots on the stack
7414 and are promoted to registers if possible. */
7415 if (type
&& TREE_CODE (type
) == RECORD_TYPE
)
7417 const int size
= int_size_in_bytes (type
);
7418 gcc_assert (size
<= 16);
7420 return function_arg_record_value (type
, mode
, slotno
, named
, regbase
);
7423 /* Unions up to 16 bytes in size are passed in integer registers. */
7424 else if (type
&& TREE_CODE (type
) == UNION_TYPE
)
7426 const int size
= int_size_in_bytes (type
);
7427 gcc_assert (size
<= 16);
7429 return function_arg_union_value (size
, mode
, slotno
, regno
);
7432 /* Floating-point vectors up to 16 bytes are passed in registers. */
7433 else if (type
&& VECTOR_TYPE_P (type
) && mode
== BLKmode
)
7435 const int size
= int_size_in_bytes (type
);
7436 gcc_assert (size
<= 16);
7438 return function_arg_vector_value (size
, slotno
, named
, regno
);
7441 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
7442 but also have the slot allocated for them.
7443 If no prototype is in scope fp values in register slots get passed
7444 in two places, either fp regs and int regs or fp regs and memory. */
7445 else if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
7446 && SPARC_FP_REG_P (regno
))
7448 rtx reg
= gen_rtx_REG (mode
, regno
);
7449 if (cum
->prototype_p
|| cum
->libcall_p
)
7455 if ((regno
- SPARC_FP_ARG_FIRST
) < SPARC_INT_ARG_MAX
* 2)
7459 /* On incoming, we don't need to know that the value
7460 is passed in %f0 and %i0, and it confuses other parts
7461 causing needless spillage even on the simplest cases. */
7465 intreg
= (SPARC_OUTGOING_INT_ARG_FIRST
7466 + (regno
- SPARC_FP_ARG_FIRST
) / 2);
7468 v0
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
7469 v1
= gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (mode
, intreg
),
7471 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
7475 v0
= gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
7476 v1
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
7477 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
7482 /* All other aggregate types are passed in an integer register in a mode
7483 corresponding to the size of the type. */
7484 else if (type
&& AGGREGATE_TYPE_P (type
))
7486 const int size
= int_size_in_bytes (type
);
7487 gcc_assert (size
<= 16);
7489 mode
= int_mode_for_size (size
* BITS_PER_UNIT
, 0).else_blk ();
7492 return gen_rtx_REG (mode
, regno
);
7495 /* Handle the TARGET_FUNCTION_ARG target hook. */
7498 sparc_function_arg (cumulative_args_t cum
, machine_mode mode
,
7499 const_tree type
, bool named
)
7501 return sparc_function_arg_1 (cum
, mode
, type
, named
, false);
7504 /* Handle the TARGET_FUNCTION_INCOMING_ARG target hook. */
7507 sparc_function_incoming_arg (cumulative_args_t cum
, machine_mode mode
,
7508 const_tree type
, bool named
)
7510 return sparc_function_arg_1 (cum
, mode
, type
, named
, true);
7513 /* For sparc64, objects requiring 16 byte alignment are passed that way. */
7516 sparc_function_arg_boundary (machine_mode mode
, const_tree type
)
7518 return ((TARGET_ARCH64
7519 && (GET_MODE_ALIGNMENT (mode
) == 128
7520 || (type
&& TYPE_ALIGN (type
) == 128)))
7525 /* For an arg passed partly in registers and partly in memory,
7526 this is the number of bytes of registers used.
7527 For args passed entirely in registers or entirely in memory, zero.
7529 Any arg that starts in the first 6 regs but won't entirely fit in them
7530 needs partial registers on v8. On v9, structures with integer
7531 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
7532 values that begin in the last fp reg [where "last fp reg" varies with the
7533 mode] will be split between that reg and memory. */
7536 sparc_arg_partial_bytes (cumulative_args_t cum
, machine_mode mode
,
7537 tree type
, bool named
)
7539 int slotno
, regno
, padding
;
7541 /* We pass false for incoming here, it doesn't matter. */
7542 slotno
= function_arg_slotno (get_cumulative_args (cum
), mode
, type
, named
,
7543 false, ®no
, &padding
);
7550 /* We are guaranteed by pass_by_reference that the size of the
7551 argument is not greater than 8 bytes, so we only need to return
7552 one word if the argument is partially passed in registers. */
7553 const int size
= GET_MODE_SIZE (mode
);
7555 if (size
> UNITS_PER_WORD
&& slotno
== SPARC_INT_ARG_MAX
- 1)
7556 return UNITS_PER_WORD
;
7560 /* We are guaranteed by pass_by_reference that the size of the
7561 argument is not greater than 16 bytes, so we only need to return
7562 one word if the argument is partially passed in registers. */
7563 if (type
&& AGGREGATE_TYPE_P (type
))
7565 const int size
= int_size_in_bytes (type
);
7567 if (size
> UNITS_PER_WORD
7568 && (slotno
== SPARC_INT_ARG_MAX
- 1
7569 || slotno
== SPARC_FP_ARG_MAX
- 1))
7570 return UNITS_PER_WORD
;
7572 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
7573 || ((GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
7574 || (type
&& VECTOR_TYPE_P (type
)))
7575 && !(TARGET_FPU
&& named
)))
7577 const int size
= (type
&& VECTOR_FLOAT_TYPE_P (type
))
7578 ? int_size_in_bytes (type
)
7579 : GET_MODE_SIZE (mode
);
7581 if (size
> UNITS_PER_WORD
&& slotno
== SPARC_INT_ARG_MAX
- 1)
7582 return UNITS_PER_WORD
;
7584 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
7585 || (type
&& VECTOR_TYPE_P (type
)))
7587 const int size
= (type
&& VECTOR_FLOAT_TYPE_P (type
))
7588 ? int_size_in_bytes (type
)
7589 : GET_MODE_SIZE (mode
);
7591 if (size
> UNITS_PER_WORD
&& slotno
== SPARC_FP_ARG_MAX
- 1)
7592 return UNITS_PER_WORD
;
7599 /* Handle the TARGET_FUNCTION_ARG_ADVANCE hook.
7600 Update the data in CUM to advance over an argument
7601 of mode MODE and data type TYPE.
7602 TYPE is null for libcalls where that information may not be available. */
7605 sparc_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
7606 const_tree type
, bool named
)
7608 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
7611 /* We pass false for incoming here, it doesn't matter. */
7612 function_arg_slotno (cum
, mode
, type
, named
, false, ®no
, &padding
);
7614 /* If argument requires leading padding, add it. */
7615 cum
->words
+= padding
;
7618 cum
->words
+= CEIL_NWORDS (GET_MODE_SIZE (mode
));
7621 /* For types that can have BLKmode, get the size from the type. */
7622 if (type
&& (AGGREGATE_TYPE_P (type
) || VECTOR_FLOAT_TYPE_P (type
)))
7624 const int size
= int_size_in_bytes (type
);
7626 /* See comment in function_arg_record_value for empty structures. */
7630 cum
->words
+= CEIL_NWORDS (size
);
7633 cum
->words
+= CEIL_NWORDS (GET_MODE_SIZE (mode
));
7637 /* Implement TARGET_FUNCTION_ARG_PADDING. For the 64-bit ABI structs
7638 are always stored left shifted in their argument slot. */
7640 static pad_direction
7641 sparc_function_arg_padding (machine_mode mode
, const_tree type
)
7643 if (TARGET_ARCH64
&& type
&& AGGREGATE_TYPE_P (type
))
7646 /* Fall back to the default. */
7647 return default_function_arg_padding (mode
, type
);
7650 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
7651 Specify whether to return the return value in memory. */
7654 sparc_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
7657 /* Original SPARC 32-bit ABI says that structures and unions, and
7658 quad-precision floats are returned in memory. But note that the
7659 first part is implemented through -fpcc-struct-return being the
7660 default, so here we only implement -freg-struct-return instead.
7661 All other base types are returned in registers.
7663 Extended ABI (as implemented by the Sun compiler) says that
7664 all complex floats are returned in registers (8 FP registers
7665 at most for '_Complex long double'). Return all complex integers
7666 in registers (4 at most for '_Complex long long').
7668 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7669 integers are returned like floats of the same size, that is in
7670 registers up to 8 bytes and in memory otherwise. Return all
7671 vector floats in memory like structure and unions; note that
7672 they always have BLKmode like the latter. */
7673 return (TYPE_MODE (type
) == BLKmode
7674 || TYPE_MODE (type
) == TFmode
7675 || (TREE_CODE (type
) == VECTOR_TYPE
7676 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
7678 /* Original SPARC 64-bit ABI says that structures and unions
7679 smaller than 32 bytes are returned in registers, as well as
7680 all other base types.
7682 Extended ABI (as implemented by the Sun compiler) says that all
7683 complex floats are returned in registers (8 FP registers at most
7684 for '_Complex long double'). Return all complex integers in
7685 registers (4 at most for '_Complex TItype').
7687 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7688 integers are returned like floats of the same size, that is in
7689 registers. Return all vector floats like structure and unions;
7690 note that they always have BLKmode like the latter. */
7691 return (TYPE_MODE (type
) == BLKmode
7692 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 32);
7695 /* Handle the TARGET_STRUCT_VALUE target hook.
7696 Return where to find the structure return value address. */
7699 sparc_struct_value_rtx (tree fndecl
, int incoming
)
7708 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, frame_pointer_rtx
,
7709 STRUCT_VALUE_OFFSET
));
7711 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, stack_pointer_rtx
,
7712 STRUCT_VALUE_OFFSET
));
7714 /* Only follow the SPARC ABI for fixed-size structure returns.
7715 Variable size structure returns are handled per the normal
7716 procedures in GCC. This is enabled by -mstd-struct-return */
7718 && sparc_std_struct_return
7719 && TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))
7720 && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))) == INTEGER_CST
)
7722 /* We must check and adjust the return address, as it is optional
7723 as to whether the return object is really provided. */
7724 rtx ret_reg
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
7725 rtx scratch
= gen_reg_rtx (SImode
);
7726 rtx_code_label
*endlab
= gen_label_rtx ();
7728 /* Calculate the return object size. */
7729 tree size
= TYPE_SIZE_UNIT (TREE_TYPE (fndecl
));
7730 rtx size_rtx
= GEN_INT (TREE_INT_CST_LOW (size
) & 0xfff);
7731 /* Construct a temporary return value. */
7733 = assign_stack_local (Pmode
, TREE_INT_CST_LOW (size
), 0);
7735 /* Implement SPARC 32-bit psABI callee return struct checking:
7737 Fetch the instruction where we will return to and see if
7738 it's an unimp instruction (the most significant 10 bits
7740 emit_move_insn (scratch
, gen_rtx_MEM (SImode
,
7741 plus_constant (Pmode
,
7743 /* Assume the size is valid and pre-adjust. */
7744 emit_insn (gen_add3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
7745 emit_cmp_and_jump_insns (scratch
, size_rtx
, EQ
, const0_rtx
, SImode
,
7747 emit_insn (gen_sub3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
7748 /* Write the address of the memory pointed to by temp_val into
7749 the memory pointed to by mem. */
7750 emit_move_insn (mem
, XEXP (temp_val
, 0));
7751 emit_label (endlab
);
7758 /* Handle TARGET_FUNCTION_VALUE, and TARGET_LIBCALL_VALUE target hook.
7759 For v9, function return values are subject to the same rules as arguments,
7760 except that up to 32 bytes may be returned in registers. */
7763 sparc_function_value_1 (const_tree type
, machine_mode mode
, bool outgoing
)
7765 /* Beware that the two values are swapped here wrt function_arg. */
7767 = outgoing
? SPARC_INCOMING_INT_ARG_FIRST
: SPARC_OUTGOING_INT_ARG_FIRST
;
7768 enum mode_class mclass
= GET_MODE_CLASS (mode
);
7771 /* Integer vectors are handled like floats as per the Sun VIS SDK.
7772 Note that integer vectors larger than 16 bytes have BLKmode so
7773 they need to be handled like floating-point vectors below. */
7774 if (type
&& VECTOR_INTEGER_TYPE_P (type
) && mode
!= BLKmode
)
7775 mclass
= MODE_FLOAT
;
7777 if (TARGET_ARCH64
&& type
)
7779 /* Structures up to 32 bytes in size are returned in registers. */
7780 if (TREE_CODE (type
) == RECORD_TYPE
)
7782 const int size
= int_size_in_bytes (type
);
7783 gcc_assert (size
<= 32);
7785 return function_arg_record_value (type
, mode
, 0, true, regbase
);
7788 /* Unions up to 32 bytes in size are returned in integer registers. */
7789 else if (TREE_CODE (type
) == UNION_TYPE
)
7791 const int size
= int_size_in_bytes (type
);
7792 gcc_assert (size
<= 32);
7794 return function_arg_union_value (size
, mode
, 0, regbase
);
7797 /* Vectors up to 32 bytes are returned in FP registers. */
7798 else if (VECTOR_TYPE_P (type
) && mode
== BLKmode
)
7800 const int size
= int_size_in_bytes (type
);
7801 gcc_assert (size
<= 32);
7803 return function_arg_vector_value (size
, 0, true, SPARC_FP_ARG_FIRST
);
7806 /* Objects that require it are returned in FP registers. */
7807 else if (mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
7810 /* All other aggregate types are returned in an integer register in a
7811 mode corresponding to the size of the type. */
7812 else if (AGGREGATE_TYPE_P (type
))
7814 /* All other aggregate types are passed in an integer register
7815 in a mode corresponding to the size of the type. */
7816 const int size
= int_size_in_bytes (type
);
7817 gcc_assert (size
<= 32);
7819 mode
= int_mode_for_size (size
* BITS_PER_UNIT
, 0).else_blk ();
7821 /* ??? We probably should have made the same ABI change in
7822 3.4.0 as the one we made for unions. The latter was
7823 required by the SCD though, while the former is not
7824 specified, so we favored compatibility and efficiency.
7826 Now we're stuck for aggregates larger than 16 bytes,
7827 because OImode vanished in the meantime. Let's not
7828 try to be unduly clever, and simply follow the ABI
7829 for unions in that case. */
7830 if (mode
== BLKmode
)
7831 return function_arg_union_value (size
, mode
, 0, regbase
);
7836 /* We should only have pointer and integer types at this point. This
7837 must match sparc_promote_function_mode. */
7838 else if (mclass
== MODE_INT
&& GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
7842 /* We should only have pointer and integer types at this point, except with
7843 -freg-struct-return. This must match sparc_promote_function_mode. */
7844 else if (TARGET_ARCH32
7845 && !(type
&& AGGREGATE_TYPE_P (type
))
7846 && mclass
== MODE_INT
7847 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
7850 if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
) && TARGET_FPU
)
7851 regno
= SPARC_FP_ARG_FIRST
;
7855 return gen_rtx_REG (mode
, regno
);
7858 /* Handle TARGET_FUNCTION_VALUE.
7859 On the SPARC, the value is found in the first "output" register, but the
7860 called function leaves it in the first "input" register. */
7863 sparc_function_value (const_tree valtype
,
7864 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
7867 return sparc_function_value_1 (valtype
, TYPE_MODE (valtype
), outgoing
);
7870 /* Handle TARGET_LIBCALL_VALUE. */
7873 sparc_libcall_value (machine_mode mode
,
7874 const_rtx fun ATTRIBUTE_UNUSED
)
7876 return sparc_function_value_1 (NULL_TREE
, mode
, false);
7879 /* Handle FUNCTION_VALUE_REGNO_P.
7880 On the SPARC, the first "output" reg is used for integer values, and the
7881 first floating point register is used for floating point values. */
7884 sparc_function_value_regno_p (const unsigned int regno
)
7886 return (regno
== 8 || (TARGET_FPU
&& regno
== 32));
7889 /* Do what is necessary for `va_start'. We look at the current function
7890 to determine if stdarg or varargs is used and return the address of
7891 the first unnamed parameter. */
7894 sparc_builtin_saveregs (void)
7896 int first_reg
= crtl
->args
.info
.words
;
7900 for (regno
= first_reg
; regno
< SPARC_INT_ARG_MAX
; regno
++)
7901 emit_move_insn (gen_rtx_MEM (word_mode
,
7902 gen_rtx_PLUS (Pmode
,
7904 GEN_INT (FIRST_PARM_OFFSET (0)
7907 gen_rtx_REG (word_mode
,
7908 SPARC_INCOMING_INT_ARG_FIRST
+ regno
));
7910 address
= gen_rtx_PLUS (Pmode
,
7912 GEN_INT (FIRST_PARM_OFFSET (0)
7913 + UNITS_PER_WORD
* first_reg
));
7918 /* Implement `va_start' for stdarg. */
7921 sparc_va_start (tree valist
, rtx nextarg
)
7923 nextarg
= expand_builtin_saveregs ();
7924 std_expand_builtin_va_start (valist
, nextarg
);
7927 /* Implement `va_arg' for stdarg. */
7930 sparc_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
7933 HOST_WIDE_INT size
, rsize
, align
;
7936 tree ptrtype
= build_pointer_type (type
);
7938 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
7941 size
= rsize
= UNITS_PER_WORD
;
7947 size
= int_size_in_bytes (type
);
7948 rsize
= ROUND_UP (size
, UNITS_PER_WORD
);
7953 /* For SPARC64, objects requiring 16-byte alignment get it. */
7954 if (TYPE_ALIGN (type
) >= 2 * (unsigned) BITS_PER_WORD
)
7955 align
= 2 * UNITS_PER_WORD
;
7957 /* SPARC-V9 ABI states that structures up to 16 bytes in size
7958 are left-justified in their slots. */
7959 if (AGGREGATE_TYPE_P (type
))
7962 size
= rsize
= UNITS_PER_WORD
;
7972 incr
= fold_build_pointer_plus_hwi (incr
, align
- 1);
7973 incr
= fold_convert (sizetype
, incr
);
7974 incr
= fold_build2 (BIT_AND_EXPR
, sizetype
, incr
,
7976 incr
= fold_convert (ptr_type_node
, incr
);
7979 gimplify_expr (&incr
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
7982 if (BYTES_BIG_ENDIAN
&& size
< rsize
)
7983 addr
= fold_build_pointer_plus_hwi (incr
, rsize
- size
);
7987 addr
= fold_convert (build_pointer_type (ptrtype
), addr
);
7988 addr
= build_va_arg_indirect_ref (addr
);
7991 /* If the address isn't aligned properly for the type, we need a temporary.
7992 FIXME: This is inefficient, usually we can do this in registers. */
7993 else if (align
== 0 && TYPE_ALIGN (type
) > BITS_PER_WORD
)
7995 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
7996 tree dest_addr
= build_fold_addr_expr (tmp
);
7997 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
7998 3, dest_addr
, addr
, size_int (rsize
));
7999 TREE_ADDRESSABLE (tmp
) = 1;
8000 gimplify_and_add (copy
, pre_p
);
8005 addr
= fold_convert (ptrtype
, addr
);
8007 incr
= fold_build_pointer_plus_hwi (incr
, rsize
);
8008 gimplify_assign (valist
, incr
, post_p
);
8010 return build_va_arg_indirect_ref (addr
);
8013 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
8014 Specify whether the vector mode is supported by the hardware. */
8017 sparc_vector_mode_supported_p (machine_mode mode
)
8019 return TARGET_VIS
&& VECTOR_MODE_P (mode
) ? true : false;
8022 /* Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook. */
8025 sparc_preferred_simd_mode (scalar_mode mode
)
8043 \f/* Implement TARGET_CAN_FOLLOW_JUMP. */
8046 sparc_can_follow_jump (const rtx_insn
*follower
, const rtx_insn
*followee
)
8048 /* Do not fold unconditional jumps that have been created for crossing
8049 partition boundaries. */
8050 if (CROSSING_JUMP_P (followee
) && !CROSSING_JUMP_P (follower
))
8056 /* Return the string to output an unconditional branch to LABEL, which is
8057 the operand number of the label.
8059 DEST is the destination insn (i.e. the label), INSN is the source. */
8062 output_ubranch (rtx dest
, rtx_insn
*insn
)
8064 static char string
[64];
8065 bool v9_form
= false;
8069 /* Even if we are trying to use cbcond for this, evaluate
8070 whether we can use V9 branches as our backup plan. */
8072 if (!CROSSING_JUMP_P (insn
) && INSN_ADDRESSES_SET_P ())
8073 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
8074 - INSN_ADDRESSES (INSN_UID (insn
)));
8076 /* Leave some instructions for "slop". */
8077 if (TARGET_V9
&& delta
>= -260000 && delta
< 260000)
8082 bool emit_nop
= emit_cbcond_nop (insn
);
8086 if (delta
< -500 || delta
> 500)
8092 rval
= "ba,a,pt\t%%xcc, %l0";
8099 rval
= "cwbe\t%%g0, %%g0, %l0\n\tnop";
8101 rval
= "cwbe\t%%g0, %%g0, %l0";
8107 strcpy (string
, "ba%*,pt\t%%xcc, ");
8109 strcpy (string
, "b%*\t");
8111 p
= strchr (string
, '\0');
8122 /* Return the string to output a conditional branch to LABEL, which is
8123 the operand number of the label. OP is the conditional expression.
8124 XEXP (OP, 0) is assumed to be a condition code register (integer or
8125 floating point) and its mode specifies what kind of comparison we made.
8127 DEST is the destination insn (i.e. the label), INSN is the source.
8129 REVERSED is nonzero if we should reverse the sense of the comparison.
8131 ANNUL is nonzero if we should generate an annulling branch. */
8134 output_cbranch (rtx op
, rtx dest
, int label
, int reversed
, int annul
,
8137 static char string
[64];
8138 enum rtx_code code
= GET_CODE (op
);
8139 rtx cc_reg
= XEXP (op
, 0);
8140 machine_mode mode
= GET_MODE (cc_reg
);
8141 const char *labelno
, *branch
;
8142 int spaces
= 8, far
;
8145 /* v9 branches are limited to +-1MB. If it is too far away,
8158 fbne,a,pn %fcc2, .LC29
8166 far
= TARGET_V9
&& (get_attr_length (insn
) >= 3);
8169 /* Reversal of FP compares takes care -- an ordered compare
8170 becomes an unordered compare and vice versa. */
8171 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
8172 code
= reverse_condition_maybe_unordered (code
);
8174 code
= reverse_condition (code
);
8177 /* Start by writing the branch condition. */
8178 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
8228 /* ??? !v9: FP branches cannot be preceded by another floating point
8229 insn. Because there is currently no concept of pre-delay slots,
8230 we can fix this only by always emitting a nop before a floating
8235 strcpy (string
, "nop\n\t");
8236 strcat (string
, branch
);
8243 if (mode
== CCVmode
|| mode
== CCXVmode
)
8249 if (mode
== CCVmode
|| mode
== CCXVmode
)
8255 if (mode
== CCNZmode
|| mode
== CCXNZmode
)
8267 if (mode
== CCNZmode
|| mode
== CCXNZmode
)
8287 strcpy (string
, branch
);
8289 spaces
-= strlen (branch
);
8290 p
= strchr (string
, '\0');
8292 /* Now add the annulling, the label, and a possible noop. */
8305 if (! far
&& insn
&& INSN_ADDRESSES_SET_P ())
8307 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
8308 - INSN_ADDRESSES (INSN_UID (insn
)));
8309 /* Leave some instructions for "slop". */
8310 if (delta
< -260000 || delta
>= 260000)
8320 labelno
= "%%icc, ";
8328 labelno
= "%%xcc, ";
8334 static char v9_fcc_labelno
[] = "%%fccX, ";
8335 /* Set the char indicating the number of the fcc reg to use. */
8336 v9_fcc_labelno
[5] = REGNO (cc_reg
) - SPARC_FIRST_V9_FCC_REG
+ '0';
8337 labelno
= v9_fcc_labelno
;
8340 gcc_assert (REGNO (cc_reg
) == SPARC_FCC_REG
);
8349 if (*labelno
&& insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
8352 ((profile_probability::from_reg_br_prob_note (XINT (note
, 0))
8353 >= profile_probability::even ()) ^ far
)
8366 strcpy (p
, labelno
);
8367 p
= strchr (p
, '\0');
8370 strcpy (p
, ".+12\n\t nop\n\tb\t");
8371 /* Skip the next insn if requested or
8372 if we know that it will be a nop. */
8373 if (annul
|| ! final_sequence
)
8387 /* Emit a library call comparison between floating point X and Y.
8388 COMPARISON is the operator to compare with (EQ, NE, GT, etc).
8389 Return the new operator to be used in the comparison sequence.
8391 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
8392 values as arguments instead of the TFmode registers themselves,
8393 that's why we cannot call emit_float_lib_cmp. */
8396 sparc_emit_float_lib_cmp (rtx x
, rtx y
, enum rtx_code comparison
)
8399 rtx slot0
, slot1
, result
, tem
, tem2
, libfunc
;
8401 enum rtx_code new_comparison
;
8406 qpfunc
= (TARGET_ARCH64
? "_Qp_feq" : "_Q_feq");
8410 qpfunc
= (TARGET_ARCH64
? "_Qp_fne" : "_Q_fne");
8414 qpfunc
= (TARGET_ARCH64
? "_Qp_fgt" : "_Q_fgt");
8418 qpfunc
= (TARGET_ARCH64
? "_Qp_fge" : "_Q_fge");
8422 qpfunc
= (TARGET_ARCH64
? "_Qp_flt" : "_Q_flt");
8426 qpfunc
= (TARGET_ARCH64
? "_Qp_fle" : "_Q_fle");
8437 qpfunc
= (TARGET_ARCH64
? "_Qp_cmp" : "_Q_cmp");
8448 tree expr
= MEM_EXPR (x
);
8450 mark_addressable (expr
);
8455 slot0
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
));
8456 emit_move_insn (slot0
, x
);
8461 tree expr
= MEM_EXPR (y
);
8463 mark_addressable (expr
);
8468 slot1
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
));
8469 emit_move_insn (slot1
, y
);
8472 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
8473 emit_library_call (libfunc
, LCT_NORMAL
,
8475 XEXP (slot0
, 0), Pmode
,
8476 XEXP (slot1
, 0), Pmode
);
8481 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
8482 emit_library_call (libfunc
, LCT_NORMAL
,
8484 x
, TFmode
, y
, TFmode
);
8489 /* Immediately move the result of the libcall into a pseudo
8490 register so reload doesn't clobber the value if it needs
8491 the return register for a spill reg. */
8492 result
= gen_reg_rtx (mode
);
8493 emit_move_insn (result
, hard_libcall_value (mode
, libfunc
));
8498 return gen_rtx_NE (VOIDmode
, result
, const0_rtx
);
8501 new_comparison
= (comparison
== UNORDERED
? EQ
: NE
);
8502 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, GEN_INT(3));
8505 new_comparison
= (comparison
== UNGT
? GT
: NE
);
8506 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, const1_rtx
);
8508 return gen_rtx_NE (VOIDmode
, result
, const2_rtx
);
8510 tem
= gen_reg_rtx (mode
);
8512 emit_insn (gen_andsi3 (tem
, result
, const1_rtx
));
8514 emit_insn (gen_anddi3 (tem
, result
, const1_rtx
));
8515 return gen_rtx_NE (VOIDmode
, tem
, const0_rtx
);
8518 tem
= gen_reg_rtx (mode
);
8520 emit_insn (gen_addsi3 (tem
, result
, const1_rtx
));
8522 emit_insn (gen_adddi3 (tem
, result
, const1_rtx
));
8523 tem2
= gen_reg_rtx (mode
);
8525 emit_insn (gen_andsi3 (tem2
, tem
, const2_rtx
));
8527 emit_insn (gen_anddi3 (tem2
, tem
, const2_rtx
));
8528 new_comparison
= (comparison
== UNEQ
? EQ
: NE
);
8529 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, tem2
, const0_rtx
);
8535 /* Generate an unsigned DImode to FP conversion. This is the same code
8536 optabs would emit if we didn't have TFmode patterns. */
8539 sparc_emit_floatunsdi (rtx
*operands
, machine_mode mode
)
8541 rtx i0
, i1
, f0
, in
, out
;
8544 in
= force_reg (DImode
, operands
[1]);
8545 rtx_code_label
*neglab
= gen_label_rtx ();
8546 rtx_code_label
*donelab
= gen_label_rtx ();
8547 i0
= gen_reg_rtx (DImode
);
8548 i1
= gen_reg_rtx (DImode
);
8549 f0
= gen_reg_rtx (mode
);
8551 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
8553 emit_insn (gen_rtx_SET (out
, gen_rtx_FLOAT (mode
, in
)));
8554 emit_jump_insn (gen_jump (donelab
));
8557 emit_label (neglab
);
8559 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
8560 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
8561 emit_insn (gen_iordi3 (i0
, i0
, i1
));
8562 emit_insn (gen_rtx_SET (f0
, gen_rtx_FLOAT (mode
, i0
)));
8563 emit_insn (gen_rtx_SET (out
, gen_rtx_PLUS (mode
, f0
, f0
)));
8565 emit_label (donelab
);
8568 /* Generate an FP to unsigned DImode conversion. This is the same code
8569 optabs would emit if we didn't have TFmode patterns. */
8572 sparc_emit_fixunsdi (rtx
*operands
, machine_mode mode
)
8574 rtx i0
, i1
, f0
, in
, out
, limit
;
8577 in
= force_reg (mode
, operands
[1]);
8578 rtx_code_label
*neglab
= gen_label_rtx ();
8579 rtx_code_label
*donelab
= gen_label_rtx ();
8580 i0
= gen_reg_rtx (DImode
);
8581 i1
= gen_reg_rtx (DImode
);
8582 limit
= gen_reg_rtx (mode
);
8583 f0
= gen_reg_rtx (mode
);
8585 emit_move_insn (limit
,
8586 const_double_from_real_value (
8587 REAL_VALUE_ATOF ("9223372036854775808.0", mode
), mode
));
8588 emit_cmp_and_jump_insns (in
, limit
, GE
, NULL_RTX
, mode
, 0, neglab
);
8590 emit_insn (gen_rtx_SET (out
,
8591 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, in
))));
8592 emit_jump_insn (gen_jump (donelab
));
8595 emit_label (neglab
);
8597 emit_insn (gen_rtx_SET (f0
, gen_rtx_MINUS (mode
, in
, limit
)));
8598 emit_insn (gen_rtx_SET (i0
,
8599 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, f0
))));
8600 emit_insn (gen_movdi (i1
, const1_rtx
));
8601 emit_insn (gen_ashldi3 (i1
, i1
, GEN_INT (63)));
8602 emit_insn (gen_xordi3 (out
, i0
, i1
));
8604 emit_label (donelab
);
8607 /* Return the string to output a compare and branch instruction to DEST.
8608 DEST is the destination insn (i.e. the label), INSN is the source,
8609 and OP is the conditional expression. */
8612 output_cbcond (rtx op
, rtx dest
, rtx_insn
*insn
)
8614 machine_mode mode
= GET_MODE (XEXP (op
, 0));
8615 enum rtx_code code
= GET_CODE (op
);
8616 const char *cond_str
, *tmpl
;
8617 int far
, emit_nop
, len
;
8618 static char string
[64];
8621 /* Compare and Branch is limited to +-2KB. If it is too far away,
8633 len
= get_attr_length (insn
);
8636 emit_nop
= len
== 2;
8639 code
= reverse_condition (code
);
8641 size_char
= ((mode
== SImode
) ? 'w' : 'x');
8691 int veryfar
= 1, delta
;
8693 if (INSN_ADDRESSES_SET_P ())
8695 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
8696 - INSN_ADDRESSES (INSN_UID (insn
)));
8697 /* Leave some instructions for "slop". */
8698 if (delta
>= -260000 && delta
< 260000)
8703 tmpl
= "c%cb%s\t%%1, %%2, .+16\n\tnop\n\tb\t%%3\n\tnop";
8705 tmpl
= "c%cb%s\t%%1, %%2, .+16\n\tnop\n\tba,pt\t%%%%xcc, %%3\n\tnop";
8710 tmpl
= "c%cb%s\t%%1, %%2, %%3\n\tnop";
8712 tmpl
= "c%cb%s\t%%1, %%2, %%3";
8715 snprintf (string
, sizeof(string
), tmpl
, size_char
, cond_str
);
8720 /* Return the string to output a conditional branch to LABEL, testing
8721 register REG. LABEL is the operand number of the label; REG is the
8722 operand number of the reg. OP is the conditional expression. The mode
8723 of REG says what kind of comparison we made.
8725 DEST is the destination insn (i.e. the label), INSN is the source.
8727 REVERSED is nonzero if we should reverse the sense of the comparison.
8729 ANNUL is nonzero if we should generate an annulling branch. */
8732 output_v9branch (rtx op
, rtx dest
, int reg
, int label
, int reversed
,
8733 int annul
, rtx_insn
*insn
)
8735 static char string
[64];
8736 enum rtx_code code
= GET_CODE (op
);
8737 machine_mode mode
= GET_MODE (XEXP (op
, 0));
8742 /* branch on register are limited to +-128KB. If it is too far away,
8755 brgez,a,pn %o1, .LC29
8761 ba,pt %xcc, .LC29 */
8763 far
= get_attr_length (insn
) >= 3;
8765 /* If not floating-point or if EQ or NE, we can just reverse the code. */
8767 code
= reverse_condition (code
);
8769 /* Only 64-bit versions of these instructions exist. */
8770 gcc_assert (mode
== DImode
);
8772 /* Start by writing the branch condition. */
8777 strcpy (string
, "brnz");
8781 strcpy (string
, "brz");
8785 strcpy (string
, "brgez");
8789 strcpy (string
, "brlz");
8793 strcpy (string
, "brlez");
8797 strcpy (string
, "brgz");
8804 p
= strchr (string
, '\0');
8806 /* Now add the annulling, reg, label, and nop. */
8813 if (insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
8816 ((profile_probability::from_reg_br_prob_note (XINT (note
, 0))
8817 >= profile_probability::even ()) ^ far
)
8822 *p
= p
< string
+ 8 ? '\t' : ' ';
8830 int veryfar
= 1, delta
;
8832 if (INSN_ADDRESSES_SET_P ())
8834 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
8835 - INSN_ADDRESSES (INSN_UID (insn
)));
8836 /* Leave some instructions for "slop". */
8837 if (delta
>= -260000 && delta
< 260000)
8841 strcpy (p
, ".+12\n\t nop\n\t");
8842 /* Skip the next insn if requested or
8843 if we know that it will be a nop. */
8844 if (annul
|| ! final_sequence
)
8854 strcpy (p
, "ba,pt\t%%xcc, ");
8868 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
8869 Such instructions cannot be used in the delay slot of return insn on v9.
8870 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
8874 epilogue_renumber (register rtx
*where
, int test
)
8876 register const char *fmt
;
8878 register enum rtx_code code
;
8883 code
= GET_CODE (*where
);
8888 if (REGNO (*where
) >= 8 && REGNO (*where
) < 24) /* oX or lX */
8890 if (! test
&& REGNO (*where
) >= 24 && REGNO (*where
) < 32)
8891 *where
= gen_rtx_REG (GET_MODE (*where
), OUTGOING_REGNO (REGNO(*where
)));
8897 case CONST_WIDE_INT
:
8901 /* Do not replace the frame pointer with the stack pointer because
8902 it can cause the delayed instruction to load below the stack.
8903 This occurs when instructions like:
8905 (set (reg/i:SI 24 %i0)
8906 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
8907 (const_int -20 [0xffffffec])) 0))
8909 are in the return delayed slot. */
8911 if (GET_CODE (XEXP (*where
, 0)) == REG
8912 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
8913 && (GET_CODE (XEXP (*where
, 1)) != CONST_INT
8914 || INTVAL (XEXP (*where
, 1)) < SPARC_STACK_BIAS
))
8919 if (SPARC_STACK_BIAS
8920 && GET_CODE (XEXP (*where
, 0)) == REG
8921 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
)
8929 fmt
= GET_RTX_FORMAT (code
);
8931 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8936 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
8937 if (epilogue_renumber (&(XVECEXP (*where
, i
, j
)), test
))
8940 else if (fmt
[i
] == 'e'
8941 && epilogue_renumber (&(XEXP (*where
, i
)), test
))
8947 /* Leaf functions and non-leaf functions have different needs. */
8950 reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
8953 reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
8955 static const int *const reg_alloc_orders
[] = {
8956 reg_leaf_alloc_order
,
8957 reg_nonleaf_alloc_order
};
8960 order_regs_for_local_alloc (void)
8962 static int last_order_nonleaf
= 1;
8964 if (df_regs_ever_live_p (15) != last_order_nonleaf
)
8966 last_order_nonleaf
= !last_order_nonleaf
;
8967 memcpy ((char *) reg_alloc_order
,
8968 (const char *) reg_alloc_orders
[last_order_nonleaf
],
8969 FIRST_PSEUDO_REGISTER
* sizeof (int));
8973 /* Return 1 if REG and MEM are legitimate enough to allow the various
8974 MEM<-->REG splits to be run. */
8977 sparc_split_reg_mem_legitimate (rtx reg
, rtx mem
)
8979 /* Punt if we are here by mistake. */
8980 gcc_assert (reload_completed
);
8982 /* We must have an offsettable memory reference. */
8983 if (!offsettable_memref_p (mem
))
8986 /* If we have legitimate args for ldd/std, we do not want
8987 the split to happen. */
8988 if ((REGNO (reg
) % 2) == 0 && mem_min_alignment (mem
, 8))
8995 /* Split a REG <-- MEM move into a pair of moves in MODE. */
8998 sparc_split_reg_mem (rtx dest
, rtx src
, machine_mode mode
)
9000 rtx high_part
= gen_highpart (mode
, dest
);
9001 rtx low_part
= gen_lowpart (mode
, dest
);
9002 rtx word0
= adjust_address (src
, mode
, 0);
9003 rtx word1
= adjust_address (src
, mode
, 4);
9005 if (reg_overlap_mentioned_p (high_part
, word1
))
9007 emit_move_insn_1 (low_part
, word1
);
9008 emit_move_insn_1 (high_part
, word0
);
9012 emit_move_insn_1 (high_part
, word0
);
9013 emit_move_insn_1 (low_part
, word1
);
9017 /* Split a MEM <-- REG move into a pair of moves in MODE. */
9020 sparc_split_mem_reg (rtx dest
, rtx src
, machine_mode mode
)
9022 rtx word0
= adjust_address (dest
, mode
, 0);
9023 rtx word1
= adjust_address (dest
, mode
, 4);
9024 rtx high_part
= gen_highpart (mode
, src
);
9025 rtx low_part
= gen_lowpart (mode
, src
);
9027 emit_move_insn_1 (word0
, high_part
);
9028 emit_move_insn_1 (word1
, low_part
);
9031 /* Like sparc_split_reg_mem_legitimate but for REG <--> REG moves. */
9034 sparc_split_reg_reg_legitimate (rtx reg1
, rtx reg2
)
9036 /* Punt if we are here by mistake. */
9037 gcc_assert (reload_completed
);
9039 if (GET_CODE (reg1
) == SUBREG
)
9040 reg1
= SUBREG_REG (reg1
);
9041 if (GET_CODE (reg1
) != REG
)
9043 const int regno1
= REGNO (reg1
);
9045 if (GET_CODE (reg2
) == SUBREG
)
9046 reg2
= SUBREG_REG (reg2
);
9047 if (GET_CODE (reg2
) != REG
)
9049 const int regno2
= REGNO (reg2
);
9051 if (SPARC_INT_REG_P (regno1
) && SPARC_INT_REG_P (regno2
))
9056 if ((SPARC_INT_REG_P (regno1
) && SPARC_FP_REG_P (regno2
))
9057 || (SPARC_FP_REG_P (regno1
) && SPARC_INT_REG_P (regno2
)))
9064 /* Split a REG <--> REG move into a pair of moves in MODE. */
9067 sparc_split_reg_reg (rtx dest
, rtx src
, machine_mode mode
)
9069 rtx dest1
= gen_highpart (mode
, dest
);
9070 rtx dest2
= gen_lowpart (mode
, dest
);
9071 rtx src1
= gen_highpart (mode
, src
);
9072 rtx src2
= gen_lowpart (mode
, src
);
9074 /* Now emit using the real source and destination we found, swapping
9075 the order if we detect overlap. */
9076 if (reg_overlap_mentioned_p (dest1
, src2
))
9078 emit_move_insn_1 (dest2
, src2
);
9079 emit_move_insn_1 (dest1
, src1
);
9083 emit_move_insn_1 (dest1
, src1
);
9084 emit_move_insn_1 (dest2
, src2
);
9088 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
9089 This makes them candidates for using ldd and std insns.
9091 Note reg1 and reg2 *must* be hard registers. */
9094 registers_ok_for_ldd_peep (rtx reg1
, rtx reg2
)
9096 /* We might have been passed a SUBREG. */
9097 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
9100 if (REGNO (reg1
) % 2 != 0)
9103 /* Integer ldd is deprecated in SPARC V9 */
9104 if (TARGET_V9
&& SPARC_INT_REG_P (REGNO (reg1
)))
9107 return (REGNO (reg1
) == REGNO (reg2
) - 1);
9110 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
9113 This can only happen when addr1 and addr2, the addresses in mem1
9114 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
9115 addr1 must also be aligned on a 64-bit boundary.
9117 Also iff dependent_reg_rtx is not null it should not be used to
9118 compute the address for mem1, i.e. we cannot optimize a sequence
9130 But, note that the transformation from:
9135 is perfectly fine. Thus, the peephole2 patterns always pass us
9136 the destination register of the first load, never the second one.
9138 For stores we don't have a similar problem, so dependent_reg_rtx is
9142 mems_ok_for_ldd_peep (rtx mem1
, rtx mem2
, rtx dependent_reg_rtx
)
9146 HOST_WIDE_INT offset1
;
9148 /* The mems cannot be volatile. */
9149 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
9152 /* MEM1 should be aligned on a 64-bit boundary. */
9153 if (MEM_ALIGN (mem1
) < 64)
9156 addr1
= XEXP (mem1
, 0);
9157 addr2
= XEXP (mem2
, 0);
9159 /* Extract a register number and offset (if used) from the first addr. */
9160 if (GET_CODE (addr1
) == PLUS
)
9162 /* If not a REG, return zero. */
9163 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
9167 reg1
= REGNO (XEXP (addr1
, 0));
9168 /* The offset must be constant! */
9169 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
9171 offset1
= INTVAL (XEXP (addr1
, 1));
9174 else if (GET_CODE (addr1
) != REG
)
9178 reg1
= REGNO (addr1
);
9179 /* This was a simple (mem (reg)) expression. Offset is 0. */
9183 /* Make sure the second address is a (mem (plus (reg) (const_int). */
9184 if (GET_CODE (addr2
) != PLUS
)
9187 if (GET_CODE (XEXP (addr2
, 0)) != REG
9188 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
9191 if (reg1
!= REGNO (XEXP (addr2
, 0)))
9194 if (dependent_reg_rtx
!= NULL_RTX
&& reg1
== REGNO (dependent_reg_rtx
))
9197 /* The first offset must be evenly divisible by 8 to ensure the
9198 address is 64-bit aligned. */
9199 if (offset1
% 8 != 0)
9202 /* The offset for the second addr must be 4 more than the first addr. */
9203 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
9206 /* All the tests passed. addr1 and addr2 are valid for ldd and std
9211 /* Return the widened memory access made of MEM1 and MEM2 in MODE. */
9214 widen_mem_for_ldd_peep (rtx mem1
, rtx mem2
, machine_mode mode
)
9216 rtx x
= widen_memory_access (mem1
, mode
, 0);
9217 MEM_NOTRAP_P (x
) = MEM_NOTRAP_P (mem1
) && MEM_NOTRAP_P (mem2
);
9221 /* Return 1 if reg is a pseudo, or is the first register in
9222 a hard register pair. This makes it suitable for use in
9223 ldd and std insns. */
9226 register_ok_for_ldd (rtx reg
)
9228 /* We might have been passed a SUBREG. */
9232 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
9233 return (REGNO (reg
) % 2 == 0);
9238 /* Return 1 if OP, a MEM, has an address which is known to be
9239 aligned to an 8-byte boundary. */
9242 memory_ok_for_ldd (rtx op
)
9244 /* In 64-bit mode, we assume that the address is word-aligned. */
9245 if (TARGET_ARCH32
&& !mem_min_alignment (op
, 8))
9248 if (! can_create_pseudo_p ()
9249 && !strict_memory_address_p (Pmode
, XEXP (op
, 0)))
9255 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
9258 sparc_print_operand_punct_valid_p (unsigned char code
)
9271 /* Implement TARGET_PRINT_OPERAND.
9272 Print operand X (an rtx) in assembler syntax to file FILE.
9273 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
9274 For `%' followed by punctuation, CODE is the punctuation and X is null. */
9277 sparc_print_operand (FILE *file
, rtx x
, int code
)
9284 /* Output an insn in a delay slot. */
9286 sparc_indent_opcode
= 1;
9288 fputs ("\n\t nop", file
);
9291 /* Output an annul flag if there's nothing for the delay slot and we
9292 are optimizing. This is always used with '(' below.
9293 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
9294 this is a dbx bug. So, we only do this when optimizing.
9295 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
9296 Always emit a nop in case the next instruction is a branch. */
9297 if (! final_sequence
&& (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
9301 /* Output a 'nop' if there's nothing for the delay slot and we are
9302 not optimizing. This is always used with '*' above. */
9303 if (! final_sequence
&& ! (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
9304 fputs ("\n\t nop", file
);
9305 else if (final_sequence
)
9306 sparc_indent_opcode
= 1;
9309 /* Output the right displacement from the saved PC on function return.
9310 The caller may have placed an "unimp" insn immediately after the call
9311 so we have to account for it. This insn is used in the 32-bit ABI
9312 when calling a function that returns a non zero-sized structure. The
9313 64-bit ABI doesn't have it. Be careful to have this test be the same
9314 as that for the call. The exception is when sparc_std_struct_return
9315 is enabled, the psABI is followed exactly and the adjustment is made
9316 by the code in sparc_struct_value_rtx. The call emitted is the same
9317 when sparc_std_struct_return is enabled. */
9319 && cfun
->returns_struct
9320 && !sparc_std_struct_return
9321 && DECL_SIZE (DECL_RESULT (current_function_decl
))
9322 && TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl
)))
9324 && !integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl
))))
9330 /* Output the Embedded Medium/Anywhere code model base register. */
9331 fputs (EMBMEDANY_BASE_REG
, file
);
9334 /* Print some local dynamic TLS name. */
9335 if (const char *name
= get_some_local_dynamic_name ())
9336 assemble_name (file
, name
);
9338 output_operand_lossage ("'%%&' used without any "
9339 "local dynamic TLS references");
9343 /* Adjust the operand to take into account a RESTORE operation. */
9344 if (GET_CODE (x
) == CONST_INT
)
9346 else if (GET_CODE (x
) != REG
)
9347 output_operand_lossage ("invalid %%Y operand");
9348 else if (REGNO (x
) < 8)
9349 fputs (reg_names
[REGNO (x
)], file
);
9350 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
9351 fputs (reg_names
[REGNO (x
)-16], file
);
9353 output_operand_lossage ("invalid %%Y operand");
9356 /* Print out the low order register name of a register pair. */
9357 if (WORDS_BIG_ENDIAN
)
9358 fputs (reg_names
[REGNO (x
)+1], file
);
9360 fputs (reg_names
[REGNO (x
)], file
);
9363 /* Print out the high order register name of a register pair. */
9364 if (WORDS_BIG_ENDIAN
)
9365 fputs (reg_names
[REGNO (x
)], file
);
9367 fputs (reg_names
[REGNO (x
)+1], file
);
9370 /* Print out the second register name of a register pair or quad.
9371 I.e., R (%o0) => %o1. */
9372 fputs (reg_names
[REGNO (x
)+1], file
);
9375 /* Print out the third register name of a register quad.
9376 I.e., S (%o0) => %o2. */
9377 fputs (reg_names
[REGNO (x
)+2], file
);
9380 /* Print out the fourth register name of a register quad.
9381 I.e., T (%o0) => %o3. */
9382 fputs (reg_names
[REGNO (x
)+3], file
);
9385 /* Print a condition code register. */
9386 if (REGNO (x
) == SPARC_ICC_REG
)
9388 switch (GET_MODE (x
))
9408 /* %fccN register */
9409 fputs (reg_names
[REGNO (x
)], file
);
9412 /* Print the operand's address only. */
9413 output_address (GET_MODE (x
), XEXP (x
, 0));
9416 /* In this case we need a register. Use %g0 if the
9417 operand is const0_rtx. */
9419 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
9421 fputs ("%g0", file
);
9428 switch (GET_CODE (x
))
9440 output_operand_lossage ("invalid %%A operand");
9448 switch (GET_CODE (x
))
9460 output_operand_lossage ("invalid %%B operand");
9467 /* This is used by the conditional move instructions. */
9470 machine_mode mode
= GET_MODE (XEXP (x
, 0));
9471 switch (GET_CODE (x
))
9474 if (mode
== CCVmode
|| mode
== CCXVmode
)
9480 if (mode
== CCVmode
|| mode
== CCXVmode
)
9486 if (mode
== CCNZmode
|| mode
== CCXNZmode
)
9498 if (mode
== CCNZmode
|| mode
== CCXNZmode
)
9540 output_operand_lossage ("invalid %%C operand");
9548 /* This are used by the movr instruction pattern. */
9551 switch (GET_CODE (x
))
9572 output_operand_lossage ("invalid %%D operand");
9582 /* Print a sign-extended character. */
9583 int i
= trunc_int_for_mode (INTVAL (x
), QImode
);
9584 fprintf (file
, "%d", i
);
9589 /* Operand must be a MEM; write its address. */
9590 if (GET_CODE (x
) != MEM
)
9591 output_operand_lossage ("invalid %%f operand");
9592 output_address (GET_MODE (x
), XEXP (x
, 0));
9597 /* Print a sign-extended 32-bit value. */
9599 if (GET_CODE(x
) == CONST_INT
)
9603 output_operand_lossage ("invalid %%s operand");
9606 i
= trunc_int_for_mode (i
, SImode
);
9607 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, i
);
9612 /* Do nothing special. */
9616 /* Undocumented flag. */
9617 output_operand_lossage ("invalid operand output code");
9620 if (GET_CODE (x
) == REG
)
9621 fputs (reg_names
[REGNO (x
)], file
);
9622 else if (GET_CODE (x
) == MEM
)
9625 /* Poor Sun assembler doesn't understand absolute addressing. */
9626 if (CONSTANT_P (XEXP (x
, 0)))
9627 fputs ("%g0+", file
);
9628 output_address (GET_MODE (x
), XEXP (x
, 0));
9631 else if (GET_CODE (x
) == HIGH
)
9633 fputs ("%hi(", file
);
9634 output_addr_const (file
, XEXP (x
, 0));
9637 else if (GET_CODE (x
) == LO_SUM
)
9639 sparc_print_operand (file
, XEXP (x
, 0), 0);
9640 if (TARGET_CM_MEDMID
)
9641 fputs ("+%l44(", file
);
9643 fputs ("+%lo(", file
);
9644 output_addr_const (file
, XEXP (x
, 1));
9647 else if (GET_CODE (x
) == CONST_DOUBLE
)
9648 output_operand_lossage ("floating-point constant not a valid immediate operand");
9650 output_addr_const (file
, x
);
9653 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
9656 sparc_print_operand_address (FILE *file
, machine_mode
/*mode*/, rtx x
)
9658 register rtx base
, index
= 0;
9660 register rtx addr
= x
;
9663 fputs (reg_names
[REGNO (addr
)], file
);
9664 else if (GET_CODE (addr
) == PLUS
)
9666 if (CONST_INT_P (XEXP (addr
, 0)))
9667 offset
= INTVAL (XEXP (addr
, 0)), base
= XEXP (addr
, 1);
9668 else if (CONST_INT_P (XEXP (addr
, 1)))
9669 offset
= INTVAL (XEXP (addr
, 1)), base
= XEXP (addr
, 0);
9671 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
9672 if (GET_CODE (base
) == LO_SUM
)
9674 gcc_assert (USE_AS_OFFSETABLE_LO10
9676 && ! TARGET_CM_MEDMID
);
9677 output_operand (XEXP (base
, 0), 0);
9678 fputs ("+%lo(", file
);
9679 output_address (VOIDmode
, XEXP (base
, 1));
9680 fprintf (file
, ")+%d", offset
);
9684 fputs (reg_names
[REGNO (base
)], file
);
9686 fprintf (file
, "%+d", offset
);
9687 else if (REG_P (index
))
9688 fprintf (file
, "+%s", reg_names
[REGNO (index
)]);
9689 else if (GET_CODE (index
) == SYMBOL_REF
9690 || GET_CODE (index
) == LABEL_REF
9691 || GET_CODE (index
) == CONST
)
9692 fputc ('+', file
), output_addr_const (file
, index
);
9693 else gcc_unreachable ();
9696 else if (GET_CODE (addr
) == MINUS
9697 && GET_CODE (XEXP (addr
, 1)) == LABEL_REF
)
9699 output_addr_const (file
, XEXP (addr
, 0));
9701 output_addr_const (file
, XEXP (addr
, 1));
9702 fputs ("-.)", file
);
9704 else if (GET_CODE (addr
) == LO_SUM
)
9706 output_operand (XEXP (addr
, 0), 0);
9707 if (TARGET_CM_MEDMID
)
9708 fputs ("+%l44(", file
);
9710 fputs ("+%lo(", file
);
9711 output_address (VOIDmode
, XEXP (addr
, 1));
9715 && GET_CODE (addr
) == CONST
9716 && GET_CODE (XEXP (addr
, 0)) == MINUS
9717 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST
9718 && GET_CODE (XEXP (XEXP (XEXP (addr
, 0), 1), 0)) == MINUS
9719 && XEXP (XEXP (XEXP (XEXP (addr
, 0), 1), 0), 1) == pc_rtx
)
9721 addr
= XEXP (addr
, 0);
9722 output_addr_const (file
, XEXP (addr
, 0));
9723 /* Group the args of the second CONST in parenthesis. */
9725 /* Skip past the second CONST--it does nothing for us. */
9726 output_addr_const (file
, XEXP (XEXP (addr
, 1), 0));
9727 /* Close the parenthesis. */
9732 output_addr_const (file
, addr
);
9736 /* Target hook for assembling integer objects. The sparc version has
9737 special handling for aligned DI-mode objects. */
9740 sparc_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
9742 /* ??? We only output .xword's for symbols and only then in environments
9743 where the assembler can handle them. */
9744 if (aligned_p
&& size
== 8 && GET_CODE (x
) != CONST_INT
)
9748 assemble_integer_with_op ("\t.xword\t", x
);
9753 assemble_aligned_integer (4, const0_rtx
);
9754 assemble_aligned_integer (4, x
);
9758 return default_assemble_integer (x
, size
, aligned_p
);
9761 /* Return the value of a code used in the .proc pseudo-op that says
9762 what kind of result this function returns. For non-C types, we pick
9763 the closest C type. */
9765 #ifndef SHORT_TYPE_SIZE
9766 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
9769 #ifndef INT_TYPE_SIZE
9770 #define INT_TYPE_SIZE BITS_PER_WORD
9773 #ifndef LONG_TYPE_SIZE
9774 #define LONG_TYPE_SIZE BITS_PER_WORD
9777 #ifndef LONG_LONG_TYPE_SIZE
9778 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
9781 #ifndef FLOAT_TYPE_SIZE
9782 #define FLOAT_TYPE_SIZE BITS_PER_WORD
9785 #ifndef DOUBLE_TYPE_SIZE
9786 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
9789 #ifndef LONG_DOUBLE_TYPE_SIZE
9790 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
9794 sparc_type_code (register tree type
)
9796 register unsigned long qualifiers
= 0;
9797 register unsigned shift
;
9799 /* Only the first 30 bits of the qualifier are valid. We must refrain from
9800 setting more, since some assemblers will give an error for this. Also,
9801 we must be careful to avoid shifts of 32 bits or more to avoid getting
9802 unpredictable results. */
9804 for (shift
= 6; shift
< 30; shift
+= 2, type
= TREE_TYPE (type
))
9806 switch (TREE_CODE (type
))
9812 qualifiers
|= (3 << shift
);
9817 qualifiers
|= (2 << shift
);
9821 case REFERENCE_TYPE
:
9823 qualifiers
|= (1 << shift
);
9827 return (qualifiers
| 8);
9830 case QUAL_UNION_TYPE
:
9831 return (qualifiers
| 9);
9834 return (qualifiers
| 10);
9837 return (qualifiers
| 16);
9840 /* If this is a range type, consider it to be the underlying
9842 if (TREE_TYPE (type
) != 0)
9845 /* Carefully distinguish all the standard types of C,
9846 without messing up if the language is not C. We do this by
9847 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
9848 look at both the names and the above fields, but that's redundant.
9849 Any type whose size is between two C types will be considered
9850 to be the wider of the two types. Also, we do not have a
9851 special code to use for "long long", so anything wider than
9852 long is treated the same. Note that we can't distinguish
9853 between "int" and "long" in this code if they are the same
9854 size, but that's fine, since neither can the assembler. */
9856 if (TYPE_PRECISION (type
) <= CHAR_TYPE_SIZE
)
9857 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 12 : 2));
9859 else if (TYPE_PRECISION (type
) <= SHORT_TYPE_SIZE
)
9860 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 13 : 3));
9862 else if (TYPE_PRECISION (type
) <= INT_TYPE_SIZE
)
9863 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 14 : 4));
9866 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 15 : 5));
9869 /* If this is a range type, consider it to be the underlying
9871 if (TREE_TYPE (type
) != 0)
9874 /* Carefully distinguish all the standard types of C,
9875 without messing up if the language is not C. */
9877 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
9878 return (qualifiers
| 6);
9881 return (qualifiers
| 7);
9883 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
9884 /* ??? We need to distinguish between double and float complex types,
9885 but I don't know how yet because I can't reach this code from
9886 existing front-ends. */
9887 return (qualifiers
| 7); /* Who knows? */
9890 case BOOLEAN_TYPE
: /* Boolean truth value type. */
9896 gcc_unreachable (); /* Not a type! */
9903 /* Nested function support. */
9905 /* Emit RTL insns to initialize the variable parts of a trampoline.
9906 FNADDR is an RTX for the address of the function's pure code.
9907 CXT is an RTX for the static chain value for the function.
9909 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
9910 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
9911 (to store insns). This is a bit excessive. Perhaps a different
9912 mechanism would be better here.
9914 Emit enough FLUSH insns to synchronize the data and instruction caches. */
9917 sparc32_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
9919 /* SPARC 32-bit trampoline:
9922 sethi %hi(static), %g2
9924 or %g2, %lo(static), %g2
9926 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
9927 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
9931 (adjust_address (m_tramp
, SImode
, 0),
9932 expand_binop (SImode
, ior_optab
,
9933 expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
, 10, 0, 1),
9934 GEN_INT (trunc_int_for_mode (0x03000000, SImode
)),
9935 NULL_RTX
, 1, OPTAB_DIRECT
));
9938 (adjust_address (m_tramp
, SImode
, 4),
9939 expand_binop (SImode
, ior_optab
,
9940 expand_shift (RSHIFT_EXPR
, SImode
, cxt
, 10, 0, 1),
9941 GEN_INT (trunc_int_for_mode (0x05000000, SImode
)),
9942 NULL_RTX
, 1, OPTAB_DIRECT
));
9945 (adjust_address (m_tramp
, SImode
, 8),
9946 expand_binop (SImode
, ior_optab
,
9947 expand_and (SImode
, fnaddr
, GEN_INT (0x3ff), NULL_RTX
),
9948 GEN_INT (trunc_int_for_mode (0x81c06000, SImode
)),
9949 NULL_RTX
, 1, OPTAB_DIRECT
));
9952 (adjust_address (m_tramp
, SImode
, 12),
9953 expand_binop (SImode
, ior_optab
,
9954 expand_and (SImode
, cxt
, GEN_INT (0x3ff), NULL_RTX
),
9955 GEN_INT (trunc_int_for_mode (0x8410a000, SImode
)),
9956 NULL_RTX
, 1, OPTAB_DIRECT
));
9958 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
9959 aligned on a 16 byte boundary so one flush clears it all. */
9960 emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp
, SImode
, 0))));
9961 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
9962 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
9963 && sparc_cpu
!= PROCESSOR_NIAGARA
9964 && sparc_cpu
!= PROCESSOR_NIAGARA2
9965 && sparc_cpu
!= PROCESSOR_NIAGARA3
9966 && sparc_cpu
!= PROCESSOR_NIAGARA4
9967 && sparc_cpu
!= PROCESSOR_NIAGARA7
9968 && sparc_cpu
!= PROCESSOR_M8
)
9969 emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp
, SImode
, 8))));
9971 /* Call __enable_execute_stack after writing onto the stack to make sure
9972 the stack address is accessible. */
9973 #ifdef HAVE_ENABLE_EXECUTE_STACK
9974 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
9975 LCT_NORMAL
, VOIDmode
, XEXP (m_tramp
, 0), Pmode
);
9980 /* The 64-bit version is simpler because it makes more sense to load the
9981 values as "immediate" data out of the trampoline. It's also easier since
9982 we can read the PC without clobbering a register. */
9985 sparc64_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
9987 /* SPARC 64-bit trampoline:
9996 emit_move_insn (adjust_address (m_tramp
, SImode
, 0),
9997 GEN_INT (trunc_int_for_mode (0x83414000, SImode
)));
9998 emit_move_insn (adjust_address (m_tramp
, SImode
, 4),
9999 GEN_INT (trunc_int_for_mode (0xca586018, SImode
)));
10000 emit_move_insn (adjust_address (m_tramp
, SImode
, 8),
10001 GEN_INT (trunc_int_for_mode (0x81c14000, SImode
)));
10002 emit_move_insn (adjust_address (m_tramp
, SImode
, 12),
10003 GEN_INT (trunc_int_for_mode (0xca586010, SImode
)));
10004 emit_move_insn (adjust_address (m_tramp
, DImode
, 16), cxt
);
10005 emit_move_insn (adjust_address (m_tramp
, DImode
, 24), fnaddr
);
10006 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 0))));
10008 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
10009 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
10010 && sparc_cpu
!= PROCESSOR_NIAGARA
10011 && sparc_cpu
!= PROCESSOR_NIAGARA2
10012 && sparc_cpu
!= PROCESSOR_NIAGARA3
10013 && sparc_cpu
!= PROCESSOR_NIAGARA4
10014 && sparc_cpu
!= PROCESSOR_NIAGARA7
10015 && sparc_cpu
!= PROCESSOR_M8
)
10016 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 8))));
10018 /* Call __enable_execute_stack after writing onto the stack to make sure
10019 the stack address is accessible. */
10020 #ifdef HAVE_ENABLE_EXECUTE_STACK
10021 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
10022 LCT_NORMAL
, VOIDmode
, XEXP (m_tramp
, 0), Pmode
);
10026 /* Worker for TARGET_TRAMPOLINE_INIT. */
10029 sparc_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
10031 rtx fnaddr
= force_reg (Pmode
, XEXP (DECL_RTL (fndecl
), 0));
10032 cxt
= force_reg (Pmode
, cxt
);
10034 sparc64_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
10036 sparc32_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
10039 /* Adjust the cost of a scheduling dependency. Return the new cost of
10040 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
10043 supersparc_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep_insn
,
10046 enum attr_type insn_type
;
10048 if (recog_memoized (insn
) < 0)
10051 insn_type
= get_attr_type (insn
);
10055 /* Data dependency; DEP_INSN writes a register that INSN reads some
10058 /* if a load, then the dependence must be on the memory address;
10059 add an extra "cycle". Note that the cost could be two cycles
10060 if the reg was written late in an instruction group; we ca not tell
10062 if (insn_type
== TYPE_LOAD
|| insn_type
== TYPE_FPLOAD
)
10065 /* Get the delay only if the address of the store is the dependence. */
10066 if (insn_type
== TYPE_STORE
|| insn_type
== TYPE_FPSTORE
)
10068 rtx pat
= PATTERN(insn
);
10069 rtx dep_pat
= PATTERN (dep_insn
);
10071 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
10072 return cost
; /* This should not happen! */
10074 /* The dependency between the two instructions was on the data that
10075 is being stored. Assume that this implies that the address of the
10076 store is not dependent. */
10077 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
10080 return cost
+ 3; /* An approximation. */
10083 /* A shift instruction cannot receive its data from an instruction
10084 in the same cycle; add a one cycle penalty. */
10085 if (insn_type
== TYPE_SHIFT
)
10086 return cost
+ 3; /* Split before cascade into shift. */
10090 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
10091 INSN writes some cycles later. */
10093 /* These are only significant for the fpu unit; writing a fp reg before
10094 the fpu has finished with it stalls the processor. */
10096 /* Reusing an integer register causes no problems. */
10097 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
10105 hypersparc_adjust_cost (rtx_insn
*insn
, int dtype
, rtx_insn
*dep_insn
,
10108 enum attr_type insn_type
, dep_type
;
10109 rtx pat
= PATTERN(insn
);
10110 rtx dep_pat
= PATTERN (dep_insn
);
10112 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
10115 insn_type
= get_attr_type (insn
);
10116 dep_type
= get_attr_type (dep_insn
);
10121 /* Data dependency; DEP_INSN writes a register that INSN reads some
10128 /* Get the delay iff the address of the store is the dependence. */
10129 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
10132 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
10139 /* If a load, then the dependence must be on the memory address. If
10140 the addresses aren't equal, then it might be a false dependency */
10141 if (dep_type
== TYPE_STORE
|| dep_type
== TYPE_FPSTORE
)
10143 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
10144 || GET_CODE (SET_DEST (dep_pat
)) != MEM
10145 || GET_CODE (SET_SRC (pat
)) != MEM
10146 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat
), 0),
10147 XEXP (SET_SRC (pat
), 0)))
10155 /* Compare to branch latency is 0. There is no benefit from
10156 separating compare and branch. */
10157 if (dep_type
== TYPE_COMPARE
)
10159 /* Floating point compare to branch latency is less than
10160 compare to conditional move. */
10161 if (dep_type
== TYPE_FPCMP
)
10170 /* Anti-dependencies only penalize the fpu unit. */
10171 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
10183 sparc_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep
, int cost
,
10188 case PROCESSOR_SUPERSPARC
:
10189 cost
= supersparc_adjust_cost (insn
, dep_type
, dep
, cost
);
10191 case PROCESSOR_HYPERSPARC
:
10192 case PROCESSOR_SPARCLITE86X
:
10193 cost
= hypersparc_adjust_cost (insn
, dep_type
, dep
, cost
);
10202 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
10203 int sched_verbose ATTRIBUTE_UNUSED
,
10204 int max_ready ATTRIBUTE_UNUSED
)
10208 sparc_use_sched_lookahead (void)
10212 case PROCESSOR_ULTRASPARC
:
10213 case PROCESSOR_ULTRASPARC3
:
10215 case PROCESSOR_SUPERSPARC
:
10216 case PROCESSOR_HYPERSPARC
:
10217 case PROCESSOR_SPARCLITE86X
:
10219 case PROCESSOR_NIAGARA4
:
10220 case PROCESSOR_NIAGARA7
:
10223 case PROCESSOR_NIAGARA
:
10224 case PROCESSOR_NIAGARA2
:
10225 case PROCESSOR_NIAGARA3
:
10232 sparc_issue_rate (void)
10236 case PROCESSOR_ULTRASPARC
:
10237 case PROCESSOR_ULTRASPARC3
:
10240 case PROCESSOR_SUPERSPARC
:
10242 case PROCESSOR_HYPERSPARC
:
10243 case PROCESSOR_SPARCLITE86X
:
10245 /* Assume V9 processors are capable of at least dual-issue. */
10246 case PROCESSOR_NIAGARA4
:
10247 case PROCESSOR_NIAGARA7
:
10249 case PROCESSOR_NIAGARA
:
10250 case PROCESSOR_NIAGARA2
:
10251 case PROCESSOR_NIAGARA3
:
10258 sparc_branch_cost (bool speed_p
, bool predictable_p
)
10263 /* For pre-V9 processors we use a single value (usually 3) to take into
10264 account the potential annulling of the delay slot (which ends up being
10265 a bubble in the pipeline slot) plus a cycle to take into consideration
10266 the instruction cache effects.
10268 On V9 and later processors, which have branch prediction facilities,
10269 we take into account whether the branch is (easily) predictable. */
10270 const int cost
= sparc_costs
->branch_cost
;
10275 case PROCESSOR_ULTRASPARC
:
10276 case PROCESSOR_ULTRASPARC3
:
10277 case PROCESSOR_NIAGARA
:
10278 case PROCESSOR_NIAGARA2
:
10279 case PROCESSOR_NIAGARA3
:
10280 case PROCESSOR_NIAGARA4
:
10281 case PROCESSOR_NIAGARA7
:
10283 return cost
+ (predictable_p
? 0 : 2);
10291 set_extends (rtx_insn
*insn
)
10293 register rtx pat
= PATTERN (insn
);
10295 switch (GET_CODE (SET_SRC (pat
)))
10297 /* Load and some shift instructions zero extend. */
10300 /* sethi clears the high bits */
10302 /* LO_SUM is used with sethi. sethi cleared the high
10303 bits and the values used with lo_sum are positive */
10305 /* Store flag stores 0 or 1 */
10315 rtx op0
= XEXP (SET_SRC (pat
), 0);
10316 rtx op1
= XEXP (SET_SRC (pat
), 1);
10317 if (GET_CODE (op1
) == CONST_INT
)
10318 return INTVAL (op1
) >= 0;
10319 if (GET_CODE (op0
) != REG
)
10321 if (sparc_check_64 (op0
, insn
) == 1)
10323 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
10328 rtx op0
= XEXP (SET_SRC (pat
), 0);
10329 rtx op1
= XEXP (SET_SRC (pat
), 1);
10330 if (GET_CODE (op0
) != REG
|| sparc_check_64 (op0
, insn
) <= 0)
10332 if (GET_CODE (op1
) == CONST_INT
)
10333 return INTVAL (op1
) >= 0;
10334 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
10337 return GET_MODE (SET_SRC (pat
)) == SImode
;
10338 /* Positive integers leave the high bits zero. */
10340 return !(INTVAL (SET_SRC (pat
)) & 0x80000000);
10343 return - (GET_MODE (SET_SRC (pat
)) == SImode
);
10345 return sparc_check_64 (SET_SRC (pat
), insn
);
10351 /* We _ought_ to have only one kind per function, but... */
10352 static GTY(()) rtx sparc_addr_diff_list
;
10353 static GTY(()) rtx sparc_addr_list
;
10356 sparc_defer_case_vector (rtx lab
, rtx vec
, int diff
)
10358 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
10360 sparc_addr_diff_list
10361 = gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_diff_list
);
10363 sparc_addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_list
);
10367 sparc_output_addr_vec (rtx vec
)
10369 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
10370 int idx
, vlen
= XVECLEN (body
, 0);
10372 #ifdef ASM_OUTPUT_ADDR_VEC_START
10373 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
10376 #ifdef ASM_OUTPUT_CASE_LABEL
10377 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
10380 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
10383 for (idx
= 0; idx
< vlen
; idx
++)
10385 ASM_OUTPUT_ADDR_VEC_ELT
10386 (asm_out_file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
10389 #ifdef ASM_OUTPUT_ADDR_VEC_END
10390 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
10395 sparc_output_addr_diff_vec (rtx vec
)
10397 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
10398 rtx base
= XEXP (XEXP (body
, 0), 0);
10399 int idx
, vlen
= XVECLEN (body
, 1);
10401 #ifdef ASM_OUTPUT_ADDR_VEC_START
10402 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
10405 #ifdef ASM_OUTPUT_CASE_LABEL
10406 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
10409 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
10412 for (idx
= 0; idx
< vlen
; idx
++)
10414 ASM_OUTPUT_ADDR_DIFF_ELT
10417 CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 1, idx
), 0)),
10418 CODE_LABEL_NUMBER (base
));
10421 #ifdef ASM_OUTPUT_ADDR_VEC_END
10422 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
10427 sparc_output_deferred_case_vectors (void)
10432 if (sparc_addr_list
== NULL_RTX
10433 && sparc_addr_diff_list
== NULL_RTX
)
10436 /* Align to cache line in the function's code section. */
10437 switch_to_section (current_function_section ());
10439 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
10441 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
10443 for (t
= sparc_addr_list
; t
; t
= XEXP (t
, 1))
10444 sparc_output_addr_vec (XEXP (t
, 0));
10445 for (t
= sparc_addr_diff_list
; t
; t
= XEXP (t
, 1))
10446 sparc_output_addr_diff_vec (XEXP (t
, 0));
10448 sparc_addr_list
= sparc_addr_diff_list
= NULL_RTX
;
10451 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
10452 unknown. Return 1 if the high bits are zero, -1 if the register is
10455 sparc_check_64 (rtx x
, rtx_insn
*insn
)
10457 /* If a register is set only once it is safe to ignore insns this
10458 code does not know how to handle. The loop will either recognize
10459 the single set and return the correct value or fail to recognize
10460 it and return 0. */
10464 gcc_assert (GET_CODE (x
) == REG
);
10466 if (GET_MODE (x
) == DImode
)
10467 y
= gen_rtx_REG (SImode
, REGNO (x
) + WORDS_BIG_ENDIAN
);
10469 if (flag_expensive_optimizations
10470 && df
&& DF_REG_DEF_COUNT (REGNO (y
)) == 1)
10476 insn
= get_last_insn_anywhere ();
10481 while ((insn
= PREV_INSN (insn
)))
10483 switch (GET_CODE (insn
))
10496 rtx pat
= PATTERN (insn
);
10497 if (GET_CODE (pat
) != SET
)
10499 if (rtx_equal_p (x
, SET_DEST (pat
)))
10500 return set_extends (insn
);
10501 if (y
&& rtx_equal_p (y
, SET_DEST (pat
)))
10502 return set_extends (insn
);
10503 if (reg_overlap_mentioned_p (SET_DEST (pat
), y
))
10511 /* Output a wide shift instruction in V8+ mode. INSN is the instruction,
10512 OPERANDS are its operands and OPCODE is the mnemonic to be used. */
10515 output_v8plus_shift (rtx_insn
*insn
, rtx
*operands
, const char *opcode
)
10517 static char asm_code
[60];
10519 /* The scratch register is only required when the destination
10520 register is not a 64-bit global or out register. */
10521 if (which_alternative
!= 2)
10522 operands
[3] = operands
[0];
10524 /* We can only shift by constants <= 63. */
10525 if (GET_CODE (operands
[2]) == CONST_INT
)
10526 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0x3f);
10528 if (GET_CODE (operands
[1]) == CONST_INT
)
10530 output_asm_insn ("mov\t%1, %3", operands
);
10534 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
10535 if (sparc_check_64 (operands
[1], insn
) <= 0)
10536 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
10537 output_asm_insn ("or\t%L1, %3, %3", operands
);
10540 strcpy (asm_code
, opcode
);
10542 if (which_alternative
!= 2)
10543 return strcat (asm_code
, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
10546 strcat (asm_code
, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
10549 /* Output rtl to increment the profiler label LABELNO
10550 for profiling a function entry. */
10553 sparc_profile_hook (int labelno
)
10558 fun
= gen_rtx_SYMBOL_REF (Pmode
, MCOUNT_FUNCTION
);
10559 if (NO_PROFILE_COUNTERS
)
10561 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
);
10565 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
10566 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
10567 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, lab
, Pmode
);
10571 #ifdef TARGET_SOLARIS
10572 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
10575 sparc_solaris_elf_asm_named_section (const char *name
, unsigned int flags
,
10576 tree decl ATTRIBUTE_UNUSED
)
10578 if (HAVE_COMDAT_GROUP
&& flags
& SECTION_LINKONCE
)
10580 solaris_elf_asm_comdat_section (name
, flags
, decl
);
10584 fprintf (asm_out_file
, "\t.section\t\"%s\"", name
);
10586 if (!(flags
& SECTION_DEBUG
))
10587 fputs (",#alloc", asm_out_file
);
10588 #if HAVE_GAS_SECTION_EXCLUDE
10589 if (flags
& SECTION_EXCLUDE
)
10590 fputs (",#exclude", asm_out_file
);
10592 if (flags
& SECTION_WRITE
)
10593 fputs (",#write", asm_out_file
);
10594 if (flags
& SECTION_TLS
)
10595 fputs (",#tls", asm_out_file
);
10596 if (flags
& SECTION_CODE
)
10597 fputs (",#execinstr", asm_out_file
);
10599 if (flags
& SECTION_NOTYPE
)
10601 else if (flags
& SECTION_BSS
)
10602 fputs (",#nobits", asm_out_file
);
10604 fputs (",#progbits", asm_out_file
);
10606 fputc ('\n', asm_out_file
);
10608 #endif /* TARGET_SOLARIS */
10610 /* We do not allow indirect calls to be optimized into sibling calls.
10612 We cannot use sibling calls when delayed branches are disabled
10613 because they will likely require the call delay slot to be filled.
10615 Also, on SPARC 32-bit we cannot emit a sibling call when the
10616 current function returns a structure. This is because the "unimp
10617 after call" convention would cause the callee to return to the
10618 wrong place. The generic code already disallows cases where the
10619 function being called returns a structure.
10621 It may seem strange how this last case could occur. Usually there
10622 is code after the call which jumps to epilogue code which dumps the
10623 return value into the struct return area. That ought to invalidate
10624 the sibling call right? Well, in the C++ case we can end up passing
10625 the pointer to the struct return area to a constructor (which returns
10626 void) and then nothing else happens. Such a sibling call would look
10627 valid without the added check here.
10629 VxWorks PIC PLT entries require the global pointer to be initialized
10630 on entry. We therefore can't emit sibling calls to them. */
10632 sparc_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
10635 && flag_delayed_branch
10636 && (TARGET_ARCH64
|| ! cfun
->returns_struct
)
10637 && !(TARGET_VXWORKS_RTP
10639 && !targetm
.binds_local_p (decl
)));
10642 /* libfunc renaming. */
10645 sparc_init_libfuncs (void)
10649 /* Use the subroutines that Sun's library provides for integer
10650 multiply and divide. The `*' prevents an underscore from
10651 being prepended by the compiler. .umul is a little faster
10653 set_optab_libfunc (smul_optab
, SImode
, "*.umul");
10654 set_optab_libfunc (sdiv_optab
, SImode
, "*.div");
10655 set_optab_libfunc (udiv_optab
, SImode
, "*.udiv");
10656 set_optab_libfunc (smod_optab
, SImode
, "*.rem");
10657 set_optab_libfunc (umod_optab
, SImode
, "*.urem");
10659 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
10660 set_optab_libfunc (add_optab
, TFmode
, "_Q_add");
10661 set_optab_libfunc (sub_optab
, TFmode
, "_Q_sub");
10662 set_optab_libfunc (neg_optab
, TFmode
, "_Q_neg");
10663 set_optab_libfunc (smul_optab
, TFmode
, "_Q_mul");
10664 set_optab_libfunc (sdiv_optab
, TFmode
, "_Q_div");
10666 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
10667 is because with soft-float, the SFmode and DFmode sqrt
10668 instructions will be absent, and the compiler will notice and
10669 try to use the TFmode sqrt instruction for calls to the
10670 builtin function sqrt, but this fails. */
10672 set_optab_libfunc (sqrt_optab
, TFmode
, "_Q_sqrt");
10674 set_optab_libfunc (eq_optab
, TFmode
, "_Q_feq");
10675 set_optab_libfunc (ne_optab
, TFmode
, "_Q_fne");
10676 set_optab_libfunc (gt_optab
, TFmode
, "_Q_fgt");
10677 set_optab_libfunc (ge_optab
, TFmode
, "_Q_fge");
10678 set_optab_libfunc (lt_optab
, TFmode
, "_Q_flt");
10679 set_optab_libfunc (le_optab
, TFmode
, "_Q_fle");
10681 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_Q_stoq");
10682 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_Q_dtoq");
10683 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_Q_qtos");
10684 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_Q_qtod");
10686 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_Q_qtoi");
10687 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_Q_qtou");
10688 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_Q_itoq");
10689 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_Q_utoq");
10691 if (DITF_CONVERSION_LIBFUNCS
)
10693 set_conv_libfunc (sfix_optab
, DImode
, TFmode
, "_Q_qtoll");
10694 set_conv_libfunc (ufix_optab
, DImode
, TFmode
, "_Q_qtoull");
10695 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
, "_Q_lltoq");
10696 set_conv_libfunc (ufloat_optab
, TFmode
, DImode
, "_Q_ulltoq");
10699 if (SUN_CONVERSION_LIBFUNCS
)
10701 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
10702 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
10703 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
10704 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
10709 /* In the SPARC 64bit ABI, SImode multiply and divide functions
10710 do not exist in the library. Make sure the compiler does not
10711 emit calls to them by accident. (It should always use the
10712 hardware instructions.) */
10713 set_optab_libfunc (smul_optab
, SImode
, 0);
10714 set_optab_libfunc (sdiv_optab
, SImode
, 0);
10715 set_optab_libfunc (udiv_optab
, SImode
, 0);
10716 set_optab_libfunc (smod_optab
, SImode
, 0);
10717 set_optab_libfunc (umod_optab
, SImode
, 0);
10719 if (SUN_INTEGER_MULTIPLY_64
)
10721 set_optab_libfunc (smul_optab
, DImode
, "__mul64");
10722 set_optab_libfunc (sdiv_optab
, DImode
, "__div64");
10723 set_optab_libfunc (udiv_optab
, DImode
, "__udiv64");
10724 set_optab_libfunc (smod_optab
, DImode
, "__rem64");
10725 set_optab_libfunc (umod_optab
, DImode
, "__urem64");
10728 if (SUN_CONVERSION_LIBFUNCS
)
10730 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftol");
10731 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoul");
10732 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtol");
10733 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoul");
10738 /* SPARC builtins. */
10739 enum sparc_builtins
10741 /* FPU builtins. */
10742 SPARC_BUILTIN_LDFSR
,
10743 SPARC_BUILTIN_STFSR
,
10745 /* VIS 1.0 builtins. */
10746 SPARC_BUILTIN_FPACK16
,
10747 SPARC_BUILTIN_FPACK32
,
10748 SPARC_BUILTIN_FPACKFIX
,
10749 SPARC_BUILTIN_FEXPAND
,
10750 SPARC_BUILTIN_FPMERGE
,
10751 SPARC_BUILTIN_FMUL8X16
,
10752 SPARC_BUILTIN_FMUL8X16AU
,
10753 SPARC_BUILTIN_FMUL8X16AL
,
10754 SPARC_BUILTIN_FMUL8SUX16
,
10755 SPARC_BUILTIN_FMUL8ULX16
,
10756 SPARC_BUILTIN_FMULD8SUX16
,
10757 SPARC_BUILTIN_FMULD8ULX16
,
10758 SPARC_BUILTIN_FALIGNDATAV4HI
,
10759 SPARC_BUILTIN_FALIGNDATAV8QI
,
10760 SPARC_BUILTIN_FALIGNDATAV2SI
,
10761 SPARC_BUILTIN_FALIGNDATADI
,
10762 SPARC_BUILTIN_WRGSR
,
10763 SPARC_BUILTIN_RDGSR
,
10764 SPARC_BUILTIN_ALIGNADDR
,
10765 SPARC_BUILTIN_ALIGNADDRL
,
10766 SPARC_BUILTIN_PDIST
,
10767 SPARC_BUILTIN_EDGE8
,
10768 SPARC_BUILTIN_EDGE8L
,
10769 SPARC_BUILTIN_EDGE16
,
10770 SPARC_BUILTIN_EDGE16L
,
10771 SPARC_BUILTIN_EDGE32
,
10772 SPARC_BUILTIN_EDGE32L
,
10773 SPARC_BUILTIN_FCMPLE16
,
10774 SPARC_BUILTIN_FCMPLE32
,
10775 SPARC_BUILTIN_FCMPNE16
,
10776 SPARC_BUILTIN_FCMPNE32
,
10777 SPARC_BUILTIN_FCMPGT16
,
10778 SPARC_BUILTIN_FCMPGT32
,
10779 SPARC_BUILTIN_FCMPEQ16
,
10780 SPARC_BUILTIN_FCMPEQ32
,
10781 SPARC_BUILTIN_FPADD16
,
10782 SPARC_BUILTIN_FPADD16S
,
10783 SPARC_BUILTIN_FPADD32
,
10784 SPARC_BUILTIN_FPADD32S
,
10785 SPARC_BUILTIN_FPSUB16
,
10786 SPARC_BUILTIN_FPSUB16S
,
10787 SPARC_BUILTIN_FPSUB32
,
10788 SPARC_BUILTIN_FPSUB32S
,
10789 SPARC_BUILTIN_ARRAY8
,
10790 SPARC_BUILTIN_ARRAY16
,
10791 SPARC_BUILTIN_ARRAY32
,
10793 /* VIS 2.0 builtins. */
10794 SPARC_BUILTIN_EDGE8N
,
10795 SPARC_BUILTIN_EDGE8LN
,
10796 SPARC_BUILTIN_EDGE16N
,
10797 SPARC_BUILTIN_EDGE16LN
,
10798 SPARC_BUILTIN_EDGE32N
,
10799 SPARC_BUILTIN_EDGE32LN
,
10800 SPARC_BUILTIN_BMASK
,
10801 SPARC_BUILTIN_BSHUFFLEV4HI
,
10802 SPARC_BUILTIN_BSHUFFLEV8QI
,
10803 SPARC_BUILTIN_BSHUFFLEV2SI
,
10804 SPARC_BUILTIN_BSHUFFLEDI
,
10806 /* VIS 3.0 builtins. */
10807 SPARC_BUILTIN_CMASK8
,
10808 SPARC_BUILTIN_CMASK16
,
10809 SPARC_BUILTIN_CMASK32
,
10810 SPARC_BUILTIN_FCHKSM16
,
10811 SPARC_BUILTIN_FSLL16
,
10812 SPARC_BUILTIN_FSLAS16
,
10813 SPARC_BUILTIN_FSRL16
,
10814 SPARC_BUILTIN_FSRA16
,
10815 SPARC_BUILTIN_FSLL32
,
10816 SPARC_BUILTIN_FSLAS32
,
10817 SPARC_BUILTIN_FSRL32
,
10818 SPARC_BUILTIN_FSRA32
,
10819 SPARC_BUILTIN_PDISTN
,
10820 SPARC_BUILTIN_FMEAN16
,
10821 SPARC_BUILTIN_FPADD64
,
10822 SPARC_BUILTIN_FPSUB64
,
10823 SPARC_BUILTIN_FPADDS16
,
10824 SPARC_BUILTIN_FPADDS16S
,
10825 SPARC_BUILTIN_FPSUBS16
,
10826 SPARC_BUILTIN_FPSUBS16S
,
10827 SPARC_BUILTIN_FPADDS32
,
10828 SPARC_BUILTIN_FPADDS32S
,
10829 SPARC_BUILTIN_FPSUBS32
,
10830 SPARC_BUILTIN_FPSUBS32S
,
10831 SPARC_BUILTIN_FUCMPLE8
,
10832 SPARC_BUILTIN_FUCMPNE8
,
10833 SPARC_BUILTIN_FUCMPGT8
,
10834 SPARC_BUILTIN_FUCMPEQ8
,
10835 SPARC_BUILTIN_FHADDS
,
10836 SPARC_BUILTIN_FHADDD
,
10837 SPARC_BUILTIN_FHSUBS
,
10838 SPARC_BUILTIN_FHSUBD
,
10839 SPARC_BUILTIN_FNHADDS
,
10840 SPARC_BUILTIN_FNHADDD
,
10841 SPARC_BUILTIN_UMULXHI
,
10842 SPARC_BUILTIN_XMULX
,
10843 SPARC_BUILTIN_XMULXHI
,
10845 /* VIS 4.0 builtins. */
10846 SPARC_BUILTIN_FPADD8
,
10847 SPARC_BUILTIN_FPADDS8
,
10848 SPARC_BUILTIN_FPADDUS8
,
10849 SPARC_BUILTIN_FPADDUS16
,
10850 SPARC_BUILTIN_FPCMPLE8
,
10851 SPARC_BUILTIN_FPCMPGT8
,
10852 SPARC_BUILTIN_FPCMPULE16
,
10853 SPARC_BUILTIN_FPCMPUGT16
,
10854 SPARC_BUILTIN_FPCMPULE32
,
10855 SPARC_BUILTIN_FPCMPUGT32
,
10856 SPARC_BUILTIN_FPMAX8
,
10857 SPARC_BUILTIN_FPMAX16
,
10858 SPARC_BUILTIN_FPMAX32
,
10859 SPARC_BUILTIN_FPMAXU8
,
10860 SPARC_BUILTIN_FPMAXU16
,
10861 SPARC_BUILTIN_FPMAXU32
,
10862 SPARC_BUILTIN_FPMIN8
,
10863 SPARC_BUILTIN_FPMIN16
,
10864 SPARC_BUILTIN_FPMIN32
,
10865 SPARC_BUILTIN_FPMINU8
,
10866 SPARC_BUILTIN_FPMINU16
,
10867 SPARC_BUILTIN_FPMINU32
,
10868 SPARC_BUILTIN_FPSUB8
,
10869 SPARC_BUILTIN_FPSUBS8
,
10870 SPARC_BUILTIN_FPSUBUS8
,
10871 SPARC_BUILTIN_FPSUBUS16
,
10873 /* VIS 4.0B builtins. */
10875 /* Note that all the DICTUNPACK* entries should be kept
10877 SPARC_BUILTIN_FIRST_DICTUNPACK
,
10878 SPARC_BUILTIN_DICTUNPACK8
= SPARC_BUILTIN_FIRST_DICTUNPACK
,
10879 SPARC_BUILTIN_DICTUNPACK16
,
10880 SPARC_BUILTIN_DICTUNPACK32
,
10881 SPARC_BUILTIN_LAST_DICTUNPACK
= SPARC_BUILTIN_DICTUNPACK32
,
10883 /* Note that all the FPCMP*SHL entries should be kept
10885 SPARC_BUILTIN_FIRST_FPCMPSHL
,
10886 SPARC_BUILTIN_FPCMPLE8SHL
= SPARC_BUILTIN_FIRST_FPCMPSHL
,
10887 SPARC_BUILTIN_FPCMPGT8SHL
,
10888 SPARC_BUILTIN_FPCMPEQ8SHL
,
10889 SPARC_BUILTIN_FPCMPNE8SHL
,
10890 SPARC_BUILTIN_FPCMPLE16SHL
,
10891 SPARC_BUILTIN_FPCMPGT16SHL
,
10892 SPARC_BUILTIN_FPCMPEQ16SHL
,
10893 SPARC_BUILTIN_FPCMPNE16SHL
,
10894 SPARC_BUILTIN_FPCMPLE32SHL
,
10895 SPARC_BUILTIN_FPCMPGT32SHL
,
10896 SPARC_BUILTIN_FPCMPEQ32SHL
,
10897 SPARC_BUILTIN_FPCMPNE32SHL
,
10898 SPARC_BUILTIN_FPCMPULE8SHL
,
10899 SPARC_BUILTIN_FPCMPUGT8SHL
,
10900 SPARC_BUILTIN_FPCMPULE16SHL
,
10901 SPARC_BUILTIN_FPCMPUGT16SHL
,
10902 SPARC_BUILTIN_FPCMPULE32SHL
,
10903 SPARC_BUILTIN_FPCMPUGT32SHL
,
10904 SPARC_BUILTIN_FPCMPDE8SHL
,
10905 SPARC_BUILTIN_FPCMPDE16SHL
,
10906 SPARC_BUILTIN_FPCMPDE32SHL
,
10907 SPARC_BUILTIN_FPCMPUR8SHL
,
10908 SPARC_BUILTIN_FPCMPUR16SHL
,
10909 SPARC_BUILTIN_FPCMPUR32SHL
,
10910 SPARC_BUILTIN_LAST_FPCMPSHL
= SPARC_BUILTIN_FPCMPUR32SHL
,
10915 static GTY (()) tree sparc_builtins
[(int) SPARC_BUILTIN_MAX
];
10916 static enum insn_code sparc_builtins_icode
[(int) SPARC_BUILTIN_MAX
];
10918 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
10919 The instruction should require a constant operand of some sort. The
10920 function prints an error if OPVAL is not valid. */
10923 check_constant_argument (enum insn_code icode
, int opnum
, rtx opval
)
10925 if (GET_CODE (opval
) != CONST_INT
)
10927 error ("%qs expects a constant argument", insn_data
[icode
].name
);
10931 if (!(*insn_data
[icode
].operand
[opnum
].predicate
) (opval
, VOIDmode
))
10933 error ("constant argument out of range for %qs", insn_data
[icode
].name
);
10939 /* Add a SPARC builtin function with NAME, ICODE, CODE and TYPE. Return the
10940 function decl or NULL_TREE if the builtin was not added. */
10943 def_builtin (const char *name
, enum insn_code icode
, enum sparc_builtins code
,
10947 = add_builtin_function (name
, type
, code
, BUILT_IN_MD
, NULL
, NULL_TREE
);
10951 sparc_builtins
[code
] = t
;
10952 sparc_builtins_icode
[code
] = icode
;
10958 /* Likewise, but also marks the function as "const". */
10961 def_builtin_const (const char *name
, enum insn_code icode
,
10962 enum sparc_builtins code
, tree type
)
10964 tree t
= def_builtin (name
, icode
, code
, type
);
10967 TREE_READONLY (t
) = 1;
10972 /* Implement the TARGET_INIT_BUILTINS target hook.
10973 Create builtin functions for special SPARC instructions. */
10976 sparc_init_builtins (void)
10979 sparc_fpu_init_builtins ();
10982 sparc_vis_init_builtins ();
10985 /* Create builtin functions for FPU instructions. */
10988 sparc_fpu_init_builtins (void)
10991 = build_function_type_list (void_type_node
,
10992 build_pointer_type (unsigned_type_node
), 0);
10993 def_builtin ("__builtin_load_fsr", CODE_FOR_ldfsr
,
10994 SPARC_BUILTIN_LDFSR
, ftype
);
10995 def_builtin ("__builtin_store_fsr", CODE_FOR_stfsr
,
10996 SPARC_BUILTIN_STFSR
, ftype
);
10999 /* Create builtin functions for VIS instructions. */
11002 sparc_vis_init_builtins (void)
11004 tree v4qi
= build_vector_type (unsigned_intQI_type_node
, 4);
11005 tree v8qi
= build_vector_type (unsigned_intQI_type_node
, 8);
11006 tree v4hi
= build_vector_type (intHI_type_node
, 4);
11007 tree v2hi
= build_vector_type (intHI_type_node
, 2);
11008 tree v2si
= build_vector_type (intSI_type_node
, 2);
11009 tree v1si
= build_vector_type (intSI_type_node
, 1);
11011 tree v4qi_ftype_v4hi
= build_function_type_list (v4qi
, v4hi
, 0);
11012 tree v8qi_ftype_v2si_v8qi
= build_function_type_list (v8qi
, v2si
, v8qi
, 0);
11013 tree v2hi_ftype_v2si
= build_function_type_list (v2hi
, v2si
, 0);
11014 tree v4hi_ftype_v4qi
= build_function_type_list (v4hi
, v4qi
, 0);
11015 tree v8qi_ftype_v4qi_v4qi
= build_function_type_list (v8qi
, v4qi
, v4qi
, 0);
11016 tree v4hi_ftype_v4qi_v4hi
= build_function_type_list (v4hi
, v4qi
, v4hi
, 0);
11017 tree v4hi_ftype_v4qi_v2hi
= build_function_type_list (v4hi
, v4qi
, v2hi
, 0);
11018 tree v2si_ftype_v4qi_v2hi
= build_function_type_list (v2si
, v4qi
, v2hi
, 0);
11019 tree v4hi_ftype_v8qi_v4hi
= build_function_type_list (v4hi
, v8qi
, v4hi
, 0);
11020 tree v4hi_ftype_v4hi_v4hi
= build_function_type_list (v4hi
, v4hi
, v4hi
, 0);
11021 tree v2si_ftype_v2si_v2si
= build_function_type_list (v2si
, v2si
, v2si
, 0);
11022 tree v8qi_ftype_v8qi_v8qi
= build_function_type_list (v8qi
, v8qi
, v8qi
, 0);
11023 tree v2hi_ftype_v2hi_v2hi
= build_function_type_list (v2hi
, v2hi
, v2hi
, 0);
11024 tree v1si_ftype_v1si_v1si
= build_function_type_list (v1si
, v1si
, v1si
, 0);
11025 tree di_ftype_v8qi_v8qi_di
= build_function_type_list (intDI_type_node
,
11027 intDI_type_node
, 0);
11028 tree di_ftype_v8qi_v8qi
= build_function_type_list (intDI_type_node
,
11030 tree si_ftype_v8qi_v8qi
= build_function_type_list (intSI_type_node
,
11032 tree v8qi_ftype_df_si
= build_function_type_list (v8qi
, double_type_node
,
11033 intSI_type_node
, 0);
11034 tree v4hi_ftype_df_si
= build_function_type_list (v4hi
, double_type_node
,
11035 intSI_type_node
, 0);
11036 tree v2si_ftype_df_si
= build_function_type_list (v2si
, double_type_node
,
11037 intDI_type_node
, 0);
11038 tree di_ftype_di_di
= build_function_type_list (intDI_type_node
,
11040 intDI_type_node
, 0);
11041 tree si_ftype_si_si
= build_function_type_list (intSI_type_node
,
11043 intSI_type_node
, 0);
11044 tree ptr_ftype_ptr_si
= build_function_type_list (ptr_type_node
,
11046 intSI_type_node
, 0);
11047 tree ptr_ftype_ptr_di
= build_function_type_list (ptr_type_node
,
11049 intDI_type_node
, 0);
11050 tree si_ftype_ptr_ptr
= build_function_type_list (intSI_type_node
,
11053 tree di_ftype_ptr_ptr
= build_function_type_list (intDI_type_node
,
11056 tree si_ftype_v4hi_v4hi
= build_function_type_list (intSI_type_node
,
11058 tree si_ftype_v2si_v2si
= build_function_type_list (intSI_type_node
,
11060 tree di_ftype_v4hi_v4hi
= build_function_type_list (intDI_type_node
,
11062 tree di_ftype_v2si_v2si
= build_function_type_list (intDI_type_node
,
11064 tree void_ftype_di
= build_function_type_list (void_type_node
,
11065 intDI_type_node
, 0);
11066 tree di_ftype_void
= build_function_type_list (intDI_type_node
,
11067 void_type_node
, 0);
11068 tree void_ftype_si
= build_function_type_list (void_type_node
,
11069 intSI_type_node
, 0);
11070 tree sf_ftype_sf_sf
= build_function_type_list (float_type_node
,
11072 float_type_node
, 0);
11073 tree df_ftype_df_df
= build_function_type_list (double_type_node
,
11075 double_type_node
, 0);
11077 /* Packing and expanding vectors. */
11078 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis
,
11079 SPARC_BUILTIN_FPACK16
, v4qi_ftype_v4hi
);
11080 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis
,
11081 SPARC_BUILTIN_FPACK32
, v8qi_ftype_v2si_v8qi
);
11082 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis
,
11083 SPARC_BUILTIN_FPACKFIX
, v2hi_ftype_v2si
);
11084 def_builtin_const ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis
,
11085 SPARC_BUILTIN_FEXPAND
, v4hi_ftype_v4qi
);
11086 def_builtin_const ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis
,
11087 SPARC_BUILTIN_FPMERGE
, v8qi_ftype_v4qi_v4qi
);
11089 /* Multiplications. */
11090 def_builtin_const ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis
,
11091 SPARC_BUILTIN_FMUL8X16
, v4hi_ftype_v4qi_v4hi
);
11092 def_builtin_const ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis
,
11093 SPARC_BUILTIN_FMUL8X16AU
, v4hi_ftype_v4qi_v2hi
);
11094 def_builtin_const ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis
,
11095 SPARC_BUILTIN_FMUL8X16AL
, v4hi_ftype_v4qi_v2hi
);
11096 def_builtin_const ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis
,
11097 SPARC_BUILTIN_FMUL8SUX16
, v4hi_ftype_v8qi_v4hi
);
11098 def_builtin_const ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis
,
11099 SPARC_BUILTIN_FMUL8ULX16
, v4hi_ftype_v8qi_v4hi
);
11100 def_builtin_const ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis
,
11101 SPARC_BUILTIN_FMULD8SUX16
, v2si_ftype_v4qi_v2hi
);
11102 def_builtin_const ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis
,
11103 SPARC_BUILTIN_FMULD8ULX16
, v2si_ftype_v4qi_v2hi
);
11105 /* Data aligning. */
11106 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis
,
11107 SPARC_BUILTIN_FALIGNDATAV4HI
, v4hi_ftype_v4hi_v4hi
);
11108 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis
,
11109 SPARC_BUILTIN_FALIGNDATAV8QI
, v8qi_ftype_v8qi_v8qi
);
11110 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis
,
11111 SPARC_BUILTIN_FALIGNDATAV2SI
, v2si_ftype_v2si_v2si
);
11112 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatav1di_vis
,
11113 SPARC_BUILTIN_FALIGNDATADI
, di_ftype_di_di
);
11115 def_builtin ("__builtin_vis_write_gsr", CODE_FOR_wrgsr_vis
,
11116 SPARC_BUILTIN_WRGSR
, void_ftype_di
);
11117 def_builtin ("__builtin_vis_read_gsr", CODE_FOR_rdgsr_vis
,
11118 SPARC_BUILTIN_RDGSR
, di_ftype_void
);
11122 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis
,
11123 SPARC_BUILTIN_ALIGNADDR
, ptr_ftype_ptr_di
);
11124 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrldi_vis
,
11125 SPARC_BUILTIN_ALIGNADDRL
, ptr_ftype_ptr_di
);
11129 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis
,
11130 SPARC_BUILTIN_ALIGNADDR
, ptr_ftype_ptr_si
);
11131 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrlsi_vis
,
11132 SPARC_BUILTIN_ALIGNADDRL
, ptr_ftype_ptr_si
);
11135 /* Pixel distance. */
11136 def_builtin_const ("__builtin_vis_pdist", CODE_FOR_pdist_vis
,
11137 SPARC_BUILTIN_PDIST
, di_ftype_v8qi_v8qi_di
);
11139 /* Edge handling. */
11142 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8di_vis
,
11143 SPARC_BUILTIN_EDGE8
, di_ftype_ptr_ptr
);
11144 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8ldi_vis
,
11145 SPARC_BUILTIN_EDGE8L
, di_ftype_ptr_ptr
);
11146 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16di_vis
,
11147 SPARC_BUILTIN_EDGE16
, di_ftype_ptr_ptr
);
11148 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16ldi_vis
,
11149 SPARC_BUILTIN_EDGE16L
, di_ftype_ptr_ptr
);
11150 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32di_vis
,
11151 SPARC_BUILTIN_EDGE32
, di_ftype_ptr_ptr
);
11152 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32ldi_vis
,
11153 SPARC_BUILTIN_EDGE32L
, di_ftype_ptr_ptr
);
11157 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8si_vis
,
11158 SPARC_BUILTIN_EDGE8
, si_ftype_ptr_ptr
);
11159 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8lsi_vis
,
11160 SPARC_BUILTIN_EDGE8L
, si_ftype_ptr_ptr
);
11161 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16si_vis
,
11162 SPARC_BUILTIN_EDGE16
, si_ftype_ptr_ptr
);
11163 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16lsi_vis
,
11164 SPARC_BUILTIN_EDGE16L
, si_ftype_ptr_ptr
);
11165 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32si_vis
,
11166 SPARC_BUILTIN_EDGE32
, si_ftype_ptr_ptr
);
11167 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32lsi_vis
,
11168 SPARC_BUILTIN_EDGE32L
, si_ftype_ptr_ptr
);
11171 /* Pixel compare. */
11174 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16di_vis
,
11175 SPARC_BUILTIN_FCMPLE16
, di_ftype_v4hi_v4hi
);
11176 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32di_vis
,
11177 SPARC_BUILTIN_FCMPLE32
, di_ftype_v2si_v2si
);
11178 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16di_vis
,
11179 SPARC_BUILTIN_FCMPNE16
, di_ftype_v4hi_v4hi
);
11180 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32di_vis
,
11181 SPARC_BUILTIN_FCMPNE32
, di_ftype_v2si_v2si
);
11182 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16di_vis
,
11183 SPARC_BUILTIN_FCMPGT16
, di_ftype_v4hi_v4hi
);
11184 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32di_vis
,
11185 SPARC_BUILTIN_FCMPGT32
, di_ftype_v2si_v2si
);
11186 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16di_vis
,
11187 SPARC_BUILTIN_FCMPEQ16
, di_ftype_v4hi_v4hi
);
11188 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32di_vis
,
11189 SPARC_BUILTIN_FCMPEQ32
, di_ftype_v2si_v2si
);
11193 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16si_vis
,
11194 SPARC_BUILTIN_FCMPLE16
, si_ftype_v4hi_v4hi
);
11195 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32si_vis
,
11196 SPARC_BUILTIN_FCMPLE32
, si_ftype_v2si_v2si
);
11197 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16si_vis
,
11198 SPARC_BUILTIN_FCMPNE16
, si_ftype_v4hi_v4hi
);
11199 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32si_vis
,
11200 SPARC_BUILTIN_FCMPNE32
, si_ftype_v2si_v2si
);
11201 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16si_vis
,
11202 SPARC_BUILTIN_FCMPGT16
, si_ftype_v4hi_v4hi
);
11203 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32si_vis
,
11204 SPARC_BUILTIN_FCMPGT32
, si_ftype_v2si_v2si
);
11205 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16si_vis
,
11206 SPARC_BUILTIN_FCMPEQ16
, si_ftype_v4hi_v4hi
);
11207 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32si_vis
,
11208 SPARC_BUILTIN_FCMPEQ32
, si_ftype_v2si_v2si
);
11211 /* Addition and subtraction. */
11212 def_builtin_const ("__builtin_vis_fpadd16", CODE_FOR_addv4hi3
,
11213 SPARC_BUILTIN_FPADD16
, v4hi_ftype_v4hi_v4hi
);
11214 def_builtin_const ("__builtin_vis_fpadd16s", CODE_FOR_addv2hi3
,
11215 SPARC_BUILTIN_FPADD16S
, v2hi_ftype_v2hi_v2hi
);
11216 def_builtin_const ("__builtin_vis_fpadd32", CODE_FOR_addv2si3
,
11217 SPARC_BUILTIN_FPADD32
, v2si_ftype_v2si_v2si
);
11218 def_builtin_const ("__builtin_vis_fpadd32s", CODE_FOR_addv1si3
,
11219 SPARC_BUILTIN_FPADD32S
, v1si_ftype_v1si_v1si
);
11220 def_builtin_const ("__builtin_vis_fpsub16", CODE_FOR_subv4hi3
,
11221 SPARC_BUILTIN_FPSUB16
, v4hi_ftype_v4hi_v4hi
);
11222 def_builtin_const ("__builtin_vis_fpsub16s", CODE_FOR_subv2hi3
,
11223 SPARC_BUILTIN_FPSUB16S
, v2hi_ftype_v2hi_v2hi
);
11224 def_builtin_const ("__builtin_vis_fpsub32", CODE_FOR_subv2si3
,
11225 SPARC_BUILTIN_FPSUB32
, v2si_ftype_v2si_v2si
);
11226 def_builtin_const ("__builtin_vis_fpsub32s", CODE_FOR_subv1si3
,
11227 SPARC_BUILTIN_FPSUB32S
, v1si_ftype_v1si_v1si
);
11229 /* Three-dimensional array addressing. */
11232 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8di_vis
,
11233 SPARC_BUILTIN_ARRAY8
, di_ftype_di_di
);
11234 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16di_vis
,
11235 SPARC_BUILTIN_ARRAY16
, di_ftype_di_di
);
11236 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32di_vis
,
11237 SPARC_BUILTIN_ARRAY32
, di_ftype_di_di
);
11241 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8si_vis
,
11242 SPARC_BUILTIN_ARRAY8
, si_ftype_si_si
);
11243 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16si_vis
,
11244 SPARC_BUILTIN_ARRAY16
, si_ftype_si_si
);
11245 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32si_vis
,
11246 SPARC_BUILTIN_ARRAY32
, si_ftype_si_si
);
11251 /* Edge handling. */
11254 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8ndi_vis
,
11255 SPARC_BUILTIN_EDGE8N
, di_ftype_ptr_ptr
);
11256 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lndi_vis
,
11257 SPARC_BUILTIN_EDGE8LN
, di_ftype_ptr_ptr
);
11258 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16ndi_vis
,
11259 SPARC_BUILTIN_EDGE16N
, di_ftype_ptr_ptr
);
11260 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lndi_vis
,
11261 SPARC_BUILTIN_EDGE16LN
, di_ftype_ptr_ptr
);
11262 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32ndi_vis
,
11263 SPARC_BUILTIN_EDGE32N
, di_ftype_ptr_ptr
);
11264 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lndi_vis
,
11265 SPARC_BUILTIN_EDGE32LN
, di_ftype_ptr_ptr
);
11269 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8nsi_vis
,
11270 SPARC_BUILTIN_EDGE8N
, si_ftype_ptr_ptr
);
11271 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lnsi_vis
,
11272 SPARC_BUILTIN_EDGE8LN
, si_ftype_ptr_ptr
);
11273 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16nsi_vis
,
11274 SPARC_BUILTIN_EDGE16N
, si_ftype_ptr_ptr
);
11275 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lnsi_vis
,
11276 SPARC_BUILTIN_EDGE16LN
, si_ftype_ptr_ptr
);
11277 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32nsi_vis
,
11278 SPARC_BUILTIN_EDGE32N
, si_ftype_ptr_ptr
);
11279 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lnsi_vis
,
11280 SPARC_BUILTIN_EDGE32LN
, si_ftype_ptr_ptr
);
11283 /* Byte mask and shuffle. */
11285 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmaskdi_vis
,
11286 SPARC_BUILTIN_BMASK
, di_ftype_di_di
);
11288 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmasksi_vis
,
11289 SPARC_BUILTIN_BMASK
, si_ftype_si_si
);
11290 def_builtin ("__builtin_vis_bshufflev4hi", CODE_FOR_bshufflev4hi_vis
,
11291 SPARC_BUILTIN_BSHUFFLEV4HI
, v4hi_ftype_v4hi_v4hi
);
11292 def_builtin ("__builtin_vis_bshufflev8qi", CODE_FOR_bshufflev8qi_vis
,
11293 SPARC_BUILTIN_BSHUFFLEV8QI
, v8qi_ftype_v8qi_v8qi
);
11294 def_builtin ("__builtin_vis_bshufflev2si", CODE_FOR_bshufflev2si_vis
,
11295 SPARC_BUILTIN_BSHUFFLEV2SI
, v2si_ftype_v2si_v2si
);
11296 def_builtin ("__builtin_vis_bshuffledi", CODE_FOR_bshufflev1di_vis
,
11297 SPARC_BUILTIN_BSHUFFLEDI
, di_ftype_di_di
);
11304 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8di_vis
,
11305 SPARC_BUILTIN_CMASK8
, void_ftype_di
);
11306 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16di_vis
,
11307 SPARC_BUILTIN_CMASK16
, void_ftype_di
);
11308 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32di_vis
,
11309 SPARC_BUILTIN_CMASK32
, void_ftype_di
);
11313 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8si_vis
,
11314 SPARC_BUILTIN_CMASK8
, void_ftype_si
);
11315 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16si_vis
,
11316 SPARC_BUILTIN_CMASK16
, void_ftype_si
);
11317 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32si_vis
,
11318 SPARC_BUILTIN_CMASK32
, void_ftype_si
);
11321 def_builtin_const ("__builtin_vis_fchksm16", CODE_FOR_fchksm16_vis
,
11322 SPARC_BUILTIN_FCHKSM16
, v4hi_ftype_v4hi_v4hi
);
11324 def_builtin_const ("__builtin_vis_fsll16", CODE_FOR_vashlv4hi3
,
11325 SPARC_BUILTIN_FSLL16
, v4hi_ftype_v4hi_v4hi
);
11326 def_builtin_const ("__builtin_vis_fslas16", CODE_FOR_vssashlv4hi3
,
11327 SPARC_BUILTIN_FSLAS16
, v4hi_ftype_v4hi_v4hi
);
11328 def_builtin_const ("__builtin_vis_fsrl16", CODE_FOR_vlshrv4hi3
,
11329 SPARC_BUILTIN_FSRL16
, v4hi_ftype_v4hi_v4hi
);
11330 def_builtin_const ("__builtin_vis_fsra16", CODE_FOR_vashrv4hi3
,
11331 SPARC_BUILTIN_FSRA16
, v4hi_ftype_v4hi_v4hi
);
11332 def_builtin_const ("__builtin_vis_fsll32", CODE_FOR_vashlv2si3
,
11333 SPARC_BUILTIN_FSLL32
, v2si_ftype_v2si_v2si
);
11334 def_builtin_const ("__builtin_vis_fslas32", CODE_FOR_vssashlv2si3
,
11335 SPARC_BUILTIN_FSLAS32
, v2si_ftype_v2si_v2si
);
11336 def_builtin_const ("__builtin_vis_fsrl32", CODE_FOR_vlshrv2si3
,
11337 SPARC_BUILTIN_FSRL32
, v2si_ftype_v2si_v2si
);
11338 def_builtin_const ("__builtin_vis_fsra32", CODE_FOR_vashrv2si3
,
11339 SPARC_BUILTIN_FSRA32
, v2si_ftype_v2si_v2si
);
11342 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistndi_vis
,
11343 SPARC_BUILTIN_PDISTN
, di_ftype_v8qi_v8qi
);
11345 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistnsi_vis
,
11346 SPARC_BUILTIN_PDISTN
, si_ftype_v8qi_v8qi
);
11348 def_builtin_const ("__builtin_vis_fmean16", CODE_FOR_fmean16_vis
,
11349 SPARC_BUILTIN_FMEAN16
, v4hi_ftype_v4hi_v4hi
);
11350 def_builtin_const ("__builtin_vis_fpadd64", CODE_FOR_fpadd64_vis
,
11351 SPARC_BUILTIN_FPADD64
, di_ftype_di_di
);
11352 def_builtin_const ("__builtin_vis_fpsub64", CODE_FOR_fpsub64_vis
,
11353 SPARC_BUILTIN_FPSUB64
, di_ftype_di_di
);
11355 def_builtin_const ("__builtin_vis_fpadds16", CODE_FOR_ssaddv4hi3
,
11356 SPARC_BUILTIN_FPADDS16
, v4hi_ftype_v4hi_v4hi
);
11357 def_builtin_const ("__builtin_vis_fpadds16s", CODE_FOR_ssaddv2hi3
,
11358 SPARC_BUILTIN_FPADDS16S
, v2hi_ftype_v2hi_v2hi
);
11359 def_builtin_const ("__builtin_vis_fpsubs16", CODE_FOR_sssubv4hi3
,
11360 SPARC_BUILTIN_FPSUBS16
, v4hi_ftype_v4hi_v4hi
);
11361 def_builtin_const ("__builtin_vis_fpsubs16s", CODE_FOR_sssubv2hi3
,
11362 SPARC_BUILTIN_FPSUBS16S
, v2hi_ftype_v2hi_v2hi
);
11363 def_builtin_const ("__builtin_vis_fpadds32", CODE_FOR_ssaddv2si3
,
11364 SPARC_BUILTIN_FPADDS32
, v2si_ftype_v2si_v2si
);
11365 def_builtin_const ("__builtin_vis_fpadds32s", CODE_FOR_ssaddv1si3
,
11366 SPARC_BUILTIN_FPADDS32S
, v1si_ftype_v1si_v1si
);
11367 def_builtin_const ("__builtin_vis_fpsubs32", CODE_FOR_sssubv2si3
,
11368 SPARC_BUILTIN_FPSUBS32
, v2si_ftype_v2si_v2si
);
11369 def_builtin_const ("__builtin_vis_fpsubs32s", CODE_FOR_sssubv1si3
,
11370 SPARC_BUILTIN_FPSUBS32S
, v1si_ftype_v1si_v1si
);
11374 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8di_vis
,
11375 SPARC_BUILTIN_FUCMPLE8
, di_ftype_v8qi_v8qi
);
11376 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8di_vis
,
11377 SPARC_BUILTIN_FUCMPNE8
, di_ftype_v8qi_v8qi
);
11378 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8di_vis
,
11379 SPARC_BUILTIN_FUCMPGT8
, di_ftype_v8qi_v8qi
);
11380 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8di_vis
,
11381 SPARC_BUILTIN_FUCMPEQ8
, di_ftype_v8qi_v8qi
);
11385 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8si_vis
,
11386 SPARC_BUILTIN_FUCMPLE8
, si_ftype_v8qi_v8qi
);
11387 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8si_vis
,
11388 SPARC_BUILTIN_FUCMPNE8
, si_ftype_v8qi_v8qi
);
11389 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8si_vis
,
11390 SPARC_BUILTIN_FUCMPGT8
, si_ftype_v8qi_v8qi
);
11391 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8si_vis
,
11392 SPARC_BUILTIN_FUCMPEQ8
, si_ftype_v8qi_v8qi
);
11395 def_builtin_const ("__builtin_vis_fhadds", CODE_FOR_fhaddsf_vis
,
11396 SPARC_BUILTIN_FHADDS
, sf_ftype_sf_sf
);
11397 def_builtin_const ("__builtin_vis_fhaddd", CODE_FOR_fhadddf_vis
,
11398 SPARC_BUILTIN_FHADDD
, df_ftype_df_df
);
11399 def_builtin_const ("__builtin_vis_fhsubs", CODE_FOR_fhsubsf_vis
,
11400 SPARC_BUILTIN_FHSUBS
, sf_ftype_sf_sf
);
11401 def_builtin_const ("__builtin_vis_fhsubd", CODE_FOR_fhsubdf_vis
,
11402 SPARC_BUILTIN_FHSUBD
, df_ftype_df_df
);
11403 def_builtin_const ("__builtin_vis_fnhadds", CODE_FOR_fnhaddsf_vis
,
11404 SPARC_BUILTIN_FNHADDS
, sf_ftype_sf_sf
);
11405 def_builtin_const ("__builtin_vis_fnhaddd", CODE_FOR_fnhadddf_vis
,
11406 SPARC_BUILTIN_FNHADDD
, df_ftype_df_df
);
11408 def_builtin_const ("__builtin_vis_umulxhi", CODE_FOR_umulxhi_vis
,
11409 SPARC_BUILTIN_UMULXHI
, di_ftype_di_di
);
11410 def_builtin_const ("__builtin_vis_xmulx", CODE_FOR_xmulx_vis
,
11411 SPARC_BUILTIN_XMULX
, di_ftype_di_di
);
11412 def_builtin_const ("__builtin_vis_xmulxhi", CODE_FOR_xmulxhi_vis
,
11413 SPARC_BUILTIN_XMULXHI
, di_ftype_di_di
);
11418 def_builtin_const ("__builtin_vis_fpadd8", CODE_FOR_addv8qi3
,
11419 SPARC_BUILTIN_FPADD8
, v8qi_ftype_v8qi_v8qi
);
11420 def_builtin_const ("__builtin_vis_fpadds8", CODE_FOR_ssaddv8qi3
,
11421 SPARC_BUILTIN_FPADDS8
, v8qi_ftype_v8qi_v8qi
);
11422 def_builtin_const ("__builtin_vis_fpaddus8", CODE_FOR_usaddv8qi3
,
11423 SPARC_BUILTIN_FPADDUS8
, v8qi_ftype_v8qi_v8qi
);
11424 def_builtin_const ("__builtin_vis_fpaddus16", CODE_FOR_usaddv4hi3
,
11425 SPARC_BUILTIN_FPADDUS16
, v4hi_ftype_v4hi_v4hi
);
11430 def_builtin_const ("__builtin_vis_fpcmple8", CODE_FOR_fpcmple8di_vis
,
11431 SPARC_BUILTIN_FPCMPLE8
, di_ftype_v8qi_v8qi
);
11432 def_builtin_const ("__builtin_vis_fpcmpgt8", CODE_FOR_fpcmpgt8di_vis
,
11433 SPARC_BUILTIN_FPCMPGT8
, di_ftype_v8qi_v8qi
);
11434 def_builtin_const ("__builtin_vis_fpcmpule16", CODE_FOR_fpcmpule16di_vis
,
11435 SPARC_BUILTIN_FPCMPULE16
, di_ftype_v4hi_v4hi
);
11436 def_builtin_const ("__builtin_vis_fpcmpugt16", CODE_FOR_fpcmpugt16di_vis
,
11437 SPARC_BUILTIN_FPCMPUGT16
, di_ftype_v4hi_v4hi
);
11438 def_builtin_const ("__builtin_vis_fpcmpule32", CODE_FOR_fpcmpule32di_vis
,
11439 SPARC_BUILTIN_FPCMPULE32
, di_ftype_v2si_v2si
);
11440 def_builtin_const ("__builtin_vis_fpcmpugt32", CODE_FOR_fpcmpugt32di_vis
,
11441 SPARC_BUILTIN_FPCMPUGT32
, di_ftype_v2si_v2si
);
11445 def_builtin_const ("__builtin_vis_fpcmple8", CODE_FOR_fpcmple8si_vis
,
11446 SPARC_BUILTIN_FPCMPLE8
, si_ftype_v8qi_v8qi
);
11447 def_builtin_const ("__builtin_vis_fpcmpgt8", CODE_FOR_fpcmpgt8si_vis
,
11448 SPARC_BUILTIN_FPCMPGT8
, si_ftype_v8qi_v8qi
);
11449 def_builtin_const ("__builtin_vis_fpcmpule16", CODE_FOR_fpcmpule16si_vis
,
11450 SPARC_BUILTIN_FPCMPULE16
, si_ftype_v4hi_v4hi
);
11451 def_builtin_const ("__builtin_vis_fpcmpugt16", CODE_FOR_fpcmpugt16si_vis
,
11452 SPARC_BUILTIN_FPCMPUGT16
, si_ftype_v4hi_v4hi
);
11453 def_builtin_const ("__builtin_vis_fpcmpule32", CODE_FOR_fpcmpule32si_vis
,
11454 SPARC_BUILTIN_FPCMPULE32
, di_ftype_v2si_v2si
);
11455 def_builtin_const ("__builtin_vis_fpcmpugt32", CODE_FOR_fpcmpugt32si_vis
,
11456 SPARC_BUILTIN_FPCMPUGT32
, di_ftype_v2si_v2si
);
11459 def_builtin_const ("__builtin_vis_fpmax8", CODE_FOR_maxv8qi3
,
11460 SPARC_BUILTIN_FPMAX8
, v8qi_ftype_v8qi_v8qi
);
11461 def_builtin_const ("__builtin_vis_fpmax16", CODE_FOR_maxv4hi3
,
11462 SPARC_BUILTIN_FPMAX16
, v4hi_ftype_v4hi_v4hi
);
11463 def_builtin_const ("__builtin_vis_fpmax32", CODE_FOR_maxv2si3
,
11464 SPARC_BUILTIN_FPMAX32
, v2si_ftype_v2si_v2si
);
11465 def_builtin_const ("__builtin_vis_fpmaxu8", CODE_FOR_maxuv8qi3
,
11466 SPARC_BUILTIN_FPMAXU8
, v8qi_ftype_v8qi_v8qi
);
11467 def_builtin_const ("__builtin_vis_fpmaxu16", CODE_FOR_maxuv4hi3
,
11468 SPARC_BUILTIN_FPMAXU16
, v4hi_ftype_v4hi_v4hi
);
11469 def_builtin_const ("__builtin_vis_fpmaxu32", CODE_FOR_maxuv2si3
,
11470 SPARC_BUILTIN_FPMAXU32
, v2si_ftype_v2si_v2si
);
11471 def_builtin_const ("__builtin_vis_fpmin8", CODE_FOR_minv8qi3
,
11472 SPARC_BUILTIN_FPMIN8
, v8qi_ftype_v8qi_v8qi
);
11473 def_builtin_const ("__builtin_vis_fpmin16", CODE_FOR_minv4hi3
,
11474 SPARC_BUILTIN_FPMIN16
, v4hi_ftype_v4hi_v4hi
);
11475 def_builtin_const ("__builtin_vis_fpmin32", CODE_FOR_minv2si3
,
11476 SPARC_BUILTIN_FPMIN32
, v2si_ftype_v2si_v2si
);
11477 def_builtin_const ("__builtin_vis_fpminu8", CODE_FOR_minuv8qi3
,
11478 SPARC_BUILTIN_FPMINU8
, v8qi_ftype_v8qi_v8qi
);
11479 def_builtin_const ("__builtin_vis_fpminu16", CODE_FOR_minuv4hi3
,
11480 SPARC_BUILTIN_FPMINU16
, v4hi_ftype_v4hi_v4hi
);
11481 def_builtin_const ("__builtin_vis_fpminu32", CODE_FOR_minuv2si3
,
11482 SPARC_BUILTIN_FPMINU32
, v2si_ftype_v2si_v2si
);
11483 def_builtin_const ("__builtin_vis_fpsub8", CODE_FOR_subv8qi3
,
11484 SPARC_BUILTIN_FPSUB8
, v8qi_ftype_v8qi_v8qi
);
11485 def_builtin_const ("__builtin_vis_fpsubs8", CODE_FOR_sssubv8qi3
,
11486 SPARC_BUILTIN_FPSUBS8
, v8qi_ftype_v8qi_v8qi
);
11487 def_builtin_const ("__builtin_vis_fpsubus8", CODE_FOR_ussubv8qi3
,
11488 SPARC_BUILTIN_FPSUBUS8
, v8qi_ftype_v8qi_v8qi
);
11489 def_builtin_const ("__builtin_vis_fpsubus16", CODE_FOR_ussubv4hi3
,
11490 SPARC_BUILTIN_FPSUBUS16
, v4hi_ftype_v4hi_v4hi
);
11495 def_builtin_const ("__builtin_vis_dictunpack8", CODE_FOR_dictunpack8
,
11496 SPARC_BUILTIN_DICTUNPACK8
, v8qi_ftype_df_si
);
11497 def_builtin_const ("__builtin_vis_dictunpack16", CODE_FOR_dictunpack16
,
11498 SPARC_BUILTIN_DICTUNPACK16
, v4hi_ftype_df_si
);
11499 def_builtin_const ("__builtin_vis_dictunpack32", CODE_FOR_dictunpack32
,
11500 SPARC_BUILTIN_DICTUNPACK32
, v2si_ftype_df_si
);
11504 tree di_ftype_v8qi_v8qi_si
= build_function_type_list (intDI_type_node
,
11506 intSI_type_node
, 0);
11507 tree di_ftype_v4hi_v4hi_si
= build_function_type_list (intDI_type_node
,
11509 intSI_type_node
, 0);
11510 tree di_ftype_v2si_v2si_si
= build_function_type_list (intDI_type_node
,
11512 intSI_type_node
, 0);
11514 def_builtin_const ("__builtin_vis_fpcmple8shl", CODE_FOR_fpcmple8dishl
,
11515 SPARC_BUILTIN_FPCMPLE8SHL
, di_ftype_v8qi_v8qi_si
);
11516 def_builtin_const ("__builtin_vis_fpcmpgt8shl", CODE_FOR_fpcmpgt8dishl
,
11517 SPARC_BUILTIN_FPCMPGT8SHL
, di_ftype_v8qi_v8qi_si
);
11518 def_builtin_const ("__builtin_vis_fpcmpeq8shl", CODE_FOR_fpcmpeq8dishl
,
11519 SPARC_BUILTIN_FPCMPEQ8SHL
, di_ftype_v8qi_v8qi_si
);
11520 def_builtin_const ("__builtin_vis_fpcmpne8shl", CODE_FOR_fpcmpne8dishl
,
11521 SPARC_BUILTIN_FPCMPNE8SHL
, di_ftype_v8qi_v8qi_si
);
11523 def_builtin_const ("__builtin_vis_fpcmple16shl", CODE_FOR_fpcmple16dishl
,
11524 SPARC_BUILTIN_FPCMPLE16SHL
, di_ftype_v4hi_v4hi_si
);
11525 def_builtin_const ("__builtin_vis_fpcmpgt16shl", CODE_FOR_fpcmpgt16dishl
,
11526 SPARC_BUILTIN_FPCMPGT16SHL
, di_ftype_v4hi_v4hi_si
);
11527 def_builtin_const ("__builtin_vis_fpcmpeq16shl", CODE_FOR_fpcmpeq16dishl
,
11528 SPARC_BUILTIN_FPCMPEQ16SHL
, di_ftype_v4hi_v4hi_si
);
11529 def_builtin_const ("__builtin_vis_fpcmpne16shl", CODE_FOR_fpcmpne16dishl
,
11530 SPARC_BUILTIN_FPCMPNE16SHL
, di_ftype_v4hi_v4hi_si
);
11532 def_builtin_const ("__builtin_vis_fpcmple32shl", CODE_FOR_fpcmple32dishl
,
11533 SPARC_BUILTIN_FPCMPLE32SHL
, di_ftype_v2si_v2si_si
);
11534 def_builtin_const ("__builtin_vis_fpcmpgt32shl", CODE_FOR_fpcmpgt32dishl
,
11535 SPARC_BUILTIN_FPCMPGT32SHL
, di_ftype_v2si_v2si_si
);
11536 def_builtin_const ("__builtin_vis_fpcmpeq32shl", CODE_FOR_fpcmpeq32dishl
,
11537 SPARC_BUILTIN_FPCMPEQ32SHL
, di_ftype_v2si_v2si_si
);
11538 def_builtin_const ("__builtin_vis_fpcmpne32shl", CODE_FOR_fpcmpne32dishl
,
11539 SPARC_BUILTIN_FPCMPNE32SHL
, di_ftype_v2si_v2si_si
);
11542 def_builtin_const ("__builtin_vis_fpcmpule8shl", CODE_FOR_fpcmpule8dishl
,
11543 SPARC_BUILTIN_FPCMPULE8SHL
, di_ftype_v8qi_v8qi_si
);
11544 def_builtin_const ("__builtin_vis_fpcmpugt8shl", CODE_FOR_fpcmpugt8dishl
,
11545 SPARC_BUILTIN_FPCMPUGT8SHL
, di_ftype_v8qi_v8qi_si
);
11547 def_builtin_const ("__builtin_vis_fpcmpule16shl", CODE_FOR_fpcmpule16dishl
,
11548 SPARC_BUILTIN_FPCMPULE16SHL
, di_ftype_v4hi_v4hi_si
);
11549 def_builtin_const ("__builtin_vis_fpcmpugt16shl", CODE_FOR_fpcmpugt16dishl
,
11550 SPARC_BUILTIN_FPCMPUGT16SHL
, di_ftype_v4hi_v4hi_si
);
11552 def_builtin_const ("__builtin_vis_fpcmpule32shl", CODE_FOR_fpcmpule32dishl
,
11553 SPARC_BUILTIN_FPCMPULE32SHL
, di_ftype_v2si_v2si_si
);
11554 def_builtin_const ("__builtin_vis_fpcmpugt32shl", CODE_FOR_fpcmpugt32dishl
,
11555 SPARC_BUILTIN_FPCMPUGT32SHL
, di_ftype_v2si_v2si_si
);
11557 def_builtin_const ("__builtin_vis_fpcmpde8shl", CODE_FOR_fpcmpde8dishl
,
11558 SPARC_BUILTIN_FPCMPDE8SHL
, di_ftype_v8qi_v8qi_si
);
11559 def_builtin_const ("__builtin_vis_fpcmpde16shl", CODE_FOR_fpcmpde16dishl
,
11560 SPARC_BUILTIN_FPCMPDE16SHL
, di_ftype_v4hi_v4hi_si
);
11561 def_builtin_const ("__builtin_vis_fpcmpde32shl", CODE_FOR_fpcmpde32dishl
,
11562 SPARC_BUILTIN_FPCMPDE32SHL
, di_ftype_v2si_v2si_si
);
11564 def_builtin_const ("__builtin_vis_fpcmpur8shl", CODE_FOR_fpcmpur8dishl
,
11565 SPARC_BUILTIN_FPCMPUR8SHL
, di_ftype_v8qi_v8qi_si
);
11566 def_builtin_const ("__builtin_vis_fpcmpur16shl", CODE_FOR_fpcmpur16dishl
,
11567 SPARC_BUILTIN_FPCMPUR16SHL
, di_ftype_v4hi_v4hi_si
);
11568 def_builtin_const ("__builtin_vis_fpcmpur32shl", CODE_FOR_fpcmpur32dishl
,
11569 SPARC_BUILTIN_FPCMPUR32SHL
, di_ftype_v2si_v2si_si
);
11574 tree si_ftype_v8qi_v8qi_si
= build_function_type_list (intSI_type_node
,
11576 intSI_type_node
, 0);
11577 tree si_ftype_v4hi_v4hi_si
= build_function_type_list (intSI_type_node
,
11579 intSI_type_node
, 0);
11580 tree si_ftype_v2si_v2si_si
= build_function_type_list (intSI_type_node
,
11582 intSI_type_node
, 0);
11584 def_builtin_const ("__builtin_vis_fpcmple8shl", CODE_FOR_fpcmple8sishl
,
11585 SPARC_BUILTIN_FPCMPLE8SHL
, si_ftype_v8qi_v8qi_si
);
11586 def_builtin_const ("__builtin_vis_fpcmpgt8shl", CODE_FOR_fpcmpgt8sishl
,
11587 SPARC_BUILTIN_FPCMPGT8SHL
, si_ftype_v8qi_v8qi_si
);
11588 def_builtin_const ("__builtin_vis_fpcmpeq8shl", CODE_FOR_fpcmpeq8sishl
,
11589 SPARC_BUILTIN_FPCMPEQ8SHL
, si_ftype_v8qi_v8qi_si
);
11590 def_builtin_const ("__builtin_vis_fpcmpne8shl", CODE_FOR_fpcmpne8sishl
,
11591 SPARC_BUILTIN_FPCMPNE8SHL
, si_ftype_v8qi_v8qi_si
);
11593 def_builtin_const ("__builtin_vis_fpcmple16shl", CODE_FOR_fpcmple16sishl
,
11594 SPARC_BUILTIN_FPCMPLE16SHL
, si_ftype_v4hi_v4hi_si
);
11595 def_builtin_const ("__builtin_vis_fpcmpgt16shl", CODE_FOR_fpcmpgt16sishl
,
11596 SPARC_BUILTIN_FPCMPGT16SHL
, si_ftype_v4hi_v4hi_si
);
11597 def_builtin_const ("__builtin_vis_fpcmpeq16shl", CODE_FOR_fpcmpeq16sishl
,
11598 SPARC_BUILTIN_FPCMPEQ16SHL
, si_ftype_v4hi_v4hi_si
);
11599 def_builtin_const ("__builtin_vis_fpcmpne16shl", CODE_FOR_fpcmpne16sishl
,
11600 SPARC_BUILTIN_FPCMPNE16SHL
, si_ftype_v4hi_v4hi_si
);
11602 def_builtin_const ("__builtin_vis_fpcmple32shl", CODE_FOR_fpcmple32sishl
,
11603 SPARC_BUILTIN_FPCMPLE32SHL
, si_ftype_v2si_v2si_si
);
11604 def_builtin_const ("__builtin_vis_fpcmpgt32shl", CODE_FOR_fpcmpgt32sishl
,
11605 SPARC_BUILTIN_FPCMPGT32SHL
, si_ftype_v2si_v2si_si
);
11606 def_builtin_const ("__builtin_vis_fpcmpeq32shl", CODE_FOR_fpcmpeq32sishl
,
11607 SPARC_BUILTIN_FPCMPEQ32SHL
, si_ftype_v2si_v2si_si
);
11608 def_builtin_const ("__builtin_vis_fpcmpne32shl", CODE_FOR_fpcmpne32sishl
,
11609 SPARC_BUILTIN_FPCMPNE32SHL
, si_ftype_v2si_v2si_si
);
11612 def_builtin_const ("__builtin_vis_fpcmpule8shl", CODE_FOR_fpcmpule8sishl
,
11613 SPARC_BUILTIN_FPCMPULE8SHL
, si_ftype_v8qi_v8qi_si
);
11614 def_builtin_const ("__builtin_vis_fpcmpugt8shl", CODE_FOR_fpcmpugt8sishl
,
11615 SPARC_BUILTIN_FPCMPUGT8SHL
, si_ftype_v8qi_v8qi_si
);
11617 def_builtin_const ("__builtin_vis_fpcmpule16shl", CODE_FOR_fpcmpule16sishl
,
11618 SPARC_BUILTIN_FPCMPULE16SHL
, si_ftype_v4hi_v4hi_si
);
11619 def_builtin_const ("__builtin_vis_fpcmpugt16shl", CODE_FOR_fpcmpugt16sishl
,
11620 SPARC_BUILTIN_FPCMPUGT16SHL
, si_ftype_v4hi_v4hi_si
);
11622 def_builtin_const ("__builtin_vis_fpcmpule32shl", CODE_FOR_fpcmpule32sishl
,
11623 SPARC_BUILTIN_FPCMPULE32SHL
, si_ftype_v2si_v2si_si
);
11624 def_builtin_const ("__builtin_vis_fpcmpugt32shl", CODE_FOR_fpcmpugt32sishl
,
11625 SPARC_BUILTIN_FPCMPUGT32SHL
, si_ftype_v2si_v2si_si
);
11627 def_builtin_const ("__builtin_vis_fpcmpde8shl", CODE_FOR_fpcmpde8sishl
,
11628 SPARC_BUILTIN_FPCMPDE8SHL
, si_ftype_v8qi_v8qi_si
);
11629 def_builtin_const ("__builtin_vis_fpcmpde16shl", CODE_FOR_fpcmpde16sishl
,
11630 SPARC_BUILTIN_FPCMPDE16SHL
, si_ftype_v4hi_v4hi_si
);
11631 def_builtin_const ("__builtin_vis_fpcmpde32shl", CODE_FOR_fpcmpde32sishl
,
11632 SPARC_BUILTIN_FPCMPDE32SHL
, si_ftype_v2si_v2si_si
);
11634 def_builtin_const ("__builtin_vis_fpcmpur8shl", CODE_FOR_fpcmpur8sishl
,
11635 SPARC_BUILTIN_FPCMPUR8SHL
, si_ftype_v8qi_v8qi_si
);
11636 def_builtin_const ("__builtin_vis_fpcmpur16shl", CODE_FOR_fpcmpur16sishl
,
11637 SPARC_BUILTIN_FPCMPUR16SHL
, si_ftype_v4hi_v4hi_si
);
11638 def_builtin_const ("__builtin_vis_fpcmpur32shl", CODE_FOR_fpcmpur32sishl
,
11639 SPARC_BUILTIN_FPCMPUR32SHL
, si_ftype_v2si_v2si_si
);
11644 /* Implement TARGET_BUILTIN_DECL hook. */
11647 sparc_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
11649 if (code
>= SPARC_BUILTIN_MAX
)
11650 return error_mark_node
;
11652 return sparc_builtins
[code
];
11655 /* Implemented TARGET_EXPAND_BUILTIN hook. */
11658 sparc_expand_builtin (tree exp
, rtx target
,
11659 rtx subtarget ATTRIBUTE_UNUSED
,
11660 machine_mode tmode ATTRIBUTE_UNUSED
,
11661 int ignore ATTRIBUTE_UNUSED
)
11663 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
11664 enum sparc_builtins code
11665 = (enum sparc_builtins
) DECL_MD_FUNCTION_CODE (fndecl
);
11666 enum insn_code icode
= sparc_builtins_icode
[code
];
11667 bool nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
11668 call_expr_arg_iterator iter
;
11675 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11677 || GET_MODE (target
) != tmode
11678 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11679 op
[0] = gen_reg_rtx (tmode
);
11686 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
11688 const struct insn_operand_data
*insn_op
;
11691 if (arg
== error_mark_node
)
11695 idx
= arg_count
- !nonvoid
;
11696 insn_op
= &insn_data
[icode
].operand
[idx
];
11697 op
[arg_count
] = expand_normal (arg
);
11699 /* Some of the builtins require constant arguments. We check
11701 if ((code
>= SPARC_BUILTIN_FIRST_FPCMPSHL
11702 && code
<= SPARC_BUILTIN_LAST_FPCMPSHL
11704 || (code
>= SPARC_BUILTIN_FIRST_DICTUNPACK
11705 && code
<= SPARC_BUILTIN_LAST_DICTUNPACK
11706 && arg_count
== 2))
11708 if (!check_constant_argument (icode
, idx
, op
[arg_count
]))
11712 if (code
== SPARC_BUILTIN_LDFSR
|| code
== SPARC_BUILTIN_STFSR
)
11714 if (!address_operand (op
[arg_count
], SImode
))
11716 op
[arg_count
] = convert_memory_address (Pmode
, op
[arg_count
]);
11717 op
[arg_count
] = copy_addr_to_reg (op
[arg_count
]);
11719 op
[arg_count
] = gen_rtx_MEM (SImode
, op
[arg_count
]);
11722 else if (insn_op
->mode
== V1DImode
11723 && GET_MODE (op
[arg_count
]) == DImode
)
11724 op
[arg_count
] = gen_lowpart (V1DImode
, op
[arg_count
]);
11726 else if (insn_op
->mode
== V1SImode
11727 && GET_MODE (op
[arg_count
]) == SImode
)
11728 op
[arg_count
] = gen_lowpart (V1SImode
, op
[arg_count
]);
11730 if (! (*insn_data
[icode
].operand
[idx
].predicate
) (op
[arg_count
],
11732 op
[arg_count
] = copy_to_mode_reg (insn_op
->mode
, op
[arg_count
]);
11738 pat
= GEN_FCN (icode
) (op
[0]);
11742 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
11744 pat
= GEN_FCN (icode
) (op
[1]);
11747 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
11750 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
11753 gcc_unreachable ();
11761 return (nonvoid
? op
[0] : const0_rtx
);
11764 /* Return the upper 16 bits of the 8x16 multiplication. */
11767 sparc_vis_mul8x16 (int e8
, int e16
)
11769 return (e8
* e16
+ 128) / 256;
11772 /* Multiply the VECTOR_CSTs CST0 and CST1 as specified by FNCODE and put
11773 the result into the array N_ELTS, whose elements are of INNER_TYPE. */
11776 sparc_handle_vis_mul8x16 (vec
<tree
> *n_elts
, enum sparc_builtins fncode
,
11777 tree inner_type
, tree cst0
, tree cst1
)
11779 unsigned i
, num
= VECTOR_CST_NELTS (cst0
);
11784 case SPARC_BUILTIN_FMUL8X16
:
11785 for (i
= 0; i
< num
; ++i
)
11788 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
11789 TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, i
)));
11790 n_elts
->quick_push (build_int_cst (inner_type
, val
));
11794 case SPARC_BUILTIN_FMUL8X16AU
:
11795 scale
= TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, 0));
11797 for (i
= 0; i
< num
; ++i
)
11800 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
11802 n_elts
->quick_push (build_int_cst (inner_type
, val
));
11806 case SPARC_BUILTIN_FMUL8X16AL
:
11807 scale
= TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, 1));
11809 for (i
= 0; i
< num
; ++i
)
11812 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
11814 n_elts
->quick_push (build_int_cst (inner_type
, val
));
11819 gcc_unreachable ();
11823 /* Implement TARGET_FOLD_BUILTIN hook.
11825 Fold builtin functions for SPARC intrinsics. If IGNORE is true the
11826 result of the function call is ignored. NULL_TREE is returned if the
11827 function could not be folded. */
11830 sparc_fold_builtin (tree fndecl
, int n_args ATTRIBUTE_UNUSED
,
11831 tree
*args
, bool ignore
)
11833 enum sparc_builtins code
11834 = (enum sparc_builtins
) DECL_MD_FUNCTION_CODE (fndecl
);
11835 tree rtype
= TREE_TYPE (TREE_TYPE (fndecl
));
11836 tree arg0
, arg1
, arg2
;
11841 case SPARC_BUILTIN_LDFSR
:
11842 case SPARC_BUILTIN_STFSR
:
11843 case SPARC_BUILTIN_ALIGNADDR
:
11844 case SPARC_BUILTIN_WRGSR
:
11845 case SPARC_BUILTIN_BMASK
:
11846 case SPARC_BUILTIN_CMASK8
:
11847 case SPARC_BUILTIN_CMASK16
:
11848 case SPARC_BUILTIN_CMASK32
:
11852 return build_zero_cst (rtype
);
11857 case SPARC_BUILTIN_FEXPAND
:
11861 if (TREE_CODE (arg0
) == VECTOR_CST
)
11863 tree inner_type
= TREE_TYPE (rtype
);
11866 tree_vector_builder
n_elts (rtype
, VECTOR_CST_NELTS (arg0
), 1);
11867 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
11869 unsigned HOST_WIDE_INT val
11870 = TREE_INT_CST_LOW (VECTOR_CST_ELT (arg0
, i
));
11871 n_elts
.quick_push (build_int_cst (inner_type
, val
<< 4));
11873 return n_elts
.build ();
11877 case SPARC_BUILTIN_FMUL8X16
:
11878 case SPARC_BUILTIN_FMUL8X16AU
:
11879 case SPARC_BUILTIN_FMUL8X16AL
:
11885 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
11887 tree inner_type
= TREE_TYPE (rtype
);
11888 tree_vector_builder
n_elts (rtype
, VECTOR_CST_NELTS (arg0
), 1);
11889 sparc_handle_vis_mul8x16 (&n_elts
, code
, inner_type
, arg0
, arg1
);
11890 return n_elts
.build ();
11894 case SPARC_BUILTIN_FPMERGE
:
11900 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
11902 tree_vector_builder
n_elts (rtype
, 2 * VECTOR_CST_NELTS (arg0
), 1);
11904 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
11906 n_elts
.quick_push (VECTOR_CST_ELT (arg0
, i
));
11907 n_elts
.quick_push (VECTOR_CST_ELT (arg1
, i
));
11910 return n_elts
.build ();
11914 case SPARC_BUILTIN_PDIST
:
11915 case SPARC_BUILTIN_PDISTN
:
11920 if (code
== SPARC_BUILTIN_PDIST
)
11926 arg2
= integer_zero_node
;
11928 if (TREE_CODE (arg0
) == VECTOR_CST
11929 && TREE_CODE (arg1
) == VECTOR_CST
11930 && TREE_CODE (arg2
) == INTEGER_CST
)
11932 bool overflow
= false;
11933 widest_int result
= wi::to_widest (arg2
);
11937 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
11939 tree e0
= VECTOR_CST_ELT (arg0
, i
);
11940 tree e1
= VECTOR_CST_ELT (arg1
, i
);
11942 wi::overflow_type neg1_ovf
, neg2_ovf
, add1_ovf
, add2_ovf
;
11944 tmp
= wi::neg (wi::to_widest (e1
), &neg1_ovf
);
11945 tmp
= wi::add (wi::to_widest (e0
), tmp
, SIGNED
, &add1_ovf
);
11946 if (wi::neg_p (tmp
))
11947 tmp
= wi::neg (tmp
, &neg2_ovf
);
11949 neg2_ovf
= wi::OVF_NONE
;
11950 result
= wi::add (result
, tmp
, SIGNED
, &add2_ovf
);
11951 overflow
|= ((neg1_ovf
!= wi::OVF_NONE
)
11952 | (neg2_ovf
!= wi::OVF_NONE
)
11953 | (add1_ovf
!= wi::OVF_NONE
)
11954 | (add2_ovf
!= wi::OVF_NONE
));
11957 gcc_assert (!overflow
);
11959 return wide_int_to_tree (rtype
, result
);
11969 /* ??? This duplicates information provided to the compiler by the
11970 ??? scheduler description. Some day, teach genautomata to output
11971 ??? the latencies and then CSE will just use that. */
11974 sparc_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
11975 int opno ATTRIBUTE_UNUSED
,
11976 int *total
, bool speed ATTRIBUTE_UNUSED
)
11978 int code
= GET_CODE (x
);
11979 bool float_mode_p
= FLOAT_MODE_P (mode
);
11990 case CONST_WIDE_INT
:
11992 if (!SPARC_SIMM13_P (CONST_WIDE_INT_ELT (x
, 0)))
11994 if (!SPARC_SIMM13_P (CONST_WIDE_INT_ELT (x
, 1)))
12013 /* If outer-code was a sign or zero extension, a cost
12014 of COSTS_N_INSNS (1) was already added in. This is
12015 why we are subtracting it back out. */
12016 if (outer_code
== ZERO_EXTEND
)
12018 *total
= sparc_costs
->int_zload
- COSTS_N_INSNS (1);
12020 else if (outer_code
== SIGN_EXTEND
)
12022 *total
= sparc_costs
->int_sload
- COSTS_N_INSNS (1);
12024 else if (float_mode_p
)
12026 *total
= sparc_costs
->float_load
;
12030 *total
= sparc_costs
->int_load
;
12038 *total
= sparc_costs
->float_plusminus
;
12040 *total
= COSTS_N_INSNS (1);
12047 gcc_assert (float_mode_p
);
12048 *total
= sparc_costs
->float_mul
;
12051 if (GET_CODE (sub
) == NEG
)
12052 sub
= XEXP (sub
, 0);
12053 *total
+= rtx_cost (sub
, mode
, FMA
, 0, speed
);
12056 if (GET_CODE (sub
) == NEG
)
12057 sub
= XEXP (sub
, 0);
12058 *total
+= rtx_cost (sub
, mode
, FMA
, 2, speed
);
12064 *total
= sparc_costs
->float_mul
;
12065 else if (TARGET_ARCH32
&& !TARGET_HARD_MUL
)
12066 *total
= COSTS_N_INSNS (25);
12072 if (sparc_costs
->int_mul_bit_factor
)
12076 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
12078 unsigned HOST_WIDE_INT value
= INTVAL (XEXP (x
, 1));
12079 for (nbits
= 0; value
!= 0; value
&= value
- 1)
12087 bit_cost
= (nbits
- 3) / sparc_costs
->int_mul_bit_factor
;
12088 bit_cost
= COSTS_N_INSNS (bit_cost
);
12091 if (mode
== DImode
|| !TARGET_HARD_MUL
)
12092 *total
= sparc_costs
->int_mulX
+ bit_cost
;
12094 *total
= sparc_costs
->int_mul
+ bit_cost
;
12101 *total
= COSTS_N_INSNS (1) + sparc_costs
->shift_penalty
;
12110 if (mode
== DFmode
)
12111 *total
= sparc_costs
->float_div_df
;
12113 *total
= sparc_costs
->float_div_sf
;
12117 if (mode
== DImode
)
12118 *total
= sparc_costs
->int_divX
;
12120 *total
= sparc_costs
->int_div
;
12125 if (! float_mode_p
)
12127 *total
= COSTS_N_INSNS (1);
12134 case UNSIGNED_FLOAT
:
12138 case FLOAT_TRUNCATE
:
12139 *total
= sparc_costs
->float_move
;
12143 if (mode
== DFmode
)
12144 *total
= sparc_costs
->float_sqrt_df
;
12146 *total
= sparc_costs
->float_sqrt_sf
;
12151 *total
= sparc_costs
->float_cmp
;
12153 *total
= COSTS_N_INSNS (1);
12158 *total
= sparc_costs
->float_cmove
;
12160 *total
= sparc_costs
->int_cmove
;
12164 /* Handle the NAND vector patterns. */
12165 if (sparc_vector_mode_supported_p (mode
)
12166 && GET_CODE (XEXP (x
, 0)) == NOT
12167 && GET_CODE (XEXP (x
, 1)) == NOT
)
12169 *total
= COSTS_N_INSNS (1);
12180 /* Return true if CLASS is either GENERAL_REGS or I64_REGS. */
12183 general_or_i64_p (reg_class_t rclass
)
12185 return (rclass
== GENERAL_REGS
|| rclass
== I64_REGS
);
12188 /* Implement TARGET_REGISTER_MOVE_COST. */
12191 sparc_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
12192 reg_class_t from
, reg_class_t to
)
12194 bool need_memory
= false;
12196 /* This helps postreload CSE to eliminate redundant comparisons. */
12197 if (from
== NO_REGS
|| to
== NO_REGS
)
12200 if (from
== FPCC_REGS
|| to
== FPCC_REGS
)
12201 need_memory
= true;
12202 else if ((FP_REG_CLASS_P (from
) && general_or_i64_p (to
))
12203 || (general_or_i64_p (from
) && FP_REG_CLASS_P (to
)))
12207 int size
= GET_MODE_SIZE (mode
);
12208 if (size
== 8 || size
== 4)
12210 if (! TARGET_ARCH32
|| size
== 4)
12216 need_memory
= true;
12221 if (sparc_cpu
== PROCESSOR_ULTRASPARC
12222 || sparc_cpu
== PROCESSOR_ULTRASPARC3
12223 || sparc_cpu
== PROCESSOR_NIAGARA
12224 || sparc_cpu
== PROCESSOR_NIAGARA2
12225 || sparc_cpu
== PROCESSOR_NIAGARA3
12226 || sparc_cpu
== PROCESSOR_NIAGARA4
12227 || sparc_cpu
== PROCESSOR_NIAGARA7
12228 || sparc_cpu
== PROCESSOR_M8
)
12237 /* Emit the sequence of insns SEQ while preserving the registers REG and REG2.
12238 This is achieved by means of a manual dynamic stack space allocation in
12239 the current frame. We make the assumption that SEQ doesn't contain any
12240 function calls, with the possible exception of calls to the GOT helper. */
12243 emit_and_preserve (rtx seq
, rtx reg
, rtx reg2
)
12245 /* We must preserve the lowest 16 words for the register save area. */
12246 HOST_WIDE_INT offset
= 16*UNITS_PER_WORD
;
12247 /* We really need only 2 words of fresh stack space. */
12248 HOST_WIDE_INT size
= SPARC_STACK_ALIGN (offset
+ 2*UNITS_PER_WORD
);
12251 = gen_rtx_MEM (word_mode
, plus_constant (Pmode
, stack_pointer_rtx
,
12252 SPARC_STACK_BIAS
+ offset
));
12254 emit_insn (gen_stack_pointer_inc (GEN_INT (-size
)));
12255 emit_insn (gen_rtx_SET (slot
, reg
));
12257 emit_insn (gen_rtx_SET (adjust_address (slot
, word_mode
, UNITS_PER_WORD
),
12261 emit_insn (gen_rtx_SET (reg2
,
12262 adjust_address (slot
, word_mode
, UNITS_PER_WORD
)));
12263 emit_insn (gen_rtx_SET (reg
, slot
));
12264 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
12267 /* Output the assembler code for a thunk function. THUNK_DECL is the
12268 declaration for the thunk function itself, FUNCTION is the decl for
12269 the target function. DELTA is an immediate constant offset to be
12270 added to THIS. If VCALL_OFFSET is nonzero, the word at address
12271 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
12274 sparc_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
12275 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
12278 const char *fnname
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk_fndecl
));
12279 rtx this_rtx
, funexp
;
12281 unsigned int int_arg_first
;
12283 reload_completed
= 1;
12284 epilogue_completed
= 1;
12286 emit_note (NOTE_INSN_PROLOGUE_END
);
12290 sparc_leaf_function_p
= 1;
12292 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
12294 else if (flag_delayed_branch
)
12296 /* We will emit a regular sibcall below, so we need to instruct
12297 output_sibcall that we are in a leaf function. */
12298 sparc_leaf_function_p
= crtl
->uses_only_leaf_regs
= 1;
12300 /* This will cause final.c to invoke leaf_renumber_regs so we
12301 must behave as if we were in a not-yet-leafified function. */
12302 int_arg_first
= SPARC_INCOMING_INT_ARG_FIRST
;
12306 /* We will emit the sibcall manually below, so we will need to
12307 manually spill non-leaf registers. */
12308 sparc_leaf_function_p
= crtl
->uses_only_leaf_regs
= 0;
12310 /* We really are in a leaf function. */
12311 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
12314 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
12315 returns a structure, the structure return pointer is there instead. */
12317 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
12318 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
+ 1);
12320 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
);
12322 /* Add DELTA. When possible use a plain add, otherwise load it into
12323 a register first. */
12326 rtx delta_rtx
= GEN_INT (delta
);
12328 if (! SPARC_SIMM13_P (delta
))
12330 rtx scratch
= gen_rtx_REG (Pmode
, 1);
12331 emit_move_insn (scratch
, delta_rtx
);
12332 delta_rtx
= scratch
;
12335 /* THIS_RTX += DELTA. */
12336 emit_insn (gen_add2_insn (this_rtx
, delta_rtx
));
12339 /* Add the word at address (*THIS_RTX + VCALL_OFFSET). */
12342 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
12343 rtx scratch
= gen_rtx_REG (Pmode
, 1);
12345 gcc_assert (vcall_offset
< 0);
12347 /* SCRATCH = *THIS_RTX. */
12348 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
, this_rtx
));
12350 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
12351 may not have any available scratch register at this point. */
12352 if (SPARC_SIMM13_P (vcall_offset
))
12354 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
12355 else if (! fixed_regs
[5]
12356 /* The below sequence is made up of at least 2 insns,
12357 while the default method may need only one. */
12358 && vcall_offset
< -8192)
12360 rtx scratch2
= gen_rtx_REG (Pmode
, 5);
12361 emit_move_insn (scratch2
, vcall_offset_rtx
);
12362 vcall_offset_rtx
= scratch2
;
12366 rtx increment
= GEN_INT (-4096);
12368 /* VCALL_OFFSET is a negative number whose typical range can be
12369 estimated as -32768..0 in 32-bit mode. In almost all cases
12370 it is therefore cheaper to emit multiple add insns than
12371 spilling and loading the constant into a register (at least
12373 while (! SPARC_SIMM13_P (vcall_offset
))
12375 emit_insn (gen_add2_insn (scratch
, increment
));
12376 vcall_offset
+= 4096;
12378 vcall_offset_rtx
= GEN_INT (vcall_offset
); /* cannot be 0 */
12381 /* SCRATCH = *(*THIS_RTX + VCALL_OFFSET). */
12382 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
,
12383 gen_rtx_PLUS (Pmode
,
12385 vcall_offset_rtx
)));
12387 /* THIS_RTX += *(*THIS_RTX + VCALL_OFFSET). */
12388 emit_insn (gen_add2_insn (this_rtx
, scratch
));
12391 /* Generate a tail call to the target function. */
12392 if (! TREE_USED (function
))
12394 assemble_external (function
);
12395 TREE_USED (function
) = 1;
12397 funexp
= XEXP (DECL_RTL (function
), 0);
12399 if (flag_delayed_branch
)
12401 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
12402 insn
= emit_call_insn (gen_sibcall (funexp
));
12403 SIBLING_CALL_P (insn
) = 1;
12407 /* The hoops we have to jump through in order to generate a sibcall
12408 without using delay slots... */
12409 rtx spill_reg
, seq
, scratch
= gen_rtx_REG (Pmode
, 1);
12413 spill_reg
= gen_rtx_REG (word_mode
, 15); /* %o7 */
12415 load_got_register (); /* clobbers %o7 */
12416 if (!TARGET_VXWORKS_RTP
)
12417 pic_offset_table_rtx
= got_register_rtx
;
12418 scratch
= sparc_legitimize_pic_address (funexp
, scratch
);
12419 seq
= get_insns ();
12421 emit_and_preserve (seq
, spill_reg
, pic_offset_table_rtx
);
12423 else if (TARGET_ARCH32
)
12425 emit_insn (gen_rtx_SET (scratch
,
12426 gen_rtx_HIGH (SImode
, funexp
)));
12427 emit_insn (gen_rtx_SET (scratch
,
12428 gen_rtx_LO_SUM (SImode
, scratch
, funexp
)));
12430 else /* TARGET_ARCH64 */
12432 switch (sparc_code_model
)
12436 /* The destination can serve as a temporary. */
12437 sparc_emit_set_symbolic_const64 (scratch
, funexp
, scratch
);
12442 /* The destination cannot serve as a temporary. */
12443 spill_reg
= gen_rtx_REG (DImode
, 15); /* %o7 */
12445 sparc_emit_set_symbolic_const64 (scratch
, funexp
, spill_reg
);
12446 seq
= get_insns ();
12448 emit_and_preserve (seq
, spill_reg
, 0);
12452 gcc_unreachable ();
12456 emit_jump_insn (gen_indirect_jump (scratch
));
12461 /* Run just enough of rest_of_compilation to get the insns emitted.
12462 There's not really enough bulk here to make other passes such as
12463 instruction scheduling worth while. */
12464 insn
= get_insns ();
12465 shorten_branches (insn
);
12466 assemble_start_function (thunk_fndecl
, fnname
);
12467 final_start_function (insn
, file
, 1);
12468 final (insn
, file
, 1);
12469 final_end_function ();
12470 assemble_end_function (thunk_fndecl
, fnname
);
12472 reload_completed
= 0;
12473 epilogue_completed
= 0;
12476 /* Return true if sparc_output_mi_thunk would be able to output the
12477 assembler code for the thunk function specified by the arguments
12478 it is passed, and false otherwise. */
12480 sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED
,
12481 HOST_WIDE_INT delta ATTRIBUTE_UNUSED
,
12482 HOST_WIDE_INT vcall_offset
,
12483 const_tree function ATTRIBUTE_UNUSED
)
12485 /* Bound the loop used in the default method above. */
12486 return (vcall_offset
>= -32768 || ! fixed_regs
[5]);
12489 /* How to allocate a 'struct machine_function'. */
12491 static struct machine_function
*
12492 sparc_init_machine_status (void)
12494 return ggc_cleared_alloc
<machine_function
> ();
12497 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
12499 static unsigned HOST_WIDE_INT
12500 sparc_asan_shadow_offset (void)
12502 return TARGET_ARCH64
? (HOST_WIDE_INT_1
<< 43) : (HOST_WIDE_INT_1
<< 29);
12505 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
12506 We need to emit DTP-relative relocations. */
12509 sparc_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
12514 fputs ("\t.word\t%r_tls_dtpoff32(", file
);
12517 fputs ("\t.xword\t%r_tls_dtpoff64(", file
);
12520 gcc_unreachable ();
12522 output_addr_const (file
, x
);
12526 /* Do whatever processing is required at the end of a file. */
12529 sparc_file_end (void)
12531 /* If we need to emit the special GOT helper function, do so now. */
12532 if (got_helper_rtx
)
12534 const char *name
= XSTR (got_helper_rtx
, 0);
12535 const char *reg_name
= reg_names
[GLOBAL_OFFSET_TABLE_REGNUM
];
12536 #ifdef DWARF2_UNWIND_INFO
12540 if (USE_HIDDEN_LINKONCE
)
12542 tree decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
12543 get_identifier (name
),
12544 build_function_type_list (void_type_node
,
12546 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
12547 NULL_TREE
, void_type_node
);
12548 TREE_PUBLIC (decl
) = 1;
12549 TREE_STATIC (decl
) = 1;
12550 make_decl_one_only (decl
, DECL_ASSEMBLER_NAME (decl
));
12551 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
12552 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
12553 resolve_unique_section (decl
, 0, flag_function_sections
);
12554 allocate_struct_function (decl
, true);
12555 cfun
->is_thunk
= 1;
12556 current_function_decl
= decl
;
12557 init_varasm_status ();
12558 assemble_start_function (decl
, name
);
12562 const int align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
12563 switch_to_section (text_section
);
12565 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
12566 ASM_OUTPUT_LABEL (asm_out_file
, name
);
12569 #ifdef DWARF2_UNWIND_INFO
12570 do_cfi
= dwarf2out_do_cfi_asm ();
12572 fprintf (asm_out_file
, "\t.cfi_startproc\n");
12574 if (flag_delayed_branch
)
12575 fprintf (asm_out_file
, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
12576 reg_name
, reg_name
);
12578 fprintf (asm_out_file
, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
12579 reg_name
, reg_name
);
12580 #ifdef DWARF2_UNWIND_INFO
12582 fprintf (asm_out_file
, "\t.cfi_endproc\n");
12586 if (NEED_INDICATE_EXEC_STACK
)
12587 file_end_indicate_exec_stack ();
12589 #ifdef TARGET_SOLARIS
12590 solaris_file_end ();
12594 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
12595 /* Implement TARGET_MANGLE_TYPE. */
12597 static const char *
12598 sparc_mangle_type (const_tree type
)
12601 && TYPE_MAIN_VARIANT (type
) == long_double_type_node
12602 && TARGET_LONG_DOUBLE_128
)
12605 /* For all other types, use normal C++ mangling. */
12610 /* Expand a membar instruction for various use cases. Both the LOAD_STORE
12611 and BEFORE_AFTER arguments of the form X_Y. They are two-bit masks where
12612 bit 0 indicates that X is true, and bit 1 indicates Y is true. */
12615 sparc_emit_membar_for_model (enum memmodel model
,
12616 int load_store
, int before_after
)
12618 /* Bits for the MEMBAR mmask field. */
12619 const int LoadLoad
= 1;
12620 const int StoreLoad
= 2;
12621 const int LoadStore
= 4;
12622 const int StoreStore
= 8;
12624 int mm
= 0, implied
= 0;
12626 switch (sparc_memory_model
)
12629 /* Sequential Consistency. All memory transactions are immediately
12630 visible in sequential execution order. No barriers needed. */
12631 implied
= LoadLoad
| StoreLoad
| LoadStore
| StoreStore
;
12635 /* Total Store Ordering: all memory transactions with store semantics
12636 are followed by an implied StoreStore. */
12637 implied
|= StoreStore
;
12639 /* If we're not looking for a raw barrer (before+after), then atomic
12640 operations get the benefit of being both load and store. */
12641 if (load_store
== 3 && before_after
== 1)
12642 implied
|= StoreLoad
;
12646 /* Partial Store Ordering: all memory transactions with load semantics
12647 are followed by an implied LoadLoad | LoadStore. */
12648 implied
|= LoadLoad
| LoadStore
;
12650 /* If we're not looking for a raw barrer (before+after), then atomic
12651 operations get the benefit of being both load and store. */
12652 if (load_store
== 3 && before_after
== 2)
12653 implied
|= StoreLoad
| StoreStore
;
12657 /* Relaxed Memory Ordering: no implicit bits. */
12661 gcc_unreachable ();
12664 if (before_after
& 1)
12666 if (is_mm_release (model
) || is_mm_acq_rel (model
)
12667 || is_mm_seq_cst (model
))
12669 if (load_store
& 1)
12670 mm
|= LoadLoad
| StoreLoad
;
12671 if (load_store
& 2)
12672 mm
|= LoadStore
| StoreStore
;
12675 if (before_after
& 2)
12677 if (is_mm_acquire (model
) || is_mm_acq_rel (model
)
12678 || is_mm_seq_cst (model
))
12680 if (load_store
& 1)
12681 mm
|= LoadLoad
| LoadStore
;
12682 if (load_store
& 2)
12683 mm
|= StoreLoad
| StoreStore
;
12687 /* Remove the bits implied by the system memory model. */
12690 /* For raw barriers (before+after), always emit a barrier.
12691 This will become a compile-time barrier if needed. */
12692 if (mm
|| before_after
== 3)
12693 emit_insn (gen_membar (GEN_INT (mm
)));
12696 /* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit
12697 compare and swap on the word containing the byte or half-word. */
12700 sparc_expand_compare_and_swap_12 (rtx bool_result
, rtx result
, rtx mem
,
12701 rtx oldval
, rtx newval
)
12703 rtx addr1
= force_reg (Pmode
, XEXP (mem
, 0));
12704 rtx addr
= gen_reg_rtx (Pmode
);
12705 rtx off
= gen_reg_rtx (SImode
);
12706 rtx oldv
= gen_reg_rtx (SImode
);
12707 rtx newv
= gen_reg_rtx (SImode
);
12708 rtx oldvalue
= gen_reg_rtx (SImode
);
12709 rtx newvalue
= gen_reg_rtx (SImode
);
12710 rtx res
= gen_reg_rtx (SImode
);
12711 rtx resv
= gen_reg_rtx (SImode
);
12712 rtx memsi
, val
, mask
, cc
;
12714 emit_insn (gen_rtx_SET (addr
, gen_rtx_AND (Pmode
, addr1
, GEN_INT (-4))));
12716 if (Pmode
!= SImode
)
12717 addr1
= gen_lowpart (SImode
, addr1
);
12718 emit_insn (gen_rtx_SET (off
, gen_rtx_AND (SImode
, addr1
, GEN_INT (3))));
12720 memsi
= gen_rtx_MEM (SImode
, addr
);
12721 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
12722 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
12724 val
= copy_to_reg (memsi
);
12726 emit_insn (gen_rtx_SET (off
,
12727 gen_rtx_XOR (SImode
, off
,
12728 GEN_INT (GET_MODE (mem
) == QImode
12731 emit_insn (gen_rtx_SET (off
, gen_rtx_ASHIFT (SImode
, off
, GEN_INT (3))));
12733 if (GET_MODE (mem
) == QImode
)
12734 mask
= force_reg (SImode
, GEN_INT (0xff));
12736 mask
= force_reg (SImode
, GEN_INT (0xffff));
12738 emit_insn (gen_rtx_SET (mask
, gen_rtx_ASHIFT (SImode
, mask
, off
)));
12740 emit_insn (gen_rtx_SET (val
,
12741 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
12744 oldval
= gen_lowpart (SImode
, oldval
);
12745 emit_insn (gen_rtx_SET (oldv
, gen_rtx_ASHIFT (SImode
, oldval
, off
)));
12747 newval
= gen_lowpart_common (SImode
, newval
);
12748 emit_insn (gen_rtx_SET (newv
, gen_rtx_ASHIFT (SImode
, newval
, off
)));
12750 emit_insn (gen_rtx_SET (oldv
, gen_rtx_AND (SImode
, oldv
, mask
)));
12752 emit_insn (gen_rtx_SET (newv
, gen_rtx_AND (SImode
, newv
, mask
)));
12754 rtx_code_label
*end_label
= gen_label_rtx ();
12755 rtx_code_label
*loop_label
= gen_label_rtx ();
12756 emit_label (loop_label
);
12758 emit_insn (gen_rtx_SET (oldvalue
, gen_rtx_IOR (SImode
, oldv
, val
)));
12760 emit_insn (gen_rtx_SET (newvalue
, gen_rtx_IOR (SImode
, newv
, val
)));
12762 emit_move_insn (bool_result
, const1_rtx
);
12764 emit_insn (gen_atomic_compare_and_swapsi_1 (res
, memsi
, oldvalue
, newvalue
));
12766 emit_cmp_and_jump_insns (res
, oldvalue
, EQ
, NULL
, SImode
, 0, end_label
);
12768 emit_insn (gen_rtx_SET (resv
,
12769 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
12772 emit_move_insn (bool_result
, const0_rtx
);
12774 cc
= gen_compare_reg_1 (NE
, resv
, val
);
12775 emit_insn (gen_rtx_SET (val
, resv
));
12777 /* Use cbranchcc4 to separate the compare and branch! */
12778 emit_jump_insn (gen_cbranchcc4 (gen_rtx_NE (VOIDmode
, cc
, const0_rtx
),
12779 cc
, const0_rtx
, loop_label
));
12781 emit_label (end_label
);
12783 emit_insn (gen_rtx_SET (res
, gen_rtx_AND (SImode
, res
, mask
)));
12785 emit_insn (gen_rtx_SET (res
, gen_rtx_LSHIFTRT (SImode
, res
, off
)));
12787 emit_move_insn (result
, gen_lowpart (GET_MODE (result
), res
));
12790 /* Expand code to perform a compare-and-swap. */
12793 sparc_expand_compare_and_swap (rtx operands
[])
12795 rtx bval
, retval
, mem
, oldval
, newval
;
12797 enum memmodel model
;
12799 bval
= operands
[0];
12800 retval
= operands
[1];
12802 oldval
= operands
[3];
12803 newval
= operands
[4];
12804 model
= (enum memmodel
) INTVAL (operands
[6]);
12805 mode
= GET_MODE (mem
);
12807 sparc_emit_membar_for_model (model
, 3, 1);
12809 if (reg_overlap_mentioned_p (retval
, oldval
))
12810 oldval
= copy_to_reg (oldval
);
12812 if (mode
== QImode
|| mode
== HImode
)
12813 sparc_expand_compare_and_swap_12 (bval
, retval
, mem
, oldval
, newval
);
12816 rtx (*gen
) (rtx
, rtx
, rtx
, rtx
);
12819 if (mode
== SImode
)
12820 gen
= gen_atomic_compare_and_swapsi_1
;
12822 gen
= gen_atomic_compare_and_swapdi_1
;
12823 emit_insn (gen (retval
, mem
, oldval
, newval
));
12825 x
= emit_store_flag (bval
, EQ
, retval
, oldval
, mode
, 1, 1);
12827 convert_move (bval
, x
, 1);
12830 sparc_emit_membar_for_model (model
, 3, 2);
12834 sparc_expand_vec_perm_bmask (machine_mode vmode
, rtx sel
)
12838 sel
= gen_lowpart (DImode
, sel
);
12842 /* inp = xxxxxxxAxxxxxxxB */
12843 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
12844 NULL_RTX
, 1, OPTAB_DIRECT
);
12845 /* t_1 = ....xxxxxxxAxxx. */
12846 sel
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, sel
),
12847 GEN_INT (3), NULL_RTX
, 1, OPTAB_DIRECT
);
12848 t_1
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_1
),
12849 GEN_INT (0x30000), NULL_RTX
, 1, OPTAB_DIRECT
);
12850 /* sel = .......B */
12851 /* t_1 = ...A.... */
12852 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_1
, sel
, 1, OPTAB_DIRECT
);
12853 /* sel = ...A...B */
12854 sel
= expand_mult (SImode
, sel
, GEN_INT (0x4444), sel
, 1);
12855 /* sel = AAAABBBB * 4 */
12856 t_1
= force_reg (SImode
, GEN_INT (0x01230123));
12857 /* sel = { A*4, A*4+1, A*4+2, ... } */
12861 /* inp = xxxAxxxBxxxCxxxD */
12862 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (8),
12863 NULL_RTX
, 1, OPTAB_DIRECT
);
12864 t_2
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
12865 NULL_RTX
, 1, OPTAB_DIRECT
);
12866 t_3
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (24),
12867 NULL_RTX
, 1, OPTAB_DIRECT
);
12868 /* t_1 = ..xxxAxxxBxxxCxx */
12869 /* t_2 = ....xxxAxxxBxxxC */
12870 /* t_3 = ......xxxAxxxBxx */
12871 sel
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, sel
),
12873 NULL_RTX
, 1, OPTAB_DIRECT
);
12874 t_1
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_1
),
12876 NULL_RTX
, 1, OPTAB_DIRECT
);
12877 t_2
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_2
),
12878 GEN_INT (0x070000),
12879 NULL_RTX
, 1, OPTAB_DIRECT
);
12880 t_3
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_3
),
12881 GEN_INT (0x07000000),
12882 NULL_RTX
, 1, OPTAB_DIRECT
);
12883 /* sel = .......D */
12884 /* t_1 = .....C.. */
12885 /* t_2 = ...B.... */
12886 /* t_3 = .A...... */
12887 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_1
, sel
, 1, OPTAB_DIRECT
);
12888 t_2
= expand_simple_binop (SImode
, IOR
, t_2
, t_3
, t_2
, 1, OPTAB_DIRECT
);
12889 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_2
, sel
, 1, OPTAB_DIRECT
);
12890 /* sel = .A.B.C.D */
12891 sel
= expand_mult (SImode
, sel
, GEN_INT (0x22), sel
, 1);
12892 /* sel = AABBCCDD * 2 */
12893 t_1
= force_reg (SImode
, GEN_INT (0x01010101));
12894 /* sel = { A*2, A*2+1, B*2, B*2+1, ... } */
12898 /* input = xAxBxCxDxExFxGxH */
12899 sel
= expand_simple_binop (DImode
, AND
, sel
,
12900 GEN_INT ((HOST_WIDE_INT
)0x0f0f0f0f << 32
12902 NULL_RTX
, 1, OPTAB_DIRECT
);
12903 /* sel = .A.B.C.D.E.F.G.H */
12904 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (4),
12905 NULL_RTX
, 1, OPTAB_DIRECT
);
12906 /* t_1 = ..A.B.C.D.E.F.G. */
12907 sel
= expand_simple_binop (DImode
, IOR
, sel
, t_1
,
12908 NULL_RTX
, 1, OPTAB_DIRECT
);
12909 /* sel = .AABBCCDDEEFFGGH */
12910 sel
= expand_simple_binop (DImode
, AND
, sel
,
12911 GEN_INT ((HOST_WIDE_INT
)0xff00ff << 32
12913 NULL_RTX
, 1, OPTAB_DIRECT
);
12914 /* sel = ..AB..CD..EF..GH */
12915 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (8),
12916 NULL_RTX
, 1, OPTAB_DIRECT
);
12917 /* t_1 = ....AB..CD..EF.. */
12918 sel
= expand_simple_binop (DImode
, IOR
, sel
, t_1
,
12919 NULL_RTX
, 1, OPTAB_DIRECT
);
12920 /* sel = ..ABABCDCDEFEFGH */
12921 sel
= expand_simple_binop (DImode
, AND
, sel
,
12922 GEN_INT ((HOST_WIDE_INT
)0xffff << 32 | 0xffff),
12923 NULL_RTX
, 1, OPTAB_DIRECT
);
12924 /* sel = ....ABCD....EFGH */
12925 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
12926 NULL_RTX
, 1, OPTAB_DIRECT
);
12927 /* t_1 = ........ABCD.... */
12928 sel
= gen_lowpart (SImode
, sel
);
12929 t_1
= gen_lowpart (SImode
, t_1
);
12933 gcc_unreachable ();
12936 /* Always perform the final addition/merge within the bmask insn. */
12937 emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode
), sel
, t_1
));
12940 /* Implement TARGET_VEC_PERM_CONST. */
12943 sparc_vectorize_vec_perm_const (machine_mode vmode
, rtx target
, rtx op0
,
12944 rtx op1
, const vec_perm_indices
&sel
)
12949 /* All permutes are supported. */
12953 /* Force target-independent code to convert constant permutations on other
12954 modes down to V8QI. Rely on this to avoid the complexity of the byte
12955 order of the permutation. */
12956 if (vmode
!= V8QImode
)
12959 unsigned int i
, mask
;
12960 for (i
= mask
= 0; i
< 8; ++i
)
12961 mask
|= (sel
[i
] & 0xf) << (28 - i
*4);
12962 rtx mask_rtx
= force_reg (SImode
, gen_int_mode (mask
, SImode
));
12964 emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode
), mask_rtx
, const0_rtx
));
12965 emit_insn (gen_bshufflev8qi_vis (target
, op0
, op1
));
12969 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
12972 sparc_frame_pointer_required (void)
12974 /* If the stack pointer is dynamically modified in the function, it cannot
12975 serve as the frame pointer. */
12976 if (cfun
->calls_alloca
)
12979 /* If the function receives nonlocal gotos, it needs to save the frame
12980 pointer in the nonlocal_goto_save_area object. */
12981 if (cfun
->has_nonlocal_label
)
12984 /* In flat mode, that's it. */
12988 /* Otherwise, the frame pointer is required if the function isn't leaf, but
12989 we cannot use sparc_leaf_function_p since it hasn't been computed yet. */
12990 return !(optimize
> 0 && crtl
->is_leaf
&& only_leaf_regs_used ());
12993 /* The way this is structured, we can't eliminate SFP in favor of SP
12994 if the frame pointer is required: we want to use the SFP->HFP elimination
12995 in that case. But the test in update_eliminables doesn't know we are
12996 assuming below that we only do the former elimination. */
12999 sparc_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
13001 return to
== HARD_FRAME_POINTER_REGNUM
|| !sparc_frame_pointer_required ();
13004 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
13005 they won't be allocated. */
13008 sparc_conditional_register_usage (void)
13010 if (PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
13012 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
13013 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
13015 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */
13016 /* then honor it. */
13017 if (TARGET_ARCH32
&& fixed_regs
[5])
13019 else if (TARGET_ARCH64
&& fixed_regs
[5] == 2)
13024 for (regno
= SPARC_FIRST_V9_FP_REG
;
13025 regno
<= SPARC_LAST_V9_FP_REG
;
13027 fixed_regs
[regno
] = 1;
13028 /* %fcc0 is used by v8 and v9. */
13029 for (regno
= SPARC_FIRST_V9_FCC_REG
+ 1;
13030 regno
<= SPARC_LAST_V9_FCC_REG
;
13032 fixed_regs
[regno
] = 1;
13037 for (regno
= 32; regno
< SPARC_LAST_V9_FCC_REG
; regno
++)
13038 fixed_regs
[regno
] = 1;
13040 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */
13041 /* then honor it. Likewise with g3 and g4. */
13042 if (fixed_regs
[2] == 2)
13043 fixed_regs
[2] = ! TARGET_APP_REGS
;
13044 if (fixed_regs
[3] == 2)
13045 fixed_regs
[3] = ! TARGET_APP_REGS
;
13046 if (TARGET_ARCH32
&& fixed_regs
[4] == 2)
13047 fixed_regs
[4] = ! TARGET_APP_REGS
;
13048 else if (TARGET_CM_EMBMEDANY
)
13050 else if (fixed_regs
[4] == 2)
13055 /* Disable leaf functions. */
13056 memset (sparc_leaf_regs
, 0, FIRST_PSEUDO_REGISTER
);
13057 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
13058 leaf_reg_remap
[regno
] = regno
;
13061 global_regs
[SPARC_GSR_REG
] = 1;
13064 /* Implement TARGET_USE_PSEUDO_PIC_REG. */
13067 sparc_use_pseudo_pic_reg (void)
13069 return !TARGET_VXWORKS_RTP
&& flag_pic
;
13072 /* Implement TARGET_INIT_PIC_REG. */
13075 sparc_init_pic_reg (void)
13080 if (!crtl
->uses_pic_offset_table
)
13084 load_got_register ();
13085 if (!TARGET_VXWORKS_RTP
)
13086 emit_move_insn (pic_offset_table_rtx
, got_register_rtx
);
13087 seq
= get_insns ();
13090 entry_edge
= single_succ_edge (ENTRY_BLOCK_PTR_FOR_FN (cfun
));
13091 insert_insn_on_edge (seq
, entry_edge
);
13092 commit_one_edge_insertion (entry_edge
);
13095 /* Implement TARGET_PREFERRED_RELOAD_CLASS:
13097 - We can't load constants into FP registers.
13098 - We can't load FP constants into integer registers when soft-float,
13099 because there is no soft-float pattern with a r/F constraint.
13100 - We can't load FP constants into integer registers for TFmode unless
13101 it is 0.0L, because there is no movtf pattern with a r/F constraint.
13102 - Try and reload integer constants (symbolic or otherwise) back into
13103 registers directly, rather than having them dumped to memory. */
13106 sparc_preferred_reload_class (rtx x
, reg_class_t rclass
)
13108 machine_mode mode
= GET_MODE (x
);
13109 if (CONSTANT_P (x
))
13111 if (FP_REG_CLASS_P (rclass
)
13112 || rclass
== GENERAL_OR_FP_REGS
13113 || rclass
== GENERAL_OR_EXTRA_FP_REGS
13114 || (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& ! TARGET_FPU
)
13115 || (mode
== TFmode
&& ! const_zero_operand (x
, mode
)))
13118 if (GET_MODE_CLASS (mode
) == MODE_INT
)
13119 return GENERAL_REGS
;
13121 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
13123 if (! FP_REG_CLASS_P (rclass
)
13124 || !(const_zero_operand (x
, mode
)
13125 || const_all_ones_operand (x
, mode
)))
13132 && (rclass
== EXTRA_FP_REGS
13133 || rclass
== GENERAL_OR_EXTRA_FP_REGS
))
13135 int regno
= true_regnum (x
);
13137 if (SPARC_INT_REG_P (regno
))
13138 return (rclass
== EXTRA_FP_REGS
13139 ? FP_REGS
: GENERAL_OR_FP_REGS
);
13145 /* Return true if we use LRA instead of reload pass. */
13153 /* Output a wide multiply instruction in V8+ mode. INSN is the instruction,
13154 OPERANDS are its operands and OPCODE is the mnemonic to be used. */
13157 output_v8plus_mult (rtx_insn
*insn
, rtx
*operands
, const char *opcode
)
13161 gcc_assert (! TARGET_ARCH64
);
13163 if (sparc_check_64 (operands
[1], insn
) <= 0)
13164 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
13165 if (which_alternative
== 1)
13166 output_asm_insn ("sllx\t%H1, 32, %H1", operands
);
13167 if (GET_CODE (operands
[2]) == CONST_INT
)
13169 if (which_alternative
== 1)
13171 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
13172 sprintf (mulstr
, "%s\t%%H1, %%2, %%L0", opcode
);
13173 output_asm_insn (mulstr
, operands
);
13174 return "srlx\t%L0, 32, %H0";
13178 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
13179 output_asm_insn ("or\t%L1, %3, %3", operands
);
13180 sprintf (mulstr
, "%s\t%%3, %%2, %%3", opcode
);
13181 output_asm_insn (mulstr
, operands
);
13182 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
13183 return "mov\t%3, %L0";
13186 else if (rtx_equal_p (operands
[1], operands
[2]))
13188 if (which_alternative
== 1)
13190 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
13191 sprintf (mulstr
, "%s\t%%H1, %%H1, %%L0", opcode
);
13192 output_asm_insn (mulstr
, operands
);
13193 return "srlx\t%L0, 32, %H0";
13197 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
13198 output_asm_insn ("or\t%L1, %3, %3", operands
);
13199 sprintf (mulstr
, "%s\t%%3, %%3, %%3", opcode
);
13200 output_asm_insn (mulstr
, operands
);
13201 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
13202 return "mov\t%3, %L0";
13205 if (sparc_check_64 (operands
[2], insn
) <= 0)
13206 output_asm_insn ("srl\t%L2, 0, %L2", operands
);
13207 if (which_alternative
== 1)
13209 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
13210 output_asm_insn ("sllx\t%H2, 32, %L1", operands
);
13211 output_asm_insn ("or\t%L2, %L1, %L1", operands
);
13212 sprintf (mulstr
, "%s\t%%H1, %%L1, %%L0", opcode
);
13213 output_asm_insn (mulstr
, operands
);
13214 return "srlx\t%L0, 32, %H0";
13218 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
13219 output_asm_insn ("sllx\t%H2, 32, %4", operands
);
13220 output_asm_insn ("or\t%L1, %3, %3", operands
);
13221 output_asm_insn ("or\t%L2, %4, %4", operands
);
13222 sprintf (mulstr
, "%s\t%%3, %%4, %%3", opcode
);
13223 output_asm_insn (mulstr
, operands
);
13224 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
13225 return "mov\t%3, %L0";
13229 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
13230 all fields of TARGET to ELT by means of VIS2 BSHUFFLE insn. MODE
13231 and INNER_MODE are the modes describing TARGET. */
13234 vector_init_bshuffle (rtx target
, rtx elt
, machine_mode mode
,
13235 machine_mode inner_mode
)
13237 rtx t1
, final_insn
, sel
;
13240 t1
= gen_reg_rtx (mode
);
13242 elt
= convert_modes (SImode
, inner_mode
, elt
, true);
13243 emit_move_insn (gen_lowpart(SImode
, t1
), elt
);
13248 final_insn
= gen_bshufflev2si_vis (target
, t1
, t1
);
13249 bmask
= 0x45674567;
13252 final_insn
= gen_bshufflev4hi_vis (target
, t1
, t1
);
13253 bmask
= 0x67676767;
13256 final_insn
= gen_bshufflev8qi_vis (target
, t1
, t1
);
13257 bmask
= 0x77777777;
13260 gcc_unreachable ();
13263 sel
= force_reg (SImode
, GEN_INT (bmask
));
13264 emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode
), sel
, const0_rtx
));
13265 emit_insn (final_insn
);
13268 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
13269 all fields of TARGET to ELT in V8QI by means of VIS FPMERGE insn. */
13272 vector_init_fpmerge (rtx target
, rtx elt
)
13274 rtx t1
, t2
, t2_low
, t3
, t3_low
;
13276 t1
= gen_reg_rtx (V4QImode
);
13277 elt
= convert_modes (SImode
, QImode
, elt
, true);
13278 emit_move_insn (gen_lowpart (SImode
, t1
), elt
);
13280 t2
= gen_reg_rtx (V8QImode
);
13281 t2_low
= gen_lowpart (V4QImode
, t2
);
13282 emit_insn (gen_fpmerge_vis (t2
, t1
, t1
));
13284 t3
= gen_reg_rtx (V8QImode
);
13285 t3_low
= gen_lowpart (V4QImode
, t3
);
13286 emit_insn (gen_fpmerge_vis (t3
, t2_low
, t2_low
));
13288 emit_insn (gen_fpmerge_vis (target
, t3_low
, t3_low
));
13291 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
13292 all fields of TARGET to ELT in V4HI by means of VIS FALIGNDATA insn. */
13295 vector_init_faligndata (rtx target
, rtx elt
)
13297 rtx t1
= gen_reg_rtx (V4HImode
);
13300 elt
= convert_modes (SImode
, HImode
, elt
, true);
13301 emit_move_insn (gen_lowpart (SImode
, t1
), elt
);
13303 emit_insn (gen_alignaddrsi_vis (gen_reg_rtx (SImode
),
13304 force_reg (SImode
, GEN_INT (6)),
13307 for (i
= 0; i
< 4; i
++)
13308 emit_insn (gen_faligndatav4hi_vis (target
, t1
, target
));
13311 /* Emit code to initialize TARGET to values for individual fields VALS. */
13314 sparc_expand_vector_init (rtx target
, rtx vals
)
13316 const machine_mode mode
= GET_MODE (target
);
13317 const machine_mode inner_mode
= GET_MODE_INNER (mode
);
13318 const int n_elts
= GET_MODE_NUNITS (mode
);
13320 bool all_same
= true;
13323 for (i
= 0; i
< n_elts
; i
++)
13325 rtx x
= XVECEXP (vals
, 0, i
);
13326 if (!(CONST_SCALAR_INT_P (x
) || CONST_DOUBLE_P (x
) || CONST_FIXED_P (x
)))
13329 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
13335 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
13339 if (GET_MODE_SIZE (inner_mode
) == GET_MODE_SIZE (mode
))
13341 if (GET_MODE_SIZE (inner_mode
) == 4)
13343 emit_move_insn (gen_lowpart (SImode
, target
),
13344 gen_lowpart (SImode
, XVECEXP (vals
, 0, 0)));
13347 else if (GET_MODE_SIZE (inner_mode
) == 8)
13349 emit_move_insn (gen_lowpart (DImode
, target
),
13350 gen_lowpart (DImode
, XVECEXP (vals
, 0, 0)));
13354 else if (GET_MODE_SIZE (inner_mode
) == GET_MODE_SIZE (word_mode
)
13355 && GET_MODE_SIZE (mode
) == 2 * GET_MODE_SIZE (word_mode
))
13357 emit_move_insn (gen_highpart (word_mode
, target
),
13358 gen_lowpart (word_mode
, XVECEXP (vals
, 0, 0)));
13359 emit_move_insn (gen_lowpart (word_mode
, target
),
13360 gen_lowpart (word_mode
, XVECEXP (vals
, 0, 1)));
13364 if (all_same
&& GET_MODE_SIZE (mode
) == 8)
13368 vector_init_bshuffle (target
, XVECEXP (vals
, 0, 0), mode
, inner_mode
);
13371 if (mode
== V8QImode
)
13373 vector_init_fpmerge (target
, XVECEXP (vals
, 0, 0));
13376 if (mode
== V4HImode
)
13378 vector_init_faligndata (target
, XVECEXP (vals
, 0, 0));
13383 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
13384 for (i
= 0; i
< n_elts
; i
++)
13385 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
13386 i
* GET_MODE_SIZE (inner_mode
)),
13387 XVECEXP (vals
, 0, i
));
13388 emit_move_insn (target
, mem
);
13391 /* Implement TARGET_SECONDARY_RELOAD. */
13394 sparc_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
13395 machine_mode mode
, secondary_reload_info
*sri
)
13397 enum reg_class rclass
= (enum reg_class
) rclass_i
;
13399 sri
->icode
= CODE_FOR_nothing
;
13400 sri
->extra_cost
= 0;
13402 /* We need a temporary when loading/storing a HImode/QImode value
13403 between memory and the FPU registers. This can happen when combine puts
13404 a paradoxical subreg in a float/fix conversion insn. */
13405 if (FP_REG_CLASS_P (rclass
)
13406 && (mode
== HImode
|| mode
== QImode
)
13407 && (GET_CODE (x
) == MEM
13408 || ((GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
13409 && true_regnum (x
) == -1)))
13410 return GENERAL_REGS
;
13412 /* On 32-bit we need a temporary when loading/storing a DFmode value
13413 between unaligned memory and the upper FPU registers. */
13415 && rclass
== EXTRA_FP_REGS
13417 && GET_CODE (x
) == MEM
13418 && ! mem_min_alignment (x
, 8))
13421 if (((TARGET_CM_MEDANY
13422 && symbolic_operand (x
, mode
))
13423 || (TARGET_CM_EMBMEDANY
13424 && text_segment_operand (x
, mode
)))
13428 sri
->icode
= direct_optab_handler (reload_in_optab
, mode
);
13430 sri
->icode
= direct_optab_handler (reload_out_optab
, mode
);
13434 if (TARGET_VIS3
&& TARGET_ARCH32
)
13436 int regno
= true_regnum (x
);
13438 /* When using VIS3 fp<-->int register moves, on 32-bit we have
13439 to move 8-byte values in 4-byte pieces. This only works via
13440 FP_REGS, and not via EXTRA_FP_REGS. Therefore if we try to
13441 move between EXTRA_FP_REGS and GENERAL_REGS, we will need
13442 an FP_REGS intermediate move. */
13443 if ((rclass
== EXTRA_FP_REGS
&& SPARC_INT_REG_P (regno
))
13444 || ((general_or_i64_p (rclass
)
13445 || rclass
== GENERAL_OR_FP_REGS
)
13446 && SPARC_FP_REG_P (regno
)))
13448 sri
->extra_cost
= 2;
13456 /* Implement TARGET_SECONDARY_MEMORY_NEEDED.
13458 On SPARC when not VIS3 it is not possible to directly move data
13459 between GENERAL_REGS and FP_REGS. */
13462 sparc_secondary_memory_needed (machine_mode mode
, reg_class_t class1
,
13463 reg_class_t class2
)
13465 return ((FP_REG_CLASS_P (class1
) != FP_REG_CLASS_P (class2
))
13467 || GET_MODE_SIZE (mode
) > 8
13468 || GET_MODE_SIZE (mode
) < 4));
13471 /* Implement TARGET_SECONDARY_MEMORY_NEEDED_MODE.
13473 get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9
13474 because the movsi and movsf patterns don't handle r/f moves.
13475 For v8 we copy the default definition. */
13477 static machine_mode
13478 sparc_secondary_memory_needed_mode (machine_mode mode
)
13482 if (GET_MODE_BITSIZE (mode
) < 32)
13483 return mode_for_size (32, GET_MODE_CLASS (mode
), 0).require ();
13488 if (GET_MODE_BITSIZE (mode
) < BITS_PER_WORD
)
13489 return mode_for_size (BITS_PER_WORD
,
13490 GET_MODE_CLASS (mode
), 0).require ();
13495 /* Emit code to conditionally move either OPERANDS[2] or OPERANDS[3] into
13496 OPERANDS[0] in MODE. OPERANDS[1] is the operator of the condition. */
13499 sparc_expand_conditional_move (machine_mode mode
, rtx
*operands
)
13501 enum rtx_code rc
= GET_CODE (operands
[1]);
13502 machine_mode cmp_mode
;
13503 rtx cc_reg
, dst
, cmp
;
13506 if (GET_MODE (XEXP (cmp
, 0)) == DImode
&& !TARGET_ARCH64
)
13509 if (GET_MODE (XEXP (cmp
, 0)) == TFmode
&& !TARGET_HARD_QUAD
)
13510 cmp
= sparc_emit_float_lib_cmp (XEXP (cmp
, 0), XEXP (cmp
, 1), rc
);
13512 cmp_mode
= GET_MODE (XEXP (cmp
, 0));
13513 rc
= GET_CODE (cmp
);
13516 if (! rtx_equal_p (operands
[2], dst
)
13517 && ! rtx_equal_p (operands
[3], dst
))
13519 if (reg_overlap_mentioned_p (dst
, cmp
))
13520 dst
= gen_reg_rtx (mode
);
13522 emit_move_insn (dst
, operands
[3]);
13524 else if (operands
[2] == dst
)
13526 operands
[2] = operands
[3];
13528 if (GET_MODE_CLASS (cmp_mode
) == MODE_FLOAT
)
13529 rc
= reverse_condition_maybe_unordered (rc
);
13531 rc
= reverse_condition (rc
);
13534 if (XEXP (cmp
, 1) == const0_rtx
13535 && GET_CODE (XEXP (cmp
, 0)) == REG
13536 && cmp_mode
== DImode
13537 && v9_regcmp_p (rc
))
13538 cc_reg
= XEXP (cmp
, 0);
13540 cc_reg
= gen_compare_reg_1 (rc
, XEXP (cmp
, 0), XEXP (cmp
, 1));
13542 cmp
= gen_rtx_fmt_ee (rc
, GET_MODE (cc_reg
), cc_reg
, const0_rtx
);
13544 emit_insn (gen_rtx_SET (dst
,
13545 gen_rtx_IF_THEN_ELSE (mode
, cmp
, operands
[2], dst
)));
13547 if (dst
!= operands
[0])
13548 emit_move_insn (operands
[0], dst
);
13553 /* Emit code to conditionally move a combination of OPERANDS[1] and OPERANDS[2]
13554 into OPERANDS[0] in MODE, depending on the outcome of the comparison of
13555 OPERANDS[4] and OPERANDS[5]. OPERANDS[3] is the operator of the condition.
13556 FCODE is the machine code to be used for OPERANDS[3] and CCODE the machine
13557 code to be used for the condition mask. */
13560 sparc_expand_vcond (machine_mode mode
, rtx
*operands
, int ccode
, int fcode
)
13562 rtx mask
, cop0
, cop1
, fcmp
, cmask
, bshuf
, gsr
;
13563 enum rtx_code code
= GET_CODE (operands
[3]);
13565 mask
= gen_reg_rtx (Pmode
);
13566 cop0
= operands
[4];
13567 cop1
= operands
[5];
13568 if (code
== LT
|| code
== GE
)
13572 code
= swap_condition (code
);
13573 t
= cop0
; cop0
= cop1
; cop1
= t
;
13576 gsr
= gen_rtx_REG (DImode
, SPARC_GSR_REG
);
13578 fcmp
= gen_rtx_UNSPEC (Pmode
,
13579 gen_rtvec (1, gen_rtx_fmt_ee (code
, mode
, cop0
, cop1
)),
13582 cmask
= gen_rtx_UNSPEC (DImode
,
13583 gen_rtvec (2, mask
, gsr
),
13586 bshuf
= gen_rtx_UNSPEC (mode
,
13587 gen_rtvec (3, operands
[1], operands
[2], gsr
),
13590 emit_insn (gen_rtx_SET (mask
, fcmp
));
13591 emit_insn (gen_rtx_SET (gsr
, cmask
));
13593 emit_insn (gen_rtx_SET (operands
[0], bshuf
));
13596 /* On sparc, any mode which naturally allocates into the float
13597 registers should return 4 here. */
13600 sparc_regmode_natural_size (machine_mode mode
)
13602 int size
= UNITS_PER_WORD
;
13606 enum mode_class mclass
= GET_MODE_CLASS (mode
);
13608 if (mclass
== MODE_FLOAT
|| mclass
== MODE_VECTOR_INT
)
13615 /* Implement TARGET_HARD_REGNO_NREGS.
13617 On SPARC, ordinary registers hold 32 bits worth; this means both
13618 integer and floating point registers. On v9, integer regs hold 64
13619 bits worth; floating point regs hold 32 bits worth (this includes the
13620 new fp regs as even the odd ones are included in the hard register
13623 static unsigned int
13624 sparc_hard_regno_nregs (unsigned int regno
, machine_mode mode
)
13626 if (regno
== SPARC_GSR_REG
)
13630 if (SPARC_INT_REG_P (regno
) || regno
== FRAME_POINTER_REGNUM
)
13631 return CEIL (GET_MODE_SIZE (mode
), UNITS_PER_WORD
);
13632 return CEIL (GET_MODE_SIZE (mode
), 4);
13634 return CEIL (GET_MODE_SIZE (mode
), UNITS_PER_WORD
);
13637 /* Implement TARGET_HARD_REGNO_MODE_OK.
13639 ??? Because of the funny way we pass parameters we should allow certain
13640 ??? types of float/complex values to be in integer registers during
13641 ??? RTL generation. This only matters on arch32. */
13644 sparc_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
13646 return (hard_regno_mode_classes
[regno
] & sparc_mode_class
[mode
]) != 0;
13649 /* Implement TARGET_MODES_TIEABLE_P.
13651 For V9 we have to deal with the fact that only the lower 32 floating
13652 point registers are 32-bit addressable. */
13655 sparc_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
13657 enum mode_class mclass1
, mclass2
;
13658 unsigned short size1
, size2
;
13660 if (mode1
== mode2
)
13663 mclass1
= GET_MODE_CLASS (mode1
);
13664 mclass2
= GET_MODE_CLASS (mode2
);
13665 if (mclass1
!= mclass2
)
13671 /* Classes are the same and we are V9 so we have to deal with upper
13672 vs. lower floating point registers. If one of the modes is a
13673 4-byte mode, and the other is not, we have to mark them as not
13674 tieable because only the lower 32 floating point register are
13675 addressable 32-bits at a time.
13677 We can't just test explicitly for SFmode, otherwise we won't
13678 cover the vector mode cases properly. */
13680 if (mclass1
!= MODE_FLOAT
&& mclass1
!= MODE_VECTOR_INT
)
13683 size1
= GET_MODE_SIZE (mode1
);
13684 size2
= GET_MODE_SIZE (mode2
);
13685 if ((size1
> 4 && size2
== 4)
13686 || (size2
> 4 && size1
== 4))
13692 /* Implement TARGET_CSTORE_MODE. */
13694 static scalar_int_mode
13695 sparc_cstore_mode (enum insn_code icode ATTRIBUTE_UNUSED
)
13697 return (TARGET_ARCH64
? DImode
: SImode
);
13700 /* Return the compound expression made of T1 and T2. */
13703 compound_expr (tree t1
, tree t2
)
13705 return build2 (COMPOUND_EXPR
, void_type_node
, t1
, t2
);
13708 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
13711 sparc_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
13716 const unsigned HOST_WIDE_INT accrued_exception_mask
= 0x1f << 5;
13717 const unsigned HOST_WIDE_INT trap_enable_mask
= 0x1f << 23;
13719 /* We generate the equivalent of feholdexcept (&fenv_var):
13721 unsigned int fenv_var;
13722 __builtin_store_fsr (&fenv_var);
13724 unsigned int tmp1_var;
13725 tmp1_var = fenv_var & ~(accrued_exception_mask | trap_enable_mask);
13727 __builtin_load_fsr (&tmp1_var); */
13729 tree fenv_var
= create_tmp_var_raw (unsigned_type_node
);
13730 TREE_ADDRESSABLE (fenv_var
) = 1;
13731 tree fenv_addr
= build_fold_addr_expr (fenv_var
);
13732 tree stfsr
= sparc_builtins
[SPARC_BUILTIN_STFSR
];
13734 = build4 (TARGET_EXPR
, unsigned_type_node
, fenv_var
,
13735 build_call_expr (stfsr
, 1, fenv_addr
), NULL_TREE
, NULL_TREE
);
13737 tree tmp1_var
= create_tmp_var_raw (unsigned_type_node
);
13738 TREE_ADDRESSABLE (tmp1_var
) = 1;
13739 tree masked_fenv_var
13740 = build2 (BIT_AND_EXPR
, unsigned_type_node
, fenv_var
,
13741 build_int_cst (unsigned_type_node
,
13742 ~(accrued_exception_mask
| trap_enable_mask
)));
13744 = build4 (TARGET_EXPR
, unsigned_type_node
, tmp1_var
, masked_fenv_var
,
13745 NULL_TREE
, NULL_TREE
);
13747 tree tmp1_addr
= build_fold_addr_expr (tmp1_var
);
13748 tree ldfsr
= sparc_builtins
[SPARC_BUILTIN_LDFSR
];
13749 tree hold_ldfsr
= build_call_expr (ldfsr
, 1, tmp1_addr
);
13751 *hold
= compound_expr (compound_expr (hold_stfsr
, hold_mask
), hold_ldfsr
);
13753 /* We reload the value of tmp1_var to clear the exceptions:
13755 __builtin_load_fsr (&tmp1_var); */
13757 *clear
= build_call_expr (ldfsr
, 1, tmp1_addr
);
13759 /* We generate the equivalent of feupdateenv (&fenv_var):
13761 unsigned int tmp2_var;
13762 __builtin_store_fsr (&tmp2_var);
13764 __builtin_load_fsr (&fenv_var);
13766 if (SPARC_LOW_FE_EXCEPT_VALUES)
13768 __atomic_feraiseexcept ((int) tmp2_var); */
13770 tree tmp2_var
= create_tmp_var_raw (unsigned_type_node
);
13771 TREE_ADDRESSABLE (tmp2_var
) = 1;
13772 tree tmp2_addr
= build_fold_addr_expr (tmp2_var
);
13774 = build4 (TARGET_EXPR
, unsigned_type_node
, tmp2_var
,
13775 build_call_expr (stfsr
, 1, tmp2_addr
), NULL_TREE
, NULL_TREE
);
13777 tree update_ldfsr
= build_call_expr (ldfsr
, 1, fenv_addr
);
13779 tree atomic_feraiseexcept
13780 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT
);
13782 = build_call_expr (atomic_feraiseexcept
, 1,
13783 fold_convert (integer_type_node
, tmp2_var
));
13785 if (SPARC_LOW_FE_EXCEPT_VALUES
)
13787 tree shifted_tmp2_var
13788 = build2 (RSHIFT_EXPR
, unsigned_type_node
, tmp2_var
,
13789 build_int_cst (unsigned_type_node
, 5));
13791 = build2 (MODIFY_EXPR
, void_type_node
, tmp2_var
, shifted_tmp2_var
);
13792 update_call
= compound_expr (update_shift
, update_call
);
13796 = compound_expr (compound_expr (update_stfsr
, update_ldfsr
), update_call
);
13799 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. Borrowed from the PA port.
13801 SImode loads to floating-point registers are not zero-extended.
13802 The definition for LOAD_EXTEND_OP specifies that integer loads
13803 narrower than BITS_PER_WORD will be zero-extended. As a result,
13804 we inhibit changes from SImode unless they are to a mode that is
13807 Likewise for SFmode, since word-mode paradoxical subregs are
13808 problematic on big-endian architectures. */
13811 sparc_can_change_mode_class (machine_mode from
, machine_mode to
,
13812 reg_class_t rclass
)
13815 && GET_MODE_SIZE (from
) == 4
13816 && GET_MODE_SIZE (to
) != 4)
13817 return !reg_classes_intersect_p (rclass
, FP_REGS
);
13821 /* Implement TARGET_CONSTANT_ALIGNMENT. */
13823 static HOST_WIDE_INT
13824 sparc_constant_alignment (const_tree exp
, HOST_WIDE_INT align
)
13826 if (TREE_CODE (exp
) == STRING_CST
)
13827 return MAX (align
, FASTEST_ALIGNMENT
);
13831 #include "gt-sparc.h"