1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987-2017 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
4 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
34 #include "stringpool.h"
40 #include "diagnostic-core.h"
42 #include "fold-const.h"
43 #include "stor-layout.h"
47 #include "insn-attr.h"
51 #include "common/common-target.h"
53 #include "langhooks.h"
56 #include "tree-pass.h"
60 /* This file should be included last. */
61 #include "target-def.h"
65 struct processor_costs
{
69 /* Integer signed load */
72 /* Integer zeroed load */
78 /* fmov, fneg, fabs */
82 const int float_plusminus
;
88 const int float_cmove
;
94 const int float_div_sf
;
97 const int float_div_df
;
100 const int float_sqrt_sf
;
103 const int float_sqrt_df
;
111 /* integer multiply cost for each bit set past the most
112 significant 3, so the formula for multiply cost becomes:
115 highest_bit = highest_clear_bit(rs1);
117 highest_bit = highest_set_bit(rs1);
120 cost = int_mul{,X} + ((highest_bit - 3) / int_mul_bit_factor);
122 A value of zero indicates that the multiply costs is fixed,
124 const int int_mul_bit_factor
;
135 /* penalty for shifts, due to scheduling rules etc. */
136 const int shift_penalty
;
140 struct processor_costs cypress_costs
= {
141 COSTS_N_INSNS (2), /* int load */
142 COSTS_N_INSNS (2), /* int signed load */
143 COSTS_N_INSNS (2), /* int zeroed load */
144 COSTS_N_INSNS (2), /* float load */
145 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
146 COSTS_N_INSNS (5), /* fadd, fsub */
147 COSTS_N_INSNS (1), /* fcmp */
148 COSTS_N_INSNS (1), /* fmov, fmovr */
149 COSTS_N_INSNS (7), /* fmul */
150 COSTS_N_INSNS (37), /* fdivs */
151 COSTS_N_INSNS (37), /* fdivd */
152 COSTS_N_INSNS (63), /* fsqrts */
153 COSTS_N_INSNS (63), /* fsqrtd */
154 COSTS_N_INSNS (1), /* imul */
155 COSTS_N_INSNS (1), /* imulX */
156 0, /* imul bit factor */
157 COSTS_N_INSNS (1), /* idiv */
158 COSTS_N_INSNS (1), /* idivX */
159 COSTS_N_INSNS (1), /* movcc/movr */
160 0, /* shift penalty */
164 struct processor_costs supersparc_costs
= {
165 COSTS_N_INSNS (1), /* int load */
166 COSTS_N_INSNS (1), /* int signed load */
167 COSTS_N_INSNS (1), /* int zeroed load */
168 COSTS_N_INSNS (0), /* float load */
169 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
170 COSTS_N_INSNS (3), /* fadd, fsub */
171 COSTS_N_INSNS (3), /* fcmp */
172 COSTS_N_INSNS (1), /* fmov, fmovr */
173 COSTS_N_INSNS (3), /* fmul */
174 COSTS_N_INSNS (6), /* fdivs */
175 COSTS_N_INSNS (9), /* fdivd */
176 COSTS_N_INSNS (12), /* fsqrts */
177 COSTS_N_INSNS (12), /* fsqrtd */
178 COSTS_N_INSNS (4), /* imul */
179 COSTS_N_INSNS (4), /* imulX */
180 0, /* imul bit factor */
181 COSTS_N_INSNS (4), /* idiv */
182 COSTS_N_INSNS (4), /* idivX */
183 COSTS_N_INSNS (1), /* movcc/movr */
184 1, /* shift penalty */
188 struct processor_costs hypersparc_costs
= {
189 COSTS_N_INSNS (1), /* int load */
190 COSTS_N_INSNS (1), /* int signed load */
191 COSTS_N_INSNS (1), /* int zeroed load */
192 COSTS_N_INSNS (1), /* float load */
193 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
194 COSTS_N_INSNS (1), /* fadd, fsub */
195 COSTS_N_INSNS (1), /* fcmp */
196 COSTS_N_INSNS (1), /* fmov, fmovr */
197 COSTS_N_INSNS (1), /* fmul */
198 COSTS_N_INSNS (8), /* fdivs */
199 COSTS_N_INSNS (12), /* fdivd */
200 COSTS_N_INSNS (17), /* fsqrts */
201 COSTS_N_INSNS (17), /* fsqrtd */
202 COSTS_N_INSNS (17), /* imul */
203 COSTS_N_INSNS (17), /* imulX */
204 0, /* imul bit factor */
205 COSTS_N_INSNS (17), /* idiv */
206 COSTS_N_INSNS (17), /* idivX */
207 COSTS_N_INSNS (1), /* movcc/movr */
208 0, /* shift penalty */
212 struct processor_costs leon_costs
= {
213 COSTS_N_INSNS (1), /* int load */
214 COSTS_N_INSNS (1), /* int signed load */
215 COSTS_N_INSNS (1), /* int zeroed load */
216 COSTS_N_INSNS (1), /* float load */
217 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
218 COSTS_N_INSNS (1), /* fadd, fsub */
219 COSTS_N_INSNS (1), /* fcmp */
220 COSTS_N_INSNS (1), /* fmov, fmovr */
221 COSTS_N_INSNS (1), /* fmul */
222 COSTS_N_INSNS (15), /* fdivs */
223 COSTS_N_INSNS (15), /* fdivd */
224 COSTS_N_INSNS (23), /* fsqrts */
225 COSTS_N_INSNS (23), /* fsqrtd */
226 COSTS_N_INSNS (5), /* imul */
227 COSTS_N_INSNS (5), /* imulX */
228 0, /* imul bit factor */
229 COSTS_N_INSNS (5), /* idiv */
230 COSTS_N_INSNS (5), /* idivX */
231 COSTS_N_INSNS (1), /* movcc/movr */
232 0, /* shift penalty */
236 struct processor_costs leon3_costs
= {
237 COSTS_N_INSNS (1), /* int load */
238 COSTS_N_INSNS (1), /* int signed load */
239 COSTS_N_INSNS (1), /* int zeroed load */
240 COSTS_N_INSNS (1), /* float load */
241 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
242 COSTS_N_INSNS (1), /* fadd, fsub */
243 COSTS_N_INSNS (1), /* fcmp */
244 COSTS_N_INSNS (1), /* fmov, fmovr */
245 COSTS_N_INSNS (1), /* fmul */
246 COSTS_N_INSNS (14), /* fdivs */
247 COSTS_N_INSNS (15), /* fdivd */
248 COSTS_N_INSNS (22), /* fsqrts */
249 COSTS_N_INSNS (23), /* fsqrtd */
250 COSTS_N_INSNS (5), /* imul */
251 COSTS_N_INSNS (5), /* imulX */
252 0, /* imul bit factor */
253 COSTS_N_INSNS (35), /* idiv */
254 COSTS_N_INSNS (35), /* idivX */
255 COSTS_N_INSNS (1), /* movcc/movr */
256 0, /* shift penalty */
260 struct processor_costs sparclet_costs
= {
261 COSTS_N_INSNS (3), /* int load */
262 COSTS_N_INSNS (3), /* int signed load */
263 COSTS_N_INSNS (1), /* int zeroed load */
264 COSTS_N_INSNS (1), /* float load */
265 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
266 COSTS_N_INSNS (1), /* fadd, fsub */
267 COSTS_N_INSNS (1), /* fcmp */
268 COSTS_N_INSNS (1), /* fmov, fmovr */
269 COSTS_N_INSNS (1), /* fmul */
270 COSTS_N_INSNS (1), /* fdivs */
271 COSTS_N_INSNS (1), /* fdivd */
272 COSTS_N_INSNS (1), /* fsqrts */
273 COSTS_N_INSNS (1), /* fsqrtd */
274 COSTS_N_INSNS (5), /* imul */
275 COSTS_N_INSNS (5), /* imulX */
276 0, /* imul bit factor */
277 COSTS_N_INSNS (5), /* idiv */
278 COSTS_N_INSNS (5), /* idivX */
279 COSTS_N_INSNS (1), /* movcc/movr */
280 0, /* shift penalty */
284 struct processor_costs ultrasparc_costs
= {
285 COSTS_N_INSNS (2), /* int load */
286 COSTS_N_INSNS (3), /* int signed load */
287 COSTS_N_INSNS (2), /* int zeroed load */
288 COSTS_N_INSNS (2), /* float load */
289 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
290 COSTS_N_INSNS (4), /* fadd, fsub */
291 COSTS_N_INSNS (1), /* fcmp */
292 COSTS_N_INSNS (2), /* fmov, fmovr */
293 COSTS_N_INSNS (4), /* fmul */
294 COSTS_N_INSNS (13), /* fdivs */
295 COSTS_N_INSNS (23), /* fdivd */
296 COSTS_N_INSNS (13), /* fsqrts */
297 COSTS_N_INSNS (23), /* fsqrtd */
298 COSTS_N_INSNS (4), /* imul */
299 COSTS_N_INSNS (4), /* imulX */
300 2, /* imul bit factor */
301 COSTS_N_INSNS (37), /* idiv */
302 COSTS_N_INSNS (68), /* idivX */
303 COSTS_N_INSNS (2), /* movcc/movr */
304 2, /* shift penalty */
308 struct processor_costs ultrasparc3_costs
= {
309 COSTS_N_INSNS (2), /* int load */
310 COSTS_N_INSNS (3), /* int signed load */
311 COSTS_N_INSNS (3), /* int zeroed load */
312 COSTS_N_INSNS (2), /* float load */
313 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
314 COSTS_N_INSNS (4), /* fadd, fsub */
315 COSTS_N_INSNS (5), /* fcmp */
316 COSTS_N_INSNS (3), /* fmov, fmovr */
317 COSTS_N_INSNS (4), /* fmul */
318 COSTS_N_INSNS (17), /* fdivs */
319 COSTS_N_INSNS (20), /* fdivd */
320 COSTS_N_INSNS (20), /* fsqrts */
321 COSTS_N_INSNS (29), /* fsqrtd */
322 COSTS_N_INSNS (6), /* imul */
323 COSTS_N_INSNS (6), /* imulX */
324 0, /* imul bit factor */
325 COSTS_N_INSNS (40), /* idiv */
326 COSTS_N_INSNS (71), /* idivX */
327 COSTS_N_INSNS (2), /* movcc/movr */
328 0, /* shift penalty */
332 struct processor_costs niagara_costs
= {
333 COSTS_N_INSNS (3), /* int load */
334 COSTS_N_INSNS (3), /* int signed load */
335 COSTS_N_INSNS (3), /* int zeroed load */
336 COSTS_N_INSNS (9), /* float load */
337 COSTS_N_INSNS (8), /* fmov, fneg, fabs */
338 COSTS_N_INSNS (8), /* fadd, fsub */
339 COSTS_N_INSNS (26), /* fcmp */
340 COSTS_N_INSNS (8), /* fmov, fmovr */
341 COSTS_N_INSNS (29), /* fmul */
342 COSTS_N_INSNS (54), /* fdivs */
343 COSTS_N_INSNS (83), /* fdivd */
344 COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */
345 COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */
346 COSTS_N_INSNS (11), /* imul */
347 COSTS_N_INSNS (11), /* imulX */
348 0, /* imul bit factor */
349 COSTS_N_INSNS (72), /* idiv */
350 COSTS_N_INSNS (72), /* idivX */
351 COSTS_N_INSNS (1), /* movcc/movr */
352 0, /* shift penalty */
356 struct processor_costs niagara2_costs
= {
357 COSTS_N_INSNS (3), /* int load */
358 COSTS_N_INSNS (3), /* int signed load */
359 COSTS_N_INSNS (3), /* int zeroed load */
360 COSTS_N_INSNS (3), /* float load */
361 COSTS_N_INSNS (6), /* fmov, fneg, fabs */
362 COSTS_N_INSNS (6), /* fadd, fsub */
363 COSTS_N_INSNS (6), /* fcmp */
364 COSTS_N_INSNS (6), /* fmov, fmovr */
365 COSTS_N_INSNS (6), /* fmul */
366 COSTS_N_INSNS (19), /* fdivs */
367 COSTS_N_INSNS (33), /* fdivd */
368 COSTS_N_INSNS (19), /* fsqrts */
369 COSTS_N_INSNS (33), /* fsqrtd */
370 COSTS_N_INSNS (5), /* imul */
371 COSTS_N_INSNS (5), /* imulX */
372 0, /* imul bit factor */
373 COSTS_N_INSNS (26), /* idiv, average of 12 - 41 cycle range */
374 COSTS_N_INSNS (26), /* idivX, average of 12 - 41 cycle range */
375 COSTS_N_INSNS (1), /* movcc/movr */
376 0, /* shift penalty */
380 struct processor_costs niagara3_costs
= {
381 COSTS_N_INSNS (3), /* int load */
382 COSTS_N_INSNS (3), /* int signed load */
383 COSTS_N_INSNS (3), /* int zeroed load */
384 COSTS_N_INSNS (3), /* float load */
385 COSTS_N_INSNS (9), /* fmov, fneg, fabs */
386 COSTS_N_INSNS (9), /* fadd, fsub */
387 COSTS_N_INSNS (9), /* fcmp */
388 COSTS_N_INSNS (9), /* fmov, fmovr */
389 COSTS_N_INSNS (9), /* fmul */
390 COSTS_N_INSNS (23), /* fdivs */
391 COSTS_N_INSNS (37), /* fdivd */
392 COSTS_N_INSNS (23), /* fsqrts */
393 COSTS_N_INSNS (37), /* fsqrtd */
394 COSTS_N_INSNS (9), /* imul */
395 COSTS_N_INSNS (9), /* imulX */
396 0, /* imul bit factor */
397 COSTS_N_INSNS (31), /* idiv, average of 17 - 45 cycle range */
398 COSTS_N_INSNS (30), /* idivX, average of 16 - 44 cycle range */
399 COSTS_N_INSNS (1), /* movcc/movr */
400 0, /* shift penalty */
404 struct processor_costs niagara4_costs
= {
405 COSTS_N_INSNS (5), /* int load */
406 COSTS_N_INSNS (5), /* int signed load */
407 COSTS_N_INSNS (5), /* int zeroed load */
408 COSTS_N_INSNS (5), /* float load */
409 COSTS_N_INSNS (11), /* fmov, fneg, fabs */
410 COSTS_N_INSNS (11), /* fadd, fsub */
411 COSTS_N_INSNS (11), /* fcmp */
412 COSTS_N_INSNS (11), /* fmov, fmovr */
413 COSTS_N_INSNS (11), /* fmul */
414 COSTS_N_INSNS (24), /* fdivs */
415 COSTS_N_INSNS (37), /* fdivd */
416 COSTS_N_INSNS (24), /* fsqrts */
417 COSTS_N_INSNS (37), /* fsqrtd */
418 COSTS_N_INSNS (12), /* imul */
419 COSTS_N_INSNS (12), /* imulX */
420 0, /* imul bit factor */
421 COSTS_N_INSNS (50), /* idiv, average of 41 - 60 cycle range */
422 COSTS_N_INSNS (35), /* idivX, average of 26 - 44 cycle range */
423 COSTS_N_INSNS (1), /* movcc/movr */
424 0, /* shift penalty */
428 struct processor_costs niagara7_costs
= {
429 COSTS_N_INSNS (5), /* int load */
430 COSTS_N_INSNS (5), /* int signed load */
431 COSTS_N_INSNS (5), /* int zeroed load */
432 COSTS_N_INSNS (5), /* float load */
433 COSTS_N_INSNS (11), /* fmov, fneg, fabs */
434 COSTS_N_INSNS (11), /* fadd, fsub */
435 COSTS_N_INSNS (11), /* fcmp */
436 COSTS_N_INSNS (11), /* fmov, fmovr */
437 COSTS_N_INSNS (11), /* fmul */
438 COSTS_N_INSNS (24), /* fdivs */
439 COSTS_N_INSNS (37), /* fdivd */
440 COSTS_N_INSNS (24), /* fsqrts */
441 COSTS_N_INSNS (37), /* fsqrtd */
442 COSTS_N_INSNS (12), /* imul */
443 COSTS_N_INSNS (12), /* imulX */
444 0, /* imul bit factor */
445 COSTS_N_INSNS (51), /* idiv, average of 42 - 61 cycle range */
446 COSTS_N_INSNS (35), /* idivX, average of 26 - 44 cycle range */
447 COSTS_N_INSNS (1), /* movcc/movr */
448 0, /* shift penalty */
452 struct processor_costs m8_costs
= {
453 COSTS_N_INSNS (3), /* int load */
454 COSTS_N_INSNS (3), /* int signed load */
455 COSTS_N_INSNS (3), /* int zeroed load */
456 COSTS_N_INSNS (3), /* float load */
457 COSTS_N_INSNS (9), /* fmov, fneg, fabs */
458 COSTS_N_INSNS (9), /* fadd, fsub */
459 COSTS_N_INSNS (9), /* fcmp */
460 COSTS_N_INSNS (9), /* fmov, fmovr */
461 COSTS_N_INSNS (9), /* fmul */
462 COSTS_N_INSNS (26), /* fdivs */
463 COSTS_N_INSNS (30), /* fdivd */
464 COSTS_N_INSNS (33), /* fsqrts */
465 COSTS_N_INSNS (41), /* fsqrtd */
466 COSTS_N_INSNS (12), /* imul */
467 COSTS_N_INSNS (10), /* imulX */
468 0, /* imul bit factor */
469 COSTS_N_INSNS (57), /* udiv/sdiv */
470 COSTS_N_INSNS (30), /* udivx/sdivx */
471 COSTS_N_INSNS (1), /* movcc/movr */
472 0, /* shift penalty */
475 static const struct processor_costs
*sparc_costs
= &cypress_costs
;
477 #ifdef HAVE_AS_RELAX_OPTION
478 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
479 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
480 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
481 somebody does not branch between the sethi and jmp. */
482 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
484 #define LEAF_SIBCALL_SLOT_RESERVED_P \
485 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
488 /* Vector to say how input registers are mapped to output registers.
489 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
490 eliminate it. You must use -fomit-frame-pointer to get that. */
491 char leaf_reg_remap
[] =
492 { 0, 1, 2, 3, 4, 5, 6, 7,
493 -1, -1, -1, -1, -1, -1, 14, -1,
494 -1, -1, -1, -1, -1, -1, -1, -1,
495 8, 9, 10, 11, 12, 13, -1, 15,
497 32, 33, 34, 35, 36, 37, 38, 39,
498 40, 41, 42, 43, 44, 45, 46, 47,
499 48, 49, 50, 51, 52, 53, 54, 55,
500 56, 57, 58, 59, 60, 61, 62, 63,
501 64, 65, 66, 67, 68, 69, 70, 71,
502 72, 73, 74, 75, 76, 77, 78, 79,
503 80, 81, 82, 83, 84, 85, 86, 87,
504 88, 89, 90, 91, 92, 93, 94, 95,
505 96, 97, 98, 99, 100, 101, 102};
507 /* Vector, indexed by hard register number, which contains 1
508 for a register that is allowable in a candidate for leaf
509 function treatment. */
510 char sparc_leaf_regs
[] =
511 { 1, 1, 1, 1, 1, 1, 1, 1,
512 0, 0, 0, 0, 0, 0, 1, 0,
513 0, 0, 0, 0, 0, 0, 0, 0,
514 1, 1, 1, 1, 1, 1, 0, 1,
515 1, 1, 1, 1, 1, 1, 1, 1,
516 1, 1, 1, 1, 1, 1, 1, 1,
517 1, 1, 1, 1, 1, 1, 1, 1,
518 1, 1, 1, 1, 1, 1, 1, 1,
519 1, 1, 1, 1, 1, 1, 1, 1,
520 1, 1, 1, 1, 1, 1, 1, 1,
521 1, 1, 1, 1, 1, 1, 1, 1,
522 1, 1, 1, 1, 1, 1, 1, 1,
523 1, 1, 1, 1, 1, 1, 1};
525 struct GTY(()) machine_function
527 /* Size of the frame of the function. */
528 HOST_WIDE_INT frame_size
;
530 /* Size of the frame of the function minus the register window save area
531 and the outgoing argument area. */
532 HOST_WIDE_INT apparent_frame_size
;
534 /* Register we pretend the frame pointer is allocated to. Normally, this
535 is %fp, but if we are in a leaf procedure, this is (%sp + offset). We
536 record "offset" separately as it may be too big for (reg + disp). */
538 HOST_WIDE_INT frame_base_offset
;
540 /* Number of global or FP registers to be saved (as 4-byte quantities). */
541 int n_global_fp_regs
;
543 /* True if the current function is leaf and uses only leaf regs,
544 so that the SPARC leaf function optimization can be applied.
545 Private version of crtl->uses_only_leaf_regs, see
546 sparc_expand_prologue for the rationale. */
549 /* True if the prologue saves local or in registers. */
550 bool save_local_in_regs_p
;
552 /* True if the data calculated by sparc_expand_prologue are valid. */
553 bool prologue_data_valid_p
;
556 #define sparc_frame_size cfun->machine->frame_size
557 #define sparc_apparent_frame_size cfun->machine->apparent_frame_size
558 #define sparc_frame_base_reg cfun->machine->frame_base_reg
559 #define sparc_frame_base_offset cfun->machine->frame_base_offset
560 #define sparc_n_global_fp_regs cfun->machine->n_global_fp_regs
561 #define sparc_leaf_function_p cfun->machine->leaf_function_p
562 #define sparc_save_local_in_regs_p cfun->machine->save_local_in_regs_p
563 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
565 /* 1 if the next opcode is to be specially indented. */
566 int sparc_indent_opcode
= 0;
568 static void sparc_option_override (void);
569 static void sparc_init_modes (void);
570 static int function_arg_slotno (const CUMULATIVE_ARGS
*, machine_mode
,
571 const_tree
, bool, bool, int *, int *);
573 static int supersparc_adjust_cost (rtx_insn
*, int, rtx_insn
*, int);
574 static int hypersparc_adjust_cost (rtx_insn
*, int, rtx_insn
*, int);
576 static void sparc_emit_set_const32 (rtx
, rtx
);
577 static void sparc_emit_set_const64 (rtx
, rtx
);
578 static void sparc_output_addr_vec (rtx
);
579 static void sparc_output_addr_diff_vec (rtx
);
580 static void sparc_output_deferred_case_vectors (void);
581 static bool sparc_legitimate_address_p (machine_mode
, rtx
, bool);
582 static bool sparc_legitimate_constant_p (machine_mode
, rtx
);
583 static rtx
sparc_builtin_saveregs (void);
584 static int epilogue_renumber (rtx
*, int);
585 static bool sparc_assemble_integer (rtx
, unsigned int, int);
586 static int set_extends (rtx_insn
*);
587 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT
);
588 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT
);
589 #ifdef TARGET_SOLARIS
590 static void sparc_solaris_elf_asm_named_section (const char *, unsigned int,
591 tree
) ATTRIBUTE_UNUSED
;
593 static int sparc_adjust_cost (rtx_insn
*, int, rtx_insn
*, int, unsigned int);
594 static int sparc_issue_rate (void);
595 static void sparc_sched_init (FILE *, int, int);
596 static int sparc_use_sched_lookahead (void);
598 static void emit_soft_tfmode_libcall (const char *, int, rtx
*);
599 static void emit_soft_tfmode_binop (enum rtx_code
, rtx
*);
600 static void emit_soft_tfmode_unop (enum rtx_code
, rtx
*);
601 static void emit_soft_tfmode_cvt (enum rtx_code
, rtx
*);
602 static void emit_hard_tfmode_operation (enum rtx_code
, rtx
*);
604 static bool sparc_function_ok_for_sibcall (tree
, tree
);
605 static void sparc_init_libfuncs (void);
606 static void sparc_init_builtins (void);
607 static void sparc_fpu_init_builtins (void);
608 static void sparc_vis_init_builtins (void);
609 static tree
sparc_builtin_decl (unsigned, bool);
610 static rtx
sparc_expand_builtin (tree
, rtx
, rtx
, machine_mode
, int);
611 static tree
sparc_fold_builtin (tree
, int, tree
*, bool);
612 static void sparc_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
613 HOST_WIDE_INT
, tree
);
614 static bool sparc_can_output_mi_thunk (const_tree
, HOST_WIDE_INT
,
615 HOST_WIDE_INT
, const_tree
);
616 static struct machine_function
* sparc_init_machine_status (void);
617 static bool sparc_cannot_force_const_mem (machine_mode
, rtx
);
618 static rtx
sparc_tls_get_addr (void);
619 static rtx
sparc_tls_got (void);
620 static int sparc_register_move_cost (machine_mode
,
621 reg_class_t
, reg_class_t
);
622 static bool sparc_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
623 static rtx
sparc_function_value (const_tree
, const_tree
, bool);
624 static rtx
sparc_libcall_value (machine_mode
, const_rtx
);
625 static bool sparc_function_value_regno_p (const unsigned int);
626 static rtx
sparc_struct_value_rtx (tree
, int);
627 static machine_mode
sparc_promote_function_mode (const_tree
, machine_mode
,
628 int *, const_tree
, int);
629 static bool sparc_return_in_memory (const_tree
, const_tree
);
630 static bool sparc_strict_argument_naming (cumulative_args_t
);
631 static void sparc_va_start (tree
, rtx
);
632 static tree
sparc_gimplify_va_arg (tree
, tree
, gimple_seq
*, gimple_seq
*);
633 static bool sparc_vector_mode_supported_p (machine_mode
);
634 static bool sparc_tls_referenced_p (rtx
);
635 static rtx
sparc_legitimize_tls_address (rtx
);
636 static rtx
sparc_legitimize_pic_address (rtx
, rtx
);
637 static rtx
sparc_legitimize_address (rtx
, rtx
, machine_mode
);
638 static rtx
sparc_delegitimize_address (rtx
);
639 static bool sparc_mode_dependent_address_p (const_rtx
, addr_space_t
);
640 static bool sparc_pass_by_reference (cumulative_args_t
,
641 machine_mode
, const_tree
, bool);
642 static void sparc_function_arg_advance (cumulative_args_t
,
643 machine_mode
, const_tree
, bool);
644 static rtx
sparc_function_arg_1 (cumulative_args_t
,
645 machine_mode
, const_tree
, bool, bool);
646 static rtx
sparc_function_arg (cumulative_args_t
,
647 machine_mode
, const_tree
, bool);
648 static rtx
sparc_function_incoming_arg (cumulative_args_t
,
649 machine_mode
, const_tree
, bool);
650 static unsigned int sparc_function_arg_boundary (machine_mode
,
652 static int sparc_arg_partial_bytes (cumulative_args_t
,
653 machine_mode
, tree
, bool);
654 static void sparc_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
655 static void sparc_file_end (void);
656 static bool sparc_frame_pointer_required (void);
657 static bool sparc_can_eliminate (const int, const int);
658 static rtx
sparc_builtin_setjmp_frame_value (void);
659 static void sparc_conditional_register_usage (void);
660 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
661 static const char *sparc_mangle_type (const_tree
);
663 static void sparc_trampoline_init (rtx
, tree
, rtx
);
664 static machine_mode
sparc_preferred_simd_mode (machine_mode
);
665 static reg_class_t
sparc_preferred_reload_class (rtx x
, reg_class_t rclass
);
666 static bool sparc_lra_p (void);
667 static bool sparc_print_operand_punct_valid_p (unsigned char);
668 static void sparc_print_operand (FILE *, rtx
, int);
669 static void sparc_print_operand_address (FILE *, machine_mode
, rtx
);
670 static reg_class_t
sparc_secondary_reload (bool, rtx
, reg_class_t
,
672 secondary_reload_info
*);
673 static machine_mode
sparc_cstore_mode (enum insn_code icode
);
674 static void sparc_atomic_assign_expand_fenv (tree
*, tree
*, tree
*);
675 static bool sparc_fixed_condition_code_regs (unsigned int *, unsigned int *);
676 static unsigned int sparc_min_arithmetic_precision (void);
678 #ifdef SUBTARGET_ATTRIBUTE_TABLE
679 /* Table of valid machine attributes. */
680 static const struct attribute_spec sparc_attribute_table
[] =
682 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
684 SUBTARGET_ATTRIBUTE_TABLE
,
685 { NULL
, 0, 0, false, false, false, NULL
, false }
689 /* Option handling. */
692 enum cmodel sparc_cmodel
;
694 char sparc_hard_reg_printed
[8];
696 /* Initialize the GCC target structure. */
698 /* The default is to use .half rather than .short for aligned HI objects. */
699 #undef TARGET_ASM_ALIGNED_HI_OP
700 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
702 #undef TARGET_ASM_UNALIGNED_HI_OP
703 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
704 #undef TARGET_ASM_UNALIGNED_SI_OP
705 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
706 #undef TARGET_ASM_UNALIGNED_DI_OP
707 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
709 /* The target hook has to handle DI-mode values. */
710 #undef TARGET_ASM_INTEGER
711 #define TARGET_ASM_INTEGER sparc_assemble_integer
713 #undef TARGET_ASM_FUNCTION_PROLOGUE
714 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
715 #undef TARGET_ASM_FUNCTION_EPILOGUE
716 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
718 #undef TARGET_SCHED_ADJUST_COST
719 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
720 #undef TARGET_SCHED_ISSUE_RATE
721 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
722 #undef TARGET_SCHED_INIT
723 #define TARGET_SCHED_INIT sparc_sched_init
724 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
725 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
727 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
728 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
730 #undef TARGET_INIT_LIBFUNCS
731 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
733 #undef TARGET_LEGITIMIZE_ADDRESS
734 #define TARGET_LEGITIMIZE_ADDRESS sparc_legitimize_address
735 #undef TARGET_DELEGITIMIZE_ADDRESS
736 #define TARGET_DELEGITIMIZE_ADDRESS sparc_delegitimize_address
737 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
738 #define TARGET_MODE_DEPENDENT_ADDRESS_P sparc_mode_dependent_address_p
740 #undef TARGET_INIT_BUILTINS
741 #define TARGET_INIT_BUILTINS sparc_init_builtins
742 #undef TARGET_BUILTIN_DECL
743 #define TARGET_BUILTIN_DECL sparc_builtin_decl
744 #undef TARGET_EXPAND_BUILTIN
745 #define TARGET_EXPAND_BUILTIN sparc_expand_builtin
746 #undef TARGET_FOLD_BUILTIN
747 #define TARGET_FOLD_BUILTIN sparc_fold_builtin
750 #undef TARGET_HAVE_TLS
751 #define TARGET_HAVE_TLS true
754 #undef TARGET_CANNOT_FORCE_CONST_MEM
755 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
757 #undef TARGET_ASM_OUTPUT_MI_THUNK
758 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
759 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
760 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
762 #undef TARGET_RTX_COSTS
763 #define TARGET_RTX_COSTS sparc_rtx_costs
764 #undef TARGET_ADDRESS_COST
765 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
766 #undef TARGET_REGISTER_MOVE_COST
767 #define TARGET_REGISTER_MOVE_COST sparc_register_move_cost
769 #undef TARGET_PROMOTE_FUNCTION_MODE
770 #define TARGET_PROMOTE_FUNCTION_MODE sparc_promote_function_mode
772 #undef TARGET_FUNCTION_VALUE
773 #define TARGET_FUNCTION_VALUE sparc_function_value
774 #undef TARGET_LIBCALL_VALUE
775 #define TARGET_LIBCALL_VALUE sparc_libcall_value
776 #undef TARGET_FUNCTION_VALUE_REGNO_P
777 #define TARGET_FUNCTION_VALUE_REGNO_P sparc_function_value_regno_p
779 #undef TARGET_STRUCT_VALUE_RTX
780 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
781 #undef TARGET_RETURN_IN_MEMORY
782 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
783 #undef TARGET_MUST_PASS_IN_STACK
784 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
785 #undef TARGET_PASS_BY_REFERENCE
786 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
787 #undef TARGET_ARG_PARTIAL_BYTES
788 #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
789 #undef TARGET_FUNCTION_ARG_ADVANCE
790 #define TARGET_FUNCTION_ARG_ADVANCE sparc_function_arg_advance
791 #undef TARGET_FUNCTION_ARG
792 #define TARGET_FUNCTION_ARG sparc_function_arg
793 #undef TARGET_FUNCTION_INCOMING_ARG
794 #define TARGET_FUNCTION_INCOMING_ARG sparc_function_incoming_arg
795 #undef TARGET_FUNCTION_ARG_BOUNDARY
796 #define TARGET_FUNCTION_ARG_BOUNDARY sparc_function_arg_boundary
798 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
799 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
800 #undef TARGET_STRICT_ARGUMENT_NAMING
801 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
803 #undef TARGET_EXPAND_BUILTIN_VA_START
804 #define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start
805 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
806 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
808 #undef TARGET_VECTOR_MODE_SUPPORTED_P
809 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
811 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
812 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE sparc_preferred_simd_mode
814 #ifdef SUBTARGET_INSERT_ATTRIBUTES
815 #undef TARGET_INSERT_ATTRIBUTES
816 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
819 #ifdef SUBTARGET_ATTRIBUTE_TABLE
820 #undef TARGET_ATTRIBUTE_TABLE
821 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
824 #undef TARGET_OPTION_OVERRIDE
825 #define TARGET_OPTION_OVERRIDE sparc_option_override
827 #ifdef TARGET_THREAD_SSP_OFFSET
828 #undef TARGET_STACK_PROTECT_GUARD
829 #define TARGET_STACK_PROTECT_GUARD hook_tree_void_null
832 #if TARGET_GNU_TLS && defined(HAVE_AS_SPARC_UA_PCREL)
833 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
834 #define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel
837 #undef TARGET_ASM_FILE_END
838 #define TARGET_ASM_FILE_END sparc_file_end
840 #undef TARGET_FRAME_POINTER_REQUIRED
841 #define TARGET_FRAME_POINTER_REQUIRED sparc_frame_pointer_required
843 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
844 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE sparc_builtin_setjmp_frame_value
846 #undef TARGET_CAN_ELIMINATE
847 #define TARGET_CAN_ELIMINATE sparc_can_eliminate
849 #undef TARGET_PREFERRED_RELOAD_CLASS
850 #define TARGET_PREFERRED_RELOAD_CLASS sparc_preferred_reload_class
852 #undef TARGET_SECONDARY_RELOAD
853 #define TARGET_SECONDARY_RELOAD sparc_secondary_reload
855 #undef TARGET_CONDITIONAL_REGISTER_USAGE
856 #define TARGET_CONDITIONAL_REGISTER_USAGE sparc_conditional_register_usage
858 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
859 #undef TARGET_MANGLE_TYPE
860 #define TARGET_MANGLE_TYPE sparc_mangle_type
864 #define TARGET_LRA_P sparc_lra_p
866 #undef TARGET_LEGITIMATE_ADDRESS_P
867 #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p
869 #undef TARGET_LEGITIMATE_CONSTANT_P
870 #define TARGET_LEGITIMATE_CONSTANT_P sparc_legitimate_constant_p
872 #undef TARGET_TRAMPOLINE_INIT
873 #define TARGET_TRAMPOLINE_INIT sparc_trampoline_init
875 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
876 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sparc_print_operand_punct_valid_p
877 #undef TARGET_PRINT_OPERAND
878 #define TARGET_PRINT_OPERAND sparc_print_operand
879 #undef TARGET_PRINT_OPERAND_ADDRESS
880 #define TARGET_PRINT_OPERAND_ADDRESS sparc_print_operand_address
882 /* The value stored by LDSTUB. */
883 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
884 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 0xff
886 #undef TARGET_CSTORE_MODE
887 #define TARGET_CSTORE_MODE sparc_cstore_mode
889 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
890 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV sparc_atomic_assign_expand_fenv
892 #undef TARGET_FIXED_CONDITION_CODE_REGS
893 #define TARGET_FIXED_CONDITION_CODE_REGS sparc_fixed_condition_code_regs
895 #undef TARGET_MIN_ARITHMETIC_PRECISION
896 #define TARGET_MIN_ARITHMETIC_PRECISION sparc_min_arithmetic_precision
898 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
899 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
901 struct gcc_target targetm
= TARGET_INITIALIZER
;
903 /* Return the memory reference contained in X if any, zero otherwise. */
908 if (GET_CODE (x
) == SIGN_EXTEND
|| GET_CODE (x
) == ZERO_EXTEND
)
917 /* We use a machine specific pass to enable workarounds for errata.
919 We need to have the (essentially) final form of the insn stream in order
920 to properly detect the various hazards. Therefore, this machine specific
921 pass runs as late as possible. */
923 /* True if INSN is a md pattern or asm statement. */
924 #define USEFUL_INSN_P(INSN) \
925 (NONDEBUG_INSN_P (INSN) \
926 && GET_CODE (PATTERN (INSN)) != USE \
927 && GET_CODE (PATTERN (INSN)) != CLOBBER)
930 sparc_do_work_around_errata (void)
932 rtx_insn
*insn
, *next
;
934 /* Force all instructions to be split into their final form. */
935 split_all_insns_noflow ();
937 /* Now look for specific patterns in the insn stream. */
938 for (insn
= get_insns (); insn
; insn
= next
)
940 bool insert_nop
= false;
943 /* Look into the instruction in a delay slot. */
944 if (NONJUMP_INSN_P (insn
))
945 if (rtx_sequence
*seq
= dyn_cast
<rtx_sequence
*> (PATTERN (insn
)))
946 insn
= seq
->insn (1);
948 /* Look for either of these two sequences:
951 1. store of word size or less (e.g. st / stb / sth / stf)
952 2. any single instruction that is not a load or store
953 3. any store instruction (e.g. st / stb / sth / stf / std / stdf)
956 1. store of double word size (e.g. std / stdf)
957 2. any store instruction (e.g. st / stb / sth / stf / std / stdf) */
959 && NONJUMP_INSN_P (insn
)
960 && (set
= single_set (insn
)) != NULL_RTX
961 && MEM_P (SET_DEST (set
)))
963 /* Sequence B begins with a double-word store. */
964 bool seq_b
= GET_MODE_SIZE (GET_MODE (SET_DEST (set
))) == 8;
968 next
= next_active_insn (insn
);
972 for (after
= next
, i
= 0; i
< 2; i
++)
974 /* Skip empty assembly statements. */
975 if ((GET_CODE (PATTERN (after
)) == UNSPEC_VOLATILE
)
976 || (USEFUL_INSN_P (after
)
977 && (asm_noperands (PATTERN (after
))>=0)
978 && !strcmp (decode_asm_operands (PATTERN (after
),
981 after
= next_active_insn (after
);
985 /* If the insn is a branch, then it cannot be problematic. */
986 if (!NONJUMP_INSN_P (after
)
987 || GET_CODE (PATTERN (after
)) == SEQUENCE
)
990 /* Sequence B is only two instructions long. */
993 /* Add NOP if followed by a store. */
994 if ((set
= single_set (after
)) != NULL_RTX
995 && MEM_P (SET_DEST (set
)))
998 /* Otherwise it is ok. */
1002 /* If the second instruction is a load or a store,
1003 then the sequence cannot be problematic. */
1006 if (((set
= single_set (after
)) != NULL_RTX
)
1007 && (MEM_P (SET_DEST (set
)) || MEM_P (SET_SRC (set
))))
1010 after
= next_active_insn (after
);
1015 /* Add NOP if third instruction is a store. */
1017 && ((set
= single_set (after
)) != NULL_RTX
)
1018 && MEM_P (SET_DEST (set
)))
1023 /* Look for a single-word load into an odd-numbered FP register. */
1024 if (sparc_fix_at697f
1025 && NONJUMP_INSN_P (insn
)
1026 && (set
= single_set (insn
)) != NULL_RTX
1027 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
1028 && MEM_P (SET_SRC (set
))
1029 && REG_P (SET_DEST (set
))
1030 && REGNO (SET_DEST (set
)) > 31
1031 && REGNO (SET_DEST (set
)) % 2 != 0)
1033 /* The wrong dependency is on the enclosing double register. */
1034 const unsigned int x
= REGNO (SET_DEST (set
)) - 1;
1035 unsigned int src1
, src2
, dest
;
1038 next
= next_active_insn (insn
);
1041 /* If the insn is a branch, then it cannot be problematic. */
1042 if (!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) == SEQUENCE
)
1045 extract_insn (next
);
1046 code
= INSN_CODE (next
);
1050 case CODE_FOR_adddf3
:
1051 case CODE_FOR_subdf3
:
1052 case CODE_FOR_muldf3
:
1053 case CODE_FOR_divdf3
:
1054 dest
= REGNO (recog_data
.operand
[0]);
1055 src1
= REGNO (recog_data
.operand
[1]);
1056 src2
= REGNO (recog_data
.operand
[2]);
1061 FPOPd %f{x,y}, %f{y,x}, %f{x,y} */
1062 if ((src1
== x
|| src2
== x
)
1063 && (dest
== src1
|| dest
== src2
))
1070 FPOPd %fx, %fx, %fx */
1073 && (code
== CODE_FOR_adddf3
|| code
== CODE_FOR_muldf3
))
1078 case CODE_FOR_sqrtdf2
:
1079 dest
= REGNO (recog_data
.operand
[0]);
1080 src1
= REGNO (recog_data
.operand
[1]);
1084 if (src1
== x
&& dest
== src1
)
1093 /* Look for a single-word load into an integer register. */
1094 else if (sparc_fix_ut699
1095 && NONJUMP_INSN_P (insn
)
1096 && (set
= single_set (insn
)) != NULL_RTX
1097 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) <= 4
1098 && mem_ref (SET_SRC (set
)) != NULL_RTX
1099 && REG_P (SET_DEST (set
))
1100 && REGNO (SET_DEST (set
)) < 32)
1102 /* There is no problem if the second memory access has a data
1103 dependency on the first single-cycle load. */
1104 rtx x
= SET_DEST (set
);
1106 next
= next_active_insn (insn
);
1109 /* If the insn is a branch, then it cannot be problematic. */
1110 if (!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) == SEQUENCE
)
1113 /* Look for a second memory access to/from an integer register. */
1114 if ((set
= single_set (next
)) != NULL_RTX
)
1116 rtx src
= SET_SRC (set
);
1117 rtx dest
= SET_DEST (set
);
1120 /* LDD is affected. */
1121 if ((mem
= mem_ref (src
)) != NULL_RTX
1123 && REGNO (dest
) < 32
1124 && !reg_mentioned_p (x
, XEXP (mem
, 0)))
1127 /* STD is *not* affected. */
1128 else if (MEM_P (dest
)
1129 && GET_MODE_SIZE (GET_MODE (dest
)) <= 4
1130 && (src
== CONST0_RTX (GET_MODE (dest
))
1133 && REGNO (src
) != REGNO (x
)))
1134 && !reg_mentioned_p (x
, XEXP (dest
, 0)))
1139 /* Look for a single-word load/operation into an FP register. */
1140 else if (sparc_fix_ut699
1141 && NONJUMP_INSN_P (insn
)
1142 && (set
= single_set (insn
)) != NULL_RTX
1143 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
1144 && REG_P (SET_DEST (set
))
1145 && REGNO (SET_DEST (set
)) > 31)
1147 /* Number of instructions in the problematic window. */
1148 const int n_insns
= 4;
1149 /* The problematic combination is with the sibling FP register. */
1150 const unsigned int x
= REGNO (SET_DEST (set
));
1151 const unsigned int y
= x
^ 1;
1155 next
= next_active_insn (insn
);
1158 /* If the insn is a branch, then it cannot be problematic. */
1159 if (!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) == SEQUENCE
)
1162 /* Look for a second load/operation into the sibling FP register. */
1163 if (!((set
= single_set (next
)) != NULL_RTX
1164 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
1165 && REG_P (SET_DEST (set
))
1166 && REGNO (SET_DEST (set
)) == y
))
1169 /* Look for a (possible) store from the FP register in the next N
1170 instructions, but bail out if it is again modified or if there
1171 is a store from the sibling FP register before this store. */
1172 for (after
= next
, i
= 0; i
< n_insns
; i
++)
1176 after
= next_active_insn (after
);
1180 /* This is a branch with an empty delay slot. */
1181 if (!NONJUMP_INSN_P (after
))
1188 /* This is a branch with a filled delay slot. */
1189 else if (rtx_sequence
*seq
=
1190 dyn_cast
<rtx_sequence
*> (PATTERN (after
)))
1195 after
= seq
->insn (1);
1197 /* This is a regular instruction. */
1201 if (after
&& (set
= single_set (after
)) != NULL_RTX
)
1203 const rtx src
= SET_SRC (set
);
1204 const rtx dest
= SET_DEST (set
);
1205 const unsigned int size
= GET_MODE_SIZE (GET_MODE (dest
));
1207 /* If the FP register is again modified before the store,
1208 then the store isn't affected. */
1210 && (REGNO (dest
) == x
1211 || (REGNO (dest
) == y
&& size
== 8)))
1214 if (MEM_P (dest
) && REG_P (src
))
1216 /* If there is a store from the sibling FP register
1217 before the store, then the store is not affected. */
1218 if (REGNO (src
) == y
|| (REGNO (src
) == x
&& size
== 8))
1221 /* Otherwise, the store is affected. */
1222 if (REGNO (src
) == x
&& size
== 4)
1230 /* If we have a branch in the first M instructions, then we
1231 cannot see the (M+2)th instruction so we play safe. */
1232 if (branch_p
&& i
<= (n_insns
- 2))
1241 next
= NEXT_INSN (insn
);
1244 emit_insn_before (gen_nop (), next
);
1252 const pass_data pass_data_work_around_errata
=
1254 RTL_PASS
, /* type */
1255 "errata", /* name */
1256 OPTGROUP_NONE
, /* optinfo_flags */
1257 TV_MACH_DEP
, /* tv_id */
1258 0, /* properties_required */
1259 0, /* properties_provided */
1260 0, /* properties_destroyed */
1261 0, /* todo_flags_start */
1262 0, /* todo_flags_finish */
1265 class pass_work_around_errata
: public rtl_opt_pass
1268 pass_work_around_errata(gcc::context
*ctxt
)
1269 : rtl_opt_pass(pass_data_work_around_errata
, ctxt
)
1272 /* opt_pass methods: */
1273 virtual bool gate (function
*)
1275 return sparc_fix_at697f
|| sparc_fix_ut699
|| sparc_fix_b2bst
;
1278 virtual unsigned int execute (function
*)
1280 return sparc_do_work_around_errata ();
1283 }; // class pass_work_around_errata
1288 make_pass_work_around_errata (gcc::context
*ctxt
)
1290 return new pass_work_around_errata (ctxt
);
1293 /* Helpers for TARGET_DEBUG_OPTIONS. */
1295 dump_target_flag_bits (const int flags
)
1297 if (flags
& MASK_64BIT
)
1298 fprintf (stderr
, "64BIT ");
1299 if (flags
& MASK_APP_REGS
)
1300 fprintf (stderr
, "APP_REGS ");
1301 if (flags
& MASK_FASTER_STRUCTS
)
1302 fprintf (stderr
, "FASTER_STRUCTS ");
1303 if (flags
& MASK_FLAT
)
1304 fprintf (stderr
, "FLAT ");
1305 if (flags
& MASK_FMAF
)
1306 fprintf (stderr
, "FMAF ");
1307 if (flags
& MASK_FPU
)
1308 fprintf (stderr
, "FPU ");
1309 if (flags
& MASK_HARD_QUAD
)
1310 fprintf (stderr
, "HARD_QUAD ");
1311 if (flags
& MASK_POPC
)
1312 fprintf (stderr
, "POPC ");
1313 if (flags
& MASK_PTR64
)
1314 fprintf (stderr
, "PTR64 ");
1315 if (flags
& MASK_STACK_BIAS
)
1316 fprintf (stderr
, "STACK_BIAS ");
1317 if (flags
& MASK_UNALIGNED_DOUBLES
)
1318 fprintf (stderr
, "UNALIGNED_DOUBLES ");
1319 if (flags
& MASK_V8PLUS
)
1320 fprintf (stderr
, "V8PLUS ");
1321 if (flags
& MASK_VIS
)
1322 fprintf (stderr
, "VIS ");
1323 if (flags
& MASK_VIS2
)
1324 fprintf (stderr
, "VIS2 ");
1325 if (flags
& MASK_VIS3
)
1326 fprintf (stderr
, "VIS3 ");
1327 if (flags
& MASK_VIS4
)
1328 fprintf (stderr
, "VIS4 ");
1329 if (flags
& MASK_VIS4B
)
1330 fprintf (stderr
, "VIS4B ");
1331 if (flags
& MASK_CBCOND
)
1332 fprintf (stderr
, "CBCOND ");
1333 if (flags
& MASK_DEPRECATED_V8_INSNS
)
1334 fprintf (stderr
, "DEPRECATED_V8_INSNS ");
1335 if (flags
& MASK_SPARCLET
)
1336 fprintf (stderr
, "SPARCLET ");
1337 if (flags
& MASK_SPARCLITE
)
1338 fprintf (stderr
, "SPARCLITE ");
1339 if (flags
& MASK_V8
)
1340 fprintf (stderr
, "V8 ");
1341 if (flags
& MASK_V9
)
1342 fprintf (stderr
, "V9 ");
1346 dump_target_flags (const char *prefix
, const int flags
)
1348 fprintf (stderr
, "%s: (%08x) [ ", prefix
, flags
);
1349 dump_target_flag_bits (flags
);
1350 fprintf(stderr
, "]\n");
1353 /* Validate and override various options, and do some machine dependent
1357 sparc_option_override (void)
1359 static struct code_model
{
1360 const char *const name
;
1361 const enum cmodel value
;
1362 } const cmodels
[] = {
1364 { "medlow", CM_MEDLOW
},
1365 { "medmid", CM_MEDMID
},
1366 { "medany", CM_MEDANY
},
1367 { "embmedany", CM_EMBMEDANY
},
1368 { NULL
, (enum cmodel
) 0 }
1370 const struct code_model
*cmodel
;
1371 /* Map TARGET_CPU_DEFAULT to value for -m{cpu,tune}=. */
1372 static struct cpu_default
{
1374 const enum processor_type processor
;
1375 } const cpu_default
[] = {
1376 /* There must be one entry here for each TARGET_CPU value. */
1377 { TARGET_CPU_sparc
, PROCESSOR_CYPRESS
},
1378 { TARGET_CPU_v8
, PROCESSOR_V8
},
1379 { TARGET_CPU_supersparc
, PROCESSOR_SUPERSPARC
},
1380 { TARGET_CPU_hypersparc
, PROCESSOR_HYPERSPARC
},
1381 { TARGET_CPU_leon
, PROCESSOR_LEON
},
1382 { TARGET_CPU_leon3
, PROCESSOR_LEON3
},
1383 { TARGET_CPU_leon3v7
, PROCESSOR_LEON3V7
},
1384 { TARGET_CPU_sparclite
, PROCESSOR_F930
},
1385 { TARGET_CPU_sparclite86x
, PROCESSOR_SPARCLITE86X
},
1386 { TARGET_CPU_sparclet
, PROCESSOR_TSC701
},
1387 { TARGET_CPU_v9
, PROCESSOR_V9
},
1388 { TARGET_CPU_ultrasparc
, PROCESSOR_ULTRASPARC
},
1389 { TARGET_CPU_ultrasparc3
, PROCESSOR_ULTRASPARC3
},
1390 { TARGET_CPU_niagara
, PROCESSOR_NIAGARA
},
1391 { TARGET_CPU_niagara2
, PROCESSOR_NIAGARA2
},
1392 { TARGET_CPU_niagara3
, PROCESSOR_NIAGARA3
},
1393 { TARGET_CPU_niagara4
, PROCESSOR_NIAGARA4
},
1394 { TARGET_CPU_niagara7
, PROCESSOR_NIAGARA7
},
1395 { TARGET_CPU_m8
, PROCESSOR_M8
},
1396 { -1, PROCESSOR_V7
}
1398 const struct cpu_default
*def
;
1399 /* Table of values for -m{cpu,tune}=. This must match the order of
1400 the enum processor_type in sparc-opts.h. */
1401 static struct cpu_table
{
1402 const char *const name
;
1405 } const cpu_table
[] = {
1406 { "v7", MASK_ISA
, 0 },
1407 { "cypress", MASK_ISA
, 0 },
1408 { "v8", MASK_ISA
, MASK_V8
},
1409 /* TI TMS390Z55 supersparc */
1410 { "supersparc", MASK_ISA
, MASK_V8
},
1411 { "hypersparc", MASK_ISA
, MASK_V8
|MASK_FPU
},
1412 { "leon", MASK_ISA
, MASK_V8
|MASK_LEON
|MASK_FPU
},
1413 { "leon3", MASK_ISA
, MASK_V8
|MASK_LEON3
|MASK_FPU
},
1414 { "leon3v7", MASK_ISA
, MASK_LEON3
|MASK_FPU
},
1415 { "sparclite", MASK_ISA
, MASK_SPARCLITE
},
1416 /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
1417 { "f930", MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
1418 /* The Fujitsu MB86934 is the recent sparclite chip, with an FPU. */
1419 { "f934", MASK_ISA
, MASK_SPARCLITE
|MASK_FPU
},
1420 { "sparclite86x", MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
1421 { "sparclet", MASK_ISA
, MASK_SPARCLET
},
1422 /* TEMIC sparclet */
1423 { "tsc701", MASK_ISA
, MASK_SPARCLET
},
1424 { "v9", MASK_ISA
, MASK_V9
},
1425 /* UltraSPARC I, II, IIi */
1426 { "ultrasparc", MASK_ISA
,
1427 /* Although insns using %y are deprecated, it is a clear win. */
1428 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
1429 /* UltraSPARC III */
1430 /* ??? Check if %y issue still holds true. */
1431 { "ultrasparc3", MASK_ISA
,
1432 MASK_V9
|MASK_DEPRECATED_V8_INSNS
|MASK_VIS2
},
1434 { "niagara", MASK_ISA
,
1435 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
1437 { "niagara2", MASK_ISA
,
1438 MASK_V9
|MASK_POPC
|MASK_VIS2
},
1440 { "niagara3", MASK_ISA
,
1441 MASK_V9
|MASK_POPC
|MASK_VIS3
|MASK_FMAF
},
1443 { "niagara4", MASK_ISA
,
1444 MASK_V9
|MASK_POPC
|MASK_VIS3
|MASK_FMAF
|MASK_CBCOND
},
1446 { "niagara7", MASK_ISA
,
1447 MASK_V9
|MASK_POPC
|MASK_VIS4
|MASK_FMAF
|MASK_CBCOND
|MASK_SUBXC
},
1450 MASK_V9
|MASK_POPC
|MASK_VIS4
|MASK_FMAF
|MASK_CBCOND
|MASK_SUBXC
1453 const struct cpu_table
*cpu
;
1456 if (sparc_debug_string
!= NULL
)
1461 p
= ASTRDUP (sparc_debug_string
);
1462 while ((q
= strtok (p
, ",")) != NULL
)
1476 if (! strcmp (q
, "all"))
1477 mask
= MASK_DEBUG_ALL
;
1478 else if (! strcmp (q
, "options"))
1479 mask
= MASK_DEBUG_OPTIONS
;
1481 error ("unknown -mdebug-%s switch", q
);
1484 sparc_debug
&= ~mask
;
1486 sparc_debug
|= mask
;
1490 if (TARGET_DEBUG_OPTIONS
)
1492 dump_target_flags("Initial target_flags", target_flags
);
1493 dump_target_flags("target_flags_explicit", target_flags_explicit
);
1496 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1497 SUBTARGET_OVERRIDE_OPTIONS
;
1500 #ifndef SPARC_BI_ARCH
1501 /* Check for unsupported architecture size. */
1502 if (!TARGET_64BIT
!= DEFAULT_ARCH32_P
)
1503 error ("%s is not supported by this configuration",
1504 DEFAULT_ARCH32_P
? "-m64" : "-m32");
1507 /* We force all 64bit archs to use 128 bit long double */
1508 if (TARGET_ARCH64
&& !TARGET_LONG_DOUBLE_128
)
1510 error ("-mlong-double-64 not allowed with -m64");
1511 target_flags
|= MASK_LONG_DOUBLE_128
;
1514 /* Code model selection. */
1515 sparc_cmodel
= SPARC_DEFAULT_CMODEL
;
1517 #ifdef SPARC_BI_ARCH
1519 sparc_cmodel
= CM_32
;
1522 if (sparc_cmodel_string
!= NULL
)
1526 for (cmodel
= &cmodels
[0]; cmodel
->name
; cmodel
++)
1527 if (strcmp (sparc_cmodel_string
, cmodel
->name
) == 0)
1529 if (cmodel
->name
== NULL
)
1530 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string
);
1532 sparc_cmodel
= cmodel
->value
;
1535 error ("-mcmodel= is not supported on 32 bit systems");
1538 /* Check that -fcall-saved-REG wasn't specified for out registers. */
1539 for (i
= 8; i
< 16; i
++)
1540 if (!call_used_regs
[i
])
1542 error ("-fcall-saved-REG is not supported for out registers");
1543 call_used_regs
[i
] = 1;
1546 /* Set the default CPU. */
1547 if (!global_options_set
.x_sparc_cpu_and_features
)
1549 for (def
= &cpu_default
[0]; def
->cpu
!= -1; ++def
)
1550 if (def
->cpu
== TARGET_CPU_DEFAULT
)
1552 gcc_assert (def
->cpu
!= -1);
1553 sparc_cpu_and_features
= def
->processor
;
1556 if (!global_options_set
.x_sparc_cpu
)
1557 sparc_cpu
= sparc_cpu_and_features
;
1559 cpu
= &cpu_table
[(int) sparc_cpu_and_features
];
1561 if (TARGET_DEBUG_OPTIONS
)
1563 fprintf (stderr
, "sparc_cpu_and_features: %s\n", cpu
->name
);
1564 fprintf (stderr
, "sparc_cpu: %s\n",
1565 cpu_table
[(int) sparc_cpu
].name
);
1566 dump_target_flags ("cpu->disable", cpu
->disable
);
1567 dump_target_flags ("cpu->enable", cpu
->enable
);
1570 target_flags
&= ~cpu
->disable
;
1571 target_flags
|= (cpu
->enable
1572 #ifndef HAVE_AS_FMAF_HPC_VIS3
1573 & ~(MASK_FMAF
| MASK_VIS3
)
1575 #ifndef HAVE_AS_SPARC4
1578 #ifndef HAVE_AS_SPARC5_VIS4
1579 & ~(MASK_VIS4
| MASK_SUBXC
)
1581 #ifndef HAVE_AS_SPARC6
1584 #ifndef HAVE_AS_LEON
1585 & ~(MASK_LEON
| MASK_LEON3
)
1587 & ~(target_flags_explicit
& MASK_FEATURES
)
1590 /* -mvis2 implies -mvis. */
1592 target_flags
|= MASK_VIS
;
1594 /* -mvis3 implies -mvis2 and -mvis. */
1596 target_flags
|= MASK_VIS2
| MASK_VIS
;
1598 /* -mvis4 implies -mvis3, -mvis2 and -mvis. */
1600 target_flags
|= MASK_VIS3
| MASK_VIS2
| MASK_VIS
;
1602 /* -mvis4b implies -mvis4, -mvis3, -mvis2 and -mvis */
1604 target_flags
|= MASK_VIS4
| MASK_VIS3
| MASK_VIS2
| MASK_VIS
;
1606 /* Don't allow -mvis, -mvis2, -mvis3, -mvis4, -mvis4b and -mfmaf if
1609 target_flags
&= ~(MASK_VIS
| MASK_VIS2
| MASK_VIS3
| MASK_VIS4
1610 | MASK_VIS4B
| MASK_FMAF
);
1612 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
1613 are available; -m64 also implies v9. */
1614 if (TARGET_VIS
|| TARGET_ARCH64
)
1616 target_flags
|= MASK_V9
;
1617 target_flags
&= ~(MASK_V8
| MASK_SPARCLET
| MASK_SPARCLITE
);
1620 /* -mvis also implies -mv8plus on 32-bit. */
1621 if (TARGET_VIS
&& ! TARGET_ARCH64
)
1622 target_flags
|= MASK_V8PLUS
;
1624 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
1625 if (TARGET_V9
&& TARGET_ARCH32
)
1626 target_flags
|= MASK_DEPRECATED_V8_INSNS
;
1628 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
1629 if (! TARGET_V9
|| TARGET_ARCH64
)
1630 target_flags
&= ~MASK_V8PLUS
;
1632 /* Don't use stack biasing in 32 bit mode. */
1634 target_flags
&= ~MASK_STACK_BIAS
;
1636 /* Use LRA instead of reload, unless otherwise instructed. */
1637 if (!(target_flags_explicit
& MASK_LRA
))
1638 target_flags
|= MASK_LRA
;
1640 /* Enable the back-to-back store errata workaround for LEON3FT. */
1641 if (sparc_fix_ut699
|| sparc_fix_ut700
|| sparc_fix_gr712rc
)
1642 sparc_fix_b2bst
= 1;
1644 /* Supply a default value for align_functions. */
1645 if (align_functions
== 0)
1647 if (sparc_cpu
== PROCESSOR_ULTRASPARC
1648 || sparc_cpu
== PROCESSOR_ULTRASPARC3
1649 || sparc_cpu
== PROCESSOR_NIAGARA
1650 || sparc_cpu
== PROCESSOR_NIAGARA2
1651 || sparc_cpu
== PROCESSOR_NIAGARA3
1652 || sparc_cpu
== PROCESSOR_NIAGARA4
)
1653 align_functions
= 32;
1654 else if (sparc_cpu
== PROCESSOR_NIAGARA7
1655 || sparc_cpu
== PROCESSOR_M8
)
1656 align_functions
= 64;
1659 /* Validate PCC_STRUCT_RETURN. */
1660 if (flag_pcc_struct_return
== DEFAULT_PCC_STRUCT_RETURN
)
1661 flag_pcc_struct_return
= (TARGET_ARCH64
? 0 : 1);
1663 /* Only use .uaxword when compiling for a 64-bit target. */
1665 targetm
.asm_out
.unaligned_op
.di
= NULL
;
1667 /* Do various machine dependent initializations. */
1668 sparc_init_modes ();
1670 /* Set up function hooks. */
1671 init_machine_status
= sparc_init_machine_status
;
1676 case PROCESSOR_CYPRESS
:
1677 sparc_costs
= &cypress_costs
;
1680 case PROCESSOR_SPARCLITE
:
1681 case PROCESSOR_SUPERSPARC
:
1682 sparc_costs
= &supersparc_costs
;
1684 case PROCESSOR_F930
:
1685 case PROCESSOR_F934
:
1686 case PROCESSOR_HYPERSPARC
:
1687 case PROCESSOR_SPARCLITE86X
:
1688 sparc_costs
= &hypersparc_costs
;
1690 case PROCESSOR_LEON
:
1691 sparc_costs
= &leon_costs
;
1693 case PROCESSOR_LEON3
:
1694 case PROCESSOR_LEON3V7
:
1695 sparc_costs
= &leon3_costs
;
1697 case PROCESSOR_SPARCLET
:
1698 case PROCESSOR_TSC701
:
1699 sparc_costs
= &sparclet_costs
;
1702 case PROCESSOR_ULTRASPARC
:
1703 sparc_costs
= &ultrasparc_costs
;
1705 case PROCESSOR_ULTRASPARC3
:
1706 sparc_costs
= &ultrasparc3_costs
;
1708 case PROCESSOR_NIAGARA
:
1709 sparc_costs
= &niagara_costs
;
1711 case PROCESSOR_NIAGARA2
:
1712 sparc_costs
= &niagara2_costs
;
1714 case PROCESSOR_NIAGARA3
:
1715 sparc_costs
= &niagara3_costs
;
1717 case PROCESSOR_NIAGARA4
:
1718 sparc_costs
= &niagara4_costs
;
1720 case PROCESSOR_NIAGARA7
:
1721 sparc_costs
= &niagara7_costs
;
1724 sparc_costs
= &m8_costs
;
1726 case PROCESSOR_NATIVE
:
1730 if (sparc_memory_model
== SMM_DEFAULT
)
1732 /* Choose the memory model for the operating system. */
1733 enum sparc_memory_model_type os_default
= SUBTARGET_DEFAULT_MEMORY_MODEL
;
1734 if (os_default
!= SMM_DEFAULT
)
1735 sparc_memory_model
= os_default
;
1736 /* Choose the most relaxed model for the processor. */
1738 sparc_memory_model
= SMM_RMO
;
1739 else if (TARGET_LEON3
)
1740 sparc_memory_model
= SMM_TSO
;
1741 else if (TARGET_LEON
)
1742 sparc_memory_model
= SMM_SC
;
1744 sparc_memory_model
= SMM_PSO
;
1746 sparc_memory_model
= SMM_SC
;
1749 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1750 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
1751 target_flags
|= MASK_LONG_DOUBLE_128
;
1754 if (TARGET_DEBUG_OPTIONS
)
1755 dump_target_flags ("Final target_flags", target_flags
);
1757 /* PARAM_SIMULTANEOUS_PREFETCHES is the number of prefetches that
1758 can run at the same time. More important, it is the threshold
1759 defining when additional prefetches will be dropped by the
1762 The UltraSPARC-III features a documented prefetch queue with a
1763 size of 8. Additional prefetches issued in the cpu are
1766 Niagara processors are different. In these processors prefetches
1767 are handled much like regular loads. The L1 miss buffer is 32
1768 entries, but prefetches start getting affected when 30 entries
1769 become occupied. That occupation could be a mix of regular loads
1770 and prefetches though. And that buffer is shared by all threads.
1771 Once the threshold is reached, if the core is running a single
1772 thread the prefetch will retry. If more than one thread is
1773 running, the prefetch will be dropped.
1775 All this makes it very difficult to determine how many
1776 simultaneous prefetches can be issued simultaneously, even in a
1777 single-threaded program. Experimental results show that setting
1778 this parameter to 32 works well when the number of threads is not
1780 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
1781 ((sparc_cpu
== PROCESSOR_ULTRASPARC
1782 || sparc_cpu
== PROCESSOR_NIAGARA
1783 || sparc_cpu
== PROCESSOR_NIAGARA2
1784 || sparc_cpu
== PROCESSOR_NIAGARA3
1785 || sparc_cpu
== PROCESSOR_NIAGARA4
)
1787 : (sparc_cpu
== PROCESSOR_ULTRASPARC3
1788 ? 8 : ((sparc_cpu
== PROCESSOR_NIAGARA7
1789 || sparc_cpu
== PROCESSOR_M8
)
1791 global_options
.x_param_values
,
1792 global_options_set
.x_param_values
);
1794 /* PARAM_L1_CACHE_LINE_SIZE is the size of the L1 cache line, in
1797 The Oracle SPARC Architecture (previously the UltraSPARC
1798 Architecture) specification states that when a PREFETCH[A]
1799 instruction is executed an implementation-specific amount of data
1800 is prefetched, and that it is at least 64 bytes long (aligned to
1803 However, this is not correct. The M7 (and implementations prior
1804 to that) does not guarantee a 64B prefetch into a cache if the
1805 line size is smaller. A single cache line is all that is ever
1806 prefetched. So for the M7, where the L1D$ has 32B lines and the
1807 L2D$ and L3 have 64B lines, a prefetch will prefetch 64B into the
1808 L2 and L3, but only 32B are brought into the L1D$. (Assuming it
1809 is a read_n prefetch, which is the only type which allocates to
1811 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
1812 (sparc_cpu
== PROCESSOR_M8
1814 global_options
.x_param_values
,
1815 global_options_set
.x_param_values
);
1817 /* PARAM_L1_CACHE_SIZE is the size of the L1D$ (most SPARC chips use
1818 Hardvard level-1 caches) in kilobytes. Both UltraSPARC and
1819 Niagara processors feature a L1D$ of 16KB. */
1820 maybe_set_param_value (PARAM_L1_CACHE_SIZE
,
1821 ((sparc_cpu
== PROCESSOR_ULTRASPARC
1822 || sparc_cpu
== PROCESSOR_ULTRASPARC3
1823 || sparc_cpu
== PROCESSOR_NIAGARA
1824 || sparc_cpu
== PROCESSOR_NIAGARA2
1825 || sparc_cpu
== PROCESSOR_NIAGARA3
1826 || sparc_cpu
== PROCESSOR_NIAGARA4
1827 || sparc_cpu
== PROCESSOR_NIAGARA7
1828 || sparc_cpu
== PROCESSOR_M8
)
1830 global_options
.x_param_values
,
1831 global_options_set
.x_param_values
);
1834 /* PARAM_L2_CACHE_SIZE is the size fo the L2 in kilobytes. Note
1835 that 512 is the default in params.def. */
1836 maybe_set_param_value (PARAM_L2_CACHE_SIZE
,
1837 ((sparc_cpu
== PROCESSOR_NIAGARA4
1838 || sparc_cpu
== PROCESSOR_M8
)
1839 ? 128 : (sparc_cpu
== PROCESSOR_NIAGARA7
1841 global_options
.x_param_values
,
1842 global_options_set
.x_param_values
);
1845 /* Disable save slot sharing for call-clobbered registers by default.
1846 The IRA sharing algorithm works on single registers only and this
1847 pessimizes for double floating-point registers. */
1848 if (!global_options_set
.x_flag_ira_share_save_slots
)
1849 flag_ira_share_save_slots
= 0;
1851 /* Only enable REE by default in 64-bit mode where it helps to eliminate
1852 redundant 32-to-64-bit extensions. */
1853 if (!global_options_set
.x_flag_ree
&& TARGET_ARCH32
)
1857 /* Miscellaneous utilities. */
1859 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
1860 or branch on register contents instructions. */
1863 v9_regcmp_p (enum rtx_code code
)
1865 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
1866 || code
== LE
|| code
== GT
);
1869 /* Nonzero if OP is a floating point constant which can
1870 be loaded into an integer register using a single
1871 sethi instruction. */
1876 if (GET_CODE (op
) == CONST_DOUBLE
)
1880 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), i
);
1881 return !SPARC_SIMM13_P (i
) && SPARC_SETHI_P (i
);
1887 /* Nonzero if OP is a floating point constant which can
1888 be loaded into an integer register using a single
1894 if (GET_CODE (op
) == CONST_DOUBLE
)
1898 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), i
);
1899 return SPARC_SIMM13_P (i
);
1905 /* Nonzero if OP is a floating point constant which can
1906 be loaded into an integer register using a high/losum
1907 instruction sequence. */
1910 fp_high_losum_p (rtx op
)
1912 /* The constraints calling this should only be in
1913 SFmode move insns, so any constant which cannot
1914 be moved using a single insn will do. */
1915 if (GET_CODE (op
) == CONST_DOUBLE
)
1919 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), i
);
1920 return !SPARC_SIMM13_P (i
) && !SPARC_SETHI_P (i
);
1926 /* Return true if the address of LABEL can be loaded by means of the
1927 mov{si,di}_pic_label_ref patterns in PIC mode. */
1930 can_use_mov_pic_label_ref (rtx label
)
1932 /* VxWorks does not impose a fixed gap between segments; the run-time
1933 gap can be different from the object-file gap. We therefore can't
1934 assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
1935 are absolutely sure that X is in the same segment as the GOT.
1936 Unfortunately, the flexibility of linker scripts means that we
1937 can't be sure of that in general, so assume that GOT-relative
1938 accesses are never valid on VxWorks. */
1939 if (TARGET_VXWORKS_RTP
)
1942 /* Similarly, if the label is non-local, it might end up being placed
1943 in a different section than the current one; now mov_pic_label_ref
1944 requires the label and the code to be in the same section. */
1945 if (LABEL_REF_NONLOCAL_P (label
))
1948 /* Finally, if we are reordering basic blocks and partition into hot
1949 and cold sections, this might happen for any label. */
1950 if (flag_reorder_blocks_and_partition
)
1956 /* Expand a move instruction. Return true if all work is done. */
1959 sparc_expand_move (machine_mode mode
, rtx
*operands
)
1961 /* Handle sets of MEM first. */
1962 if (GET_CODE (operands
[0]) == MEM
)
1964 /* 0 is a register (or a pair of registers) on SPARC. */
1965 if (register_or_zero_operand (operands
[1], mode
))
1968 if (!reload_in_progress
)
1970 operands
[0] = validize_mem (operands
[0]);
1971 operands
[1] = force_reg (mode
, operands
[1]);
1975 /* Fixup TLS cases. */
1977 && CONSTANT_P (operands
[1])
1978 && sparc_tls_referenced_p (operands
[1]))
1980 operands
[1] = sparc_legitimize_tls_address (operands
[1]);
1984 /* Fixup PIC cases. */
1985 if (flag_pic
&& CONSTANT_P (operands
[1]))
1987 if (pic_address_needs_scratch (operands
[1]))
1988 operands
[1] = sparc_legitimize_pic_address (operands
[1], NULL_RTX
);
1990 /* We cannot use the mov{si,di}_pic_label_ref patterns in all cases. */
1991 if (GET_CODE (operands
[1]) == LABEL_REF
1992 && can_use_mov_pic_label_ref (operands
[1]))
1996 emit_insn (gen_movsi_pic_label_ref (operands
[0], operands
[1]));
2002 gcc_assert (TARGET_ARCH64
);
2003 emit_insn (gen_movdi_pic_label_ref (operands
[0], operands
[1]));
2008 if (symbolic_operand (operands
[1], mode
))
2011 = sparc_legitimize_pic_address (operands
[1],
2013 ? operands
[0] : NULL_RTX
);
2018 /* If we are trying to toss an integer constant into FP registers,
2019 or loading a FP or vector constant, force it into memory. */
2020 if (CONSTANT_P (operands
[1])
2021 && REG_P (operands
[0])
2022 && (SPARC_FP_REG_P (REGNO (operands
[0]))
2023 || SCALAR_FLOAT_MODE_P (mode
)
2024 || VECTOR_MODE_P (mode
)))
2026 /* emit_group_store will send such bogosity to us when it is
2027 not storing directly into memory. So fix this up to avoid
2028 crashes in output_constant_pool. */
2029 if (operands
[1] == const0_rtx
)
2030 operands
[1] = CONST0_RTX (mode
);
2032 /* We can clear or set to all-ones FP registers if TARGET_VIS, and
2033 always other regs. */
2034 if ((TARGET_VIS
|| REGNO (operands
[0]) < SPARC_FIRST_FP_REG
)
2035 && (const_zero_operand (operands
[1], mode
)
2036 || const_all_ones_operand (operands
[1], mode
)))
2039 if (REGNO (operands
[0]) < SPARC_FIRST_FP_REG
2040 /* We are able to build any SF constant in integer registers
2041 with at most 2 instructions. */
2043 /* And any DF constant in integer registers if needed. */
2044 || (mode
== DFmode
&& !can_create_pseudo_p ())))
2047 operands
[1] = force_const_mem (mode
, operands
[1]);
2048 if (!reload_in_progress
)
2049 operands
[1] = validize_mem (operands
[1]);
2053 /* Accept non-constants and valid constants unmodified. */
2054 if (!CONSTANT_P (operands
[1])
2055 || GET_CODE (operands
[1]) == HIGH
2056 || input_operand (operands
[1], mode
))
2062 /* All QImode constants require only one insn, so proceed. */
2067 sparc_emit_set_const32 (operands
[0], operands
[1]);
2071 /* input_operand should have filtered out 32-bit mode. */
2072 sparc_emit_set_const64 (operands
[0], operands
[1]);
2078 /* TImode isn't available in 32-bit mode. */
2079 split_double (operands
[1], &high
, &low
);
2080 emit_insn (gen_movdi (operand_subword (operands
[0], 0, 0, TImode
),
2082 emit_insn (gen_movdi (operand_subword (operands
[0], 1, 0, TImode
),
2094 /* Load OP1, a 32-bit constant, into OP0, a register.
2095 We know it can't be done in one insn when we get
2096 here, the move expander guarantees this. */
2099 sparc_emit_set_const32 (rtx op0
, rtx op1
)
2101 machine_mode mode
= GET_MODE (op0
);
2104 if (can_create_pseudo_p ())
2105 temp
= gen_reg_rtx (mode
);
2107 if (GET_CODE (op1
) == CONST_INT
)
2109 gcc_assert (!small_int_operand (op1
, mode
)
2110 && !const_high_operand (op1
, mode
));
2112 /* Emit them as real moves instead of a HIGH/LO_SUM,
2113 this way CSE can see everything and reuse intermediate
2114 values if it wants. */
2115 emit_insn (gen_rtx_SET (temp
, GEN_INT (INTVAL (op1
)
2116 & ~(HOST_WIDE_INT
) 0x3ff)));
2118 emit_insn (gen_rtx_SET (op0
,
2119 gen_rtx_IOR (mode
, temp
,
2120 GEN_INT (INTVAL (op1
) & 0x3ff))));
2124 /* A symbol, emit in the traditional way. */
2125 emit_insn (gen_rtx_SET (temp
, gen_rtx_HIGH (mode
, op1
)));
2126 emit_insn (gen_rtx_SET (op0
, gen_rtx_LO_SUM (mode
, temp
, op1
)));
2130 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
2131 If TEMP is nonzero, we are forbidden to use any other scratch
2132 registers. Otherwise, we are allowed to generate them as needed.
2134 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
2135 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
2138 sparc_emit_set_symbolic_const64 (rtx op0
, rtx op1
, rtx temp
)
2140 rtx temp1
, temp2
, temp3
, temp4
, temp5
;
2143 if (temp
&& GET_MODE (temp
) == TImode
)
2146 temp
= gen_rtx_REG (DImode
, REGNO (temp
));
2149 /* SPARC-V9 code-model support. */
2150 switch (sparc_cmodel
)
2153 /* The range spanned by all instructions in the object is less
2154 than 2^31 bytes (2GB) and the distance from any instruction
2155 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
2156 than 2^31 bytes (2GB).
2158 The executable must be in the low 4TB of the virtual address
2161 sethi %hi(symbol), %temp1
2162 or %temp1, %lo(symbol), %reg */
2164 temp1
= temp
; /* op0 is allowed. */
2166 temp1
= gen_reg_rtx (DImode
);
2168 emit_insn (gen_rtx_SET (temp1
, gen_rtx_HIGH (DImode
, op1
)));
2169 emit_insn (gen_rtx_SET (op0
, gen_rtx_LO_SUM (DImode
, temp1
, op1
)));
2173 /* The range spanned by all instructions in the object is less
2174 than 2^31 bytes (2GB) and the distance from any instruction
2175 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
2176 than 2^31 bytes (2GB).
2178 The executable must be in the low 16TB of the virtual address
2181 sethi %h44(symbol), %temp1
2182 or %temp1, %m44(symbol), %temp2
2183 sllx %temp2, 12, %temp3
2184 or %temp3, %l44(symbol), %reg */
2189 temp3
= temp
; /* op0 is allowed. */
2193 temp1
= gen_reg_rtx (DImode
);
2194 temp2
= gen_reg_rtx (DImode
);
2195 temp3
= gen_reg_rtx (DImode
);
2198 emit_insn (gen_seth44 (temp1
, op1
));
2199 emit_insn (gen_setm44 (temp2
, temp1
, op1
));
2200 emit_insn (gen_rtx_SET (temp3
,
2201 gen_rtx_ASHIFT (DImode
, temp2
, GEN_INT (12))));
2202 emit_insn (gen_setl44 (op0
, temp3
, op1
));
2206 /* The range spanned by all instructions in the object is less
2207 than 2^31 bytes (2GB) and the distance from any instruction
2208 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
2209 than 2^31 bytes (2GB).
2211 The executable can be placed anywhere in the virtual address
2214 sethi %hh(symbol), %temp1
2215 sethi %lm(symbol), %temp2
2216 or %temp1, %hm(symbol), %temp3
2217 sllx %temp3, 32, %temp4
2218 or %temp4, %temp2, %temp5
2219 or %temp5, %lo(symbol), %reg */
2222 /* It is possible that one of the registers we got for operands[2]
2223 might coincide with that of operands[0] (which is why we made
2224 it TImode). Pick the other one to use as our scratch. */
2225 if (rtx_equal_p (temp
, op0
))
2227 gcc_assert (ti_temp
);
2228 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
2231 temp2
= temp
; /* op0 is _not_ allowed, see above. */
2238 temp1
= gen_reg_rtx (DImode
);
2239 temp2
= gen_reg_rtx (DImode
);
2240 temp3
= gen_reg_rtx (DImode
);
2241 temp4
= gen_reg_rtx (DImode
);
2242 temp5
= gen_reg_rtx (DImode
);
2245 emit_insn (gen_sethh (temp1
, op1
));
2246 emit_insn (gen_setlm (temp2
, op1
));
2247 emit_insn (gen_sethm (temp3
, temp1
, op1
));
2248 emit_insn (gen_rtx_SET (temp4
,
2249 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
2250 emit_insn (gen_rtx_SET (temp5
, gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2251 emit_insn (gen_setlo (op0
, temp5
, op1
));
2255 /* Old old old backwards compatibility kruft here.
2256 Essentially it is MEDLOW with a fixed 64-bit
2257 virtual base added to all data segment addresses.
2258 Text-segment stuff is computed like MEDANY, we can't
2259 reuse the code above because the relocation knobs
2262 Data segment: sethi %hi(symbol), %temp1
2263 add %temp1, EMBMEDANY_BASE_REG, %temp2
2264 or %temp2, %lo(symbol), %reg */
2265 if (data_segment_operand (op1
, GET_MODE (op1
)))
2269 temp1
= temp
; /* op0 is allowed. */
2274 temp1
= gen_reg_rtx (DImode
);
2275 temp2
= gen_reg_rtx (DImode
);
2278 emit_insn (gen_embmedany_sethi (temp1
, op1
));
2279 emit_insn (gen_embmedany_brsum (temp2
, temp1
));
2280 emit_insn (gen_embmedany_losum (op0
, temp2
, op1
));
2283 /* Text segment: sethi %uhi(symbol), %temp1
2284 sethi %hi(symbol), %temp2
2285 or %temp1, %ulo(symbol), %temp3
2286 sllx %temp3, 32, %temp4
2287 or %temp4, %temp2, %temp5
2288 or %temp5, %lo(symbol), %reg */
2293 /* It is possible that one of the registers we got for operands[2]
2294 might coincide with that of operands[0] (which is why we made
2295 it TImode). Pick the other one to use as our scratch. */
2296 if (rtx_equal_p (temp
, op0
))
2298 gcc_assert (ti_temp
);
2299 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
2302 temp2
= temp
; /* op0 is _not_ allowed, see above. */
2309 temp1
= gen_reg_rtx (DImode
);
2310 temp2
= gen_reg_rtx (DImode
);
2311 temp3
= gen_reg_rtx (DImode
);
2312 temp4
= gen_reg_rtx (DImode
);
2313 temp5
= gen_reg_rtx (DImode
);
2316 emit_insn (gen_embmedany_textuhi (temp1
, op1
));
2317 emit_insn (gen_embmedany_texthi (temp2
, op1
));
2318 emit_insn (gen_embmedany_textulo (temp3
, temp1
, op1
));
2319 emit_insn (gen_rtx_SET (temp4
,
2320 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
2321 emit_insn (gen_rtx_SET (temp5
, gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2322 emit_insn (gen_embmedany_textlo (op0
, temp5
, op1
));
2331 /* These avoid problems when cross compiling. If we do not
2332 go through all this hair then the optimizer will see
2333 invalid REG_EQUAL notes or in some cases none at all. */
2334 static rtx
gen_safe_HIGH64 (rtx
, HOST_WIDE_INT
);
2335 static rtx
gen_safe_SET64 (rtx
, HOST_WIDE_INT
);
2336 static rtx
gen_safe_OR64 (rtx
, HOST_WIDE_INT
);
2337 static rtx
gen_safe_XOR64 (rtx
, HOST_WIDE_INT
);
2339 /* The optimizer is not to assume anything about exactly
2340 which bits are set for a HIGH, they are unspecified.
2341 Unfortunately this leads to many missed optimizations
2342 during CSE. We mask out the non-HIGH bits, and matches
2343 a plain movdi, to alleviate this problem. */
2345 gen_safe_HIGH64 (rtx dest
, HOST_WIDE_INT val
)
2347 return gen_rtx_SET (dest
, GEN_INT (val
& ~(HOST_WIDE_INT
)0x3ff));
2351 gen_safe_SET64 (rtx dest
, HOST_WIDE_INT val
)
2353 return gen_rtx_SET (dest
, GEN_INT (val
));
2357 gen_safe_OR64 (rtx src
, HOST_WIDE_INT val
)
2359 return gen_rtx_IOR (DImode
, src
, GEN_INT (val
));
2363 gen_safe_XOR64 (rtx src
, HOST_WIDE_INT val
)
2365 return gen_rtx_XOR (DImode
, src
, GEN_INT (val
));
2368 /* Worker routines for 64-bit constant formation on arch64.
2369 One of the key things to be doing in these emissions is
2370 to create as many temp REGs as possible. This makes it
2371 possible for half-built constants to be used later when
2372 such values are similar to something required later on.
2373 Without doing this, the optimizer cannot see such
2376 static void sparc_emit_set_const64_quick1 (rtx
, rtx
,
2377 unsigned HOST_WIDE_INT
, int);
2380 sparc_emit_set_const64_quick1 (rtx op0
, rtx temp
,
2381 unsigned HOST_WIDE_INT low_bits
, int is_neg
)
2383 unsigned HOST_WIDE_INT high_bits
;
2386 high_bits
= (~low_bits
) & 0xffffffff;
2388 high_bits
= low_bits
;
2390 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
2393 emit_insn (gen_rtx_SET (op0
, gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2397 /* If we are XOR'ing with -1, then we should emit a one's complement
2398 instead. This way the combiner will notice logical operations
2399 such as ANDN later on and substitute. */
2400 if ((low_bits
& 0x3ff) == 0x3ff)
2402 emit_insn (gen_rtx_SET (op0
, gen_rtx_NOT (DImode
, temp
)));
2406 emit_insn (gen_rtx_SET (op0
,
2407 gen_safe_XOR64 (temp
,
2408 (-(HOST_WIDE_INT
)0x400
2409 | (low_bits
& 0x3ff)))));
2414 static void sparc_emit_set_const64_quick2 (rtx
, rtx
, unsigned HOST_WIDE_INT
,
2415 unsigned HOST_WIDE_INT
, int);
2418 sparc_emit_set_const64_quick2 (rtx op0
, rtx temp
,
2419 unsigned HOST_WIDE_INT high_bits
,
2420 unsigned HOST_WIDE_INT low_immediate
,
2425 if ((high_bits
& 0xfffffc00) != 0)
2427 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
2428 if ((high_bits
& ~0xfffffc00) != 0)
2429 emit_insn (gen_rtx_SET (op0
,
2430 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2436 emit_insn (gen_safe_SET64 (temp
, high_bits
));
2440 /* Now shift it up into place. */
2441 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, temp2
,
2442 GEN_INT (shift_count
))));
2444 /* If there is a low immediate part piece, finish up by
2445 putting that in as well. */
2446 if (low_immediate
!= 0)
2447 emit_insn (gen_rtx_SET (op0
, gen_safe_OR64 (op0
, low_immediate
)));
2450 static void sparc_emit_set_const64_longway (rtx
, rtx
, unsigned HOST_WIDE_INT
,
2451 unsigned HOST_WIDE_INT
);
2453 /* Full 64-bit constant decomposition. Even though this is the
2454 'worst' case, we still optimize a few things away. */
2456 sparc_emit_set_const64_longway (rtx op0
, rtx temp
,
2457 unsigned HOST_WIDE_INT high_bits
,
2458 unsigned HOST_WIDE_INT low_bits
)
2462 if (can_create_pseudo_p ())
2463 sub_temp
= gen_reg_rtx (DImode
);
2465 if ((high_bits
& 0xfffffc00) != 0)
2467 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
2468 if ((high_bits
& ~0xfffffc00) != 0)
2469 emit_insn (gen_rtx_SET (sub_temp
,
2470 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2476 emit_insn (gen_safe_SET64 (temp
, high_bits
));
2480 if (can_create_pseudo_p ())
2482 rtx temp2
= gen_reg_rtx (DImode
);
2483 rtx temp3
= gen_reg_rtx (DImode
);
2484 rtx temp4
= gen_reg_rtx (DImode
);
2486 emit_insn (gen_rtx_SET (temp4
, gen_rtx_ASHIFT (DImode
, sub_temp
,
2489 emit_insn (gen_safe_HIGH64 (temp2
, low_bits
));
2490 if ((low_bits
& ~0xfffffc00) != 0)
2492 emit_insn (gen_rtx_SET (temp3
,
2493 gen_safe_OR64 (temp2
, (low_bits
& 0x3ff))));
2494 emit_insn (gen_rtx_SET (op0
, gen_rtx_PLUS (DImode
, temp4
, temp3
)));
2498 emit_insn (gen_rtx_SET (op0
, gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2503 rtx low1
= GEN_INT ((low_bits
>> (32 - 12)) & 0xfff);
2504 rtx low2
= GEN_INT ((low_bits
>> (32 - 12 - 12)) & 0xfff);
2505 rtx low3
= GEN_INT ((low_bits
>> (32 - 12 - 12 - 8)) & 0x0ff);
2508 /* We are in the middle of reload, so this is really
2509 painful. However we do still make an attempt to
2510 avoid emitting truly stupid code. */
2511 if (low1
!= const0_rtx
)
2513 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, sub_temp
,
2514 GEN_INT (to_shift
))));
2515 emit_insn (gen_rtx_SET (op0
, gen_rtx_IOR (DImode
, op0
, low1
)));
2523 if (low2
!= const0_rtx
)
2525 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, sub_temp
,
2526 GEN_INT (to_shift
))));
2527 emit_insn (gen_rtx_SET (op0
, gen_rtx_IOR (DImode
, op0
, low2
)));
2535 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, sub_temp
,
2536 GEN_INT (to_shift
))));
2537 if (low3
!= const0_rtx
)
2538 emit_insn (gen_rtx_SET (op0
, gen_rtx_IOR (DImode
, op0
, low3
)));
2543 /* Analyze a 64-bit constant for certain properties. */
2544 static void analyze_64bit_constant (unsigned HOST_WIDE_INT
,
2545 unsigned HOST_WIDE_INT
,
2546 int *, int *, int *);
2549 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits
,
2550 unsigned HOST_WIDE_INT low_bits
,
2551 int *hbsp
, int *lbsp
, int *abbasp
)
2553 int lowest_bit_set
, highest_bit_set
, all_bits_between_are_set
;
2556 lowest_bit_set
= highest_bit_set
= -1;
2560 if ((lowest_bit_set
== -1)
2561 && ((low_bits
>> i
) & 1))
2563 if ((highest_bit_set
== -1)
2564 && ((high_bits
>> (32 - i
- 1)) & 1))
2565 highest_bit_set
= (64 - i
- 1);
2568 && ((highest_bit_set
== -1)
2569 || (lowest_bit_set
== -1)));
2575 if ((lowest_bit_set
== -1)
2576 && ((high_bits
>> i
) & 1))
2577 lowest_bit_set
= i
+ 32;
2578 if ((highest_bit_set
== -1)
2579 && ((low_bits
>> (32 - i
- 1)) & 1))
2580 highest_bit_set
= 32 - i
- 1;
2583 && ((highest_bit_set
== -1)
2584 || (lowest_bit_set
== -1)));
2586 /* If there are no bits set this should have gone out
2587 as one instruction! */
2588 gcc_assert (lowest_bit_set
!= -1 && highest_bit_set
!= -1);
2589 all_bits_between_are_set
= 1;
2590 for (i
= lowest_bit_set
; i
<= highest_bit_set
; i
++)
2594 if ((low_bits
& (1 << i
)) != 0)
2599 if ((high_bits
& (1 << (i
- 32))) != 0)
2602 all_bits_between_are_set
= 0;
2605 *hbsp
= highest_bit_set
;
2606 *lbsp
= lowest_bit_set
;
2607 *abbasp
= all_bits_between_are_set
;
2610 static int const64_is_2insns (unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
);
2613 const64_is_2insns (unsigned HOST_WIDE_INT high_bits
,
2614 unsigned HOST_WIDE_INT low_bits
)
2616 int highest_bit_set
, lowest_bit_set
, all_bits_between_are_set
;
2619 || high_bits
== 0xffffffff)
2622 analyze_64bit_constant (high_bits
, low_bits
,
2623 &highest_bit_set
, &lowest_bit_set
,
2624 &all_bits_between_are_set
);
2626 if ((highest_bit_set
== 63
2627 || lowest_bit_set
== 0)
2628 && all_bits_between_are_set
!= 0)
2631 if ((highest_bit_set
- lowest_bit_set
) < 21)
2637 static unsigned HOST_WIDE_INT
create_simple_focus_bits (unsigned HOST_WIDE_INT
,
2638 unsigned HOST_WIDE_INT
,
2641 static unsigned HOST_WIDE_INT
2642 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits
,
2643 unsigned HOST_WIDE_INT low_bits
,
2644 int lowest_bit_set
, int shift
)
2646 HOST_WIDE_INT hi
, lo
;
2648 if (lowest_bit_set
< 32)
2650 lo
= (low_bits
>> lowest_bit_set
) << shift
;
2651 hi
= ((high_bits
<< (32 - lowest_bit_set
)) << shift
);
2656 hi
= ((high_bits
>> (lowest_bit_set
- 32)) << shift
);
2658 gcc_assert (! (hi
& lo
));
2662 /* Here we are sure to be arch64 and this is an integer constant
2663 being loaded into a register. Emit the most efficient
2664 insn sequence possible. Detection of all the 1-insn cases
2665 has been done already. */
2667 sparc_emit_set_const64 (rtx op0
, rtx op1
)
2669 unsigned HOST_WIDE_INT high_bits
, low_bits
;
2670 int lowest_bit_set
, highest_bit_set
;
2671 int all_bits_between_are_set
;
2674 /* Sanity check that we know what we are working with. */
2675 gcc_assert (TARGET_ARCH64
2676 && (GET_CODE (op0
) == SUBREG
2677 || (REG_P (op0
) && ! SPARC_FP_REG_P (REGNO (op0
)))));
2679 if (! can_create_pseudo_p ())
2682 if (GET_CODE (op1
) != CONST_INT
)
2684 sparc_emit_set_symbolic_const64 (op0
, op1
, temp
);
2689 temp
= gen_reg_rtx (DImode
);
2691 high_bits
= ((INTVAL (op1
) >> 32) & 0xffffffff);
2692 low_bits
= (INTVAL (op1
) & 0xffffffff);
2694 /* low_bits bits 0 --> 31
2695 high_bits bits 32 --> 63 */
2697 analyze_64bit_constant (high_bits
, low_bits
,
2698 &highest_bit_set
, &lowest_bit_set
,
2699 &all_bits_between_are_set
);
2701 /* First try for a 2-insn sequence. */
2703 /* These situations are preferred because the optimizer can
2704 * do more things with them:
2706 * sllx %reg, shift, %reg
2708 * srlx %reg, shift, %reg
2709 * 3) mov some_small_const, %reg
2710 * sllx %reg, shift, %reg
2712 if (((highest_bit_set
== 63
2713 || lowest_bit_set
== 0)
2714 && all_bits_between_are_set
!= 0)
2715 || ((highest_bit_set
- lowest_bit_set
) < 12))
2717 HOST_WIDE_INT the_const
= -1;
2718 int shift
= lowest_bit_set
;
2720 if ((highest_bit_set
!= 63
2721 && lowest_bit_set
!= 0)
2722 || all_bits_between_are_set
== 0)
2725 create_simple_focus_bits (high_bits
, low_bits
,
2728 else if (lowest_bit_set
== 0)
2729 shift
= -(63 - highest_bit_set
);
2731 gcc_assert (SPARC_SIMM13_P (the_const
));
2732 gcc_assert (shift
!= 0);
2734 emit_insn (gen_safe_SET64 (temp
, the_const
));
2736 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, temp
,
2739 emit_insn (gen_rtx_SET (op0
, gen_rtx_LSHIFTRT (DImode
, temp
,
2740 GEN_INT (-shift
))));
2744 /* Now a range of 22 or less bits set somewhere.
2745 * 1) sethi %hi(focus_bits), %reg
2746 * sllx %reg, shift, %reg
2747 * 2) sethi %hi(focus_bits), %reg
2748 * srlx %reg, shift, %reg
2750 if ((highest_bit_set
- lowest_bit_set
) < 21)
2752 unsigned HOST_WIDE_INT focus_bits
=
2753 create_simple_focus_bits (high_bits
, low_bits
,
2754 lowest_bit_set
, 10);
2756 gcc_assert (SPARC_SETHI_P (focus_bits
));
2757 gcc_assert (lowest_bit_set
!= 10);
2759 emit_insn (gen_safe_HIGH64 (temp
, focus_bits
));
2761 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2762 if (lowest_bit_set
< 10)
2763 emit_insn (gen_rtx_SET (op0
,
2764 gen_rtx_LSHIFTRT (DImode
, temp
,
2765 GEN_INT (10 - lowest_bit_set
))));
2766 else if (lowest_bit_set
> 10)
2767 emit_insn (gen_rtx_SET (op0
,
2768 gen_rtx_ASHIFT (DImode
, temp
,
2769 GEN_INT (lowest_bit_set
- 10))));
2773 /* 1) sethi %hi(low_bits), %reg
2774 * or %reg, %lo(low_bits), %reg
2775 * 2) sethi %hi(~low_bits), %reg
2776 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2779 || high_bits
== 0xffffffff)
2781 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
,
2782 (high_bits
== 0xffffffff));
2786 /* Now, try 3-insn sequences. */
2788 /* 1) sethi %hi(high_bits), %reg
2789 * or %reg, %lo(high_bits), %reg
2790 * sllx %reg, 32, %reg
2794 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, 0, 32);
2798 /* We may be able to do something quick
2799 when the constant is negated, so try that. */
2800 if (const64_is_2insns ((~high_bits
) & 0xffffffff,
2801 (~low_bits
) & 0xfffffc00))
2803 /* NOTE: The trailing bits get XOR'd so we need the
2804 non-negated bits, not the negated ones. */
2805 unsigned HOST_WIDE_INT trailing_bits
= low_bits
& 0x3ff;
2807 if ((((~high_bits
) & 0xffffffff) == 0
2808 && ((~low_bits
) & 0x80000000) == 0)
2809 || (((~high_bits
) & 0xffffffff) == 0xffffffff
2810 && ((~low_bits
) & 0x80000000) != 0))
2812 unsigned HOST_WIDE_INT fast_int
= (~low_bits
& 0xffffffff);
2814 if ((SPARC_SETHI_P (fast_int
)
2815 && (~high_bits
& 0xffffffff) == 0)
2816 || SPARC_SIMM13_P (fast_int
))
2817 emit_insn (gen_safe_SET64 (temp
, fast_int
));
2819 sparc_emit_set_const64 (temp
, GEN_INT (fast_int
));
2824 negated_const
= GEN_INT (((~low_bits
) & 0xfffffc00) |
2825 (((HOST_WIDE_INT
)((~high_bits
) & 0xffffffff))<<32));
2826 sparc_emit_set_const64 (temp
, negated_const
);
2829 /* If we are XOR'ing with -1, then we should emit a one's complement
2830 instead. This way the combiner will notice logical operations
2831 such as ANDN later on and substitute. */
2832 if (trailing_bits
== 0x3ff)
2834 emit_insn (gen_rtx_SET (op0
, gen_rtx_NOT (DImode
, temp
)));
2838 emit_insn (gen_rtx_SET (op0
,
2839 gen_safe_XOR64 (temp
,
2840 (-0x400 | trailing_bits
))));
2845 /* 1) sethi %hi(xxx), %reg
2846 * or %reg, %lo(xxx), %reg
2847 * sllx %reg, yyy, %reg
2849 * ??? This is just a generalized version of the low_bits==0
2850 * thing above, FIXME...
2852 if ((highest_bit_set
- lowest_bit_set
) < 32)
2854 unsigned HOST_WIDE_INT focus_bits
=
2855 create_simple_focus_bits (high_bits
, low_bits
,
2858 /* We can't get here in this state. */
2859 gcc_assert (highest_bit_set
>= 32 && lowest_bit_set
< 32);
2861 /* So what we know is that the set bits straddle the
2862 middle of the 64-bit word. */
2863 sparc_emit_set_const64_quick2 (op0
, temp
,
2869 /* 1) sethi %hi(high_bits), %reg
2870 * or %reg, %lo(high_bits), %reg
2871 * sllx %reg, 32, %reg
2872 * or %reg, low_bits, %reg
2874 if (SPARC_SIMM13_P (low_bits
) && ((int)low_bits
> 0))
2876 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_bits
, 32);
2880 /* The easiest way when all else fails, is full decomposition. */
2881 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
);
2884 /* Implement TARGET_FIXED_CONDITION_CODE_REGS. */
2887 sparc_fixed_condition_code_regs (unsigned int *p1
, unsigned int *p2
)
2889 *p1
= SPARC_ICC_REG
;
2890 *p2
= SPARC_FCC_REG
;
2894 /* Implement TARGET_MIN_ARITHMETIC_PRECISION. */
2897 sparc_min_arithmetic_precision (void)
2902 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2903 return the mode to be used for the comparison. For floating-point,
2904 CCFP[E]mode is used. CCNZmode should be used when the first operand
2905 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2906 processing is needed. */
2909 select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
2911 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2937 else if ((GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
2938 || GET_CODE (x
) == NEG
|| GET_CODE (x
) == ASHIFT
)
2941 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2948 /* This is for the cmp<mode>_sne pattern. */
2949 if (GET_CODE (x
) == NOT
&& y
== constm1_rtx
)
2951 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2957 /* This is for the [u]addvdi4_sp32 and [u]subvdi4_sp32 patterns. */
2958 if (!TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2960 if (GET_CODE (y
) == UNSPEC
2961 && (XINT (y
, 1) == UNSPEC_ADDV
2962 || XINT (y
, 1) == UNSPEC_SUBV
2963 || XINT (y
, 1) == UNSPEC_NEGV
))
2969 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2976 /* Emit the compare insn and return the CC reg for a CODE comparison
2977 with operands X and Y. */
2980 gen_compare_reg_1 (enum rtx_code code
, rtx x
, rtx y
)
2985 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
2988 mode
= SELECT_CC_MODE (code
, x
, y
);
2990 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2991 fcc regs (cse can't tell they're really call clobbered regs and will
2992 remove a duplicate comparison even if there is an intervening function
2993 call - it will then try to reload the cc reg via an int reg which is why
2994 we need the movcc patterns). It is possible to provide the movcc
2995 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2996 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2997 to tell cse that CCFPE mode registers (even pseudos) are call
3000 /* ??? This is an experiment. Rather than making changes to cse which may
3001 or may not be easy/clean, we do our own cse. This is possible because
3002 we will generate hard registers. Cse knows they're call clobbered (it
3003 doesn't know the same thing about pseudos). If we guess wrong, no big
3004 deal, but if we win, great! */
3006 if (TARGET_V9
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
3007 #if 1 /* experiment */
3010 /* We cycle through the registers to ensure they're all exercised. */
3011 static int next_fcc_reg
= 0;
3012 /* Previous x,y for each fcc reg. */
3013 static rtx prev_args
[4][2];
3015 /* Scan prev_args for x,y. */
3016 for (reg
= 0; reg
< 4; reg
++)
3017 if (prev_args
[reg
][0] == x
&& prev_args
[reg
][1] == y
)
3022 prev_args
[reg
][0] = x
;
3023 prev_args
[reg
][1] = y
;
3024 next_fcc_reg
= (next_fcc_reg
+ 1) & 3;
3026 cc_reg
= gen_rtx_REG (mode
, reg
+ SPARC_FIRST_V9_FCC_REG
);
3029 cc_reg
= gen_reg_rtx (mode
);
3030 #endif /* ! experiment */
3031 else if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
3032 cc_reg
= gen_rtx_REG (mode
, SPARC_FCC_REG
);
3034 cc_reg
= gen_rtx_REG (mode
, SPARC_ICC_REG
);
3036 /* We shouldn't get there for TFmode if !TARGET_HARD_QUAD. If we do, this
3037 will only result in an unrecognizable insn so no point in asserting. */
3038 emit_insn (gen_rtx_SET (cc_reg
, gen_rtx_COMPARE (mode
, x
, y
)));
3044 /* Emit the compare insn and return the CC reg for the comparison in CMP. */
3047 gen_compare_reg (rtx cmp
)
3049 return gen_compare_reg_1 (GET_CODE (cmp
), XEXP (cmp
, 0), XEXP (cmp
, 1));
3052 /* This function is used for v9 only.
3053 DEST is the target of the Scc insn.
3054 CODE is the code for an Scc's comparison.
3055 X and Y are the values we compare.
3057 This function is needed to turn
3060 (gt (reg:CCX 100 %icc)
3064 (gt:DI (reg:CCX 100 %icc)
3067 IE: The instruction recognizer needs to see the mode of the comparison to
3068 find the right instruction. We could use "gt:DI" right in the
3069 define_expand, but leaving it out allows us to handle DI, SI, etc. */
3072 gen_v9_scc (rtx dest
, enum rtx_code compare_code
, rtx x
, rtx y
)
3075 && (GET_MODE (x
) == DImode
3076 || GET_MODE (dest
) == DImode
))
3079 /* Try to use the movrCC insns. */
3081 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
3083 && v9_regcmp_p (compare_code
))
3088 /* Special case for op0 != 0. This can be done with one instruction if
3091 if (compare_code
== NE
3092 && GET_MODE (dest
) == DImode
3093 && rtx_equal_p (op0
, dest
))
3095 emit_insn (gen_rtx_SET (dest
,
3096 gen_rtx_IF_THEN_ELSE (DImode
,
3097 gen_rtx_fmt_ee (compare_code
, DImode
,
3104 if (reg_overlap_mentioned_p (dest
, op0
))
3106 /* Handle the case where dest == x.
3107 We "early clobber" the result. */
3108 op0
= gen_reg_rtx (GET_MODE (x
));
3109 emit_move_insn (op0
, x
);
3112 emit_insn (gen_rtx_SET (dest
, const0_rtx
));
3113 if (GET_MODE (op0
) != DImode
)
3115 temp
= gen_reg_rtx (DImode
);
3116 convert_move (temp
, op0
, 0);
3120 emit_insn (gen_rtx_SET (dest
,
3121 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
3122 gen_rtx_fmt_ee (compare_code
, DImode
,
3130 x
= gen_compare_reg_1 (compare_code
, x
, y
);
3133 emit_insn (gen_rtx_SET (dest
, const0_rtx
));
3134 emit_insn (gen_rtx_SET (dest
,
3135 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
3136 gen_rtx_fmt_ee (compare_code
,
3137 GET_MODE (x
), x
, y
),
3138 const1_rtx
, dest
)));
3144 /* Emit an scc insn. For seq, sne, sgeu, and sltu, we can do this
3145 without jumps using the addx/subx instructions. */
3148 emit_scc_insn (rtx operands
[])
3154 /* The quad-word fp compare library routines all return nonzero to indicate
3155 true, which is different from the equivalent libgcc routines, so we must
3156 handle them specially here. */
3157 if (GET_MODE (operands
[2]) == TFmode
&& ! TARGET_HARD_QUAD
)
3159 operands
[1] = sparc_emit_float_lib_cmp (operands
[2], operands
[3],
3160 GET_CODE (operands
[1]));
3161 operands
[2] = XEXP (operands
[1], 0);
3162 operands
[3] = XEXP (operands
[1], 1);
3165 code
= GET_CODE (operands
[1]);
3168 mode
= GET_MODE (x
);
3170 /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has
3171 more applications). The exception to this is "reg != 0" which can
3172 be done in one instruction on v9 (so we do it). */
3173 if ((code
== EQ
|| code
== NE
) && (mode
== SImode
|| mode
== DImode
))
3175 if (y
!= const0_rtx
)
3176 x
= force_reg (mode
, gen_rtx_XOR (mode
, x
, y
));
3178 rtx pat
= gen_rtx_SET (operands
[0],
3179 gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
3182 /* If we can use addx/subx or addxc, add a clobber for CC. */
3183 if (mode
== SImode
|| (code
== NE
&& TARGET_VIS3
))
3186 = gen_rtx_CLOBBER (VOIDmode
,
3187 gen_rtx_REG (mode
== SImode
? CCmode
: CCXmode
,
3189 pat
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, pat
, clobber
));
3196 /* We can do LTU in DImode using the addxc instruction with VIS3. */
3199 && !((code
== LTU
|| code
== GTU
) && TARGET_VIS3
)
3200 && gen_v9_scc (operands
[0], code
, x
, y
))
3203 /* We can do LTU and GEU using the addx/subx instructions too. And
3204 for GTU/LEU, if both operands are registers swap them and fall
3205 back to the easy case. */
3206 if (code
== GTU
|| code
== LEU
)
3208 if ((GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
3209 && (GET_CODE (y
) == REG
|| GET_CODE (y
) == SUBREG
))
3214 code
= swap_condition (code
);
3218 if (code
== LTU
|| code
== GEU
)
3220 emit_insn (gen_rtx_SET (operands
[0],
3221 gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
3222 gen_compare_reg_1 (code
, x
, y
),
3227 /* All the posibilities to use addx/subx based sequences has been
3228 exhausted, try for a 3 instruction sequence using v9 conditional
3230 if (TARGET_V9
&& gen_v9_scc (operands
[0], code
, x
, y
))
3233 /* Nope, do branches. */
3237 /* Emit a conditional jump insn for the v9 architecture using comparison code
3238 CODE and jump target LABEL.
3239 This function exists to take advantage of the v9 brxx insns. */
3242 emit_v9_brxx_insn (enum rtx_code code
, rtx op0
, rtx label
)
3244 emit_jump_insn (gen_rtx_SET (pc_rtx
,
3245 gen_rtx_IF_THEN_ELSE (VOIDmode
,
3246 gen_rtx_fmt_ee (code
, GET_MODE (op0
),
3248 gen_rtx_LABEL_REF (VOIDmode
, label
),
3252 /* Emit a conditional jump insn for the UA2011 architecture using
3253 comparison code CODE and jump target LABEL. This function exists
3254 to take advantage of the UA2011 Compare and Branch insns. */
3257 emit_cbcond_insn (enum rtx_code code
, rtx op0
, rtx op1
, rtx label
)
3261 if_then_else
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
3262 gen_rtx_fmt_ee(code
, GET_MODE(op0
),
3264 gen_rtx_LABEL_REF (VOIDmode
, label
),
3267 emit_jump_insn (gen_rtx_SET (pc_rtx
, if_then_else
));
3271 emit_conditional_branch_insn (rtx operands
[])
3273 /* The quad-word fp compare library routines all return nonzero to indicate
3274 true, which is different from the equivalent libgcc routines, so we must
3275 handle them specially here. */
3276 if (GET_MODE (operands
[1]) == TFmode
&& ! TARGET_HARD_QUAD
)
3278 operands
[0] = sparc_emit_float_lib_cmp (operands
[1], operands
[2],
3279 GET_CODE (operands
[0]));
3280 operands
[1] = XEXP (operands
[0], 0);
3281 operands
[2] = XEXP (operands
[0], 1);
3284 /* If we can tell early on that the comparison is against a constant
3285 that won't fit in the 5-bit signed immediate field of a cbcond,
3286 use one of the other v9 conditional branch sequences. */
3288 && GET_CODE (operands
[1]) == REG
3289 && (GET_MODE (operands
[1]) == SImode
3290 || (TARGET_ARCH64
&& GET_MODE (operands
[1]) == DImode
))
3291 && (GET_CODE (operands
[2]) != CONST_INT
3292 || SPARC_SIMM5_P (INTVAL (operands
[2]))))
3294 emit_cbcond_insn (GET_CODE (operands
[0]), operands
[1], operands
[2], operands
[3]);
3298 if (TARGET_ARCH64
&& operands
[2] == const0_rtx
3299 && GET_CODE (operands
[1]) == REG
3300 && GET_MODE (operands
[1]) == DImode
)
3302 emit_v9_brxx_insn (GET_CODE (operands
[0]), operands
[1], operands
[3]);
3306 operands
[1] = gen_compare_reg (operands
[0]);
3307 operands
[2] = const0_rtx
;
3308 operands
[0] = gen_rtx_fmt_ee (GET_CODE (operands
[0]), VOIDmode
,
3309 operands
[1], operands
[2]);
3310 emit_jump_insn (gen_cbranchcc4 (operands
[0], operands
[1], operands
[2],
3315 /* Generate a DFmode part of a hard TFmode register.
3316 REG is the TFmode hard register, LOW is 1 for the
3317 low 64bit of the register and 0 otherwise.
3320 gen_df_reg (rtx reg
, int low
)
3322 int regno
= REGNO (reg
);
3324 if ((WORDS_BIG_ENDIAN
== 0) ^ (low
!= 0))
3325 regno
+= (TARGET_ARCH64
&& SPARC_INT_REG_P (regno
)) ? 1 : 2;
3326 return gen_rtx_REG (DFmode
, regno
);
3329 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
3330 Unlike normal calls, TFmode operands are passed by reference. It is
3331 assumed that no more than 3 operands are required. */
3334 emit_soft_tfmode_libcall (const char *func_name
, int nargs
, rtx
*operands
)
3336 rtx ret_slot
= NULL
, arg
[3], func_sym
;
3339 /* We only expect to be called for conversions, unary, and binary ops. */
3340 gcc_assert (nargs
== 2 || nargs
== 3);
3342 for (i
= 0; i
< nargs
; ++i
)
3344 rtx this_arg
= operands
[i
];
3347 /* TFmode arguments and return values are passed by reference. */
3348 if (GET_MODE (this_arg
) == TFmode
)
3350 int force_stack_temp
;
3352 force_stack_temp
= 0;
3353 if (TARGET_BUGGY_QP_LIB
&& i
== 0)
3354 force_stack_temp
= 1;
3356 if (GET_CODE (this_arg
) == MEM
3357 && ! force_stack_temp
)
3359 tree expr
= MEM_EXPR (this_arg
);
3361 mark_addressable (expr
);
3362 this_arg
= XEXP (this_arg
, 0);
3364 else if (CONSTANT_P (this_arg
)
3365 && ! force_stack_temp
)
3367 this_slot
= force_const_mem (TFmode
, this_arg
);
3368 this_arg
= XEXP (this_slot
, 0);
3372 this_slot
= assign_stack_temp (TFmode
, GET_MODE_SIZE (TFmode
));
3374 /* Operand 0 is the return value. We'll copy it out later. */
3376 emit_move_insn (this_slot
, this_arg
);
3378 ret_slot
= this_slot
;
3380 this_arg
= XEXP (this_slot
, 0);
3387 func_sym
= gen_rtx_SYMBOL_REF (Pmode
, func_name
);
3389 if (GET_MODE (operands
[0]) == TFmode
)
3392 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 2,
3393 arg
[0], GET_MODE (arg
[0]),
3394 arg
[1], GET_MODE (arg
[1]));
3396 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 3,
3397 arg
[0], GET_MODE (arg
[0]),
3398 arg
[1], GET_MODE (arg
[1]),
3399 arg
[2], GET_MODE (arg
[2]));
3402 emit_move_insn (operands
[0], ret_slot
);
3408 gcc_assert (nargs
== 2);
3410 ret
= emit_library_call_value (func_sym
, operands
[0], LCT_NORMAL
,
3411 GET_MODE (operands
[0]), 1,
3412 arg
[1], GET_MODE (arg
[1]));
3414 if (ret
!= operands
[0])
3415 emit_move_insn (operands
[0], ret
);
3419 /* Expand soft-float TFmode calls to sparc abi routines. */
3422 emit_soft_tfmode_binop (enum rtx_code code
, rtx
*operands
)
3444 emit_soft_tfmode_libcall (func
, 3, operands
);
3448 emit_soft_tfmode_unop (enum rtx_code code
, rtx
*operands
)
3452 gcc_assert (code
== SQRT
);
3455 emit_soft_tfmode_libcall (func
, 2, operands
);
3459 emit_soft_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
3466 switch (GET_MODE (operands
[1]))
3479 case FLOAT_TRUNCATE
:
3480 switch (GET_MODE (operands
[0]))
3494 switch (GET_MODE (operands
[1]))
3499 operands
[1] = gen_rtx_SIGN_EXTEND (DImode
, operands
[1]);
3509 case UNSIGNED_FLOAT
:
3510 switch (GET_MODE (operands
[1]))
3515 operands
[1] = gen_rtx_ZERO_EXTEND (DImode
, operands
[1]);
3526 switch (GET_MODE (operands
[0]))
3540 switch (GET_MODE (operands
[0]))
3557 emit_soft_tfmode_libcall (func
, 2, operands
);
3560 /* Expand a hard-float tfmode operation. All arguments must be in
3564 emit_hard_tfmode_operation (enum rtx_code code
, rtx
*operands
)
3568 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
3570 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
3571 op
= gen_rtx_fmt_e (code
, GET_MODE (operands
[0]), operands
[1]);
3575 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
3576 operands
[2] = force_reg (GET_MODE (operands
[2]), operands
[2]);
3577 op
= gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
3578 operands
[1], operands
[2]);
3581 if (register_operand (operands
[0], VOIDmode
))
3584 dest
= gen_reg_rtx (GET_MODE (operands
[0]));
3586 emit_insn (gen_rtx_SET (dest
, op
));
3588 if (dest
!= operands
[0])
3589 emit_move_insn (operands
[0], dest
);
3593 emit_tfmode_binop (enum rtx_code code
, rtx
*operands
)
3595 if (TARGET_HARD_QUAD
)
3596 emit_hard_tfmode_operation (code
, operands
);
3598 emit_soft_tfmode_binop (code
, operands
);
3602 emit_tfmode_unop (enum rtx_code code
, rtx
*operands
)
3604 if (TARGET_HARD_QUAD
)
3605 emit_hard_tfmode_operation (code
, operands
);
3607 emit_soft_tfmode_unop (code
, operands
);
3611 emit_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
3613 if (TARGET_HARD_QUAD
)
3614 emit_hard_tfmode_operation (code
, operands
);
3616 emit_soft_tfmode_cvt (code
, operands
);
3619 /* Return nonzero if a branch/jump/call instruction will be emitting
3620 nop into its delay slot. */
3623 empty_delay_slot (rtx_insn
*insn
)
3627 /* If no previous instruction (should not happen), return true. */
3628 if (PREV_INSN (insn
) == NULL
)
3631 seq
= NEXT_INSN (PREV_INSN (insn
));
3632 if (GET_CODE (PATTERN (seq
)) == SEQUENCE
)
3638 /* Return nonzero if we should emit a nop after a cbcond instruction.
3639 The cbcond instruction does not have a delay slot, however there is
3640 a severe performance penalty if a control transfer appears right
3641 after a cbcond. Therefore we emit a nop when we detect this
3645 emit_cbcond_nop (rtx_insn
*insn
)
3647 rtx next
= next_active_insn (insn
);
3652 if (NONJUMP_INSN_P (next
)
3653 && GET_CODE (PATTERN (next
)) == SEQUENCE
)
3654 next
= XVECEXP (PATTERN (next
), 0, 0);
3655 else if (CALL_P (next
)
3656 && GET_CODE (PATTERN (next
)) == PARALLEL
)
3658 rtx delay
= XVECEXP (PATTERN (next
), 0, 1);
3660 if (GET_CODE (delay
) == RETURN
)
3662 /* It's a sibling call. Do not emit the nop if we're going
3663 to emit something other than the jump itself as the first
3664 instruction of the sibcall sequence. */
3665 if (sparc_leaf_function_p
|| TARGET_FLAT
)
3670 if (NONJUMP_INSN_P (next
))
3676 /* Return nonzero if TRIAL can go into the call delay slot. */
3679 eligible_for_call_delay (rtx_insn
*trial
)
3683 if (get_attr_in_branch_delay (trial
) == IN_BRANCH_DELAY_FALSE
)
3687 call __tls_get_addr, %tgd_call (foo)
3688 add %l7, %o0, %o0, %tgd_add (foo)
3689 while Sun as/ld does not. */
3690 if (TARGET_GNU_TLS
|| !TARGET_TLS
)
3693 pat
= PATTERN (trial
);
3695 /* We must reject tgd_add{32|64}, i.e.
3696 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD)))
3697 and tldm_add{32|64}, i.e.
3698 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM)))
3700 if (GET_CODE (pat
) == SET
3701 && GET_CODE (SET_SRC (pat
)) == PLUS
)
3703 rtx unspec
= XEXP (SET_SRC (pat
), 1);
3705 if (GET_CODE (unspec
) == UNSPEC
3706 && (XINT (unspec
, 1) == UNSPEC_TLSGD
3707 || XINT (unspec
, 1) == UNSPEC_TLSLDM
))
3714 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
3715 instruction. RETURN_P is true if the v9 variant 'return' is to be
3716 considered in the test too.
3718 TRIAL must be a SET whose destination is a REG appropriate for the
3719 'restore' instruction or, if RETURN_P is true, for the 'return'
3723 eligible_for_restore_insn (rtx trial
, bool return_p
)
3725 rtx pat
= PATTERN (trial
);
3726 rtx src
= SET_SRC (pat
);
3727 bool src_is_freg
= false;
3730 /* Since we now can do moves between float and integer registers when
3731 VIS3 is enabled, we have to catch this case. We can allow such
3732 moves when doing a 'return' however. */
3734 if (GET_CODE (src_reg
) == SUBREG
)
3735 src_reg
= SUBREG_REG (src_reg
);
3736 if (GET_CODE (src_reg
) == REG
3737 && SPARC_FP_REG_P (REGNO (src_reg
)))
3740 /* The 'restore src,%g0,dest' pattern for word mode and below. */
3741 if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
3742 && arith_operand (src
, GET_MODE (src
))
3746 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
3748 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
3751 /* The 'restore src,%g0,dest' pattern for double-word mode. */
3752 else if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
3753 && arith_double_operand (src
, GET_MODE (src
))
3755 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
3757 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
3758 else if (! TARGET_FPU
&& register_operand (src
, SFmode
))
3761 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
3762 else if (! TARGET_FPU
&& TARGET_ARCH64
&& register_operand (src
, DFmode
))
3765 /* If we have the 'return' instruction, anything that does not use
3766 local or output registers and can go into a delay slot wins. */
3767 else if (return_p
&& TARGET_V9
&& !epilogue_renumber (&pat
, 1))
3770 /* The 'restore src1,src2,dest' pattern for SImode. */
3771 else if (GET_CODE (src
) == PLUS
3772 && register_operand (XEXP (src
, 0), SImode
)
3773 && arith_operand (XEXP (src
, 1), SImode
))
3776 /* The 'restore src1,src2,dest' pattern for DImode. */
3777 else if (GET_CODE (src
) == PLUS
3778 && register_operand (XEXP (src
, 0), DImode
)
3779 && arith_double_operand (XEXP (src
, 1), DImode
))
3782 /* The 'restore src1,%lo(src2),dest' pattern. */
3783 else if (GET_CODE (src
) == LO_SUM
3784 && ! TARGET_CM_MEDMID
3785 && ((register_operand (XEXP (src
, 0), SImode
)
3786 && immediate_operand (XEXP (src
, 1), SImode
))
3788 && register_operand (XEXP (src
, 0), DImode
)
3789 && immediate_operand (XEXP (src
, 1), DImode
))))
3792 /* The 'restore src,src,dest' pattern. */
3793 else if (GET_CODE (src
) == ASHIFT
3794 && (register_operand (XEXP (src
, 0), SImode
)
3795 || register_operand (XEXP (src
, 0), DImode
))
3796 && XEXP (src
, 1) == const1_rtx
)
3802 /* Return nonzero if TRIAL can go into the function return's delay slot. */
3805 eligible_for_return_delay (rtx_insn
*trial
)
3810 /* If the function uses __builtin_eh_return, the eh_return machinery
3811 occupies the delay slot. */
3812 if (crtl
->calls_eh_return
)
3815 if (get_attr_in_branch_delay (trial
) == IN_BRANCH_DELAY_FALSE
)
3818 /* In the case of a leaf or flat function, anything can go into the slot. */
3819 if (sparc_leaf_function_p
|| TARGET_FLAT
)
3822 if (!NONJUMP_INSN_P (trial
))
3825 pat
= PATTERN (trial
);
3826 if (GET_CODE (pat
) == PARALLEL
)
3832 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
3834 rtx expr
= XVECEXP (pat
, 0, i
);
3835 if (GET_CODE (expr
) != SET
)
3837 if (GET_CODE (SET_DEST (expr
)) != REG
)
3839 regno
= REGNO (SET_DEST (expr
));
3840 if (regno
>= 8 && regno
< 24)
3843 return !epilogue_renumber (&pat
, 1);
3846 if (GET_CODE (pat
) != SET
)
3849 if (GET_CODE (SET_DEST (pat
)) != REG
)
3852 regno
= REGNO (SET_DEST (pat
));
3854 /* Otherwise, only operations which can be done in tandem with
3855 a `restore' or `return' insn can go into the delay slot. */
3856 if (regno
>= 8 && regno
< 24)
3859 /* If this instruction sets up floating point register and we have a return
3860 instruction, it can probably go in. But restore will not work
3862 if (! SPARC_INT_REG_P (regno
))
3863 return TARGET_V9
&& !epilogue_renumber (&pat
, 1);
3865 return eligible_for_restore_insn (trial
, true);
3868 /* Return nonzero if TRIAL can go into the sibling call's delay slot. */
3871 eligible_for_sibcall_delay (rtx_insn
*trial
)
3875 if (get_attr_in_branch_delay (trial
) == IN_BRANCH_DELAY_FALSE
)
3878 if (!NONJUMP_INSN_P (trial
))
3881 pat
= PATTERN (trial
);
3883 if (sparc_leaf_function_p
|| TARGET_FLAT
)
3885 /* If the tail call is done using the call instruction,
3886 we have to restore %o7 in the delay slot. */
3887 if (LEAF_SIBCALL_SLOT_RESERVED_P
)
3890 /* %g1 is used to build the function address */
3891 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 1), pat
))
3897 if (GET_CODE (pat
) != SET
)
3900 /* Otherwise, only operations which can be done in tandem with
3901 a `restore' insn can go into the delay slot. */
3902 if (GET_CODE (SET_DEST (pat
)) != REG
3903 || (REGNO (SET_DEST (pat
)) >= 8 && REGNO (SET_DEST (pat
)) < 24)
3904 || ! SPARC_INT_REG_P (REGNO (SET_DEST (pat
))))
3907 /* If it mentions %o7, it can't go in, because sibcall will clobber it
3909 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 15), pat
))
3912 return eligible_for_restore_insn (trial
, false);
3915 /* Determine if it's legal to put X into the constant pool. This
3916 is not possible if X contains the address of a symbol that is
3917 not constant (TLS) or not known at final link time (PIC). */
3920 sparc_cannot_force_const_mem (machine_mode mode
, rtx x
)
3922 switch (GET_CODE (x
))
3925 case CONST_WIDE_INT
:
3928 /* Accept all non-symbolic constants. */
3932 /* Labels are OK iff we are non-PIC. */
3933 return flag_pic
!= 0;
3936 /* 'Naked' TLS symbol references are never OK,
3937 non-TLS symbols are OK iff we are non-PIC. */
3938 if (SYMBOL_REF_TLS_MODEL (x
))
3941 return flag_pic
!= 0;
3944 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0));
3947 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0))
3948 || sparc_cannot_force_const_mem (mode
, XEXP (x
, 1));
3956 /* Global Offset Table support. */
3957 static GTY(()) rtx got_helper_rtx
= NULL_RTX
;
3958 static GTY(()) rtx global_offset_table_rtx
= NULL_RTX
;
3960 /* Return the SYMBOL_REF for the Global Offset Table. */
3962 static GTY(()) rtx sparc_got_symbol
= NULL_RTX
;
3967 if (!sparc_got_symbol
)
3968 sparc_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3970 return sparc_got_symbol
;
3973 /* Ensure that we are not using patterns that are not OK with PIC. */
3983 op
= recog_data
.operand
[i
];
3984 gcc_assert (GET_CODE (op
) != SYMBOL_REF
3985 && (GET_CODE (op
) != CONST
3986 || (GET_CODE (XEXP (op
, 0)) == MINUS
3987 && XEXP (XEXP (op
, 0), 0) == sparc_got ()
3988 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST
)));
3996 /* Return true if X is an address which needs a temporary register when
3997 reloaded while generating PIC code. */
4000 pic_address_needs_scratch (rtx x
)
4002 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
4003 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
4004 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
4005 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4006 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
4012 /* Determine if a given RTX is a valid constant. We already know this
4013 satisfies CONSTANT_P. */
4016 sparc_legitimate_constant_p (machine_mode mode
, rtx x
)
4018 switch (GET_CODE (x
))
4022 if (sparc_tls_referenced_p (x
))
4027 /* Floating point constants are generally not ok.
4028 The only exception is 0.0 and all-ones in VIS. */
4030 && SCALAR_FLOAT_MODE_P (mode
)
4031 && (const_zero_operand (x
, mode
)
4032 || const_all_ones_operand (x
, mode
)))
4038 /* Vector constants are generally not ok.
4039 The only exception is 0 or -1 in VIS. */
4041 && (const_zero_operand (x
, mode
)
4042 || const_all_ones_operand (x
, mode
)))
4054 /* Determine if a given RTX is a valid constant address. */
4057 constant_address_p (rtx x
)
4059 switch (GET_CODE (x
))
4067 if (flag_pic
&& pic_address_needs_scratch (x
))
4069 return sparc_legitimate_constant_p (Pmode
, x
);
4072 return !flag_pic
&& sparc_legitimate_constant_p (Pmode
, x
);
4079 /* Nonzero if the constant value X is a legitimate general operand
4080 when generating PIC code. It is given that flag_pic is on and
4081 that X satisfies CONSTANT_P. */
4084 legitimate_pic_operand_p (rtx x
)
4086 if (pic_address_needs_scratch (x
))
4088 if (sparc_tls_referenced_p (x
))
4093 #define RTX_OK_FOR_OFFSET_P(X, MODE) \
4095 && INTVAL (X) >= -0x1000 \
4096 && INTVAL (X) <= (0x1000 - GET_MODE_SIZE (MODE)))
4098 #define RTX_OK_FOR_OLO10_P(X, MODE) \
4100 && INTVAL (X) >= -0x1000 \
4101 && INTVAL (X) <= (0xc00 - GET_MODE_SIZE (MODE)))
4103 /* Handle the TARGET_LEGITIMATE_ADDRESS_P target hook.
4105 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
4106 ordinarily. This changes a bit when generating PIC. */
4109 sparc_legitimate_address_p (machine_mode mode
, rtx addr
, bool strict
)
4111 rtx rs1
= NULL
, rs2
= NULL
, imm1
= NULL
;
4113 if (REG_P (addr
) || GET_CODE (addr
) == SUBREG
)
4115 else if (GET_CODE (addr
) == PLUS
)
4117 rs1
= XEXP (addr
, 0);
4118 rs2
= XEXP (addr
, 1);
4120 /* Canonicalize. REG comes first, if there are no regs,
4121 LO_SUM comes first. */
4123 && GET_CODE (rs1
) != SUBREG
4125 || GET_CODE (rs2
) == SUBREG
4126 || (GET_CODE (rs2
) == LO_SUM
&& GET_CODE (rs1
) != LO_SUM
)))
4128 rs1
= XEXP (addr
, 1);
4129 rs2
= XEXP (addr
, 0);
4133 && rs1
== pic_offset_table_rtx
4135 && GET_CODE (rs2
) != SUBREG
4136 && GET_CODE (rs2
) != LO_SUM
4137 && GET_CODE (rs2
) != MEM
4138 && !(GET_CODE (rs2
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs2
))
4139 && (! symbolic_operand (rs2
, VOIDmode
) || mode
== Pmode
)
4140 && (GET_CODE (rs2
) != CONST_INT
|| SMALL_INT (rs2
)))
4142 || GET_CODE (rs1
) == SUBREG
)
4143 && RTX_OK_FOR_OFFSET_P (rs2
, mode
)))
4148 else if ((REG_P (rs1
) || GET_CODE (rs1
) == SUBREG
)
4149 && (REG_P (rs2
) || GET_CODE (rs2
) == SUBREG
))
4151 /* We prohibit REG + REG for TFmode when there are no quad move insns
4152 and we consequently need to split. We do this because REG+REG
4153 is not an offsettable address. If we get the situation in reload
4154 where source and destination of a movtf pattern are both MEMs with
4155 REG+REG address, then only one of them gets converted to an
4156 offsettable address. */
4158 && ! (TARGET_ARCH64
&& TARGET_HARD_QUAD
))
4161 /* Likewise for TImode, but in all cases. */
4165 /* We prohibit REG + REG on ARCH32 if not optimizing for
4166 DFmode/DImode because then mem_min_alignment is likely to be zero
4167 after reload and the forced split would lack a matching splitter
4169 if (TARGET_ARCH32
&& !optimize
4170 && (mode
== DFmode
|| mode
== DImode
))
4173 else if (USE_AS_OFFSETABLE_LO10
4174 && GET_CODE (rs1
) == LO_SUM
4176 && ! TARGET_CM_MEDMID
4177 && RTX_OK_FOR_OLO10_P (rs2
, mode
))
4180 imm1
= XEXP (rs1
, 1);
4181 rs1
= XEXP (rs1
, 0);
4182 if (!CONSTANT_P (imm1
)
4183 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
4187 else if (GET_CODE (addr
) == LO_SUM
)
4189 rs1
= XEXP (addr
, 0);
4190 imm1
= XEXP (addr
, 1);
4192 if (!CONSTANT_P (imm1
)
4193 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
4196 /* We can't allow TFmode in 32-bit mode, because an offset greater
4197 than the alignment (8) may cause the LO_SUM to overflow. */
4198 if (mode
== TFmode
&& TARGET_ARCH32
)
4201 /* During reload, accept the HIGH+LO_SUM construct generated by
4202 sparc_legitimize_reload_address. */
4203 if (reload_in_progress
4204 && GET_CODE (rs1
) == HIGH
4205 && XEXP (rs1
, 0) == imm1
)
4208 else if (GET_CODE (addr
) == CONST_INT
&& SMALL_INT (addr
))
4213 if (GET_CODE (rs1
) == SUBREG
)
4214 rs1
= SUBREG_REG (rs1
);
4220 if (GET_CODE (rs2
) == SUBREG
)
4221 rs2
= SUBREG_REG (rs2
);
4228 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1
))
4229 || (rs2
&& !REGNO_OK_FOR_BASE_P (REGNO (rs2
))))
4234 if ((! SPARC_INT_REG_P (REGNO (rs1
))
4235 && REGNO (rs1
) != FRAME_POINTER_REGNUM
4236 && REGNO (rs1
) < FIRST_PSEUDO_REGISTER
)
4238 && (! SPARC_INT_REG_P (REGNO (rs2
))
4239 && REGNO (rs2
) != FRAME_POINTER_REGNUM
4240 && REGNO (rs2
) < FIRST_PSEUDO_REGISTER
)))
4246 /* Return the SYMBOL_REF for the tls_get_addr function. */
4248 static GTY(()) rtx sparc_tls_symbol
= NULL_RTX
;
4251 sparc_tls_get_addr (void)
4253 if (!sparc_tls_symbol
)
4254 sparc_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
4256 return sparc_tls_symbol
;
4259 /* Return the Global Offset Table to be used in TLS mode. */
4262 sparc_tls_got (void)
4264 /* In PIC mode, this is just the PIC offset table. */
4267 crtl
->uses_pic_offset_table
= 1;
4268 return pic_offset_table_rtx
;
4271 /* In non-PIC mode, Sun as (unlike GNU as) emits PC-relative relocations for
4272 the GOT symbol with the 32-bit ABI, so we reload the GOT register. */
4273 if (TARGET_SUN_TLS
&& TARGET_ARCH32
)
4275 load_got_register ();
4276 return global_offset_table_rtx
;
4279 /* In all other cases, we load a new pseudo with the GOT symbol. */
4280 return copy_to_reg (sparc_got ());
4283 /* Return true if X contains a thread-local symbol. */
4286 sparc_tls_referenced_p (rtx x
)
4288 if (!TARGET_HAVE_TLS
)
4291 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
4292 x
= XEXP (XEXP (x
, 0), 0);
4294 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
))
4297 /* That's all we handle in sparc_legitimize_tls_address for now. */
4301 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
4302 this (thread-local) address. */
4305 sparc_legitimize_tls_address (rtx addr
)
4307 rtx temp1
, temp2
, temp3
, ret
, o0
, got
;
4310 gcc_assert (can_create_pseudo_p ());
4312 if (GET_CODE (addr
) == SYMBOL_REF
)
4313 switch (SYMBOL_REF_TLS_MODEL (addr
))
4315 case TLS_MODEL_GLOBAL_DYNAMIC
:
4317 temp1
= gen_reg_rtx (SImode
);
4318 temp2
= gen_reg_rtx (SImode
);
4319 ret
= gen_reg_rtx (Pmode
);
4320 o0
= gen_rtx_REG (Pmode
, 8);
4321 got
= sparc_tls_got ();
4322 emit_insn (gen_tgd_hi22 (temp1
, addr
));
4323 emit_insn (gen_tgd_lo10 (temp2
, temp1
, addr
));
4326 emit_insn (gen_tgd_add32 (o0
, got
, temp2
, addr
));
4327 insn
= emit_call_insn (gen_tgd_call32 (o0
, sparc_tls_get_addr (),
4332 emit_insn (gen_tgd_add64 (o0
, got
, temp2
, addr
));
4333 insn
= emit_call_insn (gen_tgd_call64 (o0
, sparc_tls_get_addr (),
4336 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
4337 insn
= get_insns ();
4339 emit_libcall_block (insn
, ret
, o0
, addr
);
4342 case TLS_MODEL_LOCAL_DYNAMIC
:
4344 temp1
= gen_reg_rtx (SImode
);
4345 temp2
= gen_reg_rtx (SImode
);
4346 temp3
= gen_reg_rtx (Pmode
);
4347 ret
= gen_reg_rtx (Pmode
);
4348 o0
= gen_rtx_REG (Pmode
, 8);
4349 got
= sparc_tls_got ();
4350 emit_insn (gen_tldm_hi22 (temp1
));
4351 emit_insn (gen_tldm_lo10 (temp2
, temp1
));
4354 emit_insn (gen_tldm_add32 (o0
, got
, temp2
));
4355 insn
= emit_call_insn (gen_tldm_call32 (o0
, sparc_tls_get_addr (),
4360 emit_insn (gen_tldm_add64 (o0
, got
, temp2
));
4361 insn
= emit_call_insn (gen_tldm_call64 (o0
, sparc_tls_get_addr (),
4364 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
4365 insn
= get_insns ();
4367 emit_libcall_block (insn
, temp3
, o0
,
4368 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
4369 UNSPEC_TLSLD_BASE
));
4370 temp1
= gen_reg_rtx (SImode
);
4371 temp2
= gen_reg_rtx (SImode
);
4372 emit_insn (gen_tldo_hix22 (temp1
, addr
));
4373 emit_insn (gen_tldo_lox10 (temp2
, temp1
, addr
));
4375 emit_insn (gen_tldo_add32 (ret
, temp3
, temp2
, addr
));
4377 emit_insn (gen_tldo_add64 (ret
, temp3
, temp2
, addr
));
4380 case TLS_MODEL_INITIAL_EXEC
:
4381 temp1
= gen_reg_rtx (SImode
);
4382 temp2
= gen_reg_rtx (SImode
);
4383 temp3
= gen_reg_rtx (Pmode
);
4384 got
= sparc_tls_got ();
4385 emit_insn (gen_tie_hi22 (temp1
, addr
));
4386 emit_insn (gen_tie_lo10 (temp2
, temp1
, addr
));
4388 emit_insn (gen_tie_ld32 (temp3
, got
, temp2
, addr
));
4390 emit_insn (gen_tie_ld64 (temp3
, got
, temp2
, addr
));
4393 ret
= gen_reg_rtx (Pmode
);
4395 emit_insn (gen_tie_add32 (ret
, gen_rtx_REG (Pmode
, 7),
4398 emit_insn (gen_tie_add64 (ret
, gen_rtx_REG (Pmode
, 7),
4402 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp3
);
4405 case TLS_MODEL_LOCAL_EXEC
:
4406 temp1
= gen_reg_rtx (Pmode
);
4407 temp2
= gen_reg_rtx (Pmode
);
4410 emit_insn (gen_tle_hix22_sp32 (temp1
, addr
));
4411 emit_insn (gen_tle_lox10_sp32 (temp2
, temp1
, addr
));
4415 emit_insn (gen_tle_hix22_sp64 (temp1
, addr
));
4416 emit_insn (gen_tle_lox10_sp64 (temp2
, temp1
, addr
));
4418 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp2
);
4425 else if (GET_CODE (addr
) == CONST
)
4429 gcc_assert (GET_CODE (XEXP (addr
, 0)) == PLUS
);
4431 base
= sparc_legitimize_tls_address (XEXP (XEXP (addr
, 0), 0));
4432 offset
= XEXP (XEXP (addr
, 0), 1);
4434 base
= force_operand (base
, NULL_RTX
);
4435 if (!(GET_CODE (offset
) == CONST_INT
&& SMALL_INT (offset
)))
4436 offset
= force_reg (Pmode
, offset
);
4437 ret
= gen_rtx_PLUS (Pmode
, base
, offset
);
4441 gcc_unreachable (); /* for now ... */
4446 /* Legitimize PIC addresses. If the address is already position-independent,
4447 we return ORIG. Newly generated position-independent addresses go into a
4448 reg. This is REG if nonzero, otherwise we allocate register(s) as
4452 sparc_legitimize_pic_address (rtx orig
, rtx reg
)
4454 bool gotdata_op
= false;
4456 if (GET_CODE (orig
) == SYMBOL_REF
4457 /* See the comment in sparc_expand_move. */
4458 || (GET_CODE (orig
) == LABEL_REF
&& !can_use_mov_pic_label_ref (orig
)))
4460 rtx pic_ref
, address
;
4465 gcc_assert (can_create_pseudo_p ());
4466 reg
= gen_reg_rtx (Pmode
);
4471 /* If not during reload, allocate another temp reg here for loading
4472 in the address, so that these instructions can be optimized
4474 rtx temp_reg
= (! can_create_pseudo_p ()
4475 ? reg
: gen_reg_rtx (Pmode
));
4477 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
4478 won't get confused into thinking that these two instructions
4479 are loading in the true address of the symbol. If in the
4480 future a PIC rtx exists, that should be used instead. */
4483 emit_insn (gen_movdi_high_pic (temp_reg
, orig
));
4484 emit_insn (gen_movdi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
4488 emit_insn (gen_movsi_high_pic (temp_reg
, orig
));
4489 emit_insn (gen_movsi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
4497 crtl
->uses_pic_offset_table
= 1;
4501 insn
= emit_insn (gen_movdi_pic_gotdata_op (reg
,
4502 pic_offset_table_rtx
,
4505 insn
= emit_insn (gen_movsi_pic_gotdata_op (reg
,
4506 pic_offset_table_rtx
,
4512 = gen_const_mem (Pmode
,
4513 gen_rtx_PLUS (Pmode
,
4514 pic_offset_table_rtx
, address
));
4515 insn
= emit_move_insn (reg
, pic_ref
);
4518 /* Put a REG_EQUAL note on this insn, so that it can be optimized
4520 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
4523 else if (GET_CODE (orig
) == CONST
)
4527 if (GET_CODE (XEXP (orig
, 0)) == PLUS
4528 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
4533 gcc_assert (can_create_pseudo_p ());
4534 reg
= gen_reg_rtx (Pmode
);
4537 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
4538 base
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), reg
);
4539 offset
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
4540 base
== reg
? NULL_RTX
: reg
);
4542 if (GET_CODE (offset
) == CONST_INT
)
4544 if (SMALL_INT (offset
))
4545 return plus_constant (Pmode
, base
, INTVAL (offset
));
4546 else if (can_create_pseudo_p ())
4547 offset
= force_reg (Pmode
, offset
);
4549 /* If we reach here, then something is seriously wrong. */
4552 return gen_rtx_PLUS (Pmode
, base
, offset
);
4554 else if (GET_CODE (orig
) == LABEL_REF
)
4555 /* ??? We ought to be checking that the register is live instead, in case
4556 it is eliminated. */
4557 crtl
->uses_pic_offset_table
= 1;
4562 /* Try machine-dependent ways of modifying an illegitimate address X
4563 to be legitimate. If we find one, return the new, valid address.
4565 OLDX is the address as it was before break_out_memory_refs was called.
4566 In some cases it is useful to look at this to decide what needs to be done.
4568 MODE is the mode of the operand pointed to by X.
4570 On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
4573 sparc_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
4578 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
)
4579 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
4580 force_operand (XEXP (x
, 0), NULL_RTX
));
4581 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == MULT
)
4582 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4583 force_operand (XEXP (x
, 1), NULL_RTX
));
4584 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
4585 x
= gen_rtx_PLUS (Pmode
, force_operand (XEXP (x
, 0), NULL_RTX
),
4587 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == PLUS
)
4588 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4589 force_operand (XEXP (x
, 1), NULL_RTX
));
4591 if (x
!= orig_x
&& sparc_legitimate_address_p (mode
, x
, FALSE
))
4594 if (sparc_tls_referenced_p (x
))
4595 x
= sparc_legitimize_tls_address (x
);
4597 x
= sparc_legitimize_pic_address (x
, NULL_RTX
);
4598 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 1)))
4599 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4600 copy_to_mode_reg (Pmode
, XEXP (x
, 1)));
4601 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 0)))
4602 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
4603 copy_to_mode_reg (Pmode
, XEXP (x
, 0)));
4604 else if (GET_CODE (x
) == SYMBOL_REF
4605 || GET_CODE (x
) == CONST
4606 || GET_CODE (x
) == LABEL_REF
)
4607 x
= copy_to_suggested_reg (x
, NULL_RTX
, Pmode
);
4612 /* Delegitimize an address that was legitimized by the above function. */
4615 sparc_delegitimize_address (rtx x
)
4617 x
= delegitimize_mem_from_attrs (x
);
4619 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 1)) == UNSPEC
)
4620 switch (XINT (XEXP (x
, 1), 1))
4622 case UNSPEC_MOVE_PIC
:
4624 x
= XVECEXP (XEXP (x
, 1), 0, 0);
4625 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
4631 /* This is generated by mov{si,di}_pic_label_ref in PIC mode. */
4632 if (GET_CODE (x
) == MINUS
4633 && REG_P (XEXP (x
, 0))
4634 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
4635 && GET_CODE (XEXP (x
, 1)) == LO_SUM
4636 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == UNSPEC
4637 && XINT (XEXP (XEXP (x
, 1), 1), 1) == UNSPEC_MOVE_PIC_LABEL
)
4639 x
= XVECEXP (XEXP (XEXP (x
, 1), 1), 0, 0);
4640 gcc_assert (GET_CODE (x
) == LABEL_REF
);
4646 /* SPARC implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
4647 replace the input X, or the original X if no replacement is called for.
4648 The output parameter *WIN is 1 if the calling macro should goto WIN,
4651 For SPARC, we wish to handle addresses by splitting them into
4652 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
4653 This cuts the number of extra insns by one.
4655 Do nothing when generating PIC code and the address is a symbolic
4656 operand or requires a scratch register. */
4659 sparc_legitimize_reload_address (rtx x
, machine_mode mode
,
4660 int opnum
, int type
,
4661 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
4663 /* Decompose SImode constants into HIGH+LO_SUM. */
4665 && (mode
!= TFmode
|| TARGET_ARCH64
)
4666 && GET_MODE (x
) == SImode
4667 && GET_CODE (x
) != LO_SUM
4668 && GET_CODE (x
) != HIGH
4669 && sparc_cmodel
<= CM_MEDLOW
4671 && (symbolic_operand (x
, Pmode
) || pic_address_needs_scratch (x
))))
4673 x
= gen_rtx_LO_SUM (GET_MODE (x
), gen_rtx_HIGH (GET_MODE (x
), x
), x
);
4674 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4675 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
4676 opnum
, (enum reload_type
)type
);
4681 /* We have to recognize what we have already generated above. */
4682 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == HIGH
)
4684 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4685 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
4686 opnum
, (enum reload_type
)type
);
4695 /* Return true if ADDR (a legitimate address expression)
4696 has an effect that depends on the machine mode it is used for.
4702 is not equivalent to
4704 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
4706 because [%l7+a+1] is interpreted as the address of (a+1). */
4710 sparc_mode_dependent_address_p (const_rtx addr
,
4711 addr_space_t as ATTRIBUTE_UNUSED
)
4713 if (flag_pic
&& GET_CODE (addr
) == PLUS
)
4715 rtx op0
= XEXP (addr
, 0);
4716 rtx op1
= XEXP (addr
, 1);
4717 if (op0
== pic_offset_table_rtx
4718 && symbolic_operand (op1
, VOIDmode
))
4725 #ifdef HAVE_GAS_HIDDEN
4726 # define USE_HIDDEN_LINKONCE 1
4728 # define USE_HIDDEN_LINKONCE 0
4732 get_pc_thunk_name (char name
[32], unsigned int regno
)
4734 const char *reg_name
= reg_names
[regno
];
4736 /* Skip the leading '%' as that cannot be used in a
4740 if (USE_HIDDEN_LINKONCE
)
4741 sprintf (name
, "__sparc_get_pc_thunk.%s", reg_name
);
4743 ASM_GENERATE_INTERNAL_LABEL (name
, "LADDPC", regno
);
4746 /* Wrapper around the load_pcrel_sym{si,di} patterns. */
4749 gen_load_pcrel_sym (rtx op0
, rtx op1
, rtx op2
, rtx op3
)
4751 int orig_flag_pic
= flag_pic
;
4754 /* The load_pcrel_sym{si,di} patterns require absolute addressing. */
4757 insn
= gen_load_pcrel_symdi (op0
, op1
, op2
, op3
);
4759 insn
= gen_load_pcrel_symsi (op0
, op1
, op2
, op3
);
4760 flag_pic
= orig_flag_pic
;
4765 /* Emit code to load the GOT register. */
4768 load_got_register (void)
4770 /* In PIC mode, this will retrieve pic_offset_table_rtx. */
4771 if (!global_offset_table_rtx
)
4772 global_offset_table_rtx
= gen_rtx_REG (Pmode
, GLOBAL_OFFSET_TABLE_REGNUM
);
4774 if (TARGET_VXWORKS_RTP
)
4775 emit_insn (gen_vxworks_load_got ());
4778 /* The GOT symbol is subject to a PC-relative relocation so we need a
4779 helper function to add the PC value and thus get the final value. */
4780 if (!got_helper_rtx
)
4783 get_pc_thunk_name (name
, GLOBAL_OFFSET_TABLE_REGNUM
);
4784 got_helper_rtx
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
4787 emit_insn (gen_load_pcrel_sym (global_offset_table_rtx
, sparc_got (),
4789 GEN_INT (GLOBAL_OFFSET_TABLE_REGNUM
)));
4792 /* Need to emit this whether or not we obey regdecls,
4793 since setjmp/longjmp can cause life info to screw up.
4794 ??? In the case where we don't obey regdecls, this is not sufficient
4795 since we may not fall out the bottom. */
4796 emit_use (global_offset_table_rtx
);
4799 /* Emit a call instruction with the pattern given by PAT. ADDR is the
4800 address of the call target. */
4803 sparc_emit_call_insn (rtx pat
, rtx addr
)
4807 insn
= emit_call_insn (pat
);
4809 /* The PIC register is live on entry to VxWorks PIC PLT entries. */
4810 if (TARGET_VXWORKS_RTP
4812 && GET_CODE (addr
) == SYMBOL_REF
4813 && (SYMBOL_REF_DECL (addr
)
4814 ? !targetm
.binds_local_p (SYMBOL_REF_DECL (addr
))
4815 : !SYMBOL_REF_LOCAL_P (addr
)))
4817 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
4818 crtl
->uses_pic_offset_table
= 1;
4822 /* Return 1 if RTX is a MEM which is known to be aligned to at
4823 least a DESIRED byte boundary. */
4826 mem_min_alignment (rtx mem
, int desired
)
4828 rtx addr
, base
, offset
;
4830 /* If it's not a MEM we can't accept it. */
4831 if (GET_CODE (mem
) != MEM
)
4835 if (!TARGET_UNALIGNED_DOUBLES
4836 && MEM_ALIGN (mem
) / BITS_PER_UNIT
>= (unsigned)desired
)
4839 /* ??? The rest of the function predates MEM_ALIGN so
4840 there is probably a bit of redundancy. */
4841 addr
= XEXP (mem
, 0);
4842 base
= offset
= NULL_RTX
;
4843 if (GET_CODE (addr
) == PLUS
)
4845 if (GET_CODE (XEXP (addr
, 0)) == REG
)
4847 base
= XEXP (addr
, 0);
4849 /* What we are saying here is that if the base
4850 REG is aligned properly, the compiler will make
4851 sure any REG based index upon it will be so
4853 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
4854 offset
= XEXP (addr
, 1);
4856 offset
= const0_rtx
;
4859 else if (GET_CODE (addr
) == REG
)
4862 offset
= const0_rtx
;
4865 if (base
!= NULL_RTX
)
4867 int regno
= REGNO (base
);
4869 if (regno
!= HARD_FRAME_POINTER_REGNUM
&& regno
!= STACK_POINTER_REGNUM
)
4871 /* Check if the compiler has recorded some information
4872 about the alignment of the base REG. If reload has
4873 completed, we already matched with proper alignments.
4874 If not running global_alloc, reload might give us
4875 unaligned pointer to local stack though. */
4877 && REGNO_POINTER_ALIGN (regno
) >= desired
* BITS_PER_UNIT
)
4878 || (optimize
&& reload_completed
))
4879 && (INTVAL (offset
) & (desired
- 1)) == 0)
4884 if (((INTVAL (offset
) - SPARC_STACK_BIAS
) & (desired
- 1)) == 0)
4888 else if (! TARGET_UNALIGNED_DOUBLES
4889 || CONSTANT_P (addr
)
4890 || GET_CODE (addr
) == LO_SUM
)
4892 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
4893 is true, in which case we can only assume that an access is aligned if
4894 it is to a constant address, or the address involves a LO_SUM. */
4898 /* An obviously unaligned address. */
4903 /* Vectors to keep interesting information about registers where it can easily
4904 be got. We used to use the actual mode value as the bit number, but there
4905 are more than 32 modes now. Instead we use two tables: one indexed by
4906 hard register number, and one indexed by mode. */
4908 /* The purpose of sparc_mode_class is to shrink the range of modes so that
4909 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
4910 mapped into one sparc_mode_class mode. */
4912 enum sparc_mode_class
{
4913 H_MODE
, S_MODE
, D_MODE
, T_MODE
, O_MODE
,
4914 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
4918 /* Modes for single-word and smaller quantities. */
4920 ((1 << (int) H_MODE) | (1 << (int) S_MODE) | (1 << (int) SF_MODE))
4922 /* Modes for double-word and smaller quantities. */
4923 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << (int) DF_MODE))
4925 /* Modes for quad-word and smaller quantities. */
4926 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
4928 /* Modes for 8-word and smaller quantities. */
4929 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
4931 /* Modes for single-float quantities. */
4932 #define SF_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
4934 /* Modes for double-float and smaller quantities. */
4935 #define DF_MODES (SF_MODES | (1 << (int) D_MODE) | (1 << (int) DF_MODE))
4937 /* Modes for quad-float and smaller quantities. */
4938 #define TF_MODES (DF_MODES | (1 << (int) TF_MODE))
4940 /* Modes for quad-float pairs and smaller quantities. */
4941 #define OF_MODES (TF_MODES | (1 << (int) OF_MODE))
4943 /* Modes for double-float only quantities. */
4944 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
4946 /* Modes for quad-float and double-float only quantities. */
4947 #define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE))
4949 /* Modes for quad-float pairs and double-float only quantities. */
4950 #define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE))
4952 /* Modes for condition codes. */
4953 #define CC_MODES (1 << (int) CC_MODE)
4954 #define CCFP_MODES (1 << (int) CCFP_MODE)
4956 /* Value is 1 if register/mode pair is acceptable on sparc.
4958 The funny mixture of D and T modes is because integer operations
4959 do not specially operate on tetra quantities, so non-quad-aligned
4960 registers can hold quadword quantities (except %o4 and %i4 because
4961 they cross fixed registers).
4963 ??? Note that, despite the settings, non-double-aligned parameter
4964 registers can hold double-word quantities in 32-bit mode. */
4966 /* This points to either the 32 bit or the 64 bit version. */
4967 const int *hard_regno_mode_classes
;
4969 static const int hard_32bit_mode_classes
[] = {
4970 S_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
4971 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
4972 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
4973 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
4975 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4976 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4977 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4978 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4980 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4981 and none can hold SFmode/SImode values. */
4982 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4983 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4984 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4985 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4988 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
4990 /* %icc, %sfp, %gsr */
4991 CC_MODES
, 0, D_MODES
4994 static const int hard_64bit_mode_classes
[] = {
4995 D_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4996 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4997 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4998 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
5000 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5001 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5002 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5003 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5005 /* FP regs f32 to f63. Only the even numbered registers actually exist,
5006 and none can hold SFmode/SImode values. */
5007 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5008 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5009 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5010 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5013 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
5015 /* %icc, %sfp, %gsr */
5016 CC_MODES
, 0, D_MODES
5019 int sparc_mode_class
[NUM_MACHINE_MODES
];
5021 enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
5024 sparc_init_modes (void)
5028 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
5030 machine_mode m
= (machine_mode
) i
;
5031 unsigned int size
= GET_MODE_SIZE (m
);
5033 switch (GET_MODE_CLASS (m
))
5036 case MODE_PARTIAL_INT
:
5037 case MODE_COMPLEX_INT
:
5039 sparc_mode_class
[i
] = 1 << (int) H_MODE
;
5041 sparc_mode_class
[i
] = 1 << (int) S_MODE
;
5043 sparc_mode_class
[i
] = 1 << (int) D_MODE
;
5044 else if (size
== 16)
5045 sparc_mode_class
[i
] = 1 << (int) T_MODE
;
5046 else if (size
== 32)
5047 sparc_mode_class
[i
] = 1 << (int) O_MODE
;
5049 sparc_mode_class
[i
] = 0;
5051 case MODE_VECTOR_INT
:
5053 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
5055 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
5057 sparc_mode_class
[i
] = 0;
5060 case MODE_COMPLEX_FLOAT
:
5062 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
5064 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
5065 else if (size
== 16)
5066 sparc_mode_class
[i
] = 1 << (int) TF_MODE
;
5067 else if (size
== 32)
5068 sparc_mode_class
[i
] = 1 << (int) OF_MODE
;
5070 sparc_mode_class
[i
] = 0;
5073 if (m
== CCFPmode
|| m
== CCFPEmode
)
5074 sparc_mode_class
[i
] = 1 << (int) CCFP_MODE
;
5076 sparc_mode_class
[i
] = 1 << (int) CC_MODE
;
5079 sparc_mode_class
[i
] = 0;
5085 hard_regno_mode_classes
= hard_64bit_mode_classes
;
5087 hard_regno_mode_classes
= hard_32bit_mode_classes
;
5089 /* Initialize the array used by REGNO_REG_CLASS. */
5090 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
5092 if (i
< 16 && TARGET_V8PLUS
)
5093 sparc_regno_reg_class
[i
] = I64_REGS
;
5094 else if (i
< 32 || i
== FRAME_POINTER_REGNUM
)
5095 sparc_regno_reg_class
[i
] = GENERAL_REGS
;
5097 sparc_regno_reg_class
[i
] = FP_REGS
;
5099 sparc_regno_reg_class
[i
] = EXTRA_FP_REGS
;
5101 sparc_regno_reg_class
[i
] = FPCC_REGS
;
5103 sparc_regno_reg_class
[i
] = NO_REGS
;
5107 /* Return whether REGNO, a global or FP register, must be saved/restored. */
5110 save_global_or_fp_reg_p (unsigned int regno
,
5111 int leaf_function ATTRIBUTE_UNUSED
)
5113 return !call_used_regs
[regno
] && df_regs_ever_live_p (regno
);
5116 /* Return whether the return address register (%i7) is needed. */
5119 return_addr_reg_needed_p (int leaf_function
)
5121 /* If it is live, for example because of __builtin_return_address (0). */
5122 if (df_regs_ever_live_p (RETURN_ADDR_REGNUM
))
5125 /* Otherwise, it is needed as save register if %o7 is clobbered. */
5127 /* Loading the GOT register clobbers %o7. */
5128 || crtl
->uses_pic_offset_table
5129 || df_regs_ever_live_p (INCOMING_RETURN_ADDR_REGNUM
))
5135 /* Return whether REGNO, a local or in register, must be saved/restored. */
5138 save_local_or_in_reg_p (unsigned int regno
, int leaf_function
)
5140 /* General case: call-saved registers live at some point. */
5141 if (!call_used_regs
[regno
] && df_regs_ever_live_p (regno
))
5144 /* Frame pointer register (%fp) if needed. */
5145 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
5148 /* Return address register (%i7) if needed. */
5149 if (regno
== RETURN_ADDR_REGNUM
&& return_addr_reg_needed_p (leaf_function
))
5152 /* GOT register (%l7) if needed. */
5153 if (regno
== PIC_OFFSET_TABLE_REGNUM
&& crtl
->uses_pic_offset_table
)
5156 /* If the function accesses prior frames, the frame pointer and the return
5157 address of the previous frame must be saved on the stack. */
5158 if (crtl
->accesses_prior_frames
5159 && (regno
== HARD_FRAME_POINTER_REGNUM
|| regno
== RETURN_ADDR_REGNUM
))
5165 /* Compute the frame size required by the function. This function is called
5166 during the reload pass and also by sparc_expand_prologue. */
5169 sparc_compute_frame_size (HOST_WIDE_INT size
, int leaf_function
)
5171 HOST_WIDE_INT frame_size
, apparent_frame_size
;
5172 int args_size
, n_global_fp_regs
= 0;
5173 bool save_local_in_regs_p
= false;
5176 /* If the function allocates dynamic stack space, the dynamic offset is
5177 computed early and contains REG_PARM_STACK_SPACE, so we need to cope. */
5178 if (leaf_function
&& !cfun
->calls_alloca
)
5181 args_size
= crtl
->outgoing_args_size
+ REG_PARM_STACK_SPACE (cfun
->decl
);
5183 /* Calculate space needed for global registers. */
5186 for (i
= 0; i
< 8; i
++)
5187 if (save_global_or_fp_reg_p (i
, 0))
5188 n_global_fp_regs
+= 2;
5192 for (i
= 0; i
< 8; i
+= 2)
5193 if (save_global_or_fp_reg_p (i
, 0)
5194 || save_global_or_fp_reg_p (i
+ 1, 0))
5195 n_global_fp_regs
+= 2;
5198 /* In the flat window model, find out which local and in registers need to
5199 be saved. We don't reserve space in the current frame for them as they
5200 will be spilled into the register window save area of the caller's frame.
5201 However, as soon as we use this register window save area, we must create
5202 that of the current frame to make it the live one. */
5204 for (i
= 16; i
< 32; i
++)
5205 if (save_local_or_in_reg_p (i
, leaf_function
))
5207 save_local_in_regs_p
= true;
5211 /* Calculate space needed for FP registers. */
5212 for (i
= 32; i
< (TARGET_V9
? 96 : 64); i
+= 2)
5213 if (save_global_or_fp_reg_p (i
, 0) || save_global_or_fp_reg_p (i
+ 1, 0))
5214 n_global_fp_regs
+= 2;
5217 && n_global_fp_regs
== 0
5219 && !save_local_in_regs_p
)
5220 frame_size
= apparent_frame_size
= 0;
5223 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
5224 apparent_frame_size
= ROUND_UP (size
- STARTING_FRAME_OFFSET
, 8);
5225 apparent_frame_size
+= n_global_fp_regs
* 4;
5227 /* We need to add the size of the outgoing argument area. */
5228 frame_size
= apparent_frame_size
+ ROUND_UP (args_size
, 8);
5230 /* And that of the register window save area. */
5231 frame_size
+= FIRST_PARM_OFFSET (cfun
->decl
);
5233 /* Finally, bump to the appropriate alignment. */
5234 frame_size
= SPARC_STACK_ALIGN (frame_size
);
5237 /* Set up values for use in prologue and epilogue. */
5238 sparc_frame_size
= frame_size
;
5239 sparc_apparent_frame_size
= apparent_frame_size
;
5240 sparc_n_global_fp_regs
= n_global_fp_regs
;
5241 sparc_save_local_in_regs_p
= save_local_in_regs_p
;
5246 /* Implement the macro INITIAL_ELIMINATION_OFFSET, return the OFFSET. */
5249 sparc_initial_elimination_offset (int to
)
5253 if (to
== STACK_POINTER_REGNUM
)
5254 offset
= sparc_compute_frame_size (get_frame_size (), crtl
->is_leaf
);
5258 offset
+= SPARC_STACK_BIAS
;
5262 /* Output any necessary .register pseudo-ops. */
5265 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED
)
5267 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
5273 /* Check if %g[2367] were used without
5274 .register being printed for them already. */
5275 for (i
= 2; i
< 8; i
++)
5277 if (df_regs_ever_live_p (i
)
5278 && ! sparc_hard_reg_printed
[i
])
5280 sparc_hard_reg_printed
[i
] = 1;
5281 /* %g7 is used as TLS base register, use #ignore
5282 for it instead of #scratch. */
5283 fprintf (file
, "\t.register\t%%g%d, #%s\n", i
,
5284 i
== 7 ? "ignore" : "scratch");
5291 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
5293 #if PROBE_INTERVAL > 4096
5294 #error Cannot use indexed addressing mode for stack probing
5297 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
5298 inclusive. These are offsets from the current stack pointer.
5300 Note that we don't use the REG+REG addressing mode for the probes because
5301 of the stack bias in 64-bit mode. And it doesn't really buy us anything
5302 so the advantages of having a single code win here. */
5305 sparc_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
5307 rtx g1
= gen_rtx_REG (Pmode
, 1);
5309 /* See if we have a constant small number of probes to generate. If so,
5310 that's the easy case. */
5311 if (size
<= PROBE_INTERVAL
)
5313 emit_move_insn (g1
, GEN_INT (first
));
5314 emit_insn (gen_rtx_SET (g1
,
5315 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
5316 emit_stack_probe (plus_constant (Pmode
, g1
, -size
));
5319 /* The run-time loop is made up of 9 insns in the generic case while the
5320 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
5321 else if (size
<= 4 * PROBE_INTERVAL
)
5325 emit_move_insn (g1
, GEN_INT (first
+ PROBE_INTERVAL
));
5326 emit_insn (gen_rtx_SET (g1
,
5327 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
5328 emit_stack_probe (g1
);
5330 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
5331 it exceeds SIZE. If only two probes are needed, this will not
5332 generate any code. Then probe at FIRST + SIZE. */
5333 for (i
= 2 * PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
5335 emit_insn (gen_rtx_SET (g1
,
5336 plus_constant (Pmode
, g1
, -PROBE_INTERVAL
)));
5337 emit_stack_probe (g1
);
5340 emit_stack_probe (plus_constant (Pmode
, g1
,
5341 (i
- PROBE_INTERVAL
) - size
));
5344 /* Otherwise, do the same as above, but in a loop. Note that we must be
5345 extra careful with variables wrapping around because we might be at
5346 the very top (or the very bottom) of the address space and we have
5347 to be able to handle this case properly; in particular, we use an
5348 equality test for the loop condition. */
5351 HOST_WIDE_INT rounded_size
;
5352 rtx g4
= gen_rtx_REG (Pmode
, 4);
5354 emit_move_insn (g1
, GEN_INT (first
));
5357 /* Step 1: round SIZE to the previous multiple of the interval. */
5359 rounded_size
= ROUND_DOWN (size
, PROBE_INTERVAL
);
5360 emit_move_insn (g4
, GEN_INT (rounded_size
));
5363 /* Step 2: compute initial and final value of the loop counter. */
5365 /* TEST_ADDR = SP + FIRST. */
5366 emit_insn (gen_rtx_SET (g1
,
5367 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
5369 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
5370 emit_insn (gen_rtx_SET (g4
, gen_rtx_MINUS (Pmode
, g1
, g4
)));
5375 while (TEST_ADDR != LAST_ADDR)
5377 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
5381 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
5382 until it is equal to ROUNDED_SIZE. */
5385 emit_insn (gen_probe_stack_rangedi (g1
, g1
, g4
));
5387 emit_insn (gen_probe_stack_rangesi (g1
, g1
, g4
));
5390 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
5391 that SIZE is equal to ROUNDED_SIZE. */
5393 if (size
!= rounded_size
)
5394 emit_stack_probe (plus_constant (Pmode
, g4
, rounded_size
- size
));
5397 /* Make sure nothing is scheduled before we are done. */
5398 emit_insn (gen_blockage ());
5401 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
5402 absolute addresses. */
5405 output_probe_stack_range (rtx reg1
, rtx reg2
)
5407 static int labelno
= 0;
5411 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
++);
5414 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
5416 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
5418 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
5419 output_asm_insn ("add\t%0, %1, %0", xops
);
5421 /* Test if TEST_ADDR == LAST_ADDR. */
5423 output_asm_insn ("cmp\t%0, %1", xops
);
5425 /* Probe at TEST_ADDR and branch. */
5427 fputs ("\tbne,pt\t%xcc,", asm_out_file
);
5429 fputs ("\tbne\t", asm_out_file
);
5430 assemble_name_raw (asm_out_file
, loop_lab
);
5431 fputc ('\n', asm_out_file
);
5432 xops
[1] = GEN_INT (SPARC_STACK_BIAS
);
5433 output_asm_insn (" st\t%%g0, [%0+%1]", xops
);
5438 /* Emit code to save/restore registers from LOW to HIGH at BASE+OFFSET as
5439 needed. LOW is supposed to be double-word aligned for 32-bit registers.
5440 SAVE_P decides whether a register must be saved/restored. ACTION_TRUE
5441 is the action to be performed if SAVE_P returns true and ACTION_FALSE
5442 the action to be performed if it returns false. Return the new offset. */
5444 typedef bool (*sorr_pred_t
) (unsigned int, int);
5445 typedef enum { SORR_NONE
, SORR_ADVANCE
, SORR_SAVE
, SORR_RESTORE
} sorr_act_t
;
5448 emit_save_or_restore_regs (unsigned int low
, unsigned int high
, rtx base
,
5449 int offset
, int leaf_function
, sorr_pred_t save_p
,
5450 sorr_act_t action_true
, sorr_act_t action_false
)
5456 if (TARGET_ARCH64
&& high
<= 32)
5460 for (i
= low
; i
< high
; i
++)
5462 if (save_p (i
, leaf_function
))
5464 mem
= gen_frame_mem (DImode
, plus_constant (Pmode
,
5466 if (action_true
== SORR_SAVE
)
5468 insn
= emit_move_insn (mem
, gen_rtx_REG (DImode
, i
));
5469 RTX_FRAME_RELATED_P (insn
) = 1;
5471 else /* action_true == SORR_RESTORE */
5473 /* The frame pointer must be restored last since its old
5474 value may be used as base address for the frame. This
5475 is problematic in 64-bit mode only because of the lack
5476 of double-word load instruction. */
5477 if (i
== HARD_FRAME_POINTER_REGNUM
)
5480 emit_move_insn (gen_rtx_REG (DImode
, i
), mem
);
5484 else if (action_false
== SORR_ADVANCE
)
5490 mem
= gen_frame_mem (DImode
, plus_constant (Pmode
, base
, fp_offset
));
5491 emit_move_insn (hard_frame_pointer_rtx
, mem
);
5496 for (i
= low
; i
< high
; i
+= 2)
5498 bool reg0
= save_p (i
, leaf_function
);
5499 bool reg1
= save_p (i
+ 1, leaf_function
);
5505 mode
= SPARC_INT_REG_P (i
) ? DImode
: DFmode
;
5510 mode
= SPARC_INT_REG_P (i
) ? SImode
: SFmode
;
5515 mode
= SPARC_INT_REG_P (i
) ? SImode
: SFmode
;
5521 if (action_false
== SORR_ADVANCE
)
5526 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, base
, offset
));
5527 if (action_true
== SORR_SAVE
)
5529 insn
= emit_move_insn (mem
, gen_rtx_REG (mode
, regno
));
5530 RTX_FRAME_RELATED_P (insn
) = 1;
5534 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, base
,
5536 set1
= gen_rtx_SET (mem
, gen_rtx_REG (SImode
, regno
));
5537 RTX_FRAME_RELATED_P (set1
) = 1;
5539 = gen_frame_mem (SImode
, plus_constant (Pmode
, base
,
5541 set2
= gen_rtx_SET (mem
, gen_rtx_REG (SImode
, regno
+ 1));
5542 RTX_FRAME_RELATED_P (set2
) = 1;
5543 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
5544 gen_rtx_PARALLEL (VOIDmode
,
5545 gen_rtvec (2, set1
, set2
)));
5548 else /* action_true == SORR_RESTORE */
5549 emit_move_insn (gen_rtx_REG (mode
, regno
), mem
);
5551 /* Bump and round down to double word
5552 in case we already bumped by 4. */
5553 offset
= ROUND_DOWN (offset
+ 8, 8);
5560 /* Emit code to adjust BASE to OFFSET. Return the new base. */
5563 emit_adjust_base_to_offset (rtx base
, int offset
)
5565 /* ??? This might be optimized a little as %g1 might already have a
5566 value close enough that a single add insn will do. */
5567 /* ??? Although, all of this is probably only a temporary fix because
5568 if %g1 can hold a function result, then sparc_expand_epilogue will
5569 lose (the result will be clobbered). */
5570 rtx new_base
= gen_rtx_REG (Pmode
, 1);
5571 emit_move_insn (new_base
, GEN_INT (offset
));
5572 emit_insn (gen_rtx_SET (new_base
, gen_rtx_PLUS (Pmode
, base
, new_base
)));
5576 /* Emit code to save/restore call-saved global and FP registers. */
5579 emit_save_or_restore_global_fp_regs (rtx base
, int offset
, sorr_act_t action
)
5581 if (offset
< -4096 || offset
+ sparc_n_global_fp_regs
* 4 > 4095)
5583 base
= emit_adjust_base_to_offset (base
, offset
);
5588 = emit_save_or_restore_regs (0, 8, base
, offset
, 0,
5589 save_global_or_fp_reg_p
, action
, SORR_NONE
);
5590 emit_save_or_restore_regs (32, TARGET_V9
? 96 : 64, base
, offset
, 0,
5591 save_global_or_fp_reg_p
, action
, SORR_NONE
);
5594 /* Emit code to save/restore call-saved local and in registers. */
5597 emit_save_or_restore_local_in_regs (rtx base
, int offset
, sorr_act_t action
)
5599 if (offset
< -4096 || offset
+ 16 * UNITS_PER_WORD
> 4095)
5601 base
= emit_adjust_base_to_offset (base
, offset
);
5605 emit_save_or_restore_regs (16, 32, base
, offset
, sparc_leaf_function_p
,
5606 save_local_or_in_reg_p
, action
, SORR_ADVANCE
);
5609 /* Emit a window_save insn. */
5612 emit_window_save (rtx increment
)
5614 rtx_insn
*insn
= emit_insn (gen_window_save (increment
));
5615 RTX_FRAME_RELATED_P (insn
) = 1;
5617 /* The incoming return address (%o7) is saved in %i7. */
5618 add_reg_note (insn
, REG_CFA_REGISTER
,
5619 gen_rtx_SET (gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
),
5621 INCOMING_RETURN_ADDR_REGNUM
)));
5623 /* The window save event. */
5624 add_reg_note (insn
, REG_CFA_WINDOW_SAVE
, const0_rtx
);
5626 /* The CFA is %fp, the hard frame pointer. */
5627 add_reg_note (insn
, REG_CFA_DEF_CFA
,
5628 plus_constant (Pmode
, hard_frame_pointer_rtx
,
5629 INCOMING_FRAME_SP_OFFSET
));
5634 /* Generate an increment for the stack pointer. */
5637 gen_stack_pointer_inc (rtx increment
)
5639 return gen_rtx_SET (stack_pointer_rtx
,
5640 gen_rtx_PLUS (Pmode
,
5645 /* Expand the function prologue. The prologue is responsible for reserving
5646 storage for the frame, saving the call-saved registers and loading the
5647 GOT register if needed. */
5650 sparc_expand_prologue (void)
5655 /* Compute a snapshot of crtl->uses_only_leaf_regs. Relying
5656 on the final value of the flag means deferring the prologue/epilogue
5657 expansion until just before the second scheduling pass, which is too
5658 late to emit multiple epilogues or return insns.
5660 Of course we are making the assumption that the value of the flag
5661 will not change between now and its final value. Of the three parts
5662 of the formula, only the last one can reasonably vary. Let's take a
5663 closer look, after assuming that the first two ones are set to true
5664 (otherwise the last value is effectively silenced).
5666 If only_leaf_regs_used returns false, the global predicate will also
5667 be false so the actual frame size calculated below will be positive.
5668 As a consequence, the save_register_window insn will be emitted in
5669 the instruction stream; now this insn explicitly references %fp
5670 which is not a leaf register so only_leaf_regs_used will always
5671 return false subsequently.
5673 If only_leaf_regs_used returns true, we hope that the subsequent
5674 optimization passes won't cause non-leaf registers to pop up. For
5675 example, the regrename pass has special provisions to not rename to
5676 non-leaf registers in a leaf function. */
5677 sparc_leaf_function_p
5678 = optimize
> 0 && crtl
->is_leaf
&& only_leaf_regs_used ();
5680 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
5682 if (flag_stack_usage_info
)
5683 current_function_static_stack_size
= size
;
5685 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
5687 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
5689 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
5690 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
,
5691 size
- STACK_CHECK_PROTECT
);
5694 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
5699 else if (sparc_leaf_function_p
)
5701 rtx size_int_rtx
= GEN_INT (-size
);
5704 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
5705 else if (size
<= 8192)
5707 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
5708 RTX_FRAME_RELATED_P (insn
) = 1;
5710 /* %sp is still the CFA register. */
5711 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
5715 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
5716 emit_move_insn (size_rtx
, size_int_rtx
);
5717 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
5718 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
5719 gen_stack_pointer_inc (size_int_rtx
));
5722 RTX_FRAME_RELATED_P (insn
) = 1;
5726 rtx size_int_rtx
= GEN_INT (-size
);
5729 emit_window_save (size_int_rtx
);
5730 else if (size
<= 8192)
5732 emit_window_save (GEN_INT (-4096));
5734 /* %sp is not the CFA register anymore. */
5735 emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
5737 /* Make sure no %fp-based store is issued until after the frame is
5738 established. The offset between the frame pointer and the stack
5739 pointer is calculated relative to the value of the stack pointer
5740 at the end of the function prologue, and moving instructions that
5741 access the stack via the frame pointer between the instructions
5742 that decrement the stack pointer could result in accessing the
5743 register window save area, which is volatile. */
5744 emit_insn (gen_frame_blockage ());
5748 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
5749 emit_move_insn (size_rtx
, size_int_rtx
);
5750 emit_window_save (size_rtx
);
5754 if (sparc_leaf_function_p
)
5756 sparc_frame_base_reg
= stack_pointer_rtx
;
5757 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
5761 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
5762 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
5765 if (sparc_n_global_fp_regs
> 0)
5766 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5767 sparc_frame_base_offset
5768 - sparc_apparent_frame_size
,
5771 /* Load the GOT register if needed. */
5772 if (crtl
->uses_pic_offset_table
)
5773 load_got_register ();
5775 /* Advertise that the data calculated just above are now valid. */
5776 sparc_prologue_data_valid_p
= true;
5779 /* Expand the function prologue. The prologue is responsible for reserving
5780 storage for the frame, saving the call-saved registers and loading the
5781 GOT register if needed. */
5784 sparc_flat_expand_prologue (void)
5789 sparc_leaf_function_p
= optimize
> 0 && crtl
->is_leaf
;
5791 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
5793 if (flag_stack_usage_info
)
5794 current_function_static_stack_size
= size
;
5796 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
5798 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
5800 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
5801 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
,
5802 size
- STACK_CHECK_PROTECT
);
5805 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
5808 if (sparc_save_local_in_regs_p
)
5809 emit_save_or_restore_local_in_regs (stack_pointer_rtx
, SPARC_STACK_BIAS
,
5816 rtx size_int_rtx
, size_rtx
;
5818 size_rtx
= size_int_rtx
= GEN_INT (-size
);
5820 /* We establish the frame (i.e. decrement the stack pointer) first, even
5821 if we use a frame pointer, because we cannot clobber any call-saved
5822 registers, including the frame pointer, if we haven't created a new
5823 register save area, for the sake of compatibility with the ABI. */
5825 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
5826 else if (size
<= 8192 && !frame_pointer_needed
)
5828 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
5829 RTX_FRAME_RELATED_P (insn
) = 1;
5830 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
5834 size_rtx
= gen_rtx_REG (Pmode
, 1);
5835 emit_move_insn (size_rtx
, size_int_rtx
);
5836 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
5837 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
5838 gen_stack_pointer_inc (size_int_rtx
));
5840 RTX_FRAME_RELATED_P (insn
) = 1;
5842 /* Ensure nothing is scheduled until after the frame is established. */
5843 emit_insn (gen_blockage ());
5845 if (frame_pointer_needed
)
5847 insn
= emit_insn (gen_rtx_SET (hard_frame_pointer_rtx
,
5848 gen_rtx_MINUS (Pmode
,
5851 RTX_FRAME_RELATED_P (insn
) = 1;
5853 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
5854 gen_rtx_SET (hard_frame_pointer_rtx
,
5855 plus_constant (Pmode
, stack_pointer_rtx
,
5859 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
5861 rtx o7
= gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
);
5862 rtx i7
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
5864 insn
= emit_move_insn (i7
, o7
);
5865 RTX_FRAME_RELATED_P (insn
) = 1;
5867 add_reg_note (insn
, REG_CFA_REGISTER
, gen_rtx_SET (i7
, o7
));
5869 /* Prevent this instruction from ever being considered dead,
5870 even if this function has no epilogue. */
5875 if (frame_pointer_needed
)
5877 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
5878 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
5882 sparc_frame_base_reg
= stack_pointer_rtx
;
5883 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
5886 if (sparc_n_global_fp_regs
> 0)
5887 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5888 sparc_frame_base_offset
5889 - sparc_apparent_frame_size
,
5892 /* Load the GOT register if needed. */
5893 if (crtl
->uses_pic_offset_table
)
5894 load_got_register ();
5896 /* Advertise that the data calculated just above are now valid. */
5897 sparc_prologue_data_valid_p
= true;
5900 /* This function generates the assembly code for function entry, which boils
5901 down to emitting the necessary .register directives. */
5904 sparc_asm_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
5906 /* Check that the assumption we made in sparc_expand_prologue is valid. */
5908 gcc_assert (sparc_leaf_function_p
== crtl
->uses_only_leaf_regs
);
5910 sparc_output_scratch_registers (file
);
5913 /* Expand the function epilogue, either normal or part of a sibcall.
5914 We emit all the instructions except the return or the call. */
5917 sparc_expand_epilogue (bool for_eh
)
5919 HOST_WIDE_INT size
= sparc_frame_size
;
5921 if (cfun
->calls_alloca
)
5922 emit_insn (gen_frame_blockage ());
5924 if (sparc_n_global_fp_regs
> 0)
5925 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5926 sparc_frame_base_offset
5927 - sparc_apparent_frame_size
,
5930 if (size
== 0 || for_eh
)
5932 else if (sparc_leaf_function_p
)
5935 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
5936 else if (size
<= 8192)
5938 emit_insn (gen_stack_pointer_inc (GEN_INT (4096)));
5939 emit_insn (gen_stack_pointer_inc (GEN_INT (size
- 4096)));
5943 rtx reg
= gen_rtx_REG (Pmode
, 1);
5944 emit_move_insn (reg
, GEN_INT (size
));
5945 emit_insn (gen_stack_pointer_inc (reg
));
5950 /* Expand the function epilogue, either normal or part of a sibcall.
5951 We emit all the instructions except the return or the call. */
5954 sparc_flat_expand_epilogue (bool for_eh
)
5956 HOST_WIDE_INT size
= sparc_frame_size
;
5958 if (sparc_n_global_fp_regs
> 0)
5959 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5960 sparc_frame_base_offset
5961 - sparc_apparent_frame_size
,
5964 /* If we have a frame pointer, we'll need both to restore it before the
5965 frame is destroyed and use its current value in destroying the frame.
5966 Since we don't have an atomic way to do that in the flat window model,
5967 we save the current value into a temporary register (%g1). */
5968 if (frame_pointer_needed
&& !for_eh
)
5969 emit_move_insn (gen_rtx_REG (Pmode
, 1), hard_frame_pointer_rtx
);
5971 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
5972 emit_move_insn (gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
),
5973 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
));
5975 if (sparc_save_local_in_regs_p
)
5976 emit_save_or_restore_local_in_regs (sparc_frame_base_reg
,
5977 sparc_frame_base_offset
,
5980 if (size
== 0 || for_eh
)
5982 else if (frame_pointer_needed
)
5984 /* Make sure the frame is destroyed after everything else is done. */
5985 emit_insn (gen_blockage ());
5987 emit_move_insn (stack_pointer_rtx
, gen_rtx_REG (Pmode
, 1));
5992 emit_insn (gen_blockage ());
5995 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
5996 else if (size
<= 8192)
5998 emit_insn (gen_stack_pointer_inc (GEN_INT (4096)));
5999 emit_insn (gen_stack_pointer_inc (GEN_INT (size
- 4096)));
6003 rtx reg
= gen_rtx_REG (Pmode
, 1);
6004 emit_move_insn (reg
, GEN_INT (size
));
6005 emit_insn (gen_stack_pointer_inc (reg
));
6010 /* Return true if it is appropriate to emit `return' instructions in the
6011 body of a function. */
6014 sparc_can_use_return_insn_p (void)
6016 return sparc_prologue_data_valid_p
6017 && sparc_n_global_fp_regs
== 0
6019 ? (sparc_frame_size
== 0 && !sparc_save_local_in_regs_p
)
6020 : (sparc_frame_size
== 0 || !sparc_leaf_function_p
);
6023 /* This function generates the assembly code for function exit. */
6026 sparc_asm_function_epilogue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
6028 /* If the last two instructions of a function are "call foo; dslot;"
6029 the return address might point to the first instruction in the next
6030 function and we have to output a dummy nop for the sake of sane
6031 backtraces in such cases. This is pointless for sibling calls since
6032 the return address is explicitly adjusted. */
6034 rtx_insn
*insn
= get_last_insn ();
6036 rtx last_real_insn
= prev_real_insn (insn
);
6038 && NONJUMP_INSN_P (last_real_insn
)
6039 && GET_CODE (PATTERN (last_real_insn
)) == SEQUENCE
)
6040 last_real_insn
= XVECEXP (PATTERN (last_real_insn
), 0, 0);
6043 && CALL_P (last_real_insn
)
6044 && !SIBLING_CALL_P (last_real_insn
))
6045 fputs("\tnop\n", file
);
6047 sparc_output_deferred_case_vectors ();
6050 /* Output a 'restore' instruction. */
6053 output_restore (rtx pat
)
6059 fputs ("\t restore\n", asm_out_file
);
6063 gcc_assert (GET_CODE (pat
) == SET
);
6065 operands
[0] = SET_DEST (pat
);
6066 pat
= SET_SRC (pat
);
6068 switch (GET_CODE (pat
))
6071 operands
[1] = XEXP (pat
, 0);
6072 operands
[2] = XEXP (pat
, 1);
6073 output_asm_insn (" restore %r1, %2, %Y0", operands
);
6076 operands
[1] = XEXP (pat
, 0);
6077 operands
[2] = XEXP (pat
, 1);
6078 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands
);
6081 operands
[1] = XEXP (pat
, 0);
6082 gcc_assert (XEXP (pat
, 1) == const1_rtx
);
6083 output_asm_insn (" restore %r1, %r1, %Y0", operands
);
6087 output_asm_insn (" restore %%g0, %1, %Y0", operands
);
6092 /* Output a return. */
6095 output_return (rtx_insn
*insn
)
6097 if (crtl
->calls_eh_return
)
6099 /* If the function uses __builtin_eh_return, the eh_return
6100 machinery occupies the delay slot. */
6101 gcc_assert (!final_sequence
);
6103 if (flag_delayed_branch
)
6105 if (!TARGET_FLAT
&& TARGET_V9
)
6106 fputs ("\treturn\t%i7+8\n", asm_out_file
);
6110 fputs ("\trestore\n", asm_out_file
);
6112 fputs ("\tjmp\t%o7+8\n", asm_out_file
);
6115 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file
);
6120 fputs ("\trestore\n", asm_out_file
);
6122 fputs ("\tadd\t%sp, %g1, %sp\n", asm_out_file
);
6123 fputs ("\tjmp\t%o7+8\n\t nop\n", asm_out_file
);
6126 else if (sparc_leaf_function_p
|| TARGET_FLAT
)
6128 /* This is a leaf or flat function so we don't have to bother restoring
6129 the register window, which frees us from dealing with the convoluted
6130 semantics of restore/return. We simply output the jump to the
6131 return address and the insn in the delay slot (if any). */
6133 return "jmp\t%%o7+%)%#";
6137 /* This is a regular function so we have to restore the register window.
6138 We may have a pending insn for the delay slot, which will be either
6139 combined with the 'restore' instruction or put in the delay slot of
6140 the 'return' instruction. */
6146 delay
= NEXT_INSN (insn
);
6149 pat
= PATTERN (delay
);
6151 if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1))
6153 epilogue_renumber (&pat
, 0);
6154 return "return\t%%i7+%)%#";
6158 output_asm_insn ("jmp\t%%i7+%)", NULL
);
6159 output_restore (pat
);
6160 PATTERN (delay
) = gen_blockage ();
6161 INSN_CODE (delay
) = -1;
6166 /* The delay slot is empty. */
6168 return "return\t%%i7+%)\n\t nop";
6169 else if (flag_delayed_branch
)
6170 return "jmp\t%%i7+%)\n\t restore";
6172 return "restore\n\tjmp\t%%o7+%)\n\t nop";
6179 /* Output a sibling call. */
6182 output_sibcall (rtx_insn
*insn
, rtx call_operand
)
6186 gcc_assert (flag_delayed_branch
);
6188 operands
[0] = call_operand
;
6190 if (sparc_leaf_function_p
|| TARGET_FLAT
)
6192 /* This is a leaf or flat function so we don't have to bother restoring
6193 the register window. We simply output the jump to the function and
6194 the insn in the delay slot (if any). */
6196 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P
&& final_sequence
));
6199 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
6202 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
6203 it into branch if possible. */
6204 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
6209 /* This is a regular function so we have to restore the register window.
6210 We may have a pending insn for the delay slot, which will be combined
6211 with the 'restore' instruction. */
6213 output_asm_insn ("call\t%a0, 0", operands
);
6217 rtx_insn
*delay
= NEXT_INSN (insn
);
6220 output_restore (PATTERN (delay
));
6222 PATTERN (delay
) = gen_blockage ();
6223 INSN_CODE (delay
) = -1;
6226 output_restore (NULL_RTX
);
6232 /* Functions for handling argument passing.
6234 For 32-bit, the first 6 args are normally in registers and the rest are
6235 pushed. Any arg that starts within the first 6 words is at least
6236 partially passed in a register unless its data type forbids.
6238 For 64-bit, the argument registers are laid out as an array of 16 elements
6239 and arguments are added sequentially. The first 6 int args and up to the
6240 first 16 fp args (depending on size) are passed in regs.
6242 Slot Stack Integral Float Float in structure Double Long Double
6243 ---- ----- -------- ----- ------------------ ------ -----------
6244 15 [SP+248] %f31 %f30,%f31 %d30
6245 14 [SP+240] %f29 %f28,%f29 %d28 %q28
6246 13 [SP+232] %f27 %f26,%f27 %d26
6247 12 [SP+224] %f25 %f24,%f25 %d24 %q24
6248 11 [SP+216] %f23 %f22,%f23 %d22
6249 10 [SP+208] %f21 %f20,%f21 %d20 %q20
6250 9 [SP+200] %f19 %f18,%f19 %d18
6251 8 [SP+192] %f17 %f16,%f17 %d16 %q16
6252 7 [SP+184] %f15 %f14,%f15 %d14
6253 6 [SP+176] %f13 %f12,%f13 %d12 %q12
6254 5 [SP+168] %o5 %f11 %f10,%f11 %d10
6255 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
6256 3 [SP+152] %o3 %f7 %f6,%f7 %d6
6257 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
6258 1 [SP+136] %o1 %f3 %f2,%f3 %d2
6259 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
6261 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
6263 Integral arguments are always passed as 64-bit quantities appropriately
6266 Passing of floating point values is handled as follows.
6267 If a prototype is in scope:
6268 If the value is in a named argument (i.e. not a stdarg function or a
6269 value not part of the `...') then the value is passed in the appropriate
6271 If the value is part of the `...' and is passed in one of the first 6
6272 slots then the value is passed in the appropriate int reg.
6273 If the value is part of the `...' and is not passed in one of the first 6
6274 slots then the value is passed in memory.
6275 If a prototype is not in scope:
6276 If the value is one of the first 6 arguments the value is passed in the
6277 appropriate integer reg and the appropriate fp reg.
6278 If the value is not one of the first 6 arguments the value is passed in
6279 the appropriate fp reg and in memory.
6282 Summary of the calling conventions implemented by GCC on the SPARC:
6285 size argument return value
6287 small integer <4 int. reg. int. reg.
6288 word 4 int. reg. int. reg.
6289 double word 8 int. reg. int. reg.
6291 _Complex small integer <8 int. reg. int. reg.
6292 _Complex word 8 int. reg. int. reg.
6293 _Complex double word 16 memory int. reg.
6295 vector integer <=8 int. reg. FP reg.
6296 vector integer >8 memory memory
6298 float 4 int. reg. FP reg.
6299 double 8 int. reg. FP reg.
6300 long double 16 memory memory
6302 _Complex float 8 memory FP reg.
6303 _Complex double 16 memory FP reg.
6304 _Complex long double 32 memory FP reg.
6306 vector float any memory memory
6308 aggregate any memory memory
6313 size argument return value
6315 small integer <8 int. reg. int. reg.
6316 word 8 int. reg. int. reg.
6317 double word 16 int. reg. int. reg.
6319 _Complex small integer <16 int. reg. int. reg.
6320 _Complex word 16 int. reg. int. reg.
6321 _Complex double word 32 memory int. reg.
6323 vector integer <=16 FP reg. FP reg.
6324 vector integer 16<s<=32 memory FP reg.
6325 vector integer >32 memory memory
6327 float 4 FP reg. FP reg.
6328 double 8 FP reg. FP reg.
6329 long double 16 FP reg. FP reg.
6331 _Complex float 8 FP reg. FP reg.
6332 _Complex double 16 FP reg. FP reg.
6333 _Complex long double 32 memory FP reg.
6335 vector float <=16 FP reg. FP reg.
6336 vector float 16<s<=32 memory FP reg.
6337 vector float >32 memory memory
6339 aggregate <=16 reg. reg.
6340 aggregate 16<s<=32 memory reg.
6341 aggregate >32 memory memory
6345 Note #1: complex floating-point types follow the extended SPARC ABIs as
6346 implemented by the Sun compiler.
6348 Note #2: integral vector types follow the scalar floating-point types
6349 conventions to match what is implemented by the Sun VIS SDK.
6351 Note #3: floating-point vector types follow the aggregate types
6355 /* Maximum number of int regs for args. */
6356 #define SPARC_INT_ARG_MAX 6
6357 /* Maximum number of fp regs for args. */
6358 #define SPARC_FP_ARG_MAX 16
6359 /* Number of words (partially) occupied for a given size in units. */
6360 #define CEIL_NWORDS(SIZE) CEIL((SIZE), UNITS_PER_WORD)
6362 /* Handle the INIT_CUMULATIVE_ARGS macro.
6363 Initialize a variable CUM of type CUMULATIVE_ARGS
6364 for a call to a function whose data type is FNTYPE.
6365 For a library call, FNTYPE is 0. */
6368 init_cumulative_args (struct sparc_args
*cum
, tree fntype
, rtx
, tree
)
6371 cum
->prototype_p
= fntype
&& prototype_p (fntype
);
6372 cum
->libcall_p
= !fntype
;
6375 /* Handle promotion of pointer and integer arguments. */
6378 sparc_promote_function_mode (const_tree type
, machine_mode mode
,
6379 int *punsignedp
, const_tree
, int)
6381 if (type
&& POINTER_TYPE_P (type
))
6383 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
6387 /* Integral arguments are passed as full words, as per the ABI. */
6388 if (GET_MODE_CLASS (mode
) == MODE_INT
6389 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
6395 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
6398 sparc_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
6400 return TARGET_ARCH64
? true : false;
6403 /* Traverse the record TYPE recursively and call FUNC on its fields.
6404 NAMED is true if this is for a named parameter. DATA is passed
6405 to FUNC for each field. OFFSET is the starting position and
6406 PACKED is true if we are inside a packed record. */
6408 template <typename T
, void Func (const_tree
, HOST_WIDE_INT
, bool, T
*)>
6410 traverse_record_type (const_tree type
, bool named
, T
*data
,
6411 HOST_WIDE_INT offset
= 0, bool packed
= false)
6413 /* The ABI obviously doesn't specify how packed structures are passed.
6414 These are passed in integer regs if possible, otherwise memory. */
6416 for (tree field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
6417 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
6423 /* Walk the real fields, but skip those with no size or a zero size.
6424 ??? Fields with variable offset are handled as having zero offset. */
6425 for (tree field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
6426 if (TREE_CODE (field
) == FIELD_DECL
)
6428 if (!DECL_SIZE (field
) || integer_zerop (DECL_SIZE (field
)))
6431 HOST_WIDE_INT bitpos
= offset
;
6432 if (TREE_CODE (DECL_FIELD_OFFSET (field
)) == INTEGER_CST
)
6433 bitpos
+= int_bit_position (field
);
6435 tree field_type
= TREE_TYPE (field
);
6436 if (TREE_CODE (field_type
) == RECORD_TYPE
)
6437 traverse_record_type
<T
, Func
> (field_type
, named
, data
, bitpos
,
6442 = FLOAT_TYPE_P (field_type
) || VECTOR_TYPE_P (field_type
);
6443 Func (field
, bitpos
, fp_type
&& named
&& !packed
&& TARGET_FPU
,
6449 /* Handle recursive register classifying for structure layout. */
6453 bool fp_regs
; /* true if field eligible to FP registers. */
6454 bool fp_regs_in_first_word
; /* true if such field in first word. */
6457 /* A subroutine of function_arg_slotno. Classify the field. */
6460 classify_registers (const_tree
, HOST_WIDE_INT bitpos
, bool fp
,
6461 classify_data_t
*data
)
6465 data
->fp_regs
= true;
6466 if (bitpos
< BITS_PER_WORD
)
6467 data
->fp_regs_in_first_word
= true;
6471 /* Compute the slot number to pass an argument in.
6472 Return the slot number or -1 if passing on the stack.
6474 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6475 the preceding args and about the function being called.
6476 MODE is the argument's machine mode.
6477 TYPE is the data type of the argument (as a tree).
6478 This is null for libcalls where that information may
6480 NAMED is nonzero if this argument is a named parameter
6481 (otherwise it is an extra parameter matching an ellipsis).
6482 INCOMING is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
6483 *PREGNO records the register number to use if scalar type.
6484 *PPADDING records the amount of padding needed in words. */
6487 function_arg_slotno (const struct sparc_args
*cum
, machine_mode mode
,
6488 const_tree type
, bool named
, bool incoming
,
6489 int *pregno
, int *ppadding
)
6491 int regbase
= (incoming
6492 ? SPARC_INCOMING_INT_ARG_FIRST
6493 : SPARC_OUTGOING_INT_ARG_FIRST
);
6494 int slotno
= cum
->words
;
6495 enum mode_class mclass
;
6500 if (type
&& TREE_ADDRESSABLE (type
))
6506 && TYPE_ALIGN (type
) % PARM_BOUNDARY
!= 0)
6509 /* For SPARC64, objects requiring 16-byte alignment get it. */
6511 && (type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
)) >= 128
6512 && (slotno
& 1) != 0)
6513 slotno
++, *ppadding
= 1;
6515 mclass
= GET_MODE_CLASS (mode
);
6516 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
6518 /* Vector types deserve special treatment because they are
6519 polymorphic wrt their mode, depending upon whether VIS
6520 instructions are enabled. */
6521 if (TREE_CODE (TREE_TYPE (type
)) == REAL_TYPE
)
6523 /* The SPARC port defines no floating-point vector modes. */
6524 gcc_assert (mode
== BLKmode
);
6528 /* Integral vector types should either have a vector
6529 mode or an integral mode, because we are guaranteed
6530 by pass_by_reference that their size is not greater
6531 than 16 bytes and TImode is 16-byte wide. */
6532 gcc_assert (mode
!= BLKmode
);
6534 /* Vector integers are handled like floats according to
6536 mclass
= MODE_FLOAT
;
6543 case MODE_COMPLEX_FLOAT
:
6544 case MODE_VECTOR_INT
:
6545 if (TARGET_ARCH64
&& TARGET_FPU
&& named
)
6547 /* If all arg slots are filled, then must pass on stack. */
6548 if (slotno
>= SPARC_FP_ARG_MAX
)
6551 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
6552 /* Arguments filling only one single FP register are
6553 right-justified in the outer double FP register. */
6554 if (GET_MODE_SIZE (mode
) <= 4)
6561 case MODE_COMPLEX_INT
:
6562 /* If all arg slots are filled, then must pass on stack. */
6563 if (slotno
>= SPARC_INT_ARG_MAX
)
6566 regno
= regbase
+ slotno
;
6570 if (mode
== VOIDmode
)
6571 /* MODE is VOIDmode when generating the actual call. */
6574 gcc_assert (mode
== BLKmode
);
6578 || (TREE_CODE (type
) != RECORD_TYPE
6579 && TREE_CODE (type
) != VECTOR_TYPE
))
6581 /* If all arg slots are filled, then must pass on stack. */
6582 if (slotno
>= SPARC_INT_ARG_MAX
)
6585 regno
= regbase
+ slotno
;
6587 else /* TARGET_ARCH64 && type */
6589 /* If all arg slots are filled, then must pass on stack. */
6590 if (slotno
>= SPARC_FP_ARG_MAX
)
6593 if (TREE_CODE (type
) == RECORD_TYPE
)
6595 classify_data_t data
= { false, false };
6596 traverse_record_type
<classify_data_t
, classify_registers
>
6597 (type
, named
, &data
);
6601 /* If all FP slots are filled except for the last one and
6602 there is no FP field in the first word, then must pass
6604 if (slotno
>= SPARC_FP_ARG_MAX
- 1
6605 && !data
.fp_regs_in_first_word
)
6610 /* If all int slots are filled, then must pass on stack. */
6611 if (slotno
>= SPARC_INT_ARG_MAX
)
6616 /* PREGNO isn't set since both int and FP regs can be used. */
6629 /* Handle recursive register counting/assigning for structure layout. */
6633 int slotno
; /* slot number of the argument. */
6634 int regbase
; /* regno of the base register. */
6635 int intoffset
; /* offset of the first pending integer field. */
6636 int nregs
; /* number of words passed in registers. */
6637 bool stack
; /* true if part of the argument is on the stack. */
6638 rtx ret
; /* return expression being built. */
6641 /* A subroutine of function_arg_record_value. Compute the number of integer
6642 registers to be assigned between PARMS->intoffset and BITPOS. Return
6643 true if at least one integer register is assigned or false otherwise. */
6646 compute_int_layout (HOST_WIDE_INT bitpos
, assign_data_t
*data
, int *pnregs
)
6648 if (data
->intoffset
< 0)
6651 const int intoffset
= data
->intoffset
;
6652 data
->intoffset
= -1;
6654 const int this_slotno
= data
->slotno
+ intoffset
/ BITS_PER_WORD
;
6655 const unsigned int startbit
= ROUND_DOWN (intoffset
, BITS_PER_WORD
);
6656 const unsigned int endbit
= ROUND_UP (bitpos
, BITS_PER_WORD
);
6657 int nregs
= (endbit
- startbit
) / BITS_PER_WORD
;
6659 if (nregs
> 0 && nregs
> SPARC_INT_ARG_MAX
- this_slotno
)
6661 nregs
= SPARC_INT_ARG_MAX
- this_slotno
;
6663 /* We need to pass this field (partly) on the stack. */
6674 /* A subroutine of function_arg_record_value. Compute the number and the mode
6675 of the FP registers to be assigned for FIELD. Return true if at least one
6676 FP register is assigned or false otherwise. */
6679 compute_fp_layout (const_tree field
, HOST_WIDE_INT bitpos
,
6680 assign_data_t
*data
,
6681 int *pnregs
, machine_mode
*pmode
)
6683 const int this_slotno
= data
->slotno
+ bitpos
/ BITS_PER_WORD
;
6684 machine_mode mode
= DECL_MODE (field
);
6687 /* Slots are counted as words while regs are counted as having the size of
6688 the (inner) mode. */
6689 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
&& mode
== BLKmode
)
6691 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
6692 nregs
= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
6694 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
6696 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
6702 nslots
= CEIL_NWORDS (nregs
* GET_MODE_SIZE (mode
));
6704 if (nslots
> SPARC_FP_ARG_MAX
- this_slotno
)
6706 nslots
= SPARC_FP_ARG_MAX
- this_slotno
;
6707 nregs
= (nslots
* UNITS_PER_WORD
) / GET_MODE_SIZE (mode
);
6709 /* We need to pass this field (partly) on the stack. */
6721 /* A subroutine of function_arg_record_value. Count the number of registers
6722 to be assigned for FIELD and between PARMS->intoffset and BITPOS. */
6725 count_registers (const_tree field
, HOST_WIDE_INT bitpos
, bool fp
,
6726 assign_data_t
*data
)
6733 if (compute_int_layout (bitpos
, data
, &nregs
))
6734 data
->nregs
+= nregs
;
6736 if (compute_fp_layout (field
, bitpos
, data
, &nregs
, &mode
))
6737 data
->nregs
+= nregs
;
6741 if (data
->intoffset
< 0)
6742 data
->intoffset
= bitpos
;
6746 /* A subroutine of function_arg_record_value. Assign the bits of the
6747 structure between PARMS->intoffset and BITPOS to integer registers. */
6750 assign_int_registers (HOST_WIDE_INT bitpos
, assign_data_t
*data
)
6752 int intoffset
= data
->intoffset
;
6756 if (!compute_int_layout (bitpos
, data
, &nregs
))
6759 /* If this is the trailing part of a word, only load that much into
6760 the register. Otherwise load the whole register. Note that in
6761 the latter case we may pick up unwanted bits. It's not a problem
6762 at the moment but may wish to revisit. */
6763 if (intoffset
% BITS_PER_WORD
!= 0)
6764 mode
= smallest_mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
6769 const int this_slotno
= data
->slotno
+ intoffset
/ BITS_PER_WORD
;
6770 unsigned int regno
= data
->regbase
+ this_slotno
;
6771 intoffset
/= BITS_PER_UNIT
;
6775 rtx reg
= gen_rtx_REG (mode
, regno
);
6776 XVECEXP (data
->ret
, 0, data
->stack
+ data
->nregs
)
6777 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
6781 intoffset
= (intoffset
| (UNITS_PER_WORD
- 1)) + 1;
6783 while (--nregs
> 0);
6786 /* A subroutine of function_arg_record_value. Assign FIELD at position
6787 BITPOS to FP registers. */
6790 assign_fp_registers (const_tree field
, HOST_WIDE_INT bitpos
,
6791 assign_data_t
*data
)
6796 if (!compute_fp_layout (field
, bitpos
, data
, &nregs
, &mode
))
6799 const int this_slotno
= data
->slotno
+ bitpos
/ BITS_PER_WORD
;
6800 int regno
= SPARC_FP_ARG_FIRST
+ this_slotno
* 2;
6801 if (GET_MODE_SIZE (mode
) <= 4 && (bitpos
& 32) != 0)
6803 int pos
= bitpos
/ BITS_PER_UNIT
;
6807 rtx reg
= gen_rtx_REG (mode
, regno
);
6808 XVECEXP (data
->ret
, 0, data
->stack
+ data
->nregs
)
6809 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
6811 regno
+= GET_MODE_SIZE (mode
) / 4;
6812 pos
+= GET_MODE_SIZE (mode
);
6814 while (--nregs
> 0);
6817 /* A subroutine of function_arg_record_value. Assign FIELD and the bits of
6818 the structure between PARMS->intoffset and BITPOS to registers. */
6821 assign_registers (const_tree field
, HOST_WIDE_INT bitpos
, bool fp
,
6822 assign_data_t
*data
)
6826 assign_int_registers (bitpos
, data
);
6828 assign_fp_registers (field
, bitpos
, data
);
6832 if (data
->intoffset
< 0)
6833 data
->intoffset
= bitpos
;
6837 /* Used by function_arg and sparc_function_value_1 to implement the complex
6838 conventions of the 64-bit ABI for passing and returning structures.
6839 Return an expression valid as a return value for the FUNCTION_ARG
6840 and TARGET_FUNCTION_VALUE.
6842 TYPE is the data type of the argument (as a tree).
6843 This is null for libcalls where that information may
6845 MODE is the argument's machine mode.
6846 SLOTNO is the index number of the argument's slot in the parameter array.
6847 NAMED is true if this argument is a named parameter
6848 (otherwise it is an extra parameter matching an ellipsis).
6849 REGBASE is the regno of the base register for the parameter array. */
6852 function_arg_record_value (const_tree type
, machine_mode mode
,
6853 int slotno
, bool named
, int regbase
)
6855 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
6859 data
.slotno
= slotno
;
6860 data
.regbase
= regbase
;
6862 /* Count how many registers we need. */
6866 traverse_record_type
<assign_data_t
, count_registers
> (type
, named
, &data
);
6868 /* Take into account pending integer fields. */
6869 if (compute_int_layout (typesize
* BITS_PER_UNIT
, &data
, &nregs
))
6870 data
.nregs
+= nregs
;
6872 /* Allocate the vector and handle some annoying special cases. */
6877 /* ??? Empty structure has no value? Duh? */
6880 /* Though there's nothing really to store, return a word register
6881 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
6882 leads to breakage due to the fact that there are zero bytes to
6884 return gen_rtx_REG (mode
, regbase
);
6887 /* ??? C++ has structures with no fields, and yet a size. Give up
6888 for now and pass everything back in integer registers. */
6889 nregs
= (typesize
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6890 if (nregs
+ slotno
> SPARC_INT_ARG_MAX
)
6891 nregs
= SPARC_INT_ARG_MAX
- slotno
;
6894 gcc_assert (nregs
> 0);
6896 data
.ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (data
.stack
+ nregs
));
6898 /* If at least one field must be passed on the stack, generate
6899 (parallel [(expr_list (nil) ...) ...]) so that all fields will
6900 also be passed on the stack. We can't do much better because the
6901 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
6902 of structures for which the fields passed exclusively in registers
6903 are not at the beginning of the structure. */
6905 XVECEXP (data
.ret
, 0, 0)
6906 = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
6908 /* Assign the registers. */
6911 traverse_record_type
<assign_data_t
, assign_registers
> (type
, named
, &data
);
6913 /* Assign pending integer fields. */
6914 assign_int_registers (typesize
* BITS_PER_UNIT
, &data
);
6916 gcc_assert (data
.nregs
== nregs
);
6921 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6922 of the 64-bit ABI for passing and returning unions.
6923 Return an expression valid as a return value for the FUNCTION_ARG
6924 and TARGET_FUNCTION_VALUE.
6926 SIZE is the size in bytes of the union.
6927 MODE is the argument's machine mode.
6928 REGNO is the hard register the union will be passed in. */
6931 function_arg_union_value (int size
, machine_mode mode
, int slotno
,
6934 int nwords
= CEIL_NWORDS (size
), i
;
6937 /* See comment in previous function for empty structures. */
6939 return gen_rtx_REG (mode
, regno
);
6941 if (slotno
== SPARC_INT_ARG_MAX
- 1)
6944 regs
= gen_rtx_PARALLEL (mode
, rtvec_alloc (nwords
));
6946 for (i
= 0; i
< nwords
; i
++)
6948 /* Unions are passed left-justified. */
6949 XVECEXP (regs
, 0, i
)
6950 = gen_rtx_EXPR_LIST (VOIDmode
,
6951 gen_rtx_REG (word_mode
, regno
),
6952 GEN_INT (UNITS_PER_WORD
* i
));
6959 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6960 for passing and returning BLKmode vectors.
6961 Return an expression valid as a return value for the FUNCTION_ARG
6962 and TARGET_FUNCTION_VALUE.
6964 SIZE is the size in bytes of the vector.
6965 REGNO is the FP hard register the vector will be passed in. */
6968 function_arg_vector_value (int size
, int regno
)
6970 const int nregs
= MAX (1, size
/ 8);
6971 rtx regs
= gen_rtx_PARALLEL (BLKmode
, rtvec_alloc (nregs
));
6974 XVECEXP (regs
, 0, 0)
6975 = gen_rtx_EXPR_LIST (VOIDmode
,
6976 gen_rtx_REG (SImode
, regno
),
6979 for (int i
= 0; i
< nregs
; i
++)
6980 XVECEXP (regs
, 0, i
)
6981 = gen_rtx_EXPR_LIST (VOIDmode
,
6982 gen_rtx_REG (DImode
, regno
+ 2*i
),
6988 /* Determine where to put an argument to a function.
6989 Value is zero to push the argument on the stack,
6990 or a hard register in which to store the argument.
6992 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6993 the preceding args and about the function being called.
6994 MODE is the argument's machine mode.
6995 TYPE is the data type of the argument (as a tree).
6996 This is null for libcalls where that information may
6998 NAMED is true if this argument is a named parameter
6999 (otherwise it is an extra parameter matching an ellipsis).
7000 INCOMING_P is false for TARGET_FUNCTION_ARG, true for
7001 TARGET_FUNCTION_INCOMING_ARG. */
7004 sparc_function_arg_1 (cumulative_args_t cum_v
, machine_mode mode
,
7005 const_tree type
, bool named
, bool incoming
)
7007 const CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
7009 int regbase
= (incoming
7010 ? SPARC_INCOMING_INT_ARG_FIRST
7011 : SPARC_OUTGOING_INT_ARG_FIRST
);
7012 int slotno
, regno
, padding
;
7013 enum mode_class mclass
= GET_MODE_CLASS (mode
);
7015 slotno
= function_arg_slotno (cum
, mode
, type
, named
, incoming
,
7020 /* Vector types deserve special treatment because they are polymorphic wrt
7021 their mode, depending upon whether VIS instructions are enabled. */
7022 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
7024 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7025 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
7026 || (TARGET_ARCH64
&& size
<= 16));
7028 if (mode
== BLKmode
)
7029 return function_arg_vector_value (size
, SPARC_FP_ARG_FIRST
+ 2*slotno
);
7031 mclass
= MODE_FLOAT
;
7035 return gen_rtx_REG (mode
, regno
);
7037 /* Structures up to 16 bytes in size are passed in arg slots on the stack
7038 and are promoted to registers if possible. */
7039 if (type
&& TREE_CODE (type
) == RECORD_TYPE
)
7041 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7042 gcc_assert (size
<= 16);
7044 return function_arg_record_value (type
, mode
, slotno
, named
, regbase
);
7047 /* Unions up to 16 bytes in size are passed in integer registers. */
7048 else if (type
&& TREE_CODE (type
) == UNION_TYPE
)
7050 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7051 gcc_assert (size
<= 16);
7053 return function_arg_union_value (size
, mode
, slotno
, regno
);
7056 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
7057 but also have the slot allocated for them.
7058 If no prototype is in scope fp values in register slots get passed
7059 in two places, either fp regs and int regs or fp regs and memory. */
7060 else if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
7061 && SPARC_FP_REG_P (regno
))
7063 rtx reg
= gen_rtx_REG (mode
, regno
);
7064 if (cum
->prototype_p
|| cum
->libcall_p
)
7070 if ((regno
- SPARC_FP_ARG_FIRST
) < SPARC_INT_ARG_MAX
* 2)
7074 /* On incoming, we don't need to know that the value
7075 is passed in %f0 and %i0, and it confuses other parts
7076 causing needless spillage even on the simplest cases. */
7080 intreg
= (SPARC_OUTGOING_INT_ARG_FIRST
7081 + (regno
- SPARC_FP_ARG_FIRST
) / 2);
7083 v0
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
7084 v1
= gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (mode
, intreg
),
7086 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
7090 v0
= gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
7091 v1
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
7092 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
7097 /* All other aggregate types are passed in an integer register in a mode
7098 corresponding to the size of the type. */
7099 else if (type
&& AGGREGATE_TYPE_P (type
))
7101 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7102 gcc_assert (size
<= 16);
7104 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
7107 return gen_rtx_REG (mode
, regno
);
7110 /* Handle the TARGET_FUNCTION_ARG target hook. */
7113 sparc_function_arg (cumulative_args_t cum
, machine_mode mode
,
7114 const_tree type
, bool named
)
7116 return sparc_function_arg_1 (cum
, mode
, type
, named
, false);
7119 /* Handle the TARGET_FUNCTION_INCOMING_ARG target hook. */
7122 sparc_function_incoming_arg (cumulative_args_t cum
, machine_mode mode
,
7123 const_tree type
, bool named
)
7125 return sparc_function_arg_1 (cum
, mode
, type
, named
, true);
7128 /* For sparc64, objects requiring 16 byte alignment are passed that way. */
7131 sparc_function_arg_boundary (machine_mode mode
, const_tree type
)
7133 return ((TARGET_ARCH64
7134 && (GET_MODE_ALIGNMENT (mode
) == 128
7135 || (type
&& TYPE_ALIGN (type
) == 128)))
7140 /* For an arg passed partly in registers and partly in memory,
7141 this is the number of bytes of registers used.
7142 For args passed entirely in registers or entirely in memory, zero.
7144 Any arg that starts in the first 6 regs but won't entirely fit in them
7145 needs partial registers on v8. On v9, structures with integer
7146 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
7147 values that begin in the last fp reg [where "last fp reg" varies with the
7148 mode] will be split between that reg and memory. */
7151 sparc_arg_partial_bytes (cumulative_args_t cum
, machine_mode mode
,
7152 tree type
, bool named
)
7154 int slotno
, regno
, padding
;
7156 /* We pass false for incoming here, it doesn't matter. */
7157 slotno
= function_arg_slotno (get_cumulative_args (cum
), mode
, type
, named
,
7158 false, ®no
, &padding
);
7165 if ((slotno
+ (mode
== BLKmode
7166 ? CEIL_NWORDS (int_size_in_bytes (type
))
7167 : CEIL_NWORDS (GET_MODE_SIZE (mode
))))
7168 > SPARC_INT_ARG_MAX
)
7169 return (SPARC_INT_ARG_MAX
- slotno
) * UNITS_PER_WORD
;
7173 /* We are guaranteed by pass_by_reference that the size of the
7174 argument is not greater than 16 bytes, so we only need to return
7175 one word if the argument is partially passed in registers. */
7177 if (type
&& AGGREGATE_TYPE_P (type
))
7179 int size
= int_size_in_bytes (type
);
7181 if (size
> UNITS_PER_WORD
7182 && (slotno
== SPARC_INT_ARG_MAX
- 1
7183 || slotno
== SPARC_FP_ARG_MAX
- 1))
7184 return UNITS_PER_WORD
;
7186 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
7187 || (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
7188 && ! (TARGET_FPU
&& named
)))
7190 /* The complex types are passed as packed types. */
7191 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
7192 && slotno
== SPARC_INT_ARG_MAX
- 1)
7193 return UNITS_PER_WORD
;
7195 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
7197 if ((slotno
+ GET_MODE_SIZE (mode
) / UNITS_PER_WORD
)
7199 return UNITS_PER_WORD
;
7206 /* Handle the TARGET_PASS_BY_REFERENCE target hook.
7207 Specify whether to pass the argument by reference. */
7210 sparc_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
7211 machine_mode mode
, const_tree type
,
7212 bool named ATTRIBUTE_UNUSED
)
7215 /* Original SPARC 32-bit ABI says that structures and unions,
7216 and quad-precision floats are passed by reference. For Pascal,
7217 also pass arrays by reference. All other base types are passed
7220 Extended ABI (as implemented by the Sun compiler) says that all
7221 complex floats are passed by reference. Pass complex integers
7222 in registers up to 8 bytes. More generally, enforce the 2-word
7223 cap for passing arguments in registers.
7225 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7226 integers are passed like floats of the same size, that is in
7227 registers up to 8 bytes. Pass all vector floats by reference
7228 like structure and unions. */
7229 return ((type
&& (AGGREGATE_TYPE_P (type
) || VECTOR_FLOAT_TYPE_P (type
)))
7231 /* Catch CDImode, TFmode, DCmode and TCmode. */
7232 || GET_MODE_SIZE (mode
) > 8
7234 && TREE_CODE (type
) == VECTOR_TYPE
7235 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
7237 /* Original SPARC 64-bit ABI says that structures and unions
7238 smaller than 16 bytes are passed in registers, as well as
7239 all other base types.
7241 Extended ABI (as implemented by the Sun compiler) says that
7242 complex floats are passed in registers up to 16 bytes. Pass
7243 all complex integers in registers up to 16 bytes. More generally,
7244 enforce the 2-word cap for passing arguments in registers.
7246 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7247 integers are passed like floats of the same size, that is in
7248 registers (up to 16 bytes). Pass all vector floats like structure
7251 && (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == VECTOR_TYPE
)
7252 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 16)
7253 /* Catch CTImode and TCmode. */
7254 || GET_MODE_SIZE (mode
) > 16);
7257 /* Handle the TARGET_FUNCTION_ARG_ADVANCE hook.
7258 Update the data in CUM to advance over an argument
7259 of mode MODE and data type TYPE.
7260 TYPE is null for libcalls where that information may not be available. */
7263 sparc_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
7264 const_tree type
, bool named
)
7266 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
7269 /* We pass false for incoming here, it doesn't matter. */
7270 function_arg_slotno (cum
, mode
, type
, named
, false, ®no
, &padding
);
7272 /* If argument requires leading padding, add it. */
7273 cum
->words
+= padding
;
7276 cum
->words
+= (mode
== BLKmode
7277 ? CEIL_NWORDS (int_size_in_bytes (type
))
7278 : CEIL_NWORDS (GET_MODE_SIZE (mode
)));
7281 if (type
&& AGGREGATE_TYPE_P (type
))
7283 int size
= int_size_in_bytes (type
);
7287 else if (size
<= 16)
7289 else /* passed by reference */
7293 cum
->words
+= (mode
== BLKmode
7294 ? CEIL_NWORDS (int_size_in_bytes (type
))
7295 : CEIL_NWORDS (GET_MODE_SIZE (mode
)));
7299 /* Handle the FUNCTION_ARG_PADDING macro.
7300 For the 64 bit ABI structs are always stored left shifted in their
7304 function_arg_padding (machine_mode mode
, const_tree type
)
7306 if (TARGET_ARCH64
&& type
&& AGGREGATE_TYPE_P (type
))
7309 /* Fall back to the default. */
7310 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
7313 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
7314 Specify whether to return the return value in memory. */
7317 sparc_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
7320 /* Original SPARC 32-bit ABI says that structures and unions,
7321 and quad-precision floats are returned in memory. All other
7322 base types are returned in registers.
7324 Extended ABI (as implemented by the Sun compiler) says that
7325 all complex floats are returned in registers (8 FP registers
7326 at most for '_Complex long double'). Return all complex integers
7327 in registers (4 at most for '_Complex long long').
7329 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7330 integers are returned like floats of the same size, that is in
7331 registers up to 8 bytes and in memory otherwise. Return all
7332 vector floats in memory like structure and unions; note that
7333 they always have BLKmode like the latter. */
7334 return (TYPE_MODE (type
) == BLKmode
7335 || TYPE_MODE (type
) == TFmode
7336 || (TREE_CODE (type
) == VECTOR_TYPE
7337 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
7339 /* Original SPARC 64-bit ABI says that structures and unions
7340 smaller than 32 bytes are returned in registers, as well as
7341 all other base types.
7343 Extended ABI (as implemented by the Sun compiler) says that all
7344 complex floats are returned in registers (8 FP registers at most
7345 for '_Complex long double'). Return all complex integers in
7346 registers (4 at most for '_Complex TItype').
7348 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7349 integers are returned like floats of the same size, that is in
7350 registers. Return all vector floats like structure and unions;
7351 note that they always have BLKmode like the latter. */
7352 return (TYPE_MODE (type
) == BLKmode
7353 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 32);
7356 /* Handle the TARGET_STRUCT_VALUE target hook.
7357 Return where to find the structure return value address. */
7360 sparc_struct_value_rtx (tree fndecl
, int incoming
)
7369 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, frame_pointer_rtx
,
7370 STRUCT_VALUE_OFFSET
));
7372 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, stack_pointer_rtx
,
7373 STRUCT_VALUE_OFFSET
));
7375 /* Only follow the SPARC ABI for fixed-size structure returns.
7376 Variable size structure returns are handled per the normal
7377 procedures in GCC. This is enabled by -mstd-struct-return */
7379 && sparc_std_struct_return
7380 && TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))
7381 && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))) == INTEGER_CST
)
7383 /* We must check and adjust the return address, as it is optional
7384 as to whether the return object is really provided. */
7385 rtx ret_reg
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
7386 rtx scratch
= gen_reg_rtx (SImode
);
7387 rtx_code_label
*endlab
= gen_label_rtx ();
7389 /* Calculate the return object size. */
7390 tree size
= TYPE_SIZE_UNIT (TREE_TYPE (fndecl
));
7391 rtx size_rtx
= GEN_INT (TREE_INT_CST_LOW (size
) & 0xfff);
7392 /* Construct a temporary return value. */
7394 = assign_stack_local (Pmode
, TREE_INT_CST_LOW (size
), 0);
7396 /* Implement SPARC 32-bit psABI callee return struct checking:
7398 Fetch the instruction where we will return to and see if
7399 it's an unimp instruction (the most significant 10 bits
7401 emit_move_insn (scratch
, gen_rtx_MEM (SImode
,
7402 plus_constant (Pmode
,
7404 /* Assume the size is valid and pre-adjust. */
7405 emit_insn (gen_add3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
7406 emit_cmp_and_jump_insns (scratch
, size_rtx
, EQ
, const0_rtx
, SImode
,
7408 emit_insn (gen_sub3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
7409 /* Write the address of the memory pointed to by temp_val into
7410 the memory pointed to by mem. */
7411 emit_move_insn (mem
, XEXP (temp_val
, 0));
7412 emit_label (endlab
);
7419 /* Handle TARGET_FUNCTION_VALUE, and TARGET_LIBCALL_VALUE target hook.
7420 For v9, function return values are subject to the same rules as arguments,
7421 except that up to 32 bytes may be returned in registers. */
7424 sparc_function_value_1 (const_tree type
, machine_mode mode
,
7427 /* Beware that the two values are swapped here wrt function_arg. */
7428 int regbase
= (outgoing
7429 ? SPARC_INCOMING_INT_ARG_FIRST
7430 : SPARC_OUTGOING_INT_ARG_FIRST
);
7431 enum mode_class mclass
= GET_MODE_CLASS (mode
);
7434 /* Vector types deserve special treatment because they are polymorphic wrt
7435 their mode, depending upon whether VIS instructions are enabled. */
7436 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
7438 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7439 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
7440 || (TARGET_ARCH64
&& size
<= 32));
7442 if (mode
== BLKmode
)
7443 return function_arg_vector_value (size
, SPARC_FP_ARG_FIRST
);
7445 mclass
= MODE_FLOAT
;
7448 if (TARGET_ARCH64
&& type
)
7450 /* Structures up to 32 bytes in size are returned in registers. */
7451 if (TREE_CODE (type
) == RECORD_TYPE
)
7453 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7454 gcc_assert (size
<= 32);
7456 return function_arg_record_value (type
, mode
, 0, 1, regbase
);
7459 /* Unions up to 32 bytes in size are returned in integer registers. */
7460 else if (TREE_CODE (type
) == UNION_TYPE
)
7462 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7463 gcc_assert (size
<= 32);
7465 return function_arg_union_value (size
, mode
, 0, regbase
);
7468 /* Objects that require it are returned in FP registers. */
7469 else if (mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
7472 /* All other aggregate types are returned in an integer register in a
7473 mode corresponding to the size of the type. */
7474 else if (AGGREGATE_TYPE_P (type
))
7476 /* All other aggregate types are passed in an integer register
7477 in a mode corresponding to the size of the type. */
7478 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7479 gcc_assert (size
<= 32);
7481 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
7483 /* ??? We probably should have made the same ABI change in
7484 3.4.0 as the one we made for unions. The latter was
7485 required by the SCD though, while the former is not
7486 specified, so we favored compatibility and efficiency.
7488 Now we're stuck for aggregates larger than 16 bytes,
7489 because OImode vanished in the meantime. Let's not
7490 try to be unduly clever, and simply follow the ABI
7491 for unions in that case. */
7492 if (mode
== BLKmode
)
7493 return function_arg_union_value (size
, mode
, 0, regbase
);
7498 /* We should only have pointer and integer types at this point. This
7499 must match sparc_promote_function_mode. */
7500 else if (mclass
== MODE_INT
&& GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
7504 /* We should only have pointer and integer types at this point, except with
7505 -freg-struct-return. This must match sparc_promote_function_mode. */
7506 else if (TARGET_ARCH32
7507 && !(type
&& AGGREGATE_TYPE_P (type
))
7508 && mclass
== MODE_INT
7509 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
7512 if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
) && TARGET_FPU
)
7513 regno
= SPARC_FP_ARG_FIRST
;
7517 return gen_rtx_REG (mode
, regno
);
7520 /* Handle TARGET_FUNCTION_VALUE.
7521 On the SPARC, the value is found in the first "output" register, but the
7522 called function leaves it in the first "input" register. */
7525 sparc_function_value (const_tree valtype
,
7526 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
7529 return sparc_function_value_1 (valtype
, TYPE_MODE (valtype
), outgoing
);
7532 /* Handle TARGET_LIBCALL_VALUE. */
7535 sparc_libcall_value (machine_mode mode
,
7536 const_rtx fun ATTRIBUTE_UNUSED
)
7538 return sparc_function_value_1 (NULL_TREE
, mode
, false);
7541 /* Handle FUNCTION_VALUE_REGNO_P.
7542 On the SPARC, the first "output" reg is used for integer values, and the
7543 first floating point register is used for floating point values. */
7546 sparc_function_value_regno_p (const unsigned int regno
)
7548 return (regno
== 8 || (TARGET_FPU
&& regno
== 32));
7551 /* Do what is necessary for `va_start'. We look at the current function
7552 to determine if stdarg or varargs is used and return the address of
7553 the first unnamed parameter. */
7556 sparc_builtin_saveregs (void)
7558 int first_reg
= crtl
->args
.info
.words
;
7562 for (regno
= first_reg
; regno
< SPARC_INT_ARG_MAX
; regno
++)
7563 emit_move_insn (gen_rtx_MEM (word_mode
,
7564 gen_rtx_PLUS (Pmode
,
7566 GEN_INT (FIRST_PARM_OFFSET (0)
7569 gen_rtx_REG (word_mode
,
7570 SPARC_INCOMING_INT_ARG_FIRST
+ regno
));
7572 address
= gen_rtx_PLUS (Pmode
,
7574 GEN_INT (FIRST_PARM_OFFSET (0)
7575 + UNITS_PER_WORD
* first_reg
));
7580 /* Implement `va_start' for stdarg. */
7583 sparc_va_start (tree valist
, rtx nextarg
)
7585 nextarg
= expand_builtin_saveregs ();
7586 std_expand_builtin_va_start (valist
, nextarg
);
7589 /* Implement `va_arg' for stdarg. */
7592 sparc_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
7595 HOST_WIDE_INT size
, rsize
, align
;
7598 tree ptrtype
= build_pointer_type (type
);
7600 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
7603 size
= rsize
= UNITS_PER_WORD
;
7609 size
= int_size_in_bytes (type
);
7610 rsize
= ROUND_UP (size
, UNITS_PER_WORD
);
7615 /* For SPARC64, objects requiring 16-byte alignment get it. */
7616 if (TYPE_ALIGN (type
) >= 2 * (unsigned) BITS_PER_WORD
)
7617 align
= 2 * UNITS_PER_WORD
;
7619 /* SPARC-V9 ABI states that structures up to 16 bytes in size
7620 are left-justified in their slots. */
7621 if (AGGREGATE_TYPE_P (type
))
7624 size
= rsize
= UNITS_PER_WORD
;
7634 incr
= fold_build_pointer_plus_hwi (incr
, align
- 1);
7635 incr
= fold_convert (sizetype
, incr
);
7636 incr
= fold_build2 (BIT_AND_EXPR
, sizetype
, incr
,
7638 incr
= fold_convert (ptr_type_node
, incr
);
7641 gimplify_expr (&incr
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
7644 if (BYTES_BIG_ENDIAN
&& size
< rsize
)
7645 addr
= fold_build_pointer_plus_hwi (incr
, rsize
- size
);
7649 addr
= fold_convert (build_pointer_type (ptrtype
), addr
);
7650 addr
= build_va_arg_indirect_ref (addr
);
7653 /* If the address isn't aligned properly for the type, we need a temporary.
7654 FIXME: This is inefficient, usually we can do this in registers. */
7655 else if (align
== 0 && TYPE_ALIGN (type
) > BITS_PER_WORD
)
7657 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
7658 tree dest_addr
= build_fold_addr_expr (tmp
);
7659 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
7660 3, dest_addr
, addr
, size_int (rsize
));
7661 TREE_ADDRESSABLE (tmp
) = 1;
7662 gimplify_and_add (copy
, pre_p
);
7667 addr
= fold_convert (ptrtype
, addr
);
7669 incr
= fold_build_pointer_plus_hwi (incr
, rsize
);
7670 gimplify_assign (valist
, incr
, post_p
);
7672 return build_va_arg_indirect_ref (addr
);
7675 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
7676 Specify whether the vector mode is supported by the hardware. */
7679 sparc_vector_mode_supported_p (machine_mode mode
)
7681 return TARGET_VIS
&& VECTOR_MODE_P (mode
) ? true : false;
7684 /* Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook. */
7687 sparc_preferred_simd_mode (machine_mode mode
)
7705 /* Return the string to output an unconditional branch to LABEL, which is
7706 the operand number of the label.
7708 DEST is the destination insn (i.e. the label), INSN is the source. */
7711 output_ubranch (rtx dest
, rtx_insn
*insn
)
7713 static char string
[64];
7714 bool v9_form
= false;
7718 /* Even if we are trying to use cbcond for this, evaluate
7719 whether we can use V9 branches as our backup plan. */
7722 if (INSN_ADDRESSES_SET_P ())
7723 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
7724 - INSN_ADDRESSES (INSN_UID (insn
)));
7726 /* Leave some instructions for "slop". */
7727 if (TARGET_V9
&& delta
>= -260000 && delta
< 260000)
7732 bool emit_nop
= emit_cbcond_nop (insn
);
7736 if (delta
< -500 || delta
> 500)
7742 rval
= "ba,a,pt\t%%xcc, %l0";
7749 rval
= "cwbe\t%%g0, %%g0, %l0\n\tnop";
7751 rval
= "cwbe\t%%g0, %%g0, %l0";
7757 strcpy (string
, "ba%*,pt\t%%xcc, ");
7759 strcpy (string
, "b%*\t");
7761 p
= strchr (string
, '\0');
7772 /* Return the string to output a conditional branch to LABEL, which is
7773 the operand number of the label. OP is the conditional expression.
7774 XEXP (OP, 0) is assumed to be a condition code register (integer or
7775 floating point) and its mode specifies what kind of comparison we made.
7777 DEST is the destination insn (i.e. the label), INSN is the source.
7779 REVERSED is nonzero if we should reverse the sense of the comparison.
7781 ANNUL is nonzero if we should generate an annulling branch. */
7784 output_cbranch (rtx op
, rtx dest
, int label
, int reversed
, int annul
,
7787 static char string
[64];
7788 enum rtx_code code
= GET_CODE (op
);
7789 rtx cc_reg
= XEXP (op
, 0);
7790 machine_mode mode
= GET_MODE (cc_reg
);
7791 const char *labelno
, *branch
;
7792 int spaces
= 8, far
;
7795 /* v9 branches are limited to +-1MB. If it is too far away,
7808 fbne,a,pn %fcc2, .LC29
7816 far
= TARGET_V9
&& (get_attr_length (insn
) >= 3);
7819 /* Reversal of FP compares takes care -- an ordered compare
7820 becomes an unordered compare and vice versa. */
7821 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7822 code
= reverse_condition_maybe_unordered (code
);
7824 code
= reverse_condition (code
);
7827 /* Start by writing the branch condition. */
7828 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7878 /* ??? !v9: FP branches cannot be preceded by another floating point
7879 insn. Because there is currently no concept of pre-delay slots,
7880 we can fix this only by always emitting a nop before a floating
7885 strcpy (string
, "nop\n\t");
7886 strcat (string
, branch
);
7893 if (mode
== CCVmode
|| mode
== CCXVmode
)
7899 if (mode
== CCVmode
|| mode
== CCXVmode
)
7905 if (mode
== CCNZmode
|| mode
== CCXNZmode
)
7917 if (mode
== CCNZmode
|| mode
== CCXNZmode
)
7937 strcpy (string
, branch
);
7939 spaces
-= strlen (branch
);
7940 p
= strchr (string
, '\0');
7942 /* Now add the annulling, the label, and a possible noop. */
7955 if (! far
&& insn
&& INSN_ADDRESSES_SET_P ())
7957 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
7958 - INSN_ADDRESSES (INSN_UID (insn
)));
7959 /* Leave some instructions for "slop". */
7960 if (delta
< -260000 || delta
>= 260000)
7970 labelno
= "%%icc, ";
7978 labelno
= "%%xcc, ";
7984 static char v9_fcc_labelno
[] = "%%fccX, ";
7985 /* Set the char indicating the number of the fcc reg to use. */
7986 v9_fcc_labelno
[5] = REGNO (cc_reg
) - SPARC_FIRST_V9_FCC_REG
+ '0';
7987 labelno
= v9_fcc_labelno
;
7990 gcc_assert (REGNO (cc_reg
) == SPARC_FCC_REG
);
7999 if (*labelno
&& insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
8002 ((profile_probability::from_reg_br_prob_note (XINT (note
, 0))
8003 >= profile_probability::even ()) ^ far
)
8016 strcpy (p
, labelno
);
8017 p
= strchr (p
, '\0');
8020 strcpy (p
, ".+12\n\t nop\n\tb\t");
8021 /* Skip the next insn if requested or
8022 if we know that it will be a nop. */
8023 if (annul
|| ! final_sequence
)
8037 /* Emit a library call comparison between floating point X and Y.
8038 COMPARISON is the operator to compare with (EQ, NE, GT, etc).
8039 Return the new operator to be used in the comparison sequence.
8041 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
8042 values as arguments instead of the TFmode registers themselves,
8043 that's why we cannot call emit_float_lib_cmp. */
8046 sparc_emit_float_lib_cmp (rtx x
, rtx y
, enum rtx_code comparison
)
8049 rtx slot0
, slot1
, result
, tem
, tem2
, libfunc
;
8051 enum rtx_code new_comparison
;
8056 qpfunc
= (TARGET_ARCH64
? "_Qp_feq" : "_Q_feq");
8060 qpfunc
= (TARGET_ARCH64
? "_Qp_fne" : "_Q_fne");
8064 qpfunc
= (TARGET_ARCH64
? "_Qp_fgt" : "_Q_fgt");
8068 qpfunc
= (TARGET_ARCH64
? "_Qp_fge" : "_Q_fge");
8072 qpfunc
= (TARGET_ARCH64
? "_Qp_flt" : "_Q_flt");
8076 qpfunc
= (TARGET_ARCH64
? "_Qp_fle" : "_Q_fle");
8087 qpfunc
= (TARGET_ARCH64
? "_Qp_cmp" : "_Q_cmp");
8098 tree expr
= MEM_EXPR (x
);
8100 mark_addressable (expr
);
8105 slot0
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
));
8106 emit_move_insn (slot0
, x
);
8111 tree expr
= MEM_EXPR (y
);
8113 mark_addressable (expr
);
8118 slot1
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
));
8119 emit_move_insn (slot1
, y
);
8122 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
8123 emit_library_call (libfunc
, LCT_NORMAL
,
8125 XEXP (slot0
, 0), Pmode
,
8126 XEXP (slot1
, 0), Pmode
);
8131 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
8132 emit_library_call (libfunc
, LCT_NORMAL
,
8134 x
, TFmode
, y
, TFmode
);
8139 /* Immediately move the result of the libcall into a pseudo
8140 register so reload doesn't clobber the value if it needs
8141 the return register for a spill reg. */
8142 result
= gen_reg_rtx (mode
);
8143 emit_move_insn (result
, hard_libcall_value (mode
, libfunc
));
8148 return gen_rtx_NE (VOIDmode
, result
, const0_rtx
);
8151 new_comparison
= (comparison
== UNORDERED
? EQ
: NE
);
8152 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, GEN_INT(3));
8155 new_comparison
= (comparison
== UNGT
? GT
: NE
);
8156 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, const1_rtx
);
8158 return gen_rtx_NE (VOIDmode
, result
, const2_rtx
);
8160 tem
= gen_reg_rtx (mode
);
8162 emit_insn (gen_andsi3 (tem
, result
, const1_rtx
));
8164 emit_insn (gen_anddi3 (tem
, result
, const1_rtx
));
8165 return gen_rtx_NE (VOIDmode
, tem
, const0_rtx
);
8168 tem
= gen_reg_rtx (mode
);
8170 emit_insn (gen_addsi3 (tem
, result
, const1_rtx
));
8172 emit_insn (gen_adddi3 (tem
, result
, const1_rtx
));
8173 tem2
= gen_reg_rtx (mode
);
8175 emit_insn (gen_andsi3 (tem2
, tem
, const2_rtx
));
8177 emit_insn (gen_anddi3 (tem2
, tem
, const2_rtx
));
8178 new_comparison
= (comparison
== UNEQ
? EQ
: NE
);
8179 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, tem2
, const0_rtx
);
8185 /* Generate an unsigned DImode to FP conversion. This is the same code
8186 optabs would emit if we didn't have TFmode patterns. */
8189 sparc_emit_floatunsdi (rtx
*operands
, machine_mode mode
)
8191 rtx i0
, i1
, f0
, in
, out
;
8194 in
= force_reg (DImode
, operands
[1]);
8195 rtx_code_label
*neglab
= gen_label_rtx ();
8196 rtx_code_label
*donelab
= gen_label_rtx ();
8197 i0
= gen_reg_rtx (DImode
);
8198 i1
= gen_reg_rtx (DImode
);
8199 f0
= gen_reg_rtx (mode
);
8201 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
8203 emit_insn (gen_rtx_SET (out
, gen_rtx_FLOAT (mode
, in
)));
8204 emit_jump_insn (gen_jump (donelab
));
8207 emit_label (neglab
);
8209 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
8210 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
8211 emit_insn (gen_iordi3 (i0
, i0
, i1
));
8212 emit_insn (gen_rtx_SET (f0
, gen_rtx_FLOAT (mode
, i0
)));
8213 emit_insn (gen_rtx_SET (out
, gen_rtx_PLUS (mode
, f0
, f0
)));
8215 emit_label (donelab
);
8218 /* Generate an FP to unsigned DImode conversion. This is the same code
8219 optabs would emit if we didn't have TFmode patterns. */
8222 sparc_emit_fixunsdi (rtx
*operands
, machine_mode mode
)
8224 rtx i0
, i1
, f0
, in
, out
, limit
;
8227 in
= force_reg (mode
, operands
[1]);
8228 rtx_code_label
*neglab
= gen_label_rtx ();
8229 rtx_code_label
*donelab
= gen_label_rtx ();
8230 i0
= gen_reg_rtx (DImode
);
8231 i1
= gen_reg_rtx (DImode
);
8232 limit
= gen_reg_rtx (mode
);
8233 f0
= gen_reg_rtx (mode
);
8235 emit_move_insn (limit
,
8236 const_double_from_real_value (
8237 REAL_VALUE_ATOF ("9223372036854775808.0", mode
), mode
));
8238 emit_cmp_and_jump_insns (in
, limit
, GE
, NULL_RTX
, mode
, 0, neglab
);
8240 emit_insn (gen_rtx_SET (out
,
8241 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, in
))));
8242 emit_jump_insn (gen_jump (donelab
));
8245 emit_label (neglab
);
8247 emit_insn (gen_rtx_SET (f0
, gen_rtx_MINUS (mode
, in
, limit
)));
8248 emit_insn (gen_rtx_SET (i0
,
8249 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, f0
))));
8250 emit_insn (gen_movdi (i1
, const1_rtx
));
8251 emit_insn (gen_ashldi3 (i1
, i1
, GEN_INT (63)));
8252 emit_insn (gen_xordi3 (out
, i0
, i1
));
8254 emit_label (donelab
);
8257 /* Return the string to output a compare and branch instruction to DEST.
8258 DEST is the destination insn (i.e. the label), INSN is the source,
8259 and OP is the conditional expression. */
8262 output_cbcond (rtx op
, rtx dest
, rtx_insn
*insn
)
8264 machine_mode mode
= GET_MODE (XEXP (op
, 0));
8265 enum rtx_code code
= GET_CODE (op
);
8266 const char *cond_str
, *tmpl
;
8267 int far
, emit_nop
, len
;
8268 static char string
[64];
8271 /* Compare and Branch is limited to +-2KB. If it is too far away,
8283 len
= get_attr_length (insn
);
8286 emit_nop
= len
== 2;
8289 code
= reverse_condition (code
);
8291 size_char
= ((mode
== SImode
) ? 'w' : 'x');
8341 int veryfar
= 1, delta
;
8343 if (INSN_ADDRESSES_SET_P ())
8345 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
8346 - INSN_ADDRESSES (INSN_UID (insn
)));
8347 /* Leave some instructions for "slop". */
8348 if (delta
>= -260000 && delta
< 260000)
8353 tmpl
= "c%cb%s\t%%1, %%2, .+16\n\tnop\n\tb\t%%3\n\tnop";
8355 tmpl
= "c%cb%s\t%%1, %%2, .+16\n\tnop\n\tba,pt\t%%%%xcc, %%3\n\tnop";
8360 tmpl
= "c%cb%s\t%%1, %%2, %%3\n\tnop";
8362 tmpl
= "c%cb%s\t%%1, %%2, %%3";
8365 snprintf (string
, sizeof(string
), tmpl
, size_char
, cond_str
);
8370 /* Return the string to output a conditional branch to LABEL, testing
8371 register REG. LABEL is the operand number of the label; REG is the
8372 operand number of the reg. OP is the conditional expression. The mode
8373 of REG says what kind of comparison we made.
8375 DEST is the destination insn (i.e. the label), INSN is the source.
8377 REVERSED is nonzero if we should reverse the sense of the comparison.
8379 ANNUL is nonzero if we should generate an annulling branch. */
8382 output_v9branch (rtx op
, rtx dest
, int reg
, int label
, int reversed
,
8383 int annul
, rtx_insn
*insn
)
8385 static char string
[64];
8386 enum rtx_code code
= GET_CODE (op
);
8387 machine_mode mode
= GET_MODE (XEXP (op
, 0));
8392 /* branch on register are limited to +-128KB. If it is too far away,
8405 brgez,a,pn %o1, .LC29
8411 ba,pt %xcc, .LC29 */
8413 far
= get_attr_length (insn
) >= 3;
8415 /* If not floating-point or if EQ or NE, we can just reverse the code. */
8417 code
= reverse_condition (code
);
8419 /* Only 64 bit versions of these instructions exist. */
8420 gcc_assert (mode
== DImode
);
8422 /* Start by writing the branch condition. */
8427 strcpy (string
, "brnz");
8431 strcpy (string
, "brz");
8435 strcpy (string
, "brgez");
8439 strcpy (string
, "brlz");
8443 strcpy (string
, "brlez");
8447 strcpy (string
, "brgz");
8454 p
= strchr (string
, '\0');
8456 /* Now add the annulling, reg, label, and nop. */
8463 if (insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
8466 ((profile_probability::from_reg_br_prob_note (XINT (note
, 0))
8467 >= profile_probability::even ()) ^ far
)
8472 *p
= p
< string
+ 8 ? '\t' : ' ';
8480 int veryfar
= 1, delta
;
8482 if (INSN_ADDRESSES_SET_P ())
8484 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
8485 - INSN_ADDRESSES (INSN_UID (insn
)));
8486 /* Leave some instructions for "slop". */
8487 if (delta
>= -260000 && delta
< 260000)
8491 strcpy (p
, ".+12\n\t nop\n\t");
8492 /* Skip the next insn if requested or
8493 if we know that it will be a nop. */
8494 if (annul
|| ! final_sequence
)
8504 strcpy (p
, "ba,pt\t%%xcc, ");
8518 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
8519 Such instructions cannot be used in the delay slot of return insn on v9.
8520 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
8524 epilogue_renumber (register rtx
*where
, int test
)
8526 register const char *fmt
;
8528 register enum rtx_code code
;
8533 code
= GET_CODE (*where
);
8538 if (REGNO (*where
) >= 8 && REGNO (*where
) < 24) /* oX or lX */
8540 if (! test
&& REGNO (*where
) >= 24 && REGNO (*where
) < 32)
8541 *where
= gen_rtx_REG (GET_MODE (*where
), OUTGOING_REGNO (REGNO(*where
)));
8547 case CONST_WIDE_INT
:
8551 /* Do not replace the frame pointer with the stack pointer because
8552 it can cause the delayed instruction to load below the stack.
8553 This occurs when instructions like:
8555 (set (reg/i:SI 24 %i0)
8556 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
8557 (const_int -20 [0xffffffec])) 0))
8559 are in the return delayed slot. */
8561 if (GET_CODE (XEXP (*where
, 0)) == REG
8562 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
8563 && (GET_CODE (XEXP (*where
, 1)) != CONST_INT
8564 || INTVAL (XEXP (*where
, 1)) < SPARC_STACK_BIAS
))
8569 if (SPARC_STACK_BIAS
8570 && GET_CODE (XEXP (*where
, 0)) == REG
8571 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
)
8579 fmt
= GET_RTX_FORMAT (code
);
8581 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8586 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
8587 if (epilogue_renumber (&(XVECEXP (*where
, i
, j
)), test
))
8590 else if (fmt
[i
] == 'e'
8591 && epilogue_renumber (&(XEXP (*where
, i
)), test
))
8597 /* Leaf functions and non-leaf functions have different needs. */
8600 reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
8603 reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
8605 static const int *const reg_alloc_orders
[] = {
8606 reg_leaf_alloc_order
,
8607 reg_nonleaf_alloc_order
};
8610 order_regs_for_local_alloc (void)
8612 static int last_order_nonleaf
= 1;
8614 if (df_regs_ever_live_p (15) != last_order_nonleaf
)
8616 last_order_nonleaf
= !last_order_nonleaf
;
8617 memcpy ((char *) reg_alloc_order
,
8618 (const char *) reg_alloc_orders
[last_order_nonleaf
],
8619 FIRST_PSEUDO_REGISTER
* sizeof (int));
8623 /* Return 1 if REG and MEM are legitimate enough to allow the various
8624 MEM<-->REG splits to be run. */
8627 sparc_split_reg_mem_legitimate (rtx reg
, rtx mem
)
8629 /* Punt if we are here by mistake. */
8630 gcc_assert (reload_completed
);
8632 /* We must have an offsettable memory reference. */
8633 if (!offsettable_memref_p (mem
))
8636 /* If we have legitimate args for ldd/std, we do not want
8637 the split to happen. */
8638 if ((REGNO (reg
) % 2) == 0 && mem_min_alignment (mem
, 8))
8645 /* Split a REG <-- MEM move into a pair of moves in MODE. */
8648 sparc_split_reg_mem (rtx dest
, rtx src
, machine_mode mode
)
8650 rtx high_part
= gen_highpart (mode
, dest
);
8651 rtx low_part
= gen_lowpart (mode
, dest
);
8652 rtx word0
= adjust_address (src
, mode
, 0);
8653 rtx word1
= adjust_address (src
, mode
, 4);
8655 if (reg_overlap_mentioned_p (high_part
, word1
))
8657 emit_move_insn_1 (low_part
, word1
);
8658 emit_move_insn_1 (high_part
, word0
);
8662 emit_move_insn_1 (high_part
, word0
);
8663 emit_move_insn_1 (low_part
, word1
);
8667 /* Split a MEM <-- REG move into a pair of moves in MODE. */
8670 sparc_split_mem_reg (rtx dest
, rtx src
, machine_mode mode
)
8672 rtx word0
= adjust_address (dest
, mode
, 0);
8673 rtx word1
= adjust_address (dest
, mode
, 4);
8674 rtx high_part
= gen_highpart (mode
, src
);
8675 rtx low_part
= gen_lowpart (mode
, src
);
8677 emit_move_insn_1 (word0
, high_part
);
8678 emit_move_insn_1 (word1
, low_part
);
8681 /* Like sparc_split_reg_mem_legitimate but for REG <--> REG moves. */
8684 sparc_split_reg_reg_legitimate (rtx reg1
, rtx reg2
)
8686 /* Punt if we are here by mistake. */
8687 gcc_assert (reload_completed
);
8689 if (GET_CODE (reg1
) == SUBREG
)
8690 reg1
= SUBREG_REG (reg1
);
8691 if (GET_CODE (reg1
) != REG
)
8693 const int regno1
= REGNO (reg1
);
8695 if (GET_CODE (reg2
) == SUBREG
)
8696 reg2
= SUBREG_REG (reg2
);
8697 if (GET_CODE (reg2
) != REG
)
8699 const int regno2
= REGNO (reg2
);
8701 if (SPARC_INT_REG_P (regno1
) && SPARC_INT_REG_P (regno2
))
8706 if ((SPARC_INT_REG_P (regno1
) && SPARC_FP_REG_P (regno2
))
8707 || (SPARC_FP_REG_P (regno1
) && SPARC_INT_REG_P (regno2
)))
8714 /* Split a REG <--> REG move into a pair of moves in MODE. */
8717 sparc_split_reg_reg (rtx dest
, rtx src
, machine_mode mode
)
8719 rtx dest1
= gen_highpart (mode
, dest
);
8720 rtx dest2
= gen_lowpart (mode
, dest
);
8721 rtx src1
= gen_highpart (mode
, src
);
8722 rtx src2
= gen_lowpart (mode
, src
);
8724 /* Now emit using the real source and destination we found, swapping
8725 the order if we detect overlap. */
8726 if (reg_overlap_mentioned_p (dest1
, src2
))
8728 emit_move_insn_1 (dest2
, src2
);
8729 emit_move_insn_1 (dest1
, src1
);
8733 emit_move_insn_1 (dest1
, src1
);
8734 emit_move_insn_1 (dest2
, src2
);
8738 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
8739 This makes them candidates for using ldd and std insns.
8741 Note reg1 and reg2 *must* be hard registers. */
8744 registers_ok_for_ldd_peep (rtx reg1
, rtx reg2
)
8746 /* We might have been passed a SUBREG. */
8747 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
8750 if (REGNO (reg1
) % 2 != 0)
8753 /* Integer ldd is deprecated in SPARC V9 */
8754 if (TARGET_V9
&& SPARC_INT_REG_P (REGNO (reg1
)))
8757 return (REGNO (reg1
) == REGNO (reg2
) - 1);
8760 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
8763 This can only happen when addr1 and addr2, the addresses in mem1
8764 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
8765 addr1 must also be aligned on a 64-bit boundary.
8767 Also iff dependent_reg_rtx is not null it should not be used to
8768 compute the address for mem1, i.e. we cannot optimize a sequence
8780 But, note that the transformation from:
8785 is perfectly fine. Thus, the peephole2 patterns always pass us
8786 the destination register of the first load, never the second one.
8788 For stores we don't have a similar problem, so dependent_reg_rtx is
8792 mems_ok_for_ldd_peep (rtx mem1
, rtx mem2
, rtx dependent_reg_rtx
)
8796 HOST_WIDE_INT offset1
;
8798 /* The mems cannot be volatile. */
8799 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
8802 /* MEM1 should be aligned on a 64-bit boundary. */
8803 if (MEM_ALIGN (mem1
) < 64)
8806 addr1
= XEXP (mem1
, 0);
8807 addr2
= XEXP (mem2
, 0);
8809 /* Extract a register number and offset (if used) from the first addr. */
8810 if (GET_CODE (addr1
) == PLUS
)
8812 /* If not a REG, return zero. */
8813 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
8817 reg1
= REGNO (XEXP (addr1
, 0));
8818 /* The offset must be constant! */
8819 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
8821 offset1
= INTVAL (XEXP (addr1
, 1));
8824 else if (GET_CODE (addr1
) != REG
)
8828 reg1
= REGNO (addr1
);
8829 /* This was a simple (mem (reg)) expression. Offset is 0. */
8833 /* Make sure the second address is a (mem (plus (reg) (const_int). */
8834 if (GET_CODE (addr2
) != PLUS
)
8837 if (GET_CODE (XEXP (addr2
, 0)) != REG
8838 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
8841 if (reg1
!= REGNO (XEXP (addr2
, 0)))
8844 if (dependent_reg_rtx
!= NULL_RTX
&& reg1
== REGNO (dependent_reg_rtx
))
8847 /* The first offset must be evenly divisible by 8 to ensure the
8848 address is 64 bit aligned. */
8849 if (offset1
% 8 != 0)
8852 /* The offset for the second addr must be 4 more than the first addr. */
8853 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
8856 /* All the tests passed. addr1 and addr2 are valid for ldd and std
8861 /* Return the widened memory access made of MEM1 and MEM2 in MODE. */
8864 widen_mem_for_ldd_peep (rtx mem1
, rtx mem2
, machine_mode mode
)
8866 rtx x
= widen_memory_access (mem1
, mode
, 0);
8867 MEM_NOTRAP_P (x
) = MEM_NOTRAP_P (mem1
) && MEM_NOTRAP_P (mem2
);
8871 /* Return 1 if reg is a pseudo, or is the first register in
8872 a hard register pair. This makes it suitable for use in
8873 ldd and std insns. */
8876 register_ok_for_ldd (rtx reg
)
8878 /* We might have been passed a SUBREG. */
8882 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
8883 return (REGNO (reg
) % 2 == 0);
8888 /* Return 1 if OP, a MEM, has an address which is known to be
8889 aligned to an 8-byte boundary. */
8892 memory_ok_for_ldd (rtx op
)
8894 /* In 64-bit mode, we assume that the address is word-aligned. */
8895 if (TARGET_ARCH32
&& !mem_min_alignment (op
, 8))
8898 if (! can_create_pseudo_p ()
8899 && !strict_memory_address_p (Pmode
, XEXP (op
, 0)))
8905 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8908 sparc_print_operand_punct_valid_p (unsigned char code
)
8921 /* Implement TARGET_PRINT_OPERAND.
8922 Print operand X (an rtx) in assembler syntax to file FILE.
8923 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
8924 For `%' followed by punctuation, CODE is the punctuation and X is null. */
8927 sparc_print_operand (FILE *file
, rtx x
, int code
)
8934 /* Output an insn in a delay slot. */
8936 sparc_indent_opcode
= 1;
8938 fputs ("\n\t nop", file
);
8941 /* Output an annul flag if there's nothing for the delay slot and we
8942 are optimizing. This is always used with '(' below.
8943 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
8944 this is a dbx bug. So, we only do this when optimizing.
8945 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
8946 Always emit a nop in case the next instruction is a branch. */
8947 if (! final_sequence
&& (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
8951 /* Output a 'nop' if there's nothing for the delay slot and we are
8952 not optimizing. This is always used with '*' above. */
8953 if (! final_sequence
&& ! (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
8954 fputs ("\n\t nop", file
);
8955 else if (final_sequence
)
8956 sparc_indent_opcode
= 1;
8959 /* Output the right displacement from the saved PC on function return.
8960 The caller may have placed an "unimp" insn immediately after the call
8961 so we have to account for it. This insn is used in the 32-bit ABI
8962 when calling a function that returns a non zero-sized structure. The
8963 64-bit ABI doesn't have it. Be careful to have this test be the same
8964 as that for the call. The exception is when sparc_std_struct_return
8965 is enabled, the psABI is followed exactly and the adjustment is made
8966 by the code in sparc_struct_value_rtx. The call emitted is the same
8967 when sparc_std_struct_return is enabled. */
8969 && cfun
->returns_struct
8970 && !sparc_std_struct_return
8971 && DECL_SIZE (DECL_RESULT (current_function_decl
))
8972 && TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl
)))
8974 && !integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl
))))
8980 /* Output the Embedded Medium/Anywhere code model base register. */
8981 fputs (EMBMEDANY_BASE_REG
, file
);
8984 /* Print some local dynamic TLS name. */
8985 if (const char *name
= get_some_local_dynamic_name ())
8986 assemble_name (file
, name
);
8988 output_operand_lossage ("'%%&' used without any "
8989 "local dynamic TLS references");
8993 /* Adjust the operand to take into account a RESTORE operation. */
8994 if (GET_CODE (x
) == CONST_INT
)
8996 else if (GET_CODE (x
) != REG
)
8997 output_operand_lossage ("invalid %%Y operand");
8998 else if (REGNO (x
) < 8)
8999 fputs (reg_names
[REGNO (x
)], file
);
9000 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
9001 fputs (reg_names
[REGNO (x
)-16], file
);
9003 output_operand_lossage ("invalid %%Y operand");
9006 /* Print out the low order register name of a register pair. */
9007 if (WORDS_BIG_ENDIAN
)
9008 fputs (reg_names
[REGNO (x
)+1], file
);
9010 fputs (reg_names
[REGNO (x
)], file
);
9013 /* Print out the high order register name of a register pair. */
9014 if (WORDS_BIG_ENDIAN
)
9015 fputs (reg_names
[REGNO (x
)], file
);
9017 fputs (reg_names
[REGNO (x
)+1], file
);
9020 /* Print out the second register name of a register pair or quad.
9021 I.e., R (%o0) => %o1. */
9022 fputs (reg_names
[REGNO (x
)+1], file
);
9025 /* Print out the third register name of a register quad.
9026 I.e., S (%o0) => %o2. */
9027 fputs (reg_names
[REGNO (x
)+2], file
);
9030 /* Print out the fourth register name of a register quad.
9031 I.e., T (%o0) => %o3. */
9032 fputs (reg_names
[REGNO (x
)+3], file
);
9035 /* Print a condition code register. */
9036 if (REGNO (x
) == SPARC_ICC_REG
)
9038 switch (GET_MODE (x
))
9058 /* %fccN register */
9059 fputs (reg_names
[REGNO (x
)], file
);
9062 /* Print the operand's address only. */
9063 output_address (GET_MODE (x
), XEXP (x
, 0));
9066 /* In this case we need a register. Use %g0 if the
9067 operand is const0_rtx. */
9069 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
9071 fputs ("%g0", file
);
9078 switch (GET_CODE (x
))
9090 output_operand_lossage ("invalid %%A operand");
9098 switch (GET_CODE (x
))
9110 output_operand_lossage ("invalid %%B operand");
9117 /* This is used by the conditional move instructions. */
9120 machine_mode mode
= GET_MODE (XEXP (x
, 0));
9121 switch (GET_CODE (x
))
9124 if (mode
== CCVmode
|| mode
== CCXVmode
)
9130 if (mode
== CCVmode
|| mode
== CCXVmode
)
9136 if (mode
== CCNZmode
|| mode
== CCXNZmode
)
9148 if (mode
== CCNZmode
|| mode
== CCXNZmode
)
9190 output_operand_lossage ("invalid %%C operand");
9198 /* This are used by the movr instruction pattern. */
9201 switch (GET_CODE (x
))
9222 output_operand_lossage ("invalid %%D operand");
9232 /* Print a sign-extended character. */
9233 int i
= trunc_int_for_mode (INTVAL (x
), QImode
);
9234 fprintf (file
, "%d", i
);
9239 /* Operand must be a MEM; write its address. */
9240 if (GET_CODE (x
) != MEM
)
9241 output_operand_lossage ("invalid %%f operand");
9242 output_address (GET_MODE (x
), XEXP (x
, 0));
9247 /* Print a sign-extended 32-bit value. */
9249 if (GET_CODE(x
) == CONST_INT
)
9253 output_operand_lossage ("invalid %%s operand");
9256 i
= trunc_int_for_mode (i
, SImode
);
9257 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, i
);
9262 /* Do nothing special. */
9266 /* Undocumented flag. */
9267 output_operand_lossage ("invalid operand output code");
9270 if (GET_CODE (x
) == REG
)
9271 fputs (reg_names
[REGNO (x
)], file
);
9272 else if (GET_CODE (x
) == MEM
)
9275 /* Poor Sun assembler doesn't understand absolute addressing. */
9276 if (CONSTANT_P (XEXP (x
, 0)))
9277 fputs ("%g0+", file
);
9278 output_address (GET_MODE (x
), XEXP (x
, 0));
9281 else if (GET_CODE (x
) == HIGH
)
9283 fputs ("%hi(", file
);
9284 output_addr_const (file
, XEXP (x
, 0));
9287 else if (GET_CODE (x
) == LO_SUM
)
9289 sparc_print_operand (file
, XEXP (x
, 0), 0);
9290 if (TARGET_CM_MEDMID
)
9291 fputs ("+%l44(", file
);
9293 fputs ("+%lo(", file
);
9294 output_addr_const (file
, XEXP (x
, 1));
9297 else if (GET_CODE (x
) == CONST_DOUBLE
)
9298 output_operand_lossage ("floating-point constant not a valid immediate operand");
9300 output_addr_const (file
, x
);
9303 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
9306 sparc_print_operand_address (FILE *file
, machine_mode
/*mode*/, rtx x
)
9308 register rtx base
, index
= 0;
9310 register rtx addr
= x
;
9313 fputs (reg_names
[REGNO (addr
)], file
);
9314 else if (GET_CODE (addr
) == PLUS
)
9316 if (CONST_INT_P (XEXP (addr
, 0)))
9317 offset
= INTVAL (XEXP (addr
, 0)), base
= XEXP (addr
, 1);
9318 else if (CONST_INT_P (XEXP (addr
, 1)))
9319 offset
= INTVAL (XEXP (addr
, 1)), base
= XEXP (addr
, 0);
9321 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
9322 if (GET_CODE (base
) == LO_SUM
)
9324 gcc_assert (USE_AS_OFFSETABLE_LO10
9326 && ! TARGET_CM_MEDMID
);
9327 output_operand (XEXP (base
, 0), 0);
9328 fputs ("+%lo(", file
);
9329 output_address (VOIDmode
, XEXP (base
, 1));
9330 fprintf (file
, ")+%d", offset
);
9334 fputs (reg_names
[REGNO (base
)], file
);
9336 fprintf (file
, "%+d", offset
);
9337 else if (REG_P (index
))
9338 fprintf (file
, "+%s", reg_names
[REGNO (index
)]);
9339 else if (GET_CODE (index
) == SYMBOL_REF
9340 || GET_CODE (index
) == LABEL_REF
9341 || GET_CODE (index
) == CONST
)
9342 fputc ('+', file
), output_addr_const (file
, index
);
9343 else gcc_unreachable ();
9346 else if (GET_CODE (addr
) == MINUS
9347 && GET_CODE (XEXP (addr
, 1)) == LABEL_REF
)
9349 output_addr_const (file
, XEXP (addr
, 0));
9351 output_addr_const (file
, XEXP (addr
, 1));
9352 fputs ("-.)", file
);
9354 else if (GET_CODE (addr
) == LO_SUM
)
9356 output_operand (XEXP (addr
, 0), 0);
9357 if (TARGET_CM_MEDMID
)
9358 fputs ("+%l44(", file
);
9360 fputs ("+%lo(", file
);
9361 output_address (VOIDmode
, XEXP (addr
, 1));
9365 && GET_CODE (addr
) == CONST
9366 && GET_CODE (XEXP (addr
, 0)) == MINUS
9367 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST
9368 && GET_CODE (XEXP (XEXP (XEXP (addr
, 0), 1), 0)) == MINUS
9369 && XEXP (XEXP (XEXP (XEXP (addr
, 0), 1), 0), 1) == pc_rtx
)
9371 addr
= XEXP (addr
, 0);
9372 output_addr_const (file
, XEXP (addr
, 0));
9373 /* Group the args of the second CONST in parenthesis. */
9375 /* Skip past the second CONST--it does nothing for us. */
9376 output_addr_const (file
, XEXP (XEXP (addr
, 1), 0));
9377 /* Close the parenthesis. */
9382 output_addr_const (file
, addr
);
9386 /* Target hook for assembling integer objects. The sparc version has
9387 special handling for aligned DI-mode objects. */
9390 sparc_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
9392 /* ??? We only output .xword's for symbols and only then in environments
9393 where the assembler can handle them. */
9394 if (aligned_p
&& size
== 8 && GET_CODE (x
) != CONST_INT
)
9398 assemble_integer_with_op ("\t.xword\t", x
);
9403 assemble_aligned_integer (4, const0_rtx
);
9404 assemble_aligned_integer (4, x
);
9408 return default_assemble_integer (x
, size
, aligned_p
);
9411 /* Return the value of a code used in the .proc pseudo-op that says
9412 what kind of result this function returns. For non-C types, we pick
9413 the closest C type. */
9415 #ifndef SHORT_TYPE_SIZE
9416 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
9419 #ifndef INT_TYPE_SIZE
9420 #define INT_TYPE_SIZE BITS_PER_WORD
9423 #ifndef LONG_TYPE_SIZE
9424 #define LONG_TYPE_SIZE BITS_PER_WORD
9427 #ifndef LONG_LONG_TYPE_SIZE
9428 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
9431 #ifndef FLOAT_TYPE_SIZE
9432 #define FLOAT_TYPE_SIZE BITS_PER_WORD
9435 #ifndef DOUBLE_TYPE_SIZE
9436 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
9439 #ifndef LONG_DOUBLE_TYPE_SIZE
9440 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
9444 sparc_type_code (register tree type
)
9446 register unsigned long qualifiers
= 0;
9447 register unsigned shift
;
9449 /* Only the first 30 bits of the qualifier are valid. We must refrain from
9450 setting more, since some assemblers will give an error for this. Also,
9451 we must be careful to avoid shifts of 32 bits or more to avoid getting
9452 unpredictable results. */
9454 for (shift
= 6; shift
< 30; shift
+= 2, type
= TREE_TYPE (type
))
9456 switch (TREE_CODE (type
))
9462 qualifiers
|= (3 << shift
);
9467 qualifiers
|= (2 << shift
);
9471 case REFERENCE_TYPE
:
9473 qualifiers
|= (1 << shift
);
9477 return (qualifiers
| 8);
9480 case QUAL_UNION_TYPE
:
9481 return (qualifiers
| 9);
9484 return (qualifiers
| 10);
9487 return (qualifiers
| 16);
9490 /* If this is a range type, consider it to be the underlying
9492 if (TREE_TYPE (type
) != 0)
9495 /* Carefully distinguish all the standard types of C,
9496 without messing up if the language is not C. We do this by
9497 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
9498 look at both the names and the above fields, but that's redundant.
9499 Any type whose size is between two C types will be considered
9500 to be the wider of the two types. Also, we do not have a
9501 special code to use for "long long", so anything wider than
9502 long is treated the same. Note that we can't distinguish
9503 between "int" and "long" in this code if they are the same
9504 size, but that's fine, since neither can the assembler. */
9506 if (TYPE_PRECISION (type
) <= CHAR_TYPE_SIZE
)
9507 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 12 : 2));
9509 else if (TYPE_PRECISION (type
) <= SHORT_TYPE_SIZE
)
9510 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 13 : 3));
9512 else if (TYPE_PRECISION (type
) <= INT_TYPE_SIZE
)
9513 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 14 : 4));
9516 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 15 : 5));
9519 /* If this is a range type, consider it to be the underlying
9521 if (TREE_TYPE (type
) != 0)
9524 /* Carefully distinguish all the standard types of C,
9525 without messing up if the language is not C. */
9527 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
9528 return (qualifiers
| 6);
9531 return (qualifiers
| 7);
9533 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
9534 /* ??? We need to distinguish between double and float complex types,
9535 but I don't know how yet because I can't reach this code from
9536 existing front-ends. */
9537 return (qualifiers
| 7); /* Who knows? */
9540 case BOOLEAN_TYPE
: /* Boolean truth value type. */
9546 gcc_unreachable (); /* Not a type! */
9553 /* Nested function support. */
9555 /* Emit RTL insns to initialize the variable parts of a trampoline.
9556 FNADDR is an RTX for the address of the function's pure code.
9557 CXT is an RTX for the static chain value for the function.
9559 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
9560 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
9561 (to store insns). This is a bit excessive. Perhaps a different
9562 mechanism would be better here.
9564 Emit enough FLUSH insns to synchronize the data and instruction caches. */
9567 sparc32_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
9569 /* SPARC 32-bit trampoline:
9572 sethi %hi(static), %g2
9574 or %g2, %lo(static), %g2
9576 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
9577 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
9581 (adjust_address (m_tramp
, SImode
, 0),
9582 expand_binop (SImode
, ior_optab
,
9583 expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
, 10, 0, 1),
9584 GEN_INT (trunc_int_for_mode (0x03000000, SImode
)),
9585 NULL_RTX
, 1, OPTAB_DIRECT
));
9588 (adjust_address (m_tramp
, SImode
, 4),
9589 expand_binop (SImode
, ior_optab
,
9590 expand_shift (RSHIFT_EXPR
, SImode
, cxt
, 10, 0, 1),
9591 GEN_INT (trunc_int_for_mode (0x05000000, SImode
)),
9592 NULL_RTX
, 1, OPTAB_DIRECT
));
9595 (adjust_address (m_tramp
, SImode
, 8),
9596 expand_binop (SImode
, ior_optab
,
9597 expand_and (SImode
, fnaddr
, GEN_INT (0x3ff), NULL_RTX
),
9598 GEN_INT (trunc_int_for_mode (0x81c06000, SImode
)),
9599 NULL_RTX
, 1, OPTAB_DIRECT
));
9602 (adjust_address (m_tramp
, SImode
, 12),
9603 expand_binop (SImode
, ior_optab
,
9604 expand_and (SImode
, cxt
, GEN_INT (0x3ff), NULL_RTX
),
9605 GEN_INT (trunc_int_for_mode (0x8410a000, SImode
)),
9606 NULL_RTX
, 1, OPTAB_DIRECT
));
9608 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
9609 aligned on a 16 byte boundary so one flush clears it all. */
9610 emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp
, SImode
, 0))));
9611 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
9612 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
9613 && sparc_cpu
!= PROCESSOR_NIAGARA
9614 && sparc_cpu
!= PROCESSOR_NIAGARA2
9615 && sparc_cpu
!= PROCESSOR_NIAGARA3
9616 && sparc_cpu
!= PROCESSOR_NIAGARA4
9617 && sparc_cpu
!= PROCESSOR_NIAGARA7
9618 && sparc_cpu
!= PROCESSOR_M8
)
9619 emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp
, SImode
, 8))));
9621 /* Call __enable_execute_stack after writing onto the stack to make sure
9622 the stack address is accessible. */
9623 #ifdef HAVE_ENABLE_EXECUTE_STACK
9624 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
9625 LCT_NORMAL
, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
9630 /* The 64-bit version is simpler because it makes more sense to load the
9631 values as "immediate" data out of the trampoline. It's also easier since
9632 we can read the PC without clobbering a register. */
9635 sparc64_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
9637 /* SPARC 64-bit trampoline:
9646 emit_move_insn (adjust_address (m_tramp
, SImode
, 0),
9647 GEN_INT (trunc_int_for_mode (0x83414000, SImode
)));
9648 emit_move_insn (adjust_address (m_tramp
, SImode
, 4),
9649 GEN_INT (trunc_int_for_mode (0xca586018, SImode
)));
9650 emit_move_insn (adjust_address (m_tramp
, SImode
, 8),
9651 GEN_INT (trunc_int_for_mode (0x81c14000, SImode
)));
9652 emit_move_insn (adjust_address (m_tramp
, SImode
, 12),
9653 GEN_INT (trunc_int_for_mode (0xca586010, SImode
)));
9654 emit_move_insn (adjust_address (m_tramp
, DImode
, 16), cxt
);
9655 emit_move_insn (adjust_address (m_tramp
, DImode
, 24), fnaddr
);
9656 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 0))));
9658 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
9659 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
9660 && sparc_cpu
!= PROCESSOR_NIAGARA
9661 && sparc_cpu
!= PROCESSOR_NIAGARA2
9662 && sparc_cpu
!= PROCESSOR_NIAGARA3
9663 && sparc_cpu
!= PROCESSOR_NIAGARA4
9664 && sparc_cpu
!= PROCESSOR_NIAGARA7
9665 && sparc_cpu
!= PROCESSOR_M8
)
9666 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 8))));
9668 /* Call __enable_execute_stack after writing onto the stack to make sure
9669 the stack address is accessible. */
9670 #ifdef HAVE_ENABLE_EXECUTE_STACK
9671 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
9672 LCT_NORMAL
, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
9676 /* Worker for TARGET_TRAMPOLINE_INIT. */
9679 sparc_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
9681 rtx fnaddr
= force_reg (Pmode
, XEXP (DECL_RTL (fndecl
), 0));
9682 cxt
= force_reg (Pmode
, cxt
);
9684 sparc64_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
9686 sparc32_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
9689 /* Adjust the cost of a scheduling dependency. Return the new cost of
9690 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
9693 supersparc_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep_insn
,
9696 enum attr_type insn_type
;
9698 if (recog_memoized (insn
) < 0)
9701 insn_type
= get_attr_type (insn
);
9705 /* Data dependency; DEP_INSN writes a register that INSN reads some
9708 /* if a load, then the dependence must be on the memory address;
9709 add an extra "cycle". Note that the cost could be two cycles
9710 if the reg was written late in an instruction group; we ca not tell
9712 if (insn_type
== TYPE_LOAD
|| insn_type
== TYPE_FPLOAD
)
9715 /* Get the delay only if the address of the store is the dependence. */
9716 if (insn_type
== TYPE_STORE
|| insn_type
== TYPE_FPSTORE
)
9718 rtx pat
= PATTERN(insn
);
9719 rtx dep_pat
= PATTERN (dep_insn
);
9721 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
9722 return cost
; /* This should not happen! */
9724 /* The dependency between the two instructions was on the data that
9725 is being stored. Assume that this implies that the address of the
9726 store is not dependent. */
9727 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
9730 return cost
+ 3; /* An approximation. */
9733 /* A shift instruction cannot receive its data from an instruction
9734 in the same cycle; add a one cycle penalty. */
9735 if (insn_type
== TYPE_SHIFT
)
9736 return cost
+ 3; /* Split before cascade into shift. */
9740 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
9741 INSN writes some cycles later. */
9743 /* These are only significant for the fpu unit; writing a fp reg before
9744 the fpu has finished with it stalls the processor. */
9746 /* Reusing an integer register causes no problems. */
9747 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
9755 hypersparc_adjust_cost (rtx_insn
*insn
, int dtype
, rtx_insn
*dep_insn
,
9758 enum attr_type insn_type
, dep_type
;
9759 rtx pat
= PATTERN(insn
);
9760 rtx dep_pat
= PATTERN (dep_insn
);
9762 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
9765 insn_type
= get_attr_type (insn
);
9766 dep_type
= get_attr_type (dep_insn
);
9771 /* Data dependency; DEP_INSN writes a register that INSN reads some
9778 /* Get the delay iff the address of the store is the dependence. */
9779 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
9782 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
9789 /* If a load, then the dependence must be on the memory address. If
9790 the addresses aren't equal, then it might be a false dependency */
9791 if (dep_type
== TYPE_STORE
|| dep_type
== TYPE_FPSTORE
)
9793 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
9794 || GET_CODE (SET_DEST (dep_pat
)) != MEM
9795 || GET_CODE (SET_SRC (pat
)) != MEM
9796 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat
), 0),
9797 XEXP (SET_SRC (pat
), 0)))
9805 /* Compare to branch latency is 0. There is no benefit from
9806 separating compare and branch. */
9807 if (dep_type
== TYPE_COMPARE
)
9809 /* Floating point compare to branch latency is less than
9810 compare to conditional move. */
9811 if (dep_type
== TYPE_FPCMP
)
9820 /* Anti-dependencies only penalize the fpu unit. */
9821 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
9833 sparc_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep
, int cost
,
9838 case PROCESSOR_SUPERSPARC
:
9839 cost
= supersparc_adjust_cost (insn
, dep_type
, dep
, cost
);
9841 case PROCESSOR_HYPERSPARC
:
9842 case PROCESSOR_SPARCLITE86X
:
9843 cost
= hypersparc_adjust_cost (insn
, dep_type
, dep
, cost
);
9852 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
9853 int sched_verbose ATTRIBUTE_UNUSED
,
9854 int max_ready ATTRIBUTE_UNUSED
)
9858 sparc_use_sched_lookahead (void)
9860 if (sparc_cpu
== PROCESSOR_NIAGARA
9861 || sparc_cpu
== PROCESSOR_NIAGARA2
9862 || sparc_cpu
== PROCESSOR_NIAGARA3
)
9864 if (sparc_cpu
== PROCESSOR_NIAGARA4
9865 || sparc_cpu
== PROCESSOR_NIAGARA7
9866 || sparc_cpu
== PROCESSOR_M8
)
9868 if (sparc_cpu
== PROCESSOR_ULTRASPARC
9869 || sparc_cpu
== PROCESSOR_ULTRASPARC3
)
9871 if ((1 << sparc_cpu
) &
9872 ((1 << PROCESSOR_SUPERSPARC
) | (1 << PROCESSOR_HYPERSPARC
) |
9873 (1 << PROCESSOR_SPARCLITE86X
)))
9879 sparc_issue_rate (void)
9883 case PROCESSOR_NIAGARA
:
9884 case PROCESSOR_NIAGARA2
:
9885 case PROCESSOR_NIAGARA3
:
9888 case PROCESSOR_NIAGARA4
:
9889 case PROCESSOR_NIAGARA7
:
9891 /* Assume V9 processors are capable of at least dual-issue. */
9893 case PROCESSOR_SUPERSPARC
:
9895 case PROCESSOR_HYPERSPARC
:
9896 case PROCESSOR_SPARCLITE86X
:
9898 case PROCESSOR_ULTRASPARC
:
9899 case PROCESSOR_ULTRASPARC3
:
9906 set_extends (rtx_insn
*insn
)
9908 register rtx pat
= PATTERN (insn
);
9910 switch (GET_CODE (SET_SRC (pat
)))
9912 /* Load and some shift instructions zero extend. */
9915 /* sethi clears the high bits */
9917 /* LO_SUM is used with sethi. sethi cleared the high
9918 bits and the values used with lo_sum are positive */
9920 /* Store flag stores 0 or 1 */
9930 rtx op0
= XEXP (SET_SRC (pat
), 0);
9931 rtx op1
= XEXP (SET_SRC (pat
), 1);
9932 if (GET_CODE (op1
) == CONST_INT
)
9933 return INTVAL (op1
) >= 0;
9934 if (GET_CODE (op0
) != REG
)
9936 if (sparc_check_64 (op0
, insn
) == 1)
9938 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
9943 rtx op0
= XEXP (SET_SRC (pat
), 0);
9944 rtx op1
= XEXP (SET_SRC (pat
), 1);
9945 if (GET_CODE (op0
) != REG
|| sparc_check_64 (op0
, insn
) <= 0)
9947 if (GET_CODE (op1
) == CONST_INT
)
9948 return INTVAL (op1
) >= 0;
9949 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
9952 return GET_MODE (SET_SRC (pat
)) == SImode
;
9953 /* Positive integers leave the high bits zero. */
9955 return !(INTVAL (SET_SRC (pat
)) & 0x80000000);
9958 return - (GET_MODE (SET_SRC (pat
)) == SImode
);
9960 return sparc_check_64 (SET_SRC (pat
), insn
);
9966 /* We _ought_ to have only one kind per function, but... */
9967 static GTY(()) rtx sparc_addr_diff_list
;
9968 static GTY(()) rtx sparc_addr_list
;
9971 sparc_defer_case_vector (rtx lab
, rtx vec
, int diff
)
9973 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
9975 sparc_addr_diff_list
9976 = gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_diff_list
);
9978 sparc_addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_list
);
9982 sparc_output_addr_vec (rtx vec
)
9984 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
9985 int idx
, vlen
= XVECLEN (body
, 0);
9987 #ifdef ASM_OUTPUT_ADDR_VEC_START
9988 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
9991 #ifdef ASM_OUTPUT_CASE_LABEL
9992 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
9995 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
9998 for (idx
= 0; idx
< vlen
; idx
++)
10000 ASM_OUTPUT_ADDR_VEC_ELT
10001 (asm_out_file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
10004 #ifdef ASM_OUTPUT_ADDR_VEC_END
10005 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
10010 sparc_output_addr_diff_vec (rtx vec
)
10012 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
10013 rtx base
= XEXP (XEXP (body
, 0), 0);
10014 int idx
, vlen
= XVECLEN (body
, 1);
10016 #ifdef ASM_OUTPUT_ADDR_VEC_START
10017 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
10020 #ifdef ASM_OUTPUT_CASE_LABEL
10021 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
10024 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
10027 for (idx
= 0; idx
< vlen
; idx
++)
10029 ASM_OUTPUT_ADDR_DIFF_ELT
10032 CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 1, idx
), 0)),
10033 CODE_LABEL_NUMBER (base
));
10036 #ifdef ASM_OUTPUT_ADDR_VEC_END
10037 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
10042 sparc_output_deferred_case_vectors (void)
10047 if (sparc_addr_list
== NULL_RTX
10048 && sparc_addr_diff_list
== NULL_RTX
)
10051 /* Align to cache line in the function's code section. */
10052 switch_to_section (current_function_section ());
10054 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
10056 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
10058 for (t
= sparc_addr_list
; t
; t
= XEXP (t
, 1))
10059 sparc_output_addr_vec (XEXP (t
, 0));
10060 for (t
= sparc_addr_diff_list
; t
; t
= XEXP (t
, 1))
10061 sparc_output_addr_diff_vec (XEXP (t
, 0));
10063 sparc_addr_list
= sparc_addr_diff_list
= NULL_RTX
;
10066 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
10067 unknown. Return 1 if the high bits are zero, -1 if the register is
10070 sparc_check_64 (rtx x
, rtx_insn
*insn
)
10072 /* If a register is set only once it is safe to ignore insns this
10073 code does not know how to handle. The loop will either recognize
10074 the single set and return the correct value or fail to recognize
10075 it and return 0. */
10079 gcc_assert (GET_CODE (x
) == REG
);
10081 if (GET_MODE (x
) == DImode
)
10082 y
= gen_rtx_REG (SImode
, REGNO (x
) + WORDS_BIG_ENDIAN
);
10084 if (flag_expensive_optimizations
10085 && df
&& DF_REG_DEF_COUNT (REGNO (y
)) == 1)
10091 insn
= get_last_insn_anywhere ();
10096 while ((insn
= PREV_INSN (insn
)))
10098 switch (GET_CODE (insn
))
10111 rtx pat
= PATTERN (insn
);
10112 if (GET_CODE (pat
) != SET
)
10114 if (rtx_equal_p (x
, SET_DEST (pat
)))
10115 return set_extends (insn
);
10116 if (y
&& rtx_equal_p (y
, SET_DEST (pat
)))
10117 return set_extends (insn
);
10118 if (reg_overlap_mentioned_p (SET_DEST (pat
), y
))
10126 /* Output a wide shift instruction in V8+ mode. INSN is the instruction,
10127 OPERANDS are its operands and OPCODE is the mnemonic to be used. */
10130 output_v8plus_shift (rtx_insn
*insn
, rtx
*operands
, const char *opcode
)
10132 static char asm_code
[60];
10134 /* The scratch register is only required when the destination
10135 register is not a 64-bit global or out register. */
10136 if (which_alternative
!= 2)
10137 operands
[3] = operands
[0];
10139 /* We can only shift by constants <= 63. */
10140 if (GET_CODE (operands
[2]) == CONST_INT
)
10141 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0x3f);
10143 if (GET_CODE (operands
[1]) == CONST_INT
)
10145 output_asm_insn ("mov\t%1, %3", operands
);
10149 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
10150 if (sparc_check_64 (operands
[1], insn
) <= 0)
10151 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
10152 output_asm_insn ("or\t%L1, %3, %3", operands
);
10155 strcpy (asm_code
, opcode
);
10157 if (which_alternative
!= 2)
10158 return strcat (asm_code
, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
10161 strcat (asm_code
, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
10164 /* Output rtl to increment the profiler label LABELNO
10165 for profiling a function entry. */
10168 sparc_profile_hook (int labelno
)
10173 fun
= gen_rtx_SYMBOL_REF (Pmode
, MCOUNT_FUNCTION
);
10174 if (NO_PROFILE_COUNTERS
)
10176 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 0);
10180 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
10181 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
10182 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 1, lab
, Pmode
);
10186 #ifdef TARGET_SOLARIS
10187 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
10190 sparc_solaris_elf_asm_named_section (const char *name
, unsigned int flags
,
10191 tree decl ATTRIBUTE_UNUSED
)
10193 if (HAVE_COMDAT_GROUP
&& flags
& SECTION_LINKONCE
)
10195 solaris_elf_asm_comdat_section (name
, flags
, decl
);
10199 fprintf (asm_out_file
, "\t.section\t\"%s\"", name
);
10201 if (!(flags
& SECTION_DEBUG
))
10202 fputs (",#alloc", asm_out_file
);
10203 if (flags
& SECTION_WRITE
)
10204 fputs (",#write", asm_out_file
);
10205 if (flags
& SECTION_TLS
)
10206 fputs (",#tls", asm_out_file
);
10207 if (flags
& SECTION_CODE
)
10208 fputs (",#execinstr", asm_out_file
);
10210 if (flags
& SECTION_NOTYPE
)
10212 else if (flags
& SECTION_BSS
)
10213 fputs (",#nobits", asm_out_file
);
10215 fputs (",#progbits", asm_out_file
);
10217 fputc ('\n', asm_out_file
);
10219 #endif /* TARGET_SOLARIS */
10221 /* We do not allow indirect calls to be optimized into sibling calls.
10223 We cannot use sibling calls when delayed branches are disabled
10224 because they will likely require the call delay slot to be filled.
10226 Also, on SPARC 32-bit we cannot emit a sibling call when the
10227 current function returns a structure. This is because the "unimp
10228 after call" convention would cause the callee to return to the
10229 wrong place. The generic code already disallows cases where the
10230 function being called returns a structure.
10232 It may seem strange how this last case could occur. Usually there
10233 is code after the call which jumps to epilogue code which dumps the
10234 return value into the struct return area. That ought to invalidate
10235 the sibling call right? Well, in the C++ case we can end up passing
10236 the pointer to the struct return area to a constructor (which returns
10237 void) and then nothing else happens. Such a sibling call would look
10238 valid without the added check here.
10240 VxWorks PIC PLT entries require the global pointer to be initialized
10241 on entry. We therefore can't emit sibling calls to them. */
10243 sparc_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
10246 && flag_delayed_branch
10247 && (TARGET_ARCH64
|| ! cfun
->returns_struct
)
10248 && !(TARGET_VXWORKS_RTP
10250 && !targetm
.binds_local_p (decl
)));
10253 /* libfunc renaming. */
10256 sparc_init_libfuncs (void)
10260 /* Use the subroutines that Sun's library provides for integer
10261 multiply and divide. The `*' prevents an underscore from
10262 being prepended by the compiler. .umul is a little faster
10264 set_optab_libfunc (smul_optab
, SImode
, "*.umul");
10265 set_optab_libfunc (sdiv_optab
, SImode
, "*.div");
10266 set_optab_libfunc (udiv_optab
, SImode
, "*.udiv");
10267 set_optab_libfunc (smod_optab
, SImode
, "*.rem");
10268 set_optab_libfunc (umod_optab
, SImode
, "*.urem");
10270 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
10271 set_optab_libfunc (add_optab
, TFmode
, "_Q_add");
10272 set_optab_libfunc (sub_optab
, TFmode
, "_Q_sub");
10273 set_optab_libfunc (neg_optab
, TFmode
, "_Q_neg");
10274 set_optab_libfunc (smul_optab
, TFmode
, "_Q_mul");
10275 set_optab_libfunc (sdiv_optab
, TFmode
, "_Q_div");
10277 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
10278 is because with soft-float, the SFmode and DFmode sqrt
10279 instructions will be absent, and the compiler will notice and
10280 try to use the TFmode sqrt instruction for calls to the
10281 builtin function sqrt, but this fails. */
10283 set_optab_libfunc (sqrt_optab
, TFmode
, "_Q_sqrt");
10285 set_optab_libfunc (eq_optab
, TFmode
, "_Q_feq");
10286 set_optab_libfunc (ne_optab
, TFmode
, "_Q_fne");
10287 set_optab_libfunc (gt_optab
, TFmode
, "_Q_fgt");
10288 set_optab_libfunc (ge_optab
, TFmode
, "_Q_fge");
10289 set_optab_libfunc (lt_optab
, TFmode
, "_Q_flt");
10290 set_optab_libfunc (le_optab
, TFmode
, "_Q_fle");
10292 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_Q_stoq");
10293 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_Q_dtoq");
10294 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_Q_qtos");
10295 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_Q_qtod");
10297 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_Q_qtoi");
10298 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_Q_qtou");
10299 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_Q_itoq");
10300 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_Q_utoq");
10302 if (DITF_CONVERSION_LIBFUNCS
)
10304 set_conv_libfunc (sfix_optab
, DImode
, TFmode
, "_Q_qtoll");
10305 set_conv_libfunc (ufix_optab
, DImode
, TFmode
, "_Q_qtoull");
10306 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
, "_Q_lltoq");
10307 set_conv_libfunc (ufloat_optab
, TFmode
, DImode
, "_Q_ulltoq");
10310 if (SUN_CONVERSION_LIBFUNCS
)
10312 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
10313 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
10314 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
10315 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
10320 /* In the SPARC 64bit ABI, SImode multiply and divide functions
10321 do not exist in the library. Make sure the compiler does not
10322 emit calls to them by accident. (It should always use the
10323 hardware instructions.) */
10324 set_optab_libfunc (smul_optab
, SImode
, 0);
10325 set_optab_libfunc (sdiv_optab
, SImode
, 0);
10326 set_optab_libfunc (udiv_optab
, SImode
, 0);
10327 set_optab_libfunc (smod_optab
, SImode
, 0);
10328 set_optab_libfunc (umod_optab
, SImode
, 0);
10330 if (SUN_INTEGER_MULTIPLY_64
)
10332 set_optab_libfunc (smul_optab
, DImode
, "__mul64");
10333 set_optab_libfunc (sdiv_optab
, DImode
, "__div64");
10334 set_optab_libfunc (udiv_optab
, DImode
, "__udiv64");
10335 set_optab_libfunc (smod_optab
, DImode
, "__rem64");
10336 set_optab_libfunc (umod_optab
, DImode
, "__urem64");
10339 if (SUN_CONVERSION_LIBFUNCS
)
10341 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftol");
10342 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoul");
10343 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtol");
10344 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoul");
10349 /* SPARC builtins. */
10350 enum sparc_builtins
10352 /* FPU builtins. */
10353 SPARC_BUILTIN_LDFSR
,
10354 SPARC_BUILTIN_STFSR
,
10356 /* VIS 1.0 builtins. */
10357 SPARC_BUILTIN_FPACK16
,
10358 SPARC_BUILTIN_FPACK32
,
10359 SPARC_BUILTIN_FPACKFIX
,
10360 SPARC_BUILTIN_FEXPAND
,
10361 SPARC_BUILTIN_FPMERGE
,
10362 SPARC_BUILTIN_FMUL8X16
,
10363 SPARC_BUILTIN_FMUL8X16AU
,
10364 SPARC_BUILTIN_FMUL8X16AL
,
10365 SPARC_BUILTIN_FMUL8SUX16
,
10366 SPARC_BUILTIN_FMUL8ULX16
,
10367 SPARC_BUILTIN_FMULD8SUX16
,
10368 SPARC_BUILTIN_FMULD8ULX16
,
10369 SPARC_BUILTIN_FALIGNDATAV4HI
,
10370 SPARC_BUILTIN_FALIGNDATAV8QI
,
10371 SPARC_BUILTIN_FALIGNDATAV2SI
,
10372 SPARC_BUILTIN_FALIGNDATADI
,
10373 SPARC_BUILTIN_WRGSR
,
10374 SPARC_BUILTIN_RDGSR
,
10375 SPARC_BUILTIN_ALIGNADDR
,
10376 SPARC_BUILTIN_ALIGNADDRL
,
10377 SPARC_BUILTIN_PDIST
,
10378 SPARC_BUILTIN_EDGE8
,
10379 SPARC_BUILTIN_EDGE8L
,
10380 SPARC_BUILTIN_EDGE16
,
10381 SPARC_BUILTIN_EDGE16L
,
10382 SPARC_BUILTIN_EDGE32
,
10383 SPARC_BUILTIN_EDGE32L
,
10384 SPARC_BUILTIN_FCMPLE16
,
10385 SPARC_BUILTIN_FCMPLE32
,
10386 SPARC_BUILTIN_FCMPNE16
,
10387 SPARC_BUILTIN_FCMPNE32
,
10388 SPARC_BUILTIN_FCMPGT16
,
10389 SPARC_BUILTIN_FCMPGT32
,
10390 SPARC_BUILTIN_FCMPEQ16
,
10391 SPARC_BUILTIN_FCMPEQ32
,
10392 SPARC_BUILTIN_FPADD16
,
10393 SPARC_BUILTIN_FPADD16S
,
10394 SPARC_BUILTIN_FPADD32
,
10395 SPARC_BUILTIN_FPADD32S
,
10396 SPARC_BUILTIN_FPSUB16
,
10397 SPARC_BUILTIN_FPSUB16S
,
10398 SPARC_BUILTIN_FPSUB32
,
10399 SPARC_BUILTIN_FPSUB32S
,
10400 SPARC_BUILTIN_ARRAY8
,
10401 SPARC_BUILTIN_ARRAY16
,
10402 SPARC_BUILTIN_ARRAY32
,
10404 /* VIS 2.0 builtins. */
10405 SPARC_BUILTIN_EDGE8N
,
10406 SPARC_BUILTIN_EDGE8LN
,
10407 SPARC_BUILTIN_EDGE16N
,
10408 SPARC_BUILTIN_EDGE16LN
,
10409 SPARC_BUILTIN_EDGE32N
,
10410 SPARC_BUILTIN_EDGE32LN
,
10411 SPARC_BUILTIN_BMASK
,
10412 SPARC_BUILTIN_BSHUFFLEV4HI
,
10413 SPARC_BUILTIN_BSHUFFLEV8QI
,
10414 SPARC_BUILTIN_BSHUFFLEV2SI
,
10415 SPARC_BUILTIN_BSHUFFLEDI
,
10417 /* VIS 3.0 builtins. */
10418 SPARC_BUILTIN_CMASK8
,
10419 SPARC_BUILTIN_CMASK16
,
10420 SPARC_BUILTIN_CMASK32
,
10421 SPARC_BUILTIN_FCHKSM16
,
10422 SPARC_BUILTIN_FSLL16
,
10423 SPARC_BUILTIN_FSLAS16
,
10424 SPARC_BUILTIN_FSRL16
,
10425 SPARC_BUILTIN_FSRA16
,
10426 SPARC_BUILTIN_FSLL32
,
10427 SPARC_BUILTIN_FSLAS32
,
10428 SPARC_BUILTIN_FSRL32
,
10429 SPARC_BUILTIN_FSRA32
,
10430 SPARC_BUILTIN_PDISTN
,
10431 SPARC_BUILTIN_FMEAN16
,
10432 SPARC_BUILTIN_FPADD64
,
10433 SPARC_BUILTIN_FPSUB64
,
10434 SPARC_BUILTIN_FPADDS16
,
10435 SPARC_BUILTIN_FPADDS16S
,
10436 SPARC_BUILTIN_FPSUBS16
,
10437 SPARC_BUILTIN_FPSUBS16S
,
10438 SPARC_BUILTIN_FPADDS32
,
10439 SPARC_BUILTIN_FPADDS32S
,
10440 SPARC_BUILTIN_FPSUBS32
,
10441 SPARC_BUILTIN_FPSUBS32S
,
10442 SPARC_BUILTIN_FUCMPLE8
,
10443 SPARC_BUILTIN_FUCMPNE8
,
10444 SPARC_BUILTIN_FUCMPGT8
,
10445 SPARC_BUILTIN_FUCMPEQ8
,
10446 SPARC_BUILTIN_FHADDS
,
10447 SPARC_BUILTIN_FHADDD
,
10448 SPARC_BUILTIN_FHSUBS
,
10449 SPARC_BUILTIN_FHSUBD
,
10450 SPARC_BUILTIN_FNHADDS
,
10451 SPARC_BUILTIN_FNHADDD
,
10452 SPARC_BUILTIN_UMULXHI
,
10453 SPARC_BUILTIN_XMULX
,
10454 SPARC_BUILTIN_XMULXHI
,
10456 /* VIS 4.0 builtins. */
10457 SPARC_BUILTIN_FPADD8
,
10458 SPARC_BUILTIN_FPADDS8
,
10459 SPARC_BUILTIN_FPADDUS8
,
10460 SPARC_BUILTIN_FPADDUS16
,
10461 SPARC_BUILTIN_FPCMPLE8
,
10462 SPARC_BUILTIN_FPCMPGT8
,
10463 SPARC_BUILTIN_FPCMPULE16
,
10464 SPARC_BUILTIN_FPCMPUGT16
,
10465 SPARC_BUILTIN_FPCMPULE32
,
10466 SPARC_BUILTIN_FPCMPUGT32
,
10467 SPARC_BUILTIN_FPMAX8
,
10468 SPARC_BUILTIN_FPMAX16
,
10469 SPARC_BUILTIN_FPMAX32
,
10470 SPARC_BUILTIN_FPMAXU8
,
10471 SPARC_BUILTIN_FPMAXU16
,
10472 SPARC_BUILTIN_FPMAXU32
,
10473 SPARC_BUILTIN_FPMIN8
,
10474 SPARC_BUILTIN_FPMIN16
,
10475 SPARC_BUILTIN_FPMIN32
,
10476 SPARC_BUILTIN_FPMINU8
,
10477 SPARC_BUILTIN_FPMINU16
,
10478 SPARC_BUILTIN_FPMINU32
,
10479 SPARC_BUILTIN_FPSUB8
,
10480 SPARC_BUILTIN_FPSUBS8
,
10481 SPARC_BUILTIN_FPSUBUS8
,
10482 SPARC_BUILTIN_FPSUBUS16
,
10484 /* VIS 4.0B builtins. */
10486 /* Note that all the DICTUNPACK* entries should be kept
10488 SPARC_BUILTIN_FIRST_DICTUNPACK
,
10489 SPARC_BUILTIN_DICTUNPACK8
= SPARC_BUILTIN_FIRST_DICTUNPACK
,
10490 SPARC_BUILTIN_DICTUNPACK16
,
10491 SPARC_BUILTIN_DICTUNPACK32
,
10492 SPARC_BUILTIN_LAST_DICTUNPACK
= SPARC_BUILTIN_DICTUNPACK32
,
10494 /* Note that all the FPCMP*SHL entries should be kept
10496 SPARC_BUILTIN_FIRST_FPCMPSHL
,
10497 SPARC_BUILTIN_FPCMPLE8SHL
= SPARC_BUILTIN_FIRST_FPCMPSHL
,
10498 SPARC_BUILTIN_FPCMPGT8SHL
,
10499 SPARC_BUILTIN_FPCMPEQ8SHL
,
10500 SPARC_BUILTIN_FPCMPNE8SHL
,
10501 SPARC_BUILTIN_FPCMPLE16SHL
,
10502 SPARC_BUILTIN_FPCMPGT16SHL
,
10503 SPARC_BUILTIN_FPCMPEQ16SHL
,
10504 SPARC_BUILTIN_FPCMPNE16SHL
,
10505 SPARC_BUILTIN_FPCMPLE32SHL
,
10506 SPARC_BUILTIN_FPCMPGT32SHL
,
10507 SPARC_BUILTIN_FPCMPEQ32SHL
,
10508 SPARC_BUILTIN_FPCMPNE32SHL
,
10509 SPARC_BUILTIN_FPCMPULE8SHL
,
10510 SPARC_BUILTIN_FPCMPUGT8SHL
,
10511 SPARC_BUILTIN_FPCMPULE16SHL
,
10512 SPARC_BUILTIN_FPCMPUGT16SHL
,
10513 SPARC_BUILTIN_FPCMPULE32SHL
,
10514 SPARC_BUILTIN_FPCMPUGT32SHL
,
10515 SPARC_BUILTIN_FPCMPDE8SHL
,
10516 SPARC_BUILTIN_FPCMPDE16SHL
,
10517 SPARC_BUILTIN_FPCMPDE32SHL
,
10518 SPARC_BUILTIN_FPCMPUR8SHL
,
10519 SPARC_BUILTIN_FPCMPUR16SHL
,
10520 SPARC_BUILTIN_FPCMPUR32SHL
,
10521 SPARC_BUILTIN_LAST_FPCMPSHL
= SPARC_BUILTIN_FPCMPUR32SHL
,
10526 static GTY (()) tree sparc_builtins
[(int) SPARC_BUILTIN_MAX
];
10527 static enum insn_code sparc_builtins_icode
[(int) SPARC_BUILTIN_MAX
];
10529 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
10530 The instruction should require a constant operand of some sort. The
10531 function prints an error if OPVAL is not valid. */
10534 check_constant_argument (enum insn_code icode
, int opnum
, rtx opval
)
10536 if (GET_CODE (opval
) != CONST_INT
)
10538 error ("%qs expects a constant argument", insn_data
[icode
].name
);
10542 if (!(*insn_data
[icode
].operand
[opnum
].predicate
) (opval
, VOIDmode
))
10544 error ("constant argument out of range for %qs", insn_data
[icode
].name
);
10550 /* Add a SPARC builtin function with NAME, ICODE, CODE and TYPE. Return the
10551 function decl or NULL_TREE if the builtin was not added. */
10554 def_builtin (const char *name
, enum insn_code icode
, enum sparc_builtins code
,
10558 = add_builtin_function (name
, type
, code
, BUILT_IN_MD
, NULL
, NULL_TREE
);
10562 sparc_builtins
[code
] = t
;
10563 sparc_builtins_icode
[code
] = icode
;
10569 /* Likewise, but also marks the function as "const". */
10572 def_builtin_const (const char *name
, enum insn_code icode
,
10573 enum sparc_builtins code
, tree type
)
10575 tree t
= def_builtin (name
, icode
, code
, type
);
10578 TREE_READONLY (t
) = 1;
10583 /* Implement the TARGET_INIT_BUILTINS target hook.
10584 Create builtin functions for special SPARC instructions. */
10587 sparc_init_builtins (void)
10590 sparc_fpu_init_builtins ();
10593 sparc_vis_init_builtins ();
10596 /* Create builtin functions for FPU instructions. */
10599 sparc_fpu_init_builtins (void)
10602 = build_function_type_list (void_type_node
,
10603 build_pointer_type (unsigned_type_node
), 0);
10604 def_builtin ("__builtin_load_fsr", CODE_FOR_ldfsr
,
10605 SPARC_BUILTIN_LDFSR
, ftype
);
10606 def_builtin ("__builtin_store_fsr", CODE_FOR_stfsr
,
10607 SPARC_BUILTIN_STFSR
, ftype
);
10610 /* Create builtin functions for VIS instructions. */
10613 sparc_vis_init_builtins (void)
10615 tree v4qi
= build_vector_type (unsigned_intQI_type_node
, 4);
10616 tree v8qi
= build_vector_type (unsigned_intQI_type_node
, 8);
10617 tree v4hi
= build_vector_type (intHI_type_node
, 4);
10618 tree v2hi
= build_vector_type (intHI_type_node
, 2);
10619 tree v2si
= build_vector_type (intSI_type_node
, 2);
10620 tree v1si
= build_vector_type (intSI_type_node
, 1);
10622 tree v4qi_ftype_v4hi
= build_function_type_list (v4qi
, v4hi
, 0);
10623 tree v8qi_ftype_v2si_v8qi
= build_function_type_list (v8qi
, v2si
, v8qi
, 0);
10624 tree v2hi_ftype_v2si
= build_function_type_list (v2hi
, v2si
, 0);
10625 tree v4hi_ftype_v4qi
= build_function_type_list (v4hi
, v4qi
, 0);
10626 tree v8qi_ftype_v4qi_v4qi
= build_function_type_list (v8qi
, v4qi
, v4qi
, 0);
10627 tree v4hi_ftype_v4qi_v4hi
= build_function_type_list (v4hi
, v4qi
, v4hi
, 0);
10628 tree v4hi_ftype_v4qi_v2hi
= build_function_type_list (v4hi
, v4qi
, v2hi
, 0);
10629 tree v2si_ftype_v4qi_v2hi
= build_function_type_list (v2si
, v4qi
, v2hi
, 0);
10630 tree v4hi_ftype_v8qi_v4hi
= build_function_type_list (v4hi
, v8qi
, v4hi
, 0);
10631 tree v4hi_ftype_v4hi_v4hi
= build_function_type_list (v4hi
, v4hi
, v4hi
, 0);
10632 tree v2si_ftype_v2si_v2si
= build_function_type_list (v2si
, v2si
, v2si
, 0);
10633 tree v8qi_ftype_v8qi_v8qi
= build_function_type_list (v8qi
, v8qi
, v8qi
, 0);
10634 tree v2hi_ftype_v2hi_v2hi
= build_function_type_list (v2hi
, v2hi
, v2hi
, 0);
10635 tree v1si_ftype_v1si_v1si
= build_function_type_list (v1si
, v1si
, v1si
, 0);
10636 tree di_ftype_v8qi_v8qi_di
= build_function_type_list (intDI_type_node
,
10638 intDI_type_node
, 0);
10639 tree di_ftype_v8qi_v8qi
= build_function_type_list (intDI_type_node
,
10641 tree si_ftype_v8qi_v8qi
= build_function_type_list (intSI_type_node
,
10643 tree v8qi_ftype_df_si
= build_function_type_list (v8qi
, double_type_node
,
10644 intSI_type_node
, 0);
10645 tree v4hi_ftype_df_si
= build_function_type_list (v4hi
, double_type_node
,
10646 intSI_type_node
, 0);
10647 tree v2si_ftype_df_si
= build_function_type_list (v2si
, double_type_node
,
10648 intDI_type_node
, 0);
10649 tree di_ftype_di_di
= build_function_type_list (intDI_type_node
,
10651 intDI_type_node
, 0);
10652 tree si_ftype_si_si
= build_function_type_list (intSI_type_node
,
10654 intSI_type_node
, 0);
10655 tree ptr_ftype_ptr_si
= build_function_type_list (ptr_type_node
,
10657 intSI_type_node
, 0);
10658 tree ptr_ftype_ptr_di
= build_function_type_list (ptr_type_node
,
10660 intDI_type_node
, 0);
10661 tree si_ftype_ptr_ptr
= build_function_type_list (intSI_type_node
,
10664 tree di_ftype_ptr_ptr
= build_function_type_list (intDI_type_node
,
10667 tree si_ftype_v4hi_v4hi
= build_function_type_list (intSI_type_node
,
10669 tree si_ftype_v2si_v2si
= build_function_type_list (intSI_type_node
,
10671 tree di_ftype_v4hi_v4hi
= build_function_type_list (intDI_type_node
,
10673 tree di_ftype_v2si_v2si
= build_function_type_list (intDI_type_node
,
10675 tree void_ftype_di
= build_function_type_list (void_type_node
,
10676 intDI_type_node
, 0);
10677 tree di_ftype_void
= build_function_type_list (intDI_type_node
,
10678 void_type_node
, 0);
10679 tree void_ftype_si
= build_function_type_list (void_type_node
,
10680 intSI_type_node
, 0);
10681 tree sf_ftype_sf_sf
= build_function_type_list (float_type_node
,
10683 float_type_node
, 0);
10684 tree df_ftype_df_df
= build_function_type_list (double_type_node
,
10686 double_type_node
, 0);
10688 /* Packing and expanding vectors. */
10689 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis
,
10690 SPARC_BUILTIN_FPACK16
, v4qi_ftype_v4hi
);
10691 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis
,
10692 SPARC_BUILTIN_FPACK32
, v8qi_ftype_v2si_v8qi
);
10693 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis
,
10694 SPARC_BUILTIN_FPACKFIX
, v2hi_ftype_v2si
);
10695 def_builtin_const ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis
,
10696 SPARC_BUILTIN_FEXPAND
, v4hi_ftype_v4qi
);
10697 def_builtin_const ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis
,
10698 SPARC_BUILTIN_FPMERGE
, v8qi_ftype_v4qi_v4qi
);
10700 /* Multiplications. */
10701 def_builtin_const ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis
,
10702 SPARC_BUILTIN_FMUL8X16
, v4hi_ftype_v4qi_v4hi
);
10703 def_builtin_const ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis
,
10704 SPARC_BUILTIN_FMUL8X16AU
, v4hi_ftype_v4qi_v2hi
);
10705 def_builtin_const ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis
,
10706 SPARC_BUILTIN_FMUL8X16AL
, v4hi_ftype_v4qi_v2hi
);
10707 def_builtin_const ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis
,
10708 SPARC_BUILTIN_FMUL8SUX16
, v4hi_ftype_v8qi_v4hi
);
10709 def_builtin_const ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis
,
10710 SPARC_BUILTIN_FMUL8ULX16
, v4hi_ftype_v8qi_v4hi
);
10711 def_builtin_const ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis
,
10712 SPARC_BUILTIN_FMULD8SUX16
, v2si_ftype_v4qi_v2hi
);
10713 def_builtin_const ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis
,
10714 SPARC_BUILTIN_FMULD8ULX16
, v2si_ftype_v4qi_v2hi
);
10716 /* Data aligning. */
10717 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis
,
10718 SPARC_BUILTIN_FALIGNDATAV4HI
, v4hi_ftype_v4hi_v4hi
);
10719 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis
,
10720 SPARC_BUILTIN_FALIGNDATAV8QI
, v8qi_ftype_v8qi_v8qi
);
10721 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis
,
10722 SPARC_BUILTIN_FALIGNDATAV2SI
, v2si_ftype_v2si_v2si
);
10723 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatav1di_vis
,
10724 SPARC_BUILTIN_FALIGNDATADI
, di_ftype_di_di
);
10726 def_builtin ("__builtin_vis_write_gsr", CODE_FOR_wrgsr_vis
,
10727 SPARC_BUILTIN_WRGSR
, void_ftype_di
);
10728 def_builtin ("__builtin_vis_read_gsr", CODE_FOR_rdgsr_vis
,
10729 SPARC_BUILTIN_RDGSR
, di_ftype_void
);
10733 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis
,
10734 SPARC_BUILTIN_ALIGNADDR
, ptr_ftype_ptr_di
);
10735 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrldi_vis
,
10736 SPARC_BUILTIN_ALIGNADDRL
, ptr_ftype_ptr_di
);
10740 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis
,
10741 SPARC_BUILTIN_ALIGNADDR
, ptr_ftype_ptr_si
);
10742 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrlsi_vis
,
10743 SPARC_BUILTIN_ALIGNADDRL
, ptr_ftype_ptr_si
);
10746 /* Pixel distance. */
10747 def_builtin_const ("__builtin_vis_pdist", CODE_FOR_pdist_vis
,
10748 SPARC_BUILTIN_PDIST
, di_ftype_v8qi_v8qi_di
);
10750 /* Edge handling. */
10753 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8di_vis
,
10754 SPARC_BUILTIN_EDGE8
, di_ftype_ptr_ptr
);
10755 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8ldi_vis
,
10756 SPARC_BUILTIN_EDGE8L
, di_ftype_ptr_ptr
);
10757 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16di_vis
,
10758 SPARC_BUILTIN_EDGE16
, di_ftype_ptr_ptr
);
10759 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16ldi_vis
,
10760 SPARC_BUILTIN_EDGE16L
, di_ftype_ptr_ptr
);
10761 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32di_vis
,
10762 SPARC_BUILTIN_EDGE32
, di_ftype_ptr_ptr
);
10763 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32ldi_vis
,
10764 SPARC_BUILTIN_EDGE32L
, di_ftype_ptr_ptr
);
10768 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8si_vis
,
10769 SPARC_BUILTIN_EDGE8
, si_ftype_ptr_ptr
);
10770 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8lsi_vis
,
10771 SPARC_BUILTIN_EDGE8L
, si_ftype_ptr_ptr
);
10772 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16si_vis
,
10773 SPARC_BUILTIN_EDGE16
, si_ftype_ptr_ptr
);
10774 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16lsi_vis
,
10775 SPARC_BUILTIN_EDGE16L
, si_ftype_ptr_ptr
);
10776 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32si_vis
,
10777 SPARC_BUILTIN_EDGE32
, si_ftype_ptr_ptr
);
10778 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32lsi_vis
,
10779 SPARC_BUILTIN_EDGE32L
, si_ftype_ptr_ptr
);
10782 /* Pixel compare. */
10785 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16di_vis
,
10786 SPARC_BUILTIN_FCMPLE16
, di_ftype_v4hi_v4hi
);
10787 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32di_vis
,
10788 SPARC_BUILTIN_FCMPLE32
, di_ftype_v2si_v2si
);
10789 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16di_vis
,
10790 SPARC_BUILTIN_FCMPNE16
, di_ftype_v4hi_v4hi
);
10791 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32di_vis
,
10792 SPARC_BUILTIN_FCMPNE32
, di_ftype_v2si_v2si
);
10793 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16di_vis
,
10794 SPARC_BUILTIN_FCMPGT16
, di_ftype_v4hi_v4hi
);
10795 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32di_vis
,
10796 SPARC_BUILTIN_FCMPGT32
, di_ftype_v2si_v2si
);
10797 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16di_vis
,
10798 SPARC_BUILTIN_FCMPEQ16
, di_ftype_v4hi_v4hi
);
10799 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32di_vis
,
10800 SPARC_BUILTIN_FCMPEQ32
, di_ftype_v2si_v2si
);
10804 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16si_vis
,
10805 SPARC_BUILTIN_FCMPLE16
, si_ftype_v4hi_v4hi
);
10806 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32si_vis
,
10807 SPARC_BUILTIN_FCMPLE32
, si_ftype_v2si_v2si
);
10808 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16si_vis
,
10809 SPARC_BUILTIN_FCMPNE16
, si_ftype_v4hi_v4hi
);
10810 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32si_vis
,
10811 SPARC_BUILTIN_FCMPNE32
, si_ftype_v2si_v2si
);
10812 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16si_vis
,
10813 SPARC_BUILTIN_FCMPGT16
, si_ftype_v4hi_v4hi
);
10814 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32si_vis
,
10815 SPARC_BUILTIN_FCMPGT32
, si_ftype_v2si_v2si
);
10816 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16si_vis
,
10817 SPARC_BUILTIN_FCMPEQ16
, si_ftype_v4hi_v4hi
);
10818 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32si_vis
,
10819 SPARC_BUILTIN_FCMPEQ32
, si_ftype_v2si_v2si
);
10822 /* Addition and subtraction. */
10823 def_builtin_const ("__builtin_vis_fpadd16", CODE_FOR_addv4hi3
,
10824 SPARC_BUILTIN_FPADD16
, v4hi_ftype_v4hi_v4hi
);
10825 def_builtin_const ("__builtin_vis_fpadd16s", CODE_FOR_addv2hi3
,
10826 SPARC_BUILTIN_FPADD16S
, v2hi_ftype_v2hi_v2hi
);
10827 def_builtin_const ("__builtin_vis_fpadd32", CODE_FOR_addv2si3
,
10828 SPARC_BUILTIN_FPADD32
, v2si_ftype_v2si_v2si
);
10829 def_builtin_const ("__builtin_vis_fpadd32s", CODE_FOR_addv1si3
,
10830 SPARC_BUILTIN_FPADD32S
, v1si_ftype_v1si_v1si
);
10831 def_builtin_const ("__builtin_vis_fpsub16", CODE_FOR_subv4hi3
,
10832 SPARC_BUILTIN_FPSUB16
, v4hi_ftype_v4hi_v4hi
);
10833 def_builtin_const ("__builtin_vis_fpsub16s", CODE_FOR_subv2hi3
,
10834 SPARC_BUILTIN_FPSUB16S
, v2hi_ftype_v2hi_v2hi
);
10835 def_builtin_const ("__builtin_vis_fpsub32", CODE_FOR_subv2si3
,
10836 SPARC_BUILTIN_FPSUB32
, v2si_ftype_v2si_v2si
);
10837 def_builtin_const ("__builtin_vis_fpsub32s", CODE_FOR_subv1si3
,
10838 SPARC_BUILTIN_FPSUB32S
, v1si_ftype_v1si_v1si
);
10840 /* Three-dimensional array addressing. */
10843 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8di_vis
,
10844 SPARC_BUILTIN_ARRAY8
, di_ftype_di_di
);
10845 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16di_vis
,
10846 SPARC_BUILTIN_ARRAY16
, di_ftype_di_di
);
10847 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32di_vis
,
10848 SPARC_BUILTIN_ARRAY32
, di_ftype_di_di
);
10852 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8si_vis
,
10853 SPARC_BUILTIN_ARRAY8
, si_ftype_si_si
);
10854 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16si_vis
,
10855 SPARC_BUILTIN_ARRAY16
, si_ftype_si_si
);
10856 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32si_vis
,
10857 SPARC_BUILTIN_ARRAY32
, si_ftype_si_si
);
10862 /* Edge handling. */
10865 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8ndi_vis
,
10866 SPARC_BUILTIN_EDGE8N
, di_ftype_ptr_ptr
);
10867 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lndi_vis
,
10868 SPARC_BUILTIN_EDGE8LN
, di_ftype_ptr_ptr
);
10869 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16ndi_vis
,
10870 SPARC_BUILTIN_EDGE16N
, di_ftype_ptr_ptr
);
10871 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lndi_vis
,
10872 SPARC_BUILTIN_EDGE16LN
, di_ftype_ptr_ptr
);
10873 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32ndi_vis
,
10874 SPARC_BUILTIN_EDGE32N
, di_ftype_ptr_ptr
);
10875 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lndi_vis
,
10876 SPARC_BUILTIN_EDGE32LN
, di_ftype_ptr_ptr
);
10880 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8nsi_vis
,
10881 SPARC_BUILTIN_EDGE8N
, si_ftype_ptr_ptr
);
10882 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lnsi_vis
,
10883 SPARC_BUILTIN_EDGE8LN
, si_ftype_ptr_ptr
);
10884 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16nsi_vis
,
10885 SPARC_BUILTIN_EDGE16N
, si_ftype_ptr_ptr
);
10886 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lnsi_vis
,
10887 SPARC_BUILTIN_EDGE16LN
, si_ftype_ptr_ptr
);
10888 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32nsi_vis
,
10889 SPARC_BUILTIN_EDGE32N
, si_ftype_ptr_ptr
);
10890 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lnsi_vis
,
10891 SPARC_BUILTIN_EDGE32LN
, si_ftype_ptr_ptr
);
10894 /* Byte mask and shuffle. */
10896 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmaskdi_vis
,
10897 SPARC_BUILTIN_BMASK
, di_ftype_di_di
);
10899 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmasksi_vis
,
10900 SPARC_BUILTIN_BMASK
, si_ftype_si_si
);
10901 def_builtin ("__builtin_vis_bshufflev4hi", CODE_FOR_bshufflev4hi_vis
,
10902 SPARC_BUILTIN_BSHUFFLEV4HI
, v4hi_ftype_v4hi_v4hi
);
10903 def_builtin ("__builtin_vis_bshufflev8qi", CODE_FOR_bshufflev8qi_vis
,
10904 SPARC_BUILTIN_BSHUFFLEV8QI
, v8qi_ftype_v8qi_v8qi
);
10905 def_builtin ("__builtin_vis_bshufflev2si", CODE_FOR_bshufflev2si_vis
,
10906 SPARC_BUILTIN_BSHUFFLEV2SI
, v2si_ftype_v2si_v2si
);
10907 def_builtin ("__builtin_vis_bshuffledi", CODE_FOR_bshufflev1di_vis
,
10908 SPARC_BUILTIN_BSHUFFLEDI
, di_ftype_di_di
);
10915 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8di_vis
,
10916 SPARC_BUILTIN_CMASK8
, void_ftype_di
);
10917 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16di_vis
,
10918 SPARC_BUILTIN_CMASK16
, void_ftype_di
);
10919 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32di_vis
,
10920 SPARC_BUILTIN_CMASK32
, void_ftype_di
);
10924 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8si_vis
,
10925 SPARC_BUILTIN_CMASK8
, void_ftype_si
);
10926 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16si_vis
,
10927 SPARC_BUILTIN_CMASK16
, void_ftype_si
);
10928 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32si_vis
,
10929 SPARC_BUILTIN_CMASK32
, void_ftype_si
);
10932 def_builtin_const ("__builtin_vis_fchksm16", CODE_FOR_fchksm16_vis
,
10933 SPARC_BUILTIN_FCHKSM16
, v4hi_ftype_v4hi_v4hi
);
10935 def_builtin_const ("__builtin_vis_fsll16", CODE_FOR_vashlv4hi3
,
10936 SPARC_BUILTIN_FSLL16
, v4hi_ftype_v4hi_v4hi
);
10937 def_builtin_const ("__builtin_vis_fslas16", CODE_FOR_vssashlv4hi3
,
10938 SPARC_BUILTIN_FSLAS16
, v4hi_ftype_v4hi_v4hi
);
10939 def_builtin_const ("__builtin_vis_fsrl16", CODE_FOR_vlshrv4hi3
,
10940 SPARC_BUILTIN_FSRL16
, v4hi_ftype_v4hi_v4hi
);
10941 def_builtin_const ("__builtin_vis_fsra16", CODE_FOR_vashrv4hi3
,
10942 SPARC_BUILTIN_FSRA16
, v4hi_ftype_v4hi_v4hi
);
10943 def_builtin_const ("__builtin_vis_fsll32", CODE_FOR_vashlv2si3
,
10944 SPARC_BUILTIN_FSLL32
, v2si_ftype_v2si_v2si
);
10945 def_builtin_const ("__builtin_vis_fslas32", CODE_FOR_vssashlv2si3
,
10946 SPARC_BUILTIN_FSLAS32
, v2si_ftype_v2si_v2si
);
10947 def_builtin_const ("__builtin_vis_fsrl32", CODE_FOR_vlshrv2si3
,
10948 SPARC_BUILTIN_FSRL32
, v2si_ftype_v2si_v2si
);
10949 def_builtin_const ("__builtin_vis_fsra32", CODE_FOR_vashrv2si3
,
10950 SPARC_BUILTIN_FSRA32
, v2si_ftype_v2si_v2si
);
10953 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistndi_vis
,
10954 SPARC_BUILTIN_PDISTN
, di_ftype_v8qi_v8qi
);
10956 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistnsi_vis
,
10957 SPARC_BUILTIN_PDISTN
, si_ftype_v8qi_v8qi
);
10959 def_builtin_const ("__builtin_vis_fmean16", CODE_FOR_fmean16_vis
,
10960 SPARC_BUILTIN_FMEAN16
, v4hi_ftype_v4hi_v4hi
);
10961 def_builtin_const ("__builtin_vis_fpadd64", CODE_FOR_fpadd64_vis
,
10962 SPARC_BUILTIN_FPADD64
, di_ftype_di_di
);
10963 def_builtin_const ("__builtin_vis_fpsub64", CODE_FOR_fpsub64_vis
,
10964 SPARC_BUILTIN_FPSUB64
, di_ftype_di_di
);
10966 def_builtin_const ("__builtin_vis_fpadds16", CODE_FOR_ssaddv4hi3
,
10967 SPARC_BUILTIN_FPADDS16
, v4hi_ftype_v4hi_v4hi
);
10968 def_builtin_const ("__builtin_vis_fpadds16s", CODE_FOR_ssaddv2hi3
,
10969 SPARC_BUILTIN_FPADDS16S
, v2hi_ftype_v2hi_v2hi
);
10970 def_builtin_const ("__builtin_vis_fpsubs16", CODE_FOR_sssubv4hi3
,
10971 SPARC_BUILTIN_FPSUBS16
, v4hi_ftype_v4hi_v4hi
);
10972 def_builtin_const ("__builtin_vis_fpsubs16s", CODE_FOR_sssubv2hi3
,
10973 SPARC_BUILTIN_FPSUBS16S
, v2hi_ftype_v2hi_v2hi
);
10974 def_builtin_const ("__builtin_vis_fpadds32", CODE_FOR_ssaddv2si3
,
10975 SPARC_BUILTIN_FPADDS32
, v2si_ftype_v2si_v2si
);
10976 def_builtin_const ("__builtin_vis_fpadds32s", CODE_FOR_ssaddv1si3
,
10977 SPARC_BUILTIN_FPADDS32S
, v1si_ftype_v1si_v1si
);
10978 def_builtin_const ("__builtin_vis_fpsubs32", CODE_FOR_sssubv2si3
,
10979 SPARC_BUILTIN_FPSUBS32
, v2si_ftype_v2si_v2si
);
10980 def_builtin_const ("__builtin_vis_fpsubs32s", CODE_FOR_sssubv1si3
,
10981 SPARC_BUILTIN_FPSUBS32S
, v1si_ftype_v1si_v1si
);
10985 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8di_vis
,
10986 SPARC_BUILTIN_FUCMPLE8
, di_ftype_v8qi_v8qi
);
10987 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8di_vis
,
10988 SPARC_BUILTIN_FUCMPNE8
, di_ftype_v8qi_v8qi
);
10989 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8di_vis
,
10990 SPARC_BUILTIN_FUCMPGT8
, di_ftype_v8qi_v8qi
);
10991 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8di_vis
,
10992 SPARC_BUILTIN_FUCMPEQ8
, di_ftype_v8qi_v8qi
);
10996 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8si_vis
,
10997 SPARC_BUILTIN_FUCMPLE8
, si_ftype_v8qi_v8qi
);
10998 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8si_vis
,
10999 SPARC_BUILTIN_FUCMPNE8
, si_ftype_v8qi_v8qi
);
11000 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8si_vis
,
11001 SPARC_BUILTIN_FUCMPGT8
, si_ftype_v8qi_v8qi
);
11002 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8si_vis
,
11003 SPARC_BUILTIN_FUCMPEQ8
, si_ftype_v8qi_v8qi
);
11006 def_builtin_const ("__builtin_vis_fhadds", CODE_FOR_fhaddsf_vis
,
11007 SPARC_BUILTIN_FHADDS
, sf_ftype_sf_sf
);
11008 def_builtin_const ("__builtin_vis_fhaddd", CODE_FOR_fhadddf_vis
,
11009 SPARC_BUILTIN_FHADDD
, df_ftype_df_df
);
11010 def_builtin_const ("__builtin_vis_fhsubs", CODE_FOR_fhsubsf_vis
,
11011 SPARC_BUILTIN_FHSUBS
, sf_ftype_sf_sf
);
11012 def_builtin_const ("__builtin_vis_fhsubd", CODE_FOR_fhsubdf_vis
,
11013 SPARC_BUILTIN_FHSUBD
, df_ftype_df_df
);
11014 def_builtin_const ("__builtin_vis_fnhadds", CODE_FOR_fnhaddsf_vis
,
11015 SPARC_BUILTIN_FNHADDS
, sf_ftype_sf_sf
);
11016 def_builtin_const ("__builtin_vis_fnhaddd", CODE_FOR_fnhadddf_vis
,
11017 SPARC_BUILTIN_FNHADDD
, df_ftype_df_df
);
11019 def_builtin_const ("__builtin_vis_umulxhi", CODE_FOR_umulxhi_vis
,
11020 SPARC_BUILTIN_UMULXHI
, di_ftype_di_di
);
11021 def_builtin_const ("__builtin_vis_xmulx", CODE_FOR_xmulx_vis
,
11022 SPARC_BUILTIN_XMULX
, di_ftype_di_di
);
11023 def_builtin_const ("__builtin_vis_xmulxhi", CODE_FOR_xmulxhi_vis
,
11024 SPARC_BUILTIN_XMULXHI
, di_ftype_di_di
);
11029 def_builtin_const ("__builtin_vis_fpadd8", CODE_FOR_addv8qi3
,
11030 SPARC_BUILTIN_FPADD8
, v8qi_ftype_v8qi_v8qi
);
11031 def_builtin_const ("__builtin_vis_fpadds8", CODE_FOR_ssaddv8qi3
,
11032 SPARC_BUILTIN_FPADDS8
, v8qi_ftype_v8qi_v8qi
);
11033 def_builtin_const ("__builtin_vis_fpaddus8", CODE_FOR_usaddv8qi3
,
11034 SPARC_BUILTIN_FPADDUS8
, v8qi_ftype_v8qi_v8qi
);
11035 def_builtin_const ("__builtin_vis_fpaddus16", CODE_FOR_usaddv4hi3
,
11036 SPARC_BUILTIN_FPADDUS16
, v4hi_ftype_v4hi_v4hi
);
11041 def_builtin_const ("__builtin_vis_fpcmple8", CODE_FOR_fpcmple8di_vis
,
11042 SPARC_BUILTIN_FPCMPLE8
, di_ftype_v8qi_v8qi
);
11043 def_builtin_const ("__builtin_vis_fpcmpgt8", CODE_FOR_fpcmpgt8di_vis
,
11044 SPARC_BUILTIN_FPCMPGT8
, di_ftype_v8qi_v8qi
);
11045 def_builtin_const ("__builtin_vis_fpcmpule16", CODE_FOR_fpcmpule16di_vis
,
11046 SPARC_BUILTIN_FPCMPULE16
, di_ftype_v4hi_v4hi
);
11047 def_builtin_const ("__builtin_vis_fpcmpugt16", CODE_FOR_fpcmpugt16di_vis
,
11048 SPARC_BUILTIN_FPCMPUGT16
, di_ftype_v4hi_v4hi
);
11049 def_builtin_const ("__builtin_vis_fpcmpule32", CODE_FOR_fpcmpule32di_vis
,
11050 SPARC_BUILTIN_FPCMPULE32
, di_ftype_v2si_v2si
);
11051 def_builtin_const ("__builtin_vis_fpcmpugt32", CODE_FOR_fpcmpugt32di_vis
,
11052 SPARC_BUILTIN_FPCMPUGT32
, di_ftype_v2si_v2si
);
11056 def_builtin_const ("__builtin_vis_fpcmple8", CODE_FOR_fpcmple8si_vis
,
11057 SPARC_BUILTIN_FPCMPLE8
, si_ftype_v8qi_v8qi
);
11058 def_builtin_const ("__builtin_vis_fpcmpgt8", CODE_FOR_fpcmpgt8si_vis
,
11059 SPARC_BUILTIN_FPCMPGT8
, si_ftype_v8qi_v8qi
);
11060 def_builtin_const ("__builtin_vis_fpcmpule16", CODE_FOR_fpcmpule16si_vis
,
11061 SPARC_BUILTIN_FPCMPULE16
, si_ftype_v4hi_v4hi
);
11062 def_builtin_const ("__builtin_vis_fpcmpugt16", CODE_FOR_fpcmpugt16si_vis
,
11063 SPARC_BUILTIN_FPCMPUGT16
, si_ftype_v4hi_v4hi
);
11064 def_builtin_const ("__builtin_vis_fpcmpule32", CODE_FOR_fpcmpule32si_vis
,
11065 SPARC_BUILTIN_FPCMPULE32
, di_ftype_v2si_v2si
);
11066 def_builtin_const ("__builtin_vis_fpcmpugt32", CODE_FOR_fpcmpugt32si_vis
,
11067 SPARC_BUILTIN_FPCMPUGT32
, di_ftype_v2si_v2si
);
11070 def_builtin_const ("__builtin_vis_fpmax8", CODE_FOR_maxv8qi3
,
11071 SPARC_BUILTIN_FPMAX8
, v8qi_ftype_v8qi_v8qi
);
11072 def_builtin_const ("__builtin_vis_fpmax16", CODE_FOR_maxv4hi3
,
11073 SPARC_BUILTIN_FPMAX16
, v4hi_ftype_v4hi_v4hi
);
11074 def_builtin_const ("__builtin_vis_fpmax32", CODE_FOR_maxv2si3
,
11075 SPARC_BUILTIN_FPMAX32
, v2si_ftype_v2si_v2si
);
11076 def_builtin_const ("__builtin_vis_fpmaxu8", CODE_FOR_maxuv8qi3
,
11077 SPARC_BUILTIN_FPMAXU8
, v8qi_ftype_v8qi_v8qi
);
11078 def_builtin_const ("__builtin_vis_fpmaxu16", CODE_FOR_maxuv4hi3
,
11079 SPARC_BUILTIN_FPMAXU16
, v4hi_ftype_v4hi_v4hi
);
11080 def_builtin_const ("__builtin_vis_fpmaxu32", CODE_FOR_maxuv2si3
,
11081 SPARC_BUILTIN_FPMAXU32
, v2si_ftype_v2si_v2si
);
11082 def_builtin_const ("__builtin_vis_fpmin8", CODE_FOR_minv8qi3
,
11083 SPARC_BUILTIN_FPMIN8
, v8qi_ftype_v8qi_v8qi
);
11084 def_builtin_const ("__builtin_vis_fpmin16", CODE_FOR_minv4hi3
,
11085 SPARC_BUILTIN_FPMIN16
, v4hi_ftype_v4hi_v4hi
);
11086 def_builtin_const ("__builtin_vis_fpmin32", CODE_FOR_minv2si3
,
11087 SPARC_BUILTIN_FPMIN32
, v2si_ftype_v2si_v2si
);
11088 def_builtin_const ("__builtin_vis_fpminu8", CODE_FOR_minuv8qi3
,
11089 SPARC_BUILTIN_FPMINU8
, v8qi_ftype_v8qi_v8qi
);
11090 def_builtin_const ("__builtin_vis_fpminu16", CODE_FOR_minuv4hi3
,
11091 SPARC_BUILTIN_FPMINU16
, v4hi_ftype_v4hi_v4hi
);
11092 def_builtin_const ("__builtin_vis_fpminu32", CODE_FOR_minuv2si3
,
11093 SPARC_BUILTIN_FPMINU32
, v2si_ftype_v2si_v2si
);
11094 def_builtin_const ("__builtin_vis_fpsub8", CODE_FOR_subv8qi3
,
11095 SPARC_BUILTIN_FPSUB8
, v8qi_ftype_v8qi_v8qi
);
11096 def_builtin_const ("__builtin_vis_fpsubs8", CODE_FOR_sssubv8qi3
,
11097 SPARC_BUILTIN_FPSUBS8
, v8qi_ftype_v8qi_v8qi
);
11098 def_builtin_const ("__builtin_vis_fpsubus8", CODE_FOR_ussubv8qi3
,
11099 SPARC_BUILTIN_FPSUBUS8
, v8qi_ftype_v8qi_v8qi
);
11100 def_builtin_const ("__builtin_vis_fpsubus16", CODE_FOR_ussubv4hi3
,
11101 SPARC_BUILTIN_FPSUBUS16
, v4hi_ftype_v4hi_v4hi
);
11106 def_builtin_const ("__builtin_vis_dictunpack8", CODE_FOR_dictunpack8
,
11107 SPARC_BUILTIN_DICTUNPACK8
, v8qi_ftype_df_si
);
11108 def_builtin_const ("__builtin_vis_dictunpack16", CODE_FOR_dictunpack16
,
11109 SPARC_BUILTIN_DICTUNPACK16
, v4hi_ftype_df_si
);
11110 def_builtin_const ("__builtin_vis_dictunpack32", CODE_FOR_dictunpack32
,
11111 SPARC_BUILTIN_DICTUNPACK32
, v2si_ftype_df_si
);
11115 tree di_ftype_v8qi_v8qi_si
= build_function_type_list (intDI_type_node
,
11117 intSI_type_node
, 0);
11118 tree di_ftype_v4hi_v4hi_si
= build_function_type_list (intDI_type_node
,
11120 intSI_type_node
, 0);
11121 tree di_ftype_v2si_v2si_si
= build_function_type_list (intDI_type_node
,
11123 intSI_type_node
, 0);
11125 def_builtin_const ("__builtin_vis_fpcmple8shl", CODE_FOR_fpcmple8dishl
,
11126 SPARC_BUILTIN_FPCMPLE8SHL
, di_ftype_v8qi_v8qi_si
);
11127 def_builtin_const ("__builtin_vis_fpcmpgt8shl", CODE_FOR_fpcmpgt8dishl
,
11128 SPARC_BUILTIN_FPCMPGT8SHL
, di_ftype_v8qi_v8qi_si
);
11129 def_builtin_const ("__builtin_vis_fpcmpeq8shl", CODE_FOR_fpcmpeq8dishl
,
11130 SPARC_BUILTIN_FPCMPEQ8SHL
, di_ftype_v8qi_v8qi_si
);
11131 def_builtin_const ("__builtin_vis_fpcmpne8shl", CODE_FOR_fpcmpne8dishl
,
11132 SPARC_BUILTIN_FPCMPNE8SHL
, di_ftype_v8qi_v8qi_si
);
11134 def_builtin_const ("__builtin_vis_fpcmple16shl", CODE_FOR_fpcmple16dishl
,
11135 SPARC_BUILTIN_FPCMPLE16SHL
, di_ftype_v4hi_v4hi_si
);
11136 def_builtin_const ("__builtin_vis_fpcmpgt16shl", CODE_FOR_fpcmpgt16dishl
,
11137 SPARC_BUILTIN_FPCMPGT16SHL
, di_ftype_v4hi_v4hi_si
);
11138 def_builtin_const ("__builtin_vis_fpcmpeq16shl", CODE_FOR_fpcmpeq16dishl
,
11139 SPARC_BUILTIN_FPCMPEQ16SHL
, di_ftype_v4hi_v4hi_si
);
11140 def_builtin_const ("__builtin_vis_fpcmpne16shl", CODE_FOR_fpcmpne16dishl
,
11141 SPARC_BUILTIN_FPCMPNE16SHL
, di_ftype_v4hi_v4hi_si
);
11143 def_builtin_const ("__builtin_vis_fpcmple32shl", CODE_FOR_fpcmple32dishl
,
11144 SPARC_BUILTIN_FPCMPLE32SHL
, di_ftype_v2si_v2si_si
);
11145 def_builtin_const ("__builtin_vis_fpcmpgt32shl", CODE_FOR_fpcmpgt32dishl
,
11146 SPARC_BUILTIN_FPCMPGT32SHL
, di_ftype_v2si_v2si_si
);
11147 def_builtin_const ("__builtin_vis_fpcmpeq32shl", CODE_FOR_fpcmpeq32dishl
,
11148 SPARC_BUILTIN_FPCMPEQ32SHL
, di_ftype_v2si_v2si_si
);
11149 def_builtin_const ("__builtin_vis_fpcmpne32shl", CODE_FOR_fpcmpne32dishl
,
11150 SPARC_BUILTIN_FPCMPNE32SHL
, di_ftype_v2si_v2si_si
);
11153 def_builtin_const ("__builtin_vis_fpcmpule8shl", CODE_FOR_fpcmpule8dishl
,
11154 SPARC_BUILTIN_FPCMPULE8SHL
, di_ftype_v8qi_v8qi_si
);
11155 def_builtin_const ("__builtin_vis_fpcmpugt8shl", CODE_FOR_fpcmpugt8dishl
,
11156 SPARC_BUILTIN_FPCMPUGT8SHL
, di_ftype_v8qi_v8qi_si
);
11158 def_builtin_const ("__builtin_vis_fpcmpule16shl", CODE_FOR_fpcmpule16dishl
,
11159 SPARC_BUILTIN_FPCMPULE16SHL
, di_ftype_v4hi_v4hi_si
);
11160 def_builtin_const ("__builtin_vis_fpcmpugt16shl", CODE_FOR_fpcmpugt16dishl
,
11161 SPARC_BUILTIN_FPCMPUGT16SHL
, di_ftype_v4hi_v4hi_si
);
11163 def_builtin_const ("__builtin_vis_fpcmpule32shl", CODE_FOR_fpcmpule32dishl
,
11164 SPARC_BUILTIN_FPCMPULE32SHL
, di_ftype_v2si_v2si_si
);
11165 def_builtin_const ("__builtin_vis_fpcmpugt32shl", CODE_FOR_fpcmpugt32dishl
,
11166 SPARC_BUILTIN_FPCMPUGT32SHL
, di_ftype_v2si_v2si_si
);
11168 def_builtin_const ("__builtin_vis_fpcmpde8shl", CODE_FOR_fpcmpde8dishl
,
11169 SPARC_BUILTIN_FPCMPDE8SHL
, di_ftype_v8qi_v8qi_si
);
11170 def_builtin_const ("__builtin_vis_fpcmpde16shl", CODE_FOR_fpcmpde16dishl
,
11171 SPARC_BUILTIN_FPCMPDE16SHL
, di_ftype_v4hi_v4hi_si
);
11172 def_builtin_const ("__builtin_vis_fpcmpde32shl", CODE_FOR_fpcmpde32dishl
,
11173 SPARC_BUILTIN_FPCMPDE32SHL
, di_ftype_v2si_v2si_si
);
11175 def_builtin_const ("__builtin_vis_fpcmpur8shl", CODE_FOR_fpcmpur8dishl
,
11176 SPARC_BUILTIN_FPCMPUR8SHL
, di_ftype_v8qi_v8qi_si
);
11177 def_builtin_const ("__builtin_vis_fpcmpur16shl", CODE_FOR_fpcmpur16dishl
,
11178 SPARC_BUILTIN_FPCMPUR16SHL
, di_ftype_v4hi_v4hi_si
);
11179 def_builtin_const ("__builtin_vis_fpcmpur32shl", CODE_FOR_fpcmpur32dishl
,
11180 SPARC_BUILTIN_FPCMPUR32SHL
, di_ftype_v2si_v2si_si
);
11185 tree si_ftype_v8qi_v8qi_si
= build_function_type_list (intSI_type_node
,
11187 intSI_type_node
, 0);
11188 tree si_ftype_v4hi_v4hi_si
= build_function_type_list (intSI_type_node
,
11190 intSI_type_node
, 0);
11191 tree si_ftype_v2si_v2si_si
= build_function_type_list (intSI_type_node
,
11193 intSI_type_node
, 0);
11195 def_builtin_const ("__builtin_vis_fpcmple8shl", CODE_FOR_fpcmple8sishl
,
11196 SPARC_BUILTIN_FPCMPLE8SHL
, si_ftype_v8qi_v8qi_si
);
11197 def_builtin_const ("__builtin_vis_fpcmpgt8shl", CODE_FOR_fpcmpgt8sishl
,
11198 SPARC_BUILTIN_FPCMPGT8SHL
, si_ftype_v8qi_v8qi_si
);
11199 def_builtin_const ("__builtin_vis_fpcmpeq8shl", CODE_FOR_fpcmpeq8sishl
,
11200 SPARC_BUILTIN_FPCMPEQ8SHL
, si_ftype_v8qi_v8qi_si
);
11201 def_builtin_const ("__builtin_vis_fpcmpne8shl", CODE_FOR_fpcmpne8sishl
,
11202 SPARC_BUILTIN_FPCMPNE8SHL
, si_ftype_v8qi_v8qi_si
);
11204 def_builtin_const ("__builtin_vis_fpcmple16shl", CODE_FOR_fpcmple16sishl
,
11205 SPARC_BUILTIN_FPCMPLE16SHL
, si_ftype_v4hi_v4hi_si
);
11206 def_builtin_const ("__builtin_vis_fpcmpgt16shl", CODE_FOR_fpcmpgt16sishl
,
11207 SPARC_BUILTIN_FPCMPGT16SHL
, si_ftype_v4hi_v4hi_si
);
11208 def_builtin_const ("__builtin_vis_fpcmpeq16shl", CODE_FOR_fpcmpeq16sishl
,
11209 SPARC_BUILTIN_FPCMPEQ16SHL
, si_ftype_v4hi_v4hi_si
);
11210 def_builtin_const ("__builtin_vis_fpcmpne16shl", CODE_FOR_fpcmpne16sishl
,
11211 SPARC_BUILTIN_FPCMPNE16SHL
, si_ftype_v4hi_v4hi_si
);
11213 def_builtin_const ("__builtin_vis_fpcmple32shl", CODE_FOR_fpcmple32sishl
,
11214 SPARC_BUILTIN_FPCMPLE32SHL
, si_ftype_v2si_v2si_si
);
11215 def_builtin_const ("__builtin_vis_fpcmpgt32shl", CODE_FOR_fpcmpgt32sishl
,
11216 SPARC_BUILTIN_FPCMPGT32SHL
, si_ftype_v2si_v2si_si
);
11217 def_builtin_const ("__builtin_vis_fpcmpeq32shl", CODE_FOR_fpcmpeq32sishl
,
11218 SPARC_BUILTIN_FPCMPEQ32SHL
, si_ftype_v2si_v2si_si
);
11219 def_builtin_const ("__builtin_vis_fpcmpne32shl", CODE_FOR_fpcmpne32sishl
,
11220 SPARC_BUILTIN_FPCMPNE32SHL
, si_ftype_v2si_v2si_si
);
11223 def_builtin_const ("__builtin_vis_fpcmpule8shl", CODE_FOR_fpcmpule8sishl
,
11224 SPARC_BUILTIN_FPCMPULE8SHL
, si_ftype_v8qi_v8qi_si
);
11225 def_builtin_const ("__builtin_vis_fpcmpugt8shl", CODE_FOR_fpcmpugt8sishl
,
11226 SPARC_BUILTIN_FPCMPUGT8SHL
, si_ftype_v8qi_v8qi_si
);
11228 def_builtin_const ("__builtin_vis_fpcmpule16shl", CODE_FOR_fpcmpule16sishl
,
11229 SPARC_BUILTIN_FPCMPULE16SHL
, si_ftype_v4hi_v4hi_si
);
11230 def_builtin_const ("__builtin_vis_fpcmpugt16shl", CODE_FOR_fpcmpugt16sishl
,
11231 SPARC_BUILTIN_FPCMPUGT16SHL
, si_ftype_v4hi_v4hi_si
);
11233 def_builtin_const ("__builtin_vis_fpcmpule32shl", CODE_FOR_fpcmpule32sishl
,
11234 SPARC_BUILTIN_FPCMPULE32SHL
, si_ftype_v2si_v2si_si
);
11235 def_builtin_const ("__builtin_vis_fpcmpugt32shl", CODE_FOR_fpcmpugt32sishl
,
11236 SPARC_BUILTIN_FPCMPUGT32SHL
, si_ftype_v2si_v2si_si
);
11238 def_builtin_const ("__builtin_vis_fpcmpde8shl", CODE_FOR_fpcmpde8sishl
,
11239 SPARC_BUILTIN_FPCMPDE8SHL
, si_ftype_v8qi_v8qi_si
);
11240 def_builtin_const ("__builtin_vis_fpcmpde16shl", CODE_FOR_fpcmpde16sishl
,
11241 SPARC_BUILTIN_FPCMPDE16SHL
, si_ftype_v4hi_v4hi_si
);
11242 def_builtin_const ("__builtin_vis_fpcmpde32shl", CODE_FOR_fpcmpde32sishl
,
11243 SPARC_BUILTIN_FPCMPDE32SHL
, si_ftype_v2si_v2si_si
);
11245 def_builtin_const ("__builtin_vis_fpcmpur8shl", CODE_FOR_fpcmpur8sishl
,
11246 SPARC_BUILTIN_FPCMPUR8SHL
, si_ftype_v8qi_v8qi_si
);
11247 def_builtin_const ("__builtin_vis_fpcmpur16shl", CODE_FOR_fpcmpur16sishl
,
11248 SPARC_BUILTIN_FPCMPUR16SHL
, si_ftype_v4hi_v4hi_si
);
11249 def_builtin_const ("__builtin_vis_fpcmpur32shl", CODE_FOR_fpcmpur32sishl
,
11250 SPARC_BUILTIN_FPCMPUR32SHL
, si_ftype_v2si_v2si_si
);
11255 /* Implement TARGET_BUILTIN_DECL hook. */
11258 sparc_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
11260 if (code
>= SPARC_BUILTIN_MAX
)
11261 return error_mark_node
;
11263 return sparc_builtins
[code
];
11266 /* Implemented TARGET_EXPAND_BUILTIN hook. */
11269 sparc_expand_builtin (tree exp
, rtx target
,
11270 rtx subtarget ATTRIBUTE_UNUSED
,
11271 machine_mode tmode ATTRIBUTE_UNUSED
,
11272 int ignore ATTRIBUTE_UNUSED
)
11274 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
11275 enum sparc_builtins code
= (enum sparc_builtins
) DECL_FUNCTION_CODE (fndecl
);
11276 enum insn_code icode
= sparc_builtins_icode
[code
];
11277 bool nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
11278 call_expr_arg_iterator iter
;
11285 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11287 || GET_MODE (target
) != tmode
11288 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11289 op
[0] = gen_reg_rtx (tmode
);
11294 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
11296 const struct insn_operand_data
*insn_op
;
11299 if (arg
== error_mark_node
)
11303 idx
= arg_count
- !nonvoid
;
11304 insn_op
= &insn_data
[icode
].operand
[idx
];
11305 op
[arg_count
] = expand_normal (arg
);
11307 /* Some of the builtins require constant arguments. We check
11309 if ((code
>= SPARC_BUILTIN_FIRST_FPCMPSHL
11310 && code
<= SPARC_BUILTIN_LAST_FPCMPSHL
11312 || (code
>= SPARC_BUILTIN_FIRST_DICTUNPACK
11313 && code
<= SPARC_BUILTIN_LAST_DICTUNPACK
11314 && arg_count
== 2))
11316 if (!check_constant_argument (icode
, idx
, op
[arg_count
]))
11320 if (code
== SPARC_BUILTIN_LDFSR
|| code
== SPARC_BUILTIN_STFSR
)
11322 if (!address_operand (op
[arg_count
], SImode
))
11324 op
[arg_count
] = convert_memory_address (Pmode
, op
[arg_count
]);
11325 op
[arg_count
] = copy_addr_to_reg (op
[arg_count
]);
11327 op
[arg_count
] = gen_rtx_MEM (SImode
, op
[arg_count
]);
11330 else if (insn_op
->mode
== V1DImode
11331 && GET_MODE (op
[arg_count
]) == DImode
)
11332 op
[arg_count
] = gen_lowpart (V1DImode
, op
[arg_count
]);
11334 else if (insn_op
->mode
== V1SImode
11335 && GET_MODE (op
[arg_count
]) == SImode
)
11336 op
[arg_count
] = gen_lowpart (V1SImode
, op
[arg_count
]);
11338 if (! (*insn_data
[icode
].operand
[idx
].predicate
) (op
[arg_count
],
11340 op
[arg_count
] = copy_to_mode_reg (insn_op
->mode
, op
[arg_count
]);
11346 pat
= GEN_FCN (icode
) (op
[0]);
11350 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
11352 pat
= GEN_FCN (icode
) (op
[1]);
11355 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
11358 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
11361 gcc_unreachable ();
11369 return (nonvoid
? op
[0] : const0_rtx
);
11372 /* Return the upper 16 bits of the 8x16 multiplication. */
11375 sparc_vis_mul8x16 (int e8
, int e16
)
11377 return (e8
* e16
+ 128) / 256;
11380 /* Multiply the VECTOR_CSTs CST0 and CST1 as specified by FNCODE and put
11381 the result into the array N_ELTS, whose elements are of INNER_TYPE. */
11384 sparc_handle_vis_mul8x16 (tree
*n_elts
, enum sparc_builtins fncode
,
11385 tree inner_type
, tree cst0
, tree cst1
)
11387 unsigned i
, num
= VECTOR_CST_NELTS (cst0
);
11392 case SPARC_BUILTIN_FMUL8X16
:
11393 for (i
= 0; i
< num
; ++i
)
11396 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
11397 TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, i
)));
11398 n_elts
[i
] = build_int_cst (inner_type
, val
);
11402 case SPARC_BUILTIN_FMUL8X16AU
:
11403 scale
= TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, 0));
11405 for (i
= 0; i
< num
; ++i
)
11408 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
11410 n_elts
[i
] = build_int_cst (inner_type
, val
);
11414 case SPARC_BUILTIN_FMUL8X16AL
:
11415 scale
= TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, 1));
11417 for (i
= 0; i
< num
; ++i
)
11420 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
11422 n_elts
[i
] = build_int_cst (inner_type
, val
);
11427 gcc_unreachable ();
11431 /* Implement TARGET_FOLD_BUILTIN hook.
11433 Fold builtin functions for SPARC intrinsics. If IGNORE is true the
11434 result of the function call is ignored. NULL_TREE is returned if the
11435 function could not be folded. */
11438 sparc_fold_builtin (tree fndecl
, int n_args ATTRIBUTE_UNUSED
,
11439 tree
*args
, bool ignore
)
11441 enum sparc_builtins code
= (enum sparc_builtins
) DECL_FUNCTION_CODE (fndecl
);
11442 tree rtype
= TREE_TYPE (TREE_TYPE (fndecl
));
11443 tree arg0
, arg1
, arg2
;
11448 case SPARC_BUILTIN_LDFSR
:
11449 case SPARC_BUILTIN_STFSR
:
11450 case SPARC_BUILTIN_ALIGNADDR
:
11451 case SPARC_BUILTIN_WRGSR
:
11452 case SPARC_BUILTIN_BMASK
:
11453 case SPARC_BUILTIN_CMASK8
:
11454 case SPARC_BUILTIN_CMASK16
:
11455 case SPARC_BUILTIN_CMASK32
:
11459 return build_zero_cst (rtype
);
11464 case SPARC_BUILTIN_FEXPAND
:
11468 if (TREE_CODE (arg0
) == VECTOR_CST
)
11470 tree inner_type
= TREE_TYPE (rtype
);
11474 n_elts
= XALLOCAVEC (tree
, VECTOR_CST_NELTS (arg0
));
11475 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
11476 n_elts
[i
] = build_int_cst (inner_type
,
11478 (VECTOR_CST_ELT (arg0
, i
)) << 4);
11479 return build_vector (rtype
, n_elts
);
11483 case SPARC_BUILTIN_FMUL8X16
:
11484 case SPARC_BUILTIN_FMUL8X16AU
:
11485 case SPARC_BUILTIN_FMUL8X16AL
:
11491 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
11493 tree inner_type
= TREE_TYPE (rtype
);
11494 tree
*n_elts
= XALLOCAVEC (tree
, VECTOR_CST_NELTS (arg0
));
11495 sparc_handle_vis_mul8x16 (n_elts
, code
, inner_type
, arg0
, arg1
);
11496 return build_vector (rtype
, n_elts
);
11500 case SPARC_BUILTIN_FPMERGE
:
11506 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
11508 tree
*n_elts
= XALLOCAVEC (tree
, 2 * VECTOR_CST_NELTS (arg0
));
11510 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
11512 n_elts
[2*i
] = VECTOR_CST_ELT (arg0
, i
);
11513 n_elts
[2*i
+1] = VECTOR_CST_ELT (arg1
, i
);
11516 return build_vector (rtype
, n_elts
);
11520 case SPARC_BUILTIN_PDIST
:
11521 case SPARC_BUILTIN_PDISTN
:
11526 if (code
== SPARC_BUILTIN_PDIST
)
11532 arg2
= integer_zero_node
;
11534 if (TREE_CODE (arg0
) == VECTOR_CST
11535 && TREE_CODE (arg1
) == VECTOR_CST
11536 && TREE_CODE (arg2
) == INTEGER_CST
)
11538 bool overflow
= false;
11539 widest_int result
= wi::to_widest (arg2
);
11543 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
11545 tree e0
= VECTOR_CST_ELT (arg0
, i
);
11546 tree e1
= VECTOR_CST_ELT (arg1
, i
);
11548 bool neg1_ovf
, neg2_ovf
, add1_ovf
, add2_ovf
;
11550 tmp
= wi::neg (wi::to_widest (e1
), &neg1_ovf
);
11551 tmp
= wi::add (wi::to_widest (e0
), tmp
, SIGNED
, &add1_ovf
);
11552 if (wi::neg_p (tmp
))
11553 tmp
= wi::neg (tmp
, &neg2_ovf
);
11556 result
= wi::add (result
, tmp
, SIGNED
, &add2_ovf
);
11557 overflow
|= neg1_ovf
| neg2_ovf
| add1_ovf
| add2_ovf
;
11560 gcc_assert (!overflow
);
11562 return wide_int_to_tree (rtype
, result
);
11572 /* ??? This duplicates information provided to the compiler by the
11573 ??? scheduler description. Some day, teach genautomata to output
11574 ??? the latencies and then CSE will just use that. */
11577 sparc_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
11578 int opno ATTRIBUTE_UNUSED
,
11579 int *total
, bool speed ATTRIBUTE_UNUSED
)
11581 int code
= GET_CODE (x
);
11582 bool float_mode_p
= FLOAT_MODE_P (mode
);
11593 case CONST_WIDE_INT
:
11595 if (!SPARC_SIMM13_P (CONST_WIDE_INT_ELT (x
, 0)))
11597 if (!SPARC_SIMM13_P (CONST_WIDE_INT_ELT (x
, 1)))
11616 /* If outer-code was a sign or zero extension, a cost
11617 of COSTS_N_INSNS (1) was already added in. This is
11618 why we are subtracting it back out. */
11619 if (outer_code
== ZERO_EXTEND
)
11621 *total
= sparc_costs
->int_zload
- COSTS_N_INSNS (1);
11623 else if (outer_code
== SIGN_EXTEND
)
11625 *total
= sparc_costs
->int_sload
- COSTS_N_INSNS (1);
11627 else if (float_mode_p
)
11629 *total
= sparc_costs
->float_load
;
11633 *total
= sparc_costs
->int_load
;
11641 *total
= sparc_costs
->float_plusminus
;
11643 *total
= COSTS_N_INSNS (1);
11650 gcc_assert (float_mode_p
);
11651 *total
= sparc_costs
->float_mul
;
11654 if (GET_CODE (sub
) == NEG
)
11655 sub
= XEXP (sub
, 0);
11656 *total
+= rtx_cost (sub
, mode
, FMA
, 0, speed
);
11659 if (GET_CODE (sub
) == NEG
)
11660 sub
= XEXP (sub
, 0);
11661 *total
+= rtx_cost (sub
, mode
, FMA
, 2, speed
);
11667 *total
= sparc_costs
->float_mul
;
11668 else if (TARGET_ARCH32
&& !TARGET_HARD_MUL
)
11669 *total
= COSTS_N_INSNS (25);
11675 if (sparc_costs
->int_mul_bit_factor
)
11679 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
11681 unsigned HOST_WIDE_INT value
= INTVAL (XEXP (x
, 1));
11682 for (nbits
= 0; value
!= 0; value
&= value
- 1)
11690 bit_cost
= (nbits
- 3) / sparc_costs
->int_mul_bit_factor
;
11691 bit_cost
= COSTS_N_INSNS (bit_cost
);
11694 if (mode
== DImode
|| !TARGET_HARD_MUL
)
11695 *total
= sparc_costs
->int_mulX
+ bit_cost
;
11697 *total
= sparc_costs
->int_mul
+ bit_cost
;
11704 *total
= COSTS_N_INSNS (1) + sparc_costs
->shift_penalty
;
11713 if (mode
== DFmode
)
11714 *total
= sparc_costs
->float_div_df
;
11716 *total
= sparc_costs
->float_div_sf
;
11720 if (mode
== DImode
)
11721 *total
= sparc_costs
->int_divX
;
11723 *total
= sparc_costs
->int_div
;
11728 if (! float_mode_p
)
11730 *total
= COSTS_N_INSNS (1);
11737 case UNSIGNED_FLOAT
:
11741 case FLOAT_TRUNCATE
:
11742 *total
= sparc_costs
->float_move
;
11746 if (mode
== DFmode
)
11747 *total
= sparc_costs
->float_sqrt_df
;
11749 *total
= sparc_costs
->float_sqrt_sf
;
11754 *total
= sparc_costs
->float_cmp
;
11756 *total
= COSTS_N_INSNS (1);
11761 *total
= sparc_costs
->float_cmove
;
11763 *total
= sparc_costs
->int_cmove
;
11767 /* Handle the NAND vector patterns. */
11768 if (sparc_vector_mode_supported_p (mode
)
11769 && GET_CODE (XEXP (x
, 0)) == NOT
11770 && GET_CODE (XEXP (x
, 1)) == NOT
)
11772 *total
= COSTS_N_INSNS (1);
11783 /* Return true if CLASS is either GENERAL_REGS or I64_REGS. */
11786 general_or_i64_p (reg_class_t rclass
)
11788 return (rclass
== GENERAL_REGS
|| rclass
== I64_REGS
);
11791 /* Implement TARGET_REGISTER_MOVE_COST. */
11794 sparc_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
11795 reg_class_t from
, reg_class_t to
)
11797 bool need_memory
= false;
11799 /* This helps postreload CSE to eliminate redundant comparisons. */
11800 if (from
== NO_REGS
|| to
== NO_REGS
)
11803 if (from
== FPCC_REGS
|| to
== FPCC_REGS
)
11804 need_memory
= true;
11805 else if ((FP_REG_CLASS_P (from
) && general_or_i64_p (to
))
11806 || (general_or_i64_p (from
) && FP_REG_CLASS_P (to
)))
11810 int size
= GET_MODE_SIZE (mode
);
11811 if (size
== 8 || size
== 4)
11813 if (! TARGET_ARCH32
|| size
== 4)
11819 need_memory
= true;
11824 if (sparc_cpu
== PROCESSOR_ULTRASPARC
11825 || sparc_cpu
== PROCESSOR_ULTRASPARC3
11826 || sparc_cpu
== PROCESSOR_NIAGARA
11827 || sparc_cpu
== PROCESSOR_NIAGARA2
11828 || sparc_cpu
== PROCESSOR_NIAGARA3
11829 || sparc_cpu
== PROCESSOR_NIAGARA4
11830 || sparc_cpu
== PROCESSOR_NIAGARA7
11831 || sparc_cpu
== PROCESSOR_M8
)
11840 /* Emit the sequence of insns SEQ while preserving the registers REG and REG2.
11841 This is achieved by means of a manual dynamic stack space allocation in
11842 the current frame. We make the assumption that SEQ doesn't contain any
11843 function calls, with the possible exception of calls to the GOT helper. */
11846 emit_and_preserve (rtx seq
, rtx reg
, rtx reg2
)
11848 /* We must preserve the lowest 16 words for the register save area. */
11849 HOST_WIDE_INT offset
= 16*UNITS_PER_WORD
;
11850 /* We really need only 2 words of fresh stack space. */
11851 HOST_WIDE_INT size
= SPARC_STACK_ALIGN (offset
+ 2*UNITS_PER_WORD
);
11854 = gen_rtx_MEM (word_mode
, plus_constant (Pmode
, stack_pointer_rtx
,
11855 SPARC_STACK_BIAS
+ offset
));
11857 emit_insn (gen_stack_pointer_inc (GEN_INT (-size
)));
11858 emit_insn (gen_rtx_SET (slot
, reg
));
11860 emit_insn (gen_rtx_SET (adjust_address (slot
, word_mode
, UNITS_PER_WORD
),
11864 emit_insn (gen_rtx_SET (reg2
,
11865 adjust_address (slot
, word_mode
, UNITS_PER_WORD
)));
11866 emit_insn (gen_rtx_SET (reg
, slot
));
11867 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
11870 /* Output the assembler code for a thunk function. THUNK_DECL is the
11871 declaration for the thunk function itself, FUNCTION is the decl for
11872 the target function. DELTA is an immediate constant offset to be
11873 added to THIS. If VCALL_OFFSET is nonzero, the word at address
11874 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
11877 sparc_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
11878 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
11881 rtx this_rtx
, funexp
;
11883 unsigned int int_arg_first
;
11885 reload_completed
= 1;
11886 epilogue_completed
= 1;
11888 emit_note (NOTE_INSN_PROLOGUE_END
);
11892 sparc_leaf_function_p
= 1;
11894 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
11896 else if (flag_delayed_branch
)
11898 /* We will emit a regular sibcall below, so we need to instruct
11899 output_sibcall that we are in a leaf function. */
11900 sparc_leaf_function_p
= crtl
->uses_only_leaf_regs
= 1;
11902 /* This will cause final.c to invoke leaf_renumber_regs so we
11903 must behave as if we were in a not-yet-leafified function. */
11904 int_arg_first
= SPARC_INCOMING_INT_ARG_FIRST
;
11908 /* We will emit the sibcall manually below, so we will need to
11909 manually spill non-leaf registers. */
11910 sparc_leaf_function_p
= crtl
->uses_only_leaf_regs
= 0;
11912 /* We really are in a leaf function. */
11913 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
11916 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
11917 returns a structure, the structure return pointer is there instead. */
11919 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
11920 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
+ 1);
11922 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
);
11924 /* Add DELTA. When possible use a plain add, otherwise load it into
11925 a register first. */
11928 rtx delta_rtx
= GEN_INT (delta
);
11930 if (! SPARC_SIMM13_P (delta
))
11932 rtx scratch
= gen_rtx_REG (Pmode
, 1);
11933 emit_move_insn (scratch
, delta_rtx
);
11934 delta_rtx
= scratch
;
11937 /* THIS_RTX += DELTA. */
11938 emit_insn (gen_add2_insn (this_rtx
, delta_rtx
));
11941 /* Add the word at address (*THIS_RTX + VCALL_OFFSET). */
11944 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
11945 rtx scratch
= gen_rtx_REG (Pmode
, 1);
11947 gcc_assert (vcall_offset
< 0);
11949 /* SCRATCH = *THIS_RTX. */
11950 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
, this_rtx
));
11952 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
11953 may not have any available scratch register at this point. */
11954 if (SPARC_SIMM13_P (vcall_offset
))
11956 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
11957 else if (! fixed_regs
[5]
11958 /* The below sequence is made up of at least 2 insns,
11959 while the default method may need only one. */
11960 && vcall_offset
< -8192)
11962 rtx scratch2
= gen_rtx_REG (Pmode
, 5);
11963 emit_move_insn (scratch2
, vcall_offset_rtx
);
11964 vcall_offset_rtx
= scratch2
;
11968 rtx increment
= GEN_INT (-4096);
11970 /* VCALL_OFFSET is a negative number whose typical range can be
11971 estimated as -32768..0 in 32-bit mode. In almost all cases
11972 it is therefore cheaper to emit multiple add insns than
11973 spilling and loading the constant into a register (at least
11975 while (! SPARC_SIMM13_P (vcall_offset
))
11977 emit_insn (gen_add2_insn (scratch
, increment
));
11978 vcall_offset
+= 4096;
11980 vcall_offset_rtx
= GEN_INT (vcall_offset
); /* cannot be 0 */
11983 /* SCRATCH = *(*THIS_RTX + VCALL_OFFSET). */
11984 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
,
11985 gen_rtx_PLUS (Pmode
,
11987 vcall_offset_rtx
)));
11989 /* THIS_RTX += *(*THIS_RTX + VCALL_OFFSET). */
11990 emit_insn (gen_add2_insn (this_rtx
, scratch
));
11993 /* Generate a tail call to the target function. */
11994 if (! TREE_USED (function
))
11996 assemble_external (function
);
11997 TREE_USED (function
) = 1;
11999 funexp
= XEXP (DECL_RTL (function
), 0);
12001 if (flag_delayed_branch
)
12003 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
12004 insn
= emit_call_insn (gen_sibcall (funexp
));
12005 SIBLING_CALL_P (insn
) = 1;
12009 /* The hoops we have to jump through in order to generate a sibcall
12010 without using delay slots... */
12011 rtx spill_reg
, seq
, scratch
= gen_rtx_REG (Pmode
, 1);
12015 spill_reg
= gen_rtx_REG (word_mode
, 15); /* %o7 */
12017 load_got_register (); /* clobbers %o7 */
12018 scratch
= sparc_legitimize_pic_address (funexp
, scratch
);
12019 seq
= get_insns ();
12021 emit_and_preserve (seq
, spill_reg
, pic_offset_table_rtx
);
12023 else if (TARGET_ARCH32
)
12025 emit_insn (gen_rtx_SET (scratch
,
12026 gen_rtx_HIGH (SImode
, funexp
)));
12027 emit_insn (gen_rtx_SET (scratch
,
12028 gen_rtx_LO_SUM (SImode
, scratch
, funexp
)));
12030 else /* TARGET_ARCH64 */
12032 switch (sparc_cmodel
)
12036 /* The destination can serve as a temporary. */
12037 sparc_emit_set_symbolic_const64 (scratch
, funexp
, scratch
);
12042 /* The destination cannot serve as a temporary. */
12043 spill_reg
= gen_rtx_REG (DImode
, 15); /* %o7 */
12045 sparc_emit_set_symbolic_const64 (scratch
, funexp
, spill_reg
);
12046 seq
= get_insns ();
12048 emit_and_preserve (seq
, spill_reg
, 0);
12052 gcc_unreachable ();
12056 emit_jump_insn (gen_indirect_jump (scratch
));
12061 /* Run just enough of rest_of_compilation to get the insns emitted.
12062 There's not really enough bulk here to make other passes such as
12063 instruction scheduling worth while. Note that use_thunk calls
12064 assemble_start_function and assemble_end_function. */
12065 insn
= get_insns ();
12066 shorten_branches (insn
);
12067 final_start_function (insn
, file
, 1);
12068 final (insn
, file
, 1);
12069 final_end_function ();
12071 reload_completed
= 0;
12072 epilogue_completed
= 0;
12075 /* Return true if sparc_output_mi_thunk would be able to output the
12076 assembler code for the thunk function specified by the arguments
12077 it is passed, and false otherwise. */
12079 sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED
,
12080 HOST_WIDE_INT delta ATTRIBUTE_UNUSED
,
12081 HOST_WIDE_INT vcall_offset
,
12082 const_tree function ATTRIBUTE_UNUSED
)
12084 /* Bound the loop used in the default method above. */
12085 return (vcall_offset
>= -32768 || ! fixed_regs
[5]);
12088 /* How to allocate a 'struct machine_function'. */
12090 static struct machine_function
*
12091 sparc_init_machine_status (void)
12093 return ggc_cleared_alloc
<machine_function
> ();
12096 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
12097 We need to emit DTP-relative relocations. */
12100 sparc_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
12105 fputs ("\t.word\t%r_tls_dtpoff32(", file
);
12108 fputs ("\t.xword\t%r_tls_dtpoff64(", file
);
12111 gcc_unreachable ();
12113 output_addr_const (file
, x
);
12117 /* Do whatever processing is required at the end of a file. */
12120 sparc_file_end (void)
12122 /* If we need to emit the special GOT helper function, do so now. */
12123 if (got_helper_rtx
)
12125 const char *name
= XSTR (got_helper_rtx
, 0);
12126 const char *reg_name
= reg_names
[GLOBAL_OFFSET_TABLE_REGNUM
];
12127 #ifdef DWARF2_UNWIND_INFO
12131 if (USE_HIDDEN_LINKONCE
)
12133 tree decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
12134 get_identifier (name
),
12135 build_function_type_list (void_type_node
,
12137 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
12138 NULL_TREE
, void_type_node
);
12139 TREE_PUBLIC (decl
) = 1;
12140 TREE_STATIC (decl
) = 1;
12141 make_decl_one_only (decl
, DECL_ASSEMBLER_NAME (decl
));
12142 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
12143 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
12144 resolve_unique_section (decl
, 0, flag_function_sections
);
12145 allocate_struct_function (decl
, true);
12146 cfun
->is_thunk
= 1;
12147 current_function_decl
= decl
;
12148 init_varasm_status ();
12149 assemble_start_function (decl
, name
);
12153 const int align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
12154 switch_to_section (text_section
);
12156 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
12157 ASM_OUTPUT_LABEL (asm_out_file
, name
);
12160 #ifdef DWARF2_UNWIND_INFO
12161 do_cfi
= dwarf2out_do_cfi_asm ();
12163 fprintf (asm_out_file
, "\t.cfi_startproc\n");
12165 if (flag_delayed_branch
)
12166 fprintf (asm_out_file
, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
12167 reg_name
, reg_name
);
12169 fprintf (asm_out_file
, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
12170 reg_name
, reg_name
);
12171 #ifdef DWARF2_UNWIND_INFO
12173 fprintf (asm_out_file
, "\t.cfi_endproc\n");
12177 if (NEED_INDICATE_EXEC_STACK
)
12178 file_end_indicate_exec_stack ();
12180 #ifdef TARGET_SOLARIS
12181 solaris_file_end ();
12185 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
12186 /* Implement TARGET_MANGLE_TYPE. */
12188 static const char *
12189 sparc_mangle_type (const_tree type
)
12192 && TYPE_MAIN_VARIANT (type
) == long_double_type_node
12193 && TARGET_LONG_DOUBLE_128
)
12196 /* For all other types, use normal C++ mangling. */
12201 /* Expand a membar instruction for various use cases. Both the LOAD_STORE
12202 and BEFORE_AFTER arguments of the form X_Y. They are two-bit masks where
12203 bit 0 indicates that X is true, and bit 1 indicates Y is true. */
12206 sparc_emit_membar_for_model (enum memmodel model
,
12207 int load_store
, int before_after
)
12209 /* Bits for the MEMBAR mmask field. */
12210 const int LoadLoad
= 1;
12211 const int StoreLoad
= 2;
12212 const int LoadStore
= 4;
12213 const int StoreStore
= 8;
12215 int mm
= 0, implied
= 0;
12217 switch (sparc_memory_model
)
12220 /* Sequential Consistency. All memory transactions are immediately
12221 visible in sequential execution order. No barriers needed. */
12222 implied
= LoadLoad
| StoreLoad
| LoadStore
| StoreStore
;
12226 /* Total Store Ordering: all memory transactions with store semantics
12227 are followed by an implied StoreStore. */
12228 implied
|= StoreStore
;
12230 /* If we're not looking for a raw barrer (before+after), then atomic
12231 operations get the benefit of being both load and store. */
12232 if (load_store
== 3 && before_after
== 1)
12233 implied
|= StoreLoad
;
12237 /* Partial Store Ordering: all memory transactions with load semantics
12238 are followed by an implied LoadLoad | LoadStore. */
12239 implied
|= LoadLoad
| LoadStore
;
12241 /* If we're not looking for a raw barrer (before+after), then atomic
12242 operations get the benefit of being both load and store. */
12243 if (load_store
== 3 && before_after
== 2)
12244 implied
|= StoreLoad
| StoreStore
;
12248 /* Relaxed Memory Ordering: no implicit bits. */
12252 gcc_unreachable ();
12255 if (before_after
& 1)
12257 if (is_mm_release (model
) || is_mm_acq_rel (model
)
12258 || is_mm_seq_cst (model
))
12260 if (load_store
& 1)
12261 mm
|= LoadLoad
| StoreLoad
;
12262 if (load_store
& 2)
12263 mm
|= LoadStore
| StoreStore
;
12266 if (before_after
& 2)
12268 if (is_mm_acquire (model
) || is_mm_acq_rel (model
)
12269 || is_mm_seq_cst (model
))
12271 if (load_store
& 1)
12272 mm
|= LoadLoad
| LoadStore
;
12273 if (load_store
& 2)
12274 mm
|= StoreLoad
| StoreStore
;
12278 /* Remove the bits implied by the system memory model. */
12281 /* For raw barriers (before+after), always emit a barrier.
12282 This will become a compile-time barrier if needed. */
12283 if (mm
|| before_after
== 3)
12284 emit_insn (gen_membar (GEN_INT (mm
)));
12287 /* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit
12288 compare and swap on the word containing the byte or half-word. */
12291 sparc_expand_compare_and_swap_12 (rtx bool_result
, rtx result
, rtx mem
,
12292 rtx oldval
, rtx newval
)
12294 rtx addr1
= force_reg (Pmode
, XEXP (mem
, 0));
12295 rtx addr
= gen_reg_rtx (Pmode
);
12296 rtx off
= gen_reg_rtx (SImode
);
12297 rtx oldv
= gen_reg_rtx (SImode
);
12298 rtx newv
= gen_reg_rtx (SImode
);
12299 rtx oldvalue
= gen_reg_rtx (SImode
);
12300 rtx newvalue
= gen_reg_rtx (SImode
);
12301 rtx res
= gen_reg_rtx (SImode
);
12302 rtx resv
= gen_reg_rtx (SImode
);
12303 rtx memsi
, val
, mask
, cc
;
12305 emit_insn (gen_rtx_SET (addr
, gen_rtx_AND (Pmode
, addr1
, GEN_INT (-4))));
12307 if (Pmode
!= SImode
)
12308 addr1
= gen_lowpart (SImode
, addr1
);
12309 emit_insn (gen_rtx_SET (off
, gen_rtx_AND (SImode
, addr1
, GEN_INT (3))));
12311 memsi
= gen_rtx_MEM (SImode
, addr
);
12312 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
12313 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
12315 val
= copy_to_reg (memsi
);
12317 emit_insn (gen_rtx_SET (off
,
12318 gen_rtx_XOR (SImode
, off
,
12319 GEN_INT (GET_MODE (mem
) == QImode
12322 emit_insn (gen_rtx_SET (off
, gen_rtx_ASHIFT (SImode
, off
, GEN_INT (3))));
12324 if (GET_MODE (mem
) == QImode
)
12325 mask
= force_reg (SImode
, GEN_INT (0xff));
12327 mask
= force_reg (SImode
, GEN_INT (0xffff));
12329 emit_insn (gen_rtx_SET (mask
, gen_rtx_ASHIFT (SImode
, mask
, off
)));
12331 emit_insn (gen_rtx_SET (val
,
12332 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
12335 oldval
= gen_lowpart (SImode
, oldval
);
12336 emit_insn (gen_rtx_SET (oldv
, gen_rtx_ASHIFT (SImode
, oldval
, off
)));
12338 newval
= gen_lowpart_common (SImode
, newval
);
12339 emit_insn (gen_rtx_SET (newv
, gen_rtx_ASHIFT (SImode
, newval
, off
)));
12341 emit_insn (gen_rtx_SET (oldv
, gen_rtx_AND (SImode
, oldv
, mask
)));
12343 emit_insn (gen_rtx_SET (newv
, gen_rtx_AND (SImode
, newv
, mask
)));
12345 rtx_code_label
*end_label
= gen_label_rtx ();
12346 rtx_code_label
*loop_label
= gen_label_rtx ();
12347 emit_label (loop_label
);
12349 emit_insn (gen_rtx_SET (oldvalue
, gen_rtx_IOR (SImode
, oldv
, val
)));
12351 emit_insn (gen_rtx_SET (newvalue
, gen_rtx_IOR (SImode
, newv
, val
)));
12353 emit_move_insn (bool_result
, const1_rtx
);
12355 emit_insn (gen_atomic_compare_and_swapsi_1 (res
, memsi
, oldvalue
, newvalue
));
12357 emit_cmp_and_jump_insns (res
, oldvalue
, EQ
, NULL
, SImode
, 0, end_label
);
12359 emit_insn (gen_rtx_SET (resv
,
12360 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
12363 emit_move_insn (bool_result
, const0_rtx
);
12365 cc
= gen_compare_reg_1 (NE
, resv
, val
);
12366 emit_insn (gen_rtx_SET (val
, resv
));
12368 /* Use cbranchcc4 to separate the compare and branch! */
12369 emit_jump_insn (gen_cbranchcc4 (gen_rtx_NE (VOIDmode
, cc
, const0_rtx
),
12370 cc
, const0_rtx
, loop_label
));
12372 emit_label (end_label
);
12374 emit_insn (gen_rtx_SET (res
, gen_rtx_AND (SImode
, res
, mask
)));
12376 emit_insn (gen_rtx_SET (res
, gen_rtx_LSHIFTRT (SImode
, res
, off
)));
12378 emit_move_insn (result
, gen_lowpart (GET_MODE (result
), res
));
12381 /* Expand code to perform a compare-and-swap. */
12384 sparc_expand_compare_and_swap (rtx operands
[])
12386 rtx bval
, retval
, mem
, oldval
, newval
;
12388 enum memmodel model
;
12390 bval
= operands
[0];
12391 retval
= operands
[1];
12393 oldval
= operands
[3];
12394 newval
= operands
[4];
12395 model
= (enum memmodel
) INTVAL (operands
[6]);
12396 mode
= GET_MODE (mem
);
12398 sparc_emit_membar_for_model (model
, 3, 1);
12400 if (reg_overlap_mentioned_p (retval
, oldval
))
12401 oldval
= copy_to_reg (oldval
);
12403 if (mode
== QImode
|| mode
== HImode
)
12404 sparc_expand_compare_and_swap_12 (bval
, retval
, mem
, oldval
, newval
);
12407 rtx (*gen
) (rtx
, rtx
, rtx
, rtx
);
12410 if (mode
== SImode
)
12411 gen
= gen_atomic_compare_and_swapsi_1
;
12413 gen
= gen_atomic_compare_and_swapdi_1
;
12414 emit_insn (gen (retval
, mem
, oldval
, newval
));
12416 x
= emit_store_flag (bval
, EQ
, retval
, oldval
, mode
, 1, 1);
12418 convert_move (bval
, x
, 1);
12421 sparc_emit_membar_for_model (model
, 3, 2);
12425 sparc_expand_vec_perm_bmask (machine_mode vmode
, rtx sel
)
12429 sel
= gen_lowpart (DImode
, sel
);
12433 /* inp = xxxxxxxAxxxxxxxB */
12434 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
12435 NULL_RTX
, 1, OPTAB_DIRECT
);
12436 /* t_1 = ....xxxxxxxAxxx. */
12437 sel
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, sel
),
12438 GEN_INT (3), NULL_RTX
, 1, OPTAB_DIRECT
);
12439 t_1
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_1
),
12440 GEN_INT (0x30000), NULL_RTX
, 1, OPTAB_DIRECT
);
12441 /* sel = .......B */
12442 /* t_1 = ...A.... */
12443 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_1
, sel
, 1, OPTAB_DIRECT
);
12444 /* sel = ...A...B */
12445 sel
= expand_mult (SImode
, sel
, GEN_INT (0x4444), sel
, 1);
12446 /* sel = AAAABBBB * 4 */
12447 t_1
= force_reg (SImode
, GEN_INT (0x01230123));
12448 /* sel = { A*4, A*4+1, A*4+2, ... } */
12452 /* inp = xxxAxxxBxxxCxxxD */
12453 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (8),
12454 NULL_RTX
, 1, OPTAB_DIRECT
);
12455 t_2
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
12456 NULL_RTX
, 1, OPTAB_DIRECT
);
12457 t_3
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (24),
12458 NULL_RTX
, 1, OPTAB_DIRECT
);
12459 /* t_1 = ..xxxAxxxBxxxCxx */
12460 /* t_2 = ....xxxAxxxBxxxC */
12461 /* t_3 = ......xxxAxxxBxx */
12462 sel
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, sel
),
12464 NULL_RTX
, 1, OPTAB_DIRECT
);
12465 t_1
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_1
),
12467 NULL_RTX
, 1, OPTAB_DIRECT
);
12468 t_2
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_2
),
12469 GEN_INT (0x070000),
12470 NULL_RTX
, 1, OPTAB_DIRECT
);
12471 t_3
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_3
),
12472 GEN_INT (0x07000000),
12473 NULL_RTX
, 1, OPTAB_DIRECT
);
12474 /* sel = .......D */
12475 /* t_1 = .....C.. */
12476 /* t_2 = ...B.... */
12477 /* t_3 = .A...... */
12478 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_1
, sel
, 1, OPTAB_DIRECT
);
12479 t_2
= expand_simple_binop (SImode
, IOR
, t_2
, t_3
, t_2
, 1, OPTAB_DIRECT
);
12480 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_2
, sel
, 1, OPTAB_DIRECT
);
12481 /* sel = .A.B.C.D */
12482 sel
= expand_mult (SImode
, sel
, GEN_INT (0x22), sel
, 1);
12483 /* sel = AABBCCDD * 2 */
12484 t_1
= force_reg (SImode
, GEN_INT (0x01010101));
12485 /* sel = { A*2, A*2+1, B*2, B*2+1, ... } */
12489 /* input = xAxBxCxDxExFxGxH */
12490 sel
= expand_simple_binop (DImode
, AND
, sel
,
12491 GEN_INT ((HOST_WIDE_INT
)0x0f0f0f0f << 32
12493 NULL_RTX
, 1, OPTAB_DIRECT
);
12494 /* sel = .A.B.C.D.E.F.G.H */
12495 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (4),
12496 NULL_RTX
, 1, OPTAB_DIRECT
);
12497 /* t_1 = ..A.B.C.D.E.F.G. */
12498 sel
= expand_simple_binop (DImode
, IOR
, sel
, t_1
,
12499 NULL_RTX
, 1, OPTAB_DIRECT
);
12500 /* sel = .AABBCCDDEEFFGGH */
12501 sel
= expand_simple_binop (DImode
, AND
, sel
,
12502 GEN_INT ((HOST_WIDE_INT
)0xff00ff << 32
12504 NULL_RTX
, 1, OPTAB_DIRECT
);
12505 /* sel = ..AB..CD..EF..GH */
12506 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (8),
12507 NULL_RTX
, 1, OPTAB_DIRECT
);
12508 /* t_1 = ....AB..CD..EF.. */
12509 sel
= expand_simple_binop (DImode
, IOR
, sel
, t_1
,
12510 NULL_RTX
, 1, OPTAB_DIRECT
);
12511 /* sel = ..ABABCDCDEFEFGH */
12512 sel
= expand_simple_binop (DImode
, AND
, sel
,
12513 GEN_INT ((HOST_WIDE_INT
)0xffff << 32 | 0xffff),
12514 NULL_RTX
, 1, OPTAB_DIRECT
);
12515 /* sel = ....ABCD....EFGH */
12516 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
12517 NULL_RTX
, 1, OPTAB_DIRECT
);
12518 /* t_1 = ........ABCD.... */
12519 sel
= gen_lowpart (SImode
, sel
);
12520 t_1
= gen_lowpart (SImode
, t_1
);
12524 gcc_unreachable ();
12527 /* Always perform the final addition/merge within the bmask insn. */
12528 emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode
), sel
, t_1
));
12531 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
12534 sparc_frame_pointer_required (void)
12536 /* If the stack pointer is dynamically modified in the function, it cannot
12537 serve as the frame pointer. */
12538 if (cfun
->calls_alloca
)
12541 /* If the function receives nonlocal gotos, it needs to save the frame
12542 pointer in the nonlocal_goto_save_area object. */
12543 if (cfun
->has_nonlocal_label
)
12546 /* In flat mode, that's it. */
12550 /* Otherwise, the frame pointer is required if the function isn't leaf, but
12551 we cannot use sparc_leaf_function_p since it hasn't been computed yet. */
12552 return !(optimize
> 0 && crtl
->is_leaf
&& only_leaf_regs_used ());
12555 /* The way this is structured, we can't eliminate SFP in favor of SP
12556 if the frame pointer is required: we want to use the SFP->HFP elimination
12557 in that case. But the test in update_eliminables doesn't know we are
12558 assuming below that we only do the former elimination. */
12561 sparc_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
12563 return to
== HARD_FRAME_POINTER_REGNUM
|| !sparc_frame_pointer_required ();
12566 /* Return the hard frame pointer directly to bypass the stack bias. */
12569 sparc_builtin_setjmp_frame_value (void)
12571 return hard_frame_pointer_rtx
;
12574 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
12575 they won't be allocated. */
12578 sparc_conditional_register_usage (void)
12580 if (PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
12582 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
12583 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
12585 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */
12586 /* then honor it. */
12587 if (TARGET_ARCH32
&& fixed_regs
[5])
12589 else if (TARGET_ARCH64
&& fixed_regs
[5] == 2)
12594 for (regno
= SPARC_FIRST_V9_FP_REG
;
12595 regno
<= SPARC_LAST_V9_FP_REG
;
12597 fixed_regs
[regno
] = 1;
12598 /* %fcc0 is used by v8 and v9. */
12599 for (regno
= SPARC_FIRST_V9_FCC_REG
+ 1;
12600 regno
<= SPARC_LAST_V9_FCC_REG
;
12602 fixed_regs
[regno
] = 1;
12607 for (regno
= 32; regno
< SPARC_LAST_V9_FCC_REG
; regno
++)
12608 fixed_regs
[regno
] = 1;
12610 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */
12611 /* then honor it. Likewise with g3 and g4. */
12612 if (fixed_regs
[2] == 2)
12613 fixed_regs
[2] = ! TARGET_APP_REGS
;
12614 if (fixed_regs
[3] == 2)
12615 fixed_regs
[3] = ! TARGET_APP_REGS
;
12616 if (TARGET_ARCH32
&& fixed_regs
[4] == 2)
12617 fixed_regs
[4] = ! TARGET_APP_REGS
;
12618 else if (TARGET_CM_EMBMEDANY
)
12620 else if (fixed_regs
[4] == 2)
12625 /* Disable leaf functions. */
12626 memset (sparc_leaf_regs
, 0, FIRST_PSEUDO_REGISTER
);
12627 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
12628 leaf_reg_remap
[regno
] = regno
;
12631 global_regs
[SPARC_GSR_REG
] = 1;
12634 /* Implement TARGET_PREFERRED_RELOAD_CLASS:
12636 - We can't load constants into FP registers.
12637 - We can't load FP constants into integer registers when soft-float,
12638 because there is no soft-float pattern with a r/F constraint.
12639 - We can't load FP constants into integer registers for TFmode unless
12640 it is 0.0L, because there is no movtf pattern with a r/F constraint.
12641 - Try and reload integer constants (symbolic or otherwise) back into
12642 registers directly, rather than having them dumped to memory. */
12645 sparc_preferred_reload_class (rtx x
, reg_class_t rclass
)
12647 machine_mode mode
= GET_MODE (x
);
12648 if (CONSTANT_P (x
))
12650 if (FP_REG_CLASS_P (rclass
)
12651 || rclass
== GENERAL_OR_FP_REGS
12652 || rclass
== GENERAL_OR_EXTRA_FP_REGS
12653 || (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& ! TARGET_FPU
)
12654 || (mode
== TFmode
&& ! const_zero_operand (x
, mode
)))
12657 if (GET_MODE_CLASS (mode
) == MODE_INT
)
12658 return GENERAL_REGS
;
12660 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
12662 if (! FP_REG_CLASS_P (rclass
)
12663 || !(const_zero_operand (x
, mode
)
12664 || const_all_ones_operand (x
, mode
)))
12671 && (rclass
== EXTRA_FP_REGS
12672 || rclass
== GENERAL_OR_EXTRA_FP_REGS
))
12674 int regno
= true_regnum (x
);
12676 if (SPARC_INT_REG_P (regno
))
12677 return (rclass
== EXTRA_FP_REGS
12678 ? FP_REGS
: GENERAL_OR_FP_REGS
);
12684 /* Return true if we use LRA instead of reload pass. */
12692 /* Output a wide multiply instruction in V8+ mode. INSN is the instruction,
12693 OPERANDS are its operands and OPCODE is the mnemonic to be used. */
12696 output_v8plus_mult (rtx_insn
*insn
, rtx
*operands
, const char *opcode
)
12700 gcc_assert (! TARGET_ARCH64
);
12702 if (sparc_check_64 (operands
[1], insn
) <= 0)
12703 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
12704 if (which_alternative
== 1)
12705 output_asm_insn ("sllx\t%H1, 32, %H1", operands
);
12706 if (GET_CODE (operands
[2]) == CONST_INT
)
12708 if (which_alternative
== 1)
12710 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
12711 sprintf (mulstr
, "%s\t%%H1, %%2, %%L0", opcode
);
12712 output_asm_insn (mulstr
, operands
);
12713 return "srlx\t%L0, 32, %H0";
12717 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
12718 output_asm_insn ("or\t%L1, %3, %3", operands
);
12719 sprintf (mulstr
, "%s\t%%3, %%2, %%3", opcode
);
12720 output_asm_insn (mulstr
, operands
);
12721 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
12722 return "mov\t%3, %L0";
12725 else if (rtx_equal_p (operands
[1], operands
[2]))
12727 if (which_alternative
== 1)
12729 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
12730 sprintf (mulstr
, "%s\t%%H1, %%H1, %%L0", opcode
);
12731 output_asm_insn (mulstr
, operands
);
12732 return "srlx\t%L0, 32, %H0";
12736 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
12737 output_asm_insn ("or\t%L1, %3, %3", operands
);
12738 sprintf (mulstr
, "%s\t%%3, %%3, %%3", opcode
);
12739 output_asm_insn (mulstr
, operands
);
12740 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
12741 return "mov\t%3, %L0";
12744 if (sparc_check_64 (operands
[2], insn
) <= 0)
12745 output_asm_insn ("srl\t%L2, 0, %L2", operands
);
12746 if (which_alternative
== 1)
12748 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
12749 output_asm_insn ("sllx\t%H2, 32, %L1", operands
);
12750 output_asm_insn ("or\t%L2, %L1, %L1", operands
);
12751 sprintf (mulstr
, "%s\t%%H1, %%L1, %%L0", opcode
);
12752 output_asm_insn (mulstr
, operands
);
12753 return "srlx\t%L0, 32, %H0";
12757 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
12758 output_asm_insn ("sllx\t%H2, 32, %4", operands
);
12759 output_asm_insn ("or\t%L1, %3, %3", operands
);
12760 output_asm_insn ("or\t%L2, %4, %4", operands
);
12761 sprintf (mulstr
, "%s\t%%3, %%4, %%3", opcode
);
12762 output_asm_insn (mulstr
, operands
);
12763 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
12764 return "mov\t%3, %L0";
12768 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
12769 all fields of TARGET to ELT by means of VIS2 BSHUFFLE insn. MODE
12770 and INNER_MODE are the modes describing TARGET. */
12773 vector_init_bshuffle (rtx target
, rtx elt
, machine_mode mode
,
12774 machine_mode inner_mode
)
12776 rtx t1
, final_insn
, sel
;
12779 t1
= gen_reg_rtx (mode
);
12781 elt
= convert_modes (SImode
, inner_mode
, elt
, true);
12782 emit_move_insn (gen_lowpart(SImode
, t1
), elt
);
12787 final_insn
= gen_bshufflev2si_vis (target
, t1
, t1
);
12788 bmask
= 0x45674567;
12791 final_insn
= gen_bshufflev4hi_vis (target
, t1
, t1
);
12792 bmask
= 0x67676767;
12795 final_insn
= gen_bshufflev8qi_vis (target
, t1
, t1
);
12796 bmask
= 0x77777777;
12799 gcc_unreachable ();
12802 sel
= force_reg (SImode
, GEN_INT (bmask
));
12803 emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode
), sel
, const0_rtx
));
12804 emit_insn (final_insn
);
12807 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
12808 all fields of TARGET to ELT in V8QI by means of VIS FPMERGE insn. */
12811 vector_init_fpmerge (rtx target
, rtx elt
)
12813 rtx t1
, t2
, t2_low
, t3
, t3_low
;
12815 t1
= gen_reg_rtx (V4QImode
);
12816 elt
= convert_modes (SImode
, QImode
, elt
, true);
12817 emit_move_insn (gen_lowpart (SImode
, t1
), elt
);
12819 t2
= gen_reg_rtx (V8QImode
);
12820 t2_low
= gen_lowpart (V4QImode
, t2
);
12821 emit_insn (gen_fpmerge_vis (t2
, t1
, t1
));
12823 t3
= gen_reg_rtx (V8QImode
);
12824 t3_low
= gen_lowpart (V4QImode
, t3
);
12825 emit_insn (gen_fpmerge_vis (t3
, t2_low
, t2_low
));
12827 emit_insn (gen_fpmerge_vis (target
, t3_low
, t3_low
));
12830 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
12831 all fields of TARGET to ELT in V4HI by means of VIS FALIGNDATA insn. */
12834 vector_init_faligndata (rtx target
, rtx elt
)
12836 rtx t1
= gen_reg_rtx (V4HImode
);
12839 elt
= convert_modes (SImode
, HImode
, elt
, true);
12840 emit_move_insn (gen_lowpart (SImode
, t1
), elt
);
12842 emit_insn (gen_alignaddrsi_vis (gen_reg_rtx (SImode
),
12843 force_reg (SImode
, GEN_INT (6)),
12846 for (i
= 0; i
< 4; i
++)
12847 emit_insn (gen_faligndatav4hi_vis (target
, t1
, target
));
12850 /* Emit code to initialize TARGET to values for individual fields VALS. */
12853 sparc_expand_vector_init (rtx target
, rtx vals
)
12855 const machine_mode mode
= GET_MODE (target
);
12856 const machine_mode inner_mode
= GET_MODE_INNER (mode
);
12857 const int n_elts
= GET_MODE_NUNITS (mode
);
12859 bool all_same
= true;
12862 for (i
= 0; i
< n_elts
; i
++)
12864 rtx x
= XVECEXP (vals
, 0, i
);
12865 if (!(CONST_SCALAR_INT_P (x
) || CONST_DOUBLE_P (x
) || CONST_FIXED_P (x
)))
12868 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
12874 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
12878 if (GET_MODE_SIZE (inner_mode
) == GET_MODE_SIZE (mode
))
12880 if (GET_MODE_SIZE (inner_mode
) == 4)
12882 emit_move_insn (gen_lowpart (SImode
, target
),
12883 gen_lowpart (SImode
, XVECEXP (vals
, 0, 0)));
12886 else if (GET_MODE_SIZE (inner_mode
) == 8)
12888 emit_move_insn (gen_lowpart (DImode
, target
),
12889 gen_lowpart (DImode
, XVECEXP (vals
, 0, 0)));
12893 else if (GET_MODE_SIZE (inner_mode
) == GET_MODE_SIZE (word_mode
)
12894 && GET_MODE_SIZE (mode
) == 2 * GET_MODE_SIZE (word_mode
))
12896 emit_move_insn (gen_highpart (word_mode
, target
),
12897 gen_lowpart (word_mode
, XVECEXP (vals
, 0, 0)));
12898 emit_move_insn (gen_lowpart (word_mode
, target
),
12899 gen_lowpart (word_mode
, XVECEXP (vals
, 0, 1)));
12903 if (all_same
&& GET_MODE_SIZE (mode
) == 8)
12907 vector_init_bshuffle (target
, XVECEXP (vals
, 0, 0), mode
, inner_mode
);
12910 if (mode
== V8QImode
)
12912 vector_init_fpmerge (target
, XVECEXP (vals
, 0, 0));
12915 if (mode
== V4HImode
)
12917 vector_init_faligndata (target
, XVECEXP (vals
, 0, 0));
12922 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
12923 for (i
= 0; i
< n_elts
; i
++)
12924 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
12925 i
* GET_MODE_SIZE (inner_mode
)),
12926 XVECEXP (vals
, 0, i
));
12927 emit_move_insn (target
, mem
);
12930 /* Implement TARGET_SECONDARY_RELOAD. */
12933 sparc_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
12934 machine_mode mode
, secondary_reload_info
*sri
)
12936 enum reg_class rclass
= (enum reg_class
) rclass_i
;
12938 sri
->icode
= CODE_FOR_nothing
;
12939 sri
->extra_cost
= 0;
12941 /* We need a temporary when loading/storing a HImode/QImode value
12942 between memory and the FPU registers. This can happen when combine puts
12943 a paradoxical subreg in a float/fix conversion insn. */
12944 if (FP_REG_CLASS_P (rclass
)
12945 && (mode
== HImode
|| mode
== QImode
)
12946 && (GET_CODE (x
) == MEM
12947 || ((GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
12948 && true_regnum (x
) == -1)))
12949 return GENERAL_REGS
;
12951 /* On 32-bit we need a temporary when loading/storing a DFmode value
12952 between unaligned memory and the upper FPU registers. */
12954 && rclass
== EXTRA_FP_REGS
12956 && GET_CODE (x
) == MEM
12957 && ! mem_min_alignment (x
, 8))
12960 if (((TARGET_CM_MEDANY
12961 && symbolic_operand (x
, mode
))
12962 || (TARGET_CM_EMBMEDANY
12963 && text_segment_operand (x
, mode
)))
12967 sri
->icode
= direct_optab_handler (reload_in_optab
, mode
);
12969 sri
->icode
= direct_optab_handler (reload_out_optab
, mode
);
12973 if (TARGET_VIS3
&& TARGET_ARCH32
)
12975 int regno
= true_regnum (x
);
12977 /* When using VIS3 fp<-->int register moves, on 32-bit we have
12978 to move 8-byte values in 4-byte pieces. This only works via
12979 FP_REGS, and not via EXTRA_FP_REGS. Therefore if we try to
12980 move between EXTRA_FP_REGS and GENERAL_REGS, we will need
12981 an FP_REGS intermediate move. */
12982 if ((rclass
== EXTRA_FP_REGS
&& SPARC_INT_REG_P (regno
))
12983 || ((general_or_i64_p (rclass
)
12984 || rclass
== GENERAL_OR_FP_REGS
)
12985 && SPARC_FP_REG_P (regno
)))
12987 sri
->extra_cost
= 2;
12995 /* Emit code to conditionally move either OPERANDS[2] or OPERANDS[3] into
12996 OPERANDS[0] in MODE. OPERANDS[1] is the operator of the condition. */
12999 sparc_expand_conditional_move (machine_mode mode
, rtx
*operands
)
13001 enum rtx_code rc
= GET_CODE (operands
[1]);
13002 machine_mode cmp_mode
;
13003 rtx cc_reg
, dst
, cmp
;
13006 if (GET_MODE (XEXP (cmp
, 0)) == DImode
&& !TARGET_ARCH64
)
13009 if (GET_MODE (XEXP (cmp
, 0)) == TFmode
&& !TARGET_HARD_QUAD
)
13010 cmp
= sparc_emit_float_lib_cmp (XEXP (cmp
, 0), XEXP (cmp
, 1), rc
);
13012 cmp_mode
= GET_MODE (XEXP (cmp
, 0));
13013 rc
= GET_CODE (cmp
);
13016 if (! rtx_equal_p (operands
[2], dst
)
13017 && ! rtx_equal_p (operands
[3], dst
))
13019 if (reg_overlap_mentioned_p (dst
, cmp
))
13020 dst
= gen_reg_rtx (mode
);
13022 emit_move_insn (dst
, operands
[3]);
13024 else if (operands
[2] == dst
)
13026 operands
[2] = operands
[3];
13028 if (GET_MODE_CLASS (cmp_mode
) == MODE_FLOAT
)
13029 rc
= reverse_condition_maybe_unordered (rc
);
13031 rc
= reverse_condition (rc
);
13034 if (XEXP (cmp
, 1) == const0_rtx
13035 && GET_CODE (XEXP (cmp
, 0)) == REG
13036 && cmp_mode
== DImode
13037 && v9_regcmp_p (rc
))
13038 cc_reg
= XEXP (cmp
, 0);
13040 cc_reg
= gen_compare_reg_1 (rc
, XEXP (cmp
, 0), XEXP (cmp
, 1));
13042 cmp
= gen_rtx_fmt_ee (rc
, GET_MODE (cc_reg
), cc_reg
, const0_rtx
);
13044 emit_insn (gen_rtx_SET (dst
,
13045 gen_rtx_IF_THEN_ELSE (mode
, cmp
, operands
[2], dst
)));
13047 if (dst
!= operands
[0])
13048 emit_move_insn (operands
[0], dst
);
13053 /* Emit code to conditionally move a combination of OPERANDS[1] and OPERANDS[2]
13054 into OPERANDS[0] in MODE, depending on the outcome of the comparison of
13055 OPERANDS[4] and OPERANDS[5]. OPERANDS[3] is the operator of the condition.
13056 FCODE is the machine code to be used for OPERANDS[3] and CCODE the machine
13057 code to be used for the condition mask. */
13060 sparc_expand_vcond (machine_mode mode
, rtx
*operands
, int ccode
, int fcode
)
13062 rtx mask
, cop0
, cop1
, fcmp
, cmask
, bshuf
, gsr
;
13063 enum rtx_code code
= GET_CODE (operands
[3]);
13065 mask
= gen_reg_rtx (Pmode
);
13066 cop0
= operands
[4];
13067 cop1
= operands
[5];
13068 if (code
== LT
|| code
== GE
)
13072 code
= swap_condition (code
);
13073 t
= cop0
; cop0
= cop1
; cop1
= t
;
13076 gsr
= gen_rtx_REG (DImode
, SPARC_GSR_REG
);
13078 fcmp
= gen_rtx_UNSPEC (Pmode
,
13079 gen_rtvec (1, gen_rtx_fmt_ee (code
, mode
, cop0
, cop1
)),
13082 cmask
= gen_rtx_UNSPEC (DImode
,
13083 gen_rtvec (2, mask
, gsr
),
13086 bshuf
= gen_rtx_UNSPEC (mode
,
13087 gen_rtvec (3, operands
[1], operands
[2], gsr
),
13090 emit_insn (gen_rtx_SET (mask
, fcmp
));
13091 emit_insn (gen_rtx_SET (gsr
, cmask
));
13093 emit_insn (gen_rtx_SET (operands
[0], bshuf
));
13096 /* On sparc, any mode which naturally allocates into the float
13097 registers should return 4 here. */
13100 sparc_regmode_natural_size (machine_mode mode
)
13102 int size
= UNITS_PER_WORD
;
13106 enum mode_class mclass
= GET_MODE_CLASS (mode
);
13108 if (mclass
== MODE_FLOAT
|| mclass
== MODE_VECTOR_INT
)
13115 /* Return TRUE if it is a good idea to tie two pseudo registers
13116 when one has mode MODE1 and one has mode MODE2.
13117 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
13118 for any hard reg, then this must be FALSE for correct output.
13120 For V9 we have to deal with the fact that only the lower 32 floating
13121 point registers are 32-bit addressable. */
13124 sparc_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
13126 enum mode_class mclass1
, mclass2
;
13127 unsigned short size1
, size2
;
13129 if (mode1
== mode2
)
13132 mclass1
= GET_MODE_CLASS (mode1
);
13133 mclass2
= GET_MODE_CLASS (mode2
);
13134 if (mclass1
!= mclass2
)
13140 /* Classes are the same and we are V9 so we have to deal with upper
13141 vs. lower floating point registers. If one of the modes is a
13142 4-byte mode, and the other is not, we have to mark them as not
13143 tieable because only the lower 32 floating point register are
13144 addressable 32-bits at a time.
13146 We can't just test explicitly for SFmode, otherwise we won't
13147 cover the vector mode cases properly. */
13149 if (mclass1
!= MODE_FLOAT
&& mclass1
!= MODE_VECTOR_INT
)
13152 size1
= GET_MODE_SIZE (mode1
);
13153 size2
= GET_MODE_SIZE (mode2
);
13154 if ((size1
> 4 && size2
== 4)
13155 || (size2
> 4 && size1
== 4))
13161 /* Implement TARGET_CSTORE_MODE. */
13163 static machine_mode
13164 sparc_cstore_mode (enum insn_code icode ATTRIBUTE_UNUSED
)
13166 return (TARGET_ARCH64
? DImode
: SImode
);
13169 /* Return the compound expression made of T1 and T2. */
13172 compound_expr (tree t1
, tree t2
)
13174 return build2 (COMPOUND_EXPR
, void_type_node
, t1
, t2
);
13177 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
13180 sparc_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
13185 const unsigned HOST_WIDE_INT accrued_exception_mask
= 0x1f << 5;
13186 const unsigned HOST_WIDE_INT trap_enable_mask
= 0x1f << 23;
13188 /* We generate the equivalent of feholdexcept (&fenv_var):
13190 unsigned int fenv_var;
13191 __builtin_store_fsr (&fenv_var);
13193 unsigned int tmp1_var;
13194 tmp1_var = fenv_var & ~(accrued_exception_mask | trap_enable_mask);
13196 __builtin_load_fsr (&tmp1_var); */
13198 tree fenv_var
= create_tmp_var_raw (unsigned_type_node
);
13199 TREE_ADDRESSABLE (fenv_var
) = 1;
13200 tree fenv_addr
= build_fold_addr_expr (fenv_var
);
13201 tree stfsr
= sparc_builtins
[SPARC_BUILTIN_STFSR
];
13203 = build4 (TARGET_EXPR
, unsigned_type_node
, fenv_var
,
13204 build_call_expr (stfsr
, 1, fenv_addr
), NULL_TREE
, NULL_TREE
);
13206 tree tmp1_var
= create_tmp_var_raw (unsigned_type_node
);
13207 TREE_ADDRESSABLE (tmp1_var
) = 1;
13208 tree masked_fenv_var
13209 = build2 (BIT_AND_EXPR
, unsigned_type_node
, fenv_var
,
13210 build_int_cst (unsigned_type_node
,
13211 ~(accrued_exception_mask
| trap_enable_mask
)));
13213 = build4 (TARGET_EXPR
, unsigned_type_node
, tmp1_var
, masked_fenv_var
,
13214 NULL_TREE
, NULL_TREE
);
13216 tree tmp1_addr
= build_fold_addr_expr (tmp1_var
);
13217 tree ldfsr
= sparc_builtins
[SPARC_BUILTIN_LDFSR
];
13218 tree hold_ldfsr
= build_call_expr (ldfsr
, 1, tmp1_addr
);
13220 *hold
= compound_expr (compound_expr (hold_stfsr
, hold_mask
), hold_ldfsr
);
13222 /* We reload the value of tmp1_var to clear the exceptions:
13224 __builtin_load_fsr (&tmp1_var); */
13226 *clear
= build_call_expr (ldfsr
, 1, tmp1_addr
);
13228 /* We generate the equivalent of feupdateenv (&fenv_var):
13230 unsigned int tmp2_var;
13231 __builtin_store_fsr (&tmp2_var);
13233 __builtin_load_fsr (&fenv_var);
13235 if (SPARC_LOW_FE_EXCEPT_VALUES)
13237 __atomic_feraiseexcept ((int) tmp2_var); */
13239 tree tmp2_var
= create_tmp_var_raw (unsigned_type_node
);
13240 TREE_ADDRESSABLE (tmp2_var
) = 1;
13241 tree tmp2_addr
= build_fold_addr_expr (tmp2_var
);
13243 = build4 (TARGET_EXPR
, unsigned_type_node
, tmp2_var
,
13244 build_call_expr (stfsr
, 1, tmp2_addr
), NULL_TREE
, NULL_TREE
);
13246 tree update_ldfsr
= build_call_expr (ldfsr
, 1, fenv_addr
);
13248 tree atomic_feraiseexcept
13249 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT
);
13251 = build_call_expr (atomic_feraiseexcept
, 1,
13252 fold_convert (integer_type_node
, tmp2_var
));
13254 if (SPARC_LOW_FE_EXCEPT_VALUES
)
13256 tree shifted_tmp2_var
13257 = build2 (RSHIFT_EXPR
, unsigned_type_node
, tmp2_var
,
13258 build_int_cst (unsigned_type_node
, 5));
13260 = build2 (MODIFY_EXPR
, void_type_node
, tmp2_var
, shifted_tmp2_var
);
13261 update_call
= compound_expr (update_shift
, update_call
);
13265 = compound_expr (compound_expr (update_stfsr
, update_ldfsr
), update_call
);
13268 #include "gt-sparc.h"