1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987-2018 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
4 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
23 #define IN_TARGET_CODE 1
27 #include "coretypes.h"
36 #include "stringpool.h"
43 #include "diagnostic-core.h"
45 #include "fold-const.h"
46 #include "stor-layout.h"
50 #include "insn-attr.h"
54 #include "common/common-target.h"
56 #include "langhooks.h"
59 #include "tree-pass.h"
62 #include "tree-vector-builder.h"
64 /* This file should be included last. */
65 #include "target-def.h"
69 struct processor_costs
{
73 /* Integer signed load */
76 /* Integer zeroed load */
82 /* fmov, fneg, fabs */
86 const int float_plusminus
;
92 const int float_cmove
;
98 const int float_div_sf
;
101 const int float_div_df
;
104 const int float_sqrt_sf
;
107 const int float_sqrt_df
;
115 /* integer multiply cost for each bit set past the most
116 significant 3, so the formula for multiply cost becomes:
119 highest_bit = highest_clear_bit(rs1);
121 highest_bit = highest_set_bit(rs1);
124 cost = int_mul{,X} + ((highest_bit - 3) / int_mul_bit_factor);
126 A value of zero indicates that the multiply costs is fixed,
128 const int int_mul_bit_factor
;
139 /* penalty for shifts, due to scheduling rules etc. */
140 const int shift_penalty
;
144 struct processor_costs cypress_costs
= {
145 COSTS_N_INSNS (2), /* int load */
146 COSTS_N_INSNS (2), /* int signed load */
147 COSTS_N_INSNS (2), /* int zeroed load */
148 COSTS_N_INSNS (2), /* float load */
149 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
150 COSTS_N_INSNS (5), /* fadd, fsub */
151 COSTS_N_INSNS (1), /* fcmp */
152 COSTS_N_INSNS (1), /* fmov, fmovr */
153 COSTS_N_INSNS (7), /* fmul */
154 COSTS_N_INSNS (37), /* fdivs */
155 COSTS_N_INSNS (37), /* fdivd */
156 COSTS_N_INSNS (63), /* fsqrts */
157 COSTS_N_INSNS (63), /* fsqrtd */
158 COSTS_N_INSNS (1), /* imul */
159 COSTS_N_INSNS (1), /* imulX */
160 0, /* imul bit factor */
161 COSTS_N_INSNS (1), /* idiv */
162 COSTS_N_INSNS (1), /* idivX */
163 COSTS_N_INSNS (1), /* movcc/movr */
164 0, /* shift penalty */
168 struct processor_costs supersparc_costs
= {
169 COSTS_N_INSNS (1), /* int load */
170 COSTS_N_INSNS (1), /* int signed load */
171 COSTS_N_INSNS (1), /* int zeroed load */
172 COSTS_N_INSNS (0), /* float load */
173 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
174 COSTS_N_INSNS (3), /* fadd, fsub */
175 COSTS_N_INSNS (3), /* fcmp */
176 COSTS_N_INSNS (1), /* fmov, fmovr */
177 COSTS_N_INSNS (3), /* fmul */
178 COSTS_N_INSNS (6), /* fdivs */
179 COSTS_N_INSNS (9), /* fdivd */
180 COSTS_N_INSNS (12), /* fsqrts */
181 COSTS_N_INSNS (12), /* fsqrtd */
182 COSTS_N_INSNS (4), /* imul */
183 COSTS_N_INSNS (4), /* imulX */
184 0, /* imul bit factor */
185 COSTS_N_INSNS (4), /* idiv */
186 COSTS_N_INSNS (4), /* idivX */
187 COSTS_N_INSNS (1), /* movcc/movr */
188 1, /* shift penalty */
192 struct processor_costs hypersparc_costs
= {
193 COSTS_N_INSNS (1), /* int load */
194 COSTS_N_INSNS (1), /* int signed load */
195 COSTS_N_INSNS (1), /* int zeroed load */
196 COSTS_N_INSNS (1), /* float load */
197 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
198 COSTS_N_INSNS (1), /* fadd, fsub */
199 COSTS_N_INSNS (1), /* fcmp */
200 COSTS_N_INSNS (1), /* fmov, fmovr */
201 COSTS_N_INSNS (1), /* fmul */
202 COSTS_N_INSNS (8), /* fdivs */
203 COSTS_N_INSNS (12), /* fdivd */
204 COSTS_N_INSNS (17), /* fsqrts */
205 COSTS_N_INSNS (17), /* fsqrtd */
206 COSTS_N_INSNS (17), /* imul */
207 COSTS_N_INSNS (17), /* imulX */
208 0, /* imul bit factor */
209 COSTS_N_INSNS (17), /* idiv */
210 COSTS_N_INSNS (17), /* idivX */
211 COSTS_N_INSNS (1), /* movcc/movr */
212 0, /* shift penalty */
216 struct processor_costs leon_costs
= {
217 COSTS_N_INSNS (1), /* int load */
218 COSTS_N_INSNS (1), /* int signed load */
219 COSTS_N_INSNS (1), /* int zeroed load */
220 COSTS_N_INSNS (1), /* float load */
221 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
222 COSTS_N_INSNS (1), /* fadd, fsub */
223 COSTS_N_INSNS (1), /* fcmp */
224 COSTS_N_INSNS (1), /* fmov, fmovr */
225 COSTS_N_INSNS (1), /* fmul */
226 COSTS_N_INSNS (15), /* fdivs */
227 COSTS_N_INSNS (15), /* fdivd */
228 COSTS_N_INSNS (23), /* fsqrts */
229 COSTS_N_INSNS (23), /* fsqrtd */
230 COSTS_N_INSNS (5), /* imul */
231 COSTS_N_INSNS (5), /* imulX */
232 0, /* imul bit factor */
233 COSTS_N_INSNS (5), /* idiv */
234 COSTS_N_INSNS (5), /* idivX */
235 COSTS_N_INSNS (1), /* movcc/movr */
236 0, /* shift penalty */
240 struct processor_costs leon3_costs
= {
241 COSTS_N_INSNS (1), /* int load */
242 COSTS_N_INSNS (1), /* int signed load */
243 COSTS_N_INSNS (1), /* int zeroed load */
244 COSTS_N_INSNS (1), /* float load */
245 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
246 COSTS_N_INSNS (1), /* fadd, fsub */
247 COSTS_N_INSNS (1), /* fcmp */
248 COSTS_N_INSNS (1), /* fmov, fmovr */
249 COSTS_N_INSNS (1), /* fmul */
250 COSTS_N_INSNS (14), /* fdivs */
251 COSTS_N_INSNS (15), /* fdivd */
252 COSTS_N_INSNS (22), /* fsqrts */
253 COSTS_N_INSNS (23), /* fsqrtd */
254 COSTS_N_INSNS (5), /* imul */
255 COSTS_N_INSNS (5), /* imulX */
256 0, /* imul bit factor */
257 COSTS_N_INSNS (35), /* idiv */
258 COSTS_N_INSNS (35), /* idivX */
259 COSTS_N_INSNS (1), /* movcc/movr */
260 0, /* shift penalty */
264 struct processor_costs sparclet_costs
= {
265 COSTS_N_INSNS (3), /* int load */
266 COSTS_N_INSNS (3), /* int signed load */
267 COSTS_N_INSNS (1), /* int zeroed load */
268 COSTS_N_INSNS (1), /* float load */
269 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
270 COSTS_N_INSNS (1), /* fadd, fsub */
271 COSTS_N_INSNS (1), /* fcmp */
272 COSTS_N_INSNS (1), /* fmov, fmovr */
273 COSTS_N_INSNS (1), /* fmul */
274 COSTS_N_INSNS (1), /* fdivs */
275 COSTS_N_INSNS (1), /* fdivd */
276 COSTS_N_INSNS (1), /* fsqrts */
277 COSTS_N_INSNS (1), /* fsqrtd */
278 COSTS_N_INSNS (5), /* imul */
279 COSTS_N_INSNS (5), /* imulX */
280 0, /* imul bit factor */
281 COSTS_N_INSNS (5), /* idiv */
282 COSTS_N_INSNS (5), /* idivX */
283 COSTS_N_INSNS (1), /* movcc/movr */
284 0, /* shift penalty */
288 struct processor_costs ultrasparc_costs
= {
289 COSTS_N_INSNS (2), /* int load */
290 COSTS_N_INSNS (3), /* int signed load */
291 COSTS_N_INSNS (2), /* int zeroed load */
292 COSTS_N_INSNS (2), /* float load */
293 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
294 COSTS_N_INSNS (4), /* fadd, fsub */
295 COSTS_N_INSNS (1), /* fcmp */
296 COSTS_N_INSNS (2), /* fmov, fmovr */
297 COSTS_N_INSNS (4), /* fmul */
298 COSTS_N_INSNS (13), /* fdivs */
299 COSTS_N_INSNS (23), /* fdivd */
300 COSTS_N_INSNS (13), /* fsqrts */
301 COSTS_N_INSNS (23), /* fsqrtd */
302 COSTS_N_INSNS (4), /* imul */
303 COSTS_N_INSNS (4), /* imulX */
304 2, /* imul bit factor */
305 COSTS_N_INSNS (37), /* idiv */
306 COSTS_N_INSNS (68), /* idivX */
307 COSTS_N_INSNS (2), /* movcc/movr */
308 2, /* shift penalty */
312 struct processor_costs ultrasparc3_costs
= {
313 COSTS_N_INSNS (2), /* int load */
314 COSTS_N_INSNS (3), /* int signed load */
315 COSTS_N_INSNS (3), /* int zeroed load */
316 COSTS_N_INSNS (2), /* float load */
317 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
318 COSTS_N_INSNS (4), /* fadd, fsub */
319 COSTS_N_INSNS (5), /* fcmp */
320 COSTS_N_INSNS (3), /* fmov, fmovr */
321 COSTS_N_INSNS (4), /* fmul */
322 COSTS_N_INSNS (17), /* fdivs */
323 COSTS_N_INSNS (20), /* fdivd */
324 COSTS_N_INSNS (20), /* fsqrts */
325 COSTS_N_INSNS (29), /* fsqrtd */
326 COSTS_N_INSNS (6), /* imul */
327 COSTS_N_INSNS (6), /* imulX */
328 0, /* imul bit factor */
329 COSTS_N_INSNS (40), /* idiv */
330 COSTS_N_INSNS (71), /* idivX */
331 COSTS_N_INSNS (2), /* movcc/movr */
332 0, /* shift penalty */
336 struct processor_costs niagara_costs
= {
337 COSTS_N_INSNS (3), /* int load */
338 COSTS_N_INSNS (3), /* int signed load */
339 COSTS_N_INSNS (3), /* int zeroed load */
340 COSTS_N_INSNS (9), /* float load */
341 COSTS_N_INSNS (8), /* fmov, fneg, fabs */
342 COSTS_N_INSNS (8), /* fadd, fsub */
343 COSTS_N_INSNS (26), /* fcmp */
344 COSTS_N_INSNS (8), /* fmov, fmovr */
345 COSTS_N_INSNS (29), /* fmul */
346 COSTS_N_INSNS (54), /* fdivs */
347 COSTS_N_INSNS (83), /* fdivd */
348 COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */
349 COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */
350 COSTS_N_INSNS (11), /* imul */
351 COSTS_N_INSNS (11), /* imulX */
352 0, /* imul bit factor */
353 COSTS_N_INSNS (72), /* idiv */
354 COSTS_N_INSNS (72), /* idivX */
355 COSTS_N_INSNS (1), /* movcc/movr */
356 0, /* shift penalty */
360 struct processor_costs niagara2_costs
= {
361 COSTS_N_INSNS (3), /* int load */
362 COSTS_N_INSNS (3), /* int signed load */
363 COSTS_N_INSNS (3), /* int zeroed load */
364 COSTS_N_INSNS (3), /* float load */
365 COSTS_N_INSNS (6), /* fmov, fneg, fabs */
366 COSTS_N_INSNS (6), /* fadd, fsub */
367 COSTS_N_INSNS (6), /* fcmp */
368 COSTS_N_INSNS (6), /* fmov, fmovr */
369 COSTS_N_INSNS (6), /* fmul */
370 COSTS_N_INSNS (19), /* fdivs */
371 COSTS_N_INSNS (33), /* fdivd */
372 COSTS_N_INSNS (19), /* fsqrts */
373 COSTS_N_INSNS (33), /* fsqrtd */
374 COSTS_N_INSNS (5), /* imul */
375 COSTS_N_INSNS (5), /* imulX */
376 0, /* imul bit factor */
377 COSTS_N_INSNS (26), /* idiv, average of 12 - 41 cycle range */
378 COSTS_N_INSNS (26), /* idivX, average of 12 - 41 cycle range */
379 COSTS_N_INSNS (1), /* movcc/movr */
380 0, /* shift penalty */
384 struct processor_costs niagara3_costs
= {
385 COSTS_N_INSNS (3), /* int load */
386 COSTS_N_INSNS (3), /* int signed load */
387 COSTS_N_INSNS (3), /* int zeroed load */
388 COSTS_N_INSNS (3), /* float load */
389 COSTS_N_INSNS (9), /* fmov, fneg, fabs */
390 COSTS_N_INSNS (9), /* fadd, fsub */
391 COSTS_N_INSNS (9), /* fcmp */
392 COSTS_N_INSNS (9), /* fmov, fmovr */
393 COSTS_N_INSNS (9), /* fmul */
394 COSTS_N_INSNS (23), /* fdivs */
395 COSTS_N_INSNS (37), /* fdivd */
396 COSTS_N_INSNS (23), /* fsqrts */
397 COSTS_N_INSNS (37), /* fsqrtd */
398 COSTS_N_INSNS (9), /* imul */
399 COSTS_N_INSNS (9), /* imulX */
400 0, /* imul bit factor */
401 COSTS_N_INSNS (31), /* idiv, average of 17 - 45 cycle range */
402 COSTS_N_INSNS (30), /* idivX, average of 16 - 44 cycle range */
403 COSTS_N_INSNS (1), /* movcc/movr */
404 0, /* shift penalty */
408 struct processor_costs niagara4_costs
= {
409 COSTS_N_INSNS (5), /* int load */
410 COSTS_N_INSNS (5), /* int signed load */
411 COSTS_N_INSNS (5), /* int zeroed load */
412 COSTS_N_INSNS (5), /* float load */
413 COSTS_N_INSNS (11), /* fmov, fneg, fabs */
414 COSTS_N_INSNS (11), /* fadd, fsub */
415 COSTS_N_INSNS (11), /* fcmp */
416 COSTS_N_INSNS (11), /* fmov, fmovr */
417 COSTS_N_INSNS (11), /* fmul */
418 COSTS_N_INSNS (24), /* fdivs */
419 COSTS_N_INSNS (37), /* fdivd */
420 COSTS_N_INSNS (24), /* fsqrts */
421 COSTS_N_INSNS (37), /* fsqrtd */
422 COSTS_N_INSNS (12), /* imul */
423 COSTS_N_INSNS (12), /* imulX */
424 0, /* imul bit factor */
425 COSTS_N_INSNS (50), /* idiv, average of 41 - 60 cycle range */
426 COSTS_N_INSNS (35), /* idivX, average of 26 - 44 cycle range */
427 COSTS_N_INSNS (1), /* movcc/movr */
428 0, /* shift penalty */
432 struct processor_costs niagara7_costs
= {
433 COSTS_N_INSNS (5), /* int load */
434 COSTS_N_INSNS (5), /* int signed load */
435 COSTS_N_INSNS (5), /* int zeroed load */
436 COSTS_N_INSNS (5), /* float load */
437 COSTS_N_INSNS (11), /* fmov, fneg, fabs */
438 COSTS_N_INSNS (11), /* fadd, fsub */
439 COSTS_N_INSNS (11), /* fcmp */
440 COSTS_N_INSNS (11), /* fmov, fmovr */
441 COSTS_N_INSNS (11), /* fmul */
442 COSTS_N_INSNS (24), /* fdivs */
443 COSTS_N_INSNS (37), /* fdivd */
444 COSTS_N_INSNS (24), /* fsqrts */
445 COSTS_N_INSNS (37), /* fsqrtd */
446 COSTS_N_INSNS (12), /* imul */
447 COSTS_N_INSNS (12), /* imulX */
448 0, /* imul bit factor */
449 COSTS_N_INSNS (51), /* idiv, average of 42 - 61 cycle range */
450 COSTS_N_INSNS (35), /* idivX, average of 26 - 44 cycle range */
451 COSTS_N_INSNS (1), /* movcc/movr */
452 0, /* shift penalty */
456 struct processor_costs m8_costs
= {
457 COSTS_N_INSNS (3), /* int load */
458 COSTS_N_INSNS (3), /* int signed load */
459 COSTS_N_INSNS (3), /* int zeroed load */
460 COSTS_N_INSNS (3), /* float load */
461 COSTS_N_INSNS (9), /* fmov, fneg, fabs */
462 COSTS_N_INSNS (9), /* fadd, fsub */
463 COSTS_N_INSNS (9), /* fcmp */
464 COSTS_N_INSNS (9), /* fmov, fmovr */
465 COSTS_N_INSNS (9), /* fmul */
466 COSTS_N_INSNS (26), /* fdivs */
467 COSTS_N_INSNS (30), /* fdivd */
468 COSTS_N_INSNS (33), /* fsqrts */
469 COSTS_N_INSNS (41), /* fsqrtd */
470 COSTS_N_INSNS (12), /* imul */
471 COSTS_N_INSNS (10), /* imulX */
472 0, /* imul bit factor */
473 COSTS_N_INSNS (57), /* udiv/sdiv */
474 COSTS_N_INSNS (30), /* udivx/sdivx */
475 COSTS_N_INSNS (1), /* movcc/movr */
476 0, /* shift penalty */
479 static const struct processor_costs
*sparc_costs
= &cypress_costs
;
481 #ifdef HAVE_AS_RELAX_OPTION
482 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
483 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
484 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
485 somebody does not branch between the sethi and jmp. */
486 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
488 #define LEAF_SIBCALL_SLOT_RESERVED_P \
489 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
492 /* Vector to say how input registers are mapped to output registers.
493 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
494 eliminate it. You must use -fomit-frame-pointer to get that. */
495 char leaf_reg_remap
[] =
496 { 0, 1, 2, 3, 4, 5, 6, 7,
497 -1, -1, -1, -1, -1, -1, 14, -1,
498 -1, -1, -1, -1, -1, -1, -1, -1,
499 8, 9, 10, 11, 12, 13, -1, 15,
501 32, 33, 34, 35, 36, 37, 38, 39,
502 40, 41, 42, 43, 44, 45, 46, 47,
503 48, 49, 50, 51, 52, 53, 54, 55,
504 56, 57, 58, 59, 60, 61, 62, 63,
505 64, 65, 66, 67, 68, 69, 70, 71,
506 72, 73, 74, 75, 76, 77, 78, 79,
507 80, 81, 82, 83, 84, 85, 86, 87,
508 88, 89, 90, 91, 92, 93, 94, 95,
509 96, 97, 98, 99, 100, 101, 102};
511 /* Vector, indexed by hard register number, which contains 1
512 for a register that is allowable in a candidate for leaf
513 function treatment. */
514 char sparc_leaf_regs
[] =
515 { 1, 1, 1, 1, 1, 1, 1, 1,
516 0, 0, 0, 0, 0, 0, 1, 0,
517 0, 0, 0, 0, 0, 0, 0, 0,
518 1, 1, 1, 1, 1, 1, 0, 1,
519 1, 1, 1, 1, 1, 1, 1, 1,
520 1, 1, 1, 1, 1, 1, 1, 1,
521 1, 1, 1, 1, 1, 1, 1, 1,
522 1, 1, 1, 1, 1, 1, 1, 1,
523 1, 1, 1, 1, 1, 1, 1, 1,
524 1, 1, 1, 1, 1, 1, 1, 1,
525 1, 1, 1, 1, 1, 1, 1, 1,
526 1, 1, 1, 1, 1, 1, 1, 1,
527 1, 1, 1, 1, 1, 1, 1};
529 struct GTY(()) machine_function
531 /* Size of the frame of the function. */
532 HOST_WIDE_INT frame_size
;
534 /* Size of the frame of the function minus the register window save area
535 and the outgoing argument area. */
536 HOST_WIDE_INT apparent_frame_size
;
538 /* Register we pretend the frame pointer is allocated to. Normally, this
539 is %fp, but if we are in a leaf procedure, this is (%sp + offset). We
540 record "offset" separately as it may be too big for (reg + disp). */
542 HOST_WIDE_INT frame_base_offset
;
544 /* Number of global or FP registers to be saved (as 4-byte quantities). */
545 int n_global_fp_regs
;
547 /* True if the current function is leaf and uses only leaf regs,
548 so that the SPARC leaf function optimization can be applied.
549 Private version of crtl->uses_only_leaf_regs, see
550 sparc_expand_prologue for the rationale. */
553 /* True if the prologue saves local or in registers. */
554 bool save_local_in_regs_p
;
556 /* True if the data calculated by sparc_expand_prologue are valid. */
557 bool prologue_data_valid_p
;
560 #define sparc_frame_size cfun->machine->frame_size
561 #define sparc_apparent_frame_size cfun->machine->apparent_frame_size
562 #define sparc_frame_base_reg cfun->machine->frame_base_reg
563 #define sparc_frame_base_offset cfun->machine->frame_base_offset
564 #define sparc_n_global_fp_regs cfun->machine->n_global_fp_regs
565 #define sparc_leaf_function_p cfun->machine->leaf_function_p
566 #define sparc_save_local_in_regs_p cfun->machine->save_local_in_regs_p
567 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
569 /* 1 if the next opcode is to be specially indented. */
570 int sparc_indent_opcode
= 0;
572 static void sparc_option_override (void);
573 static void sparc_init_modes (void);
574 static int function_arg_slotno (const CUMULATIVE_ARGS
*, machine_mode
,
575 const_tree
, bool, bool, int *, int *);
577 static int supersparc_adjust_cost (rtx_insn
*, int, rtx_insn
*, int);
578 static int hypersparc_adjust_cost (rtx_insn
*, int, rtx_insn
*, int);
580 static void sparc_emit_set_const32 (rtx
, rtx
);
581 static void sparc_emit_set_const64 (rtx
, rtx
);
582 static void sparc_output_addr_vec (rtx
);
583 static void sparc_output_addr_diff_vec (rtx
);
584 static void sparc_output_deferred_case_vectors (void);
585 static bool sparc_legitimate_address_p (machine_mode
, rtx
, bool);
586 static bool sparc_legitimate_constant_p (machine_mode
, rtx
);
587 static rtx
sparc_builtin_saveregs (void);
588 static int epilogue_renumber (rtx
*, int);
589 static bool sparc_assemble_integer (rtx
, unsigned int, int);
590 static int set_extends (rtx_insn
*);
591 static void sparc_asm_function_prologue (FILE *);
592 static void sparc_asm_function_epilogue (FILE *);
593 #ifdef TARGET_SOLARIS
594 static void sparc_solaris_elf_asm_named_section (const char *, unsigned int,
595 tree
) ATTRIBUTE_UNUSED
;
597 static int sparc_adjust_cost (rtx_insn
*, int, rtx_insn
*, int, unsigned int);
598 static int sparc_issue_rate (void);
599 static void sparc_sched_init (FILE *, int, int);
600 static int sparc_use_sched_lookahead (void);
602 static void emit_soft_tfmode_libcall (const char *, int, rtx
*);
603 static void emit_soft_tfmode_binop (enum rtx_code
, rtx
*);
604 static void emit_soft_tfmode_unop (enum rtx_code
, rtx
*);
605 static void emit_soft_tfmode_cvt (enum rtx_code
, rtx
*);
606 static void emit_hard_tfmode_operation (enum rtx_code
, rtx
*);
608 static bool sparc_function_ok_for_sibcall (tree
, tree
);
609 static void sparc_init_libfuncs (void);
610 static void sparc_init_builtins (void);
611 static void sparc_fpu_init_builtins (void);
612 static void sparc_vis_init_builtins (void);
613 static tree
sparc_builtin_decl (unsigned, bool);
614 static rtx
sparc_expand_builtin (tree
, rtx
, rtx
, machine_mode
, int);
615 static tree
sparc_fold_builtin (tree
, int, tree
*, bool);
616 static void sparc_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
617 HOST_WIDE_INT
, tree
);
618 static bool sparc_can_output_mi_thunk (const_tree
, HOST_WIDE_INT
,
619 HOST_WIDE_INT
, const_tree
);
620 static struct machine_function
* sparc_init_machine_status (void);
621 static bool sparc_cannot_force_const_mem (machine_mode
, rtx
);
622 static rtx
sparc_tls_get_addr (void);
623 static rtx
sparc_tls_got (void);
624 static int sparc_register_move_cost (machine_mode
,
625 reg_class_t
, reg_class_t
);
626 static bool sparc_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
627 static rtx
sparc_function_value (const_tree
, const_tree
, bool);
628 static rtx
sparc_libcall_value (machine_mode
, const_rtx
);
629 static bool sparc_function_value_regno_p (const unsigned int);
630 static rtx
sparc_struct_value_rtx (tree
, int);
631 static machine_mode
sparc_promote_function_mode (const_tree
, machine_mode
,
632 int *, const_tree
, int);
633 static bool sparc_return_in_memory (const_tree
, const_tree
);
634 static bool sparc_strict_argument_naming (cumulative_args_t
);
635 static void sparc_va_start (tree
, rtx
);
636 static tree
sparc_gimplify_va_arg (tree
, tree
, gimple_seq
*, gimple_seq
*);
637 static bool sparc_vector_mode_supported_p (machine_mode
);
638 static bool sparc_tls_referenced_p (rtx
);
639 static rtx
sparc_legitimize_tls_address (rtx
);
640 static rtx
sparc_legitimize_pic_address (rtx
, rtx
);
641 static rtx
sparc_legitimize_address (rtx
, rtx
, machine_mode
);
642 static rtx
sparc_delegitimize_address (rtx
);
643 static bool sparc_mode_dependent_address_p (const_rtx
, addr_space_t
);
644 static bool sparc_pass_by_reference (cumulative_args_t
,
645 machine_mode
, const_tree
, bool);
646 static void sparc_function_arg_advance (cumulative_args_t
,
647 machine_mode
, const_tree
, bool);
648 static rtx
sparc_function_arg_1 (cumulative_args_t
,
649 machine_mode
, const_tree
, bool, bool);
650 static rtx
sparc_function_arg (cumulative_args_t
,
651 machine_mode
, const_tree
, bool);
652 static rtx
sparc_function_incoming_arg (cumulative_args_t
,
653 machine_mode
, const_tree
, bool);
654 static pad_direction
sparc_function_arg_padding (machine_mode
, const_tree
);
655 static unsigned int sparc_function_arg_boundary (machine_mode
,
657 static int sparc_arg_partial_bytes (cumulative_args_t
,
658 machine_mode
, tree
, bool);
659 static void sparc_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
660 static void sparc_file_end (void);
661 static bool sparc_frame_pointer_required (void);
662 static bool sparc_can_eliminate (const int, const int);
663 static rtx
sparc_builtin_setjmp_frame_value (void);
664 static void sparc_conditional_register_usage (void);
665 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
666 static const char *sparc_mangle_type (const_tree
);
668 static void sparc_trampoline_init (rtx
, tree
, rtx
);
669 static machine_mode
sparc_preferred_simd_mode (scalar_mode
);
670 static reg_class_t
sparc_preferred_reload_class (rtx x
, reg_class_t rclass
);
671 static bool sparc_lra_p (void);
672 static bool sparc_print_operand_punct_valid_p (unsigned char);
673 static void sparc_print_operand (FILE *, rtx
, int);
674 static void sparc_print_operand_address (FILE *, machine_mode
, rtx
);
675 static reg_class_t
sparc_secondary_reload (bool, rtx
, reg_class_t
,
677 secondary_reload_info
*);
678 static bool sparc_secondary_memory_needed (machine_mode
, reg_class_t
,
680 static machine_mode
sparc_secondary_memory_needed_mode (machine_mode
);
681 static scalar_int_mode
sparc_cstore_mode (enum insn_code icode
);
682 static void sparc_atomic_assign_expand_fenv (tree
*, tree
*, tree
*);
683 static bool sparc_fixed_condition_code_regs (unsigned int *, unsigned int *);
684 static unsigned int sparc_min_arithmetic_precision (void);
685 static unsigned int sparc_hard_regno_nregs (unsigned int, machine_mode
);
686 static bool sparc_hard_regno_mode_ok (unsigned int, machine_mode
);
687 static bool sparc_modes_tieable_p (machine_mode
, machine_mode
);
688 static bool sparc_can_change_mode_class (machine_mode
, machine_mode
,
690 static HOST_WIDE_INT
sparc_constant_alignment (const_tree
, HOST_WIDE_INT
);
691 static bool sparc_vectorize_vec_perm_const (machine_mode
, rtx
, rtx
, rtx
,
692 const vec_perm_indices
&);
694 #ifdef SUBTARGET_ATTRIBUTE_TABLE
695 /* Table of valid machine attributes. */
696 static const struct attribute_spec sparc_attribute_table
[] =
698 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
699 do_diagnostic, handler, exclude } */
700 SUBTARGET_ATTRIBUTE_TABLE
,
701 { NULL
, 0, 0, false, false, false, false, NULL
, NULL
}
705 /* Option handling. */
708 enum cmodel sparc_cmodel
;
710 char sparc_hard_reg_printed
[8];
712 /* Initialize the GCC target structure. */
714 /* The default is to use .half rather than .short for aligned HI objects. */
715 #undef TARGET_ASM_ALIGNED_HI_OP
716 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
718 #undef TARGET_ASM_UNALIGNED_HI_OP
719 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
720 #undef TARGET_ASM_UNALIGNED_SI_OP
721 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
722 #undef TARGET_ASM_UNALIGNED_DI_OP
723 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
725 /* The target hook has to handle DI-mode values. */
726 #undef TARGET_ASM_INTEGER
727 #define TARGET_ASM_INTEGER sparc_assemble_integer
729 #undef TARGET_ASM_FUNCTION_PROLOGUE
730 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
731 #undef TARGET_ASM_FUNCTION_EPILOGUE
732 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
734 #undef TARGET_SCHED_ADJUST_COST
735 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
736 #undef TARGET_SCHED_ISSUE_RATE
737 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
738 #undef TARGET_SCHED_INIT
739 #define TARGET_SCHED_INIT sparc_sched_init
740 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
741 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
743 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
744 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
746 #undef TARGET_INIT_LIBFUNCS
747 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
749 #undef TARGET_LEGITIMIZE_ADDRESS
750 #define TARGET_LEGITIMIZE_ADDRESS sparc_legitimize_address
751 #undef TARGET_DELEGITIMIZE_ADDRESS
752 #define TARGET_DELEGITIMIZE_ADDRESS sparc_delegitimize_address
753 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
754 #define TARGET_MODE_DEPENDENT_ADDRESS_P sparc_mode_dependent_address_p
756 #undef TARGET_INIT_BUILTINS
757 #define TARGET_INIT_BUILTINS sparc_init_builtins
758 #undef TARGET_BUILTIN_DECL
759 #define TARGET_BUILTIN_DECL sparc_builtin_decl
760 #undef TARGET_EXPAND_BUILTIN
761 #define TARGET_EXPAND_BUILTIN sparc_expand_builtin
762 #undef TARGET_FOLD_BUILTIN
763 #define TARGET_FOLD_BUILTIN sparc_fold_builtin
766 #undef TARGET_HAVE_TLS
767 #define TARGET_HAVE_TLS true
770 #undef TARGET_CANNOT_FORCE_CONST_MEM
771 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
773 #undef TARGET_ASM_OUTPUT_MI_THUNK
774 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
775 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
776 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
778 #undef TARGET_RTX_COSTS
779 #define TARGET_RTX_COSTS sparc_rtx_costs
780 #undef TARGET_ADDRESS_COST
781 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
782 #undef TARGET_REGISTER_MOVE_COST
783 #define TARGET_REGISTER_MOVE_COST sparc_register_move_cost
785 #undef TARGET_PROMOTE_FUNCTION_MODE
786 #define TARGET_PROMOTE_FUNCTION_MODE sparc_promote_function_mode
788 #undef TARGET_FUNCTION_VALUE
789 #define TARGET_FUNCTION_VALUE sparc_function_value
790 #undef TARGET_LIBCALL_VALUE
791 #define TARGET_LIBCALL_VALUE sparc_libcall_value
792 #undef TARGET_FUNCTION_VALUE_REGNO_P
793 #define TARGET_FUNCTION_VALUE_REGNO_P sparc_function_value_regno_p
795 #undef TARGET_STRUCT_VALUE_RTX
796 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
797 #undef TARGET_RETURN_IN_MEMORY
798 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
799 #undef TARGET_MUST_PASS_IN_STACK
800 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
801 #undef TARGET_PASS_BY_REFERENCE
802 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
803 #undef TARGET_ARG_PARTIAL_BYTES
804 #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
805 #undef TARGET_FUNCTION_ARG_ADVANCE
806 #define TARGET_FUNCTION_ARG_ADVANCE sparc_function_arg_advance
807 #undef TARGET_FUNCTION_ARG
808 #define TARGET_FUNCTION_ARG sparc_function_arg
809 #undef TARGET_FUNCTION_INCOMING_ARG
810 #define TARGET_FUNCTION_INCOMING_ARG sparc_function_incoming_arg
811 #undef TARGET_FUNCTION_ARG_PADDING
812 #define TARGET_FUNCTION_ARG_PADDING sparc_function_arg_padding
813 #undef TARGET_FUNCTION_ARG_BOUNDARY
814 #define TARGET_FUNCTION_ARG_BOUNDARY sparc_function_arg_boundary
816 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
817 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
818 #undef TARGET_STRICT_ARGUMENT_NAMING
819 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
821 #undef TARGET_EXPAND_BUILTIN_VA_START
822 #define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start
823 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
824 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
826 #undef TARGET_VECTOR_MODE_SUPPORTED_P
827 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
829 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
830 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE sparc_preferred_simd_mode
832 #ifdef SUBTARGET_INSERT_ATTRIBUTES
833 #undef TARGET_INSERT_ATTRIBUTES
834 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
837 #ifdef SUBTARGET_ATTRIBUTE_TABLE
838 #undef TARGET_ATTRIBUTE_TABLE
839 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
842 #undef TARGET_OPTION_OVERRIDE
843 #define TARGET_OPTION_OVERRIDE sparc_option_override
845 #ifdef TARGET_THREAD_SSP_OFFSET
846 #undef TARGET_STACK_PROTECT_GUARD
847 #define TARGET_STACK_PROTECT_GUARD hook_tree_void_null
850 #if TARGET_GNU_TLS && defined(HAVE_AS_SPARC_UA_PCREL)
851 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
852 #define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel
855 #undef TARGET_ASM_FILE_END
856 #define TARGET_ASM_FILE_END sparc_file_end
858 #undef TARGET_FRAME_POINTER_REQUIRED
859 #define TARGET_FRAME_POINTER_REQUIRED sparc_frame_pointer_required
861 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
862 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE sparc_builtin_setjmp_frame_value
864 #undef TARGET_CAN_ELIMINATE
865 #define TARGET_CAN_ELIMINATE sparc_can_eliminate
867 #undef TARGET_PREFERRED_RELOAD_CLASS
868 #define TARGET_PREFERRED_RELOAD_CLASS sparc_preferred_reload_class
870 #undef TARGET_SECONDARY_RELOAD
871 #define TARGET_SECONDARY_RELOAD sparc_secondary_reload
872 #undef TARGET_SECONDARY_MEMORY_NEEDED
873 #define TARGET_SECONDARY_MEMORY_NEEDED sparc_secondary_memory_needed
874 #undef TARGET_SECONDARY_MEMORY_NEEDED_MODE
875 #define TARGET_SECONDARY_MEMORY_NEEDED_MODE sparc_secondary_memory_needed_mode
877 #undef TARGET_CONDITIONAL_REGISTER_USAGE
878 #define TARGET_CONDITIONAL_REGISTER_USAGE sparc_conditional_register_usage
880 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
881 #undef TARGET_MANGLE_TYPE
882 #define TARGET_MANGLE_TYPE sparc_mangle_type
886 #define TARGET_LRA_P sparc_lra_p
888 #undef TARGET_LEGITIMATE_ADDRESS_P
889 #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p
891 #undef TARGET_LEGITIMATE_CONSTANT_P
892 #define TARGET_LEGITIMATE_CONSTANT_P sparc_legitimate_constant_p
894 #undef TARGET_TRAMPOLINE_INIT
895 #define TARGET_TRAMPOLINE_INIT sparc_trampoline_init
897 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
898 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sparc_print_operand_punct_valid_p
899 #undef TARGET_PRINT_OPERAND
900 #define TARGET_PRINT_OPERAND sparc_print_operand
901 #undef TARGET_PRINT_OPERAND_ADDRESS
902 #define TARGET_PRINT_OPERAND_ADDRESS sparc_print_operand_address
904 /* The value stored by LDSTUB. */
905 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
906 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 0xff
908 #undef TARGET_CSTORE_MODE
909 #define TARGET_CSTORE_MODE sparc_cstore_mode
911 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
912 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV sparc_atomic_assign_expand_fenv
914 #undef TARGET_FIXED_CONDITION_CODE_REGS
915 #define TARGET_FIXED_CONDITION_CODE_REGS sparc_fixed_condition_code_regs
917 #undef TARGET_MIN_ARITHMETIC_PRECISION
918 #define TARGET_MIN_ARITHMETIC_PRECISION sparc_min_arithmetic_precision
920 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
921 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
923 #undef TARGET_HARD_REGNO_NREGS
924 #define TARGET_HARD_REGNO_NREGS sparc_hard_regno_nregs
925 #undef TARGET_HARD_REGNO_MODE_OK
926 #define TARGET_HARD_REGNO_MODE_OK sparc_hard_regno_mode_ok
928 #undef TARGET_MODES_TIEABLE_P
929 #define TARGET_MODES_TIEABLE_P sparc_modes_tieable_p
931 #undef TARGET_CAN_CHANGE_MODE_CLASS
932 #define TARGET_CAN_CHANGE_MODE_CLASS sparc_can_change_mode_class
934 #undef TARGET_CONSTANT_ALIGNMENT
935 #define TARGET_CONSTANT_ALIGNMENT sparc_constant_alignment
937 #undef TARGET_VECTORIZE_VEC_PERM_CONST
938 #define TARGET_VECTORIZE_VEC_PERM_CONST sparc_vectorize_vec_perm_const
940 struct gcc_target targetm
= TARGET_INITIALIZER
;
942 /* Return the memory reference contained in X if any, zero otherwise. */
947 if (GET_CODE (x
) == SIGN_EXTEND
|| GET_CODE (x
) == ZERO_EXTEND
)
956 /* True if any of INSN's source register(s) is REG. */
959 insn_uses_reg_p (rtx_insn
*insn
, unsigned int reg
)
962 return ((REG_P (recog_data
.operand
[1])
963 && REGNO (recog_data
.operand
[1]) == reg
)
964 || (recog_data
.n_operands
== 3
965 && REG_P (recog_data
.operand
[2])
966 && REGNO (recog_data
.operand
[2]) == reg
));
969 /* True if INSN is a floating-point division or square-root. */
972 div_sqrt_insn_p (rtx_insn
*insn
)
974 if (GET_CODE (PATTERN (insn
)) != SET
)
977 switch (get_attr_type (insn
))
989 /* True if INSN is a floating-point instruction. */
992 fpop_insn_p (rtx_insn
*insn
)
994 if (GET_CODE (PATTERN (insn
)) != SET
)
997 switch (get_attr_type (insn
))
1014 /* True if INSN is an atomic instruction. */
1017 atomic_insn_for_leon3_p (rtx_insn
*insn
)
1019 switch (INSN_CODE (insn
))
1021 case CODE_FOR_swapsi
:
1022 case CODE_FOR_ldstub
:
1023 case CODE_FOR_atomic_compare_and_swap_leon3_1
:
1030 /* We use a machine specific pass to enable workarounds for errata.
1032 We need to have the (essentially) final form of the insn stream in order
1033 to properly detect the various hazards. Therefore, this machine specific
1034 pass runs as late as possible. */
1036 /* True if INSN is a md pattern or asm statement. */
1037 #define USEFUL_INSN_P(INSN) \
1038 (NONDEBUG_INSN_P (INSN) \
1039 && GET_CODE (PATTERN (INSN)) != USE \
1040 && GET_CODE (PATTERN (INSN)) != CLOBBER)
1043 sparc_do_work_around_errata (void)
1045 rtx_insn
*insn
, *next
;
1047 /* Force all instructions to be split into their final form. */
1048 split_all_insns_noflow ();
1050 /* Now look for specific patterns in the insn stream. */
1051 for (insn
= get_insns (); insn
; insn
= next
)
1053 bool insert_nop
= false;
1058 /* Look into the instruction in a delay slot. */
1059 if (NONJUMP_INSN_P (insn
)
1060 && (seq
= dyn_cast
<rtx_sequence
*> (PATTERN (insn
))))
1062 jump
= seq
->insn (0);
1063 insn
= seq
->insn (1);
1065 else if (JUMP_P (insn
))
1070 /* Place a NOP at the branch target of an integer branch if it is a
1071 floating-point operation or a floating-point branch. */
1072 if (sparc_fix_gr712rc
1074 && jump_to_label_p (jump
)
1075 && get_attr_branch_type (jump
) == BRANCH_TYPE_ICC
)
1077 rtx_insn
*target
= next_active_insn (JUMP_LABEL_AS_INSN (jump
));
1079 && (fpop_insn_p (target
)
1081 && get_attr_branch_type (target
) == BRANCH_TYPE_FCC
)))
1082 emit_insn_before (gen_nop (), target
);
1085 /* Insert a NOP between load instruction and atomic instruction. Insert
1086 a NOP at branch target if there is a load in delay slot and an atomic
1087 instruction at branch target. */
1089 && NONJUMP_INSN_P (insn
)
1090 && (set
= single_set (insn
)) != NULL_RTX
1091 && mem_ref (SET_SRC (set
))
1092 && REG_P (SET_DEST (set
)))
1094 if (jump
&& jump_to_label_p (jump
))
1096 rtx_insn
*target
= next_active_insn (JUMP_LABEL_AS_INSN (jump
));
1097 if (target
&& atomic_insn_for_leon3_p (target
))
1098 emit_insn_before (gen_nop (), target
);
1101 next
= next_active_insn (insn
);
1105 if (atomic_insn_for_leon3_p (next
))
1109 /* Look for a sequence that starts with a fdiv or fsqrt instruction and
1110 ends with another fdiv or fsqrt instruction with no dependencies on
1111 the former, along with an appropriate pattern in between. */
1112 if (sparc_fix_lost_divsqrt
1113 && NONJUMP_INSN_P (insn
)
1114 && div_sqrt_insn_p (insn
))
1120 const unsigned int dest_reg
= REGNO (SET_DEST (single_set (insn
)));
1122 next
= next_active_insn (insn
);
1126 for (after
= next
, i
= 0; i
< 4; i
++)
1128 /* Count floating-point operations. */
1129 if (i
!= 3 && fpop_insn_p (after
))
1131 /* If the insn uses the destination register of
1132 the div/sqrt, then it cannot be problematic. */
1133 if (insn_uses_reg_p (after
, dest_reg
))
1138 /* Count floating-point loads. */
1140 && (set
= single_set (after
)) != NULL_RTX
1141 && REG_P (SET_DEST (set
))
1142 && REGNO (SET_DEST (set
)) > 31)
1144 /* If the insn uses the destination register of
1145 the div/sqrt, then it cannot be problematic. */
1146 if (REGNO (SET_DEST (set
)) == dest_reg
)
1151 /* Check if this is a problematic sequence. */
1154 && div_sqrt_insn_p (after
))
1156 /* If this is the short version of the problematic
1157 sequence we add two NOPs in a row to also prevent
1158 the long version. */
1160 emit_insn_before (gen_nop (), next
);
1165 /* No need to scan past a second div/sqrt. */
1166 if (div_sqrt_insn_p (after
))
1169 /* Insert NOP before branch. */
1171 && (!NONJUMP_INSN_P (after
)
1172 || GET_CODE (PATTERN (after
)) == SEQUENCE
))
1178 after
= next_active_insn (after
);
1184 /* Look for either of these two sequences:
1187 1. store of word size or less (e.g. st / stb / sth / stf)
1188 2. any single instruction that is not a load or store
1189 3. any store instruction (e.g. st / stb / sth / stf / std / stdf)
1192 1. store of double word size (e.g. std / stdf)
1193 2. any store instruction (e.g. st / stb / sth / stf / std / stdf) */
1195 && NONJUMP_INSN_P (insn
)
1196 && (set
= single_set (insn
)) != NULL_RTX
1197 && MEM_P (SET_DEST (set
)))
1199 /* Sequence B begins with a double-word store. */
1200 bool seq_b
= GET_MODE_SIZE (GET_MODE (SET_DEST (set
))) == 8;
1204 next
= next_active_insn (insn
);
1208 for (after
= next
, i
= 0; i
< 2; i
++)
1210 /* Skip empty assembly statements. */
1211 if ((GET_CODE (PATTERN (after
)) == UNSPEC_VOLATILE
)
1212 || (USEFUL_INSN_P (after
)
1213 && (asm_noperands (PATTERN (after
))>=0)
1214 && !strcmp (decode_asm_operands (PATTERN (after
),
1217 after
= next_active_insn (after
);
1221 /* If the insn is a branch, then it cannot be problematic. */
1222 if (!NONJUMP_INSN_P (after
)
1223 || GET_CODE (PATTERN (after
)) == SEQUENCE
)
1226 /* Sequence B is only two instructions long. */
1229 /* Add NOP if followed by a store. */
1230 if ((set
= single_set (after
)) != NULL_RTX
1231 && MEM_P (SET_DEST (set
)))
1234 /* Otherwise it is ok. */
1238 /* If the second instruction is a load or a store,
1239 then the sequence cannot be problematic. */
1242 if ((set
= single_set (after
)) != NULL_RTX
1243 && (MEM_P (SET_DEST (set
)) || mem_ref (SET_SRC (set
))))
1246 after
= next_active_insn (after
);
1251 /* Add NOP if third instruction is a store. */
1253 && (set
= single_set (after
)) != NULL_RTX
1254 && MEM_P (SET_DEST (set
)))
1259 /* Look for a single-word load into an odd-numbered FP register. */
1260 else if (sparc_fix_at697f
1261 && NONJUMP_INSN_P (insn
)
1262 && (set
= single_set (insn
)) != NULL_RTX
1263 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
1264 && mem_ref (SET_SRC (set
))
1265 && REG_P (SET_DEST (set
))
1266 && REGNO (SET_DEST (set
)) > 31
1267 && REGNO (SET_DEST (set
)) % 2 != 0)
1269 /* The wrong dependency is on the enclosing double register. */
1270 const unsigned int x
= REGNO (SET_DEST (set
)) - 1;
1271 unsigned int src1
, src2
, dest
;
1274 next
= next_active_insn (insn
);
1277 /* If the insn is a branch, then it cannot be problematic. */
1278 if (!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) == SEQUENCE
)
1281 extract_insn (next
);
1282 code
= INSN_CODE (next
);
1286 case CODE_FOR_adddf3
:
1287 case CODE_FOR_subdf3
:
1288 case CODE_FOR_muldf3
:
1289 case CODE_FOR_divdf3
:
1290 dest
= REGNO (recog_data
.operand
[0]);
1291 src1
= REGNO (recog_data
.operand
[1]);
1292 src2
= REGNO (recog_data
.operand
[2]);
1297 FPOPd %f{x,y}, %f{y,x}, %f{x,y} */
1298 if ((src1
== x
|| src2
== x
)
1299 && (dest
== src1
|| dest
== src2
))
1306 FPOPd %fx, %fx, %fx */
1309 && (code
== CODE_FOR_adddf3
|| code
== CODE_FOR_muldf3
))
1314 case CODE_FOR_sqrtdf2
:
1315 dest
= REGNO (recog_data
.operand
[0]);
1316 src1
= REGNO (recog_data
.operand
[1]);
1320 if (src1
== x
&& dest
== src1
)
1329 /* Look for a single-word load into an integer register. */
1330 else if (sparc_fix_ut699
1331 && NONJUMP_INSN_P (insn
)
1332 && (set
= single_set (insn
)) != NULL_RTX
1333 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) <= 4
1334 && (mem_ref (SET_SRC (set
)) != NULL_RTX
1335 || INSN_CODE (insn
) == CODE_FOR_movsi_pic_gotdata_op
)
1336 && REG_P (SET_DEST (set
))
1337 && REGNO (SET_DEST (set
)) < 32)
1339 /* There is no problem if the second memory access has a data
1340 dependency on the first single-cycle load. */
1341 rtx x
= SET_DEST (set
);
1343 next
= next_active_insn (insn
);
1346 /* If the insn is a branch, then it cannot be problematic. */
1347 if (!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) == SEQUENCE
)
1350 /* Look for a second memory access to/from an integer register. */
1351 if ((set
= single_set (next
)) != NULL_RTX
)
1353 rtx src
= SET_SRC (set
);
1354 rtx dest
= SET_DEST (set
);
1357 /* LDD is affected. */
1358 if ((mem
= mem_ref (src
)) != NULL_RTX
1360 && REGNO (dest
) < 32
1361 && !reg_mentioned_p (x
, XEXP (mem
, 0)))
1364 /* STD is *not* affected. */
1365 else if (MEM_P (dest
)
1366 && GET_MODE_SIZE (GET_MODE (dest
)) <= 4
1367 && (src
== CONST0_RTX (GET_MODE (dest
))
1370 && REGNO (src
) != REGNO (x
)))
1371 && !reg_mentioned_p (x
, XEXP (dest
, 0)))
1374 /* GOT accesses uses LD. */
1375 else if (INSN_CODE (next
) == CODE_FOR_movsi_pic_gotdata_op
1376 && !reg_mentioned_p (x
, XEXP (XEXP (src
, 0), 1)))
1381 /* Look for a single-word load/operation into an FP register. */
1382 else if (sparc_fix_ut699
1383 && NONJUMP_INSN_P (insn
)
1384 && (set
= single_set (insn
)) != NULL_RTX
1385 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
1386 && REG_P (SET_DEST (set
))
1387 && REGNO (SET_DEST (set
)) > 31)
1389 /* Number of instructions in the problematic window. */
1390 const int n_insns
= 4;
1391 /* The problematic combination is with the sibling FP register. */
1392 const unsigned int x
= REGNO (SET_DEST (set
));
1393 const unsigned int y
= x
^ 1;
1397 next
= next_active_insn (insn
);
1400 /* If the insn is a branch, then it cannot be problematic. */
1401 if (!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) == SEQUENCE
)
1404 /* Look for a second load/operation into the sibling FP register. */
1405 if (!((set
= single_set (next
)) != NULL_RTX
1406 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
1407 && REG_P (SET_DEST (set
))
1408 && REGNO (SET_DEST (set
)) == y
))
1411 /* Look for a (possible) store from the FP register in the next N
1412 instructions, but bail out if it is again modified or if there
1413 is a store from the sibling FP register before this store. */
1414 for (after
= next
, i
= 0; i
< n_insns
; i
++)
1418 after
= next_active_insn (after
);
1422 /* This is a branch with an empty delay slot. */
1423 if (!NONJUMP_INSN_P (after
))
1430 /* This is a branch with a filled delay slot. */
1431 else if (rtx_sequence
*seq
=
1432 dyn_cast
<rtx_sequence
*> (PATTERN (after
)))
1437 after
= seq
->insn (1);
1439 /* This is a regular instruction. */
1443 if (after
&& (set
= single_set (after
)) != NULL_RTX
)
1445 const rtx src
= SET_SRC (set
);
1446 const rtx dest
= SET_DEST (set
);
1447 const unsigned int size
= GET_MODE_SIZE (GET_MODE (dest
));
1449 /* If the FP register is again modified before the store,
1450 then the store isn't affected. */
1452 && (REGNO (dest
) == x
1453 || (REGNO (dest
) == y
&& size
== 8)))
1456 if (MEM_P (dest
) && REG_P (src
))
1458 /* If there is a store from the sibling FP register
1459 before the store, then the store is not affected. */
1460 if (REGNO (src
) == y
|| (REGNO (src
) == x
&& size
== 8))
1463 /* Otherwise, the store is affected. */
1464 if (REGNO (src
) == x
&& size
== 4)
1472 /* If we have a branch in the first M instructions, then we
1473 cannot see the (M+2)th instruction so we play safe. */
1474 if (branch_p
&& i
<= (n_insns
- 2))
1483 next
= NEXT_INSN (insn
);
1486 emit_insn_before (gen_nop (), next
);
1494 const pass_data pass_data_work_around_errata
=
1496 RTL_PASS
, /* type */
1497 "errata", /* name */
1498 OPTGROUP_NONE
, /* optinfo_flags */
1499 TV_MACH_DEP
, /* tv_id */
1500 0, /* properties_required */
1501 0, /* properties_provided */
1502 0, /* properties_destroyed */
1503 0, /* todo_flags_start */
1504 0, /* todo_flags_finish */
1507 class pass_work_around_errata
: public rtl_opt_pass
1510 pass_work_around_errata(gcc::context
*ctxt
)
1511 : rtl_opt_pass(pass_data_work_around_errata
, ctxt
)
1514 /* opt_pass methods: */
1515 virtual bool gate (function
*)
1517 return sparc_fix_at697f
|| sparc_fix_ut699
|| sparc_fix_b2bst
1518 || sparc_fix_gr712rc
|| sparc_fix_ut700
|| sparc_fix_lost_divsqrt
;
1521 virtual unsigned int execute (function
*)
1523 return sparc_do_work_around_errata ();
1526 }; // class pass_work_around_errata
1531 make_pass_work_around_errata (gcc::context
*ctxt
)
1533 return new pass_work_around_errata (ctxt
);
1536 /* Helpers for TARGET_DEBUG_OPTIONS. */
1538 dump_target_flag_bits (const int flags
)
1540 if (flags
& MASK_64BIT
)
1541 fprintf (stderr
, "64BIT ");
1542 if (flags
& MASK_APP_REGS
)
1543 fprintf (stderr
, "APP_REGS ");
1544 if (flags
& MASK_FASTER_STRUCTS
)
1545 fprintf (stderr
, "FASTER_STRUCTS ");
1546 if (flags
& MASK_FLAT
)
1547 fprintf (stderr
, "FLAT ");
1548 if (flags
& MASK_FMAF
)
1549 fprintf (stderr
, "FMAF ");
1550 if (flags
& MASK_FSMULD
)
1551 fprintf (stderr
, "FSMULD ");
1552 if (flags
& MASK_FPU
)
1553 fprintf (stderr
, "FPU ");
1554 if (flags
& MASK_HARD_QUAD
)
1555 fprintf (stderr
, "HARD_QUAD ");
1556 if (flags
& MASK_POPC
)
1557 fprintf (stderr
, "POPC ");
1558 if (flags
& MASK_PTR64
)
1559 fprintf (stderr
, "PTR64 ");
1560 if (flags
& MASK_STACK_BIAS
)
1561 fprintf (stderr
, "STACK_BIAS ");
1562 if (flags
& MASK_UNALIGNED_DOUBLES
)
1563 fprintf (stderr
, "UNALIGNED_DOUBLES ");
1564 if (flags
& MASK_V8PLUS
)
1565 fprintf (stderr
, "V8PLUS ");
1566 if (flags
& MASK_VIS
)
1567 fprintf (stderr
, "VIS ");
1568 if (flags
& MASK_VIS2
)
1569 fprintf (stderr
, "VIS2 ");
1570 if (flags
& MASK_VIS3
)
1571 fprintf (stderr
, "VIS3 ");
1572 if (flags
& MASK_VIS4
)
1573 fprintf (stderr
, "VIS4 ");
1574 if (flags
& MASK_VIS4B
)
1575 fprintf (stderr
, "VIS4B ");
1576 if (flags
& MASK_CBCOND
)
1577 fprintf (stderr
, "CBCOND ");
1578 if (flags
& MASK_DEPRECATED_V8_INSNS
)
1579 fprintf (stderr
, "DEPRECATED_V8_INSNS ");
1580 if (flags
& MASK_SPARCLET
)
1581 fprintf (stderr
, "SPARCLET ");
1582 if (flags
& MASK_SPARCLITE
)
1583 fprintf (stderr
, "SPARCLITE ");
1584 if (flags
& MASK_V8
)
1585 fprintf (stderr
, "V8 ");
1586 if (flags
& MASK_V9
)
1587 fprintf (stderr
, "V9 ");
1591 dump_target_flags (const char *prefix
, const int flags
)
1593 fprintf (stderr
, "%s: (%08x) [ ", prefix
, flags
);
1594 dump_target_flag_bits (flags
);
1595 fprintf(stderr
, "]\n");
1598 /* Validate and override various options, and do some machine dependent
1602 sparc_option_override (void)
1604 static struct code_model
{
1605 const char *const name
;
1606 const enum cmodel value
;
1607 } const cmodels
[] = {
1609 { "medlow", CM_MEDLOW
},
1610 { "medmid", CM_MEDMID
},
1611 { "medany", CM_MEDANY
},
1612 { "embmedany", CM_EMBMEDANY
},
1613 { NULL
, (enum cmodel
) 0 }
1615 const struct code_model
*cmodel
;
1616 /* Map TARGET_CPU_DEFAULT to value for -m{cpu,tune}=. */
1617 static struct cpu_default
{
1619 const enum processor_type processor
;
1620 } const cpu_default
[] = {
1621 /* There must be one entry here for each TARGET_CPU value. */
1622 { TARGET_CPU_sparc
, PROCESSOR_CYPRESS
},
1623 { TARGET_CPU_v8
, PROCESSOR_V8
},
1624 { TARGET_CPU_supersparc
, PROCESSOR_SUPERSPARC
},
1625 { TARGET_CPU_hypersparc
, PROCESSOR_HYPERSPARC
},
1626 { TARGET_CPU_leon
, PROCESSOR_LEON
},
1627 { TARGET_CPU_leon3
, PROCESSOR_LEON3
},
1628 { TARGET_CPU_leon3v7
, PROCESSOR_LEON3V7
},
1629 { TARGET_CPU_sparclite
, PROCESSOR_F930
},
1630 { TARGET_CPU_sparclite86x
, PROCESSOR_SPARCLITE86X
},
1631 { TARGET_CPU_sparclet
, PROCESSOR_TSC701
},
1632 { TARGET_CPU_v9
, PROCESSOR_V9
},
1633 { TARGET_CPU_ultrasparc
, PROCESSOR_ULTRASPARC
},
1634 { TARGET_CPU_ultrasparc3
, PROCESSOR_ULTRASPARC3
},
1635 { TARGET_CPU_niagara
, PROCESSOR_NIAGARA
},
1636 { TARGET_CPU_niagara2
, PROCESSOR_NIAGARA2
},
1637 { TARGET_CPU_niagara3
, PROCESSOR_NIAGARA3
},
1638 { TARGET_CPU_niagara4
, PROCESSOR_NIAGARA4
},
1639 { TARGET_CPU_niagara7
, PROCESSOR_NIAGARA7
},
1640 { TARGET_CPU_m8
, PROCESSOR_M8
},
1641 { -1, PROCESSOR_V7
}
1643 const struct cpu_default
*def
;
1644 /* Table of values for -m{cpu,tune}=. This must match the order of
1645 the enum processor_type in sparc-opts.h. */
1646 static struct cpu_table
{
1647 const char *const name
;
1650 } const cpu_table
[] = {
1651 { "v7", MASK_ISA
|MASK_FSMULD
, 0 },
1652 { "cypress", MASK_ISA
|MASK_FSMULD
, 0 },
1653 { "v8", MASK_ISA
, MASK_V8
},
1654 /* TI TMS390Z55 supersparc */
1655 { "supersparc", MASK_ISA
, MASK_V8
},
1656 { "hypersparc", MASK_ISA
, MASK_V8
},
1657 { "leon", MASK_ISA
|MASK_FSMULD
, MASK_V8
|MASK_LEON
},
1658 { "leon3", MASK_ISA
, MASK_V8
|MASK_LEON3
},
1659 { "leon3v7", MASK_ISA
|MASK_FSMULD
, MASK_LEON3
},
1660 { "sparclite", MASK_ISA
|MASK_FSMULD
, MASK_SPARCLITE
},
1661 /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
1662 { "f930", MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
1663 /* The Fujitsu MB86934 is the recent sparclite chip, with an FPU. */
1664 { "f934", MASK_ISA
|MASK_FSMULD
, MASK_SPARCLITE
},
1665 { "sparclite86x", MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
1666 { "sparclet", MASK_ISA
|MASK_FSMULD
, MASK_SPARCLET
},
1667 /* TEMIC sparclet */
1668 { "tsc701", MASK_ISA
|MASK_FSMULD
, MASK_SPARCLET
},
1669 { "v9", MASK_ISA
, MASK_V9
},
1670 /* UltraSPARC I, II, IIi */
1671 { "ultrasparc", MASK_ISA
,
1672 /* Although insns using %y are deprecated, it is a clear win. */
1673 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
1674 /* UltraSPARC III */
1675 /* ??? Check if %y issue still holds true. */
1676 { "ultrasparc3", MASK_ISA
,
1677 MASK_V9
|MASK_DEPRECATED_V8_INSNS
|MASK_VIS2
},
1679 { "niagara", MASK_ISA
,
1680 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
1682 { "niagara2", MASK_ISA
,
1683 MASK_V9
|MASK_POPC
|MASK_VIS2
},
1685 { "niagara3", MASK_ISA
,
1686 MASK_V9
|MASK_POPC
|MASK_VIS3
|MASK_FMAF
},
1688 { "niagara4", MASK_ISA
,
1689 MASK_V9
|MASK_POPC
|MASK_VIS3
|MASK_FMAF
|MASK_CBCOND
},
1691 { "niagara7", MASK_ISA
,
1692 MASK_V9
|MASK_POPC
|MASK_VIS4
|MASK_FMAF
|MASK_CBCOND
|MASK_SUBXC
},
1695 MASK_V9
|MASK_POPC
|MASK_VIS4
|MASK_FMAF
|MASK_CBCOND
|MASK_SUBXC
|MASK_VIS4B
}
1697 const struct cpu_table
*cpu
;
1700 if (sparc_debug_string
!= NULL
)
1705 p
= ASTRDUP (sparc_debug_string
);
1706 while ((q
= strtok (p
, ",")) != NULL
)
1720 if (! strcmp (q
, "all"))
1721 mask
= MASK_DEBUG_ALL
;
1722 else if (! strcmp (q
, "options"))
1723 mask
= MASK_DEBUG_OPTIONS
;
1725 error ("unknown -mdebug-%s switch", q
);
1728 sparc_debug
&= ~mask
;
1730 sparc_debug
|= mask
;
1734 /* Enable the FsMULd instruction by default if not explicitly specified by
1735 the user. It may be later disabled by the CPU (explicitly or not). */
1736 if (TARGET_FPU
&& !(target_flags_explicit
& MASK_FSMULD
))
1737 target_flags
|= MASK_FSMULD
;
1739 if (TARGET_DEBUG_OPTIONS
)
1741 dump_target_flags("Initial target_flags", target_flags
);
1742 dump_target_flags("target_flags_explicit", target_flags_explicit
);
1745 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1746 SUBTARGET_OVERRIDE_OPTIONS
;
1749 #ifndef SPARC_BI_ARCH
1750 /* Check for unsupported architecture size. */
1751 if (!TARGET_64BIT
!= DEFAULT_ARCH32_P
)
1752 error ("%s is not supported by this configuration",
1753 DEFAULT_ARCH32_P
? "-m64" : "-m32");
1756 /* We force all 64bit archs to use 128 bit long double */
1757 if (TARGET_ARCH64
&& !TARGET_LONG_DOUBLE_128
)
1759 error ("-mlong-double-64 not allowed with -m64");
1760 target_flags
|= MASK_LONG_DOUBLE_128
;
1763 /* Code model selection. */
1764 sparc_cmodel
= SPARC_DEFAULT_CMODEL
;
1766 #ifdef SPARC_BI_ARCH
1768 sparc_cmodel
= CM_32
;
1771 if (sparc_cmodel_string
!= NULL
)
1775 for (cmodel
= &cmodels
[0]; cmodel
->name
; cmodel
++)
1776 if (strcmp (sparc_cmodel_string
, cmodel
->name
) == 0)
1778 if (cmodel
->name
== NULL
)
1779 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string
);
1781 sparc_cmodel
= cmodel
->value
;
1784 error ("-mcmodel= is not supported on 32-bit systems");
1787 /* Check that -fcall-saved-REG wasn't specified for out registers. */
1788 for (i
= 8; i
< 16; i
++)
1789 if (!call_used_regs
[i
])
1791 error ("-fcall-saved-REG is not supported for out registers");
1792 call_used_regs
[i
] = 1;
1795 /* Set the default CPU if no -mcpu option was specified. */
1796 if (!global_options_set
.x_sparc_cpu_and_features
)
1798 for (def
= &cpu_default
[0]; def
->cpu
!= -1; ++def
)
1799 if (def
->cpu
== TARGET_CPU_DEFAULT
)
1801 gcc_assert (def
->cpu
!= -1);
1802 sparc_cpu_and_features
= def
->processor
;
1805 /* Set the default CPU if no -mtune option was specified. */
1806 if (!global_options_set
.x_sparc_cpu
)
1807 sparc_cpu
= sparc_cpu_and_features
;
1809 cpu
= &cpu_table
[(int) sparc_cpu_and_features
];
1811 if (TARGET_DEBUG_OPTIONS
)
1813 fprintf (stderr
, "sparc_cpu_and_features: %s\n", cpu
->name
);
1814 dump_target_flags ("cpu->disable", cpu
->disable
);
1815 dump_target_flags ("cpu->enable", cpu
->enable
);
1818 target_flags
&= ~cpu
->disable
;
1819 target_flags
|= (cpu
->enable
1820 #ifndef HAVE_AS_FMAF_HPC_VIS3
1821 & ~(MASK_FMAF
| MASK_VIS3
)
1823 #ifndef HAVE_AS_SPARC4
1826 #ifndef HAVE_AS_SPARC5_VIS4
1827 & ~(MASK_VIS4
| MASK_SUBXC
)
1829 #ifndef HAVE_AS_SPARC6
1832 #ifndef HAVE_AS_LEON
1833 & ~(MASK_LEON
| MASK_LEON3
)
1835 & ~(target_flags_explicit
& MASK_FEATURES
)
1838 /* -mvis2 implies -mvis. */
1840 target_flags
|= MASK_VIS
;
1842 /* -mvis3 implies -mvis2 and -mvis. */
1844 target_flags
|= MASK_VIS2
| MASK_VIS
;
1846 /* -mvis4 implies -mvis3, -mvis2 and -mvis. */
1848 target_flags
|= MASK_VIS3
| MASK_VIS2
| MASK_VIS
;
1850 /* -mvis4b implies -mvis4, -mvis3, -mvis2 and -mvis */
1852 target_flags
|= MASK_VIS4
| MASK_VIS3
| MASK_VIS2
| MASK_VIS
;
1854 /* Don't allow -mvis, -mvis2, -mvis3, -mvis4, -mvis4b, -mfmaf and -mfsmuld if
1857 target_flags
&= ~(MASK_VIS
| MASK_VIS2
| MASK_VIS3
| MASK_VIS4
1858 | MASK_VIS4B
| MASK_FMAF
| MASK_FSMULD
);
1860 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
1861 are available; -m64 also implies v9. */
1862 if (TARGET_VIS
|| TARGET_ARCH64
)
1864 target_flags
|= MASK_V9
;
1865 target_flags
&= ~(MASK_V8
| MASK_SPARCLET
| MASK_SPARCLITE
);
1868 /* -mvis also implies -mv8plus on 32-bit. */
1869 if (TARGET_VIS
&& !TARGET_ARCH64
)
1870 target_flags
|= MASK_V8PLUS
;
1872 /* Use the deprecated v8 insns for sparc64 in 32-bit mode. */
1873 if (TARGET_V9
&& TARGET_ARCH32
)
1874 target_flags
|= MASK_DEPRECATED_V8_INSNS
;
1876 /* V8PLUS requires V9 and makes no sense in 64-bit mode. */
1877 if (!TARGET_V9
|| TARGET_ARCH64
)
1878 target_flags
&= ~MASK_V8PLUS
;
1880 /* Don't use stack biasing in 32-bit mode. */
1882 target_flags
&= ~MASK_STACK_BIAS
;
1884 /* Use LRA instead of reload, unless otherwise instructed. */
1885 if (!(target_flags_explicit
& MASK_LRA
))
1886 target_flags
|= MASK_LRA
;
1888 /* Enable applicable errata workarounds for LEON3FT. */
1889 if (sparc_fix_ut699
|| sparc_fix_ut700
|| sparc_fix_gr712rc
)
1891 sparc_fix_b2bst
= 1;
1892 sparc_fix_lost_divsqrt
= 1;
1895 /* Disable FsMULd for the UT699 since it doesn't work correctly. */
1896 if (sparc_fix_ut699
)
1897 target_flags
&= ~MASK_FSMULD
;
1899 /* Supply a default value for align_functions. */
1900 if (align_functions
== 0)
1902 if (sparc_cpu
== PROCESSOR_ULTRASPARC
1903 || sparc_cpu
== PROCESSOR_ULTRASPARC3
1904 || sparc_cpu
== PROCESSOR_NIAGARA
1905 || sparc_cpu
== PROCESSOR_NIAGARA2
1906 || sparc_cpu
== PROCESSOR_NIAGARA3
1907 || sparc_cpu
== PROCESSOR_NIAGARA4
)
1908 align_functions
= 32;
1909 else if (sparc_cpu
== PROCESSOR_NIAGARA7
1910 || sparc_cpu
== PROCESSOR_M8
)
1911 align_functions
= 64;
1914 /* Validate PCC_STRUCT_RETURN. */
1915 if (flag_pcc_struct_return
== DEFAULT_PCC_STRUCT_RETURN
)
1916 flag_pcc_struct_return
= (TARGET_ARCH64
? 0 : 1);
1918 /* Only use .uaxword when compiling for a 64-bit target. */
1920 targetm
.asm_out
.unaligned_op
.di
= NULL
;
1922 /* Do various machine dependent initializations. */
1923 sparc_init_modes ();
1925 /* Set up function hooks. */
1926 init_machine_status
= sparc_init_machine_status
;
1931 case PROCESSOR_CYPRESS
:
1932 sparc_costs
= &cypress_costs
;
1935 case PROCESSOR_SPARCLITE
:
1936 case PROCESSOR_SUPERSPARC
:
1937 sparc_costs
= &supersparc_costs
;
1939 case PROCESSOR_F930
:
1940 case PROCESSOR_F934
:
1941 case PROCESSOR_HYPERSPARC
:
1942 case PROCESSOR_SPARCLITE86X
:
1943 sparc_costs
= &hypersparc_costs
;
1945 case PROCESSOR_LEON
:
1946 sparc_costs
= &leon_costs
;
1948 case PROCESSOR_LEON3
:
1949 case PROCESSOR_LEON3V7
:
1950 sparc_costs
= &leon3_costs
;
1952 case PROCESSOR_SPARCLET
:
1953 case PROCESSOR_TSC701
:
1954 sparc_costs
= &sparclet_costs
;
1957 case PROCESSOR_ULTRASPARC
:
1958 sparc_costs
= &ultrasparc_costs
;
1960 case PROCESSOR_ULTRASPARC3
:
1961 sparc_costs
= &ultrasparc3_costs
;
1963 case PROCESSOR_NIAGARA
:
1964 sparc_costs
= &niagara_costs
;
1966 case PROCESSOR_NIAGARA2
:
1967 sparc_costs
= &niagara2_costs
;
1969 case PROCESSOR_NIAGARA3
:
1970 sparc_costs
= &niagara3_costs
;
1972 case PROCESSOR_NIAGARA4
:
1973 sparc_costs
= &niagara4_costs
;
1975 case PROCESSOR_NIAGARA7
:
1976 sparc_costs
= &niagara7_costs
;
1979 sparc_costs
= &m8_costs
;
1981 case PROCESSOR_NATIVE
:
1985 if (sparc_memory_model
== SMM_DEFAULT
)
1987 /* Choose the memory model for the operating system. */
1988 enum sparc_memory_model_type os_default
= SUBTARGET_DEFAULT_MEMORY_MODEL
;
1989 if (os_default
!= SMM_DEFAULT
)
1990 sparc_memory_model
= os_default
;
1991 /* Choose the most relaxed model for the processor. */
1993 sparc_memory_model
= SMM_RMO
;
1994 else if (TARGET_LEON3
)
1995 sparc_memory_model
= SMM_TSO
;
1996 else if (TARGET_LEON
)
1997 sparc_memory_model
= SMM_SC
;
1999 sparc_memory_model
= SMM_PSO
;
2001 sparc_memory_model
= SMM_SC
;
2004 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
2005 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
2006 target_flags
|= MASK_LONG_DOUBLE_128
;
2009 if (TARGET_DEBUG_OPTIONS
)
2010 dump_target_flags ("Final target_flags", target_flags
);
2012 /* PARAM_SIMULTANEOUS_PREFETCHES is the number of prefetches that
2013 can run at the same time. More important, it is the threshold
2014 defining when additional prefetches will be dropped by the
2017 The UltraSPARC-III features a documented prefetch queue with a
2018 size of 8. Additional prefetches issued in the cpu are
2021 Niagara processors are different. In these processors prefetches
2022 are handled much like regular loads. The L1 miss buffer is 32
2023 entries, but prefetches start getting affected when 30 entries
2024 become occupied. That occupation could be a mix of regular loads
2025 and prefetches though. And that buffer is shared by all threads.
2026 Once the threshold is reached, if the core is running a single
2027 thread the prefetch will retry. If more than one thread is
2028 running, the prefetch will be dropped.
2030 All this makes it very difficult to determine how many
2031 simultaneous prefetches can be issued simultaneously, even in a
2032 single-threaded program. Experimental results show that setting
2033 this parameter to 32 works well when the number of threads is not
2035 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
2036 ((sparc_cpu
== PROCESSOR_ULTRASPARC
2037 || sparc_cpu
== PROCESSOR_NIAGARA
2038 || sparc_cpu
== PROCESSOR_NIAGARA2
2039 || sparc_cpu
== PROCESSOR_NIAGARA3
2040 || sparc_cpu
== PROCESSOR_NIAGARA4
)
2042 : (sparc_cpu
== PROCESSOR_ULTRASPARC3
2043 ? 8 : ((sparc_cpu
== PROCESSOR_NIAGARA7
2044 || sparc_cpu
== PROCESSOR_M8
)
2046 global_options
.x_param_values
,
2047 global_options_set
.x_param_values
);
2049 /* PARAM_L1_CACHE_LINE_SIZE is the size of the L1 cache line, in
2052 The Oracle SPARC Architecture (previously the UltraSPARC
2053 Architecture) specification states that when a PREFETCH[A]
2054 instruction is executed an implementation-specific amount of data
2055 is prefetched, and that it is at least 64 bytes long (aligned to
2058 However, this is not correct. The M7 (and implementations prior
2059 to that) does not guarantee a 64B prefetch into a cache if the
2060 line size is smaller. A single cache line is all that is ever
2061 prefetched. So for the M7, where the L1D$ has 32B lines and the
2062 L2D$ and L3 have 64B lines, a prefetch will prefetch 64B into the
2063 L2 and L3, but only 32B are brought into the L1D$. (Assuming it
2064 is a read_n prefetch, which is the only type which allocates to
2066 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
2067 (sparc_cpu
== PROCESSOR_M8
2069 global_options
.x_param_values
,
2070 global_options_set
.x_param_values
);
2072 /* PARAM_L1_CACHE_SIZE is the size of the L1D$ (most SPARC chips use
2073 Hardvard level-1 caches) in kilobytes. Both UltraSPARC and
2074 Niagara processors feature a L1D$ of 16KB. */
2075 maybe_set_param_value (PARAM_L1_CACHE_SIZE
,
2076 ((sparc_cpu
== PROCESSOR_ULTRASPARC
2077 || sparc_cpu
== PROCESSOR_ULTRASPARC3
2078 || sparc_cpu
== PROCESSOR_NIAGARA
2079 || sparc_cpu
== PROCESSOR_NIAGARA2
2080 || sparc_cpu
== PROCESSOR_NIAGARA3
2081 || sparc_cpu
== PROCESSOR_NIAGARA4
2082 || sparc_cpu
== PROCESSOR_NIAGARA7
2083 || sparc_cpu
== PROCESSOR_M8
)
2085 global_options
.x_param_values
,
2086 global_options_set
.x_param_values
);
2089 /* PARAM_L2_CACHE_SIZE is the size fo the L2 in kilobytes. Note
2090 that 512 is the default in params.def. */
2091 maybe_set_param_value (PARAM_L2_CACHE_SIZE
,
2092 ((sparc_cpu
== PROCESSOR_NIAGARA4
2093 || sparc_cpu
== PROCESSOR_M8
)
2094 ? 128 : (sparc_cpu
== PROCESSOR_NIAGARA7
2096 global_options
.x_param_values
,
2097 global_options_set
.x_param_values
);
2100 /* Disable save slot sharing for call-clobbered registers by default.
2101 The IRA sharing algorithm works on single registers only and this
2102 pessimizes for double floating-point registers. */
2103 if (!global_options_set
.x_flag_ira_share_save_slots
)
2104 flag_ira_share_save_slots
= 0;
2106 /* Only enable REE by default in 64-bit mode where it helps to eliminate
2107 redundant 32-to-64-bit extensions. */
2108 if (!global_options_set
.x_flag_ree
&& TARGET_ARCH32
)
2112 /* Miscellaneous utilities. */
2114 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
2115 or branch on register contents instructions. */
2118 v9_regcmp_p (enum rtx_code code
)
2120 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
2121 || code
== LE
|| code
== GT
);
2124 /* Nonzero if OP is a floating point constant which can
2125 be loaded into an integer register using a single
2126 sethi instruction. */
2131 if (GET_CODE (op
) == CONST_DOUBLE
)
2135 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), i
);
2136 return !SPARC_SIMM13_P (i
) && SPARC_SETHI_P (i
);
2142 /* Nonzero if OP is a floating point constant which can
2143 be loaded into an integer register using a single
2149 if (GET_CODE (op
) == CONST_DOUBLE
)
2153 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), i
);
2154 return SPARC_SIMM13_P (i
);
2160 /* Nonzero if OP is a floating point constant which can
2161 be loaded into an integer register using a high/losum
2162 instruction sequence. */
2165 fp_high_losum_p (rtx op
)
2167 /* The constraints calling this should only be in
2168 SFmode move insns, so any constant which cannot
2169 be moved using a single insn will do. */
2170 if (GET_CODE (op
) == CONST_DOUBLE
)
2174 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), i
);
2175 return !SPARC_SIMM13_P (i
) && !SPARC_SETHI_P (i
);
2181 /* Return true if the address of LABEL can be loaded by means of the
2182 mov{si,di}_pic_label_ref patterns in PIC mode. */
2185 can_use_mov_pic_label_ref (rtx label
)
2187 /* VxWorks does not impose a fixed gap between segments; the run-time
2188 gap can be different from the object-file gap. We therefore can't
2189 assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
2190 are absolutely sure that X is in the same segment as the GOT.
2191 Unfortunately, the flexibility of linker scripts means that we
2192 can't be sure of that in general, so assume that GOT-relative
2193 accesses are never valid on VxWorks. */
2194 if (TARGET_VXWORKS_RTP
)
2197 /* Similarly, if the label is non-local, it might end up being placed
2198 in a different section than the current one; now mov_pic_label_ref
2199 requires the label and the code to be in the same section. */
2200 if (LABEL_REF_NONLOCAL_P (label
))
2203 /* Finally, if we are reordering basic blocks and partition into hot
2204 and cold sections, this might happen for any label. */
2205 if (flag_reorder_blocks_and_partition
)
2211 /* Expand a move instruction. Return true if all work is done. */
2214 sparc_expand_move (machine_mode mode
, rtx
*operands
)
2216 /* Handle sets of MEM first. */
2217 if (GET_CODE (operands
[0]) == MEM
)
2219 /* 0 is a register (or a pair of registers) on SPARC. */
2220 if (register_or_zero_operand (operands
[1], mode
))
2223 if (!reload_in_progress
)
2225 operands
[0] = validize_mem (operands
[0]);
2226 operands
[1] = force_reg (mode
, operands
[1]);
2230 /* Fixup TLS cases. */
2232 && CONSTANT_P (operands
[1])
2233 && sparc_tls_referenced_p (operands
[1]))
2235 operands
[1] = sparc_legitimize_tls_address (operands
[1]);
2239 /* Fixup PIC cases. */
2240 if (flag_pic
&& CONSTANT_P (operands
[1]))
2242 if (pic_address_needs_scratch (operands
[1]))
2243 operands
[1] = sparc_legitimize_pic_address (operands
[1], NULL_RTX
);
2245 /* We cannot use the mov{si,di}_pic_label_ref patterns in all cases. */
2246 if (GET_CODE (operands
[1]) == LABEL_REF
2247 && can_use_mov_pic_label_ref (operands
[1]))
2251 emit_insn (gen_movsi_pic_label_ref (operands
[0], operands
[1]));
2257 gcc_assert (TARGET_ARCH64
);
2258 emit_insn (gen_movdi_pic_label_ref (operands
[0], operands
[1]));
2263 if (symbolic_operand (operands
[1], mode
))
2266 = sparc_legitimize_pic_address (operands
[1],
2268 ? operands
[0] : NULL_RTX
);
2273 /* If we are trying to toss an integer constant into FP registers,
2274 or loading a FP or vector constant, force it into memory. */
2275 if (CONSTANT_P (operands
[1])
2276 && REG_P (operands
[0])
2277 && (SPARC_FP_REG_P (REGNO (operands
[0]))
2278 || SCALAR_FLOAT_MODE_P (mode
)
2279 || VECTOR_MODE_P (mode
)))
2281 /* emit_group_store will send such bogosity to us when it is
2282 not storing directly into memory. So fix this up to avoid
2283 crashes in output_constant_pool. */
2284 if (operands
[1] == const0_rtx
)
2285 operands
[1] = CONST0_RTX (mode
);
2287 /* We can clear or set to all-ones FP registers if TARGET_VIS, and
2288 always other regs. */
2289 if ((TARGET_VIS
|| REGNO (operands
[0]) < SPARC_FIRST_FP_REG
)
2290 && (const_zero_operand (operands
[1], mode
)
2291 || const_all_ones_operand (operands
[1], mode
)))
2294 if (REGNO (operands
[0]) < SPARC_FIRST_FP_REG
2295 /* We are able to build any SF constant in integer registers
2296 with at most 2 instructions. */
2298 /* And any DF constant in integer registers if needed. */
2299 || (mode
== DFmode
&& !can_create_pseudo_p ())))
2302 operands
[1] = force_const_mem (mode
, operands
[1]);
2303 if (!reload_in_progress
)
2304 operands
[1] = validize_mem (operands
[1]);
2308 /* Accept non-constants and valid constants unmodified. */
2309 if (!CONSTANT_P (operands
[1])
2310 || GET_CODE (operands
[1]) == HIGH
2311 || input_operand (operands
[1], mode
))
2317 /* All QImode constants require only one insn, so proceed. */
2322 sparc_emit_set_const32 (operands
[0], operands
[1]);
2326 /* input_operand should have filtered out 32-bit mode. */
2327 sparc_emit_set_const64 (operands
[0], operands
[1]);
2333 /* TImode isn't available in 32-bit mode. */
2334 split_double (operands
[1], &high
, &low
);
2335 emit_insn (gen_movdi (operand_subword (operands
[0], 0, 0, TImode
),
2337 emit_insn (gen_movdi (operand_subword (operands
[0], 1, 0, TImode
),
2349 /* Load OP1, a 32-bit constant, into OP0, a register.
2350 We know it can't be done in one insn when we get
2351 here, the move expander guarantees this. */
2354 sparc_emit_set_const32 (rtx op0
, rtx op1
)
2356 machine_mode mode
= GET_MODE (op0
);
2359 if (can_create_pseudo_p ())
2360 temp
= gen_reg_rtx (mode
);
2362 if (GET_CODE (op1
) == CONST_INT
)
2364 gcc_assert (!small_int_operand (op1
, mode
)
2365 && !const_high_operand (op1
, mode
));
2367 /* Emit them as real moves instead of a HIGH/LO_SUM,
2368 this way CSE can see everything and reuse intermediate
2369 values if it wants. */
2370 emit_insn (gen_rtx_SET (temp
, GEN_INT (INTVAL (op1
)
2371 & ~(HOST_WIDE_INT
) 0x3ff)));
2373 emit_insn (gen_rtx_SET (op0
,
2374 gen_rtx_IOR (mode
, temp
,
2375 GEN_INT (INTVAL (op1
) & 0x3ff))));
2379 /* A symbol, emit in the traditional way. */
2380 emit_insn (gen_rtx_SET (temp
, gen_rtx_HIGH (mode
, op1
)));
2381 emit_insn (gen_rtx_SET (op0
, gen_rtx_LO_SUM (mode
, temp
, op1
)));
2385 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
2386 If TEMP is nonzero, we are forbidden to use any other scratch
2387 registers. Otherwise, we are allowed to generate them as needed.
2389 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
2390 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
2393 sparc_emit_set_symbolic_const64 (rtx op0
, rtx op1
, rtx temp
)
2395 rtx cst
, temp1
, temp2
, temp3
, temp4
, temp5
;
2398 /* Deal with too large offsets. */
2399 if (GET_CODE (op1
) == CONST
2400 && GET_CODE (XEXP (op1
, 0)) == PLUS
2401 && CONST_INT_P (cst
= XEXP (XEXP (op1
, 0), 1))
2402 && trunc_int_for_mode (INTVAL (cst
), SImode
) != INTVAL (cst
))
2405 temp1
= gen_reg_rtx (DImode
);
2406 temp2
= gen_reg_rtx (DImode
);
2407 sparc_emit_set_const64 (temp2
, cst
);
2408 sparc_emit_set_symbolic_const64 (temp1
, XEXP (XEXP (op1
, 0), 0),
2410 emit_insn (gen_rtx_SET (op0
, gen_rtx_PLUS (DImode
, temp1
, temp2
)));
2414 if (temp
&& GET_MODE (temp
) == TImode
)
2417 temp
= gen_rtx_REG (DImode
, REGNO (temp
));
2420 /* SPARC-V9 code-model support. */
2421 switch (sparc_cmodel
)
2424 /* The range spanned by all instructions in the object is less
2425 than 2^31 bytes (2GB) and the distance from any instruction
2426 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
2427 than 2^31 bytes (2GB).
2429 The executable must be in the low 4TB of the virtual address
2432 sethi %hi(symbol), %temp1
2433 or %temp1, %lo(symbol), %reg */
2435 temp1
= temp
; /* op0 is allowed. */
2437 temp1
= gen_reg_rtx (DImode
);
2439 emit_insn (gen_rtx_SET (temp1
, gen_rtx_HIGH (DImode
, op1
)));
2440 emit_insn (gen_rtx_SET (op0
, gen_rtx_LO_SUM (DImode
, temp1
, op1
)));
2444 /* The range spanned by all instructions in the object is less
2445 than 2^31 bytes (2GB) and the distance from any instruction
2446 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
2447 than 2^31 bytes (2GB).
2449 The executable must be in the low 16TB of the virtual address
2452 sethi %h44(symbol), %temp1
2453 or %temp1, %m44(symbol), %temp2
2454 sllx %temp2, 12, %temp3
2455 or %temp3, %l44(symbol), %reg */
2460 temp3
= temp
; /* op0 is allowed. */
2464 temp1
= gen_reg_rtx (DImode
);
2465 temp2
= gen_reg_rtx (DImode
);
2466 temp3
= gen_reg_rtx (DImode
);
2469 emit_insn (gen_seth44 (temp1
, op1
));
2470 emit_insn (gen_setm44 (temp2
, temp1
, op1
));
2471 emit_insn (gen_rtx_SET (temp3
,
2472 gen_rtx_ASHIFT (DImode
, temp2
, GEN_INT (12))));
2473 emit_insn (gen_setl44 (op0
, temp3
, op1
));
2477 /* The range spanned by all instructions in the object is less
2478 than 2^31 bytes (2GB) and the distance from any instruction
2479 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
2480 than 2^31 bytes (2GB).
2482 The executable can be placed anywhere in the virtual address
2485 sethi %hh(symbol), %temp1
2486 sethi %lm(symbol), %temp2
2487 or %temp1, %hm(symbol), %temp3
2488 sllx %temp3, 32, %temp4
2489 or %temp4, %temp2, %temp5
2490 or %temp5, %lo(symbol), %reg */
2493 /* It is possible that one of the registers we got for operands[2]
2494 might coincide with that of operands[0] (which is why we made
2495 it TImode). Pick the other one to use as our scratch. */
2496 if (rtx_equal_p (temp
, op0
))
2498 gcc_assert (ti_temp
);
2499 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
2502 temp2
= temp
; /* op0 is _not_ allowed, see above. */
2509 temp1
= gen_reg_rtx (DImode
);
2510 temp2
= gen_reg_rtx (DImode
);
2511 temp3
= gen_reg_rtx (DImode
);
2512 temp4
= gen_reg_rtx (DImode
);
2513 temp5
= gen_reg_rtx (DImode
);
2516 emit_insn (gen_sethh (temp1
, op1
));
2517 emit_insn (gen_setlm (temp2
, op1
));
2518 emit_insn (gen_sethm (temp3
, temp1
, op1
));
2519 emit_insn (gen_rtx_SET (temp4
,
2520 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
2521 emit_insn (gen_rtx_SET (temp5
, gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2522 emit_insn (gen_setlo (op0
, temp5
, op1
));
2526 /* Old old old backwards compatibility kruft here.
2527 Essentially it is MEDLOW with a fixed 64-bit
2528 virtual base added to all data segment addresses.
2529 Text-segment stuff is computed like MEDANY, we can't
2530 reuse the code above because the relocation knobs
2533 Data segment: sethi %hi(symbol), %temp1
2534 add %temp1, EMBMEDANY_BASE_REG, %temp2
2535 or %temp2, %lo(symbol), %reg */
2536 if (data_segment_operand (op1
, GET_MODE (op1
)))
2540 temp1
= temp
; /* op0 is allowed. */
2545 temp1
= gen_reg_rtx (DImode
);
2546 temp2
= gen_reg_rtx (DImode
);
2549 emit_insn (gen_embmedany_sethi (temp1
, op1
));
2550 emit_insn (gen_embmedany_brsum (temp2
, temp1
));
2551 emit_insn (gen_embmedany_losum (op0
, temp2
, op1
));
2554 /* Text segment: sethi %uhi(symbol), %temp1
2555 sethi %hi(symbol), %temp2
2556 or %temp1, %ulo(symbol), %temp3
2557 sllx %temp3, 32, %temp4
2558 or %temp4, %temp2, %temp5
2559 or %temp5, %lo(symbol), %reg */
2564 /* It is possible that one of the registers we got for operands[2]
2565 might coincide with that of operands[0] (which is why we made
2566 it TImode). Pick the other one to use as our scratch. */
2567 if (rtx_equal_p (temp
, op0
))
2569 gcc_assert (ti_temp
);
2570 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
2573 temp2
= temp
; /* op0 is _not_ allowed, see above. */
2580 temp1
= gen_reg_rtx (DImode
);
2581 temp2
= gen_reg_rtx (DImode
);
2582 temp3
= gen_reg_rtx (DImode
);
2583 temp4
= gen_reg_rtx (DImode
);
2584 temp5
= gen_reg_rtx (DImode
);
2587 emit_insn (gen_embmedany_textuhi (temp1
, op1
));
2588 emit_insn (gen_embmedany_texthi (temp2
, op1
));
2589 emit_insn (gen_embmedany_textulo (temp3
, temp1
, op1
));
2590 emit_insn (gen_rtx_SET (temp4
,
2591 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
2592 emit_insn (gen_rtx_SET (temp5
, gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2593 emit_insn (gen_embmedany_textlo (op0
, temp5
, op1
));
2602 /* These avoid problems when cross compiling. If we do not
2603 go through all this hair then the optimizer will see
2604 invalid REG_EQUAL notes or in some cases none at all. */
2605 static rtx
gen_safe_HIGH64 (rtx
, HOST_WIDE_INT
);
2606 static rtx
gen_safe_SET64 (rtx
, HOST_WIDE_INT
);
2607 static rtx
gen_safe_OR64 (rtx
, HOST_WIDE_INT
);
2608 static rtx
gen_safe_XOR64 (rtx
, HOST_WIDE_INT
);
2610 /* The optimizer is not to assume anything about exactly
2611 which bits are set for a HIGH, they are unspecified.
2612 Unfortunately this leads to many missed optimizations
2613 during CSE. We mask out the non-HIGH bits, and matches
2614 a plain movdi, to alleviate this problem. */
2616 gen_safe_HIGH64 (rtx dest
, HOST_WIDE_INT val
)
2618 return gen_rtx_SET (dest
, GEN_INT (val
& ~(HOST_WIDE_INT
)0x3ff));
2622 gen_safe_SET64 (rtx dest
, HOST_WIDE_INT val
)
2624 return gen_rtx_SET (dest
, GEN_INT (val
));
2628 gen_safe_OR64 (rtx src
, HOST_WIDE_INT val
)
2630 return gen_rtx_IOR (DImode
, src
, GEN_INT (val
));
2634 gen_safe_XOR64 (rtx src
, HOST_WIDE_INT val
)
2636 return gen_rtx_XOR (DImode
, src
, GEN_INT (val
));
2639 /* Worker routines for 64-bit constant formation on arch64.
2640 One of the key things to be doing in these emissions is
2641 to create as many temp REGs as possible. This makes it
2642 possible for half-built constants to be used later when
2643 such values are similar to something required later on.
2644 Without doing this, the optimizer cannot see such
2647 static void sparc_emit_set_const64_quick1 (rtx
, rtx
,
2648 unsigned HOST_WIDE_INT
, int);
2651 sparc_emit_set_const64_quick1 (rtx op0
, rtx temp
,
2652 unsigned HOST_WIDE_INT low_bits
, int is_neg
)
2654 unsigned HOST_WIDE_INT high_bits
;
2657 high_bits
= (~low_bits
) & 0xffffffff;
2659 high_bits
= low_bits
;
2661 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
2664 emit_insn (gen_rtx_SET (op0
, gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2668 /* If we are XOR'ing with -1, then we should emit a one's complement
2669 instead. This way the combiner will notice logical operations
2670 such as ANDN later on and substitute. */
2671 if ((low_bits
& 0x3ff) == 0x3ff)
2673 emit_insn (gen_rtx_SET (op0
, gen_rtx_NOT (DImode
, temp
)));
2677 emit_insn (gen_rtx_SET (op0
,
2678 gen_safe_XOR64 (temp
,
2679 (-(HOST_WIDE_INT
)0x400
2680 | (low_bits
& 0x3ff)))));
2685 static void sparc_emit_set_const64_quick2 (rtx
, rtx
, unsigned HOST_WIDE_INT
,
2686 unsigned HOST_WIDE_INT
, int);
2689 sparc_emit_set_const64_quick2 (rtx op0
, rtx temp
,
2690 unsigned HOST_WIDE_INT high_bits
,
2691 unsigned HOST_WIDE_INT low_immediate
,
2696 if ((high_bits
& 0xfffffc00) != 0)
2698 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
2699 if ((high_bits
& ~0xfffffc00) != 0)
2700 emit_insn (gen_rtx_SET (op0
,
2701 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2707 emit_insn (gen_safe_SET64 (temp
, high_bits
));
2711 /* Now shift it up into place. */
2712 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, temp2
,
2713 GEN_INT (shift_count
))));
2715 /* If there is a low immediate part piece, finish up by
2716 putting that in as well. */
2717 if (low_immediate
!= 0)
2718 emit_insn (gen_rtx_SET (op0
, gen_safe_OR64 (op0
, low_immediate
)));
2721 static void sparc_emit_set_const64_longway (rtx
, rtx
, unsigned HOST_WIDE_INT
,
2722 unsigned HOST_WIDE_INT
);
2724 /* Full 64-bit constant decomposition. Even though this is the
2725 'worst' case, we still optimize a few things away. */
2727 sparc_emit_set_const64_longway (rtx op0
, rtx temp
,
2728 unsigned HOST_WIDE_INT high_bits
,
2729 unsigned HOST_WIDE_INT low_bits
)
2733 if (can_create_pseudo_p ())
2734 sub_temp
= gen_reg_rtx (DImode
);
2736 if ((high_bits
& 0xfffffc00) != 0)
2738 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
2739 if ((high_bits
& ~0xfffffc00) != 0)
2740 emit_insn (gen_rtx_SET (sub_temp
,
2741 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2747 emit_insn (gen_safe_SET64 (temp
, high_bits
));
2751 if (can_create_pseudo_p ())
2753 rtx temp2
= gen_reg_rtx (DImode
);
2754 rtx temp3
= gen_reg_rtx (DImode
);
2755 rtx temp4
= gen_reg_rtx (DImode
);
2757 emit_insn (gen_rtx_SET (temp4
, gen_rtx_ASHIFT (DImode
, sub_temp
,
2760 emit_insn (gen_safe_HIGH64 (temp2
, low_bits
));
2761 if ((low_bits
& ~0xfffffc00) != 0)
2763 emit_insn (gen_rtx_SET (temp3
,
2764 gen_safe_OR64 (temp2
, (low_bits
& 0x3ff))));
2765 emit_insn (gen_rtx_SET (op0
, gen_rtx_PLUS (DImode
, temp4
, temp3
)));
2769 emit_insn (gen_rtx_SET (op0
, gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2774 rtx low1
= GEN_INT ((low_bits
>> (32 - 12)) & 0xfff);
2775 rtx low2
= GEN_INT ((low_bits
>> (32 - 12 - 12)) & 0xfff);
2776 rtx low3
= GEN_INT ((low_bits
>> (32 - 12 - 12 - 8)) & 0x0ff);
2779 /* We are in the middle of reload, so this is really
2780 painful. However we do still make an attempt to
2781 avoid emitting truly stupid code. */
2782 if (low1
!= const0_rtx
)
2784 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, sub_temp
,
2785 GEN_INT (to_shift
))));
2786 emit_insn (gen_rtx_SET (op0
, gen_rtx_IOR (DImode
, op0
, low1
)));
2794 if (low2
!= const0_rtx
)
2796 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, sub_temp
,
2797 GEN_INT (to_shift
))));
2798 emit_insn (gen_rtx_SET (op0
, gen_rtx_IOR (DImode
, op0
, low2
)));
2806 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, sub_temp
,
2807 GEN_INT (to_shift
))));
2808 if (low3
!= const0_rtx
)
2809 emit_insn (gen_rtx_SET (op0
, gen_rtx_IOR (DImode
, op0
, low3
)));
2814 /* Analyze a 64-bit constant for certain properties. */
2815 static void analyze_64bit_constant (unsigned HOST_WIDE_INT
,
2816 unsigned HOST_WIDE_INT
,
2817 int *, int *, int *);
2820 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits
,
2821 unsigned HOST_WIDE_INT low_bits
,
2822 int *hbsp
, int *lbsp
, int *abbasp
)
2824 int lowest_bit_set
, highest_bit_set
, all_bits_between_are_set
;
2827 lowest_bit_set
= highest_bit_set
= -1;
2831 if ((lowest_bit_set
== -1)
2832 && ((low_bits
>> i
) & 1))
2834 if ((highest_bit_set
== -1)
2835 && ((high_bits
>> (32 - i
- 1)) & 1))
2836 highest_bit_set
= (64 - i
- 1);
2839 && ((highest_bit_set
== -1)
2840 || (lowest_bit_set
== -1)));
2846 if ((lowest_bit_set
== -1)
2847 && ((high_bits
>> i
) & 1))
2848 lowest_bit_set
= i
+ 32;
2849 if ((highest_bit_set
== -1)
2850 && ((low_bits
>> (32 - i
- 1)) & 1))
2851 highest_bit_set
= 32 - i
- 1;
2854 && ((highest_bit_set
== -1)
2855 || (lowest_bit_set
== -1)));
2857 /* If there are no bits set this should have gone out
2858 as one instruction! */
2859 gcc_assert (lowest_bit_set
!= -1 && highest_bit_set
!= -1);
2860 all_bits_between_are_set
= 1;
2861 for (i
= lowest_bit_set
; i
<= highest_bit_set
; i
++)
2865 if ((low_bits
& (1 << i
)) != 0)
2870 if ((high_bits
& (1 << (i
- 32))) != 0)
2873 all_bits_between_are_set
= 0;
2876 *hbsp
= highest_bit_set
;
2877 *lbsp
= lowest_bit_set
;
2878 *abbasp
= all_bits_between_are_set
;
2881 static int const64_is_2insns (unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
);
2884 const64_is_2insns (unsigned HOST_WIDE_INT high_bits
,
2885 unsigned HOST_WIDE_INT low_bits
)
2887 int highest_bit_set
, lowest_bit_set
, all_bits_between_are_set
;
2890 || high_bits
== 0xffffffff)
2893 analyze_64bit_constant (high_bits
, low_bits
,
2894 &highest_bit_set
, &lowest_bit_set
,
2895 &all_bits_between_are_set
);
2897 if ((highest_bit_set
== 63
2898 || lowest_bit_set
== 0)
2899 && all_bits_between_are_set
!= 0)
2902 if ((highest_bit_set
- lowest_bit_set
) < 21)
2908 static unsigned HOST_WIDE_INT
create_simple_focus_bits (unsigned HOST_WIDE_INT
,
2909 unsigned HOST_WIDE_INT
,
2912 static unsigned HOST_WIDE_INT
2913 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits
,
2914 unsigned HOST_WIDE_INT low_bits
,
2915 int lowest_bit_set
, int shift
)
2917 HOST_WIDE_INT hi
, lo
;
2919 if (lowest_bit_set
< 32)
2921 lo
= (low_bits
>> lowest_bit_set
) << shift
;
2922 hi
= ((high_bits
<< (32 - lowest_bit_set
)) << shift
);
2927 hi
= ((high_bits
>> (lowest_bit_set
- 32)) << shift
);
2929 gcc_assert (! (hi
& lo
));
2933 /* Here we are sure to be arch64 and this is an integer constant
2934 being loaded into a register. Emit the most efficient
2935 insn sequence possible. Detection of all the 1-insn cases
2936 has been done already. */
2938 sparc_emit_set_const64 (rtx op0
, rtx op1
)
2940 unsigned HOST_WIDE_INT high_bits
, low_bits
;
2941 int lowest_bit_set
, highest_bit_set
;
2942 int all_bits_between_are_set
;
2945 /* Sanity check that we know what we are working with. */
2946 gcc_assert (TARGET_ARCH64
2947 && (GET_CODE (op0
) == SUBREG
2948 || (REG_P (op0
) && ! SPARC_FP_REG_P (REGNO (op0
)))));
2950 if (! can_create_pseudo_p ())
2953 if (GET_CODE (op1
) != CONST_INT
)
2955 sparc_emit_set_symbolic_const64 (op0
, op1
, temp
);
2960 temp
= gen_reg_rtx (DImode
);
2962 high_bits
= ((INTVAL (op1
) >> 32) & 0xffffffff);
2963 low_bits
= (INTVAL (op1
) & 0xffffffff);
2965 /* low_bits bits 0 --> 31
2966 high_bits bits 32 --> 63 */
2968 analyze_64bit_constant (high_bits
, low_bits
,
2969 &highest_bit_set
, &lowest_bit_set
,
2970 &all_bits_between_are_set
);
2972 /* First try for a 2-insn sequence. */
2974 /* These situations are preferred because the optimizer can
2975 * do more things with them:
2977 * sllx %reg, shift, %reg
2979 * srlx %reg, shift, %reg
2980 * 3) mov some_small_const, %reg
2981 * sllx %reg, shift, %reg
2983 if (((highest_bit_set
== 63
2984 || lowest_bit_set
== 0)
2985 && all_bits_between_are_set
!= 0)
2986 || ((highest_bit_set
- lowest_bit_set
) < 12))
2988 HOST_WIDE_INT the_const
= -1;
2989 int shift
= lowest_bit_set
;
2991 if ((highest_bit_set
!= 63
2992 && lowest_bit_set
!= 0)
2993 || all_bits_between_are_set
== 0)
2996 create_simple_focus_bits (high_bits
, low_bits
,
2999 else if (lowest_bit_set
== 0)
3000 shift
= -(63 - highest_bit_set
);
3002 gcc_assert (SPARC_SIMM13_P (the_const
));
3003 gcc_assert (shift
!= 0);
3005 emit_insn (gen_safe_SET64 (temp
, the_const
));
3007 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, temp
,
3010 emit_insn (gen_rtx_SET (op0
, gen_rtx_LSHIFTRT (DImode
, temp
,
3011 GEN_INT (-shift
))));
3015 /* Now a range of 22 or less bits set somewhere.
3016 * 1) sethi %hi(focus_bits), %reg
3017 * sllx %reg, shift, %reg
3018 * 2) sethi %hi(focus_bits), %reg
3019 * srlx %reg, shift, %reg
3021 if ((highest_bit_set
- lowest_bit_set
) < 21)
3023 unsigned HOST_WIDE_INT focus_bits
=
3024 create_simple_focus_bits (high_bits
, low_bits
,
3025 lowest_bit_set
, 10);
3027 gcc_assert (SPARC_SETHI_P (focus_bits
));
3028 gcc_assert (lowest_bit_set
!= 10);
3030 emit_insn (gen_safe_HIGH64 (temp
, focus_bits
));
3032 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
3033 if (lowest_bit_set
< 10)
3034 emit_insn (gen_rtx_SET (op0
,
3035 gen_rtx_LSHIFTRT (DImode
, temp
,
3036 GEN_INT (10 - lowest_bit_set
))));
3037 else if (lowest_bit_set
> 10)
3038 emit_insn (gen_rtx_SET (op0
,
3039 gen_rtx_ASHIFT (DImode
, temp
,
3040 GEN_INT (lowest_bit_set
- 10))));
3044 /* 1) sethi %hi(low_bits), %reg
3045 * or %reg, %lo(low_bits), %reg
3046 * 2) sethi %hi(~low_bits), %reg
3047 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
3050 || high_bits
== 0xffffffff)
3052 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
,
3053 (high_bits
== 0xffffffff));
3057 /* Now, try 3-insn sequences. */
3059 /* 1) sethi %hi(high_bits), %reg
3060 * or %reg, %lo(high_bits), %reg
3061 * sllx %reg, 32, %reg
3065 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, 0, 32);
3069 /* We may be able to do something quick
3070 when the constant is negated, so try that. */
3071 if (const64_is_2insns ((~high_bits
) & 0xffffffff,
3072 (~low_bits
) & 0xfffffc00))
3074 /* NOTE: The trailing bits get XOR'd so we need the
3075 non-negated bits, not the negated ones. */
3076 unsigned HOST_WIDE_INT trailing_bits
= low_bits
& 0x3ff;
3078 if ((((~high_bits
) & 0xffffffff) == 0
3079 && ((~low_bits
) & 0x80000000) == 0)
3080 || (((~high_bits
) & 0xffffffff) == 0xffffffff
3081 && ((~low_bits
) & 0x80000000) != 0))
3083 unsigned HOST_WIDE_INT fast_int
= (~low_bits
& 0xffffffff);
3085 if ((SPARC_SETHI_P (fast_int
)
3086 && (~high_bits
& 0xffffffff) == 0)
3087 || SPARC_SIMM13_P (fast_int
))
3088 emit_insn (gen_safe_SET64 (temp
, fast_int
));
3090 sparc_emit_set_const64 (temp
, GEN_INT (fast_int
));
3095 negated_const
= GEN_INT (((~low_bits
) & 0xfffffc00) |
3096 (((HOST_WIDE_INT
)((~high_bits
) & 0xffffffff))<<32));
3097 sparc_emit_set_const64 (temp
, negated_const
);
3100 /* If we are XOR'ing with -1, then we should emit a one's complement
3101 instead. This way the combiner will notice logical operations
3102 such as ANDN later on and substitute. */
3103 if (trailing_bits
== 0x3ff)
3105 emit_insn (gen_rtx_SET (op0
, gen_rtx_NOT (DImode
, temp
)));
3109 emit_insn (gen_rtx_SET (op0
,
3110 gen_safe_XOR64 (temp
,
3111 (-0x400 | trailing_bits
))));
3116 /* 1) sethi %hi(xxx), %reg
3117 * or %reg, %lo(xxx), %reg
3118 * sllx %reg, yyy, %reg
3120 * ??? This is just a generalized version of the low_bits==0
3121 * thing above, FIXME...
3123 if ((highest_bit_set
- lowest_bit_set
) < 32)
3125 unsigned HOST_WIDE_INT focus_bits
=
3126 create_simple_focus_bits (high_bits
, low_bits
,
3129 /* We can't get here in this state. */
3130 gcc_assert (highest_bit_set
>= 32 && lowest_bit_set
< 32);
3132 /* So what we know is that the set bits straddle the
3133 middle of the 64-bit word. */
3134 sparc_emit_set_const64_quick2 (op0
, temp
,
3140 /* 1) sethi %hi(high_bits), %reg
3141 * or %reg, %lo(high_bits), %reg
3142 * sllx %reg, 32, %reg
3143 * or %reg, low_bits, %reg
3145 if (SPARC_SIMM13_P (low_bits
) && ((int)low_bits
> 0))
3147 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_bits
, 32);
3151 /* The easiest way when all else fails, is full decomposition. */
3152 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
);
3155 /* Implement TARGET_FIXED_CONDITION_CODE_REGS. */
3158 sparc_fixed_condition_code_regs (unsigned int *p1
, unsigned int *p2
)
3160 *p1
= SPARC_ICC_REG
;
3161 *p2
= SPARC_FCC_REG
;
3165 /* Implement TARGET_MIN_ARITHMETIC_PRECISION. */
3168 sparc_min_arithmetic_precision (void)
3173 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
3174 return the mode to be used for the comparison. For floating-point,
3175 CCFP[E]mode is used. CCNZmode should be used when the first operand
3176 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
3177 processing is needed. */
3180 select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
3182 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
3208 else if ((GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
3209 || GET_CODE (x
) == NEG
|| GET_CODE (x
) == ASHIFT
)
3212 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
3219 /* This is for the cmp<mode>_sne pattern. */
3220 if (GET_CODE (x
) == NOT
&& y
== constm1_rtx
)
3222 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
3228 /* This is for the [u]addvdi4_sp32 and [u]subvdi4_sp32 patterns. */
3229 if (!TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
3231 if (GET_CODE (y
) == UNSPEC
3232 && (XINT (y
, 1) == UNSPEC_ADDV
3233 || XINT (y
, 1) == UNSPEC_SUBV
3234 || XINT (y
, 1) == UNSPEC_NEGV
))
3240 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
3247 /* Emit the compare insn and return the CC reg for a CODE comparison
3248 with operands X and Y. */
3251 gen_compare_reg_1 (enum rtx_code code
, rtx x
, rtx y
)
3256 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
3259 mode
= SELECT_CC_MODE (code
, x
, y
);
3261 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
3262 fcc regs (cse can't tell they're really call clobbered regs and will
3263 remove a duplicate comparison even if there is an intervening function
3264 call - it will then try to reload the cc reg via an int reg which is why
3265 we need the movcc patterns). It is possible to provide the movcc
3266 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
3267 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
3268 to tell cse that CCFPE mode registers (even pseudos) are call
3271 /* ??? This is an experiment. Rather than making changes to cse which may
3272 or may not be easy/clean, we do our own cse. This is possible because
3273 we will generate hard registers. Cse knows they're call clobbered (it
3274 doesn't know the same thing about pseudos). If we guess wrong, no big
3275 deal, but if we win, great! */
3277 if (TARGET_V9
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
3278 #if 1 /* experiment */
3281 /* We cycle through the registers to ensure they're all exercised. */
3282 static int next_fcc_reg
= 0;
3283 /* Previous x,y for each fcc reg. */
3284 static rtx prev_args
[4][2];
3286 /* Scan prev_args for x,y. */
3287 for (reg
= 0; reg
< 4; reg
++)
3288 if (prev_args
[reg
][0] == x
&& prev_args
[reg
][1] == y
)
3293 prev_args
[reg
][0] = x
;
3294 prev_args
[reg
][1] = y
;
3295 next_fcc_reg
= (next_fcc_reg
+ 1) & 3;
3297 cc_reg
= gen_rtx_REG (mode
, reg
+ SPARC_FIRST_V9_FCC_REG
);
3300 cc_reg
= gen_reg_rtx (mode
);
3301 #endif /* ! experiment */
3302 else if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
3303 cc_reg
= gen_rtx_REG (mode
, SPARC_FCC_REG
);
3305 cc_reg
= gen_rtx_REG (mode
, SPARC_ICC_REG
);
3307 /* We shouldn't get there for TFmode if !TARGET_HARD_QUAD. If we do, this
3308 will only result in an unrecognizable insn so no point in asserting. */
3309 emit_insn (gen_rtx_SET (cc_reg
, gen_rtx_COMPARE (mode
, x
, y
)));
3315 /* Emit the compare insn and return the CC reg for the comparison in CMP. */
3318 gen_compare_reg (rtx cmp
)
3320 return gen_compare_reg_1 (GET_CODE (cmp
), XEXP (cmp
, 0), XEXP (cmp
, 1));
3323 /* This function is used for v9 only.
3324 DEST is the target of the Scc insn.
3325 CODE is the code for an Scc's comparison.
3326 X and Y are the values we compare.
3328 This function is needed to turn
3331 (gt (reg:CCX 100 %icc)
3335 (gt:DI (reg:CCX 100 %icc)
3338 IE: The instruction recognizer needs to see the mode of the comparison to
3339 find the right instruction. We could use "gt:DI" right in the
3340 define_expand, but leaving it out allows us to handle DI, SI, etc. */
3343 gen_v9_scc (rtx dest
, enum rtx_code compare_code
, rtx x
, rtx y
)
3346 && (GET_MODE (x
) == DImode
3347 || GET_MODE (dest
) == DImode
))
3350 /* Try to use the movrCC insns. */
3352 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
3354 && v9_regcmp_p (compare_code
))
3359 /* Special case for op0 != 0. This can be done with one instruction if
3362 if (compare_code
== NE
3363 && GET_MODE (dest
) == DImode
3364 && rtx_equal_p (op0
, dest
))
3366 emit_insn (gen_rtx_SET (dest
,
3367 gen_rtx_IF_THEN_ELSE (DImode
,
3368 gen_rtx_fmt_ee (compare_code
, DImode
,
3375 if (reg_overlap_mentioned_p (dest
, op0
))
3377 /* Handle the case where dest == x.
3378 We "early clobber" the result. */
3379 op0
= gen_reg_rtx (GET_MODE (x
));
3380 emit_move_insn (op0
, x
);
3383 emit_insn (gen_rtx_SET (dest
, const0_rtx
));
3384 if (GET_MODE (op0
) != DImode
)
3386 temp
= gen_reg_rtx (DImode
);
3387 convert_move (temp
, op0
, 0);
3391 emit_insn (gen_rtx_SET (dest
,
3392 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
3393 gen_rtx_fmt_ee (compare_code
, DImode
,
3401 x
= gen_compare_reg_1 (compare_code
, x
, y
);
3404 emit_insn (gen_rtx_SET (dest
, const0_rtx
));
3405 emit_insn (gen_rtx_SET (dest
,
3406 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
3407 gen_rtx_fmt_ee (compare_code
,
3408 GET_MODE (x
), x
, y
),
3409 const1_rtx
, dest
)));
3415 /* Emit an scc insn. For seq, sne, sgeu, and sltu, we can do this
3416 without jumps using the addx/subx instructions. */
3419 emit_scc_insn (rtx operands
[])
3425 /* The quad-word fp compare library routines all return nonzero to indicate
3426 true, which is different from the equivalent libgcc routines, so we must
3427 handle them specially here. */
3428 if (GET_MODE (operands
[2]) == TFmode
&& ! TARGET_HARD_QUAD
)
3430 operands
[1] = sparc_emit_float_lib_cmp (operands
[2], operands
[3],
3431 GET_CODE (operands
[1]));
3432 operands
[2] = XEXP (operands
[1], 0);
3433 operands
[3] = XEXP (operands
[1], 1);
3436 code
= GET_CODE (operands
[1]);
3439 mode
= GET_MODE (x
);
3441 /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has
3442 more applications). The exception to this is "reg != 0" which can
3443 be done in one instruction on v9 (so we do it). */
3444 if ((code
== EQ
|| code
== NE
) && (mode
== SImode
|| mode
== DImode
))
3446 if (y
!= const0_rtx
)
3447 x
= force_reg (mode
, gen_rtx_XOR (mode
, x
, y
));
3449 rtx pat
= gen_rtx_SET (operands
[0],
3450 gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
3453 /* If we can use addx/subx or addxc, add a clobber for CC. */
3454 if (mode
== SImode
|| (code
== NE
&& TARGET_VIS3
))
3457 = gen_rtx_CLOBBER (VOIDmode
,
3458 gen_rtx_REG (mode
== SImode
? CCmode
: CCXmode
,
3460 pat
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, pat
, clobber
));
3467 /* We can do LTU in DImode using the addxc instruction with VIS3. */
3470 && !((code
== LTU
|| code
== GTU
) && TARGET_VIS3
)
3471 && gen_v9_scc (operands
[0], code
, x
, y
))
3474 /* We can do LTU and GEU using the addx/subx instructions too. And
3475 for GTU/LEU, if both operands are registers swap them and fall
3476 back to the easy case. */
3477 if (code
== GTU
|| code
== LEU
)
3479 if ((GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
3480 && (GET_CODE (y
) == REG
|| GET_CODE (y
) == SUBREG
))
3485 code
= swap_condition (code
);
3489 if (code
== LTU
|| code
== GEU
)
3491 emit_insn (gen_rtx_SET (operands
[0],
3492 gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
3493 gen_compare_reg_1 (code
, x
, y
),
3498 /* All the posibilities to use addx/subx based sequences has been
3499 exhausted, try for a 3 instruction sequence using v9 conditional
3501 if (TARGET_V9
&& gen_v9_scc (operands
[0], code
, x
, y
))
3504 /* Nope, do branches. */
3508 /* Emit a conditional jump insn for the v9 architecture using comparison code
3509 CODE and jump target LABEL.
3510 This function exists to take advantage of the v9 brxx insns. */
3513 emit_v9_brxx_insn (enum rtx_code code
, rtx op0
, rtx label
)
3515 emit_jump_insn (gen_rtx_SET (pc_rtx
,
3516 gen_rtx_IF_THEN_ELSE (VOIDmode
,
3517 gen_rtx_fmt_ee (code
, GET_MODE (op0
),
3519 gen_rtx_LABEL_REF (VOIDmode
, label
),
3523 /* Emit a conditional jump insn for the UA2011 architecture using
3524 comparison code CODE and jump target LABEL. This function exists
3525 to take advantage of the UA2011 Compare and Branch insns. */
3528 emit_cbcond_insn (enum rtx_code code
, rtx op0
, rtx op1
, rtx label
)
3532 if_then_else
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
3533 gen_rtx_fmt_ee(code
, GET_MODE(op0
),
3535 gen_rtx_LABEL_REF (VOIDmode
, label
),
3538 emit_jump_insn (gen_rtx_SET (pc_rtx
, if_then_else
));
3542 emit_conditional_branch_insn (rtx operands
[])
3544 /* The quad-word fp compare library routines all return nonzero to indicate
3545 true, which is different from the equivalent libgcc routines, so we must
3546 handle them specially here. */
3547 if (GET_MODE (operands
[1]) == TFmode
&& ! TARGET_HARD_QUAD
)
3549 operands
[0] = sparc_emit_float_lib_cmp (operands
[1], operands
[2],
3550 GET_CODE (operands
[0]));
3551 operands
[1] = XEXP (operands
[0], 0);
3552 operands
[2] = XEXP (operands
[0], 1);
3555 /* If we can tell early on that the comparison is against a constant
3556 that won't fit in the 5-bit signed immediate field of a cbcond,
3557 use one of the other v9 conditional branch sequences. */
3559 && GET_CODE (operands
[1]) == REG
3560 && (GET_MODE (operands
[1]) == SImode
3561 || (TARGET_ARCH64
&& GET_MODE (operands
[1]) == DImode
))
3562 && (GET_CODE (operands
[2]) != CONST_INT
3563 || SPARC_SIMM5_P (INTVAL (operands
[2]))))
3565 emit_cbcond_insn (GET_CODE (operands
[0]), operands
[1], operands
[2], operands
[3]);
3569 if (TARGET_ARCH64
&& operands
[2] == const0_rtx
3570 && GET_CODE (operands
[1]) == REG
3571 && GET_MODE (operands
[1]) == DImode
)
3573 emit_v9_brxx_insn (GET_CODE (operands
[0]), operands
[1], operands
[3]);
3577 operands
[1] = gen_compare_reg (operands
[0]);
3578 operands
[2] = const0_rtx
;
3579 operands
[0] = gen_rtx_fmt_ee (GET_CODE (operands
[0]), VOIDmode
,
3580 operands
[1], operands
[2]);
3581 emit_jump_insn (gen_cbranchcc4 (operands
[0], operands
[1], operands
[2],
3586 /* Generate a DFmode part of a hard TFmode register.
3587 REG is the TFmode hard register, LOW is 1 for the
3588 low 64bit of the register and 0 otherwise.
3591 gen_df_reg (rtx reg
, int low
)
3593 int regno
= REGNO (reg
);
3595 if ((WORDS_BIG_ENDIAN
== 0) ^ (low
!= 0))
3596 regno
+= (TARGET_ARCH64
&& SPARC_INT_REG_P (regno
)) ? 1 : 2;
3597 return gen_rtx_REG (DFmode
, regno
);
3600 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
3601 Unlike normal calls, TFmode operands are passed by reference. It is
3602 assumed that no more than 3 operands are required. */
3605 emit_soft_tfmode_libcall (const char *func_name
, int nargs
, rtx
*operands
)
3607 rtx ret_slot
= NULL
, arg
[3], func_sym
;
3610 /* We only expect to be called for conversions, unary, and binary ops. */
3611 gcc_assert (nargs
== 2 || nargs
== 3);
3613 for (i
= 0; i
< nargs
; ++i
)
3615 rtx this_arg
= operands
[i
];
3618 /* TFmode arguments and return values are passed by reference. */
3619 if (GET_MODE (this_arg
) == TFmode
)
3621 int force_stack_temp
;
3623 force_stack_temp
= 0;
3624 if (TARGET_BUGGY_QP_LIB
&& i
== 0)
3625 force_stack_temp
= 1;
3627 if (GET_CODE (this_arg
) == MEM
3628 && ! force_stack_temp
)
3630 tree expr
= MEM_EXPR (this_arg
);
3632 mark_addressable (expr
);
3633 this_arg
= XEXP (this_arg
, 0);
3635 else if (CONSTANT_P (this_arg
)
3636 && ! force_stack_temp
)
3638 this_slot
= force_const_mem (TFmode
, this_arg
);
3639 this_arg
= XEXP (this_slot
, 0);
3643 this_slot
= assign_stack_temp (TFmode
, GET_MODE_SIZE (TFmode
));
3645 /* Operand 0 is the return value. We'll copy it out later. */
3647 emit_move_insn (this_slot
, this_arg
);
3649 ret_slot
= this_slot
;
3651 this_arg
= XEXP (this_slot
, 0);
3658 func_sym
= gen_rtx_SYMBOL_REF (Pmode
, func_name
);
3660 if (GET_MODE (operands
[0]) == TFmode
)
3663 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
,
3664 arg
[0], GET_MODE (arg
[0]),
3665 arg
[1], GET_MODE (arg
[1]));
3667 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
,
3668 arg
[0], GET_MODE (arg
[0]),
3669 arg
[1], GET_MODE (arg
[1]),
3670 arg
[2], GET_MODE (arg
[2]));
3673 emit_move_insn (operands
[0], ret_slot
);
3679 gcc_assert (nargs
== 2);
3681 ret
= emit_library_call_value (func_sym
, operands
[0], LCT_NORMAL
,
3682 GET_MODE (operands
[0]),
3683 arg
[1], GET_MODE (arg
[1]));
3685 if (ret
!= operands
[0])
3686 emit_move_insn (operands
[0], ret
);
3690 /* Expand soft-float TFmode calls to sparc abi routines. */
3693 emit_soft_tfmode_binop (enum rtx_code code
, rtx
*operands
)
3715 emit_soft_tfmode_libcall (func
, 3, operands
);
3719 emit_soft_tfmode_unop (enum rtx_code code
, rtx
*operands
)
3723 gcc_assert (code
== SQRT
);
3726 emit_soft_tfmode_libcall (func
, 2, operands
);
3730 emit_soft_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
3737 switch (GET_MODE (operands
[1]))
3750 case FLOAT_TRUNCATE
:
3751 switch (GET_MODE (operands
[0]))
3765 switch (GET_MODE (operands
[1]))
3770 operands
[1] = gen_rtx_SIGN_EXTEND (DImode
, operands
[1]);
3780 case UNSIGNED_FLOAT
:
3781 switch (GET_MODE (operands
[1]))
3786 operands
[1] = gen_rtx_ZERO_EXTEND (DImode
, operands
[1]);
3797 switch (GET_MODE (operands
[0]))
3811 switch (GET_MODE (operands
[0]))
3828 emit_soft_tfmode_libcall (func
, 2, operands
);
3831 /* Expand a hard-float tfmode operation. All arguments must be in
3835 emit_hard_tfmode_operation (enum rtx_code code
, rtx
*operands
)
3839 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
3841 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
3842 op
= gen_rtx_fmt_e (code
, GET_MODE (operands
[0]), operands
[1]);
3846 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
3847 operands
[2] = force_reg (GET_MODE (operands
[2]), operands
[2]);
3848 op
= gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
3849 operands
[1], operands
[2]);
3852 if (register_operand (operands
[0], VOIDmode
))
3855 dest
= gen_reg_rtx (GET_MODE (operands
[0]));
3857 emit_insn (gen_rtx_SET (dest
, op
));
3859 if (dest
!= operands
[0])
3860 emit_move_insn (operands
[0], dest
);
3864 emit_tfmode_binop (enum rtx_code code
, rtx
*operands
)
3866 if (TARGET_HARD_QUAD
)
3867 emit_hard_tfmode_operation (code
, operands
);
3869 emit_soft_tfmode_binop (code
, operands
);
3873 emit_tfmode_unop (enum rtx_code code
, rtx
*operands
)
3875 if (TARGET_HARD_QUAD
)
3876 emit_hard_tfmode_operation (code
, operands
);
3878 emit_soft_tfmode_unop (code
, operands
);
3882 emit_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
3884 if (TARGET_HARD_QUAD
)
3885 emit_hard_tfmode_operation (code
, operands
);
3887 emit_soft_tfmode_cvt (code
, operands
);
3890 /* Return nonzero if a branch/jump/call instruction will be emitting
3891 nop into its delay slot. */
3894 empty_delay_slot (rtx_insn
*insn
)
3898 /* If no previous instruction (should not happen), return true. */
3899 if (PREV_INSN (insn
) == NULL
)
3902 seq
= NEXT_INSN (PREV_INSN (insn
));
3903 if (GET_CODE (PATTERN (seq
)) == SEQUENCE
)
3909 /* Return nonzero if we should emit a nop after a cbcond instruction.
3910 The cbcond instruction does not have a delay slot, however there is
3911 a severe performance penalty if a control transfer appears right
3912 after a cbcond. Therefore we emit a nop when we detect this
3916 emit_cbcond_nop (rtx_insn
*insn
)
3918 rtx next
= next_active_insn (insn
);
3923 if (NONJUMP_INSN_P (next
)
3924 && GET_CODE (PATTERN (next
)) == SEQUENCE
)
3925 next
= XVECEXP (PATTERN (next
), 0, 0);
3926 else if (CALL_P (next
)
3927 && GET_CODE (PATTERN (next
)) == PARALLEL
)
3929 rtx delay
= XVECEXP (PATTERN (next
), 0, 1);
3931 if (GET_CODE (delay
) == RETURN
)
3933 /* It's a sibling call. Do not emit the nop if we're going
3934 to emit something other than the jump itself as the first
3935 instruction of the sibcall sequence. */
3936 if (sparc_leaf_function_p
|| TARGET_FLAT
)
3941 if (NONJUMP_INSN_P (next
))
3947 /* Return nonzero if TRIAL can go into the call delay slot. */
3950 eligible_for_call_delay (rtx_insn
*trial
)
3954 if (get_attr_in_branch_delay (trial
) == IN_BRANCH_DELAY_FALSE
)
3958 call __tls_get_addr, %tgd_call (foo)
3959 add %l7, %o0, %o0, %tgd_add (foo)
3960 while Sun as/ld does not. */
3961 if (TARGET_GNU_TLS
|| !TARGET_TLS
)
3964 pat
= PATTERN (trial
);
3966 /* We must reject tgd_add{32|64}, i.e.
3967 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD)))
3968 and tldm_add{32|64}, i.e.
3969 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM)))
3971 if (GET_CODE (pat
) == SET
3972 && GET_CODE (SET_SRC (pat
)) == PLUS
)
3974 rtx unspec
= XEXP (SET_SRC (pat
), 1);
3976 if (GET_CODE (unspec
) == UNSPEC
3977 && (XINT (unspec
, 1) == UNSPEC_TLSGD
3978 || XINT (unspec
, 1) == UNSPEC_TLSLDM
))
3985 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
3986 instruction. RETURN_P is true if the v9 variant 'return' is to be
3987 considered in the test too.
3989 TRIAL must be a SET whose destination is a REG appropriate for the
3990 'restore' instruction or, if RETURN_P is true, for the 'return'
3994 eligible_for_restore_insn (rtx trial
, bool return_p
)
3996 rtx pat
= PATTERN (trial
);
3997 rtx src
= SET_SRC (pat
);
3998 bool src_is_freg
= false;
4001 /* Since we now can do moves between float and integer registers when
4002 VIS3 is enabled, we have to catch this case. We can allow such
4003 moves when doing a 'return' however. */
4005 if (GET_CODE (src_reg
) == SUBREG
)
4006 src_reg
= SUBREG_REG (src_reg
);
4007 if (GET_CODE (src_reg
) == REG
4008 && SPARC_FP_REG_P (REGNO (src_reg
)))
4011 /* The 'restore src,%g0,dest' pattern for word mode and below. */
4012 if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
4013 && arith_operand (src
, GET_MODE (src
))
4017 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
4019 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
4022 /* The 'restore src,%g0,dest' pattern for double-word mode. */
4023 else if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
4024 && arith_double_operand (src
, GET_MODE (src
))
4026 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
4028 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
4029 else if (! TARGET_FPU
&& register_operand (src
, SFmode
))
4032 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
4033 else if (! TARGET_FPU
&& TARGET_ARCH64
&& register_operand (src
, DFmode
))
4036 /* If we have the 'return' instruction, anything that does not use
4037 local or output registers and can go into a delay slot wins. */
4038 else if (return_p
&& TARGET_V9
&& !epilogue_renumber (&pat
, 1))
4041 /* The 'restore src1,src2,dest' pattern for SImode. */
4042 else if (GET_CODE (src
) == PLUS
4043 && register_operand (XEXP (src
, 0), SImode
)
4044 && arith_operand (XEXP (src
, 1), SImode
))
4047 /* The 'restore src1,src2,dest' pattern for DImode. */
4048 else if (GET_CODE (src
) == PLUS
4049 && register_operand (XEXP (src
, 0), DImode
)
4050 && arith_double_operand (XEXP (src
, 1), DImode
))
4053 /* The 'restore src1,%lo(src2),dest' pattern. */
4054 else if (GET_CODE (src
) == LO_SUM
4055 && ! TARGET_CM_MEDMID
4056 && ((register_operand (XEXP (src
, 0), SImode
)
4057 && immediate_operand (XEXP (src
, 1), SImode
))
4059 && register_operand (XEXP (src
, 0), DImode
)
4060 && immediate_operand (XEXP (src
, 1), DImode
))))
4063 /* The 'restore src,src,dest' pattern. */
4064 else if (GET_CODE (src
) == ASHIFT
4065 && (register_operand (XEXP (src
, 0), SImode
)
4066 || register_operand (XEXP (src
, 0), DImode
))
4067 && XEXP (src
, 1) == const1_rtx
)
4073 /* Return nonzero if TRIAL can go into the function return's delay slot. */
4076 eligible_for_return_delay (rtx_insn
*trial
)
4081 /* If the function uses __builtin_eh_return, the eh_return machinery
4082 occupies the delay slot. */
4083 if (crtl
->calls_eh_return
)
4086 if (get_attr_in_branch_delay (trial
) == IN_BRANCH_DELAY_FALSE
)
4089 /* In the case of a leaf or flat function, anything can go into the slot. */
4090 if (sparc_leaf_function_p
|| TARGET_FLAT
)
4093 if (!NONJUMP_INSN_P (trial
))
4096 pat
= PATTERN (trial
);
4097 if (GET_CODE (pat
) == PARALLEL
)
4103 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
4105 rtx expr
= XVECEXP (pat
, 0, i
);
4106 if (GET_CODE (expr
) != SET
)
4108 if (GET_CODE (SET_DEST (expr
)) != REG
)
4110 regno
= REGNO (SET_DEST (expr
));
4111 if (regno
>= 8 && regno
< 24)
4114 return !epilogue_renumber (&pat
, 1);
4117 if (GET_CODE (pat
) != SET
)
4120 if (GET_CODE (SET_DEST (pat
)) != REG
)
4123 regno
= REGNO (SET_DEST (pat
));
4125 /* Otherwise, only operations which can be done in tandem with
4126 a `restore' or `return' insn can go into the delay slot. */
4127 if (regno
>= 8 && regno
< 24)
4130 /* If this instruction sets up floating point register and we have a return
4131 instruction, it can probably go in. But restore will not work
4133 if (! SPARC_INT_REG_P (regno
))
4134 return TARGET_V9
&& !epilogue_renumber (&pat
, 1);
4136 return eligible_for_restore_insn (trial
, true);
4139 /* Return nonzero if TRIAL can go into the sibling call's delay slot. */
4142 eligible_for_sibcall_delay (rtx_insn
*trial
)
4146 if (get_attr_in_branch_delay (trial
) == IN_BRANCH_DELAY_FALSE
)
4149 if (!NONJUMP_INSN_P (trial
))
4152 pat
= PATTERN (trial
);
4154 if (sparc_leaf_function_p
|| TARGET_FLAT
)
4156 /* If the tail call is done using the call instruction,
4157 we have to restore %o7 in the delay slot. */
4158 if (LEAF_SIBCALL_SLOT_RESERVED_P
)
4161 /* %g1 is used to build the function address */
4162 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 1), pat
))
4168 if (GET_CODE (pat
) != SET
)
4171 /* Otherwise, only operations which can be done in tandem with
4172 a `restore' insn can go into the delay slot. */
4173 if (GET_CODE (SET_DEST (pat
)) != REG
4174 || (REGNO (SET_DEST (pat
)) >= 8 && REGNO (SET_DEST (pat
)) < 24)
4175 || ! SPARC_INT_REG_P (REGNO (SET_DEST (pat
))))
4178 /* If it mentions %o7, it can't go in, because sibcall will clobber it
4180 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 15), pat
))
4183 return eligible_for_restore_insn (trial
, false);
4186 /* Determine if it's legal to put X into the constant pool. This
4187 is not possible if X contains the address of a symbol that is
4188 not constant (TLS) or not known at final link time (PIC). */
4191 sparc_cannot_force_const_mem (machine_mode mode
, rtx x
)
4193 switch (GET_CODE (x
))
4196 case CONST_WIDE_INT
:
4199 /* Accept all non-symbolic constants. */
4203 /* Labels are OK iff we are non-PIC. */
4204 return flag_pic
!= 0;
4207 /* 'Naked' TLS symbol references are never OK,
4208 non-TLS symbols are OK iff we are non-PIC. */
4209 if (SYMBOL_REF_TLS_MODEL (x
))
4212 return flag_pic
!= 0;
4215 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0));
4218 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0))
4219 || sparc_cannot_force_const_mem (mode
, XEXP (x
, 1));
4227 /* Global Offset Table support. */
4228 static GTY(()) rtx got_helper_rtx
= NULL_RTX
;
4229 static GTY(()) rtx global_offset_table_rtx
= NULL_RTX
;
4231 /* Return the SYMBOL_REF for the Global Offset Table. */
4233 static GTY(()) rtx sparc_got_symbol
= NULL_RTX
;
4238 if (!sparc_got_symbol
)
4239 sparc_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
4241 return sparc_got_symbol
;
4244 /* Ensure that we are not using patterns that are not OK with PIC. */
4254 op
= recog_data
.operand
[i
];
4255 gcc_assert (GET_CODE (op
) != SYMBOL_REF
4256 && (GET_CODE (op
) != CONST
4257 || (GET_CODE (XEXP (op
, 0)) == MINUS
4258 && XEXP (XEXP (op
, 0), 0) == sparc_got ()
4259 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST
)));
4267 /* Return true if X is an address which needs a temporary register when
4268 reloaded while generating PIC code. */
4271 pic_address_needs_scratch (rtx x
)
4273 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
4274 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
4275 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
4276 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4277 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
4283 /* Determine if a given RTX is a valid constant. We already know this
4284 satisfies CONSTANT_P. */
4287 sparc_legitimate_constant_p (machine_mode mode
, rtx x
)
4289 switch (GET_CODE (x
))
4293 if (sparc_tls_referenced_p (x
))
4298 /* Floating point constants are generally not ok.
4299 The only exception is 0.0 and all-ones in VIS. */
4301 && SCALAR_FLOAT_MODE_P (mode
)
4302 && (const_zero_operand (x
, mode
)
4303 || const_all_ones_operand (x
, mode
)))
4309 /* Vector constants are generally not ok.
4310 The only exception is 0 or -1 in VIS. */
4312 && (const_zero_operand (x
, mode
)
4313 || const_all_ones_operand (x
, mode
)))
4325 /* Determine if a given RTX is a valid constant address. */
4328 constant_address_p (rtx x
)
4330 switch (GET_CODE (x
))
4338 if (flag_pic
&& pic_address_needs_scratch (x
))
4340 return sparc_legitimate_constant_p (Pmode
, x
);
4343 return !flag_pic
&& sparc_legitimate_constant_p (Pmode
, x
);
4350 /* Nonzero if the constant value X is a legitimate general operand
4351 when generating PIC code. It is given that flag_pic is on and
4352 that X satisfies CONSTANT_P. */
4355 legitimate_pic_operand_p (rtx x
)
4357 if (pic_address_needs_scratch (x
))
4359 if (sparc_tls_referenced_p (x
))
4364 #define RTX_OK_FOR_OFFSET_P(X, MODE) \
4366 && INTVAL (X) >= -0x1000 \
4367 && INTVAL (X) <= (0x1000 - GET_MODE_SIZE (MODE)))
4369 #define RTX_OK_FOR_OLO10_P(X, MODE) \
4371 && INTVAL (X) >= -0x1000 \
4372 && INTVAL (X) <= (0xc00 - GET_MODE_SIZE (MODE)))
4374 /* Handle the TARGET_LEGITIMATE_ADDRESS_P target hook.
4376 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
4377 ordinarily. This changes a bit when generating PIC. */
4380 sparc_legitimate_address_p (machine_mode mode
, rtx addr
, bool strict
)
4382 rtx rs1
= NULL
, rs2
= NULL
, imm1
= NULL
;
4384 if (REG_P (addr
) || GET_CODE (addr
) == SUBREG
)
4386 else if (GET_CODE (addr
) == PLUS
)
4388 rs1
= XEXP (addr
, 0);
4389 rs2
= XEXP (addr
, 1);
4391 /* Canonicalize. REG comes first, if there are no regs,
4392 LO_SUM comes first. */
4394 && GET_CODE (rs1
) != SUBREG
4396 || GET_CODE (rs2
) == SUBREG
4397 || (GET_CODE (rs2
) == LO_SUM
&& GET_CODE (rs1
) != LO_SUM
)))
4399 rs1
= XEXP (addr
, 1);
4400 rs2
= XEXP (addr
, 0);
4404 && rs1
== pic_offset_table_rtx
4406 && GET_CODE (rs2
) != SUBREG
4407 && GET_CODE (rs2
) != LO_SUM
4408 && GET_CODE (rs2
) != MEM
4409 && !(GET_CODE (rs2
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs2
))
4410 && (! symbolic_operand (rs2
, VOIDmode
) || mode
== Pmode
)
4411 && (GET_CODE (rs2
) != CONST_INT
|| SMALL_INT (rs2
)))
4413 || GET_CODE (rs1
) == SUBREG
)
4414 && RTX_OK_FOR_OFFSET_P (rs2
, mode
)))
4419 else if ((REG_P (rs1
) || GET_CODE (rs1
) == SUBREG
)
4420 && (REG_P (rs2
) || GET_CODE (rs2
) == SUBREG
))
4422 /* We prohibit REG + REG for TFmode when there are no quad move insns
4423 and we consequently need to split. We do this because REG+REG
4424 is not an offsettable address. If we get the situation in reload
4425 where source and destination of a movtf pattern are both MEMs with
4426 REG+REG address, then only one of them gets converted to an
4427 offsettable address. */
4429 && ! (TARGET_ARCH64
&& TARGET_HARD_QUAD
))
4432 /* Likewise for TImode, but in all cases. */
4436 /* We prohibit REG + REG on ARCH32 if not optimizing for
4437 DFmode/DImode because then mem_min_alignment is likely to be zero
4438 after reload and the forced split would lack a matching splitter
4440 if (TARGET_ARCH32
&& !optimize
4441 && (mode
== DFmode
|| mode
== DImode
))
4444 else if (USE_AS_OFFSETABLE_LO10
4445 && GET_CODE (rs1
) == LO_SUM
4447 && ! TARGET_CM_MEDMID
4448 && RTX_OK_FOR_OLO10_P (rs2
, mode
))
4451 imm1
= XEXP (rs1
, 1);
4452 rs1
= XEXP (rs1
, 0);
4453 if (!CONSTANT_P (imm1
)
4454 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
4458 else if (GET_CODE (addr
) == LO_SUM
)
4460 rs1
= XEXP (addr
, 0);
4461 imm1
= XEXP (addr
, 1);
4463 if (!CONSTANT_P (imm1
)
4464 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
4467 /* We can't allow TFmode in 32-bit mode, because an offset greater
4468 than the alignment (8) may cause the LO_SUM to overflow. */
4469 if (mode
== TFmode
&& TARGET_ARCH32
)
4472 /* During reload, accept the HIGH+LO_SUM construct generated by
4473 sparc_legitimize_reload_address. */
4474 if (reload_in_progress
4475 && GET_CODE (rs1
) == HIGH
4476 && XEXP (rs1
, 0) == imm1
)
4479 else if (GET_CODE (addr
) == CONST_INT
&& SMALL_INT (addr
))
4484 if (GET_CODE (rs1
) == SUBREG
)
4485 rs1
= SUBREG_REG (rs1
);
4491 if (GET_CODE (rs2
) == SUBREG
)
4492 rs2
= SUBREG_REG (rs2
);
4499 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1
))
4500 || (rs2
&& !REGNO_OK_FOR_BASE_P (REGNO (rs2
))))
4505 if ((! SPARC_INT_REG_P (REGNO (rs1
))
4506 && REGNO (rs1
) != FRAME_POINTER_REGNUM
4507 && REGNO (rs1
) < FIRST_PSEUDO_REGISTER
)
4509 && (! SPARC_INT_REG_P (REGNO (rs2
))
4510 && REGNO (rs2
) != FRAME_POINTER_REGNUM
4511 && REGNO (rs2
) < FIRST_PSEUDO_REGISTER
)))
4517 /* Return the SYMBOL_REF for the tls_get_addr function. */
4519 static GTY(()) rtx sparc_tls_symbol
= NULL_RTX
;
4522 sparc_tls_get_addr (void)
4524 if (!sparc_tls_symbol
)
4525 sparc_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
4527 return sparc_tls_symbol
;
4530 /* Return the Global Offset Table to be used in TLS mode. */
4533 sparc_tls_got (void)
4535 /* In PIC mode, this is just the PIC offset table. */
4538 crtl
->uses_pic_offset_table
= 1;
4539 return pic_offset_table_rtx
;
4542 /* In non-PIC mode, Sun as (unlike GNU as) emits PC-relative relocations for
4543 the GOT symbol with the 32-bit ABI, so we reload the GOT register. */
4544 if (TARGET_SUN_TLS
&& TARGET_ARCH32
)
4546 load_got_register ();
4547 return global_offset_table_rtx
;
4550 /* In all other cases, we load a new pseudo with the GOT symbol. */
4551 return copy_to_reg (sparc_got ());
4554 /* Return true if X contains a thread-local symbol. */
4557 sparc_tls_referenced_p (rtx x
)
4559 if (!TARGET_HAVE_TLS
)
4562 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
4563 x
= XEXP (XEXP (x
, 0), 0);
4565 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
))
4568 /* That's all we handle in sparc_legitimize_tls_address for now. */
4572 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
4573 this (thread-local) address. */
4576 sparc_legitimize_tls_address (rtx addr
)
4578 rtx temp1
, temp2
, temp3
, ret
, o0
, got
;
4581 gcc_assert (can_create_pseudo_p ());
4583 if (GET_CODE (addr
) == SYMBOL_REF
)
4584 switch (SYMBOL_REF_TLS_MODEL (addr
))
4586 case TLS_MODEL_GLOBAL_DYNAMIC
:
4588 temp1
= gen_reg_rtx (SImode
);
4589 temp2
= gen_reg_rtx (SImode
);
4590 ret
= gen_reg_rtx (Pmode
);
4591 o0
= gen_rtx_REG (Pmode
, 8);
4592 got
= sparc_tls_got ();
4593 emit_insn (gen_tgd_hi22 (temp1
, addr
));
4594 emit_insn (gen_tgd_lo10 (temp2
, temp1
, addr
));
4597 emit_insn (gen_tgd_add32 (o0
, got
, temp2
, addr
));
4598 insn
= emit_call_insn (gen_tgd_call32 (o0
, sparc_tls_get_addr (),
4603 emit_insn (gen_tgd_add64 (o0
, got
, temp2
, addr
));
4604 insn
= emit_call_insn (gen_tgd_call64 (o0
, sparc_tls_get_addr (),
4607 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
4608 insn
= get_insns ();
4610 emit_libcall_block (insn
, ret
, o0
, addr
);
4613 case TLS_MODEL_LOCAL_DYNAMIC
:
4615 temp1
= gen_reg_rtx (SImode
);
4616 temp2
= gen_reg_rtx (SImode
);
4617 temp3
= gen_reg_rtx (Pmode
);
4618 ret
= gen_reg_rtx (Pmode
);
4619 o0
= gen_rtx_REG (Pmode
, 8);
4620 got
= sparc_tls_got ();
4621 emit_insn (gen_tldm_hi22 (temp1
));
4622 emit_insn (gen_tldm_lo10 (temp2
, temp1
));
4625 emit_insn (gen_tldm_add32 (o0
, got
, temp2
));
4626 insn
= emit_call_insn (gen_tldm_call32 (o0
, sparc_tls_get_addr (),
4631 emit_insn (gen_tldm_add64 (o0
, got
, temp2
));
4632 insn
= emit_call_insn (gen_tldm_call64 (o0
, sparc_tls_get_addr (),
4635 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
4636 insn
= get_insns ();
4638 emit_libcall_block (insn
, temp3
, o0
,
4639 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
4640 UNSPEC_TLSLD_BASE
));
4641 temp1
= gen_reg_rtx (SImode
);
4642 temp2
= gen_reg_rtx (SImode
);
4643 emit_insn (gen_tldo_hix22 (temp1
, addr
));
4644 emit_insn (gen_tldo_lox10 (temp2
, temp1
, addr
));
4646 emit_insn (gen_tldo_add32 (ret
, temp3
, temp2
, addr
));
4648 emit_insn (gen_tldo_add64 (ret
, temp3
, temp2
, addr
));
4651 case TLS_MODEL_INITIAL_EXEC
:
4652 temp1
= gen_reg_rtx (SImode
);
4653 temp2
= gen_reg_rtx (SImode
);
4654 temp3
= gen_reg_rtx (Pmode
);
4655 got
= sparc_tls_got ();
4656 emit_insn (gen_tie_hi22 (temp1
, addr
));
4657 emit_insn (gen_tie_lo10 (temp2
, temp1
, addr
));
4659 emit_insn (gen_tie_ld32 (temp3
, got
, temp2
, addr
));
4661 emit_insn (gen_tie_ld64 (temp3
, got
, temp2
, addr
));
4664 ret
= gen_reg_rtx (Pmode
);
4666 emit_insn (gen_tie_add32 (ret
, gen_rtx_REG (Pmode
, 7),
4669 emit_insn (gen_tie_add64 (ret
, gen_rtx_REG (Pmode
, 7),
4673 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp3
);
4676 case TLS_MODEL_LOCAL_EXEC
:
4677 temp1
= gen_reg_rtx (Pmode
);
4678 temp2
= gen_reg_rtx (Pmode
);
4681 emit_insn (gen_tle_hix22_sp32 (temp1
, addr
));
4682 emit_insn (gen_tle_lox10_sp32 (temp2
, temp1
, addr
));
4686 emit_insn (gen_tle_hix22_sp64 (temp1
, addr
));
4687 emit_insn (gen_tle_lox10_sp64 (temp2
, temp1
, addr
));
4689 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp2
);
4696 else if (GET_CODE (addr
) == CONST
)
4700 gcc_assert (GET_CODE (XEXP (addr
, 0)) == PLUS
);
4702 base
= sparc_legitimize_tls_address (XEXP (XEXP (addr
, 0), 0));
4703 offset
= XEXP (XEXP (addr
, 0), 1);
4705 base
= force_operand (base
, NULL_RTX
);
4706 if (!(GET_CODE (offset
) == CONST_INT
&& SMALL_INT (offset
)))
4707 offset
= force_reg (Pmode
, offset
);
4708 ret
= gen_rtx_PLUS (Pmode
, base
, offset
);
4712 gcc_unreachable (); /* for now ... */
4717 /* Legitimize PIC addresses. If the address is already position-independent,
4718 we return ORIG. Newly generated position-independent addresses go into a
4719 reg. This is REG if nonzero, otherwise we allocate register(s) as
4723 sparc_legitimize_pic_address (rtx orig
, rtx reg
)
4725 bool gotdata_op
= false;
4727 if (GET_CODE (orig
) == SYMBOL_REF
4728 /* See the comment in sparc_expand_move. */
4729 || (GET_CODE (orig
) == LABEL_REF
&& !can_use_mov_pic_label_ref (orig
)))
4731 rtx pic_ref
, address
;
4736 gcc_assert (can_create_pseudo_p ());
4737 reg
= gen_reg_rtx (Pmode
);
4742 /* If not during reload, allocate another temp reg here for loading
4743 in the address, so that these instructions can be optimized
4745 rtx temp_reg
= (! can_create_pseudo_p ()
4746 ? reg
: gen_reg_rtx (Pmode
));
4748 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
4749 won't get confused into thinking that these two instructions
4750 are loading in the true address of the symbol. If in the
4751 future a PIC rtx exists, that should be used instead. */
4754 emit_insn (gen_movdi_high_pic (temp_reg
, orig
));
4755 emit_insn (gen_movdi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
4759 emit_insn (gen_movsi_high_pic (temp_reg
, orig
));
4760 emit_insn (gen_movsi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
4768 crtl
->uses_pic_offset_table
= 1;
4772 insn
= emit_insn (gen_movdi_pic_gotdata_op (reg
,
4773 pic_offset_table_rtx
,
4776 insn
= emit_insn (gen_movsi_pic_gotdata_op (reg
,
4777 pic_offset_table_rtx
,
4783 = gen_const_mem (Pmode
,
4784 gen_rtx_PLUS (Pmode
,
4785 pic_offset_table_rtx
, address
));
4786 insn
= emit_move_insn (reg
, pic_ref
);
4789 /* Put a REG_EQUAL note on this insn, so that it can be optimized
4791 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
4794 else if (GET_CODE (orig
) == CONST
)
4798 if (GET_CODE (XEXP (orig
, 0)) == PLUS
4799 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
4804 gcc_assert (can_create_pseudo_p ());
4805 reg
= gen_reg_rtx (Pmode
);
4808 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
4809 base
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), reg
);
4810 offset
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
4811 base
== reg
? NULL_RTX
: reg
);
4813 if (GET_CODE (offset
) == CONST_INT
)
4815 if (SMALL_INT (offset
))
4816 return plus_constant (Pmode
, base
, INTVAL (offset
));
4817 else if (can_create_pseudo_p ())
4818 offset
= force_reg (Pmode
, offset
);
4820 /* If we reach here, then something is seriously wrong. */
4823 return gen_rtx_PLUS (Pmode
, base
, offset
);
4825 else if (GET_CODE (orig
) == LABEL_REF
)
4826 /* ??? We ought to be checking that the register is live instead, in case
4827 it is eliminated. */
4828 crtl
->uses_pic_offset_table
= 1;
4833 /* Try machine-dependent ways of modifying an illegitimate address X
4834 to be legitimate. If we find one, return the new, valid address.
4836 OLDX is the address as it was before break_out_memory_refs was called.
4837 In some cases it is useful to look at this to decide what needs to be done.
4839 MODE is the mode of the operand pointed to by X.
4841 On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
4844 sparc_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
4849 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
)
4850 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
4851 force_operand (XEXP (x
, 0), NULL_RTX
));
4852 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == MULT
)
4853 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4854 force_operand (XEXP (x
, 1), NULL_RTX
));
4855 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
4856 x
= gen_rtx_PLUS (Pmode
, force_operand (XEXP (x
, 0), NULL_RTX
),
4858 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == PLUS
)
4859 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4860 force_operand (XEXP (x
, 1), NULL_RTX
));
4862 if (x
!= orig_x
&& sparc_legitimate_address_p (mode
, x
, FALSE
))
4865 if (sparc_tls_referenced_p (x
))
4866 x
= sparc_legitimize_tls_address (x
);
4868 x
= sparc_legitimize_pic_address (x
, NULL_RTX
);
4869 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 1)))
4870 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4871 copy_to_mode_reg (Pmode
, XEXP (x
, 1)));
4872 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 0)))
4873 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
4874 copy_to_mode_reg (Pmode
, XEXP (x
, 0)));
4875 else if (GET_CODE (x
) == SYMBOL_REF
4876 || GET_CODE (x
) == CONST
4877 || GET_CODE (x
) == LABEL_REF
)
4878 x
= copy_to_suggested_reg (x
, NULL_RTX
, Pmode
);
4883 /* Delegitimize an address that was legitimized by the above function. */
4886 sparc_delegitimize_address (rtx x
)
4888 x
= delegitimize_mem_from_attrs (x
);
4890 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 1)) == UNSPEC
)
4891 switch (XINT (XEXP (x
, 1), 1))
4893 case UNSPEC_MOVE_PIC
:
4895 x
= XVECEXP (XEXP (x
, 1), 0, 0);
4896 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
4902 /* This is generated by mov{si,di}_pic_label_ref in PIC mode. */
4903 if (GET_CODE (x
) == MINUS
4904 && REG_P (XEXP (x
, 0))
4905 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
4906 && GET_CODE (XEXP (x
, 1)) == LO_SUM
4907 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == UNSPEC
4908 && XINT (XEXP (XEXP (x
, 1), 1), 1) == UNSPEC_MOVE_PIC_LABEL
)
4910 x
= XVECEXP (XEXP (XEXP (x
, 1), 1), 0, 0);
4911 gcc_assert (GET_CODE (x
) == LABEL_REF
);
4917 /* SPARC implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
4918 replace the input X, or the original X if no replacement is called for.
4919 The output parameter *WIN is 1 if the calling macro should goto WIN,
4922 For SPARC, we wish to handle addresses by splitting them into
4923 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
4924 This cuts the number of extra insns by one.
4926 Do nothing when generating PIC code and the address is a symbolic
4927 operand or requires a scratch register. */
4930 sparc_legitimize_reload_address (rtx x
, machine_mode mode
,
4931 int opnum
, int type
,
4932 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
4934 /* Decompose SImode constants into HIGH+LO_SUM. */
4936 && (mode
!= TFmode
|| TARGET_ARCH64
)
4937 && GET_MODE (x
) == SImode
4938 && GET_CODE (x
) != LO_SUM
4939 && GET_CODE (x
) != HIGH
4940 && sparc_cmodel
<= CM_MEDLOW
4942 && (symbolic_operand (x
, Pmode
) || pic_address_needs_scratch (x
))))
4944 x
= gen_rtx_LO_SUM (GET_MODE (x
), gen_rtx_HIGH (GET_MODE (x
), x
), x
);
4945 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4946 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
4947 opnum
, (enum reload_type
)type
);
4952 /* We have to recognize what we have already generated above. */
4953 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == HIGH
)
4955 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4956 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
4957 opnum
, (enum reload_type
)type
);
4966 /* Return true if ADDR (a legitimate address expression)
4967 has an effect that depends on the machine mode it is used for.
4973 is not equivalent to
4975 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
4977 because [%l7+a+1] is interpreted as the address of (a+1). */
4981 sparc_mode_dependent_address_p (const_rtx addr
,
4982 addr_space_t as ATTRIBUTE_UNUSED
)
4984 if (flag_pic
&& GET_CODE (addr
) == PLUS
)
4986 rtx op0
= XEXP (addr
, 0);
4987 rtx op1
= XEXP (addr
, 1);
4988 if (op0
== pic_offset_table_rtx
4989 && symbolic_operand (op1
, VOIDmode
))
4996 #ifdef HAVE_GAS_HIDDEN
4997 # define USE_HIDDEN_LINKONCE 1
4999 # define USE_HIDDEN_LINKONCE 0
5003 get_pc_thunk_name (char name
[32], unsigned int regno
)
5005 const char *reg_name
= reg_names
[regno
];
5007 /* Skip the leading '%' as that cannot be used in a
5011 if (USE_HIDDEN_LINKONCE
)
5012 sprintf (name
, "__sparc_get_pc_thunk.%s", reg_name
);
5014 ASM_GENERATE_INTERNAL_LABEL (name
, "LADDPC", regno
);
5017 /* Wrapper around the load_pcrel_sym{si,di} patterns. */
5020 gen_load_pcrel_sym (rtx op0
, rtx op1
, rtx op2
, rtx op3
)
5022 int orig_flag_pic
= flag_pic
;
5025 /* The load_pcrel_sym{si,di} patterns require absolute addressing. */
5028 insn
= gen_load_pcrel_symdi (op0
, op1
, op2
, op3
);
5030 insn
= gen_load_pcrel_symsi (op0
, op1
, op2
, op3
);
5031 flag_pic
= orig_flag_pic
;
5036 /* Emit code to load the GOT register. */
5039 load_got_register (void)
5041 /* In PIC mode, this will retrieve pic_offset_table_rtx. */
5042 if (!global_offset_table_rtx
)
5043 global_offset_table_rtx
= gen_rtx_REG (Pmode
, GLOBAL_OFFSET_TABLE_REGNUM
);
5045 if (TARGET_VXWORKS_RTP
)
5046 emit_insn (gen_vxworks_load_got ());
5049 /* The GOT symbol is subject to a PC-relative relocation so we need a
5050 helper function to add the PC value and thus get the final value. */
5051 if (!got_helper_rtx
)
5054 get_pc_thunk_name (name
, GLOBAL_OFFSET_TABLE_REGNUM
);
5055 got_helper_rtx
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
5058 emit_insn (gen_load_pcrel_sym (global_offset_table_rtx
, sparc_got (),
5060 GEN_INT (GLOBAL_OFFSET_TABLE_REGNUM
)));
5063 /* Need to emit this whether or not we obey regdecls,
5064 since setjmp/longjmp can cause life info to screw up.
5065 ??? In the case where we don't obey regdecls, this is not sufficient
5066 since we may not fall out the bottom. */
5067 emit_use (global_offset_table_rtx
);
5070 /* Emit a call instruction with the pattern given by PAT. ADDR is the
5071 address of the call target. */
5074 sparc_emit_call_insn (rtx pat
, rtx addr
)
5078 insn
= emit_call_insn (pat
);
5080 /* The PIC register is live on entry to VxWorks PIC PLT entries. */
5081 if (TARGET_VXWORKS_RTP
5083 && GET_CODE (addr
) == SYMBOL_REF
5084 && (SYMBOL_REF_DECL (addr
)
5085 ? !targetm
.binds_local_p (SYMBOL_REF_DECL (addr
))
5086 : !SYMBOL_REF_LOCAL_P (addr
)))
5088 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
5089 crtl
->uses_pic_offset_table
= 1;
5093 /* Return 1 if RTX is a MEM which is known to be aligned to at
5094 least a DESIRED byte boundary. */
5097 mem_min_alignment (rtx mem
, int desired
)
5099 rtx addr
, base
, offset
;
5101 /* If it's not a MEM we can't accept it. */
5102 if (GET_CODE (mem
) != MEM
)
5106 if (!TARGET_UNALIGNED_DOUBLES
5107 && MEM_ALIGN (mem
) / BITS_PER_UNIT
>= (unsigned)desired
)
5110 /* ??? The rest of the function predates MEM_ALIGN so
5111 there is probably a bit of redundancy. */
5112 addr
= XEXP (mem
, 0);
5113 base
= offset
= NULL_RTX
;
5114 if (GET_CODE (addr
) == PLUS
)
5116 if (GET_CODE (XEXP (addr
, 0)) == REG
)
5118 base
= XEXP (addr
, 0);
5120 /* What we are saying here is that if the base
5121 REG is aligned properly, the compiler will make
5122 sure any REG based index upon it will be so
5124 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
5125 offset
= XEXP (addr
, 1);
5127 offset
= const0_rtx
;
5130 else if (GET_CODE (addr
) == REG
)
5133 offset
= const0_rtx
;
5136 if (base
!= NULL_RTX
)
5138 int regno
= REGNO (base
);
5140 if (regno
!= HARD_FRAME_POINTER_REGNUM
&& regno
!= STACK_POINTER_REGNUM
)
5142 /* Check if the compiler has recorded some information
5143 about the alignment of the base REG. If reload has
5144 completed, we already matched with proper alignments.
5145 If not running global_alloc, reload might give us
5146 unaligned pointer to local stack though. */
5148 && REGNO_POINTER_ALIGN (regno
) >= desired
* BITS_PER_UNIT
)
5149 || (optimize
&& reload_completed
))
5150 && (INTVAL (offset
) & (desired
- 1)) == 0)
5155 if (((INTVAL (offset
) - SPARC_STACK_BIAS
) & (desired
- 1)) == 0)
5159 else if (! TARGET_UNALIGNED_DOUBLES
5160 || CONSTANT_P (addr
)
5161 || GET_CODE (addr
) == LO_SUM
)
5163 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
5164 is true, in which case we can only assume that an access is aligned if
5165 it is to a constant address, or the address involves a LO_SUM. */
5169 /* An obviously unaligned address. */
5174 /* Vectors to keep interesting information about registers where it can easily
5175 be got. We used to use the actual mode value as the bit number, but there
5176 are more than 32 modes now. Instead we use two tables: one indexed by
5177 hard register number, and one indexed by mode. */
5179 /* The purpose of sparc_mode_class is to shrink the range of modes so that
5180 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
5181 mapped into one sparc_mode_class mode. */
5183 enum sparc_mode_class
{
5184 H_MODE
, S_MODE
, D_MODE
, T_MODE
, O_MODE
,
5185 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
5189 /* Modes for single-word and smaller quantities. */
5191 ((1 << (int) H_MODE) | (1 << (int) S_MODE) | (1 << (int) SF_MODE))
5193 /* Modes for double-word and smaller quantities. */
5194 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << (int) DF_MODE))
5196 /* Modes for quad-word and smaller quantities. */
5197 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
5199 /* Modes for 8-word and smaller quantities. */
5200 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
5202 /* Modes for single-float quantities. */
5203 #define SF_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
5205 /* Modes for double-float and smaller quantities. */
5206 #define DF_MODES (SF_MODES | (1 << (int) D_MODE) | (1 << (int) DF_MODE))
5208 /* Modes for quad-float and smaller quantities. */
5209 #define TF_MODES (DF_MODES | (1 << (int) TF_MODE))
5211 /* Modes for quad-float pairs and smaller quantities. */
5212 #define OF_MODES (TF_MODES | (1 << (int) OF_MODE))
5214 /* Modes for double-float only quantities. */
5215 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
5217 /* Modes for quad-float and double-float only quantities. */
5218 #define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE))
5220 /* Modes for quad-float pairs and double-float only quantities. */
5221 #define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE))
5223 /* Modes for condition codes. */
5224 #define CC_MODES (1 << (int) CC_MODE)
5225 #define CCFP_MODES (1 << (int) CCFP_MODE)
5227 /* Value is 1 if register/mode pair is acceptable on sparc.
5229 The funny mixture of D and T modes is because integer operations
5230 do not specially operate on tetra quantities, so non-quad-aligned
5231 registers can hold quadword quantities (except %o4 and %i4 because
5232 they cross fixed registers).
5234 ??? Note that, despite the settings, non-double-aligned parameter
5235 registers can hold double-word quantities in 32-bit mode. */
5237 /* This points to either the 32-bit or the 64-bit version. */
5238 static const int *hard_regno_mode_classes
;
5240 static const int hard_32bit_mode_classes
[] = {
5241 S_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
5242 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
5243 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
5244 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
5246 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5247 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5248 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5249 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5251 /* FP regs f32 to f63. Only the even numbered registers actually exist,
5252 and none can hold SFmode/SImode values. */
5253 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5254 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5255 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5256 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5259 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
5261 /* %icc, %sfp, %gsr */
5262 CC_MODES
, 0, D_MODES
5265 static const int hard_64bit_mode_classes
[] = {
5266 D_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
5267 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
5268 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
5269 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
5271 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5272 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5273 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5274 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5276 /* FP regs f32 to f63. Only the even numbered registers actually exist,
5277 and none can hold SFmode/SImode values. */
5278 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5279 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5280 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5281 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5284 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
5286 /* %icc, %sfp, %gsr */
5287 CC_MODES
, 0, D_MODES
5290 static int sparc_mode_class
[NUM_MACHINE_MODES
];
5292 enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
5295 sparc_init_modes (void)
5299 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
5301 machine_mode m
= (machine_mode
) i
;
5302 unsigned int size
= GET_MODE_SIZE (m
);
5304 switch (GET_MODE_CLASS (m
))
5307 case MODE_PARTIAL_INT
:
5308 case MODE_COMPLEX_INT
:
5310 sparc_mode_class
[i
] = 1 << (int) H_MODE
;
5312 sparc_mode_class
[i
] = 1 << (int) S_MODE
;
5314 sparc_mode_class
[i
] = 1 << (int) D_MODE
;
5315 else if (size
== 16)
5316 sparc_mode_class
[i
] = 1 << (int) T_MODE
;
5317 else if (size
== 32)
5318 sparc_mode_class
[i
] = 1 << (int) O_MODE
;
5320 sparc_mode_class
[i
] = 0;
5322 case MODE_VECTOR_INT
:
5324 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
5326 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
5328 sparc_mode_class
[i
] = 0;
5331 case MODE_COMPLEX_FLOAT
:
5333 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
5335 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
5336 else if (size
== 16)
5337 sparc_mode_class
[i
] = 1 << (int) TF_MODE
;
5338 else if (size
== 32)
5339 sparc_mode_class
[i
] = 1 << (int) OF_MODE
;
5341 sparc_mode_class
[i
] = 0;
5344 if (m
== CCFPmode
|| m
== CCFPEmode
)
5345 sparc_mode_class
[i
] = 1 << (int) CCFP_MODE
;
5347 sparc_mode_class
[i
] = 1 << (int) CC_MODE
;
5350 sparc_mode_class
[i
] = 0;
5356 hard_regno_mode_classes
= hard_64bit_mode_classes
;
5358 hard_regno_mode_classes
= hard_32bit_mode_classes
;
5360 /* Initialize the array used by REGNO_REG_CLASS. */
5361 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
5363 if (i
< 16 && TARGET_V8PLUS
)
5364 sparc_regno_reg_class
[i
] = I64_REGS
;
5365 else if (i
< 32 || i
== FRAME_POINTER_REGNUM
)
5366 sparc_regno_reg_class
[i
] = GENERAL_REGS
;
5368 sparc_regno_reg_class
[i
] = FP_REGS
;
5370 sparc_regno_reg_class
[i
] = EXTRA_FP_REGS
;
5372 sparc_regno_reg_class
[i
] = FPCC_REGS
;
5374 sparc_regno_reg_class
[i
] = NO_REGS
;
5378 /* Return whether REGNO, a global or FP register, must be saved/restored. */
5381 save_global_or_fp_reg_p (unsigned int regno
,
5382 int leaf_function ATTRIBUTE_UNUSED
)
5384 return !call_used_regs
[regno
] && df_regs_ever_live_p (regno
);
5387 /* Return whether the return address register (%i7) is needed. */
5390 return_addr_reg_needed_p (int leaf_function
)
5392 /* If it is live, for example because of __builtin_return_address (0). */
5393 if (df_regs_ever_live_p (RETURN_ADDR_REGNUM
))
5396 /* Otherwise, it is needed as save register if %o7 is clobbered. */
5398 /* Loading the GOT register clobbers %o7. */
5399 || crtl
->uses_pic_offset_table
5400 || df_regs_ever_live_p (INCOMING_RETURN_ADDR_REGNUM
))
5406 /* Return whether REGNO, a local or in register, must be saved/restored. */
5409 save_local_or_in_reg_p (unsigned int regno
, int leaf_function
)
5411 /* General case: call-saved registers live at some point. */
5412 if (!call_used_regs
[regno
] && df_regs_ever_live_p (regno
))
5415 /* Frame pointer register (%fp) if needed. */
5416 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
5419 /* Return address register (%i7) if needed. */
5420 if (regno
== RETURN_ADDR_REGNUM
&& return_addr_reg_needed_p (leaf_function
))
5423 /* GOT register (%l7) if needed. */
5424 if (regno
== PIC_OFFSET_TABLE_REGNUM
&& crtl
->uses_pic_offset_table
)
5427 /* If the function accesses prior frames, the frame pointer and the return
5428 address of the previous frame must be saved on the stack. */
5429 if (crtl
->accesses_prior_frames
5430 && (regno
== HARD_FRAME_POINTER_REGNUM
|| regno
== RETURN_ADDR_REGNUM
))
5436 /* Compute the frame size required by the function. This function is called
5437 during the reload pass and also by sparc_expand_prologue. */
5440 sparc_compute_frame_size (HOST_WIDE_INT size
, int leaf_function
)
5442 HOST_WIDE_INT frame_size
, apparent_frame_size
;
5443 int args_size
, n_global_fp_regs
= 0;
5444 bool save_local_in_regs_p
= false;
5447 /* If the function allocates dynamic stack space, the dynamic offset is
5448 computed early and contains REG_PARM_STACK_SPACE, so we need to cope. */
5449 if (leaf_function
&& !cfun
->calls_alloca
)
5452 args_size
= crtl
->outgoing_args_size
+ REG_PARM_STACK_SPACE (cfun
->decl
);
5454 /* Calculate space needed for global registers. */
5457 for (i
= 0; i
< 8; i
++)
5458 if (save_global_or_fp_reg_p (i
, 0))
5459 n_global_fp_regs
+= 2;
5463 for (i
= 0; i
< 8; i
+= 2)
5464 if (save_global_or_fp_reg_p (i
, 0)
5465 || save_global_or_fp_reg_p (i
+ 1, 0))
5466 n_global_fp_regs
+= 2;
5469 /* In the flat window model, find out which local and in registers need to
5470 be saved. We don't reserve space in the current frame for them as they
5471 will be spilled into the register window save area of the caller's frame.
5472 However, as soon as we use this register window save area, we must create
5473 that of the current frame to make it the live one. */
5475 for (i
= 16; i
< 32; i
++)
5476 if (save_local_or_in_reg_p (i
, leaf_function
))
5478 save_local_in_regs_p
= true;
5482 /* Calculate space needed for FP registers. */
5483 for (i
= 32; i
< (TARGET_V9
? 96 : 64); i
+= 2)
5484 if (save_global_or_fp_reg_p (i
, 0) || save_global_or_fp_reg_p (i
+ 1, 0))
5485 n_global_fp_regs
+= 2;
5488 && n_global_fp_regs
== 0
5490 && !save_local_in_regs_p
)
5491 frame_size
= apparent_frame_size
= 0;
5494 /* Start from the apparent frame size. */
5495 apparent_frame_size
= ROUND_UP (size
, 8) + n_global_fp_regs
* 4;
5497 /* We need to add the size of the outgoing argument area. */
5498 frame_size
= apparent_frame_size
+ ROUND_UP (args_size
, 8);
5500 /* And that of the register window save area. */
5501 frame_size
+= FIRST_PARM_OFFSET (cfun
->decl
);
5503 /* Finally, bump to the appropriate alignment. */
5504 frame_size
= SPARC_STACK_ALIGN (frame_size
);
5507 /* Set up values for use in prologue and epilogue. */
5508 sparc_frame_size
= frame_size
;
5509 sparc_apparent_frame_size
= apparent_frame_size
;
5510 sparc_n_global_fp_regs
= n_global_fp_regs
;
5511 sparc_save_local_in_regs_p
= save_local_in_regs_p
;
5516 /* Implement the macro INITIAL_ELIMINATION_OFFSET, return the OFFSET. */
5519 sparc_initial_elimination_offset (int to
)
5523 if (to
== STACK_POINTER_REGNUM
)
5524 offset
= sparc_compute_frame_size (get_frame_size (), crtl
->is_leaf
);
5528 offset
+= SPARC_STACK_BIAS
;
5532 /* Output any necessary .register pseudo-ops. */
5535 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED
)
5537 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
5543 /* Check if %g[2367] were used without
5544 .register being printed for them already. */
5545 for (i
= 2; i
< 8; i
++)
5547 if (df_regs_ever_live_p (i
)
5548 && ! sparc_hard_reg_printed
[i
])
5550 sparc_hard_reg_printed
[i
] = 1;
5551 /* %g7 is used as TLS base register, use #ignore
5552 for it instead of #scratch. */
5553 fprintf (file
, "\t.register\t%%g%d, #%s\n", i
,
5554 i
== 7 ? "ignore" : "scratch");
5561 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
5563 #if PROBE_INTERVAL > 4096
5564 #error Cannot use indexed addressing mode for stack probing
5567 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
5568 inclusive. These are offsets from the current stack pointer.
5570 Note that we don't use the REG+REG addressing mode for the probes because
5571 of the stack bias in 64-bit mode. And it doesn't really buy us anything
5572 so the advantages of having a single code win here. */
5575 sparc_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
5577 rtx g1
= gen_rtx_REG (Pmode
, 1);
5579 /* See if we have a constant small number of probes to generate. If so,
5580 that's the easy case. */
5581 if (size
<= PROBE_INTERVAL
)
5583 emit_move_insn (g1
, GEN_INT (first
));
5584 emit_insn (gen_rtx_SET (g1
,
5585 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
5586 emit_stack_probe (plus_constant (Pmode
, g1
, -size
));
5589 /* The run-time loop is made up of 9 insns in the generic case while the
5590 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
5591 else if (size
<= 4 * PROBE_INTERVAL
)
5595 emit_move_insn (g1
, GEN_INT (first
+ PROBE_INTERVAL
));
5596 emit_insn (gen_rtx_SET (g1
,
5597 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
5598 emit_stack_probe (g1
);
5600 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
5601 it exceeds SIZE. If only two probes are needed, this will not
5602 generate any code. Then probe at FIRST + SIZE. */
5603 for (i
= 2 * PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
5605 emit_insn (gen_rtx_SET (g1
,
5606 plus_constant (Pmode
, g1
, -PROBE_INTERVAL
)));
5607 emit_stack_probe (g1
);
5610 emit_stack_probe (plus_constant (Pmode
, g1
,
5611 (i
- PROBE_INTERVAL
) - size
));
5614 /* Otherwise, do the same as above, but in a loop. Note that we must be
5615 extra careful with variables wrapping around because we might be at
5616 the very top (or the very bottom) of the address space and we have
5617 to be able to handle this case properly; in particular, we use an
5618 equality test for the loop condition. */
5621 HOST_WIDE_INT rounded_size
;
5622 rtx g4
= gen_rtx_REG (Pmode
, 4);
5624 emit_move_insn (g1
, GEN_INT (first
));
5627 /* Step 1: round SIZE to the previous multiple of the interval. */
5629 rounded_size
= ROUND_DOWN (size
, PROBE_INTERVAL
);
5630 emit_move_insn (g4
, GEN_INT (rounded_size
));
5633 /* Step 2: compute initial and final value of the loop counter. */
5635 /* TEST_ADDR = SP + FIRST. */
5636 emit_insn (gen_rtx_SET (g1
,
5637 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
5639 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
5640 emit_insn (gen_rtx_SET (g4
, gen_rtx_MINUS (Pmode
, g1
, g4
)));
5645 while (TEST_ADDR != LAST_ADDR)
5647 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
5651 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
5652 until it is equal to ROUNDED_SIZE. */
5655 emit_insn (gen_probe_stack_rangedi (g1
, g1
, g4
));
5657 emit_insn (gen_probe_stack_rangesi (g1
, g1
, g4
));
5660 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
5661 that SIZE is equal to ROUNDED_SIZE. */
5663 if (size
!= rounded_size
)
5664 emit_stack_probe (plus_constant (Pmode
, g4
, rounded_size
- size
));
5667 /* Make sure nothing is scheduled before we are done. */
5668 emit_insn (gen_blockage ());
5671 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
5672 absolute addresses. */
5675 output_probe_stack_range (rtx reg1
, rtx reg2
)
5677 static int labelno
= 0;
5681 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
++);
5684 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
5686 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
5688 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
5689 output_asm_insn ("add\t%0, %1, %0", xops
);
5691 /* Test if TEST_ADDR == LAST_ADDR. */
5693 output_asm_insn ("cmp\t%0, %1", xops
);
5695 /* Probe at TEST_ADDR and branch. */
5697 fputs ("\tbne,pt\t%xcc,", asm_out_file
);
5699 fputs ("\tbne\t", asm_out_file
);
5700 assemble_name_raw (asm_out_file
, loop_lab
);
5701 fputc ('\n', asm_out_file
);
5702 xops
[1] = GEN_INT (SPARC_STACK_BIAS
);
5703 output_asm_insn (" st\t%%g0, [%0+%1]", xops
);
5708 /* Emit code to save/restore registers from LOW to HIGH at BASE+OFFSET as
5709 needed. LOW is supposed to be double-word aligned for 32-bit registers.
5710 SAVE_P decides whether a register must be saved/restored. ACTION_TRUE
5711 is the action to be performed if SAVE_P returns true and ACTION_FALSE
5712 the action to be performed if it returns false. Return the new offset. */
5714 typedef bool (*sorr_pred_t
) (unsigned int, int);
5715 typedef enum { SORR_NONE
, SORR_ADVANCE
, SORR_SAVE
, SORR_RESTORE
} sorr_act_t
;
5718 emit_save_or_restore_regs (unsigned int low
, unsigned int high
, rtx base
,
5719 int offset
, int leaf_function
, sorr_pred_t save_p
,
5720 sorr_act_t action_true
, sorr_act_t action_false
)
5726 if (TARGET_ARCH64
&& high
<= 32)
5730 for (i
= low
; i
< high
; i
++)
5732 if (save_p (i
, leaf_function
))
5734 mem
= gen_frame_mem (DImode
, plus_constant (Pmode
,
5736 if (action_true
== SORR_SAVE
)
5738 insn
= emit_move_insn (mem
, gen_rtx_REG (DImode
, i
));
5739 RTX_FRAME_RELATED_P (insn
) = 1;
5741 else /* action_true == SORR_RESTORE */
5743 /* The frame pointer must be restored last since its old
5744 value may be used as base address for the frame. This
5745 is problematic in 64-bit mode only because of the lack
5746 of double-word load instruction. */
5747 if (i
== HARD_FRAME_POINTER_REGNUM
)
5750 emit_move_insn (gen_rtx_REG (DImode
, i
), mem
);
5754 else if (action_false
== SORR_ADVANCE
)
5760 mem
= gen_frame_mem (DImode
, plus_constant (Pmode
, base
, fp_offset
));
5761 emit_move_insn (hard_frame_pointer_rtx
, mem
);
5766 for (i
= low
; i
< high
; i
+= 2)
5768 bool reg0
= save_p (i
, leaf_function
);
5769 bool reg1
= save_p (i
+ 1, leaf_function
);
5775 mode
= SPARC_INT_REG_P (i
) ? E_DImode
: E_DFmode
;
5780 mode
= SPARC_INT_REG_P (i
) ? E_SImode
: E_SFmode
;
5785 mode
= SPARC_INT_REG_P (i
) ? E_SImode
: E_SFmode
;
5791 if (action_false
== SORR_ADVANCE
)
5796 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, base
, offset
));
5797 if (action_true
== SORR_SAVE
)
5799 insn
= emit_move_insn (mem
, gen_rtx_REG (mode
, regno
));
5800 RTX_FRAME_RELATED_P (insn
) = 1;
5804 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, base
,
5806 set1
= gen_rtx_SET (mem
, gen_rtx_REG (SImode
, regno
));
5807 RTX_FRAME_RELATED_P (set1
) = 1;
5809 = gen_frame_mem (SImode
, plus_constant (Pmode
, base
,
5811 set2
= gen_rtx_SET (mem
, gen_rtx_REG (SImode
, regno
+ 1));
5812 RTX_FRAME_RELATED_P (set2
) = 1;
5813 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
5814 gen_rtx_PARALLEL (VOIDmode
,
5815 gen_rtvec (2, set1
, set2
)));
5818 else /* action_true == SORR_RESTORE */
5819 emit_move_insn (gen_rtx_REG (mode
, regno
), mem
);
5821 /* Bump and round down to double word
5822 in case we already bumped by 4. */
5823 offset
= ROUND_DOWN (offset
+ 8, 8);
5830 /* Emit code to adjust BASE to OFFSET. Return the new base. */
5833 emit_adjust_base_to_offset (rtx base
, int offset
)
5835 /* ??? This might be optimized a little as %g1 might already have a
5836 value close enough that a single add insn will do. */
5837 /* ??? Although, all of this is probably only a temporary fix because
5838 if %g1 can hold a function result, then sparc_expand_epilogue will
5839 lose (the result will be clobbered). */
5840 rtx new_base
= gen_rtx_REG (Pmode
, 1);
5841 emit_move_insn (new_base
, GEN_INT (offset
));
5842 emit_insn (gen_rtx_SET (new_base
, gen_rtx_PLUS (Pmode
, base
, new_base
)));
5846 /* Emit code to save/restore call-saved global and FP registers. */
5849 emit_save_or_restore_global_fp_regs (rtx base
, int offset
, sorr_act_t action
)
5851 if (offset
< -4096 || offset
+ sparc_n_global_fp_regs
* 4 > 4095)
5853 base
= emit_adjust_base_to_offset (base
, offset
);
5858 = emit_save_or_restore_regs (0, 8, base
, offset
, 0,
5859 save_global_or_fp_reg_p
, action
, SORR_NONE
);
5860 emit_save_or_restore_regs (32, TARGET_V9
? 96 : 64, base
, offset
, 0,
5861 save_global_or_fp_reg_p
, action
, SORR_NONE
);
5864 /* Emit code to save/restore call-saved local and in registers. */
5867 emit_save_or_restore_local_in_regs (rtx base
, int offset
, sorr_act_t action
)
5869 if (offset
< -4096 || offset
+ 16 * UNITS_PER_WORD
> 4095)
5871 base
= emit_adjust_base_to_offset (base
, offset
);
5875 emit_save_or_restore_regs (16, 32, base
, offset
, sparc_leaf_function_p
,
5876 save_local_or_in_reg_p
, action
, SORR_ADVANCE
);
5879 /* Emit a window_save insn. */
5882 emit_window_save (rtx increment
)
5884 rtx_insn
*insn
= emit_insn (gen_window_save (increment
));
5885 RTX_FRAME_RELATED_P (insn
) = 1;
5887 /* The incoming return address (%o7) is saved in %i7. */
5888 add_reg_note (insn
, REG_CFA_REGISTER
,
5889 gen_rtx_SET (gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
),
5891 INCOMING_RETURN_ADDR_REGNUM
)));
5893 /* The window save event. */
5894 add_reg_note (insn
, REG_CFA_WINDOW_SAVE
, const0_rtx
);
5896 /* The CFA is %fp, the hard frame pointer. */
5897 add_reg_note (insn
, REG_CFA_DEF_CFA
,
5898 plus_constant (Pmode
, hard_frame_pointer_rtx
,
5899 INCOMING_FRAME_SP_OFFSET
));
5904 /* Generate an increment for the stack pointer. */
5907 gen_stack_pointer_inc (rtx increment
)
5909 return gen_rtx_SET (stack_pointer_rtx
,
5910 gen_rtx_PLUS (Pmode
,
5915 /* Expand the function prologue. The prologue is responsible for reserving
5916 storage for the frame, saving the call-saved registers and loading the
5917 GOT register if needed. */
5920 sparc_expand_prologue (void)
5925 /* Compute a snapshot of crtl->uses_only_leaf_regs. Relying
5926 on the final value of the flag means deferring the prologue/epilogue
5927 expansion until just before the second scheduling pass, which is too
5928 late to emit multiple epilogues or return insns.
5930 Of course we are making the assumption that the value of the flag
5931 will not change between now and its final value. Of the three parts
5932 of the formula, only the last one can reasonably vary. Let's take a
5933 closer look, after assuming that the first two ones are set to true
5934 (otherwise the last value is effectively silenced).
5936 If only_leaf_regs_used returns false, the global predicate will also
5937 be false so the actual frame size calculated below will be positive.
5938 As a consequence, the save_register_window insn will be emitted in
5939 the instruction stream; now this insn explicitly references %fp
5940 which is not a leaf register so only_leaf_regs_used will always
5941 return false subsequently.
5943 If only_leaf_regs_used returns true, we hope that the subsequent
5944 optimization passes won't cause non-leaf registers to pop up. For
5945 example, the regrename pass has special provisions to not rename to
5946 non-leaf registers in a leaf function. */
5947 sparc_leaf_function_p
5948 = optimize
> 0 && crtl
->is_leaf
&& only_leaf_regs_used ();
5950 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
5952 if (flag_stack_usage_info
)
5953 current_function_static_stack_size
= size
;
5955 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
5956 || flag_stack_clash_protection
)
5958 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
5960 if (size
> PROBE_INTERVAL
&& size
> get_stack_check_protect ())
5961 sparc_emit_probe_stack_range (get_stack_check_protect (),
5962 size
- get_stack_check_protect ());
5965 sparc_emit_probe_stack_range (get_stack_check_protect (), size
);
5970 else if (sparc_leaf_function_p
)
5972 rtx size_int_rtx
= GEN_INT (-size
);
5975 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
5976 else if (size
<= 8192)
5978 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
5979 RTX_FRAME_RELATED_P (insn
) = 1;
5981 /* %sp is still the CFA register. */
5982 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
5986 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
5987 emit_move_insn (size_rtx
, size_int_rtx
);
5988 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
5989 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
5990 gen_stack_pointer_inc (size_int_rtx
));
5993 RTX_FRAME_RELATED_P (insn
) = 1;
5997 rtx size_int_rtx
= GEN_INT (-size
);
6000 emit_window_save (size_int_rtx
);
6001 else if (size
<= 8192)
6003 emit_window_save (GEN_INT (-4096));
6005 /* %sp is not the CFA register anymore. */
6006 emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
6008 /* Make sure no %fp-based store is issued until after the frame is
6009 established. The offset between the frame pointer and the stack
6010 pointer is calculated relative to the value of the stack pointer
6011 at the end of the function prologue, and moving instructions that
6012 access the stack via the frame pointer between the instructions
6013 that decrement the stack pointer could result in accessing the
6014 register window save area, which is volatile. */
6015 emit_insn (gen_frame_blockage ());
6019 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
6020 emit_move_insn (size_rtx
, size_int_rtx
);
6021 emit_window_save (size_rtx
);
6025 if (sparc_leaf_function_p
)
6027 sparc_frame_base_reg
= stack_pointer_rtx
;
6028 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
6032 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
6033 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
6036 if (sparc_n_global_fp_regs
> 0)
6037 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
6038 sparc_frame_base_offset
6039 - sparc_apparent_frame_size
,
6042 /* Load the GOT register if needed. */
6043 if (crtl
->uses_pic_offset_table
)
6044 load_got_register ();
6046 /* Advertise that the data calculated just above are now valid. */
6047 sparc_prologue_data_valid_p
= true;
6050 /* Expand the function prologue. The prologue is responsible for reserving
6051 storage for the frame, saving the call-saved registers and loading the
6052 GOT register if needed. */
6055 sparc_flat_expand_prologue (void)
6060 sparc_leaf_function_p
= optimize
> 0 && crtl
->is_leaf
;
6062 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
6064 if (flag_stack_usage_info
)
6065 current_function_static_stack_size
= size
;
6067 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
6068 || flag_stack_clash_protection
)
6070 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
6072 if (size
> PROBE_INTERVAL
&& size
> get_stack_check_protect ())
6073 sparc_emit_probe_stack_range (get_stack_check_protect (),
6074 size
- get_stack_check_protect ());
6077 sparc_emit_probe_stack_range (get_stack_check_protect (), size
);
6080 if (sparc_save_local_in_regs_p
)
6081 emit_save_or_restore_local_in_regs (stack_pointer_rtx
, SPARC_STACK_BIAS
,
6088 rtx size_int_rtx
, size_rtx
;
6090 size_rtx
= size_int_rtx
= GEN_INT (-size
);
6092 /* We establish the frame (i.e. decrement the stack pointer) first, even
6093 if we use a frame pointer, because we cannot clobber any call-saved
6094 registers, including the frame pointer, if we haven't created a new
6095 register save area, for the sake of compatibility with the ABI. */
6097 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
6098 else if (size
<= 8192 && !frame_pointer_needed
)
6100 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
6101 RTX_FRAME_RELATED_P (insn
) = 1;
6102 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
6106 size_rtx
= gen_rtx_REG (Pmode
, 1);
6107 emit_move_insn (size_rtx
, size_int_rtx
);
6108 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
6109 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
6110 gen_stack_pointer_inc (size_int_rtx
));
6112 RTX_FRAME_RELATED_P (insn
) = 1;
6114 /* Ensure nothing is scheduled until after the frame is established. */
6115 emit_insn (gen_blockage ());
6117 if (frame_pointer_needed
)
6119 insn
= emit_insn (gen_rtx_SET (hard_frame_pointer_rtx
,
6120 gen_rtx_MINUS (Pmode
,
6123 RTX_FRAME_RELATED_P (insn
) = 1;
6125 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
6126 gen_rtx_SET (hard_frame_pointer_rtx
,
6127 plus_constant (Pmode
, stack_pointer_rtx
,
6131 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
6133 rtx o7
= gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
);
6134 rtx i7
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
6136 insn
= emit_move_insn (i7
, o7
);
6137 RTX_FRAME_RELATED_P (insn
) = 1;
6139 add_reg_note (insn
, REG_CFA_REGISTER
, gen_rtx_SET (i7
, o7
));
6141 /* Prevent this instruction from ever being considered dead,
6142 even if this function has no epilogue. */
6147 if (frame_pointer_needed
)
6149 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
6150 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
6154 sparc_frame_base_reg
= stack_pointer_rtx
;
6155 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
6158 if (sparc_n_global_fp_regs
> 0)
6159 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
6160 sparc_frame_base_offset
6161 - sparc_apparent_frame_size
,
6164 /* Load the GOT register if needed. */
6165 if (crtl
->uses_pic_offset_table
)
6166 load_got_register ();
6168 /* Advertise that the data calculated just above are now valid. */
6169 sparc_prologue_data_valid_p
= true;
6172 /* This function generates the assembly code for function entry, which boils
6173 down to emitting the necessary .register directives. */
6176 sparc_asm_function_prologue (FILE *file
)
6178 /* Check that the assumption we made in sparc_expand_prologue is valid. */
6180 gcc_assert (sparc_leaf_function_p
== crtl
->uses_only_leaf_regs
);
6182 sparc_output_scratch_registers (file
);
6185 /* Expand the function epilogue, either normal or part of a sibcall.
6186 We emit all the instructions except the return or the call. */
6189 sparc_expand_epilogue (bool for_eh
)
6191 HOST_WIDE_INT size
= sparc_frame_size
;
6193 if (cfun
->calls_alloca
)
6194 emit_insn (gen_frame_blockage ());
6196 if (sparc_n_global_fp_regs
> 0)
6197 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
6198 sparc_frame_base_offset
6199 - sparc_apparent_frame_size
,
6202 if (size
== 0 || for_eh
)
6204 else if (sparc_leaf_function_p
)
6207 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
6208 else if (size
<= 8192)
6210 emit_insn (gen_stack_pointer_inc (GEN_INT (4096)));
6211 emit_insn (gen_stack_pointer_inc (GEN_INT (size
- 4096)));
6215 rtx reg
= gen_rtx_REG (Pmode
, 1);
6216 emit_move_insn (reg
, GEN_INT (size
));
6217 emit_insn (gen_stack_pointer_inc (reg
));
6222 /* Expand the function epilogue, either normal or part of a sibcall.
6223 We emit all the instructions except the return or the call. */
6226 sparc_flat_expand_epilogue (bool for_eh
)
6228 HOST_WIDE_INT size
= sparc_frame_size
;
6230 if (sparc_n_global_fp_regs
> 0)
6231 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
6232 sparc_frame_base_offset
6233 - sparc_apparent_frame_size
,
6236 /* If we have a frame pointer, we'll need both to restore it before the
6237 frame is destroyed and use its current value in destroying the frame.
6238 Since we don't have an atomic way to do that in the flat window model,
6239 we save the current value into a temporary register (%g1). */
6240 if (frame_pointer_needed
&& !for_eh
)
6241 emit_move_insn (gen_rtx_REG (Pmode
, 1), hard_frame_pointer_rtx
);
6243 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
6244 emit_move_insn (gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
),
6245 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
));
6247 if (sparc_save_local_in_regs_p
)
6248 emit_save_or_restore_local_in_regs (sparc_frame_base_reg
,
6249 sparc_frame_base_offset
,
6252 if (size
== 0 || for_eh
)
6254 else if (frame_pointer_needed
)
6256 /* Make sure the frame is destroyed after everything else is done. */
6257 emit_insn (gen_blockage ());
6259 emit_move_insn (stack_pointer_rtx
, gen_rtx_REG (Pmode
, 1));
6264 emit_insn (gen_blockage ());
6267 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
6268 else if (size
<= 8192)
6270 emit_insn (gen_stack_pointer_inc (GEN_INT (4096)));
6271 emit_insn (gen_stack_pointer_inc (GEN_INT (size
- 4096)));
6275 rtx reg
= gen_rtx_REG (Pmode
, 1);
6276 emit_move_insn (reg
, GEN_INT (size
));
6277 emit_insn (gen_stack_pointer_inc (reg
));
6282 /* Return true if it is appropriate to emit `return' instructions in the
6283 body of a function. */
6286 sparc_can_use_return_insn_p (void)
6288 return sparc_prologue_data_valid_p
6289 && sparc_n_global_fp_regs
== 0
6291 ? (sparc_frame_size
== 0 && !sparc_save_local_in_regs_p
)
6292 : (sparc_frame_size
== 0 || !sparc_leaf_function_p
);
6295 /* This function generates the assembly code for function exit. */
6298 sparc_asm_function_epilogue (FILE *file
)
6300 /* If the last two instructions of a function are "call foo; dslot;"
6301 the return address might point to the first instruction in the next
6302 function and we have to output a dummy nop for the sake of sane
6303 backtraces in such cases. This is pointless for sibling calls since
6304 the return address is explicitly adjusted. */
6306 rtx_insn
*insn
= get_last_insn ();
6308 rtx last_real_insn
= prev_real_insn (insn
);
6310 && NONJUMP_INSN_P (last_real_insn
)
6311 && GET_CODE (PATTERN (last_real_insn
)) == SEQUENCE
)
6312 last_real_insn
= XVECEXP (PATTERN (last_real_insn
), 0, 0);
6315 && CALL_P (last_real_insn
)
6316 && !SIBLING_CALL_P (last_real_insn
))
6317 fputs("\tnop\n", file
);
6319 sparc_output_deferred_case_vectors ();
6322 /* Output a 'restore' instruction. */
6325 output_restore (rtx pat
)
6331 fputs ("\t restore\n", asm_out_file
);
6335 gcc_assert (GET_CODE (pat
) == SET
);
6337 operands
[0] = SET_DEST (pat
);
6338 pat
= SET_SRC (pat
);
6340 switch (GET_CODE (pat
))
6343 operands
[1] = XEXP (pat
, 0);
6344 operands
[2] = XEXP (pat
, 1);
6345 output_asm_insn (" restore %r1, %2, %Y0", operands
);
6348 operands
[1] = XEXP (pat
, 0);
6349 operands
[2] = XEXP (pat
, 1);
6350 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands
);
6353 operands
[1] = XEXP (pat
, 0);
6354 gcc_assert (XEXP (pat
, 1) == const1_rtx
);
6355 output_asm_insn (" restore %r1, %r1, %Y0", operands
);
6359 output_asm_insn (" restore %%g0, %1, %Y0", operands
);
6364 /* Output a return. */
6367 output_return (rtx_insn
*insn
)
6369 if (crtl
->calls_eh_return
)
6371 /* If the function uses __builtin_eh_return, the eh_return
6372 machinery occupies the delay slot. */
6373 gcc_assert (!final_sequence
);
6375 if (flag_delayed_branch
)
6377 if (!TARGET_FLAT
&& TARGET_V9
)
6378 fputs ("\treturn\t%i7+8\n", asm_out_file
);
6382 fputs ("\trestore\n", asm_out_file
);
6384 fputs ("\tjmp\t%o7+8\n", asm_out_file
);
6387 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file
);
6392 fputs ("\trestore\n", asm_out_file
);
6394 fputs ("\tadd\t%sp, %g1, %sp\n", asm_out_file
);
6395 fputs ("\tjmp\t%o7+8\n\t nop\n", asm_out_file
);
6398 else if (sparc_leaf_function_p
|| TARGET_FLAT
)
6400 /* This is a leaf or flat function so we don't have to bother restoring
6401 the register window, which frees us from dealing with the convoluted
6402 semantics of restore/return. We simply output the jump to the
6403 return address and the insn in the delay slot (if any). */
6405 return "jmp\t%%o7+%)%#";
6409 /* This is a regular function so we have to restore the register window.
6410 We may have a pending insn for the delay slot, which will be either
6411 combined with the 'restore' instruction or put in the delay slot of
6412 the 'return' instruction. */
6420 delay
= NEXT_INSN (insn
);
6423 pat
= PATTERN (delay
);
6425 if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1))
6427 epilogue_renumber (&pat
, 0);
6428 return "return\t%%i7+%)%#";
6432 output_asm_insn ("jmp\t%%i7+%)", NULL
);
6434 /* We're going to output the insn in the delay slot manually.
6435 Make sure to output its source location first. */
6436 PATTERN (delay
) = gen_blockage ();
6437 INSN_CODE (delay
) = -1;
6438 final_scan_insn (delay
, asm_out_file
, optimize
, 0, &seen
);
6439 INSN_LOCATION (delay
) = UNKNOWN_LOCATION
;
6441 output_restore (pat
);
6446 /* The delay slot is empty. */
6448 return "return\t%%i7+%)\n\t nop";
6449 else if (flag_delayed_branch
)
6450 return "jmp\t%%i7+%)\n\t restore";
6452 return "restore\n\tjmp\t%%o7+%)\n\t nop";
6459 /* Output a sibling call. */
6462 output_sibcall (rtx_insn
*insn
, rtx call_operand
)
6466 gcc_assert (flag_delayed_branch
);
6468 operands
[0] = call_operand
;
6470 if (sparc_leaf_function_p
|| TARGET_FLAT
)
6472 /* This is a leaf or flat function so we don't have to bother restoring
6473 the register window. We simply output the jump to the function and
6474 the insn in the delay slot (if any). */
6476 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P
&& final_sequence
));
6479 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
6482 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
6483 it into branch if possible. */
6484 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
6489 /* This is a regular function so we have to restore the register window.
6490 We may have a pending insn for the delay slot, which will be combined
6491 with the 'restore' instruction. */
6493 output_asm_insn ("call\t%a0, 0", operands
);
6501 delay
= NEXT_INSN (insn
);
6504 pat
= PATTERN (delay
);
6506 /* We're going to output the insn in the delay slot manually.
6507 Make sure to output its source location first. */
6508 PATTERN (delay
) = gen_blockage ();
6509 INSN_CODE (delay
) = -1;
6510 final_scan_insn (delay
, asm_out_file
, optimize
, 0, &seen
);
6511 INSN_LOCATION (delay
) = UNKNOWN_LOCATION
;
6513 output_restore (pat
);
6516 output_restore (NULL_RTX
);
6522 /* Functions for handling argument passing.
6524 For 32-bit, the first 6 args are normally in registers and the rest are
6525 pushed. Any arg that starts within the first 6 words is at least
6526 partially passed in a register unless its data type forbids.
6528 For 64-bit, the argument registers are laid out as an array of 16 elements
6529 and arguments are added sequentially. The first 6 int args and up to the
6530 first 16 fp args (depending on size) are passed in regs.
6532 Slot Stack Integral Float Float in structure Double Long Double
6533 ---- ----- -------- ----- ------------------ ------ -----------
6534 15 [SP+248] %f31 %f30,%f31 %d30
6535 14 [SP+240] %f29 %f28,%f29 %d28 %q28
6536 13 [SP+232] %f27 %f26,%f27 %d26
6537 12 [SP+224] %f25 %f24,%f25 %d24 %q24
6538 11 [SP+216] %f23 %f22,%f23 %d22
6539 10 [SP+208] %f21 %f20,%f21 %d20 %q20
6540 9 [SP+200] %f19 %f18,%f19 %d18
6541 8 [SP+192] %f17 %f16,%f17 %d16 %q16
6542 7 [SP+184] %f15 %f14,%f15 %d14
6543 6 [SP+176] %f13 %f12,%f13 %d12 %q12
6544 5 [SP+168] %o5 %f11 %f10,%f11 %d10
6545 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
6546 3 [SP+152] %o3 %f7 %f6,%f7 %d6
6547 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
6548 1 [SP+136] %o1 %f3 %f2,%f3 %d2
6549 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
6551 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
6553 Integral arguments are always passed as 64-bit quantities appropriately
6556 Passing of floating point values is handled as follows.
6557 If a prototype is in scope:
6558 If the value is in a named argument (i.e. not a stdarg function or a
6559 value not part of the `...') then the value is passed in the appropriate
6561 If the value is part of the `...' and is passed in one of the first 6
6562 slots then the value is passed in the appropriate int reg.
6563 If the value is part of the `...' and is not passed in one of the first 6
6564 slots then the value is passed in memory.
6565 If a prototype is not in scope:
6566 If the value is one of the first 6 arguments the value is passed in the
6567 appropriate integer reg and the appropriate fp reg.
6568 If the value is not one of the first 6 arguments the value is passed in
6569 the appropriate fp reg and in memory.
6572 Summary of the calling conventions implemented by GCC on the SPARC:
6575 size argument return value
6577 small integer <4 int. reg. int. reg.
6578 word 4 int. reg. int. reg.
6579 double word 8 int. reg. int. reg.
6581 _Complex small integer <8 int. reg. int. reg.
6582 _Complex word 8 int. reg. int. reg.
6583 _Complex double word 16 memory int. reg.
6585 vector integer <=8 int. reg. FP reg.
6586 vector integer >8 memory memory
6588 float 4 int. reg. FP reg.
6589 double 8 int. reg. FP reg.
6590 long double 16 memory memory
6592 _Complex float 8 memory FP reg.
6593 _Complex double 16 memory FP reg.
6594 _Complex long double 32 memory FP reg.
6596 vector float any memory memory
6598 aggregate any memory memory
6603 size argument return value
6605 small integer <8 int. reg. int. reg.
6606 word 8 int. reg. int. reg.
6607 double word 16 int. reg. int. reg.
6609 _Complex small integer <16 int. reg. int. reg.
6610 _Complex word 16 int. reg. int. reg.
6611 _Complex double word 32 memory int. reg.
6613 vector integer <=16 FP reg. FP reg.
6614 vector integer 16<s<=32 memory FP reg.
6615 vector integer >32 memory memory
6617 float 4 FP reg. FP reg.
6618 double 8 FP reg. FP reg.
6619 long double 16 FP reg. FP reg.
6621 _Complex float 8 FP reg. FP reg.
6622 _Complex double 16 FP reg. FP reg.
6623 _Complex long double 32 memory FP reg.
6625 vector float <=16 FP reg. FP reg.
6626 vector float 16<s<=32 memory FP reg.
6627 vector float >32 memory memory
6629 aggregate <=16 reg. reg.
6630 aggregate 16<s<=32 memory reg.
6631 aggregate >32 memory memory
6635 Note #1: complex floating-point types follow the extended SPARC ABIs as
6636 implemented by the Sun compiler.
6638 Note #2: integral vector types follow the scalar floating-point types
6639 conventions to match what is implemented by the Sun VIS SDK.
6641 Note #3: floating-point vector types follow the aggregate types
6645 /* Maximum number of int regs for args. */
6646 #define SPARC_INT_ARG_MAX 6
6647 /* Maximum number of fp regs for args. */
6648 #define SPARC_FP_ARG_MAX 16
6649 /* Number of words (partially) occupied for a given size in units. */
6650 #define CEIL_NWORDS(SIZE) CEIL((SIZE), UNITS_PER_WORD)
6652 /* Handle the INIT_CUMULATIVE_ARGS macro.
6653 Initialize a variable CUM of type CUMULATIVE_ARGS
6654 for a call to a function whose data type is FNTYPE.
6655 For a library call, FNTYPE is 0. */
6658 init_cumulative_args (struct sparc_args
*cum
, tree fntype
, rtx
, tree
)
6661 cum
->prototype_p
= fntype
&& prototype_p (fntype
);
6662 cum
->libcall_p
= !fntype
;
6665 /* Handle promotion of pointer and integer arguments. */
6668 sparc_promote_function_mode (const_tree type
, machine_mode mode
,
6669 int *punsignedp
, const_tree
, int)
6671 if (type
&& POINTER_TYPE_P (type
))
6673 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
6677 /* Integral arguments are passed as full words, as per the ABI. */
6678 if (GET_MODE_CLASS (mode
) == MODE_INT
6679 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
6685 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
6688 sparc_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
6690 return TARGET_ARCH64
? true : false;
6693 /* Traverse the record TYPE recursively and call FUNC on its fields.
6694 NAMED is true if this is for a named parameter. DATA is passed
6695 to FUNC for each field. OFFSET is the starting position and
6696 PACKED is true if we are inside a packed record. */
6698 template <typename T
, void Func (const_tree
, HOST_WIDE_INT
, bool, T
*)>
6700 traverse_record_type (const_tree type
, bool named
, T
*data
,
6701 HOST_WIDE_INT offset
= 0, bool packed
= false)
6703 /* The ABI obviously doesn't specify how packed structures are passed.
6704 These are passed in integer regs if possible, otherwise memory. */
6706 for (tree field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
6707 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
6713 /* Walk the real fields, but skip those with no size or a zero size.
6714 ??? Fields with variable offset are handled as having zero offset. */
6715 for (tree field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
6716 if (TREE_CODE (field
) == FIELD_DECL
)
6718 if (!DECL_SIZE (field
) || integer_zerop (DECL_SIZE (field
)))
6721 HOST_WIDE_INT bitpos
= offset
;
6722 if (TREE_CODE (DECL_FIELD_OFFSET (field
)) == INTEGER_CST
)
6723 bitpos
+= int_bit_position (field
);
6725 tree field_type
= TREE_TYPE (field
);
6726 if (TREE_CODE (field_type
) == RECORD_TYPE
)
6727 traverse_record_type
<T
, Func
> (field_type
, named
, data
, bitpos
,
6732 = FLOAT_TYPE_P (field_type
) || VECTOR_TYPE_P (field_type
);
6733 Func (field
, bitpos
, fp_type
&& named
&& !packed
&& TARGET_FPU
,
6739 /* Handle recursive register classifying for structure layout. */
6743 bool fp_regs
; /* true if field eligible to FP registers. */
6744 bool fp_regs_in_first_word
; /* true if such field in first word. */
6747 /* A subroutine of function_arg_slotno. Classify the field. */
6750 classify_registers (const_tree
, HOST_WIDE_INT bitpos
, bool fp
,
6751 classify_data_t
*data
)
6755 data
->fp_regs
= true;
6756 if (bitpos
< BITS_PER_WORD
)
6757 data
->fp_regs_in_first_word
= true;
6761 /* Compute the slot number to pass an argument in.
6762 Return the slot number or -1 if passing on the stack.
6764 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6765 the preceding args and about the function being called.
6766 MODE is the argument's machine mode.
6767 TYPE is the data type of the argument (as a tree).
6768 This is null for libcalls where that information may
6770 NAMED is nonzero if this argument is a named parameter
6771 (otherwise it is an extra parameter matching an ellipsis).
6772 INCOMING is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
6773 *PREGNO records the register number to use if scalar type.
6774 *PPADDING records the amount of padding needed in words. */
6777 function_arg_slotno (const struct sparc_args
*cum
, machine_mode mode
,
6778 const_tree type
, bool named
, bool incoming
,
6779 int *pregno
, int *ppadding
)
6781 int regbase
= (incoming
6782 ? SPARC_INCOMING_INT_ARG_FIRST
6783 : SPARC_OUTGOING_INT_ARG_FIRST
);
6784 int slotno
= cum
->words
;
6785 enum mode_class mclass
;
6790 if (type
&& TREE_ADDRESSABLE (type
))
6796 && TYPE_ALIGN (type
) % PARM_BOUNDARY
!= 0)
6799 /* For SPARC64, objects requiring 16-byte alignment get it. */
6801 && (type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
)) >= 128
6802 && (slotno
& 1) != 0)
6803 slotno
++, *ppadding
= 1;
6805 mclass
= GET_MODE_CLASS (mode
);
6806 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
6808 /* Vector types deserve special treatment because they are
6809 polymorphic wrt their mode, depending upon whether VIS
6810 instructions are enabled. */
6811 if (TREE_CODE (TREE_TYPE (type
)) == REAL_TYPE
)
6813 /* The SPARC port defines no floating-point vector modes. */
6814 gcc_assert (mode
== BLKmode
);
6818 /* Integral vector types should either have a vector
6819 mode or an integral mode, because we are guaranteed
6820 by pass_by_reference that their size is not greater
6821 than 16 bytes and TImode is 16-byte wide. */
6822 gcc_assert (mode
!= BLKmode
);
6824 /* Vector integers are handled like floats according to
6826 mclass
= MODE_FLOAT
;
6833 case MODE_COMPLEX_FLOAT
:
6834 case MODE_VECTOR_INT
:
6835 if (TARGET_ARCH64
&& TARGET_FPU
&& named
)
6837 /* If all arg slots are filled, then must pass on stack. */
6838 if (slotno
>= SPARC_FP_ARG_MAX
)
6841 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
6842 /* Arguments filling only one single FP register are
6843 right-justified in the outer double FP register. */
6844 if (GET_MODE_SIZE (mode
) <= 4)
6851 case MODE_COMPLEX_INT
:
6852 /* If all arg slots are filled, then must pass on stack. */
6853 if (slotno
>= SPARC_INT_ARG_MAX
)
6856 regno
= regbase
+ slotno
;
6860 if (mode
== VOIDmode
)
6861 /* MODE is VOIDmode when generating the actual call. */
6864 gcc_assert (mode
== BLKmode
);
6868 || (TREE_CODE (type
) != RECORD_TYPE
6869 && TREE_CODE (type
) != VECTOR_TYPE
))
6871 /* If all arg slots are filled, then must pass on stack. */
6872 if (slotno
>= SPARC_INT_ARG_MAX
)
6875 regno
= regbase
+ slotno
;
6877 else /* TARGET_ARCH64 && type */
6879 /* If all arg slots are filled, then must pass on stack. */
6880 if (slotno
>= SPARC_FP_ARG_MAX
)
6883 if (TREE_CODE (type
) == RECORD_TYPE
)
6885 classify_data_t data
= { false, false };
6886 traverse_record_type
<classify_data_t
, classify_registers
>
6887 (type
, named
, &data
);
6891 /* If all FP slots are filled except for the last one and
6892 there is no FP field in the first word, then must pass
6894 if (slotno
>= SPARC_FP_ARG_MAX
- 1
6895 && !data
.fp_regs_in_first_word
)
6900 /* If all int slots are filled, then must pass on stack. */
6901 if (slotno
>= SPARC_INT_ARG_MAX
)
6906 /* PREGNO isn't set since both int and FP regs can be used. */
6919 /* Handle recursive register counting/assigning for structure layout. */
6923 int slotno
; /* slot number of the argument. */
6924 int regbase
; /* regno of the base register. */
6925 int intoffset
; /* offset of the first pending integer field. */
6926 int nregs
; /* number of words passed in registers. */
6927 bool stack
; /* true if part of the argument is on the stack. */
6928 rtx ret
; /* return expression being built. */
6931 /* A subroutine of function_arg_record_value. Compute the number of integer
6932 registers to be assigned between PARMS->intoffset and BITPOS. Return
6933 true if at least one integer register is assigned or false otherwise. */
6936 compute_int_layout (HOST_WIDE_INT bitpos
, assign_data_t
*data
, int *pnregs
)
6938 if (data
->intoffset
< 0)
6941 const int intoffset
= data
->intoffset
;
6942 data
->intoffset
= -1;
6944 const int this_slotno
= data
->slotno
+ intoffset
/ BITS_PER_WORD
;
6945 const unsigned int startbit
= ROUND_DOWN (intoffset
, BITS_PER_WORD
);
6946 const unsigned int endbit
= ROUND_UP (bitpos
, BITS_PER_WORD
);
6947 int nregs
= (endbit
- startbit
) / BITS_PER_WORD
;
6949 if (nregs
> 0 && nregs
> SPARC_INT_ARG_MAX
- this_slotno
)
6951 nregs
= SPARC_INT_ARG_MAX
- this_slotno
;
6953 /* We need to pass this field (partly) on the stack. */
6964 /* A subroutine of function_arg_record_value. Compute the number and the mode
6965 of the FP registers to be assigned for FIELD. Return true if at least one
6966 FP register is assigned or false otherwise. */
6969 compute_fp_layout (const_tree field
, HOST_WIDE_INT bitpos
,
6970 assign_data_t
*data
,
6971 int *pnregs
, machine_mode
*pmode
)
6973 const int this_slotno
= data
->slotno
+ bitpos
/ BITS_PER_WORD
;
6974 machine_mode mode
= DECL_MODE (field
);
6977 /* Slots are counted as words while regs are counted as having the size of
6978 the (inner) mode. */
6979 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
&& mode
== BLKmode
)
6981 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
6982 nregs
= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
6984 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
6986 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
6992 nslots
= CEIL_NWORDS (nregs
* GET_MODE_SIZE (mode
));
6994 if (nslots
> SPARC_FP_ARG_MAX
- this_slotno
)
6996 nslots
= SPARC_FP_ARG_MAX
- this_slotno
;
6997 nregs
= (nslots
* UNITS_PER_WORD
) / GET_MODE_SIZE (mode
);
6999 /* We need to pass this field (partly) on the stack. */
7011 /* A subroutine of function_arg_record_value. Count the number of registers
7012 to be assigned for FIELD and between PARMS->intoffset and BITPOS. */
7015 count_registers (const_tree field
, HOST_WIDE_INT bitpos
, bool fp
,
7016 assign_data_t
*data
)
7023 if (compute_int_layout (bitpos
, data
, &nregs
))
7024 data
->nregs
+= nregs
;
7026 if (compute_fp_layout (field
, bitpos
, data
, &nregs
, &mode
))
7027 data
->nregs
+= nregs
;
7031 if (data
->intoffset
< 0)
7032 data
->intoffset
= bitpos
;
7036 /* A subroutine of function_arg_record_value. Assign the bits of the
7037 structure between PARMS->intoffset and BITPOS to integer registers. */
7040 assign_int_registers (HOST_WIDE_INT bitpos
, assign_data_t
*data
)
7042 int intoffset
= data
->intoffset
;
7046 if (!compute_int_layout (bitpos
, data
, &nregs
))
7049 /* If this is the trailing part of a word, only load that much into
7050 the register. Otherwise load the whole register. Note that in
7051 the latter case we may pick up unwanted bits. It's not a problem
7052 at the moment but may wish to revisit. */
7053 if (intoffset
% BITS_PER_WORD
!= 0)
7054 mode
= smallest_int_mode_for_size (BITS_PER_WORD
7055 - intoffset
% BITS_PER_WORD
);
7059 const int this_slotno
= data
->slotno
+ intoffset
/ BITS_PER_WORD
;
7060 unsigned int regno
= data
->regbase
+ this_slotno
;
7061 intoffset
/= BITS_PER_UNIT
;
7065 rtx reg
= gen_rtx_REG (mode
, regno
);
7066 XVECEXP (data
->ret
, 0, data
->stack
+ data
->nregs
)
7067 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
7071 intoffset
= (intoffset
| (UNITS_PER_WORD
- 1)) + 1;
7073 while (--nregs
> 0);
7076 /* A subroutine of function_arg_record_value. Assign FIELD at position
7077 BITPOS to FP registers. */
7080 assign_fp_registers (const_tree field
, HOST_WIDE_INT bitpos
,
7081 assign_data_t
*data
)
7086 if (!compute_fp_layout (field
, bitpos
, data
, &nregs
, &mode
))
7089 const int this_slotno
= data
->slotno
+ bitpos
/ BITS_PER_WORD
;
7090 int regno
= SPARC_FP_ARG_FIRST
+ this_slotno
* 2;
7091 if (GET_MODE_SIZE (mode
) <= 4 && (bitpos
& 32) != 0)
7093 int pos
= bitpos
/ BITS_PER_UNIT
;
7097 rtx reg
= gen_rtx_REG (mode
, regno
);
7098 XVECEXP (data
->ret
, 0, data
->stack
+ data
->nregs
)
7099 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
7101 regno
+= GET_MODE_SIZE (mode
) / 4;
7102 pos
+= GET_MODE_SIZE (mode
);
7104 while (--nregs
> 0);
7107 /* A subroutine of function_arg_record_value. Assign FIELD and the bits of
7108 the structure between PARMS->intoffset and BITPOS to registers. */
7111 assign_registers (const_tree field
, HOST_WIDE_INT bitpos
, bool fp
,
7112 assign_data_t
*data
)
7116 assign_int_registers (bitpos
, data
);
7118 assign_fp_registers (field
, bitpos
, data
);
7122 if (data
->intoffset
< 0)
7123 data
->intoffset
= bitpos
;
7127 /* Used by function_arg and sparc_function_value_1 to implement the complex
7128 conventions of the 64-bit ABI for passing and returning structures.
7129 Return an expression valid as a return value for the FUNCTION_ARG
7130 and TARGET_FUNCTION_VALUE.
7132 TYPE is the data type of the argument (as a tree).
7133 This is null for libcalls where that information may
7135 MODE is the argument's machine mode.
7136 SLOTNO is the index number of the argument's slot in the parameter array.
7137 NAMED is true if this argument is a named parameter
7138 (otherwise it is an extra parameter matching an ellipsis).
7139 REGBASE is the regno of the base register for the parameter array. */
7142 function_arg_record_value (const_tree type
, machine_mode mode
,
7143 int slotno
, bool named
, int regbase
)
7145 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
7149 data
.slotno
= slotno
;
7150 data
.regbase
= regbase
;
7152 /* Count how many registers we need. */
7156 traverse_record_type
<assign_data_t
, count_registers
> (type
, named
, &data
);
7158 /* Take into account pending integer fields. */
7159 if (compute_int_layout (typesize
* BITS_PER_UNIT
, &data
, &nregs
))
7160 data
.nregs
+= nregs
;
7162 /* Allocate the vector and handle some annoying special cases. */
7167 /* ??? Empty structure has no value? Duh? */
7170 /* Though there's nothing really to store, return a word register
7171 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
7172 leads to breakage due to the fact that there are zero bytes to
7174 return gen_rtx_REG (mode
, regbase
);
7177 /* ??? C++ has structures with no fields, and yet a size. Give up
7178 for now and pass everything back in integer registers. */
7179 nregs
= (typesize
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
7180 if (nregs
+ slotno
> SPARC_INT_ARG_MAX
)
7181 nregs
= SPARC_INT_ARG_MAX
- slotno
;
7184 gcc_assert (nregs
> 0);
7186 data
.ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (data
.stack
+ nregs
));
7188 /* If at least one field must be passed on the stack, generate
7189 (parallel [(expr_list (nil) ...) ...]) so that all fields will
7190 also be passed on the stack. We can't do much better because the
7191 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
7192 of structures for which the fields passed exclusively in registers
7193 are not at the beginning of the structure. */
7195 XVECEXP (data
.ret
, 0, 0)
7196 = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
7198 /* Assign the registers. */
7201 traverse_record_type
<assign_data_t
, assign_registers
> (type
, named
, &data
);
7203 /* Assign pending integer fields. */
7204 assign_int_registers (typesize
* BITS_PER_UNIT
, &data
);
7206 gcc_assert (data
.nregs
== nregs
);
7211 /* Used by function_arg and sparc_function_value_1 to implement the conventions
7212 of the 64-bit ABI for passing and returning unions.
7213 Return an expression valid as a return value for the FUNCTION_ARG
7214 and TARGET_FUNCTION_VALUE.
7216 SIZE is the size in bytes of the union.
7217 MODE is the argument's machine mode.
7218 REGNO is the hard register the union will be passed in. */
7221 function_arg_union_value (int size
, machine_mode mode
, int slotno
,
7224 int nwords
= CEIL_NWORDS (size
), i
;
7227 /* See comment in previous function for empty structures. */
7229 return gen_rtx_REG (mode
, regno
);
7231 if (slotno
== SPARC_INT_ARG_MAX
- 1)
7234 regs
= gen_rtx_PARALLEL (mode
, rtvec_alloc (nwords
));
7236 for (i
= 0; i
< nwords
; i
++)
7238 /* Unions are passed left-justified. */
7239 XVECEXP (regs
, 0, i
)
7240 = gen_rtx_EXPR_LIST (VOIDmode
,
7241 gen_rtx_REG (word_mode
, regno
),
7242 GEN_INT (UNITS_PER_WORD
* i
));
7249 /* Used by function_arg and sparc_function_value_1 to implement the conventions
7250 for passing and returning BLKmode vectors.
7251 Return an expression valid as a return value for the FUNCTION_ARG
7252 and TARGET_FUNCTION_VALUE.
7254 SIZE is the size in bytes of the vector.
7255 REGNO is the FP hard register the vector will be passed in. */
7258 function_arg_vector_value (int size
, int regno
)
7260 const int nregs
= MAX (1, size
/ 8);
7261 rtx regs
= gen_rtx_PARALLEL (BLKmode
, rtvec_alloc (nregs
));
7264 XVECEXP (regs
, 0, 0)
7265 = gen_rtx_EXPR_LIST (VOIDmode
,
7266 gen_rtx_REG (SImode
, regno
),
7269 for (int i
= 0; i
< nregs
; i
++)
7270 XVECEXP (regs
, 0, i
)
7271 = gen_rtx_EXPR_LIST (VOIDmode
,
7272 gen_rtx_REG (DImode
, regno
+ 2*i
),
7278 /* Determine where to put an argument to a function.
7279 Value is zero to push the argument on the stack,
7280 or a hard register in which to store the argument.
7282 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7283 the preceding args and about the function being called.
7284 MODE is the argument's machine mode.
7285 TYPE is the data type of the argument (as a tree).
7286 This is null for libcalls where that information may
7288 NAMED is true if this argument is a named parameter
7289 (otherwise it is an extra parameter matching an ellipsis).
7290 INCOMING_P is false for TARGET_FUNCTION_ARG, true for
7291 TARGET_FUNCTION_INCOMING_ARG. */
7294 sparc_function_arg_1 (cumulative_args_t cum_v
, machine_mode mode
,
7295 const_tree type
, bool named
, bool incoming
)
7297 const CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
7299 int regbase
= (incoming
7300 ? SPARC_INCOMING_INT_ARG_FIRST
7301 : SPARC_OUTGOING_INT_ARG_FIRST
);
7302 int slotno
, regno
, padding
;
7303 enum mode_class mclass
= GET_MODE_CLASS (mode
);
7305 slotno
= function_arg_slotno (cum
, mode
, type
, named
, incoming
,
7310 /* Vector types deserve special treatment because they are polymorphic wrt
7311 their mode, depending upon whether VIS instructions are enabled. */
7312 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
7314 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7315 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
7316 || (TARGET_ARCH64
&& size
<= 16));
7318 if (mode
== BLKmode
)
7319 return function_arg_vector_value (size
, SPARC_FP_ARG_FIRST
+ 2*slotno
);
7321 mclass
= MODE_FLOAT
;
7325 return gen_rtx_REG (mode
, regno
);
7327 /* Structures up to 16 bytes in size are passed in arg slots on the stack
7328 and are promoted to registers if possible. */
7329 if (type
&& TREE_CODE (type
) == RECORD_TYPE
)
7331 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7332 gcc_assert (size
<= 16);
7334 return function_arg_record_value (type
, mode
, slotno
, named
, regbase
);
7337 /* Unions up to 16 bytes in size are passed in integer registers. */
7338 else if (type
&& TREE_CODE (type
) == UNION_TYPE
)
7340 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7341 gcc_assert (size
<= 16);
7343 return function_arg_union_value (size
, mode
, slotno
, regno
);
7346 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
7347 but also have the slot allocated for them.
7348 If no prototype is in scope fp values in register slots get passed
7349 in two places, either fp regs and int regs or fp regs and memory. */
7350 else if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
7351 && SPARC_FP_REG_P (regno
))
7353 rtx reg
= gen_rtx_REG (mode
, regno
);
7354 if (cum
->prototype_p
|| cum
->libcall_p
)
7360 if ((regno
- SPARC_FP_ARG_FIRST
) < SPARC_INT_ARG_MAX
* 2)
7364 /* On incoming, we don't need to know that the value
7365 is passed in %f0 and %i0, and it confuses other parts
7366 causing needless spillage even on the simplest cases. */
7370 intreg
= (SPARC_OUTGOING_INT_ARG_FIRST
7371 + (regno
- SPARC_FP_ARG_FIRST
) / 2);
7373 v0
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
7374 v1
= gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (mode
, intreg
),
7376 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
7380 v0
= gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
7381 v1
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
7382 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
7387 /* All other aggregate types are passed in an integer register in a mode
7388 corresponding to the size of the type. */
7389 else if (type
&& AGGREGATE_TYPE_P (type
))
7391 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7392 gcc_assert (size
<= 16);
7394 mode
= int_mode_for_size (size
* BITS_PER_UNIT
, 0).else_blk ();
7397 return gen_rtx_REG (mode
, regno
);
7400 /* Handle the TARGET_FUNCTION_ARG target hook. */
7403 sparc_function_arg (cumulative_args_t cum
, machine_mode mode
,
7404 const_tree type
, bool named
)
7406 return sparc_function_arg_1 (cum
, mode
, type
, named
, false);
7409 /* Handle the TARGET_FUNCTION_INCOMING_ARG target hook. */
7412 sparc_function_incoming_arg (cumulative_args_t cum
, machine_mode mode
,
7413 const_tree type
, bool named
)
7415 return sparc_function_arg_1 (cum
, mode
, type
, named
, true);
7418 /* For sparc64, objects requiring 16 byte alignment are passed that way. */
7421 sparc_function_arg_boundary (machine_mode mode
, const_tree type
)
7423 return ((TARGET_ARCH64
7424 && (GET_MODE_ALIGNMENT (mode
) == 128
7425 || (type
&& TYPE_ALIGN (type
) == 128)))
7430 /* For an arg passed partly in registers and partly in memory,
7431 this is the number of bytes of registers used.
7432 For args passed entirely in registers or entirely in memory, zero.
7434 Any arg that starts in the first 6 regs but won't entirely fit in them
7435 needs partial registers on v8. On v9, structures with integer
7436 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
7437 values that begin in the last fp reg [where "last fp reg" varies with the
7438 mode] will be split between that reg and memory. */
7441 sparc_arg_partial_bytes (cumulative_args_t cum
, machine_mode mode
,
7442 tree type
, bool named
)
7444 int slotno
, regno
, padding
;
7446 /* We pass false for incoming here, it doesn't matter. */
7447 slotno
= function_arg_slotno (get_cumulative_args (cum
), mode
, type
, named
,
7448 false, ®no
, &padding
);
7455 if ((slotno
+ (mode
== BLKmode
7456 ? CEIL_NWORDS (int_size_in_bytes (type
))
7457 : CEIL_NWORDS (GET_MODE_SIZE (mode
))))
7458 > SPARC_INT_ARG_MAX
)
7459 return (SPARC_INT_ARG_MAX
- slotno
) * UNITS_PER_WORD
;
7463 /* We are guaranteed by pass_by_reference that the size of the
7464 argument is not greater than 16 bytes, so we only need to return
7465 one word if the argument is partially passed in registers. */
7467 if (type
&& AGGREGATE_TYPE_P (type
))
7469 int size
= int_size_in_bytes (type
);
7471 if (size
> UNITS_PER_WORD
7472 && (slotno
== SPARC_INT_ARG_MAX
- 1
7473 || slotno
== SPARC_FP_ARG_MAX
- 1))
7474 return UNITS_PER_WORD
;
7476 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
7477 || (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
7478 && ! (TARGET_FPU
&& named
)))
7480 /* The complex types are passed as packed types. */
7481 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
7482 && slotno
== SPARC_INT_ARG_MAX
- 1)
7483 return UNITS_PER_WORD
;
7485 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
7487 if ((slotno
+ GET_MODE_SIZE (mode
) / UNITS_PER_WORD
)
7489 return UNITS_PER_WORD
;
7496 /* Handle the TARGET_PASS_BY_REFERENCE target hook.
7497 Specify whether to pass the argument by reference. */
7500 sparc_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
7501 machine_mode mode
, const_tree type
,
7502 bool named ATTRIBUTE_UNUSED
)
7505 /* Original SPARC 32-bit ABI says that structures and unions,
7506 and quad-precision floats are passed by reference. For Pascal,
7507 also pass arrays by reference. All other base types are passed
7510 Extended ABI (as implemented by the Sun compiler) says that all
7511 complex floats are passed by reference. Pass complex integers
7512 in registers up to 8 bytes. More generally, enforce the 2-word
7513 cap for passing arguments in registers.
7515 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7516 integers are passed like floats of the same size, that is in
7517 registers up to 8 bytes. Pass all vector floats by reference
7518 like structure and unions. */
7519 return ((type
&& (AGGREGATE_TYPE_P (type
) || VECTOR_FLOAT_TYPE_P (type
)))
7521 /* Catch CDImode, TFmode, DCmode and TCmode. */
7522 || GET_MODE_SIZE (mode
) > 8
7524 && TREE_CODE (type
) == VECTOR_TYPE
7525 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
7527 /* Original SPARC 64-bit ABI says that structures and unions
7528 smaller than 16 bytes are passed in registers, as well as
7529 all other base types.
7531 Extended ABI (as implemented by the Sun compiler) says that
7532 complex floats are passed in registers up to 16 bytes. Pass
7533 all complex integers in registers up to 16 bytes. More generally,
7534 enforce the 2-word cap for passing arguments in registers.
7536 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7537 integers are passed like floats of the same size, that is in
7538 registers (up to 16 bytes). Pass all vector floats like structure
7541 && (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == VECTOR_TYPE
)
7542 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 16)
7543 /* Catch CTImode and TCmode. */
7544 || GET_MODE_SIZE (mode
) > 16);
7547 /* Handle the TARGET_FUNCTION_ARG_ADVANCE hook.
7548 Update the data in CUM to advance over an argument
7549 of mode MODE and data type TYPE.
7550 TYPE is null for libcalls where that information may not be available. */
7553 sparc_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
7554 const_tree type
, bool named
)
7556 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
7559 /* We pass false for incoming here, it doesn't matter. */
7560 function_arg_slotno (cum
, mode
, type
, named
, false, ®no
, &padding
);
7562 /* If argument requires leading padding, add it. */
7563 cum
->words
+= padding
;
7566 cum
->words
+= (mode
== BLKmode
7567 ? CEIL_NWORDS (int_size_in_bytes (type
))
7568 : CEIL_NWORDS (GET_MODE_SIZE (mode
)));
7571 if (type
&& AGGREGATE_TYPE_P (type
))
7573 int size
= int_size_in_bytes (type
);
7577 else if (size
<= 16)
7579 else /* passed by reference */
7583 cum
->words
+= (mode
== BLKmode
7584 ? CEIL_NWORDS (int_size_in_bytes (type
))
7585 : CEIL_NWORDS (GET_MODE_SIZE (mode
)));
7589 /* Implement TARGET_FUNCTION_ARG_PADDING. For the 64-bit ABI structs
7590 are always stored left shifted in their argument slot. */
7592 static pad_direction
7593 sparc_function_arg_padding (machine_mode mode
, const_tree type
)
7595 if (TARGET_ARCH64
&& type
&& AGGREGATE_TYPE_P (type
))
7598 /* Fall back to the default. */
7599 return default_function_arg_padding (mode
, type
);
7602 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
7603 Specify whether to return the return value in memory. */
7606 sparc_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
7609 /* Original SPARC 32-bit ABI says that structures and unions,
7610 and quad-precision floats are returned in memory. All other
7611 base types are returned in registers.
7613 Extended ABI (as implemented by the Sun compiler) says that
7614 all complex floats are returned in registers (8 FP registers
7615 at most for '_Complex long double'). Return all complex integers
7616 in registers (4 at most for '_Complex long long').
7618 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7619 integers are returned like floats of the same size, that is in
7620 registers up to 8 bytes and in memory otherwise. Return all
7621 vector floats in memory like structure and unions; note that
7622 they always have BLKmode like the latter. */
7623 return (TYPE_MODE (type
) == BLKmode
7624 || TYPE_MODE (type
) == TFmode
7625 || (TREE_CODE (type
) == VECTOR_TYPE
7626 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
7628 /* Original SPARC 64-bit ABI says that structures and unions
7629 smaller than 32 bytes are returned in registers, as well as
7630 all other base types.
7632 Extended ABI (as implemented by the Sun compiler) says that all
7633 complex floats are returned in registers (8 FP registers at most
7634 for '_Complex long double'). Return all complex integers in
7635 registers (4 at most for '_Complex TItype').
7637 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7638 integers are returned like floats of the same size, that is in
7639 registers. Return all vector floats like structure and unions;
7640 note that they always have BLKmode like the latter. */
7641 return (TYPE_MODE (type
) == BLKmode
7642 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 32);
7645 /* Handle the TARGET_STRUCT_VALUE target hook.
7646 Return where to find the structure return value address. */
7649 sparc_struct_value_rtx (tree fndecl
, int incoming
)
7658 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, frame_pointer_rtx
,
7659 STRUCT_VALUE_OFFSET
));
7661 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, stack_pointer_rtx
,
7662 STRUCT_VALUE_OFFSET
));
7664 /* Only follow the SPARC ABI for fixed-size structure returns.
7665 Variable size structure returns are handled per the normal
7666 procedures in GCC. This is enabled by -mstd-struct-return */
7668 && sparc_std_struct_return
7669 && TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))
7670 && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))) == INTEGER_CST
)
7672 /* We must check and adjust the return address, as it is optional
7673 as to whether the return object is really provided. */
7674 rtx ret_reg
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
7675 rtx scratch
= gen_reg_rtx (SImode
);
7676 rtx_code_label
*endlab
= gen_label_rtx ();
7678 /* Calculate the return object size. */
7679 tree size
= TYPE_SIZE_UNIT (TREE_TYPE (fndecl
));
7680 rtx size_rtx
= GEN_INT (TREE_INT_CST_LOW (size
) & 0xfff);
7681 /* Construct a temporary return value. */
7683 = assign_stack_local (Pmode
, TREE_INT_CST_LOW (size
), 0);
7685 /* Implement SPARC 32-bit psABI callee return struct checking:
7687 Fetch the instruction where we will return to and see if
7688 it's an unimp instruction (the most significant 10 bits
7690 emit_move_insn (scratch
, gen_rtx_MEM (SImode
,
7691 plus_constant (Pmode
,
7693 /* Assume the size is valid and pre-adjust. */
7694 emit_insn (gen_add3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
7695 emit_cmp_and_jump_insns (scratch
, size_rtx
, EQ
, const0_rtx
, SImode
,
7697 emit_insn (gen_sub3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
7698 /* Write the address of the memory pointed to by temp_val into
7699 the memory pointed to by mem. */
7700 emit_move_insn (mem
, XEXP (temp_val
, 0));
7701 emit_label (endlab
);
7708 /* Handle TARGET_FUNCTION_VALUE, and TARGET_LIBCALL_VALUE target hook.
7709 For v9, function return values are subject to the same rules as arguments,
7710 except that up to 32 bytes may be returned in registers. */
7713 sparc_function_value_1 (const_tree type
, machine_mode mode
,
7716 /* Beware that the two values are swapped here wrt function_arg. */
7717 int regbase
= (outgoing
7718 ? SPARC_INCOMING_INT_ARG_FIRST
7719 : SPARC_OUTGOING_INT_ARG_FIRST
);
7720 enum mode_class mclass
= GET_MODE_CLASS (mode
);
7723 /* Vector types deserve special treatment because they are polymorphic wrt
7724 their mode, depending upon whether VIS instructions are enabled. */
7725 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
7727 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7728 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
7729 || (TARGET_ARCH64
&& size
<= 32));
7731 if (mode
== BLKmode
)
7732 return function_arg_vector_value (size
, SPARC_FP_ARG_FIRST
);
7734 mclass
= MODE_FLOAT
;
7737 if (TARGET_ARCH64
&& type
)
7739 /* Structures up to 32 bytes in size are returned in registers. */
7740 if (TREE_CODE (type
) == RECORD_TYPE
)
7742 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7743 gcc_assert (size
<= 32);
7745 return function_arg_record_value (type
, mode
, 0, 1, regbase
);
7748 /* Unions up to 32 bytes in size are returned in integer registers. */
7749 else if (TREE_CODE (type
) == UNION_TYPE
)
7751 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7752 gcc_assert (size
<= 32);
7754 return function_arg_union_value (size
, mode
, 0, regbase
);
7757 /* Objects that require it are returned in FP registers. */
7758 else if (mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
7761 /* All other aggregate types are returned in an integer register in a
7762 mode corresponding to the size of the type. */
7763 else if (AGGREGATE_TYPE_P (type
))
7765 /* All other aggregate types are passed in an integer register
7766 in a mode corresponding to the size of the type. */
7767 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7768 gcc_assert (size
<= 32);
7770 mode
= int_mode_for_size (size
* BITS_PER_UNIT
, 0).else_blk ();
7772 /* ??? We probably should have made the same ABI change in
7773 3.4.0 as the one we made for unions. The latter was
7774 required by the SCD though, while the former is not
7775 specified, so we favored compatibility and efficiency.
7777 Now we're stuck for aggregates larger than 16 bytes,
7778 because OImode vanished in the meantime. Let's not
7779 try to be unduly clever, and simply follow the ABI
7780 for unions in that case. */
7781 if (mode
== BLKmode
)
7782 return function_arg_union_value (size
, mode
, 0, regbase
);
7787 /* We should only have pointer and integer types at this point. This
7788 must match sparc_promote_function_mode. */
7789 else if (mclass
== MODE_INT
&& GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
7793 /* We should only have pointer and integer types at this point, except with
7794 -freg-struct-return. This must match sparc_promote_function_mode. */
7795 else if (TARGET_ARCH32
7796 && !(type
&& AGGREGATE_TYPE_P (type
))
7797 && mclass
== MODE_INT
7798 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
7801 if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
) && TARGET_FPU
)
7802 regno
= SPARC_FP_ARG_FIRST
;
7806 return gen_rtx_REG (mode
, regno
);
7809 /* Handle TARGET_FUNCTION_VALUE.
7810 On the SPARC, the value is found in the first "output" register, but the
7811 called function leaves it in the first "input" register. */
7814 sparc_function_value (const_tree valtype
,
7815 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
7818 return sparc_function_value_1 (valtype
, TYPE_MODE (valtype
), outgoing
);
7821 /* Handle TARGET_LIBCALL_VALUE. */
7824 sparc_libcall_value (machine_mode mode
,
7825 const_rtx fun ATTRIBUTE_UNUSED
)
7827 return sparc_function_value_1 (NULL_TREE
, mode
, false);
7830 /* Handle FUNCTION_VALUE_REGNO_P.
7831 On the SPARC, the first "output" reg is used for integer values, and the
7832 first floating point register is used for floating point values. */
7835 sparc_function_value_regno_p (const unsigned int regno
)
7837 return (regno
== 8 || (TARGET_FPU
&& regno
== 32));
7840 /* Do what is necessary for `va_start'. We look at the current function
7841 to determine if stdarg or varargs is used and return the address of
7842 the first unnamed parameter. */
7845 sparc_builtin_saveregs (void)
7847 int first_reg
= crtl
->args
.info
.words
;
7851 for (regno
= first_reg
; regno
< SPARC_INT_ARG_MAX
; regno
++)
7852 emit_move_insn (gen_rtx_MEM (word_mode
,
7853 gen_rtx_PLUS (Pmode
,
7855 GEN_INT (FIRST_PARM_OFFSET (0)
7858 gen_rtx_REG (word_mode
,
7859 SPARC_INCOMING_INT_ARG_FIRST
+ regno
));
7861 address
= gen_rtx_PLUS (Pmode
,
7863 GEN_INT (FIRST_PARM_OFFSET (0)
7864 + UNITS_PER_WORD
* first_reg
));
7869 /* Implement `va_start' for stdarg. */
7872 sparc_va_start (tree valist
, rtx nextarg
)
7874 nextarg
= expand_builtin_saveregs ();
7875 std_expand_builtin_va_start (valist
, nextarg
);
7878 /* Implement `va_arg' for stdarg. */
7881 sparc_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
7884 HOST_WIDE_INT size
, rsize
, align
;
7887 tree ptrtype
= build_pointer_type (type
);
7889 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
7892 size
= rsize
= UNITS_PER_WORD
;
7898 size
= int_size_in_bytes (type
);
7899 rsize
= ROUND_UP (size
, UNITS_PER_WORD
);
7904 /* For SPARC64, objects requiring 16-byte alignment get it. */
7905 if (TYPE_ALIGN (type
) >= 2 * (unsigned) BITS_PER_WORD
)
7906 align
= 2 * UNITS_PER_WORD
;
7908 /* SPARC-V9 ABI states that structures up to 16 bytes in size
7909 are left-justified in their slots. */
7910 if (AGGREGATE_TYPE_P (type
))
7913 size
= rsize
= UNITS_PER_WORD
;
7923 incr
= fold_build_pointer_plus_hwi (incr
, align
- 1);
7924 incr
= fold_convert (sizetype
, incr
);
7925 incr
= fold_build2 (BIT_AND_EXPR
, sizetype
, incr
,
7927 incr
= fold_convert (ptr_type_node
, incr
);
7930 gimplify_expr (&incr
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
7933 if (BYTES_BIG_ENDIAN
&& size
< rsize
)
7934 addr
= fold_build_pointer_plus_hwi (incr
, rsize
- size
);
7938 addr
= fold_convert (build_pointer_type (ptrtype
), addr
);
7939 addr
= build_va_arg_indirect_ref (addr
);
7942 /* If the address isn't aligned properly for the type, we need a temporary.
7943 FIXME: This is inefficient, usually we can do this in registers. */
7944 else if (align
== 0 && TYPE_ALIGN (type
) > BITS_PER_WORD
)
7946 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
7947 tree dest_addr
= build_fold_addr_expr (tmp
);
7948 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
7949 3, dest_addr
, addr
, size_int (rsize
));
7950 TREE_ADDRESSABLE (tmp
) = 1;
7951 gimplify_and_add (copy
, pre_p
);
7956 addr
= fold_convert (ptrtype
, addr
);
7958 incr
= fold_build_pointer_plus_hwi (incr
, rsize
);
7959 gimplify_assign (valist
, incr
, post_p
);
7961 return build_va_arg_indirect_ref (addr
);
7964 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
7965 Specify whether the vector mode is supported by the hardware. */
7968 sparc_vector_mode_supported_p (machine_mode mode
)
7970 return TARGET_VIS
&& VECTOR_MODE_P (mode
) ? true : false;
7973 /* Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook. */
7976 sparc_preferred_simd_mode (scalar_mode mode
)
7994 /* Return the string to output an unconditional branch to LABEL, which is
7995 the operand number of the label.
7997 DEST is the destination insn (i.e. the label), INSN is the source. */
8000 output_ubranch (rtx dest
, rtx_insn
*insn
)
8002 static char string
[64];
8003 bool v9_form
= false;
8007 /* Even if we are trying to use cbcond for this, evaluate
8008 whether we can use V9 branches as our backup plan. */
8011 if (INSN_ADDRESSES_SET_P ())
8012 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
8013 - INSN_ADDRESSES (INSN_UID (insn
)));
8015 /* Leave some instructions for "slop". */
8016 if (TARGET_V9
&& delta
>= -260000 && delta
< 260000)
8021 bool emit_nop
= emit_cbcond_nop (insn
);
8025 if (delta
< -500 || delta
> 500)
8031 rval
= "ba,a,pt\t%%xcc, %l0";
8038 rval
= "cwbe\t%%g0, %%g0, %l0\n\tnop";
8040 rval
= "cwbe\t%%g0, %%g0, %l0";
8046 strcpy (string
, "ba%*,pt\t%%xcc, ");
8048 strcpy (string
, "b%*\t");
8050 p
= strchr (string
, '\0');
8061 /* Return the string to output a conditional branch to LABEL, which is
8062 the operand number of the label. OP is the conditional expression.
8063 XEXP (OP, 0) is assumed to be a condition code register (integer or
8064 floating point) and its mode specifies what kind of comparison we made.
8066 DEST is the destination insn (i.e. the label), INSN is the source.
8068 REVERSED is nonzero if we should reverse the sense of the comparison.
8070 ANNUL is nonzero if we should generate an annulling branch. */
8073 output_cbranch (rtx op
, rtx dest
, int label
, int reversed
, int annul
,
8076 static char string
[64];
8077 enum rtx_code code
= GET_CODE (op
);
8078 rtx cc_reg
= XEXP (op
, 0);
8079 machine_mode mode
= GET_MODE (cc_reg
);
8080 const char *labelno
, *branch
;
8081 int spaces
= 8, far
;
8084 /* v9 branches are limited to +-1MB. If it is too far away,
8097 fbne,a,pn %fcc2, .LC29
8105 far
= TARGET_V9
&& (get_attr_length (insn
) >= 3);
8108 /* Reversal of FP compares takes care -- an ordered compare
8109 becomes an unordered compare and vice versa. */
8110 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
8111 code
= reverse_condition_maybe_unordered (code
);
8113 code
= reverse_condition (code
);
8116 /* Start by writing the branch condition. */
8117 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
8167 /* ??? !v9: FP branches cannot be preceded by another floating point
8168 insn. Because there is currently no concept of pre-delay slots,
8169 we can fix this only by always emitting a nop before a floating
8174 strcpy (string
, "nop\n\t");
8175 strcat (string
, branch
);
8182 if (mode
== CCVmode
|| mode
== CCXVmode
)
8188 if (mode
== CCVmode
|| mode
== CCXVmode
)
8194 if (mode
== CCNZmode
|| mode
== CCXNZmode
)
8206 if (mode
== CCNZmode
|| mode
== CCXNZmode
)
8226 strcpy (string
, branch
);
8228 spaces
-= strlen (branch
);
8229 p
= strchr (string
, '\0');
8231 /* Now add the annulling, the label, and a possible noop. */
8244 if (! far
&& insn
&& INSN_ADDRESSES_SET_P ())
8246 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
8247 - INSN_ADDRESSES (INSN_UID (insn
)));
8248 /* Leave some instructions for "slop". */
8249 if (delta
< -260000 || delta
>= 260000)
8259 labelno
= "%%icc, ";
8267 labelno
= "%%xcc, ";
8273 static char v9_fcc_labelno
[] = "%%fccX, ";
8274 /* Set the char indicating the number of the fcc reg to use. */
8275 v9_fcc_labelno
[5] = REGNO (cc_reg
) - SPARC_FIRST_V9_FCC_REG
+ '0';
8276 labelno
= v9_fcc_labelno
;
8279 gcc_assert (REGNO (cc_reg
) == SPARC_FCC_REG
);
8288 if (*labelno
&& insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
8291 ((profile_probability::from_reg_br_prob_note (XINT (note
, 0))
8292 >= profile_probability::even ()) ^ far
)
8305 strcpy (p
, labelno
);
8306 p
= strchr (p
, '\0');
8309 strcpy (p
, ".+12\n\t nop\n\tb\t");
8310 /* Skip the next insn if requested or
8311 if we know that it will be a nop. */
8312 if (annul
|| ! final_sequence
)
8326 /* Emit a library call comparison between floating point X and Y.
8327 COMPARISON is the operator to compare with (EQ, NE, GT, etc).
8328 Return the new operator to be used in the comparison sequence.
8330 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
8331 values as arguments instead of the TFmode registers themselves,
8332 that's why we cannot call emit_float_lib_cmp. */
8335 sparc_emit_float_lib_cmp (rtx x
, rtx y
, enum rtx_code comparison
)
8338 rtx slot0
, slot1
, result
, tem
, tem2
, libfunc
;
8340 enum rtx_code new_comparison
;
8345 qpfunc
= (TARGET_ARCH64
? "_Qp_feq" : "_Q_feq");
8349 qpfunc
= (TARGET_ARCH64
? "_Qp_fne" : "_Q_fne");
8353 qpfunc
= (TARGET_ARCH64
? "_Qp_fgt" : "_Q_fgt");
8357 qpfunc
= (TARGET_ARCH64
? "_Qp_fge" : "_Q_fge");
8361 qpfunc
= (TARGET_ARCH64
? "_Qp_flt" : "_Q_flt");
8365 qpfunc
= (TARGET_ARCH64
? "_Qp_fle" : "_Q_fle");
8376 qpfunc
= (TARGET_ARCH64
? "_Qp_cmp" : "_Q_cmp");
8387 tree expr
= MEM_EXPR (x
);
8389 mark_addressable (expr
);
8394 slot0
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
));
8395 emit_move_insn (slot0
, x
);
8400 tree expr
= MEM_EXPR (y
);
8402 mark_addressable (expr
);
8407 slot1
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
));
8408 emit_move_insn (slot1
, y
);
8411 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
8412 emit_library_call (libfunc
, LCT_NORMAL
,
8414 XEXP (slot0
, 0), Pmode
,
8415 XEXP (slot1
, 0), Pmode
);
8420 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
8421 emit_library_call (libfunc
, LCT_NORMAL
,
8423 x
, TFmode
, y
, TFmode
);
8428 /* Immediately move the result of the libcall into a pseudo
8429 register so reload doesn't clobber the value if it needs
8430 the return register for a spill reg. */
8431 result
= gen_reg_rtx (mode
);
8432 emit_move_insn (result
, hard_libcall_value (mode
, libfunc
));
8437 return gen_rtx_NE (VOIDmode
, result
, const0_rtx
);
8440 new_comparison
= (comparison
== UNORDERED
? EQ
: NE
);
8441 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, GEN_INT(3));
8444 new_comparison
= (comparison
== UNGT
? GT
: NE
);
8445 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, const1_rtx
);
8447 return gen_rtx_NE (VOIDmode
, result
, const2_rtx
);
8449 tem
= gen_reg_rtx (mode
);
8451 emit_insn (gen_andsi3 (tem
, result
, const1_rtx
));
8453 emit_insn (gen_anddi3 (tem
, result
, const1_rtx
));
8454 return gen_rtx_NE (VOIDmode
, tem
, const0_rtx
);
8457 tem
= gen_reg_rtx (mode
);
8459 emit_insn (gen_addsi3 (tem
, result
, const1_rtx
));
8461 emit_insn (gen_adddi3 (tem
, result
, const1_rtx
));
8462 tem2
= gen_reg_rtx (mode
);
8464 emit_insn (gen_andsi3 (tem2
, tem
, const2_rtx
));
8466 emit_insn (gen_anddi3 (tem2
, tem
, const2_rtx
));
8467 new_comparison
= (comparison
== UNEQ
? EQ
: NE
);
8468 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, tem2
, const0_rtx
);
8474 /* Generate an unsigned DImode to FP conversion. This is the same code
8475 optabs would emit if we didn't have TFmode patterns. */
8478 sparc_emit_floatunsdi (rtx
*operands
, machine_mode mode
)
8480 rtx i0
, i1
, f0
, in
, out
;
8483 in
= force_reg (DImode
, operands
[1]);
8484 rtx_code_label
*neglab
= gen_label_rtx ();
8485 rtx_code_label
*donelab
= gen_label_rtx ();
8486 i0
= gen_reg_rtx (DImode
);
8487 i1
= gen_reg_rtx (DImode
);
8488 f0
= gen_reg_rtx (mode
);
8490 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
8492 emit_insn (gen_rtx_SET (out
, gen_rtx_FLOAT (mode
, in
)));
8493 emit_jump_insn (gen_jump (donelab
));
8496 emit_label (neglab
);
8498 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
8499 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
8500 emit_insn (gen_iordi3 (i0
, i0
, i1
));
8501 emit_insn (gen_rtx_SET (f0
, gen_rtx_FLOAT (mode
, i0
)));
8502 emit_insn (gen_rtx_SET (out
, gen_rtx_PLUS (mode
, f0
, f0
)));
8504 emit_label (donelab
);
8507 /* Generate an FP to unsigned DImode conversion. This is the same code
8508 optabs would emit if we didn't have TFmode patterns. */
8511 sparc_emit_fixunsdi (rtx
*operands
, machine_mode mode
)
8513 rtx i0
, i1
, f0
, in
, out
, limit
;
8516 in
= force_reg (mode
, operands
[1]);
8517 rtx_code_label
*neglab
= gen_label_rtx ();
8518 rtx_code_label
*donelab
= gen_label_rtx ();
8519 i0
= gen_reg_rtx (DImode
);
8520 i1
= gen_reg_rtx (DImode
);
8521 limit
= gen_reg_rtx (mode
);
8522 f0
= gen_reg_rtx (mode
);
8524 emit_move_insn (limit
,
8525 const_double_from_real_value (
8526 REAL_VALUE_ATOF ("9223372036854775808.0", mode
), mode
));
8527 emit_cmp_and_jump_insns (in
, limit
, GE
, NULL_RTX
, mode
, 0, neglab
);
8529 emit_insn (gen_rtx_SET (out
,
8530 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, in
))));
8531 emit_jump_insn (gen_jump (donelab
));
8534 emit_label (neglab
);
8536 emit_insn (gen_rtx_SET (f0
, gen_rtx_MINUS (mode
, in
, limit
)));
8537 emit_insn (gen_rtx_SET (i0
,
8538 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, f0
))));
8539 emit_insn (gen_movdi (i1
, const1_rtx
));
8540 emit_insn (gen_ashldi3 (i1
, i1
, GEN_INT (63)));
8541 emit_insn (gen_xordi3 (out
, i0
, i1
));
8543 emit_label (donelab
);
8546 /* Return the string to output a compare and branch instruction to DEST.
8547 DEST is the destination insn (i.e. the label), INSN is the source,
8548 and OP is the conditional expression. */
8551 output_cbcond (rtx op
, rtx dest
, rtx_insn
*insn
)
8553 machine_mode mode
= GET_MODE (XEXP (op
, 0));
8554 enum rtx_code code
= GET_CODE (op
);
8555 const char *cond_str
, *tmpl
;
8556 int far
, emit_nop
, len
;
8557 static char string
[64];
8560 /* Compare and Branch is limited to +-2KB. If it is too far away,
8572 len
= get_attr_length (insn
);
8575 emit_nop
= len
== 2;
8578 code
= reverse_condition (code
);
8580 size_char
= ((mode
== SImode
) ? 'w' : 'x');
8630 int veryfar
= 1, delta
;
8632 if (INSN_ADDRESSES_SET_P ())
8634 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
8635 - INSN_ADDRESSES (INSN_UID (insn
)));
8636 /* Leave some instructions for "slop". */
8637 if (delta
>= -260000 && delta
< 260000)
8642 tmpl
= "c%cb%s\t%%1, %%2, .+16\n\tnop\n\tb\t%%3\n\tnop";
8644 tmpl
= "c%cb%s\t%%1, %%2, .+16\n\tnop\n\tba,pt\t%%%%xcc, %%3\n\tnop";
8649 tmpl
= "c%cb%s\t%%1, %%2, %%3\n\tnop";
8651 tmpl
= "c%cb%s\t%%1, %%2, %%3";
8654 snprintf (string
, sizeof(string
), tmpl
, size_char
, cond_str
);
8659 /* Return the string to output a conditional branch to LABEL, testing
8660 register REG. LABEL is the operand number of the label; REG is the
8661 operand number of the reg. OP is the conditional expression. The mode
8662 of REG says what kind of comparison we made.
8664 DEST is the destination insn (i.e. the label), INSN is the source.
8666 REVERSED is nonzero if we should reverse the sense of the comparison.
8668 ANNUL is nonzero if we should generate an annulling branch. */
8671 output_v9branch (rtx op
, rtx dest
, int reg
, int label
, int reversed
,
8672 int annul
, rtx_insn
*insn
)
8674 static char string
[64];
8675 enum rtx_code code
= GET_CODE (op
);
8676 machine_mode mode
= GET_MODE (XEXP (op
, 0));
8681 /* branch on register are limited to +-128KB. If it is too far away,
8694 brgez,a,pn %o1, .LC29
8700 ba,pt %xcc, .LC29 */
8702 far
= get_attr_length (insn
) >= 3;
8704 /* If not floating-point or if EQ or NE, we can just reverse the code. */
8706 code
= reverse_condition (code
);
8708 /* Only 64-bit versions of these instructions exist. */
8709 gcc_assert (mode
== DImode
);
8711 /* Start by writing the branch condition. */
8716 strcpy (string
, "brnz");
8720 strcpy (string
, "brz");
8724 strcpy (string
, "brgez");
8728 strcpy (string
, "brlz");
8732 strcpy (string
, "brlez");
8736 strcpy (string
, "brgz");
8743 p
= strchr (string
, '\0');
8745 /* Now add the annulling, reg, label, and nop. */
8752 if (insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
8755 ((profile_probability::from_reg_br_prob_note (XINT (note
, 0))
8756 >= profile_probability::even ()) ^ far
)
8761 *p
= p
< string
+ 8 ? '\t' : ' ';
8769 int veryfar
= 1, delta
;
8771 if (INSN_ADDRESSES_SET_P ())
8773 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
8774 - INSN_ADDRESSES (INSN_UID (insn
)));
8775 /* Leave some instructions for "slop". */
8776 if (delta
>= -260000 && delta
< 260000)
8780 strcpy (p
, ".+12\n\t nop\n\t");
8781 /* Skip the next insn if requested or
8782 if we know that it will be a nop. */
8783 if (annul
|| ! final_sequence
)
8793 strcpy (p
, "ba,pt\t%%xcc, ");
8807 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
8808 Such instructions cannot be used in the delay slot of return insn on v9.
8809 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
8813 epilogue_renumber (register rtx
*where
, int test
)
8815 register const char *fmt
;
8817 register enum rtx_code code
;
8822 code
= GET_CODE (*where
);
8827 if (REGNO (*where
) >= 8 && REGNO (*where
) < 24) /* oX or lX */
8829 if (! test
&& REGNO (*where
) >= 24 && REGNO (*where
) < 32)
8830 *where
= gen_rtx_REG (GET_MODE (*where
), OUTGOING_REGNO (REGNO(*where
)));
8836 case CONST_WIDE_INT
:
8840 /* Do not replace the frame pointer with the stack pointer because
8841 it can cause the delayed instruction to load below the stack.
8842 This occurs when instructions like:
8844 (set (reg/i:SI 24 %i0)
8845 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
8846 (const_int -20 [0xffffffec])) 0))
8848 are in the return delayed slot. */
8850 if (GET_CODE (XEXP (*where
, 0)) == REG
8851 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
8852 && (GET_CODE (XEXP (*where
, 1)) != CONST_INT
8853 || INTVAL (XEXP (*where
, 1)) < SPARC_STACK_BIAS
))
8858 if (SPARC_STACK_BIAS
8859 && GET_CODE (XEXP (*where
, 0)) == REG
8860 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
)
8868 fmt
= GET_RTX_FORMAT (code
);
8870 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8875 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
8876 if (epilogue_renumber (&(XVECEXP (*where
, i
, j
)), test
))
8879 else if (fmt
[i
] == 'e'
8880 && epilogue_renumber (&(XEXP (*where
, i
)), test
))
8886 /* Leaf functions and non-leaf functions have different needs. */
8889 reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
8892 reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
8894 static const int *const reg_alloc_orders
[] = {
8895 reg_leaf_alloc_order
,
8896 reg_nonleaf_alloc_order
};
8899 order_regs_for_local_alloc (void)
8901 static int last_order_nonleaf
= 1;
8903 if (df_regs_ever_live_p (15) != last_order_nonleaf
)
8905 last_order_nonleaf
= !last_order_nonleaf
;
8906 memcpy ((char *) reg_alloc_order
,
8907 (const char *) reg_alloc_orders
[last_order_nonleaf
],
8908 FIRST_PSEUDO_REGISTER
* sizeof (int));
8912 /* Return 1 if REG and MEM are legitimate enough to allow the various
8913 MEM<-->REG splits to be run. */
8916 sparc_split_reg_mem_legitimate (rtx reg
, rtx mem
)
8918 /* Punt if we are here by mistake. */
8919 gcc_assert (reload_completed
);
8921 /* We must have an offsettable memory reference. */
8922 if (!offsettable_memref_p (mem
))
8925 /* If we have legitimate args for ldd/std, we do not want
8926 the split to happen. */
8927 if ((REGNO (reg
) % 2) == 0 && mem_min_alignment (mem
, 8))
8934 /* Split a REG <-- MEM move into a pair of moves in MODE. */
8937 sparc_split_reg_mem (rtx dest
, rtx src
, machine_mode mode
)
8939 rtx high_part
= gen_highpart (mode
, dest
);
8940 rtx low_part
= gen_lowpart (mode
, dest
);
8941 rtx word0
= adjust_address (src
, mode
, 0);
8942 rtx word1
= adjust_address (src
, mode
, 4);
8944 if (reg_overlap_mentioned_p (high_part
, word1
))
8946 emit_move_insn_1 (low_part
, word1
);
8947 emit_move_insn_1 (high_part
, word0
);
8951 emit_move_insn_1 (high_part
, word0
);
8952 emit_move_insn_1 (low_part
, word1
);
8956 /* Split a MEM <-- REG move into a pair of moves in MODE. */
8959 sparc_split_mem_reg (rtx dest
, rtx src
, machine_mode mode
)
8961 rtx word0
= adjust_address (dest
, mode
, 0);
8962 rtx word1
= adjust_address (dest
, mode
, 4);
8963 rtx high_part
= gen_highpart (mode
, src
);
8964 rtx low_part
= gen_lowpart (mode
, src
);
8966 emit_move_insn_1 (word0
, high_part
);
8967 emit_move_insn_1 (word1
, low_part
);
8970 /* Like sparc_split_reg_mem_legitimate but for REG <--> REG moves. */
8973 sparc_split_reg_reg_legitimate (rtx reg1
, rtx reg2
)
8975 /* Punt if we are here by mistake. */
8976 gcc_assert (reload_completed
);
8978 if (GET_CODE (reg1
) == SUBREG
)
8979 reg1
= SUBREG_REG (reg1
);
8980 if (GET_CODE (reg1
) != REG
)
8982 const int regno1
= REGNO (reg1
);
8984 if (GET_CODE (reg2
) == SUBREG
)
8985 reg2
= SUBREG_REG (reg2
);
8986 if (GET_CODE (reg2
) != REG
)
8988 const int regno2
= REGNO (reg2
);
8990 if (SPARC_INT_REG_P (regno1
) && SPARC_INT_REG_P (regno2
))
8995 if ((SPARC_INT_REG_P (regno1
) && SPARC_FP_REG_P (regno2
))
8996 || (SPARC_FP_REG_P (regno1
) && SPARC_INT_REG_P (regno2
)))
9003 /* Split a REG <--> REG move into a pair of moves in MODE. */
9006 sparc_split_reg_reg (rtx dest
, rtx src
, machine_mode mode
)
9008 rtx dest1
= gen_highpart (mode
, dest
);
9009 rtx dest2
= gen_lowpart (mode
, dest
);
9010 rtx src1
= gen_highpart (mode
, src
);
9011 rtx src2
= gen_lowpart (mode
, src
);
9013 /* Now emit using the real source and destination we found, swapping
9014 the order if we detect overlap. */
9015 if (reg_overlap_mentioned_p (dest1
, src2
))
9017 emit_move_insn_1 (dest2
, src2
);
9018 emit_move_insn_1 (dest1
, src1
);
9022 emit_move_insn_1 (dest1
, src1
);
9023 emit_move_insn_1 (dest2
, src2
);
9027 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
9028 This makes them candidates for using ldd and std insns.
9030 Note reg1 and reg2 *must* be hard registers. */
9033 registers_ok_for_ldd_peep (rtx reg1
, rtx reg2
)
9035 /* We might have been passed a SUBREG. */
9036 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
9039 if (REGNO (reg1
) % 2 != 0)
9042 /* Integer ldd is deprecated in SPARC V9 */
9043 if (TARGET_V9
&& SPARC_INT_REG_P (REGNO (reg1
)))
9046 return (REGNO (reg1
) == REGNO (reg2
) - 1);
9049 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
9052 This can only happen when addr1 and addr2, the addresses in mem1
9053 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
9054 addr1 must also be aligned on a 64-bit boundary.
9056 Also iff dependent_reg_rtx is not null it should not be used to
9057 compute the address for mem1, i.e. we cannot optimize a sequence
9069 But, note that the transformation from:
9074 is perfectly fine. Thus, the peephole2 patterns always pass us
9075 the destination register of the first load, never the second one.
9077 For stores we don't have a similar problem, so dependent_reg_rtx is
9081 mems_ok_for_ldd_peep (rtx mem1
, rtx mem2
, rtx dependent_reg_rtx
)
9085 HOST_WIDE_INT offset1
;
9087 /* The mems cannot be volatile. */
9088 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
9091 /* MEM1 should be aligned on a 64-bit boundary. */
9092 if (MEM_ALIGN (mem1
) < 64)
9095 addr1
= XEXP (mem1
, 0);
9096 addr2
= XEXP (mem2
, 0);
9098 /* Extract a register number and offset (if used) from the first addr. */
9099 if (GET_CODE (addr1
) == PLUS
)
9101 /* If not a REG, return zero. */
9102 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
9106 reg1
= REGNO (XEXP (addr1
, 0));
9107 /* The offset must be constant! */
9108 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
9110 offset1
= INTVAL (XEXP (addr1
, 1));
9113 else if (GET_CODE (addr1
) != REG
)
9117 reg1
= REGNO (addr1
);
9118 /* This was a simple (mem (reg)) expression. Offset is 0. */
9122 /* Make sure the second address is a (mem (plus (reg) (const_int). */
9123 if (GET_CODE (addr2
) != PLUS
)
9126 if (GET_CODE (XEXP (addr2
, 0)) != REG
9127 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
9130 if (reg1
!= REGNO (XEXP (addr2
, 0)))
9133 if (dependent_reg_rtx
!= NULL_RTX
&& reg1
== REGNO (dependent_reg_rtx
))
9136 /* The first offset must be evenly divisible by 8 to ensure the
9137 address is 64-bit aligned. */
9138 if (offset1
% 8 != 0)
9141 /* The offset for the second addr must be 4 more than the first addr. */
9142 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
9145 /* All the tests passed. addr1 and addr2 are valid for ldd and std
9150 /* Return the widened memory access made of MEM1 and MEM2 in MODE. */
9153 widen_mem_for_ldd_peep (rtx mem1
, rtx mem2
, machine_mode mode
)
9155 rtx x
= widen_memory_access (mem1
, mode
, 0);
9156 MEM_NOTRAP_P (x
) = MEM_NOTRAP_P (mem1
) && MEM_NOTRAP_P (mem2
);
9160 /* Return 1 if reg is a pseudo, or is the first register in
9161 a hard register pair. This makes it suitable for use in
9162 ldd and std insns. */
9165 register_ok_for_ldd (rtx reg
)
9167 /* We might have been passed a SUBREG. */
9171 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
9172 return (REGNO (reg
) % 2 == 0);
9177 /* Return 1 if OP, a MEM, has an address which is known to be
9178 aligned to an 8-byte boundary. */
9181 memory_ok_for_ldd (rtx op
)
9183 /* In 64-bit mode, we assume that the address is word-aligned. */
9184 if (TARGET_ARCH32
&& !mem_min_alignment (op
, 8))
9187 if (! can_create_pseudo_p ()
9188 && !strict_memory_address_p (Pmode
, XEXP (op
, 0)))
9194 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
9197 sparc_print_operand_punct_valid_p (unsigned char code
)
9210 /* Implement TARGET_PRINT_OPERAND.
9211 Print operand X (an rtx) in assembler syntax to file FILE.
9212 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
9213 For `%' followed by punctuation, CODE is the punctuation and X is null. */
9216 sparc_print_operand (FILE *file
, rtx x
, int code
)
9223 /* Output an insn in a delay slot. */
9225 sparc_indent_opcode
= 1;
9227 fputs ("\n\t nop", file
);
9230 /* Output an annul flag if there's nothing for the delay slot and we
9231 are optimizing. This is always used with '(' below.
9232 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
9233 this is a dbx bug. So, we only do this when optimizing.
9234 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
9235 Always emit a nop in case the next instruction is a branch. */
9236 if (! final_sequence
&& (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
9240 /* Output a 'nop' if there's nothing for the delay slot and we are
9241 not optimizing. This is always used with '*' above. */
9242 if (! final_sequence
&& ! (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
9243 fputs ("\n\t nop", file
);
9244 else if (final_sequence
)
9245 sparc_indent_opcode
= 1;
9248 /* Output the right displacement from the saved PC on function return.
9249 The caller may have placed an "unimp" insn immediately after the call
9250 so we have to account for it. This insn is used in the 32-bit ABI
9251 when calling a function that returns a non zero-sized structure. The
9252 64-bit ABI doesn't have it. Be careful to have this test be the same
9253 as that for the call. The exception is when sparc_std_struct_return
9254 is enabled, the psABI is followed exactly and the adjustment is made
9255 by the code in sparc_struct_value_rtx. The call emitted is the same
9256 when sparc_std_struct_return is enabled. */
9258 && cfun
->returns_struct
9259 && !sparc_std_struct_return
9260 && DECL_SIZE (DECL_RESULT (current_function_decl
))
9261 && TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl
)))
9263 && !integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl
))))
9269 /* Output the Embedded Medium/Anywhere code model base register. */
9270 fputs (EMBMEDANY_BASE_REG
, file
);
9273 /* Print some local dynamic TLS name. */
9274 if (const char *name
= get_some_local_dynamic_name ())
9275 assemble_name (file
, name
);
9277 output_operand_lossage ("'%%&' used without any "
9278 "local dynamic TLS references");
9282 /* Adjust the operand to take into account a RESTORE operation. */
9283 if (GET_CODE (x
) == CONST_INT
)
9285 else if (GET_CODE (x
) != REG
)
9286 output_operand_lossage ("invalid %%Y operand");
9287 else if (REGNO (x
) < 8)
9288 fputs (reg_names
[REGNO (x
)], file
);
9289 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
9290 fputs (reg_names
[REGNO (x
)-16], file
);
9292 output_operand_lossage ("invalid %%Y operand");
9295 /* Print out the low order register name of a register pair. */
9296 if (WORDS_BIG_ENDIAN
)
9297 fputs (reg_names
[REGNO (x
)+1], file
);
9299 fputs (reg_names
[REGNO (x
)], file
);
9302 /* Print out the high order register name of a register pair. */
9303 if (WORDS_BIG_ENDIAN
)
9304 fputs (reg_names
[REGNO (x
)], file
);
9306 fputs (reg_names
[REGNO (x
)+1], file
);
9309 /* Print out the second register name of a register pair or quad.
9310 I.e., R (%o0) => %o1. */
9311 fputs (reg_names
[REGNO (x
)+1], file
);
9314 /* Print out the third register name of a register quad.
9315 I.e., S (%o0) => %o2. */
9316 fputs (reg_names
[REGNO (x
)+2], file
);
9319 /* Print out the fourth register name of a register quad.
9320 I.e., T (%o0) => %o3. */
9321 fputs (reg_names
[REGNO (x
)+3], file
);
9324 /* Print a condition code register. */
9325 if (REGNO (x
) == SPARC_ICC_REG
)
9327 switch (GET_MODE (x
))
9347 /* %fccN register */
9348 fputs (reg_names
[REGNO (x
)], file
);
9351 /* Print the operand's address only. */
9352 output_address (GET_MODE (x
), XEXP (x
, 0));
9355 /* In this case we need a register. Use %g0 if the
9356 operand is const0_rtx. */
9358 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
9360 fputs ("%g0", file
);
9367 switch (GET_CODE (x
))
9379 output_operand_lossage ("invalid %%A operand");
9387 switch (GET_CODE (x
))
9399 output_operand_lossage ("invalid %%B operand");
9406 /* This is used by the conditional move instructions. */
9409 machine_mode mode
= GET_MODE (XEXP (x
, 0));
9410 switch (GET_CODE (x
))
9413 if (mode
== CCVmode
|| mode
== CCXVmode
)
9419 if (mode
== CCVmode
|| mode
== CCXVmode
)
9425 if (mode
== CCNZmode
|| mode
== CCXNZmode
)
9437 if (mode
== CCNZmode
|| mode
== CCXNZmode
)
9479 output_operand_lossage ("invalid %%C operand");
9487 /* This are used by the movr instruction pattern. */
9490 switch (GET_CODE (x
))
9511 output_operand_lossage ("invalid %%D operand");
9521 /* Print a sign-extended character. */
9522 int i
= trunc_int_for_mode (INTVAL (x
), QImode
);
9523 fprintf (file
, "%d", i
);
9528 /* Operand must be a MEM; write its address. */
9529 if (GET_CODE (x
) != MEM
)
9530 output_operand_lossage ("invalid %%f operand");
9531 output_address (GET_MODE (x
), XEXP (x
, 0));
9536 /* Print a sign-extended 32-bit value. */
9538 if (GET_CODE(x
) == CONST_INT
)
9542 output_operand_lossage ("invalid %%s operand");
9545 i
= trunc_int_for_mode (i
, SImode
);
9546 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, i
);
9551 /* Do nothing special. */
9555 /* Undocumented flag. */
9556 output_operand_lossage ("invalid operand output code");
9559 if (GET_CODE (x
) == REG
)
9560 fputs (reg_names
[REGNO (x
)], file
);
9561 else if (GET_CODE (x
) == MEM
)
9564 /* Poor Sun assembler doesn't understand absolute addressing. */
9565 if (CONSTANT_P (XEXP (x
, 0)))
9566 fputs ("%g0+", file
);
9567 output_address (GET_MODE (x
), XEXP (x
, 0));
9570 else if (GET_CODE (x
) == HIGH
)
9572 fputs ("%hi(", file
);
9573 output_addr_const (file
, XEXP (x
, 0));
9576 else if (GET_CODE (x
) == LO_SUM
)
9578 sparc_print_operand (file
, XEXP (x
, 0), 0);
9579 if (TARGET_CM_MEDMID
)
9580 fputs ("+%l44(", file
);
9582 fputs ("+%lo(", file
);
9583 output_addr_const (file
, XEXP (x
, 1));
9586 else if (GET_CODE (x
) == CONST_DOUBLE
)
9587 output_operand_lossage ("floating-point constant not a valid immediate operand");
9589 output_addr_const (file
, x
);
9592 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
9595 sparc_print_operand_address (FILE *file
, machine_mode
/*mode*/, rtx x
)
9597 register rtx base
, index
= 0;
9599 register rtx addr
= x
;
9602 fputs (reg_names
[REGNO (addr
)], file
);
9603 else if (GET_CODE (addr
) == PLUS
)
9605 if (CONST_INT_P (XEXP (addr
, 0)))
9606 offset
= INTVAL (XEXP (addr
, 0)), base
= XEXP (addr
, 1);
9607 else if (CONST_INT_P (XEXP (addr
, 1)))
9608 offset
= INTVAL (XEXP (addr
, 1)), base
= XEXP (addr
, 0);
9610 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
9611 if (GET_CODE (base
) == LO_SUM
)
9613 gcc_assert (USE_AS_OFFSETABLE_LO10
9615 && ! TARGET_CM_MEDMID
);
9616 output_operand (XEXP (base
, 0), 0);
9617 fputs ("+%lo(", file
);
9618 output_address (VOIDmode
, XEXP (base
, 1));
9619 fprintf (file
, ")+%d", offset
);
9623 fputs (reg_names
[REGNO (base
)], file
);
9625 fprintf (file
, "%+d", offset
);
9626 else if (REG_P (index
))
9627 fprintf (file
, "+%s", reg_names
[REGNO (index
)]);
9628 else if (GET_CODE (index
) == SYMBOL_REF
9629 || GET_CODE (index
) == LABEL_REF
9630 || GET_CODE (index
) == CONST
)
9631 fputc ('+', file
), output_addr_const (file
, index
);
9632 else gcc_unreachable ();
9635 else if (GET_CODE (addr
) == MINUS
9636 && GET_CODE (XEXP (addr
, 1)) == LABEL_REF
)
9638 output_addr_const (file
, XEXP (addr
, 0));
9640 output_addr_const (file
, XEXP (addr
, 1));
9641 fputs ("-.)", file
);
9643 else if (GET_CODE (addr
) == LO_SUM
)
9645 output_operand (XEXP (addr
, 0), 0);
9646 if (TARGET_CM_MEDMID
)
9647 fputs ("+%l44(", file
);
9649 fputs ("+%lo(", file
);
9650 output_address (VOIDmode
, XEXP (addr
, 1));
9654 && GET_CODE (addr
) == CONST
9655 && GET_CODE (XEXP (addr
, 0)) == MINUS
9656 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST
9657 && GET_CODE (XEXP (XEXP (XEXP (addr
, 0), 1), 0)) == MINUS
9658 && XEXP (XEXP (XEXP (XEXP (addr
, 0), 1), 0), 1) == pc_rtx
)
9660 addr
= XEXP (addr
, 0);
9661 output_addr_const (file
, XEXP (addr
, 0));
9662 /* Group the args of the second CONST in parenthesis. */
9664 /* Skip past the second CONST--it does nothing for us. */
9665 output_addr_const (file
, XEXP (XEXP (addr
, 1), 0));
9666 /* Close the parenthesis. */
9671 output_addr_const (file
, addr
);
9675 /* Target hook for assembling integer objects. The sparc version has
9676 special handling for aligned DI-mode objects. */
9679 sparc_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
9681 /* ??? We only output .xword's for symbols and only then in environments
9682 where the assembler can handle them. */
9683 if (aligned_p
&& size
== 8 && GET_CODE (x
) != CONST_INT
)
9687 assemble_integer_with_op ("\t.xword\t", x
);
9692 assemble_aligned_integer (4, const0_rtx
);
9693 assemble_aligned_integer (4, x
);
9697 return default_assemble_integer (x
, size
, aligned_p
);
9700 /* Return the value of a code used in the .proc pseudo-op that says
9701 what kind of result this function returns. For non-C types, we pick
9702 the closest C type. */
9704 #ifndef SHORT_TYPE_SIZE
9705 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
9708 #ifndef INT_TYPE_SIZE
9709 #define INT_TYPE_SIZE BITS_PER_WORD
9712 #ifndef LONG_TYPE_SIZE
9713 #define LONG_TYPE_SIZE BITS_PER_WORD
9716 #ifndef LONG_LONG_TYPE_SIZE
9717 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
9720 #ifndef FLOAT_TYPE_SIZE
9721 #define FLOAT_TYPE_SIZE BITS_PER_WORD
9724 #ifndef DOUBLE_TYPE_SIZE
9725 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
9728 #ifndef LONG_DOUBLE_TYPE_SIZE
9729 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
9733 sparc_type_code (register tree type
)
9735 register unsigned long qualifiers
= 0;
9736 register unsigned shift
;
9738 /* Only the first 30 bits of the qualifier are valid. We must refrain from
9739 setting more, since some assemblers will give an error for this. Also,
9740 we must be careful to avoid shifts of 32 bits or more to avoid getting
9741 unpredictable results. */
9743 for (shift
= 6; shift
< 30; shift
+= 2, type
= TREE_TYPE (type
))
9745 switch (TREE_CODE (type
))
9751 qualifiers
|= (3 << shift
);
9756 qualifiers
|= (2 << shift
);
9760 case REFERENCE_TYPE
:
9762 qualifiers
|= (1 << shift
);
9766 return (qualifiers
| 8);
9769 case QUAL_UNION_TYPE
:
9770 return (qualifiers
| 9);
9773 return (qualifiers
| 10);
9776 return (qualifiers
| 16);
9779 /* If this is a range type, consider it to be the underlying
9781 if (TREE_TYPE (type
) != 0)
9784 /* Carefully distinguish all the standard types of C,
9785 without messing up if the language is not C. We do this by
9786 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
9787 look at both the names and the above fields, but that's redundant.
9788 Any type whose size is between two C types will be considered
9789 to be the wider of the two types. Also, we do not have a
9790 special code to use for "long long", so anything wider than
9791 long is treated the same. Note that we can't distinguish
9792 between "int" and "long" in this code if they are the same
9793 size, but that's fine, since neither can the assembler. */
9795 if (TYPE_PRECISION (type
) <= CHAR_TYPE_SIZE
)
9796 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 12 : 2));
9798 else if (TYPE_PRECISION (type
) <= SHORT_TYPE_SIZE
)
9799 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 13 : 3));
9801 else if (TYPE_PRECISION (type
) <= INT_TYPE_SIZE
)
9802 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 14 : 4));
9805 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 15 : 5));
9808 /* If this is a range type, consider it to be the underlying
9810 if (TREE_TYPE (type
) != 0)
9813 /* Carefully distinguish all the standard types of C,
9814 without messing up if the language is not C. */
9816 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
9817 return (qualifiers
| 6);
9820 return (qualifiers
| 7);
9822 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
9823 /* ??? We need to distinguish between double and float complex types,
9824 but I don't know how yet because I can't reach this code from
9825 existing front-ends. */
9826 return (qualifiers
| 7); /* Who knows? */
9829 case BOOLEAN_TYPE
: /* Boolean truth value type. */
9835 gcc_unreachable (); /* Not a type! */
9842 /* Nested function support. */
9844 /* Emit RTL insns to initialize the variable parts of a trampoline.
9845 FNADDR is an RTX for the address of the function's pure code.
9846 CXT is an RTX for the static chain value for the function.
9848 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
9849 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
9850 (to store insns). This is a bit excessive. Perhaps a different
9851 mechanism would be better here.
9853 Emit enough FLUSH insns to synchronize the data and instruction caches. */
9856 sparc32_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
9858 /* SPARC 32-bit trampoline:
9861 sethi %hi(static), %g2
9863 or %g2, %lo(static), %g2
9865 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
9866 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
9870 (adjust_address (m_tramp
, SImode
, 0),
9871 expand_binop (SImode
, ior_optab
,
9872 expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
, 10, 0, 1),
9873 GEN_INT (trunc_int_for_mode (0x03000000, SImode
)),
9874 NULL_RTX
, 1, OPTAB_DIRECT
));
9877 (adjust_address (m_tramp
, SImode
, 4),
9878 expand_binop (SImode
, ior_optab
,
9879 expand_shift (RSHIFT_EXPR
, SImode
, cxt
, 10, 0, 1),
9880 GEN_INT (trunc_int_for_mode (0x05000000, SImode
)),
9881 NULL_RTX
, 1, OPTAB_DIRECT
));
9884 (adjust_address (m_tramp
, SImode
, 8),
9885 expand_binop (SImode
, ior_optab
,
9886 expand_and (SImode
, fnaddr
, GEN_INT (0x3ff), NULL_RTX
),
9887 GEN_INT (trunc_int_for_mode (0x81c06000, SImode
)),
9888 NULL_RTX
, 1, OPTAB_DIRECT
));
9891 (adjust_address (m_tramp
, SImode
, 12),
9892 expand_binop (SImode
, ior_optab
,
9893 expand_and (SImode
, cxt
, GEN_INT (0x3ff), NULL_RTX
),
9894 GEN_INT (trunc_int_for_mode (0x8410a000, SImode
)),
9895 NULL_RTX
, 1, OPTAB_DIRECT
));
9897 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
9898 aligned on a 16 byte boundary so one flush clears it all. */
9899 emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp
, SImode
, 0))));
9900 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
9901 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
9902 && sparc_cpu
!= PROCESSOR_NIAGARA
9903 && sparc_cpu
!= PROCESSOR_NIAGARA2
9904 && sparc_cpu
!= PROCESSOR_NIAGARA3
9905 && sparc_cpu
!= PROCESSOR_NIAGARA4
9906 && sparc_cpu
!= PROCESSOR_NIAGARA7
9907 && sparc_cpu
!= PROCESSOR_M8
)
9908 emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp
, SImode
, 8))));
9910 /* Call __enable_execute_stack after writing onto the stack to make sure
9911 the stack address is accessible. */
9912 #ifdef HAVE_ENABLE_EXECUTE_STACK
9913 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
9914 LCT_NORMAL
, VOIDmode
, XEXP (m_tramp
, 0), Pmode
);
9919 /* The 64-bit version is simpler because it makes more sense to load the
9920 values as "immediate" data out of the trampoline. It's also easier since
9921 we can read the PC without clobbering a register. */
9924 sparc64_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
9926 /* SPARC 64-bit trampoline:
9935 emit_move_insn (adjust_address (m_tramp
, SImode
, 0),
9936 GEN_INT (trunc_int_for_mode (0x83414000, SImode
)));
9937 emit_move_insn (adjust_address (m_tramp
, SImode
, 4),
9938 GEN_INT (trunc_int_for_mode (0xca586018, SImode
)));
9939 emit_move_insn (adjust_address (m_tramp
, SImode
, 8),
9940 GEN_INT (trunc_int_for_mode (0x81c14000, SImode
)));
9941 emit_move_insn (adjust_address (m_tramp
, SImode
, 12),
9942 GEN_INT (trunc_int_for_mode (0xca586010, SImode
)));
9943 emit_move_insn (adjust_address (m_tramp
, DImode
, 16), cxt
);
9944 emit_move_insn (adjust_address (m_tramp
, DImode
, 24), fnaddr
);
9945 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 0))));
9947 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
9948 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
9949 && sparc_cpu
!= PROCESSOR_NIAGARA
9950 && sparc_cpu
!= PROCESSOR_NIAGARA2
9951 && sparc_cpu
!= PROCESSOR_NIAGARA3
9952 && sparc_cpu
!= PROCESSOR_NIAGARA4
9953 && sparc_cpu
!= PROCESSOR_NIAGARA7
9954 && sparc_cpu
!= PROCESSOR_M8
)
9955 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 8))));
9957 /* Call __enable_execute_stack after writing onto the stack to make sure
9958 the stack address is accessible. */
9959 #ifdef HAVE_ENABLE_EXECUTE_STACK
9960 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
9961 LCT_NORMAL
, VOIDmode
, XEXP (m_tramp
, 0), Pmode
);
9965 /* Worker for TARGET_TRAMPOLINE_INIT. */
9968 sparc_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
9970 rtx fnaddr
= force_reg (Pmode
, XEXP (DECL_RTL (fndecl
), 0));
9971 cxt
= force_reg (Pmode
, cxt
);
9973 sparc64_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
9975 sparc32_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
9978 /* Adjust the cost of a scheduling dependency. Return the new cost of
9979 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
9982 supersparc_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep_insn
,
9985 enum attr_type insn_type
;
9987 if (recog_memoized (insn
) < 0)
9990 insn_type
= get_attr_type (insn
);
9994 /* Data dependency; DEP_INSN writes a register that INSN reads some
9997 /* if a load, then the dependence must be on the memory address;
9998 add an extra "cycle". Note that the cost could be two cycles
9999 if the reg was written late in an instruction group; we ca not tell
10001 if (insn_type
== TYPE_LOAD
|| insn_type
== TYPE_FPLOAD
)
10004 /* Get the delay only if the address of the store is the dependence. */
10005 if (insn_type
== TYPE_STORE
|| insn_type
== TYPE_FPSTORE
)
10007 rtx pat
= PATTERN(insn
);
10008 rtx dep_pat
= PATTERN (dep_insn
);
10010 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
10011 return cost
; /* This should not happen! */
10013 /* The dependency between the two instructions was on the data that
10014 is being stored. Assume that this implies that the address of the
10015 store is not dependent. */
10016 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
10019 return cost
+ 3; /* An approximation. */
10022 /* A shift instruction cannot receive its data from an instruction
10023 in the same cycle; add a one cycle penalty. */
10024 if (insn_type
== TYPE_SHIFT
)
10025 return cost
+ 3; /* Split before cascade into shift. */
10029 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
10030 INSN writes some cycles later. */
10032 /* These are only significant for the fpu unit; writing a fp reg before
10033 the fpu has finished with it stalls the processor. */
10035 /* Reusing an integer register causes no problems. */
10036 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
10044 hypersparc_adjust_cost (rtx_insn
*insn
, int dtype
, rtx_insn
*dep_insn
,
10047 enum attr_type insn_type
, dep_type
;
10048 rtx pat
= PATTERN(insn
);
10049 rtx dep_pat
= PATTERN (dep_insn
);
10051 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
10054 insn_type
= get_attr_type (insn
);
10055 dep_type
= get_attr_type (dep_insn
);
10060 /* Data dependency; DEP_INSN writes a register that INSN reads some
10067 /* Get the delay iff the address of the store is the dependence. */
10068 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
10071 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
10078 /* If a load, then the dependence must be on the memory address. If
10079 the addresses aren't equal, then it might be a false dependency */
10080 if (dep_type
== TYPE_STORE
|| dep_type
== TYPE_FPSTORE
)
10082 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
10083 || GET_CODE (SET_DEST (dep_pat
)) != MEM
10084 || GET_CODE (SET_SRC (pat
)) != MEM
10085 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat
), 0),
10086 XEXP (SET_SRC (pat
), 0)))
10094 /* Compare to branch latency is 0. There is no benefit from
10095 separating compare and branch. */
10096 if (dep_type
== TYPE_COMPARE
)
10098 /* Floating point compare to branch latency is less than
10099 compare to conditional move. */
10100 if (dep_type
== TYPE_FPCMP
)
10109 /* Anti-dependencies only penalize the fpu unit. */
10110 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
10122 sparc_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep
, int cost
,
10127 case PROCESSOR_SUPERSPARC
:
10128 cost
= supersparc_adjust_cost (insn
, dep_type
, dep
, cost
);
10130 case PROCESSOR_HYPERSPARC
:
10131 case PROCESSOR_SPARCLITE86X
:
10132 cost
= hypersparc_adjust_cost (insn
, dep_type
, dep
, cost
);
10141 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
10142 int sched_verbose ATTRIBUTE_UNUSED
,
10143 int max_ready ATTRIBUTE_UNUSED
)
10147 sparc_use_sched_lookahead (void)
10149 if (sparc_cpu
== PROCESSOR_NIAGARA
10150 || sparc_cpu
== PROCESSOR_NIAGARA2
10151 || sparc_cpu
== PROCESSOR_NIAGARA3
)
10153 if (sparc_cpu
== PROCESSOR_NIAGARA4
10154 || sparc_cpu
== PROCESSOR_NIAGARA7
10155 || sparc_cpu
== PROCESSOR_M8
)
10157 if (sparc_cpu
== PROCESSOR_ULTRASPARC
10158 || sparc_cpu
== PROCESSOR_ULTRASPARC3
)
10160 if ((1 << sparc_cpu
) &
10161 ((1 << PROCESSOR_SUPERSPARC
) | (1 << PROCESSOR_HYPERSPARC
) |
10162 (1 << PROCESSOR_SPARCLITE86X
)))
10168 sparc_issue_rate (void)
10172 case PROCESSOR_NIAGARA
:
10173 case PROCESSOR_NIAGARA2
:
10174 case PROCESSOR_NIAGARA3
:
10177 case PROCESSOR_NIAGARA4
:
10178 case PROCESSOR_NIAGARA7
:
10180 /* Assume V9 processors are capable of at least dual-issue. */
10182 case PROCESSOR_SUPERSPARC
:
10184 case PROCESSOR_HYPERSPARC
:
10185 case PROCESSOR_SPARCLITE86X
:
10187 case PROCESSOR_ULTRASPARC
:
10188 case PROCESSOR_ULTRASPARC3
:
10195 set_extends (rtx_insn
*insn
)
10197 register rtx pat
= PATTERN (insn
);
10199 switch (GET_CODE (SET_SRC (pat
)))
10201 /* Load and some shift instructions zero extend. */
10204 /* sethi clears the high bits */
10206 /* LO_SUM is used with sethi. sethi cleared the high
10207 bits and the values used with lo_sum are positive */
10209 /* Store flag stores 0 or 1 */
10219 rtx op0
= XEXP (SET_SRC (pat
), 0);
10220 rtx op1
= XEXP (SET_SRC (pat
), 1);
10221 if (GET_CODE (op1
) == CONST_INT
)
10222 return INTVAL (op1
) >= 0;
10223 if (GET_CODE (op0
) != REG
)
10225 if (sparc_check_64 (op0
, insn
) == 1)
10227 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
10232 rtx op0
= XEXP (SET_SRC (pat
), 0);
10233 rtx op1
= XEXP (SET_SRC (pat
), 1);
10234 if (GET_CODE (op0
) != REG
|| sparc_check_64 (op0
, insn
) <= 0)
10236 if (GET_CODE (op1
) == CONST_INT
)
10237 return INTVAL (op1
) >= 0;
10238 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
10241 return GET_MODE (SET_SRC (pat
)) == SImode
;
10242 /* Positive integers leave the high bits zero. */
10244 return !(INTVAL (SET_SRC (pat
)) & 0x80000000);
10247 return - (GET_MODE (SET_SRC (pat
)) == SImode
);
10249 return sparc_check_64 (SET_SRC (pat
), insn
);
10255 /* We _ought_ to have only one kind per function, but... */
10256 static GTY(()) rtx sparc_addr_diff_list
;
10257 static GTY(()) rtx sparc_addr_list
;
10260 sparc_defer_case_vector (rtx lab
, rtx vec
, int diff
)
10262 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
10264 sparc_addr_diff_list
10265 = gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_diff_list
);
10267 sparc_addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_list
);
10271 sparc_output_addr_vec (rtx vec
)
10273 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
10274 int idx
, vlen
= XVECLEN (body
, 0);
10276 #ifdef ASM_OUTPUT_ADDR_VEC_START
10277 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
10280 #ifdef ASM_OUTPUT_CASE_LABEL
10281 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
10284 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
10287 for (idx
= 0; idx
< vlen
; idx
++)
10289 ASM_OUTPUT_ADDR_VEC_ELT
10290 (asm_out_file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
10293 #ifdef ASM_OUTPUT_ADDR_VEC_END
10294 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
10299 sparc_output_addr_diff_vec (rtx vec
)
10301 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
10302 rtx base
= XEXP (XEXP (body
, 0), 0);
10303 int idx
, vlen
= XVECLEN (body
, 1);
10305 #ifdef ASM_OUTPUT_ADDR_VEC_START
10306 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
10309 #ifdef ASM_OUTPUT_CASE_LABEL
10310 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
10313 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
10316 for (idx
= 0; idx
< vlen
; idx
++)
10318 ASM_OUTPUT_ADDR_DIFF_ELT
10321 CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 1, idx
), 0)),
10322 CODE_LABEL_NUMBER (base
));
10325 #ifdef ASM_OUTPUT_ADDR_VEC_END
10326 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
10331 sparc_output_deferred_case_vectors (void)
10336 if (sparc_addr_list
== NULL_RTX
10337 && sparc_addr_diff_list
== NULL_RTX
)
10340 /* Align to cache line in the function's code section. */
10341 switch_to_section (current_function_section ());
10343 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
10345 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
10347 for (t
= sparc_addr_list
; t
; t
= XEXP (t
, 1))
10348 sparc_output_addr_vec (XEXP (t
, 0));
10349 for (t
= sparc_addr_diff_list
; t
; t
= XEXP (t
, 1))
10350 sparc_output_addr_diff_vec (XEXP (t
, 0));
10352 sparc_addr_list
= sparc_addr_diff_list
= NULL_RTX
;
10355 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
10356 unknown. Return 1 if the high bits are zero, -1 if the register is
10359 sparc_check_64 (rtx x
, rtx_insn
*insn
)
10361 /* If a register is set only once it is safe to ignore insns this
10362 code does not know how to handle. The loop will either recognize
10363 the single set and return the correct value or fail to recognize
10364 it and return 0. */
10368 gcc_assert (GET_CODE (x
) == REG
);
10370 if (GET_MODE (x
) == DImode
)
10371 y
= gen_rtx_REG (SImode
, REGNO (x
) + WORDS_BIG_ENDIAN
);
10373 if (flag_expensive_optimizations
10374 && df
&& DF_REG_DEF_COUNT (REGNO (y
)) == 1)
10380 insn
= get_last_insn_anywhere ();
10385 while ((insn
= PREV_INSN (insn
)))
10387 switch (GET_CODE (insn
))
10400 rtx pat
= PATTERN (insn
);
10401 if (GET_CODE (pat
) != SET
)
10403 if (rtx_equal_p (x
, SET_DEST (pat
)))
10404 return set_extends (insn
);
10405 if (y
&& rtx_equal_p (y
, SET_DEST (pat
)))
10406 return set_extends (insn
);
10407 if (reg_overlap_mentioned_p (SET_DEST (pat
), y
))
10415 /* Output a wide shift instruction in V8+ mode. INSN is the instruction,
10416 OPERANDS are its operands and OPCODE is the mnemonic to be used. */
10419 output_v8plus_shift (rtx_insn
*insn
, rtx
*operands
, const char *opcode
)
10421 static char asm_code
[60];
10423 /* The scratch register is only required when the destination
10424 register is not a 64-bit global or out register. */
10425 if (which_alternative
!= 2)
10426 operands
[3] = operands
[0];
10428 /* We can only shift by constants <= 63. */
10429 if (GET_CODE (operands
[2]) == CONST_INT
)
10430 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0x3f);
10432 if (GET_CODE (operands
[1]) == CONST_INT
)
10434 output_asm_insn ("mov\t%1, %3", operands
);
10438 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
10439 if (sparc_check_64 (operands
[1], insn
) <= 0)
10440 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
10441 output_asm_insn ("or\t%L1, %3, %3", operands
);
10444 strcpy (asm_code
, opcode
);
10446 if (which_alternative
!= 2)
10447 return strcat (asm_code
, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
10450 strcat (asm_code
, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
10453 /* Output rtl to increment the profiler label LABELNO
10454 for profiling a function entry. */
10457 sparc_profile_hook (int labelno
)
10462 fun
= gen_rtx_SYMBOL_REF (Pmode
, MCOUNT_FUNCTION
);
10463 if (NO_PROFILE_COUNTERS
)
10465 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
);
10469 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
10470 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
10471 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, lab
, Pmode
);
10475 #ifdef TARGET_SOLARIS
10476 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
10479 sparc_solaris_elf_asm_named_section (const char *name
, unsigned int flags
,
10480 tree decl ATTRIBUTE_UNUSED
)
10482 if (HAVE_COMDAT_GROUP
&& flags
& SECTION_LINKONCE
)
10484 solaris_elf_asm_comdat_section (name
, flags
, decl
);
10488 fprintf (asm_out_file
, "\t.section\t\"%s\"", name
);
10490 if (!(flags
& SECTION_DEBUG
))
10491 fputs (",#alloc", asm_out_file
);
10492 if (flags
& SECTION_WRITE
)
10493 fputs (",#write", asm_out_file
);
10494 if (flags
& SECTION_TLS
)
10495 fputs (",#tls", asm_out_file
);
10496 if (flags
& SECTION_CODE
)
10497 fputs (",#execinstr", asm_out_file
);
10499 if (flags
& SECTION_NOTYPE
)
10501 else if (flags
& SECTION_BSS
)
10502 fputs (",#nobits", asm_out_file
);
10504 fputs (",#progbits", asm_out_file
);
10506 fputc ('\n', asm_out_file
);
10508 #endif /* TARGET_SOLARIS */
10510 /* We do not allow indirect calls to be optimized into sibling calls.
10512 We cannot use sibling calls when delayed branches are disabled
10513 because they will likely require the call delay slot to be filled.
10515 Also, on SPARC 32-bit we cannot emit a sibling call when the
10516 current function returns a structure. This is because the "unimp
10517 after call" convention would cause the callee to return to the
10518 wrong place. The generic code already disallows cases where the
10519 function being called returns a structure.
10521 It may seem strange how this last case could occur. Usually there
10522 is code after the call which jumps to epilogue code which dumps the
10523 return value into the struct return area. That ought to invalidate
10524 the sibling call right? Well, in the C++ case we can end up passing
10525 the pointer to the struct return area to a constructor (which returns
10526 void) and then nothing else happens. Such a sibling call would look
10527 valid without the added check here.
10529 VxWorks PIC PLT entries require the global pointer to be initialized
10530 on entry. We therefore can't emit sibling calls to them. */
10532 sparc_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
10535 && flag_delayed_branch
10536 && (TARGET_ARCH64
|| ! cfun
->returns_struct
)
10537 && !(TARGET_VXWORKS_RTP
10539 && !targetm
.binds_local_p (decl
)));
10542 /* libfunc renaming. */
10545 sparc_init_libfuncs (void)
10549 /* Use the subroutines that Sun's library provides for integer
10550 multiply and divide. The `*' prevents an underscore from
10551 being prepended by the compiler. .umul is a little faster
10553 set_optab_libfunc (smul_optab
, SImode
, "*.umul");
10554 set_optab_libfunc (sdiv_optab
, SImode
, "*.div");
10555 set_optab_libfunc (udiv_optab
, SImode
, "*.udiv");
10556 set_optab_libfunc (smod_optab
, SImode
, "*.rem");
10557 set_optab_libfunc (umod_optab
, SImode
, "*.urem");
10559 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
10560 set_optab_libfunc (add_optab
, TFmode
, "_Q_add");
10561 set_optab_libfunc (sub_optab
, TFmode
, "_Q_sub");
10562 set_optab_libfunc (neg_optab
, TFmode
, "_Q_neg");
10563 set_optab_libfunc (smul_optab
, TFmode
, "_Q_mul");
10564 set_optab_libfunc (sdiv_optab
, TFmode
, "_Q_div");
10566 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
10567 is because with soft-float, the SFmode and DFmode sqrt
10568 instructions will be absent, and the compiler will notice and
10569 try to use the TFmode sqrt instruction for calls to the
10570 builtin function sqrt, but this fails. */
10572 set_optab_libfunc (sqrt_optab
, TFmode
, "_Q_sqrt");
10574 set_optab_libfunc (eq_optab
, TFmode
, "_Q_feq");
10575 set_optab_libfunc (ne_optab
, TFmode
, "_Q_fne");
10576 set_optab_libfunc (gt_optab
, TFmode
, "_Q_fgt");
10577 set_optab_libfunc (ge_optab
, TFmode
, "_Q_fge");
10578 set_optab_libfunc (lt_optab
, TFmode
, "_Q_flt");
10579 set_optab_libfunc (le_optab
, TFmode
, "_Q_fle");
10581 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_Q_stoq");
10582 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_Q_dtoq");
10583 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_Q_qtos");
10584 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_Q_qtod");
10586 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_Q_qtoi");
10587 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_Q_qtou");
10588 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_Q_itoq");
10589 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_Q_utoq");
10591 if (DITF_CONVERSION_LIBFUNCS
)
10593 set_conv_libfunc (sfix_optab
, DImode
, TFmode
, "_Q_qtoll");
10594 set_conv_libfunc (ufix_optab
, DImode
, TFmode
, "_Q_qtoull");
10595 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
, "_Q_lltoq");
10596 set_conv_libfunc (ufloat_optab
, TFmode
, DImode
, "_Q_ulltoq");
10599 if (SUN_CONVERSION_LIBFUNCS
)
10601 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
10602 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
10603 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
10604 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
10609 /* In the SPARC 64bit ABI, SImode multiply and divide functions
10610 do not exist in the library. Make sure the compiler does not
10611 emit calls to them by accident. (It should always use the
10612 hardware instructions.) */
10613 set_optab_libfunc (smul_optab
, SImode
, 0);
10614 set_optab_libfunc (sdiv_optab
, SImode
, 0);
10615 set_optab_libfunc (udiv_optab
, SImode
, 0);
10616 set_optab_libfunc (smod_optab
, SImode
, 0);
10617 set_optab_libfunc (umod_optab
, SImode
, 0);
10619 if (SUN_INTEGER_MULTIPLY_64
)
10621 set_optab_libfunc (smul_optab
, DImode
, "__mul64");
10622 set_optab_libfunc (sdiv_optab
, DImode
, "__div64");
10623 set_optab_libfunc (udiv_optab
, DImode
, "__udiv64");
10624 set_optab_libfunc (smod_optab
, DImode
, "__rem64");
10625 set_optab_libfunc (umod_optab
, DImode
, "__urem64");
10628 if (SUN_CONVERSION_LIBFUNCS
)
10630 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftol");
10631 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoul");
10632 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtol");
10633 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoul");
10638 /* SPARC builtins. */
10639 enum sparc_builtins
10641 /* FPU builtins. */
10642 SPARC_BUILTIN_LDFSR
,
10643 SPARC_BUILTIN_STFSR
,
10645 /* VIS 1.0 builtins. */
10646 SPARC_BUILTIN_FPACK16
,
10647 SPARC_BUILTIN_FPACK32
,
10648 SPARC_BUILTIN_FPACKFIX
,
10649 SPARC_BUILTIN_FEXPAND
,
10650 SPARC_BUILTIN_FPMERGE
,
10651 SPARC_BUILTIN_FMUL8X16
,
10652 SPARC_BUILTIN_FMUL8X16AU
,
10653 SPARC_BUILTIN_FMUL8X16AL
,
10654 SPARC_BUILTIN_FMUL8SUX16
,
10655 SPARC_BUILTIN_FMUL8ULX16
,
10656 SPARC_BUILTIN_FMULD8SUX16
,
10657 SPARC_BUILTIN_FMULD8ULX16
,
10658 SPARC_BUILTIN_FALIGNDATAV4HI
,
10659 SPARC_BUILTIN_FALIGNDATAV8QI
,
10660 SPARC_BUILTIN_FALIGNDATAV2SI
,
10661 SPARC_BUILTIN_FALIGNDATADI
,
10662 SPARC_BUILTIN_WRGSR
,
10663 SPARC_BUILTIN_RDGSR
,
10664 SPARC_BUILTIN_ALIGNADDR
,
10665 SPARC_BUILTIN_ALIGNADDRL
,
10666 SPARC_BUILTIN_PDIST
,
10667 SPARC_BUILTIN_EDGE8
,
10668 SPARC_BUILTIN_EDGE8L
,
10669 SPARC_BUILTIN_EDGE16
,
10670 SPARC_BUILTIN_EDGE16L
,
10671 SPARC_BUILTIN_EDGE32
,
10672 SPARC_BUILTIN_EDGE32L
,
10673 SPARC_BUILTIN_FCMPLE16
,
10674 SPARC_BUILTIN_FCMPLE32
,
10675 SPARC_BUILTIN_FCMPNE16
,
10676 SPARC_BUILTIN_FCMPNE32
,
10677 SPARC_BUILTIN_FCMPGT16
,
10678 SPARC_BUILTIN_FCMPGT32
,
10679 SPARC_BUILTIN_FCMPEQ16
,
10680 SPARC_BUILTIN_FCMPEQ32
,
10681 SPARC_BUILTIN_FPADD16
,
10682 SPARC_BUILTIN_FPADD16S
,
10683 SPARC_BUILTIN_FPADD32
,
10684 SPARC_BUILTIN_FPADD32S
,
10685 SPARC_BUILTIN_FPSUB16
,
10686 SPARC_BUILTIN_FPSUB16S
,
10687 SPARC_BUILTIN_FPSUB32
,
10688 SPARC_BUILTIN_FPSUB32S
,
10689 SPARC_BUILTIN_ARRAY8
,
10690 SPARC_BUILTIN_ARRAY16
,
10691 SPARC_BUILTIN_ARRAY32
,
10693 /* VIS 2.0 builtins. */
10694 SPARC_BUILTIN_EDGE8N
,
10695 SPARC_BUILTIN_EDGE8LN
,
10696 SPARC_BUILTIN_EDGE16N
,
10697 SPARC_BUILTIN_EDGE16LN
,
10698 SPARC_BUILTIN_EDGE32N
,
10699 SPARC_BUILTIN_EDGE32LN
,
10700 SPARC_BUILTIN_BMASK
,
10701 SPARC_BUILTIN_BSHUFFLEV4HI
,
10702 SPARC_BUILTIN_BSHUFFLEV8QI
,
10703 SPARC_BUILTIN_BSHUFFLEV2SI
,
10704 SPARC_BUILTIN_BSHUFFLEDI
,
10706 /* VIS 3.0 builtins. */
10707 SPARC_BUILTIN_CMASK8
,
10708 SPARC_BUILTIN_CMASK16
,
10709 SPARC_BUILTIN_CMASK32
,
10710 SPARC_BUILTIN_FCHKSM16
,
10711 SPARC_BUILTIN_FSLL16
,
10712 SPARC_BUILTIN_FSLAS16
,
10713 SPARC_BUILTIN_FSRL16
,
10714 SPARC_BUILTIN_FSRA16
,
10715 SPARC_BUILTIN_FSLL32
,
10716 SPARC_BUILTIN_FSLAS32
,
10717 SPARC_BUILTIN_FSRL32
,
10718 SPARC_BUILTIN_FSRA32
,
10719 SPARC_BUILTIN_PDISTN
,
10720 SPARC_BUILTIN_FMEAN16
,
10721 SPARC_BUILTIN_FPADD64
,
10722 SPARC_BUILTIN_FPSUB64
,
10723 SPARC_BUILTIN_FPADDS16
,
10724 SPARC_BUILTIN_FPADDS16S
,
10725 SPARC_BUILTIN_FPSUBS16
,
10726 SPARC_BUILTIN_FPSUBS16S
,
10727 SPARC_BUILTIN_FPADDS32
,
10728 SPARC_BUILTIN_FPADDS32S
,
10729 SPARC_BUILTIN_FPSUBS32
,
10730 SPARC_BUILTIN_FPSUBS32S
,
10731 SPARC_BUILTIN_FUCMPLE8
,
10732 SPARC_BUILTIN_FUCMPNE8
,
10733 SPARC_BUILTIN_FUCMPGT8
,
10734 SPARC_BUILTIN_FUCMPEQ8
,
10735 SPARC_BUILTIN_FHADDS
,
10736 SPARC_BUILTIN_FHADDD
,
10737 SPARC_BUILTIN_FHSUBS
,
10738 SPARC_BUILTIN_FHSUBD
,
10739 SPARC_BUILTIN_FNHADDS
,
10740 SPARC_BUILTIN_FNHADDD
,
10741 SPARC_BUILTIN_UMULXHI
,
10742 SPARC_BUILTIN_XMULX
,
10743 SPARC_BUILTIN_XMULXHI
,
10745 /* VIS 4.0 builtins. */
10746 SPARC_BUILTIN_FPADD8
,
10747 SPARC_BUILTIN_FPADDS8
,
10748 SPARC_BUILTIN_FPADDUS8
,
10749 SPARC_BUILTIN_FPADDUS16
,
10750 SPARC_BUILTIN_FPCMPLE8
,
10751 SPARC_BUILTIN_FPCMPGT8
,
10752 SPARC_BUILTIN_FPCMPULE16
,
10753 SPARC_BUILTIN_FPCMPUGT16
,
10754 SPARC_BUILTIN_FPCMPULE32
,
10755 SPARC_BUILTIN_FPCMPUGT32
,
10756 SPARC_BUILTIN_FPMAX8
,
10757 SPARC_BUILTIN_FPMAX16
,
10758 SPARC_BUILTIN_FPMAX32
,
10759 SPARC_BUILTIN_FPMAXU8
,
10760 SPARC_BUILTIN_FPMAXU16
,
10761 SPARC_BUILTIN_FPMAXU32
,
10762 SPARC_BUILTIN_FPMIN8
,
10763 SPARC_BUILTIN_FPMIN16
,
10764 SPARC_BUILTIN_FPMIN32
,
10765 SPARC_BUILTIN_FPMINU8
,
10766 SPARC_BUILTIN_FPMINU16
,
10767 SPARC_BUILTIN_FPMINU32
,
10768 SPARC_BUILTIN_FPSUB8
,
10769 SPARC_BUILTIN_FPSUBS8
,
10770 SPARC_BUILTIN_FPSUBUS8
,
10771 SPARC_BUILTIN_FPSUBUS16
,
10773 /* VIS 4.0B builtins. */
10775 /* Note that all the DICTUNPACK* entries should be kept
10777 SPARC_BUILTIN_FIRST_DICTUNPACK
,
10778 SPARC_BUILTIN_DICTUNPACK8
= SPARC_BUILTIN_FIRST_DICTUNPACK
,
10779 SPARC_BUILTIN_DICTUNPACK16
,
10780 SPARC_BUILTIN_DICTUNPACK32
,
10781 SPARC_BUILTIN_LAST_DICTUNPACK
= SPARC_BUILTIN_DICTUNPACK32
,
10783 /* Note that all the FPCMP*SHL entries should be kept
10785 SPARC_BUILTIN_FIRST_FPCMPSHL
,
10786 SPARC_BUILTIN_FPCMPLE8SHL
= SPARC_BUILTIN_FIRST_FPCMPSHL
,
10787 SPARC_BUILTIN_FPCMPGT8SHL
,
10788 SPARC_BUILTIN_FPCMPEQ8SHL
,
10789 SPARC_BUILTIN_FPCMPNE8SHL
,
10790 SPARC_BUILTIN_FPCMPLE16SHL
,
10791 SPARC_BUILTIN_FPCMPGT16SHL
,
10792 SPARC_BUILTIN_FPCMPEQ16SHL
,
10793 SPARC_BUILTIN_FPCMPNE16SHL
,
10794 SPARC_BUILTIN_FPCMPLE32SHL
,
10795 SPARC_BUILTIN_FPCMPGT32SHL
,
10796 SPARC_BUILTIN_FPCMPEQ32SHL
,
10797 SPARC_BUILTIN_FPCMPNE32SHL
,
10798 SPARC_BUILTIN_FPCMPULE8SHL
,
10799 SPARC_BUILTIN_FPCMPUGT8SHL
,
10800 SPARC_BUILTIN_FPCMPULE16SHL
,
10801 SPARC_BUILTIN_FPCMPUGT16SHL
,
10802 SPARC_BUILTIN_FPCMPULE32SHL
,
10803 SPARC_BUILTIN_FPCMPUGT32SHL
,
10804 SPARC_BUILTIN_FPCMPDE8SHL
,
10805 SPARC_BUILTIN_FPCMPDE16SHL
,
10806 SPARC_BUILTIN_FPCMPDE32SHL
,
10807 SPARC_BUILTIN_FPCMPUR8SHL
,
10808 SPARC_BUILTIN_FPCMPUR16SHL
,
10809 SPARC_BUILTIN_FPCMPUR32SHL
,
10810 SPARC_BUILTIN_LAST_FPCMPSHL
= SPARC_BUILTIN_FPCMPUR32SHL
,
10815 static GTY (()) tree sparc_builtins
[(int) SPARC_BUILTIN_MAX
];
10816 static enum insn_code sparc_builtins_icode
[(int) SPARC_BUILTIN_MAX
];
10818 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
10819 The instruction should require a constant operand of some sort. The
10820 function prints an error if OPVAL is not valid. */
10823 check_constant_argument (enum insn_code icode
, int opnum
, rtx opval
)
10825 if (GET_CODE (opval
) != CONST_INT
)
10827 error ("%qs expects a constant argument", insn_data
[icode
].name
);
10831 if (!(*insn_data
[icode
].operand
[opnum
].predicate
) (opval
, VOIDmode
))
10833 error ("constant argument out of range for %qs", insn_data
[icode
].name
);
10839 /* Add a SPARC builtin function with NAME, ICODE, CODE and TYPE. Return the
10840 function decl or NULL_TREE if the builtin was not added. */
10843 def_builtin (const char *name
, enum insn_code icode
, enum sparc_builtins code
,
10847 = add_builtin_function (name
, type
, code
, BUILT_IN_MD
, NULL
, NULL_TREE
);
10851 sparc_builtins
[code
] = t
;
10852 sparc_builtins_icode
[code
] = icode
;
10858 /* Likewise, but also marks the function as "const". */
10861 def_builtin_const (const char *name
, enum insn_code icode
,
10862 enum sparc_builtins code
, tree type
)
10864 tree t
= def_builtin (name
, icode
, code
, type
);
10867 TREE_READONLY (t
) = 1;
10872 /* Implement the TARGET_INIT_BUILTINS target hook.
10873 Create builtin functions for special SPARC instructions. */
10876 sparc_init_builtins (void)
10879 sparc_fpu_init_builtins ();
10882 sparc_vis_init_builtins ();
10885 /* Create builtin functions for FPU instructions. */
10888 sparc_fpu_init_builtins (void)
10891 = build_function_type_list (void_type_node
,
10892 build_pointer_type (unsigned_type_node
), 0);
10893 def_builtin ("__builtin_load_fsr", CODE_FOR_ldfsr
,
10894 SPARC_BUILTIN_LDFSR
, ftype
);
10895 def_builtin ("__builtin_store_fsr", CODE_FOR_stfsr
,
10896 SPARC_BUILTIN_STFSR
, ftype
);
10899 /* Create builtin functions for VIS instructions. */
10902 sparc_vis_init_builtins (void)
10904 tree v4qi
= build_vector_type (unsigned_intQI_type_node
, 4);
10905 tree v8qi
= build_vector_type (unsigned_intQI_type_node
, 8);
10906 tree v4hi
= build_vector_type (intHI_type_node
, 4);
10907 tree v2hi
= build_vector_type (intHI_type_node
, 2);
10908 tree v2si
= build_vector_type (intSI_type_node
, 2);
10909 tree v1si
= build_vector_type (intSI_type_node
, 1);
10911 tree v4qi_ftype_v4hi
= build_function_type_list (v4qi
, v4hi
, 0);
10912 tree v8qi_ftype_v2si_v8qi
= build_function_type_list (v8qi
, v2si
, v8qi
, 0);
10913 tree v2hi_ftype_v2si
= build_function_type_list (v2hi
, v2si
, 0);
10914 tree v4hi_ftype_v4qi
= build_function_type_list (v4hi
, v4qi
, 0);
10915 tree v8qi_ftype_v4qi_v4qi
= build_function_type_list (v8qi
, v4qi
, v4qi
, 0);
10916 tree v4hi_ftype_v4qi_v4hi
= build_function_type_list (v4hi
, v4qi
, v4hi
, 0);
10917 tree v4hi_ftype_v4qi_v2hi
= build_function_type_list (v4hi
, v4qi
, v2hi
, 0);
10918 tree v2si_ftype_v4qi_v2hi
= build_function_type_list (v2si
, v4qi
, v2hi
, 0);
10919 tree v4hi_ftype_v8qi_v4hi
= build_function_type_list (v4hi
, v8qi
, v4hi
, 0);
10920 tree v4hi_ftype_v4hi_v4hi
= build_function_type_list (v4hi
, v4hi
, v4hi
, 0);
10921 tree v2si_ftype_v2si_v2si
= build_function_type_list (v2si
, v2si
, v2si
, 0);
10922 tree v8qi_ftype_v8qi_v8qi
= build_function_type_list (v8qi
, v8qi
, v8qi
, 0);
10923 tree v2hi_ftype_v2hi_v2hi
= build_function_type_list (v2hi
, v2hi
, v2hi
, 0);
10924 tree v1si_ftype_v1si_v1si
= build_function_type_list (v1si
, v1si
, v1si
, 0);
10925 tree di_ftype_v8qi_v8qi_di
= build_function_type_list (intDI_type_node
,
10927 intDI_type_node
, 0);
10928 tree di_ftype_v8qi_v8qi
= build_function_type_list (intDI_type_node
,
10930 tree si_ftype_v8qi_v8qi
= build_function_type_list (intSI_type_node
,
10932 tree v8qi_ftype_df_si
= build_function_type_list (v8qi
, double_type_node
,
10933 intSI_type_node
, 0);
10934 tree v4hi_ftype_df_si
= build_function_type_list (v4hi
, double_type_node
,
10935 intSI_type_node
, 0);
10936 tree v2si_ftype_df_si
= build_function_type_list (v2si
, double_type_node
,
10937 intDI_type_node
, 0);
10938 tree di_ftype_di_di
= build_function_type_list (intDI_type_node
,
10940 intDI_type_node
, 0);
10941 tree si_ftype_si_si
= build_function_type_list (intSI_type_node
,
10943 intSI_type_node
, 0);
10944 tree ptr_ftype_ptr_si
= build_function_type_list (ptr_type_node
,
10946 intSI_type_node
, 0);
10947 tree ptr_ftype_ptr_di
= build_function_type_list (ptr_type_node
,
10949 intDI_type_node
, 0);
10950 tree si_ftype_ptr_ptr
= build_function_type_list (intSI_type_node
,
10953 tree di_ftype_ptr_ptr
= build_function_type_list (intDI_type_node
,
10956 tree si_ftype_v4hi_v4hi
= build_function_type_list (intSI_type_node
,
10958 tree si_ftype_v2si_v2si
= build_function_type_list (intSI_type_node
,
10960 tree di_ftype_v4hi_v4hi
= build_function_type_list (intDI_type_node
,
10962 tree di_ftype_v2si_v2si
= build_function_type_list (intDI_type_node
,
10964 tree void_ftype_di
= build_function_type_list (void_type_node
,
10965 intDI_type_node
, 0);
10966 tree di_ftype_void
= build_function_type_list (intDI_type_node
,
10967 void_type_node
, 0);
10968 tree void_ftype_si
= build_function_type_list (void_type_node
,
10969 intSI_type_node
, 0);
10970 tree sf_ftype_sf_sf
= build_function_type_list (float_type_node
,
10972 float_type_node
, 0);
10973 tree df_ftype_df_df
= build_function_type_list (double_type_node
,
10975 double_type_node
, 0);
10977 /* Packing and expanding vectors. */
10978 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis
,
10979 SPARC_BUILTIN_FPACK16
, v4qi_ftype_v4hi
);
10980 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis
,
10981 SPARC_BUILTIN_FPACK32
, v8qi_ftype_v2si_v8qi
);
10982 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis
,
10983 SPARC_BUILTIN_FPACKFIX
, v2hi_ftype_v2si
);
10984 def_builtin_const ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis
,
10985 SPARC_BUILTIN_FEXPAND
, v4hi_ftype_v4qi
);
10986 def_builtin_const ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis
,
10987 SPARC_BUILTIN_FPMERGE
, v8qi_ftype_v4qi_v4qi
);
10989 /* Multiplications. */
10990 def_builtin_const ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis
,
10991 SPARC_BUILTIN_FMUL8X16
, v4hi_ftype_v4qi_v4hi
);
10992 def_builtin_const ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis
,
10993 SPARC_BUILTIN_FMUL8X16AU
, v4hi_ftype_v4qi_v2hi
);
10994 def_builtin_const ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis
,
10995 SPARC_BUILTIN_FMUL8X16AL
, v4hi_ftype_v4qi_v2hi
);
10996 def_builtin_const ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis
,
10997 SPARC_BUILTIN_FMUL8SUX16
, v4hi_ftype_v8qi_v4hi
);
10998 def_builtin_const ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis
,
10999 SPARC_BUILTIN_FMUL8ULX16
, v4hi_ftype_v8qi_v4hi
);
11000 def_builtin_const ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis
,
11001 SPARC_BUILTIN_FMULD8SUX16
, v2si_ftype_v4qi_v2hi
);
11002 def_builtin_const ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis
,
11003 SPARC_BUILTIN_FMULD8ULX16
, v2si_ftype_v4qi_v2hi
);
11005 /* Data aligning. */
11006 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis
,
11007 SPARC_BUILTIN_FALIGNDATAV4HI
, v4hi_ftype_v4hi_v4hi
);
11008 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis
,
11009 SPARC_BUILTIN_FALIGNDATAV8QI
, v8qi_ftype_v8qi_v8qi
);
11010 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis
,
11011 SPARC_BUILTIN_FALIGNDATAV2SI
, v2si_ftype_v2si_v2si
);
11012 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatav1di_vis
,
11013 SPARC_BUILTIN_FALIGNDATADI
, di_ftype_di_di
);
11015 def_builtin ("__builtin_vis_write_gsr", CODE_FOR_wrgsr_vis
,
11016 SPARC_BUILTIN_WRGSR
, void_ftype_di
);
11017 def_builtin ("__builtin_vis_read_gsr", CODE_FOR_rdgsr_vis
,
11018 SPARC_BUILTIN_RDGSR
, di_ftype_void
);
11022 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis
,
11023 SPARC_BUILTIN_ALIGNADDR
, ptr_ftype_ptr_di
);
11024 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrldi_vis
,
11025 SPARC_BUILTIN_ALIGNADDRL
, ptr_ftype_ptr_di
);
11029 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis
,
11030 SPARC_BUILTIN_ALIGNADDR
, ptr_ftype_ptr_si
);
11031 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrlsi_vis
,
11032 SPARC_BUILTIN_ALIGNADDRL
, ptr_ftype_ptr_si
);
11035 /* Pixel distance. */
11036 def_builtin_const ("__builtin_vis_pdist", CODE_FOR_pdist_vis
,
11037 SPARC_BUILTIN_PDIST
, di_ftype_v8qi_v8qi_di
);
11039 /* Edge handling. */
11042 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8di_vis
,
11043 SPARC_BUILTIN_EDGE8
, di_ftype_ptr_ptr
);
11044 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8ldi_vis
,
11045 SPARC_BUILTIN_EDGE8L
, di_ftype_ptr_ptr
);
11046 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16di_vis
,
11047 SPARC_BUILTIN_EDGE16
, di_ftype_ptr_ptr
);
11048 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16ldi_vis
,
11049 SPARC_BUILTIN_EDGE16L
, di_ftype_ptr_ptr
);
11050 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32di_vis
,
11051 SPARC_BUILTIN_EDGE32
, di_ftype_ptr_ptr
);
11052 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32ldi_vis
,
11053 SPARC_BUILTIN_EDGE32L
, di_ftype_ptr_ptr
);
11057 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8si_vis
,
11058 SPARC_BUILTIN_EDGE8
, si_ftype_ptr_ptr
);
11059 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8lsi_vis
,
11060 SPARC_BUILTIN_EDGE8L
, si_ftype_ptr_ptr
);
11061 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16si_vis
,
11062 SPARC_BUILTIN_EDGE16
, si_ftype_ptr_ptr
);
11063 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16lsi_vis
,
11064 SPARC_BUILTIN_EDGE16L
, si_ftype_ptr_ptr
);
11065 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32si_vis
,
11066 SPARC_BUILTIN_EDGE32
, si_ftype_ptr_ptr
);
11067 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32lsi_vis
,
11068 SPARC_BUILTIN_EDGE32L
, si_ftype_ptr_ptr
);
11071 /* Pixel compare. */
11074 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16di_vis
,
11075 SPARC_BUILTIN_FCMPLE16
, di_ftype_v4hi_v4hi
);
11076 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32di_vis
,
11077 SPARC_BUILTIN_FCMPLE32
, di_ftype_v2si_v2si
);
11078 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16di_vis
,
11079 SPARC_BUILTIN_FCMPNE16
, di_ftype_v4hi_v4hi
);
11080 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32di_vis
,
11081 SPARC_BUILTIN_FCMPNE32
, di_ftype_v2si_v2si
);
11082 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16di_vis
,
11083 SPARC_BUILTIN_FCMPGT16
, di_ftype_v4hi_v4hi
);
11084 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32di_vis
,
11085 SPARC_BUILTIN_FCMPGT32
, di_ftype_v2si_v2si
);
11086 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16di_vis
,
11087 SPARC_BUILTIN_FCMPEQ16
, di_ftype_v4hi_v4hi
);
11088 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32di_vis
,
11089 SPARC_BUILTIN_FCMPEQ32
, di_ftype_v2si_v2si
);
11093 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16si_vis
,
11094 SPARC_BUILTIN_FCMPLE16
, si_ftype_v4hi_v4hi
);
11095 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32si_vis
,
11096 SPARC_BUILTIN_FCMPLE32
, si_ftype_v2si_v2si
);
11097 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16si_vis
,
11098 SPARC_BUILTIN_FCMPNE16
, si_ftype_v4hi_v4hi
);
11099 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32si_vis
,
11100 SPARC_BUILTIN_FCMPNE32
, si_ftype_v2si_v2si
);
11101 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16si_vis
,
11102 SPARC_BUILTIN_FCMPGT16
, si_ftype_v4hi_v4hi
);
11103 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32si_vis
,
11104 SPARC_BUILTIN_FCMPGT32
, si_ftype_v2si_v2si
);
11105 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16si_vis
,
11106 SPARC_BUILTIN_FCMPEQ16
, si_ftype_v4hi_v4hi
);
11107 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32si_vis
,
11108 SPARC_BUILTIN_FCMPEQ32
, si_ftype_v2si_v2si
);
11111 /* Addition and subtraction. */
11112 def_builtin_const ("__builtin_vis_fpadd16", CODE_FOR_addv4hi3
,
11113 SPARC_BUILTIN_FPADD16
, v4hi_ftype_v4hi_v4hi
);
11114 def_builtin_const ("__builtin_vis_fpadd16s", CODE_FOR_addv2hi3
,
11115 SPARC_BUILTIN_FPADD16S
, v2hi_ftype_v2hi_v2hi
);
11116 def_builtin_const ("__builtin_vis_fpadd32", CODE_FOR_addv2si3
,
11117 SPARC_BUILTIN_FPADD32
, v2si_ftype_v2si_v2si
);
11118 def_builtin_const ("__builtin_vis_fpadd32s", CODE_FOR_addv1si3
,
11119 SPARC_BUILTIN_FPADD32S
, v1si_ftype_v1si_v1si
);
11120 def_builtin_const ("__builtin_vis_fpsub16", CODE_FOR_subv4hi3
,
11121 SPARC_BUILTIN_FPSUB16
, v4hi_ftype_v4hi_v4hi
);
11122 def_builtin_const ("__builtin_vis_fpsub16s", CODE_FOR_subv2hi3
,
11123 SPARC_BUILTIN_FPSUB16S
, v2hi_ftype_v2hi_v2hi
);
11124 def_builtin_const ("__builtin_vis_fpsub32", CODE_FOR_subv2si3
,
11125 SPARC_BUILTIN_FPSUB32
, v2si_ftype_v2si_v2si
);
11126 def_builtin_const ("__builtin_vis_fpsub32s", CODE_FOR_subv1si3
,
11127 SPARC_BUILTIN_FPSUB32S
, v1si_ftype_v1si_v1si
);
11129 /* Three-dimensional array addressing. */
11132 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8di_vis
,
11133 SPARC_BUILTIN_ARRAY8
, di_ftype_di_di
);
11134 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16di_vis
,
11135 SPARC_BUILTIN_ARRAY16
, di_ftype_di_di
);
11136 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32di_vis
,
11137 SPARC_BUILTIN_ARRAY32
, di_ftype_di_di
);
11141 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8si_vis
,
11142 SPARC_BUILTIN_ARRAY8
, si_ftype_si_si
);
11143 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16si_vis
,
11144 SPARC_BUILTIN_ARRAY16
, si_ftype_si_si
);
11145 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32si_vis
,
11146 SPARC_BUILTIN_ARRAY32
, si_ftype_si_si
);
11151 /* Edge handling. */
11154 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8ndi_vis
,
11155 SPARC_BUILTIN_EDGE8N
, di_ftype_ptr_ptr
);
11156 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lndi_vis
,
11157 SPARC_BUILTIN_EDGE8LN
, di_ftype_ptr_ptr
);
11158 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16ndi_vis
,
11159 SPARC_BUILTIN_EDGE16N
, di_ftype_ptr_ptr
);
11160 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lndi_vis
,
11161 SPARC_BUILTIN_EDGE16LN
, di_ftype_ptr_ptr
);
11162 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32ndi_vis
,
11163 SPARC_BUILTIN_EDGE32N
, di_ftype_ptr_ptr
);
11164 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lndi_vis
,
11165 SPARC_BUILTIN_EDGE32LN
, di_ftype_ptr_ptr
);
11169 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8nsi_vis
,
11170 SPARC_BUILTIN_EDGE8N
, si_ftype_ptr_ptr
);
11171 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lnsi_vis
,
11172 SPARC_BUILTIN_EDGE8LN
, si_ftype_ptr_ptr
);
11173 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16nsi_vis
,
11174 SPARC_BUILTIN_EDGE16N
, si_ftype_ptr_ptr
);
11175 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lnsi_vis
,
11176 SPARC_BUILTIN_EDGE16LN
, si_ftype_ptr_ptr
);
11177 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32nsi_vis
,
11178 SPARC_BUILTIN_EDGE32N
, si_ftype_ptr_ptr
);
11179 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lnsi_vis
,
11180 SPARC_BUILTIN_EDGE32LN
, si_ftype_ptr_ptr
);
11183 /* Byte mask and shuffle. */
11185 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmaskdi_vis
,
11186 SPARC_BUILTIN_BMASK
, di_ftype_di_di
);
11188 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmasksi_vis
,
11189 SPARC_BUILTIN_BMASK
, si_ftype_si_si
);
11190 def_builtin ("__builtin_vis_bshufflev4hi", CODE_FOR_bshufflev4hi_vis
,
11191 SPARC_BUILTIN_BSHUFFLEV4HI
, v4hi_ftype_v4hi_v4hi
);
11192 def_builtin ("__builtin_vis_bshufflev8qi", CODE_FOR_bshufflev8qi_vis
,
11193 SPARC_BUILTIN_BSHUFFLEV8QI
, v8qi_ftype_v8qi_v8qi
);
11194 def_builtin ("__builtin_vis_bshufflev2si", CODE_FOR_bshufflev2si_vis
,
11195 SPARC_BUILTIN_BSHUFFLEV2SI
, v2si_ftype_v2si_v2si
);
11196 def_builtin ("__builtin_vis_bshuffledi", CODE_FOR_bshufflev1di_vis
,
11197 SPARC_BUILTIN_BSHUFFLEDI
, di_ftype_di_di
);
11204 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8di_vis
,
11205 SPARC_BUILTIN_CMASK8
, void_ftype_di
);
11206 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16di_vis
,
11207 SPARC_BUILTIN_CMASK16
, void_ftype_di
);
11208 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32di_vis
,
11209 SPARC_BUILTIN_CMASK32
, void_ftype_di
);
11213 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8si_vis
,
11214 SPARC_BUILTIN_CMASK8
, void_ftype_si
);
11215 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16si_vis
,
11216 SPARC_BUILTIN_CMASK16
, void_ftype_si
);
11217 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32si_vis
,
11218 SPARC_BUILTIN_CMASK32
, void_ftype_si
);
11221 def_builtin_const ("__builtin_vis_fchksm16", CODE_FOR_fchksm16_vis
,
11222 SPARC_BUILTIN_FCHKSM16
, v4hi_ftype_v4hi_v4hi
);
11224 def_builtin_const ("__builtin_vis_fsll16", CODE_FOR_vashlv4hi3
,
11225 SPARC_BUILTIN_FSLL16
, v4hi_ftype_v4hi_v4hi
);
11226 def_builtin_const ("__builtin_vis_fslas16", CODE_FOR_vssashlv4hi3
,
11227 SPARC_BUILTIN_FSLAS16
, v4hi_ftype_v4hi_v4hi
);
11228 def_builtin_const ("__builtin_vis_fsrl16", CODE_FOR_vlshrv4hi3
,
11229 SPARC_BUILTIN_FSRL16
, v4hi_ftype_v4hi_v4hi
);
11230 def_builtin_const ("__builtin_vis_fsra16", CODE_FOR_vashrv4hi3
,
11231 SPARC_BUILTIN_FSRA16
, v4hi_ftype_v4hi_v4hi
);
11232 def_builtin_const ("__builtin_vis_fsll32", CODE_FOR_vashlv2si3
,
11233 SPARC_BUILTIN_FSLL32
, v2si_ftype_v2si_v2si
);
11234 def_builtin_const ("__builtin_vis_fslas32", CODE_FOR_vssashlv2si3
,
11235 SPARC_BUILTIN_FSLAS32
, v2si_ftype_v2si_v2si
);
11236 def_builtin_const ("__builtin_vis_fsrl32", CODE_FOR_vlshrv2si3
,
11237 SPARC_BUILTIN_FSRL32
, v2si_ftype_v2si_v2si
);
11238 def_builtin_const ("__builtin_vis_fsra32", CODE_FOR_vashrv2si3
,
11239 SPARC_BUILTIN_FSRA32
, v2si_ftype_v2si_v2si
);
11242 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistndi_vis
,
11243 SPARC_BUILTIN_PDISTN
, di_ftype_v8qi_v8qi
);
11245 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistnsi_vis
,
11246 SPARC_BUILTIN_PDISTN
, si_ftype_v8qi_v8qi
);
11248 def_builtin_const ("__builtin_vis_fmean16", CODE_FOR_fmean16_vis
,
11249 SPARC_BUILTIN_FMEAN16
, v4hi_ftype_v4hi_v4hi
);
11250 def_builtin_const ("__builtin_vis_fpadd64", CODE_FOR_fpadd64_vis
,
11251 SPARC_BUILTIN_FPADD64
, di_ftype_di_di
);
11252 def_builtin_const ("__builtin_vis_fpsub64", CODE_FOR_fpsub64_vis
,
11253 SPARC_BUILTIN_FPSUB64
, di_ftype_di_di
);
11255 def_builtin_const ("__builtin_vis_fpadds16", CODE_FOR_ssaddv4hi3
,
11256 SPARC_BUILTIN_FPADDS16
, v4hi_ftype_v4hi_v4hi
);
11257 def_builtin_const ("__builtin_vis_fpadds16s", CODE_FOR_ssaddv2hi3
,
11258 SPARC_BUILTIN_FPADDS16S
, v2hi_ftype_v2hi_v2hi
);
11259 def_builtin_const ("__builtin_vis_fpsubs16", CODE_FOR_sssubv4hi3
,
11260 SPARC_BUILTIN_FPSUBS16
, v4hi_ftype_v4hi_v4hi
);
11261 def_builtin_const ("__builtin_vis_fpsubs16s", CODE_FOR_sssubv2hi3
,
11262 SPARC_BUILTIN_FPSUBS16S
, v2hi_ftype_v2hi_v2hi
);
11263 def_builtin_const ("__builtin_vis_fpadds32", CODE_FOR_ssaddv2si3
,
11264 SPARC_BUILTIN_FPADDS32
, v2si_ftype_v2si_v2si
);
11265 def_builtin_const ("__builtin_vis_fpadds32s", CODE_FOR_ssaddv1si3
,
11266 SPARC_BUILTIN_FPADDS32S
, v1si_ftype_v1si_v1si
);
11267 def_builtin_const ("__builtin_vis_fpsubs32", CODE_FOR_sssubv2si3
,
11268 SPARC_BUILTIN_FPSUBS32
, v2si_ftype_v2si_v2si
);
11269 def_builtin_const ("__builtin_vis_fpsubs32s", CODE_FOR_sssubv1si3
,
11270 SPARC_BUILTIN_FPSUBS32S
, v1si_ftype_v1si_v1si
);
11274 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8di_vis
,
11275 SPARC_BUILTIN_FUCMPLE8
, di_ftype_v8qi_v8qi
);
11276 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8di_vis
,
11277 SPARC_BUILTIN_FUCMPNE8
, di_ftype_v8qi_v8qi
);
11278 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8di_vis
,
11279 SPARC_BUILTIN_FUCMPGT8
, di_ftype_v8qi_v8qi
);
11280 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8di_vis
,
11281 SPARC_BUILTIN_FUCMPEQ8
, di_ftype_v8qi_v8qi
);
11285 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8si_vis
,
11286 SPARC_BUILTIN_FUCMPLE8
, si_ftype_v8qi_v8qi
);
11287 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8si_vis
,
11288 SPARC_BUILTIN_FUCMPNE8
, si_ftype_v8qi_v8qi
);
11289 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8si_vis
,
11290 SPARC_BUILTIN_FUCMPGT8
, si_ftype_v8qi_v8qi
);
11291 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8si_vis
,
11292 SPARC_BUILTIN_FUCMPEQ8
, si_ftype_v8qi_v8qi
);
11295 def_builtin_const ("__builtin_vis_fhadds", CODE_FOR_fhaddsf_vis
,
11296 SPARC_BUILTIN_FHADDS
, sf_ftype_sf_sf
);
11297 def_builtin_const ("__builtin_vis_fhaddd", CODE_FOR_fhadddf_vis
,
11298 SPARC_BUILTIN_FHADDD
, df_ftype_df_df
);
11299 def_builtin_const ("__builtin_vis_fhsubs", CODE_FOR_fhsubsf_vis
,
11300 SPARC_BUILTIN_FHSUBS
, sf_ftype_sf_sf
);
11301 def_builtin_const ("__builtin_vis_fhsubd", CODE_FOR_fhsubdf_vis
,
11302 SPARC_BUILTIN_FHSUBD
, df_ftype_df_df
);
11303 def_builtin_const ("__builtin_vis_fnhadds", CODE_FOR_fnhaddsf_vis
,
11304 SPARC_BUILTIN_FNHADDS
, sf_ftype_sf_sf
);
11305 def_builtin_const ("__builtin_vis_fnhaddd", CODE_FOR_fnhadddf_vis
,
11306 SPARC_BUILTIN_FNHADDD
, df_ftype_df_df
);
11308 def_builtin_const ("__builtin_vis_umulxhi", CODE_FOR_umulxhi_vis
,
11309 SPARC_BUILTIN_UMULXHI
, di_ftype_di_di
);
11310 def_builtin_const ("__builtin_vis_xmulx", CODE_FOR_xmulx_vis
,
11311 SPARC_BUILTIN_XMULX
, di_ftype_di_di
);
11312 def_builtin_const ("__builtin_vis_xmulxhi", CODE_FOR_xmulxhi_vis
,
11313 SPARC_BUILTIN_XMULXHI
, di_ftype_di_di
);
11318 def_builtin_const ("__builtin_vis_fpadd8", CODE_FOR_addv8qi3
,
11319 SPARC_BUILTIN_FPADD8
, v8qi_ftype_v8qi_v8qi
);
11320 def_builtin_const ("__builtin_vis_fpadds8", CODE_FOR_ssaddv8qi3
,
11321 SPARC_BUILTIN_FPADDS8
, v8qi_ftype_v8qi_v8qi
);
11322 def_builtin_const ("__builtin_vis_fpaddus8", CODE_FOR_usaddv8qi3
,
11323 SPARC_BUILTIN_FPADDUS8
, v8qi_ftype_v8qi_v8qi
);
11324 def_builtin_const ("__builtin_vis_fpaddus16", CODE_FOR_usaddv4hi3
,
11325 SPARC_BUILTIN_FPADDUS16
, v4hi_ftype_v4hi_v4hi
);
11330 def_builtin_const ("__builtin_vis_fpcmple8", CODE_FOR_fpcmple8di_vis
,
11331 SPARC_BUILTIN_FPCMPLE8
, di_ftype_v8qi_v8qi
);
11332 def_builtin_const ("__builtin_vis_fpcmpgt8", CODE_FOR_fpcmpgt8di_vis
,
11333 SPARC_BUILTIN_FPCMPGT8
, di_ftype_v8qi_v8qi
);
11334 def_builtin_const ("__builtin_vis_fpcmpule16", CODE_FOR_fpcmpule16di_vis
,
11335 SPARC_BUILTIN_FPCMPULE16
, di_ftype_v4hi_v4hi
);
11336 def_builtin_const ("__builtin_vis_fpcmpugt16", CODE_FOR_fpcmpugt16di_vis
,
11337 SPARC_BUILTIN_FPCMPUGT16
, di_ftype_v4hi_v4hi
);
11338 def_builtin_const ("__builtin_vis_fpcmpule32", CODE_FOR_fpcmpule32di_vis
,
11339 SPARC_BUILTIN_FPCMPULE32
, di_ftype_v2si_v2si
);
11340 def_builtin_const ("__builtin_vis_fpcmpugt32", CODE_FOR_fpcmpugt32di_vis
,
11341 SPARC_BUILTIN_FPCMPUGT32
, di_ftype_v2si_v2si
);
11345 def_builtin_const ("__builtin_vis_fpcmple8", CODE_FOR_fpcmple8si_vis
,
11346 SPARC_BUILTIN_FPCMPLE8
, si_ftype_v8qi_v8qi
);
11347 def_builtin_const ("__builtin_vis_fpcmpgt8", CODE_FOR_fpcmpgt8si_vis
,
11348 SPARC_BUILTIN_FPCMPGT8
, si_ftype_v8qi_v8qi
);
11349 def_builtin_const ("__builtin_vis_fpcmpule16", CODE_FOR_fpcmpule16si_vis
,
11350 SPARC_BUILTIN_FPCMPULE16
, si_ftype_v4hi_v4hi
);
11351 def_builtin_const ("__builtin_vis_fpcmpugt16", CODE_FOR_fpcmpugt16si_vis
,
11352 SPARC_BUILTIN_FPCMPUGT16
, si_ftype_v4hi_v4hi
);
11353 def_builtin_const ("__builtin_vis_fpcmpule32", CODE_FOR_fpcmpule32si_vis
,
11354 SPARC_BUILTIN_FPCMPULE32
, di_ftype_v2si_v2si
);
11355 def_builtin_const ("__builtin_vis_fpcmpugt32", CODE_FOR_fpcmpugt32si_vis
,
11356 SPARC_BUILTIN_FPCMPUGT32
, di_ftype_v2si_v2si
);
11359 def_builtin_const ("__builtin_vis_fpmax8", CODE_FOR_maxv8qi3
,
11360 SPARC_BUILTIN_FPMAX8
, v8qi_ftype_v8qi_v8qi
);
11361 def_builtin_const ("__builtin_vis_fpmax16", CODE_FOR_maxv4hi3
,
11362 SPARC_BUILTIN_FPMAX16
, v4hi_ftype_v4hi_v4hi
);
11363 def_builtin_const ("__builtin_vis_fpmax32", CODE_FOR_maxv2si3
,
11364 SPARC_BUILTIN_FPMAX32
, v2si_ftype_v2si_v2si
);
11365 def_builtin_const ("__builtin_vis_fpmaxu8", CODE_FOR_maxuv8qi3
,
11366 SPARC_BUILTIN_FPMAXU8
, v8qi_ftype_v8qi_v8qi
);
11367 def_builtin_const ("__builtin_vis_fpmaxu16", CODE_FOR_maxuv4hi3
,
11368 SPARC_BUILTIN_FPMAXU16
, v4hi_ftype_v4hi_v4hi
);
11369 def_builtin_const ("__builtin_vis_fpmaxu32", CODE_FOR_maxuv2si3
,
11370 SPARC_BUILTIN_FPMAXU32
, v2si_ftype_v2si_v2si
);
11371 def_builtin_const ("__builtin_vis_fpmin8", CODE_FOR_minv8qi3
,
11372 SPARC_BUILTIN_FPMIN8
, v8qi_ftype_v8qi_v8qi
);
11373 def_builtin_const ("__builtin_vis_fpmin16", CODE_FOR_minv4hi3
,
11374 SPARC_BUILTIN_FPMIN16
, v4hi_ftype_v4hi_v4hi
);
11375 def_builtin_const ("__builtin_vis_fpmin32", CODE_FOR_minv2si3
,
11376 SPARC_BUILTIN_FPMIN32
, v2si_ftype_v2si_v2si
);
11377 def_builtin_const ("__builtin_vis_fpminu8", CODE_FOR_minuv8qi3
,
11378 SPARC_BUILTIN_FPMINU8
, v8qi_ftype_v8qi_v8qi
);
11379 def_builtin_const ("__builtin_vis_fpminu16", CODE_FOR_minuv4hi3
,
11380 SPARC_BUILTIN_FPMINU16
, v4hi_ftype_v4hi_v4hi
);
11381 def_builtin_const ("__builtin_vis_fpminu32", CODE_FOR_minuv2si3
,
11382 SPARC_BUILTIN_FPMINU32
, v2si_ftype_v2si_v2si
);
11383 def_builtin_const ("__builtin_vis_fpsub8", CODE_FOR_subv8qi3
,
11384 SPARC_BUILTIN_FPSUB8
, v8qi_ftype_v8qi_v8qi
);
11385 def_builtin_const ("__builtin_vis_fpsubs8", CODE_FOR_sssubv8qi3
,
11386 SPARC_BUILTIN_FPSUBS8
, v8qi_ftype_v8qi_v8qi
);
11387 def_builtin_const ("__builtin_vis_fpsubus8", CODE_FOR_ussubv8qi3
,
11388 SPARC_BUILTIN_FPSUBUS8
, v8qi_ftype_v8qi_v8qi
);
11389 def_builtin_const ("__builtin_vis_fpsubus16", CODE_FOR_ussubv4hi3
,
11390 SPARC_BUILTIN_FPSUBUS16
, v4hi_ftype_v4hi_v4hi
);
11395 def_builtin_const ("__builtin_vis_dictunpack8", CODE_FOR_dictunpack8
,
11396 SPARC_BUILTIN_DICTUNPACK8
, v8qi_ftype_df_si
);
11397 def_builtin_const ("__builtin_vis_dictunpack16", CODE_FOR_dictunpack16
,
11398 SPARC_BUILTIN_DICTUNPACK16
, v4hi_ftype_df_si
);
11399 def_builtin_const ("__builtin_vis_dictunpack32", CODE_FOR_dictunpack32
,
11400 SPARC_BUILTIN_DICTUNPACK32
, v2si_ftype_df_si
);
11404 tree di_ftype_v8qi_v8qi_si
= build_function_type_list (intDI_type_node
,
11406 intSI_type_node
, 0);
11407 tree di_ftype_v4hi_v4hi_si
= build_function_type_list (intDI_type_node
,
11409 intSI_type_node
, 0);
11410 tree di_ftype_v2si_v2si_si
= build_function_type_list (intDI_type_node
,
11412 intSI_type_node
, 0);
11414 def_builtin_const ("__builtin_vis_fpcmple8shl", CODE_FOR_fpcmple8dishl
,
11415 SPARC_BUILTIN_FPCMPLE8SHL
, di_ftype_v8qi_v8qi_si
);
11416 def_builtin_const ("__builtin_vis_fpcmpgt8shl", CODE_FOR_fpcmpgt8dishl
,
11417 SPARC_BUILTIN_FPCMPGT8SHL
, di_ftype_v8qi_v8qi_si
);
11418 def_builtin_const ("__builtin_vis_fpcmpeq8shl", CODE_FOR_fpcmpeq8dishl
,
11419 SPARC_BUILTIN_FPCMPEQ8SHL
, di_ftype_v8qi_v8qi_si
);
11420 def_builtin_const ("__builtin_vis_fpcmpne8shl", CODE_FOR_fpcmpne8dishl
,
11421 SPARC_BUILTIN_FPCMPNE8SHL
, di_ftype_v8qi_v8qi_si
);
11423 def_builtin_const ("__builtin_vis_fpcmple16shl", CODE_FOR_fpcmple16dishl
,
11424 SPARC_BUILTIN_FPCMPLE16SHL
, di_ftype_v4hi_v4hi_si
);
11425 def_builtin_const ("__builtin_vis_fpcmpgt16shl", CODE_FOR_fpcmpgt16dishl
,
11426 SPARC_BUILTIN_FPCMPGT16SHL
, di_ftype_v4hi_v4hi_si
);
11427 def_builtin_const ("__builtin_vis_fpcmpeq16shl", CODE_FOR_fpcmpeq16dishl
,
11428 SPARC_BUILTIN_FPCMPEQ16SHL
, di_ftype_v4hi_v4hi_si
);
11429 def_builtin_const ("__builtin_vis_fpcmpne16shl", CODE_FOR_fpcmpne16dishl
,
11430 SPARC_BUILTIN_FPCMPNE16SHL
, di_ftype_v4hi_v4hi_si
);
11432 def_builtin_const ("__builtin_vis_fpcmple32shl", CODE_FOR_fpcmple32dishl
,
11433 SPARC_BUILTIN_FPCMPLE32SHL
, di_ftype_v2si_v2si_si
);
11434 def_builtin_const ("__builtin_vis_fpcmpgt32shl", CODE_FOR_fpcmpgt32dishl
,
11435 SPARC_BUILTIN_FPCMPGT32SHL
, di_ftype_v2si_v2si_si
);
11436 def_builtin_const ("__builtin_vis_fpcmpeq32shl", CODE_FOR_fpcmpeq32dishl
,
11437 SPARC_BUILTIN_FPCMPEQ32SHL
, di_ftype_v2si_v2si_si
);
11438 def_builtin_const ("__builtin_vis_fpcmpne32shl", CODE_FOR_fpcmpne32dishl
,
11439 SPARC_BUILTIN_FPCMPNE32SHL
, di_ftype_v2si_v2si_si
);
11442 def_builtin_const ("__builtin_vis_fpcmpule8shl", CODE_FOR_fpcmpule8dishl
,
11443 SPARC_BUILTIN_FPCMPULE8SHL
, di_ftype_v8qi_v8qi_si
);
11444 def_builtin_const ("__builtin_vis_fpcmpugt8shl", CODE_FOR_fpcmpugt8dishl
,
11445 SPARC_BUILTIN_FPCMPUGT8SHL
, di_ftype_v8qi_v8qi_si
);
11447 def_builtin_const ("__builtin_vis_fpcmpule16shl", CODE_FOR_fpcmpule16dishl
,
11448 SPARC_BUILTIN_FPCMPULE16SHL
, di_ftype_v4hi_v4hi_si
);
11449 def_builtin_const ("__builtin_vis_fpcmpugt16shl", CODE_FOR_fpcmpugt16dishl
,
11450 SPARC_BUILTIN_FPCMPUGT16SHL
, di_ftype_v4hi_v4hi_si
);
11452 def_builtin_const ("__builtin_vis_fpcmpule32shl", CODE_FOR_fpcmpule32dishl
,
11453 SPARC_BUILTIN_FPCMPULE32SHL
, di_ftype_v2si_v2si_si
);
11454 def_builtin_const ("__builtin_vis_fpcmpugt32shl", CODE_FOR_fpcmpugt32dishl
,
11455 SPARC_BUILTIN_FPCMPUGT32SHL
, di_ftype_v2si_v2si_si
);
11457 def_builtin_const ("__builtin_vis_fpcmpde8shl", CODE_FOR_fpcmpde8dishl
,
11458 SPARC_BUILTIN_FPCMPDE8SHL
, di_ftype_v8qi_v8qi_si
);
11459 def_builtin_const ("__builtin_vis_fpcmpde16shl", CODE_FOR_fpcmpde16dishl
,
11460 SPARC_BUILTIN_FPCMPDE16SHL
, di_ftype_v4hi_v4hi_si
);
11461 def_builtin_const ("__builtin_vis_fpcmpde32shl", CODE_FOR_fpcmpde32dishl
,
11462 SPARC_BUILTIN_FPCMPDE32SHL
, di_ftype_v2si_v2si_si
);
11464 def_builtin_const ("__builtin_vis_fpcmpur8shl", CODE_FOR_fpcmpur8dishl
,
11465 SPARC_BUILTIN_FPCMPUR8SHL
, di_ftype_v8qi_v8qi_si
);
11466 def_builtin_const ("__builtin_vis_fpcmpur16shl", CODE_FOR_fpcmpur16dishl
,
11467 SPARC_BUILTIN_FPCMPUR16SHL
, di_ftype_v4hi_v4hi_si
);
11468 def_builtin_const ("__builtin_vis_fpcmpur32shl", CODE_FOR_fpcmpur32dishl
,
11469 SPARC_BUILTIN_FPCMPUR32SHL
, di_ftype_v2si_v2si_si
);
11474 tree si_ftype_v8qi_v8qi_si
= build_function_type_list (intSI_type_node
,
11476 intSI_type_node
, 0);
11477 tree si_ftype_v4hi_v4hi_si
= build_function_type_list (intSI_type_node
,
11479 intSI_type_node
, 0);
11480 tree si_ftype_v2si_v2si_si
= build_function_type_list (intSI_type_node
,
11482 intSI_type_node
, 0);
11484 def_builtin_const ("__builtin_vis_fpcmple8shl", CODE_FOR_fpcmple8sishl
,
11485 SPARC_BUILTIN_FPCMPLE8SHL
, si_ftype_v8qi_v8qi_si
);
11486 def_builtin_const ("__builtin_vis_fpcmpgt8shl", CODE_FOR_fpcmpgt8sishl
,
11487 SPARC_BUILTIN_FPCMPGT8SHL
, si_ftype_v8qi_v8qi_si
);
11488 def_builtin_const ("__builtin_vis_fpcmpeq8shl", CODE_FOR_fpcmpeq8sishl
,
11489 SPARC_BUILTIN_FPCMPEQ8SHL
, si_ftype_v8qi_v8qi_si
);
11490 def_builtin_const ("__builtin_vis_fpcmpne8shl", CODE_FOR_fpcmpne8sishl
,
11491 SPARC_BUILTIN_FPCMPNE8SHL
, si_ftype_v8qi_v8qi_si
);
11493 def_builtin_const ("__builtin_vis_fpcmple16shl", CODE_FOR_fpcmple16sishl
,
11494 SPARC_BUILTIN_FPCMPLE16SHL
, si_ftype_v4hi_v4hi_si
);
11495 def_builtin_const ("__builtin_vis_fpcmpgt16shl", CODE_FOR_fpcmpgt16sishl
,
11496 SPARC_BUILTIN_FPCMPGT16SHL
, si_ftype_v4hi_v4hi_si
);
11497 def_builtin_const ("__builtin_vis_fpcmpeq16shl", CODE_FOR_fpcmpeq16sishl
,
11498 SPARC_BUILTIN_FPCMPEQ16SHL
, si_ftype_v4hi_v4hi_si
);
11499 def_builtin_const ("__builtin_vis_fpcmpne16shl", CODE_FOR_fpcmpne16sishl
,
11500 SPARC_BUILTIN_FPCMPNE16SHL
, si_ftype_v4hi_v4hi_si
);
11502 def_builtin_const ("__builtin_vis_fpcmple32shl", CODE_FOR_fpcmple32sishl
,
11503 SPARC_BUILTIN_FPCMPLE32SHL
, si_ftype_v2si_v2si_si
);
11504 def_builtin_const ("__builtin_vis_fpcmpgt32shl", CODE_FOR_fpcmpgt32sishl
,
11505 SPARC_BUILTIN_FPCMPGT32SHL
, si_ftype_v2si_v2si_si
);
11506 def_builtin_const ("__builtin_vis_fpcmpeq32shl", CODE_FOR_fpcmpeq32sishl
,
11507 SPARC_BUILTIN_FPCMPEQ32SHL
, si_ftype_v2si_v2si_si
);
11508 def_builtin_const ("__builtin_vis_fpcmpne32shl", CODE_FOR_fpcmpne32sishl
,
11509 SPARC_BUILTIN_FPCMPNE32SHL
, si_ftype_v2si_v2si_si
);
11512 def_builtin_const ("__builtin_vis_fpcmpule8shl", CODE_FOR_fpcmpule8sishl
,
11513 SPARC_BUILTIN_FPCMPULE8SHL
, si_ftype_v8qi_v8qi_si
);
11514 def_builtin_const ("__builtin_vis_fpcmpugt8shl", CODE_FOR_fpcmpugt8sishl
,
11515 SPARC_BUILTIN_FPCMPUGT8SHL
, si_ftype_v8qi_v8qi_si
);
11517 def_builtin_const ("__builtin_vis_fpcmpule16shl", CODE_FOR_fpcmpule16sishl
,
11518 SPARC_BUILTIN_FPCMPULE16SHL
, si_ftype_v4hi_v4hi_si
);
11519 def_builtin_const ("__builtin_vis_fpcmpugt16shl", CODE_FOR_fpcmpugt16sishl
,
11520 SPARC_BUILTIN_FPCMPUGT16SHL
, si_ftype_v4hi_v4hi_si
);
11522 def_builtin_const ("__builtin_vis_fpcmpule32shl", CODE_FOR_fpcmpule32sishl
,
11523 SPARC_BUILTIN_FPCMPULE32SHL
, si_ftype_v2si_v2si_si
);
11524 def_builtin_const ("__builtin_vis_fpcmpugt32shl", CODE_FOR_fpcmpugt32sishl
,
11525 SPARC_BUILTIN_FPCMPUGT32SHL
, si_ftype_v2si_v2si_si
);
11527 def_builtin_const ("__builtin_vis_fpcmpde8shl", CODE_FOR_fpcmpde8sishl
,
11528 SPARC_BUILTIN_FPCMPDE8SHL
, si_ftype_v8qi_v8qi_si
);
11529 def_builtin_const ("__builtin_vis_fpcmpde16shl", CODE_FOR_fpcmpde16sishl
,
11530 SPARC_BUILTIN_FPCMPDE16SHL
, si_ftype_v4hi_v4hi_si
);
11531 def_builtin_const ("__builtin_vis_fpcmpde32shl", CODE_FOR_fpcmpde32sishl
,
11532 SPARC_BUILTIN_FPCMPDE32SHL
, si_ftype_v2si_v2si_si
);
11534 def_builtin_const ("__builtin_vis_fpcmpur8shl", CODE_FOR_fpcmpur8sishl
,
11535 SPARC_BUILTIN_FPCMPUR8SHL
, si_ftype_v8qi_v8qi_si
);
11536 def_builtin_const ("__builtin_vis_fpcmpur16shl", CODE_FOR_fpcmpur16sishl
,
11537 SPARC_BUILTIN_FPCMPUR16SHL
, si_ftype_v4hi_v4hi_si
);
11538 def_builtin_const ("__builtin_vis_fpcmpur32shl", CODE_FOR_fpcmpur32sishl
,
11539 SPARC_BUILTIN_FPCMPUR32SHL
, si_ftype_v2si_v2si_si
);
11544 /* Implement TARGET_BUILTIN_DECL hook. */
11547 sparc_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
11549 if (code
>= SPARC_BUILTIN_MAX
)
11550 return error_mark_node
;
11552 return sparc_builtins
[code
];
11555 /* Implemented TARGET_EXPAND_BUILTIN hook. */
11558 sparc_expand_builtin (tree exp
, rtx target
,
11559 rtx subtarget ATTRIBUTE_UNUSED
,
11560 machine_mode tmode ATTRIBUTE_UNUSED
,
11561 int ignore ATTRIBUTE_UNUSED
)
11563 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
11564 enum sparc_builtins code
= (enum sparc_builtins
) DECL_FUNCTION_CODE (fndecl
);
11565 enum insn_code icode
= sparc_builtins_icode
[code
];
11566 bool nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
11567 call_expr_arg_iterator iter
;
11574 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11576 || GET_MODE (target
) != tmode
11577 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11578 op
[0] = gen_reg_rtx (tmode
);
11583 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
11585 const struct insn_operand_data
*insn_op
;
11588 if (arg
== error_mark_node
)
11592 idx
= arg_count
- !nonvoid
;
11593 insn_op
= &insn_data
[icode
].operand
[idx
];
11594 op
[arg_count
] = expand_normal (arg
);
11596 /* Some of the builtins require constant arguments. We check
11598 if ((code
>= SPARC_BUILTIN_FIRST_FPCMPSHL
11599 && code
<= SPARC_BUILTIN_LAST_FPCMPSHL
11601 || (code
>= SPARC_BUILTIN_FIRST_DICTUNPACK
11602 && code
<= SPARC_BUILTIN_LAST_DICTUNPACK
11603 && arg_count
== 2))
11605 if (!check_constant_argument (icode
, idx
, op
[arg_count
]))
11609 if (code
== SPARC_BUILTIN_LDFSR
|| code
== SPARC_BUILTIN_STFSR
)
11611 if (!address_operand (op
[arg_count
], SImode
))
11613 op
[arg_count
] = convert_memory_address (Pmode
, op
[arg_count
]);
11614 op
[arg_count
] = copy_addr_to_reg (op
[arg_count
]);
11616 op
[arg_count
] = gen_rtx_MEM (SImode
, op
[arg_count
]);
11619 else if (insn_op
->mode
== V1DImode
11620 && GET_MODE (op
[arg_count
]) == DImode
)
11621 op
[arg_count
] = gen_lowpart (V1DImode
, op
[arg_count
]);
11623 else if (insn_op
->mode
== V1SImode
11624 && GET_MODE (op
[arg_count
]) == SImode
)
11625 op
[arg_count
] = gen_lowpart (V1SImode
, op
[arg_count
]);
11627 if (! (*insn_data
[icode
].operand
[idx
].predicate
) (op
[arg_count
],
11629 op
[arg_count
] = copy_to_mode_reg (insn_op
->mode
, op
[arg_count
]);
11635 pat
= GEN_FCN (icode
) (op
[0]);
11639 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
11641 pat
= GEN_FCN (icode
) (op
[1]);
11644 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
11647 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
11650 gcc_unreachable ();
11658 return (nonvoid
? op
[0] : const0_rtx
);
11661 /* Return the upper 16 bits of the 8x16 multiplication. */
11664 sparc_vis_mul8x16 (int e8
, int e16
)
11666 return (e8
* e16
+ 128) / 256;
11669 /* Multiply the VECTOR_CSTs CST0 and CST1 as specified by FNCODE and put
11670 the result into the array N_ELTS, whose elements are of INNER_TYPE. */
11673 sparc_handle_vis_mul8x16 (vec
<tree
> *n_elts
, enum sparc_builtins fncode
,
11674 tree inner_type
, tree cst0
, tree cst1
)
11676 unsigned i
, num
= VECTOR_CST_NELTS (cst0
);
11681 case SPARC_BUILTIN_FMUL8X16
:
11682 for (i
= 0; i
< num
; ++i
)
11685 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
11686 TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, i
)));
11687 n_elts
->quick_push (build_int_cst (inner_type
, val
));
11691 case SPARC_BUILTIN_FMUL8X16AU
:
11692 scale
= TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, 0));
11694 for (i
= 0; i
< num
; ++i
)
11697 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
11699 n_elts
->quick_push (build_int_cst (inner_type
, val
));
11703 case SPARC_BUILTIN_FMUL8X16AL
:
11704 scale
= TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, 1));
11706 for (i
= 0; i
< num
; ++i
)
11709 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
11711 n_elts
->quick_push (build_int_cst (inner_type
, val
));
11716 gcc_unreachable ();
11720 /* Implement TARGET_FOLD_BUILTIN hook.
11722 Fold builtin functions for SPARC intrinsics. If IGNORE is true the
11723 result of the function call is ignored. NULL_TREE is returned if the
11724 function could not be folded. */
11727 sparc_fold_builtin (tree fndecl
, int n_args ATTRIBUTE_UNUSED
,
11728 tree
*args
, bool ignore
)
11730 enum sparc_builtins code
= (enum sparc_builtins
) DECL_FUNCTION_CODE (fndecl
);
11731 tree rtype
= TREE_TYPE (TREE_TYPE (fndecl
));
11732 tree arg0
, arg1
, arg2
;
11737 case SPARC_BUILTIN_LDFSR
:
11738 case SPARC_BUILTIN_STFSR
:
11739 case SPARC_BUILTIN_ALIGNADDR
:
11740 case SPARC_BUILTIN_WRGSR
:
11741 case SPARC_BUILTIN_BMASK
:
11742 case SPARC_BUILTIN_CMASK8
:
11743 case SPARC_BUILTIN_CMASK16
:
11744 case SPARC_BUILTIN_CMASK32
:
11748 return build_zero_cst (rtype
);
11753 case SPARC_BUILTIN_FEXPAND
:
11757 if (TREE_CODE (arg0
) == VECTOR_CST
)
11759 tree inner_type
= TREE_TYPE (rtype
);
11762 tree_vector_builder
n_elts (rtype
, VECTOR_CST_NELTS (arg0
), 1);
11763 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
11765 unsigned HOST_WIDE_INT val
11766 = TREE_INT_CST_LOW (VECTOR_CST_ELT (arg0
, i
));
11767 n_elts
.quick_push (build_int_cst (inner_type
, val
<< 4));
11769 return n_elts
.build ();
11773 case SPARC_BUILTIN_FMUL8X16
:
11774 case SPARC_BUILTIN_FMUL8X16AU
:
11775 case SPARC_BUILTIN_FMUL8X16AL
:
11781 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
11783 tree inner_type
= TREE_TYPE (rtype
);
11784 tree_vector_builder
n_elts (rtype
, VECTOR_CST_NELTS (arg0
), 1);
11785 sparc_handle_vis_mul8x16 (&n_elts
, code
, inner_type
, arg0
, arg1
);
11786 return n_elts
.build ();
11790 case SPARC_BUILTIN_FPMERGE
:
11796 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
11798 tree_vector_builder
n_elts (rtype
, 2 * VECTOR_CST_NELTS (arg0
), 1);
11800 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
11802 n_elts
.quick_push (VECTOR_CST_ELT (arg0
, i
));
11803 n_elts
.quick_push (VECTOR_CST_ELT (arg1
, i
));
11806 return n_elts
.build ();
11810 case SPARC_BUILTIN_PDIST
:
11811 case SPARC_BUILTIN_PDISTN
:
11816 if (code
== SPARC_BUILTIN_PDIST
)
11822 arg2
= integer_zero_node
;
11824 if (TREE_CODE (arg0
) == VECTOR_CST
11825 && TREE_CODE (arg1
) == VECTOR_CST
11826 && TREE_CODE (arg2
) == INTEGER_CST
)
11828 bool overflow
= false;
11829 widest_int result
= wi::to_widest (arg2
);
11833 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
11835 tree e0
= VECTOR_CST_ELT (arg0
, i
);
11836 tree e1
= VECTOR_CST_ELT (arg1
, i
);
11838 bool neg1_ovf
, neg2_ovf
, add1_ovf
, add2_ovf
;
11840 tmp
= wi::neg (wi::to_widest (e1
), &neg1_ovf
);
11841 tmp
= wi::add (wi::to_widest (e0
), tmp
, SIGNED
, &add1_ovf
);
11842 if (wi::neg_p (tmp
))
11843 tmp
= wi::neg (tmp
, &neg2_ovf
);
11846 result
= wi::add (result
, tmp
, SIGNED
, &add2_ovf
);
11847 overflow
|= neg1_ovf
| neg2_ovf
| add1_ovf
| add2_ovf
;
11850 gcc_assert (!overflow
);
11852 return wide_int_to_tree (rtype
, result
);
11862 /* ??? This duplicates information provided to the compiler by the
11863 ??? scheduler description. Some day, teach genautomata to output
11864 ??? the latencies and then CSE will just use that. */
11867 sparc_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
11868 int opno ATTRIBUTE_UNUSED
,
11869 int *total
, bool speed ATTRIBUTE_UNUSED
)
11871 int code
= GET_CODE (x
);
11872 bool float_mode_p
= FLOAT_MODE_P (mode
);
11883 case CONST_WIDE_INT
:
11885 if (!SPARC_SIMM13_P (CONST_WIDE_INT_ELT (x
, 0)))
11887 if (!SPARC_SIMM13_P (CONST_WIDE_INT_ELT (x
, 1)))
11906 /* If outer-code was a sign or zero extension, a cost
11907 of COSTS_N_INSNS (1) was already added in. This is
11908 why we are subtracting it back out. */
11909 if (outer_code
== ZERO_EXTEND
)
11911 *total
= sparc_costs
->int_zload
- COSTS_N_INSNS (1);
11913 else if (outer_code
== SIGN_EXTEND
)
11915 *total
= sparc_costs
->int_sload
- COSTS_N_INSNS (1);
11917 else if (float_mode_p
)
11919 *total
= sparc_costs
->float_load
;
11923 *total
= sparc_costs
->int_load
;
11931 *total
= sparc_costs
->float_plusminus
;
11933 *total
= COSTS_N_INSNS (1);
11940 gcc_assert (float_mode_p
);
11941 *total
= sparc_costs
->float_mul
;
11944 if (GET_CODE (sub
) == NEG
)
11945 sub
= XEXP (sub
, 0);
11946 *total
+= rtx_cost (sub
, mode
, FMA
, 0, speed
);
11949 if (GET_CODE (sub
) == NEG
)
11950 sub
= XEXP (sub
, 0);
11951 *total
+= rtx_cost (sub
, mode
, FMA
, 2, speed
);
11957 *total
= sparc_costs
->float_mul
;
11958 else if (TARGET_ARCH32
&& !TARGET_HARD_MUL
)
11959 *total
= COSTS_N_INSNS (25);
11965 if (sparc_costs
->int_mul_bit_factor
)
11969 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
11971 unsigned HOST_WIDE_INT value
= INTVAL (XEXP (x
, 1));
11972 for (nbits
= 0; value
!= 0; value
&= value
- 1)
11980 bit_cost
= (nbits
- 3) / sparc_costs
->int_mul_bit_factor
;
11981 bit_cost
= COSTS_N_INSNS (bit_cost
);
11984 if (mode
== DImode
|| !TARGET_HARD_MUL
)
11985 *total
= sparc_costs
->int_mulX
+ bit_cost
;
11987 *total
= sparc_costs
->int_mul
+ bit_cost
;
11994 *total
= COSTS_N_INSNS (1) + sparc_costs
->shift_penalty
;
12003 if (mode
== DFmode
)
12004 *total
= sparc_costs
->float_div_df
;
12006 *total
= sparc_costs
->float_div_sf
;
12010 if (mode
== DImode
)
12011 *total
= sparc_costs
->int_divX
;
12013 *total
= sparc_costs
->int_div
;
12018 if (! float_mode_p
)
12020 *total
= COSTS_N_INSNS (1);
12027 case UNSIGNED_FLOAT
:
12031 case FLOAT_TRUNCATE
:
12032 *total
= sparc_costs
->float_move
;
12036 if (mode
== DFmode
)
12037 *total
= sparc_costs
->float_sqrt_df
;
12039 *total
= sparc_costs
->float_sqrt_sf
;
12044 *total
= sparc_costs
->float_cmp
;
12046 *total
= COSTS_N_INSNS (1);
12051 *total
= sparc_costs
->float_cmove
;
12053 *total
= sparc_costs
->int_cmove
;
12057 /* Handle the NAND vector patterns. */
12058 if (sparc_vector_mode_supported_p (mode
)
12059 && GET_CODE (XEXP (x
, 0)) == NOT
12060 && GET_CODE (XEXP (x
, 1)) == NOT
)
12062 *total
= COSTS_N_INSNS (1);
12073 /* Return true if CLASS is either GENERAL_REGS or I64_REGS. */
12076 general_or_i64_p (reg_class_t rclass
)
12078 return (rclass
== GENERAL_REGS
|| rclass
== I64_REGS
);
12081 /* Implement TARGET_REGISTER_MOVE_COST. */
12084 sparc_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
12085 reg_class_t from
, reg_class_t to
)
12087 bool need_memory
= false;
12089 /* This helps postreload CSE to eliminate redundant comparisons. */
12090 if (from
== NO_REGS
|| to
== NO_REGS
)
12093 if (from
== FPCC_REGS
|| to
== FPCC_REGS
)
12094 need_memory
= true;
12095 else if ((FP_REG_CLASS_P (from
) && general_or_i64_p (to
))
12096 || (general_or_i64_p (from
) && FP_REG_CLASS_P (to
)))
12100 int size
= GET_MODE_SIZE (mode
);
12101 if (size
== 8 || size
== 4)
12103 if (! TARGET_ARCH32
|| size
== 4)
12109 need_memory
= true;
12114 if (sparc_cpu
== PROCESSOR_ULTRASPARC
12115 || sparc_cpu
== PROCESSOR_ULTRASPARC3
12116 || sparc_cpu
== PROCESSOR_NIAGARA
12117 || sparc_cpu
== PROCESSOR_NIAGARA2
12118 || sparc_cpu
== PROCESSOR_NIAGARA3
12119 || sparc_cpu
== PROCESSOR_NIAGARA4
12120 || sparc_cpu
== PROCESSOR_NIAGARA7
12121 || sparc_cpu
== PROCESSOR_M8
)
12130 /* Emit the sequence of insns SEQ while preserving the registers REG and REG2.
12131 This is achieved by means of a manual dynamic stack space allocation in
12132 the current frame. We make the assumption that SEQ doesn't contain any
12133 function calls, with the possible exception of calls to the GOT helper. */
12136 emit_and_preserve (rtx seq
, rtx reg
, rtx reg2
)
12138 /* We must preserve the lowest 16 words for the register save area. */
12139 HOST_WIDE_INT offset
= 16*UNITS_PER_WORD
;
12140 /* We really need only 2 words of fresh stack space. */
12141 HOST_WIDE_INT size
= SPARC_STACK_ALIGN (offset
+ 2*UNITS_PER_WORD
);
12144 = gen_rtx_MEM (word_mode
, plus_constant (Pmode
, stack_pointer_rtx
,
12145 SPARC_STACK_BIAS
+ offset
));
12147 emit_insn (gen_stack_pointer_inc (GEN_INT (-size
)));
12148 emit_insn (gen_rtx_SET (slot
, reg
));
12150 emit_insn (gen_rtx_SET (adjust_address (slot
, word_mode
, UNITS_PER_WORD
),
12154 emit_insn (gen_rtx_SET (reg2
,
12155 adjust_address (slot
, word_mode
, UNITS_PER_WORD
)));
12156 emit_insn (gen_rtx_SET (reg
, slot
));
12157 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
12160 /* Output the assembler code for a thunk function. THUNK_DECL is the
12161 declaration for the thunk function itself, FUNCTION is the decl for
12162 the target function. DELTA is an immediate constant offset to be
12163 added to THIS. If VCALL_OFFSET is nonzero, the word at address
12164 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
12167 sparc_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
12168 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
12171 rtx this_rtx
, funexp
;
12173 unsigned int int_arg_first
;
12175 reload_completed
= 1;
12176 epilogue_completed
= 1;
12178 emit_note (NOTE_INSN_PROLOGUE_END
);
12182 sparc_leaf_function_p
= 1;
12184 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
12186 else if (flag_delayed_branch
)
12188 /* We will emit a regular sibcall below, so we need to instruct
12189 output_sibcall that we are in a leaf function. */
12190 sparc_leaf_function_p
= crtl
->uses_only_leaf_regs
= 1;
12192 /* This will cause final.c to invoke leaf_renumber_regs so we
12193 must behave as if we were in a not-yet-leafified function. */
12194 int_arg_first
= SPARC_INCOMING_INT_ARG_FIRST
;
12198 /* We will emit the sibcall manually below, so we will need to
12199 manually spill non-leaf registers. */
12200 sparc_leaf_function_p
= crtl
->uses_only_leaf_regs
= 0;
12202 /* We really are in a leaf function. */
12203 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
12206 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
12207 returns a structure, the structure return pointer is there instead. */
12209 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
12210 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
+ 1);
12212 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
);
12214 /* Add DELTA. When possible use a plain add, otherwise load it into
12215 a register first. */
12218 rtx delta_rtx
= GEN_INT (delta
);
12220 if (! SPARC_SIMM13_P (delta
))
12222 rtx scratch
= gen_rtx_REG (Pmode
, 1);
12223 emit_move_insn (scratch
, delta_rtx
);
12224 delta_rtx
= scratch
;
12227 /* THIS_RTX += DELTA. */
12228 emit_insn (gen_add2_insn (this_rtx
, delta_rtx
));
12231 /* Add the word at address (*THIS_RTX + VCALL_OFFSET). */
12234 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
12235 rtx scratch
= gen_rtx_REG (Pmode
, 1);
12237 gcc_assert (vcall_offset
< 0);
12239 /* SCRATCH = *THIS_RTX. */
12240 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
, this_rtx
));
12242 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
12243 may not have any available scratch register at this point. */
12244 if (SPARC_SIMM13_P (vcall_offset
))
12246 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
12247 else if (! fixed_regs
[5]
12248 /* The below sequence is made up of at least 2 insns,
12249 while the default method may need only one. */
12250 && vcall_offset
< -8192)
12252 rtx scratch2
= gen_rtx_REG (Pmode
, 5);
12253 emit_move_insn (scratch2
, vcall_offset_rtx
);
12254 vcall_offset_rtx
= scratch2
;
12258 rtx increment
= GEN_INT (-4096);
12260 /* VCALL_OFFSET is a negative number whose typical range can be
12261 estimated as -32768..0 in 32-bit mode. In almost all cases
12262 it is therefore cheaper to emit multiple add insns than
12263 spilling and loading the constant into a register (at least
12265 while (! SPARC_SIMM13_P (vcall_offset
))
12267 emit_insn (gen_add2_insn (scratch
, increment
));
12268 vcall_offset
+= 4096;
12270 vcall_offset_rtx
= GEN_INT (vcall_offset
); /* cannot be 0 */
12273 /* SCRATCH = *(*THIS_RTX + VCALL_OFFSET). */
12274 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
,
12275 gen_rtx_PLUS (Pmode
,
12277 vcall_offset_rtx
)));
12279 /* THIS_RTX += *(*THIS_RTX + VCALL_OFFSET). */
12280 emit_insn (gen_add2_insn (this_rtx
, scratch
));
12283 /* Generate a tail call to the target function. */
12284 if (! TREE_USED (function
))
12286 assemble_external (function
);
12287 TREE_USED (function
) = 1;
12289 funexp
= XEXP (DECL_RTL (function
), 0);
12291 if (flag_delayed_branch
)
12293 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
12294 insn
= emit_call_insn (gen_sibcall (funexp
));
12295 SIBLING_CALL_P (insn
) = 1;
12299 /* The hoops we have to jump through in order to generate a sibcall
12300 without using delay slots... */
12301 rtx spill_reg
, seq
, scratch
= gen_rtx_REG (Pmode
, 1);
12305 spill_reg
= gen_rtx_REG (word_mode
, 15); /* %o7 */
12307 load_got_register (); /* clobbers %o7 */
12308 scratch
= sparc_legitimize_pic_address (funexp
, scratch
);
12309 seq
= get_insns ();
12311 emit_and_preserve (seq
, spill_reg
, pic_offset_table_rtx
);
12313 else if (TARGET_ARCH32
)
12315 emit_insn (gen_rtx_SET (scratch
,
12316 gen_rtx_HIGH (SImode
, funexp
)));
12317 emit_insn (gen_rtx_SET (scratch
,
12318 gen_rtx_LO_SUM (SImode
, scratch
, funexp
)));
12320 else /* TARGET_ARCH64 */
12322 switch (sparc_cmodel
)
12326 /* The destination can serve as a temporary. */
12327 sparc_emit_set_symbolic_const64 (scratch
, funexp
, scratch
);
12332 /* The destination cannot serve as a temporary. */
12333 spill_reg
= gen_rtx_REG (DImode
, 15); /* %o7 */
12335 sparc_emit_set_symbolic_const64 (scratch
, funexp
, spill_reg
);
12336 seq
= get_insns ();
12338 emit_and_preserve (seq
, spill_reg
, 0);
12342 gcc_unreachable ();
12346 emit_jump_insn (gen_indirect_jump (scratch
));
12351 /* Run just enough of rest_of_compilation to get the insns emitted.
12352 There's not really enough bulk here to make other passes such as
12353 instruction scheduling worth while. Note that use_thunk calls
12354 assemble_start_function and assemble_end_function. */
12355 insn
= get_insns ();
12356 shorten_branches (insn
);
12357 final_start_function (insn
, file
, 1);
12358 final (insn
, file
, 1);
12359 final_end_function ();
12361 reload_completed
= 0;
12362 epilogue_completed
= 0;
12365 /* Return true if sparc_output_mi_thunk would be able to output the
12366 assembler code for the thunk function specified by the arguments
12367 it is passed, and false otherwise. */
12369 sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED
,
12370 HOST_WIDE_INT delta ATTRIBUTE_UNUSED
,
12371 HOST_WIDE_INT vcall_offset
,
12372 const_tree function ATTRIBUTE_UNUSED
)
12374 /* Bound the loop used in the default method above. */
12375 return (vcall_offset
>= -32768 || ! fixed_regs
[5]);
12378 /* How to allocate a 'struct machine_function'. */
12380 static struct machine_function
*
12381 sparc_init_machine_status (void)
12383 return ggc_cleared_alloc
<machine_function
> ();
12386 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
12387 We need to emit DTP-relative relocations. */
12390 sparc_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
12395 fputs ("\t.word\t%r_tls_dtpoff32(", file
);
12398 fputs ("\t.xword\t%r_tls_dtpoff64(", file
);
12401 gcc_unreachable ();
12403 output_addr_const (file
, x
);
12407 /* Do whatever processing is required at the end of a file. */
12410 sparc_file_end (void)
12412 /* If we need to emit the special GOT helper function, do so now. */
12413 if (got_helper_rtx
)
12415 const char *name
= XSTR (got_helper_rtx
, 0);
12416 const char *reg_name
= reg_names
[GLOBAL_OFFSET_TABLE_REGNUM
];
12417 #ifdef DWARF2_UNWIND_INFO
12421 if (USE_HIDDEN_LINKONCE
)
12423 tree decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
12424 get_identifier (name
),
12425 build_function_type_list (void_type_node
,
12427 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
12428 NULL_TREE
, void_type_node
);
12429 TREE_PUBLIC (decl
) = 1;
12430 TREE_STATIC (decl
) = 1;
12431 make_decl_one_only (decl
, DECL_ASSEMBLER_NAME (decl
));
12432 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
12433 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
12434 resolve_unique_section (decl
, 0, flag_function_sections
);
12435 allocate_struct_function (decl
, true);
12436 cfun
->is_thunk
= 1;
12437 current_function_decl
= decl
;
12438 init_varasm_status ();
12439 assemble_start_function (decl
, name
);
12443 const int align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
12444 switch_to_section (text_section
);
12446 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
12447 ASM_OUTPUT_LABEL (asm_out_file
, name
);
12450 #ifdef DWARF2_UNWIND_INFO
12451 do_cfi
= dwarf2out_do_cfi_asm ();
12453 fprintf (asm_out_file
, "\t.cfi_startproc\n");
12455 if (flag_delayed_branch
)
12456 fprintf (asm_out_file
, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
12457 reg_name
, reg_name
);
12459 fprintf (asm_out_file
, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
12460 reg_name
, reg_name
);
12461 #ifdef DWARF2_UNWIND_INFO
12463 fprintf (asm_out_file
, "\t.cfi_endproc\n");
12467 if (NEED_INDICATE_EXEC_STACK
)
12468 file_end_indicate_exec_stack ();
12470 #ifdef TARGET_SOLARIS
12471 solaris_file_end ();
12475 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
12476 /* Implement TARGET_MANGLE_TYPE. */
12478 static const char *
12479 sparc_mangle_type (const_tree type
)
12482 && TYPE_MAIN_VARIANT (type
) == long_double_type_node
12483 && TARGET_LONG_DOUBLE_128
)
12486 /* For all other types, use normal C++ mangling. */
12491 /* Expand a membar instruction for various use cases. Both the LOAD_STORE
12492 and BEFORE_AFTER arguments of the form X_Y. They are two-bit masks where
12493 bit 0 indicates that X is true, and bit 1 indicates Y is true. */
12496 sparc_emit_membar_for_model (enum memmodel model
,
12497 int load_store
, int before_after
)
12499 /* Bits for the MEMBAR mmask field. */
12500 const int LoadLoad
= 1;
12501 const int StoreLoad
= 2;
12502 const int LoadStore
= 4;
12503 const int StoreStore
= 8;
12505 int mm
= 0, implied
= 0;
12507 switch (sparc_memory_model
)
12510 /* Sequential Consistency. All memory transactions are immediately
12511 visible in sequential execution order. No barriers needed. */
12512 implied
= LoadLoad
| StoreLoad
| LoadStore
| StoreStore
;
12516 /* Total Store Ordering: all memory transactions with store semantics
12517 are followed by an implied StoreStore. */
12518 implied
|= StoreStore
;
12520 /* If we're not looking for a raw barrer (before+after), then atomic
12521 operations get the benefit of being both load and store. */
12522 if (load_store
== 3 && before_after
== 1)
12523 implied
|= StoreLoad
;
12527 /* Partial Store Ordering: all memory transactions with load semantics
12528 are followed by an implied LoadLoad | LoadStore. */
12529 implied
|= LoadLoad
| LoadStore
;
12531 /* If we're not looking for a raw barrer (before+after), then atomic
12532 operations get the benefit of being both load and store. */
12533 if (load_store
== 3 && before_after
== 2)
12534 implied
|= StoreLoad
| StoreStore
;
12538 /* Relaxed Memory Ordering: no implicit bits. */
12542 gcc_unreachable ();
12545 if (before_after
& 1)
12547 if (is_mm_release (model
) || is_mm_acq_rel (model
)
12548 || is_mm_seq_cst (model
))
12550 if (load_store
& 1)
12551 mm
|= LoadLoad
| StoreLoad
;
12552 if (load_store
& 2)
12553 mm
|= LoadStore
| StoreStore
;
12556 if (before_after
& 2)
12558 if (is_mm_acquire (model
) || is_mm_acq_rel (model
)
12559 || is_mm_seq_cst (model
))
12561 if (load_store
& 1)
12562 mm
|= LoadLoad
| LoadStore
;
12563 if (load_store
& 2)
12564 mm
|= StoreLoad
| StoreStore
;
12568 /* Remove the bits implied by the system memory model. */
12571 /* For raw barriers (before+after), always emit a barrier.
12572 This will become a compile-time barrier if needed. */
12573 if (mm
|| before_after
== 3)
12574 emit_insn (gen_membar (GEN_INT (mm
)));
12577 /* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit
12578 compare and swap on the word containing the byte or half-word. */
12581 sparc_expand_compare_and_swap_12 (rtx bool_result
, rtx result
, rtx mem
,
12582 rtx oldval
, rtx newval
)
12584 rtx addr1
= force_reg (Pmode
, XEXP (mem
, 0));
12585 rtx addr
= gen_reg_rtx (Pmode
);
12586 rtx off
= gen_reg_rtx (SImode
);
12587 rtx oldv
= gen_reg_rtx (SImode
);
12588 rtx newv
= gen_reg_rtx (SImode
);
12589 rtx oldvalue
= gen_reg_rtx (SImode
);
12590 rtx newvalue
= gen_reg_rtx (SImode
);
12591 rtx res
= gen_reg_rtx (SImode
);
12592 rtx resv
= gen_reg_rtx (SImode
);
12593 rtx memsi
, val
, mask
, cc
;
12595 emit_insn (gen_rtx_SET (addr
, gen_rtx_AND (Pmode
, addr1
, GEN_INT (-4))));
12597 if (Pmode
!= SImode
)
12598 addr1
= gen_lowpart (SImode
, addr1
);
12599 emit_insn (gen_rtx_SET (off
, gen_rtx_AND (SImode
, addr1
, GEN_INT (3))));
12601 memsi
= gen_rtx_MEM (SImode
, addr
);
12602 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
12603 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
12605 val
= copy_to_reg (memsi
);
12607 emit_insn (gen_rtx_SET (off
,
12608 gen_rtx_XOR (SImode
, off
,
12609 GEN_INT (GET_MODE (mem
) == QImode
12612 emit_insn (gen_rtx_SET (off
, gen_rtx_ASHIFT (SImode
, off
, GEN_INT (3))));
12614 if (GET_MODE (mem
) == QImode
)
12615 mask
= force_reg (SImode
, GEN_INT (0xff));
12617 mask
= force_reg (SImode
, GEN_INT (0xffff));
12619 emit_insn (gen_rtx_SET (mask
, gen_rtx_ASHIFT (SImode
, mask
, off
)));
12621 emit_insn (gen_rtx_SET (val
,
12622 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
12625 oldval
= gen_lowpart (SImode
, oldval
);
12626 emit_insn (gen_rtx_SET (oldv
, gen_rtx_ASHIFT (SImode
, oldval
, off
)));
12628 newval
= gen_lowpart_common (SImode
, newval
);
12629 emit_insn (gen_rtx_SET (newv
, gen_rtx_ASHIFT (SImode
, newval
, off
)));
12631 emit_insn (gen_rtx_SET (oldv
, gen_rtx_AND (SImode
, oldv
, mask
)));
12633 emit_insn (gen_rtx_SET (newv
, gen_rtx_AND (SImode
, newv
, mask
)));
12635 rtx_code_label
*end_label
= gen_label_rtx ();
12636 rtx_code_label
*loop_label
= gen_label_rtx ();
12637 emit_label (loop_label
);
12639 emit_insn (gen_rtx_SET (oldvalue
, gen_rtx_IOR (SImode
, oldv
, val
)));
12641 emit_insn (gen_rtx_SET (newvalue
, gen_rtx_IOR (SImode
, newv
, val
)));
12643 emit_move_insn (bool_result
, const1_rtx
);
12645 emit_insn (gen_atomic_compare_and_swapsi_1 (res
, memsi
, oldvalue
, newvalue
));
12647 emit_cmp_and_jump_insns (res
, oldvalue
, EQ
, NULL
, SImode
, 0, end_label
);
12649 emit_insn (gen_rtx_SET (resv
,
12650 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
12653 emit_move_insn (bool_result
, const0_rtx
);
12655 cc
= gen_compare_reg_1 (NE
, resv
, val
);
12656 emit_insn (gen_rtx_SET (val
, resv
));
12658 /* Use cbranchcc4 to separate the compare and branch! */
12659 emit_jump_insn (gen_cbranchcc4 (gen_rtx_NE (VOIDmode
, cc
, const0_rtx
),
12660 cc
, const0_rtx
, loop_label
));
12662 emit_label (end_label
);
12664 emit_insn (gen_rtx_SET (res
, gen_rtx_AND (SImode
, res
, mask
)));
12666 emit_insn (gen_rtx_SET (res
, gen_rtx_LSHIFTRT (SImode
, res
, off
)));
12668 emit_move_insn (result
, gen_lowpart (GET_MODE (result
), res
));
12671 /* Expand code to perform a compare-and-swap. */
12674 sparc_expand_compare_and_swap (rtx operands
[])
12676 rtx bval
, retval
, mem
, oldval
, newval
;
12678 enum memmodel model
;
12680 bval
= operands
[0];
12681 retval
= operands
[1];
12683 oldval
= operands
[3];
12684 newval
= operands
[4];
12685 model
= (enum memmodel
) INTVAL (operands
[6]);
12686 mode
= GET_MODE (mem
);
12688 sparc_emit_membar_for_model (model
, 3, 1);
12690 if (reg_overlap_mentioned_p (retval
, oldval
))
12691 oldval
= copy_to_reg (oldval
);
12693 if (mode
== QImode
|| mode
== HImode
)
12694 sparc_expand_compare_and_swap_12 (bval
, retval
, mem
, oldval
, newval
);
12697 rtx (*gen
) (rtx
, rtx
, rtx
, rtx
);
12700 if (mode
== SImode
)
12701 gen
= gen_atomic_compare_and_swapsi_1
;
12703 gen
= gen_atomic_compare_and_swapdi_1
;
12704 emit_insn (gen (retval
, mem
, oldval
, newval
));
12706 x
= emit_store_flag (bval
, EQ
, retval
, oldval
, mode
, 1, 1);
12708 convert_move (bval
, x
, 1);
12711 sparc_emit_membar_for_model (model
, 3, 2);
12715 sparc_expand_vec_perm_bmask (machine_mode vmode
, rtx sel
)
12719 sel
= gen_lowpart (DImode
, sel
);
12723 /* inp = xxxxxxxAxxxxxxxB */
12724 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
12725 NULL_RTX
, 1, OPTAB_DIRECT
);
12726 /* t_1 = ....xxxxxxxAxxx. */
12727 sel
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, sel
),
12728 GEN_INT (3), NULL_RTX
, 1, OPTAB_DIRECT
);
12729 t_1
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_1
),
12730 GEN_INT (0x30000), NULL_RTX
, 1, OPTAB_DIRECT
);
12731 /* sel = .......B */
12732 /* t_1 = ...A.... */
12733 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_1
, sel
, 1, OPTAB_DIRECT
);
12734 /* sel = ...A...B */
12735 sel
= expand_mult (SImode
, sel
, GEN_INT (0x4444), sel
, 1);
12736 /* sel = AAAABBBB * 4 */
12737 t_1
= force_reg (SImode
, GEN_INT (0x01230123));
12738 /* sel = { A*4, A*4+1, A*4+2, ... } */
12742 /* inp = xxxAxxxBxxxCxxxD */
12743 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (8),
12744 NULL_RTX
, 1, OPTAB_DIRECT
);
12745 t_2
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
12746 NULL_RTX
, 1, OPTAB_DIRECT
);
12747 t_3
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (24),
12748 NULL_RTX
, 1, OPTAB_DIRECT
);
12749 /* t_1 = ..xxxAxxxBxxxCxx */
12750 /* t_2 = ....xxxAxxxBxxxC */
12751 /* t_3 = ......xxxAxxxBxx */
12752 sel
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, sel
),
12754 NULL_RTX
, 1, OPTAB_DIRECT
);
12755 t_1
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_1
),
12757 NULL_RTX
, 1, OPTAB_DIRECT
);
12758 t_2
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_2
),
12759 GEN_INT (0x070000),
12760 NULL_RTX
, 1, OPTAB_DIRECT
);
12761 t_3
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_3
),
12762 GEN_INT (0x07000000),
12763 NULL_RTX
, 1, OPTAB_DIRECT
);
12764 /* sel = .......D */
12765 /* t_1 = .....C.. */
12766 /* t_2 = ...B.... */
12767 /* t_3 = .A...... */
12768 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_1
, sel
, 1, OPTAB_DIRECT
);
12769 t_2
= expand_simple_binop (SImode
, IOR
, t_2
, t_3
, t_2
, 1, OPTAB_DIRECT
);
12770 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_2
, sel
, 1, OPTAB_DIRECT
);
12771 /* sel = .A.B.C.D */
12772 sel
= expand_mult (SImode
, sel
, GEN_INT (0x22), sel
, 1);
12773 /* sel = AABBCCDD * 2 */
12774 t_1
= force_reg (SImode
, GEN_INT (0x01010101));
12775 /* sel = { A*2, A*2+1, B*2, B*2+1, ... } */
12779 /* input = xAxBxCxDxExFxGxH */
12780 sel
= expand_simple_binop (DImode
, AND
, sel
,
12781 GEN_INT ((HOST_WIDE_INT
)0x0f0f0f0f << 32
12783 NULL_RTX
, 1, OPTAB_DIRECT
);
12784 /* sel = .A.B.C.D.E.F.G.H */
12785 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (4),
12786 NULL_RTX
, 1, OPTAB_DIRECT
);
12787 /* t_1 = ..A.B.C.D.E.F.G. */
12788 sel
= expand_simple_binop (DImode
, IOR
, sel
, t_1
,
12789 NULL_RTX
, 1, OPTAB_DIRECT
);
12790 /* sel = .AABBCCDDEEFFGGH */
12791 sel
= expand_simple_binop (DImode
, AND
, sel
,
12792 GEN_INT ((HOST_WIDE_INT
)0xff00ff << 32
12794 NULL_RTX
, 1, OPTAB_DIRECT
);
12795 /* sel = ..AB..CD..EF..GH */
12796 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (8),
12797 NULL_RTX
, 1, OPTAB_DIRECT
);
12798 /* t_1 = ....AB..CD..EF.. */
12799 sel
= expand_simple_binop (DImode
, IOR
, sel
, t_1
,
12800 NULL_RTX
, 1, OPTAB_DIRECT
);
12801 /* sel = ..ABABCDCDEFEFGH */
12802 sel
= expand_simple_binop (DImode
, AND
, sel
,
12803 GEN_INT ((HOST_WIDE_INT
)0xffff << 32 | 0xffff),
12804 NULL_RTX
, 1, OPTAB_DIRECT
);
12805 /* sel = ....ABCD....EFGH */
12806 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
12807 NULL_RTX
, 1, OPTAB_DIRECT
);
12808 /* t_1 = ........ABCD.... */
12809 sel
= gen_lowpart (SImode
, sel
);
12810 t_1
= gen_lowpart (SImode
, t_1
);
12814 gcc_unreachable ();
12817 /* Always perform the final addition/merge within the bmask insn. */
12818 emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode
), sel
, t_1
));
12821 /* Implement TARGET_VEC_PERM_CONST. */
12824 sparc_vectorize_vec_perm_const (machine_mode vmode
, rtx target
, rtx op0
,
12825 rtx op1
, const vec_perm_indices
&sel
)
12827 /* All permutes are supported. */
12831 /* Force target-independent code to convert constant permutations on other
12832 modes down to V8QI. Rely on this to avoid the complexity of the byte
12833 order of the permutation. */
12834 if (vmode
!= V8QImode
)
12837 unsigned int i
, mask
;
12838 for (i
= mask
= 0; i
< 8; ++i
)
12839 mask
|= (sel
[i
] & 0xf) << (28 - i
*4);
12840 rtx mask_rtx
= force_reg (SImode
, gen_int_mode (mask
, SImode
));
12842 emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode
), mask_rtx
, const0_rtx
));
12843 emit_insn (gen_bshufflev8qi_vis (target
, op0
, op1
));
12847 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
12850 sparc_frame_pointer_required (void)
12852 /* If the stack pointer is dynamically modified in the function, it cannot
12853 serve as the frame pointer. */
12854 if (cfun
->calls_alloca
)
12857 /* If the function receives nonlocal gotos, it needs to save the frame
12858 pointer in the nonlocal_goto_save_area object. */
12859 if (cfun
->has_nonlocal_label
)
12862 /* In flat mode, that's it. */
12866 /* Otherwise, the frame pointer is required if the function isn't leaf, but
12867 we cannot use sparc_leaf_function_p since it hasn't been computed yet. */
12868 return !(optimize
> 0 && crtl
->is_leaf
&& only_leaf_regs_used ());
12871 /* The way this is structured, we can't eliminate SFP in favor of SP
12872 if the frame pointer is required: we want to use the SFP->HFP elimination
12873 in that case. But the test in update_eliminables doesn't know we are
12874 assuming below that we only do the former elimination. */
12877 sparc_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
12879 return to
== HARD_FRAME_POINTER_REGNUM
|| !sparc_frame_pointer_required ();
12882 /* Return the hard frame pointer directly to bypass the stack bias. */
12885 sparc_builtin_setjmp_frame_value (void)
12887 return hard_frame_pointer_rtx
;
12890 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
12891 they won't be allocated. */
12894 sparc_conditional_register_usage (void)
12896 if (PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
12898 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
12899 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
12901 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */
12902 /* then honor it. */
12903 if (TARGET_ARCH32
&& fixed_regs
[5])
12905 else if (TARGET_ARCH64
&& fixed_regs
[5] == 2)
12910 for (regno
= SPARC_FIRST_V9_FP_REG
;
12911 regno
<= SPARC_LAST_V9_FP_REG
;
12913 fixed_regs
[regno
] = 1;
12914 /* %fcc0 is used by v8 and v9. */
12915 for (regno
= SPARC_FIRST_V9_FCC_REG
+ 1;
12916 regno
<= SPARC_LAST_V9_FCC_REG
;
12918 fixed_regs
[regno
] = 1;
12923 for (regno
= 32; regno
< SPARC_LAST_V9_FCC_REG
; regno
++)
12924 fixed_regs
[regno
] = 1;
12926 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */
12927 /* then honor it. Likewise with g3 and g4. */
12928 if (fixed_regs
[2] == 2)
12929 fixed_regs
[2] = ! TARGET_APP_REGS
;
12930 if (fixed_regs
[3] == 2)
12931 fixed_regs
[3] = ! TARGET_APP_REGS
;
12932 if (TARGET_ARCH32
&& fixed_regs
[4] == 2)
12933 fixed_regs
[4] = ! TARGET_APP_REGS
;
12934 else if (TARGET_CM_EMBMEDANY
)
12936 else if (fixed_regs
[4] == 2)
12941 /* Disable leaf functions. */
12942 memset (sparc_leaf_regs
, 0, FIRST_PSEUDO_REGISTER
);
12943 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
12944 leaf_reg_remap
[regno
] = regno
;
12947 global_regs
[SPARC_GSR_REG
] = 1;
12950 /* Implement TARGET_PREFERRED_RELOAD_CLASS:
12952 - We can't load constants into FP registers.
12953 - We can't load FP constants into integer registers when soft-float,
12954 because there is no soft-float pattern with a r/F constraint.
12955 - We can't load FP constants into integer registers for TFmode unless
12956 it is 0.0L, because there is no movtf pattern with a r/F constraint.
12957 - Try and reload integer constants (symbolic or otherwise) back into
12958 registers directly, rather than having them dumped to memory. */
12961 sparc_preferred_reload_class (rtx x
, reg_class_t rclass
)
12963 machine_mode mode
= GET_MODE (x
);
12964 if (CONSTANT_P (x
))
12966 if (FP_REG_CLASS_P (rclass
)
12967 || rclass
== GENERAL_OR_FP_REGS
12968 || rclass
== GENERAL_OR_EXTRA_FP_REGS
12969 || (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& ! TARGET_FPU
)
12970 || (mode
== TFmode
&& ! const_zero_operand (x
, mode
)))
12973 if (GET_MODE_CLASS (mode
) == MODE_INT
)
12974 return GENERAL_REGS
;
12976 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
12978 if (! FP_REG_CLASS_P (rclass
)
12979 || !(const_zero_operand (x
, mode
)
12980 || const_all_ones_operand (x
, mode
)))
12987 && (rclass
== EXTRA_FP_REGS
12988 || rclass
== GENERAL_OR_EXTRA_FP_REGS
))
12990 int regno
= true_regnum (x
);
12992 if (SPARC_INT_REG_P (regno
))
12993 return (rclass
== EXTRA_FP_REGS
12994 ? FP_REGS
: GENERAL_OR_FP_REGS
);
13000 /* Return true if we use LRA instead of reload pass. */
13008 /* Output a wide multiply instruction in V8+ mode. INSN is the instruction,
13009 OPERANDS are its operands and OPCODE is the mnemonic to be used. */
13012 output_v8plus_mult (rtx_insn
*insn
, rtx
*operands
, const char *opcode
)
13016 gcc_assert (! TARGET_ARCH64
);
13018 if (sparc_check_64 (operands
[1], insn
) <= 0)
13019 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
13020 if (which_alternative
== 1)
13021 output_asm_insn ("sllx\t%H1, 32, %H1", operands
);
13022 if (GET_CODE (operands
[2]) == CONST_INT
)
13024 if (which_alternative
== 1)
13026 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
13027 sprintf (mulstr
, "%s\t%%H1, %%2, %%L0", opcode
);
13028 output_asm_insn (mulstr
, operands
);
13029 return "srlx\t%L0, 32, %H0";
13033 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
13034 output_asm_insn ("or\t%L1, %3, %3", operands
);
13035 sprintf (mulstr
, "%s\t%%3, %%2, %%3", opcode
);
13036 output_asm_insn (mulstr
, operands
);
13037 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
13038 return "mov\t%3, %L0";
13041 else if (rtx_equal_p (operands
[1], operands
[2]))
13043 if (which_alternative
== 1)
13045 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
13046 sprintf (mulstr
, "%s\t%%H1, %%H1, %%L0", opcode
);
13047 output_asm_insn (mulstr
, operands
);
13048 return "srlx\t%L0, 32, %H0";
13052 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
13053 output_asm_insn ("or\t%L1, %3, %3", operands
);
13054 sprintf (mulstr
, "%s\t%%3, %%3, %%3", opcode
);
13055 output_asm_insn (mulstr
, operands
);
13056 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
13057 return "mov\t%3, %L0";
13060 if (sparc_check_64 (operands
[2], insn
) <= 0)
13061 output_asm_insn ("srl\t%L2, 0, %L2", operands
);
13062 if (which_alternative
== 1)
13064 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
13065 output_asm_insn ("sllx\t%H2, 32, %L1", operands
);
13066 output_asm_insn ("or\t%L2, %L1, %L1", operands
);
13067 sprintf (mulstr
, "%s\t%%H1, %%L1, %%L0", opcode
);
13068 output_asm_insn (mulstr
, operands
);
13069 return "srlx\t%L0, 32, %H0";
13073 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
13074 output_asm_insn ("sllx\t%H2, 32, %4", operands
);
13075 output_asm_insn ("or\t%L1, %3, %3", operands
);
13076 output_asm_insn ("or\t%L2, %4, %4", operands
);
13077 sprintf (mulstr
, "%s\t%%3, %%4, %%3", opcode
);
13078 output_asm_insn (mulstr
, operands
);
13079 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
13080 return "mov\t%3, %L0";
13084 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
13085 all fields of TARGET to ELT by means of VIS2 BSHUFFLE insn. MODE
13086 and INNER_MODE are the modes describing TARGET. */
13089 vector_init_bshuffle (rtx target
, rtx elt
, machine_mode mode
,
13090 machine_mode inner_mode
)
13092 rtx t1
, final_insn
, sel
;
13095 t1
= gen_reg_rtx (mode
);
13097 elt
= convert_modes (SImode
, inner_mode
, elt
, true);
13098 emit_move_insn (gen_lowpart(SImode
, t1
), elt
);
13103 final_insn
= gen_bshufflev2si_vis (target
, t1
, t1
);
13104 bmask
= 0x45674567;
13107 final_insn
= gen_bshufflev4hi_vis (target
, t1
, t1
);
13108 bmask
= 0x67676767;
13111 final_insn
= gen_bshufflev8qi_vis (target
, t1
, t1
);
13112 bmask
= 0x77777777;
13115 gcc_unreachable ();
13118 sel
= force_reg (SImode
, GEN_INT (bmask
));
13119 emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode
), sel
, const0_rtx
));
13120 emit_insn (final_insn
);
13123 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
13124 all fields of TARGET to ELT in V8QI by means of VIS FPMERGE insn. */
13127 vector_init_fpmerge (rtx target
, rtx elt
)
13129 rtx t1
, t2
, t2_low
, t3
, t3_low
;
13131 t1
= gen_reg_rtx (V4QImode
);
13132 elt
= convert_modes (SImode
, QImode
, elt
, true);
13133 emit_move_insn (gen_lowpart (SImode
, t1
), elt
);
13135 t2
= gen_reg_rtx (V8QImode
);
13136 t2_low
= gen_lowpart (V4QImode
, t2
);
13137 emit_insn (gen_fpmerge_vis (t2
, t1
, t1
));
13139 t3
= gen_reg_rtx (V8QImode
);
13140 t3_low
= gen_lowpart (V4QImode
, t3
);
13141 emit_insn (gen_fpmerge_vis (t3
, t2_low
, t2_low
));
13143 emit_insn (gen_fpmerge_vis (target
, t3_low
, t3_low
));
13146 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
13147 all fields of TARGET to ELT in V4HI by means of VIS FALIGNDATA insn. */
13150 vector_init_faligndata (rtx target
, rtx elt
)
13152 rtx t1
= gen_reg_rtx (V4HImode
);
13155 elt
= convert_modes (SImode
, HImode
, elt
, true);
13156 emit_move_insn (gen_lowpart (SImode
, t1
), elt
);
13158 emit_insn (gen_alignaddrsi_vis (gen_reg_rtx (SImode
),
13159 force_reg (SImode
, GEN_INT (6)),
13162 for (i
= 0; i
< 4; i
++)
13163 emit_insn (gen_faligndatav4hi_vis (target
, t1
, target
));
13166 /* Emit code to initialize TARGET to values for individual fields VALS. */
13169 sparc_expand_vector_init (rtx target
, rtx vals
)
13171 const machine_mode mode
= GET_MODE (target
);
13172 const machine_mode inner_mode
= GET_MODE_INNER (mode
);
13173 const int n_elts
= GET_MODE_NUNITS (mode
);
13175 bool all_same
= true;
13178 for (i
= 0; i
< n_elts
; i
++)
13180 rtx x
= XVECEXP (vals
, 0, i
);
13181 if (!(CONST_SCALAR_INT_P (x
) || CONST_DOUBLE_P (x
) || CONST_FIXED_P (x
)))
13184 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
13190 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
13194 if (GET_MODE_SIZE (inner_mode
) == GET_MODE_SIZE (mode
))
13196 if (GET_MODE_SIZE (inner_mode
) == 4)
13198 emit_move_insn (gen_lowpart (SImode
, target
),
13199 gen_lowpart (SImode
, XVECEXP (vals
, 0, 0)));
13202 else if (GET_MODE_SIZE (inner_mode
) == 8)
13204 emit_move_insn (gen_lowpart (DImode
, target
),
13205 gen_lowpart (DImode
, XVECEXP (vals
, 0, 0)));
13209 else if (GET_MODE_SIZE (inner_mode
) == GET_MODE_SIZE (word_mode
)
13210 && GET_MODE_SIZE (mode
) == 2 * GET_MODE_SIZE (word_mode
))
13212 emit_move_insn (gen_highpart (word_mode
, target
),
13213 gen_lowpart (word_mode
, XVECEXP (vals
, 0, 0)));
13214 emit_move_insn (gen_lowpart (word_mode
, target
),
13215 gen_lowpart (word_mode
, XVECEXP (vals
, 0, 1)));
13219 if (all_same
&& GET_MODE_SIZE (mode
) == 8)
13223 vector_init_bshuffle (target
, XVECEXP (vals
, 0, 0), mode
, inner_mode
);
13226 if (mode
== V8QImode
)
13228 vector_init_fpmerge (target
, XVECEXP (vals
, 0, 0));
13231 if (mode
== V4HImode
)
13233 vector_init_faligndata (target
, XVECEXP (vals
, 0, 0));
13238 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
13239 for (i
= 0; i
< n_elts
; i
++)
13240 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
13241 i
* GET_MODE_SIZE (inner_mode
)),
13242 XVECEXP (vals
, 0, i
));
13243 emit_move_insn (target
, mem
);
13246 /* Implement TARGET_SECONDARY_RELOAD. */
13249 sparc_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
13250 machine_mode mode
, secondary_reload_info
*sri
)
13252 enum reg_class rclass
= (enum reg_class
) rclass_i
;
13254 sri
->icode
= CODE_FOR_nothing
;
13255 sri
->extra_cost
= 0;
13257 /* We need a temporary when loading/storing a HImode/QImode value
13258 between memory and the FPU registers. This can happen when combine puts
13259 a paradoxical subreg in a float/fix conversion insn. */
13260 if (FP_REG_CLASS_P (rclass
)
13261 && (mode
== HImode
|| mode
== QImode
)
13262 && (GET_CODE (x
) == MEM
13263 || ((GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
13264 && true_regnum (x
) == -1)))
13265 return GENERAL_REGS
;
13267 /* On 32-bit we need a temporary when loading/storing a DFmode value
13268 between unaligned memory and the upper FPU registers. */
13270 && rclass
== EXTRA_FP_REGS
13272 && GET_CODE (x
) == MEM
13273 && ! mem_min_alignment (x
, 8))
13276 if (((TARGET_CM_MEDANY
13277 && symbolic_operand (x
, mode
))
13278 || (TARGET_CM_EMBMEDANY
13279 && text_segment_operand (x
, mode
)))
13283 sri
->icode
= direct_optab_handler (reload_in_optab
, mode
);
13285 sri
->icode
= direct_optab_handler (reload_out_optab
, mode
);
13289 if (TARGET_VIS3
&& TARGET_ARCH32
)
13291 int regno
= true_regnum (x
);
13293 /* When using VIS3 fp<-->int register moves, on 32-bit we have
13294 to move 8-byte values in 4-byte pieces. This only works via
13295 FP_REGS, and not via EXTRA_FP_REGS. Therefore if we try to
13296 move between EXTRA_FP_REGS and GENERAL_REGS, we will need
13297 an FP_REGS intermediate move. */
13298 if ((rclass
== EXTRA_FP_REGS
&& SPARC_INT_REG_P (regno
))
13299 || ((general_or_i64_p (rclass
)
13300 || rclass
== GENERAL_OR_FP_REGS
)
13301 && SPARC_FP_REG_P (regno
)))
13303 sri
->extra_cost
= 2;
13311 /* Implement TARGET_SECONDARY_MEMORY_NEEDED.
13313 On SPARC when not VIS3 it is not possible to directly move data
13314 between GENERAL_REGS and FP_REGS. */
13317 sparc_secondary_memory_needed (machine_mode mode
, reg_class_t class1
,
13318 reg_class_t class2
)
13320 return ((FP_REG_CLASS_P (class1
) != FP_REG_CLASS_P (class2
))
13322 || GET_MODE_SIZE (mode
) > 8
13323 || GET_MODE_SIZE (mode
) < 4));
13326 /* Implement TARGET_SECONDARY_MEMORY_NEEDED_MODE.
13328 get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9
13329 because the movsi and movsf patterns don't handle r/f moves.
13330 For v8 we copy the default definition. */
13332 static machine_mode
13333 sparc_secondary_memory_needed_mode (machine_mode mode
)
13337 if (GET_MODE_BITSIZE (mode
) < 32)
13338 return mode_for_size (32, GET_MODE_CLASS (mode
), 0).require ();
13343 if (GET_MODE_BITSIZE (mode
) < BITS_PER_WORD
)
13344 return mode_for_size (BITS_PER_WORD
,
13345 GET_MODE_CLASS (mode
), 0).require ();
13350 /* Emit code to conditionally move either OPERANDS[2] or OPERANDS[3] into
13351 OPERANDS[0] in MODE. OPERANDS[1] is the operator of the condition. */
13354 sparc_expand_conditional_move (machine_mode mode
, rtx
*operands
)
13356 enum rtx_code rc
= GET_CODE (operands
[1]);
13357 machine_mode cmp_mode
;
13358 rtx cc_reg
, dst
, cmp
;
13361 if (GET_MODE (XEXP (cmp
, 0)) == DImode
&& !TARGET_ARCH64
)
13364 if (GET_MODE (XEXP (cmp
, 0)) == TFmode
&& !TARGET_HARD_QUAD
)
13365 cmp
= sparc_emit_float_lib_cmp (XEXP (cmp
, 0), XEXP (cmp
, 1), rc
);
13367 cmp_mode
= GET_MODE (XEXP (cmp
, 0));
13368 rc
= GET_CODE (cmp
);
13371 if (! rtx_equal_p (operands
[2], dst
)
13372 && ! rtx_equal_p (operands
[3], dst
))
13374 if (reg_overlap_mentioned_p (dst
, cmp
))
13375 dst
= gen_reg_rtx (mode
);
13377 emit_move_insn (dst
, operands
[3]);
13379 else if (operands
[2] == dst
)
13381 operands
[2] = operands
[3];
13383 if (GET_MODE_CLASS (cmp_mode
) == MODE_FLOAT
)
13384 rc
= reverse_condition_maybe_unordered (rc
);
13386 rc
= reverse_condition (rc
);
13389 if (XEXP (cmp
, 1) == const0_rtx
13390 && GET_CODE (XEXP (cmp
, 0)) == REG
13391 && cmp_mode
== DImode
13392 && v9_regcmp_p (rc
))
13393 cc_reg
= XEXP (cmp
, 0);
13395 cc_reg
= gen_compare_reg_1 (rc
, XEXP (cmp
, 0), XEXP (cmp
, 1));
13397 cmp
= gen_rtx_fmt_ee (rc
, GET_MODE (cc_reg
), cc_reg
, const0_rtx
);
13399 emit_insn (gen_rtx_SET (dst
,
13400 gen_rtx_IF_THEN_ELSE (mode
, cmp
, operands
[2], dst
)));
13402 if (dst
!= operands
[0])
13403 emit_move_insn (operands
[0], dst
);
13408 /* Emit code to conditionally move a combination of OPERANDS[1] and OPERANDS[2]
13409 into OPERANDS[0] in MODE, depending on the outcome of the comparison of
13410 OPERANDS[4] and OPERANDS[5]. OPERANDS[3] is the operator of the condition.
13411 FCODE is the machine code to be used for OPERANDS[3] and CCODE the machine
13412 code to be used for the condition mask. */
13415 sparc_expand_vcond (machine_mode mode
, rtx
*operands
, int ccode
, int fcode
)
13417 rtx mask
, cop0
, cop1
, fcmp
, cmask
, bshuf
, gsr
;
13418 enum rtx_code code
= GET_CODE (operands
[3]);
13420 mask
= gen_reg_rtx (Pmode
);
13421 cop0
= operands
[4];
13422 cop1
= operands
[5];
13423 if (code
== LT
|| code
== GE
)
13427 code
= swap_condition (code
);
13428 t
= cop0
; cop0
= cop1
; cop1
= t
;
13431 gsr
= gen_rtx_REG (DImode
, SPARC_GSR_REG
);
13433 fcmp
= gen_rtx_UNSPEC (Pmode
,
13434 gen_rtvec (1, gen_rtx_fmt_ee (code
, mode
, cop0
, cop1
)),
13437 cmask
= gen_rtx_UNSPEC (DImode
,
13438 gen_rtvec (2, mask
, gsr
),
13441 bshuf
= gen_rtx_UNSPEC (mode
,
13442 gen_rtvec (3, operands
[1], operands
[2], gsr
),
13445 emit_insn (gen_rtx_SET (mask
, fcmp
));
13446 emit_insn (gen_rtx_SET (gsr
, cmask
));
13448 emit_insn (gen_rtx_SET (operands
[0], bshuf
));
13451 /* On sparc, any mode which naturally allocates into the float
13452 registers should return 4 here. */
13455 sparc_regmode_natural_size (machine_mode mode
)
13457 int size
= UNITS_PER_WORD
;
13461 enum mode_class mclass
= GET_MODE_CLASS (mode
);
13463 if (mclass
== MODE_FLOAT
|| mclass
== MODE_VECTOR_INT
)
13470 /* Implement TARGET_HARD_REGNO_NREGS.
13472 On SPARC, ordinary registers hold 32 bits worth; this means both
13473 integer and floating point registers. On v9, integer regs hold 64
13474 bits worth; floating point regs hold 32 bits worth (this includes the
13475 new fp regs as even the odd ones are included in the hard register
13478 static unsigned int
13479 sparc_hard_regno_nregs (unsigned int regno
, machine_mode mode
)
13481 if (regno
== SPARC_GSR_REG
)
13485 if (SPARC_INT_REG_P (regno
) || regno
== FRAME_POINTER_REGNUM
)
13486 return CEIL (GET_MODE_SIZE (mode
), UNITS_PER_WORD
);
13487 return CEIL (GET_MODE_SIZE (mode
), 4);
13489 return CEIL (GET_MODE_SIZE (mode
), UNITS_PER_WORD
);
13492 /* Implement TARGET_HARD_REGNO_MODE_OK.
13494 ??? Because of the funny way we pass parameters we should allow certain
13495 ??? types of float/complex values to be in integer registers during
13496 ??? RTL generation. This only matters on arch32. */
13499 sparc_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
13501 return (hard_regno_mode_classes
[regno
] & sparc_mode_class
[mode
]) != 0;
13504 /* Implement TARGET_MODES_TIEABLE_P.
13506 For V9 we have to deal with the fact that only the lower 32 floating
13507 point registers are 32-bit addressable. */
13510 sparc_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
13512 enum mode_class mclass1
, mclass2
;
13513 unsigned short size1
, size2
;
13515 if (mode1
== mode2
)
13518 mclass1
= GET_MODE_CLASS (mode1
);
13519 mclass2
= GET_MODE_CLASS (mode2
);
13520 if (mclass1
!= mclass2
)
13526 /* Classes are the same and we are V9 so we have to deal with upper
13527 vs. lower floating point registers. If one of the modes is a
13528 4-byte mode, and the other is not, we have to mark them as not
13529 tieable because only the lower 32 floating point register are
13530 addressable 32-bits at a time.
13532 We can't just test explicitly for SFmode, otherwise we won't
13533 cover the vector mode cases properly. */
13535 if (mclass1
!= MODE_FLOAT
&& mclass1
!= MODE_VECTOR_INT
)
13538 size1
= GET_MODE_SIZE (mode1
);
13539 size2
= GET_MODE_SIZE (mode2
);
13540 if ((size1
> 4 && size2
== 4)
13541 || (size2
> 4 && size1
== 4))
13547 /* Implement TARGET_CSTORE_MODE. */
13549 static scalar_int_mode
13550 sparc_cstore_mode (enum insn_code icode ATTRIBUTE_UNUSED
)
13552 return (TARGET_ARCH64
? DImode
: SImode
);
13555 /* Return the compound expression made of T1 and T2. */
13558 compound_expr (tree t1
, tree t2
)
13560 return build2 (COMPOUND_EXPR
, void_type_node
, t1
, t2
);
13563 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
13566 sparc_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
13571 const unsigned HOST_WIDE_INT accrued_exception_mask
= 0x1f << 5;
13572 const unsigned HOST_WIDE_INT trap_enable_mask
= 0x1f << 23;
13574 /* We generate the equivalent of feholdexcept (&fenv_var):
13576 unsigned int fenv_var;
13577 __builtin_store_fsr (&fenv_var);
13579 unsigned int tmp1_var;
13580 tmp1_var = fenv_var & ~(accrued_exception_mask | trap_enable_mask);
13582 __builtin_load_fsr (&tmp1_var); */
13584 tree fenv_var
= create_tmp_var_raw (unsigned_type_node
);
13585 TREE_ADDRESSABLE (fenv_var
) = 1;
13586 tree fenv_addr
= build_fold_addr_expr (fenv_var
);
13587 tree stfsr
= sparc_builtins
[SPARC_BUILTIN_STFSR
];
13589 = build4 (TARGET_EXPR
, unsigned_type_node
, fenv_var
,
13590 build_call_expr (stfsr
, 1, fenv_addr
), NULL_TREE
, NULL_TREE
);
13592 tree tmp1_var
= create_tmp_var_raw (unsigned_type_node
);
13593 TREE_ADDRESSABLE (tmp1_var
) = 1;
13594 tree masked_fenv_var
13595 = build2 (BIT_AND_EXPR
, unsigned_type_node
, fenv_var
,
13596 build_int_cst (unsigned_type_node
,
13597 ~(accrued_exception_mask
| trap_enable_mask
)));
13599 = build4 (TARGET_EXPR
, unsigned_type_node
, tmp1_var
, masked_fenv_var
,
13600 NULL_TREE
, NULL_TREE
);
13602 tree tmp1_addr
= build_fold_addr_expr (tmp1_var
);
13603 tree ldfsr
= sparc_builtins
[SPARC_BUILTIN_LDFSR
];
13604 tree hold_ldfsr
= build_call_expr (ldfsr
, 1, tmp1_addr
);
13606 *hold
= compound_expr (compound_expr (hold_stfsr
, hold_mask
), hold_ldfsr
);
13608 /* We reload the value of tmp1_var to clear the exceptions:
13610 __builtin_load_fsr (&tmp1_var); */
13612 *clear
= build_call_expr (ldfsr
, 1, tmp1_addr
);
13614 /* We generate the equivalent of feupdateenv (&fenv_var):
13616 unsigned int tmp2_var;
13617 __builtin_store_fsr (&tmp2_var);
13619 __builtin_load_fsr (&fenv_var);
13621 if (SPARC_LOW_FE_EXCEPT_VALUES)
13623 __atomic_feraiseexcept ((int) tmp2_var); */
13625 tree tmp2_var
= create_tmp_var_raw (unsigned_type_node
);
13626 TREE_ADDRESSABLE (tmp2_var
) = 1;
13627 tree tmp2_addr
= build_fold_addr_expr (tmp2_var
);
13629 = build4 (TARGET_EXPR
, unsigned_type_node
, tmp2_var
,
13630 build_call_expr (stfsr
, 1, tmp2_addr
), NULL_TREE
, NULL_TREE
);
13632 tree update_ldfsr
= build_call_expr (ldfsr
, 1, fenv_addr
);
13634 tree atomic_feraiseexcept
13635 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT
);
13637 = build_call_expr (atomic_feraiseexcept
, 1,
13638 fold_convert (integer_type_node
, tmp2_var
));
13640 if (SPARC_LOW_FE_EXCEPT_VALUES
)
13642 tree shifted_tmp2_var
13643 = build2 (RSHIFT_EXPR
, unsigned_type_node
, tmp2_var
,
13644 build_int_cst (unsigned_type_node
, 5));
13646 = build2 (MODIFY_EXPR
, void_type_node
, tmp2_var
, shifted_tmp2_var
);
13647 update_call
= compound_expr (update_shift
, update_call
);
13651 = compound_expr (compound_expr (update_stfsr
, update_ldfsr
), update_call
);
13654 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. Borrowed from the PA port.
13656 SImode loads to floating-point registers are not zero-extended.
13657 The definition for LOAD_EXTEND_OP specifies that integer loads
13658 narrower than BITS_PER_WORD will be zero-extended. As a result,
13659 we inhibit changes from SImode unless they are to a mode that is
13662 Likewise for SFmode, since word-mode paradoxical subregs are
13663 problematic on big-endian architectures. */
13666 sparc_can_change_mode_class (machine_mode from
, machine_mode to
,
13667 reg_class_t rclass
)
13670 && GET_MODE_SIZE (from
) == 4
13671 && GET_MODE_SIZE (to
) != 4)
13672 return !reg_classes_intersect_p (rclass
, FP_REGS
);
13676 /* Implement TARGET_CONSTANT_ALIGNMENT. */
13678 static HOST_WIDE_INT
13679 sparc_constant_alignment (const_tree exp
, HOST_WIDE_INT align
)
13681 if (TREE_CODE (exp
) == STRING_CST
)
13682 return MAX (align
, FASTEST_ALIGNMENT
);
13686 #include "gt-sparc.h"