1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987-2019 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
4 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
23 #define IN_TARGET_CODE 1
27 #include "coretypes.h"
36 #include "stringpool.h"
43 #include "diagnostic-core.h"
45 #include "fold-const.h"
46 #include "stor-layout.h"
50 #include "insn-attr.h"
55 #include "common/common-target.h"
57 #include "langhooks.h"
60 #include "tree-pass.h"
63 #include "tree-vector-builder.h"
65 /* This file should be included last. */
66 #include "target-def.h"
70 struct processor_costs
{
74 /* Integer signed load */
77 /* Integer zeroed load */
83 /* fmov, fneg, fabs */
87 const int float_plusminus
;
93 const int float_cmove
;
99 const int float_div_sf
;
102 const int float_div_df
;
105 const int float_sqrt_sf
;
108 const int float_sqrt_df
;
116 /* integer multiply cost for each bit set past the most
117 significant 3, so the formula for multiply cost becomes:
120 highest_bit = highest_clear_bit(rs1);
122 highest_bit = highest_set_bit(rs1);
125 cost = int_mul{,X} + ((highest_bit - 3) / int_mul_bit_factor);
127 A value of zero indicates that the multiply costs is fixed,
129 const int int_mul_bit_factor
;
140 /* penalty for shifts, due to scheduling rules etc. */
141 const int shift_penalty
;
143 /* cost of a (predictable) branch. */
144 const int branch_cost
;
148 struct processor_costs cypress_costs
= {
149 COSTS_N_INSNS (2), /* int load */
150 COSTS_N_INSNS (2), /* int signed load */
151 COSTS_N_INSNS (2), /* int zeroed load */
152 COSTS_N_INSNS (2), /* float load */
153 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
154 COSTS_N_INSNS (5), /* fadd, fsub */
155 COSTS_N_INSNS (1), /* fcmp */
156 COSTS_N_INSNS (1), /* fmov, fmovr */
157 COSTS_N_INSNS (7), /* fmul */
158 COSTS_N_INSNS (37), /* fdivs */
159 COSTS_N_INSNS (37), /* fdivd */
160 COSTS_N_INSNS (63), /* fsqrts */
161 COSTS_N_INSNS (63), /* fsqrtd */
162 COSTS_N_INSNS (1), /* imul */
163 COSTS_N_INSNS (1), /* imulX */
164 0, /* imul bit factor */
165 COSTS_N_INSNS (1), /* idiv */
166 COSTS_N_INSNS (1), /* idivX */
167 COSTS_N_INSNS (1), /* movcc/movr */
168 0, /* shift penalty */
173 struct processor_costs supersparc_costs
= {
174 COSTS_N_INSNS (1), /* int load */
175 COSTS_N_INSNS (1), /* int signed load */
176 COSTS_N_INSNS (1), /* int zeroed load */
177 COSTS_N_INSNS (0), /* float load */
178 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
179 COSTS_N_INSNS (3), /* fadd, fsub */
180 COSTS_N_INSNS (3), /* fcmp */
181 COSTS_N_INSNS (1), /* fmov, fmovr */
182 COSTS_N_INSNS (3), /* fmul */
183 COSTS_N_INSNS (6), /* fdivs */
184 COSTS_N_INSNS (9), /* fdivd */
185 COSTS_N_INSNS (12), /* fsqrts */
186 COSTS_N_INSNS (12), /* fsqrtd */
187 COSTS_N_INSNS (4), /* imul */
188 COSTS_N_INSNS (4), /* imulX */
189 0, /* imul bit factor */
190 COSTS_N_INSNS (4), /* idiv */
191 COSTS_N_INSNS (4), /* idivX */
192 COSTS_N_INSNS (1), /* movcc/movr */
193 1, /* shift penalty */
198 struct processor_costs hypersparc_costs
= {
199 COSTS_N_INSNS (1), /* int load */
200 COSTS_N_INSNS (1), /* int signed load */
201 COSTS_N_INSNS (1), /* int zeroed load */
202 COSTS_N_INSNS (1), /* float load */
203 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
204 COSTS_N_INSNS (1), /* fadd, fsub */
205 COSTS_N_INSNS (1), /* fcmp */
206 COSTS_N_INSNS (1), /* fmov, fmovr */
207 COSTS_N_INSNS (1), /* fmul */
208 COSTS_N_INSNS (8), /* fdivs */
209 COSTS_N_INSNS (12), /* fdivd */
210 COSTS_N_INSNS (17), /* fsqrts */
211 COSTS_N_INSNS (17), /* fsqrtd */
212 COSTS_N_INSNS (17), /* imul */
213 COSTS_N_INSNS (17), /* imulX */
214 0, /* imul bit factor */
215 COSTS_N_INSNS (17), /* idiv */
216 COSTS_N_INSNS (17), /* idivX */
217 COSTS_N_INSNS (1), /* movcc/movr */
218 0, /* shift penalty */
223 struct processor_costs leon_costs
= {
224 COSTS_N_INSNS (1), /* int load */
225 COSTS_N_INSNS (1), /* int signed load */
226 COSTS_N_INSNS (1), /* int zeroed load */
227 COSTS_N_INSNS (1), /* float load */
228 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
229 COSTS_N_INSNS (1), /* fadd, fsub */
230 COSTS_N_INSNS (1), /* fcmp */
231 COSTS_N_INSNS (1), /* fmov, fmovr */
232 COSTS_N_INSNS (1), /* fmul */
233 COSTS_N_INSNS (15), /* fdivs */
234 COSTS_N_INSNS (15), /* fdivd */
235 COSTS_N_INSNS (23), /* fsqrts */
236 COSTS_N_INSNS (23), /* fsqrtd */
237 COSTS_N_INSNS (5), /* imul */
238 COSTS_N_INSNS (5), /* imulX */
239 0, /* imul bit factor */
240 COSTS_N_INSNS (5), /* idiv */
241 COSTS_N_INSNS (5), /* idivX */
242 COSTS_N_INSNS (1), /* movcc/movr */
243 0, /* shift penalty */
248 struct processor_costs leon3_costs
= {
249 COSTS_N_INSNS (1), /* int load */
250 COSTS_N_INSNS (1), /* int signed load */
251 COSTS_N_INSNS (1), /* int zeroed load */
252 COSTS_N_INSNS (1), /* float load */
253 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
254 COSTS_N_INSNS (1), /* fadd, fsub */
255 COSTS_N_INSNS (1), /* fcmp */
256 COSTS_N_INSNS (1), /* fmov, fmovr */
257 COSTS_N_INSNS (1), /* fmul */
258 COSTS_N_INSNS (14), /* fdivs */
259 COSTS_N_INSNS (15), /* fdivd */
260 COSTS_N_INSNS (22), /* fsqrts */
261 COSTS_N_INSNS (23), /* fsqrtd */
262 COSTS_N_INSNS (5), /* imul */
263 COSTS_N_INSNS (5), /* imulX */
264 0, /* imul bit factor */
265 COSTS_N_INSNS (35), /* idiv */
266 COSTS_N_INSNS (35), /* idivX */
267 COSTS_N_INSNS (1), /* movcc/movr */
268 0, /* shift penalty */
273 struct processor_costs sparclet_costs
= {
274 COSTS_N_INSNS (3), /* int load */
275 COSTS_N_INSNS (3), /* int signed load */
276 COSTS_N_INSNS (1), /* int zeroed load */
277 COSTS_N_INSNS (1), /* float load */
278 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
279 COSTS_N_INSNS (1), /* fadd, fsub */
280 COSTS_N_INSNS (1), /* fcmp */
281 COSTS_N_INSNS (1), /* fmov, fmovr */
282 COSTS_N_INSNS (1), /* fmul */
283 COSTS_N_INSNS (1), /* fdivs */
284 COSTS_N_INSNS (1), /* fdivd */
285 COSTS_N_INSNS (1), /* fsqrts */
286 COSTS_N_INSNS (1), /* fsqrtd */
287 COSTS_N_INSNS (5), /* imul */
288 COSTS_N_INSNS (5), /* imulX */
289 0, /* imul bit factor */
290 COSTS_N_INSNS (5), /* idiv */
291 COSTS_N_INSNS (5), /* idivX */
292 COSTS_N_INSNS (1), /* movcc/movr */
293 0, /* shift penalty */
298 struct processor_costs ultrasparc_costs
= {
299 COSTS_N_INSNS (2), /* int load */
300 COSTS_N_INSNS (3), /* int signed load */
301 COSTS_N_INSNS (2), /* int zeroed load */
302 COSTS_N_INSNS (2), /* float load */
303 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
304 COSTS_N_INSNS (4), /* fadd, fsub */
305 COSTS_N_INSNS (1), /* fcmp */
306 COSTS_N_INSNS (2), /* fmov, fmovr */
307 COSTS_N_INSNS (4), /* fmul */
308 COSTS_N_INSNS (13), /* fdivs */
309 COSTS_N_INSNS (23), /* fdivd */
310 COSTS_N_INSNS (13), /* fsqrts */
311 COSTS_N_INSNS (23), /* fsqrtd */
312 COSTS_N_INSNS (4), /* imul */
313 COSTS_N_INSNS (4), /* imulX */
314 2, /* imul bit factor */
315 COSTS_N_INSNS (37), /* idiv */
316 COSTS_N_INSNS (68), /* idivX */
317 COSTS_N_INSNS (2), /* movcc/movr */
318 2, /* shift penalty */
323 struct processor_costs ultrasparc3_costs
= {
324 COSTS_N_INSNS (2), /* int load */
325 COSTS_N_INSNS (3), /* int signed load */
326 COSTS_N_INSNS (3), /* int zeroed load */
327 COSTS_N_INSNS (2), /* float load */
328 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
329 COSTS_N_INSNS (4), /* fadd, fsub */
330 COSTS_N_INSNS (5), /* fcmp */
331 COSTS_N_INSNS (3), /* fmov, fmovr */
332 COSTS_N_INSNS (4), /* fmul */
333 COSTS_N_INSNS (17), /* fdivs */
334 COSTS_N_INSNS (20), /* fdivd */
335 COSTS_N_INSNS (20), /* fsqrts */
336 COSTS_N_INSNS (29), /* fsqrtd */
337 COSTS_N_INSNS (6), /* imul */
338 COSTS_N_INSNS (6), /* imulX */
339 0, /* imul bit factor */
340 COSTS_N_INSNS (40), /* idiv */
341 COSTS_N_INSNS (71), /* idivX */
342 COSTS_N_INSNS (2), /* movcc/movr */
343 0, /* shift penalty */
348 struct processor_costs niagara_costs
= {
349 COSTS_N_INSNS (3), /* int load */
350 COSTS_N_INSNS (3), /* int signed load */
351 COSTS_N_INSNS (3), /* int zeroed load */
352 COSTS_N_INSNS (9), /* float load */
353 COSTS_N_INSNS (8), /* fmov, fneg, fabs */
354 COSTS_N_INSNS (8), /* fadd, fsub */
355 COSTS_N_INSNS (26), /* fcmp */
356 COSTS_N_INSNS (8), /* fmov, fmovr */
357 COSTS_N_INSNS (29), /* fmul */
358 COSTS_N_INSNS (54), /* fdivs */
359 COSTS_N_INSNS (83), /* fdivd */
360 COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */
361 COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */
362 COSTS_N_INSNS (11), /* imul */
363 COSTS_N_INSNS (11), /* imulX */
364 0, /* imul bit factor */
365 COSTS_N_INSNS (72), /* idiv */
366 COSTS_N_INSNS (72), /* idivX */
367 COSTS_N_INSNS (1), /* movcc/movr */
368 0, /* shift penalty */
373 struct processor_costs niagara2_costs
= {
374 COSTS_N_INSNS (3), /* int load */
375 COSTS_N_INSNS (3), /* int signed load */
376 COSTS_N_INSNS (3), /* int zeroed load */
377 COSTS_N_INSNS (3), /* float load */
378 COSTS_N_INSNS (6), /* fmov, fneg, fabs */
379 COSTS_N_INSNS (6), /* fadd, fsub */
380 COSTS_N_INSNS (6), /* fcmp */
381 COSTS_N_INSNS (6), /* fmov, fmovr */
382 COSTS_N_INSNS (6), /* fmul */
383 COSTS_N_INSNS (19), /* fdivs */
384 COSTS_N_INSNS (33), /* fdivd */
385 COSTS_N_INSNS (19), /* fsqrts */
386 COSTS_N_INSNS (33), /* fsqrtd */
387 COSTS_N_INSNS (5), /* imul */
388 COSTS_N_INSNS (5), /* imulX */
389 0, /* imul bit factor */
390 COSTS_N_INSNS (26), /* idiv, average of 12 - 41 cycle range */
391 COSTS_N_INSNS (26), /* idivX, average of 12 - 41 cycle range */
392 COSTS_N_INSNS (1), /* movcc/movr */
393 0, /* shift penalty */
398 struct processor_costs niagara3_costs
= {
399 COSTS_N_INSNS (3), /* int load */
400 COSTS_N_INSNS (3), /* int signed load */
401 COSTS_N_INSNS (3), /* int zeroed load */
402 COSTS_N_INSNS (3), /* float load */
403 COSTS_N_INSNS (9), /* fmov, fneg, fabs */
404 COSTS_N_INSNS (9), /* fadd, fsub */
405 COSTS_N_INSNS (9), /* fcmp */
406 COSTS_N_INSNS (9), /* fmov, fmovr */
407 COSTS_N_INSNS (9), /* fmul */
408 COSTS_N_INSNS (23), /* fdivs */
409 COSTS_N_INSNS (37), /* fdivd */
410 COSTS_N_INSNS (23), /* fsqrts */
411 COSTS_N_INSNS (37), /* fsqrtd */
412 COSTS_N_INSNS (9), /* imul */
413 COSTS_N_INSNS (9), /* imulX */
414 0, /* imul bit factor */
415 COSTS_N_INSNS (31), /* idiv, average of 17 - 45 cycle range */
416 COSTS_N_INSNS (30), /* idivX, average of 16 - 44 cycle range */
417 COSTS_N_INSNS (1), /* movcc/movr */
418 0, /* shift penalty */
423 struct processor_costs niagara4_costs
= {
424 COSTS_N_INSNS (5), /* int load */
425 COSTS_N_INSNS (5), /* int signed load */
426 COSTS_N_INSNS (5), /* int zeroed load */
427 COSTS_N_INSNS (5), /* float load */
428 COSTS_N_INSNS (11), /* fmov, fneg, fabs */
429 COSTS_N_INSNS (11), /* fadd, fsub */
430 COSTS_N_INSNS (11), /* fcmp */
431 COSTS_N_INSNS (11), /* fmov, fmovr */
432 COSTS_N_INSNS (11), /* fmul */
433 COSTS_N_INSNS (24), /* fdivs */
434 COSTS_N_INSNS (37), /* fdivd */
435 COSTS_N_INSNS (24), /* fsqrts */
436 COSTS_N_INSNS (37), /* fsqrtd */
437 COSTS_N_INSNS (12), /* imul */
438 COSTS_N_INSNS (12), /* imulX */
439 0, /* imul bit factor */
440 COSTS_N_INSNS (50), /* idiv, average of 41 - 60 cycle range */
441 COSTS_N_INSNS (35), /* idivX, average of 26 - 44 cycle range */
442 COSTS_N_INSNS (1), /* movcc/movr */
443 0, /* shift penalty */
448 struct processor_costs niagara7_costs
= {
449 COSTS_N_INSNS (5), /* int load */
450 COSTS_N_INSNS (5), /* int signed load */
451 COSTS_N_INSNS (5), /* int zeroed load */
452 COSTS_N_INSNS (5), /* float load */
453 COSTS_N_INSNS (11), /* fmov, fneg, fabs */
454 COSTS_N_INSNS (11), /* fadd, fsub */
455 COSTS_N_INSNS (11), /* fcmp */
456 COSTS_N_INSNS (11), /* fmov, fmovr */
457 COSTS_N_INSNS (11), /* fmul */
458 COSTS_N_INSNS (24), /* fdivs */
459 COSTS_N_INSNS (37), /* fdivd */
460 COSTS_N_INSNS (24), /* fsqrts */
461 COSTS_N_INSNS (37), /* fsqrtd */
462 COSTS_N_INSNS (12), /* imul */
463 COSTS_N_INSNS (12), /* imulX */
464 0, /* imul bit factor */
465 COSTS_N_INSNS (51), /* idiv, average of 42 - 61 cycle range */
466 COSTS_N_INSNS (35), /* idivX, average of 26 - 44 cycle range */
467 COSTS_N_INSNS (1), /* movcc/movr */
468 0, /* shift penalty */
473 struct processor_costs m8_costs
= {
474 COSTS_N_INSNS (3), /* int load */
475 COSTS_N_INSNS (3), /* int signed load */
476 COSTS_N_INSNS (3), /* int zeroed load */
477 COSTS_N_INSNS (3), /* float load */
478 COSTS_N_INSNS (9), /* fmov, fneg, fabs */
479 COSTS_N_INSNS (9), /* fadd, fsub */
480 COSTS_N_INSNS (9), /* fcmp */
481 COSTS_N_INSNS (9), /* fmov, fmovr */
482 COSTS_N_INSNS (9), /* fmul */
483 COSTS_N_INSNS (26), /* fdivs */
484 COSTS_N_INSNS (30), /* fdivd */
485 COSTS_N_INSNS (33), /* fsqrts */
486 COSTS_N_INSNS (41), /* fsqrtd */
487 COSTS_N_INSNS (12), /* imul */
488 COSTS_N_INSNS (10), /* imulX */
489 0, /* imul bit factor */
490 COSTS_N_INSNS (57), /* udiv/sdiv */
491 COSTS_N_INSNS (30), /* udivx/sdivx */
492 COSTS_N_INSNS (1), /* movcc/movr */
493 0, /* shift penalty */
497 static const struct processor_costs
*sparc_costs
= &cypress_costs
;
499 #ifdef HAVE_AS_RELAX_OPTION
500 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
501 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
502 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
503 somebody does not branch between the sethi and jmp. */
504 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
506 #define LEAF_SIBCALL_SLOT_RESERVED_P \
507 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
510 /* Vector to say how input registers are mapped to output registers.
511 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
512 eliminate it. You must use -fomit-frame-pointer to get that. */
513 char leaf_reg_remap
[] =
514 { 0, 1, 2, 3, 4, 5, 6, 7,
515 -1, -1, -1, -1, -1, -1, 14, -1,
516 -1, -1, -1, -1, -1, -1, -1, -1,
517 8, 9, 10, 11, 12, 13, -1, 15,
519 32, 33, 34, 35, 36, 37, 38, 39,
520 40, 41, 42, 43, 44, 45, 46, 47,
521 48, 49, 50, 51, 52, 53, 54, 55,
522 56, 57, 58, 59, 60, 61, 62, 63,
523 64, 65, 66, 67, 68, 69, 70, 71,
524 72, 73, 74, 75, 76, 77, 78, 79,
525 80, 81, 82, 83, 84, 85, 86, 87,
526 88, 89, 90, 91, 92, 93, 94, 95,
527 96, 97, 98, 99, 100, 101, 102};
529 /* Vector, indexed by hard register number, which contains 1
530 for a register that is allowable in a candidate for leaf
531 function treatment. */
532 char sparc_leaf_regs
[] =
533 { 1, 1, 1, 1, 1, 1, 1, 1,
534 0, 0, 0, 0, 0, 0, 1, 0,
535 0, 0, 0, 0, 0, 0, 0, 0,
536 1, 1, 1, 1, 1, 1, 0, 1,
537 1, 1, 1, 1, 1, 1, 1, 1,
538 1, 1, 1, 1, 1, 1, 1, 1,
539 1, 1, 1, 1, 1, 1, 1, 1,
540 1, 1, 1, 1, 1, 1, 1, 1,
541 1, 1, 1, 1, 1, 1, 1, 1,
542 1, 1, 1, 1, 1, 1, 1, 1,
543 1, 1, 1, 1, 1, 1, 1, 1,
544 1, 1, 1, 1, 1, 1, 1, 1,
545 1, 1, 1, 1, 1, 1, 1};
547 struct GTY(()) machine_function
549 /* Size of the frame of the function. */
550 HOST_WIDE_INT frame_size
;
552 /* Size of the frame of the function minus the register window save area
553 and the outgoing argument area. */
554 HOST_WIDE_INT apparent_frame_size
;
556 /* Register we pretend the frame pointer is allocated to. Normally, this
557 is %fp, but if we are in a leaf procedure, this is (%sp + offset). We
558 record "offset" separately as it may be too big for (reg + disp). */
560 HOST_WIDE_INT frame_base_offset
;
562 /* Number of global or FP registers to be saved (as 4-byte quantities). */
563 int n_global_fp_regs
;
565 /* True if the current function is leaf and uses only leaf regs,
566 so that the SPARC leaf function optimization can be applied.
567 Private version of crtl->uses_only_leaf_regs, see
568 sparc_expand_prologue for the rationale. */
571 /* True if the prologue saves local or in registers. */
572 bool save_local_in_regs_p
;
574 /* True if the data calculated by sparc_expand_prologue are valid. */
575 bool prologue_data_valid_p
;
578 #define sparc_frame_size cfun->machine->frame_size
579 #define sparc_apparent_frame_size cfun->machine->apparent_frame_size
580 #define sparc_frame_base_reg cfun->machine->frame_base_reg
581 #define sparc_frame_base_offset cfun->machine->frame_base_offset
582 #define sparc_n_global_fp_regs cfun->machine->n_global_fp_regs
583 #define sparc_leaf_function_p cfun->machine->leaf_function_p
584 #define sparc_save_local_in_regs_p cfun->machine->save_local_in_regs_p
585 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
587 /* 1 if the next opcode is to be specially indented. */
588 int sparc_indent_opcode
= 0;
590 static void sparc_option_override (void);
591 static void sparc_init_modes (void);
592 static int function_arg_slotno (const CUMULATIVE_ARGS
*, machine_mode
,
593 const_tree
, bool, bool, int *, int *);
595 static int supersparc_adjust_cost (rtx_insn
*, int, rtx_insn
*, int);
596 static int hypersparc_adjust_cost (rtx_insn
*, int, rtx_insn
*, int);
598 static void sparc_emit_set_const32 (rtx
, rtx
);
599 static void sparc_emit_set_const64 (rtx
, rtx
);
600 static void sparc_output_addr_vec (rtx
);
601 static void sparc_output_addr_diff_vec (rtx
);
602 static void sparc_output_deferred_case_vectors (void);
603 static bool sparc_legitimate_address_p (machine_mode
, rtx
, bool);
604 static bool sparc_legitimate_constant_p (machine_mode
, rtx
);
605 static rtx
sparc_builtin_saveregs (void);
606 static int epilogue_renumber (rtx
*, int);
607 static bool sparc_assemble_integer (rtx
, unsigned int, int);
608 static int set_extends (rtx_insn
*);
609 static void sparc_asm_function_prologue (FILE *);
610 static void sparc_asm_function_epilogue (FILE *);
611 #ifdef TARGET_SOLARIS
612 static void sparc_solaris_elf_asm_named_section (const char *, unsigned int,
613 tree
) ATTRIBUTE_UNUSED
;
615 static int sparc_adjust_cost (rtx_insn
*, int, rtx_insn
*, int, unsigned int);
616 static int sparc_issue_rate (void);
617 static void sparc_sched_init (FILE *, int, int);
618 static int sparc_use_sched_lookahead (void);
620 static void emit_soft_tfmode_libcall (const char *, int, rtx
*);
621 static void emit_soft_tfmode_binop (enum rtx_code
, rtx
*);
622 static void emit_soft_tfmode_unop (enum rtx_code
, rtx
*);
623 static void emit_soft_tfmode_cvt (enum rtx_code
, rtx
*);
624 static void emit_hard_tfmode_operation (enum rtx_code
, rtx
*);
626 static bool sparc_function_ok_for_sibcall (tree
, tree
);
627 static void sparc_init_libfuncs (void);
628 static void sparc_init_builtins (void);
629 static void sparc_fpu_init_builtins (void);
630 static void sparc_vis_init_builtins (void);
631 static tree
sparc_builtin_decl (unsigned, bool);
632 static rtx
sparc_expand_builtin (tree
, rtx
, rtx
, machine_mode
, int);
633 static tree
sparc_fold_builtin (tree
, int, tree
*, bool);
634 static void sparc_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
635 HOST_WIDE_INT
, tree
);
636 static bool sparc_can_output_mi_thunk (const_tree
, HOST_WIDE_INT
,
637 HOST_WIDE_INT
, const_tree
);
638 static struct machine_function
* sparc_init_machine_status (void);
639 static bool sparc_cannot_force_const_mem (machine_mode
, rtx
);
640 static rtx
sparc_tls_get_addr (void);
641 static rtx
sparc_tls_got (void);
642 static int sparc_register_move_cost (machine_mode
,
643 reg_class_t
, reg_class_t
);
644 static bool sparc_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
645 static machine_mode
sparc_promote_function_mode (const_tree
, machine_mode
,
646 int *, const_tree
, int);
647 static bool sparc_strict_argument_naming (cumulative_args_t
);
648 static void sparc_va_start (tree
, rtx
);
649 static tree
sparc_gimplify_va_arg (tree
, tree
, gimple_seq
*, gimple_seq
*);
650 static bool sparc_vector_mode_supported_p (machine_mode
);
651 static bool sparc_tls_referenced_p (rtx
);
652 static rtx
sparc_legitimize_tls_address (rtx
);
653 static rtx
sparc_legitimize_pic_address (rtx
, rtx
);
654 static rtx
sparc_legitimize_address (rtx
, rtx
, machine_mode
);
655 static rtx
sparc_delegitimize_address (rtx
);
656 static bool sparc_mode_dependent_address_p (const_rtx
, addr_space_t
);
657 static bool sparc_pass_by_reference (cumulative_args_t
,
658 machine_mode
, const_tree
, bool);
659 static void sparc_function_arg_advance (cumulative_args_t
,
660 machine_mode
, const_tree
, bool);
661 static rtx
sparc_function_arg_1 (cumulative_args_t
,
662 machine_mode
, const_tree
, bool, bool);
663 static rtx
sparc_function_arg (cumulative_args_t
,
664 machine_mode
, const_tree
, bool);
665 static rtx
sparc_function_incoming_arg (cumulative_args_t
,
666 machine_mode
, const_tree
, bool);
667 static pad_direction
sparc_function_arg_padding (machine_mode
, const_tree
);
668 static unsigned int sparc_function_arg_boundary (machine_mode
,
670 static int sparc_arg_partial_bytes (cumulative_args_t
,
671 machine_mode
, tree
, bool);
672 static bool sparc_return_in_memory (const_tree
, const_tree
);
673 static rtx
sparc_struct_value_rtx (tree
, int);
674 static rtx
sparc_function_value (const_tree
, const_tree
, bool);
675 static rtx
sparc_libcall_value (machine_mode
, const_rtx
);
676 static bool sparc_function_value_regno_p (const unsigned int);
677 static unsigned HOST_WIDE_INT
sparc_asan_shadow_offset (void);
678 static void sparc_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
679 static void sparc_file_end (void);
680 static bool sparc_frame_pointer_required (void);
681 static bool sparc_can_eliminate (const int, const int);
682 static rtx
sparc_builtin_setjmp_frame_value (void);
683 static void sparc_conditional_register_usage (void);
684 static bool sparc_use_pseudo_pic_reg (void);
685 static void sparc_init_pic_reg (void);
686 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
687 static const char *sparc_mangle_type (const_tree
);
689 static void sparc_trampoline_init (rtx
, tree
, rtx
);
690 static machine_mode
sparc_preferred_simd_mode (scalar_mode
);
691 static reg_class_t
sparc_preferred_reload_class (rtx x
, reg_class_t rclass
);
692 static bool sparc_lra_p (void);
693 static bool sparc_print_operand_punct_valid_p (unsigned char);
694 static void sparc_print_operand (FILE *, rtx
, int);
695 static void sparc_print_operand_address (FILE *, machine_mode
, rtx
);
696 static reg_class_t
sparc_secondary_reload (bool, rtx
, reg_class_t
,
698 secondary_reload_info
*);
699 static bool sparc_secondary_memory_needed (machine_mode
, reg_class_t
,
701 static machine_mode
sparc_secondary_memory_needed_mode (machine_mode
);
702 static scalar_int_mode
sparc_cstore_mode (enum insn_code icode
);
703 static void sparc_atomic_assign_expand_fenv (tree
*, tree
*, tree
*);
704 static bool sparc_fixed_condition_code_regs (unsigned int *, unsigned int *);
705 static unsigned int sparc_min_arithmetic_precision (void);
706 static unsigned int sparc_hard_regno_nregs (unsigned int, machine_mode
);
707 static bool sparc_hard_regno_mode_ok (unsigned int, machine_mode
);
708 static bool sparc_modes_tieable_p (machine_mode
, machine_mode
);
709 static bool sparc_can_change_mode_class (machine_mode
, machine_mode
,
711 static HOST_WIDE_INT
sparc_constant_alignment (const_tree
, HOST_WIDE_INT
);
712 static bool sparc_vectorize_vec_perm_const (machine_mode
, rtx
, rtx
, rtx
,
713 const vec_perm_indices
&);
714 static bool sparc_can_follow_jump (const rtx_insn
*, const rtx_insn
*);
716 #ifdef SUBTARGET_ATTRIBUTE_TABLE
717 /* Table of valid machine attributes. */
718 static const struct attribute_spec sparc_attribute_table
[] =
720 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
721 do_diagnostic, handler, exclude } */
722 SUBTARGET_ATTRIBUTE_TABLE
,
723 { NULL
, 0, 0, false, false, false, false, NULL
, NULL
}
727 /* Option handling. */
730 enum cmodel sparc_cmodel
;
732 char sparc_hard_reg_printed
[8];
734 /* Initialize the GCC target structure. */
736 /* The default is to use .half rather than .short for aligned HI objects. */
737 #undef TARGET_ASM_ALIGNED_HI_OP
738 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
740 #undef TARGET_ASM_UNALIGNED_HI_OP
741 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
742 #undef TARGET_ASM_UNALIGNED_SI_OP
743 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
744 #undef TARGET_ASM_UNALIGNED_DI_OP
745 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
747 /* The target hook has to handle DI-mode values. */
748 #undef TARGET_ASM_INTEGER
749 #define TARGET_ASM_INTEGER sparc_assemble_integer
751 #undef TARGET_ASM_FUNCTION_PROLOGUE
752 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
753 #undef TARGET_ASM_FUNCTION_EPILOGUE
754 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
756 #undef TARGET_SCHED_ADJUST_COST
757 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
758 #undef TARGET_SCHED_ISSUE_RATE
759 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
760 #undef TARGET_SCHED_INIT
761 #define TARGET_SCHED_INIT sparc_sched_init
762 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
763 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
765 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
766 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
768 #undef TARGET_INIT_LIBFUNCS
769 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
771 #undef TARGET_LEGITIMIZE_ADDRESS
772 #define TARGET_LEGITIMIZE_ADDRESS sparc_legitimize_address
773 #undef TARGET_DELEGITIMIZE_ADDRESS
774 #define TARGET_DELEGITIMIZE_ADDRESS sparc_delegitimize_address
775 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
776 #define TARGET_MODE_DEPENDENT_ADDRESS_P sparc_mode_dependent_address_p
778 #undef TARGET_INIT_BUILTINS
779 #define TARGET_INIT_BUILTINS sparc_init_builtins
780 #undef TARGET_BUILTIN_DECL
781 #define TARGET_BUILTIN_DECL sparc_builtin_decl
782 #undef TARGET_EXPAND_BUILTIN
783 #define TARGET_EXPAND_BUILTIN sparc_expand_builtin
784 #undef TARGET_FOLD_BUILTIN
785 #define TARGET_FOLD_BUILTIN sparc_fold_builtin
788 #undef TARGET_HAVE_TLS
789 #define TARGET_HAVE_TLS true
792 #undef TARGET_CANNOT_FORCE_CONST_MEM
793 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
795 #undef TARGET_ASM_OUTPUT_MI_THUNK
796 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
797 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
798 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
800 #undef TARGET_RTX_COSTS
801 #define TARGET_RTX_COSTS sparc_rtx_costs
802 #undef TARGET_ADDRESS_COST
803 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
804 #undef TARGET_REGISTER_MOVE_COST
805 #define TARGET_REGISTER_MOVE_COST sparc_register_move_cost
807 #undef TARGET_PROMOTE_FUNCTION_MODE
808 #define TARGET_PROMOTE_FUNCTION_MODE sparc_promote_function_mode
809 #undef TARGET_STRICT_ARGUMENT_NAMING
810 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
812 #undef TARGET_MUST_PASS_IN_STACK
813 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
814 #undef TARGET_PASS_BY_REFERENCE
815 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
816 #undef TARGET_ARG_PARTIAL_BYTES
817 #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
818 #undef TARGET_FUNCTION_ARG_ADVANCE
819 #define TARGET_FUNCTION_ARG_ADVANCE sparc_function_arg_advance
820 #undef TARGET_FUNCTION_ARG
821 #define TARGET_FUNCTION_ARG sparc_function_arg
822 #undef TARGET_FUNCTION_INCOMING_ARG
823 #define TARGET_FUNCTION_INCOMING_ARG sparc_function_incoming_arg
824 #undef TARGET_FUNCTION_ARG_PADDING
825 #define TARGET_FUNCTION_ARG_PADDING sparc_function_arg_padding
826 #undef TARGET_FUNCTION_ARG_BOUNDARY
827 #define TARGET_FUNCTION_ARG_BOUNDARY sparc_function_arg_boundary
829 #undef TARGET_RETURN_IN_MEMORY
830 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
831 #undef TARGET_STRUCT_VALUE_RTX
832 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
833 #undef TARGET_FUNCTION_VALUE
834 #define TARGET_FUNCTION_VALUE sparc_function_value
835 #undef TARGET_LIBCALL_VALUE
836 #define TARGET_LIBCALL_VALUE sparc_libcall_value
837 #undef TARGET_FUNCTION_VALUE_REGNO_P
838 #define TARGET_FUNCTION_VALUE_REGNO_P sparc_function_value_regno_p
840 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
841 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
843 #undef TARGET_ASAN_SHADOW_OFFSET
844 #define TARGET_ASAN_SHADOW_OFFSET sparc_asan_shadow_offset
846 #undef TARGET_EXPAND_BUILTIN_VA_START
847 #define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start
848 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
849 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
851 #undef TARGET_VECTOR_MODE_SUPPORTED_P
852 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
854 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
855 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE sparc_preferred_simd_mode
857 #ifdef SUBTARGET_INSERT_ATTRIBUTES
858 #undef TARGET_INSERT_ATTRIBUTES
859 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
862 #ifdef SUBTARGET_ATTRIBUTE_TABLE
863 #undef TARGET_ATTRIBUTE_TABLE
864 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
867 #undef TARGET_OPTION_OVERRIDE
868 #define TARGET_OPTION_OVERRIDE sparc_option_override
870 #ifdef TARGET_THREAD_SSP_OFFSET
871 #undef TARGET_STACK_PROTECT_GUARD
872 #define TARGET_STACK_PROTECT_GUARD hook_tree_void_null
875 #if TARGET_GNU_TLS && defined(HAVE_AS_SPARC_UA_PCREL)
876 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
877 #define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel
880 #undef TARGET_ASM_FILE_END
881 #define TARGET_ASM_FILE_END sparc_file_end
883 #undef TARGET_FRAME_POINTER_REQUIRED
884 #define TARGET_FRAME_POINTER_REQUIRED sparc_frame_pointer_required
886 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
887 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE sparc_builtin_setjmp_frame_value
889 #undef TARGET_CAN_ELIMINATE
890 #define TARGET_CAN_ELIMINATE sparc_can_eliminate
892 #undef TARGET_PREFERRED_RELOAD_CLASS
893 #define TARGET_PREFERRED_RELOAD_CLASS sparc_preferred_reload_class
895 #undef TARGET_SECONDARY_RELOAD
896 #define TARGET_SECONDARY_RELOAD sparc_secondary_reload
897 #undef TARGET_SECONDARY_MEMORY_NEEDED
898 #define TARGET_SECONDARY_MEMORY_NEEDED sparc_secondary_memory_needed
899 #undef TARGET_SECONDARY_MEMORY_NEEDED_MODE
900 #define TARGET_SECONDARY_MEMORY_NEEDED_MODE sparc_secondary_memory_needed_mode
902 #undef TARGET_CONDITIONAL_REGISTER_USAGE
903 #define TARGET_CONDITIONAL_REGISTER_USAGE sparc_conditional_register_usage
905 #undef TARGET_INIT_PIC_REG
906 #define TARGET_INIT_PIC_REG sparc_init_pic_reg
908 #undef TARGET_USE_PSEUDO_PIC_REG
909 #define TARGET_USE_PSEUDO_PIC_REG sparc_use_pseudo_pic_reg
911 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
912 #undef TARGET_MANGLE_TYPE
913 #define TARGET_MANGLE_TYPE sparc_mangle_type
917 #define TARGET_LRA_P sparc_lra_p
919 #undef TARGET_LEGITIMATE_ADDRESS_P
920 #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p
922 #undef TARGET_LEGITIMATE_CONSTANT_P
923 #define TARGET_LEGITIMATE_CONSTANT_P sparc_legitimate_constant_p
925 #undef TARGET_TRAMPOLINE_INIT
926 #define TARGET_TRAMPOLINE_INIT sparc_trampoline_init
928 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
929 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sparc_print_operand_punct_valid_p
930 #undef TARGET_PRINT_OPERAND
931 #define TARGET_PRINT_OPERAND sparc_print_operand
932 #undef TARGET_PRINT_OPERAND_ADDRESS
933 #define TARGET_PRINT_OPERAND_ADDRESS sparc_print_operand_address
935 /* The value stored by LDSTUB. */
936 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
937 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 0xff
939 #undef TARGET_CSTORE_MODE
940 #define TARGET_CSTORE_MODE sparc_cstore_mode
942 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
943 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV sparc_atomic_assign_expand_fenv
945 #undef TARGET_FIXED_CONDITION_CODE_REGS
946 #define TARGET_FIXED_CONDITION_CODE_REGS sparc_fixed_condition_code_regs
948 #undef TARGET_MIN_ARITHMETIC_PRECISION
949 #define TARGET_MIN_ARITHMETIC_PRECISION sparc_min_arithmetic_precision
951 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
952 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
954 #undef TARGET_HARD_REGNO_NREGS
955 #define TARGET_HARD_REGNO_NREGS sparc_hard_regno_nregs
956 #undef TARGET_HARD_REGNO_MODE_OK
957 #define TARGET_HARD_REGNO_MODE_OK sparc_hard_regno_mode_ok
959 #undef TARGET_MODES_TIEABLE_P
960 #define TARGET_MODES_TIEABLE_P sparc_modes_tieable_p
962 #undef TARGET_CAN_CHANGE_MODE_CLASS
963 #define TARGET_CAN_CHANGE_MODE_CLASS sparc_can_change_mode_class
965 #undef TARGET_CONSTANT_ALIGNMENT
966 #define TARGET_CONSTANT_ALIGNMENT sparc_constant_alignment
968 #undef TARGET_VECTORIZE_VEC_PERM_CONST
969 #define TARGET_VECTORIZE_VEC_PERM_CONST sparc_vectorize_vec_perm_const
971 #undef TARGET_CAN_FOLLOW_JUMP
972 #define TARGET_CAN_FOLLOW_JUMP sparc_can_follow_jump
974 struct gcc_target targetm
= TARGET_INITIALIZER
;
976 /* Return the memory reference contained in X if any, zero otherwise. */
981 if (GET_CODE (x
) == SIGN_EXTEND
|| GET_CODE (x
) == ZERO_EXTEND
)
990 /* True if any of INSN's source register(s) is REG. */
993 insn_uses_reg_p (rtx_insn
*insn
, unsigned int reg
)
996 return ((REG_P (recog_data
.operand
[1])
997 && REGNO (recog_data
.operand
[1]) == reg
)
998 || (recog_data
.n_operands
== 3
999 && REG_P (recog_data
.operand
[2])
1000 && REGNO (recog_data
.operand
[2]) == reg
));
1003 /* True if INSN is a floating-point division or square-root. */
1006 div_sqrt_insn_p (rtx_insn
*insn
)
1008 if (GET_CODE (PATTERN (insn
)) != SET
)
1011 switch (get_attr_type (insn
))
1023 /* True if INSN is a floating-point instruction. */
1026 fpop_insn_p (rtx_insn
*insn
)
1028 if (GET_CODE (PATTERN (insn
)) != SET
)
1031 switch (get_attr_type (insn
))
1048 /* True if INSN is an atomic instruction. */
1051 atomic_insn_for_leon3_p (rtx_insn
*insn
)
1053 switch (INSN_CODE (insn
))
1055 case CODE_FOR_swapsi
:
1056 case CODE_FOR_ldstub
:
1057 case CODE_FOR_atomic_compare_and_swap_leon3_1
:
1064 /* We use a machine specific pass to enable workarounds for errata.
1066 We need to have the (essentially) final form of the insn stream in order
1067 to properly detect the various hazards. Therefore, this machine specific
1068 pass runs as late as possible. */
1070 /* True if INSN is a md pattern or asm statement. */
1071 #define USEFUL_INSN_P(INSN) \
1072 (NONDEBUG_INSN_P (INSN) \
1073 && GET_CODE (PATTERN (INSN)) != USE \
1074 && GET_CODE (PATTERN (INSN)) != CLOBBER)
1077 sparc_do_work_around_errata (void)
1079 rtx_insn
*insn
, *next
;
1081 /* Force all instructions to be split into their final form. */
1082 split_all_insns_noflow ();
1084 /* Now look for specific patterns in the insn stream. */
1085 for (insn
= get_insns (); insn
; insn
= next
)
1087 bool insert_nop
= false;
1092 /* Look into the instruction in a delay slot. */
1093 if (NONJUMP_INSN_P (insn
)
1094 && (seq
= dyn_cast
<rtx_sequence
*> (PATTERN (insn
))))
1096 jump
= seq
->insn (0);
1097 insn
= seq
->insn (1);
1099 else if (JUMP_P (insn
))
1104 /* Place a NOP at the branch target of an integer branch if it is a
1105 floating-point operation or a floating-point branch. */
1106 if (sparc_fix_gr712rc
1108 && jump_to_label_p (jump
)
1109 && get_attr_branch_type (jump
) == BRANCH_TYPE_ICC
)
1111 rtx_insn
*target
= next_active_insn (JUMP_LABEL_AS_INSN (jump
));
1113 && (fpop_insn_p (target
)
1115 && get_attr_branch_type (target
) == BRANCH_TYPE_FCC
)))
1116 emit_insn_before (gen_nop (), target
);
1119 /* Insert a NOP between load instruction and atomic instruction. Insert
1120 a NOP at branch target if there is a load in delay slot and an atomic
1121 instruction at branch target. */
1123 && NONJUMP_INSN_P (insn
)
1124 && (set
= single_set (insn
)) != NULL_RTX
1125 && mem_ref (SET_SRC (set
))
1126 && REG_P (SET_DEST (set
)))
1128 if (jump
&& jump_to_label_p (jump
))
1130 rtx_insn
*target
= next_active_insn (JUMP_LABEL_AS_INSN (jump
));
1131 if (target
&& atomic_insn_for_leon3_p (target
))
1132 emit_insn_before (gen_nop (), target
);
1135 next
= next_active_insn (insn
);
1139 if (atomic_insn_for_leon3_p (next
))
1143 /* Look for a sequence that starts with a fdiv or fsqrt instruction and
1144 ends with another fdiv or fsqrt instruction with no dependencies on
1145 the former, along with an appropriate pattern in between. */
1146 if (sparc_fix_lost_divsqrt
1147 && NONJUMP_INSN_P (insn
)
1148 && div_sqrt_insn_p (insn
))
1154 const unsigned int dest_reg
= REGNO (SET_DEST (single_set (insn
)));
1156 next
= next_active_insn (insn
);
1160 for (after
= next
, i
= 0; i
< 4; i
++)
1162 /* Count floating-point operations. */
1163 if (i
!= 3 && fpop_insn_p (after
))
1165 /* If the insn uses the destination register of
1166 the div/sqrt, then it cannot be problematic. */
1167 if (insn_uses_reg_p (after
, dest_reg
))
1172 /* Count floating-point loads. */
1174 && (set
= single_set (after
)) != NULL_RTX
1175 && REG_P (SET_DEST (set
))
1176 && REGNO (SET_DEST (set
)) > 31)
1178 /* If the insn uses the destination register of
1179 the div/sqrt, then it cannot be problematic. */
1180 if (REGNO (SET_DEST (set
)) == dest_reg
)
1185 /* Check if this is a problematic sequence. */
1188 && div_sqrt_insn_p (after
))
1190 /* If this is the short version of the problematic
1191 sequence we add two NOPs in a row to also prevent
1192 the long version. */
1194 emit_insn_before (gen_nop (), next
);
1199 /* No need to scan past a second div/sqrt. */
1200 if (div_sqrt_insn_p (after
))
1203 /* Insert NOP before branch. */
1205 && (!NONJUMP_INSN_P (after
)
1206 || GET_CODE (PATTERN (after
)) == SEQUENCE
))
1212 after
= next_active_insn (after
);
1218 /* Look for either of these two sequences:
1221 1. store of word size or less (e.g. st / stb / sth / stf)
1222 2. any single instruction that is not a load or store
1223 3. any store instruction (e.g. st / stb / sth / stf / std / stdf)
1226 1. store of double word size (e.g. std / stdf)
1227 2. any store instruction (e.g. st / stb / sth / stf / std / stdf) */
1229 && NONJUMP_INSN_P (insn
)
1230 && (set
= single_set (insn
)) != NULL_RTX
1231 && MEM_P (SET_DEST (set
)))
1233 /* Sequence B begins with a double-word store. */
1234 bool seq_b
= GET_MODE_SIZE (GET_MODE (SET_DEST (set
))) == 8;
1238 next
= next_active_insn (insn
);
1242 for (after
= next
, i
= 0; i
< 2; i
++)
1244 /* Skip empty assembly statements. */
1245 if ((GET_CODE (PATTERN (after
)) == UNSPEC_VOLATILE
)
1246 || (USEFUL_INSN_P (after
)
1247 && (asm_noperands (PATTERN (after
))>=0)
1248 && !strcmp (decode_asm_operands (PATTERN (after
),
1251 after
= next_active_insn (after
);
1255 /* If the insn is a branch, then it cannot be problematic. */
1256 if (!NONJUMP_INSN_P (after
)
1257 || GET_CODE (PATTERN (after
)) == SEQUENCE
)
1260 /* Sequence B is only two instructions long. */
1263 /* Add NOP if followed by a store. */
1264 if ((set
= single_set (after
)) != NULL_RTX
1265 && MEM_P (SET_DEST (set
)))
1268 /* Otherwise it is ok. */
1272 /* If the second instruction is a load or a store,
1273 then the sequence cannot be problematic. */
1276 if ((set
= single_set (after
)) != NULL_RTX
1277 && (MEM_P (SET_DEST (set
)) || mem_ref (SET_SRC (set
))))
1280 after
= next_active_insn (after
);
1285 /* Add NOP if third instruction is a store. */
1287 && (set
= single_set (after
)) != NULL_RTX
1288 && MEM_P (SET_DEST (set
)))
1293 /* Look for a single-word load into an odd-numbered FP register. */
1294 else if (sparc_fix_at697f
1295 && NONJUMP_INSN_P (insn
)
1296 && (set
= single_set (insn
)) != NULL_RTX
1297 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
1298 && mem_ref (SET_SRC (set
))
1299 && REG_P (SET_DEST (set
))
1300 && REGNO (SET_DEST (set
)) > 31
1301 && REGNO (SET_DEST (set
)) % 2 != 0)
1303 /* The wrong dependency is on the enclosing double register. */
1304 const unsigned int x
= REGNO (SET_DEST (set
)) - 1;
1305 unsigned int src1
, src2
, dest
;
1308 next
= next_active_insn (insn
);
1311 /* If the insn is a branch, then it cannot be problematic. */
1312 if (!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) == SEQUENCE
)
1315 extract_insn (next
);
1316 code
= INSN_CODE (next
);
1320 case CODE_FOR_adddf3
:
1321 case CODE_FOR_subdf3
:
1322 case CODE_FOR_muldf3
:
1323 case CODE_FOR_divdf3
:
1324 dest
= REGNO (recog_data
.operand
[0]);
1325 src1
= REGNO (recog_data
.operand
[1]);
1326 src2
= REGNO (recog_data
.operand
[2]);
1331 FPOPd %f{x,y}, %f{y,x}, %f{x,y} */
1332 if ((src1
== x
|| src2
== x
)
1333 && (dest
== src1
|| dest
== src2
))
1340 FPOPd %fx, %fx, %fx */
1343 && (code
== CODE_FOR_adddf3
|| code
== CODE_FOR_muldf3
))
1348 case CODE_FOR_sqrtdf2
:
1349 dest
= REGNO (recog_data
.operand
[0]);
1350 src1
= REGNO (recog_data
.operand
[1]);
1354 if (src1
== x
&& dest
== src1
)
1363 /* Look for a single-word load into an integer register. */
1364 else if (sparc_fix_ut699
1365 && NONJUMP_INSN_P (insn
)
1366 && (set
= single_set (insn
)) != NULL_RTX
1367 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) <= 4
1368 && (mem_ref (SET_SRC (set
)) != NULL_RTX
1369 || INSN_CODE (insn
) == CODE_FOR_movsi_pic_gotdata_op
)
1370 && REG_P (SET_DEST (set
))
1371 && REGNO (SET_DEST (set
)) < 32)
1373 /* There is no problem if the second memory access has a data
1374 dependency on the first single-cycle load. */
1375 rtx x
= SET_DEST (set
);
1377 next
= next_active_insn (insn
);
1380 /* If the insn is a branch, then it cannot be problematic. */
1381 if (!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) == SEQUENCE
)
1384 /* Look for a second memory access to/from an integer register. */
1385 if ((set
= single_set (next
)) != NULL_RTX
)
1387 rtx src
= SET_SRC (set
);
1388 rtx dest
= SET_DEST (set
);
1391 /* LDD is affected. */
1392 if ((mem
= mem_ref (src
)) != NULL_RTX
1394 && REGNO (dest
) < 32
1395 && !reg_mentioned_p (x
, XEXP (mem
, 0)))
1398 /* STD is *not* affected. */
1399 else if (MEM_P (dest
)
1400 && GET_MODE_SIZE (GET_MODE (dest
)) <= 4
1401 && (src
== CONST0_RTX (GET_MODE (dest
))
1404 && REGNO (src
) != REGNO (x
)))
1405 && !reg_mentioned_p (x
, XEXP (dest
, 0)))
1408 /* GOT accesses uses LD. */
1409 else if (INSN_CODE (next
) == CODE_FOR_movsi_pic_gotdata_op
1410 && !reg_mentioned_p (x
, XEXP (XEXP (src
, 0), 1)))
1415 /* Look for a single-word load/operation into an FP register. */
1416 else if (sparc_fix_ut699
1417 && NONJUMP_INSN_P (insn
)
1418 && (set
= single_set (insn
)) != NULL_RTX
1419 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
1420 && REG_P (SET_DEST (set
))
1421 && REGNO (SET_DEST (set
)) > 31)
1423 /* Number of instructions in the problematic window. */
1424 const int n_insns
= 4;
1425 /* The problematic combination is with the sibling FP register. */
1426 const unsigned int x
= REGNO (SET_DEST (set
));
1427 const unsigned int y
= x
^ 1;
1431 next
= next_active_insn (insn
);
1434 /* If the insn is a branch, then it cannot be problematic. */
1435 if (!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) == SEQUENCE
)
1438 /* Look for a second load/operation into the sibling FP register. */
1439 if (!((set
= single_set (next
)) != NULL_RTX
1440 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
1441 && REG_P (SET_DEST (set
))
1442 && REGNO (SET_DEST (set
)) == y
))
1445 /* Look for a (possible) store from the FP register in the next N
1446 instructions, but bail out if it is again modified or if there
1447 is a store from the sibling FP register before this store. */
1448 for (after
= next
, i
= 0; i
< n_insns
; i
++)
1452 after
= next_active_insn (after
);
1456 /* This is a branch with an empty delay slot. */
1457 if (!NONJUMP_INSN_P (after
))
1464 /* This is a branch with a filled delay slot. */
1465 else if (rtx_sequence
*seq
=
1466 dyn_cast
<rtx_sequence
*> (PATTERN (after
)))
1471 after
= seq
->insn (1);
1473 /* This is a regular instruction. */
1477 if (after
&& (set
= single_set (after
)) != NULL_RTX
)
1479 const rtx src
= SET_SRC (set
);
1480 const rtx dest
= SET_DEST (set
);
1481 const unsigned int size
= GET_MODE_SIZE (GET_MODE (dest
));
1483 /* If the FP register is again modified before the store,
1484 then the store isn't affected. */
1486 && (REGNO (dest
) == x
1487 || (REGNO (dest
) == y
&& size
== 8)))
1490 if (MEM_P (dest
) && REG_P (src
))
1492 /* If there is a store from the sibling FP register
1493 before the store, then the store is not affected. */
1494 if (REGNO (src
) == y
|| (REGNO (src
) == x
&& size
== 8))
1497 /* Otherwise, the store is affected. */
1498 if (REGNO (src
) == x
&& size
== 4)
1506 /* If we have a branch in the first M instructions, then we
1507 cannot see the (M+2)th instruction so we play safe. */
1508 if (branch_p
&& i
<= (n_insns
- 2))
1517 next
= NEXT_INSN (insn
);
1520 emit_insn_before (gen_nop (), next
);
1528 const pass_data pass_data_work_around_errata
=
1530 RTL_PASS
, /* type */
1531 "errata", /* name */
1532 OPTGROUP_NONE
, /* optinfo_flags */
1533 TV_MACH_DEP
, /* tv_id */
1534 0, /* properties_required */
1535 0, /* properties_provided */
1536 0, /* properties_destroyed */
1537 0, /* todo_flags_start */
1538 0, /* todo_flags_finish */
1541 class pass_work_around_errata
: public rtl_opt_pass
1544 pass_work_around_errata(gcc::context
*ctxt
)
1545 : rtl_opt_pass(pass_data_work_around_errata
, ctxt
)
1548 /* opt_pass methods: */
1549 virtual bool gate (function
*)
1551 return sparc_fix_at697f
1552 || sparc_fix_ut699
|| sparc_fix_ut700
|| sparc_fix_gr712rc
1553 || sparc_fix_b2bst
|| sparc_fix_lost_divsqrt
;
1556 virtual unsigned int execute (function
*)
1558 return sparc_do_work_around_errata ();
1561 }; // class pass_work_around_errata
1566 make_pass_work_around_errata (gcc::context
*ctxt
)
1568 return new pass_work_around_errata (ctxt
);
1571 /* Helpers for TARGET_DEBUG_OPTIONS. */
1573 dump_target_flag_bits (const int flags
)
1575 if (flags
& MASK_64BIT
)
1576 fprintf (stderr
, "64BIT ");
1577 if (flags
& MASK_APP_REGS
)
1578 fprintf (stderr
, "APP_REGS ");
1579 if (flags
& MASK_FASTER_STRUCTS
)
1580 fprintf (stderr
, "FASTER_STRUCTS ");
1581 if (flags
& MASK_FLAT
)
1582 fprintf (stderr
, "FLAT ");
1583 if (flags
& MASK_FMAF
)
1584 fprintf (stderr
, "FMAF ");
1585 if (flags
& MASK_FSMULD
)
1586 fprintf (stderr
, "FSMULD ");
1587 if (flags
& MASK_FPU
)
1588 fprintf (stderr
, "FPU ");
1589 if (flags
& MASK_HARD_QUAD
)
1590 fprintf (stderr
, "HARD_QUAD ");
1591 if (flags
& MASK_POPC
)
1592 fprintf (stderr
, "POPC ");
1593 if (flags
& MASK_PTR64
)
1594 fprintf (stderr
, "PTR64 ");
1595 if (flags
& MASK_STACK_BIAS
)
1596 fprintf (stderr
, "STACK_BIAS ");
1597 if (flags
& MASK_UNALIGNED_DOUBLES
)
1598 fprintf (stderr
, "UNALIGNED_DOUBLES ");
1599 if (flags
& MASK_V8PLUS
)
1600 fprintf (stderr
, "V8PLUS ");
1601 if (flags
& MASK_VIS
)
1602 fprintf (stderr
, "VIS ");
1603 if (flags
& MASK_VIS2
)
1604 fprintf (stderr
, "VIS2 ");
1605 if (flags
& MASK_VIS3
)
1606 fprintf (stderr
, "VIS3 ");
1607 if (flags
& MASK_VIS4
)
1608 fprintf (stderr
, "VIS4 ");
1609 if (flags
& MASK_VIS4B
)
1610 fprintf (stderr
, "VIS4B ");
1611 if (flags
& MASK_CBCOND
)
1612 fprintf (stderr
, "CBCOND ");
1613 if (flags
& MASK_DEPRECATED_V8_INSNS
)
1614 fprintf (stderr
, "DEPRECATED_V8_INSNS ");
1615 if (flags
& MASK_SPARCLET
)
1616 fprintf (stderr
, "SPARCLET ");
1617 if (flags
& MASK_SPARCLITE
)
1618 fprintf (stderr
, "SPARCLITE ");
1619 if (flags
& MASK_V8
)
1620 fprintf (stderr
, "V8 ");
1621 if (flags
& MASK_V9
)
1622 fprintf (stderr
, "V9 ");
1626 dump_target_flags (const char *prefix
, const int flags
)
1628 fprintf (stderr
, "%s: (%08x) [ ", prefix
, flags
);
1629 dump_target_flag_bits (flags
);
1630 fprintf(stderr
, "]\n");
1633 /* Validate and override various options, and do some machine dependent
1637 sparc_option_override (void)
1639 static struct code_model
{
1640 const char *const name
;
1641 const enum cmodel value
;
1642 } const cmodels
[] = {
1644 { "medlow", CM_MEDLOW
},
1645 { "medmid", CM_MEDMID
},
1646 { "medany", CM_MEDANY
},
1647 { "embmedany", CM_EMBMEDANY
},
1648 { NULL
, (enum cmodel
) 0 }
1650 const struct code_model
*cmodel
;
1651 /* Map TARGET_CPU_DEFAULT to value for -m{cpu,tune}=. */
1652 static struct cpu_default
{
1654 const enum processor_type processor
;
1655 } const cpu_default
[] = {
1656 /* There must be one entry here for each TARGET_CPU value. */
1657 { TARGET_CPU_sparc
, PROCESSOR_CYPRESS
},
1658 { TARGET_CPU_v8
, PROCESSOR_V8
},
1659 { TARGET_CPU_supersparc
, PROCESSOR_SUPERSPARC
},
1660 { TARGET_CPU_hypersparc
, PROCESSOR_HYPERSPARC
},
1661 { TARGET_CPU_leon
, PROCESSOR_LEON
},
1662 { TARGET_CPU_leon3
, PROCESSOR_LEON3
},
1663 { TARGET_CPU_leon3v7
, PROCESSOR_LEON3V7
},
1664 { TARGET_CPU_sparclite
, PROCESSOR_F930
},
1665 { TARGET_CPU_sparclite86x
, PROCESSOR_SPARCLITE86X
},
1666 { TARGET_CPU_sparclet
, PROCESSOR_TSC701
},
1667 { TARGET_CPU_v9
, PROCESSOR_V9
},
1668 { TARGET_CPU_ultrasparc
, PROCESSOR_ULTRASPARC
},
1669 { TARGET_CPU_ultrasparc3
, PROCESSOR_ULTRASPARC3
},
1670 { TARGET_CPU_niagara
, PROCESSOR_NIAGARA
},
1671 { TARGET_CPU_niagara2
, PROCESSOR_NIAGARA2
},
1672 { TARGET_CPU_niagara3
, PROCESSOR_NIAGARA3
},
1673 { TARGET_CPU_niagara4
, PROCESSOR_NIAGARA4
},
1674 { TARGET_CPU_niagara7
, PROCESSOR_NIAGARA7
},
1675 { TARGET_CPU_m8
, PROCESSOR_M8
},
1676 { -1, PROCESSOR_V7
}
1678 const struct cpu_default
*def
;
1679 /* Table of values for -m{cpu,tune}=. This must match the order of
1680 the enum processor_type in sparc-opts.h. */
1681 static struct cpu_table
{
1682 const char *const name
;
1685 } const cpu_table
[] = {
1686 { "v7", MASK_ISA
, 0 },
1687 { "cypress", MASK_ISA
, 0 },
1688 { "v8", MASK_ISA
, MASK_V8
},
1689 /* TI TMS390Z55 supersparc */
1690 { "supersparc", MASK_ISA
, MASK_V8
},
1691 { "hypersparc", MASK_ISA
, MASK_V8
},
1692 { "leon", MASK_ISA
|MASK_FSMULD
, MASK_V8
|MASK_LEON
},
1693 { "leon3", MASK_ISA
, MASK_V8
|MASK_LEON3
},
1694 { "leon3v7", MASK_ISA
, MASK_LEON3
},
1695 { "sparclite", MASK_ISA
, MASK_SPARCLITE
},
1696 /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
1697 { "f930", MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
1698 /* The Fujitsu MB86934 is the recent sparclite chip, with an FPU. */
1699 { "f934", MASK_ISA
, MASK_SPARCLITE
},
1700 { "sparclite86x", MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
1701 { "sparclet", MASK_ISA
, MASK_SPARCLET
},
1702 /* TEMIC sparclet */
1703 { "tsc701", MASK_ISA
, MASK_SPARCLET
},
1704 { "v9", MASK_ISA
, MASK_V9
},
1705 /* UltraSPARC I, II, IIi */
1706 { "ultrasparc", MASK_ISA
,
1707 /* Although insns using %y are deprecated, it is a clear win. */
1708 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
1709 /* UltraSPARC III */
1710 /* ??? Check if %y issue still holds true. */
1711 { "ultrasparc3", MASK_ISA
,
1712 MASK_V9
|MASK_DEPRECATED_V8_INSNS
|MASK_VIS2
},
1714 { "niagara", MASK_ISA
,
1715 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
1717 { "niagara2", MASK_ISA
,
1718 MASK_V9
|MASK_POPC
|MASK_VIS2
},
1720 { "niagara3", MASK_ISA
,
1721 MASK_V9
|MASK_POPC
|MASK_VIS3
|MASK_FMAF
},
1723 { "niagara4", MASK_ISA
,
1724 MASK_V9
|MASK_POPC
|MASK_VIS3
|MASK_FMAF
|MASK_CBCOND
},
1726 { "niagara7", MASK_ISA
,
1727 MASK_V9
|MASK_POPC
|MASK_VIS4
|MASK_FMAF
|MASK_CBCOND
|MASK_SUBXC
},
1730 MASK_V9
|MASK_POPC
|MASK_VIS4B
|MASK_FMAF
|MASK_CBCOND
|MASK_SUBXC
}
1732 const struct cpu_table
*cpu
;
1735 if (sparc_debug_string
!= NULL
)
1740 p
= ASTRDUP (sparc_debug_string
);
1741 while ((q
= strtok (p
, ",")) != NULL
)
1755 if (! strcmp (q
, "all"))
1756 mask
= MASK_DEBUG_ALL
;
1757 else if (! strcmp (q
, "options"))
1758 mask
= MASK_DEBUG_OPTIONS
;
1760 error ("unknown -mdebug-%s switch", q
);
1763 sparc_debug
&= ~mask
;
1765 sparc_debug
|= mask
;
1769 /* Enable the FsMULd instruction by default if not explicitly specified by
1770 the user. It may be later disabled by the CPU (explicitly or not). */
1771 if (TARGET_FPU
&& !(target_flags_explicit
& MASK_FSMULD
))
1772 target_flags
|= MASK_FSMULD
;
1774 if (TARGET_DEBUG_OPTIONS
)
1776 dump_target_flags("Initial target_flags", target_flags
);
1777 dump_target_flags("target_flags_explicit", target_flags_explicit
);
1780 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1781 SUBTARGET_OVERRIDE_OPTIONS
;
1784 #ifndef SPARC_BI_ARCH
1785 /* Check for unsupported architecture size. */
1786 if (!TARGET_64BIT
!= DEFAULT_ARCH32_P
)
1787 error ("%s is not supported by this configuration",
1788 DEFAULT_ARCH32_P
? "-m64" : "-m32");
1791 /* We force all 64bit archs to use 128 bit long double */
1792 if (TARGET_ARCH64
&& !TARGET_LONG_DOUBLE_128
)
1794 error ("-mlong-double-64 not allowed with -m64");
1795 target_flags
|= MASK_LONG_DOUBLE_128
;
1798 /* Code model selection. */
1799 sparc_cmodel
= SPARC_DEFAULT_CMODEL
;
1801 #ifdef SPARC_BI_ARCH
1803 sparc_cmodel
= CM_32
;
1806 if (sparc_cmodel_string
!= NULL
)
1810 for (cmodel
= &cmodels
[0]; cmodel
->name
; cmodel
++)
1811 if (strcmp (sparc_cmodel_string
, cmodel
->name
) == 0)
1813 if (cmodel
->name
== NULL
)
1814 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string
);
1816 sparc_cmodel
= cmodel
->value
;
1819 error ("-mcmodel= is not supported on 32-bit systems");
1822 /* Check that -fcall-saved-REG wasn't specified for out registers. */
1823 for (i
= 8; i
< 16; i
++)
1824 if (!call_used_regs
[i
])
1826 error ("-fcall-saved-REG is not supported for out registers");
1827 call_used_regs
[i
] = 1;
1830 /* Set the default CPU if no -mcpu option was specified. */
1831 if (!global_options_set
.x_sparc_cpu_and_features
)
1833 for (def
= &cpu_default
[0]; def
->cpu
!= -1; ++def
)
1834 if (def
->cpu
== TARGET_CPU_DEFAULT
)
1836 gcc_assert (def
->cpu
!= -1);
1837 sparc_cpu_and_features
= def
->processor
;
1840 /* Set the default CPU if no -mtune option was specified. */
1841 if (!global_options_set
.x_sparc_cpu
)
1842 sparc_cpu
= sparc_cpu_and_features
;
1844 cpu
= &cpu_table
[(int) sparc_cpu_and_features
];
1846 if (TARGET_DEBUG_OPTIONS
)
1848 fprintf (stderr
, "sparc_cpu_and_features: %s\n", cpu
->name
);
1849 dump_target_flags ("cpu->disable", cpu
->disable
);
1850 dump_target_flags ("cpu->enable", cpu
->enable
);
1853 target_flags
&= ~cpu
->disable
;
1854 target_flags
|= (cpu
->enable
1855 #ifndef HAVE_AS_FMAF_HPC_VIS3
1856 & ~(MASK_FMAF
| MASK_VIS3
)
1858 #ifndef HAVE_AS_SPARC4
1861 #ifndef HAVE_AS_SPARC5_VIS4
1862 & ~(MASK_VIS4
| MASK_SUBXC
)
1864 #ifndef HAVE_AS_SPARC6
1867 #ifndef HAVE_AS_LEON
1868 & ~(MASK_LEON
| MASK_LEON3
)
1870 & ~(target_flags_explicit
& MASK_FEATURES
)
1873 /* FsMULd is a V8 instruction. */
1874 if (!TARGET_V8
&& !TARGET_V9
)
1875 target_flags
&= ~MASK_FSMULD
;
1877 /* -mvis2 implies -mvis. */
1879 target_flags
|= MASK_VIS
;
1881 /* -mvis3 implies -mvis2 and -mvis. */
1883 target_flags
|= MASK_VIS2
| MASK_VIS
;
1885 /* -mvis4 implies -mvis3, -mvis2 and -mvis. */
1887 target_flags
|= MASK_VIS3
| MASK_VIS2
| MASK_VIS
;
1889 /* -mvis4b implies -mvis4, -mvis3, -mvis2 and -mvis */
1891 target_flags
|= MASK_VIS4
| MASK_VIS3
| MASK_VIS2
| MASK_VIS
;
1893 /* Don't allow -mvis, -mvis2, -mvis3, -mvis4, -mvis4b, -mfmaf and -mfsmuld if
1896 target_flags
&= ~(MASK_VIS
| MASK_VIS2
| MASK_VIS3
| MASK_VIS4
1897 | MASK_VIS4B
| MASK_FMAF
| MASK_FSMULD
);
1899 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
1900 are available; -m64 also implies v9. */
1901 if (TARGET_VIS
|| TARGET_ARCH64
)
1903 target_flags
|= MASK_V9
;
1904 target_flags
&= ~(MASK_V8
| MASK_SPARCLET
| MASK_SPARCLITE
);
1907 /* -mvis also implies -mv8plus on 32-bit. */
1908 if (TARGET_VIS
&& !TARGET_ARCH64
)
1909 target_flags
|= MASK_V8PLUS
;
1911 /* Use the deprecated v8 insns for sparc64 in 32-bit mode. */
1912 if (TARGET_V9
&& TARGET_ARCH32
)
1913 target_flags
|= MASK_DEPRECATED_V8_INSNS
;
1915 /* V8PLUS requires V9 and makes no sense in 64-bit mode. */
1916 if (!TARGET_V9
|| TARGET_ARCH64
)
1917 target_flags
&= ~MASK_V8PLUS
;
1919 /* Don't use stack biasing in 32-bit mode. */
1921 target_flags
&= ~MASK_STACK_BIAS
;
1923 /* Use LRA instead of reload, unless otherwise instructed. */
1924 if (!(target_flags_explicit
& MASK_LRA
))
1925 target_flags
|= MASK_LRA
;
1927 /* Enable applicable errata workarounds for LEON3FT. */
1928 if (sparc_fix_ut699
|| sparc_fix_ut700
|| sparc_fix_gr712rc
)
1930 sparc_fix_b2bst
= 1;
1931 sparc_fix_lost_divsqrt
= 1;
1934 /* Disable FsMULd for the UT699 since it doesn't work correctly. */
1935 if (sparc_fix_ut699
)
1936 target_flags
&= ~MASK_FSMULD
;
1938 /* Supply a default value for align_functions. */
1939 if (flag_align_functions
&& !str_align_functions
)
1941 if (sparc_cpu
== PROCESSOR_ULTRASPARC
1942 || sparc_cpu
== PROCESSOR_ULTRASPARC3
1943 || sparc_cpu
== PROCESSOR_NIAGARA
1944 || sparc_cpu
== PROCESSOR_NIAGARA2
1945 || sparc_cpu
== PROCESSOR_NIAGARA3
1946 || sparc_cpu
== PROCESSOR_NIAGARA4
)
1947 str_align_functions
= "32";
1948 else if (sparc_cpu
== PROCESSOR_NIAGARA7
1949 || sparc_cpu
== PROCESSOR_M8
)
1950 str_align_functions
= "64";
1953 /* Validate PCC_STRUCT_RETURN. */
1954 if (flag_pcc_struct_return
== DEFAULT_PCC_STRUCT_RETURN
)
1955 flag_pcc_struct_return
= (TARGET_ARCH64
? 0 : 1);
1957 /* Only use .uaxword when compiling for a 64-bit target. */
1959 targetm
.asm_out
.unaligned_op
.di
= NULL
;
1961 /* Do various machine dependent initializations. */
1962 sparc_init_modes ();
1964 /* Set up function hooks. */
1965 init_machine_status
= sparc_init_machine_status
;
1970 case PROCESSOR_CYPRESS
:
1971 sparc_costs
= &cypress_costs
;
1974 case PROCESSOR_SPARCLITE
:
1975 case PROCESSOR_SUPERSPARC
:
1976 sparc_costs
= &supersparc_costs
;
1978 case PROCESSOR_F930
:
1979 case PROCESSOR_F934
:
1980 case PROCESSOR_HYPERSPARC
:
1981 case PROCESSOR_SPARCLITE86X
:
1982 sparc_costs
= &hypersparc_costs
;
1984 case PROCESSOR_LEON
:
1985 sparc_costs
= &leon_costs
;
1987 case PROCESSOR_LEON3
:
1988 case PROCESSOR_LEON3V7
:
1989 sparc_costs
= &leon3_costs
;
1991 case PROCESSOR_SPARCLET
:
1992 case PROCESSOR_TSC701
:
1993 sparc_costs
= &sparclet_costs
;
1996 case PROCESSOR_ULTRASPARC
:
1997 sparc_costs
= &ultrasparc_costs
;
1999 case PROCESSOR_ULTRASPARC3
:
2000 sparc_costs
= &ultrasparc3_costs
;
2002 case PROCESSOR_NIAGARA
:
2003 sparc_costs
= &niagara_costs
;
2005 case PROCESSOR_NIAGARA2
:
2006 sparc_costs
= &niagara2_costs
;
2008 case PROCESSOR_NIAGARA3
:
2009 sparc_costs
= &niagara3_costs
;
2011 case PROCESSOR_NIAGARA4
:
2012 sparc_costs
= &niagara4_costs
;
2014 case PROCESSOR_NIAGARA7
:
2015 sparc_costs
= &niagara7_costs
;
2018 sparc_costs
= &m8_costs
;
2020 case PROCESSOR_NATIVE
:
2024 if (sparc_memory_model
== SMM_DEFAULT
)
2026 /* Choose the memory model for the operating system. */
2027 enum sparc_memory_model_type os_default
= SUBTARGET_DEFAULT_MEMORY_MODEL
;
2028 if (os_default
!= SMM_DEFAULT
)
2029 sparc_memory_model
= os_default
;
2030 /* Choose the most relaxed model for the processor. */
2032 sparc_memory_model
= SMM_RMO
;
2033 else if (TARGET_LEON3
)
2034 sparc_memory_model
= SMM_TSO
;
2035 else if (TARGET_LEON
)
2036 sparc_memory_model
= SMM_SC
;
2038 sparc_memory_model
= SMM_PSO
;
2040 sparc_memory_model
= SMM_SC
;
2043 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
2044 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
2045 target_flags
|= MASK_LONG_DOUBLE_128
;
2048 if (TARGET_DEBUG_OPTIONS
)
2049 dump_target_flags ("Final target_flags", target_flags
);
2051 /* PARAM_SIMULTANEOUS_PREFETCHES is the number of prefetches that
2052 can run at the same time. More important, it is the threshold
2053 defining when additional prefetches will be dropped by the
2056 The UltraSPARC-III features a documented prefetch queue with a
2057 size of 8. Additional prefetches issued in the cpu are
2060 Niagara processors are different. In these processors prefetches
2061 are handled much like regular loads. The L1 miss buffer is 32
2062 entries, but prefetches start getting affected when 30 entries
2063 become occupied. That occupation could be a mix of regular loads
2064 and prefetches though. And that buffer is shared by all threads.
2065 Once the threshold is reached, if the core is running a single
2066 thread the prefetch will retry. If more than one thread is
2067 running, the prefetch will be dropped.
2069 All this makes it very difficult to determine how many
2070 simultaneous prefetches can be issued simultaneously, even in a
2071 single-threaded program. Experimental results show that setting
2072 this parameter to 32 works well when the number of threads is not
2074 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
2075 ((sparc_cpu
== PROCESSOR_ULTRASPARC
2076 || sparc_cpu
== PROCESSOR_NIAGARA
2077 || sparc_cpu
== PROCESSOR_NIAGARA2
2078 || sparc_cpu
== PROCESSOR_NIAGARA3
2079 || sparc_cpu
== PROCESSOR_NIAGARA4
)
2081 : (sparc_cpu
== PROCESSOR_ULTRASPARC3
2082 ? 8 : ((sparc_cpu
== PROCESSOR_NIAGARA7
2083 || sparc_cpu
== PROCESSOR_M8
)
2085 global_options
.x_param_values
,
2086 global_options_set
.x_param_values
);
2088 /* PARAM_L1_CACHE_LINE_SIZE is the size of the L1 cache line, in
2091 The Oracle SPARC Architecture (previously the UltraSPARC
2092 Architecture) specification states that when a PREFETCH[A]
2093 instruction is executed an implementation-specific amount of data
2094 is prefetched, and that it is at least 64 bytes long (aligned to
2097 However, this is not correct. The M7 (and implementations prior
2098 to that) does not guarantee a 64B prefetch into a cache if the
2099 line size is smaller. A single cache line is all that is ever
2100 prefetched. So for the M7, where the L1D$ has 32B lines and the
2101 L2D$ and L3 have 64B lines, a prefetch will prefetch 64B into the
2102 L2 and L3, but only 32B are brought into the L1D$. (Assuming it
2103 is a read_n prefetch, which is the only type which allocates to
2105 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
2106 (sparc_cpu
== PROCESSOR_M8
2108 global_options
.x_param_values
,
2109 global_options_set
.x_param_values
);
2111 /* PARAM_L1_CACHE_SIZE is the size of the L1D$ (most SPARC chips use
2112 Hardvard level-1 caches) in kilobytes. Both UltraSPARC and
2113 Niagara processors feature a L1D$ of 16KB. */
2114 maybe_set_param_value (PARAM_L1_CACHE_SIZE
,
2115 ((sparc_cpu
== PROCESSOR_ULTRASPARC
2116 || sparc_cpu
== PROCESSOR_ULTRASPARC3
2117 || sparc_cpu
== PROCESSOR_NIAGARA
2118 || sparc_cpu
== PROCESSOR_NIAGARA2
2119 || sparc_cpu
== PROCESSOR_NIAGARA3
2120 || sparc_cpu
== PROCESSOR_NIAGARA4
2121 || sparc_cpu
== PROCESSOR_NIAGARA7
2122 || sparc_cpu
== PROCESSOR_M8
)
2124 global_options
.x_param_values
,
2125 global_options_set
.x_param_values
);
2128 /* PARAM_L2_CACHE_SIZE is the size fo the L2 in kilobytes. Note
2129 that 512 is the default in params.def. */
2130 maybe_set_param_value (PARAM_L2_CACHE_SIZE
,
2131 ((sparc_cpu
== PROCESSOR_NIAGARA4
2132 || sparc_cpu
== PROCESSOR_M8
)
2133 ? 128 : (sparc_cpu
== PROCESSOR_NIAGARA7
2135 global_options
.x_param_values
,
2136 global_options_set
.x_param_values
);
2139 /* Disable save slot sharing for call-clobbered registers by default.
2140 The IRA sharing algorithm works on single registers only and this
2141 pessimizes for double floating-point registers. */
2142 if (!global_options_set
.x_flag_ira_share_save_slots
)
2143 flag_ira_share_save_slots
= 0;
2145 /* Only enable REE by default in 64-bit mode where it helps to eliminate
2146 redundant 32-to-64-bit extensions. */
2147 if (!global_options_set
.x_flag_ree
&& TARGET_ARCH32
)
2151 /* Miscellaneous utilities. */
2153 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
2154 or branch on register contents instructions. */
2157 v9_regcmp_p (enum rtx_code code
)
2159 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
2160 || code
== LE
|| code
== GT
);
2163 /* Nonzero if OP is a floating point constant which can
2164 be loaded into an integer register using a single
2165 sethi instruction. */
2170 if (GET_CODE (op
) == CONST_DOUBLE
)
2174 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), i
);
2175 return !SPARC_SIMM13_P (i
) && SPARC_SETHI_P (i
);
2181 /* Nonzero if OP is a floating point constant which can
2182 be loaded into an integer register using a single
2188 if (GET_CODE (op
) == CONST_DOUBLE
)
2192 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), i
);
2193 return SPARC_SIMM13_P (i
);
2199 /* Nonzero if OP is a floating point constant which can
2200 be loaded into an integer register using a high/losum
2201 instruction sequence. */
2204 fp_high_losum_p (rtx op
)
2206 /* The constraints calling this should only be in
2207 SFmode move insns, so any constant which cannot
2208 be moved using a single insn will do. */
2209 if (GET_CODE (op
) == CONST_DOUBLE
)
2213 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), i
);
2214 return !SPARC_SIMM13_P (i
) && !SPARC_SETHI_P (i
);
2220 /* Return true if the address of LABEL can be loaded by means of the
2221 mov{si,di}_pic_label_ref patterns in PIC mode. */
2224 can_use_mov_pic_label_ref (rtx label
)
2226 /* VxWorks does not impose a fixed gap between segments; the run-time
2227 gap can be different from the object-file gap. We therefore can't
2228 assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
2229 are absolutely sure that X is in the same segment as the GOT.
2230 Unfortunately, the flexibility of linker scripts means that we
2231 can't be sure of that in general, so assume that GOT-relative
2232 accesses are never valid on VxWorks. */
2233 if (TARGET_VXWORKS_RTP
)
2236 /* Similarly, if the label is non-local, it might end up being placed
2237 in a different section than the current one; now mov_pic_label_ref
2238 requires the label and the code to be in the same section. */
2239 if (LABEL_REF_NONLOCAL_P (label
))
2242 /* Finally, if we are reordering basic blocks and partition into hot
2243 and cold sections, this might happen for any label. */
2244 if (flag_reorder_blocks_and_partition
)
2250 /* Expand a move instruction. Return true if all work is done. */
2253 sparc_expand_move (machine_mode mode
, rtx
*operands
)
2255 /* Handle sets of MEM first. */
2256 if (GET_CODE (operands
[0]) == MEM
)
2258 /* 0 is a register (or a pair of registers) on SPARC. */
2259 if (register_or_zero_operand (operands
[1], mode
))
2262 if (!reload_in_progress
)
2264 operands
[0] = validize_mem (operands
[0]);
2265 operands
[1] = force_reg (mode
, operands
[1]);
2269 /* Fix up TLS cases. */
2271 && CONSTANT_P (operands
[1])
2272 && sparc_tls_referenced_p (operands
[1]))
2274 operands
[1] = sparc_legitimize_tls_address (operands
[1]);
2278 /* Fix up PIC cases. */
2279 if (flag_pic
&& CONSTANT_P (operands
[1]))
2281 if (pic_address_needs_scratch (operands
[1]))
2282 operands
[1] = sparc_legitimize_pic_address (operands
[1], NULL_RTX
);
2284 /* We cannot use the mov{si,di}_pic_label_ref patterns in all cases. */
2285 if ((GET_CODE (operands
[1]) == LABEL_REF
2286 && can_use_mov_pic_label_ref (operands
[1]))
2287 || (GET_CODE (operands
[1]) == CONST
2288 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
2289 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
2290 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == CONST_INT
2291 && can_use_mov_pic_label_ref (XEXP (XEXP (operands
[1], 0), 0))))
2295 emit_insn (gen_movsi_pic_label_ref (operands
[0], operands
[1]));
2301 emit_insn (gen_movdi_pic_label_ref (operands
[0], operands
[1]));
2306 if (symbolic_operand (operands
[1], mode
))
2309 = sparc_legitimize_pic_address (operands
[1],
2311 ? operands
[0] : NULL_RTX
);
2316 /* If we are trying to toss an integer constant into FP registers,
2317 or loading a FP or vector constant, force it into memory. */
2318 if (CONSTANT_P (operands
[1])
2319 && REG_P (operands
[0])
2320 && (SPARC_FP_REG_P (REGNO (operands
[0]))
2321 || SCALAR_FLOAT_MODE_P (mode
)
2322 || VECTOR_MODE_P (mode
)))
2324 /* emit_group_store will send such bogosity to us when it is
2325 not storing directly into memory. So fix this up to avoid
2326 crashes in output_constant_pool. */
2327 if (operands
[1] == const0_rtx
)
2328 operands
[1] = CONST0_RTX (mode
);
2330 /* We can clear or set to all-ones FP registers if TARGET_VIS, and
2331 always other regs. */
2332 if ((TARGET_VIS
|| REGNO (operands
[0]) < SPARC_FIRST_FP_REG
)
2333 && (const_zero_operand (operands
[1], mode
)
2334 || const_all_ones_operand (operands
[1], mode
)))
2337 if (REGNO (operands
[0]) < SPARC_FIRST_FP_REG
2338 /* We are able to build any SF constant in integer registers
2339 with at most 2 instructions. */
2341 /* And any DF constant in integer registers if needed. */
2342 || (mode
== DFmode
&& !can_create_pseudo_p ())))
2345 operands
[1] = force_const_mem (mode
, operands
[1]);
2346 if (!reload_in_progress
)
2347 operands
[1] = validize_mem (operands
[1]);
2351 /* Accept non-constants and valid constants unmodified. */
2352 if (!CONSTANT_P (operands
[1])
2353 || GET_CODE (operands
[1]) == HIGH
2354 || input_operand (operands
[1], mode
))
2360 /* All QImode constants require only one insn, so proceed. */
2365 sparc_emit_set_const32 (operands
[0], operands
[1]);
2369 /* input_operand should have filtered out 32-bit mode. */
2370 sparc_emit_set_const64 (operands
[0], operands
[1]);
2376 /* TImode isn't available in 32-bit mode. */
2377 split_double (operands
[1], &high
, &low
);
2378 emit_insn (gen_movdi (operand_subword (operands
[0], 0, 0, TImode
),
2380 emit_insn (gen_movdi (operand_subword (operands
[0], 1, 0, TImode
),
2392 /* Load OP1, a 32-bit constant, into OP0, a register.
2393 We know it can't be done in one insn when we get
2394 here, the move expander guarantees this. */
2397 sparc_emit_set_const32 (rtx op0
, rtx op1
)
2399 machine_mode mode
= GET_MODE (op0
);
2402 if (can_create_pseudo_p ())
2403 temp
= gen_reg_rtx (mode
);
2405 if (GET_CODE (op1
) == CONST_INT
)
2407 gcc_assert (!small_int_operand (op1
, mode
)
2408 && !const_high_operand (op1
, mode
));
2410 /* Emit them as real moves instead of a HIGH/LO_SUM,
2411 this way CSE can see everything and reuse intermediate
2412 values if it wants. */
2413 emit_insn (gen_rtx_SET (temp
, GEN_INT (INTVAL (op1
)
2414 & ~(HOST_WIDE_INT
) 0x3ff)));
2416 emit_insn (gen_rtx_SET (op0
,
2417 gen_rtx_IOR (mode
, temp
,
2418 GEN_INT (INTVAL (op1
) & 0x3ff))));
2422 /* A symbol, emit in the traditional way. */
2423 emit_insn (gen_rtx_SET (temp
, gen_rtx_HIGH (mode
, op1
)));
2424 emit_insn (gen_rtx_SET (op0
, gen_rtx_LO_SUM (mode
, temp
, op1
)));
2428 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
2429 If TEMP is nonzero, we are forbidden to use any other scratch
2430 registers. Otherwise, we are allowed to generate them as needed.
2432 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
2433 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
2436 sparc_emit_set_symbolic_const64 (rtx op0
, rtx op1
, rtx temp
)
2438 rtx cst
, temp1
, temp2
, temp3
, temp4
, temp5
;
2441 /* Deal with too large offsets. */
2442 if (GET_CODE (op1
) == CONST
2443 && GET_CODE (XEXP (op1
, 0)) == PLUS
2444 && CONST_INT_P (cst
= XEXP (XEXP (op1
, 0), 1))
2445 && trunc_int_for_mode (INTVAL (cst
), SImode
) != INTVAL (cst
))
2448 temp1
= gen_reg_rtx (DImode
);
2449 temp2
= gen_reg_rtx (DImode
);
2450 sparc_emit_set_const64 (temp2
, cst
);
2451 sparc_emit_set_symbolic_const64 (temp1
, XEXP (XEXP (op1
, 0), 0),
2453 emit_insn (gen_rtx_SET (op0
, gen_rtx_PLUS (DImode
, temp1
, temp2
)));
2457 if (temp
&& GET_MODE (temp
) == TImode
)
2460 temp
= gen_rtx_REG (DImode
, REGNO (temp
));
2463 /* SPARC-V9 code-model support. */
2464 switch (sparc_cmodel
)
2467 /* The range spanned by all instructions in the object is less
2468 than 2^31 bytes (2GB) and the distance from any instruction
2469 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
2470 than 2^31 bytes (2GB).
2472 The executable must be in the low 4TB of the virtual address
2475 sethi %hi(symbol), %temp1
2476 or %temp1, %lo(symbol), %reg */
2478 temp1
= temp
; /* op0 is allowed. */
2480 temp1
= gen_reg_rtx (DImode
);
2482 emit_insn (gen_rtx_SET (temp1
, gen_rtx_HIGH (DImode
, op1
)));
2483 emit_insn (gen_rtx_SET (op0
, gen_rtx_LO_SUM (DImode
, temp1
, op1
)));
2487 /* The range spanned by all instructions in the object is less
2488 than 2^31 bytes (2GB) and the distance from any instruction
2489 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
2490 than 2^31 bytes (2GB).
2492 The executable must be in the low 16TB of the virtual address
2495 sethi %h44(symbol), %temp1
2496 or %temp1, %m44(symbol), %temp2
2497 sllx %temp2, 12, %temp3
2498 or %temp3, %l44(symbol), %reg */
2503 temp3
= temp
; /* op0 is allowed. */
2507 temp1
= gen_reg_rtx (DImode
);
2508 temp2
= gen_reg_rtx (DImode
);
2509 temp3
= gen_reg_rtx (DImode
);
2512 emit_insn (gen_seth44 (temp1
, op1
));
2513 emit_insn (gen_setm44 (temp2
, temp1
, op1
));
2514 emit_insn (gen_rtx_SET (temp3
,
2515 gen_rtx_ASHIFT (DImode
, temp2
, GEN_INT (12))));
2516 emit_insn (gen_setl44 (op0
, temp3
, op1
));
2520 /* The range spanned by all instructions in the object is less
2521 than 2^31 bytes (2GB) and the distance from any instruction
2522 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
2523 than 2^31 bytes (2GB).
2525 The executable can be placed anywhere in the virtual address
2528 sethi %hh(symbol), %temp1
2529 sethi %lm(symbol), %temp2
2530 or %temp1, %hm(symbol), %temp3
2531 sllx %temp3, 32, %temp4
2532 or %temp4, %temp2, %temp5
2533 or %temp5, %lo(symbol), %reg */
2536 /* It is possible that one of the registers we got for operands[2]
2537 might coincide with that of operands[0] (which is why we made
2538 it TImode). Pick the other one to use as our scratch. */
2539 if (rtx_equal_p (temp
, op0
))
2541 gcc_assert (ti_temp
);
2542 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
2545 temp2
= temp
; /* op0 is _not_ allowed, see above. */
2552 temp1
= gen_reg_rtx (DImode
);
2553 temp2
= gen_reg_rtx (DImode
);
2554 temp3
= gen_reg_rtx (DImode
);
2555 temp4
= gen_reg_rtx (DImode
);
2556 temp5
= gen_reg_rtx (DImode
);
2559 emit_insn (gen_sethh (temp1
, op1
));
2560 emit_insn (gen_setlm (temp2
, op1
));
2561 emit_insn (gen_sethm (temp3
, temp1
, op1
));
2562 emit_insn (gen_rtx_SET (temp4
,
2563 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
2564 emit_insn (gen_rtx_SET (temp5
, gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2565 emit_insn (gen_setlo (op0
, temp5
, op1
));
2569 /* Old old old backwards compatibility kruft here.
2570 Essentially it is MEDLOW with a fixed 64-bit
2571 virtual base added to all data segment addresses.
2572 Text-segment stuff is computed like MEDANY, we can't
2573 reuse the code above because the relocation knobs
2576 Data segment: sethi %hi(symbol), %temp1
2577 add %temp1, EMBMEDANY_BASE_REG, %temp2
2578 or %temp2, %lo(symbol), %reg */
2579 if (data_segment_operand (op1
, GET_MODE (op1
)))
2583 temp1
= temp
; /* op0 is allowed. */
2588 temp1
= gen_reg_rtx (DImode
);
2589 temp2
= gen_reg_rtx (DImode
);
2592 emit_insn (gen_embmedany_sethi (temp1
, op1
));
2593 emit_insn (gen_embmedany_brsum (temp2
, temp1
));
2594 emit_insn (gen_embmedany_losum (op0
, temp2
, op1
));
2597 /* Text segment: sethi %uhi(symbol), %temp1
2598 sethi %hi(symbol), %temp2
2599 or %temp1, %ulo(symbol), %temp3
2600 sllx %temp3, 32, %temp4
2601 or %temp4, %temp2, %temp5
2602 or %temp5, %lo(symbol), %reg */
2607 /* It is possible that one of the registers we got for operands[2]
2608 might coincide with that of operands[0] (which is why we made
2609 it TImode). Pick the other one to use as our scratch. */
2610 if (rtx_equal_p (temp
, op0
))
2612 gcc_assert (ti_temp
);
2613 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
2616 temp2
= temp
; /* op0 is _not_ allowed, see above. */
2623 temp1
= gen_reg_rtx (DImode
);
2624 temp2
= gen_reg_rtx (DImode
);
2625 temp3
= gen_reg_rtx (DImode
);
2626 temp4
= gen_reg_rtx (DImode
);
2627 temp5
= gen_reg_rtx (DImode
);
2630 emit_insn (gen_embmedany_textuhi (temp1
, op1
));
2631 emit_insn (gen_embmedany_texthi (temp2
, op1
));
2632 emit_insn (gen_embmedany_textulo (temp3
, temp1
, op1
));
2633 emit_insn (gen_rtx_SET (temp4
,
2634 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
2635 emit_insn (gen_rtx_SET (temp5
, gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2636 emit_insn (gen_embmedany_textlo (op0
, temp5
, op1
));
2645 /* These avoid problems when cross compiling. If we do not
2646 go through all this hair then the optimizer will see
2647 invalid REG_EQUAL notes or in some cases none at all. */
2648 static rtx
gen_safe_HIGH64 (rtx
, HOST_WIDE_INT
);
2649 static rtx
gen_safe_SET64 (rtx
, HOST_WIDE_INT
);
2650 static rtx
gen_safe_OR64 (rtx
, HOST_WIDE_INT
);
2651 static rtx
gen_safe_XOR64 (rtx
, HOST_WIDE_INT
);
2653 /* The optimizer is not to assume anything about exactly
2654 which bits are set for a HIGH, they are unspecified.
2655 Unfortunately this leads to many missed optimizations
2656 during CSE. We mask out the non-HIGH bits, and matches
2657 a plain movdi, to alleviate this problem. */
2659 gen_safe_HIGH64 (rtx dest
, HOST_WIDE_INT val
)
2661 return gen_rtx_SET (dest
, GEN_INT (val
& ~(HOST_WIDE_INT
)0x3ff));
2665 gen_safe_SET64 (rtx dest
, HOST_WIDE_INT val
)
2667 return gen_rtx_SET (dest
, GEN_INT (val
));
2671 gen_safe_OR64 (rtx src
, HOST_WIDE_INT val
)
2673 return gen_rtx_IOR (DImode
, src
, GEN_INT (val
));
2677 gen_safe_XOR64 (rtx src
, HOST_WIDE_INT val
)
2679 return gen_rtx_XOR (DImode
, src
, GEN_INT (val
));
2682 /* Worker routines for 64-bit constant formation on arch64.
2683 One of the key things to be doing in these emissions is
2684 to create as many temp REGs as possible. This makes it
2685 possible for half-built constants to be used later when
2686 such values are similar to something required later on.
2687 Without doing this, the optimizer cannot see such
2690 static void sparc_emit_set_const64_quick1 (rtx
, rtx
,
2691 unsigned HOST_WIDE_INT
, int);
2694 sparc_emit_set_const64_quick1 (rtx op0
, rtx temp
,
2695 unsigned HOST_WIDE_INT low_bits
, int is_neg
)
2697 unsigned HOST_WIDE_INT high_bits
;
2700 high_bits
= (~low_bits
) & 0xffffffff;
2702 high_bits
= low_bits
;
2704 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
2707 emit_insn (gen_rtx_SET (op0
, gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2711 /* If we are XOR'ing with -1, then we should emit a one's complement
2712 instead. This way the combiner will notice logical operations
2713 such as ANDN later on and substitute. */
2714 if ((low_bits
& 0x3ff) == 0x3ff)
2716 emit_insn (gen_rtx_SET (op0
, gen_rtx_NOT (DImode
, temp
)));
2720 emit_insn (gen_rtx_SET (op0
,
2721 gen_safe_XOR64 (temp
,
2722 (-(HOST_WIDE_INT
)0x400
2723 | (low_bits
& 0x3ff)))));
2728 static void sparc_emit_set_const64_quick2 (rtx
, rtx
, unsigned HOST_WIDE_INT
,
2729 unsigned HOST_WIDE_INT
, int);
2732 sparc_emit_set_const64_quick2 (rtx op0
, rtx temp
,
2733 unsigned HOST_WIDE_INT high_bits
,
2734 unsigned HOST_WIDE_INT low_immediate
,
2739 if ((high_bits
& 0xfffffc00) != 0)
2741 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
2742 if ((high_bits
& ~0xfffffc00) != 0)
2743 emit_insn (gen_rtx_SET (op0
,
2744 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2750 emit_insn (gen_safe_SET64 (temp
, high_bits
));
2754 /* Now shift it up into place. */
2755 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, temp2
,
2756 GEN_INT (shift_count
))));
2758 /* If there is a low immediate part piece, finish up by
2759 putting that in as well. */
2760 if (low_immediate
!= 0)
2761 emit_insn (gen_rtx_SET (op0
, gen_safe_OR64 (op0
, low_immediate
)));
2764 static void sparc_emit_set_const64_longway (rtx
, rtx
, unsigned HOST_WIDE_INT
,
2765 unsigned HOST_WIDE_INT
);
2767 /* Full 64-bit constant decomposition. Even though this is the
2768 'worst' case, we still optimize a few things away. */
2770 sparc_emit_set_const64_longway (rtx op0
, rtx temp
,
2771 unsigned HOST_WIDE_INT high_bits
,
2772 unsigned HOST_WIDE_INT low_bits
)
2776 if (can_create_pseudo_p ())
2777 sub_temp
= gen_reg_rtx (DImode
);
2779 if ((high_bits
& 0xfffffc00) != 0)
2781 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
2782 if ((high_bits
& ~0xfffffc00) != 0)
2783 emit_insn (gen_rtx_SET (sub_temp
,
2784 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2790 emit_insn (gen_safe_SET64 (temp
, high_bits
));
2794 if (can_create_pseudo_p ())
2796 rtx temp2
= gen_reg_rtx (DImode
);
2797 rtx temp3
= gen_reg_rtx (DImode
);
2798 rtx temp4
= gen_reg_rtx (DImode
);
2800 emit_insn (gen_rtx_SET (temp4
, gen_rtx_ASHIFT (DImode
, sub_temp
,
2803 emit_insn (gen_safe_HIGH64 (temp2
, low_bits
));
2804 if ((low_bits
& ~0xfffffc00) != 0)
2806 emit_insn (gen_rtx_SET (temp3
,
2807 gen_safe_OR64 (temp2
, (low_bits
& 0x3ff))));
2808 emit_insn (gen_rtx_SET (op0
, gen_rtx_PLUS (DImode
, temp4
, temp3
)));
2812 emit_insn (gen_rtx_SET (op0
, gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2817 rtx low1
= GEN_INT ((low_bits
>> (32 - 12)) & 0xfff);
2818 rtx low2
= GEN_INT ((low_bits
>> (32 - 12 - 12)) & 0xfff);
2819 rtx low3
= GEN_INT ((low_bits
>> (32 - 12 - 12 - 8)) & 0x0ff);
2822 /* We are in the middle of reload, so this is really
2823 painful. However we do still make an attempt to
2824 avoid emitting truly stupid code. */
2825 if (low1
!= const0_rtx
)
2827 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, sub_temp
,
2828 GEN_INT (to_shift
))));
2829 emit_insn (gen_rtx_SET (op0
, gen_rtx_IOR (DImode
, op0
, low1
)));
2837 if (low2
!= const0_rtx
)
2839 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, sub_temp
,
2840 GEN_INT (to_shift
))));
2841 emit_insn (gen_rtx_SET (op0
, gen_rtx_IOR (DImode
, op0
, low2
)));
2849 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, sub_temp
,
2850 GEN_INT (to_shift
))));
2851 if (low3
!= const0_rtx
)
2852 emit_insn (gen_rtx_SET (op0
, gen_rtx_IOR (DImode
, op0
, low3
)));
2857 /* Analyze a 64-bit constant for certain properties. */
2858 static void analyze_64bit_constant (unsigned HOST_WIDE_INT
,
2859 unsigned HOST_WIDE_INT
,
2860 int *, int *, int *);
2863 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits
,
2864 unsigned HOST_WIDE_INT low_bits
,
2865 int *hbsp
, int *lbsp
, int *abbasp
)
2867 int lowest_bit_set
, highest_bit_set
, all_bits_between_are_set
;
2870 lowest_bit_set
= highest_bit_set
= -1;
2874 if ((lowest_bit_set
== -1)
2875 && ((low_bits
>> i
) & 1))
2877 if ((highest_bit_set
== -1)
2878 && ((high_bits
>> (32 - i
- 1)) & 1))
2879 highest_bit_set
= (64 - i
- 1);
2882 && ((highest_bit_set
== -1)
2883 || (lowest_bit_set
== -1)));
2889 if ((lowest_bit_set
== -1)
2890 && ((high_bits
>> i
) & 1))
2891 lowest_bit_set
= i
+ 32;
2892 if ((highest_bit_set
== -1)
2893 && ((low_bits
>> (32 - i
- 1)) & 1))
2894 highest_bit_set
= 32 - i
- 1;
2897 && ((highest_bit_set
== -1)
2898 || (lowest_bit_set
== -1)));
2900 /* If there are no bits set this should have gone out
2901 as one instruction! */
2902 gcc_assert (lowest_bit_set
!= -1 && highest_bit_set
!= -1);
2903 all_bits_between_are_set
= 1;
2904 for (i
= lowest_bit_set
; i
<= highest_bit_set
; i
++)
2908 if ((low_bits
& (1 << i
)) != 0)
2913 if ((high_bits
& (1 << (i
- 32))) != 0)
2916 all_bits_between_are_set
= 0;
2919 *hbsp
= highest_bit_set
;
2920 *lbsp
= lowest_bit_set
;
2921 *abbasp
= all_bits_between_are_set
;
2924 static int const64_is_2insns (unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
);
2927 const64_is_2insns (unsigned HOST_WIDE_INT high_bits
,
2928 unsigned HOST_WIDE_INT low_bits
)
2930 int highest_bit_set
, lowest_bit_set
, all_bits_between_are_set
;
2933 || high_bits
== 0xffffffff)
2936 analyze_64bit_constant (high_bits
, low_bits
,
2937 &highest_bit_set
, &lowest_bit_set
,
2938 &all_bits_between_are_set
);
2940 if ((highest_bit_set
== 63
2941 || lowest_bit_set
== 0)
2942 && all_bits_between_are_set
!= 0)
2945 if ((highest_bit_set
- lowest_bit_set
) < 21)
2951 static unsigned HOST_WIDE_INT
create_simple_focus_bits (unsigned HOST_WIDE_INT
,
2952 unsigned HOST_WIDE_INT
,
2955 static unsigned HOST_WIDE_INT
2956 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits
,
2957 unsigned HOST_WIDE_INT low_bits
,
2958 int lowest_bit_set
, int shift
)
2960 HOST_WIDE_INT hi
, lo
;
2962 if (lowest_bit_set
< 32)
2964 lo
= (low_bits
>> lowest_bit_set
) << shift
;
2965 hi
= ((high_bits
<< (32 - lowest_bit_set
)) << shift
);
2970 hi
= ((high_bits
>> (lowest_bit_set
- 32)) << shift
);
2972 gcc_assert (! (hi
& lo
));
2976 /* Here we are sure to be arch64 and this is an integer constant
2977 being loaded into a register. Emit the most efficient
2978 insn sequence possible. Detection of all the 1-insn cases
2979 has been done already. */
2981 sparc_emit_set_const64 (rtx op0
, rtx op1
)
2983 unsigned HOST_WIDE_INT high_bits
, low_bits
;
2984 int lowest_bit_set
, highest_bit_set
;
2985 int all_bits_between_are_set
;
2988 /* Sanity check that we know what we are working with. */
2989 gcc_assert (TARGET_ARCH64
2990 && (GET_CODE (op0
) == SUBREG
2991 || (REG_P (op0
) && ! SPARC_FP_REG_P (REGNO (op0
)))));
2993 if (! can_create_pseudo_p ())
2996 if (GET_CODE (op1
) != CONST_INT
)
2998 sparc_emit_set_symbolic_const64 (op0
, op1
, temp
);
3003 temp
= gen_reg_rtx (DImode
);
3005 high_bits
= ((INTVAL (op1
) >> 32) & 0xffffffff);
3006 low_bits
= (INTVAL (op1
) & 0xffffffff);
3008 /* low_bits bits 0 --> 31
3009 high_bits bits 32 --> 63 */
3011 analyze_64bit_constant (high_bits
, low_bits
,
3012 &highest_bit_set
, &lowest_bit_set
,
3013 &all_bits_between_are_set
);
3015 /* First try for a 2-insn sequence. */
3017 /* These situations are preferred because the optimizer can
3018 * do more things with them:
3020 * sllx %reg, shift, %reg
3022 * srlx %reg, shift, %reg
3023 * 3) mov some_small_const, %reg
3024 * sllx %reg, shift, %reg
3026 if (((highest_bit_set
== 63
3027 || lowest_bit_set
== 0)
3028 && all_bits_between_are_set
!= 0)
3029 || ((highest_bit_set
- lowest_bit_set
) < 12))
3031 HOST_WIDE_INT the_const
= -1;
3032 int shift
= lowest_bit_set
;
3034 if ((highest_bit_set
!= 63
3035 && lowest_bit_set
!= 0)
3036 || all_bits_between_are_set
== 0)
3039 create_simple_focus_bits (high_bits
, low_bits
,
3042 else if (lowest_bit_set
== 0)
3043 shift
= -(63 - highest_bit_set
);
3045 gcc_assert (SPARC_SIMM13_P (the_const
));
3046 gcc_assert (shift
!= 0);
3048 emit_insn (gen_safe_SET64 (temp
, the_const
));
3050 emit_insn (gen_rtx_SET (op0
, gen_rtx_ASHIFT (DImode
, temp
,
3053 emit_insn (gen_rtx_SET (op0
, gen_rtx_LSHIFTRT (DImode
, temp
,
3054 GEN_INT (-shift
))));
3058 /* Now a range of 22 or less bits set somewhere.
3059 * 1) sethi %hi(focus_bits), %reg
3060 * sllx %reg, shift, %reg
3061 * 2) sethi %hi(focus_bits), %reg
3062 * srlx %reg, shift, %reg
3064 if ((highest_bit_set
- lowest_bit_set
) < 21)
3066 unsigned HOST_WIDE_INT focus_bits
=
3067 create_simple_focus_bits (high_bits
, low_bits
,
3068 lowest_bit_set
, 10);
3070 gcc_assert (SPARC_SETHI_P (focus_bits
));
3071 gcc_assert (lowest_bit_set
!= 10);
3073 emit_insn (gen_safe_HIGH64 (temp
, focus_bits
));
3075 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
3076 if (lowest_bit_set
< 10)
3077 emit_insn (gen_rtx_SET (op0
,
3078 gen_rtx_LSHIFTRT (DImode
, temp
,
3079 GEN_INT (10 - lowest_bit_set
))));
3080 else if (lowest_bit_set
> 10)
3081 emit_insn (gen_rtx_SET (op0
,
3082 gen_rtx_ASHIFT (DImode
, temp
,
3083 GEN_INT (lowest_bit_set
- 10))));
3087 /* 1) sethi %hi(low_bits), %reg
3088 * or %reg, %lo(low_bits), %reg
3089 * 2) sethi %hi(~low_bits), %reg
3090 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
3093 || high_bits
== 0xffffffff)
3095 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
,
3096 (high_bits
== 0xffffffff));
3100 /* Now, try 3-insn sequences. */
3102 /* 1) sethi %hi(high_bits), %reg
3103 * or %reg, %lo(high_bits), %reg
3104 * sllx %reg, 32, %reg
3108 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, 0, 32);
3112 /* We may be able to do something quick
3113 when the constant is negated, so try that. */
3114 if (const64_is_2insns ((~high_bits
) & 0xffffffff,
3115 (~low_bits
) & 0xfffffc00))
3117 /* NOTE: The trailing bits get XOR'd so we need the
3118 non-negated bits, not the negated ones. */
3119 unsigned HOST_WIDE_INT trailing_bits
= low_bits
& 0x3ff;
3121 if ((((~high_bits
) & 0xffffffff) == 0
3122 && ((~low_bits
) & 0x80000000) == 0)
3123 || (((~high_bits
) & 0xffffffff) == 0xffffffff
3124 && ((~low_bits
) & 0x80000000) != 0))
3126 unsigned HOST_WIDE_INT fast_int
= (~low_bits
& 0xffffffff);
3128 if ((SPARC_SETHI_P (fast_int
)
3129 && (~high_bits
& 0xffffffff) == 0)
3130 || SPARC_SIMM13_P (fast_int
))
3131 emit_insn (gen_safe_SET64 (temp
, fast_int
));
3133 sparc_emit_set_const64 (temp
, GEN_INT (fast_int
));
3138 negated_const
= GEN_INT (((~low_bits
) & 0xfffffc00) |
3139 (((HOST_WIDE_INT
)((~high_bits
) & 0xffffffff))<<32));
3140 sparc_emit_set_const64 (temp
, negated_const
);
3143 /* If we are XOR'ing with -1, then we should emit a one's complement
3144 instead. This way the combiner will notice logical operations
3145 such as ANDN later on and substitute. */
3146 if (trailing_bits
== 0x3ff)
3148 emit_insn (gen_rtx_SET (op0
, gen_rtx_NOT (DImode
, temp
)));
3152 emit_insn (gen_rtx_SET (op0
,
3153 gen_safe_XOR64 (temp
,
3154 (-0x400 | trailing_bits
))));
3159 /* 1) sethi %hi(xxx), %reg
3160 * or %reg, %lo(xxx), %reg
3161 * sllx %reg, yyy, %reg
3163 * ??? This is just a generalized version of the low_bits==0
3164 * thing above, FIXME...
3166 if ((highest_bit_set
- lowest_bit_set
) < 32)
3168 unsigned HOST_WIDE_INT focus_bits
=
3169 create_simple_focus_bits (high_bits
, low_bits
,
3172 /* We can't get here in this state. */
3173 gcc_assert (highest_bit_set
>= 32 && lowest_bit_set
< 32);
3175 /* So what we know is that the set bits straddle the
3176 middle of the 64-bit word. */
3177 sparc_emit_set_const64_quick2 (op0
, temp
,
3183 /* 1) sethi %hi(high_bits), %reg
3184 * or %reg, %lo(high_bits), %reg
3185 * sllx %reg, 32, %reg
3186 * or %reg, low_bits, %reg
3188 if (SPARC_SIMM13_P (low_bits
) && ((int)low_bits
> 0))
3190 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_bits
, 32);
3194 /* The easiest way when all else fails, is full decomposition. */
3195 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
);
3198 /* Implement TARGET_FIXED_CONDITION_CODE_REGS. */
3201 sparc_fixed_condition_code_regs (unsigned int *p1
, unsigned int *p2
)
3203 *p1
= SPARC_ICC_REG
;
3204 *p2
= SPARC_FCC_REG
;
3208 /* Implement TARGET_MIN_ARITHMETIC_PRECISION. */
3211 sparc_min_arithmetic_precision (void)
3216 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
3217 return the mode to be used for the comparison. For floating-point,
3218 CCFP[E]mode is used. CCNZmode should be used when the first operand
3219 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
3220 processing is needed. */
3223 select_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
3225 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
3251 else if ((GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
3252 || GET_CODE (x
) == NEG
|| GET_CODE (x
) == ASHIFT
)
3255 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
3262 /* This is for the cmp<mode>_sne pattern. */
3263 if (GET_CODE (x
) == NOT
&& y
== constm1_rtx
)
3265 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
3271 /* This is for the [u]addvdi4_sp32 and [u]subvdi4_sp32 patterns. */
3272 if (!TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
3274 if (GET_CODE (y
) == UNSPEC
3275 && (XINT (y
, 1) == UNSPEC_ADDV
3276 || XINT (y
, 1) == UNSPEC_SUBV
3277 || XINT (y
, 1) == UNSPEC_NEGV
))
3283 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
3290 /* Emit the compare insn and return the CC reg for a CODE comparison
3291 with operands X and Y. */
3294 gen_compare_reg_1 (enum rtx_code code
, rtx x
, rtx y
)
3299 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
3302 mode
= SELECT_CC_MODE (code
, x
, y
);
3304 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
3305 fcc regs (cse can't tell they're really call clobbered regs and will
3306 remove a duplicate comparison even if there is an intervening function
3307 call - it will then try to reload the cc reg via an int reg which is why
3308 we need the movcc patterns). It is possible to provide the movcc
3309 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
3310 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
3311 to tell cse that CCFPE mode registers (even pseudos) are call
3314 /* ??? This is an experiment. Rather than making changes to cse which may
3315 or may not be easy/clean, we do our own cse. This is possible because
3316 we will generate hard registers. Cse knows they're call clobbered (it
3317 doesn't know the same thing about pseudos). If we guess wrong, no big
3318 deal, but if we win, great! */
3320 if (TARGET_V9
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
3321 #if 1 /* experiment */
3324 /* We cycle through the registers to ensure they're all exercised. */
3325 static int next_fcc_reg
= 0;
3326 /* Previous x,y for each fcc reg. */
3327 static rtx prev_args
[4][2];
3329 /* Scan prev_args for x,y. */
3330 for (reg
= 0; reg
< 4; reg
++)
3331 if (prev_args
[reg
][0] == x
&& prev_args
[reg
][1] == y
)
3336 prev_args
[reg
][0] = x
;
3337 prev_args
[reg
][1] = y
;
3338 next_fcc_reg
= (next_fcc_reg
+ 1) & 3;
3340 cc_reg
= gen_rtx_REG (mode
, reg
+ SPARC_FIRST_V9_FCC_REG
);
3343 cc_reg
= gen_reg_rtx (mode
);
3344 #endif /* ! experiment */
3345 else if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
3346 cc_reg
= gen_rtx_REG (mode
, SPARC_FCC_REG
);
3348 cc_reg
= gen_rtx_REG (mode
, SPARC_ICC_REG
);
3350 /* We shouldn't get there for TFmode if !TARGET_HARD_QUAD. If we do, this
3351 will only result in an unrecognizable insn so no point in asserting. */
3352 emit_insn (gen_rtx_SET (cc_reg
, gen_rtx_COMPARE (mode
, x
, y
)));
3358 /* Emit the compare insn and return the CC reg for the comparison in CMP. */
3361 gen_compare_reg (rtx cmp
)
3363 return gen_compare_reg_1 (GET_CODE (cmp
), XEXP (cmp
, 0), XEXP (cmp
, 1));
3366 /* This function is used for v9 only.
3367 DEST is the target of the Scc insn.
3368 CODE is the code for an Scc's comparison.
3369 X and Y are the values we compare.
3371 This function is needed to turn
3374 (gt (reg:CCX 100 %icc)
3378 (gt:DI (reg:CCX 100 %icc)
3381 IE: The instruction recognizer needs to see the mode of the comparison to
3382 find the right instruction. We could use "gt:DI" right in the
3383 define_expand, but leaving it out allows us to handle DI, SI, etc. */
3386 gen_v9_scc (rtx dest
, enum rtx_code compare_code
, rtx x
, rtx y
)
3389 && (GET_MODE (x
) == DImode
3390 || GET_MODE (dest
) == DImode
))
3393 /* Try to use the movrCC insns. */
3395 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
3397 && v9_regcmp_p (compare_code
))
3402 /* Special case for op0 != 0. This can be done with one instruction if
3405 if (compare_code
== NE
3406 && GET_MODE (dest
) == DImode
3407 && rtx_equal_p (op0
, dest
))
3409 emit_insn (gen_rtx_SET (dest
,
3410 gen_rtx_IF_THEN_ELSE (DImode
,
3411 gen_rtx_fmt_ee (compare_code
, DImode
,
3418 if (reg_overlap_mentioned_p (dest
, op0
))
3420 /* Handle the case where dest == x.
3421 We "early clobber" the result. */
3422 op0
= gen_reg_rtx (GET_MODE (x
));
3423 emit_move_insn (op0
, x
);
3426 emit_insn (gen_rtx_SET (dest
, const0_rtx
));
3427 if (GET_MODE (op0
) != DImode
)
3429 temp
= gen_reg_rtx (DImode
);
3430 convert_move (temp
, op0
, 0);
3434 emit_insn (gen_rtx_SET (dest
,
3435 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
3436 gen_rtx_fmt_ee (compare_code
, DImode
,
3444 x
= gen_compare_reg_1 (compare_code
, x
, y
);
3447 emit_insn (gen_rtx_SET (dest
, const0_rtx
));
3448 emit_insn (gen_rtx_SET (dest
,
3449 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
3450 gen_rtx_fmt_ee (compare_code
,
3451 GET_MODE (x
), x
, y
),
3452 const1_rtx
, dest
)));
3458 /* Emit an scc insn. For seq, sne, sgeu, and sltu, we can do this
3459 without jumps using the addx/subx instructions. */
3462 emit_scc_insn (rtx operands
[])
3468 /* The quad-word fp compare library routines all return nonzero to indicate
3469 true, which is different from the equivalent libgcc routines, so we must
3470 handle them specially here. */
3471 if (GET_MODE (operands
[2]) == TFmode
&& ! TARGET_HARD_QUAD
)
3473 operands
[1] = sparc_emit_float_lib_cmp (operands
[2], operands
[3],
3474 GET_CODE (operands
[1]));
3475 operands
[2] = XEXP (operands
[1], 0);
3476 operands
[3] = XEXP (operands
[1], 1);
3479 code
= GET_CODE (operands
[1]);
3482 mode
= GET_MODE (x
);
3484 /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has
3485 more applications). The exception to this is "reg != 0" which can
3486 be done in one instruction on v9 (so we do it). */
3487 if ((code
== EQ
|| code
== NE
) && (mode
== SImode
|| mode
== DImode
))
3489 if (y
!= const0_rtx
)
3490 x
= force_reg (mode
, gen_rtx_XOR (mode
, x
, y
));
3492 rtx pat
= gen_rtx_SET (operands
[0],
3493 gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
3496 /* If we can use addx/subx or addxc, add a clobber for CC. */
3497 if (mode
== SImode
|| (code
== NE
&& TARGET_VIS3
))
3500 = gen_rtx_CLOBBER (VOIDmode
,
3501 gen_rtx_REG (mode
== SImode
? CCmode
: CCXmode
,
3503 pat
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, pat
, clobber
));
3510 /* We can do LTU in DImode using the addxc instruction with VIS3. */
3513 && !((code
== LTU
|| code
== GTU
) && TARGET_VIS3
)
3514 && gen_v9_scc (operands
[0], code
, x
, y
))
3517 /* We can do LTU and GEU using the addx/subx instructions too. And
3518 for GTU/LEU, if both operands are registers swap them and fall
3519 back to the easy case. */
3520 if (code
== GTU
|| code
== LEU
)
3522 if ((GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
3523 && (GET_CODE (y
) == REG
|| GET_CODE (y
) == SUBREG
))
3528 code
= swap_condition (code
);
3532 if (code
== LTU
|| code
== GEU
)
3534 emit_insn (gen_rtx_SET (operands
[0],
3535 gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
3536 gen_compare_reg_1 (code
, x
, y
),
3541 /* All the posibilities to use addx/subx based sequences has been
3542 exhausted, try for a 3 instruction sequence using v9 conditional
3544 if (TARGET_V9
&& gen_v9_scc (operands
[0], code
, x
, y
))
3547 /* Nope, do branches. */
3551 /* Emit a conditional jump insn for the v9 architecture using comparison code
3552 CODE and jump target LABEL.
3553 This function exists to take advantage of the v9 brxx insns. */
3556 emit_v9_brxx_insn (enum rtx_code code
, rtx op0
, rtx label
)
3558 emit_jump_insn (gen_rtx_SET (pc_rtx
,
3559 gen_rtx_IF_THEN_ELSE (VOIDmode
,
3560 gen_rtx_fmt_ee (code
, GET_MODE (op0
),
3562 gen_rtx_LABEL_REF (VOIDmode
, label
),
3566 /* Emit a conditional jump insn for the UA2011 architecture using
3567 comparison code CODE and jump target LABEL. This function exists
3568 to take advantage of the UA2011 Compare and Branch insns. */
3571 emit_cbcond_insn (enum rtx_code code
, rtx op0
, rtx op1
, rtx label
)
3575 if_then_else
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
3576 gen_rtx_fmt_ee(code
, GET_MODE(op0
),
3578 gen_rtx_LABEL_REF (VOIDmode
, label
),
3581 emit_jump_insn (gen_rtx_SET (pc_rtx
, if_then_else
));
3585 emit_conditional_branch_insn (rtx operands
[])
3587 /* The quad-word fp compare library routines all return nonzero to indicate
3588 true, which is different from the equivalent libgcc routines, so we must
3589 handle them specially here. */
3590 if (GET_MODE (operands
[1]) == TFmode
&& ! TARGET_HARD_QUAD
)
3592 operands
[0] = sparc_emit_float_lib_cmp (operands
[1], operands
[2],
3593 GET_CODE (operands
[0]));
3594 operands
[1] = XEXP (operands
[0], 0);
3595 operands
[2] = XEXP (operands
[0], 1);
3598 /* If we can tell early on that the comparison is against a constant
3599 that won't fit in the 5-bit signed immediate field of a cbcond,
3600 use one of the other v9 conditional branch sequences. */
3602 && GET_CODE (operands
[1]) == REG
3603 && (GET_MODE (operands
[1]) == SImode
3604 || (TARGET_ARCH64
&& GET_MODE (operands
[1]) == DImode
))
3605 && (GET_CODE (operands
[2]) != CONST_INT
3606 || SPARC_SIMM5_P (INTVAL (operands
[2]))))
3608 emit_cbcond_insn (GET_CODE (operands
[0]), operands
[1], operands
[2], operands
[3]);
3612 if (TARGET_ARCH64
&& operands
[2] == const0_rtx
3613 && GET_CODE (operands
[1]) == REG
3614 && GET_MODE (operands
[1]) == DImode
)
3616 emit_v9_brxx_insn (GET_CODE (operands
[0]), operands
[1], operands
[3]);
3620 operands
[1] = gen_compare_reg (operands
[0]);
3621 operands
[2] = const0_rtx
;
3622 operands
[0] = gen_rtx_fmt_ee (GET_CODE (operands
[0]), VOIDmode
,
3623 operands
[1], operands
[2]);
3624 emit_jump_insn (gen_cbranchcc4 (operands
[0], operands
[1], operands
[2],
3629 /* Generate a DFmode part of a hard TFmode register.
3630 REG is the TFmode hard register, LOW is 1 for the
3631 low 64bit of the register and 0 otherwise.
3634 gen_df_reg (rtx reg
, int low
)
3636 int regno
= REGNO (reg
);
3638 if ((WORDS_BIG_ENDIAN
== 0) ^ (low
!= 0))
3639 regno
+= (TARGET_ARCH64
&& SPARC_INT_REG_P (regno
)) ? 1 : 2;
3640 return gen_rtx_REG (DFmode
, regno
);
3643 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
3644 Unlike normal calls, TFmode operands are passed by reference. It is
3645 assumed that no more than 3 operands are required. */
3648 emit_soft_tfmode_libcall (const char *func_name
, int nargs
, rtx
*operands
)
3650 rtx ret_slot
= NULL
, arg
[3], func_sym
;
3653 /* We only expect to be called for conversions, unary, and binary ops. */
3654 gcc_assert (nargs
== 2 || nargs
== 3);
3656 for (i
= 0; i
< nargs
; ++i
)
3658 rtx this_arg
= operands
[i
];
3661 /* TFmode arguments and return values are passed by reference. */
3662 if (GET_MODE (this_arg
) == TFmode
)
3664 int force_stack_temp
;
3666 force_stack_temp
= 0;
3667 if (TARGET_BUGGY_QP_LIB
&& i
== 0)
3668 force_stack_temp
= 1;
3670 if (GET_CODE (this_arg
) == MEM
3671 && ! force_stack_temp
)
3673 tree expr
= MEM_EXPR (this_arg
);
3675 mark_addressable (expr
);
3676 this_arg
= XEXP (this_arg
, 0);
3678 else if (CONSTANT_P (this_arg
)
3679 && ! force_stack_temp
)
3681 this_slot
= force_const_mem (TFmode
, this_arg
);
3682 this_arg
= XEXP (this_slot
, 0);
3686 this_slot
= assign_stack_temp (TFmode
, GET_MODE_SIZE (TFmode
));
3688 /* Operand 0 is the return value. We'll copy it out later. */
3690 emit_move_insn (this_slot
, this_arg
);
3692 ret_slot
= this_slot
;
3694 this_arg
= XEXP (this_slot
, 0);
3701 func_sym
= gen_rtx_SYMBOL_REF (Pmode
, func_name
);
3703 if (GET_MODE (operands
[0]) == TFmode
)
3706 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
,
3707 arg
[0], GET_MODE (arg
[0]),
3708 arg
[1], GET_MODE (arg
[1]));
3710 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
,
3711 arg
[0], GET_MODE (arg
[0]),
3712 arg
[1], GET_MODE (arg
[1]),
3713 arg
[2], GET_MODE (arg
[2]));
3716 emit_move_insn (operands
[0], ret_slot
);
3722 gcc_assert (nargs
== 2);
3724 ret
= emit_library_call_value (func_sym
, operands
[0], LCT_NORMAL
,
3725 GET_MODE (operands
[0]),
3726 arg
[1], GET_MODE (arg
[1]));
3728 if (ret
!= operands
[0])
3729 emit_move_insn (operands
[0], ret
);
3733 /* Expand soft-float TFmode calls to sparc abi routines. */
3736 emit_soft_tfmode_binop (enum rtx_code code
, rtx
*operands
)
3758 emit_soft_tfmode_libcall (func
, 3, operands
);
3762 emit_soft_tfmode_unop (enum rtx_code code
, rtx
*operands
)
3766 gcc_assert (code
== SQRT
);
3769 emit_soft_tfmode_libcall (func
, 2, operands
);
3773 emit_soft_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
3780 switch (GET_MODE (operands
[1]))
3793 case FLOAT_TRUNCATE
:
3794 switch (GET_MODE (operands
[0]))
3808 switch (GET_MODE (operands
[1]))
3813 operands
[1] = gen_rtx_SIGN_EXTEND (DImode
, operands
[1]);
3823 case UNSIGNED_FLOAT
:
3824 switch (GET_MODE (operands
[1]))
3829 operands
[1] = gen_rtx_ZERO_EXTEND (DImode
, operands
[1]);
3840 switch (GET_MODE (operands
[0]))
3854 switch (GET_MODE (operands
[0]))
3871 emit_soft_tfmode_libcall (func
, 2, operands
);
3874 /* Expand a hard-float tfmode operation. All arguments must be in
3878 emit_hard_tfmode_operation (enum rtx_code code
, rtx
*operands
)
3882 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
3884 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
3885 op
= gen_rtx_fmt_e (code
, GET_MODE (operands
[0]), operands
[1]);
3889 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
3890 operands
[2] = force_reg (GET_MODE (operands
[2]), operands
[2]);
3891 op
= gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
3892 operands
[1], operands
[2]);
3895 if (register_operand (operands
[0], VOIDmode
))
3898 dest
= gen_reg_rtx (GET_MODE (operands
[0]));
3900 emit_insn (gen_rtx_SET (dest
, op
));
3902 if (dest
!= operands
[0])
3903 emit_move_insn (operands
[0], dest
);
3907 emit_tfmode_binop (enum rtx_code code
, rtx
*operands
)
3909 if (TARGET_HARD_QUAD
)
3910 emit_hard_tfmode_operation (code
, operands
);
3912 emit_soft_tfmode_binop (code
, operands
);
3916 emit_tfmode_unop (enum rtx_code code
, rtx
*operands
)
3918 if (TARGET_HARD_QUAD
)
3919 emit_hard_tfmode_operation (code
, operands
);
3921 emit_soft_tfmode_unop (code
, operands
);
3925 emit_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
3927 if (TARGET_HARD_QUAD
)
3928 emit_hard_tfmode_operation (code
, operands
);
3930 emit_soft_tfmode_cvt (code
, operands
);
3933 /* Return nonzero if a branch/jump/call instruction will be emitting
3934 nop into its delay slot. */
3937 empty_delay_slot (rtx_insn
*insn
)
3941 /* If no previous instruction (should not happen), return true. */
3942 if (PREV_INSN (insn
) == NULL
)
3945 seq
= NEXT_INSN (PREV_INSN (insn
));
3946 if (GET_CODE (PATTERN (seq
)) == SEQUENCE
)
3952 /* Return nonzero if we should emit a nop after a cbcond instruction.
3953 The cbcond instruction does not have a delay slot, however there is
3954 a severe performance penalty if a control transfer appears right
3955 after a cbcond. Therefore we emit a nop when we detect this
3959 emit_cbcond_nop (rtx_insn
*insn
)
3961 rtx next
= next_active_insn (insn
);
3966 if (NONJUMP_INSN_P (next
)
3967 && GET_CODE (PATTERN (next
)) == SEQUENCE
)
3968 next
= XVECEXP (PATTERN (next
), 0, 0);
3969 else if (CALL_P (next
)
3970 && GET_CODE (PATTERN (next
)) == PARALLEL
)
3972 rtx delay
= XVECEXP (PATTERN (next
), 0, 1);
3974 if (GET_CODE (delay
) == RETURN
)
3976 /* It's a sibling call. Do not emit the nop if we're going
3977 to emit something other than the jump itself as the first
3978 instruction of the sibcall sequence. */
3979 if (sparc_leaf_function_p
|| TARGET_FLAT
)
3984 if (NONJUMP_INSN_P (next
))
3990 /* Return nonzero if TRIAL can go into the call delay slot. */
3993 eligible_for_call_delay (rtx_insn
*trial
)
3997 if (get_attr_in_branch_delay (trial
) == IN_BRANCH_DELAY_FALSE
)
4001 call __tls_get_addr, %tgd_call (foo)
4002 add %l7, %o0, %o0, %tgd_add (foo)
4003 while Sun as/ld does not. */
4004 if (TARGET_GNU_TLS
|| !TARGET_TLS
)
4007 pat
= PATTERN (trial
);
4009 /* We must reject tgd_add{32|64}, i.e.
4010 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD)))
4011 and tldm_add{32|64}, i.e.
4012 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM)))
4014 if (GET_CODE (pat
) == SET
4015 && GET_CODE (SET_SRC (pat
)) == PLUS
)
4017 rtx unspec
= XEXP (SET_SRC (pat
), 1);
4019 if (GET_CODE (unspec
) == UNSPEC
4020 && (XINT (unspec
, 1) == UNSPEC_TLSGD
4021 || XINT (unspec
, 1) == UNSPEC_TLSLDM
))
4028 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
4029 instruction. RETURN_P is true if the v9 variant 'return' is to be
4030 considered in the test too.
4032 TRIAL must be a SET whose destination is a REG appropriate for the
4033 'restore' instruction or, if RETURN_P is true, for the 'return'
4037 eligible_for_restore_insn (rtx trial
, bool return_p
)
4039 rtx pat
= PATTERN (trial
);
4040 rtx src
= SET_SRC (pat
);
4041 bool src_is_freg
= false;
4044 /* Since we now can do moves between float and integer registers when
4045 VIS3 is enabled, we have to catch this case. We can allow such
4046 moves when doing a 'return' however. */
4048 if (GET_CODE (src_reg
) == SUBREG
)
4049 src_reg
= SUBREG_REG (src_reg
);
4050 if (GET_CODE (src_reg
) == REG
4051 && SPARC_FP_REG_P (REGNO (src_reg
)))
4054 /* The 'restore src,%g0,dest' pattern for word mode and below. */
4055 if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
4056 && arith_operand (src
, GET_MODE (src
))
4060 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
4062 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
4065 /* The 'restore src,%g0,dest' pattern for double-word mode. */
4066 else if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
4067 && arith_double_operand (src
, GET_MODE (src
))
4069 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
4071 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
4072 else if (! TARGET_FPU
&& register_operand (src
, SFmode
))
4075 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
4076 else if (! TARGET_FPU
&& TARGET_ARCH64
&& register_operand (src
, DFmode
))
4079 /* If we have the 'return' instruction, anything that does not use
4080 local or output registers and can go into a delay slot wins. */
4081 else if (return_p
&& TARGET_V9
&& !epilogue_renumber (&pat
, 1))
4084 /* The 'restore src1,src2,dest' pattern for SImode. */
4085 else if (GET_CODE (src
) == PLUS
4086 && register_operand (XEXP (src
, 0), SImode
)
4087 && arith_operand (XEXP (src
, 1), SImode
))
4090 /* The 'restore src1,src2,dest' pattern for DImode. */
4091 else if (GET_CODE (src
) == PLUS
4092 && register_operand (XEXP (src
, 0), DImode
)
4093 && arith_double_operand (XEXP (src
, 1), DImode
))
4096 /* The 'restore src1,%lo(src2),dest' pattern. */
4097 else if (GET_CODE (src
) == LO_SUM
4098 && ! TARGET_CM_MEDMID
4099 && ((register_operand (XEXP (src
, 0), SImode
)
4100 && immediate_operand (XEXP (src
, 1), SImode
))
4102 && register_operand (XEXP (src
, 0), DImode
)
4103 && immediate_operand (XEXP (src
, 1), DImode
))))
4106 /* The 'restore src,src,dest' pattern. */
4107 else if (GET_CODE (src
) == ASHIFT
4108 && (register_operand (XEXP (src
, 0), SImode
)
4109 || register_operand (XEXP (src
, 0), DImode
))
4110 && XEXP (src
, 1) == const1_rtx
)
4116 /* Return nonzero if TRIAL can go into the function return's delay slot. */
4119 eligible_for_return_delay (rtx_insn
*trial
)
4124 /* If the function uses __builtin_eh_return, the eh_return machinery
4125 occupies the delay slot. */
4126 if (crtl
->calls_eh_return
)
4129 if (get_attr_in_branch_delay (trial
) == IN_BRANCH_DELAY_FALSE
)
4132 /* In the case of a leaf or flat function, anything can go into the slot. */
4133 if (sparc_leaf_function_p
|| TARGET_FLAT
)
4136 if (!NONJUMP_INSN_P (trial
))
4139 pat
= PATTERN (trial
);
4140 if (GET_CODE (pat
) == PARALLEL
)
4146 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
4148 rtx expr
= XVECEXP (pat
, 0, i
);
4149 if (GET_CODE (expr
) != SET
)
4151 if (GET_CODE (SET_DEST (expr
)) != REG
)
4153 regno
= REGNO (SET_DEST (expr
));
4154 if (regno
>= 8 && regno
< 24)
4157 return !epilogue_renumber (&pat
, 1);
4160 if (GET_CODE (pat
) != SET
)
4163 if (GET_CODE (SET_DEST (pat
)) != REG
)
4166 regno
= REGNO (SET_DEST (pat
));
4168 /* Otherwise, only operations which can be done in tandem with
4169 a `restore' or `return' insn can go into the delay slot. */
4170 if (regno
>= 8 && regno
< 24)
4173 /* If this instruction sets up floating point register and we have a return
4174 instruction, it can probably go in. But restore will not work
4176 if (! SPARC_INT_REG_P (regno
))
4177 return TARGET_V9
&& !epilogue_renumber (&pat
, 1);
4179 return eligible_for_restore_insn (trial
, true);
4182 /* Return nonzero if TRIAL can go into the sibling call's delay slot. */
4185 eligible_for_sibcall_delay (rtx_insn
*trial
)
4189 if (get_attr_in_branch_delay (trial
) == IN_BRANCH_DELAY_FALSE
)
4192 if (!NONJUMP_INSN_P (trial
))
4195 pat
= PATTERN (trial
);
4197 if (sparc_leaf_function_p
|| TARGET_FLAT
)
4199 /* If the tail call is done using the call instruction,
4200 we have to restore %o7 in the delay slot. */
4201 if (LEAF_SIBCALL_SLOT_RESERVED_P
)
4204 /* %g1 is used to build the function address */
4205 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 1), pat
))
4211 if (GET_CODE (pat
) != SET
)
4214 /* Otherwise, only operations which can be done in tandem with
4215 a `restore' insn can go into the delay slot. */
4216 if (GET_CODE (SET_DEST (pat
)) != REG
4217 || (REGNO (SET_DEST (pat
)) >= 8 && REGNO (SET_DEST (pat
)) < 24)
4218 || ! SPARC_INT_REG_P (REGNO (SET_DEST (pat
))))
4221 /* If it mentions %o7, it can't go in, because sibcall will clobber it
4223 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 15), pat
))
4226 return eligible_for_restore_insn (trial
, false);
4229 /* Determine if it's legal to put X into the constant pool. This
4230 is not possible if X contains the address of a symbol that is
4231 not constant (TLS) or not known at final link time (PIC). */
4234 sparc_cannot_force_const_mem (machine_mode mode
, rtx x
)
4236 switch (GET_CODE (x
))
4239 case CONST_WIDE_INT
:
4242 /* Accept all non-symbolic constants. */
4246 /* Labels are OK iff we are non-PIC. */
4247 return flag_pic
!= 0;
4250 /* 'Naked' TLS symbol references are never OK,
4251 non-TLS symbols are OK iff we are non-PIC. */
4252 if (SYMBOL_REF_TLS_MODEL (x
))
4255 return flag_pic
!= 0;
4258 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0));
4261 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0))
4262 || sparc_cannot_force_const_mem (mode
, XEXP (x
, 1));
4270 /* Global Offset Table support. */
4271 static GTY(()) rtx got_helper_rtx
= NULL_RTX
;
4272 static GTY(()) rtx global_offset_table_rtx
= NULL_RTX
;
4274 /* Return the SYMBOL_REF for the Global Offset Table. */
4276 static GTY(()) rtx sparc_got_symbol
= NULL_RTX
;
4281 if (!sparc_got_symbol
)
4282 sparc_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
4284 return sparc_got_symbol
;
4287 /* Ensure that we are not using patterns that are not OK with PIC. */
4297 op
= recog_data
.operand
[i
];
4298 gcc_assert (GET_CODE (op
) != SYMBOL_REF
4299 && (GET_CODE (op
) != CONST
4300 || (GET_CODE (XEXP (op
, 0)) == MINUS
4301 && XEXP (XEXP (op
, 0), 0) == sparc_got ()
4302 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST
)));
4310 /* Return true if X is an address which needs a temporary register when
4311 reloaded while generating PIC code. */
4314 pic_address_needs_scratch (rtx x
)
4316 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
4317 if (GET_CODE (x
) == CONST
4318 && GET_CODE (XEXP (x
, 0)) == PLUS
4319 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
4320 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4321 && !SMALL_INT (XEXP (XEXP (x
, 0), 1)))
4327 /* Determine if a given RTX is a valid constant. We already know this
4328 satisfies CONSTANT_P. */
4331 sparc_legitimate_constant_p (machine_mode mode
, rtx x
)
4333 switch (GET_CODE (x
))
4337 if (sparc_tls_referenced_p (x
))
4342 /* Floating point constants are generally not ok.
4343 The only exception is 0.0 and all-ones in VIS. */
4345 && SCALAR_FLOAT_MODE_P (mode
)
4346 && (const_zero_operand (x
, mode
)
4347 || const_all_ones_operand (x
, mode
)))
4353 /* Vector constants are generally not ok.
4354 The only exception is 0 or -1 in VIS. */
4356 && (const_zero_operand (x
, mode
)
4357 || const_all_ones_operand (x
, mode
)))
4369 /* Determine if a given RTX is a valid constant address. */
4372 constant_address_p (rtx x
)
4374 switch (GET_CODE (x
))
4382 if (flag_pic
&& pic_address_needs_scratch (x
))
4384 return sparc_legitimate_constant_p (Pmode
, x
);
4387 return !flag_pic
&& sparc_legitimate_constant_p (Pmode
, x
);
4394 /* Nonzero if the constant value X is a legitimate general operand
4395 when generating PIC code. It is given that flag_pic is on and
4396 that X satisfies CONSTANT_P. */
4399 legitimate_pic_operand_p (rtx x
)
4401 if (pic_address_needs_scratch (x
))
4403 if (sparc_tls_referenced_p (x
))
4408 /* Return true if X is a representation of the PIC register. */
4411 sparc_pic_register_p (rtx x
)
4413 if (!REG_P (x
) || !pic_offset_table_rtx
)
4416 if (x
== pic_offset_table_rtx
)
4419 if (!HARD_REGISTER_P (pic_offset_table_rtx
)
4420 && (HARD_REGISTER_P (x
) || lra_in_progress
)
4421 && ORIGINAL_REGNO (x
) == REGNO (pic_offset_table_rtx
))
4427 #define RTX_OK_FOR_OFFSET_P(X, MODE) \
4429 && INTVAL (X) >= -0x1000 \
4430 && INTVAL (X) <= (0x1000 - GET_MODE_SIZE (MODE)))
4432 #define RTX_OK_FOR_OLO10_P(X, MODE) \
4434 && INTVAL (X) >= -0x1000 \
4435 && INTVAL (X) <= (0xc00 - GET_MODE_SIZE (MODE)))
4437 /* Handle the TARGET_LEGITIMATE_ADDRESS_P target hook.
4439 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
4440 ordinarily. This changes a bit when generating PIC. */
4443 sparc_legitimate_address_p (machine_mode mode
, rtx addr
, bool strict
)
4445 rtx rs1
= NULL
, rs2
= NULL
, imm1
= NULL
;
4447 if (REG_P (addr
) || GET_CODE (addr
) == SUBREG
)
4449 else if (GET_CODE (addr
) == PLUS
)
4451 rs1
= XEXP (addr
, 0);
4452 rs2
= XEXP (addr
, 1);
4454 /* Canonicalize. REG comes first, if there are no regs,
4455 LO_SUM comes first. */
4457 && GET_CODE (rs1
) != SUBREG
4459 || GET_CODE (rs2
) == SUBREG
4460 || (GET_CODE (rs2
) == LO_SUM
&& GET_CODE (rs1
) != LO_SUM
)))
4462 rs1
= XEXP (addr
, 1);
4463 rs2
= XEXP (addr
, 0);
4467 && sparc_pic_register_p (rs1
)
4469 && GET_CODE (rs2
) != SUBREG
4470 && GET_CODE (rs2
) != LO_SUM
4471 && GET_CODE (rs2
) != MEM
4472 && !(GET_CODE (rs2
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs2
))
4473 && (! symbolic_operand (rs2
, VOIDmode
) || mode
== Pmode
)
4474 && (GET_CODE (rs2
) != CONST_INT
|| SMALL_INT (rs2
)))
4476 || GET_CODE (rs1
) == SUBREG
)
4477 && RTX_OK_FOR_OFFSET_P (rs2
, mode
)))
4482 else if ((REG_P (rs1
) || GET_CODE (rs1
) == SUBREG
)
4483 && (REG_P (rs2
) || GET_CODE (rs2
) == SUBREG
))
4485 /* We prohibit REG + REG for TFmode when there are no quad move insns
4486 and we consequently need to split. We do this because REG+REG
4487 is not an offsettable address. If we get the situation in reload
4488 where source and destination of a movtf pattern are both MEMs with
4489 REG+REG address, then only one of them gets converted to an
4490 offsettable address. */
4492 && ! (TARGET_ARCH64
&& TARGET_HARD_QUAD
))
4495 /* Likewise for TImode, but in all cases. */
4499 /* We prohibit REG + REG on ARCH32 if not optimizing for
4500 DFmode/DImode because then mem_min_alignment is likely to be zero
4501 after reload and the forced split would lack a matching splitter
4503 if (TARGET_ARCH32
&& !optimize
4504 && (mode
== DFmode
|| mode
== DImode
))
4507 else if (USE_AS_OFFSETABLE_LO10
4508 && GET_CODE (rs1
) == LO_SUM
4510 && ! TARGET_CM_MEDMID
4511 && RTX_OK_FOR_OLO10_P (rs2
, mode
))
4514 imm1
= XEXP (rs1
, 1);
4515 rs1
= XEXP (rs1
, 0);
4516 if (!CONSTANT_P (imm1
)
4517 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
4521 else if (GET_CODE (addr
) == LO_SUM
)
4523 rs1
= XEXP (addr
, 0);
4524 imm1
= XEXP (addr
, 1);
4526 if (!CONSTANT_P (imm1
)
4527 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
4530 /* We can't allow TFmode in 32-bit mode, because an offset greater
4531 than the alignment (8) may cause the LO_SUM to overflow. */
4532 if (mode
== TFmode
&& TARGET_ARCH32
)
4535 /* During reload, accept the HIGH+LO_SUM construct generated by
4536 sparc_legitimize_reload_address. */
4537 if (reload_in_progress
4538 && GET_CODE (rs1
) == HIGH
4539 && XEXP (rs1
, 0) == imm1
)
4542 else if (GET_CODE (addr
) == CONST_INT
&& SMALL_INT (addr
))
4547 if (GET_CODE (rs1
) == SUBREG
)
4548 rs1
= SUBREG_REG (rs1
);
4554 if (GET_CODE (rs2
) == SUBREG
)
4555 rs2
= SUBREG_REG (rs2
);
4562 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1
))
4563 || (rs2
&& !REGNO_OK_FOR_BASE_P (REGNO (rs2
))))
4568 if ((! SPARC_INT_REG_P (REGNO (rs1
))
4569 && REGNO (rs1
) != FRAME_POINTER_REGNUM
4570 && REGNO (rs1
) < FIRST_PSEUDO_REGISTER
)
4572 && (! SPARC_INT_REG_P (REGNO (rs2
))
4573 && REGNO (rs2
) != FRAME_POINTER_REGNUM
4574 && REGNO (rs2
) < FIRST_PSEUDO_REGISTER
)))
4580 /* Return the SYMBOL_REF for the tls_get_addr function. */
4582 static GTY(()) rtx sparc_tls_symbol
= NULL_RTX
;
4585 sparc_tls_get_addr (void)
4587 if (!sparc_tls_symbol
)
4588 sparc_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
4590 return sparc_tls_symbol
;
4593 /* Return the Global Offset Table to be used in TLS mode. */
4596 sparc_tls_got (void)
4598 /* In PIC mode, this is just the PIC offset table. */
4601 crtl
->uses_pic_offset_table
= 1;
4602 return pic_offset_table_rtx
;
4605 /* In non-PIC mode, Sun as (unlike GNU as) emits PC-relative relocations for
4606 the GOT symbol with the 32-bit ABI, so we reload the GOT register. */
4607 if (TARGET_SUN_TLS
&& TARGET_ARCH32
)
4609 load_got_register ();
4610 return global_offset_table_rtx
;
4613 /* In all other cases, we load a new pseudo with the GOT symbol. */
4614 return copy_to_reg (sparc_got ());
4617 /* Return true if X contains a thread-local symbol. */
4620 sparc_tls_referenced_p (rtx x
)
4622 if (!TARGET_HAVE_TLS
)
4625 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
4626 x
= XEXP (XEXP (x
, 0), 0);
4628 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
))
4631 /* That's all we handle in sparc_legitimize_tls_address for now. */
4635 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
4636 this (thread-local) address. */
4639 sparc_legitimize_tls_address (rtx addr
)
4641 rtx temp1
, temp2
, temp3
, ret
, o0
, got
;
4644 gcc_assert (can_create_pseudo_p ());
4646 if (GET_CODE (addr
) == SYMBOL_REF
)
4647 switch (SYMBOL_REF_TLS_MODEL (addr
))
4649 case TLS_MODEL_GLOBAL_DYNAMIC
:
4651 temp1
= gen_reg_rtx (SImode
);
4652 temp2
= gen_reg_rtx (SImode
);
4653 ret
= gen_reg_rtx (Pmode
);
4654 o0
= gen_rtx_REG (Pmode
, 8);
4655 got
= sparc_tls_got ();
4656 emit_insn (gen_tgd_hi22 (temp1
, addr
));
4657 emit_insn (gen_tgd_lo10 (temp2
, temp1
, addr
));
4660 emit_insn (gen_tgd_add32 (o0
, got
, temp2
, addr
));
4661 insn
= emit_call_insn (gen_tgd_call32 (o0
, sparc_tls_get_addr (),
4666 emit_insn (gen_tgd_add64 (o0
, got
, temp2
, addr
));
4667 insn
= emit_call_insn (gen_tgd_call64 (o0
, sparc_tls_get_addr (),
4670 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
4671 insn
= get_insns ();
4673 emit_libcall_block (insn
, ret
, o0
, addr
);
4676 case TLS_MODEL_LOCAL_DYNAMIC
:
4678 temp1
= gen_reg_rtx (SImode
);
4679 temp2
= gen_reg_rtx (SImode
);
4680 temp3
= gen_reg_rtx (Pmode
);
4681 ret
= gen_reg_rtx (Pmode
);
4682 o0
= gen_rtx_REG (Pmode
, 8);
4683 got
= sparc_tls_got ();
4684 emit_insn (gen_tldm_hi22 (temp1
));
4685 emit_insn (gen_tldm_lo10 (temp2
, temp1
));
4688 emit_insn (gen_tldm_add32 (o0
, got
, temp2
));
4689 insn
= emit_call_insn (gen_tldm_call32 (o0
, sparc_tls_get_addr (),
4694 emit_insn (gen_tldm_add64 (o0
, got
, temp2
));
4695 insn
= emit_call_insn (gen_tldm_call64 (o0
, sparc_tls_get_addr (),
4698 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
4699 insn
= get_insns ();
4701 emit_libcall_block (insn
, temp3
, o0
,
4702 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
4703 UNSPEC_TLSLD_BASE
));
4704 temp1
= gen_reg_rtx (SImode
);
4705 temp2
= gen_reg_rtx (SImode
);
4706 emit_insn (gen_tldo_hix22 (temp1
, addr
));
4707 emit_insn (gen_tldo_lox10 (temp2
, temp1
, addr
));
4709 emit_insn (gen_tldo_add32 (ret
, temp3
, temp2
, addr
));
4711 emit_insn (gen_tldo_add64 (ret
, temp3
, temp2
, addr
));
4714 case TLS_MODEL_INITIAL_EXEC
:
4715 temp1
= gen_reg_rtx (SImode
);
4716 temp2
= gen_reg_rtx (SImode
);
4717 temp3
= gen_reg_rtx (Pmode
);
4718 got
= sparc_tls_got ();
4719 emit_insn (gen_tie_hi22 (temp1
, addr
));
4720 emit_insn (gen_tie_lo10 (temp2
, temp1
, addr
));
4722 emit_insn (gen_tie_ld32 (temp3
, got
, temp2
, addr
));
4724 emit_insn (gen_tie_ld64 (temp3
, got
, temp2
, addr
));
4727 ret
= gen_reg_rtx (Pmode
);
4729 emit_insn (gen_tie_add32 (ret
, gen_rtx_REG (Pmode
, 7),
4732 emit_insn (gen_tie_add64 (ret
, gen_rtx_REG (Pmode
, 7),
4736 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp3
);
4739 case TLS_MODEL_LOCAL_EXEC
:
4740 temp1
= gen_reg_rtx (Pmode
);
4741 temp2
= gen_reg_rtx (Pmode
);
4744 emit_insn (gen_tle_hix22_sp32 (temp1
, addr
));
4745 emit_insn (gen_tle_lox10_sp32 (temp2
, temp1
, addr
));
4749 emit_insn (gen_tle_hix22_sp64 (temp1
, addr
));
4750 emit_insn (gen_tle_lox10_sp64 (temp2
, temp1
, addr
));
4752 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp2
);
4759 else if (GET_CODE (addr
) == CONST
)
4763 gcc_assert (GET_CODE (XEXP (addr
, 0)) == PLUS
);
4765 base
= sparc_legitimize_tls_address (XEXP (XEXP (addr
, 0), 0));
4766 offset
= XEXP (XEXP (addr
, 0), 1);
4768 base
= force_operand (base
, NULL_RTX
);
4769 if (!(GET_CODE (offset
) == CONST_INT
&& SMALL_INT (offset
)))
4770 offset
= force_reg (Pmode
, offset
);
4771 ret
= gen_rtx_PLUS (Pmode
, base
, offset
);
4775 gcc_unreachable (); /* for now ... */
4780 /* Legitimize PIC addresses. If the address is already position-independent,
4781 we return ORIG. Newly generated position-independent addresses go into a
4782 reg. This is REG if nonzero, otherwise we allocate register(s) as
4786 sparc_legitimize_pic_address (rtx orig
, rtx reg
)
4788 if (GET_CODE (orig
) == SYMBOL_REF
4789 /* See the comment in sparc_expand_move. */
4790 || (GET_CODE (orig
) == LABEL_REF
&& !can_use_mov_pic_label_ref (orig
)))
4792 bool gotdata_op
= false;
4793 rtx pic_ref
, address
;
4798 gcc_assert (can_create_pseudo_p ());
4799 reg
= gen_reg_rtx (Pmode
);
4804 /* If not during reload, allocate another temp reg here for loading
4805 in the address, so that these instructions can be optimized
4807 rtx temp_reg
= can_create_pseudo_p () ? gen_reg_rtx (Pmode
) : reg
;
4809 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
4810 won't get confused into thinking that these two instructions
4811 are loading in the true address of the symbol. If in the
4812 future a PIC rtx exists, that should be used instead. */
4815 emit_insn (gen_movdi_high_pic (temp_reg
, orig
));
4816 emit_insn (gen_movdi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
4820 emit_insn (gen_movsi_high_pic (temp_reg
, orig
));
4821 emit_insn (gen_movsi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
4830 crtl
->uses_pic_offset_table
= 1;
4834 insn
= emit_insn (gen_movdi_pic_gotdata_op (reg
,
4835 pic_offset_table_rtx
,
4838 insn
= emit_insn (gen_movsi_pic_gotdata_op (reg
,
4839 pic_offset_table_rtx
,
4845 = gen_const_mem (Pmode
,
4846 gen_rtx_PLUS (Pmode
,
4847 pic_offset_table_rtx
, address
));
4848 insn
= emit_move_insn (reg
, pic_ref
);
4851 /* Put a REG_EQUAL note on this insn, so that it can be optimized
4853 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
4856 else if (GET_CODE (orig
) == CONST
)
4860 if (GET_CODE (XEXP (orig
, 0)) == PLUS
4861 && sparc_pic_register_p (XEXP (XEXP (orig
, 0), 0)))
4866 gcc_assert (can_create_pseudo_p ());
4867 reg
= gen_reg_rtx (Pmode
);
4870 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
4871 base
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), reg
);
4872 offset
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
4873 base
== reg
? NULL_RTX
: reg
);
4875 if (GET_CODE (offset
) == CONST_INT
)
4877 if (SMALL_INT (offset
))
4878 return plus_constant (Pmode
, base
, INTVAL (offset
));
4879 else if (can_create_pseudo_p ())
4880 offset
= force_reg (Pmode
, offset
);
4882 /* If we reach here, then something is seriously wrong. */
4885 return gen_rtx_PLUS (Pmode
, base
, offset
);
4887 else if (GET_CODE (orig
) == LABEL_REF
)
4888 /* ??? We ought to be checking that the register is live instead, in case
4889 it is eliminated. */
4890 crtl
->uses_pic_offset_table
= 1;
4895 /* Try machine-dependent ways of modifying an illegitimate address X
4896 to be legitimate. If we find one, return the new, valid address.
4898 OLDX is the address as it was before break_out_memory_refs was called.
4899 In some cases it is useful to look at this to decide what needs to be done.
4901 MODE is the mode of the operand pointed to by X.
4903 On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
4906 sparc_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
4911 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
)
4912 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
4913 force_operand (XEXP (x
, 0), NULL_RTX
));
4914 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == MULT
)
4915 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4916 force_operand (XEXP (x
, 1), NULL_RTX
));
4917 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
4918 x
= gen_rtx_PLUS (Pmode
, force_operand (XEXP (x
, 0), NULL_RTX
),
4920 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == PLUS
)
4921 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4922 force_operand (XEXP (x
, 1), NULL_RTX
));
4924 if (x
!= orig_x
&& sparc_legitimate_address_p (mode
, x
, FALSE
))
4927 if (sparc_tls_referenced_p (x
))
4928 x
= sparc_legitimize_tls_address (x
);
4930 x
= sparc_legitimize_pic_address (x
, NULL_RTX
);
4931 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 1)))
4932 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4933 copy_to_mode_reg (Pmode
, XEXP (x
, 1)));
4934 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 0)))
4935 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
4936 copy_to_mode_reg (Pmode
, XEXP (x
, 0)));
4937 else if (GET_CODE (x
) == SYMBOL_REF
4938 || GET_CODE (x
) == CONST
4939 || GET_CODE (x
) == LABEL_REF
)
4940 x
= copy_to_suggested_reg (x
, NULL_RTX
, Pmode
);
4945 /* Delegitimize an address that was legitimized by the above function. */
4948 sparc_delegitimize_address (rtx x
)
4950 x
= delegitimize_mem_from_attrs (x
);
4952 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 1)) == UNSPEC
)
4953 switch (XINT (XEXP (x
, 1), 1))
4955 case UNSPEC_MOVE_PIC
:
4957 x
= XVECEXP (XEXP (x
, 1), 0, 0);
4958 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
4964 /* This is generated by mov{si,di}_pic_label_ref in PIC mode. */
4965 if (GET_CODE (x
) == MINUS
4966 && sparc_pic_register_p (XEXP (x
, 0))
4967 && GET_CODE (XEXP (x
, 1)) == LO_SUM
4968 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == UNSPEC
4969 && XINT (XEXP (XEXP (x
, 1), 1), 1) == UNSPEC_MOVE_PIC_LABEL
)
4971 x
= XVECEXP (XEXP (XEXP (x
, 1), 1), 0, 0);
4972 gcc_assert (GET_CODE (x
) == LABEL_REF
4973 || (GET_CODE (x
) == CONST
4974 && GET_CODE (XEXP (x
, 0)) == PLUS
4975 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
4976 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
));
4982 /* SPARC implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
4983 replace the input X, or the original X if no replacement is called for.
4984 The output parameter *WIN is 1 if the calling macro should goto WIN,
4987 For SPARC, we wish to handle addresses by splitting them into
4988 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
4989 This cuts the number of extra insns by one.
4991 Do nothing when generating PIC code and the address is a symbolic
4992 operand or requires a scratch register. */
4995 sparc_legitimize_reload_address (rtx x
, machine_mode mode
,
4996 int opnum
, int type
,
4997 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
4999 /* Decompose SImode constants into HIGH+LO_SUM. */
5001 && (mode
!= TFmode
|| TARGET_ARCH64
)
5002 && GET_MODE (x
) == SImode
5003 && GET_CODE (x
) != LO_SUM
5004 && GET_CODE (x
) != HIGH
5005 && sparc_cmodel
<= CM_MEDLOW
5007 && (symbolic_operand (x
, Pmode
) || pic_address_needs_scratch (x
))))
5009 x
= gen_rtx_LO_SUM (GET_MODE (x
), gen_rtx_HIGH (GET_MODE (x
), x
), x
);
5010 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
5011 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
5012 opnum
, (enum reload_type
)type
);
5017 /* We have to recognize what we have already generated above. */
5018 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == HIGH
)
5020 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
5021 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
5022 opnum
, (enum reload_type
)type
);
5031 /* Return true if ADDR (a legitimate address expression)
5032 has an effect that depends on the machine mode it is used for.
5038 is not equivalent to
5040 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
5042 because [%l7+a+1] is interpreted as the address of (a+1). */
5046 sparc_mode_dependent_address_p (const_rtx addr
,
5047 addr_space_t as ATTRIBUTE_UNUSED
)
5049 if (GET_CODE (addr
) == PLUS
5050 && sparc_pic_register_p (XEXP (addr
, 0))
5051 && symbolic_operand (XEXP (addr
, 1), VOIDmode
))
5057 #ifdef HAVE_GAS_HIDDEN
5058 # define USE_HIDDEN_LINKONCE 1
5060 # define USE_HIDDEN_LINKONCE 0
5064 get_pc_thunk_name (char name
[32], unsigned int regno
)
5066 const char *reg_name
= reg_names
[regno
];
5068 /* Skip the leading '%' as that cannot be used in a
5072 if (USE_HIDDEN_LINKONCE
)
5073 sprintf (name
, "__sparc_get_pc_thunk.%s", reg_name
);
5075 ASM_GENERATE_INTERNAL_LABEL (name
, "LADDPC", regno
);
5078 /* Wrapper around the load_pcrel_sym{si,di} patterns. */
5081 gen_load_pcrel_sym (rtx op0
, rtx op1
, rtx op2
)
5083 int orig_flag_pic
= flag_pic
;
5086 /* The load_pcrel_sym{si,di} patterns require absolute addressing. */
5089 insn
= gen_load_pcrel_symdi (op0
, op1
, op2
, GEN_INT (REGNO (op0
)));
5091 insn
= gen_load_pcrel_symsi (op0
, op1
, op2
, GEN_INT (REGNO (op0
)));
5092 flag_pic
= orig_flag_pic
;
5097 /* Emit code to load the GOT register. */
5100 load_got_register (void)
5102 if (!global_offset_table_rtx
)
5103 global_offset_table_rtx
= gen_rtx_REG (Pmode
, GLOBAL_OFFSET_TABLE_REGNUM
);
5105 if (TARGET_VXWORKS_RTP
)
5106 emit_insn (gen_vxworks_load_got ());
5109 /* The GOT symbol is subject to a PC-relative relocation so we need a
5110 helper function to add the PC value and thus get the final value. */
5111 if (!got_helper_rtx
)
5114 get_pc_thunk_name (name
, GLOBAL_OFFSET_TABLE_REGNUM
);
5115 got_helper_rtx
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
5118 emit_insn (gen_load_pcrel_sym (global_offset_table_rtx
, sparc_got (),
5123 /* Emit a call instruction with the pattern given by PAT. ADDR is the
5124 address of the call target. */
5127 sparc_emit_call_insn (rtx pat
, rtx addr
)
5131 insn
= emit_call_insn (pat
);
5133 /* The PIC register is live on entry to VxWorks PIC PLT entries. */
5134 if (TARGET_VXWORKS_RTP
5136 && GET_CODE (addr
) == SYMBOL_REF
5137 && (SYMBOL_REF_DECL (addr
)
5138 ? !targetm
.binds_local_p (SYMBOL_REF_DECL (addr
))
5139 : !SYMBOL_REF_LOCAL_P (addr
)))
5141 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
5142 crtl
->uses_pic_offset_table
= 1;
5146 /* Return 1 if RTX is a MEM which is known to be aligned to at
5147 least a DESIRED byte boundary. */
5150 mem_min_alignment (rtx mem
, int desired
)
5152 rtx addr
, base
, offset
;
5154 /* If it's not a MEM we can't accept it. */
5155 if (GET_CODE (mem
) != MEM
)
5159 if (!TARGET_UNALIGNED_DOUBLES
5160 && MEM_ALIGN (mem
) / BITS_PER_UNIT
>= (unsigned)desired
)
5163 /* ??? The rest of the function predates MEM_ALIGN so
5164 there is probably a bit of redundancy. */
5165 addr
= XEXP (mem
, 0);
5166 base
= offset
= NULL_RTX
;
5167 if (GET_CODE (addr
) == PLUS
)
5169 if (GET_CODE (XEXP (addr
, 0)) == REG
)
5171 base
= XEXP (addr
, 0);
5173 /* What we are saying here is that if the base
5174 REG is aligned properly, the compiler will make
5175 sure any REG based index upon it will be so
5177 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
5178 offset
= XEXP (addr
, 1);
5180 offset
= const0_rtx
;
5183 else if (GET_CODE (addr
) == REG
)
5186 offset
= const0_rtx
;
5189 if (base
!= NULL_RTX
)
5191 int regno
= REGNO (base
);
5193 if (regno
!= HARD_FRAME_POINTER_REGNUM
&& regno
!= STACK_POINTER_REGNUM
)
5195 /* Check if the compiler has recorded some information
5196 about the alignment of the base REG. If reload has
5197 completed, we already matched with proper alignments.
5198 If not running global_alloc, reload might give us
5199 unaligned pointer to local stack though. */
5201 && REGNO_POINTER_ALIGN (regno
) >= desired
* BITS_PER_UNIT
)
5202 || (optimize
&& reload_completed
))
5203 && (INTVAL (offset
) & (desired
- 1)) == 0)
5208 if (((INTVAL (offset
) - SPARC_STACK_BIAS
) & (desired
- 1)) == 0)
5212 else if (! TARGET_UNALIGNED_DOUBLES
5213 || CONSTANT_P (addr
)
5214 || GET_CODE (addr
) == LO_SUM
)
5216 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
5217 is true, in which case we can only assume that an access is aligned if
5218 it is to a constant address, or the address involves a LO_SUM. */
5222 /* An obviously unaligned address. */
5227 /* Vectors to keep interesting information about registers where it can easily
5228 be got. We used to use the actual mode value as the bit number, but there
5229 are more than 32 modes now. Instead we use two tables: one indexed by
5230 hard register number, and one indexed by mode. */
5232 /* The purpose of sparc_mode_class is to shrink the range of modes so that
5233 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
5234 mapped into one sparc_mode_class mode. */
5236 enum sparc_mode_class
{
5237 H_MODE
, S_MODE
, D_MODE
, T_MODE
, O_MODE
,
5238 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
5242 /* Modes for single-word and smaller quantities. */
5244 ((1 << (int) H_MODE) | (1 << (int) S_MODE) | (1 << (int) SF_MODE))
5246 /* Modes for double-word and smaller quantities. */
5247 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << (int) DF_MODE))
5249 /* Modes for quad-word and smaller quantities. */
5250 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
5252 /* Modes for 8-word and smaller quantities. */
5253 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
5255 /* Modes for single-float quantities. */
5256 #define SF_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
5258 /* Modes for double-float and smaller quantities. */
5259 #define DF_MODES (SF_MODES | (1 << (int) D_MODE) | (1 << (int) DF_MODE))
5261 /* Modes for quad-float and smaller quantities. */
5262 #define TF_MODES (DF_MODES | (1 << (int) TF_MODE))
5264 /* Modes for quad-float pairs and smaller quantities. */
5265 #define OF_MODES (TF_MODES | (1 << (int) OF_MODE))
5267 /* Modes for double-float only quantities. */
5268 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
5270 /* Modes for quad-float and double-float only quantities. */
5271 #define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE))
5273 /* Modes for quad-float pairs and double-float only quantities. */
5274 #define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE))
5276 /* Modes for condition codes. */
5277 #define CC_MODES (1 << (int) CC_MODE)
5278 #define CCFP_MODES (1 << (int) CCFP_MODE)
5280 /* Value is 1 if register/mode pair is acceptable on sparc.
5282 The funny mixture of D and T modes is because integer operations
5283 do not specially operate on tetra quantities, so non-quad-aligned
5284 registers can hold quadword quantities (except %o4 and %i4 because
5285 they cross fixed registers).
5287 ??? Note that, despite the settings, non-double-aligned parameter
5288 registers can hold double-word quantities in 32-bit mode. */
5290 /* This points to either the 32-bit or the 64-bit version. */
5291 static const int *hard_regno_mode_classes
;
5293 static const int hard_32bit_mode_classes
[] = {
5294 S_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
5295 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
5296 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
5297 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
5299 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5300 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5301 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5302 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5304 /* FP regs f32 to f63. Only the even numbered registers actually exist,
5305 and none can hold SFmode/SImode values. */
5306 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5307 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5308 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5309 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5312 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
5314 /* %icc, %sfp, %gsr */
5315 CC_MODES
, 0, D_MODES
5318 static const int hard_64bit_mode_classes
[] = {
5319 D_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
5320 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
5321 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
5322 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
5324 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5325 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5326 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5327 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
5329 /* FP regs f32 to f63. Only the even numbered registers actually exist,
5330 and none can hold SFmode/SImode values. */
5331 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5332 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5333 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5334 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
5337 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
5339 /* %icc, %sfp, %gsr */
5340 CC_MODES
, 0, D_MODES
5343 static int sparc_mode_class
[NUM_MACHINE_MODES
];
5345 enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
5348 sparc_init_modes (void)
5352 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
5354 machine_mode m
= (machine_mode
) i
;
5355 unsigned int size
= GET_MODE_SIZE (m
);
5357 switch (GET_MODE_CLASS (m
))
5360 case MODE_PARTIAL_INT
:
5361 case MODE_COMPLEX_INT
:
5363 sparc_mode_class
[i
] = 1 << (int) H_MODE
;
5365 sparc_mode_class
[i
] = 1 << (int) S_MODE
;
5367 sparc_mode_class
[i
] = 1 << (int) D_MODE
;
5368 else if (size
== 16)
5369 sparc_mode_class
[i
] = 1 << (int) T_MODE
;
5370 else if (size
== 32)
5371 sparc_mode_class
[i
] = 1 << (int) O_MODE
;
5373 sparc_mode_class
[i
] = 0;
5375 case MODE_VECTOR_INT
:
5377 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
5379 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
5381 sparc_mode_class
[i
] = 0;
5384 case MODE_COMPLEX_FLOAT
:
5386 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
5388 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
5389 else if (size
== 16)
5390 sparc_mode_class
[i
] = 1 << (int) TF_MODE
;
5391 else if (size
== 32)
5392 sparc_mode_class
[i
] = 1 << (int) OF_MODE
;
5394 sparc_mode_class
[i
] = 0;
5397 if (m
== CCFPmode
|| m
== CCFPEmode
)
5398 sparc_mode_class
[i
] = 1 << (int) CCFP_MODE
;
5400 sparc_mode_class
[i
] = 1 << (int) CC_MODE
;
5403 sparc_mode_class
[i
] = 0;
5409 hard_regno_mode_classes
= hard_64bit_mode_classes
;
5411 hard_regno_mode_classes
= hard_32bit_mode_classes
;
5413 /* Initialize the array used by REGNO_REG_CLASS. */
5414 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
5416 if (i
< 16 && TARGET_V8PLUS
)
5417 sparc_regno_reg_class
[i
] = I64_REGS
;
5418 else if (i
< 32 || i
== FRAME_POINTER_REGNUM
)
5419 sparc_regno_reg_class
[i
] = GENERAL_REGS
;
5421 sparc_regno_reg_class
[i
] = FP_REGS
;
5423 sparc_regno_reg_class
[i
] = EXTRA_FP_REGS
;
5425 sparc_regno_reg_class
[i
] = FPCC_REGS
;
5427 sparc_regno_reg_class
[i
] = NO_REGS
;
5431 /* Return whether REGNO, a global or FP register, must be saved/restored. */
5434 save_global_or_fp_reg_p (unsigned int regno
,
5435 int leaf_function ATTRIBUTE_UNUSED
)
5437 return !call_used_regs
[regno
] && df_regs_ever_live_p (regno
);
5440 /* Return whether the return address register (%i7) is needed. */
5443 return_addr_reg_needed_p (int leaf_function
)
5445 /* If it is live, for example because of __builtin_return_address (0). */
5446 if (df_regs_ever_live_p (RETURN_ADDR_REGNUM
))
5449 /* Otherwise, it is needed as save register if %o7 is clobbered. */
5451 /* Loading the GOT register clobbers %o7. */
5452 || crtl
->uses_pic_offset_table
5453 || df_regs_ever_live_p (INCOMING_RETURN_ADDR_REGNUM
))
5459 /* Return whether REGNO, a local or in register, must be saved/restored. */
5462 save_local_or_in_reg_p (unsigned int regno
, int leaf_function
)
5464 /* General case: call-saved registers live at some point. */
5465 if (!call_used_regs
[regno
] && df_regs_ever_live_p (regno
))
5468 /* Frame pointer register (%fp) if needed. */
5469 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
5472 /* Return address register (%i7) if needed. */
5473 if (regno
== RETURN_ADDR_REGNUM
&& return_addr_reg_needed_p (leaf_function
))
5476 /* GOT register (%l7) if needed. */
5477 if (regno
== PIC_OFFSET_TABLE_REGNUM
&& crtl
->uses_pic_offset_table
)
5480 /* If the function accesses prior frames, the frame pointer and the return
5481 address of the previous frame must be saved on the stack. */
5482 if (crtl
->accesses_prior_frames
5483 && (regno
== HARD_FRAME_POINTER_REGNUM
|| regno
== RETURN_ADDR_REGNUM
))
5489 /* Compute the frame size required by the function. This function is called
5490 during the reload pass and also by sparc_expand_prologue. */
5492 static HOST_WIDE_INT
5493 sparc_compute_frame_size (HOST_WIDE_INT size
, int leaf_function
)
5495 HOST_WIDE_INT frame_size
, apparent_frame_size
;
5496 int args_size
, n_global_fp_regs
= 0;
5497 bool save_local_in_regs_p
= false;
5500 /* If the function allocates dynamic stack space, the dynamic offset is
5501 computed early and contains REG_PARM_STACK_SPACE, so we need to cope. */
5502 if (leaf_function
&& !cfun
->calls_alloca
)
5505 args_size
= crtl
->outgoing_args_size
+ REG_PARM_STACK_SPACE (cfun
->decl
);
5507 /* Calculate space needed for global registers. */
5510 for (i
= 0; i
< 8; i
++)
5511 if (save_global_or_fp_reg_p (i
, 0))
5512 n_global_fp_regs
+= 2;
5516 for (i
= 0; i
< 8; i
+= 2)
5517 if (save_global_or_fp_reg_p (i
, 0)
5518 || save_global_or_fp_reg_p (i
+ 1, 0))
5519 n_global_fp_regs
+= 2;
5522 /* In the flat window model, find out which local and in registers need to
5523 be saved. We don't reserve space in the current frame for them as they
5524 will be spilled into the register window save area of the caller's frame.
5525 However, as soon as we use this register window save area, we must create
5526 that of the current frame to make it the live one. */
5528 for (i
= 16; i
< 32; i
++)
5529 if (save_local_or_in_reg_p (i
, leaf_function
))
5531 save_local_in_regs_p
= true;
5535 /* Calculate space needed for FP registers. */
5536 for (i
= 32; i
< (TARGET_V9
? 96 : 64); i
+= 2)
5537 if (save_global_or_fp_reg_p (i
, 0) || save_global_or_fp_reg_p (i
+ 1, 0))
5538 n_global_fp_regs
+= 2;
5541 && n_global_fp_regs
== 0
5543 && !save_local_in_regs_p
)
5544 frame_size
= apparent_frame_size
= 0;
5547 /* Start from the apparent frame size. */
5548 apparent_frame_size
= ROUND_UP (size
, 8) + n_global_fp_regs
* 4;
5550 /* We need to add the size of the outgoing argument area. */
5551 frame_size
= apparent_frame_size
+ ROUND_UP (args_size
, 8);
5553 /* And that of the register window save area. */
5554 frame_size
+= FIRST_PARM_OFFSET (cfun
->decl
);
5556 /* Finally, bump to the appropriate alignment. */
5557 frame_size
= SPARC_STACK_ALIGN (frame_size
);
5560 /* Set up values for use in prologue and epilogue. */
5561 sparc_frame_size
= frame_size
;
5562 sparc_apparent_frame_size
= apparent_frame_size
;
5563 sparc_n_global_fp_regs
= n_global_fp_regs
;
5564 sparc_save_local_in_regs_p
= save_local_in_regs_p
;
5569 /* Implement the macro INITIAL_ELIMINATION_OFFSET, return the OFFSET. */
5572 sparc_initial_elimination_offset (int to
)
5576 if (to
== STACK_POINTER_REGNUM
)
5577 offset
= sparc_compute_frame_size (get_frame_size (), crtl
->is_leaf
);
5581 offset
+= SPARC_STACK_BIAS
;
5585 /* Output any necessary .register pseudo-ops. */
5588 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED
)
5595 /* Check if %g[2367] were used without
5596 .register being printed for them already. */
5597 for (i
= 2; i
< 8; i
++)
5599 if (df_regs_ever_live_p (i
)
5600 && ! sparc_hard_reg_printed
[i
])
5602 sparc_hard_reg_printed
[i
] = 1;
5603 /* %g7 is used as TLS base register, use #ignore
5604 for it instead of #scratch. */
5605 fprintf (file
, "\t.register\t%%g%d, #%s\n", i
,
5606 i
== 7 ? "ignore" : "scratch");
5612 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
5614 #if PROBE_INTERVAL > 4096
5615 #error Cannot use indexed addressing mode for stack probing
5618 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
5619 inclusive. These are offsets from the current stack pointer.
5621 Note that we don't use the REG+REG addressing mode for the probes because
5622 of the stack bias in 64-bit mode. And it doesn't really buy us anything
5623 so the advantages of having a single code win here. */
5626 sparc_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
5628 rtx g1
= gen_rtx_REG (Pmode
, 1);
5630 /* See if we have a constant small number of probes to generate. If so,
5631 that's the easy case. */
5632 if (size
<= PROBE_INTERVAL
)
5634 emit_move_insn (g1
, GEN_INT (first
));
5635 emit_insn (gen_rtx_SET (g1
,
5636 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
5637 emit_stack_probe (plus_constant (Pmode
, g1
, -size
));
5640 /* The run-time loop is made up of 9 insns in the generic case while the
5641 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
5642 else if (size
<= 4 * PROBE_INTERVAL
)
5646 emit_move_insn (g1
, GEN_INT (first
+ PROBE_INTERVAL
));
5647 emit_insn (gen_rtx_SET (g1
,
5648 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
5649 emit_stack_probe (g1
);
5651 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
5652 it exceeds SIZE. If only two probes are needed, this will not
5653 generate any code. Then probe at FIRST + SIZE. */
5654 for (i
= 2 * PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
5656 emit_insn (gen_rtx_SET (g1
,
5657 plus_constant (Pmode
, g1
, -PROBE_INTERVAL
)));
5658 emit_stack_probe (g1
);
5661 emit_stack_probe (plus_constant (Pmode
, g1
,
5662 (i
- PROBE_INTERVAL
) - size
));
5665 /* Otherwise, do the same as above, but in a loop. Note that we must be
5666 extra careful with variables wrapping around because we might be at
5667 the very top (or the very bottom) of the address space and we have
5668 to be able to handle this case properly; in particular, we use an
5669 equality test for the loop condition. */
5672 HOST_WIDE_INT rounded_size
;
5673 rtx g4
= gen_rtx_REG (Pmode
, 4);
5675 emit_move_insn (g1
, GEN_INT (first
));
5678 /* Step 1: round SIZE to the previous multiple of the interval. */
5680 rounded_size
= ROUND_DOWN (size
, PROBE_INTERVAL
);
5681 emit_move_insn (g4
, GEN_INT (rounded_size
));
5684 /* Step 2: compute initial and final value of the loop counter. */
5686 /* TEST_ADDR = SP + FIRST. */
5687 emit_insn (gen_rtx_SET (g1
,
5688 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
5690 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
5691 emit_insn (gen_rtx_SET (g4
, gen_rtx_MINUS (Pmode
, g1
, g4
)));
5696 while (TEST_ADDR != LAST_ADDR)
5698 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
5702 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
5703 until it is equal to ROUNDED_SIZE. */
5706 emit_insn (gen_probe_stack_rangedi (g1
, g1
, g4
));
5708 emit_insn (gen_probe_stack_rangesi (g1
, g1
, g4
));
5711 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
5712 that SIZE is equal to ROUNDED_SIZE. */
5714 if (size
!= rounded_size
)
5715 emit_stack_probe (plus_constant (Pmode
, g4
, rounded_size
- size
));
5718 /* Make sure nothing is scheduled before we are done. */
5719 emit_insn (gen_blockage ());
5722 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
5723 absolute addresses. */
5726 output_probe_stack_range (rtx reg1
, rtx reg2
)
5728 static int labelno
= 0;
5732 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
++);
5735 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
5737 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
5739 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
5740 output_asm_insn ("add\t%0, %1, %0", xops
);
5742 /* Test if TEST_ADDR == LAST_ADDR. */
5744 output_asm_insn ("cmp\t%0, %1", xops
);
5746 /* Probe at TEST_ADDR and branch. */
5748 fputs ("\tbne,pt\t%xcc,", asm_out_file
);
5750 fputs ("\tbne\t", asm_out_file
);
5751 assemble_name_raw (asm_out_file
, loop_lab
);
5752 fputc ('\n', asm_out_file
);
5753 xops
[1] = GEN_INT (SPARC_STACK_BIAS
);
5754 output_asm_insn (" st\t%%g0, [%0+%1]", xops
);
5759 /* Emit code to save/restore registers from LOW to HIGH at BASE+OFFSET as
5760 needed. LOW is supposed to be double-word aligned for 32-bit registers.
5761 SAVE_P decides whether a register must be saved/restored. ACTION_TRUE
5762 is the action to be performed if SAVE_P returns true and ACTION_FALSE
5763 the action to be performed if it returns false. Return the new offset. */
5765 typedef bool (*sorr_pred_t
) (unsigned int, int);
5766 typedef enum { SORR_NONE
, SORR_ADVANCE
, SORR_SAVE
, SORR_RESTORE
} sorr_act_t
;
5769 emit_save_or_restore_regs (unsigned int low
, unsigned int high
, rtx base
,
5770 int offset
, int leaf_function
, sorr_pred_t save_p
,
5771 sorr_act_t action_true
, sorr_act_t action_false
)
5777 if (TARGET_ARCH64
&& high
<= 32)
5781 for (i
= low
; i
< high
; i
++)
5783 if (save_p (i
, leaf_function
))
5785 mem
= gen_frame_mem (DImode
, plus_constant (Pmode
,
5787 if (action_true
== SORR_SAVE
)
5789 insn
= emit_move_insn (mem
, gen_rtx_REG (DImode
, i
));
5790 RTX_FRAME_RELATED_P (insn
) = 1;
5792 else /* action_true == SORR_RESTORE */
5794 /* The frame pointer must be restored last since its old
5795 value may be used as base address for the frame. This
5796 is problematic in 64-bit mode only because of the lack
5797 of double-word load instruction. */
5798 if (i
== HARD_FRAME_POINTER_REGNUM
)
5801 emit_move_insn (gen_rtx_REG (DImode
, i
), mem
);
5805 else if (action_false
== SORR_ADVANCE
)
5811 mem
= gen_frame_mem (DImode
, plus_constant (Pmode
, base
, fp_offset
));
5812 emit_move_insn (hard_frame_pointer_rtx
, mem
);
5817 for (i
= low
; i
< high
; i
+= 2)
5819 bool reg0
= save_p (i
, leaf_function
);
5820 bool reg1
= save_p (i
+ 1, leaf_function
);
5826 mode
= SPARC_INT_REG_P (i
) ? E_DImode
: E_DFmode
;
5831 mode
= SPARC_INT_REG_P (i
) ? E_SImode
: E_SFmode
;
5836 mode
= SPARC_INT_REG_P (i
) ? E_SImode
: E_SFmode
;
5842 if (action_false
== SORR_ADVANCE
)
5847 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, base
, offset
));
5848 if (action_true
== SORR_SAVE
)
5850 insn
= emit_move_insn (mem
, gen_rtx_REG (mode
, regno
));
5851 RTX_FRAME_RELATED_P (insn
) = 1;
5855 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, base
,
5857 set1
= gen_rtx_SET (mem
, gen_rtx_REG (SImode
, regno
));
5858 RTX_FRAME_RELATED_P (set1
) = 1;
5860 = gen_frame_mem (SImode
, plus_constant (Pmode
, base
,
5862 set2
= gen_rtx_SET (mem
, gen_rtx_REG (SImode
, regno
+ 1));
5863 RTX_FRAME_RELATED_P (set2
) = 1;
5864 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
5865 gen_rtx_PARALLEL (VOIDmode
,
5866 gen_rtvec (2, set1
, set2
)));
5869 else /* action_true == SORR_RESTORE */
5870 emit_move_insn (gen_rtx_REG (mode
, regno
), mem
);
5872 /* Bump and round down to double word
5873 in case we already bumped by 4. */
5874 offset
= ROUND_DOWN (offset
+ 8, 8);
5881 /* Emit code to adjust BASE to OFFSET. Return the new base. */
5884 emit_adjust_base_to_offset (rtx base
, int offset
)
5886 /* ??? This might be optimized a little as %g1 might already have a
5887 value close enough that a single add insn will do. */
5888 /* ??? Although, all of this is probably only a temporary fix because
5889 if %g1 can hold a function result, then sparc_expand_epilogue will
5890 lose (the result will be clobbered). */
5891 rtx new_base
= gen_rtx_REG (Pmode
, 1);
5892 emit_move_insn (new_base
, GEN_INT (offset
));
5893 emit_insn (gen_rtx_SET (new_base
, gen_rtx_PLUS (Pmode
, base
, new_base
)));
5897 /* Emit code to save/restore call-saved global and FP registers. */
5900 emit_save_or_restore_global_fp_regs (rtx base
, int offset
, sorr_act_t action
)
5902 if (offset
< -4096 || offset
+ sparc_n_global_fp_regs
* 4 > 4095)
5904 base
= emit_adjust_base_to_offset (base
, offset
);
5909 = emit_save_or_restore_regs (0, 8, base
, offset
, 0,
5910 save_global_or_fp_reg_p
, action
, SORR_NONE
);
5911 emit_save_or_restore_regs (32, TARGET_V9
? 96 : 64, base
, offset
, 0,
5912 save_global_or_fp_reg_p
, action
, SORR_NONE
);
5915 /* Emit code to save/restore call-saved local and in registers. */
5918 emit_save_or_restore_local_in_regs (rtx base
, int offset
, sorr_act_t action
)
5920 if (offset
< -4096 || offset
+ 16 * UNITS_PER_WORD
> 4095)
5922 base
= emit_adjust_base_to_offset (base
, offset
);
5926 emit_save_or_restore_regs (16, 32, base
, offset
, sparc_leaf_function_p
,
5927 save_local_or_in_reg_p
, action
, SORR_ADVANCE
);
5930 /* Emit a window_save insn. */
5933 emit_window_save (rtx increment
)
5935 rtx_insn
*insn
= emit_insn (gen_window_save (increment
));
5936 RTX_FRAME_RELATED_P (insn
) = 1;
5938 /* The incoming return address (%o7) is saved in %i7. */
5939 add_reg_note (insn
, REG_CFA_REGISTER
,
5940 gen_rtx_SET (gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
),
5942 INCOMING_RETURN_ADDR_REGNUM
)));
5944 /* The window save event. */
5945 add_reg_note (insn
, REG_CFA_WINDOW_SAVE
, const0_rtx
);
5947 /* The CFA is %fp, the hard frame pointer. */
5948 add_reg_note (insn
, REG_CFA_DEF_CFA
,
5949 plus_constant (Pmode
, hard_frame_pointer_rtx
,
5950 INCOMING_FRAME_SP_OFFSET
));
5955 /* Generate an increment for the stack pointer. */
5958 gen_stack_pointer_inc (rtx increment
)
5960 return gen_rtx_SET (stack_pointer_rtx
,
5961 gen_rtx_PLUS (Pmode
,
5966 /* Expand the function prologue. The prologue is responsible for reserving
5967 storage for the frame, saving the call-saved registers and loading the
5968 GOT register if needed. */
5971 sparc_expand_prologue (void)
5976 /* Compute a snapshot of crtl->uses_only_leaf_regs. Relying
5977 on the final value of the flag means deferring the prologue/epilogue
5978 expansion until just before the second scheduling pass, which is too
5979 late to emit multiple epilogues or return insns.
5981 Of course we are making the assumption that the value of the flag
5982 will not change between now and its final value. Of the three parts
5983 of the formula, only the last one can reasonably vary. Let's take a
5984 closer look, after assuming that the first two ones are set to true
5985 (otherwise the last value is effectively silenced).
5987 If only_leaf_regs_used returns false, the global predicate will also
5988 be false so the actual frame size calculated below will be positive.
5989 As a consequence, the save_register_window insn will be emitted in
5990 the instruction stream; now this insn explicitly references %fp
5991 which is not a leaf register so only_leaf_regs_used will always
5992 return false subsequently.
5994 If only_leaf_regs_used returns true, we hope that the subsequent
5995 optimization passes won't cause non-leaf registers to pop up. For
5996 example, the regrename pass has special provisions to not rename to
5997 non-leaf registers in a leaf function. */
5998 sparc_leaf_function_p
5999 = optimize
> 0 && crtl
->is_leaf
&& only_leaf_regs_used ();
6001 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
6003 if (flag_stack_usage_info
)
6004 current_function_static_stack_size
= size
;
6006 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
6007 || flag_stack_clash_protection
)
6009 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
6011 if (size
> PROBE_INTERVAL
&& size
> get_stack_check_protect ())
6012 sparc_emit_probe_stack_range (get_stack_check_protect (),
6013 size
- get_stack_check_protect ());
6016 sparc_emit_probe_stack_range (get_stack_check_protect (), size
);
6021 else if (sparc_leaf_function_p
)
6023 rtx size_int_rtx
= GEN_INT (-size
);
6026 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
6027 else if (size
<= 8192)
6029 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
6030 RTX_FRAME_RELATED_P (insn
) = 1;
6032 /* %sp is still the CFA register. */
6033 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
6037 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
6038 emit_move_insn (size_rtx
, size_int_rtx
);
6039 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
6040 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
6041 gen_stack_pointer_inc (size_int_rtx
));
6044 RTX_FRAME_RELATED_P (insn
) = 1;
6048 rtx size_int_rtx
= GEN_INT (-size
);
6051 emit_window_save (size_int_rtx
);
6052 else if (size
<= 8192)
6054 emit_window_save (GEN_INT (-4096));
6056 /* %sp is not the CFA register anymore. */
6057 emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
6059 /* Make sure no %fp-based store is issued until after the frame is
6060 established. The offset between the frame pointer and the stack
6061 pointer is calculated relative to the value of the stack pointer
6062 at the end of the function prologue, and moving instructions that
6063 access the stack via the frame pointer between the instructions
6064 that decrement the stack pointer could result in accessing the
6065 register window save area, which is volatile. */
6066 emit_insn (gen_frame_blockage ());
6070 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
6071 emit_move_insn (size_rtx
, size_int_rtx
);
6072 emit_window_save (size_rtx
);
6076 if (sparc_leaf_function_p
)
6078 sparc_frame_base_reg
= stack_pointer_rtx
;
6079 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
6083 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
6084 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
6087 if (sparc_n_global_fp_regs
> 0)
6088 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
6089 sparc_frame_base_offset
6090 - sparc_apparent_frame_size
,
6093 /* Advertise that the data calculated just above are now valid. */
6094 sparc_prologue_data_valid_p
= true;
6097 /* Expand the function prologue. The prologue is responsible for reserving
6098 storage for the frame, saving the call-saved registers and loading the
6099 GOT register if needed. */
6102 sparc_flat_expand_prologue (void)
6107 sparc_leaf_function_p
= optimize
> 0 && crtl
->is_leaf
;
6109 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
6111 if (flag_stack_usage_info
)
6112 current_function_static_stack_size
= size
;
6114 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
6115 || flag_stack_clash_protection
)
6117 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
6119 if (size
> PROBE_INTERVAL
&& size
> get_stack_check_protect ())
6120 sparc_emit_probe_stack_range (get_stack_check_protect (),
6121 size
- get_stack_check_protect ());
6124 sparc_emit_probe_stack_range (get_stack_check_protect (), size
);
6127 if (sparc_save_local_in_regs_p
)
6128 emit_save_or_restore_local_in_regs (stack_pointer_rtx
, SPARC_STACK_BIAS
,
6135 rtx size_int_rtx
, size_rtx
;
6137 size_rtx
= size_int_rtx
= GEN_INT (-size
);
6139 /* We establish the frame (i.e. decrement the stack pointer) first, even
6140 if we use a frame pointer, because we cannot clobber any call-saved
6141 registers, including the frame pointer, if we haven't created a new
6142 register save area, for the sake of compatibility with the ABI. */
6144 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
6145 else if (size
<= 8192 && !frame_pointer_needed
)
6147 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
6148 RTX_FRAME_RELATED_P (insn
) = 1;
6149 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
6153 size_rtx
= gen_rtx_REG (Pmode
, 1);
6154 emit_move_insn (size_rtx
, size_int_rtx
);
6155 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
6156 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
6157 gen_stack_pointer_inc (size_int_rtx
));
6159 RTX_FRAME_RELATED_P (insn
) = 1;
6161 /* Ensure nothing is scheduled until after the frame is established. */
6162 emit_insn (gen_blockage ());
6164 if (frame_pointer_needed
)
6166 insn
= emit_insn (gen_rtx_SET (hard_frame_pointer_rtx
,
6167 gen_rtx_MINUS (Pmode
,
6170 RTX_FRAME_RELATED_P (insn
) = 1;
6172 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
6173 gen_rtx_SET (hard_frame_pointer_rtx
,
6174 plus_constant (Pmode
, stack_pointer_rtx
,
6178 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
6180 rtx o7
= gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
);
6181 rtx i7
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
6183 insn
= emit_move_insn (i7
, o7
);
6184 RTX_FRAME_RELATED_P (insn
) = 1;
6186 add_reg_note (insn
, REG_CFA_REGISTER
, gen_rtx_SET (i7
, o7
));
6188 /* Prevent this instruction from ever being considered dead,
6189 even if this function has no epilogue. */
6194 if (frame_pointer_needed
)
6196 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
6197 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
6201 sparc_frame_base_reg
= stack_pointer_rtx
;
6202 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
6205 if (sparc_n_global_fp_regs
> 0)
6206 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
6207 sparc_frame_base_offset
6208 - sparc_apparent_frame_size
,
6211 /* Advertise that the data calculated just above are now valid. */
6212 sparc_prologue_data_valid_p
= true;
6215 /* This function generates the assembly code for function entry, which boils
6216 down to emitting the necessary .register directives. */
6219 sparc_asm_function_prologue (FILE *file
)
6221 /* Check that the assumption we made in sparc_expand_prologue is valid. */
6223 gcc_assert (sparc_leaf_function_p
== crtl
->uses_only_leaf_regs
);
6225 sparc_output_scratch_registers (file
);
6228 /* Expand the function epilogue, either normal or part of a sibcall.
6229 We emit all the instructions except the return or the call. */
6232 sparc_expand_epilogue (bool for_eh
)
6234 HOST_WIDE_INT size
= sparc_frame_size
;
6236 if (cfun
->calls_alloca
)
6237 emit_insn (gen_frame_blockage ());
6239 if (sparc_n_global_fp_regs
> 0)
6240 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
6241 sparc_frame_base_offset
6242 - sparc_apparent_frame_size
,
6245 if (size
== 0 || for_eh
)
6247 else if (sparc_leaf_function_p
)
6250 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
6251 else if (size
<= 8192)
6253 emit_insn (gen_stack_pointer_inc (GEN_INT (4096)));
6254 emit_insn (gen_stack_pointer_inc (GEN_INT (size
- 4096)));
6258 rtx reg
= gen_rtx_REG (Pmode
, 1);
6259 emit_move_insn (reg
, GEN_INT (size
));
6260 emit_insn (gen_stack_pointer_inc (reg
));
6265 /* Expand the function epilogue, either normal or part of a sibcall.
6266 We emit all the instructions except the return or the call. */
6269 sparc_flat_expand_epilogue (bool for_eh
)
6271 HOST_WIDE_INT size
= sparc_frame_size
;
6273 if (sparc_n_global_fp_regs
> 0)
6274 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
6275 sparc_frame_base_offset
6276 - sparc_apparent_frame_size
,
6279 /* If we have a frame pointer, we'll need both to restore it before the
6280 frame is destroyed and use its current value in destroying the frame.
6281 Since we don't have an atomic way to do that in the flat window model,
6282 we save the current value into a temporary register (%g1). */
6283 if (frame_pointer_needed
&& !for_eh
)
6284 emit_move_insn (gen_rtx_REG (Pmode
, 1), hard_frame_pointer_rtx
);
6286 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
6287 emit_move_insn (gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
),
6288 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
));
6290 if (sparc_save_local_in_regs_p
)
6291 emit_save_or_restore_local_in_regs (sparc_frame_base_reg
,
6292 sparc_frame_base_offset
,
6295 if (size
== 0 || for_eh
)
6297 else if (frame_pointer_needed
)
6299 /* Make sure the frame is destroyed after everything else is done. */
6300 emit_insn (gen_blockage ());
6302 emit_move_insn (stack_pointer_rtx
, gen_rtx_REG (Pmode
, 1));
6307 emit_insn (gen_blockage ());
6310 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
6311 else if (size
<= 8192)
6313 emit_insn (gen_stack_pointer_inc (GEN_INT (4096)));
6314 emit_insn (gen_stack_pointer_inc (GEN_INT (size
- 4096)));
6318 rtx reg
= gen_rtx_REG (Pmode
, 1);
6319 emit_move_insn (reg
, GEN_INT (size
));
6320 emit_insn (gen_stack_pointer_inc (reg
));
6325 /* Return true if it is appropriate to emit `return' instructions in the
6326 body of a function. */
6329 sparc_can_use_return_insn_p (void)
6331 return sparc_prologue_data_valid_p
6332 && sparc_n_global_fp_regs
== 0
6334 ? (sparc_frame_size
== 0 && !sparc_save_local_in_regs_p
)
6335 : (sparc_frame_size
== 0 || !sparc_leaf_function_p
);
6338 /* This function generates the assembly code for function exit. */
6341 sparc_asm_function_epilogue (FILE *file
)
6343 /* If the last two instructions of a function are "call foo; dslot;"
6344 the return address might point to the first instruction in the next
6345 function and we have to output a dummy nop for the sake of sane
6346 backtraces in such cases. This is pointless for sibling calls since
6347 the return address is explicitly adjusted. */
6349 rtx_insn
*insn
= get_last_insn ();
6351 rtx last_real_insn
= prev_real_insn (insn
);
6353 && NONJUMP_INSN_P (last_real_insn
)
6354 && GET_CODE (PATTERN (last_real_insn
)) == SEQUENCE
)
6355 last_real_insn
= XVECEXP (PATTERN (last_real_insn
), 0, 0);
6358 && CALL_P (last_real_insn
)
6359 && !SIBLING_CALL_P (last_real_insn
))
6360 fputs("\tnop\n", file
);
6362 sparc_output_deferred_case_vectors ();
6365 /* Output a 'restore' instruction. */
6368 output_restore (rtx pat
)
6374 fputs ("\t restore\n", asm_out_file
);
6378 gcc_assert (GET_CODE (pat
) == SET
);
6380 operands
[0] = SET_DEST (pat
);
6381 pat
= SET_SRC (pat
);
6383 switch (GET_CODE (pat
))
6386 operands
[1] = XEXP (pat
, 0);
6387 operands
[2] = XEXP (pat
, 1);
6388 output_asm_insn (" restore %r1, %2, %Y0", operands
);
6391 operands
[1] = XEXP (pat
, 0);
6392 operands
[2] = XEXP (pat
, 1);
6393 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands
);
6396 operands
[1] = XEXP (pat
, 0);
6397 gcc_assert (XEXP (pat
, 1) == const1_rtx
);
6398 output_asm_insn (" restore %r1, %r1, %Y0", operands
);
6402 output_asm_insn (" restore %%g0, %1, %Y0", operands
);
6407 /* Output a return. */
6410 output_return (rtx_insn
*insn
)
6412 if (crtl
->calls_eh_return
)
6414 /* If the function uses __builtin_eh_return, the eh_return
6415 machinery occupies the delay slot. */
6416 gcc_assert (!final_sequence
);
6418 if (flag_delayed_branch
)
6420 if (!TARGET_FLAT
&& TARGET_V9
)
6421 fputs ("\treturn\t%i7+8\n", asm_out_file
);
6425 fputs ("\trestore\n", asm_out_file
);
6427 fputs ("\tjmp\t%o7+8\n", asm_out_file
);
6430 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file
);
6435 fputs ("\trestore\n", asm_out_file
);
6437 fputs ("\tadd\t%sp, %g1, %sp\n", asm_out_file
);
6438 fputs ("\tjmp\t%o7+8\n\t nop\n", asm_out_file
);
6441 else if (sparc_leaf_function_p
|| TARGET_FLAT
)
6443 /* This is a leaf or flat function so we don't have to bother restoring
6444 the register window, which frees us from dealing with the convoluted
6445 semantics of restore/return. We simply output the jump to the
6446 return address and the insn in the delay slot (if any). */
6448 return "jmp\t%%o7+%)%#";
6452 /* This is a regular function so we have to restore the register window.
6453 We may have a pending insn for the delay slot, which will be either
6454 combined with the 'restore' instruction or put in the delay slot of
6455 the 'return' instruction. */
6462 delay
= NEXT_INSN (insn
);
6465 pat
= PATTERN (delay
);
6467 if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1))
6469 epilogue_renumber (&pat
, 0);
6470 return "return\t%%i7+%)%#";
6474 output_asm_insn ("jmp\t%%i7+%)", NULL
);
6476 /* We're going to output the insn in the delay slot manually.
6477 Make sure to output its source location first. */
6478 PATTERN (delay
) = gen_blockage ();
6479 INSN_CODE (delay
) = -1;
6480 final_scan_insn (delay
, asm_out_file
, optimize
, 0, NULL
);
6481 INSN_LOCATION (delay
) = UNKNOWN_LOCATION
;
6483 output_restore (pat
);
6488 /* The delay slot is empty. */
6490 return "return\t%%i7+%)\n\t nop";
6491 else if (flag_delayed_branch
)
6492 return "jmp\t%%i7+%)\n\t restore";
6494 return "restore\n\tjmp\t%%o7+%)\n\t nop";
6501 /* Output a sibling call. */
6504 output_sibcall (rtx_insn
*insn
, rtx call_operand
)
6508 gcc_assert (flag_delayed_branch
);
6510 operands
[0] = call_operand
;
6512 if (sparc_leaf_function_p
|| TARGET_FLAT
)
6514 /* This is a leaf or flat function so we don't have to bother restoring
6515 the register window. We simply output the jump to the function and
6516 the insn in the delay slot (if any). */
6518 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P
&& final_sequence
));
6521 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
6524 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
6525 it into branch if possible. */
6526 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
6531 /* This is a regular function so we have to restore the register window.
6532 We may have a pending insn for the delay slot, which will be combined
6533 with the 'restore' instruction. */
6535 output_asm_insn ("call\t%a0, 0", operands
);
6542 delay
= NEXT_INSN (insn
);
6545 pat
= PATTERN (delay
);
6547 /* We're going to output the insn in the delay slot manually.
6548 Make sure to output its source location first. */
6549 PATTERN (delay
) = gen_blockage ();
6550 INSN_CODE (delay
) = -1;
6551 final_scan_insn (delay
, asm_out_file
, optimize
, 0, NULL
);
6552 INSN_LOCATION (delay
) = UNKNOWN_LOCATION
;
6554 output_restore (pat
);
6557 output_restore (NULL_RTX
);
6563 /* Functions for handling argument passing.
6565 For 32-bit, the first 6 args are normally in registers and the rest are
6566 pushed. Any arg that starts within the first 6 words is at least
6567 partially passed in a register unless its data type forbids.
6569 For 64-bit, the argument registers are laid out as an array of 16 elements
6570 and arguments are added sequentially. The first 6 int args and up to the
6571 first 16 fp args (depending on size) are passed in regs.
6573 Slot Stack Integral Float Float in structure Double Long Double
6574 ---- ----- -------- ----- ------------------ ------ -----------
6575 15 [SP+248] %f31 %f30,%f31 %d30
6576 14 [SP+240] %f29 %f28,%f29 %d28 %q28
6577 13 [SP+232] %f27 %f26,%f27 %d26
6578 12 [SP+224] %f25 %f24,%f25 %d24 %q24
6579 11 [SP+216] %f23 %f22,%f23 %d22
6580 10 [SP+208] %f21 %f20,%f21 %d20 %q20
6581 9 [SP+200] %f19 %f18,%f19 %d18
6582 8 [SP+192] %f17 %f16,%f17 %d16 %q16
6583 7 [SP+184] %f15 %f14,%f15 %d14
6584 6 [SP+176] %f13 %f12,%f13 %d12 %q12
6585 5 [SP+168] %o5 %f11 %f10,%f11 %d10
6586 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
6587 3 [SP+152] %o3 %f7 %f6,%f7 %d6
6588 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
6589 1 [SP+136] %o1 %f3 %f2,%f3 %d2
6590 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
6592 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
6594 Integral arguments are always passed as 64-bit quantities appropriately
6597 Passing of floating point values is handled as follows.
6598 If a prototype is in scope:
6599 If the value is in a named argument (i.e. not a stdarg function or a
6600 value not part of the `...') then the value is passed in the appropriate
6602 If the value is part of the `...' and is passed in one of the first 6
6603 slots then the value is passed in the appropriate int reg.
6604 If the value is part of the `...' and is not passed in one of the first 6
6605 slots then the value is passed in memory.
6606 If a prototype is not in scope:
6607 If the value is one of the first 6 arguments the value is passed in the
6608 appropriate integer reg and the appropriate fp reg.
6609 If the value is not one of the first 6 arguments the value is passed in
6610 the appropriate fp reg and in memory.
6613 Summary of the calling conventions implemented by GCC on the SPARC:
6616 size argument return value
6618 small integer <4 int. reg. int. reg.
6619 word 4 int. reg. int. reg.
6620 double word 8 int. reg. int. reg.
6622 _Complex small integer <8 int. reg. int. reg.
6623 _Complex word 8 int. reg. int. reg.
6624 _Complex double word 16 memory int. reg.
6626 vector integer <=8 int. reg. FP reg.
6627 vector integer >8 memory memory
6629 float 4 int. reg. FP reg.
6630 double 8 int. reg. FP reg.
6631 long double 16 memory memory
6633 _Complex float 8 memory FP reg.
6634 _Complex double 16 memory FP reg.
6635 _Complex long double 32 memory FP reg.
6637 vector float any memory memory
6639 aggregate any memory memory
6644 size argument return value
6646 small integer <8 int. reg. int. reg.
6647 word 8 int. reg. int. reg.
6648 double word 16 int. reg. int. reg.
6650 _Complex small integer <16 int. reg. int. reg.
6651 _Complex word 16 int. reg. int. reg.
6652 _Complex double word 32 memory int. reg.
6654 vector integer <=16 FP reg. FP reg.
6655 vector integer 16<s<=32 memory FP reg.
6656 vector integer >32 memory memory
6658 float 4 FP reg. FP reg.
6659 double 8 FP reg. FP reg.
6660 long double 16 FP reg. FP reg.
6662 _Complex float 8 FP reg. FP reg.
6663 _Complex double 16 FP reg. FP reg.
6664 _Complex long double 32 memory FP reg.
6666 vector float <=16 FP reg. FP reg.
6667 vector float 16<s<=32 memory FP reg.
6668 vector float >32 memory memory
6670 aggregate <=16 reg. reg.
6671 aggregate 16<s<=32 memory reg.
6672 aggregate >32 memory memory
6676 Note #1: complex floating-point types follow the extended SPARC ABIs as
6677 implemented by the Sun compiler.
6679 Note #2: integer vector types follow the scalar floating-point types
6680 conventions to match what is implemented by the Sun VIS SDK.
6682 Note #3: floating-point vector types follow the aggregate types
6686 /* Maximum number of int regs for args. */
6687 #define SPARC_INT_ARG_MAX 6
6688 /* Maximum number of fp regs for args. */
6689 #define SPARC_FP_ARG_MAX 16
6690 /* Number of words (partially) occupied for a given size in units. */
6691 #define CEIL_NWORDS(SIZE) CEIL((SIZE), UNITS_PER_WORD)
6693 /* Handle the INIT_CUMULATIVE_ARGS macro.
6694 Initialize a variable CUM of type CUMULATIVE_ARGS
6695 for a call to a function whose data type is FNTYPE.
6696 For a library call, FNTYPE is 0. */
6699 init_cumulative_args (struct sparc_args
*cum
, tree fntype
, rtx
, tree
)
6702 cum
->prototype_p
= fntype
&& prototype_p (fntype
);
6703 cum
->libcall_p
= !fntype
;
6706 /* Handle promotion of pointer and integer arguments. */
6709 sparc_promote_function_mode (const_tree type
, machine_mode mode
,
6710 int *punsignedp
, const_tree
, int)
6712 if (type
&& POINTER_TYPE_P (type
))
6714 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
6718 /* Integral arguments are passed as full words, as per the ABI. */
6719 if (GET_MODE_CLASS (mode
) == MODE_INT
6720 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
6726 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
6729 sparc_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
6731 return TARGET_ARCH64
? true : false;
6734 /* Handle the TARGET_PASS_BY_REFERENCE target hook.
6735 Specify whether to pass the argument by reference. */
6738 sparc_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
6739 machine_mode mode
, const_tree type
,
6740 bool named ATTRIBUTE_UNUSED
)
6743 /* Original SPARC 32-bit ABI says that structures and unions,
6744 and quad-precision floats are passed by reference.
6745 All other base types are passed in registers.
6747 Extended ABI (as implemented by the Sun compiler) says that all
6748 complex floats are passed by reference. Pass complex integers
6749 in registers up to 8 bytes. More generally, enforce the 2-word
6750 cap for passing arguments in registers.
6752 Vector ABI (as implemented by the Sun VIS SDK) says that integer
6753 vectors are passed like floats of the same size, that is in
6754 registers up to 8 bytes. Pass all vector floats by reference
6755 like structure and unions. */
6756 return ((type
&& (AGGREGATE_TYPE_P (type
) || VECTOR_FLOAT_TYPE_P (type
)))
6758 /* Catch CDImode, TFmode, DCmode and TCmode. */
6759 || GET_MODE_SIZE (mode
) > 8
6761 && VECTOR_TYPE_P (type
)
6762 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
6764 /* Original SPARC 64-bit ABI says that structures and unions
6765 smaller than 16 bytes are passed in registers, as well as
6766 all other base types.
6768 Extended ABI (as implemented by the Sun compiler) says that
6769 complex floats are passed in registers up to 16 bytes. Pass
6770 all complex integers in registers up to 16 bytes. More generally,
6771 enforce the 2-word cap for passing arguments in registers.
6773 Vector ABI (as implemented by the Sun VIS SDK) says that integer
6774 vectors are passed like floats of the same size, that is in
6775 registers (up to 16 bytes). Pass all vector floats like structure
6778 && (AGGREGATE_TYPE_P (type
) || VECTOR_TYPE_P (type
))
6779 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 16)
6780 /* Catch CTImode and TCmode. */
6781 || GET_MODE_SIZE (mode
) > 16);
6784 /* Traverse the record TYPE recursively and call FUNC on its fields.
6785 NAMED is true if this is for a named parameter. DATA is passed
6786 to FUNC for each field. OFFSET is the starting position and
6787 PACKED is true if we are inside a packed record. */
6789 template <typename T
, void Func (const_tree
, int, bool, T
*)>
6791 traverse_record_type (const_tree type
, bool named
, T
*data
,
6792 int offset
= 0, bool packed
= false)
6794 /* The ABI obviously doesn't specify how packed structures are passed.
6795 These are passed in integer regs if possible, otherwise memory. */
6797 for (tree field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
6798 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
6804 /* Walk the real fields, but skip those with no size or a zero size.
6805 ??? Fields with variable offset are handled as having zero offset. */
6806 for (tree field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
6807 if (TREE_CODE (field
) == FIELD_DECL
)
6809 if (!DECL_SIZE (field
) || integer_zerop (DECL_SIZE (field
)))
6812 int bitpos
= offset
;
6813 if (TREE_CODE (DECL_FIELD_OFFSET (field
)) == INTEGER_CST
)
6814 bitpos
+= int_bit_position (field
);
6816 tree field_type
= TREE_TYPE (field
);
6817 if (TREE_CODE (field_type
) == RECORD_TYPE
)
6818 traverse_record_type
<T
, Func
> (field_type
, named
, data
, bitpos
,
6823 = FLOAT_TYPE_P (field_type
) || VECTOR_TYPE_P (field_type
);
6824 Func (field
, bitpos
, fp_type
&& named
&& !packed
&& TARGET_FPU
,
6830 /* Handle recursive register classifying for structure layout. */
6834 bool fp_regs
; /* true if field eligible to FP registers. */
6835 bool fp_regs_in_first_word
; /* true if such field in first word. */
6838 /* A subroutine of function_arg_slotno. Classify the field. */
6841 classify_registers (const_tree
, int bitpos
, bool fp
, classify_data_t
*data
)
6845 data
->fp_regs
= true;
6846 if (bitpos
< BITS_PER_WORD
)
6847 data
->fp_regs_in_first_word
= true;
6851 /* Compute the slot number to pass an argument in.
6852 Return the slot number or -1 if passing on the stack.
6854 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6855 the preceding args and about the function being called.
6856 MODE is the argument's machine mode.
6857 TYPE is the data type of the argument (as a tree).
6858 This is null for libcalls where that information may
6860 NAMED is nonzero if this argument is a named parameter
6861 (otherwise it is an extra parameter matching an ellipsis).
6862 INCOMING is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
6863 *PREGNO records the register number to use if scalar type.
6864 *PPADDING records the amount of padding needed in words. */
6867 function_arg_slotno (const struct sparc_args
*cum
, machine_mode mode
,
6868 const_tree type
, bool named
, bool incoming
,
6869 int *pregno
, int *ppadding
)
6872 = incoming
? SPARC_INCOMING_INT_ARG_FIRST
: SPARC_OUTGOING_INT_ARG_FIRST
;
6873 int slotno
= cum
->words
, regno
;
6874 enum mode_class mclass
= GET_MODE_CLASS (mode
);
6876 if (type
&& TREE_ADDRESSABLE (type
))
6879 /* In 64-bit mode, objects requiring 16-byte alignment get it. */
6881 && (type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
)) >= 128
6882 && (slotno
& 1) != 0)
6890 /* Vector types deserve special treatment because they are polymorphic wrt
6891 their mode, depending upon whether VIS instructions are enabled. */
6892 if (type
&& VECTOR_TYPE_P (type
))
6894 if (TREE_CODE (TREE_TYPE (type
)) == REAL_TYPE
)
6896 /* The SPARC port defines no floating-point vector modes. */
6897 gcc_assert (mode
== BLKmode
);
6901 /* Integer vector types should either have a vector
6902 mode or an integral mode, because we are guaranteed
6903 by pass_by_reference that their size is not greater
6904 than 16 bytes and TImode is 16-byte wide. */
6905 gcc_assert (mode
!= BLKmode
);
6907 /* Integer vectors are handled like floats as per
6909 mclass
= MODE_FLOAT
;
6916 case MODE_COMPLEX_FLOAT
:
6917 case MODE_VECTOR_INT
:
6918 if (TARGET_ARCH64
&& TARGET_FPU
&& named
)
6920 /* If all arg slots are filled, then must pass on stack. */
6921 if (slotno
>= SPARC_FP_ARG_MAX
)
6924 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
6925 /* Arguments filling only one single FP register are
6926 right-justified in the outer double FP register. */
6927 if (GET_MODE_SIZE (mode
) <= 4)
6934 case MODE_COMPLEX_INT
:
6935 /* If all arg slots are filled, then must pass on stack. */
6936 if (slotno
>= SPARC_INT_ARG_MAX
)
6939 regno
= regbase
+ slotno
;
6943 /* MODE is VOIDmode when generating the actual call. */
6944 if (mode
== VOIDmode
)
6947 if (TARGET_64BIT
&& TARGET_FPU
&& named
6949 && (TREE_CODE (type
) == RECORD_TYPE
|| VECTOR_TYPE_P (type
)))
6951 /* If all arg slots are filled, then must pass on stack. */
6952 if (slotno
>= SPARC_FP_ARG_MAX
)
6955 if (TREE_CODE (type
) == RECORD_TYPE
)
6957 classify_data_t data
= { false, false };
6958 traverse_record_type
<classify_data_t
, classify_registers
>
6959 (type
, named
, &data
);
6963 /* If all FP slots are filled except for the last one and
6964 there is no FP field in the first word, then must pass
6966 if (slotno
>= SPARC_FP_ARG_MAX
- 1
6967 && !data
.fp_regs_in_first_word
)
6972 /* If all int slots are filled, then must pass on stack. */
6973 if (slotno
>= SPARC_INT_ARG_MAX
)
6977 /* PREGNO isn't set since both int and FP regs can be used. */
6981 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
6985 /* If all arg slots are filled, then must pass on stack. */
6986 if (slotno
>= SPARC_INT_ARG_MAX
)
6989 regno
= regbase
+ slotno
;
7001 /* Handle recursive register counting/assigning for structure layout. */
7005 int slotno
; /* slot number of the argument. */
7006 int regbase
; /* regno of the base register. */
7007 int intoffset
; /* offset of the first pending integer field. */
7008 int nregs
; /* number of words passed in registers. */
7009 bool stack
; /* true if part of the argument is on the stack. */
7010 rtx ret
; /* return expression being built. */
7013 /* A subroutine of function_arg_record_value. Compute the number of integer
7014 registers to be assigned between PARMS->intoffset and BITPOS. Return
7015 true if at least one integer register is assigned or false otherwise. */
7018 compute_int_layout (int bitpos
, assign_data_t
*data
, int *pnregs
)
7020 if (data
->intoffset
< 0)
7023 const int intoffset
= data
->intoffset
;
7024 data
->intoffset
= -1;
7026 const int this_slotno
= data
->slotno
+ intoffset
/ BITS_PER_WORD
;
7027 const unsigned int startbit
= ROUND_DOWN (intoffset
, BITS_PER_WORD
);
7028 const unsigned int endbit
= ROUND_UP (bitpos
, BITS_PER_WORD
);
7029 int nregs
= (endbit
- startbit
) / BITS_PER_WORD
;
7031 if (nregs
> 0 && nregs
> SPARC_INT_ARG_MAX
- this_slotno
)
7033 nregs
= SPARC_INT_ARG_MAX
- this_slotno
;
7035 /* We need to pass this field (partly) on the stack. */
7046 /* A subroutine of function_arg_record_value. Compute the number and the mode
7047 of the FP registers to be assigned for FIELD. Return true if at least one
7048 FP register is assigned or false otherwise. */
7051 compute_fp_layout (const_tree field
, int bitpos
, assign_data_t
*data
,
7052 int *pnregs
, machine_mode
*pmode
)
7054 const int this_slotno
= data
->slotno
+ bitpos
/ BITS_PER_WORD
;
7055 machine_mode mode
= DECL_MODE (field
);
7058 /* Slots are counted as words while regs are counted as having the size of
7059 the (inner) mode. */
7060 if (VECTOR_TYPE_P (TREE_TYPE (field
)) && mode
== BLKmode
)
7062 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
7063 nregs
= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
7065 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
7067 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
7073 nslots
= CEIL_NWORDS (nregs
* GET_MODE_SIZE (mode
));
7075 if (nslots
> SPARC_FP_ARG_MAX
- this_slotno
)
7077 nslots
= SPARC_FP_ARG_MAX
- this_slotno
;
7078 nregs
= (nslots
* UNITS_PER_WORD
) / GET_MODE_SIZE (mode
);
7080 /* We need to pass this field (partly) on the stack. */
7092 /* A subroutine of function_arg_record_value. Count the number of registers
7093 to be assigned for FIELD and between PARMS->intoffset and BITPOS. */
7096 count_registers (const_tree field
, int bitpos
, bool fp
, assign_data_t
*data
)
7103 if (compute_int_layout (bitpos
, data
, &nregs
))
7104 data
->nregs
+= nregs
;
7106 if (compute_fp_layout (field
, bitpos
, data
, &nregs
, &mode
))
7107 data
->nregs
+= nregs
;
7111 if (data
->intoffset
< 0)
7112 data
->intoffset
= bitpos
;
7116 /* A subroutine of function_arg_record_value. Assign the bits of the
7117 structure between PARMS->intoffset and BITPOS to integer registers. */
7120 assign_int_registers (int bitpos
, assign_data_t
*data
)
7122 int intoffset
= data
->intoffset
;
7126 if (!compute_int_layout (bitpos
, data
, &nregs
))
7129 /* If this is the trailing part of a word, only load that much into
7130 the register. Otherwise load the whole register. Note that in
7131 the latter case we may pick up unwanted bits. It's not a problem
7132 at the moment but may wish to revisit. */
7133 if (intoffset
% BITS_PER_WORD
!= 0)
7134 mode
= smallest_int_mode_for_size (BITS_PER_WORD
7135 - intoffset
% BITS_PER_WORD
);
7139 const int this_slotno
= data
->slotno
+ intoffset
/ BITS_PER_WORD
;
7140 unsigned int regno
= data
->regbase
+ this_slotno
;
7141 intoffset
/= BITS_PER_UNIT
;
7145 rtx reg
= gen_rtx_REG (mode
, regno
);
7146 XVECEXP (data
->ret
, 0, data
->stack
+ data
->nregs
)
7147 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
7151 intoffset
= (intoffset
| (UNITS_PER_WORD
- 1)) + 1;
7153 while (--nregs
> 0);
7156 /* A subroutine of function_arg_record_value. Assign FIELD at position
7157 BITPOS to FP registers. */
7160 assign_fp_registers (const_tree field
, int bitpos
, assign_data_t
*data
)
7165 if (!compute_fp_layout (field
, bitpos
, data
, &nregs
, &mode
))
7168 const int this_slotno
= data
->slotno
+ bitpos
/ BITS_PER_WORD
;
7169 int regno
= SPARC_FP_ARG_FIRST
+ this_slotno
* 2;
7170 if (GET_MODE_SIZE (mode
) <= 4 && (bitpos
& 32) != 0)
7172 int pos
= bitpos
/ BITS_PER_UNIT
;
7176 rtx reg
= gen_rtx_REG (mode
, regno
);
7177 XVECEXP (data
->ret
, 0, data
->stack
+ data
->nregs
)
7178 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
7180 regno
+= GET_MODE_SIZE (mode
) / 4;
7181 pos
+= GET_MODE_SIZE (mode
);
7183 while (--nregs
> 0);
7186 /* A subroutine of function_arg_record_value. Assign FIELD and the bits of
7187 the structure between PARMS->intoffset and BITPOS to registers. */
7190 assign_registers (const_tree field
, int bitpos
, bool fp
, assign_data_t
*data
)
7194 assign_int_registers (bitpos
, data
);
7196 assign_fp_registers (field
, bitpos
, data
);
7200 if (data
->intoffset
< 0)
7201 data
->intoffset
= bitpos
;
7205 /* Used by function_arg and function_value to implement the complex
7206 conventions of the 64-bit ABI for passing and returning structures.
7207 Return an expression valid as a return value for the FUNCTION_ARG
7208 and TARGET_FUNCTION_VALUE.
7210 TYPE is the data type of the argument (as a tree).
7211 This is null for libcalls where that information may
7213 MODE is the argument's machine mode.
7214 SLOTNO is the index number of the argument's slot in the parameter array.
7215 NAMED is true if this argument is a named parameter
7216 (otherwise it is an extra parameter matching an ellipsis).
7217 REGBASE is the regno of the base register for the parameter array. */
7220 function_arg_record_value (const_tree type
, machine_mode mode
,
7221 int slotno
, bool named
, int regbase
)
7223 const int size
= int_size_in_bytes (type
);
7227 data
.slotno
= slotno
;
7228 data
.regbase
= regbase
;
7230 /* Count how many registers we need. */
7234 traverse_record_type
<assign_data_t
, count_registers
> (type
, named
, &data
);
7236 /* Take into account pending integer fields. */
7237 if (compute_int_layout (size
* BITS_PER_UNIT
, &data
, &nregs
))
7238 data
.nregs
+= nregs
;
7240 /* Allocate the vector and handle some annoying special cases. */
7245 /* ??? Empty structure has no value? Duh? */
7248 /* Though there's nothing really to store, return a word register
7249 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
7250 leads to breakage due to the fact that there are zero bytes to
7252 return gen_rtx_REG (mode
, regbase
);
7255 /* ??? C++ has structures with no fields, and yet a size. Give up
7256 for now and pass everything back in integer registers. */
7257 nregs
= CEIL_NWORDS (size
);
7258 if (nregs
+ slotno
> SPARC_INT_ARG_MAX
)
7259 nregs
= SPARC_INT_ARG_MAX
- slotno
;
7262 gcc_assert (nregs
> 0);
7264 data
.ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (data
.stack
+ nregs
));
7266 /* If at least one field must be passed on the stack, generate
7267 (parallel [(expr_list (nil) ...) ...]) so that all fields will
7268 also be passed on the stack. We can't do much better because the
7269 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
7270 of structures for which the fields passed exclusively in registers
7271 are not at the beginning of the structure. */
7273 XVECEXP (data
.ret
, 0, 0)
7274 = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
7276 /* Assign the registers. */
7279 traverse_record_type
<assign_data_t
, assign_registers
> (type
, named
, &data
);
7281 /* Assign pending integer fields. */
7282 assign_int_registers (size
* BITS_PER_UNIT
, &data
);
7284 gcc_assert (data
.nregs
== nregs
);
7289 /* Used by function_arg and function_value to implement the conventions
7290 of the 64-bit ABI for passing and returning unions.
7291 Return an expression valid as a return value for the FUNCTION_ARG
7292 and TARGET_FUNCTION_VALUE.
7294 SIZE is the size in bytes of the union.
7295 MODE is the argument's machine mode.
7296 SLOTNO is the index number of the argument's slot in the parameter array.
7297 REGNO is the hard register the union will be passed in. */
7300 function_arg_union_value (int size
, machine_mode mode
, int slotno
, int regno
)
7302 unsigned int nwords
;
7304 /* See comment in function_arg_record_value for empty structures. */
7306 return gen_rtx_REG (mode
, regno
);
7308 if (slotno
== SPARC_INT_ARG_MAX
- 1)
7311 nwords
= CEIL_NWORDS (size
);
7313 rtx regs
= gen_rtx_PARALLEL (mode
, rtvec_alloc (nwords
));
7315 /* Unions are passed left-justified. */
7316 for (unsigned int i
= 0; i
< nwords
; i
++)
7317 XVECEXP (regs
, 0, i
)
7318 = gen_rtx_EXPR_LIST (VOIDmode
,
7319 gen_rtx_REG (word_mode
, regno
+ i
),
7320 GEN_INT (UNITS_PER_WORD
* i
));
7325 /* Used by function_arg and function_value to implement the conventions
7326 of the 64-bit ABI for passing and returning BLKmode vectors.
7327 Return an expression valid as a return value for the FUNCTION_ARG
7328 and TARGET_FUNCTION_VALUE.
7330 SIZE is the size in bytes of the vector.
7331 SLOTNO is the index number of the argument's slot in the parameter array.
7332 NAMED is true if this argument is a named parameter
7333 (otherwise it is an extra parameter matching an ellipsis).
7334 REGNO is the hard register the vector will be passed in. */
7337 function_arg_vector_value (int size
, int slotno
, bool named
, int regno
)
7339 const int mult
= (named
? 2 : 1);
7340 unsigned int nwords
;
7342 if (slotno
== (named
? SPARC_FP_ARG_MAX
: SPARC_INT_ARG_MAX
) - 1)
7345 nwords
= CEIL_NWORDS (size
);
7347 rtx regs
= gen_rtx_PARALLEL (BLKmode
, rtvec_alloc (nwords
));
7349 if (size
< UNITS_PER_WORD
)
7350 XVECEXP (regs
, 0, 0)
7351 = gen_rtx_EXPR_LIST (VOIDmode
,
7352 gen_rtx_REG (SImode
, regno
),
7355 for (unsigned int i
= 0; i
< nwords
; i
++)
7356 XVECEXP (regs
, 0, i
)
7357 = gen_rtx_EXPR_LIST (VOIDmode
,
7358 gen_rtx_REG (word_mode
, regno
+ i
* mult
),
7359 GEN_INT (i
* UNITS_PER_WORD
));
7364 /* Determine where to put an argument to a function.
7365 Value is zero to push the argument on the stack,
7366 or a hard register in which to store the argument.
7368 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7369 the preceding args and about the function being called.
7370 MODE is the argument's machine mode.
7371 TYPE is the data type of the argument (as a tree).
7372 This is null for libcalls where that information may
7374 NAMED is true if this argument is a named parameter
7375 (otherwise it is an extra parameter matching an ellipsis).
7376 INCOMING_P is false for TARGET_FUNCTION_ARG, true for
7377 TARGET_FUNCTION_INCOMING_ARG. */
7380 sparc_function_arg_1 (cumulative_args_t cum_v
, machine_mode mode
,
7381 const_tree type
, bool named
, bool incoming
)
7383 const CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
7385 = incoming
? SPARC_INCOMING_INT_ARG_FIRST
: SPARC_OUTGOING_INT_ARG_FIRST
;
7386 int slotno
, regno
, padding
;
7387 enum mode_class mclass
= GET_MODE_CLASS (mode
);
7390 = function_arg_slotno (cum
, mode
, type
, named
, incoming
, ®no
, &padding
);
7394 /* Integer vectors are handled like floats as per the Sun VIS SDK. */
7395 if (type
&& VECTOR_INTEGER_TYPE_P (type
))
7396 mclass
= MODE_FLOAT
;
7399 return gen_rtx_REG (mode
, regno
);
7401 /* Structures up to 16 bytes in size are passed in arg slots on the stack
7402 and are promoted to registers if possible. */
7403 if (type
&& TREE_CODE (type
) == RECORD_TYPE
)
7405 const int size
= int_size_in_bytes (type
);
7406 gcc_assert (size
<= 16);
7408 return function_arg_record_value (type
, mode
, slotno
, named
, regbase
);
7411 /* Unions up to 16 bytes in size are passed in integer registers. */
7412 else if (type
&& TREE_CODE (type
) == UNION_TYPE
)
7414 const int size
= int_size_in_bytes (type
);
7415 gcc_assert (size
<= 16);
7417 return function_arg_union_value (size
, mode
, slotno
, regno
);
7420 /* Floating-point vectors up to 16 bytes are passed in registers. */
7421 else if (type
&& VECTOR_TYPE_P (type
) && mode
== BLKmode
)
7423 const int size
= int_size_in_bytes (type
);
7424 gcc_assert (size
<= 16);
7426 return function_arg_vector_value (size
, slotno
, named
, regno
);
7429 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
7430 but also have the slot allocated for them.
7431 If no prototype is in scope fp values in register slots get passed
7432 in two places, either fp regs and int regs or fp regs and memory. */
7433 else if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
7434 && SPARC_FP_REG_P (regno
))
7436 rtx reg
= gen_rtx_REG (mode
, regno
);
7437 if (cum
->prototype_p
|| cum
->libcall_p
)
7443 if ((regno
- SPARC_FP_ARG_FIRST
) < SPARC_INT_ARG_MAX
* 2)
7447 /* On incoming, we don't need to know that the value
7448 is passed in %f0 and %i0, and it confuses other parts
7449 causing needless spillage even on the simplest cases. */
7453 intreg
= (SPARC_OUTGOING_INT_ARG_FIRST
7454 + (regno
- SPARC_FP_ARG_FIRST
) / 2);
7456 v0
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
7457 v1
= gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (mode
, intreg
),
7459 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
7463 v0
= gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
7464 v1
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
7465 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
7470 /* All other aggregate types are passed in an integer register in a mode
7471 corresponding to the size of the type. */
7472 else if (type
&& AGGREGATE_TYPE_P (type
))
7474 const int size
= int_size_in_bytes (type
);
7475 gcc_assert (size
<= 16);
7477 mode
= int_mode_for_size (size
* BITS_PER_UNIT
, 0).else_blk ();
7480 return gen_rtx_REG (mode
, regno
);
7483 /* Handle the TARGET_FUNCTION_ARG target hook. */
7486 sparc_function_arg (cumulative_args_t cum
, machine_mode mode
,
7487 const_tree type
, bool named
)
7489 return sparc_function_arg_1 (cum
, mode
, type
, named
, false);
7492 /* Handle the TARGET_FUNCTION_INCOMING_ARG target hook. */
7495 sparc_function_incoming_arg (cumulative_args_t cum
, machine_mode mode
,
7496 const_tree type
, bool named
)
7498 return sparc_function_arg_1 (cum
, mode
, type
, named
, true);
7501 /* For sparc64, objects requiring 16 byte alignment are passed that way. */
7504 sparc_function_arg_boundary (machine_mode mode
, const_tree type
)
7506 return ((TARGET_ARCH64
7507 && (GET_MODE_ALIGNMENT (mode
) == 128
7508 || (type
&& TYPE_ALIGN (type
) == 128)))
7513 /* For an arg passed partly in registers and partly in memory,
7514 this is the number of bytes of registers used.
7515 For args passed entirely in registers or entirely in memory, zero.
7517 Any arg that starts in the first 6 regs but won't entirely fit in them
7518 needs partial registers on v8. On v9, structures with integer
7519 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
7520 values that begin in the last fp reg [where "last fp reg" varies with the
7521 mode] will be split between that reg and memory. */
7524 sparc_arg_partial_bytes (cumulative_args_t cum
, machine_mode mode
,
7525 tree type
, bool named
)
7527 int slotno
, regno
, padding
;
7529 /* We pass false for incoming here, it doesn't matter. */
7530 slotno
= function_arg_slotno (get_cumulative_args (cum
), mode
, type
, named
,
7531 false, ®no
, &padding
);
7538 /* We are guaranteed by pass_by_reference that the size of the
7539 argument is not greater than 8 bytes, so we only need to return
7540 one word if the argument is partially passed in registers. */
7541 const int size
= GET_MODE_SIZE (mode
);
7543 if (size
> UNITS_PER_WORD
&& slotno
== SPARC_INT_ARG_MAX
- 1)
7544 return UNITS_PER_WORD
;
7548 /* We are guaranteed by pass_by_reference that the size of the
7549 argument is not greater than 16 bytes, so we only need to return
7550 one word if the argument is partially passed in registers. */
7551 if (type
&& AGGREGATE_TYPE_P (type
))
7553 const int size
= int_size_in_bytes (type
);
7555 if (size
> UNITS_PER_WORD
7556 && (slotno
== SPARC_INT_ARG_MAX
- 1
7557 || slotno
== SPARC_FP_ARG_MAX
- 1))
7558 return UNITS_PER_WORD
;
7560 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
7561 || ((GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
7562 || (type
&& VECTOR_TYPE_P (type
)))
7563 && !(TARGET_FPU
&& named
)))
7565 const int size
= (type
&& VECTOR_FLOAT_TYPE_P (type
))
7566 ? int_size_in_bytes (type
)
7567 : GET_MODE_SIZE (mode
);
7569 if (size
> UNITS_PER_WORD
&& slotno
== SPARC_INT_ARG_MAX
- 1)
7570 return UNITS_PER_WORD
;
7572 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
7573 || (type
&& VECTOR_TYPE_P (type
)))
7575 const int size
= (type
&& VECTOR_FLOAT_TYPE_P (type
))
7576 ? int_size_in_bytes (type
)
7577 : GET_MODE_SIZE (mode
);
7579 if (size
> UNITS_PER_WORD
&& slotno
== SPARC_FP_ARG_MAX
- 1)
7580 return UNITS_PER_WORD
;
7587 /* Handle the TARGET_FUNCTION_ARG_ADVANCE hook.
7588 Update the data in CUM to advance over an argument
7589 of mode MODE and data type TYPE.
7590 TYPE is null for libcalls where that information may not be available. */
7593 sparc_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
7594 const_tree type
, bool named
)
7596 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
7599 /* We pass false for incoming here, it doesn't matter. */
7600 function_arg_slotno (cum
, mode
, type
, named
, false, ®no
, &padding
);
7602 /* If argument requires leading padding, add it. */
7603 cum
->words
+= padding
;
7606 cum
->words
+= CEIL_NWORDS (GET_MODE_SIZE (mode
));
7609 /* For types that can have BLKmode, get the size from the type. */
7610 if (type
&& (AGGREGATE_TYPE_P (type
) || VECTOR_FLOAT_TYPE_P (type
)))
7612 const int size
= int_size_in_bytes (type
);
7614 /* See comment in function_arg_record_value for empty structures. */
7618 cum
->words
+= CEIL_NWORDS (size
);
7621 cum
->words
+= CEIL_NWORDS (GET_MODE_SIZE (mode
));
7625 /* Implement TARGET_FUNCTION_ARG_PADDING. For the 64-bit ABI structs
7626 are always stored left shifted in their argument slot. */
7628 static pad_direction
7629 sparc_function_arg_padding (machine_mode mode
, const_tree type
)
7631 if (TARGET_ARCH64
&& type
&& AGGREGATE_TYPE_P (type
))
7634 /* Fall back to the default. */
7635 return default_function_arg_padding (mode
, type
);
7638 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
7639 Specify whether to return the return value in memory. */
7642 sparc_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
7645 /* Original SPARC 32-bit ABI says that structures and unions, and
7646 quad-precision floats are returned in memory. But note that the
7647 first part is implemented through -fpcc-struct-return being the
7648 default, so here we only implement -freg-struct-return instead.
7649 All other base types are returned in registers.
7651 Extended ABI (as implemented by the Sun compiler) says that
7652 all complex floats are returned in registers (8 FP registers
7653 at most for '_Complex long double'). Return all complex integers
7654 in registers (4 at most for '_Complex long long').
7656 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7657 integers are returned like floats of the same size, that is in
7658 registers up to 8 bytes and in memory otherwise. Return all
7659 vector floats in memory like structure and unions; note that
7660 they always have BLKmode like the latter. */
7661 return (TYPE_MODE (type
) == BLKmode
7662 || TYPE_MODE (type
) == TFmode
7663 || (TREE_CODE (type
) == VECTOR_TYPE
7664 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
7666 /* Original SPARC 64-bit ABI says that structures and unions
7667 smaller than 32 bytes are returned in registers, as well as
7668 all other base types.
7670 Extended ABI (as implemented by the Sun compiler) says that all
7671 complex floats are returned in registers (8 FP registers at most
7672 for '_Complex long double'). Return all complex integers in
7673 registers (4 at most for '_Complex TItype').
7675 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7676 integers are returned like floats of the same size, that is in
7677 registers. Return all vector floats like structure and unions;
7678 note that they always have BLKmode like the latter. */
7679 return (TYPE_MODE (type
) == BLKmode
7680 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 32);
7683 /* Handle the TARGET_STRUCT_VALUE target hook.
7684 Return where to find the structure return value address. */
7687 sparc_struct_value_rtx (tree fndecl
, int incoming
)
7696 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, frame_pointer_rtx
,
7697 STRUCT_VALUE_OFFSET
));
7699 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, stack_pointer_rtx
,
7700 STRUCT_VALUE_OFFSET
));
7702 /* Only follow the SPARC ABI for fixed-size structure returns.
7703 Variable size structure returns are handled per the normal
7704 procedures in GCC. This is enabled by -mstd-struct-return */
7706 && sparc_std_struct_return
7707 && TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))
7708 && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))) == INTEGER_CST
)
7710 /* We must check and adjust the return address, as it is optional
7711 as to whether the return object is really provided. */
7712 rtx ret_reg
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
7713 rtx scratch
= gen_reg_rtx (SImode
);
7714 rtx_code_label
*endlab
= gen_label_rtx ();
7716 /* Calculate the return object size. */
7717 tree size
= TYPE_SIZE_UNIT (TREE_TYPE (fndecl
));
7718 rtx size_rtx
= GEN_INT (TREE_INT_CST_LOW (size
) & 0xfff);
7719 /* Construct a temporary return value. */
7721 = assign_stack_local (Pmode
, TREE_INT_CST_LOW (size
), 0);
7723 /* Implement SPARC 32-bit psABI callee return struct checking:
7725 Fetch the instruction where we will return to and see if
7726 it's an unimp instruction (the most significant 10 bits
7728 emit_move_insn (scratch
, gen_rtx_MEM (SImode
,
7729 plus_constant (Pmode
,
7731 /* Assume the size is valid and pre-adjust. */
7732 emit_insn (gen_add3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
7733 emit_cmp_and_jump_insns (scratch
, size_rtx
, EQ
, const0_rtx
, SImode
,
7735 emit_insn (gen_sub3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
7736 /* Write the address of the memory pointed to by temp_val into
7737 the memory pointed to by mem. */
7738 emit_move_insn (mem
, XEXP (temp_val
, 0));
7739 emit_label (endlab
);
7746 /* Handle TARGET_FUNCTION_VALUE, and TARGET_LIBCALL_VALUE target hook.
7747 For v9, function return values are subject to the same rules as arguments,
7748 except that up to 32 bytes may be returned in registers. */
7751 sparc_function_value_1 (const_tree type
, machine_mode mode
, bool outgoing
)
7753 /* Beware that the two values are swapped here wrt function_arg. */
7755 = outgoing
? SPARC_INCOMING_INT_ARG_FIRST
: SPARC_OUTGOING_INT_ARG_FIRST
;
7756 enum mode_class mclass
= GET_MODE_CLASS (mode
);
7759 /* Integer vectors are handled like floats as per the Sun VIS SDK.
7760 Note that integer vectors larger than 16 bytes have BLKmode so
7761 they need to be handled like floating-point vectors below. */
7762 if (type
&& VECTOR_INTEGER_TYPE_P (type
) && mode
!= BLKmode
)
7763 mclass
= MODE_FLOAT
;
7765 if (TARGET_ARCH64
&& type
)
7767 /* Structures up to 32 bytes in size are returned in registers. */
7768 if (TREE_CODE (type
) == RECORD_TYPE
)
7770 const int size
= int_size_in_bytes (type
);
7771 gcc_assert (size
<= 32);
7773 return function_arg_record_value (type
, mode
, 0, true, regbase
);
7776 /* Unions up to 32 bytes in size are returned in integer registers. */
7777 else if (TREE_CODE (type
) == UNION_TYPE
)
7779 const int size
= int_size_in_bytes (type
);
7780 gcc_assert (size
<= 32);
7782 return function_arg_union_value (size
, mode
, 0, regbase
);
7785 /* Vectors up to 32 bytes are returned in FP registers. */
7786 else if (VECTOR_TYPE_P (type
) && mode
== BLKmode
)
7788 const int size
= int_size_in_bytes (type
);
7789 gcc_assert (size
<= 32);
7791 return function_arg_vector_value (size
, 0, true, SPARC_FP_ARG_FIRST
);
7794 /* Objects that require it are returned in FP registers. */
7795 else if (mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
7798 /* All other aggregate types are returned in an integer register in a
7799 mode corresponding to the size of the type. */
7800 else if (AGGREGATE_TYPE_P (type
))
7802 /* All other aggregate types are passed in an integer register
7803 in a mode corresponding to the size of the type. */
7804 const int size
= int_size_in_bytes (type
);
7805 gcc_assert (size
<= 32);
7807 mode
= int_mode_for_size (size
* BITS_PER_UNIT
, 0).else_blk ();
7809 /* ??? We probably should have made the same ABI change in
7810 3.4.0 as the one we made for unions. The latter was
7811 required by the SCD though, while the former is not
7812 specified, so we favored compatibility and efficiency.
7814 Now we're stuck for aggregates larger than 16 bytes,
7815 because OImode vanished in the meantime. Let's not
7816 try to be unduly clever, and simply follow the ABI
7817 for unions in that case. */
7818 if (mode
== BLKmode
)
7819 return function_arg_union_value (size
, mode
, 0, regbase
);
7824 /* We should only have pointer and integer types at this point. This
7825 must match sparc_promote_function_mode. */
7826 else if (mclass
== MODE_INT
&& GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
7830 /* We should only have pointer and integer types at this point, except with
7831 -freg-struct-return. This must match sparc_promote_function_mode. */
7832 else if (TARGET_ARCH32
7833 && !(type
&& AGGREGATE_TYPE_P (type
))
7834 && mclass
== MODE_INT
7835 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
7838 if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
) && TARGET_FPU
)
7839 regno
= SPARC_FP_ARG_FIRST
;
7843 return gen_rtx_REG (mode
, regno
);
7846 /* Handle TARGET_FUNCTION_VALUE.
7847 On the SPARC, the value is found in the first "output" register, but the
7848 called function leaves it in the first "input" register. */
7851 sparc_function_value (const_tree valtype
,
7852 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
7855 return sparc_function_value_1 (valtype
, TYPE_MODE (valtype
), outgoing
);
7858 /* Handle TARGET_LIBCALL_VALUE. */
7861 sparc_libcall_value (machine_mode mode
,
7862 const_rtx fun ATTRIBUTE_UNUSED
)
7864 return sparc_function_value_1 (NULL_TREE
, mode
, false);
7867 /* Handle FUNCTION_VALUE_REGNO_P.
7868 On the SPARC, the first "output" reg is used for integer values, and the
7869 first floating point register is used for floating point values. */
7872 sparc_function_value_regno_p (const unsigned int regno
)
7874 return (regno
== 8 || (TARGET_FPU
&& regno
== 32));
7877 /* Do what is necessary for `va_start'. We look at the current function
7878 to determine if stdarg or varargs is used and return the address of
7879 the first unnamed parameter. */
7882 sparc_builtin_saveregs (void)
7884 int first_reg
= crtl
->args
.info
.words
;
7888 for (regno
= first_reg
; regno
< SPARC_INT_ARG_MAX
; regno
++)
7889 emit_move_insn (gen_rtx_MEM (word_mode
,
7890 gen_rtx_PLUS (Pmode
,
7892 GEN_INT (FIRST_PARM_OFFSET (0)
7895 gen_rtx_REG (word_mode
,
7896 SPARC_INCOMING_INT_ARG_FIRST
+ regno
));
7898 address
= gen_rtx_PLUS (Pmode
,
7900 GEN_INT (FIRST_PARM_OFFSET (0)
7901 + UNITS_PER_WORD
* first_reg
));
7906 /* Implement `va_start' for stdarg. */
7909 sparc_va_start (tree valist
, rtx nextarg
)
7911 nextarg
= expand_builtin_saveregs ();
7912 std_expand_builtin_va_start (valist
, nextarg
);
7915 /* Implement `va_arg' for stdarg. */
7918 sparc_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
7921 HOST_WIDE_INT size
, rsize
, align
;
7924 tree ptrtype
= build_pointer_type (type
);
7926 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
7929 size
= rsize
= UNITS_PER_WORD
;
7935 size
= int_size_in_bytes (type
);
7936 rsize
= ROUND_UP (size
, UNITS_PER_WORD
);
7941 /* For SPARC64, objects requiring 16-byte alignment get it. */
7942 if (TYPE_ALIGN (type
) >= 2 * (unsigned) BITS_PER_WORD
)
7943 align
= 2 * UNITS_PER_WORD
;
7945 /* SPARC-V9 ABI states that structures up to 16 bytes in size
7946 are left-justified in their slots. */
7947 if (AGGREGATE_TYPE_P (type
))
7950 size
= rsize
= UNITS_PER_WORD
;
7960 incr
= fold_build_pointer_plus_hwi (incr
, align
- 1);
7961 incr
= fold_convert (sizetype
, incr
);
7962 incr
= fold_build2 (BIT_AND_EXPR
, sizetype
, incr
,
7964 incr
= fold_convert (ptr_type_node
, incr
);
7967 gimplify_expr (&incr
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
7970 if (BYTES_BIG_ENDIAN
&& size
< rsize
)
7971 addr
= fold_build_pointer_plus_hwi (incr
, rsize
- size
);
7975 addr
= fold_convert (build_pointer_type (ptrtype
), addr
);
7976 addr
= build_va_arg_indirect_ref (addr
);
7979 /* If the address isn't aligned properly for the type, we need a temporary.
7980 FIXME: This is inefficient, usually we can do this in registers. */
7981 else if (align
== 0 && TYPE_ALIGN (type
) > BITS_PER_WORD
)
7983 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
7984 tree dest_addr
= build_fold_addr_expr (tmp
);
7985 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
7986 3, dest_addr
, addr
, size_int (rsize
));
7987 TREE_ADDRESSABLE (tmp
) = 1;
7988 gimplify_and_add (copy
, pre_p
);
7993 addr
= fold_convert (ptrtype
, addr
);
7995 incr
= fold_build_pointer_plus_hwi (incr
, rsize
);
7996 gimplify_assign (valist
, incr
, post_p
);
7998 return build_va_arg_indirect_ref (addr
);
8001 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
8002 Specify whether the vector mode is supported by the hardware. */
8005 sparc_vector_mode_supported_p (machine_mode mode
)
8007 return TARGET_VIS
&& VECTOR_MODE_P (mode
) ? true : false;
8010 /* Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook. */
8013 sparc_preferred_simd_mode (scalar_mode mode
)
8031 \f/* Implement TARGET_CAN_FOLLOW_JUMP. */
8034 sparc_can_follow_jump (const rtx_insn
*follower
, const rtx_insn
*followee
)
8036 /* Do not fold unconditional jumps that have been created for crossing
8037 partition boundaries. */
8038 if (CROSSING_JUMP_P (followee
) && !CROSSING_JUMP_P (follower
))
8044 /* Return the string to output an unconditional branch to LABEL, which is
8045 the operand number of the label.
8047 DEST is the destination insn (i.e. the label), INSN is the source. */
8050 output_ubranch (rtx dest
, rtx_insn
*insn
)
8052 static char string
[64];
8053 bool v9_form
= false;
8057 /* Even if we are trying to use cbcond for this, evaluate
8058 whether we can use V9 branches as our backup plan. */
8060 if (!CROSSING_JUMP_P (insn
) && INSN_ADDRESSES_SET_P ())
8061 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
8062 - INSN_ADDRESSES (INSN_UID (insn
)));
8064 /* Leave some instructions for "slop". */
8065 if (TARGET_V9
&& delta
>= -260000 && delta
< 260000)
8070 bool emit_nop
= emit_cbcond_nop (insn
);
8074 if (delta
< -500 || delta
> 500)
8080 rval
= "ba,a,pt\t%%xcc, %l0";
8087 rval
= "cwbe\t%%g0, %%g0, %l0\n\tnop";
8089 rval
= "cwbe\t%%g0, %%g0, %l0";
8095 strcpy (string
, "ba%*,pt\t%%xcc, ");
8097 strcpy (string
, "b%*\t");
8099 p
= strchr (string
, '\0');
8110 /* Return the string to output a conditional branch to LABEL, which is
8111 the operand number of the label. OP is the conditional expression.
8112 XEXP (OP, 0) is assumed to be a condition code register (integer or
8113 floating point) and its mode specifies what kind of comparison we made.
8115 DEST is the destination insn (i.e. the label), INSN is the source.
8117 REVERSED is nonzero if we should reverse the sense of the comparison.
8119 ANNUL is nonzero if we should generate an annulling branch. */
8122 output_cbranch (rtx op
, rtx dest
, int label
, int reversed
, int annul
,
8125 static char string
[64];
8126 enum rtx_code code
= GET_CODE (op
);
8127 rtx cc_reg
= XEXP (op
, 0);
8128 machine_mode mode
= GET_MODE (cc_reg
);
8129 const char *labelno
, *branch
;
8130 int spaces
= 8, far
;
8133 /* v9 branches are limited to +-1MB. If it is too far away,
8146 fbne,a,pn %fcc2, .LC29
8154 far
= TARGET_V9
&& (get_attr_length (insn
) >= 3);
8157 /* Reversal of FP compares takes care -- an ordered compare
8158 becomes an unordered compare and vice versa. */
8159 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
8160 code
= reverse_condition_maybe_unordered (code
);
8162 code
= reverse_condition (code
);
8165 /* Start by writing the branch condition. */
8166 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
8216 /* ??? !v9: FP branches cannot be preceded by another floating point
8217 insn. Because there is currently no concept of pre-delay slots,
8218 we can fix this only by always emitting a nop before a floating
8223 strcpy (string
, "nop\n\t");
8224 strcat (string
, branch
);
8231 if (mode
== CCVmode
|| mode
== CCXVmode
)
8237 if (mode
== CCVmode
|| mode
== CCXVmode
)
8243 if (mode
== CCNZmode
|| mode
== CCXNZmode
)
8255 if (mode
== CCNZmode
|| mode
== CCXNZmode
)
8275 strcpy (string
, branch
);
8277 spaces
-= strlen (branch
);
8278 p
= strchr (string
, '\0');
8280 /* Now add the annulling, the label, and a possible noop. */
8293 if (! far
&& insn
&& INSN_ADDRESSES_SET_P ())
8295 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
8296 - INSN_ADDRESSES (INSN_UID (insn
)));
8297 /* Leave some instructions for "slop". */
8298 if (delta
< -260000 || delta
>= 260000)
8308 labelno
= "%%icc, ";
8316 labelno
= "%%xcc, ";
8322 static char v9_fcc_labelno
[] = "%%fccX, ";
8323 /* Set the char indicating the number of the fcc reg to use. */
8324 v9_fcc_labelno
[5] = REGNO (cc_reg
) - SPARC_FIRST_V9_FCC_REG
+ '0';
8325 labelno
= v9_fcc_labelno
;
8328 gcc_assert (REGNO (cc_reg
) == SPARC_FCC_REG
);
8337 if (*labelno
&& insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
8340 ((profile_probability::from_reg_br_prob_note (XINT (note
, 0))
8341 >= profile_probability::even ()) ^ far
)
8354 strcpy (p
, labelno
);
8355 p
= strchr (p
, '\0');
8358 strcpy (p
, ".+12\n\t nop\n\tb\t");
8359 /* Skip the next insn if requested or
8360 if we know that it will be a nop. */
8361 if (annul
|| ! final_sequence
)
8375 /* Emit a library call comparison between floating point X and Y.
8376 COMPARISON is the operator to compare with (EQ, NE, GT, etc).
8377 Return the new operator to be used in the comparison sequence.
8379 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
8380 values as arguments instead of the TFmode registers themselves,
8381 that's why we cannot call emit_float_lib_cmp. */
8384 sparc_emit_float_lib_cmp (rtx x
, rtx y
, enum rtx_code comparison
)
8387 rtx slot0
, slot1
, result
, tem
, tem2
, libfunc
;
8389 enum rtx_code new_comparison
;
8394 qpfunc
= (TARGET_ARCH64
? "_Qp_feq" : "_Q_feq");
8398 qpfunc
= (TARGET_ARCH64
? "_Qp_fne" : "_Q_fne");
8402 qpfunc
= (TARGET_ARCH64
? "_Qp_fgt" : "_Q_fgt");
8406 qpfunc
= (TARGET_ARCH64
? "_Qp_fge" : "_Q_fge");
8410 qpfunc
= (TARGET_ARCH64
? "_Qp_flt" : "_Q_flt");
8414 qpfunc
= (TARGET_ARCH64
? "_Qp_fle" : "_Q_fle");
8425 qpfunc
= (TARGET_ARCH64
? "_Qp_cmp" : "_Q_cmp");
8436 tree expr
= MEM_EXPR (x
);
8438 mark_addressable (expr
);
8443 slot0
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
));
8444 emit_move_insn (slot0
, x
);
8449 tree expr
= MEM_EXPR (y
);
8451 mark_addressable (expr
);
8456 slot1
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
));
8457 emit_move_insn (slot1
, y
);
8460 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
8461 emit_library_call (libfunc
, LCT_NORMAL
,
8463 XEXP (slot0
, 0), Pmode
,
8464 XEXP (slot1
, 0), Pmode
);
8469 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
8470 emit_library_call (libfunc
, LCT_NORMAL
,
8472 x
, TFmode
, y
, TFmode
);
8477 /* Immediately move the result of the libcall into a pseudo
8478 register so reload doesn't clobber the value if it needs
8479 the return register for a spill reg. */
8480 result
= gen_reg_rtx (mode
);
8481 emit_move_insn (result
, hard_libcall_value (mode
, libfunc
));
8486 return gen_rtx_NE (VOIDmode
, result
, const0_rtx
);
8489 new_comparison
= (comparison
== UNORDERED
? EQ
: NE
);
8490 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, GEN_INT(3));
8493 new_comparison
= (comparison
== UNGT
? GT
: NE
);
8494 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, const1_rtx
);
8496 return gen_rtx_NE (VOIDmode
, result
, const2_rtx
);
8498 tem
= gen_reg_rtx (mode
);
8500 emit_insn (gen_andsi3 (tem
, result
, const1_rtx
));
8502 emit_insn (gen_anddi3 (tem
, result
, const1_rtx
));
8503 return gen_rtx_NE (VOIDmode
, tem
, const0_rtx
);
8506 tem
= gen_reg_rtx (mode
);
8508 emit_insn (gen_addsi3 (tem
, result
, const1_rtx
));
8510 emit_insn (gen_adddi3 (tem
, result
, const1_rtx
));
8511 tem2
= gen_reg_rtx (mode
);
8513 emit_insn (gen_andsi3 (tem2
, tem
, const2_rtx
));
8515 emit_insn (gen_anddi3 (tem2
, tem
, const2_rtx
));
8516 new_comparison
= (comparison
== UNEQ
? EQ
: NE
);
8517 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, tem2
, const0_rtx
);
8523 /* Generate an unsigned DImode to FP conversion. This is the same code
8524 optabs would emit if we didn't have TFmode patterns. */
8527 sparc_emit_floatunsdi (rtx
*operands
, machine_mode mode
)
8529 rtx i0
, i1
, f0
, in
, out
;
8532 in
= force_reg (DImode
, operands
[1]);
8533 rtx_code_label
*neglab
= gen_label_rtx ();
8534 rtx_code_label
*donelab
= gen_label_rtx ();
8535 i0
= gen_reg_rtx (DImode
);
8536 i1
= gen_reg_rtx (DImode
);
8537 f0
= gen_reg_rtx (mode
);
8539 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
8541 emit_insn (gen_rtx_SET (out
, gen_rtx_FLOAT (mode
, in
)));
8542 emit_jump_insn (gen_jump (donelab
));
8545 emit_label (neglab
);
8547 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
8548 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
8549 emit_insn (gen_iordi3 (i0
, i0
, i1
));
8550 emit_insn (gen_rtx_SET (f0
, gen_rtx_FLOAT (mode
, i0
)));
8551 emit_insn (gen_rtx_SET (out
, gen_rtx_PLUS (mode
, f0
, f0
)));
8553 emit_label (donelab
);
8556 /* Generate an FP to unsigned DImode conversion. This is the same code
8557 optabs would emit if we didn't have TFmode patterns. */
8560 sparc_emit_fixunsdi (rtx
*operands
, machine_mode mode
)
8562 rtx i0
, i1
, f0
, in
, out
, limit
;
8565 in
= force_reg (mode
, operands
[1]);
8566 rtx_code_label
*neglab
= gen_label_rtx ();
8567 rtx_code_label
*donelab
= gen_label_rtx ();
8568 i0
= gen_reg_rtx (DImode
);
8569 i1
= gen_reg_rtx (DImode
);
8570 limit
= gen_reg_rtx (mode
);
8571 f0
= gen_reg_rtx (mode
);
8573 emit_move_insn (limit
,
8574 const_double_from_real_value (
8575 REAL_VALUE_ATOF ("9223372036854775808.0", mode
), mode
));
8576 emit_cmp_and_jump_insns (in
, limit
, GE
, NULL_RTX
, mode
, 0, neglab
);
8578 emit_insn (gen_rtx_SET (out
,
8579 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, in
))));
8580 emit_jump_insn (gen_jump (donelab
));
8583 emit_label (neglab
);
8585 emit_insn (gen_rtx_SET (f0
, gen_rtx_MINUS (mode
, in
, limit
)));
8586 emit_insn (gen_rtx_SET (i0
,
8587 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, f0
))));
8588 emit_insn (gen_movdi (i1
, const1_rtx
));
8589 emit_insn (gen_ashldi3 (i1
, i1
, GEN_INT (63)));
8590 emit_insn (gen_xordi3 (out
, i0
, i1
));
8592 emit_label (donelab
);
8595 /* Return the string to output a compare and branch instruction to DEST.
8596 DEST is the destination insn (i.e. the label), INSN is the source,
8597 and OP is the conditional expression. */
8600 output_cbcond (rtx op
, rtx dest
, rtx_insn
*insn
)
8602 machine_mode mode
= GET_MODE (XEXP (op
, 0));
8603 enum rtx_code code
= GET_CODE (op
);
8604 const char *cond_str
, *tmpl
;
8605 int far
, emit_nop
, len
;
8606 static char string
[64];
8609 /* Compare and Branch is limited to +-2KB. If it is too far away,
8621 len
= get_attr_length (insn
);
8624 emit_nop
= len
== 2;
8627 code
= reverse_condition (code
);
8629 size_char
= ((mode
== SImode
) ? 'w' : 'x');
8679 int veryfar
= 1, delta
;
8681 if (INSN_ADDRESSES_SET_P ())
8683 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
8684 - INSN_ADDRESSES (INSN_UID (insn
)));
8685 /* Leave some instructions for "slop". */
8686 if (delta
>= -260000 && delta
< 260000)
8691 tmpl
= "c%cb%s\t%%1, %%2, .+16\n\tnop\n\tb\t%%3\n\tnop";
8693 tmpl
= "c%cb%s\t%%1, %%2, .+16\n\tnop\n\tba,pt\t%%%%xcc, %%3\n\tnop";
8698 tmpl
= "c%cb%s\t%%1, %%2, %%3\n\tnop";
8700 tmpl
= "c%cb%s\t%%1, %%2, %%3";
8703 snprintf (string
, sizeof(string
), tmpl
, size_char
, cond_str
);
8708 /* Return the string to output a conditional branch to LABEL, testing
8709 register REG. LABEL is the operand number of the label; REG is the
8710 operand number of the reg. OP is the conditional expression. The mode
8711 of REG says what kind of comparison we made.
8713 DEST is the destination insn (i.e. the label), INSN is the source.
8715 REVERSED is nonzero if we should reverse the sense of the comparison.
8717 ANNUL is nonzero if we should generate an annulling branch. */
8720 output_v9branch (rtx op
, rtx dest
, int reg
, int label
, int reversed
,
8721 int annul
, rtx_insn
*insn
)
8723 static char string
[64];
8724 enum rtx_code code
= GET_CODE (op
);
8725 machine_mode mode
= GET_MODE (XEXP (op
, 0));
8730 /* branch on register are limited to +-128KB. If it is too far away,
8743 brgez,a,pn %o1, .LC29
8749 ba,pt %xcc, .LC29 */
8751 far
= get_attr_length (insn
) >= 3;
8753 /* If not floating-point or if EQ or NE, we can just reverse the code. */
8755 code
= reverse_condition (code
);
8757 /* Only 64-bit versions of these instructions exist. */
8758 gcc_assert (mode
== DImode
);
8760 /* Start by writing the branch condition. */
8765 strcpy (string
, "brnz");
8769 strcpy (string
, "brz");
8773 strcpy (string
, "brgez");
8777 strcpy (string
, "brlz");
8781 strcpy (string
, "brlez");
8785 strcpy (string
, "brgz");
8792 p
= strchr (string
, '\0');
8794 /* Now add the annulling, reg, label, and nop. */
8801 if (insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
8804 ((profile_probability::from_reg_br_prob_note (XINT (note
, 0))
8805 >= profile_probability::even ()) ^ far
)
8810 *p
= p
< string
+ 8 ? '\t' : ' ';
8818 int veryfar
= 1, delta
;
8820 if (INSN_ADDRESSES_SET_P ())
8822 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
8823 - INSN_ADDRESSES (INSN_UID (insn
)));
8824 /* Leave some instructions for "slop". */
8825 if (delta
>= -260000 && delta
< 260000)
8829 strcpy (p
, ".+12\n\t nop\n\t");
8830 /* Skip the next insn if requested or
8831 if we know that it will be a nop. */
8832 if (annul
|| ! final_sequence
)
8842 strcpy (p
, "ba,pt\t%%xcc, ");
8856 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
8857 Such instructions cannot be used in the delay slot of return insn on v9.
8858 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
8862 epilogue_renumber (register rtx
*where
, int test
)
8864 register const char *fmt
;
8866 register enum rtx_code code
;
8871 code
= GET_CODE (*where
);
8876 if (REGNO (*where
) >= 8 && REGNO (*where
) < 24) /* oX or lX */
8878 if (! test
&& REGNO (*where
) >= 24 && REGNO (*where
) < 32)
8879 *where
= gen_rtx_REG (GET_MODE (*where
), OUTGOING_REGNO (REGNO(*where
)));
8885 case CONST_WIDE_INT
:
8889 /* Do not replace the frame pointer with the stack pointer because
8890 it can cause the delayed instruction to load below the stack.
8891 This occurs when instructions like:
8893 (set (reg/i:SI 24 %i0)
8894 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
8895 (const_int -20 [0xffffffec])) 0))
8897 are in the return delayed slot. */
8899 if (GET_CODE (XEXP (*where
, 0)) == REG
8900 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
8901 && (GET_CODE (XEXP (*where
, 1)) != CONST_INT
8902 || INTVAL (XEXP (*where
, 1)) < SPARC_STACK_BIAS
))
8907 if (SPARC_STACK_BIAS
8908 && GET_CODE (XEXP (*where
, 0)) == REG
8909 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
)
8917 fmt
= GET_RTX_FORMAT (code
);
8919 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8924 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
8925 if (epilogue_renumber (&(XVECEXP (*where
, i
, j
)), test
))
8928 else if (fmt
[i
] == 'e'
8929 && epilogue_renumber (&(XEXP (*where
, i
)), test
))
8935 /* Leaf functions and non-leaf functions have different needs. */
8938 reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
8941 reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
8943 static const int *const reg_alloc_orders
[] = {
8944 reg_leaf_alloc_order
,
8945 reg_nonleaf_alloc_order
};
8948 order_regs_for_local_alloc (void)
8950 static int last_order_nonleaf
= 1;
8952 if (df_regs_ever_live_p (15) != last_order_nonleaf
)
8954 last_order_nonleaf
= !last_order_nonleaf
;
8955 memcpy ((char *) reg_alloc_order
,
8956 (const char *) reg_alloc_orders
[last_order_nonleaf
],
8957 FIRST_PSEUDO_REGISTER
* sizeof (int));
8961 /* Return 1 if REG and MEM are legitimate enough to allow the various
8962 MEM<-->REG splits to be run. */
8965 sparc_split_reg_mem_legitimate (rtx reg
, rtx mem
)
8967 /* Punt if we are here by mistake. */
8968 gcc_assert (reload_completed
);
8970 /* We must have an offsettable memory reference. */
8971 if (!offsettable_memref_p (mem
))
8974 /* If we have legitimate args for ldd/std, we do not want
8975 the split to happen. */
8976 if ((REGNO (reg
) % 2) == 0 && mem_min_alignment (mem
, 8))
8983 /* Split a REG <-- MEM move into a pair of moves in MODE. */
8986 sparc_split_reg_mem (rtx dest
, rtx src
, machine_mode mode
)
8988 rtx high_part
= gen_highpart (mode
, dest
);
8989 rtx low_part
= gen_lowpart (mode
, dest
);
8990 rtx word0
= adjust_address (src
, mode
, 0);
8991 rtx word1
= adjust_address (src
, mode
, 4);
8993 if (reg_overlap_mentioned_p (high_part
, word1
))
8995 emit_move_insn_1 (low_part
, word1
);
8996 emit_move_insn_1 (high_part
, word0
);
9000 emit_move_insn_1 (high_part
, word0
);
9001 emit_move_insn_1 (low_part
, word1
);
9005 /* Split a MEM <-- REG move into a pair of moves in MODE. */
9008 sparc_split_mem_reg (rtx dest
, rtx src
, machine_mode mode
)
9010 rtx word0
= adjust_address (dest
, mode
, 0);
9011 rtx word1
= adjust_address (dest
, mode
, 4);
9012 rtx high_part
= gen_highpart (mode
, src
);
9013 rtx low_part
= gen_lowpart (mode
, src
);
9015 emit_move_insn_1 (word0
, high_part
);
9016 emit_move_insn_1 (word1
, low_part
);
9019 /* Like sparc_split_reg_mem_legitimate but for REG <--> REG moves. */
9022 sparc_split_reg_reg_legitimate (rtx reg1
, rtx reg2
)
9024 /* Punt if we are here by mistake. */
9025 gcc_assert (reload_completed
);
9027 if (GET_CODE (reg1
) == SUBREG
)
9028 reg1
= SUBREG_REG (reg1
);
9029 if (GET_CODE (reg1
) != REG
)
9031 const int regno1
= REGNO (reg1
);
9033 if (GET_CODE (reg2
) == SUBREG
)
9034 reg2
= SUBREG_REG (reg2
);
9035 if (GET_CODE (reg2
) != REG
)
9037 const int regno2
= REGNO (reg2
);
9039 if (SPARC_INT_REG_P (regno1
) && SPARC_INT_REG_P (regno2
))
9044 if ((SPARC_INT_REG_P (regno1
) && SPARC_FP_REG_P (regno2
))
9045 || (SPARC_FP_REG_P (regno1
) && SPARC_INT_REG_P (regno2
)))
9052 /* Split a REG <--> REG move into a pair of moves in MODE. */
9055 sparc_split_reg_reg (rtx dest
, rtx src
, machine_mode mode
)
9057 rtx dest1
= gen_highpart (mode
, dest
);
9058 rtx dest2
= gen_lowpart (mode
, dest
);
9059 rtx src1
= gen_highpart (mode
, src
);
9060 rtx src2
= gen_lowpart (mode
, src
);
9062 /* Now emit using the real source and destination we found, swapping
9063 the order if we detect overlap. */
9064 if (reg_overlap_mentioned_p (dest1
, src2
))
9066 emit_move_insn_1 (dest2
, src2
);
9067 emit_move_insn_1 (dest1
, src1
);
9071 emit_move_insn_1 (dest1
, src1
);
9072 emit_move_insn_1 (dest2
, src2
);
9076 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
9077 This makes them candidates for using ldd and std insns.
9079 Note reg1 and reg2 *must* be hard registers. */
9082 registers_ok_for_ldd_peep (rtx reg1
, rtx reg2
)
9084 /* We might have been passed a SUBREG. */
9085 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
9088 if (REGNO (reg1
) % 2 != 0)
9091 /* Integer ldd is deprecated in SPARC V9 */
9092 if (TARGET_V9
&& SPARC_INT_REG_P (REGNO (reg1
)))
9095 return (REGNO (reg1
) == REGNO (reg2
) - 1);
9098 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
9101 This can only happen when addr1 and addr2, the addresses in mem1
9102 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
9103 addr1 must also be aligned on a 64-bit boundary.
9105 Also iff dependent_reg_rtx is not null it should not be used to
9106 compute the address for mem1, i.e. we cannot optimize a sequence
9118 But, note that the transformation from:
9123 is perfectly fine. Thus, the peephole2 patterns always pass us
9124 the destination register of the first load, never the second one.
9126 For stores we don't have a similar problem, so dependent_reg_rtx is
9130 mems_ok_for_ldd_peep (rtx mem1
, rtx mem2
, rtx dependent_reg_rtx
)
9134 HOST_WIDE_INT offset1
;
9136 /* The mems cannot be volatile. */
9137 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
9140 /* MEM1 should be aligned on a 64-bit boundary. */
9141 if (MEM_ALIGN (mem1
) < 64)
9144 addr1
= XEXP (mem1
, 0);
9145 addr2
= XEXP (mem2
, 0);
9147 /* Extract a register number and offset (if used) from the first addr. */
9148 if (GET_CODE (addr1
) == PLUS
)
9150 /* If not a REG, return zero. */
9151 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
9155 reg1
= REGNO (XEXP (addr1
, 0));
9156 /* The offset must be constant! */
9157 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
9159 offset1
= INTVAL (XEXP (addr1
, 1));
9162 else if (GET_CODE (addr1
) != REG
)
9166 reg1
= REGNO (addr1
);
9167 /* This was a simple (mem (reg)) expression. Offset is 0. */
9171 /* Make sure the second address is a (mem (plus (reg) (const_int). */
9172 if (GET_CODE (addr2
) != PLUS
)
9175 if (GET_CODE (XEXP (addr2
, 0)) != REG
9176 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
9179 if (reg1
!= REGNO (XEXP (addr2
, 0)))
9182 if (dependent_reg_rtx
!= NULL_RTX
&& reg1
== REGNO (dependent_reg_rtx
))
9185 /* The first offset must be evenly divisible by 8 to ensure the
9186 address is 64-bit aligned. */
9187 if (offset1
% 8 != 0)
9190 /* The offset for the second addr must be 4 more than the first addr. */
9191 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
9194 /* All the tests passed. addr1 and addr2 are valid for ldd and std
9199 /* Return the widened memory access made of MEM1 and MEM2 in MODE. */
9202 widen_mem_for_ldd_peep (rtx mem1
, rtx mem2
, machine_mode mode
)
9204 rtx x
= widen_memory_access (mem1
, mode
, 0);
9205 MEM_NOTRAP_P (x
) = MEM_NOTRAP_P (mem1
) && MEM_NOTRAP_P (mem2
);
9209 /* Return 1 if reg is a pseudo, or is the first register in
9210 a hard register pair. This makes it suitable for use in
9211 ldd and std insns. */
9214 register_ok_for_ldd (rtx reg
)
9216 /* We might have been passed a SUBREG. */
9220 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
9221 return (REGNO (reg
) % 2 == 0);
9226 /* Return 1 if OP, a MEM, has an address which is known to be
9227 aligned to an 8-byte boundary. */
9230 memory_ok_for_ldd (rtx op
)
9232 /* In 64-bit mode, we assume that the address is word-aligned. */
9233 if (TARGET_ARCH32
&& !mem_min_alignment (op
, 8))
9236 if (! can_create_pseudo_p ()
9237 && !strict_memory_address_p (Pmode
, XEXP (op
, 0)))
9243 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
9246 sparc_print_operand_punct_valid_p (unsigned char code
)
9259 /* Implement TARGET_PRINT_OPERAND.
9260 Print operand X (an rtx) in assembler syntax to file FILE.
9261 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
9262 For `%' followed by punctuation, CODE is the punctuation and X is null. */
9265 sparc_print_operand (FILE *file
, rtx x
, int code
)
9272 /* Output an insn in a delay slot. */
9274 sparc_indent_opcode
= 1;
9276 fputs ("\n\t nop", file
);
9279 /* Output an annul flag if there's nothing for the delay slot and we
9280 are optimizing. This is always used with '(' below.
9281 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
9282 this is a dbx bug. So, we only do this when optimizing.
9283 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
9284 Always emit a nop in case the next instruction is a branch. */
9285 if (! final_sequence
&& (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
9289 /* Output a 'nop' if there's nothing for the delay slot and we are
9290 not optimizing. This is always used with '*' above. */
9291 if (! final_sequence
&& ! (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
9292 fputs ("\n\t nop", file
);
9293 else if (final_sequence
)
9294 sparc_indent_opcode
= 1;
9297 /* Output the right displacement from the saved PC on function return.
9298 The caller may have placed an "unimp" insn immediately after the call
9299 so we have to account for it. This insn is used in the 32-bit ABI
9300 when calling a function that returns a non zero-sized structure. The
9301 64-bit ABI doesn't have it. Be careful to have this test be the same
9302 as that for the call. The exception is when sparc_std_struct_return
9303 is enabled, the psABI is followed exactly and the adjustment is made
9304 by the code in sparc_struct_value_rtx. The call emitted is the same
9305 when sparc_std_struct_return is enabled. */
9307 && cfun
->returns_struct
9308 && !sparc_std_struct_return
9309 && DECL_SIZE (DECL_RESULT (current_function_decl
))
9310 && TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl
)))
9312 && !integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl
))))
9318 /* Output the Embedded Medium/Anywhere code model base register. */
9319 fputs (EMBMEDANY_BASE_REG
, file
);
9322 /* Print some local dynamic TLS name. */
9323 if (const char *name
= get_some_local_dynamic_name ())
9324 assemble_name (file
, name
);
9326 output_operand_lossage ("'%%&' used without any "
9327 "local dynamic TLS references");
9331 /* Adjust the operand to take into account a RESTORE operation. */
9332 if (GET_CODE (x
) == CONST_INT
)
9334 else if (GET_CODE (x
) != REG
)
9335 output_operand_lossage ("invalid %%Y operand");
9336 else if (REGNO (x
) < 8)
9337 fputs (reg_names
[REGNO (x
)], file
);
9338 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
9339 fputs (reg_names
[REGNO (x
)-16], file
);
9341 output_operand_lossage ("invalid %%Y operand");
9344 /* Print out the low order register name of a register pair. */
9345 if (WORDS_BIG_ENDIAN
)
9346 fputs (reg_names
[REGNO (x
)+1], file
);
9348 fputs (reg_names
[REGNO (x
)], file
);
9351 /* Print out the high order register name of a register pair. */
9352 if (WORDS_BIG_ENDIAN
)
9353 fputs (reg_names
[REGNO (x
)], file
);
9355 fputs (reg_names
[REGNO (x
)+1], file
);
9358 /* Print out the second register name of a register pair or quad.
9359 I.e., R (%o0) => %o1. */
9360 fputs (reg_names
[REGNO (x
)+1], file
);
9363 /* Print out the third register name of a register quad.
9364 I.e., S (%o0) => %o2. */
9365 fputs (reg_names
[REGNO (x
)+2], file
);
9368 /* Print out the fourth register name of a register quad.
9369 I.e., T (%o0) => %o3. */
9370 fputs (reg_names
[REGNO (x
)+3], file
);
9373 /* Print a condition code register. */
9374 if (REGNO (x
) == SPARC_ICC_REG
)
9376 switch (GET_MODE (x
))
9396 /* %fccN register */
9397 fputs (reg_names
[REGNO (x
)], file
);
9400 /* Print the operand's address only. */
9401 output_address (GET_MODE (x
), XEXP (x
, 0));
9404 /* In this case we need a register. Use %g0 if the
9405 operand is const0_rtx. */
9407 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
9409 fputs ("%g0", file
);
9416 switch (GET_CODE (x
))
9428 output_operand_lossage ("invalid %%A operand");
9436 switch (GET_CODE (x
))
9448 output_operand_lossage ("invalid %%B operand");
9455 /* This is used by the conditional move instructions. */
9458 machine_mode mode
= GET_MODE (XEXP (x
, 0));
9459 switch (GET_CODE (x
))
9462 if (mode
== CCVmode
|| mode
== CCXVmode
)
9468 if (mode
== CCVmode
|| mode
== CCXVmode
)
9474 if (mode
== CCNZmode
|| mode
== CCXNZmode
)
9486 if (mode
== CCNZmode
|| mode
== CCXNZmode
)
9528 output_operand_lossage ("invalid %%C operand");
9536 /* This are used by the movr instruction pattern. */
9539 switch (GET_CODE (x
))
9560 output_operand_lossage ("invalid %%D operand");
9570 /* Print a sign-extended character. */
9571 int i
= trunc_int_for_mode (INTVAL (x
), QImode
);
9572 fprintf (file
, "%d", i
);
9577 /* Operand must be a MEM; write its address. */
9578 if (GET_CODE (x
) != MEM
)
9579 output_operand_lossage ("invalid %%f operand");
9580 output_address (GET_MODE (x
), XEXP (x
, 0));
9585 /* Print a sign-extended 32-bit value. */
9587 if (GET_CODE(x
) == CONST_INT
)
9591 output_operand_lossage ("invalid %%s operand");
9594 i
= trunc_int_for_mode (i
, SImode
);
9595 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, i
);
9600 /* Do nothing special. */
9604 /* Undocumented flag. */
9605 output_operand_lossage ("invalid operand output code");
9608 if (GET_CODE (x
) == REG
)
9609 fputs (reg_names
[REGNO (x
)], file
);
9610 else if (GET_CODE (x
) == MEM
)
9613 /* Poor Sun assembler doesn't understand absolute addressing. */
9614 if (CONSTANT_P (XEXP (x
, 0)))
9615 fputs ("%g0+", file
);
9616 output_address (GET_MODE (x
), XEXP (x
, 0));
9619 else if (GET_CODE (x
) == HIGH
)
9621 fputs ("%hi(", file
);
9622 output_addr_const (file
, XEXP (x
, 0));
9625 else if (GET_CODE (x
) == LO_SUM
)
9627 sparc_print_operand (file
, XEXP (x
, 0), 0);
9628 if (TARGET_CM_MEDMID
)
9629 fputs ("+%l44(", file
);
9631 fputs ("+%lo(", file
);
9632 output_addr_const (file
, XEXP (x
, 1));
9635 else if (GET_CODE (x
) == CONST_DOUBLE
)
9636 output_operand_lossage ("floating-point constant not a valid immediate operand");
9638 output_addr_const (file
, x
);
9641 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
9644 sparc_print_operand_address (FILE *file
, machine_mode
/*mode*/, rtx x
)
9646 register rtx base
, index
= 0;
9648 register rtx addr
= x
;
9651 fputs (reg_names
[REGNO (addr
)], file
);
9652 else if (GET_CODE (addr
) == PLUS
)
9654 if (CONST_INT_P (XEXP (addr
, 0)))
9655 offset
= INTVAL (XEXP (addr
, 0)), base
= XEXP (addr
, 1);
9656 else if (CONST_INT_P (XEXP (addr
, 1)))
9657 offset
= INTVAL (XEXP (addr
, 1)), base
= XEXP (addr
, 0);
9659 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
9660 if (GET_CODE (base
) == LO_SUM
)
9662 gcc_assert (USE_AS_OFFSETABLE_LO10
9664 && ! TARGET_CM_MEDMID
);
9665 output_operand (XEXP (base
, 0), 0);
9666 fputs ("+%lo(", file
);
9667 output_address (VOIDmode
, XEXP (base
, 1));
9668 fprintf (file
, ")+%d", offset
);
9672 fputs (reg_names
[REGNO (base
)], file
);
9674 fprintf (file
, "%+d", offset
);
9675 else if (REG_P (index
))
9676 fprintf (file
, "+%s", reg_names
[REGNO (index
)]);
9677 else if (GET_CODE (index
) == SYMBOL_REF
9678 || GET_CODE (index
) == LABEL_REF
9679 || GET_CODE (index
) == CONST
)
9680 fputc ('+', file
), output_addr_const (file
, index
);
9681 else gcc_unreachable ();
9684 else if (GET_CODE (addr
) == MINUS
9685 && GET_CODE (XEXP (addr
, 1)) == LABEL_REF
)
9687 output_addr_const (file
, XEXP (addr
, 0));
9689 output_addr_const (file
, XEXP (addr
, 1));
9690 fputs ("-.)", file
);
9692 else if (GET_CODE (addr
) == LO_SUM
)
9694 output_operand (XEXP (addr
, 0), 0);
9695 if (TARGET_CM_MEDMID
)
9696 fputs ("+%l44(", file
);
9698 fputs ("+%lo(", file
);
9699 output_address (VOIDmode
, XEXP (addr
, 1));
9703 && GET_CODE (addr
) == CONST
9704 && GET_CODE (XEXP (addr
, 0)) == MINUS
9705 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST
9706 && GET_CODE (XEXP (XEXP (XEXP (addr
, 0), 1), 0)) == MINUS
9707 && XEXP (XEXP (XEXP (XEXP (addr
, 0), 1), 0), 1) == pc_rtx
)
9709 addr
= XEXP (addr
, 0);
9710 output_addr_const (file
, XEXP (addr
, 0));
9711 /* Group the args of the second CONST in parenthesis. */
9713 /* Skip past the second CONST--it does nothing for us. */
9714 output_addr_const (file
, XEXP (XEXP (addr
, 1), 0));
9715 /* Close the parenthesis. */
9720 output_addr_const (file
, addr
);
9724 /* Target hook for assembling integer objects. The sparc version has
9725 special handling for aligned DI-mode objects. */
9728 sparc_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
9730 /* ??? We only output .xword's for symbols and only then in environments
9731 where the assembler can handle them. */
9732 if (aligned_p
&& size
== 8 && GET_CODE (x
) != CONST_INT
)
9736 assemble_integer_with_op ("\t.xword\t", x
);
9741 assemble_aligned_integer (4, const0_rtx
);
9742 assemble_aligned_integer (4, x
);
9746 return default_assemble_integer (x
, size
, aligned_p
);
9749 /* Return the value of a code used in the .proc pseudo-op that says
9750 what kind of result this function returns. For non-C types, we pick
9751 the closest C type. */
9753 #ifndef SHORT_TYPE_SIZE
9754 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
9757 #ifndef INT_TYPE_SIZE
9758 #define INT_TYPE_SIZE BITS_PER_WORD
9761 #ifndef LONG_TYPE_SIZE
9762 #define LONG_TYPE_SIZE BITS_PER_WORD
9765 #ifndef LONG_LONG_TYPE_SIZE
9766 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
9769 #ifndef FLOAT_TYPE_SIZE
9770 #define FLOAT_TYPE_SIZE BITS_PER_WORD
9773 #ifndef DOUBLE_TYPE_SIZE
9774 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
9777 #ifndef LONG_DOUBLE_TYPE_SIZE
9778 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
9782 sparc_type_code (register tree type
)
9784 register unsigned long qualifiers
= 0;
9785 register unsigned shift
;
9787 /* Only the first 30 bits of the qualifier are valid. We must refrain from
9788 setting more, since some assemblers will give an error for this. Also,
9789 we must be careful to avoid shifts of 32 bits or more to avoid getting
9790 unpredictable results. */
9792 for (shift
= 6; shift
< 30; shift
+= 2, type
= TREE_TYPE (type
))
9794 switch (TREE_CODE (type
))
9800 qualifiers
|= (3 << shift
);
9805 qualifiers
|= (2 << shift
);
9809 case REFERENCE_TYPE
:
9811 qualifiers
|= (1 << shift
);
9815 return (qualifiers
| 8);
9818 case QUAL_UNION_TYPE
:
9819 return (qualifiers
| 9);
9822 return (qualifiers
| 10);
9825 return (qualifiers
| 16);
9828 /* If this is a range type, consider it to be the underlying
9830 if (TREE_TYPE (type
) != 0)
9833 /* Carefully distinguish all the standard types of C,
9834 without messing up if the language is not C. We do this by
9835 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
9836 look at both the names and the above fields, but that's redundant.
9837 Any type whose size is between two C types will be considered
9838 to be the wider of the two types. Also, we do not have a
9839 special code to use for "long long", so anything wider than
9840 long is treated the same. Note that we can't distinguish
9841 between "int" and "long" in this code if they are the same
9842 size, but that's fine, since neither can the assembler. */
9844 if (TYPE_PRECISION (type
) <= CHAR_TYPE_SIZE
)
9845 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 12 : 2));
9847 else if (TYPE_PRECISION (type
) <= SHORT_TYPE_SIZE
)
9848 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 13 : 3));
9850 else if (TYPE_PRECISION (type
) <= INT_TYPE_SIZE
)
9851 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 14 : 4));
9854 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 15 : 5));
9857 /* If this is a range type, consider it to be the underlying
9859 if (TREE_TYPE (type
) != 0)
9862 /* Carefully distinguish all the standard types of C,
9863 without messing up if the language is not C. */
9865 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
9866 return (qualifiers
| 6);
9869 return (qualifiers
| 7);
9871 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
9872 /* ??? We need to distinguish between double and float complex types,
9873 but I don't know how yet because I can't reach this code from
9874 existing front-ends. */
9875 return (qualifiers
| 7); /* Who knows? */
9878 case BOOLEAN_TYPE
: /* Boolean truth value type. */
9884 gcc_unreachable (); /* Not a type! */
9891 /* Nested function support. */
9893 /* Emit RTL insns to initialize the variable parts of a trampoline.
9894 FNADDR is an RTX for the address of the function's pure code.
9895 CXT is an RTX for the static chain value for the function.
9897 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
9898 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
9899 (to store insns). This is a bit excessive. Perhaps a different
9900 mechanism would be better here.
9902 Emit enough FLUSH insns to synchronize the data and instruction caches. */
9905 sparc32_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
9907 /* SPARC 32-bit trampoline:
9910 sethi %hi(static), %g2
9912 or %g2, %lo(static), %g2
9914 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
9915 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
9919 (adjust_address (m_tramp
, SImode
, 0),
9920 expand_binop (SImode
, ior_optab
,
9921 expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
, 10, 0, 1),
9922 GEN_INT (trunc_int_for_mode (0x03000000, SImode
)),
9923 NULL_RTX
, 1, OPTAB_DIRECT
));
9926 (adjust_address (m_tramp
, SImode
, 4),
9927 expand_binop (SImode
, ior_optab
,
9928 expand_shift (RSHIFT_EXPR
, SImode
, cxt
, 10, 0, 1),
9929 GEN_INT (trunc_int_for_mode (0x05000000, SImode
)),
9930 NULL_RTX
, 1, OPTAB_DIRECT
));
9933 (adjust_address (m_tramp
, SImode
, 8),
9934 expand_binop (SImode
, ior_optab
,
9935 expand_and (SImode
, fnaddr
, GEN_INT (0x3ff), NULL_RTX
),
9936 GEN_INT (trunc_int_for_mode (0x81c06000, SImode
)),
9937 NULL_RTX
, 1, OPTAB_DIRECT
));
9940 (adjust_address (m_tramp
, SImode
, 12),
9941 expand_binop (SImode
, ior_optab
,
9942 expand_and (SImode
, cxt
, GEN_INT (0x3ff), NULL_RTX
),
9943 GEN_INT (trunc_int_for_mode (0x8410a000, SImode
)),
9944 NULL_RTX
, 1, OPTAB_DIRECT
));
9946 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
9947 aligned on a 16 byte boundary so one flush clears it all. */
9948 emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp
, SImode
, 0))));
9949 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
9950 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
9951 && sparc_cpu
!= PROCESSOR_NIAGARA
9952 && sparc_cpu
!= PROCESSOR_NIAGARA2
9953 && sparc_cpu
!= PROCESSOR_NIAGARA3
9954 && sparc_cpu
!= PROCESSOR_NIAGARA4
9955 && sparc_cpu
!= PROCESSOR_NIAGARA7
9956 && sparc_cpu
!= PROCESSOR_M8
)
9957 emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp
, SImode
, 8))));
9959 /* Call __enable_execute_stack after writing onto the stack to make sure
9960 the stack address is accessible. */
9961 #ifdef HAVE_ENABLE_EXECUTE_STACK
9962 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
9963 LCT_NORMAL
, VOIDmode
, XEXP (m_tramp
, 0), Pmode
);
9968 /* The 64-bit version is simpler because it makes more sense to load the
9969 values as "immediate" data out of the trampoline. It's also easier since
9970 we can read the PC without clobbering a register. */
9973 sparc64_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
9975 /* SPARC 64-bit trampoline:
9984 emit_move_insn (adjust_address (m_tramp
, SImode
, 0),
9985 GEN_INT (trunc_int_for_mode (0x83414000, SImode
)));
9986 emit_move_insn (adjust_address (m_tramp
, SImode
, 4),
9987 GEN_INT (trunc_int_for_mode (0xca586018, SImode
)));
9988 emit_move_insn (adjust_address (m_tramp
, SImode
, 8),
9989 GEN_INT (trunc_int_for_mode (0x81c14000, SImode
)));
9990 emit_move_insn (adjust_address (m_tramp
, SImode
, 12),
9991 GEN_INT (trunc_int_for_mode (0xca586010, SImode
)));
9992 emit_move_insn (adjust_address (m_tramp
, DImode
, 16), cxt
);
9993 emit_move_insn (adjust_address (m_tramp
, DImode
, 24), fnaddr
);
9994 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 0))));
9996 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
9997 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
9998 && sparc_cpu
!= PROCESSOR_NIAGARA
9999 && sparc_cpu
!= PROCESSOR_NIAGARA2
10000 && sparc_cpu
!= PROCESSOR_NIAGARA3
10001 && sparc_cpu
!= PROCESSOR_NIAGARA4
10002 && sparc_cpu
!= PROCESSOR_NIAGARA7
10003 && sparc_cpu
!= PROCESSOR_M8
)
10004 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 8))));
10006 /* Call __enable_execute_stack after writing onto the stack to make sure
10007 the stack address is accessible. */
10008 #ifdef HAVE_ENABLE_EXECUTE_STACK
10009 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
10010 LCT_NORMAL
, VOIDmode
, XEXP (m_tramp
, 0), Pmode
);
10014 /* Worker for TARGET_TRAMPOLINE_INIT. */
10017 sparc_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
10019 rtx fnaddr
= force_reg (Pmode
, XEXP (DECL_RTL (fndecl
), 0));
10020 cxt
= force_reg (Pmode
, cxt
);
10022 sparc64_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
10024 sparc32_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
10027 /* Adjust the cost of a scheduling dependency. Return the new cost of
10028 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
10031 supersparc_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep_insn
,
10034 enum attr_type insn_type
;
10036 if (recog_memoized (insn
) < 0)
10039 insn_type
= get_attr_type (insn
);
10043 /* Data dependency; DEP_INSN writes a register that INSN reads some
10046 /* if a load, then the dependence must be on the memory address;
10047 add an extra "cycle". Note that the cost could be two cycles
10048 if the reg was written late in an instruction group; we ca not tell
10050 if (insn_type
== TYPE_LOAD
|| insn_type
== TYPE_FPLOAD
)
10053 /* Get the delay only if the address of the store is the dependence. */
10054 if (insn_type
== TYPE_STORE
|| insn_type
== TYPE_FPSTORE
)
10056 rtx pat
= PATTERN(insn
);
10057 rtx dep_pat
= PATTERN (dep_insn
);
10059 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
10060 return cost
; /* This should not happen! */
10062 /* The dependency between the two instructions was on the data that
10063 is being stored. Assume that this implies that the address of the
10064 store is not dependent. */
10065 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
10068 return cost
+ 3; /* An approximation. */
10071 /* A shift instruction cannot receive its data from an instruction
10072 in the same cycle; add a one cycle penalty. */
10073 if (insn_type
== TYPE_SHIFT
)
10074 return cost
+ 3; /* Split before cascade into shift. */
10078 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
10079 INSN writes some cycles later. */
10081 /* These are only significant for the fpu unit; writing a fp reg before
10082 the fpu has finished with it stalls the processor. */
10084 /* Reusing an integer register causes no problems. */
10085 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
10093 hypersparc_adjust_cost (rtx_insn
*insn
, int dtype
, rtx_insn
*dep_insn
,
10096 enum attr_type insn_type
, dep_type
;
10097 rtx pat
= PATTERN(insn
);
10098 rtx dep_pat
= PATTERN (dep_insn
);
10100 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
10103 insn_type
= get_attr_type (insn
);
10104 dep_type
= get_attr_type (dep_insn
);
10109 /* Data dependency; DEP_INSN writes a register that INSN reads some
10116 /* Get the delay iff the address of the store is the dependence. */
10117 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
10120 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
10127 /* If a load, then the dependence must be on the memory address. If
10128 the addresses aren't equal, then it might be a false dependency */
10129 if (dep_type
== TYPE_STORE
|| dep_type
== TYPE_FPSTORE
)
10131 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
10132 || GET_CODE (SET_DEST (dep_pat
)) != MEM
10133 || GET_CODE (SET_SRC (pat
)) != MEM
10134 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat
), 0),
10135 XEXP (SET_SRC (pat
), 0)))
10143 /* Compare to branch latency is 0. There is no benefit from
10144 separating compare and branch. */
10145 if (dep_type
== TYPE_COMPARE
)
10147 /* Floating point compare to branch latency is less than
10148 compare to conditional move. */
10149 if (dep_type
== TYPE_FPCMP
)
10158 /* Anti-dependencies only penalize the fpu unit. */
10159 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
10171 sparc_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep
, int cost
,
10176 case PROCESSOR_SUPERSPARC
:
10177 cost
= supersparc_adjust_cost (insn
, dep_type
, dep
, cost
);
10179 case PROCESSOR_HYPERSPARC
:
10180 case PROCESSOR_SPARCLITE86X
:
10181 cost
= hypersparc_adjust_cost (insn
, dep_type
, dep
, cost
);
10190 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
10191 int sched_verbose ATTRIBUTE_UNUSED
,
10192 int max_ready ATTRIBUTE_UNUSED
)
10196 sparc_use_sched_lookahead (void)
10200 case PROCESSOR_ULTRASPARC
:
10201 case PROCESSOR_ULTRASPARC3
:
10203 case PROCESSOR_SUPERSPARC
:
10204 case PROCESSOR_HYPERSPARC
:
10205 case PROCESSOR_SPARCLITE86X
:
10207 case PROCESSOR_NIAGARA4
:
10208 case PROCESSOR_NIAGARA7
:
10211 case PROCESSOR_NIAGARA
:
10212 case PROCESSOR_NIAGARA2
:
10213 case PROCESSOR_NIAGARA3
:
10220 sparc_issue_rate (void)
10224 case PROCESSOR_ULTRASPARC
:
10225 case PROCESSOR_ULTRASPARC3
:
10228 case PROCESSOR_SUPERSPARC
:
10230 case PROCESSOR_HYPERSPARC
:
10231 case PROCESSOR_SPARCLITE86X
:
10233 /* Assume V9 processors are capable of at least dual-issue. */
10234 case PROCESSOR_NIAGARA4
:
10235 case PROCESSOR_NIAGARA7
:
10237 case PROCESSOR_NIAGARA
:
10238 case PROCESSOR_NIAGARA2
:
10239 case PROCESSOR_NIAGARA3
:
10246 sparc_branch_cost (bool speed_p
, bool predictable_p
)
10251 /* For pre-V9 processors we use a single value (usually 3) to take into
10252 account the potential annulling of the delay slot (which ends up being
10253 a bubble in the pipeline slot) plus a cycle to take into consideration
10254 the instruction cache effects.
10256 On V9 and later processors, which have branch prediction facilities,
10257 we take into account whether the branch is (easily) predictable. */
10258 const int cost
= sparc_costs
->branch_cost
;
10263 case PROCESSOR_ULTRASPARC
:
10264 case PROCESSOR_ULTRASPARC3
:
10265 case PROCESSOR_NIAGARA
:
10266 case PROCESSOR_NIAGARA2
:
10267 case PROCESSOR_NIAGARA3
:
10268 case PROCESSOR_NIAGARA4
:
10269 case PROCESSOR_NIAGARA7
:
10271 return cost
+ (predictable_p
? 0 : 2);
10279 set_extends (rtx_insn
*insn
)
10281 register rtx pat
= PATTERN (insn
);
10283 switch (GET_CODE (SET_SRC (pat
)))
10285 /* Load and some shift instructions zero extend. */
10288 /* sethi clears the high bits */
10290 /* LO_SUM is used with sethi. sethi cleared the high
10291 bits and the values used with lo_sum are positive */
10293 /* Store flag stores 0 or 1 */
10303 rtx op0
= XEXP (SET_SRC (pat
), 0);
10304 rtx op1
= XEXP (SET_SRC (pat
), 1);
10305 if (GET_CODE (op1
) == CONST_INT
)
10306 return INTVAL (op1
) >= 0;
10307 if (GET_CODE (op0
) != REG
)
10309 if (sparc_check_64 (op0
, insn
) == 1)
10311 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
10316 rtx op0
= XEXP (SET_SRC (pat
), 0);
10317 rtx op1
= XEXP (SET_SRC (pat
), 1);
10318 if (GET_CODE (op0
) != REG
|| sparc_check_64 (op0
, insn
) <= 0)
10320 if (GET_CODE (op1
) == CONST_INT
)
10321 return INTVAL (op1
) >= 0;
10322 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
10325 return GET_MODE (SET_SRC (pat
)) == SImode
;
10326 /* Positive integers leave the high bits zero. */
10328 return !(INTVAL (SET_SRC (pat
)) & 0x80000000);
10331 return - (GET_MODE (SET_SRC (pat
)) == SImode
);
10333 return sparc_check_64 (SET_SRC (pat
), insn
);
10339 /* We _ought_ to have only one kind per function, but... */
10340 static GTY(()) rtx sparc_addr_diff_list
;
10341 static GTY(()) rtx sparc_addr_list
;
10344 sparc_defer_case_vector (rtx lab
, rtx vec
, int diff
)
10346 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
10348 sparc_addr_diff_list
10349 = gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_diff_list
);
10351 sparc_addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_list
);
10355 sparc_output_addr_vec (rtx vec
)
10357 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
10358 int idx
, vlen
= XVECLEN (body
, 0);
10360 #ifdef ASM_OUTPUT_ADDR_VEC_START
10361 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
10364 #ifdef ASM_OUTPUT_CASE_LABEL
10365 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
10368 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
10371 for (idx
= 0; idx
< vlen
; idx
++)
10373 ASM_OUTPUT_ADDR_VEC_ELT
10374 (asm_out_file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
10377 #ifdef ASM_OUTPUT_ADDR_VEC_END
10378 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
10383 sparc_output_addr_diff_vec (rtx vec
)
10385 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
10386 rtx base
= XEXP (XEXP (body
, 0), 0);
10387 int idx
, vlen
= XVECLEN (body
, 1);
10389 #ifdef ASM_OUTPUT_ADDR_VEC_START
10390 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
10393 #ifdef ASM_OUTPUT_CASE_LABEL
10394 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
10397 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
10400 for (idx
= 0; idx
< vlen
; idx
++)
10402 ASM_OUTPUT_ADDR_DIFF_ELT
10405 CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 1, idx
), 0)),
10406 CODE_LABEL_NUMBER (base
));
10409 #ifdef ASM_OUTPUT_ADDR_VEC_END
10410 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
10415 sparc_output_deferred_case_vectors (void)
10420 if (sparc_addr_list
== NULL_RTX
10421 && sparc_addr_diff_list
== NULL_RTX
)
10424 /* Align to cache line in the function's code section. */
10425 switch_to_section (current_function_section ());
10427 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
10429 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
10431 for (t
= sparc_addr_list
; t
; t
= XEXP (t
, 1))
10432 sparc_output_addr_vec (XEXP (t
, 0));
10433 for (t
= sparc_addr_diff_list
; t
; t
= XEXP (t
, 1))
10434 sparc_output_addr_diff_vec (XEXP (t
, 0));
10436 sparc_addr_list
= sparc_addr_diff_list
= NULL_RTX
;
10439 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
10440 unknown. Return 1 if the high bits are zero, -1 if the register is
10443 sparc_check_64 (rtx x
, rtx_insn
*insn
)
10445 /* If a register is set only once it is safe to ignore insns this
10446 code does not know how to handle. The loop will either recognize
10447 the single set and return the correct value or fail to recognize
10448 it and return 0. */
10452 gcc_assert (GET_CODE (x
) == REG
);
10454 if (GET_MODE (x
) == DImode
)
10455 y
= gen_rtx_REG (SImode
, REGNO (x
) + WORDS_BIG_ENDIAN
);
10457 if (flag_expensive_optimizations
10458 && df
&& DF_REG_DEF_COUNT (REGNO (y
)) == 1)
10464 insn
= get_last_insn_anywhere ();
10469 while ((insn
= PREV_INSN (insn
)))
10471 switch (GET_CODE (insn
))
10484 rtx pat
= PATTERN (insn
);
10485 if (GET_CODE (pat
) != SET
)
10487 if (rtx_equal_p (x
, SET_DEST (pat
)))
10488 return set_extends (insn
);
10489 if (y
&& rtx_equal_p (y
, SET_DEST (pat
)))
10490 return set_extends (insn
);
10491 if (reg_overlap_mentioned_p (SET_DEST (pat
), y
))
10499 /* Output a wide shift instruction in V8+ mode. INSN is the instruction,
10500 OPERANDS are its operands and OPCODE is the mnemonic to be used. */
10503 output_v8plus_shift (rtx_insn
*insn
, rtx
*operands
, const char *opcode
)
10505 static char asm_code
[60];
10507 /* The scratch register is only required when the destination
10508 register is not a 64-bit global or out register. */
10509 if (which_alternative
!= 2)
10510 operands
[3] = operands
[0];
10512 /* We can only shift by constants <= 63. */
10513 if (GET_CODE (operands
[2]) == CONST_INT
)
10514 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0x3f);
10516 if (GET_CODE (operands
[1]) == CONST_INT
)
10518 output_asm_insn ("mov\t%1, %3", operands
);
10522 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
10523 if (sparc_check_64 (operands
[1], insn
) <= 0)
10524 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
10525 output_asm_insn ("or\t%L1, %3, %3", operands
);
10528 strcpy (asm_code
, opcode
);
10530 if (which_alternative
!= 2)
10531 return strcat (asm_code
, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
10534 strcat (asm_code
, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
10537 /* Output rtl to increment the profiler label LABELNO
10538 for profiling a function entry. */
10541 sparc_profile_hook (int labelno
)
10546 fun
= gen_rtx_SYMBOL_REF (Pmode
, MCOUNT_FUNCTION
);
10547 if (NO_PROFILE_COUNTERS
)
10549 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
);
10553 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
10554 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
10555 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, lab
, Pmode
);
10559 #ifdef TARGET_SOLARIS
10560 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
10563 sparc_solaris_elf_asm_named_section (const char *name
, unsigned int flags
,
10564 tree decl ATTRIBUTE_UNUSED
)
10566 if (HAVE_COMDAT_GROUP
&& flags
& SECTION_LINKONCE
)
10568 solaris_elf_asm_comdat_section (name
, flags
, decl
);
10572 fprintf (asm_out_file
, "\t.section\t\"%s\"", name
);
10574 if (!(flags
& SECTION_DEBUG
))
10575 fputs (",#alloc", asm_out_file
);
10576 #if HAVE_GAS_SECTION_EXCLUDE
10577 if (flags
& SECTION_EXCLUDE
)
10578 fputs (",#exclude", asm_out_file
);
10580 if (flags
& SECTION_WRITE
)
10581 fputs (",#write", asm_out_file
);
10582 if (flags
& SECTION_TLS
)
10583 fputs (",#tls", asm_out_file
);
10584 if (flags
& SECTION_CODE
)
10585 fputs (",#execinstr", asm_out_file
);
10587 if (flags
& SECTION_NOTYPE
)
10589 else if (flags
& SECTION_BSS
)
10590 fputs (",#nobits", asm_out_file
);
10592 fputs (",#progbits", asm_out_file
);
10594 fputc ('\n', asm_out_file
);
10596 #endif /* TARGET_SOLARIS */
10598 /* We do not allow indirect calls to be optimized into sibling calls.
10600 We cannot use sibling calls when delayed branches are disabled
10601 because they will likely require the call delay slot to be filled.
10603 Also, on SPARC 32-bit we cannot emit a sibling call when the
10604 current function returns a structure. This is because the "unimp
10605 after call" convention would cause the callee to return to the
10606 wrong place. The generic code already disallows cases where the
10607 function being called returns a structure.
10609 It may seem strange how this last case could occur. Usually there
10610 is code after the call which jumps to epilogue code which dumps the
10611 return value into the struct return area. That ought to invalidate
10612 the sibling call right? Well, in the C++ case we can end up passing
10613 the pointer to the struct return area to a constructor (which returns
10614 void) and then nothing else happens. Such a sibling call would look
10615 valid without the added check here.
10617 VxWorks PIC PLT entries require the global pointer to be initialized
10618 on entry. We therefore can't emit sibling calls to them. */
10620 sparc_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
10623 && flag_delayed_branch
10624 && (TARGET_ARCH64
|| ! cfun
->returns_struct
)
10625 && !(TARGET_VXWORKS_RTP
10627 && !targetm
.binds_local_p (decl
)));
10630 /* libfunc renaming. */
10633 sparc_init_libfuncs (void)
10637 /* Use the subroutines that Sun's library provides for integer
10638 multiply and divide. The `*' prevents an underscore from
10639 being prepended by the compiler. .umul is a little faster
10641 set_optab_libfunc (smul_optab
, SImode
, "*.umul");
10642 set_optab_libfunc (sdiv_optab
, SImode
, "*.div");
10643 set_optab_libfunc (udiv_optab
, SImode
, "*.udiv");
10644 set_optab_libfunc (smod_optab
, SImode
, "*.rem");
10645 set_optab_libfunc (umod_optab
, SImode
, "*.urem");
10647 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
10648 set_optab_libfunc (add_optab
, TFmode
, "_Q_add");
10649 set_optab_libfunc (sub_optab
, TFmode
, "_Q_sub");
10650 set_optab_libfunc (neg_optab
, TFmode
, "_Q_neg");
10651 set_optab_libfunc (smul_optab
, TFmode
, "_Q_mul");
10652 set_optab_libfunc (sdiv_optab
, TFmode
, "_Q_div");
10654 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
10655 is because with soft-float, the SFmode and DFmode sqrt
10656 instructions will be absent, and the compiler will notice and
10657 try to use the TFmode sqrt instruction for calls to the
10658 builtin function sqrt, but this fails. */
10660 set_optab_libfunc (sqrt_optab
, TFmode
, "_Q_sqrt");
10662 set_optab_libfunc (eq_optab
, TFmode
, "_Q_feq");
10663 set_optab_libfunc (ne_optab
, TFmode
, "_Q_fne");
10664 set_optab_libfunc (gt_optab
, TFmode
, "_Q_fgt");
10665 set_optab_libfunc (ge_optab
, TFmode
, "_Q_fge");
10666 set_optab_libfunc (lt_optab
, TFmode
, "_Q_flt");
10667 set_optab_libfunc (le_optab
, TFmode
, "_Q_fle");
10669 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_Q_stoq");
10670 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_Q_dtoq");
10671 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_Q_qtos");
10672 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_Q_qtod");
10674 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_Q_qtoi");
10675 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_Q_qtou");
10676 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_Q_itoq");
10677 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_Q_utoq");
10679 if (DITF_CONVERSION_LIBFUNCS
)
10681 set_conv_libfunc (sfix_optab
, DImode
, TFmode
, "_Q_qtoll");
10682 set_conv_libfunc (ufix_optab
, DImode
, TFmode
, "_Q_qtoull");
10683 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
, "_Q_lltoq");
10684 set_conv_libfunc (ufloat_optab
, TFmode
, DImode
, "_Q_ulltoq");
10687 if (SUN_CONVERSION_LIBFUNCS
)
10689 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
10690 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
10691 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
10692 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
10697 /* In the SPARC 64bit ABI, SImode multiply and divide functions
10698 do not exist in the library. Make sure the compiler does not
10699 emit calls to them by accident. (It should always use the
10700 hardware instructions.) */
10701 set_optab_libfunc (smul_optab
, SImode
, 0);
10702 set_optab_libfunc (sdiv_optab
, SImode
, 0);
10703 set_optab_libfunc (udiv_optab
, SImode
, 0);
10704 set_optab_libfunc (smod_optab
, SImode
, 0);
10705 set_optab_libfunc (umod_optab
, SImode
, 0);
10707 if (SUN_INTEGER_MULTIPLY_64
)
10709 set_optab_libfunc (smul_optab
, DImode
, "__mul64");
10710 set_optab_libfunc (sdiv_optab
, DImode
, "__div64");
10711 set_optab_libfunc (udiv_optab
, DImode
, "__udiv64");
10712 set_optab_libfunc (smod_optab
, DImode
, "__rem64");
10713 set_optab_libfunc (umod_optab
, DImode
, "__urem64");
10716 if (SUN_CONVERSION_LIBFUNCS
)
10718 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftol");
10719 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoul");
10720 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtol");
10721 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoul");
10726 /* SPARC builtins. */
10727 enum sparc_builtins
10729 /* FPU builtins. */
10730 SPARC_BUILTIN_LDFSR
,
10731 SPARC_BUILTIN_STFSR
,
10733 /* VIS 1.0 builtins. */
10734 SPARC_BUILTIN_FPACK16
,
10735 SPARC_BUILTIN_FPACK32
,
10736 SPARC_BUILTIN_FPACKFIX
,
10737 SPARC_BUILTIN_FEXPAND
,
10738 SPARC_BUILTIN_FPMERGE
,
10739 SPARC_BUILTIN_FMUL8X16
,
10740 SPARC_BUILTIN_FMUL8X16AU
,
10741 SPARC_BUILTIN_FMUL8X16AL
,
10742 SPARC_BUILTIN_FMUL8SUX16
,
10743 SPARC_BUILTIN_FMUL8ULX16
,
10744 SPARC_BUILTIN_FMULD8SUX16
,
10745 SPARC_BUILTIN_FMULD8ULX16
,
10746 SPARC_BUILTIN_FALIGNDATAV4HI
,
10747 SPARC_BUILTIN_FALIGNDATAV8QI
,
10748 SPARC_BUILTIN_FALIGNDATAV2SI
,
10749 SPARC_BUILTIN_FALIGNDATADI
,
10750 SPARC_BUILTIN_WRGSR
,
10751 SPARC_BUILTIN_RDGSR
,
10752 SPARC_BUILTIN_ALIGNADDR
,
10753 SPARC_BUILTIN_ALIGNADDRL
,
10754 SPARC_BUILTIN_PDIST
,
10755 SPARC_BUILTIN_EDGE8
,
10756 SPARC_BUILTIN_EDGE8L
,
10757 SPARC_BUILTIN_EDGE16
,
10758 SPARC_BUILTIN_EDGE16L
,
10759 SPARC_BUILTIN_EDGE32
,
10760 SPARC_BUILTIN_EDGE32L
,
10761 SPARC_BUILTIN_FCMPLE16
,
10762 SPARC_BUILTIN_FCMPLE32
,
10763 SPARC_BUILTIN_FCMPNE16
,
10764 SPARC_BUILTIN_FCMPNE32
,
10765 SPARC_BUILTIN_FCMPGT16
,
10766 SPARC_BUILTIN_FCMPGT32
,
10767 SPARC_BUILTIN_FCMPEQ16
,
10768 SPARC_BUILTIN_FCMPEQ32
,
10769 SPARC_BUILTIN_FPADD16
,
10770 SPARC_BUILTIN_FPADD16S
,
10771 SPARC_BUILTIN_FPADD32
,
10772 SPARC_BUILTIN_FPADD32S
,
10773 SPARC_BUILTIN_FPSUB16
,
10774 SPARC_BUILTIN_FPSUB16S
,
10775 SPARC_BUILTIN_FPSUB32
,
10776 SPARC_BUILTIN_FPSUB32S
,
10777 SPARC_BUILTIN_ARRAY8
,
10778 SPARC_BUILTIN_ARRAY16
,
10779 SPARC_BUILTIN_ARRAY32
,
10781 /* VIS 2.0 builtins. */
10782 SPARC_BUILTIN_EDGE8N
,
10783 SPARC_BUILTIN_EDGE8LN
,
10784 SPARC_BUILTIN_EDGE16N
,
10785 SPARC_BUILTIN_EDGE16LN
,
10786 SPARC_BUILTIN_EDGE32N
,
10787 SPARC_BUILTIN_EDGE32LN
,
10788 SPARC_BUILTIN_BMASK
,
10789 SPARC_BUILTIN_BSHUFFLEV4HI
,
10790 SPARC_BUILTIN_BSHUFFLEV8QI
,
10791 SPARC_BUILTIN_BSHUFFLEV2SI
,
10792 SPARC_BUILTIN_BSHUFFLEDI
,
10794 /* VIS 3.0 builtins. */
10795 SPARC_BUILTIN_CMASK8
,
10796 SPARC_BUILTIN_CMASK16
,
10797 SPARC_BUILTIN_CMASK32
,
10798 SPARC_BUILTIN_FCHKSM16
,
10799 SPARC_BUILTIN_FSLL16
,
10800 SPARC_BUILTIN_FSLAS16
,
10801 SPARC_BUILTIN_FSRL16
,
10802 SPARC_BUILTIN_FSRA16
,
10803 SPARC_BUILTIN_FSLL32
,
10804 SPARC_BUILTIN_FSLAS32
,
10805 SPARC_BUILTIN_FSRL32
,
10806 SPARC_BUILTIN_FSRA32
,
10807 SPARC_BUILTIN_PDISTN
,
10808 SPARC_BUILTIN_FMEAN16
,
10809 SPARC_BUILTIN_FPADD64
,
10810 SPARC_BUILTIN_FPSUB64
,
10811 SPARC_BUILTIN_FPADDS16
,
10812 SPARC_BUILTIN_FPADDS16S
,
10813 SPARC_BUILTIN_FPSUBS16
,
10814 SPARC_BUILTIN_FPSUBS16S
,
10815 SPARC_BUILTIN_FPADDS32
,
10816 SPARC_BUILTIN_FPADDS32S
,
10817 SPARC_BUILTIN_FPSUBS32
,
10818 SPARC_BUILTIN_FPSUBS32S
,
10819 SPARC_BUILTIN_FUCMPLE8
,
10820 SPARC_BUILTIN_FUCMPNE8
,
10821 SPARC_BUILTIN_FUCMPGT8
,
10822 SPARC_BUILTIN_FUCMPEQ8
,
10823 SPARC_BUILTIN_FHADDS
,
10824 SPARC_BUILTIN_FHADDD
,
10825 SPARC_BUILTIN_FHSUBS
,
10826 SPARC_BUILTIN_FHSUBD
,
10827 SPARC_BUILTIN_FNHADDS
,
10828 SPARC_BUILTIN_FNHADDD
,
10829 SPARC_BUILTIN_UMULXHI
,
10830 SPARC_BUILTIN_XMULX
,
10831 SPARC_BUILTIN_XMULXHI
,
10833 /* VIS 4.0 builtins. */
10834 SPARC_BUILTIN_FPADD8
,
10835 SPARC_BUILTIN_FPADDS8
,
10836 SPARC_BUILTIN_FPADDUS8
,
10837 SPARC_BUILTIN_FPADDUS16
,
10838 SPARC_BUILTIN_FPCMPLE8
,
10839 SPARC_BUILTIN_FPCMPGT8
,
10840 SPARC_BUILTIN_FPCMPULE16
,
10841 SPARC_BUILTIN_FPCMPUGT16
,
10842 SPARC_BUILTIN_FPCMPULE32
,
10843 SPARC_BUILTIN_FPCMPUGT32
,
10844 SPARC_BUILTIN_FPMAX8
,
10845 SPARC_BUILTIN_FPMAX16
,
10846 SPARC_BUILTIN_FPMAX32
,
10847 SPARC_BUILTIN_FPMAXU8
,
10848 SPARC_BUILTIN_FPMAXU16
,
10849 SPARC_BUILTIN_FPMAXU32
,
10850 SPARC_BUILTIN_FPMIN8
,
10851 SPARC_BUILTIN_FPMIN16
,
10852 SPARC_BUILTIN_FPMIN32
,
10853 SPARC_BUILTIN_FPMINU8
,
10854 SPARC_BUILTIN_FPMINU16
,
10855 SPARC_BUILTIN_FPMINU32
,
10856 SPARC_BUILTIN_FPSUB8
,
10857 SPARC_BUILTIN_FPSUBS8
,
10858 SPARC_BUILTIN_FPSUBUS8
,
10859 SPARC_BUILTIN_FPSUBUS16
,
10861 /* VIS 4.0B builtins. */
10863 /* Note that all the DICTUNPACK* entries should be kept
10865 SPARC_BUILTIN_FIRST_DICTUNPACK
,
10866 SPARC_BUILTIN_DICTUNPACK8
= SPARC_BUILTIN_FIRST_DICTUNPACK
,
10867 SPARC_BUILTIN_DICTUNPACK16
,
10868 SPARC_BUILTIN_DICTUNPACK32
,
10869 SPARC_BUILTIN_LAST_DICTUNPACK
= SPARC_BUILTIN_DICTUNPACK32
,
10871 /* Note that all the FPCMP*SHL entries should be kept
10873 SPARC_BUILTIN_FIRST_FPCMPSHL
,
10874 SPARC_BUILTIN_FPCMPLE8SHL
= SPARC_BUILTIN_FIRST_FPCMPSHL
,
10875 SPARC_BUILTIN_FPCMPGT8SHL
,
10876 SPARC_BUILTIN_FPCMPEQ8SHL
,
10877 SPARC_BUILTIN_FPCMPNE8SHL
,
10878 SPARC_BUILTIN_FPCMPLE16SHL
,
10879 SPARC_BUILTIN_FPCMPGT16SHL
,
10880 SPARC_BUILTIN_FPCMPEQ16SHL
,
10881 SPARC_BUILTIN_FPCMPNE16SHL
,
10882 SPARC_BUILTIN_FPCMPLE32SHL
,
10883 SPARC_BUILTIN_FPCMPGT32SHL
,
10884 SPARC_BUILTIN_FPCMPEQ32SHL
,
10885 SPARC_BUILTIN_FPCMPNE32SHL
,
10886 SPARC_BUILTIN_FPCMPULE8SHL
,
10887 SPARC_BUILTIN_FPCMPUGT8SHL
,
10888 SPARC_BUILTIN_FPCMPULE16SHL
,
10889 SPARC_BUILTIN_FPCMPUGT16SHL
,
10890 SPARC_BUILTIN_FPCMPULE32SHL
,
10891 SPARC_BUILTIN_FPCMPUGT32SHL
,
10892 SPARC_BUILTIN_FPCMPDE8SHL
,
10893 SPARC_BUILTIN_FPCMPDE16SHL
,
10894 SPARC_BUILTIN_FPCMPDE32SHL
,
10895 SPARC_BUILTIN_FPCMPUR8SHL
,
10896 SPARC_BUILTIN_FPCMPUR16SHL
,
10897 SPARC_BUILTIN_FPCMPUR32SHL
,
10898 SPARC_BUILTIN_LAST_FPCMPSHL
= SPARC_BUILTIN_FPCMPUR32SHL
,
10903 static GTY (()) tree sparc_builtins
[(int) SPARC_BUILTIN_MAX
];
10904 static enum insn_code sparc_builtins_icode
[(int) SPARC_BUILTIN_MAX
];
10906 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
10907 The instruction should require a constant operand of some sort. The
10908 function prints an error if OPVAL is not valid. */
10911 check_constant_argument (enum insn_code icode
, int opnum
, rtx opval
)
10913 if (GET_CODE (opval
) != CONST_INT
)
10915 error ("%qs expects a constant argument", insn_data
[icode
].name
);
10919 if (!(*insn_data
[icode
].operand
[opnum
].predicate
) (opval
, VOIDmode
))
10921 error ("constant argument out of range for %qs", insn_data
[icode
].name
);
10927 /* Add a SPARC builtin function with NAME, ICODE, CODE and TYPE. Return the
10928 function decl or NULL_TREE if the builtin was not added. */
10931 def_builtin (const char *name
, enum insn_code icode
, enum sparc_builtins code
,
10935 = add_builtin_function (name
, type
, code
, BUILT_IN_MD
, NULL
, NULL_TREE
);
10939 sparc_builtins
[code
] = t
;
10940 sparc_builtins_icode
[code
] = icode
;
10946 /* Likewise, but also marks the function as "const". */
10949 def_builtin_const (const char *name
, enum insn_code icode
,
10950 enum sparc_builtins code
, tree type
)
10952 tree t
= def_builtin (name
, icode
, code
, type
);
10955 TREE_READONLY (t
) = 1;
10960 /* Implement the TARGET_INIT_BUILTINS target hook.
10961 Create builtin functions for special SPARC instructions. */
10964 sparc_init_builtins (void)
10967 sparc_fpu_init_builtins ();
10970 sparc_vis_init_builtins ();
10973 /* Create builtin functions for FPU instructions. */
10976 sparc_fpu_init_builtins (void)
10979 = build_function_type_list (void_type_node
,
10980 build_pointer_type (unsigned_type_node
), 0);
10981 def_builtin ("__builtin_load_fsr", CODE_FOR_ldfsr
,
10982 SPARC_BUILTIN_LDFSR
, ftype
);
10983 def_builtin ("__builtin_store_fsr", CODE_FOR_stfsr
,
10984 SPARC_BUILTIN_STFSR
, ftype
);
10987 /* Create builtin functions for VIS instructions. */
10990 sparc_vis_init_builtins (void)
10992 tree v4qi
= build_vector_type (unsigned_intQI_type_node
, 4);
10993 tree v8qi
= build_vector_type (unsigned_intQI_type_node
, 8);
10994 tree v4hi
= build_vector_type (intHI_type_node
, 4);
10995 tree v2hi
= build_vector_type (intHI_type_node
, 2);
10996 tree v2si
= build_vector_type (intSI_type_node
, 2);
10997 tree v1si
= build_vector_type (intSI_type_node
, 1);
10999 tree v4qi_ftype_v4hi
= build_function_type_list (v4qi
, v4hi
, 0);
11000 tree v8qi_ftype_v2si_v8qi
= build_function_type_list (v8qi
, v2si
, v8qi
, 0);
11001 tree v2hi_ftype_v2si
= build_function_type_list (v2hi
, v2si
, 0);
11002 tree v4hi_ftype_v4qi
= build_function_type_list (v4hi
, v4qi
, 0);
11003 tree v8qi_ftype_v4qi_v4qi
= build_function_type_list (v8qi
, v4qi
, v4qi
, 0);
11004 tree v4hi_ftype_v4qi_v4hi
= build_function_type_list (v4hi
, v4qi
, v4hi
, 0);
11005 tree v4hi_ftype_v4qi_v2hi
= build_function_type_list (v4hi
, v4qi
, v2hi
, 0);
11006 tree v2si_ftype_v4qi_v2hi
= build_function_type_list (v2si
, v4qi
, v2hi
, 0);
11007 tree v4hi_ftype_v8qi_v4hi
= build_function_type_list (v4hi
, v8qi
, v4hi
, 0);
11008 tree v4hi_ftype_v4hi_v4hi
= build_function_type_list (v4hi
, v4hi
, v4hi
, 0);
11009 tree v2si_ftype_v2si_v2si
= build_function_type_list (v2si
, v2si
, v2si
, 0);
11010 tree v8qi_ftype_v8qi_v8qi
= build_function_type_list (v8qi
, v8qi
, v8qi
, 0);
11011 tree v2hi_ftype_v2hi_v2hi
= build_function_type_list (v2hi
, v2hi
, v2hi
, 0);
11012 tree v1si_ftype_v1si_v1si
= build_function_type_list (v1si
, v1si
, v1si
, 0);
11013 tree di_ftype_v8qi_v8qi_di
= build_function_type_list (intDI_type_node
,
11015 intDI_type_node
, 0);
11016 tree di_ftype_v8qi_v8qi
= build_function_type_list (intDI_type_node
,
11018 tree si_ftype_v8qi_v8qi
= build_function_type_list (intSI_type_node
,
11020 tree v8qi_ftype_df_si
= build_function_type_list (v8qi
, double_type_node
,
11021 intSI_type_node
, 0);
11022 tree v4hi_ftype_df_si
= build_function_type_list (v4hi
, double_type_node
,
11023 intSI_type_node
, 0);
11024 tree v2si_ftype_df_si
= build_function_type_list (v2si
, double_type_node
,
11025 intDI_type_node
, 0);
11026 tree di_ftype_di_di
= build_function_type_list (intDI_type_node
,
11028 intDI_type_node
, 0);
11029 tree si_ftype_si_si
= build_function_type_list (intSI_type_node
,
11031 intSI_type_node
, 0);
11032 tree ptr_ftype_ptr_si
= build_function_type_list (ptr_type_node
,
11034 intSI_type_node
, 0);
11035 tree ptr_ftype_ptr_di
= build_function_type_list (ptr_type_node
,
11037 intDI_type_node
, 0);
11038 tree si_ftype_ptr_ptr
= build_function_type_list (intSI_type_node
,
11041 tree di_ftype_ptr_ptr
= build_function_type_list (intDI_type_node
,
11044 tree si_ftype_v4hi_v4hi
= build_function_type_list (intSI_type_node
,
11046 tree si_ftype_v2si_v2si
= build_function_type_list (intSI_type_node
,
11048 tree di_ftype_v4hi_v4hi
= build_function_type_list (intDI_type_node
,
11050 tree di_ftype_v2si_v2si
= build_function_type_list (intDI_type_node
,
11052 tree void_ftype_di
= build_function_type_list (void_type_node
,
11053 intDI_type_node
, 0);
11054 tree di_ftype_void
= build_function_type_list (intDI_type_node
,
11055 void_type_node
, 0);
11056 tree void_ftype_si
= build_function_type_list (void_type_node
,
11057 intSI_type_node
, 0);
11058 tree sf_ftype_sf_sf
= build_function_type_list (float_type_node
,
11060 float_type_node
, 0);
11061 tree df_ftype_df_df
= build_function_type_list (double_type_node
,
11063 double_type_node
, 0);
11065 /* Packing and expanding vectors. */
11066 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis
,
11067 SPARC_BUILTIN_FPACK16
, v4qi_ftype_v4hi
);
11068 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis
,
11069 SPARC_BUILTIN_FPACK32
, v8qi_ftype_v2si_v8qi
);
11070 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis
,
11071 SPARC_BUILTIN_FPACKFIX
, v2hi_ftype_v2si
);
11072 def_builtin_const ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis
,
11073 SPARC_BUILTIN_FEXPAND
, v4hi_ftype_v4qi
);
11074 def_builtin_const ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis
,
11075 SPARC_BUILTIN_FPMERGE
, v8qi_ftype_v4qi_v4qi
);
11077 /* Multiplications. */
11078 def_builtin_const ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis
,
11079 SPARC_BUILTIN_FMUL8X16
, v4hi_ftype_v4qi_v4hi
);
11080 def_builtin_const ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis
,
11081 SPARC_BUILTIN_FMUL8X16AU
, v4hi_ftype_v4qi_v2hi
);
11082 def_builtin_const ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis
,
11083 SPARC_BUILTIN_FMUL8X16AL
, v4hi_ftype_v4qi_v2hi
);
11084 def_builtin_const ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis
,
11085 SPARC_BUILTIN_FMUL8SUX16
, v4hi_ftype_v8qi_v4hi
);
11086 def_builtin_const ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis
,
11087 SPARC_BUILTIN_FMUL8ULX16
, v4hi_ftype_v8qi_v4hi
);
11088 def_builtin_const ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis
,
11089 SPARC_BUILTIN_FMULD8SUX16
, v2si_ftype_v4qi_v2hi
);
11090 def_builtin_const ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis
,
11091 SPARC_BUILTIN_FMULD8ULX16
, v2si_ftype_v4qi_v2hi
);
11093 /* Data aligning. */
11094 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis
,
11095 SPARC_BUILTIN_FALIGNDATAV4HI
, v4hi_ftype_v4hi_v4hi
);
11096 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis
,
11097 SPARC_BUILTIN_FALIGNDATAV8QI
, v8qi_ftype_v8qi_v8qi
);
11098 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis
,
11099 SPARC_BUILTIN_FALIGNDATAV2SI
, v2si_ftype_v2si_v2si
);
11100 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatav1di_vis
,
11101 SPARC_BUILTIN_FALIGNDATADI
, di_ftype_di_di
);
11103 def_builtin ("__builtin_vis_write_gsr", CODE_FOR_wrgsr_vis
,
11104 SPARC_BUILTIN_WRGSR
, void_ftype_di
);
11105 def_builtin ("__builtin_vis_read_gsr", CODE_FOR_rdgsr_vis
,
11106 SPARC_BUILTIN_RDGSR
, di_ftype_void
);
11110 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis
,
11111 SPARC_BUILTIN_ALIGNADDR
, ptr_ftype_ptr_di
);
11112 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrldi_vis
,
11113 SPARC_BUILTIN_ALIGNADDRL
, ptr_ftype_ptr_di
);
11117 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis
,
11118 SPARC_BUILTIN_ALIGNADDR
, ptr_ftype_ptr_si
);
11119 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrlsi_vis
,
11120 SPARC_BUILTIN_ALIGNADDRL
, ptr_ftype_ptr_si
);
11123 /* Pixel distance. */
11124 def_builtin_const ("__builtin_vis_pdist", CODE_FOR_pdist_vis
,
11125 SPARC_BUILTIN_PDIST
, di_ftype_v8qi_v8qi_di
);
11127 /* Edge handling. */
11130 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8di_vis
,
11131 SPARC_BUILTIN_EDGE8
, di_ftype_ptr_ptr
);
11132 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8ldi_vis
,
11133 SPARC_BUILTIN_EDGE8L
, di_ftype_ptr_ptr
);
11134 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16di_vis
,
11135 SPARC_BUILTIN_EDGE16
, di_ftype_ptr_ptr
);
11136 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16ldi_vis
,
11137 SPARC_BUILTIN_EDGE16L
, di_ftype_ptr_ptr
);
11138 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32di_vis
,
11139 SPARC_BUILTIN_EDGE32
, di_ftype_ptr_ptr
);
11140 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32ldi_vis
,
11141 SPARC_BUILTIN_EDGE32L
, di_ftype_ptr_ptr
);
11145 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8si_vis
,
11146 SPARC_BUILTIN_EDGE8
, si_ftype_ptr_ptr
);
11147 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8lsi_vis
,
11148 SPARC_BUILTIN_EDGE8L
, si_ftype_ptr_ptr
);
11149 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16si_vis
,
11150 SPARC_BUILTIN_EDGE16
, si_ftype_ptr_ptr
);
11151 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16lsi_vis
,
11152 SPARC_BUILTIN_EDGE16L
, si_ftype_ptr_ptr
);
11153 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32si_vis
,
11154 SPARC_BUILTIN_EDGE32
, si_ftype_ptr_ptr
);
11155 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32lsi_vis
,
11156 SPARC_BUILTIN_EDGE32L
, si_ftype_ptr_ptr
);
11159 /* Pixel compare. */
11162 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16di_vis
,
11163 SPARC_BUILTIN_FCMPLE16
, di_ftype_v4hi_v4hi
);
11164 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32di_vis
,
11165 SPARC_BUILTIN_FCMPLE32
, di_ftype_v2si_v2si
);
11166 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16di_vis
,
11167 SPARC_BUILTIN_FCMPNE16
, di_ftype_v4hi_v4hi
);
11168 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32di_vis
,
11169 SPARC_BUILTIN_FCMPNE32
, di_ftype_v2si_v2si
);
11170 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16di_vis
,
11171 SPARC_BUILTIN_FCMPGT16
, di_ftype_v4hi_v4hi
);
11172 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32di_vis
,
11173 SPARC_BUILTIN_FCMPGT32
, di_ftype_v2si_v2si
);
11174 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16di_vis
,
11175 SPARC_BUILTIN_FCMPEQ16
, di_ftype_v4hi_v4hi
);
11176 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32di_vis
,
11177 SPARC_BUILTIN_FCMPEQ32
, di_ftype_v2si_v2si
);
11181 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16si_vis
,
11182 SPARC_BUILTIN_FCMPLE16
, si_ftype_v4hi_v4hi
);
11183 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32si_vis
,
11184 SPARC_BUILTIN_FCMPLE32
, si_ftype_v2si_v2si
);
11185 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16si_vis
,
11186 SPARC_BUILTIN_FCMPNE16
, si_ftype_v4hi_v4hi
);
11187 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32si_vis
,
11188 SPARC_BUILTIN_FCMPNE32
, si_ftype_v2si_v2si
);
11189 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16si_vis
,
11190 SPARC_BUILTIN_FCMPGT16
, si_ftype_v4hi_v4hi
);
11191 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32si_vis
,
11192 SPARC_BUILTIN_FCMPGT32
, si_ftype_v2si_v2si
);
11193 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16si_vis
,
11194 SPARC_BUILTIN_FCMPEQ16
, si_ftype_v4hi_v4hi
);
11195 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32si_vis
,
11196 SPARC_BUILTIN_FCMPEQ32
, si_ftype_v2si_v2si
);
11199 /* Addition and subtraction. */
11200 def_builtin_const ("__builtin_vis_fpadd16", CODE_FOR_addv4hi3
,
11201 SPARC_BUILTIN_FPADD16
, v4hi_ftype_v4hi_v4hi
);
11202 def_builtin_const ("__builtin_vis_fpadd16s", CODE_FOR_addv2hi3
,
11203 SPARC_BUILTIN_FPADD16S
, v2hi_ftype_v2hi_v2hi
);
11204 def_builtin_const ("__builtin_vis_fpadd32", CODE_FOR_addv2si3
,
11205 SPARC_BUILTIN_FPADD32
, v2si_ftype_v2si_v2si
);
11206 def_builtin_const ("__builtin_vis_fpadd32s", CODE_FOR_addv1si3
,
11207 SPARC_BUILTIN_FPADD32S
, v1si_ftype_v1si_v1si
);
11208 def_builtin_const ("__builtin_vis_fpsub16", CODE_FOR_subv4hi3
,
11209 SPARC_BUILTIN_FPSUB16
, v4hi_ftype_v4hi_v4hi
);
11210 def_builtin_const ("__builtin_vis_fpsub16s", CODE_FOR_subv2hi3
,
11211 SPARC_BUILTIN_FPSUB16S
, v2hi_ftype_v2hi_v2hi
);
11212 def_builtin_const ("__builtin_vis_fpsub32", CODE_FOR_subv2si3
,
11213 SPARC_BUILTIN_FPSUB32
, v2si_ftype_v2si_v2si
);
11214 def_builtin_const ("__builtin_vis_fpsub32s", CODE_FOR_subv1si3
,
11215 SPARC_BUILTIN_FPSUB32S
, v1si_ftype_v1si_v1si
);
11217 /* Three-dimensional array addressing. */
11220 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8di_vis
,
11221 SPARC_BUILTIN_ARRAY8
, di_ftype_di_di
);
11222 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16di_vis
,
11223 SPARC_BUILTIN_ARRAY16
, di_ftype_di_di
);
11224 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32di_vis
,
11225 SPARC_BUILTIN_ARRAY32
, di_ftype_di_di
);
11229 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8si_vis
,
11230 SPARC_BUILTIN_ARRAY8
, si_ftype_si_si
);
11231 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16si_vis
,
11232 SPARC_BUILTIN_ARRAY16
, si_ftype_si_si
);
11233 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32si_vis
,
11234 SPARC_BUILTIN_ARRAY32
, si_ftype_si_si
);
11239 /* Edge handling. */
11242 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8ndi_vis
,
11243 SPARC_BUILTIN_EDGE8N
, di_ftype_ptr_ptr
);
11244 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lndi_vis
,
11245 SPARC_BUILTIN_EDGE8LN
, di_ftype_ptr_ptr
);
11246 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16ndi_vis
,
11247 SPARC_BUILTIN_EDGE16N
, di_ftype_ptr_ptr
);
11248 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lndi_vis
,
11249 SPARC_BUILTIN_EDGE16LN
, di_ftype_ptr_ptr
);
11250 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32ndi_vis
,
11251 SPARC_BUILTIN_EDGE32N
, di_ftype_ptr_ptr
);
11252 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lndi_vis
,
11253 SPARC_BUILTIN_EDGE32LN
, di_ftype_ptr_ptr
);
11257 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8nsi_vis
,
11258 SPARC_BUILTIN_EDGE8N
, si_ftype_ptr_ptr
);
11259 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lnsi_vis
,
11260 SPARC_BUILTIN_EDGE8LN
, si_ftype_ptr_ptr
);
11261 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16nsi_vis
,
11262 SPARC_BUILTIN_EDGE16N
, si_ftype_ptr_ptr
);
11263 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lnsi_vis
,
11264 SPARC_BUILTIN_EDGE16LN
, si_ftype_ptr_ptr
);
11265 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32nsi_vis
,
11266 SPARC_BUILTIN_EDGE32N
, si_ftype_ptr_ptr
);
11267 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lnsi_vis
,
11268 SPARC_BUILTIN_EDGE32LN
, si_ftype_ptr_ptr
);
11271 /* Byte mask and shuffle. */
11273 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmaskdi_vis
,
11274 SPARC_BUILTIN_BMASK
, di_ftype_di_di
);
11276 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmasksi_vis
,
11277 SPARC_BUILTIN_BMASK
, si_ftype_si_si
);
11278 def_builtin ("__builtin_vis_bshufflev4hi", CODE_FOR_bshufflev4hi_vis
,
11279 SPARC_BUILTIN_BSHUFFLEV4HI
, v4hi_ftype_v4hi_v4hi
);
11280 def_builtin ("__builtin_vis_bshufflev8qi", CODE_FOR_bshufflev8qi_vis
,
11281 SPARC_BUILTIN_BSHUFFLEV8QI
, v8qi_ftype_v8qi_v8qi
);
11282 def_builtin ("__builtin_vis_bshufflev2si", CODE_FOR_bshufflev2si_vis
,
11283 SPARC_BUILTIN_BSHUFFLEV2SI
, v2si_ftype_v2si_v2si
);
11284 def_builtin ("__builtin_vis_bshuffledi", CODE_FOR_bshufflev1di_vis
,
11285 SPARC_BUILTIN_BSHUFFLEDI
, di_ftype_di_di
);
11292 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8di_vis
,
11293 SPARC_BUILTIN_CMASK8
, void_ftype_di
);
11294 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16di_vis
,
11295 SPARC_BUILTIN_CMASK16
, void_ftype_di
);
11296 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32di_vis
,
11297 SPARC_BUILTIN_CMASK32
, void_ftype_di
);
11301 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8si_vis
,
11302 SPARC_BUILTIN_CMASK8
, void_ftype_si
);
11303 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16si_vis
,
11304 SPARC_BUILTIN_CMASK16
, void_ftype_si
);
11305 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32si_vis
,
11306 SPARC_BUILTIN_CMASK32
, void_ftype_si
);
11309 def_builtin_const ("__builtin_vis_fchksm16", CODE_FOR_fchksm16_vis
,
11310 SPARC_BUILTIN_FCHKSM16
, v4hi_ftype_v4hi_v4hi
);
11312 def_builtin_const ("__builtin_vis_fsll16", CODE_FOR_vashlv4hi3
,
11313 SPARC_BUILTIN_FSLL16
, v4hi_ftype_v4hi_v4hi
);
11314 def_builtin_const ("__builtin_vis_fslas16", CODE_FOR_vssashlv4hi3
,
11315 SPARC_BUILTIN_FSLAS16
, v4hi_ftype_v4hi_v4hi
);
11316 def_builtin_const ("__builtin_vis_fsrl16", CODE_FOR_vlshrv4hi3
,
11317 SPARC_BUILTIN_FSRL16
, v4hi_ftype_v4hi_v4hi
);
11318 def_builtin_const ("__builtin_vis_fsra16", CODE_FOR_vashrv4hi3
,
11319 SPARC_BUILTIN_FSRA16
, v4hi_ftype_v4hi_v4hi
);
11320 def_builtin_const ("__builtin_vis_fsll32", CODE_FOR_vashlv2si3
,
11321 SPARC_BUILTIN_FSLL32
, v2si_ftype_v2si_v2si
);
11322 def_builtin_const ("__builtin_vis_fslas32", CODE_FOR_vssashlv2si3
,
11323 SPARC_BUILTIN_FSLAS32
, v2si_ftype_v2si_v2si
);
11324 def_builtin_const ("__builtin_vis_fsrl32", CODE_FOR_vlshrv2si3
,
11325 SPARC_BUILTIN_FSRL32
, v2si_ftype_v2si_v2si
);
11326 def_builtin_const ("__builtin_vis_fsra32", CODE_FOR_vashrv2si3
,
11327 SPARC_BUILTIN_FSRA32
, v2si_ftype_v2si_v2si
);
11330 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistndi_vis
,
11331 SPARC_BUILTIN_PDISTN
, di_ftype_v8qi_v8qi
);
11333 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistnsi_vis
,
11334 SPARC_BUILTIN_PDISTN
, si_ftype_v8qi_v8qi
);
11336 def_builtin_const ("__builtin_vis_fmean16", CODE_FOR_fmean16_vis
,
11337 SPARC_BUILTIN_FMEAN16
, v4hi_ftype_v4hi_v4hi
);
11338 def_builtin_const ("__builtin_vis_fpadd64", CODE_FOR_fpadd64_vis
,
11339 SPARC_BUILTIN_FPADD64
, di_ftype_di_di
);
11340 def_builtin_const ("__builtin_vis_fpsub64", CODE_FOR_fpsub64_vis
,
11341 SPARC_BUILTIN_FPSUB64
, di_ftype_di_di
);
11343 def_builtin_const ("__builtin_vis_fpadds16", CODE_FOR_ssaddv4hi3
,
11344 SPARC_BUILTIN_FPADDS16
, v4hi_ftype_v4hi_v4hi
);
11345 def_builtin_const ("__builtin_vis_fpadds16s", CODE_FOR_ssaddv2hi3
,
11346 SPARC_BUILTIN_FPADDS16S
, v2hi_ftype_v2hi_v2hi
);
11347 def_builtin_const ("__builtin_vis_fpsubs16", CODE_FOR_sssubv4hi3
,
11348 SPARC_BUILTIN_FPSUBS16
, v4hi_ftype_v4hi_v4hi
);
11349 def_builtin_const ("__builtin_vis_fpsubs16s", CODE_FOR_sssubv2hi3
,
11350 SPARC_BUILTIN_FPSUBS16S
, v2hi_ftype_v2hi_v2hi
);
11351 def_builtin_const ("__builtin_vis_fpadds32", CODE_FOR_ssaddv2si3
,
11352 SPARC_BUILTIN_FPADDS32
, v2si_ftype_v2si_v2si
);
11353 def_builtin_const ("__builtin_vis_fpadds32s", CODE_FOR_ssaddv1si3
,
11354 SPARC_BUILTIN_FPADDS32S
, v1si_ftype_v1si_v1si
);
11355 def_builtin_const ("__builtin_vis_fpsubs32", CODE_FOR_sssubv2si3
,
11356 SPARC_BUILTIN_FPSUBS32
, v2si_ftype_v2si_v2si
);
11357 def_builtin_const ("__builtin_vis_fpsubs32s", CODE_FOR_sssubv1si3
,
11358 SPARC_BUILTIN_FPSUBS32S
, v1si_ftype_v1si_v1si
);
11362 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8di_vis
,
11363 SPARC_BUILTIN_FUCMPLE8
, di_ftype_v8qi_v8qi
);
11364 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8di_vis
,
11365 SPARC_BUILTIN_FUCMPNE8
, di_ftype_v8qi_v8qi
);
11366 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8di_vis
,
11367 SPARC_BUILTIN_FUCMPGT8
, di_ftype_v8qi_v8qi
);
11368 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8di_vis
,
11369 SPARC_BUILTIN_FUCMPEQ8
, di_ftype_v8qi_v8qi
);
11373 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8si_vis
,
11374 SPARC_BUILTIN_FUCMPLE8
, si_ftype_v8qi_v8qi
);
11375 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8si_vis
,
11376 SPARC_BUILTIN_FUCMPNE8
, si_ftype_v8qi_v8qi
);
11377 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8si_vis
,
11378 SPARC_BUILTIN_FUCMPGT8
, si_ftype_v8qi_v8qi
);
11379 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8si_vis
,
11380 SPARC_BUILTIN_FUCMPEQ8
, si_ftype_v8qi_v8qi
);
11383 def_builtin_const ("__builtin_vis_fhadds", CODE_FOR_fhaddsf_vis
,
11384 SPARC_BUILTIN_FHADDS
, sf_ftype_sf_sf
);
11385 def_builtin_const ("__builtin_vis_fhaddd", CODE_FOR_fhadddf_vis
,
11386 SPARC_BUILTIN_FHADDD
, df_ftype_df_df
);
11387 def_builtin_const ("__builtin_vis_fhsubs", CODE_FOR_fhsubsf_vis
,
11388 SPARC_BUILTIN_FHSUBS
, sf_ftype_sf_sf
);
11389 def_builtin_const ("__builtin_vis_fhsubd", CODE_FOR_fhsubdf_vis
,
11390 SPARC_BUILTIN_FHSUBD
, df_ftype_df_df
);
11391 def_builtin_const ("__builtin_vis_fnhadds", CODE_FOR_fnhaddsf_vis
,
11392 SPARC_BUILTIN_FNHADDS
, sf_ftype_sf_sf
);
11393 def_builtin_const ("__builtin_vis_fnhaddd", CODE_FOR_fnhadddf_vis
,
11394 SPARC_BUILTIN_FNHADDD
, df_ftype_df_df
);
11396 def_builtin_const ("__builtin_vis_umulxhi", CODE_FOR_umulxhi_vis
,
11397 SPARC_BUILTIN_UMULXHI
, di_ftype_di_di
);
11398 def_builtin_const ("__builtin_vis_xmulx", CODE_FOR_xmulx_vis
,
11399 SPARC_BUILTIN_XMULX
, di_ftype_di_di
);
11400 def_builtin_const ("__builtin_vis_xmulxhi", CODE_FOR_xmulxhi_vis
,
11401 SPARC_BUILTIN_XMULXHI
, di_ftype_di_di
);
11406 def_builtin_const ("__builtin_vis_fpadd8", CODE_FOR_addv8qi3
,
11407 SPARC_BUILTIN_FPADD8
, v8qi_ftype_v8qi_v8qi
);
11408 def_builtin_const ("__builtin_vis_fpadds8", CODE_FOR_ssaddv8qi3
,
11409 SPARC_BUILTIN_FPADDS8
, v8qi_ftype_v8qi_v8qi
);
11410 def_builtin_const ("__builtin_vis_fpaddus8", CODE_FOR_usaddv8qi3
,
11411 SPARC_BUILTIN_FPADDUS8
, v8qi_ftype_v8qi_v8qi
);
11412 def_builtin_const ("__builtin_vis_fpaddus16", CODE_FOR_usaddv4hi3
,
11413 SPARC_BUILTIN_FPADDUS16
, v4hi_ftype_v4hi_v4hi
);
11418 def_builtin_const ("__builtin_vis_fpcmple8", CODE_FOR_fpcmple8di_vis
,
11419 SPARC_BUILTIN_FPCMPLE8
, di_ftype_v8qi_v8qi
);
11420 def_builtin_const ("__builtin_vis_fpcmpgt8", CODE_FOR_fpcmpgt8di_vis
,
11421 SPARC_BUILTIN_FPCMPGT8
, di_ftype_v8qi_v8qi
);
11422 def_builtin_const ("__builtin_vis_fpcmpule16", CODE_FOR_fpcmpule16di_vis
,
11423 SPARC_BUILTIN_FPCMPULE16
, di_ftype_v4hi_v4hi
);
11424 def_builtin_const ("__builtin_vis_fpcmpugt16", CODE_FOR_fpcmpugt16di_vis
,
11425 SPARC_BUILTIN_FPCMPUGT16
, di_ftype_v4hi_v4hi
);
11426 def_builtin_const ("__builtin_vis_fpcmpule32", CODE_FOR_fpcmpule32di_vis
,
11427 SPARC_BUILTIN_FPCMPULE32
, di_ftype_v2si_v2si
);
11428 def_builtin_const ("__builtin_vis_fpcmpugt32", CODE_FOR_fpcmpugt32di_vis
,
11429 SPARC_BUILTIN_FPCMPUGT32
, di_ftype_v2si_v2si
);
11433 def_builtin_const ("__builtin_vis_fpcmple8", CODE_FOR_fpcmple8si_vis
,
11434 SPARC_BUILTIN_FPCMPLE8
, si_ftype_v8qi_v8qi
);
11435 def_builtin_const ("__builtin_vis_fpcmpgt8", CODE_FOR_fpcmpgt8si_vis
,
11436 SPARC_BUILTIN_FPCMPGT8
, si_ftype_v8qi_v8qi
);
11437 def_builtin_const ("__builtin_vis_fpcmpule16", CODE_FOR_fpcmpule16si_vis
,
11438 SPARC_BUILTIN_FPCMPULE16
, si_ftype_v4hi_v4hi
);
11439 def_builtin_const ("__builtin_vis_fpcmpugt16", CODE_FOR_fpcmpugt16si_vis
,
11440 SPARC_BUILTIN_FPCMPUGT16
, si_ftype_v4hi_v4hi
);
11441 def_builtin_const ("__builtin_vis_fpcmpule32", CODE_FOR_fpcmpule32si_vis
,
11442 SPARC_BUILTIN_FPCMPULE32
, di_ftype_v2si_v2si
);
11443 def_builtin_const ("__builtin_vis_fpcmpugt32", CODE_FOR_fpcmpugt32si_vis
,
11444 SPARC_BUILTIN_FPCMPUGT32
, di_ftype_v2si_v2si
);
11447 def_builtin_const ("__builtin_vis_fpmax8", CODE_FOR_maxv8qi3
,
11448 SPARC_BUILTIN_FPMAX8
, v8qi_ftype_v8qi_v8qi
);
11449 def_builtin_const ("__builtin_vis_fpmax16", CODE_FOR_maxv4hi3
,
11450 SPARC_BUILTIN_FPMAX16
, v4hi_ftype_v4hi_v4hi
);
11451 def_builtin_const ("__builtin_vis_fpmax32", CODE_FOR_maxv2si3
,
11452 SPARC_BUILTIN_FPMAX32
, v2si_ftype_v2si_v2si
);
11453 def_builtin_const ("__builtin_vis_fpmaxu8", CODE_FOR_maxuv8qi3
,
11454 SPARC_BUILTIN_FPMAXU8
, v8qi_ftype_v8qi_v8qi
);
11455 def_builtin_const ("__builtin_vis_fpmaxu16", CODE_FOR_maxuv4hi3
,
11456 SPARC_BUILTIN_FPMAXU16
, v4hi_ftype_v4hi_v4hi
);
11457 def_builtin_const ("__builtin_vis_fpmaxu32", CODE_FOR_maxuv2si3
,
11458 SPARC_BUILTIN_FPMAXU32
, v2si_ftype_v2si_v2si
);
11459 def_builtin_const ("__builtin_vis_fpmin8", CODE_FOR_minv8qi3
,
11460 SPARC_BUILTIN_FPMIN8
, v8qi_ftype_v8qi_v8qi
);
11461 def_builtin_const ("__builtin_vis_fpmin16", CODE_FOR_minv4hi3
,
11462 SPARC_BUILTIN_FPMIN16
, v4hi_ftype_v4hi_v4hi
);
11463 def_builtin_const ("__builtin_vis_fpmin32", CODE_FOR_minv2si3
,
11464 SPARC_BUILTIN_FPMIN32
, v2si_ftype_v2si_v2si
);
11465 def_builtin_const ("__builtin_vis_fpminu8", CODE_FOR_minuv8qi3
,
11466 SPARC_BUILTIN_FPMINU8
, v8qi_ftype_v8qi_v8qi
);
11467 def_builtin_const ("__builtin_vis_fpminu16", CODE_FOR_minuv4hi3
,
11468 SPARC_BUILTIN_FPMINU16
, v4hi_ftype_v4hi_v4hi
);
11469 def_builtin_const ("__builtin_vis_fpminu32", CODE_FOR_minuv2si3
,
11470 SPARC_BUILTIN_FPMINU32
, v2si_ftype_v2si_v2si
);
11471 def_builtin_const ("__builtin_vis_fpsub8", CODE_FOR_subv8qi3
,
11472 SPARC_BUILTIN_FPSUB8
, v8qi_ftype_v8qi_v8qi
);
11473 def_builtin_const ("__builtin_vis_fpsubs8", CODE_FOR_sssubv8qi3
,
11474 SPARC_BUILTIN_FPSUBS8
, v8qi_ftype_v8qi_v8qi
);
11475 def_builtin_const ("__builtin_vis_fpsubus8", CODE_FOR_ussubv8qi3
,
11476 SPARC_BUILTIN_FPSUBUS8
, v8qi_ftype_v8qi_v8qi
);
11477 def_builtin_const ("__builtin_vis_fpsubus16", CODE_FOR_ussubv4hi3
,
11478 SPARC_BUILTIN_FPSUBUS16
, v4hi_ftype_v4hi_v4hi
);
11483 def_builtin_const ("__builtin_vis_dictunpack8", CODE_FOR_dictunpack8
,
11484 SPARC_BUILTIN_DICTUNPACK8
, v8qi_ftype_df_si
);
11485 def_builtin_const ("__builtin_vis_dictunpack16", CODE_FOR_dictunpack16
,
11486 SPARC_BUILTIN_DICTUNPACK16
, v4hi_ftype_df_si
);
11487 def_builtin_const ("__builtin_vis_dictunpack32", CODE_FOR_dictunpack32
,
11488 SPARC_BUILTIN_DICTUNPACK32
, v2si_ftype_df_si
);
11492 tree di_ftype_v8qi_v8qi_si
= build_function_type_list (intDI_type_node
,
11494 intSI_type_node
, 0);
11495 tree di_ftype_v4hi_v4hi_si
= build_function_type_list (intDI_type_node
,
11497 intSI_type_node
, 0);
11498 tree di_ftype_v2si_v2si_si
= build_function_type_list (intDI_type_node
,
11500 intSI_type_node
, 0);
11502 def_builtin_const ("__builtin_vis_fpcmple8shl", CODE_FOR_fpcmple8dishl
,
11503 SPARC_BUILTIN_FPCMPLE8SHL
, di_ftype_v8qi_v8qi_si
);
11504 def_builtin_const ("__builtin_vis_fpcmpgt8shl", CODE_FOR_fpcmpgt8dishl
,
11505 SPARC_BUILTIN_FPCMPGT8SHL
, di_ftype_v8qi_v8qi_si
);
11506 def_builtin_const ("__builtin_vis_fpcmpeq8shl", CODE_FOR_fpcmpeq8dishl
,
11507 SPARC_BUILTIN_FPCMPEQ8SHL
, di_ftype_v8qi_v8qi_si
);
11508 def_builtin_const ("__builtin_vis_fpcmpne8shl", CODE_FOR_fpcmpne8dishl
,
11509 SPARC_BUILTIN_FPCMPNE8SHL
, di_ftype_v8qi_v8qi_si
);
11511 def_builtin_const ("__builtin_vis_fpcmple16shl", CODE_FOR_fpcmple16dishl
,
11512 SPARC_BUILTIN_FPCMPLE16SHL
, di_ftype_v4hi_v4hi_si
);
11513 def_builtin_const ("__builtin_vis_fpcmpgt16shl", CODE_FOR_fpcmpgt16dishl
,
11514 SPARC_BUILTIN_FPCMPGT16SHL
, di_ftype_v4hi_v4hi_si
);
11515 def_builtin_const ("__builtin_vis_fpcmpeq16shl", CODE_FOR_fpcmpeq16dishl
,
11516 SPARC_BUILTIN_FPCMPEQ16SHL
, di_ftype_v4hi_v4hi_si
);
11517 def_builtin_const ("__builtin_vis_fpcmpne16shl", CODE_FOR_fpcmpne16dishl
,
11518 SPARC_BUILTIN_FPCMPNE16SHL
, di_ftype_v4hi_v4hi_si
);
11520 def_builtin_const ("__builtin_vis_fpcmple32shl", CODE_FOR_fpcmple32dishl
,
11521 SPARC_BUILTIN_FPCMPLE32SHL
, di_ftype_v2si_v2si_si
);
11522 def_builtin_const ("__builtin_vis_fpcmpgt32shl", CODE_FOR_fpcmpgt32dishl
,
11523 SPARC_BUILTIN_FPCMPGT32SHL
, di_ftype_v2si_v2si_si
);
11524 def_builtin_const ("__builtin_vis_fpcmpeq32shl", CODE_FOR_fpcmpeq32dishl
,
11525 SPARC_BUILTIN_FPCMPEQ32SHL
, di_ftype_v2si_v2si_si
);
11526 def_builtin_const ("__builtin_vis_fpcmpne32shl", CODE_FOR_fpcmpne32dishl
,
11527 SPARC_BUILTIN_FPCMPNE32SHL
, di_ftype_v2si_v2si_si
);
11530 def_builtin_const ("__builtin_vis_fpcmpule8shl", CODE_FOR_fpcmpule8dishl
,
11531 SPARC_BUILTIN_FPCMPULE8SHL
, di_ftype_v8qi_v8qi_si
);
11532 def_builtin_const ("__builtin_vis_fpcmpugt8shl", CODE_FOR_fpcmpugt8dishl
,
11533 SPARC_BUILTIN_FPCMPUGT8SHL
, di_ftype_v8qi_v8qi_si
);
11535 def_builtin_const ("__builtin_vis_fpcmpule16shl", CODE_FOR_fpcmpule16dishl
,
11536 SPARC_BUILTIN_FPCMPULE16SHL
, di_ftype_v4hi_v4hi_si
);
11537 def_builtin_const ("__builtin_vis_fpcmpugt16shl", CODE_FOR_fpcmpugt16dishl
,
11538 SPARC_BUILTIN_FPCMPUGT16SHL
, di_ftype_v4hi_v4hi_si
);
11540 def_builtin_const ("__builtin_vis_fpcmpule32shl", CODE_FOR_fpcmpule32dishl
,
11541 SPARC_BUILTIN_FPCMPULE32SHL
, di_ftype_v2si_v2si_si
);
11542 def_builtin_const ("__builtin_vis_fpcmpugt32shl", CODE_FOR_fpcmpugt32dishl
,
11543 SPARC_BUILTIN_FPCMPUGT32SHL
, di_ftype_v2si_v2si_si
);
11545 def_builtin_const ("__builtin_vis_fpcmpde8shl", CODE_FOR_fpcmpde8dishl
,
11546 SPARC_BUILTIN_FPCMPDE8SHL
, di_ftype_v8qi_v8qi_si
);
11547 def_builtin_const ("__builtin_vis_fpcmpde16shl", CODE_FOR_fpcmpde16dishl
,
11548 SPARC_BUILTIN_FPCMPDE16SHL
, di_ftype_v4hi_v4hi_si
);
11549 def_builtin_const ("__builtin_vis_fpcmpde32shl", CODE_FOR_fpcmpde32dishl
,
11550 SPARC_BUILTIN_FPCMPDE32SHL
, di_ftype_v2si_v2si_si
);
11552 def_builtin_const ("__builtin_vis_fpcmpur8shl", CODE_FOR_fpcmpur8dishl
,
11553 SPARC_BUILTIN_FPCMPUR8SHL
, di_ftype_v8qi_v8qi_si
);
11554 def_builtin_const ("__builtin_vis_fpcmpur16shl", CODE_FOR_fpcmpur16dishl
,
11555 SPARC_BUILTIN_FPCMPUR16SHL
, di_ftype_v4hi_v4hi_si
);
11556 def_builtin_const ("__builtin_vis_fpcmpur32shl", CODE_FOR_fpcmpur32dishl
,
11557 SPARC_BUILTIN_FPCMPUR32SHL
, di_ftype_v2si_v2si_si
);
11562 tree si_ftype_v8qi_v8qi_si
= build_function_type_list (intSI_type_node
,
11564 intSI_type_node
, 0);
11565 tree si_ftype_v4hi_v4hi_si
= build_function_type_list (intSI_type_node
,
11567 intSI_type_node
, 0);
11568 tree si_ftype_v2si_v2si_si
= build_function_type_list (intSI_type_node
,
11570 intSI_type_node
, 0);
11572 def_builtin_const ("__builtin_vis_fpcmple8shl", CODE_FOR_fpcmple8sishl
,
11573 SPARC_BUILTIN_FPCMPLE8SHL
, si_ftype_v8qi_v8qi_si
);
11574 def_builtin_const ("__builtin_vis_fpcmpgt8shl", CODE_FOR_fpcmpgt8sishl
,
11575 SPARC_BUILTIN_FPCMPGT8SHL
, si_ftype_v8qi_v8qi_si
);
11576 def_builtin_const ("__builtin_vis_fpcmpeq8shl", CODE_FOR_fpcmpeq8sishl
,
11577 SPARC_BUILTIN_FPCMPEQ8SHL
, si_ftype_v8qi_v8qi_si
);
11578 def_builtin_const ("__builtin_vis_fpcmpne8shl", CODE_FOR_fpcmpne8sishl
,
11579 SPARC_BUILTIN_FPCMPNE8SHL
, si_ftype_v8qi_v8qi_si
);
11581 def_builtin_const ("__builtin_vis_fpcmple16shl", CODE_FOR_fpcmple16sishl
,
11582 SPARC_BUILTIN_FPCMPLE16SHL
, si_ftype_v4hi_v4hi_si
);
11583 def_builtin_const ("__builtin_vis_fpcmpgt16shl", CODE_FOR_fpcmpgt16sishl
,
11584 SPARC_BUILTIN_FPCMPGT16SHL
, si_ftype_v4hi_v4hi_si
);
11585 def_builtin_const ("__builtin_vis_fpcmpeq16shl", CODE_FOR_fpcmpeq16sishl
,
11586 SPARC_BUILTIN_FPCMPEQ16SHL
, si_ftype_v4hi_v4hi_si
);
11587 def_builtin_const ("__builtin_vis_fpcmpne16shl", CODE_FOR_fpcmpne16sishl
,
11588 SPARC_BUILTIN_FPCMPNE16SHL
, si_ftype_v4hi_v4hi_si
);
11590 def_builtin_const ("__builtin_vis_fpcmple32shl", CODE_FOR_fpcmple32sishl
,
11591 SPARC_BUILTIN_FPCMPLE32SHL
, si_ftype_v2si_v2si_si
);
11592 def_builtin_const ("__builtin_vis_fpcmpgt32shl", CODE_FOR_fpcmpgt32sishl
,
11593 SPARC_BUILTIN_FPCMPGT32SHL
, si_ftype_v2si_v2si_si
);
11594 def_builtin_const ("__builtin_vis_fpcmpeq32shl", CODE_FOR_fpcmpeq32sishl
,
11595 SPARC_BUILTIN_FPCMPEQ32SHL
, si_ftype_v2si_v2si_si
);
11596 def_builtin_const ("__builtin_vis_fpcmpne32shl", CODE_FOR_fpcmpne32sishl
,
11597 SPARC_BUILTIN_FPCMPNE32SHL
, si_ftype_v2si_v2si_si
);
11600 def_builtin_const ("__builtin_vis_fpcmpule8shl", CODE_FOR_fpcmpule8sishl
,
11601 SPARC_BUILTIN_FPCMPULE8SHL
, si_ftype_v8qi_v8qi_si
);
11602 def_builtin_const ("__builtin_vis_fpcmpugt8shl", CODE_FOR_fpcmpugt8sishl
,
11603 SPARC_BUILTIN_FPCMPUGT8SHL
, si_ftype_v8qi_v8qi_si
);
11605 def_builtin_const ("__builtin_vis_fpcmpule16shl", CODE_FOR_fpcmpule16sishl
,
11606 SPARC_BUILTIN_FPCMPULE16SHL
, si_ftype_v4hi_v4hi_si
);
11607 def_builtin_const ("__builtin_vis_fpcmpugt16shl", CODE_FOR_fpcmpugt16sishl
,
11608 SPARC_BUILTIN_FPCMPUGT16SHL
, si_ftype_v4hi_v4hi_si
);
11610 def_builtin_const ("__builtin_vis_fpcmpule32shl", CODE_FOR_fpcmpule32sishl
,
11611 SPARC_BUILTIN_FPCMPULE32SHL
, si_ftype_v2si_v2si_si
);
11612 def_builtin_const ("__builtin_vis_fpcmpugt32shl", CODE_FOR_fpcmpugt32sishl
,
11613 SPARC_BUILTIN_FPCMPUGT32SHL
, si_ftype_v2si_v2si_si
);
11615 def_builtin_const ("__builtin_vis_fpcmpde8shl", CODE_FOR_fpcmpde8sishl
,
11616 SPARC_BUILTIN_FPCMPDE8SHL
, si_ftype_v8qi_v8qi_si
);
11617 def_builtin_const ("__builtin_vis_fpcmpde16shl", CODE_FOR_fpcmpde16sishl
,
11618 SPARC_BUILTIN_FPCMPDE16SHL
, si_ftype_v4hi_v4hi_si
);
11619 def_builtin_const ("__builtin_vis_fpcmpde32shl", CODE_FOR_fpcmpde32sishl
,
11620 SPARC_BUILTIN_FPCMPDE32SHL
, si_ftype_v2si_v2si_si
);
11622 def_builtin_const ("__builtin_vis_fpcmpur8shl", CODE_FOR_fpcmpur8sishl
,
11623 SPARC_BUILTIN_FPCMPUR8SHL
, si_ftype_v8qi_v8qi_si
);
11624 def_builtin_const ("__builtin_vis_fpcmpur16shl", CODE_FOR_fpcmpur16sishl
,
11625 SPARC_BUILTIN_FPCMPUR16SHL
, si_ftype_v4hi_v4hi_si
);
11626 def_builtin_const ("__builtin_vis_fpcmpur32shl", CODE_FOR_fpcmpur32sishl
,
11627 SPARC_BUILTIN_FPCMPUR32SHL
, si_ftype_v2si_v2si_si
);
11632 /* Implement TARGET_BUILTIN_DECL hook. */
11635 sparc_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
11637 if (code
>= SPARC_BUILTIN_MAX
)
11638 return error_mark_node
;
11640 return sparc_builtins
[code
];
11643 /* Implemented TARGET_EXPAND_BUILTIN hook. */
11646 sparc_expand_builtin (tree exp
, rtx target
,
11647 rtx subtarget ATTRIBUTE_UNUSED
,
11648 machine_mode tmode ATTRIBUTE_UNUSED
,
11649 int ignore ATTRIBUTE_UNUSED
)
11651 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
11652 enum sparc_builtins code
= (enum sparc_builtins
) DECL_FUNCTION_CODE (fndecl
);
11653 enum insn_code icode
= sparc_builtins_icode
[code
];
11654 bool nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
11655 call_expr_arg_iterator iter
;
11662 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11664 || GET_MODE (target
) != tmode
11665 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11666 op
[0] = gen_reg_rtx (tmode
);
11673 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
11675 const struct insn_operand_data
*insn_op
;
11678 if (arg
== error_mark_node
)
11682 idx
= arg_count
- !nonvoid
;
11683 insn_op
= &insn_data
[icode
].operand
[idx
];
11684 op
[arg_count
] = expand_normal (arg
);
11686 /* Some of the builtins require constant arguments. We check
11688 if ((code
>= SPARC_BUILTIN_FIRST_FPCMPSHL
11689 && code
<= SPARC_BUILTIN_LAST_FPCMPSHL
11691 || (code
>= SPARC_BUILTIN_FIRST_DICTUNPACK
11692 && code
<= SPARC_BUILTIN_LAST_DICTUNPACK
11693 && arg_count
== 2))
11695 if (!check_constant_argument (icode
, idx
, op
[arg_count
]))
11699 if (code
== SPARC_BUILTIN_LDFSR
|| code
== SPARC_BUILTIN_STFSR
)
11701 if (!address_operand (op
[arg_count
], SImode
))
11703 op
[arg_count
] = convert_memory_address (Pmode
, op
[arg_count
]);
11704 op
[arg_count
] = copy_addr_to_reg (op
[arg_count
]);
11706 op
[arg_count
] = gen_rtx_MEM (SImode
, op
[arg_count
]);
11709 else if (insn_op
->mode
== V1DImode
11710 && GET_MODE (op
[arg_count
]) == DImode
)
11711 op
[arg_count
] = gen_lowpart (V1DImode
, op
[arg_count
]);
11713 else if (insn_op
->mode
== V1SImode
11714 && GET_MODE (op
[arg_count
]) == SImode
)
11715 op
[arg_count
] = gen_lowpart (V1SImode
, op
[arg_count
]);
11717 if (! (*insn_data
[icode
].operand
[idx
].predicate
) (op
[arg_count
],
11719 op
[arg_count
] = copy_to_mode_reg (insn_op
->mode
, op
[arg_count
]);
11725 pat
= GEN_FCN (icode
) (op
[0]);
11729 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
11731 pat
= GEN_FCN (icode
) (op
[1]);
11734 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
11737 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
11740 gcc_unreachable ();
11748 return (nonvoid
? op
[0] : const0_rtx
);
11751 /* Return the upper 16 bits of the 8x16 multiplication. */
11754 sparc_vis_mul8x16 (int e8
, int e16
)
11756 return (e8
* e16
+ 128) / 256;
11759 /* Multiply the VECTOR_CSTs CST0 and CST1 as specified by FNCODE and put
11760 the result into the array N_ELTS, whose elements are of INNER_TYPE. */
11763 sparc_handle_vis_mul8x16 (vec
<tree
> *n_elts
, enum sparc_builtins fncode
,
11764 tree inner_type
, tree cst0
, tree cst1
)
11766 unsigned i
, num
= VECTOR_CST_NELTS (cst0
);
11771 case SPARC_BUILTIN_FMUL8X16
:
11772 for (i
= 0; i
< num
; ++i
)
11775 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
11776 TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, i
)));
11777 n_elts
->quick_push (build_int_cst (inner_type
, val
));
11781 case SPARC_BUILTIN_FMUL8X16AU
:
11782 scale
= TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, 0));
11784 for (i
= 0; i
< num
; ++i
)
11787 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
11789 n_elts
->quick_push (build_int_cst (inner_type
, val
));
11793 case SPARC_BUILTIN_FMUL8X16AL
:
11794 scale
= TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, 1));
11796 for (i
= 0; i
< num
; ++i
)
11799 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
11801 n_elts
->quick_push (build_int_cst (inner_type
, val
));
11806 gcc_unreachable ();
11810 /* Implement TARGET_FOLD_BUILTIN hook.
11812 Fold builtin functions for SPARC intrinsics. If IGNORE is true the
11813 result of the function call is ignored. NULL_TREE is returned if the
11814 function could not be folded. */
11817 sparc_fold_builtin (tree fndecl
, int n_args ATTRIBUTE_UNUSED
,
11818 tree
*args
, bool ignore
)
11820 enum sparc_builtins code
= (enum sparc_builtins
) DECL_FUNCTION_CODE (fndecl
);
11821 tree rtype
= TREE_TYPE (TREE_TYPE (fndecl
));
11822 tree arg0
, arg1
, arg2
;
11827 case SPARC_BUILTIN_LDFSR
:
11828 case SPARC_BUILTIN_STFSR
:
11829 case SPARC_BUILTIN_ALIGNADDR
:
11830 case SPARC_BUILTIN_WRGSR
:
11831 case SPARC_BUILTIN_BMASK
:
11832 case SPARC_BUILTIN_CMASK8
:
11833 case SPARC_BUILTIN_CMASK16
:
11834 case SPARC_BUILTIN_CMASK32
:
11838 return build_zero_cst (rtype
);
11843 case SPARC_BUILTIN_FEXPAND
:
11847 if (TREE_CODE (arg0
) == VECTOR_CST
)
11849 tree inner_type
= TREE_TYPE (rtype
);
11852 tree_vector_builder
n_elts (rtype
, VECTOR_CST_NELTS (arg0
), 1);
11853 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
11855 unsigned HOST_WIDE_INT val
11856 = TREE_INT_CST_LOW (VECTOR_CST_ELT (arg0
, i
));
11857 n_elts
.quick_push (build_int_cst (inner_type
, val
<< 4));
11859 return n_elts
.build ();
11863 case SPARC_BUILTIN_FMUL8X16
:
11864 case SPARC_BUILTIN_FMUL8X16AU
:
11865 case SPARC_BUILTIN_FMUL8X16AL
:
11871 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
11873 tree inner_type
= TREE_TYPE (rtype
);
11874 tree_vector_builder
n_elts (rtype
, VECTOR_CST_NELTS (arg0
), 1);
11875 sparc_handle_vis_mul8x16 (&n_elts
, code
, inner_type
, arg0
, arg1
);
11876 return n_elts
.build ();
11880 case SPARC_BUILTIN_FPMERGE
:
11886 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
11888 tree_vector_builder
n_elts (rtype
, 2 * VECTOR_CST_NELTS (arg0
), 1);
11890 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
11892 n_elts
.quick_push (VECTOR_CST_ELT (arg0
, i
));
11893 n_elts
.quick_push (VECTOR_CST_ELT (arg1
, i
));
11896 return n_elts
.build ();
11900 case SPARC_BUILTIN_PDIST
:
11901 case SPARC_BUILTIN_PDISTN
:
11906 if (code
== SPARC_BUILTIN_PDIST
)
11912 arg2
= integer_zero_node
;
11914 if (TREE_CODE (arg0
) == VECTOR_CST
11915 && TREE_CODE (arg1
) == VECTOR_CST
11916 && TREE_CODE (arg2
) == INTEGER_CST
)
11918 bool overflow
= false;
11919 widest_int result
= wi::to_widest (arg2
);
11923 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
11925 tree e0
= VECTOR_CST_ELT (arg0
, i
);
11926 tree e1
= VECTOR_CST_ELT (arg1
, i
);
11928 wi::overflow_type neg1_ovf
, neg2_ovf
, add1_ovf
, add2_ovf
;
11930 tmp
= wi::neg (wi::to_widest (e1
), &neg1_ovf
);
11931 tmp
= wi::add (wi::to_widest (e0
), tmp
, SIGNED
, &add1_ovf
);
11932 if (wi::neg_p (tmp
))
11933 tmp
= wi::neg (tmp
, &neg2_ovf
);
11935 neg2_ovf
= wi::OVF_NONE
;
11936 result
= wi::add (result
, tmp
, SIGNED
, &add2_ovf
);
11937 overflow
|= ((neg1_ovf
!= wi::OVF_NONE
)
11938 | (neg2_ovf
!= wi::OVF_NONE
)
11939 | (add1_ovf
!= wi::OVF_NONE
)
11940 | (add2_ovf
!= wi::OVF_NONE
));
11943 gcc_assert (!overflow
);
11945 return wide_int_to_tree (rtype
, result
);
11955 /* ??? This duplicates information provided to the compiler by the
11956 ??? scheduler description. Some day, teach genautomata to output
11957 ??? the latencies and then CSE will just use that. */
11960 sparc_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
11961 int opno ATTRIBUTE_UNUSED
,
11962 int *total
, bool speed ATTRIBUTE_UNUSED
)
11964 int code
= GET_CODE (x
);
11965 bool float_mode_p
= FLOAT_MODE_P (mode
);
11976 case CONST_WIDE_INT
:
11978 if (!SPARC_SIMM13_P (CONST_WIDE_INT_ELT (x
, 0)))
11980 if (!SPARC_SIMM13_P (CONST_WIDE_INT_ELT (x
, 1)))
11999 /* If outer-code was a sign or zero extension, a cost
12000 of COSTS_N_INSNS (1) was already added in. This is
12001 why we are subtracting it back out. */
12002 if (outer_code
== ZERO_EXTEND
)
12004 *total
= sparc_costs
->int_zload
- COSTS_N_INSNS (1);
12006 else if (outer_code
== SIGN_EXTEND
)
12008 *total
= sparc_costs
->int_sload
- COSTS_N_INSNS (1);
12010 else if (float_mode_p
)
12012 *total
= sparc_costs
->float_load
;
12016 *total
= sparc_costs
->int_load
;
12024 *total
= sparc_costs
->float_plusminus
;
12026 *total
= COSTS_N_INSNS (1);
12033 gcc_assert (float_mode_p
);
12034 *total
= sparc_costs
->float_mul
;
12037 if (GET_CODE (sub
) == NEG
)
12038 sub
= XEXP (sub
, 0);
12039 *total
+= rtx_cost (sub
, mode
, FMA
, 0, speed
);
12042 if (GET_CODE (sub
) == NEG
)
12043 sub
= XEXP (sub
, 0);
12044 *total
+= rtx_cost (sub
, mode
, FMA
, 2, speed
);
12050 *total
= sparc_costs
->float_mul
;
12051 else if (TARGET_ARCH32
&& !TARGET_HARD_MUL
)
12052 *total
= COSTS_N_INSNS (25);
12058 if (sparc_costs
->int_mul_bit_factor
)
12062 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
12064 unsigned HOST_WIDE_INT value
= INTVAL (XEXP (x
, 1));
12065 for (nbits
= 0; value
!= 0; value
&= value
- 1)
12073 bit_cost
= (nbits
- 3) / sparc_costs
->int_mul_bit_factor
;
12074 bit_cost
= COSTS_N_INSNS (bit_cost
);
12077 if (mode
== DImode
|| !TARGET_HARD_MUL
)
12078 *total
= sparc_costs
->int_mulX
+ bit_cost
;
12080 *total
= sparc_costs
->int_mul
+ bit_cost
;
12087 *total
= COSTS_N_INSNS (1) + sparc_costs
->shift_penalty
;
12096 if (mode
== DFmode
)
12097 *total
= sparc_costs
->float_div_df
;
12099 *total
= sparc_costs
->float_div_sf
;
12103 if (mode
== DImode
)
12104 *total
= sparc_costs
->int_divX
;
12106 *total
= sparc_costs
->int_div
;
12111 if (! float_mode_p
)
12113 *total
= COSTS_N_INSNS (1);
12120 case UNSIGNED_FLOAT
:
12124 case FLOAT_TRUNCATE
:
12125 *total
= sparc_costs
->float_move
;
12129 if (mode
== DFmode
)
12130 *total
= sparc_costs
->float_sqrt_df
;
12132 *total
= sparc_costs
->float_sqrt_sf
;
12137 *total
= sparc_costs
->float_cmp
;
12139 *total
= COSTS_N_INSNS (1);
12144 *total
= sparc_costs
->float_cmove
;
12146 *total
= sparc_costs
->int_cmove
;
12150 /* Handle the NAND vector patterns. */
12151 if (sparc_vector_mode_supported_p (mode
)
12152 && GET_CODE (XEXP (x
, 0)) == NOT
12153 && GET_CODE (XEXP (x
, 1)) == NOT
)
12155 *total
= COSTS_N_INSNS (1);
12166 /* Return true if CLASS is either GENERAL_REGS or I64_REGS. */
12169 general_or_i64_p (reg_class_t rclass
)
12171 return (rclass
== GENERAL_REGS
|| rclass
== I64_REGS
);
12174 /* Implement TARGET_REGISTER_MOVE_COST. */
12177 sparc_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
12178 reg_class_t from
, reg_class_t to
)
12180 bool need_memory
= false;
12182 /* This helps postreload CSE to eliminate redundant comparisons. */
12183 if (from
== NO_REGS
|| to
== NO_REGS
)
12186 if (from
== FPCC_REGS
|| to
== FPCC_REGS
)
12187 need_memory
= true;
12188 else if ((FP_REG_CLASS_P (from
) && general_or_i64_p (to
))
12189 || (general_or_i64_p (from
) && FP_REG_CLASS_P (to
)))
12193 int size
= GET_MODE_SIZE (mode
);
12194 if (size
== 8 || size
== 4)
12196 if (! TARGET_ARCH32
|| size
== 4)
12202 need_memory
= true;
12207 if (sparc_cpu
== PROCESSOR_ULTRASPARC
12208 || sparc_cpu
== PROCESSOR_ULTRASPARC3
12209 || sparc_cpu
== PROCESSOR_NIAGARA
12210 || sparc_cpu
== PROCESSOR_NIAGARA2
12211 || sparc_cpu
== PROCESSOR_NIAGARA3
12212 || sparc_cpu
== PROCESSOR_NIAGARA4
12213 || sparc_cpu
== PROCESSOR_NIAGARA7
12214 || sparc_cpu
== PROCESSOR_M8
)
12223 /* Emit the sequence of insns SEQ while preserving the registers REG and REG2.
12224 This is achieved by means of a manual dynamic stack space allocation in
12225 the current frame. We make the assumption that SEQ doesn't contain any
12226 function calls, with the possible exception of calls to the GOT helper. */
12229 emit_and_preserve (rtx seq
, rtx reg
, rtx reg2
)
12231 /* We must preserve the lowest 16 words for the register save area. */
12232 HOST_WIDE_INT offset
= 16*UNITS_PER_WORD
;
12233 /* We really need only 2 words of fresh stack space. */
12234 HOST_WIDE_INT size
= SPARC_STACK_ALIGN (offset
+ 2*UNITS_PER_WORD
);
12237 = gen_rtx_MEM (word_mode
, plus_constant (Pmode
, stack_pointer_rtx
,
12238 SPARC_STACK_BIAS
+ offset
));
12240 emit_insn (gen_stack_pointer_inc (GEN_INT (-size
)));
12241 emit_insn (gen_rtx_SET (slot
, reg
));
12243 emit_insn (gen_rtx_SET (adjust_address (slot
, word_mode
, UNITS_PER_WORD
),
12247 emit_insn (gen_rtx_SET (reg2
,
12248 adjust_address (slot
, word_mode
, UNITS_PER_WORD
)));
12249 emit_insn (gen_rtx_SET (reg
, slot
));
12250 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
12253 /* Output the assembler code for a thunk function. THUNK_DECL is the
12254 declaration for the thunk function itself, FUNCTION is the decl for
12255 the target function. DELTA is an immediate constant offset to be
12256 added to THIS. If VCALL_OFFSET is nonzero, the word at address
12257 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
12260 sparc_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
12261 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
12264 rtx this_rtx
, funexp
;
12266 unsigned int int_arg_first
;
12268 reload_completed
= 1;
12269 epilogue_completed
= 1;
12271 emit_note (NOTE_INSN_PROLOGUE_END
);
12275 sparc_leaf_function_p
= 1;
12277 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
12279 else if (flag_delayed_branch
)
12281 /* We will emit a regular sibcall below, so we need to instruct
12282 output_sibcall that we are in a leaf function. */
12283 sparc_leaf_function_p
= crtl
->uses_only_leaf_regs
= 1;
12285 /* This will cause final.c to invoke leaf_renumber_regs so we
12286 must behave as if we were in a not-yet-leafified function. */
12287 int_arg_first
= SPARC_INCOMING_INT_ARG_FIRST
;
12291 /* We will emit the sibcall manually below, so we will need to
12292 manually spill non-leaf registers. */
12293 sparc_leaf_function_p
= crtl
->uses_only_leaf_regs
= 0;
12295 /* We really are in a leaf function. */
12296 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
12299 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
12300 returns a structure, the structure return pointer is there instead. */
12302 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
12303 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
+ 1);
12305 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
);
12307 /* Add DELTA. When possible use a plain add, otherwise load it into
12308 a register first. */
12311 rtx delta_rtx
= GEN_INT (delta
);
12313 if (! SPARC_SIMM13_P (delta
))
12315 rtx scratch
= gen_rtx_REG (Pmode
, 1);
12316 emit_move_insn (scratch
, delta_rtx
);
12317 delta_rtx
= scratch
;
12320 /* THIS_RTX += DELTA. */
12321 emit_insn (gen_add2_insn (this_rtx
, delta_rtx
));
12324 /* Add the word at address (*THIS_RTX + VCALL_OFFSET). */
12327 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
12328 rtx scratch
= gen_rtx_REG (Pmode
, 1);
12330 gcc_assert (vcall_offset
< 0);
12332 /* SCRATCH = *THIS_RTX. */
12333 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
, this_rtx
));
12335 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
12336 may not have any available scratch register at this point. */
12337 if (SPARC_SIMM13_P (vcall_offset
))
12339 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
12340 else if (! fixed_regs
[5]
12341 /* The below sequence is made up of at least 2 insns,
12342 while the default method may need only one. */
12343 && vcall_offset
< -8192)
12345 rtx scratch2
= gen_rtx_REG (Pmode
, 5);
12346 emit_move_insn (scratch2
, vcall_offset_rtx
);
12347 vcall_offset_rtx
= scratch2
;
12351 rtx increment
= GEN_INT (-4096);
12353 /* VCALL_OFFSET is a negative number whose typical range can be
12354 estimated as -32768..0 in 32-bit mode. In almost all cases
12355 it is therefore cheaper to emit multiple add insns than
12356 spilling and loading the constant into a register (at least
12358 while (! SPARC_SIMM13_P (vcall_offset
))
12360 emit_insn (gen_add2_insn (scratch
, increment
));
12361 vcall_offset
+= 4096;
12363 vcall_offset_rtx
= GEN_INT (vcall_offset
); /* cannot be 0 */
12366 /* SCRATCH = *(*THIS_RTX + VCALL_OFFSET). */
12367 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
,
12368 gen_rtx_PLUS (Pmode
,
12370 vcall_offset_rtx
)));
12372 /* THIS_RTX += *(*THIS_RTX + VCALL_OFFSET). */
12373 emit_insn (gen_add2_insn (this_rtx
, scratch
));
12376 /* Generate a tail call to the target function. */
12377 if (! TREE_USED (function
))
12379 assemble_external (function
);
12380 TREE_USED (function
) = 1;
12382 funexp
= XEXP (DECL_RTL (function
), 0);
12384 if (flag_delayed_branch
)
12386 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
12387 insn
= emit_call_insn (gen_sibcall (funexp
));
12388 SIBLING_CALL_P (insn
) = 1;
12392 /* The hoops we have to jump through in order to generate a sibcall
12393 without using delay slots... */
12394 rtx spill_reg
, seq
, scratch
= gen_rtx_REG (Pmode
, 1);
12398 spill_reg
= gen_rtx_REG (word_mode
, 15); /* %o7 */
12400 load_got_register (); /* clobbers %o7 */
12401 if (!TARGET_VXWORKS_RTP
)
12402 pic_offset_table_rtx
= global_offset_table_rtx
;
12403 scratch
= sparc_legitimize_pic_address (funexp
, scratch
);
12404 seq
= get_insns ();
12406 emit_and_preserve (seq
, spill_reg
, pic_offset_table_rtx
);
12408 else if (TARGET_ARCH32
)
12410 emit_insn (gen_rtx_SET (scratch
,
12411 gen_rtx_HIGH (SImode
, funexp
)));
12412 emit_insn (gen_rtx_SET (scratch
,
12413 gen_rtx_LO_SUM (SImode
, scratch
, funexp
)));
12415 else /* TARGET_ARCH64 */
12417 switch (sparc_cmodel
)
12421 /* The destination can serve as a temporary. */
12422 sparc_emit_set_symbolic_const64 (scratch
, funexp
, scratch
);
12427 /* The destination cannot serve as a temporary. */
12428 spill_reg
= gen_rtx_REG (DImode
, 15); /* %o7 */
12430 sparc_emit_set_symbolic_const64 (scratch
, funexp
, spill_reg
);
12431 seq
= get_insns ();
12433 emit_and_preserve (seq
, spill_reg
, 0);
12437 gcc_unreachable ();
12441 emit_jump_insn (gen_indirect_jump (scratch
));
12446 /* Run just enough of rest_of_compilation to get the insns emitted.
12447 There's not really enough bulk here to make other passes such as
12448 instruction scheduling worth while. Note that use_thunk calls
12449 assemble_start_function and assemble_end_function. */
12450 insn
= get_insns ();
12451 shorten_branches (insn
);
12452 final_start_function (insn
, file
, 1);
12453 final (insn
, file
, 1);
12454 final_end_function ();
12456 reload_completed
= 0;
12457 epilogue_completed
= 0;
12460 /* Return true if sparc_output_mi_thunk would be able to output the
12461 assembler code for the thunk function specified by the arguments
12462 it is passed, and false otherwise. */
12464 sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED
,
12465 HOST_WIDE_INT delta ATTRIBUTE_UNUSED
,
12466 HOST_WIDE_INT vcall_offset
,
12467 const_tree function ATTRIBUTE_UNUSED
)
12469 /* Bound the loop used in the default method above. */
12470 return (vcall_offset
>= -32768 || ! fixed_regs
[5]);
12473 /* How to allocate a 'struct machine_function'. */
12475 static struct machine_function
*
12476 sparc_init_machine_status (void)
12478 return ggc_cleared_alloc
<machine_function
> ();
12481 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
12483 static unsigned HOST_WIDE_INT
12484 sparc_asan_shadow_offset (void)
12486 return TARGET_ARCH64
? HOST_WIDE_INT_C (0x7fff8000) : (HOST_WIDE_INT_1
<< 29);
12489 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
12490 We need to emit DTP-relative relocations. */
12493 sparc_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
12498 fputs ("\t.word\t%r_tls_dtpoff32(", file
);
12501 fputs ("\t.xword\t%r_tls_dtpoff64(", file
);
12504 gcc_unreachable ();
12506 output_addr_const (file
, x
);
12510 /* Do whatever processing is required at the end of a file. */
12513 sparc_file_end (void)
12515 /* If we need to emit the special GOT helper function, do so now. */
12516 if (got_helper_rtx
)
12518 const char *name
= XSTR (got_helper_rtx
, 0);
12519 const char *reg_name
= reg_names
[GLOBAL_OFFSET_TABLE_REGNUM
];
12520 #ifdef DWARF2_UNWIND_INFO
12524 if (USE_HIDDEN_LINKONCE
)
12526 tree decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
12527 get_identifier (name
),
12528 build_function_type_list (void_type_node
,
12530 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
12531 NULL_TREE
, void_type_node
);
12532 TREE_PUBLIC (decl
) = 1;
12533 TREE_STATIC (decl
) = 1;
12534 make_decl_one_only (decl
, DECL_ASSEMBLER_NAME (decl
));
12535 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
12536 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
12537 resolve_unique_section (decl
, 0, flag_function_sections
);
12538 allocate_struct_function (decl
, true);
12539 cfun
->is_thunk
= 1;
12540 current_function_decl
= decl
;
12541 init_varasm_status ();
12542 assemble_start_function (decl
, name
);
12546 const int align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
12547 switch_to_section (text_section
);
12549 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
12550 ASM_OUTPUT_LABEL (asm_out_file
, name
);
12553 #ifdef DWARF2_UNWIND_INFO
12554 do_cfi
= dwarf2out_do_cfi_asm ();
12556 fprintf (asm_out_file
, "\t.cfi_startproc\n");
12558 if (flag_delayed_branch
)
12559 fprintf (asm_out_file
, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
12560 reg_name
, reg_name
);
12562 fprintf (asm_out_file
, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
12563 reg_name
, reg_name
);
12564 #ifdef DWARF2_UNWIND_INFO
12566 fprintf (asm_out_file
, "\t.cfi_endproc\n");
12570 if (NEED_INDICATE_EXEC_STACK
)
12571 file_end_indicate_exec_stack ();
12573 #ifdef TARGET_SOLARIS
12574 solaris_file_end ();
12578 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
12579 /* Implement TARGET_MANGLE_TYPE. */
12581 static const char *
12582 sparc_mangle_type (const_tree type
)
12585 && TYPE_MAIN_VARIANT (type
) == long_double_type_node
12586 && TARGET_LONG_DOUBLE_128
)
12589 /* For all other types, use normal C++ mangling. */
12594 /* Expand a membar instruction for various use cases. Both the LOAD_STORE
12595 and BEFORE_AFTER arguments of the form X_Y. They are two-bit masks where
12596 bit 0 indicates that X is true, and bit 1 indicates Y is true. */
12599 sparc_emit_membar_for_model (enum memmodel model
,
12600 int load_store
, int before_after
)
12602 /* Bits for the MEMBAR mmask field. */
12603 const int LoadLoad
= 1;
12604 const int StoreLoad
= 2;
12605 const int LoadStore
= 4;
12606 const int StoreStore
= 8;
12608 int mm
= 0, implied
= 0;
12610 switch (sparc_memory_model
)
12613 /* Sequential Consistency. All memory transactions are immediately
12614 visible in sequential execution order. No barriers needed. */
12615 implied
= LoadLoad
| StoreLoad
| LoadStore
| StoreStore
;
12619 /* Total Store Ordering: all memory transactions with store semantics
12620 are followed by an implied StoreStore. */
12621 implied
|= StoreStore
;
12623 /* If we're not looking for a raw barrer (before+after), then atomic
12624 operations get the benefit of being both load and store. */
12625 if (load_store
== 3 && before_after
== 1)
12626 implied
|= StoreLoad
;
12630 /* Partial Store Ordering: all memory transactions with load semantics
12631 are followed by an implied LoadLoad | LoadStore. */
12632 implied
|= LoadLoad
| LoadStore
;
12634 /* If we're not looking for a raw barrer (before+after), then atomic
12635 operations get the benefit of being both load and store. */
12636 if (load_store
== 3 && before_after
== 2)
12637 implied
|= StoreLoad
| StoreStore
;
12641 /* Relaxed Memory Ordering: no implicit bits. */
12645 gcc_unreachable ();
12648 if (before_after
& 1)
12650 if (is_mm_release (model
) || is_mm_acq_rel (model
)
12651 || is_mm_seq_cst (model
))
12653 if (load_store
& 1)
12654 mm
|= LoadLoad
| StoreLoad
;
12655 if (load_store
& 2)
12656 mm
|= LoadStore
| StoreStore
;
12659 if (before_after
& 2)
12661 if (is_mm_acquire (model
) || is_mm_acq_rel (model
)
12662 || is_mm_seq_cst (model
))
12664 if (load_store
& 1)
12665 mm
|= LoadLoad
| LoadStore
;
12666 if (load_store
& 2)
12667 mm
|= StoreLoad
| StoreStore
;
12671 /* Remove the bits implied by the system memory model. */
12674 /* For raw barriers (before+after), always emit a barrier.
12675 This will become a compile-time barrier if needed. */
12676 if (mm
|| before_after
== 3)
12677 emit_insn (gen_membar (GEN_INT (mm
)));
12680 /* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit
12681 compare and swap on the word containing the byte or half-word. */
12684 sparc_expand_compare_and_swap_12 (rtx bool_result
, rtx result
, rtx mem
,
12685 rtx oldval
, rtx newval
)
12687 rtx addr1
= force_reg (Pmode
, XEXP (mem
, 0));
12688 rtx addr
= gen_reg_rtx (Pmode
);
12689 rtx off
= gen_reg_rtx (SImode
);
12690 rtx oldv
= gen_reg_rtx (SImode
);
12691 rtx newv
= gen_reg_rtx (SImode
);
12692 rtx oldvalue
= gen_reg_rtx (SImode
);
12693 rtx newvalue
= gen_reg_rtx (SImode
);
12694 rtx res
= gen_reg_rtx (SImode
);
12695 rtx resv
= gen_reg_rtx (SImode
);
12696 rtx memsi
, val
, mask
, cc
;
12698 emit_insn (gen_rtx_SET (addr
, gen_rtx_AND (Pmode
, addr1
, GEN_INT (-4))));
12700 if (Pmode
!= SImode
)
12701 addr1
= gen_lowpart (SImode
, addr1
);
12702 emit_insn (gen_rtx_SET (off
, gen_rtx_AND (SImode
, addr1
, GEN_INT (3))));
12704 memsi
= gen_rtx_MEM (SImode
, addr
);
12705 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
12706 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
12708 val
= copy_to_reg (memsi
);
12710 emit_insn (gen_rtx_SET (off
,
12711 gen_rtx_XOR (SImode
, off
,
12712 GEN_INT (GET_MODE (mem
) == QImode
12715 emit_insn (gen_rtx_SET (off
, gen_rtx_ASHIFT (SImode
, off
, GEN_INT (3))));
12717 if (GET_MODE (mem
) == QImode
)
12718 mask
= force_reg (SImode
, GEN_INT (0xff));
12720 mask
= force_reg (SImode
, GEN_INT (0xffff));
12722 emit_insn (gen_rtx_SET (mask
, gen_rtx_ASHIFT (SImode
, mask
, off
)));
12724 emit_insn (gen_rtx_SET (val
,
12725 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
12728 oldval
= gen_lowpart (SImode
, oldval
);
12729 emit_insn (gen_rtx_SET (oldv
, gen_rtx_ASHIFT (SImode
, oldval
, off
)));
12731 newval
= gen_lowpart_common (SImode
, newval
);
12732 emit_insn (gen_rtx_SET (newv
, gen_rtx_ASHIFT (SImode
, newval
, off
)));
12734 emit_insn (gen_rtx_SET (oldv
, gen_rtx_AND (SImode
, oldv
, mask
)));
12736 emit_insn (gen_rtx_SET (newv
, gen_rtx_AND (SImode
, newv
, mask
)));
12738 rtx_code_label
*end_label
= gen_label_rtx ();
12739 rtx_code_label
*loop_label
= gen_label_rtx ();
12740 emit_label (loop_label
);
12742 emit_insn (gen_rtx_SET (oldvalue
, gen_rtx_IOR (SImode
, oldv
, val
)));
12744 emit_insn (gen_rtx_SET (newvalue
, gen_rtx_IOR (SImode
, newv
, val
)));
12746 emit_move_insn (bool_result
, const1_rtx
);
12748 emit_insn (gen_atomic_compare_and_swapsi_1 (res
, memsi
, oldvalue
, newvalue
));
12750 emit_cmp_and_jump_insns (res
, oldvalue
, EQ
, NULL
, SImode
, 0, end_label
);
12752 emit_insn (gen_rtx_SET (resv
,
12753 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
12756 emit_move_insn (bool_result
, const0_rtx
);
12758 cc
= gen_compare_reg_1 (NE
, resv
, val
);
12759 emit_insn (gen_rtx_SET (val
, resv
));
12761 /* Use cbranchcc4 to separate the compare and branch! */
12762 emit_jump_insn (gen_cbranchcc4 (gen_rtx_NE (VOIDmode
, cc
, const0_rtx
),
12763 cc
, const0_rtx
, loop_label
));
12765 emit_label (end_label
);
12767 emit_insn (gen_rtx_SET (res
, gen_rtx_AND (SImode
, res
, mask
)));
12769 emit_insn (gen_rtx_SET (res
, gen_rtx_LSHIFTRT (SImode
, res
, off
)));
12771 emit_move_insn (result
, gen_lowpart (GET_MODE (result
), res
));
12774 /* Expand code to perform a compare-and-swap. */
12777 sparc_expand_compare_and_swap (rtx operands
[])
12779 rtx bval
, retval
, mem
, oldval
, newval
;
12781 enum memmodel model
;
12783 bval
= operands
[0];
12784 retval
= operands
[1];
12786 oldval
= operands
[3];
12787 newval
= operands
[4];
12788 model
= (enum memmodel
) INTVAL (operands
[6]);
12789 mode
= GET_MODE (mem
);
12791 sparc_emit_membar_for_model (model
, 3, 1);
12793 if (reg_overlap_mentioned_p (retval
, oldval
))
12794 oldval
= copy_to_reg (oldval
);
12796 if (mode
== QImode
|| mode
== HImode
)
12797 sparc_expand_compare_and_swap_12 (bval
, retval
, mem
, oldval
, newval
);
12800 rtx (*gen
) (rtx
, rtx
, rtx
, rtx
);
12803 if (mode
== SImode
)
12804 gen
= gen_atomic_compare_and_swapsi_1
;
12806 gen
= gen_atomic_compare_and_swapdi_1
;
12807 emit_insn (gen (retval
, mem
, oldval
, newval
));
12809 x
= emit_store_flag (bval
, EQ
, retval
, oldval
, mode
, 1, 1);
12811 convert_move (bval
, x
, 1);
12814 sparc_emit_membar_for_model (model
, 3, 2);
12818 sparc_expand_vec_perm_bmask (machine_mode vmode
, rtx sel
)
12822 sel
= gen_lowpart (DImode
, sel
);
12826 /* inp = xxxxxxxAxxxxxxxB */
12827 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
12828 NULL_RTX
, 1, OPTAB_DIRECT
);
12829 /* t_1 = ....xxxxxxxAxxx. */
12830 sel
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, sel
),
12831 GEN_INT (3), NULL_RTX
, 1, OPTAB_DIRECT
);
12832 t_1
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_1
),
12833 GEN_INT (0x30000), NULL_RTX
, 1, OPTAB_DIRECT
);
12834 /* sel = .......B */
12835 /* t_1 = ...A.... */
12836 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_1
, sel
, 1, OPTAB_DIRECT
);
12837 /* sel = ...A...B */
12838 sel
= expand_mult (SImode
, sel
, GEN_INT (0x4444), sel
, 1);
12839 /* sel = AAAABBBB * 4 */
12840 t_1
= force_reg (SImode
, GEN_INT (0x01230123));
12841 /* sel = { A*4, A*4+1, A*4+2, ... } */
12845 /* inp = xxxAxxxBxxxCxxxD */
12846 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (8),
12847 NULL_RTX
, 1, OPTAB_DIRECT
);
12848 t_2
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
12849 NULL_RTX
, 1, OPTAB_DIRECT
);
12850 t_3
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (24),
12851 NULL_RTX
, 1, OPTAB_DIRECT
);
12852 /* t_1 = ..xxxAxxxBxxxCxx */
12853 /* t_2 = ....xxxAxxxBxxxC */
12854 /* t_3 = ......xxxAxxxBxx */
12855 sel
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, sel
),
12857 NULL_RTX
, 1, OPTAB_DIRECT
);
12858 t_1
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_1
),
12860 NULL_RTX
, 1, OPTAB_DIRECT
);
12861 t_2
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_2
),
12862 GEN_INT (0x070000),
12863 NULL_RTX
, 1, OPTAB_DIRECT
);
12864 t_3
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_3
),
12865 GEN_INT (0x07000000),
12866 NULL_RTX
, 1, OPTAB_DIRECT
);
12867 /* sel = .......D */
12868 /* t_1 = .....C.. */
12869 /* t_2 = ...B.... */
12870 /* t_3 = .A...... */
12871 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_1
, sel
, 1, OPTAB_DIRECT
);
12872 t_2
= expand_simple_binop (SImode
, IOR
, t_2
, t_3
, t_2
, 1, OPTAB_DIRECT
);
12873 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_2
, sel
, 1, OPTAB_DIRECT
);
12874 /* sel = .A.B.C.D */
12875 sel
= expand_mult (SImode
, sel
, GEN_INT (0x22), sel
, 1);
12876 /* sel = AABBCCDD * 2 */
12877 t_1
= force_reg (SImode
, GEN_INT (0x01010101));
12878 /* sel = { A*2, A*2+1, B*2, B*2+1, ... } */
12882 /* input = xAxBxCxDxExFxGxH */
12883 sel
= expand_simple_binop (DImode
, AND
, sel
,
12884 GEN_INT ((HOST_WIDE_INT
)0x0f0f0f0f << 32
12886 NULL_RTX
, 1, OPTAB_DIRECT
);
12887 /* sel = .A.B.C.D.E.F.G.H */
12888 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (4),
12889 NULL_RTX
, 1, OPTAB_DIRECT
);
12890 /* t_1 = ..A.B.C.D.E.F.G. */
12891 sel
= expand_simple_binop (DImode
, IOR
, sel
, t_1
,
12892 NULL_RTX
, 1, OPTAB_DIRECT
);
12893 /* sel = .AABBCCDDEEFFGGH */
12894 sel
= expand_simple_binop (DImode
, AND
, sel
,
12895 GEN_INT ((HOST_WIDE_INT
)0xff00ff << 32
12897 NULL_RTX
, 1, OPTAB_DIRECT
);
12898 /* sel = ..AB..CD..EF..GH */
12899 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (8),
12900 NULL_RTX
, 1, OPTAB_DIRECT
);
12901 /* t_1 = ....AB..CD..EF.. */
12902 sel
= expand_simple_binop (DImode
, IOR
, sel
, t_1
,
12903 NULL_RTX
, 1, OPTAB_DIRECT
);
12904 /* sel = ..ABABCDCDEFEFGH */
12905 sel
= expand_simple_binop (DImode
, AND
, sel
,
12906 GEN_INT ((HOST_WIDE_INT
)0xffff << 32 | 0xffff),
12907 NULL_RTX
, 1, OPTAB_DIRECT
);
12908 /* sel = ....ABCD....EFGH */
12909 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
12910 NULL_RTX
, 1, OPTAB_DIRECT
);
12911 /* t_1 = ........ABCD.... */
12912 sel
= gen_lowpart (SImode
, sel
);
12913 t_1
= gen_lowpart (SImode
, t_1
);
12917 gcc_unreachable ();
12920 /* Always perform the final addition/merge within the bmask insn. */
12921 emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode
), sel
, t_1
));
12924 /* Implement TARGET_VEC_PERM_CONST. */
12927 sparc_vectorize_vec_perm_const (machine_mode vmode
, rtx target
, rtx op0
,
12928 rtx op1
, const vec_perm_indices
&sel
)
12933 /* All permutes are supported. */
12937 /* Force target-independent code to convert constant permutations on other
12938 modes down to V8QI. Rely on this to avoid the complexity of the byte
12939 order of the permutation. */
12940 if (vmode
!= V8QImode
)
12943 unsigned int i
, mask
;
12944 for (i
= mask
= 0; i
< 8; ++i
)
12945 mask
|= (sel
[i
] & 0xf) << (28 - i
*4);
12946 rtx mask_rtx
= force_reg (SImode
, gen_int_mode (mask
, SImode
));
12948 emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode
), mask_rtx
, const0_rtx
));
12949 emit_insn (gen_bshufflev8qi_vis (target
, op0
, op1
));
12953 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
12956 sparc_frame_pointer_required (void)
12958 /* If the stack pointer is dynamically modified in the function, it cannot
12959 serve as the frame pointer. */
12960 if (cfun
->calls_alloca
)
12963 /* If the function receives nonlocal gotos, it needs to save the frame
12964 pointer in the nonlocal_goto_save_area object. */
12965 if (cfun
->has_nonlocal_label
)
12968 /* In flat mode, that's it. */
12972 /* Otherwise, the frame pointer is required if the function isn't leaf, but
12973 we cannot use sparc_leaf_function_p since it hasn't been computed yet. */
12974 return !(optimize
> 0 && crtl
->is_leaf
&& only_leaf_regs_used ());
12977 /* The way this is structured, we can't eliminate SFP in favor of SP
12978 if the frame pointer is required: we want to use the SFP->HFP elimination
12979 in that case. But the test in update_eliminables doesn't know we are
12980 assuming below that we only do the former elimination. */
12983 sparc_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
12985 return to
== HARD_FRAME_POINTER_REGNUM
|| !sparc_frame_pointer_required ();
12988 /* Return the hard frame pointer directly to bypass the stack bias. */
12991 sparc_builtin_setjmp_frame_value (void)
12993 return hard_frame_pointer_rtx
;
12996 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
12997 they won't be allocated. */
13000 sparc_conditional_register_usage (void)
13002 if (PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
13004 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
13005 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
13007 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */
13008 /* then honor it. */
13009 if (TARGET_ARCH32
&& fixed_regs
[5])
13011 else if (TARGET_ARCH64
&& fixed_regs
[5] == 2)
13016 for (regno
= SPARC_FIRST_V9_FP_REG
;
13017 regno
<= SPARC_LAST_V9_FP_REG
;
13019 fixed_regs
[regno
] = 1;
13020 /* %fcc0 is used by v8 and v9. */
13021 for (regno
= SPARC_FIRST_V9_FCC_REG
+ 1;
13022 regno
<= SPARC_LAST_V9_FCC_REG
;
13024 fixed_regs
[regno
] = 1;
13029 for (regno
= 32; regno
< SPARC_LAST_V9_FCC_REG
; regno
++)
13030 fixed_regs
[regno
] = 1;
13032 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */
13033 /* then honor it. Likewise with g3 and g4. */
13034 if (fixed_regs
[2] == 2)
13035 fixed_regs
[2] = ! TARGET_APP_REGS
;
13036 if (fixed_regs
[3] == 2)
13037 fixed_regs
[3] = ! TARGET_APP_REGS
;
13038 if (TARGET_ARCH32
&& fixed_regs
[4] == 2)
13039 fixed_regs
[4] = ! TARGET_APP_REGS
;
13040 else if (TARGET_CM_EMBMEDANY
)
13042 else if (fixed_regs
[4] == 2)
13047 /* Disable leaf functions. */
13048 memset (sparc_leaf_regs
, 0, FIRST_PSEUDO_REGISTER
);
13049 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
13050 leaf_reg_remap
[regno
] = regno
;
13053 global_regs
[SPARC_GSR_REG
] = 1;
13056 /* Implement TARGET_USE_PSEUDO_PIC_REG. */
13059 sparc_use_pseudo_pic_reg (void)
13061 return !TARGET_VXWORKS_RTP
&& flag_pic
;
13064 /* Implement TARGET_INIT_PIC_REG. */
13067 sparc_init_pic_reg (void)
13072 if (!crtl
->uses_pic_offset_table
)
13076 load_got_register ();
13077 if (!TARGET_VXWORKS_RTP
)
13078 emit_move_insn (pic_offset_table_rtx
, global_offset_table_rtx
);
13079 seq
= get_insns ();
13082 entry_edge
= single_succ_edge (ENTRY_BLOCK_PTR_FOR_FN (cfun
));
13083 insert_insn_on_edge (seq
, entry_edge
);
13084 commit_one_edge_insertion (entry_edge
);
13087 /* Implement TARGET_PREFERRED_RELOAD_CLASS:
13089 - We can't load constants into FP registers.
13090 - We can't load FP constants into integer registers when soft-float,
13091 because there is no soft-float pattern with a r/F constraint.
13092 - We can't load FP constants into integer registers for TFmode unless
13093 it is 0.0L, because there is no movtf pattern with a r/F constraint.
13094 - Try and reload integer constants (symbolic or otherwise) back into
13095 registers directly, rather than having them dumped to memory. */
13098 sparc_preferred_reload_class (rtx x
, reg_class_t rclass
)
13100 machine_mode mode
= GET_MODE (x
);
13101 if (CONSTANT_P (x
))
13103 if (FP_REG_CLASS_P (rclass
)
13104 || rclass
== GENERAL_OR_FP_REGS
13105 || rclass
== GENERAL_OR_EXTRA_FP_REGS
13106 || (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& ! TARGET_FPU
)
13107 || (mode
== TFmode
&& ! const_zero_operand (x
, mode
)))
13110 if (GET_MODE_CLASS (mode
) == MODE_INT
)
13111 return GENERAL_REGS
;
13113 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
13115 if (! FP_REG_CLASS_P (rclass
)
13116 || !(const_zero_operand (x
, mode
)
13117 || const_all_ones_operand (x
, mode
)))
13124 && (rclass
== EXTRA_FP_REGS
13125 || rclass
== GENERAL_OR_EXTRA_FP_REGS
))
13127 int regno
= true_regnum (x
);
13129 if (SPARC_INT_REG_P (regno
))
13130 return (rclass
== EXTRA_FP_REGS
13131 ? FP_REGS
: GENERAL_OR_FP_REGS
);
13137 /* Return true if we use LRA instead of reload pass. */
13145 /* Output a wide multiply instruction in V8+ mode. INSN is the instruction,
13146 OPERANDS are its operands and OPCODE is the mnemonic to be used. */
13149 output_v8plus_mult (rtx_insn
*insn
, rtx
*operands
, const char *opcode
)
13153 gcc_assert (! TARGET_ARCH64
);
13155 if (sparc_check_64 (operands
[1], insn
) <= 0)
13156 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
13157 if (which_alternative
== 1)
13158 output_asm_insn ("sllx\t%H1, 32, %H1", operands
);
13159 if (GET_CODE (operands
[2]) == CONST_INT
)
13161 if (which_alternative
== 1)
13163 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
13164 sprintf (mulstr
, "%s\t%%H1, %%2, %%L0", opcode
);
13165 output_asm_insn (mulstr
, operands
);
13166 return "srlx\t%L0, 32, %H0";
13170 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
13171 output_asm_insn ("or\t%L1, %3, %3", operands
);
13172 sprintf (mulstr
, "%s\t%%3, %%2, %%3", opcode
);
13173 output_asm_insn (mulstr
, operands
);
13174 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
13175 return "mov\t%3, %L0";
13178 else if (rtx_equal_p (operands
[1], operands
[2]))
13180 if (which_alternative
== 1)
13182 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
13183 sprintf (mulstr
, "%s\t%%H1, %%H1, %%L0", opcode
);
13184 output_asm_insn (mulstr
, operands
);
13185 return "srlx\t%L0, 32, %H0";
13189 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
13190 output_asm_insn ("or\t%L1, %3, %3", operands
);
13191 sprintf (mulstr
, "%s\t%%3, %%3, %%3", opcode
);
13192 output_asm_insn (mulstr
, operands
);
13193 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
13194 return "mov\t%3, %L0";
13197 if (sparc_check_64 (operands
[2], insn
) <= 0)
13198 output_asm_insn ("srl\t%L2, 0, %L2", operands
);
13199 if (which_alternative
== 1)
13201 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
13202 output_asm_insn ("sllx\t%H2, 32, %L1", operands
);
13203 output_asm_insn ("or\t%L2, %L1, %L1", operands
);
13204 sprintf (mulstr
, "%s\t%%H1, %%L1, %%L0", opcode
);
13205 output_asm_insn (mulstr
, operands
);
13206 return "srlx\t%L0, 32, %H0";
13210 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
13211 output_asm_insn ("sllx\t%H2, 32, %4", operands
);
13212 output_asm_insn ("or\t%L1, %3, %3", operands
);
13213 output_asm_insn ("or\t%L2, %4, %4", operands
);
13214 sprintf (mulstr
, "%s\t%%3, %%4, %%3", opcode
);
13215 output_asm_insn (mulstr
, operands
);
13216 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
13217 return "mov\t%3, %L0";
13221 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
13222 all fields of TARGET to ELT by means of VIS2 BSHUFFLE insn. MODE
13223 and INNER_MODE are the modes describing TARGET. */
13226 vector_init_bshuffle (rtx target
, rtx elt
, machine_mode mode
,
13227 machine_mode inner_mode
)
13229 rtx t1
, final_insn
, sel
;
13232 t1
= gen_reg_rtx (mode
);
13234 elt
= convert_modes (SImode
, inner_mode
, elt
, true);
13235 emit_move_insn (gen_lowpart(SImode
, t1
), elt
);
13240 final_insn
= gen_bshufflev2si_vis (target
, t1
, t1
);
13241 bmask
= 0x45674567;
13244 final_insn
= gen_bshufflev4hi_vis (target
, t1
, t1
);
13245 bmask
= 0x67676767;
13248 final_insn
= gen_bshufflev8qi_vis (target
, t1
, t1
);
13249 bmask
= 0x77777777;
13252 gcc_unreachable ();
13255 sel
= force_reg (SImode
, GEN_INT (bmask
));
13256 emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode
), sel
, const0_rtx
));
13257 emit_insn (final_insn
);
13260 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
13261 all fields of TARGET to ELT in V8QI by means of VIS FPMERGE insn. */
13264 vector_init_fpmerge (rtx target
, rtx elt
)
13266 rtx t1
, t2
, t2_low
, t3
, t3_low
;
13268 t1
= gen_reg_rtx (V4QImode
);
13269 elt
= convert_modes (SImode
, QImode
, elt
, true);
13270 emit_move_insn (gen_lowpart (SImode
, t1
), elt
);
13272 t2
= gen_reg_rtx (V8QImode
);
13273 t2_low
= gen_lowpart (V4QImode
, t2
);
13274 emit_insn (gen_fpmerge_vis (t2
, t1
, t1
));
13276 t3
= gen_reg_rtx (V8QImode
);
13277 t3_low
= gen_lowpart (V4QImode
, t3
);
13278 emit_insn (gen_fpmerge_vis (t3
, t2_low
, t2_low
));
13280 emit_insn (gen_fpmerge_vis (target
, t3_low
, t3_low
));
13283 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
13284 all fields of TARGET to ELT in V4HI by means of VIS FALIGNDATA insn. */
13287 vector_init_faligndata (rtx target
, rtx elt
)
13289 rtx t1
= gen_reg_rtx (V4HImode
);
13292 elt
= convert_modes (SImode
, HImode
, elt
, true);
13293 emit_move_insn (gen_lowpart (SImode
, t1
), elt
);
13295 emit_insn (gen_alignaddrsi_vis (gen_reg_rtx (SImode
),
13296 force_reg (SImode
, GEN_INT (6)),
13299 for (i
= 0; i
< 4; i
++)
13300 emit_insn (gen_faligndatav4hi_vis (target
, t1
, target
));
13303 /* Emit code to initialize TARGET to values for individual fields VALS. */
13306 sparc_expand_vector_init (rtx target
, rtx vals
)
13308 const machine_mode mode
= GET_MODE (target
);
13309 const machine_mode inner_mode
= GET_MODE_INNER (mode
);
13310 const int n_elts
= GET_MODE_NUNITS (mode
);
13312 bool all_same
= true;
13315 for (i
= 0; i
< n_elts
; i
++)
13317 rtx x
= XVECEXP (vals
, 0, i
);
13318 if (!(CONST_SCALAR_INT_P (x
) || CONST_DOUBLE_P (x
) || CONST_FIXED_P (x
)))
13321 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
13327 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
13331 if (GET_MODE_SIZE (inner_mode
) == GET_MODE_SIZE (mode
))
13333 if (GET_MODE_SIZE (inner_mode
) == 4)
13335 emit_move_insn (gen_lowpart (SImode
, target
),
13336 gen_lowpart (SImode
, XVECEXP (vals
, 0, 0)));
13339 else if (GET_MODE_SIZE (inner_mode
) == 8)
13341 emit_move_insn (gen_lowpart (DImode
, target
),
13342 gen_lowpart (DImode
, XVECEXP (vals
, 0, 0)));
13346 else if (GET_MODE_SIZE (inner_mode
) == GET_MODE_SIZE (word_mode
)
13347 && GET_MODE_SIZE (mode
) == 2 * GET_MODE_SIZE (word_mode
))
13349 emit_move_insn (gen_highpart (word_mode
, target
),
13350 gen_lowpart (word_mode
, XVECEXP (vals
, 0, 0)));
13351 emit_move_insn (gen_lowpart (word_mode
, target
),
13352 gen_lowpart (word_mode
, XVECEXP (vals
, 0, 1)));
13356 if (all_same
&& GET_MODE_SIZE (mode
) == 8)
13360 vector_init_bshuffle (target
, XVECEXP (vals
, 0, 0), mode
, inner_mode
);
13363 if (mode
== V8QImode
)
13365 vector_init_fpmerge (target
, XVECEXP (vals
, 0, 0));
13368 if (mode
== V4HImode
)
13370 vector_init_faligndata (target
, XVECEXP (vals
, 0, 0));
13375 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
13376 for (i
= 0; i
< n_elts
; i
++)
13377 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
13378 i
* GET_MODE_SIZE (inner_mode
)),
13379 XVECEXP (vals
, 0, i
));
13380 emit_move_insn (target
, mem
);
13383 /* Implement TARGET_SECONDARY_RELOAD. */
13386 sparc_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
13387 machine_mode mode
, secondary_reload_info
*sri
)
13389 enum reg_class rclass
= (enum reg_class
) rclass_i
;
13391 sri
->icode
= CODE_FOR_nothing
;
13392 sri
->extra_cost
= 0;
13394 /* We need a temporary when loading/storing a HImode/QImode value
13395 between memory and the FPU registers. This can happen when combine puts
13396 a paradoxical subreg in a float/fix conversion insn. */
13397 if (FP_REG_CLASS_P (rclass
)
13398 && (mode
== HImode
|| mode
== QImode
)
13399 && (GET_CODE (x
) == MEM
13400 || ((GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
13401 && true_regnum (x
) == -1)))
13402 return GENERAL_REGS
;
13404 /* On 32-bit we need a temporary when loading/storing a DFmode value
13405 between unaligned memory and the upper FPU registers. */
13407 && rclass
== EXTRA_FP_REGS
13409 && GET_CODE (x
) == MEM
13410 && ! mem_min_alignment (x
, 8))
13413 if (((TARGET_CM_MEDANY
13414 && symbolic_operand (x
, mode
))
13415 || (TARGET_CM_EMBMEDANY
13416 && text_segment_operand (x
, mode
)))
13420 sri
->icode
= direct_optab_handler (reload_in_optab
, mode
);
13422 sri
->icode
= direct_optab_handler (reload_out_optab
, mode
);
13426 if (TARGET_VIS3
&& TARGET_ARCH32
)
13428 int regno
= true_regnum (x
);
13430 /* When using VIS3 fp<-->int register moves, on 32-bit we have
13431 to move 8-byte values in 4-byte pieces. This only works via
13432 FP_REGS, and not via EXTRA_FP_REGS. Therefore if we try to
13433 move between EXTRA_FP_REGS and GENERAL_REGS, we will need
13434 an FP_REGS intermediate move. */
13435 if ((rclass
== EXTRA_FP_REGS
&& SPARC_INT_REG_P (regno
))
13436 || ((general_or_i64_p (rclass
)
13437 || rclass
== GENERAL_OR_FP_REGS
)
13438 && SPARC_FP_REG_P (regno
)))
13440 sri
->extra_cost
= 2;
13448 /* Implement TARGET_SECONDARY_MEMORY_NEEDED.
13450 On SPARC when not VIS3 it is not possible to directly move data
13451 between GENERAL_REGS and FP_REGS. */
13454 sparc_secondary_memory_needed (machine_mode mode
, reg_class_t class1
,
13455 reg_class_t class2
)
13457 return ((FP_REG_CLASS_P (class1
) != FP_REG_CLASS_P (class2
))
13459 || GET_MODE_SIZE (mode
) > 8
13460 || GET_MODE_SIZE (mode
) < 4));
13463 /* Implement TARGET_SECONDARY_MEMORY_NEEDED_MODE.
13465 get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9
13466 because the movsi and movsf patterns don't handle r/f moves.
13467 For v8 we copy the default definition. */
13469 static machine_mode
13470 sparc_secondary_memory_needed_mode (machine_mode mode
)
13474 if (GET_MODE_BITSIZE (mode
) < 32)
13475 return mode_for_size (32, GET_MODE_CLASS (mode
), 0).require ();
13480 if (GET_MODE_BITSIZE (mode
) < BITS_PER_WORD
)
13481 return mode_for_size (BITS_PER_WORD
,
13482 GET_MODE_CLASS (mode
), 0).require ();
13487 /* Emit code to conditionally move either OPERANDS[2] or OPERANDS[3] into
13488 OPERANDS[0] in MODE. OPERANDS[1] is the operator of the condition. */
13491 sparc_expand_conditional_move (machine_mode mode
, rtx
*operands
)
13493 enum rtx_code rc
= GET_CODE (operands
[1]);
13494 machine_mode cmp_mode
;
13495 rtx cc_reg
, dst
, cmp
;
13498 if (GET_MODE (XEXP (cmp
, 0)) == DImode
&& !TARGET_ARCH64
)
13501 if (GET_MODE (XEXP (cmp
, 0)) == TFmode
&& !TARGET_HARD_QUAD
)
13502 cmp
= sparc_emit_float_lib_cmp (XEXP (cmp
, 0), XEXP (cmp
, 1), rc
);
13504 cmp_mode
= GET_MODE (XEXP (cmp
, 0));
13505 rc
= GET_CODE (cmp
);
13508 if (! rtx_equal_p (operands
[2], dst
)
13509 && ! rtx_equal_p (operands
[3], dst
))
13511 if (reg_overlap_mentioned_p (dst
, cmp
))
13512 dst
= gen_reg_rtx (mode
);
13514 emit_move_insn (dst
, operands
[3]);
13516 else if (operands
[2] == dst
)
13518 operands
[2] = operands
[3];
13520 if (GET_MODE_CLASS (cmp_mode
) == MODE_FLOAT
)
13521 rc
= reverse_condition_maybe_unordered (rc
);
13523 rc
= reverse_condition (rc
);
13526 if (XEXP (cmp
, 1) == const0_rtx
13527 && GET_CODE (XEXP (cmp
, 0)) == REG
13528 && cmp_mode
== DImode
13529 && v9_regcmp_p (rc
))
13530 cc_reg
= XEXP (cmp
, 0);
13532 cc_reg
= gen_compare_reg_1 (rc
, XEXP (cmp
, 0), XEXP (cmp
, 1));
13534 cmp
= gen_rtx_fmt_ee (rc
, GET_MODE (cc_reg
), cc_reg
, const0_rtx
);
13536 emit_insn (gen_rtx_SET (dst
,
13537 gen_rtx_IF_THEN_ELSE (mode
, cmp
, operands
[2], dst
)));
13539 if (dst
!= operands
[0])
13540 emit_move_insn (operands
[0], dst
);
13545 /* Emit code to conditionally move a combination of OPERANDS[1] and OPERANDS[2]
13546 into OPERANDS[0] in MODE, depending on the outcome of the comparison of
13547 OPERANDS[4] and OPERANDS[5]. OPERANDS[3] is the operator of the condition.
13548 FCODE is the machine code to be used for OPERANDS[3] and CCODE the machine
13549 code to be used for the condition mask. */
13552 sparc_expand_vcond (machine_mode mode
, rtx
*operands
, int ccode
, int fcode
)
13554 rtx mask
, cop0
, cop1
, fcmp
, cmask
, bshuf
, gsr
;
13555 enum rtx_code code
= GET_CODE (operands
[3]);
13557 mask
= gen_reg_rtx (Pmode
);
13558 cop0
= operands
[4];
13559 cop1
= operands
[5];
13560 if (code
== LT
|| code
== GE
)
13564 code
= swap_condition (code
);
13565 t
= cop0
; cop0
= cop1
; cop1
= t
;
13568 gsr
= gen_rtx_REG (DImode
, SPARC_GSR_REG
);
13570 fcmp
= gen_rtx_UNSPEC (Pmode
,
13571 gen_rtvec (1, gen_rtx_fmt_ee (code
, mode
, cop0
, cop1
)),
13574 cmask
= gen_rtx_UNSPEC (DImode
,
13575 gen_rtvec (2, mask
, gsr
),
13578 bshuf
= gen_rtx_UNSPEC (mode
,
13579 gen_rtvec (3, operands
[1], operands
[2], gsr
),
13582 emit_insn (gen_rtx_SET (mask
, fcmp
));
13583 emit_insn (gen_rtx_SET (gsr
, cmask
));
13585 emit_insn (gen_rtx_SET (operands
[0], bshuf
));
13588 /* On sparc, any mode which naturally allocates into the float
13589 registers should return 4 here. */
13592 sparc_regmode_natural_size (machine_mode mode
)
13594 int size
= UNITS_PER_WORD
;
13598 enum mode_class mclass
= GET_MODE_CLASS (mode
);
13600 if (mclass
== MODE_FLOAT
|| mclass
== MODE_VECTOR_INT
)
13607 /* Implement TARGET_HARD_REGNO_NREGS.
13609 On SPARC, ordinary registers hold 32 bits worth; this means both
13610 integer and floating point registers. On v9, integer regs hold 64
13611 bits worth; floating point regs hold 32 bits worth (this includes the
13612 new fp regs as even the odd ones are included in the hard register
13615 static unsigned int
13616 sparc_hard_regno_nregs (unsigned int regno
, machine_mode mode
)
13618 if (regno
== SPARC_GSR_REG
)
13622 if (SPARC_INT_REG_P (regno
) || regno
== FRAME_POINTER_REGNUM
)
13623 return CEIL (GET_MODE_SIZE (mode
), UNITS_PER_WORD
);
13624 return CEIL (GET_MODE_SIZE (mode
), 4);
13626 return CEIL (GET_MODE_SIZE (mode
), UNITS_PER_WORD
);
13629 /* Implement TARGET_HARD_REGNO_MODE_OK.
13631 ??? Because of the funny way we pass parameters we should allow certain
13632 ??? types of float/complex values to be in integer registers during
13633 ??? RTL generation. This only matters on arch32. */
13636 sparc_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
13638 return (hard_regno_mode_classes
[regno
] & sparc_mode_class
[mode
]) != 0;
13641 /* Implement TARGET_MODES_TIEABLE_P.
13643 For V9 we have to deal with the fact that only the lower 32 floating
13644 point registers are 32-bit addressable. */
13647 sparc_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
13649 enum mode_class mclass1
, mclass2
;
13650 unsigned short size1
, size2
;
13652 if (mode1
== mode2
)
13655 mclass1
= GET_MODE_CLASS (mode1
);
13656 mclass2
= GET_MODE_CLASS (mode2
);
13657 if (mclass1
!= mclass2
)
13663 /* Classes are the same and we are V9 so we have to deal with upper
13664 vs. lower floating point registers. If one of the modes is a
13665 4-byte mode, and the other is not, we have to mark them as not
13666 tieable because only the lower 32 floating point register are
13667 addressable 32-bits at a time.
13669 We can't just test explicitly for SFmode, otherwise we won't
13670 cover the vector mode cases properly. */
13672 if (mclass1
!= MODE_FLOAT
&& mclass1
!= MODE_VECTOR_INT
)
13675 size1
= GET_MODE_SIZE (mode1
);
13676 size2
= GET_MODE_SIZE (mode2
);
13677 if ((size1
> 4 && size2
== 4)
13678 || (size2
> 4 && size1
== 4))
13684 /* Implement TARGET_CSTORE_MODE. */
13686 static scalar_int_mode
13687 sparc_cstore_mode (enum insn_code icode ATTRIBUTE_UNUSED
)
13689 return (TARGET_ARCH64
? DImode
: SImode
);
13692 /* Return the compound expression made of T1 and T2. */
13695 compound_expr (tree t1
, tree t2
)
13697 return build2 (COMPOUND_EXPR
, void_type_node
, t1
, t2
);
13700 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
13703 sparc_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
13708 const unsigned HOST_WIDE_INT accrued_exception_mask
= 0x1f << 5;
13709 const unsigned HOST_WIDE_INT trap_enable_mask
= 0x1f << 23;
13711 /* We generate the equivalent of feholdexcept (&fenv_var):
13713 unsigned int fenv_var;
13714 __builtin_store_fsr (&fenv_var);
13716 unsigned int tmp1_var;
13717 tmp1_var = fenv_var & ~(accrued_exception_mask | trap_enable_mask);
13719 __builtin_load_fsr (&tmp1_var); */
13721 tree fenv_var
= create_tmp_var_raw (unsigned_type_node
);
13722 TREE_ADDRESSABLE (fenv_var
) = 1;
13723 tree fenv_addr
= build_fold_addr_expr (fenv_var
);
13724 tree stfsr
= sparc_builtins
[SPARC_BUILTIN_STFSR
];
13726 = build4 (TARGET_EXPR
, unsigned_type_node
, fenv_var
,
13727 build_call_expr (stfsr
, 1, fenv_addr
), NULL_TREE
, NULL_TREE
);
13729 tree tmp1_var
= create_tmp_var_raw (unsigned_type_node
);
13730 TREE_ADDRESSABLE (tmp1_var
) = 1;
13731 tree masked_fenv_var
13732 = build2 (BIT_AND_EXPR
, unsigned_type_node
, fenv_var
,
13733 build_int_cst (unsigned_type_node
,
13734 ~(accrued_exception_mask
| trap_enable_mask
)));
13736 = build4 (TARGET_EXPR
, unsigned_type_node
, tmp1_var
, masked_fenv_var
,
13737 NULL_TREE
, NULL_TREE
);
13739 tree tmp1_addr
= build_fold_addr_expr (tmp1_var
);
13740 tree ldfsr
= sparc_builtins
[SPARC_BUILTIN_LDFSR
];
13741 tree hold_ldfsr
= build_call_expr (ldfsr
, 1, tmp1_addr
);
13743 *hold
= compound_expr (compound_expr (hold_stfsr
, hold_mask
), hold_ldfsr
);
13745 /* We reload the value of tmp1_var to clear the exceptions:
13747 __builtin_load_fsr (&tmp1_var); */
13749 *clear
= build_call_expr (ldfsr
, 1, tmp1_addr
);
13751 /* We generate the equivalent of feupdateenv (&fenv_var):
13753 unsigned int tmp2_var;
13754 __builtin_store_fsr (&tmp2_var);
13756 __builtin_load_fsr (&fenv_var);
13758 if (SPARC_LOW_FE_EXCEPT_VALUES)
13760 __atomic_feraiseexcept ((int) tmp2_var); */
13762 tree tmp2_var
= create_tmp_var_raw (unsigned_type_node
);
13763 TREE_ADDRESSABLE (tmp2_var
) = 1;
13764 tree tmp2_addr
= build_fold_addr_expr (tmp2_var
);
13766 = build4 (TARGET_EXPR
, unsigned_type_node
, tmp2_var
,
13767 build_call_expr (stfsr
, 1, tmp2_addr
), NULL_TREE
, NULL_TREE
);
13769 tree update_ldfsr
= build_call_expr (ldfsr
, 1, fenv_addr
);
13771 tree atomic_feraiseexcept
13772 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT
);
13774 = build_call_expr (atomic_feraiseexcept
, 1,
13775 fold_convert (integer_type_node
, tmp2_var
));
13777 if (SPARC_LOW_FE_EXCEPT_VALUES
)
13779 tree shifted_tmp2_var
13780 = build2 (RSHIFT_EXPR
, unsigned_type_node
, tmp2_var
,
13781 build_int_cst (unsigned_type_node
, 5));
13783 = build2 (MODIFY_EXPR
, void_type_node
, tmp2_var
, shifted_tmp2_var
);
13784 update_call
= compound_expr (update_shift
, update_call
);
13788 = compound_expr (compound_expr (update_stfsr
, update_ldfsr
), update_call
);
13791 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. Borrowed from the PA port.
13793 SImode loads to floating-point registers are not zero-extended.
13794 The definition for LOAD_EXTEND_OP specifies that integer loads
13795 narrower than BITS_PER_WORD will be zero-extended. As a result,
13796 we inhibit changes from SImode unless they are to a mode that is
13799 Likewise for SFmode, since word-mode paradoxical subregs are
13800 problematic on big-endian architectures. */
13803 sparc_can_change_mode_class (machine_mode from
, machine_mode to
,
13804 reg_class_t rclass
)
13807 && GET_MODE_SIZE (from
) == 4
13808 && GET_MODE_SIZE (to
) != 4)
13809 return !reg_classes_intersect_p (rclass
, FP_REGS
);
13813 /* Implement TARGET_CONSTANT_ALIGNMENT. */
13815 static HOST_WIDE_INT
13816 sparc_constant_alignment (const_tree exp
, HOST_WIDE_INT align
)
13818 if (TREE_CODE (exp
) == STRING_CST
)
13819 return MAX (align
, FASTEST_ALIGNMENT
);
13823 #include "gt-sparc.h"