1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987-2016 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com).
4 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
23 #include "config/vxworks-dummy.h"
25 /* Note that some other tm.h files include this one and then override
26 whatever definitions are necessary. */
28 #define TARGET_CPU_CPP_BUILTINS() sparc_target_macros ()
30 /* Specify this in a cover file to provide bi-architecture (32/64) support. */
31 /* #define SPARC_BI_ARCH */
33 /* Macro used later in this file to determine default architecture. */
34 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0)
36 /* TARGET_ARCH{32,64} are the main macros to decide which of the two
37 architectures to compile for. We allow targets to choose compile time or
40 #if defined(__sparcv9) || defined(__arch64__)
41 #define TARGET_ARCH32 0
43 #define TARGET_ARCH32 1
47 #define TARGET_ARCH32 (! TARGET_64BIT)
49 #define TARGET_ARCH32 (DEFAULT_ARCH32_P)
50 #endif /* SPARC_BI_ARCH */
51 #endif /* IN_LIBGCC2 */
52 #define TARGET_ARCH64 (! TARGET_ARCH32)
54 /* Code model selection in 64-bit environment.
56 The machine mode used for addresses is 32-bit wide:
58 TARGET_CM_32: 32-bit address space.
59 It is the code model used when generating 32-bit code.
61 The machine mode used for addresses is 64-bit wide:
63 TARGET_CM_MEDLOW: 32-bit address space.
64 The executable must be in the low 32 bits of memory.
65 This avoids generating %uhi and %ulo terms. Programs
66 can be statically or dynamically linked.
68 TARGET_CM_MEDMID: 44-bit address space.
69 The executable must be in the low 44 bits of memory,
70 and the %[hml]44 terms are used. The text and data
71 segments have a maximum size of 2GB (31-bit span).
72 The maximum offset from any instruction to the label
73 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span).
75 TARGET_CM_MEDANY: 64-bit address space.
76 The text and data segments have a maximum size of 2GB
77 (31-bit span) and may be located anywhere in memory.
78 The maximum offset from any instruction to the label
79 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span).
81 TARGET_CM_EMBMEDANY: 64-bit address space.
82 The text and data segments have a maximum size of 2GB
83 (31-bit span) and may be located anywhere in memory.
84 The global register %g4 contains the start address of
85 the data segment. Programs are statically linked and
88 Different code models are not supported in 32-bit environment. */
99 extern enum cmodel sparc_cmodel
;
101 /* V9 code model selection. */
102 #define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW)
103 #define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID)
104 #define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY)
105 #define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY)
107 #define SPARC_DEFAULT_CMODEL CM_32
109 /* Do not use the .note.GNU-stack convention by default. */
110 #define NEED_INDICATE_EXEC_STACK 0
112 /* This is call-clobbered in the normal ABI, but is reserved in the
113 home grown (aka upward compatible) embedded ABI. */
114 #define EMBMEDANY_BASE_REG "%g4"
116 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile,
117 and specified by the user via --with-cpu=foo.
118 This specifies the cpu implementation, not the architecture size. */
119 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit
121 #define TARGET_CPU_sparc 0
122 #define TARGET_CPU_v7 0 /* alias */
123 #define TARGET_CPU_cypress 0 /* alias */
124 #define TARGET_CPU_v8 1 /* generic v8 implementation */
125 #define TARGET_CPU_supersparc 2
126 #define TARGET_CPU_hypersparc 3
127 #define TARGET_CPU_leon 4
128 #define TARGET_CPU_leon3 5
129 #define TARGET_CPU_leon3v7 6
130 #define TARGET_CPU_sparclite 7
131 #define TARGET_CPU_f930 7 /* alias */
132 #define TARGET_CPU_f934 7 /* alias */
133 #define TARGET_CPU_sparclite86x 8
134 #define TARGET_CPU_sparclet 9
135 #define TARGET_CPU_tsc701 9 /* alias */
136 #define TARGET_CPU_v9 10 /* generic v9 implementation */
137 #define TARGET_CPU_sparcv9 10 /* alias */
138 #define TARGET_CPU_sparc64 10 /* alias */
139 #define TARGET_CPU_ultrasparc 11
140 #define TARGET_CPU_ultrasparc3 12
141 #define TARGET_CPU_niagara 13
142 #define TARGET_CPU_niagara2 14
143 #define TARGET_CPU_niagara3 15
144 #define TARGET_CPU_niagara4 16
146 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
147 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
148 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \
149 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara \
150 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 \
151 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara3 \
152 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara4
154 #define CPP_CPU32_DEFAULT_SPEC ""
155 #define ASM_CPU32_DEFAULT_SPEC ""
157 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9
158 /* ??? What does Sun's CC pass? */
159 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
160 /* ??? It's not clear how other assemblers will handle this, so by default
161 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case
162 is handled in sol2.h. */
163 #define ASM_CPU64_DEFAULT_SPEC "-Av9"
165 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
166 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
167 #define ASM_CPU64_DEFAULT_SPEC "-Av9a"
169 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
170 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
171 #define ASM_CPU64_DEFAULT_SPEC "-Av9b"
173 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara
174 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
175 #define ASM_CPU64_DEFAULT_SPEC "-Av9b"
177 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara2
178 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
179 #define ASM_CPU64_DEFAULT_SPEC "-Av9b"
181 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara3
182 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
183 #define ASM_CPU64_DEFAULT_SPEC "-Av9" AS_NIAGARA3_FLAG
185 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara4
186 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
187 #define ASM_CPU64_DEFAULT_SPEC AS_NIAGARA4_FLAG
192 #define CPP_CPU64_DEFAULT_SPEC ""
193 #define ASM_CPU64_DEFAULT_SPEC ""
195 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \
196 || TARGET_CPU_DEFAULT == TARGET_CPU_v8
197 #define CPP_CPU32_DEFAULT_SPEC ""
198 #define ASM_CPU32_DEFAULT_SPEC ""
201 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet
202 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__"
203 #define ASM_CPU32_DEFAULT_SPEC "-Asparclet"
206 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite
207 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__"
208 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
211 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x
212 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__"
213 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
216 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc
217 #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__"
218 #define ASM_CPU32_DEFAULT_SPEC ""
221 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc
222 #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__"
223 #define ASM_CPU32_DEFAULT_SPEC ""
226 #if TARGET_CPU_DEFAULT == TARGET_CPU_leon \
227 || TARGET_CPU_DEFAULT == TARGET_CPU_leon3
228 #define CPP_CPU32_DEFAULT_SPEC "-D__leon__ -D__sparc_v8__"
229 #define ASM_CPU32_DEFAULT_SPEC AS_LEON_FLAG
232 #if TARGET_CPU_DEFAULT == TARGET_CPU_leon3v7
233 #define CPP_CPU32_DEFAULT_SPEC "-D__leon__"
234 #define ASM_CPU32_DEFAULT_SPEC AS_LEONV7_FLAG
239 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC)
240 #error Unrecognized value in TARGET_CPU_DEFAULT.
245 #define CPP_CPU_DEFAULT_SPEC \
246 (DEFAULT_ARCH32_P ? "\
247 %{m64:" CPP_CPU64_DEFAULT_SPEC "} \
248 %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \
250 %{m32:" CPP_CPU32_DEFAULT_SPEC "} \
251 %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \
253 #define ASM_CPU_DEFAULT_SPEC \
254 (DEFAULT_ARCH32_P ? "\
255 %{m64:" ASM_CPU64_DEFAULT_SPEC "} \
256 %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \
258 %{m32:" ASM_CPU32_DEFAULT_SPEC "} \
259 %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \
262 #else /* !SPARC_BI_ARCH */
264 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC)
265 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC)
267 #endif /* !SPARC_BI_ARCH */
269 /* Define macros to distinguish architectures. */
271 /* Common CPP definitions used by CPP_SPEC amongst the various targets
272 for handling -mcpu=xxx switches. */
273 #define CPP_CPU_SPEC "\
274 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \
275 %{mcpu=sparclite:-D__sparclite__} \
276 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \
277 %{mcpu=sparclite86x:-D__sparclite86x__} \
278 %{mcpu=v8:-D__sparc_v8__} \
279 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
280 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \
281 %{mcpu=leon:-D__leon__ -D__sparc_v8__} \
282 %{mcpu=leon3:-D__leon__ -D__sparc_v8__} \
283 %{mcpu=leon3v7:-D__leon__} \
284 %{mcpu=v9:-D__sparc_v9__} \
285 %{mcpu=ultrasparc:-D__sparc_v9__} \
286 %{mcpu=ultrasparc3:-D__sparc_v9__} \
287 %{mcpu=niagara:-D__sparc_v9__} \
288 %{mcpu=niagara2:-D__sparc_v9__} \
289 %{mcpu=niagara3:-D__sparc_v9__} \
290 %{mcpu=niagara4:-D__sparc_v9__} \
291 %{!mcpu*:%(cpp_cpu_default)} \
293 #define CPP_ARCH32_SPEC ""
294 #define CPP_ARCH64_SPEC "-D__arch64__"
296 #define CPP_ARCH_DEFAULT_SPEC \
297 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC)
299 #define CPP_ARCH_SPEC "\
300 %{m32:%(cpp_arch32)} \
301 %{m64:%(cpp_arch64)} \
302 %{!m32:%{!m64:%(cpp_arch_default)}} \
305 /* Macros to distinguish the endianness, window model and FP support. */
306 #define CPP_OTHER_SPEC "\
308 %{msoft-float:-D_SOFT_FLOAT} \
311 /* Macros to distinguish the particular subtarget. */
312 #define CPP_SUBTARGET_SPEC ""
315 "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_other) %(cpp_subtarget)"
317 /* This used to translate -dalign to -malign, but that is no good
318 because it can't turn off the usual meaning of making debugging dumps. */
322 /* Override in target specific files. */
323 #define ASM_CPU_SPEC "\
324 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \
325 %{mcpu=sparclite:-Asparclite} \
326 %{mcpu=sparclite86x:-Asparclite} \
327 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
329 %{mcpu=supersparc:-Av8} \
330 %{mcpu=hypersparc:-Av8} \
331 %{mcpu=leon:" AS_LEON_FLAG "} \
332 %{mcpu=leon3:" AS_LEON_FLAG "} \
333 %{mcpu=leon3v7:" AS_LEONV7_FLAG "} \
334 %{mv8plus:-Av8plus} \
336 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
337 %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \
338 %{mcpu=niagara:%{!mv8plus:-Av9b}} \
339 %{mcpu=niagara2:%{!mv8plus:-Av9b}} \
340 %{mcpu=niagara3:%{!mv8plus:-Av9" AS_NIAGARA3_FLAG "}} \
341 %{mcpu=niagara4:%{!mv8plus:" AS_NIAGARA4_FLAG "}} \
342 %{!mcpu*:%(asm_cpu_default)} \
345 /* Word size selection, among other things.
346 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */
348 #define ASM_ARCH32_SPEC "-32"
349 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
350 #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs"
352 #define ASM_ARCH64_SPEC "-64"
354 #define ASM_ARCH_DEFAULT_SPEC \
355 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC)
357 #define ASM_ARCH_SPEC "\
358 %{m32:%(asm_arch32)} \
359 %{m64:%(asm_arch64)} \
360 %{!m32:%{!m64:%(asm_arch_default)}} \
363 #ifdef HAVE_AS_RELAX_OPTION
364 #define ASM_RELAX_SPEC "%{!mno-relax:-relax}"
366 #define ASM_RELAX_SPEC ""
369 /* Special flags to the Sun-4 assembler when using pipe for input. */
372 %{!pg:%{!p:%{" FPIE_OR_FPIC_SPEC ":-k}}} %{keep-local-as-symbols:-L} \
373 %(asm_cpu) %(asm_relax)"
375 /* This macro defines names of additional specifications to put in the specs
376 that can be used in various specifications like CC1_SPEC. Its definition
377 is an initializer with a subgrouping for each command option.
379 Each subgrouping contains a string constant, that defines the
380 specification name, and a string constant that used by the GCC driver
383 Do not define this macro if it does not need to do anything. */
385 #define EXTRA_SPECS \
386 { "cpp_cpu", CPP_CPU_SPEC }, \
387 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
388 { "cpp_arch32", CPP_ARCH32_SPEC }, \
389 { "cpp_arch64", CPP_ARCH64_SPEC }, \
390 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\
391 { "cpp_arch", CPP_ARCH_SPEC }, \
392 { "cpp_other", CPP_OTHER_SPEC }, \
393 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
394 { "asm_cpu", ASM_CPU_SPEC }, \
395 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \
396 { "asm_arch32", ASM_ARCH32_SPEC }, \
397 { "asm_arch64", ASM_ARCH64_SPEC }, \
398 { "asm_relax", ASM_RELAX_SPEC }, \
399 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\
400 { "asm_arch", ASM_ARCH_SPEC }, \
401 SUBTARGET_EXTRA_SPECS
403 #define SUBTARGET_EXTRA_SPECS
405 /* Because libgcc can generate references back to libc (via .umul etc.) we have
406 to list libc again after the second libgcc. */
407 #define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G %L"
410 #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int")
411 #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int")
413 /* ??? This should be 32 bits for v9 but what can we do? */
414 #define WCHAR_TYPE "short unsigned int"
415 #define WCHAR_TYPE_SIZE 16
417 /* Mask of all CPU selection flags. */
419 (MASK_SPARCLITE + MASK_SPARCLET \
420 + MASK_V8 + MASK_V9 + MASK_DEPRECATED_V8_INSNS)
422 /* TARGET_HARD_MUL: Use 32-bit hardware multiply instructions but not %y. */
423 #define TARGET_HARD_MUL \
424 (TARGET_SPARCLITE || TARGET_SPARCLET \
425 || TARGET_V8 || TARGET_DEPRECATED_V8_INSNS)
427 /* TARGET_HARD_MUL32: Use 32-bit hardware multiply instructions with %y
428 to get high 32 bits. False in 64-bit or V8+ because multiply stores
429 a 64-bit result in a register. */
430 #define TARGET_HARD_MUL32 \
431 (TARGET_HARD_MUL && TARGET_ARCH32 && !TARGET_V8PLUS)
433 /* MASK_APP_REGS must always be the default because that's what
434 FIXED_REGISTERS is set to and -ffixed- is processed before
435 TARGET_CONDITIONAL_REGISTER_USAGE is called (where we process
437 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU)
439 /* Recast the cpu class to be the cpu attribute.
440 Every file includes us, but not every file includes insn-attr.h. */
441 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)
443 /* Support for a compile-time default CPU, et cetera. The rules are:
444 --with-cpu is ignored if -mcpu is specified.
445 --with-tune is ignored if -mtune is specified.
446 --with-float is ignored if -mhard-float, -msoft-float, -mfpu, or -mno-fpu
448 #define OPTION_DEFAULT_SPECS \
449 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
450 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
451 {"float", "%{!msoft-float:%{!mhard-float:%{!mfpu:%{!mno-fpu:-m%(VALUE)-float}}}}" }
453 /* target machine storage layout */
455 /* Define this if most significant bit is lowest numbered
456 in instructions that operate on numbered bit-fields. */
457 #define BITS_BIG_ENDIAN 1
459 /* Define this if most significant byte of a word is the lowest numbered. */
460 #define BYTES_BIG_ENDIAN 1
462 /* Define this if most significant word of a multiword number is the lowest
464 #define WORDS_BIG_ENDIAN 1
466 #define MAX_BITS_PER_WORD 64
468 /* Width of a word, in units (bytes). */
469 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4)
471 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
473 #define MIN_UNITS_PER_WORD 4
476 /* Now define the sizes of the C data types. */
477 #define SHORT_TYPE_SIZE 16
478 #define INT_TYPE_SIZE 32
479 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32)
480 #define LONG_LONG_TYPE_SIZE 64
481 #define FLOAT_TYPE_SIZE 32
482 #define DOUBLE_TYPE_SIZE 64
484 /* LONG_DOUBLE_TYPE_SIZE is defined per OS even though the
485 SPARC ABI says that it is 128-bit wide. */
486 /* #define LONG_DOUBLE_TYPE_SIZE 128 */
488 /* The widest floating-point format really supported by the hardware. */
489 #define WIDEST_HARDWARE_FP_SIZE 64
491 /* Width in bits of a pointer. This is the size of ptr_mode. */
492 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32)
494 /* This is the machine mode used for addresses. */
495 #define Pmode (TARGET_ARCH64 ? DImode : SImode)
497 /* If we have to extend pointers (only when TARGET_ARCH64 and not
498 TARGET_PTR64), we want to do it unsigned. This macro does nothing
499 if ptr_mode and Pmode are the same. */
500 #define POINTERS_EXTEND_UNSIGNED 1
502 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
503 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
505 /* Boundary (in *bits*) on which stack pointer should be aligned. */
506 /* FIXME, this is wrong when TARGET_ARCH64 and TARGET_STACK_BIAS, because
507 then %sp+2047 is 128-bit aligned so %sp is really only byte-aligned. */
508 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64)
510 /* Temporary hack until the FIXME above is fixed. */
511 #define SPARC_STACK_BOUNDARY_HACK (TARGET_ARCH64 && TARGET_STACK_BIAS)
513 /* ALIGN FRAMES on double word boundaries */
514 #define SPARC_STACK_ALIGN(LOC) ROUND_UP ((LOC), UNITS_PER_WORD * 2)
516 /* Allocation boundary (in *bits*) for the code of a function. */
517 #define FUNCTION_BOUNDARY 32
519 /* Alignment of field after `int : 0' in a structure. */
520 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
522 /* Every structure's size must be a multiple of this. */
523 #define STRUCTURE_SIZE_BOUNDARY 8
525 /* A bit-field declared as `int' forces `int' alignment for the struct. */
526 #define PCC_BITFIELD_TYPE_MATTERS 1
528 /* No data type wants to be aligned rounder than this. */
529 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64)
531 /* The best alignment to use in cases where we have a choice. */
532 #define FASTEST_ALIGNMENT 64
534 /* Define this macro as an expression for the alignment of a structure
535 (given by STRUCT as a tree node) if the alignment computed in the
536 usual way is COMPUTED and the alignment explicitly specified was
539 The default is to use SPECIFIED if it is larger; otherwise, use
540 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */
541 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \
542 (TARGET_FASTER_STRUCTS ? \
543 ((TREE_CODE (STRUCT) == RECORD_TYPE \
544 || TREE_CODE (STRUCT) == UNION_TYPE \
545 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \
546 && TYPE_FIELDS (STRUCT) != 0 \
547 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \
548 : MAX ((COMPUTED), (SPECIFIED))) \
549 : MAX ((COMPUTED), (SPECIFIED)))
551 /* An integer expression for the size in bits of the largest integer machine
552 mode that should actually be used. We allow pairs of registers. */
553 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_ARCH64 ? TImode : DImode)
555 /* We need 2 words, so we can save the stack pointer and the return register
556 of the function containing a non-local goto target. */
557 #define STACK_SAVEAREA_MODE(LEVEL) \
558 ((LEVEL) == SAVE_NONLOCAL ? (TARGET_ARCH64 ? TImode : DImode) : Pmode)
560 /* Make strings word-aligned so strcpy from constants will be faster. */
561 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
562 ((TREE_CODE (EXP) == STRING_CST \
563 && (ALIGN) < FASTEST_ALIGNMENT) \
564 ? FASTEST_ALIGNMENT : (ALIGN))
566 /* Make arrays of chars word-aligned for the same reasons. */
567 #define DATA_ALIGNMENT(TYPE, ALIGN) \
568 (TREE_CODE (TYPE) == ARRAY_TYPE \
569 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
570 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
572 /* Make local arrays of chars word-aligned for the same reasons. */
573 #define LOCAL_ALIGNMENT(TYPE, ALIGN) DATA_ALIGNMENT (TYPE, ALIGN)
575 /* Set this nonzero if move instructions will actually fail to work
576 when given unaligned data. */
577 #define STRICT_ALIGNMENT 1
579 /* Things that must be doubleword aligned cannot go in the text section,
580 because the linker fails to align the text section enough!
581 Put them in the data section. This macro is only used in this file. */
582 #define MAX_TEXT_ALIGN 32
584 /* Standard register usage. */
586 /* Number of actual hardware registers.
587 The hardware registers are assigned numbers for the compiler
588 from 0 to just below FIRST_PSEUDO_REGISTER.
589 All registers that the compiler knows about must be given numbers,
590 even those that are not normally considered general registers.
592 SPARC has 32 integer registers and 32 floating point registers.
593 64-bit SPARC has 32 additional fp regs, but the odd numbered ones are not
594 accessible. We still account for them to simplify register computations
595 (e.g.: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
597 Register 100 is used as the integer condition code register.
598 Register 101 is used as the soft frame pointer register. */
600 #define FIRST_PSEUDO_REGISTER 103
602 #define SPARC_FIRST_INT_REG 0
603 #define SPARC_LAST_INT_REG 31
604 #define SPARC_FIRST_FP_REG 32
605 /* Additional V9 fp regs. */
606 #define SPARC_FIRST_V9_FP_REG 64
607 #define SPARC_LAST_V9_FP_REG 95
608 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */
609 #define SPARC_FIRST_V9_FCC_REG 96
610 #define SPARC_LAST_V9_FCC_REG 99
612 #define SPARC_FCC_REG 96
613 /* Integer CC reg. We don't distinguish %icc from %xcc. */
614 #define SPARC_ICC_REG 100
615 #define SPARC_GSR_REG 102
617 /* Nonzero if REGNO is an fp reg. */
618 #define SPARC_FP_REG_P(REGNO) \
619 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG)
621 /* Nonzero if REGNO is an int reg. */
622 #define SPARC_INT_REG_P(REGNO) \
623 (((unsigned) (REGNO)) <= SPARC_LAST_INT_REG)
625 /* Argument passing regs. */
626 #define SPARC_OUTGOING_INT_ARG_FIRST 8
627 #define SPARC_INCOMING_INT_ARG_FIRST (TARGET_FLAT ? 8 : 24)
628 #define SPARC_FP_ARG_FIRST 32
630 /* 1 for registers that have pervasive standard uses
631 and are not available for the register allocator.
634 g1 is free to use as temporary.
635 g2-g4 are reserved for applications. Gcc normally uses them as
636 temporaries, but this can be disabled via the -mno-app-regs option.
637 g5 through g7 are reserved for the operating system.
640 g1,g5 are free to use as temporaries, and are free to use between calls
641 if the call is to an external function via the PLT.
642 g4 is free to use as a temporary in the non-embedded case.
643 g4 is reserved in the embedded case.
644 g2-g3 are reserved for applications. Gcc normally uses them as
645 temporaries, but this can be disabled via the -mno-app-regs option.
646 g6-g7 are reserved for the operating system (or application in
648 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must
649 currently be a fixed register until this pattern is rewritten.
650 Register 1 is also used when restoring call-preserved registers in large
653 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in
654 TARGET_CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-.
657 #define FIXED_REGISTERS \
658 {1, 0, 2, 2, 2, 2, 1, 1, \
659 0, 0, 0, 0, 0, 0, 1, 0, \
660 0, 0, 0, 0, 0, 0, 0, 0, \
661 0, 0, 0, 0, 0, 0, 0, 1, \
663 0, 0, 0, 0, 0, 0, 0, 0, \
664 0, 0, 0, 0, 0, 0, 0, 0, \
665 0, 0, 0, 0, 0, 0, 0, 0, \
666 0, 0, 0, 0, 0, 0, 0, 0, \
668 0, 0, 0, 0, 0, 0, 0, 0, \
669 0, 0, 0, 0, 0, 0, 0, 0, \
670 0, 0, 0, 0, 0, 0, 0, 0, \
671 0, 0, 0, 0, 0, 0, 0, 0, \
675 /* 1 for registers not available across function calls.
676 These must include the FIXED_REGISTERS and also any
677 registers that can be used without being saved.
678 The latter must include the registers where values are returned
679 and the register where structure-value addresses are passed.
680 Aside from that, you can include as many other registers as you like. */
682 #define CALL_USED_REGISTERS \
683 {1, 1, 1, 1, 1, 1, 1, 1, \
684 1, 1, 1, 1, 1, 1, 1, 1, \
685 0, 0, 0, 0, 0, 0, 0, 0, \
686 0, 0, 0, 0, 0, 0, 0, 1, \
688 1, 1, 1, 1, 1, 1, 1, 1, \
689 1, 1, 1, 1, 1, 1, 1, 1, \
690 1, 1, 1, 1, 1, 1, 1, 1, \
691 1, 1, 1, 1, 1, 1, 1, 1, \
693 1, 1, 1, 1, 1, 1, 1, 1, \
694 1, 1, 1, 1, 1, 1, 1, 1, \
695 1, 1, 1, 1, 1, 1, 1, 1, \
696 1, 1, 1, 1, 1, 1, 1, 1, \
700 /* 1 for registers not available across function calls.
701 Unlike the above, this need not include the FIXED_REGISTERS, but any
702 registers that can be used without being saved.
703 The latter must include the registers where values are returned
704 and the register where structure-value addresses are passed.
705 Aside from that, you can include as many other registers as you like. */
707 #define CALL_REALLY_USED_REGISTERS \
708 {1, 1, 1, 1, 1, 1, 1, 1, \
709 1, 1, 1, 1, 1, 1, 1, 1, \
710 0, 0, 0, 0, 0, 0, 0, 0, \
711 0, 0, 0, 0, 0, 0, 0, 0, \
713 1, 1, 1, 1, 1, 1, 1, 1, \
714 1, 1, 1, 1, 1, 1, 1, 1, \
715 1, 1, 1, 1, 1, 1, 1, 1, \
716 1, 1, 1, 1, 1, 1, 1, 1, \
718 1, 1, 1, 1, 1, 1, 1, 1, \
719 1, 1, 1, 1, 1, 1, 1, 1, \
720 1, 1, 1, 1, 1, 1, 1, 1, \
721 1, 1, 1, 1, 1, 1, 1, 1, \
725 /* Return number of consecutive hard regs needed starting at reg REGNO
726 to hold something of mode MODE.
727 This is ordinarily the length in words of a value of mode MODE
728 but can be less for certain modes in special long registers.
730 On SPARC, ordinary registers hold 32 bits worth;
731 this means both integer and floating point registers.
732 On v9, integer regs hold 64 bits worth; floating point regs hold
733 32 bits worth (this includes the new fp regs as even the odd ones are
734 included in the hard register count). */
736 #define HARD_REGNO_NREGS(REGNO, MODE) \
737 ((REGNO) == SPARC_GSR_REG ? 1 : \
739 ? (SPARC_INT_REG_P (REGNO) || (REGNO) == FRAME_POINTER_REGNUM \
740 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \
741 : (GET_MODE_SIZE (MODE) + 3) / 4) \
742 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
744 /* Due to the ARCH64 discrepancy above we must override this next
746 #define REGMODE_NATURAL_SIZE(MODE) sparc_regmode_natural_size (MODE)
748 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
749 See sparc.c for how we initialize this. */
750 extern const int *hard_regno_mode_classes
;
751 extern int sparc_mode_class
[];
753 /* ??? Because of the funny way we pass parameters we should allow certain
754 ??? types of float/complex values to be in integer registers during
755 ??? RTL generation. This only matters on arch32. */
756 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
757 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)
759 /* Value is 1 if it is OK to rename a hard register FROM to another hard
760 register TO. We cannot rename %g1 as it may be used before the save
761 register window instruction in the prologue. */
762 #define HARD_REGNO_RENAME_OK(FROM, TO) ((FROM) != 1)
764 #define MODES_TIEABLE_P(MODE1, MODE2) sparc_modes_tieable_p (MODE1, MODE2)
766 /* Specify the registers used for certain standard purposes.
767 The values of these macros are register numbers. */
769 /* Register to use for pushing function arguments. */
770 #define STACK_POINTER_REGNUM 14
772 /* The stack bias (amount by which the hardware register is offset by). */
773 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0)
775 /* Actual top-of-stack address is 92/176 greater than the contents of the
776 stack pointer register for !v9/v9. That is:
777 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return
778 address, and 6*4 bytes for the 6 register parameters.
779 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer
781 #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS)
783 /* Base register for access to local variables of the function. */
784 #define HARD_FRAME_POINTER_REGNUM 30
786 /* The soft frame pointer does not have the stack bias applied. */
787 #define FRAME_POINTER_REGNUM 101
789 /* Given the stack bias, the stack pointer isn't actually aligned. */
790 #define INIT_EXPANDERS \
792 if (crtl->emit.regno_pointer_align && SPARC_STACK_BIAS) \
794 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT; \
795 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \
799 /* Base register for access to arguments of the function. */
800 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
802 /* Register in which static-chain is passed to a function. This must
803 not be a register used by the prologue. */
804 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2)
806 /* Register which holds the global offset table, if any. */
808 #define GLOBAL_OFFSET_TABLE_REGNUM 23
810 /* Register which holds offset table for position-independent
813 #define PIC_OFFSET_TABLE_REGNUM \
814 (flag_pic ? GLOBAL_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
816 /* Pick a default value we can notice from override_options:
819 Originally it was -1, but later on the container of options changed to
820 unsigned byte, so we decided to pick 127 as default value, which does
821 reflect an undefined default value in case of 0/1. */
823 #define DEFAULT_PCC_STRUCT_RETURN 127
825 /* Functions which return large structures get the address
826 to place the wanted value at offset 64 from the frame.
827 Must reserve 64 bytes for the in and local registers.
828 v9: Functions which return large structures get the address to place the
829 wanted value from an invisible first argument. */
830 #define STRUCT_VALUE_OFFSET 64
832 /* Define the classes of registers for register constraints in the
833 machine description. Also define ranges of constants.
835 One of the classes must always be named ALL_REGS and include all hard regs.
836 If there is more than one class, another class must be named NO_REGS
837 and contain no registers.
839 The name GENERAL_REGS must be the name of a class (or an alias for
840 another name such as ALL_REGS). This is the class of registers
841 that is allowed by "g" or "r" in a register constraint.
842 Also, registers outside this class are allocated only when
843 instructions express preferences for them.
845 The classes must be numbered in nondecreasing order; that is,
846 a larger-numbered class must never be contained completely
847 in a smaller-numbered class.
849 For any two classes, it is very desirable that there be another
850 class that represents their union. */
852 /* The SPARC has various kinds of registers: general, floating point,
853 and condition codes [well, it has others as well, but none that we
854 care directly about].
856 For v9 we must distinguish between the upper and lower floating point
857 registers because the upper ones can't hold SFmode values.
858 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s)
859 satisfying a group need for a class will also satisfy a single need for
860 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp
863 It is important that one class contains all the general and all the standard
864 fp regs. Otherwise find_reg() won't properly allocate int regs for moves,
865 because reg_class_record() will bias the selection in favor of fp regs,
866 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS,
867 because FP_REGS > GENERAL_REGS.
869 It is also important that one class contain all the general and all
870 the fp regs. Otherwise when spilling a DFmode reg, it may be from
871 EXTRA_FP_REGS but find_reloads() may use class
872 GENERAL_OR_FP_REGS. This will cause allocate_reload_reg() to die
873 because the compiler thinks it doesn't have a spill reg when in
876 v9 also has 4 floating point condition code registers. Since we don't
877 have a class that is the union of FPCC_REGS with either of the others,
878 it is important that it appear first. Otherwise the compiler will die
879 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its
882 It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine
883 may try to use it to hold an SImode value. See register_operand.
884 ??? Should %fcc[0123] be handled similarly?
887 enum reg_class
{ NO_REGS
, FPCC_REGS
, I64_REGS
, GENERAL_REGS
, FP_REGS
,
888 EXTRA_FP_REGS
, GENERAL_OR_FP_REGS
, GENERAL_OR_EXTRA_FP_REGS
,
889 ALL_REGS
, LIM_REG_CLASSES
};
891 #define N_REG_CLASSES (int) LIM_REG_CLASSES
893 /* Give names of register classes as strings for dump file. */
895 #define REG_CLASS_NAMES \
896 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \
897 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \
900 /* Define which registers fit in which classes.
901 This is an initializer for a vector of HARD_REG_SET
902 of length N_REG_CLASSES. */
904 #define REG_CLASS_CONTENTS \
905 {{0, 0, 0, 0}, /* NO_REGS */ \
906 {0, 0, 0, 0xf}, /* FPCC_REGS */ \
907 {0xffff, 0, 0, 0}, /* I64_REGS */ \
908 {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \
909 {0, -1, 0, 0}, /* FP_REGS */ \
910 {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \
911 {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \
912 {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \
913 {-1, -1, -1, 0x7f}} /* ALL_REGS */
915 /* The same information, inverted:
916 Return the class number of the smallest class containing
917 reg number REGNO. This could be a conditional expression
918 or could index an array. */
920 extern enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
922 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
924 /* Defines invalid mode changes. Borrowed from the PA port.
926 SImode loads to floating-point registers are not zero-extended.
927 The definition for LOAD_EXTEND_OP specifies that integer loads
928 narrower than BITS_PER_WORD will be zero-extended. As a result,
929 we inhibit changes from SImode unless they are to a mode that is
932 Likewise for SFmode, since word-mode paradoxical subregs are
933 problematic on big-endian architectures. */
935 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
937 && GET_MODE_SIZE (FROM) == 4 \
938 && GET_MODE_SIZE (TO) != 4 \
939 ? reg_classes_intersect_p (CLASS, FP_REGS) : 0)
941 /* This is the order in which to allocate registers normally.
943 We put %f0-%f7 last among the float registers, so as to make it more
944 likely that a pseudo-register which dies in the float return register
945 area will get allocated to the float return register, thus saving a move
946 instruction at the end of the function.
948 Similarly for integer return value registers.
950 We know in this case that we will not end up with a leaf function.
952 The register allocator is given the global and out registers first
953 because these registers are call clobbered and thus less useful to
954 global register allocation.
956 Next we list the local and in registers. They are not call clobbered
957 and thus very useful for global register allocation. We list the input
958 registers before the locals so that it is more likely the incoming
959 arguments received in those registers can just stay there and not be
962 #define REG_ALLOC_ORDER \
963 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \
964 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \
966 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \
967 29, 28, 27, 26, 25, 24, 31, /* %i5-%i0,%i7 */\
968 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
969 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
970 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
971 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
972 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
973 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
974 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
975 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \
976 96, 97, 98, 99, /* %fcc0-3 */ \
977 100, 0, 14, 30, 101, 102 } /* %icc, %g0, %o6, %i6, %sfp, %gsr */
979 /* This is the order in which to allocate registers for
980 leaf functions. If all registers can fit in the global and
981 output registers, then we have the possibility of having a leaf
984 The macro actually mentioned the input registers first,
985 because they get renumbered into the output registers once
986 we know really do have a leaf function.
988 To be more precise, this register allocation order is used
989 when %o7 is found to not be clobbered right before register
990 allocation. Normally, the reason %o7 would be clobbered is
991 due to a call which could not be transformed into a sibling
994 As a consequence, it is possible to use the leaf register
995 allocation order and not end up with a leaf function. We will
996 not get suboptimal register allocation in that case because by
997 definition of being potentially leaf, there were no function
998 calls. Therefore, allocation order within the local register
999 window is not critical like it is when we do have function calls. */
1001 #define REG_LEAF_ALLOC_ORDER \
1002 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \
1003 29, 28, 27, 26, 25, 24, /* %i5-%i0 */ \
1005 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \
1006 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \
1007 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1008 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1009 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1010 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1011 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1012 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1013 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1014 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \
1015 96, 97, 98, 99, /* %fcc0-3 */ \
1016 100, 0, 14, 30, 31, 101, 102 } /* %icc, %g0, %o6, %i6, %i7, %sfp, %gsr */
1018 #define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc ()
1020 extern char sparc_leaf_regs
[];
1021 #define LEAF_REGISTERS sparc_leaf_regs
1023 extern char leaf_reg_remap
[];
1024 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
1026 /* The class value for index registers, and the one for base regs. */
1027 #define INDEX_REG_CLASS GENERAL_REGS
1028 #define BASE_REG_CLASS GENERAL_REGS
1030 /* Local macro to handle the two v9 classes of FP regs. */
1031 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)
1033 /* Predicates for 5-bit, 10-bit, 11-bit and 13-bit signed constants. */
1034 #define SPARC_SIMM5_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x10 < 0x20)
1035 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)
1036 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800)
1037 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000)
1039 /* 10- and 11-bit immediates are only used for a few specific insns.
1040 SMALL_INT is used throughout the port so we continue to use it. */
1041 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X)))
1043 /* Predicate for constants that can be loaded with a sethi instruction.
1044 This is the general, 64-bit aware, bitwise version that ensures that
1045 only constants whose representation fits in the mask
1049 are accepted. It will reject, for example, negative SImode constants
1050 on 64-bit hosts, so correct handling is to mask the value beforehand
1051 according to the mode of the instruction. */
1052 #define SPARC_SETHI_P(X) \
1053 (((unsigned HOST_WIDE_INT) (X) \
1054 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0)
1056 /* Version of the above predicate for SImode constants and below. */
1057 #define SPARC_SETHI32_P(X) \
1058 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode)))
1060 /* On SPARC when not VIS3 it is not possible to directly move data
1061 between GENERAL_REGS and FP_REGS. */
1062 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1063 ((FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2)) \
1065 || GET_MODE_SIZE (MODE) > 8 \
1066 || GET_MODE_SIZE (MODE) < 4))
1068 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9
1069 because the movsi and movsf patterns don't handle r/f moves.
1070 For v8 we copy the default definition. */
1071 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1073 ? (GET_MODE_BITSIZE (MODE) < 32 \
1074 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1076 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \
1077 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \
1080 /* Return the maximum number of consecutive registers
1081 needed to represent mode MODE in a register of class CLASS. */
1082 /* On SPARC, this is the size of MODE in words. */
1083 #define CLASS_MAX_NREGS(CLASS, MODE) \
1084 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \
1085 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1087 /* Stack layout; function entry, exit and calling. */
1089 /* Define this if pushing a word on the stack
1090 makes the stack pointer a smaller address. */
1091 #define STACK_GROWS_DOWNWARD 1
1093 /* Define this to nonzero if the nominal address of the stack frame
1094 is at the high-address end of the local variables;
1095 that is, each additional local variable allocated
1096 goes at a more negative offset in the frame. */
1097 #define FRAME_GROWS_DOWNWARD 1
1099 /* Offset within stack frame to start allocating local variables at.
1100 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1101 first local allocated. Otherwise, it is the offset to the BEGINNING
1102 of the first local allocated. */
1103 #define STARTING_FRAME_OFFSET 0
1105 /* Offset of first parameter from the argument pointer register value.
1106 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg
1107 even if this function isn't going to use it.
1108 v9: This is 128 for the ins and locals. */
1109 #define FIRST_PARM_OFFSET(FNDECL) \
1110 (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD)
1112 /* Offset from the argument pointer register value to the CFA.
1113 This is different from FIRST_PARM_OFFSET because the register window
1114 comes between the CFA and the arguments. */
1115 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1117 /* When a parameter is passed in a register, stack space is still
1119 !v9: All 6 possible integer registers have backing store allocated.
1120 v9: Only space for the arguments passed is allocated. */
1121 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special
1122 meaning to the backend. Further, we need to be able to detect if a
1123 varargs/unprototyped function is called, as they may want to spill more
1124 registers than we've provided space. Ugly, ugly. So for now we retain
1125 all 6 slots even for v9. */
1126 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD)
1128 /* Definitions for register elimination. */
1130 #define ELIMINABLE_REGS \
1131 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1132 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} }
1134 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1137 (OFFSET) = sparc_initial_elimination_offset ((TO)); \
1141 /* Keep the stack pointer constant throughout the function.
1142 This is both an optimization and a necessity: longjmp
1143 doesn't behave itself when the stack pointer moves within
1145 #define ACCUMULATE_OUTGOING_ARGS 1
1147 /* Define this macro if the target machine has "register windows". This
1148 C expression returns the register number as seen by the called function
1149 corresponding to register number OUT as seen by the calling function.
1150 Return OUT if register number OUT is not an outbound register. */
1152 #define INCOMING_REGNO(OUT) \
1153 ((TARGET_FLAT || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
1155 /* Define this macro if the target machine has "register windows". This
1156 C expression returns the register number as seen by the calling function
1157 corresponding to register number IN as seen by the called function.
1158 Return IN if register number IN is not an inbound register. */
1160 #define OUTGOING_REGNO(IN) \
1161 ((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
1163 /* Define this macro if the target machine has register windows. This
1164 C expression returns true if the register is call-saved but is in the
1167 #define LOCAL_REGNO(REGNO) \
1168 (!TARGET_FLAT && (REGNO) >= 16 && (REGNO) <= 31)
1170 /* Define the size of space to allocate for the return value of an
1173 #define APPLY_RESULT_SIZE (TARGET_ARCH64 ? 24 : 16)
1175 /* 1 if N is a possible register number for function argument passing.
1176 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */
1178 #define FUNCTION_ARG_REGNO_P(N) \
1179 (((N) >= 8 && (N) <= 13) \
1180 || (TARGET_ARCH64 && TARGET_FPU && (N) >= 32 && (N) <= 63))
1182 /* Define a data type for recording info about an argument list
1183 during the scan of that argument list. This data type should
1184 hold all necessary information about the function itself
1185 and about the args processed so far, enough to enable macros
1186 such as FUNCTION_ARG to determine where the next arg should go.
1188 On SPARC (!v9), this is a single integer, which is a number of words
1189 of arguments scanned so far (including the invisible argument,
1190 if any, which holds the structure-value-address).
1191 Thus 7 or more means all following args should go on the stack.
1193 For v9, we also need to know whether a prototype is present. */
1196 int words
; /* number of words passed so far */
1197 int prototype_p
; /* nonzero if a prototype is present */
1198 int libcall_p
; /* nonzero if a library call */
1200 #define CUMULATIVE_ARGS struct sparc_args
1202 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1203 for a call to a function whose data type is FNTYPE.
1204 For a library call, FNTYPE is 0. */
1206 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1207 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL));
1209 /* If defined, a C expression which determines whether, and in which direction,
1210 to pad out an argument with extra space. The value should be of type
1211 `enum direction': either `upward' to pad above the argument,
1212 `downward' to pad below, or `none' to inhibit padding. */
1214 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1215 function_arg_padding ((MODE), (TYPE))
1218 /* Generate the special assembly code needed to tell the assembler whatever
1219 it might need to know about the return value of a function.
1221 For SPARC assemblers, we need to output a .proc pseudo-op which conveys
1222 information to the assembler relating to peephole optimization (done in
1225 #define ASM_DECLARE_RESULT(FILE, RESULT) \
1226 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT)))
1228 /* Output the special assembly code needed to tell the assembler some
1229 register is used as global register variable.
1231 SPARC 64bit psABI declares registers %g2 and %g3 as application
1232 registers and %g6 and %g7 as OS registers. Any object using them
1233 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them
1234 and how they are used (scratch or some global variable).
1235 Linker will then refuse to link together objects which use those
1236 registers incompatibly.
1238 Unless the registers are used for scratch, two different global
1239 registers cannot be declared to the same name, so in the unlikely
1240 case of a global register variable occupying more than one register
1241 we prefix the second and following registers with .gnu.part1. etc. */
1243 extern GTY(()) char sparc_hard_reg_printed
[8];
1245 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
1246 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \
1248 if (TARGET_ARCH64) \
1250 int end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \
1252 for (reg = (REGNO); reg < 8 && reg < end; reg++) \
1253 if ((reg & ~1) == 2 || (reg & ~1) == 6) \
1255 if (reg == (REGNO)) \
1256 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \
1258 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \
1259 reg, reg - (REGNO), (NAME)); \
1260 sparc_hard_reg_printed[reg] = 1; \
1267 /* Emit rtl for profiling. */
1268 #define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL)
1270 /* All the work done in PROFILE_HOOK, but still required. */
1271 #define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0)
1273 /* Set the name of the mcount function for the system. */
1274 #define MCOUNT_FUNCTION "*mcount"
1276 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1277 the stack pointer does not matter. The value is tested only in
1278 functions that have frame pointers. */
1279 #define EXIT_IGNORE_STACK 1
1281 /* Length in units of the trampoline for entering a nested function. */
1282 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16)
1284 /* Alignment required for trampolines, in bits. */
1285 #define TRAMPOLINE_ALIGNMENT 128
1287 /* Generate RTL to flush the register windows so as to make arbitrary frames
1289 #define SETUP_FRAME_ADDRESSES() \
1292 emit_insn (gen_flush_register_windows ());\
1295 /* Given an rtx for the address of a frame,
1296 return an rtx for the address of the word in the frame
1297 that holds the dynamic chain--the previous frame's address. */
1298 #define DYNAMIC_CHAIN_ADDRESS(frame) \
1299 plus_constant (Pmode, frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS)
1301 /* Given an rtx for the frame pointer,
1302 return an rtx for the address of the frame. */
1303 #define FRAME_ADDR_RTX(frame) plus_constant (Pmode, frame, SPARC_STACK_BIAS)
1305 /* The return address isn't on the stack, it is in a register, so we can't
1306 access it from the current frame pointer. We can access it from the
1307 previous frame pointer though by reading a value from the register window
1309 #define RETURN_ADDR_IN_PREVIOUS_FRAME 1
1311 /* This is the offset of the return address to the true next instruction to be
1312 executed for the current function. */
1313 #define RETURN_ADDR_OFFSET \
1314 (8 + 4 * (! TARGET_ARCH64 && cfun->returns_struct))
1316 /* The current return address is in %i7. The return address of anything
1317 farther back is in the register window save area at [%fp+60]. */
1318 /* ??? This ignores the fact that the actual return address is +8 for normal
1319 returns, and +12 for structure returns. */
1320 #define RETURN_ADDR_REGNUM 31
1321 #define RETURN_ADDR_RTX(count, frame) \
1323 ? gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM) \
1324 : gen_rtx_MEM (Pmode, \
1325 memory_address (Pmode, plus_constant (Pmode, frame, \
1326 15 * UNITS_PER_WORD \
1327 + SPARC_STACK_BIAS))))
1329 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's
1330 +12, but always using +8 is close enough for frame unwind purposes.
1331 Actually, just using %o7 is close enough for unwinding, but %o7+8
1332 is something you can return to. */
1333 #define INCOMING_RETURN_ADDR_REGNUM 15
1334 #define INCOMING_RETURN_ADDR_RTX \
1335 plus_constant (word_mode, \
1336 gen_rtx_REG (word_mode, INCOMING_RETURN_ADDR_REGNUM), 8)
1337 #define DWARF_FRAME_RETURN_COLUMN \
1338 DWARF_FRAME_REGNUM (INCOMING_RETURN_ADDR_REGNUM)
1340 /* The offset from the incoming value of %sp to the top of the stack frame
1341 for the current function. On sparc64, we have to account for the stack
1343 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS
1345 /* Describe how we implement __builtin_eh_return. */
1346 #define EH_RETURN_REGNUM 1
1347 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM)
1348 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_REGNUM)
1350 /* Define registers used by the epilogue and return instruction. */
1351 #define EPILOGUE_USES(REGNO) \
1352 ((REGNO) == RETURN_ADDR_REGNUM \
1354 && epilogue_completed \
1355 && (REGNO) == INCOMING_RETURN_ADDR_REGNUM) \
1356 || (crtl->calls_eh_return && (REGNO) == EH_RETURN_REGNUM))
1358 /* Select a format to encode pointers in exception handling data. CODE
1359 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1360 true if the symbol may be affected by dynamic relocations.
1362 If assembler and linker properly support .uaword %r_disp32(foo),
1363 then use PC relative 32-bit relocations instead of absolute relocs
1364 for shared libraries. On sparc64, use pc relative 32-bit relocs even
1365 for binaries, to save memory.
1367 binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the
1368 symbol %r_disp32() is against was not local, but .hidden. In that
1369 case, we have to use DW_EH_PE_absptr for pic personality. */
1370 #ifdef HAVE_AS_SPARC_UA_PCREL
1371 #ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN
1372 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1374 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
1375 : ((TARGET_ARCH64 && ! GLOBAL) \
1376 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
1379 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1381 ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \
1382 : ((TARGET_ARCH64 && ! GLOBAL) \
1383 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
1387 /* Emit a PC-relative relocation. */
1388 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
1390 fputs (integer_asm_op (SIZE, FALSE), FILE); \
1391 fprintf (FILE, "%%r_disp%d(", SIZE * 8); \
1392 assemble_name (FILE, LABEL); \
1393 fputc (')', FILE); \
1397 /* Addressing modes, and classification of registers for them. */
1399 /* Macros to check register numbers against specific register classes. */
1401 /* These assume that REGNO is a hard or pseudo reg number.
1402 They give nonzero only if REGNO is a hard reg of the suitable class
1403 or a pseudo reg currently allocated to a suitable hard reg.
1404 Since they use reg_renumber, they are safe only once reg_renumber
1405 has been allocated, which happens in reginfo.c during register
1408 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1409 (SPARC_INT_REG_P (REGNO) || SPARC_INT_REG_P (reg_renumber[REGNO]) \
1410 || (REGNO) == FRAME_POINTER_REGNUM \
1411 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)
1413 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
1415 #define REGNO_OK_FOR_FP_P(REGNO) \
1416 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \
1417 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)))
1419 #define REGNO_OK_FOR_CCFP_P(REGNO) \
1421 && (((unsigned) (REGNO) - 96 < (unsigned)4) \
1422 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4)))
1424 /* Maximum number of registers that can appear in a valid memory address. */
1426 #define MAX_REGS_PER_ADDRESS 2
1428 /* Recognize any constant value that is a valid address.
1429 When PIC, we do not accept an address that would require a scratch reg
1430 to load into a register. */
1432 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1434 /* Define this, so that when PIC, reload won't try to reload invalid
1435 addresses which require two reload registers. */
1437 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1439 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */
1441 #ifdef HAVE_AS_OFFSETABLE_LO10
1442 #define USE_AS_OFFSETABLE_LO10 1
1444 #define USE_AS_OFFSETABLE_LO10 0
1447 /* Try a machine-dependent way of reloading an illegitimate address
1448 operand. If we find one, push the reload and jump to WIN. This
1449 macro is used in only one place: `find_reloads_address' in reload.c. */
1450 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1453 (X) = sparc_legitimize_reload_address ((X), (MODE), (OPNUM), \
1454 (int)(TYPE), (IND_LEVELS), &win); \
1459 /* Specify the machine mode that this machine uses
1460 for the index in the tablejump instruction. */
1461 /* If we ever implement any of the full models (such as CM_FULLANY),
1462 this has to be DImode in that case */
1463 #ifdef HAVE_GAS_SUBSECTION_ORDERING
1464 #define CASE_VECTOR_MODE \
1465 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode)
1467 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise
1468 we have to sign extend which slows things down. */
1469 #define CASE_VECTOR_MODE \
1470 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode)
1473 /* Define this as 1 if `char' should by default be signed; else as 0. */
1474 #define DEFAULT_SIGNED_CHAR 1
1476 /* Max number of bytes we can move from memory to memory
1477 in one reasonably fast instruction. */
1480 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1481 move-instruction pairs, we will do a movmem or libcall instead. */
1483 #define MOVE_RATIO(speed) ((speed) ? 8 : 3)
1485 /* Define if operations between registers always perform the operation
1486 on the full register even if a narrower mode is specified. */
1487 #define WORD_REGISTER_OPERATIONS 1
1489 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1490 will either zero-extend or sign-extend. The value of this macro should
1491 be the code that says which one of the two operations is implicitly
1492 done, UNKNOWN if none. */
1493 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1495 /* Nonzero if access to memory by bytes is slow and undesirable.
1496 For RISC chips, it means that access to memory by bytes is no
1497 better than access by words when possible, so grab a whole word
1498 and maybe make use of that. */
1499 #define SLOW_BYTE_ACCESS 1
1501 /* Define this to be nonzero if shift instructions ignore all but the low-order
1503 #define SHIFT_COUNT_TRUNCATED 1
1505 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1506 is done just by pretending it is already truncated. */
1507 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1509 /* For SImode, we make sure the top 32-bits of the register are clear and
1510 then we subtract 32 from the lzd instruction result. */
1511 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1512 ((VALUE) = ((MODE) == SImode ? 32 : 64), 1)
1514 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1515 return the mode to be used for the comparison. For floating-point,
1516 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
1517 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
1518 processing is needed. */
1519 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y))
1521 /* Return nonzero if MODE implies a floating point inequality can be
1522 reversed. For SPARC this is always true because we have a full
1523 compliment of ordered and unordered comparisons, but until generic
1524 code knows how to reverse it correctly we keep the old definition. */
1525 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode)
1527 /* A function address in a call instruction for indexing purposes. */
1528 #define FUNCTION_MODE Pmode
1530 /* Define this if addresses of constant functions
1531 shouldn't be put through pseudo regs where they can be cse'd.
1532 Desirable on machines where ordinary constants are expensive
1533 but a CALL with constant address is cheap. */
1534 #define NO_FUNCTION_CSE 1
1536 /* The _Q_* comparison libcalls return booleans. */
1537 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode)
1539 /* Assume by default that the _Qp_* 64-bit libcalls are implemented such
1540 that the inputs are fully consumed before the output memory is clobbered. */
1542 #define TARGET_BUGGY_QP_LIB 0
1544 /* Assume by default that we do not have the Solaris-specific conversion
1545 routines nor 64-bit integer multiply and divide routines. */
1547 #define SUN_CONVERSION_LIBFUNCS 0
1548 #define DITF_CONVERSION_LIBFUNCS 0
1549 #define SUN_INTEGER_MULTIPLY_64 0
1551 /* Provide the cost of a branch. For pre-v9 processors we use
1552 a value of 3 to take into account the potential annulling of
1553 the delay slot (which ends up being a bubble in the pipeline slot)
1554 plus a cycle to take into consideration the instruction cache
1557 On v9 and later, which have branch prediction facilities, we set
1558 it to the depth of the pipeline as that is the cost of a
1559 mispredicted branch.
1561 On Niagara, normal branches insert 3 bubbles into the pipe
1562 and annulled branches insert 4 bubbles.
1564 On Niagara-2 and Niagara-3, a not-taken branch costs 1 cycle whereas
1565 a taken branch costs 6 cycles. */
1567 #define BRANCH_COST(speed_p, predictable_p) \
1568 ((sparc_cpu == PROCESSOR_V9 \
1569 || sparc_cpu == PROCESSOR_ULTRASPARC) \
1571 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \
1573 : (sparc_cpu == PROCESSOR_NIAGARA \
1575 : ((sparc_cpu == PROCESSOR_NIAGARA2 \
1576 || sparc_cpu == PROCESSOR_NIAGARA3) \
1580 /* Control the assembler format that we output. */
1582 /* A C string constant describing how to begin a comment in the target
1583 assembler language. The compiler assumes that the comment will end at
1584 the end of the line. */
1586 #define ASM_COMMENT_START "!"
1588 /* Output to assembler file text saying following lines
1589 may contain character constants, extra white space, comments, etc. */
1591 #define ASM_APP_ON ""
1593 /* Output to assembler file text saying following lines
1594 no longer contain unusual constructs. */
1596 #define ASM_APP_OFF ""
1598 /* How to refer to registers in assembler output.
1599 This sequence is indexed by compiler's hard-register-number (see above). */
1601 #define REGISTER_NAMES \
1602 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
1603 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
1604 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
1605 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
1606 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
1607 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
1608 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
1609 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \
1610 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \
1611 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \
1612 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \
1613 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \
1614 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp", "%gsr" }
1616 /* Define additional names for use in asm clobbers and asm declarations. */
1618 #define ADDITIONAL_REGISTER_NAMES \
1619 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}}
1621 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length
1622 can run past this up to a continuation point. Once we used 1500, but
1623 a single entry in C++ can run more than 500 bytes, due to the length of
1624 mangled symbol names. dbxout.c should really be fixed to do
1625 continuations when they are actually needed instead of trying to
1627 #define DBX_CONTIN_LENGTH 1000
1629 /* This is how to output a command to make the user-level label named NAME
1630 defined for reference from other files. */
1632 /* Globalizing directive for a label. */
1633 #define GLOBAL_ASM_OP "\t.global "
1635 /* The prefix to add to user-visible assembler symbols. */
1637 #define USER_LABEL_PREFIX "_"
1639 /* This is how to store into the string LABEL
1640 the symbol_ref name of an internal numbered label where
1641 PREFIX is the class of label and NUM is the number within the class.
1642 This is suitable for output with `assemble_name'. */
1644 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1645 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM))
1647 /* This is how we hook in and defer the case-vector until the end of
1649 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \
1650 sparc_defer_case_vector ((LAB),(VEC), 0)
1652 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \
1653 sparc_defer_case_vector ((LAB),(VEC), 1)
1655 /* This is how to output an element of a case-vector that is absolute. */
1657 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1660 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1661 if (CASE_VECTOR_MODE == SImode) \
1662 fprintf (FILE, "\t.word\t"); \
1664 fprintf (FILE, "\t.xword\t"); \
1665 assemble_name (FILE, label); \
1666 fputc ('\n', FILE); \
1669 /* This is how to output an element of a case-vector that is relative.
1670 (SPARC uses such vectors only when generating PIC.) */
1672 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1675 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \
1676 if (CASE_VECTOR_MODE == SImode) \
1677 fprintf (FILE, "\t.word\t"); \
1679 fprintf (FILE, "\t.xword\t"); \
1680 assemble_name (FILE, label); \
1681 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \
1682 fputc ('-', FILE); \
1683 assemble_name (FILE, label); \
1684 fputc ('\n', FILE); \
1687 /* This is what to output before and after case-vector (both
1688 relative and absolute). If .subsection -1 works, we put case-vectors
1689 at the beginning of the current section. */
1691 #ifdef HAVE_GAS_SUBSECTION_ORDERING
1693 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \
1694 fprintf(FILE, "\t.subsection\t-1\n")
1696 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \
1697 fprintf(FILE, "\t.previous\n")
1701 /* This is how to output an assembler line
1702 that says to advance the location counter
1703 to a multiple of 2**LOG bytes. */
1705 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1707 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
1709 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1710 fprintf (FILE, "\t.skip " HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
1712 /* This says how to output an assembler line
1713 to define a global common symbol. */
1715 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1716 ( fputs ("\t.common ", (FILE)), \
1717 assemble_name ((FILE), (NAME)), \
1718 fprintf ((FILE), "," HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\"\n", (SIZE)))
1720 /* This says how to output an assembler line to define a local common
1723 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
1724 ( fputs ("\t.reserve ", (FILE)), \
1725 assemble_name ((FILE), (NAME)), \
1726 fprintf ((FILE), "," HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\",%u\n", \
1727 (SIZE), ((ALIGNED) / BITS_PER_UNIT)))
1729 /* A C statement (sans semicolon) to output to the stdio stream
1730 FILE the assembler definition of uninitialized global DECL named
1731 NAME whose size is SIZE bytes and alignment is ALIGN bytes.
1732 Try to use asm_output_aligned_bss to implement this macro. */
1734 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1736 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
1739 /* Output #ident as a .ident. */
1741 #undef TARGET_ASM_OUTPUT_IDENT
1742 #define TARGET_ASM_OUTPUT_IDENT default_asm_output_ident_directive
1744 /* Prettify the assembly. */
1746 extern int sparc_indent_opcode
;
1748 #define ASM_OUTPUT_OPCODE(FILE, PTR) \
1750 if (sparc_indent_opcode) \
1753 sparc_indent_opcode = 0; \
1757 /* TLS support defaulting to original Sun flavor. GNU extensions
1758 must be activated in separate configuration files. */
1760 #define TARGET_TLS 1
1762 #define TARGET_TLS 0
1765 #define TARGET_SUN_TLS TARGET_TLS
1766 #define TARGET_GNU_TLS 0
1768 #ifdef HAVE_AS_FMAF_HPC_VIS3
1769 #define AS_NIAGARA3_FLAG "d"
1771 #define AS_NIAGARA3_FLAG "b"
1774 #ifdef HAVE_AS_SPARC4
1775 #define AS_NIAGARA4_FLAG "-xarch=sparc4"
1777 #define AS_NIAGARA4_FLAG "-Av9" AS_NIAGARA3_FLAG
1781 #define AS_LEON_FLAG "-Aleon"
1782 #define AS_LEONV7_FLAG "-Aleon"
1784 #define AS_LEON_FLAG "-Av8"
1785 #define AS_LEONV7_FLAG "-Av7"
1788 /* We use gcc _mcount for profiling. */
1789 #define NO_PROFILE_COUNTERS 0
1792 #define MASK_DEBUG_OPTIONS 0x01 /* debug option handling */
1793 #define MASK_DEBUG_ALL MASK_DEBUG_OPTIONS
1795 #define TARGET_DEBUG_OPTIONS (sparc_debug & MASK_DEBUG_OPTIONS)
1797 /* By default, use the weakest memory model for the cpu. */
1798 #ifndef SUBTARGET_DEFAULT_MEMORY_MODEL
1799 #define SUBTARGET_DEFAULT_MEMORY_MODEL SMM_DEFAULT
1802 /* Define this to 1 if the FE_EXCEPT values defined in fenv.h start at 1. */
1803 #define SPARC_LOW_FE_EXCEPT_VALUES 0
1805 #define TARGET_SUPPORTS_WIDE_INT 1