1 ;; Machine description for SPARC.
2 ;; Copyright (C) 1987-2019 Free Software Foundation, Inc.
3 ;; Contributed by Michael Tiemann (tiemann@cygnus.com)
4 ;; 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 3, or (at your option)
14 ;; GCC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 (define_c_enum "unspec" [
105 (define_c_enum "unspecv" [
108 UNSPECV_SPECULATION_BARRIER
110 UNSPECV_PROBE_STACK_RANGE
215 (define_mode_iterator I [QI HI SI DI])
216 (define_mode_iterator P [(SI "TARGET_ARCH32") (DI "TARGET_ARCH64")])
217 (define_mode_iterator W [SI (DI "TARGET_ARCH64")])
218 (define_mode_iterator F [SF DF TF])
220 ;; The upper 32 fp regs on the v9 can't hold SFmode values. To deal with this
221 ;; a second register class, EXTRA_FP_REGS, exists for the v9 chip. The name
222 ;; is a bit of a misnomer as it covers all 64 fp regs. The corresponding
223 ;; constraint letter is 'e'. To avoid any confusion, 'e' is used instead of
224 ;; 'f' for all DF/TFmode values, including those that are specific to the v8.
226 ;; Attribute for cpu type.
227 ;; These must match the values of the enum processor_type in sparc-opts.h.
252 (const (symbol_ref "sparc_cpu_attr")))
254 ;; Attribute for the instruction set.
255 ;; At present we only need to distinguish v9/!v9, but for clarity we
256 ;; test TARGET_V8 too.
257 (define_attr "isa" "v7,v8,v9,sparclet"
259 (cond [(symbol_ref "TARGET_V9") (const_string "v9")
260 (symbol_ref "TARGET_V8") (const_string "v8")
261 (symbol_ref "TARGET_SPARCLET") (const_string "sparclet")]
262 (const_string "v7"))))
264 (define_attr "cpu_feature" "none,fpu,fpunotv9,v9,vis,vis3,vis4,vis4b"
265 (const_string "none"))
267 (define_attr "lra" "disabled,enabled"
268 (const_string "enabled"))
270 (define_attr "enabled" ""
271 (cond [(eq_attr "cpu_feature" "none")
272 (cond [(eq_attr "lra" "disabled") (symbol_ref "!TARGET_LRA")] (const_int 1))
273 (eq_attr "cpu_feature" "fpu") (symbol_ref "TARGET_FPU")
274 (eq_attr "cpu_feature" "fpunotv9") (symbol_ref "TARGET_FPU && !TARGET_V9")
275 (eq_attr "cpu_feature" "v9") (symbol_ref "TARGET_V9")
276 (eq_attr "cpu_feature" "vis") (symbol_ref "TARGET_VIS")
277 (eq_attr "cpu_feature" "vis3") (symbol_ref "TARGET_VIS3")
278 (eq_attr "cpu_feature" "vis4") (symbol_ref "TARGET_VIS4")
279 (eq_attr "cpu_feature" "vis4b") (symbol_ref "TARGET_VIS4B")]
282 ;; The SPARC instructions used by the backend are organized into a
283 ;; hierarchy using the insn attributes "type" and "subtype".
285 ;; The mnemonics used in the list below are the architectural names
286 ;; used in the Oracle SPARC Architecture specs. A / character
287 ;; separates the type from the subtype where appropriate. For
288 ;; brevity, text enclosed in {} denotes alternatives, while text
289 ;; enclosed in [] is optional.
291 ;; Please keep this list updated. It is of great help for keeping the
292 ;; correctness and coherence of the DFA schedulers.
295 ;; ialuX: ADD[X]C SUB[X]C
296 ;; shift: SLL[X] SRL[X] SRA[X]
297 ;; cmove: MOV{A,N,NE,E,G,LE,GE,L,GU,LEU,CC,CS,POS,NEG,VC,VS}
298 ;; MOVF{A,N,U,G,UG,L,UL,LG,NE,E,UE,GE,UGE,LE,ULE,O}
299 ;; MOVR{Z,LEZ,LZ,NZ,GZ,GEZ}
300 ;; compare: ADDcc ADDCcc ANDcc ORcc SUBcc SUBCcc XORcc XNORcc
301 ;; imul: MULX SMUL[cc] UMUL UMULXHI XMULX XMULXHI
304 ;; load/regular: LD{UB,UH,UW} LDFSR
305 ;; load/prefetch: PREFETCH
306 ;; fpload: LDF LDDF LDQF
307 ;; sload: LD{SB,SH,SW}
308 ;; store: ST{B,H,W,X} STFSR
309 ;; fpstore: STF STDF STQF
310 ;; cbcond: CWB{NE,E,G,LE,GE,L,GU,LEU,CC,CS,POS,NEG,VC,VS}
311 ;; CXB{NE,E,G,LE,GE,L,GU,LEU,CC,CS,POS,NEG,VC,VS}
312 ;; uncond_branch: BA BPA JMPL
313 ;; branch: B{NE,E,G,LE,GE,L,GU,LEU,CC,CS,POS,NEG,VC,VS}
314 ;; BP{NE,E,G,LE,GE,L,GU,LEU,CC,CS,POS,NEG,VC,VS}
315 ;; FB{U,G,UG,L,UL,LG,NE,BE,UE,GE,UGE,LE,ULE,O}
317 ;; return: RESTORE RETURN
318 ;; fpmove: FABS{s,d,q} FMOV{s,d,q} FNEG{s,d,q}
319 ;; fpcmove: FMOV{S,D,Q}{icc,xcc,fcc}
320 ;; fpcrmove: FMOVR{s,d,q}{Z,LEZ,LZ,NZ,GZ,GEZ}
321 ;; fp: FADD{s,d,q} FSUB{s,d,q} FHSUB{s,d} FNHADD{s,d} FNADD{s,d}
322 ;; FiTO{s,d,q} FsTO{i,x,d,q} FdTO{i,x,s,q} FxTO{d,s,q} FqTO{i,x,s,d}
323 ;; fpcmp: FCMP{s,d,q} FCMPE{s,d,q}
324 ;; fpmul: FMADD{s,d} FMSUB{s,d} FMUL{s,d,q} FNMADD{s,d}
325 ;; FNMSUB{s,d} FNMUL{s,d} FNsMULd FsMULd
327 ;; array: ARRAY{8,16,32}
329 ;; edge: EDGE{8,16,32}[L]cc
330 ;; edgen: EDGE{8,16,32}[L]n
332 ;; fpsqrts: FSQRT{s,q}
336 ;; fga/addsub64: FP{ADD,SUB}64
337 ;; fga/fpu: FCHKSM16 FEXPANd FMEAN16 FPMERGE
338 ;; FS{LL,RA,RL}{16,32}
339 ;; fga/maxmin: FP{MAX,MIN}[U]{8,16,32}
340 ;; fga/cmask: CMASK{8,16,32}
341 ;; fga/other: BSHUFFLE FALIGNDATAg FP{ADD,SUB}[S]{8,16,32}
342 ;; FP{ADD,SUB}US{8,16} DICTUNPACK
343 ;; gsr/reg: RDGSR WRGSR
344 ;; gsr/alignaddr: ALIGNADDRESS[_LITTLE]
345 ;; vismv/double: FSRC2d
346 ;; vismv/single: MOVwTOs FSRC2s
347 ;; vismv/movstouw: MOVsTOuw
348 ;; vismv/movxtod: MOVxTOd
349 ;; vismv/movdtox: MOVdTOx
350 ;; visl/single: F{AND,NAND,NOR,OR,NOT1}s
351 ;; F{AND,OR}NOT{1,2}s
352 ;; FONEs F{ZERO,XNOR,XOR}s FNOT2s
353 ;; visl/double: FONEd FZEROd FNOT1d F{OR,AND,XOR}d F{NOR,NAND,XNOR}d
354 ;; F{OR,AND}NOT1d F{OR,AND}NOT2d
355 ;; viscmp: FPCMP{LE,GT,NE,EQ}{8,16,32} FPCMPU{LE,GT,NE,EQ}{8,16,32}
356 ;; FPCMP{LE,GT,EQ,NE}{8,16,32}SHL FPCMPU{LE,GT,EQ,NE}{8,16,32}SHL
357 ;; FPCMPDE{8,16,32}SHL FPCMPUR{8,16,32}SHL
358 ;; fgm_pack: FPACKFIX FPACK{8,16,32}
359 ;; fgm_mul: FMUL8SUx16 FMUL8ULx16 FMUL8x16 FMUL8x16AL
360 ;; FMUL8x16AU FMULD8SUx16 FMULD8ULx16
367 uncond_branch,branch,call,sibcall,call_no_delay_slot,return,
368 cbcond,uncond_cbcond,
376 fga,visl,vismv,viscmp,
377 fgm_pack,fgm_mul,pdist,pdistn,edge,edgen,gsr,array,bmask,
380 multi,savew,flushw,iflush,trap,lzd"
381 (const_string "ialu"))
383 (define_attr "subtype"
384 "single,double,movstouw,movxtod,movdtox,
385 addsub64,cmask,fpu,maxmin,other,
388 (const_string "single"))
390 ;; True if branch/call has empty delay slot and will emit a nop in it
391 (define_attr "empty_delay_slot" "false,true"
392 (symbol_ref "(empty_delay_slot (insn)
393 ? EMPTY_DELAY_SLOT_TRUE : EMPTY_DELAY_SLOT_FALSE)"))
395 ;; True if we are making use of compare-and-branch instructions.
396 ;; True if we should emit a nop after a cbcond instruction
397 (define_attr "emit_cbcond_nop" "false,true"
398 (symbol_ref "(emit_cbcond_nop (insn)
399 ? EMIT_CBCOND_NOP_TRUE : EMIT_CBCOND_NOP_FALSE)"))
401 (define_attr "branch_type" "none,icc,fcc,reg"
402 (const_string "none"))
404 (define_attr "pic" "false,true"
405 (symbol_ref "(flag_pic != 0
406 ? PIC_TRUE : PIC_FALSE)"))
408 (define_attr "calls_alloca" "false,true"
409 (symbol_ref "(cfun->calls_alloca != 0
410 ? CALLS_ALLOCA_TRUE : CALLS_ALLOCA_FALSE)"))
412 (define_attr "calls_eh_return" "false,true"
413 (symbol_ref "(crtl->calls_eh_return != 0
414 ? CALLS_EH_RETURN_TRUE : CALLS_EH_RETURN_FALSE)"))
416 (define_attr "leaf_function" "false,true"
417 (symbol_ref "(crtl->uses_only_leaf_regs != 0
418 ? LEAF_FUNCTION_TRUE : LEAF_FUNCTION_FALSE)"))
420 (define_attr "delayed_branch" "false,true"
421 (symbol_ref "(flag_delayed_branch != 0
422 ? DELAYED_BRANCH_TRUE : DELAYED_BRANCH_FALSE)"))
424 (define_attr "flat" "false,true"
425 (symbol_ref "(TARGET_FLAT != 0
426 ? FLAT_TRUE : FLAT_FALSE)"))
428 (define_attr "fix_ut699" "false,true"
429 (symbol_ref "(sparc_fix_ut699 != 0
430 ? FIX_UT699_TRUE : FIX_UT699_FALSE)"))
432 (define_attr "fix_b2bst" "false,true"
433 (symbol_ref "(sparc_fix_b2bst != 0
434 ? FIX_B2BST_TRUE : FIX_B2BST_FALSE)"))
436 (define_attr "fix_lost_divsqrt" "false,true"
437 (symbol_ref "(sparc_fix_lost_divsqrt != 0
438 ? FIX_LOST_DIVSQRT_TRUE : FIX_LOST_DIVSQRT_FALSE)"))
440 (define_attr "fix_gr712rc" "false,true"
441 (symbol_ref "(sparc_fix_gr712rc != 0
442 ? FIX_GR712RC_TRUE : FIX_GR712RC_FALSE)"))
444 ;; Length (in # of insns).
445 ;; Beware that setting a length greater or equal to 3 for conditional branches
446 ;; has a side-effect (see output_cbranch and output_v9branch).
447 (define_attr "length" ""
448 (cond [(eq_attr "type" "uncond_branch,call")
449 (if_then_else (eq_attr "empty_delay_slot" "true")
452 (eq_attr "type" "sibcall")
453 (if_then_else (ior (eq_attr "leaf_function" "true")
454 (eq_attr "flat" "true"))
455 (if_then_else (eq_attr "empty_delay_slot" "true")
458 (if_then_else (eq_attr "empty_delay_slot" "true")
461 (eq_attr "branch_type" "icc")
462 (if_then_else (match_operand 0 "v9_comparison_operator" "")
463 (if_then_else (lt (pc) (match_dup 1))
464 (if_then_else (lt (minus (match_dup 1) (pc)) (const_int 260000))
465 (if_then_else (eq_attr "empty_delay_slot" "true")
468 (if_then_else (eq_attr "empty_delay_slot" "true")
471 (if_then_else (lt (minus (pc) (match_dup 1)) (const_int 260000))
472 (if_then_else (eq_attr "empty_delay_slot" "true")
475 (if_then_else (eq_attr "empty_delay_slot" "true")
478 (if_then_else (eq_attr "empty_delay_slot" "true")
481 (eq_attr "branch_type" "fcc")
482 (if_then_else (match_operand 0 "fcc0_register_operand" "")
483 (if_then_else (eq_attr "empty_delay_slot" "true")
484 (if_then_else (not (match_test "TARGET_V9"))
487 (if_then_else (not (match_test "TARGET_V9"))
490 (if_then_else (lt (pc) (match_dup 2))
491 (if_then_else (lt (minus (match_dup 2) (pc)) (const_int 260000))
492 (if_then_else (eq_attr "empty_delay_slot" "true")
495 (if_then_else (eq_attr "empty_delay_slot" "true")
498 (if_then_else (lt (minus (pc) (match_dup 2)) (const_int 260000))
499 (if_then_else (eq_attr "empty_delay_slot" "true")
502 (if_then_else (eq_attr "empty_delay_slot" "true")
505 (eq_attr "branch_type" "reg")
506 (if_then_else (lt (pc) (match_dup 2))
507 (if_then_else (lt (minus (match_dup 2) (pc)) (const_int 32000))
508 (if_then_else (eq_attr "empty_delay_slot" "true")
511 (if_then_else (eq_attr "empty_delay_slot" "true")
514 (if_then_else (lt (minus (pc) (match_dup 2)) (const_int 32000))
515 (if_then_else (eq_attr "empty_delay_slot" "true")
518 (if_then_else (eq_attr "empty_delay_slot" "true")
521 (eq_attr "type" "cbcond")
522 (if_then_else (lt (pc) (match_dup 3))
523 (if_then_else (lt (minus (match_dup 3) (pc)) (const_int 500))
524 (if_then_else (eq_attr "emit_cbcond_nop" "true")
528 (if_then_else (lt (minus (pc) (match_dup 3)) (const_int 500))
529 (if_then_else (eq_attr "emit_cbcond_nop" "true")
533 (eq_attr "type" "uncond_cbcond")
534 (if_then_else (lt (pc) (match_dup 0))
535 (if_then_else (lt (minus (match_dup 0) (pc)) (const_int 500))
536 (if_then_else (eq_attr "emit_cbcond_nop" "true")
540 (if_then_else (lt (minus (pc) (match_dup 0)) (const_int 500))
541 (if_then_else (eq_attr "emit_cbcond_nop" "true")
548 (define_attr "fptype" "single,double"
549 (const_string "single"))
551 ;; FP precision specific to the UT699.
552 (define_attr "fptype_ut699" "none,single"
553 (const_string "none"))
555 ;; UltraSPARC-III integer load type.
556 (define_attr "us3load_type" "2cycle,3cycle"
557 (const_string "2cycle"))
559 (define_asm_attributes
560 [(set_attr "length" "2")
561 (set_attr "type" "multi")])
563 ;; Attributes for branch scheduling
564 (define_attr "in_call_delay" "false,true"
565 (symbol_ref "(eligible_for_call_delay (insn)
566 ? IN_CALL_DELAY_TRUE : IN_CALL_DELAY_FALSE)"))
568 (define_attr "in_sibcall_delay" "false,true"
569 (symbol_ref "(eligible_for_sibcall_delay (insn)
570 ? IN_SIBCALL_DELAY_TRUE : IN_SIBCALL_DELAY_FALSE)"))
572 (define_attr "in_return_delay" "false,true"
573 (symbol_ref "(eligible_for_return_delay (insn)
574 ? IN_RETURN_DELAY_TRUE : IN_RETURN_DELAY_FALSE)"))
576 ;; ??? !v9: Should implement the notion of predelay slots for floating-point
577 ;; branches. This would allow us to remove the nop always inserted before
578 ;; a floating point branch.
580 ;; ??? It is OK for fill_simple_delay_slots to put load/store instructions
581 ;; in a delay slot, but it is not OK for fill_eager_delay_slots to do so.
582 ;; This is because doing so will add several pipeline stalls to the path
583 ;; that the load/store did not come from. Unfortunately, there is no way
584 ;; to prevent fill_eager_delay_slots from using load/store without completely
585 ;; disabling them. For the SPEC benchmark set, this is a serious lose,
586 ;; because it prevents us from moving back the final store of inner loops.
588 (define_attr "in_branch_delay" "false,true"
589 (cond [(eq_attr "type" "uncond_branch,branch,cbcond,uncond_cbcond,call,sibcall,call_no_delay_slot,multi")
590 (const_string "false")
591 (and (eq_attr "fix_lost_divsqrt" "true")
592 (eq_attr "type" "fpdivs,fpsqrts,fpdivd,fpsqrtd"))
593 (const_string "false")
594 (and (eq_attr "fix_b2bst" "true") (eq_attr "type" "store,fpstore"))
595 (const_string "false")
596 (and (eq_attr "fix_ut699" "true") (eq_attr "type" "load,sload"))
597 (const_string "false")
598 (and (eq_attr "fix_ut699" "true")
599 (and (eq_attr "type" "fpload,fp,fpmove,fpmul,fpdivs,fpsqrts")
600 (ior (eq_attr "fptype" "single")
601 (eq_attr "fptype_ut699" "single"))))
602 (const_string "false")
603 (eq_attr "length" "1")
604 (const_string "true")
605 ] (const_string "false")))
607 (define_attr "in_integer_branch_annul_delay" "false,true"
608 (cond [(and (eq_attr "fix_gr712rc" "true")
609 (eq_attr "type" "fp,fpcmp,fpmove,fpcmove,fpmul,
610 fpdivs,fpsqrts,fpdivd,fpsqrtd"))
611 (const_string "false")
612 (eq_attr "in_branch_delay" "true")
613 (const_string "true")
614 ] (const_string "false")))
616 (define_delay (eq_attr "type" "call")
617 [(eq_attr "in_call_delay" "true") (nil) (nil)])
619 (define_delay (eq_attr "type" "sibcall")
620 [(eq_attr "in_sibcall_delay" "true") (nil) (nil)])
622 (define_delay (eq_attr "type" "return")
623 [(eq_attr "in_return_delay" "true") (nil) (nil)])
625 (define_delay (and (eq_attr "type" "branch")
626 (not (eq_attr "branch_type" "icc")))
627 [(eq_attr "in_branch_delay" "true") (nil) (eq_attr "in_branch_delay" "true")])
629 (define_delay (and (eq_attr "type" "branch")
630 (eq_attr "branch_type" "icc"))
631 [(eq_attr "in_branch_delay" "true") (nil)
632 (eq_attr "in_integer_branch_annul_delay" "true")])
634 (define_delay (eq_attr "type" "uncond_branch")
635 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
638 ;; Include SPARC DFA schedulers
640 (include "cypress.md")
641 (include "supersparc.md")
642 (include "hypersparc.md")
644 (include "sparclet.md")
645 (include "ultra1_2.md")
646 (include "ultra3.md")
647 (include "niagara.md")
648 (include "niagara2.md")
649 (include "niagara4.md")
650 (include "niagara7.md")
654 ;; Operand and operator predicates and constraints
656 (include "predicates.md")
657 (include "constraints.md")
660 ;; Compare instructions.
662 ;; These are just the DEFINE_INSNs to match the patterns and the
663 ;; DEFINE_SPLITs for some of the scc insns that actually require
664 ;; more than one machine instruction. DEFINE_EXPANDs are further down.
666 (define_insn "*cmpsi_insn"
667 [(set (reg:CC CC_REG)
668 (compare:CC (match_operand:SI 0 "register_operand" "r")
669 (match_operand:SI 1 "arith_operand" "rI")))]
672 [(set_attr "type" "compare")])
674 (define_insn "*cmpdi_sp64"
675 [(set (reg:CCX CC_REG)
676 (compare:CCX (match_operand:DI 0 "register_operand" "r")
677 (match_operand:DI 1 "arith_operand" "rI")))]
680 [(set_attr "type" "compare")])
682 (define_insn "*cmpsi_sne"
683 [(set (reg:CCC CC_REG)
684 (compare:CCC (not:SI (match_operand:SI 0 "arith_operand" "rI"))
688 [(set_attr "type" "compare")])
690 (define_insn "*cmpdi_sne"
691 [(set (reg:CCXC CC_REG)
692 (compare:CCXC (not:DI (match_operand:DI 0 "arith_operand" "rI"))
696 [(set_attr "type" "compare")])
698 (define_insn "*cmpsf_fpe"
699 [(set (match_operand:CCFPE 0 "fcc_register_operand" "=c")
700 (compare:CCFPE (match_operand:SF 1 "register_operand" "f")
701 (match_operand:SF 2 "register_operand" "f")))]
705 return "fcmpes\t%0, %1, %2";
706 return "fcmpes\t%1, %2";
708 [(set_attr "type" "fpcmp")])
710 (define_insn "*cmpdf_fpe"
711 [(set (match_operand:CCFPE 0 "fcc_register_operand" "=c")
712 (compare:CCFPE (match_operand:DF 1 "register_operand" "e")
713 (match_operand:DF 2 "register_operand" "e")))]
717 return "fcmped\t%0, %1, %2";
718 return "fcmped\t%1, %2";
720 [(set_attr "type" "fpcmp")
721 (set_attr "fptype" "double")])
723 (define_insn "*cmptf_fpe"
724 [(set (match_operand:CCFPE 0 "fcc_register_operand" "=c")
725 (compare:CCFPE (match_operand:TF 1 "register_operand" "e")
726 (match_operand:TF 2 "register_operand" "e")))]
727 "TARGET_FPU && TARGET_HARD_QUAD"
730 return "fcmpeq\t%0, %1, %2";
731 return "fcmpeq\t%1, %2";
733 [(set_attr "type" "fpcmp")])
735 (define_insn "*cmpsf_fp"
736 [(set (match_operand:CCFP 0 "fcc_register_operand" "=c")
737 (compare:CCFP (match_operand:SF 1 "register_operand" "f")
738 (match_operand:SF 2 "register_operand" "f")))]
742 return "fcmps\t%0, %1, %2";
743 return "fcmps\t%1, %2";
745 [(set_attr "type" "fpcmp")])
747 (define_insn "*cmpdf_fp"
748 [(set (match_operand:CCFP 0 "fcc_register_operand" "=c")
749 (compare:CCFP (match_operand:DF 1 "register_operand" "e")
750 (match_operand:DF 2 "register_operand" "e")))]
754 return "fcmpd\t%0, %1, %2";
755 return "fcmpd\t%1, %2";
757 [(set_attr "type" "fpcmp")
758 (set_attr "fptype" "double")])
760 (define_insn "*cmptf_fp"
761 [(set (match_operand:CCFP 0 "fcc_register_operand" "=c")
762 (compare:CCFP (match_operand:TF 1 "register_operand" "e")
763 (match_operand:TF 2 "register_operand" "e")))]
764 "TARGET_FPU && TARGET_HARD_QUAD"
767 return "fcmpq\t%0, %1, %2";
768 return "fcmpq\t%1, %2";
770 [(set_attr "type" "fpcmp")])
772 ;; Next come the scc insns.
774 ;; Note that the boolean result (operand 0) takes on DImode
775 ;; (not SImode) when TARGET_ARCH64.
777 (define_expand "cstoresi4"
778 [(use (match_operator 1 "comparison_operator"
779 [(match_operand:SI 2 "compare_operand" "")
780 (match_operand:SI 3 "arith_operand" "")]))
781 (clobber (match_operand:SI 0 "cstore_result_operand"))]
784 if (GET_CODE (operands[2]) == ZERO_EXTRACT && operands[3] != const0_rtx)
785 operands[2] = force_reg (SImode, operands[2]);
786 if (emit_scc_insn (operands)) DONE; else FAIL;
789 (define_expand "cstoredi4"
790 [(use (match_operator 1 "comparison_operator"
791 [(match_operand:DI 2 "compare_operand" "")
792 (match_operand:DI 3 "arith_operand" "")]))
793 (clobber (match_operand:SI 0 "cstore_result_operand"))]
796 if (GET_CODE (operands[2]) == ZERO_EXTRACT && operands[3] != const0_rtx)
797 operands[2] = force_reg (DImode, operands[2]);
798 if (emit_scc_insn (operands)) DONE; else FAIL;
801 (define_expand "cstore<F:mode>4"
802 [(use (match_operator 1 "comparison_operator"
803 [(match_operand:F 2 "register_operand" "")
804 (match_operand:F 3 "register_operand" "")]))
805 (clobber (match_operand:SI 0 "cstore_result_operand"))]
808 if (emit_scc_insn (operands)) DONE; else FAIL;
811 ;; The SNE and SEQ patterns are special because they can be done
812 ;; without any branching and do not involve a COMPARE.
814 (define_insn_and_split "*snesi<W:mode>_zero"
815 [(set (match_operand:W 0 "register_operand" "=r")
816 (ne:W (match_operand:SI 1 "register_operand" "r")
818 (clobber (reg:CC CC_REG))]
822 [(set (reg:CCC CC_REG) (compare:CCC (not:SI (match_dup 1)) (const_int -1)))
823 (set (match_dup 0) (ltu:W (reg:CCC CC_REG) (const_int 0)))]
825 [(set_attr "length" "2")])
827 (define_insn_and_split "*neg_snesi<W:mode>_zero"
828 [(set (match_operand:W 0 "register_operand" "=r")
829 (neg:W (ne:W (match_operand:SI 1 "register_operand" "r")
831 (clobber (reg:CC CC_REG))]
835 [(set (reg:CCC CC_REG) (compare:CCC (not:SI (match_dup 1)) (const_int -1)))
836 (set (match_dup 0) (neg:W (ltu:W (reg:CCC CC_REG) (const_int 0))))]
838 [(set_attr "length" "2")])
840 (define_insn_and_split "*snedi<W:mode>_zero"
841 [(set (match_operand:W 0 "register_operand" "=&r")
842 (ne:W (match_operand:DI 1 "register_operand" "r")
844 "TARGET_ARCH64 && !TARGET_VIS3"
846 "&& !reg_overlap_mentioned_p (operands[1], operands[0])"
847 [(set (match_dup 0) (const_int 0))
848 (set (match_dup 0) (if_then_else:W (ne:DI (match_dup 1) (const_int 0))
852 [(set_attr "length" "2")])
854 (define_insn_and_split "*snedi<W:mode>_zero_vis3"
855 [(set (match_operand:W 0 "register_operand" "=r")
856 (ne:W (match_operand:DI 1 "register_operand" "r")
858 (clobber (reg:CCX CC_REG))]
859 "TARGET_ARCH64 && TARGET_VIS3"
862 [(set (reg:CCXC CC_REG) (compare:CCXC (not:DI (match_dup 1)) (const_int -1)))
863 (set (match_dup 0) (ltu:W (reg:CCXC CC_REG) (const_int 0)))]
865 [(set_attr "length" "2")])
867 (define_insn_and_split "*neg_snedi<W:mode>_zero"
868 [(set (match_operand:W 0 "register_operand" "=&r")
869 (neg:W (ne:W (match_operand:DI 1 "register_operand" "r")
871 "TARGET_ARCH64 && !TARGET_SUBXC"
873 "&& !reg_overlap_mentioned_p (operands[1], operands[0])"
874 [(set (match_dup 0) (const_int 0))
875 (set (match_dup 0) (if_then_else:W (ne:DI (match_dup 1) (const_int 0))
879 [(set_attr "length" "2")])
881 (define_insn_and_split "*neg_snedi<W:mode>_zero_subxc"
882 [(set (match_operand:W 0 "register_operand" "=&r")
883 (neg:W (ne:W (match_operand:DI 1 "register_operand" "r")
885 (clobber (reg:CCX CC_REG))]
886 "TARGET_ARCH64 && TARGET_SUBXC"
889 [(set (reg:CCXC CC_REG) (compare:CCXC (not:DI (match_dup 1)) (const_int -1)))
890 (set (match_dup 0) (neg:W (ltu:W (reg:CCXC CC_REG) (const_int 0))))]
892 [(set_attr "length" "2")])
894 (define_insn_and_split "*seqsi<W:mode>_zero"
895 [(set (match_operand:W 0 "register_operand" "=r")
896 (eq:W (match_operand:SI 1 "register_operand" "r")
898 (clobber (reg:CC CC_REG))]
902 [(set (reg:CCC CC_REG) (compare:CCC (not:SI (match_dup 1)) (const_int -1)))
903 (set (match_dup 0) (geu:W (reg:CCC CC_REG) (const_int 0)))]
905 [(set_attr "length" "2")])
907 (define_insn_and_split "*neg_seqsi<W:mode>_zero"
908 [(set (match_operand:W 0 "register_operand" "=r")
909 (neg:W (eq:W (match_operand:SI 1 "register_operand" "r")
911 (clobber (reg:CC CC_REG))]
915 [(set (reg:CCC CC_REG) (compare:CCC (not:SI (match_dup 1)) (const_int -1)))
916 (set (match_dup 0) (neg:W (geu:W (reg:CCC CC_REG) (const_int 0))))]
918 [(set_attr "length" "2")])
920 (define_insn_and_split "*seqdi<W:mode>_zero"
921 [(set (match_operand:W 0 "register_operand" "=&r")
922 (eq:W (match_operand:DI 1 "register_operand" "r")
926 "&& !reg_overlap_mentioned_p (operands[1], operands[0])"
927 [(set (match_dup 0) (const_int 0))
928 (set (match_dup 0) (if_then_else:W (eq:DI (match_dup 1) (const_int 0))
932 [(set_attr "length" "2")])
934 (define_insn_and_split "*neg_seqdi<W:mode>_zero"
935 [(set (match_operand:W 0 "register_operand" "=&r")
936 (neg:W (eq:W (match_operand:DI 1 "register_operand" "r")
940 "&& !reg_overlap_mentioned_p (operands[1], operands[0])"
941 [(set (match_dup 0) (const_int 0))
942 (set (match_dup 0) (if_then_else:W (eq:DI (match_dup 1) (const_int 0))
946 [(set_attr "length" "2")])
948 ;; We can also do (x + (i == 0)) and related, so put them in.
950 (define_insn_and_split "*plus_snesi<W:mode>_zero"
951 [(set (match_operand:W 0 "register_operand" "=r")
952 (plus:W (ne:W (match_operand:SI 1 "register_operand" "r")
954 (match_operand:W 2 "register_operand" "r")))
955 (clobber (reg:CC CC_REG))]
959 [(set (reg:CCC CC_REG) (compare:CCC (not:SI (match_dup 1)) (const_int -1)))
960 (set (match_dup 0) (plus:W (ltu:W (reg:CCC CC_REG) (const_int 0))
963 [(set_attr "length" "2")])
965 (define_insn_and_split "*plus_plus_snesi<W:mode>_zero"
966 [(set (match_operand:W 0 "register_operand" "=r")
967 (plus:W (plus:W (ne:W (match_operand:SI 1 "register_operand" "r")
969 (match_operand:W 2 "register_operand" "r"))
970 (match_operand:W 3 "register_operand" "r")))
971 (clobber (reg:CC CC_REG))]
975 [(set (reg:CCC CC_REG) (compare:CCC (not:SI (match_dup 1)) (const_int -1)))
976 (set (match_dup 0) (plus:W (plus:W (ltu:W (reg:CCC CC_REG) (const_int 0))
980 [(set_attr "length" "2")])
982 (define_insn_and_split "*plus_snedi<W:mode>_zero"
983 [(set (match_operand:W 0 "register_operand" "=r")
984 (plus:W (ne:W (match_operand:DI 1 "register_operand" "r")
986 (match_operand:W 2 "register_operand" "r")))
987 (clobber (reg:CCX CC_REG))]
988 "TARGET_ARCH64 && TARGET_VIS3"
991 [(set (reg:CCXC CC_REG) (compare:CCXC (not:DI (match_dup 1)) (const_int -1)))
992 (set (match_dup 0) (plus:W (ltu:W (reg:CCXC CC_REG) (const_int 0))
995 [(set_attr "length" "2")])
997 (define_insn_and_split "*plus_plus_snedi<W:mode>_zero"
998 [(set (match_operand:W 0 "register_operand" "=r")
999 (plus:W (plus:W (ne:W (match_operand:DI 1 "register_operand" "r")
1001 (match_operand:W 2 "register_operand" "r"))
1002 (match_operand:W 3 "register_operand" "r")))
1003 (clobber (reg:CCX CC_REG))]
1004 "TARGET_ARCH64 && TARGET_VIS3"
1007 [(set (reg:CCXC CC_REG) (compare:CCXC (not:DI (match_dup 1)) (const_int -1)))
1008 (set (match_dup 0) (plus:W (plus:W (ltu:W (reg:CCXC CC_REG) (const_int 0))
1012 [(set_attr "length" "2")])
1014 (define_insn_and_split "*minus_snesi<W:mode>_zero"
1015 [(set (match_operand:W 0 "register_operand" "=r")
1016 (minus:W (match_operand:W 2 "register_operand" "r")
1017 (ne:W (match_operand:SI 1 "register_operand" "r")
1019 (clobber (reg:CC CC_REG))]
1023 [(set (reg:CCC CC_REG) (compare:CCC (not:SI (match_dup 1)) (const_int -1)))
1024 (set (match_dup 0) (minus:W (match_dup 2)
1025 (ltu:W (reg:CCC CC_REG) (const_int 0))))]
1027 [(set_attr "length" "2")])
1029 (define_insn_and_split "*minus_minus_snesi<W:mode>_zero"
1030 [(set (match_operand:W 0 "register_operand" "=r")
1031 (minus:W (minus:W (match_operand:W 2 "register_operand" "r")
1032 (ne:W (match_operand:SI 1 "register_operand" "r")
1034 (match_operand:W 3 "register_operand" "r")))
1035 (clobber (reg:CC CC_REG))]
1039 [(set (reg:CCC CC_REG) (compare:CCC (not:SI (match_dup 1)) (const_int -1)))
1040 (set (match_dup 0) (minus:W (minus:W (match_dup 2)
1041 (ltu:W (reg:CCC CC_REG) (const_int 0)))
1044 [(set_attr "length" "2")])
1046 (define_insn_and_split "*minus_snedi<W:mode>_zero"
1047 [(set (match_operand:W 0 "register_operand" "=r")
1048 (minus:W (match_operand:W 2 "register_operand" "r")
1049 (ne:W (match_operand:DI 1 "register_operand" "r")
1051 (clobber (reg:CCX CC_REG))]
1052 "TARGET_ARCH64 && TARGET_SUBXC"
1055 [(set (reg:CCXC CC_REG) (compare:CCXC (not:DI (match_dup 1)) (const_int -1)))
1056 (set (match_dup 0) (minus:W (match_dup 2)
1057 (ltu:W (reg:CCXC CC_REG) (const_int 0))))]
1059 [(set_attr "length" "2")])
1061 (define_insn_and_split "*minus_minus_snedi<W:mode>_zero"
1062 [(set (match_operand:W 0 "register_operand" "=r")
1063 (minus:W (minus:W (match_operand:W 2 "register_operand" "r")
1064 (ne:W (match_operand:DI 1 "register_operand" "r")
1066 (match_operand:W 3 "register_operand" "r")))
1067 (clobber (reg:CCX CC_REG))]
1068 "TARGET_ARCH64 && TARGET_SUBXC"
1071 [(set (reg:CCXC CC_REG) (compare:CCXC (not:DI (match_dup 1)) (const_int -1)))
1072 (set (match_dup 0) (minus:W (minus:W (match_dup 2)
1073 (ltu:W (reg:CCXC CC_REG) (const_int 0)))
1076 [(set_attr "length" "2")])
1078 (define_insn_and_split "*plus_seqsi<W:mode>_zero"
1079 [(set (match_operand:W 0 "register_operand" "=r")
1080 (plus:W (eq:W (match_operand:SI 1 "register_operand" "r")
1082 (match_operand:W 2 "register_operand" "r")))
1083 (clobber (reg:CC CC_REG))]
1087 [(set (reg:CCC CC_REG) (compare:CCC (not:SI (match_dup 1)) (const_int -1)))
1088 (set (match_dup 0) (plus:W (geu:W (reg:CCC CC_REG) (const_int 0))
1091 [(set_attr "length" "2")])
1093 (define_insn_and_split "*minus_seqsi<W:mode>_zero"
1094 [(set (match_operand:W 0 "register_operand" "=r")
1095 (minus:W (match_operand:W 2 "register_operand" "r")
1096 (eq:W (match_operand:SI 1 "register_operand" "r")
1098 (clobber (reg:CC CC_REG))]
1102 [(set (reg:CCC CC_REG) (compare:CCC (not:SI (match_dup 1)) (const_int -1)))
1103 (set (match_dup 0) (minus:W (match_dup 2)
1104 (geu:W (reg:CCC CC_REG) (const_int 0))))]
1106 [(set_attr "length" "2")])
1108 ;; We can also do GEU and LTU directly, but these operate after a compare.
1110 (define_insn "*sltu<W:mode>_insn"
1111 [(set (match_operand:W 0 "register_operand" "=r")
1112 (ltu:W (match_operand 1 "icc_register_operand" "X") (const_int 0)))]
1113 "GET_MODE (operands[1]) == CCmode || GET_MODE (operands[1]) == CCCmode"
1115 [(set_attr "type" "ialuX")])
1117 (define_insn "*plus_sltu<W:mode>"
1118 [(set (match_operand:W 0 "register_operand" "=r")
1119 (plus:W (ltu:W (match_operand 2 "icc_register_operand" "X")
1121 (match_operand:W 1 "arith_operand" "rI")))]
1122 "GET_MODE (operands[2]) == CCmode || GET_MODE (operands[2]) == CCCmode"
1123 "addx\t%%g0, %1, %0"
1124 [(set_attr "type" "ialuX")])
1126 (define_insn "*plus_plus_sltu<W:mode>"
1127 [(set (match_operand:W 0 "register_operand" "=r")
1128 (plus:W (plus:W (ltu:W (match_operand 3 "icc_register_operand" "X")
1130 (match_operand:W 1 "register_operand" "%r"))
1131 (match_operand:W 2 "arith_operand" "rI")))]
1132 "GET_MODE (operands[3]) == CCmode || GET_MODE (operands[3]) == CCCmode"
1134 [(set_attr "type" "ialuX")])
1136 (define_insn "*neg_sgeu<W:mode>"
1137 [(set (match_operand:W 0 "register_operand" "=r")
1138 (neg:W (geu:W (match_operand 1 "icc_register_operand" "X")
1140 "GET_MODE (operands[1]) == CCmode || GET_MODE (operands[1]) == CCCmode"
1141 "addx\t%%g0, -1, %0"
1142 [(set_attr "type" "ialuX")])
1144 (define_insn "*neg_sgeusidi"
1145 [(set (match_operand:DI 0 "register_operand" "=r")
1146 (sign_extend:DI (neg:SI (geu:SI (match_operand 1 "icc_register_operand" "X")
1149 && (GET_MODE (operands[1]) == CCmode || GET_MODE (operands[1]) == CCCmode)"
1150 "addx\t%%g0, -1, %0"
1151 [(set_attr "type" "ialuX")])
1153 (define_insn "*minus_sgeu<W:mode>"
1154 [(set (match_operand:W 0 "register_operand" "=r")
1155 (minus:W (match_operand:W 1 "register_operand" "r")
1156 (geu:W (match_operand 2 "icc_register_operand" "X")
1158 "GET_MODE (operands[2]) == CCmode || GET_MODE (operands[2]) == CCCmode"
1160 [(set_attr "type" "ialuX")])
1162 (define_insn "*addx<W:mode>"
1163 [(set (match_operand:W 0 "register_operand" "=r")
1164 (plus:W (plus:W (match_operand:W 1 "register_operand" "%r")
1165 (match_operand:W 2 "arith_operand" "rI"))
1166 (ltu:W (match_operand 3 "icc_register_operand" "X")
1168 "GET_MODE (operands[3]) == CCmode || GET_MODE (operands[3]) == CCCmode"
1170 [(set_attr "type" "ialuX")])
1172 (define_insn "*sltu<W:mode>_insn_vis3"
1173 [(set (match_operand:W 0 "register_operand" "=r")
1174 (ltu:W (match_operand 1 "icc_register_operand" "X") (const_int 0)))]
1175 "TARGET_ARCH64 && TARGET_VIS3
1176 && (GET_MODE (operands[1]) == CCXmode || GET_MODE (operands[1]) == CCXCmode)"
1177 "addxc\t%%g0, %%g0, %0"
1178 [(set_attr "type" "ialuX")])
1180 (define_insn "*plus_sltu<W:mode>_vis3"
1181 [(set (match_operand:W 0 "register_operand" "=r")
1182 (plus:W (ltu:W (match_operand 2 "icc_register_operand" "X")
1184 (match_operand:W 1 "register_operand" "r")))]
1185 "TARGET_ARCH64 && TARGET_VIS3
1186 && (GET_MODE (operands[2]) == CCXmode || GET_MODE (operands[2]) == CCXCmode)"
1187 "addxc\t%%g0, %1, %0"
1188 [(set_attr "type" "ialuX")])
1190 (define_insn "*plus_plus_sltu<W:mode>_vis3"
1191 [(set (match_operand:W 0 "register_operand" "=r")
1192 (plus:W (plus:W (ltu:W (match_operand 3 "icc_register_operand" "X")
1194 (match_operand:W 1 "register_operand" "%r"))
1195 (match_operand:W 2 "register_operand" "r")))]
1196 "TARGET_ARCH64 && TARGET_VIS3
1197 && (GET_MODE (operands[3]) == CCXmode || GET_MODE (operands[3]) == CCXCmode)"
1199 [(set_attr "type" "ialuX")])
1201 (define_insn "*addxc<W:mode>"
1202 [(set (match_operand:W 0 "register_operand" "=r")
1203 (plus:W (plus:W (match_operand:W 1 "register_operand" "%r")
1204 (match_operand:W 2 "register_operand" "r"))
1205 (ltu:W (match_operand 3 "icc_register_operand" "X")
1207 "TARGET_ARCH64 && TARGET_VIS3
1208 && (GET_MODE (operands[3]) == CCXmode || GET_MODE (operands[3]) == CCXCmode)"
1210 [(set_attr "type" "ialuX")])
1212 (define_insn "*neg_sltu<W:mode>"
1213 [(set (match_operand:W 0 "register_operand" "=r")
1214 (neg:W (ltu:W (match_operand 1 "icc_register_operand" "X")
1216 "GET_MODE (operands[1]) == CCmode || GET_MODE (operands[1]) == CCCmode"
1218 [(set_attr "type" "ialuX")])
1220 (define_insn "*neg_sltusidi"
1221 [(set (match_operand:DI 0 "register_operand" "=r")
1222 (sign_extend:DI (neg:SI (ltu:SI (match_operand 1 "icc_register_operand" "X")
1225 && (GET_MODE (operands[1]) == CCmode || GET_MODE (operands[1]) == CCCmode)"
1227 [(set_attr "type" "ialuX")])
1229 (define_insn "*minus_neg_sltu<W:mode>"
1230 [(set (match_operand:W 0 "register_operand" "=r")
1231 (minus:W (neg:W (ltu:W (match_operand 2 "icc_register_operand" "X")
1233 (match_operand:W 1 "arith_operand" "rI")))]
1234 "GET_MODE (operands[2]) == CCmode || GET_MODE (operands[2]) == CCCmode"
1235 "subx\t%%g0, %1, %0"
1236 [(set_attr "type" "ialuX")])
1238 (define_insn "*neg_plus_sltu<W:mode>"
1239 [(set (match_operand:W 0 "register_operand" "=r")
1240 (neg:W (plus:W (ltu:W (match_operand 2 "icc_register_operand" "X")
1242 (match_operand:W 1 "arith_operand" "rI"))))]
1243 "GET_MODE (operands[2]) == CCmode || GET_MODE (operands[2]) == CCCmode"
1244 "subx\t%%g0, %1, %0"
1245 [(set_attr "type" "ialuX")])
1247 (define_insn "*minus_sltu<W:mode>"
1248 [(set (match_operand:W 0 "register_operand" "=r")
1249 (minus:W (match_operand:W 1 "register_operand" "r")
1250 (ltu:W (match_operand 2 "icc_register_operand" "X")
1252 "GET_MODE (operands[2]) == CCmode || GET_MODE (operands[2]) == CCCmode"
1254 [(set_attr "type" "ialuX")])
1256 (define_insn "*minus_minus_sltu<W:mode>"
1257 [(set (match_operand:W 0 "register_operand" "=r")
1258 (minus:W (minus:W (match_operand:W 1 "register_or_zero_operand" "rJ")
1259 (ltu:W (match_operand 3 "icc_register_operand" "X")
1261 (match_operand:W 2 "arith_operand" "rI")))]
1262 "GET_MODE (operands[3]) == CCmode || GET_MODE (operands[3]) == CCCmode"
1264 [(set_attr "type" "ialuX")])
1266 (define_insn "*sgeu<W:mode>_insn"
1267 [(set (match_operand:W 0 "register_operand" "=r")
1268 (geu:W (match_operand 1 "icc_register_operand" "X") (const_int 0)))]
1269 "GET_MODE (operands[1]) == CCmode || GET_MODE (operands[1]) == CCCmode"
1270 "subx\t%%g0, -1, %0"
1271 [(set_attr "type" "ialuX")])
1273 (define_insn "*plus_sgeu<W:mode>"
1274 [(set (match_operand:W 0 "register_operand" "=r")
1275 (plus:W (geu:W (match_operand 2 "icc_register_operand" "X")
1277 (match_operand:W 1 "register_operand" "r")))]
1278 "GET_MODE (operands[2]) == CCmode || GET_MODE (operands[2]) == CCCmode"
1280 [(set_attr "type" "ialuX")])
1282 (define_insn "*subx<W:mode>"
1283 [(set (match_operand:W 0 "register_operand" "=r")
1284 (minus:W (minus:W (match_operand:W 1 "register_or_zero_operand" "rJ")
1285 (match_operand:W 2 "arith_operand" "rI"))
1286 (ltu:W (match_operand 3 "icc_register_operand" "X")
1288 "GET_MODE (operands[3]) == CCmode || GET_MODE (operands[3]) == CCCmode"
1290 [(set_attr "type" "ialuX")])
1292 (define_insn "*neg_sltu<W:mode>_subxc"
1293 [(set (match_operand:W 0 "register_operand" "=r")
1294 (neg:W (ltu:W (match_operand 1 "icc_register_operand" "X")
1296 "TARGET_ARCH64 && TARGET_SUBXC
1297 && (GET_MODE (operands[1]) == CCXmode || GET_MODE (operands[1]) == CCXCmode)"
1298 "subxc\t%%g0, %%g0, %0"
1299 [(set_attr "type" "ialuX")])
1301 (define_insn "*minus_neg_sltu<W:mode>_subxc"
1302 [(set (match_operand:W 0 "register_operand" "=r")
1303 (minus:W (neg:W (ltu:W (match_operand 2 "icc_register_operand" "X")
1305 (match_operand:W 1 "register_operand" "r")))]
1306 "TARGET_ARCH64 && TARGET_SUBXC
1307 && (GET_MODE (operands[2]) == CCXmode || GET_MODE (operands[2]) == CCXCmode)"
1308 "subxc\t%%g0, %1, %0"
1309 [(set_attr "type" "ialuX")])
1311 (define_insn "*neg_plus_sltu<W:mode>_subxc"
1312 [(set (match_operand:W 0 "register_operand" "=r")
1313 (neg:W (plus:W (ltu:W (match_operand 2 "icc_register_operand" "X")
1315 (match_operand:W 1 "register_operand" "r"))))]
1316 "TARGET_ARCH64 && TARGET_SUBXC
1317 && (GET_MODE (operands[2]) == CCXmode || GET_MODE (operands[2]) == CCXCmode)"
1318 "subxc\t%%g0, %1, %0"
1319 [(set_attr "type" "ialuX")])
1321 (define_insn "*minus_sltu<W:mode>_subxc"
1322 [(set (match_operand:W 0 "register_operand" "=r")
1323 (minus:W (match_operand:W 1 "register_operand" "r")
1324 (ltu:W (match_operand 2 "icc_register_operand" "X")
1326 "TARGET_ARCH64 && TARGET_SUBXC
1327 && (GET_MODE (operands[2]) == CCXmode || GET_MODE (operands[2]) == CCXCmode)"
1328 "subxc\t%1, %%g0, %0"
1329 [(set_attr "type" "ialuX")])
1331 (define_insn "*minus_minus_sltu<W:mode>_subxc"
1332 [(set (match_operand:W 0 "register_operand" "=r")
1333 (minus:W (minus:W (match_operand:W 1 "register_or_zero_operand" "rJ")
1334 (ltu:W (match_operand 3 "icc_register_operand" "X")
1336 (match_operand:W 2 "register_operand" "r")))]
1337 "TARGET_ARCH64 && TARGET_SUBXC
1338 && (GET_MODE (operands[3]) == CCXmode || GET_MODE (operands[3]) == CCXCmode)"
1339 "subxc\t%r1, %2, %0"
1340 [(set_attr "type" "ialuX")])
1342 (define_insn "*subxc<W:mode>"
1343 [(set (match_operand:W 0 "register_operand" "=r")
1344 (minus:W (minus:W (match_operand:W 1 "register_or_zero_operand" "rJ")
1345 (match_operand:W 2 "register_operand" "r"))
1346 (ltu:W (match_operand 3 "icc_register_operand" "X")
1348 "TARGET_ARCH64 && TARGET_SUBXC
1349 && (GET_MODE (operands[3]) == CCXmode || GET_MODE (operands[3]) == CCXCmode)"
1350 "subxc\t%r1, %2, %0"
1351 [(set_attr "type" "ialuX")])
1354 [(set (match_operand:W 0 "register_operand" "")
1355 (match_operator:W 1 "icc_comparison_operator"
1356 [(match_operand 2 "icc_register_operand" "") (const_int 0)]))]
1358 /* 64-bit LTU is better implemented using addxc with VIS3. */
1359 && !(GET_CODE (operands[1]) == LTU
1360 && (GET_MODE (operands[2]) == CCXmode
1361 || GET_MODE (operands[2]) == CCXCmode)
1363 /* 32-bit LTU/GEU are better implemented using addx/subx. */
1364 && !((GET_CODE (operands[1]) == LTU || GET_CODE (operands[1]) == GEU)
1365 && (GET_MODE (operands[2]) == CCmode
1366 || GET_MODE (operands[2]) == CCCmode))"
1367 [(set (match_dup 0) (const_int 0))
1369 (if_then_else:SI (match_op_dup:W 1 [(match_dup 2) (const_int 0)])
1374 ;; These control RTL generation for conditional jump insns
1376 (define_expand "cbranchcc4"
1378 (if_then_else (match_operator 0 "comparison_operator"
1379 [(match_operand 1 "compare_operand" "")
1380 (match_operand 2 "const_zero_operand" "")])
1381 (label_ref (match_operand 3 "" ""))
1386 (define_expand "cbranchsi4"
1387 [(use (match_operator 0 "comparison_operator"
1388 [(match_operand:SI 1 "compare_operand" "")
1389 (match_operand:SI 2 "arith_operand" "")]))
1390 (use (match_operand 3 ""))]
1393 if (GET_CODE (operands[1]) == ZERO_EXTRACT && operands[2] != const0_rtx)
1394 operands[1] = force_reg (SImode, operands[1]);
1395 emit_conditional_branch_insn (operands);
1399 (define_expand "cbranchdi4"
1400 [(use (match_operator 0 "comparison_operator"
1401 [(match_operand:DI 1 "compare_operand" "")
1402 (match_operand:DI 2 "arith_operand" "")]))
1403 (use (match_operand 3 ""))]
1406 if (GET_CODE (operands[1]) == ZERO_EXTRACT && operands[2] != const0_rtx)
1407 operands[1] = force_reg (DImode, operands[1]);
1408 emit_conditional_branch_insn (operands);
1412 (define_expand "cbranch<F:mode>4"
1413 [(use (match_operator 0 "comparison_operator"
1414 [(match_operand:F 1 "register_operand" "")
1415 (match_operand:F 2 "register_operand" "")]))
1416 (use (match_operand 3 ""))]
1419 emit_conditional_branch_insn (operands);
1424 ;; Now match both normal and inverted jump.
1426 ;; XXX fpcmp nop braindamage
1427 (define_insn "*normal_branch"
1429 (if_then_else (match_operator 0 "icc_comparison_operator"
1430 [(reg CC_REG) (const_int 0)])
1431 (label_ref (match_operand 1 "" ""))
1435 return output_cbranch (operands[0], operands[1], 1, 0,
1436 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
1439 [(set_attr "type" "branch")
1440 (set_attr "branch_type" "icc")])
1442 ;; XXX fpcmp nop braindamage
1443 (define_insn "*inverted_branch"
1445 (if_then_else (match_operator 0 "icc_comparison_operator"
1446 [(reg CC_REG) (const_int 0)])
1448 (label_ref (match_operand 1 "" ""))))]
1451 return output_cbranch (operands[0], operands[1], 1, 1,
1452 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
1455 [(set_attr "type" "branch")
1456 (set_attr "branch_type" "icc")])
1458 ;; XXX fpcmp nop braindamage
1459 (define_insn "*normal_fp_branch"
1461 (if_then_else (match_operator 1 "comparison_operator"
1462 [(match_operand:CCFP 0 "fcc_register_operand" "c")
1464 (label_ref (match_operand 2 "" ""))
1468 return output_cbranch (operands[1], operands[2], 2, 0,
1469 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
1472 [(set_attr "type" "branch")
1473 (set_attr "branch_type" "fcc")])
1475 ;; XXX fpcmp nop braindamage
1476 (define_insn "*inverted_fp_branch"
1478 (if_then_else (match_operator 1 "comparison_operator"
1479 [(match_operand:CCFP 0 "fcc_register_operand" "c")
1482 (label_ref (match_operand 2 "" ""))))]
1485 return output_cbranch (operands[1], operands[2], 2, 1,
1486 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
1489 [(set_attr "type" "branch")
1490 (set_attr "branch_type" "fcc")])
1492 ;; XXX fpcmp nop braindamage
1493 (define_insn "*normal_fpe_branch"
1495 (if_then_else (match_operator 1 "comparison_operator"
1496 [(match_operand:CCFPE 0 "fcc_register_operand" "c")
1498 (label_ref (match_operand 2 "" ""))
1502 return output_cbranch (operands[1], operands[2], 2, 0,
1503 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
1506 [(set_attr "type" "branch")
1507 (set_attr "branch_type" "fcc")])
1509 ;; XXX fpcmp nop braindamage
1510 (define_insn "*inverted_fpe_branch"
1512 (if_then_else (match_operator 1 "comparison_operator"
1513 [(match_operand:CCFPE 0 "fcc_register_operand" "c")
1516 (label_ref (match_operand 2 "" ""))))]
1519 return output_cbranch (operands[1], operands[2], 2, 1,
1520 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
1523 [(set_attr "type" "branch")
1524 (set_attr "branch_type" "fcc")])
1526 ;; SPARC V9-specific jump insns. None of these are guaranteed to be
1527 ;; in the architecture.
1529 (define_insn "*cbcond_sp32"
1531 (if_then_else (match_operator 0 "comparison_operator"
1532 [(match_operand:SI 1 "register_operand" "r")
1533 (match_operand:SI 2 "arith5_operand" "rA")])
1534 (label_ref (match_operand 3 "" ""))
1538 return output_cbcond (operands[0], operands[3], insn);
1540 [(set_attr "type" "cbcond")])
1542 (define_insn "*cbcond_sp64"
1544 (if_then_else (match_operator 0 "comparison_operator"
1545 [(match_operand:DI 1 "register_operand" "r")
1546 (match_operand:DI 2 "arith5_operand" "rA")])
1547 (label_ref (match_operand 3 "" ""))
1549 "TARGET_ARCH64 && TARGET_CBCOND"
1551 return output_cbcond (operands[0], operands[3], insn);
1553 [(set_attr "type" "cbcond")])
1555 ;; There are no 32-bit brreg insns.
1557 (define_insn "*normal_int_branch_sp64"
1559 (if_then_else (match_operator 0 "v9_register_comparison_operator"
1560 [(match_operand:DI 1 "register_operand" "r")
1562 (label_ref (match_operand 2 "" ""))
1566 return output_v9branch (operands[0], operands[2], 1, 2, 0,
1567 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
1570 [(set_attr "type" "branch")
1571 (set_attr "branch_type" "reg")])
1573 (define_insn "*inverted_int_branch_sp64"
1575 (if_then_else (match_operator 0 "v9_register_comparison_operator"
1576 [(match_operand:DI 1 "register_operand" "r")
1579 (label_ref (match_operand 2 "" ""))))]
1582 return output_v9branch (operands[0], operands[2], 1, 2, 1,
1583 final_sequence && INSN_ANNULLED_BRANCH_P (insn),
1586 [(set_attr "type" "branch")
1587 (set_attr "branch_type" "reg")])
1590 ;; Load in operand 0 the (absolute) address of operand 1, which is a symbolic
1591 ;; value subject to a PC-relative relocation. Operand 2 is a helper function
1592 ;; that adds the PC value at the call point to register #(operand 3).
1594 ;; Even on V9 we use this call sequence with a stub, instead of "rd %pc, ..."
1595 ;; because the RDPC instruction is extremely expensive and incurs a complete
1596 ;; instruction pipeline flush.
1598 (define_insn "load_pcrel_sym<P:mode>"
1599 [(set (match_operand:P 0 "register_operand" "=r")
1600 (unspec:P [(match_operand:P 1 "symbolic_operand" "")
1601 (match_operand:P 2 "call_address_operand" "")
1602 (match_operand:P 3 "const_int_operand" "")]
1603 UNSPEC_LOAD_PCREL_SYM))
1604 (clobber (reg:P O7_REG))]
1605 "REGNO (operands[0]) == INTVAL (operands[3])"
1607 if (flag_delayed_branch)
1608 return "sethi\t%%hi(%a1-4), %0\n\tcall\t%a2\n\t add\t%0, %%lo(%a1+4), %0";
1610 return "sethi\t%%hi(%a1-8), %0\n\tadd\t%0, %%lo(%a1-4), %0\n\tcall\t%a2\n\t nop";
1612 [(set (attr "type") (const_string "multi"))
1613 (set (attr "length")
1614 (if_then_else (eq_attr "delayed_branch" "true")
1619 ;; Integer move instructions
1621 (define_expand "movqi"
1622 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1623 (match_operand:QI 1 "general_operand" ""))]
1626 if (sparc_expand_move (QImode, operands))
1630 (define_insn "*movqi_insn"
1631 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m")
1632 (match_operand:QI 1 "input_operand" "rI,m,rJ"))]
1633 "(register_operand (operands[0], QImode)
1634 || register_or_zero_operand (operands[1], QImode))"
1639 [(set_attr "type" "*,load,store")
1640 (set_attr "subtype" "*,regular,*")
1641 (set_attr "us3load_type" "*,3cycle,*")])
1643 (define_expand "movhi"
1644 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1645 (match_operand:HI 1 "general_operand" ""))]
1648 if (sparc_expand_move (HImode, operands))
1652 (define_insn "*movhi_insn"
1653 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
1654 (match_operand:HI 1 "input_operand" "rI,K,m,rJ"))]
1655 "(register_operand (operands[0], HImode)
1656 || register_or_zero_operand (operands[1], HImode))"
1659 sethi\t%%hi(%a1), %0
1662 [(set_attr "type" "*,*,load,store")
1663 (set_attr "subtype" "*,*,regular,*")
1664 (set_attr "us3load_type" "*,*,3cycle,*")])
1666 ;; We always work with constants here.
1667 (define_insn "*movhi_lo_sum"
1668 [(set (match_operand:HI 0 "register_operand" "=r")
1669 (ior:HI (match_operand:HI 1 "register_operand" "%r")
1670 (match_operand:HI 2 "small_int_operand" "I")))]
1674 (define_expand "movsi"
1675 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1676 (match_operand:SI 1 "general_operand" ""))]
1679 if (sparc_expand_move (SImode, operands))
1683 (define_insn "*movsi_insn"
1684 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m, r,*f,*f,*f, m,d,d")
1685 (match_operand:SI 1 "input_operand" "rI,K,m,rJ,*f, r, f, m,*f,J,P"))]
1686 "register_operand (operands[0], SImode)
1687 || register_or_zero_or_all_ones_operand (operands[1], SImode)"
1690 sethi\t%%hi(%a1), %0
1700 [(set_attr "type" "*,*,load,store,vismv,vismv,fpmove,fpload,fpstore,visl,visl")
1701 (set_attr "subtype" "*,*,regular,*,movstouw,single,*,*,*,single,single")
1702 (set_attr "cpu_feature" "*,*,*,*,vis3,vis3,*,*,*,vis,vis")])
1704 (define_insn "*movsi_lo_sum"
1705 [(set (match_operand:SI 0 "register_operand" "=r")
1706 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
1707 (match_operand:SI 2 "immediate_operand" "in")))]
1709 "or\t%1, %%lo(%a2), %0")
1711 (define_insn "*movsi_high"
1712 [(set (match_operand:SI 0 "register_operand" "=r")
1713 (high:SI (match_operand:SI 1 "immediate_operand" "in")))]
1715 "sethi\t%%hi(%a1), %0")
1717 ;; The next two patterns must wrap the SYMBOL_REF in an UNSPEC
1718 ;; so that CSE won't optimize the address computation away.
1719 (define_insn "movsi_lo_sum_pic"
1720 [(set (match_operand:SI 0 "register_operand" "=r")
1721 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
1722 (unspec:SI [(match_operand:SI 2 "immediate_operand" "in")]
1726 #ifdef HAVE_AS_SPARC_GOTDATA_OP
1727 return "xor\t%1, %%gdop_lox10(%a2), %0";
1729 return "or\t%1, %%lo(%a2), %0";
1733 (define_insn "movsi_high_pic"
1734 [(set (match_operand:SI 0 "register_operand" "=r")
1735 (high:SI (unspec:SI [(match_operand 1 "" "")] UNSPEC_MOVE_PIC)))]
1736 "flag_pic && check_pic (1)"
1738 #ifdef HAVE_AS_SPARC_GOTDATA_OP
1739 return "sethi\t%%gdop_hix22(%a1), %0";
1741 return "sethi\t%%hi(%a1), %0";
1745 (define_insn "movsi_pic_gotdata_op"
1746 [(set (match_operand:SI 0 "register_operand" "=r")
1747 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1748 (match_operand:SI 2 "register_operand" "r")
1749 (match_operand 3 "symbolic_operand" "")]
1750 UNSPEC_MOVE_GOTDATA))]
1751 "flag_pic && check_pic (1)"
1753 #ifdef HAVE_AS_SPARC_GOTDATA_OP
1754 return "ld\t[%1 + %2], %0, %%gdop(%a3)";
1756 return "ld\t[%1 + %2], %0";
1759 [(set_attr "type" "load")
1760 (set_attr "subtype" "regular")])
1762 (define_expand "movsi_pic_label_ref"
1763 [(set (match_dup 3) (high:SI
1764 (unspec:SI [(match_operand:SI 1 "symbolic_operand" "")
1765 (match_dup 2)] UNSPEC_MOVE_PIC_LABEL)))
1766 (set (match_dup 4) (lo_sum:SI (match_dup 3)
1767 (unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_MOVE_PIC_LABEL)))
1768 (set (match_operand:SI 0 "register_operand" "=r")
1769 (minus:SI (match_dup 5) (match_dup 4)))]
1772 crtl->uses_pic_offset_table = 1;
1773 operands[2] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
1774 if (!can_create_pseudo_p ())
1776 operands[3] = operands[0];
1777 operands[4] = operands[0];
1781 operands[3] = gen_reg_rtx (SImode);
1782 operands[4] = gen_reg_rtx (SImode);
1784 operands[5] = pic_offset_table_rtx;
1787 (define_insn "*movsi_high_pic_label_ref"
1788 [(set (match_operand:SI 0 "register_operand" "=r")
1790 (unspec:SI [(match_operand:SI 1 "symbolic_operand" "")
1791 (match_operand:SI 2 "" "")] UNSPEC_MOVE_PIC_LABEL)))]
1793 "sethi\t%%hi(%a2-(%a1-.)), %0")
1795 (define_insn "*movsi_lo_sum_pic_label_ref"
1796 [(set (match_operand:SI 0 "register_operand" "=r")
1797 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
1798 (unspec:SI [(match_operand:SI 2 "symbolic_operand" "")
1799 (match_operand:SI 3 "" "")] UNSPEC_MOVE_PIC_LABEL)))]
1801 "or\t%1, %%lo(%a3-(%a2-.)), %0")
1803 ;; Set up the PIC register for VxWorks.
1805 (define_expand "vxworks_load_got"
1807 (high:SI (match_dup 1)))
1809 (mem:SI (lo_sum:SI (match_dup 0) (match_dup 1))))
1811 (mem:SI (lo_sum:SI (match_dup 0) (match_dup 2))))]
1812 "TARGET_VXWORKS_RTP"
1814 operands[0] = pic_offset_table_rtx;
1815 operands[1] = gen_rtx_SYMBOL_REF (SImode, VXWORKS_GOTT_BASE);
1816 operands[2] = gen_rtx_SYMBOL_REF (SImode, VXWORKS_GOTT_INDEX);
1819 (define_expand "movdi"
1820 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1821 (match_operand:DI 1 "general_operand" ""))]
1824 if (sparc_expand_move (DImode, operands))
1828 ;; Be careful, fmovd does not exist when !v9.
1829 ;; We match MEM moves directly when we have correct even
1830 ;; numbered registers, but fall into splits otherwise.
1831 ;; The constraint ordering here is really important to
1832 ;; avoid insane problems in reload, especially for patterns
1835 ;; (set (mem:DI (plus:SI (reg:SI 30 %fp)
1836 ;; (const_int -5016)))
1840 (define_insn "*movdi_insn_sp32"
1841 [(set (match_operand:DI 0 "nonimmediate_operand"
1842 "=T,o,U,T,r,o,r,r,?*f,?T,?*f,?o,?*e,?*e, r,?*f,?*e,?T,*b,*b")
1843 (match_operand:DI 1 "input_operand"
1844 " J,J,T,U,o,r,i,r, T,*f, o,*f, *e, *e,?*f, r, T,*e, J, P"))]
1846 && (register_operand (operands[0], DImode)
1847 || register_or_zero_operand (operands[1], DImode))"
1869 [(set_attr "type" "store,*,load,store,load,store,*,*,fpload,fpstore,*,*,fpmove,*,*,*,fpload,fpstore,visl,
1871 (set_attr "subtype" "*,*,regular,*,regular,*,*,*,*,*,*,*,*,*,*,*,*,*,double,double")
1872 (set_attr "length" "*,2,*,*,*,*,2,2,*,*,2,2,*,2,2,2,*,*,*,*")
1873 (set_attr "fptype" "*,*,*,*,*,*,*,*,*,*,*,*,double,*,*,*,*,*,double,double")
1874 (set_attr "cpu_feature" "v9,*,*,*,*,*,*,*,fpu,fpu,fpu,fpu,v9,fpunotv9,vis3,vis3,fpu,fpu,vis,vis")
1875 (set_attr "lra" "*,*,disabled,disabled,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*")])
1877 (define_insn "*movdi_insn_sp64"
1878 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r, m, r,*e,?*e,?*e,?W,b,b")
1879 (match_operand:DI 1 "input_operand" "rI,N,m,rJ,*e, r, *e, W,*e,J,P"))]
1881 && (register_operand (operands[0], DImode)
1882 || register_or_zero_or_all_ones_operand (operands[1], DImode))"
1885 sethi\t%%hi(%a1), %0
1895 [(set_attr "type" "*,*,load,store,vismv,vismv,fpmove,fpload,fpstore,visl,visl")
1896 (set_attr "subtype" "*,*,regular,*,movdtox,movxtod,*,*,*,double,double")
1897 (set_attr "fptype" "*,*,*,*,*,*,double,*,*,double,double")
1898 (set_attr "cpu_feature" "*,*,*,*,vis3,vis3,*,*,*,vis,vis")])
1900 (define_expand "movdi_pic_label_ref"
1901 [(set (match_dup 3) (high:DI
1902 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")
1903 (match_dup 2)] UNSPEC_MOVE_PIC_LABEL)))
1904 (set (match_dup 4) (lo_sum:DI (match_dup 3)
1905 (unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_MOVE_PIC_LABEL)))
1906 (set (match_operand:DI 0 "register_operand" "=r")
1907 (minus:DI (match_dup 5) (match_dup 4)))]
1908 "TARGET_ARCH64 && flag_pic"
1910 crtl->uses_pic_offset_table = 1;
1911 operands[2] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
1912 if (!can_create_pseudo_p ())
1914 operands[3] = operands[0];
1915 operands[4] = operands[0];
1919 operands[3] = gen_reg_rtx (DImode);
1920 operands[4] = gen_reg_rtx (DImode);
1922 operands[5] = pic_offset_table_rtx;
1925 (define_insn "*movdi_high_pic_label_ref"
1926 [(set (match_operand:DI 0 "register_operand" "=r")
1928 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")
1929 (match_operand:DI 2 "" "")] UNSPEC_MOVE_PIC_LABEL)))]
1930 "TARGET_ARCH64 && flag_pic"
1931 "sethi\t%%hi(%a2-(%a1-.)), %0")
1933 (define_insn "*movdi_lo_sum_pic_label_ref"
1934 [(set (match_operand:DI 0 "register_operand" "=r")
1935 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
1936 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")
1937 (match_operand:DI 3 "" "")] UNSPEC_MOVE_PIC_LABEL)))]
1938 "TARGET_ARCH64 && flag_pic"
1939 "or\t%1, %%lo(%a3-(%a2-.)), %0")
1941 ;; SPARC-v9 code model support insns. See sparc_emit_set_symbolic_const64
1942 ;; in sparc.c to see what is going on here... PIC stuff comes first.
1944 (define_insn "movdi_lo_sum_pic"
1945 [(set (match_operand:DI 0 "register_operand" "=r")
1946 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
1947 (unspec:DI [(match_operand:DI 2 "immediate_operand" "in")]
1949 "TARGET_ARCH64 && flag_pic"
1951 #ifdef HAVE_AS_SPARC_GOTDATA_OP
1952 return "xor\t%1, %%gdop_lox10(%a2), %0";
1954 return "or\t%1, %%lo(%a2), %0";
1958 (define_insn "movdi_high_pic"
1959 [(set (match_operand:DI 0 "register_operand" "=r")
1960 (high:DI (unspec:DI [(match_operand 1 "" "")] UNSPEC_MOVE_PIC)))]
1961 "TARGET_ARCH64 && flag_pic && check_pic (1)"
1963 #ifdef HAVE_AS_SPARC_GOTDATA_OP
1964 return "sethi\t%%gdop_hix22(%a1), %0";
1966 return "sethi\t%%hi(%a1), %0";
1970 (define_insn "movdi_pic_gotdata_op"
1971 [(set (match_operand:DI 0 "register_operand" "=r")
1972 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
1973 (match_operand:DI 2 "register_operand" "r")
1974 (match_operand 3 "symbolic_operand" "")]
1975 UNSPEC_MOVE_GOTDATA))]
1976 "TARGET_ARCH64 && flag_pic && check_pic (1)"
1978 #ifdef HAVE_AS_SPARC_GOTDATA_OP
1979 return "ldx\t[%1 + %2], %0, %%gdop(%a3)";
1981 return "ldx\t[%1 + %2], %0";
1984 [(set_attr "type" "load")
1985 (set_attr "subtype" "regular")])
1987 (define_insn "*sethi_di_medlow_embmedany_pic"
1988 [(set (match_operand:DI 0 "register_operand" "=r")
1989 (high:DI (match_operand:DI 1 "medium_pic_operand" "")))]
1990 "(TARGET_CM_MEDLOW || TARGET_CM_EMBMEDANY) && flag_pic && check_pic (1)"
1991 "sethi\t%%hi(%a1), %0")
1993 (define_insn "*sethi_di_medlow"
1994 [(set (match_operand:DI 0 "register_operand" "=r")
1995 (high:DI (match_operand:DI 1 "symbolic_operand" "")))]
1996 "TARGET_CM_MEDLOW && !flag_pic"
1997 "sethi\t%%hi(%a1), %0")
1999 (define_insn "*losum_di_medlow"
2000 [(set (match_operand:DI 0 "register_operand" "=r")
2001 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2002 (match_operand:DI 2 "symbolic_operand" "")))]
2003 "TARGET_CM_MEDLOW && !flag_pic"
2004 "or\t%1, %%lo(%a2), %0")
2006 (define_insn "seth44"
2007 [(set (match_operand:DI 0 "register_operand" "=r")
2008 (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
2010 "TARGET_CM_MEDMID && !flag_pic"
2011 "sethi\t%%h44(%a1), %0")
2013 (define_insn "setm44"
2014 [(set (match_operand:DI 0 "register_operand" "=r")
2015 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2016 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
2018 "TARGET_CM_MEDMID && !flag_pic"
2019 "or\t%1, %%m44(%a2), %0")
2021 (define_insn "setl44"
2022 [(set (match_operand:DI 0 "register_operand" "=r")
2023 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2024 (match_operand:DI 2 "symbolic_operand" "")))]
2025 "TARGET_CM_MEDMID && !flag_pic"
2026 "or\t%1, %%l44(%a2), %0")
2028 (define_insn "sethh"
2029 [(set (match_operand:DI 0 "register_operand" "=r")
2030 (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
2032 "TARGET_CM_MEDANY && !flag_pic"
2033 "sethi\t%%hh(%a1), %0")
2035 (define_insn "setlm"
2036 [(set (match_operand:DI 0 "register_operand" "=r")
2037 (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
2039 "TARGET_CM_MEDANY && !flag_pic"
2040 "sethi\t%%lm(%a1), %0")
2042 (define_insn "sethm"
2043 [(set (match_operand:DI 0 "register_operand" "=r")
2044 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2045 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
2046 UNSPEC_EMB_SETHM)))]
2047 "TARGET_CM_MEDANY && !flag_pic"
2048 "or\t%1, %%hm(%a2), %0")
2050 (define_insn "setlo"
2051 [(set (match_operand:DI 0 "register_operand" "=r")
2052 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2053 (match_operand:DI 2 "symbolic_operand" "")))]
2054 "TARGET_CM_MEDANY && !flag_pic"
2055 "or\t%1, %%lo(%a2), %0")
2057 (define_insn "embmedany_sethi"
2058 [(set (match_operand:DI 0 "register_operand" "=r")
2059 (high:DI (unspec:DI [(match_operand:DI 1 "data_segment_operand" "")]
2060 UNSPEC_EMB_HISUM)))]
2061 "TARGET_CM_EMBMEDANY && !flag_pic"
2062 "sethi\t%%hi(%a1), %0")
2064 (define_insn "embmedany_losum"
2065 [(set (match_operand:DI 0 "register_operand" "=r")
2066 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2067 (match_operand:DI 2 "data_segment_operand" "")))]
2068 "TARGET_CM_EMBMEDANY && !flag_pic"
2069 "add\t%1, %%lo(%a2), %0")
2071 (define_insn "embmedany_brsum"
2072 [(set (match_operand:DI 0 "register_operand" "=r")
2073 (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
2075 "TARGET_CM_EMBMEDANY && !flag_pic"
2078 (define_insn "embmedany_textuhi"
2079 [(set (match_operand:DI 0 "register_operand" "=r")
2080 (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")]
2081 UNSPEC_EMB_TEXTUHI)))]
2082 "TARGET_CM_EMBMEDANY && !flag_pic"
2083 "sethi\t%%uhi(%a1), %0")
2085 (define_insn "embmedany_texthi"
2086 [(set (match_operand:DI 0 "register_operand" "=r")
2087 (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")]
2088 UNSPEC_EMB_TEXTHI)))]
2089 "TARGET_CM_EMBMEDANY && !flag_pic"
2090 "sethi\t%%hi(%a1), %0")
2092 (define_insn "embmedany_textulo"
2093 [(set (match_operand:DI 0 "register_operand" "=r")
2094 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2095 (unspec:DI [(match_operand:DI 2 "text_segment_operand" "")]
2096 UNSPEC_EMB_TEXTULO)))]
2097 "TARGET_CM_EMBMEDANY && !flag_pic"
2098 "or\t%1, %%ulo(%a2), %0")
2100 (define_insn "embmedany_textlo"
2101 [(set (match_operand:DI 0 "register_operand" "=r")
2102 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2103 (match_operand:DI 2 "text_segment_operand" "")))]
2104 "TARGET_CM_EMBMEDANY && !flag_pic"
2105 "or\t%1, %%lo(%a2), %0")
2107 ;; Now some patterns to help reload out a bit.
2108 (define_expand "reload_indi"
2109 [(parallel [(match_operand:DI 0 "register_operand" "=r")
2110 (match_operand:DI 1 "immediate_operand" "")
2111 (match_operand:TI 2 "register_operand" "=&r")])]
2112 "(TARGET_CM_MEDANY || TARGET_CM_EMBMEDANY) && !flag_pic"
2114 sparc_emit_set_symbolic_const64 (operands[0], operands[1], operands[2]);
2118 (define_expand "reload_outdi"
2119 [(parallel [(match_operand:DI 0 "register_operand" "=r")
2120 (match_operand:DI 1 "immediate_operand" "")
2121 (match_operand:TI 2 "register_operand" "=&r")])]
2122 "(TARGET_CM_MEDANY || TARGET_CM_EMBMEDANY) && !flag_pic"
2124 sparc_emit_set_symbolic_const64 (operands[0], operands[1], operands[2]);
2128 ;; Split up putting CONSTs and REGs into DI regs when !arch64
2130 [(set (match_operand:DI 0 "register_operand" "")
2131 (match_operand:DI 1 "const_int_operand" ""))]
2134 && ((GET_CODE (operands[0]) == REG
2135 && SPARC_INT_REG_P (REGNO (operands[0])))
2136 || (GET_CODE (operands[0]) == SUBREG
2137 && GET_CODE (SUBREG_REG (operands[0])) == REG
2138 && SPARC_INT_REG_P (REGNO (SUBREG_REG (operands[0])))))"
2139 [(clobber (const_int 0))]
2141 HOST_WIDE_INT low = trunc_int_for_mode (INTVAL (operands[1]), SImode);
2142 HOST_WIDE_INT high = trunc_int_for_mode (INTVAL (operands[1]) >> 32, SImode);
2143 rtx high_part = gen_highpart (SImode, operands[0]);
2144 rtx low_part = gen_lowpart (SImode, operands[0]);
2146 emit_move_insn_1 (high_part, GEN_INT (high));
2148 /* Slick... but this loses if the constant can be done in one insn. */
2149 if (low == high && !SPARC_SETHI32_P (high) && !SPARC_SIMM13_P (high))
2150 emit_move_insn_1 (low_part, high_part);
2152 emit_move_insn_1 (low_part, GEN_INT (low));
2158 [(set (match_operand:DI 0 "register_operand" "")
2159 (match_operand:DI 1 "register_operand" ""))]
2163 && sparc_split_reg_reg_legitimate (operands[0], operands[1])))"
2164 [(clobber (const_int 0))]
2166 sparc_split_reg_reg (operands[0], operands[1], SImode);
2170 ;; Now handle the cases of memory moves from/to non-even
2171 ;; DI mode register pairs.
2173 [(set (match_operand:DI 0 "register_operand" "")
2174 (match_operand:DI 1 "memory_operand" ""))]
2177 && sparc_split_reg_mem_legitimate (operands[0], operands[1])"
2178 [(clobber (const_int 0))]
2180 sparc_split_reg_mem (operands[0], operands[1], SImode);
2185 [(set (match_operand:DI 0 "memory_operand" "")
2186 (match_operand:DI 1 "register_operand" ""))]
2189 && sparc_split_reg_mem_legitimate (operands[1], operands[0])"
2190 [(clobber (const_int 0))]
2192 sparc_split_mem_reg (operands[0], operands[1], SImode);
2197 [(set (match_operand:DI 0 "memory_operand" "")
2198 (match_operand:DI 1 "const_zero_operand" ""))]
2202 && !mem_min_alignment (operands[0], 8)))
2203 && offsettable_memref_p (operands[0])"
2204 [(clobber (const_int 0))]
2206 emit_move_insn_1 (adjust_address (operands[0], SImode, 0), const0_rtx);
2207 emit_move_insn_1 (adjust_address (operands[0], SImode, 4), const0_rtx);
2211 (define_expand "movti"
2212 [(set (match_operand:TI 0 "nonimmediate_operand" "")
2213 (match_operand:TI 1 "general_operand" ""))]
2216 if (sparc_expand_move (TImode, operands))
2220 ;; We need to prevent reload from splitting TImode moves, because it
2221 ;; might decide to overwrite a pointer with the value it points to.
2222 ;; In that case we have to do the loads in the appropriate order so
2223 ;; that the pointer is not destroyed too early.
2225 (define_insn "*movti_insn_sp64"
2226 [(set (match_operand:TI 0 "nonimmediate_operand" "=r , o,?*e,?o,b")
2227 (match_operand:TI 1 "input_operand" "roJ,rJ, eo, e,J"))]
2229 && !TARGET_HARD_QUAD
2230 && (register_operand (operands[0], TImode)
2231 || register_or_zero_operand (operands[1], TImode))"
2233 [(set_attr "length" "2,2,2,2,2")
2234 (set_attr "cpu_feature" "*,*,fpu,fpu,vis")])
2236 (define_insn "*movti_insn_sp64_hq"
2237 [(set (match_operand:TI 0 "nonimmediate_operand" "=r , o,?*e,?*e,?m,b")
2238 (match_operand:TI 1 "input_operand" "roJ,rJ, e, m, e,J"))]
2241 && (register_operand (operands[0], TImode)
2242 || register_or_zero_operand (operands[1], TImode))"
2250 [(set_attr "type" "*,*,fpmove,fpload,fpstore,*")
2251 (set_attr "length" "2,2,*,*,*,2")])
2253 ;; Now all the splits to handle multi-insn TI mode moves.
2255 [(set (match_operand:TI 0 "register_operand" "")
2256 (match_operand:TI 1 "register_operand" ""))]
2259 && !TARGET_HARD_QUAD)
2260 || (!fp_register_operand (operands[0], TImode)
2261 && !fp_register_operand (operands[1], TImode)))"
2262 [(clobber (const_int 0))]
2264 rtx set_dest = operands[0];
2265 rtx set_src = operands[1];
2269 dest1 = gen_highpart (DImode, set_dest);
2270 dest2 = gen_lowpart (DImode, set_dest);
2271 src1 = gen_highpart (DImode, set_src);
2272 src2 = gen_lowpart (DImode, set_src);
2274 /* Now emit using the real source and destination we found, swapping
2275 the order if we detect overlap. */
2276 if (reg_overlap_mentioned_p (dest1, src2))
2278 emit_insn (gen_movdi (dest2, src2));
2279 emit_insn (gen_movdi (dest1, src1));
2283 emit_insn (gen_movdi (dest1, src1));
2284 emit_insn (gen_movdi (dest2, src2));
2290 [(set (match_operand:TI 0 "nonimmediate_operand" "")
2291 (match_operand:TI 1 "const_zero_operand" ""))]
2293 [(clobber (const_int 0))]
2295 rtx set_dest = operands[0];
2298 switch (GET_CODE (set_dest))
2301 dest1 = gen_highpart (DImode, set_dest);
2302 dest2 = gen_lowpart (DImode, set_dest);
2305 dest1 = adjust_address (set_dest, DImode, 0);
2306 dest2 = adjust_address (set_dest, DImode, 8);
2312 emit_insn (gen_movdi (dest1, const0_rtx));
2313 emit_insn (gen_movdi (dest2, const0_rtx));
2318 [(set (match_operand:TI 0 "register_operand" "")
2319 (match_operand:TI 1 "memory_operand" ""))]
2321 && offsettable_memref_p (operands[1])
2322 && (!TARGET_HARD_QUAD
2323 || !fp_register_operand (operands[0], TImode))"
2324 [(clobber (const_int 0))]
2326 rtx word0 = adjust_address (operands[1], DImode, 0);
2327 rtx word1 = adjust_address (operands[1], DImode, 8);
2328 rtx set_dest, dest1, dest2;
2330 set_dest = operands[0];
2332 dest1 = gen_highpart (DImode, set_dest);
2333 dest2 = gen_lowpart (DImode, set_dest);
2335 /* Now output, ordering such that we don't clobber any registers
2336 mentioned in the address. */
2337 if (reg_overlap_mentioned_p (dest1, word1))
2340 emit_insn (gen_movdi (dest2, word1));
2341 emit_insn (gen_movdi (dest1, word0));
2345 emit_insn (gen_movdi (dest1, word0));
2346 emit_insn (gen_movdi (dest2, word1));
2352 [(set (match_operand:TI 0 "memory_operand" "")
2353 (match_operand:TI 1 "register_operand" ""))]
2355 && offsettable_memref_p (operands[0])
2356 && (!TARGET_HARD_QUAD
2357 || !fp_register_operand (operands[1], TImode))"
2358 [(clobber (const_int 0))]
2360 rtx set_src = operands[1];
2362 emit_insn (gen_movdi (adjust_address (operands[0], DImode, 0),
2363 gen_highpart (DImode, set_src)));
2364 emit_insn (gen_movdi (adjust_address (operands[0], DImode, 8),
2365 gen_lowpart (DImode, set_src)));
2370 ;; Floating point move instructions
2372 (define_expand "movsf"
2373 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2374 (match_operand:SF 1 "general_operand" ""))]
2377 if (sparc_expand_move (SFmode, operands))
2381 (define_insn "*movsf_insn"
2382 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,f, *r,*r,*r,*r, f,f,*r,m, m")
2383 (match_operand:SF 1 "input_operand" "G,C,f,*rR, Q, S, f,*r,m, m,f,*rG"))]
2384 "(register_operand (operands[0], SFmode)
2385 || register_or_zero_or_all_ones_operand (operands[1], SFmode))"
2387 if (GET_CODE (operands[1]) == CONST_DOUBLE
2388 && (which_alternative == 3
2389 || which_alternative == 4
2390 || which_alternative == 5))
2394 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (operands[1]), i);
2395 operands[1] = GEN_INT (i);
2398 switch (which_alternative)
2401 return "fzeros\t%0";
2405 return "fmovs\t%1, %0";
2407 return "mov\t%1, %0";
2409 return "sethi\t%%hi(%a1), %0";
2413 return "movstouw\t%1, %0";
2415 return "movwtos\t%1, %0";
2418 return "ld\t%1, %0";
2421 return "st\t%r1, %0";
2426 [(set_attr "type" "visl,visl,fpmove,*,*,*,vismv,vismv,fpload,load,fpstore,store")
2427 (set_attr "subtype" "single,single,*,*,*,*,movstouw,single,*,regular,*,*")
2428 (set_attr "cpu_feature" "vis,vis,fpu,*,*,*,vis3,vis3,fpu,*,fpu,*")])
2430 ;; The following 3 patterns build SFmode constants in integer registers.
2432 (define_insn "*movsf_lo_sum"
2433 [(set (match_operand:SF 0 "register_operand" "=r")
2434 (lo_sum:SF (match_operand:SF 1 "register_operand" "r")
2435 (match_operand:SF 2 "fp_const_high_losum_operand" "S")))]
2440 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (operands[2]), i);
2441 operands[2] = GEN_INT (i);
2442 return "or\t%1, %%lo(%a2), %0";
2445 (define_insn "*movsf_high"
2446 [(set (match_operand:SF 0 "register_operand" "=r")
2447 (high:SF (match_operand:SF 1 "fp_const_high_losum_operand" "S")))]
2452 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (operands[1]), i);
2453 operands[1] = GEN_INT (i);
2454 return "sethi\t%%hi(%1), %0";
2458 [(set (match_operand:SF 0 "register_operand" "")
2459 (match_operand:SF 1 "fp_const_high_losum_operand" ""))]
2460 "REG_P (operands[0]) && SPARC_INT_REG_P (REGNO (operands[0]))"
2461 [(set (match_dup 0) (high:SF (match_dup 1)))
2462 (set (match_dup 0) (lo_sum:SF (match_dup 0) (match_dup 1)))])
2464 (define_expand "movdf"
2465 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2466 (match_operand:DF 1 "general_operand" ""))]
2469 if (sparc_expand_move (DFmode, operands))
2473 (define_insn "*movdf_insn_sp32"
2474 [(set (match_operand:DF 0 "nonimmediate_operand"
2475 "=T,o,b,b,e,e,*r, f, e,T,U,T, f,o, *r,*r, o")
2476 (match_operand:DF 1 "input_operand"
2477 " G,G,G,C,e,e, f,*r,T#F,e,T,U,o#F,f,*rF, o,*r"))]
2479 && (register_operand (operands[0], DFmode)
2480 || register_or_zero_or_all_ones_operand (operands[1], DFmode))"
2499 [(set_attr "type" "store,*,visl,visl,fpmove,*,*,*,fpload,fpstore,load,store,*,*,*,load,store")
2500 (set_attr "subtype" "*,*,double,double,*,*,*,*,*,*,regular,*,*,*,*,regular,*")
2501 (set_attr "length" "*,2,*,*,*,2,2,2,*,*,*,*,2,2,2,*,*")
2502 (set_attr "fptype" "*,*,double,double,double,*,*,*,*,*,*,*,*,*,*,*,*")
2503 (set_attr "cpu_feature" "v9,*,vis,vis,v9,fpunotv9,vis3,vis3,fpu,fpu,*,*,fpu,fpu,*,*,*")
2504 (set_attr "lra" "*,*,*,*,*,*,*,*,*,*,disabled,disabled,*,*,*,*,*")])
2506 (define_insn "*movdf_insn_sp64"
2507 [(set (match_operand:DF 0 "nonimmediate_operand" "=b,b,e,*r, e, e,W, *r,*r, m,*r")
2508 (match_operand:DF 1 "input_operand" "G,C,e, e,*r,W#F,e,*rG, m,*rG, F"))]
2510 && (register_operand (operands[0], DFmode)
2511 || register_or_zero_or_all_ones_operand (operands[1], DFmode))"
2524 [(set_attr "type" "visl,visl,fpmove,vismv,vismv,load,store,*,load,store,*")
2525 (set_attr "subtype" "double,double,*,movdtox,movxtod,regular,*,*,regular,*,*")
2526 (set_attr "length" "*,*,*,*,*,*,*,*,*,*,2")
2527 (set_attr "fptype" "double,double,double,double,double,*,*,*,*,*,*")
2528 (set_attr "cpu_feature" "vis,vis,fpu,vis3,vis3,fpu,fpu,*,*,*,*")])
2530 ;; This pattern builds DFmode constants in integer registers.
2532 [(set (match_operand:DF 0 "register_operand" "")
2533 (match_operand:DF 1 "const_double_operand" ""))]
2535 && REG_P (operands[0])
2536 && SPARC_INT_REG_P (REGNO (operands[0]))
2537 && !const_zero_operand (operands[1], GET_MODE (operands[0]))"
2538 [(clobber (const_int 0))]
2540 operands[0] = gen_raw_REG (DImode, REGNO (operands[0]));
2544 rtx tem = simplify_subreg (DImode, operands[1], DFmode, 0);
2545 emit_insn (gen_movdi (operands[0], tem));
2549 rtx hi = simplify_subreg (SImode, operands[1], DFmode, 0);
2550 rtx lo = simplify_subreg (SImode, operands[1], DFmode, 4);
2551 rtx high_part = gen_highpart (SImode, operands[0]);
2552 rtx low_part = gen_lowpart (SImode, operands[0]);
2554 gcc_assert (GET_CODE (hi) == CONST_INT);
2555 gcc_assert (GET_CODE (lo) == CONST_INT);
2557 emit_move_insn_1 (high_part, hi);
2559 /* Slick... but this loses if the constant can be done in one insn. */
2561 && !SPARC_SETHI32_P (INTVAL (hi))
2562 && !SPARC_SIMM13_P (INTVAL (hi)))
2563 emit_move_insn_1 (low_part, high_part);
2565 emit_move_insn_1 (low_part, lo);
2570 ;; Ok, now the splits to handle all the multi insn and
2571 ;; mis-aligned memory address cases.
2572 ;; In these splits please take note that we must be
2573 ;; careful when V9 but not ARCH64 because the integer
2574 ;; register DFmode cases must be handled.
2576 [(set (match_operand:DF 0 "register_operand" "")
2577 (match_operand:DF 1 "const_zero_operand" ""))]
2580 && ((GET_CODE (operands[0]) == REG
2581 && SPARC_INT_REG_P (REGNO (operands[0])))
2582 || (GET_CODE (operands[0]) == SUBREG
2583 && GET_CODE (SUBREG_REG (operands[0])) == REG
2584 && SPARC_INT_REG_P (REGNO (SUBREG_REG (operands[0])))))"
2585 [(clobber (const_int 0))]
2587 emit_move_insn_1 (gen_highpart (SFmode, operands[0]), CONST0_RTX (SFmode));
2588 emit_move_insn_1 (gen_lowpart (SFmode, operands[0]), CONST0_RTX (SFmode));
2593 [(set (match_operand:DF 0 "register_operand" "")
2594 (match_operand:DF 1 "register_operand" ""))]
2598 && sparc_split_reg_reg_legitimate (operands[0], operands[1])))"
2599 [(clobber (const_int 0))]
2601 sparc_split_reg_reg (operands[0], operands[1], SFmode);
2606 [(set (match_operand:DF 0 "register_operand" "")
2607 (match_operand:DF 1 "memory_operand" ""))]
2610 && sparc_split_reg_mem_legitimate (operands[0], operands[1])"
2611 [(clobber (const_int 0))]
2613 sparc_split_reg_mem (operands[0], operands[1], SFmode);
2618 [(set (match_operand:DF 0 "memory_operand" "")
2619 (match_operand:DF 1 "register_operand" ""))]
2622 && sparc_split_reg_mem_legitimate (operands[1], operands[0])"
2623 [(clobber (const_int 0))]
2625 sparc_split_mem_reg (operands[0], operands[1], SFmode);
2630 [(set (match_operand:DF 0 "memory_operand" "")
2631 (match_operand:DF 1 "const_zero_operand" ""))]
2635 && !mem_min_alignment (operands[0], 8)))
2636 && offsettable_memref_p (operands[0])"
2637 [(clobber (const_int 0))]
2639 emit_move_insn_1 (adjust_address (operands[0], SFmode, 0), CONST0_RTX (SFmode));
2640 emit_move_insn_1 (adjust_address (operands[0], SFmode, 4), CONST0_RTX (SFmode));
2644 (define_expand "movtf"
2645 [(set (match_operand:TF 0 "nonimmediate_operand" "")
2646 (match_operand:TF 1 "general_operand" ""))]
2649 if (sparc_expand_move (TFmode, operands))
2653 (define_insn "*movtf_insn_sp32"
2654 [(set (match_operand:TF 0 "nonimmediate_operand" "=b, e,o, o, r")
2655 (match_operand:TF 1 "input_operand" " G,oe,e,rG,roG"))]
2657 && (register_operand (operands[0], TFmode)
2658 || register_or_zero_operand (operands[1], TFmode))"
2660 [(set_attr "length" "4,4,4,4,4")
2661 (set_attr "cpu_feature" "fpu,fpu,fpu,*,*")])
2663 (define_insn "*movtf_insn_sp64"
2664 [(set (match_operand:TF 0 "nonimmediate_operand" "=b, e,o, o, r")
2665 (match_operand:TF 1 "input_operand" "G,oe,e,rG,roG"))]
2667 && !TARGET_HARD_QUAD
2668 && (register_operand (operands[0], TFmode)
2669 || register_or_zero_operand (operands[1], TFmode))"
2671 [(set_attr "length" "2,2,2,2,2")
2672 (set_attr "cpu_feature" "fpu,fpu,fpu,*,*")])
2674 (define_insn "*movtf_insn_sp64_hq"
2675 [(set (match_operand:TF 0 "nonimmediate_operand" "=b,e,e,m, o, r")
2676 (match_operand:TF 1 "input_operand" "G,e,m,e,rG,roG"))]
2679 && (register_operand (operands[0], TFmode)
2680 || register_or_zero_operand (operands[1], TFmode))"
2688 [(set_attr "type" "*,fpmove,fpload,fpstore,*,*")
2689 (set_attr "length" "2,*,*,*,2,2")])
2691 ;; Now all the splits to handle multi-insn TF mode moves.
2693 [(set (match_operand:TF 0 "register_operand" "")
2694 (match_operand:TF 1 "register_operand" ""))]
2698 && !TARGET_HARD_QUAD)
2699 || (!fp_register_operand (operands[0], TFmode)
2700 && !fp_register_operand (operands[1], TFmode)))"
2701 [(clobber (const_int 0))]
2703 rtx set_dest = operands[0];
2704 rtx set_src = operands[1];
2708 dest1 = gen_df_reg (set_dest, 0);
2709 dest2 = gen_df_reg (set_dest, 1);
2710 src1 = gen_df_reg (set_src, 0);
2711 src2 = gen_df_reg (set_src, 1);
2713 /* Now emit using the real source and destination we found, swapping
2714 the order if we detect overlap. */
2715 if (reg_overlap_mentioned_p (dest1, src2))
2717 emit_insn (gen_movdf (dest2, src2));
2718 emit_insn (gen_movdf (dest1, src1));
2722 emit_insn (gen_movdf (dest1, src1));
2723 emit_insn (gen_movdf (dest2, src2));
2729 [(set (match_operand:TF 0 "nonimmediate_operand" "")
2730 (match_operand:TF 1 "const_zero_operand" ""))]
2732 [(clobber (const_int 0))]
2734 rtx set_dest = operands[0];
2737 switch (GET_CODE (set_dest))
2740 dest1 = gen_df_reg (set_dest, 0);
2741 dest2 = gen_df_reg (set_dest, 1);
2744 dest1 = adjust_address (set_dest, DFmode, 0);
2745 dest2 = adjust_address (set_dest, DFmode, 8);
2751 emit_insn (gen_movdf (dest1, CONST0_RTX (DFmode)));
2752 emit_insn (gen_movdf (dest2, CONST0_RTX (DFmode)));
2757 [(set (match_operand:TF 0 "register_operand" "")
2758 (match_operand:TF 1 "memory_operand" ""))]
2760 && offsettable_memref_p (operands[1])
2762 || !TARGET_HARD_QUAD
2763 || !fp_register_operand (operands[0], TFmode)))"
2764 [(clobber (const_int 0))]
2766 rtx word0 = adjust_address (operands[1], DFmode, 0);
2767 rtx word1 = adjust_address (operands[1], DFmode, 8);
2768 rtx set_dest, dest1, dest2;
2770 set_dest = operands[0];
2772 dest1 = gen_df_reg (set_dest, 0);
2773 dest2 = gen_df_reg (set_dest, 1);
2775 /* Now output, ordering such that we don't clobber any registers
2776 mentioned in the address. */
2777 if (reg_overlap_mentioned_p (dest1, word1))
2780 emit_insn (gen_movdf (dest2, word1));
2781 emit_insn (gen_movdf (dest1, word0));
2785 emit_insn (gen_movdf (dest1, word0));
2786 emit_insn (gen_movdf (dest2, word1));
2792 [(set (match_operand:TF 0 "memory_operand" "")
2793 (match_operand:TF 1 "register_operand" ""))]
2795 && offsettable_memref_p (operands[0])
2797 || !TARGET_HARD_QUAD
2798 || !fp_register_operand (operands[1], TFmode)))"
2799 [(clobber (const_int 0))]
2801 rtx set_src = operands[1];
2803 emit_insn (gen_movdf (adjust_address (operands[0], DFmode, 0),
2804 gen_df_reg (set_src, 0)));
2805 emit_insn (gen_movdf (adjust_address (operands[0], DFmode, 8),
2806 gen_df_reg (set_src, 1)));
2811 ;; SPARC-V9 conditional move instructions
2813 ;; We can handle larger constants here for some flavors, but for now we keep
2814 ;; it simple and only allow those constants supported by all flavors.
2815 ;; Note that emit_conditional_move canonicalizes operands 2,3 so that operand
2816 ;; 3 contains the constant if one is present, but we handle either for
2817 ;; generality (sparc.c puts a constant in operand 2).
2819 ;; Our instruction patterns, on the other hand, canonicalize such that
2820 ;; operand 3 must be the set destination.
2822 (define_expand "mov<I:mode>cc"
2823 [(set (match_operand:I 0 "register_operand" "")
2824 (if_then_else:I (match_operand 1 "comparison_operator" "")
2825 (match_operand:I 2 "arith10_operand" "")
2826 (match_operand:I 3 "arith10_operand" "")))]
2827 "TARGET_V9 && !(<I:MODE>mode == DImode && TARGET_ARCH32)"
2829 if (!sparc_expand_conditional_move (<I:MODE>mode, operands))
2834 (define_expand "mov<F:mode>cc"
2835 [(set (match_operand:F 0 "register_operand" "")
2836 (if_then_else:F (match_operand 1 "comparison_operator" "")
2837 (match_operand:F 2 "register_operand" "")
2838 (match_operand:F 3 "register_operand" "")))]
2839 "TARGET_V9 && TARGET_FPU"
2841 if (!sparc_expand_conditional_move (<F:MODE>mode, operands))
2846 (define_insn "*mov<I:mode>_cc_v9"
2847 [(set (match_operand:I 0 "register_operand" "=r")
2848 (if_then_else:I (match_operator 1 "icc_or_fcc_comparison_operator"
2849 [(match_operand 2 "icc_or_fcc_register_operand" "X")
2851 (match_operand:I 3 "arith11_operand" "rL")
2852 (match_operand:I 4 "register_operand" "0")))]
2853 "TARGET_V9 && !(<I:MODE>mode == DImode && TARGET_ARCH32)"
2854 "mov%C1\t%x2, %3, %0"
2855 [(set_attr "type" "cmove")])
2857 (define_insn "*mov<I:mode>_cc_reg_sp64"
2858 [(set (match_operand:I 0 "register_operand" "=r")
2859 (if_then_else:I (match_operator 1 "v9_register_comparison_operator"
2860 [(match_operand:DI 2 "register_operand" "r")
2862 (match_operand:I 3 "arith10_operand" "rM")
2863 (match_operand:I 4 "register_operand" "0")))]
2865 "movr%D1\t%2, %r3, %0"
2866 [(set_attr "type" "cmove")])
2868 (define_insn "*movsf_cc_v9"
2869 [(set (match_operand:SF 0 "register_operand" "=f")
2870 (if_then_else:SF (match_operator 1 "icc_or_fcc_comparison_operator"
2871 [(match_operand 2 "icc_or_fcc_register_operand" "X")
2873 (match_operand:SF 3 "register_operand" "f")
2874 (match_operand:SF 4 "register_operand" "0")))]
2875 "TARGET_V9 && TARGET_FPU"
2876 "fmovs%C1\t%x2, %3, %0"
2877 [(set_attr "type" "fpcmove")])
2879 (define_insn "*movsf_cc_reg_sp64"
2880 [(set (match_operand:SF 0 "register_operand" "=f")
2881 (if_then_else:SF (match_operator 1 "v9_register_comparison_operator"
2882 [(match_operand:DI 2 "register_operand" "r")
2884 (match_operand:SF 3 "register_operand" "f")
2885 (match_operand:SF 4 "register_operand" "0")))]
2886 "TARGET_ARCH64 && TARGET_FPU"
2887 "fmovrs%D1\t%2, %3, %0"
2888 [(set_attr "type" "fpcrmove")])
2890 ;; Named because invoked by movtf_cc_v9
2891 (define_insn "movdf_cc_v9"
2892 [(set (match_operand:DF 0 "register_operand" "=e")
2893 (if_then_else:DF (match_operator 1 "icc_or_fcc_comparison_operator"
2894 [(match_operand 2 "icc_or_fcc_register_operand" "X")
2896 (match_operand:DF 3 "register_operand" "e")
2897 (match_operand:DF 4 "register_operand" "0")))]
2898 "TARGET_V9 && TARGET_FPU"
2899 "fmovd%C1\t%x2, %3, %0"
2900 [(set_attr "type" "fpcmove")
2901 (set_attr "fptype" "double")])
2903 ;; Named because invoked by movtf_cc_reg_sp64
2904 (define_insn "movdf_cc_reg_sp64"
2905 [(set (match_operand:DF 0 "register_operand" "=e")
2906 (if_then_else:DF (match_operator 1 "v9_register_comparison_operator"
2907 [(match_operand:DI 2 "register_operand" "r")
2909 (match_operand:DF 3 "register_operand" "e")
2910 (match_operand:DF 4 "register_operand" "0")))]
2911 "TARGET_ARCH64 && TARGET_FPU"
2912 "fmovrd%D1\t%2, %3, %0"
2913 [(set_attr "type" "fpcrmove")
2914 (set_attr "fptype" "double")])
2916 (define_insn "*movtf_cc_hq_v9"
2917 [(set (match_operand:TF 0 "register_operand" "=e")
2918 (if_then_else:TF (match_operator 1 "icc_or_fcc_comparison_operator"
2919 [(match_operand 2 "icc_or_fcc_register_operand" "X")
2921 (match_operand:TF 3 "register_operand" "e")
2922 (match_operand:TF 4 "register_operand" "0")))]
2923 "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD"
2924 "fmovq%C1\t%x2, %3, %0"
2925 [(set_attr "type" "fpcmove")])
2927 (define_insn "*movtf_cc_reg_hq_sp64"
2928 [(set (match_operand:TF 0 "register_operand" "=e")
2929 (if_then_else:TF (match_operator 1 "v9_register_comparison_operator"
2930 [(match_operand:DI 2 "register_operand" "r")
2932 (match_operand:TF 3 "register_operand" "e")
2933 (match_operand:TF 4 "register_operand" "0")))]
2934 "TARGET_ARCH64 && TARGET_FPU && TARGET_HARD_QUAD"
2935 "fmovrq%D1\t%2, %3, %0"
2936 [(set_attr "type" "fpcrmove")])
2938 (define_insn_and_split "*movtf_cc_v9"
2939 [(set (match_operand:TF 0 "register_operand" "=e")
2940 (if_then_else:TF (match_operator 1 "icc_or_fcc_comparison_operator"
2941 [(match_operand 2 "icc_or_fcc_register_operand" "X")
2943 (match_operand:TF 3 "register_operand" "e")
2944 (match_operand:TF 4 "register_operand" "0")))]
2945 "TARGET_V9 && TARGET_FPU && !TARGET_HARD_QUAD"
2947 "&& reload_completed"
2948 [(clobber (const_int 0))]
2950 rtx set_dest = operands[0];
2951 rtx set_srca = operands[3];
2955 dest1 = gen_df_reg (set_dest, 0);
2956 dest2 = gen_df_reg (set_dest, 1);
2957 srca1 = gen_df_reg (set_srca, 0);
2958 srca2 = gen_df_reg (set_srca, 1);
2960 if (reg_overlap_mentioned_p (dest1, srca2))
2962 emit_insn (gen_movdf_cc_v9 (dest2, operands[1], operands[2],
2964 emit_insn (gen_movdf_cc_v9 (dest1, operands[1], operands[2],
2969 emit_insn (gen_movdf_cc_v9 (dest1, operands[1], operands[2],
2971 emit_insn (gen_movdf_cc_v9 (dest2, operands[1], operands[2],
2976 [(set_attr "length" "2")])
2978 (define_insn_and_split "*movtf_cc_reg_sp64"
2979 [(set (match_operand:TF 0 "register_operand" "=e")
2980 (if_then_else:TF (match_operator 1 "v9_register_comparison_operator"
2981 [(match_operand:DI 2 "register_operand" "r")
2983 (match_operand:TF 3 "register_operand" "e")
2984 (match_operand:TF 4 "register_operand" "0")))]
2985 "TARGET_ARCH64 && TARGET_FPU && !TARGET_HARD_QUAD"
2987 "&& reload_completed"
2988 [(clobber (const_int 0))]
2990 rtx set_dest = operands[0];
2991 rtx set_srca = operands[3];
2995 dest1 = gen_df_reg (set_dest, 0);
2996 dest2 = gen_df_reg (set_dest, 1);
2997 srca1 = gen_df_reg (set_srca, 0);
2998 srca2 = gen_df_reg (set_srca, 1);
3000 if (reg_overlap_mentioned_p (dest1, srca2))
3002 emit_insn (gen_movdf_cc_reg_sp64 (dest2, operands[1], operands[2],
3004 emit_insn (gen_movdf_cc_reg_sp64 (dest1, operands[1], operands[2],
3009 emit_insn (gen_movdf_cc_reg_sp64 (dest1, operands[1], operands[2],
3011 emit_insn (gen_movdf_cc_reg_sp64 (dest2, operands[1], operands[2],
3016 [(set_attr "length" "2")])
3019 ;; Zero-extension instructions
3021 ;; These patterns originally accepted general_operands, however, slightly
3022 ;; better code is generated by only accepting register_operands, and then
3023 ;; letting combine generate the ldu[hb] insns.
3025 (define_expand "zero_extendhisi2"
3026 [(set (match_operand:SI 0 "register_operand" "")
3027 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
3030 rtx temp = gen_reg_rtx (SImode);
3031 rtx shift_16 = GEN_INT (16);
3032 int op1_subbyte = 0;
3034 if (GET_CODE (operand1) == SUBREG)
3036 op1_subbyte = SUBREG_BYTE (operand1);
3037 op1_subbyte /= GET_MODE_SIZE (SImode);
3038 op1_subbyte *= GET_MODE_SIZE (SImode);
3039 operand1 = XEXP (operand1, 0);
3042 emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subbyte),
3044 emit_insn (gen_lshrsi3 (operand0, temp, shift_16));
3048 (define_insn "*zero_extendhisi2_insn"
3049 [(set (match_operand:SI 0 "register_operand" "=r")
3050 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
3053 [(set_attr "type" "load")
3054 (set_attr "subtype" "regular")
3055 (set_attr "us3load_type" "3cycle")])
3057 (define_expand "zero_extendqihi2"
3058 [(set (match_operand:HI 0 "register_operand" "")
3059 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
3063 (define_insn "*zero_extendqihi2_insn"
3064 [(set (match_operand:HI 0 "register_operand" "=r,r")
3065 (zero_extend:HI (match_operand:QI 1 "input_operand" "r,m")))]
3066 "GET_CODE (operands[1]) != CONST_INT"
3070 [(set_attr "type" "*,load")
3071 (set_attr "subtype" "*,regular")
3072 (set_attr "us3load_type" "*,3cycle")])
3074 (define_expand "zero_extendqisi2"
3075 [(set (match_operand:SI 0 "register_operand" "")
3076 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
3080 (define_insn "*zero_extendqisi2_insn"
3081 [(set (match_operand:SI 0 "register_operand" "=r,r")
3082 (zero_extend:SI (match_operand:QI 1 "input_operand" "r,m")))]
3083 "GET_CODE (operands[1]) != CONST_INT"
3087 [(set_attr "type" "*,load")
3088 (set_attr "subtype" "*,regular")
3089 (set_attr "us3load_type" "*,3cycle")])
3091 (define_expand "zero_extendqidi2"
3092 [(set (match_operand:DI 0 "register_operand" "")
3093 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
3097 (define_insn "*zero_extendqidi2_insn"
3098 [(set (match_operand:DI 0 "register_operand" "=r,r")
3099 (zero_extend:DI (match_operand:QI 1 "input_operand" "r,m")))]
3100 "TARGET_ARCH64 && GET_CODE (operands[1]) != CONST_INT"
3104 [(set_attr "type" "*,load")
3105 (set_attr "subtype" "*,regular")
3106 (set_attr "us3load_type" "*,3cycle")])
3108 (define_expand "zero_extendhidi2"
3109 [(set (match_operand:DI 0 "register_operand" "")
3110 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
3113 rtx temp = gen_reg_rtx (DImode);
3114 rtx shift_48 = GEN_INT (48);
3115 int op1_subbyte = 0;
3117 if (GET_CODE (operand1) == SUBREG)
3119 op1_subbyte = SUBREG_BYTE (operand1);
3120 op1_subbyte /= GET_MODE_SIZE (DImode);
3121 op1_subbyte *= GET_MODE_SIZE (DImode);
3122 operand1 = XEXP (operand1, 0);
3125 emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1, op1_subbyte),
3127 emit_insn (gen_lshrdi3 (operand0, temp, shift_48));
3131 (define_insn "*zero_extendhidi2_insn"
3132 [(set (match_operand:DI 0 "register_operand" "=r")
3133 (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
3136 [(set_attr "type" "load")
3137 (set_attr "subtype" "regular")
3138 (set_attr "us3load_type" "3cycle")])
3140 ;; ??? Write truncdisi pattern using sra?
3142 (define_expand "zero_extendsidi2"
3143 [(set (match_operand:DI 0 "register_operand" "")
3144 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))]
3148 (define_insn "*zero_extendsidi2_insn_sp64"
3149 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
3150 (zero_extend:DI (match_operand:SI 1 "input_operand" "r,m,*f")))]
3152 && GET_CODE (operands[1]) != CONST_INT"
3157 [(set_attr "type" "shift,load,vismv")
3158 (set_attr "subtype" "*,regular,movstouw")
3159 (set_attr "cpu_feature" "*,*,vis3")])
3161 (define_insn_and_split "*zero_extendsidi2_insn_sp32"
3162 [(set (match_operand:DI 0 "register_operand" "=r")
3163 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
3166 "&& reload_completed"
3167 [(set (match_dup 2) (match_dup 1))
3168 (set (match_dup 3) (const_int 0))]
3169 "operands[2] = gen_lowpart (SImode, operands[0]);
3170 operands[3] = gen_highpart (SImode, operands[0]);"
3171 [(set_attr "length" "2")])
3173 ;; Simplify comparisons of extended values.
3175 (define_insn "*cmp_zero_extendqisi2"
3176 [(set (reg:CC CC_REG)
3177 (compare:CC (zero_extend:SI (match_operand:QI 0 "register_operand" "r"))
3180 "andcc\t%0, 0xff, %%g0"
3181 [(set_attr "type" "compare")])
3183 (define_insn "*cmp_zero_qi"
3184 [(set (reg:CC CC_REG)
3185 (compare:CC (match_operand:QI 0 "register_operand" "r")
3188 "andcc\t%0, 0xff, %%g0"
3189 [(set_attr "type" "compare")])
3191 (define_insn "*cmp_zero_extendqisi2_set"
3192 [(set (reg:CC CC_REG)
3193 (compare:CC (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
3195 (set (match_operand:SI 0 "register_operand" "=r")
3196 (zero_extend:SI (match_dup 1)))]
3198 "andcc\t%1, 0xff, %0"
3199 [(set_attr "type" "compare")])
3201 (define_insn "*cmp_zero_extendqisi2_andcc_set"
3202 [(set (reg:CC CC_REG)
3203 (compare:CC (and:SI (match_operand:SI 1 "register_operand" "r")
3206 (set (match_operand:SI 0 "register_operand" "=r")
3207 (zero_extend:SI (subreg:QI (match_dup 1) 0)))]
3209 "andcc\t%1, 0xff, %0"
3210 [(set_attr "type" "compare")])
3212 (define_insn "*cmp_zero_extendqidi2"
3213 [(set (reg:CCX CC_REG)
3214 (compare:CCX (zero_extend:DI (match_operand:QI 0 "register_operand" "r"))
3217 "andcc\t%0, 0xff, %%g0"
3218 [(set_attr "type" "compare")])
3220 (define_insn "*cmp_zero_qi_sp64"
3221 [(set (reg:CCX CC_REG)
3222 (compare:CCX (match_operand:QI 0 "register_operand" "r")
3225 "andcc\t%0, 0xff, %%g0"
3226 [(set_attr "type" "compare")])
3228 (define_insn "*cmp_zero_extendqidi2_set"
3229 [(set (reg:CCX CC_REG)
3230 (compare:CCX (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
3232 (set (match_operand:DI 0 "register_operand" "=r")
3233 (zero_extend:DI (match_dup 1)))]
3235 "andcc\t%1, 0xff, %0"
3236 [(set_attr "type" "compare")])
3238 (define_insn "*cmp_zero_extendqidi2_andcc_set"
3239 [(set (reg:CCX CC_REG)
3240 (compare:CCX (and:DI (match_operand:DI 1 "register_operand" "r")
3243 (set (match_operand:DI 0 "register_operand" "=r")
3244 (zero_extend:DI (subreg:QI (match_dup 1) 0)))]
3246 "andcc\t%1, 0xff, %0"
3247 [(set_attr "type" "compare")])
3249 ;; Similarly, handle {SI,DI}->QI mode truncation followed by a compare.
3251 (define_insn "*cmp_siqi_trunc"
3252 [(set (reg:CC CC_REG)
3253 (compare:CC (subreg:QI (match_operand:SI 0 "register_operand" "r") 3)
3256 "andcc\t%0, 0xff, %%g0"
3257 [(set_attr "type" "compare")])
3259 (define_insn "*cmp_siqi_trunc_set"
3260 [(set (reg:CC CC_REG)
3261 (compare:CC (subreg:QI (match_operand:SI 1 "register_operand" "r") 3)
3263 (set (match_operand:QI 0 "register_operand" "=r")
3264 (subreg:QI (match_dup 1) 3))]
3266 "andcc\t%1, 0xff, %0"
3267 [(set_attr "type" "compare")])
3269 (define_insn "*cmp_diqi_trunc"
3270 [(set (reg:CC CC_REG)
3271 (compare:CC (subreg:QI (match_operand:DI 0 "register_operand" "r") 7)
3274 "andcc\t%0, 0xff, %%g0"
3275 [(set_attr "type" "compare")])
3277 (define_insn "*cmp_diqi_trunc_set"
3278 [(set (reg:CC CC_REG)
3279 (compare:CC (subreg:QI (match_operand:DI 1 "register_operand" "r") 7)
3281 (set (match_operand:QI 0 "register_operand" "=r")
3282 (subreg:QI (match_dup 1) 7))]
3284 "andcc\t%1, 0xff, %0"
3285 [(set_attr "type" "compare")])
3288 ;; Sign-extension instructions
3290 ;; These patterns originally accepted general_operands, however, slightly
3291 ;; better code is generated by only accepting register_operands, and then
3292 ;; letting combine generate the lds[hb] insns.
3294 (define_expand "extendhisi2"
3295 [(set (match_operand:SI 0 "register_operand" "")
3296 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
3299 rtx temp = gen_reg_rtx (SImode);
3300 rtx shift_16 = GEN_INT (16);
3301 int op1_subbyte = 0;
3303 if (GET_CODE (operand1) == SUBREG)
3305 op1_subbyte = SUBREG_BYTE (operand1);
3306 op1_subbyte /= GET_MODE_SIZE (SImode);
3307 op1_subbyte *= GET_MODE_SIZE (SImode);
3308 operand1 = XEXP (operand1, 0);
3311 emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subbyte),
3313 emit_insn (gen_ashrsi3 (operand0, temp, shift_16));
3317 (define_insn "*sign_extendhisi2_insn"
3318 [(set (match_operand:SI 0 "register_operand" "=r")
3319 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
3322 [(set_attr "type" "sload")
3323 (set_attr "us3load_type" "3cycle")])
3325 (define_expand "extendqihi2"
3326 [(set (match_operand:HI 0 "register_operand" "")
3327 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
3330 rtx temp = gen_reg_rtx (SImode);
3331 rtx shift_24 = GEN_INT (24);
3332 int op1_subbyte = 0;
3333 int op0_subbyte = 0;
3335 if (GET_CODE (operand1) == SUBREG)
3337 op1_subbyte = SUBREG_BYTE (operand1);
3338 op1_subbyte /= GET_MODE_SIZE (SImode);
3339 op1_subbyte *= GET_MODE_SIZE (SImode);
3340 operand1 = XEXP (operand1, 0);
3342 if (GET_CODE (operand0) == SUBREG)
3344 op0_subbyte = SUBREG_BYTE (operand0);
3345 op0_subbyte /= GET_MODE_SIZE (SImode);
3346 op0_subbyte *= GET_MODE_SIZE (SImode);
3347 operand0 = XEXP (operand0, 0);
3349 emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subbyte),
3351 if (GET_MODE (operand0) != SImode)
3352 operand0 = gen_rtx_SUBREG (SImode, operand0, op0_subbyte);
3353 emit_insn (gen_ashrsi3 (operand0, temp, shift_24));
3357 (define_insn "*sign_extendqihi2_insn"
3358 [(set (match_operand:HI 0 "register_operand" "=r")
3359 (sign_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
3362 [(set_attr "type" "sload")
3363 (set_attr "us3load_type" "3cycle")])
3365 (define_expand "extendqisi2"
3366 [(set (match_operand:SI 0 "register_operand" "")
3367 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
3370 rtx temp = gen_reg_rtx (SImode);
3371 rtx shift_24 = GEN_INT (24);
3372 int op1_subbyte = 0;
3374 if (GET_CODE (operand1) == SUBREG)
3376 op1_subbyte = SUBREG_BYTE (operand1);
3377 op1_subbyte /= GET_MODE_SIZE (SImode);
3378 op1_subbyte *= GET_MODE_SIZE (SImode);
3379 operand1 = XEXP (operand1, 0);
3382 emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subbyte),
3384 emit_insn (gen_ashrsi3 (operand0, temp, shift_24));
3388 (define_insn "*sign_extendqisi2_insn"
3389 [(set (match_operand:SI 0 "register_operand" "=r")
3390 (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
3393 [(set_attr "type" "sload")
3394 (set_attr "us3load_type" "3cycle")])
3396 (define_expand "extendqidi2"
3397 [(set (match_operand:DI 0 "register_operand" "")
3398 (sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
3401 rtx temp = gen_reg_rtx (DImode);
3402 rtx shift_56 = GEN_INT (56);
3403 int op1_subbyte = 0;
3405 if (GET_CODE (operand1) == SUBREG)
3407 op1_subbyte = SUBREG_BYTE (operand1);
3408 op1_subbyte /= GET_MODE_SIZE (DImode);
3409 op1_subbyte *= GET_MODE_SIZE (DImode);
3410 operand1 = XEXP (operand1, 0);
3413 emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1, op1_subbyte),
3415 emit_insn (gen_ashrdi3 (operand0, temp, shift_56));
3419 (define_insn "*sign_extendqidi2_insn"
3420 [(set (match_operand:DI 0 "register_operand" "=r")
3421 (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
3424 [(set_attr "type" "sload")
3425 (set_attr "us3load_type" "3cycle")])
3427 (define_expand "extendhidi2"
3428 [(set (match_operand:DI 0 "register_operand" "")
3429 (sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
3432 rtx temp = gen_reg_rtx (DImode);
3433 rtx shift_48 = GEN_INT (48);
3434 int op1_subbyte = 0;
3436 if (GET_CODE (operand1) == SUBREG)
3438 op1_subbyte = SUBREG_BYTE (operand1);
3439 op1_subbyte /= GET_MODE_SIZE (DImode);
3440 op1_subbyte *= GET_MODE_SIZE (DImode);
3441 operand1 = XEXP (operand1, 0);
3444 emit_insn (gen_ashldi3 (temp, gen_rtx_SUBREG (DImode, operand1, op1_subbyte),
3446 emit_insn (gen_ashrdi3 (operand0, temp, shift_48));
3450 (define_insn "*sign_extendhidi2_insn"
3451 [(set (match_operand:DI 0 "register_operand" "=r")
3452 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
3455 [(set_attr "type" "sload")
3456 (set_attr "us3load_type" "3cycle")])
3458 (define_expand "extendsidi2"
3459 [(set (match_operand:DI 0 "register_operand" "")
3460 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))]
3464 (define_insn "*sign_extendsidi2_insn"
3465 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
3466 (sign_extend:DI (match_operand:SI 1 "input_operand" "r,m,*f")))]
3472 [(set_attr "type" "shift,sload,vismv")
3473 (set_attr "us3load_type" "*,3cycle,*")
3474 (set_attr "cpu_feature" "*,*,vis3")])
3477 ;; Special pattern for optimizing bit-field compares. This is needed
3478 ;; because combine uses this as a canonical form.
3480 (define_insn "*cmp_zero_extract"
3481 [(set (reg:CC CC_REG)
3483 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
3484 (match_operand:SI 1 "small_int_operand" "I")
3485 (match_operand:SI 2 "small_int_operand" "I"))
3487 "INTVAL (operands[2]) > 19"
3489 int len = INTVAL (operands[1]);
3490 int pos = 32 - INTVAL (operands[2]) - len;
3491 HOST_WIDE_INT mask = ((1 << len) - 1) << pos;
3492 operands[1] = GEN_INT (mask);
3493 return "andcc\t%0, %1, %%g0";
3495 [(set_attr "type" "compare")])
3497 (define_insn "*cmp_zero_extract_sp64"
3498 [(set (reg:CCX CC_REG)
3500 (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
3501 (match_operand:SI 1 "small_int_operand" "I")
3502 (match_operand:SI 2 "small_int_operand" "I"))
3504 "TARGET_ARCH64 && INTVAL (operands[2]) > 51"
3506 int len = INTVAL (operands[1]);
3507 int pos = 64 - INTVAL (operands[2]) - len;
3508 HOST_WIDE_INT mask = (((unsigned HOST_WIDE_INT) 1 << len) - 1) << pos;
3509 operands[1] = GEN_INT (mask);
3510 return "andcc\t%0, %1, %%g0";
3512 [(set_attr "type" "compare")])
3515 ;; Conversions between float, double and long double.
3517 (define_insn "extendsfdf2"
3518 [(set (match_operand:DF 0 "register_operand" "=e")
3519 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
3522 [(set_attr "type" "fp")
3523 (set_attr "fptype" "double")])
3525 (define_expand "extendsftf2"
3526 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3527 (float_extend:TF (match_operand:SF 1 "register_operand" "")))]
3528 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
3529 "emit_tfmode_cvt (FLOAT_EXTEND, operands); DONE;")
3531 (define_insn "*extendsftf2_hq"
3532 [(set (match_operand:TF 0 "register_operand" "=e")
3533 (float_extend:TF (match_operand:SF 1 "register_operand" "f")))]
3534 "TARGET_FPU && TARGET_HARD_QUAD"
3536 [(set_attr "type" "fp")])
3538 (define_expand "extenddftf2"
3539 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3540 (float_extend:TF (match_operand:DF 1 "register_operand" "")))]
3541 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
3542 "emit_tfmode_cvt (FLOAT_EXTEND, operands); DONE;")
3544 (define_insn "*extenddftf2_hq"
3545 [(set (match_operand:TF 0 "register_operand" "=e")
3546 (float_extend:TF (match_operand:DF 1 "register_operand" "e")))]
3547 "TARGET_FPU && TARGET_HARD_QUAD"
3549 [(set_attr "type" "fp")])
3551 (define_insn "truncdfsf2"
3552 [(set (match_operand:SF 0 "register_operand" "=f")
3553 (float_truncate:SF (match_operand:DF 1 "register_operand" "e")))]
3556 [(set_attr "type" "fp")
3557 (set_attr "fptype" "double")
3558 (set_attr "fptype_ut699" "single")])
3560 (define_expand "trunctfsf2"
3561 [(set (match_operand:SF 0 "register_operand" "")
3562 (float_truncate:SF (match_operand:TF 1 "general_operand" "")))]
3563 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
3564 "emit_tfmode_cvt (FLOAT_TRUNCATE, operands); DONE;")
3566 (define_insn "*trunctfsf2_hq"
3567 [(set (match_operand:SF 0 "register_operand" "=f")
3568 (float_truncate:SF (match_operand:TF 1 "register_operand" "e")))]
3569 "TARGET_FPU && TARGET_HARD_QUAD"
3571 [(set_attr "type" "fp")])
3573 (define_expand "trunctfdf2"
3574 [(set (match_operand:DF 0 "register_operand" "")
3575 (float_truncate:DF (match_operand:TF 1 "general_operand" "")))]
3576 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
3577 "emit_tfmode_cvt (FLOAT_TRUNCATE, operands); DONE;")
3579 (define_insn "*trunctfdf2_hq"
3580 [(set (match_operand:DF 0 "register_operand" "=e")
3581 (float_truncate:DF (match_operand:TF 1 "register_operand" "e")))]
3582 "TARGET_FPU && TARGET_HARD_QUAD"
3584 [(set_attr "type" "fp")])
3587 ;; Conversion between fixed point and floating point.
3589 (define_insn "floatsisf2"
3590 [(set (match_operand:SF 0 "register_operand" "=f")
3591 (float:SF (match_operand:SI 1 "register_operand" "f")))]
3594 [(set_attr "type" "fp")
3595 (set_attr "fptype" "single")])
3597 (define_insn "floatsidf2"
3598 [(set (match_operand:DF 0 "register_operand" "=e")
3599 (float:DF (match_operand:SI 1 "register_operand" "f")))]
3602 [(set_attr "type" "fp")
3603 (set_attr "fptype" "double")])
3605 (define_expand "floatsitf2"
3606 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3607 (float:TF (match_operand:SI 1 "register_operand" "")))]
3608 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
3609 "emit_tfmode_cvt (FLOAT, operands); DONE;")
3611 (define_insn "*floatsitf2_hq"
3612 [(set (match_operand:TF 0 "register_operand" "=e")
3613 (float:TF (match_operand:SI 1 "register_operand" "f")))]
3614 "TARGET_FPU && TARGET_HARD_QUAD"
3616 [(set_attr "type" "fp")])
3618 (define_expand "floatunssitf2"
3619 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3620 (unsigned_float:TF (match_operand:SI 1 "register_operand" "")))]
3621 "TARGET_FPU && TARGET_ARCH64 && !TARGET_HARD_QUAD"
3622 "emit_tfmode_cvt (UNSIGNED_FLOAT, operands); DONE;")
3624 ;; Now the same for 64 bit sources.
3626 (define_insn "floatdisf2"
3627 [(set (match_operand:SF 0 "register_operand" "=f")
3628 (float:SF (match_operand:DI 1 "register_operand" "e")))]
3629 "TARGET_V9 && TARGET_FPU"
3631 [(set_attr "type" "fp")
3632 (set_attr "fptype" "double")])
3634 (define_expand "floatunsdisf2"
3635 [(use (match_operand:SF 0 "register_operand" ""))
3636 (use (match_operand:DI 1 "general_operand" ""))]
3637 "TARGET_ARCH64 && TARGET_FPU"
3638 "sparc_emit_floatunsdi (operands, SFmode); DONE;")
3640 (define_insn "floatdidf2"
3641 [(set (match_operand:DF 0 "register_operand" "=e")
3642 (float:DF (match_operand:DI 1 "register_operand" "e")))]
3643 "TARGET_V9 && TARGET_FPU"
3645 [(set_attr "type" "fp")
3646 (set_attr "fptype" "double")])
3648 (define_expand "floatunsdidf2"
3649 [(use (match_operand:DF 0 "register_operand" ""))
3650 (use (match_operand:DI 1 "general_operand" ""))]
3651 "TARGET_ARCH64 && TARGET_FPU"
3652 "sparc_emit_floatunsdi (operands, DFmode); DONE;")
3654 (define_expand "floatditf2"
3655 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3656 (float:TF (match_operand:DI 1 "register_operand" "")))]
3657 "TARGET_FPU && TARGET_V9 && (TARGET_HARD_QUAD || TARGET_ARCH64)"
3658 "emit_tfmode_cvt (FLOAT, operands); DONE;")
3660 (define_insn "*floatditf2_hq"
3661 [(set (match_operand:TF 0 "register_operand" "=e")
3662 (float:TF (match_operand:DI 1 "register_operand" "e")))]
3663 "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD"
3665 [(set_attr "type" "fp")])
3667 (define_expand "floatunsditf2"
3668 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3669 (unsigned_float:TF (match_operand:DI 1 "register_operand" "")))]
3670 "TARGET_FPU && TARGET_ARCH64 && !TARGET_HARD_QUAD"
3671 "emit_tfmode_cvt (UNSIGNED_FLOAT, operands); DONE;")
3673 ;; Convert a float to an actual integer.
3674 ;; Truncation is performed as part of the conversion.
3676 (define_insn "fix_truncsfsi2"
3677 [(set (match_operand:SI 0 "register_operand" "=f")
3678 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
3681 [(set_attr "type" "fp")
3682 (set_attr "fptype" "single")])
3684 (define_insn "fix_truncdfsi2"
3685 [(set (match_operand:SI 0 "register_operand" "=f")
3686 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "e"))))]
3689 [(set_attr "type" "fp")
3690 (set_attr "fptype" "double")
3691 (set_attr "fptype_ut699" "single")])
3693 (define_expand "fix_trunctfsi2"
3694 [(set (match_operand:SI 0 "register_operand" "")
3695 (fix:SI (match_operand:TF 1 "general_operand" "")))]
3696 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
3697 "emit_tfmode_cvt (FIX, operands); DONE;")
3699 (define_insn "*fix_trunctfsi2_hq"
3700 [(set (match_operand:SI 0 "register_operand" "=f")
3701 (fix:SI (match_operand:TF 1 "register_operand" "e")))]
3702 "TARGET_FPU && TARGET_HARD_QUAD"
3704 [(set_attr "type" "fp")])
3706 (define_expand "fixuns_trunctfsi2"
3707 [(set (match_operand:SI 0 "register_operand" "")
3708 (unsigned_fix:SI (match_operand:TF 1 "general_operand" "")))]
3709 "TARGET_FPU && TARGET_ARCH64 && !TARGET_HARD_QUAD"
3710 "emit_tfmode_cvt (UNSIGNED_FIX, operands); DONE;")
3712 ;; Now the same, for V9 targets
3714 (define_insn "fix_truncsfdi2"
3715 [(set (match_operand:DI 0 "register_operand" "=e")
3716 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
3717 "TARGET_V9 && TARGET_FPU"
3719 [(set_attr "type" "fp")
3720 (set_attr "fptype" "double")])
3722 (define_expand "fixuns_truncsfdi2"
3723 [(use (match_operand:DI 0 "register_operand" ""))
3724 (use (match_operand:SF 1 "general_operand" ""))]
3725 "TARGET_ARCH64 && TARGET_FPU"
3726 "sparc_emit_fixunsdi (operands, SFmode); DONE;")
3728 (define_insn "fix_truncdfdi2"
3729 [(set (match_operand:DI 0 "register_operand" "=e")
3730 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "e"))))]
3731 "TARGET_V9 && TARGET_FPU"
3733 [(set_attr "type" "fp")
3734 (set_attr "fptype" "double")])
3736 (define_expand "fixuns_truncdfdi2"
3737 [(use (match_operand:DI 0 "register_operand" ""))
3738 (use (match_operand:DF 1 "general_operand" ""))]
3739 "TARGET_ARCH64 && TARGET_FPU"
3740 "sparc_emit_fixunsdi (operands, DFmode); DONE;")
3742 (define_expand "fix_trunctfdi2"
3743 [(set (match_operand:DI 0 "register_operand" "")
3744 (fix:DI (match_operand:TF 1 "general_operand" "")))]
3745 "TARGET_V9 && TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
3746 "emit_tfmode_cvt (FIX, operands); DONE;")
3748 (define_insn "*fix_trunctfdi2_hq"
3749 [(set (match_operand:DI 0 "register_operand" "=e")
3750 (fix:DI (match_operand:TF 1 "register_operand" "e")))]
3751 "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD"
3753 [(set_attr "type" "fp")])
3755 (define_expand "fixuns_trunctfdi2"
3756 [(set (match_operand:DI 0 "register_operand" "")
3757 (unsigned_fix:DI (match_operand:TF 1 "general_operand" "")))]
3758 "TARGET_FPU && TARGET_ARCH64 && !TARGET_HARD_QUAD"
3759 "emit_tfmode_cvt (UNSIGNED_FIX, operands); DONE;")
3762 ;; Integer addition/subtraction instructions.
3764 (define_expand "adddi3"
3765 [(set (match_operand:DI 0 "register_operand" "")
3766 (plus:DI (match_operand:DI 1 "register_operand" "")
3767 (match_operand:DI 2 "arith_double_add_operand" "")))]
3772 emit_insn (gen_adddi3_sp32 (operands[0], operands[1], operands[2]));
3777 (define_expand "uaddvdi4"
3778 [(parallel [(set (reg:CCXC CC_REG)
3779 (compare:CCXC (plus:DI (match_operand:DI 1 "register_operand")
3780 (match_operand:DI 2 "arith_add_operand"))
3782 (set (match_operand:DI 0 "register_operand")
3783 (plus:DI (match_dup 1) (match_dup 2)))])
3784 (set (pc) (if_then_else (ltu (reg:CCXC CC_REG) (const_int 0))
3785 (label_ref (match_operand 3))
3791 emit_insn (gen_uaddvdi4_sp32 (operands[0], operands[1], operands[2]));
3792 rtx x = gen_rtx_LTU (VOIDmode, gen_rtx_REG (CCCmode, SPARC_ICC_REG),
3794 emit_jump_insn (gen_cbranchcc4 (x, XEXP (x, 0), XEXP (x, 1), operands[3]));
3799 (define_expand "addvdi4"
3800 [(parallel [(set (reg:CCXV CC_REG)
3801 (compare:CCXV (plus:DI (match_operand:DI 1 "register_operand")
3802 (match_operand:DI 2 "arith_add_operand"))
3803 (unspec:DI [(match_dup 1) (match_dup 2)]
3805 (set (match_operand:DI 0 "register_operand")
3806 (plus:DI (match_dup 1) (match_dup 2)))])
3807 (set (pc) (if_then_else (ne (reg:CCXV CC_REG) (const_int 0))
3808 (label_ref (match_operand 3))
3814 emit_insn (gen_addvdi4_sp32 (operands[0], operands[1], operands[2]));
3815 rtx x = gen_rtx_NE (VOIDmode, gen_rtx_REG (CCVmode, SPARC_ICC_REG),
3817 emit_jump_insn (gen_cbranchcc4 (x, XEXP (x, 0), XEXP (x, 1), operands[3]));
3822 (define_insn_and_split "adddi3_sp32"
3823 [(set (match_operand:DI 0 "register_operand" "=&r")
3824 (plus:DI (match_operand:DI 1 "register_operand" "%r")
3825 (match_operand:DI 2 "arith_double_operand" "rHI")))
3826 (clobber (reg:CC CC_REG))]
3829 "&& reload_completed"
3830 [(parallel [(set (reg:CCC CC_REG)
3831 (compare:CCC (plus:SI (match_dup 4) (match_dup 5))
3834 (plus:SI (match_dup 4) (match_dup 5)))])
3836 (plus:SI (plus:SI (match_dup 7) (match_dup 8))
3837 (ltu:SI (reg:CCC CC_REG) (const_int 0))))]
3839 operands[3] = gen_lowpart (SImode, operands[0]);
3840 operands[4] = gen_lowpart (SImode, operands[1]);
3841 operands[5] = gen_lowpart (SImode, operands[2]);
3842 operands[6] = gen_highpart (SImode, operands[0]);
3843 operands[7] = gen_highpart_mode (SImode, DImode, operands[1]);
3844 operands[8] = gen_highpart_mode (SImode, DImode, operands[2]);
3846 [(set_attr "length" "2")])
3848 (define_insn_and_split "uaddvdi4_sp32"
3849 [(set (reg:CCC CC_REG)
3850 (compare:CCC (plus:DI (match_operand:DI 1 "register_operand" "%r")
3851 (match_operand:DI 2 "arith_double_operand" "rHI"))
3853 (set (match_operand:DI 0 "register_operand" "=&r")
3854 (plus:DI (match_dup 1) (match_dup 2)))]
3857 "&& reload_completed"
3858 [(parallel [(set (reg:CCC CC_REG)
3859 (compare:CCC (plus:SI (match_dup 4) (match_dup 5))
3862 (plus:SI (match_dup 4) (match_dup 5)))])
3863 (parallel [(set (reg:CCC CC_REG)
3864 (compare:CCC (zero_extend:DI
3865 (plus:SI (plus:SI (match_dup 7) (match_dup 8))
3866 (ltu:SI (reg:CCC CC_REG)
3868 (plus:DI (plus:DI (zero_extend:DI (match_dup 7))
3869 (zero_extend:DI (match_dup 8)))
3870 (ltu:DI (reg:CCC CC_REG)
3873 (plus:SI (plus:SI (match_dup 7) (match_dup 8))
3874 (ltu:SI (reg:CCC CC_REG)
3877 operands[3] = gen_lowpart (SImode, operands[0]);
3878 operands[4] = gen_lowpart (SImode, operands[1]);
3879 operands[5] = gen_lowpart (SImode, operands[2]);
3880 operands[6] = gen_highpart (SImode, operands[0]);
3881 operands[7] = gen_highpart_mode (SImode, DImode, operands[1]);
3882 operands[8] = gen_highpart_mode (SImode, DImode, operands[2]);
3884 [(set_attr "length" "2")])
3886 (define_insn_and_split "addvdi4_sp32"
3887 [(set (reg:CCV CC_REG)
3888 (compare:CCV (plus:DI (match_operand:DI 1 "register_operand" "%r")
3889 (match_operand:DI 2 "arith_double_operand" "rHI"))
3890 (unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_ADDV)))
3891 (set (match_operand:DI 0 "register_operand" "=&r")
3892 (plus:DI (match_dup 1) (match_dup 2)))]
3895 "&& reload_completed"
3896 [(parallel [(set (reg:CCC CC_REG)
3897 (compare:CCC (plus:SI (match_dup 4) (match_dup 5))
3900 (plus:SI (match_dup 4) (match_dup 5)))])
3901 (parallel [(set (reg:CCV CC_REG)
3902 (compare:CCV (plus:SI (plus:SI (match_dup 7) (match_dup 8))
3903 (ltu:SI (reg:CCC CC_REG)
3905 (unspec:SI [(plus:SI (match_dup 7) (match_dup 8))
3906 (ltu:SI (reg:CCC CC_REG)
3910 (plus:SI (plus:SI (match_dup 7) (match_dup 8))
3911 (ltu:SI (reg:CCC CC_REG) (const_int 0))))])]
3913 operands[3] = gen_lowpart (SImode, operands[0]);
3914 operands[4] = gen_lowpart (SImode, operands[1]);
3915 operands[5] = gen_lowpart (SImode, operands[2]);
3916 operands[6] = gen_highpart (SImode, operands[0]);
3917 operands[7] = gen_highpart_mode (SImode, DImode, operands[1]);
3918 operands[8] = gen_highpart_mode (SImode, DImode, operands[2]);
3920 [(set_attr "length" "2")])
3922 (define_insn_and_split "*addx_extend_sp32"
3923 [(set (match_operand:DI 0 "register_operand" "=r")
3924 (zero_extend:DI (plus:SI (plus:SI
3925 (match_operand:SI 1 "register_operand" "%r")
3926 (match_operand:SI 2 "arith_operand" "rI"))
3927 (ltu:SI (reg:CCC CC_REG) (const_int 0)))))]
3930 "&& reload_completed"
3931 [(set (match_dup 3) (plus:SI (plus:SI (match_dup 1) (match_dup 2))
3932 (ltu:SI (reg:CCC CC_REG) (const_int 0))))
3933 (set (match_dup 4) (const_int 0))]
3934 "operands[3] = gen_lowpart (SImode, operands[0]);
3935 operands[4] = gen_highpart (SImode, operands[0]);"
3936 [(set_attr "length" "2")])
3938 (define_insn_and_split "*adddi3_extend_sp32"
3939 [(set (match_operand:DI 0 "register_operand" "=&r")
3940 (plus:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
3941 (match_operand:DI 2 "register_operand" "r")))
3942 (clobber (reg:CC CC_REG))]
3945 "&& reload_completed"
3946 [(parallel [(set (reg:CCC CC_REG)
3947 (compare:CCC (plus:SI (match_dup 3) (match_dup 1))
3949 (set (match_dup 5) (plus:SI (match_dup 3) (match_dup 1)))])
3951 (plus:SI (plus:SI (match_dup 4) (const_int 0))
3952 (ltu:SI (reg:CCC CC_REG) (const_int 0))))]
3953 "operands[3] = gen_lowpart (SImode, operands[2]);
3954 operands[4] = gen_highpart (SImode, operands[2]);
3955 operands[5] = gen_lowpart (SImode, operands[0]);
3956 operands[6] = gen_highpart (SImode, operands[0]);"
3957 [(set_attr "length" "2")])
3959 (define_insn "*adddi3_sp64"
3960 [(set (match_operand:DI 0 "register_operand" "=r,r")
3961 (plus:DI (match_operand:DI 1 "register_operand" "%r,r")
3962 (match_operand:DI 2 "arith_add_operand" "rI,O")))]
3968 (define_insn "addsi3"
3969 [(set (match_operand:SI 0 "register_operand" "=r,r")
3970 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
3971 (match_operand:SI 2 "arith_add_operand" "rI,O")))]
3976 [(set_attr "type" "*,*")
3977 (set_attr "fptype" "*,*")])
3979 (define_expand "uaddvsi4"
3980 [(parallel [(set (reg:CCC CC_REG)
3981 (compare:CCC (plus:SI (match_operand:SI 1 "register_operand")
3982 (match_operand:SI 2 "arith_operand"))
3984 (set (match_operand:SI 0 "register_operand")
3985 (plus:SI (match_dup 1) (match_dup 2)))])
3986 (set (pc) (if_then_else (ltu (reg:CCC CC_REG) (const_int 0))
3987 (label_ref (match_operand 3))
3991 (define_expand "addvsi4"
3992 [(parallel [(set (reg:CCV CC_REG)
3993 (compare:CCV (plus:SI (match_operand:SI 1 "register_operand")
3994 (match_operand:SI 2 "arith_operand"))
3995 (unspec:SI [(match_dup 1) (match_dup 2)]
3997 (set (match_operand:SI 0 "register_operand")
3998 (plus:SI (match_dup 1) (match_dup 2)))])
3999 (set (pc) (if_then_else (ne (reg:CCV CC_REG) (const_int 0))
4000 (label_ref (match_operand 3))
4004 (define_insn "*cmp_ccnz_plus"
4005 [(set (reg:CCNZ CC_REG)
4006 (compare:CCNZ (plus:SI (match_operand:SI 0 "register_operand" "%r")
4007 (match_operand:SI 1 "arith_operand" "rI"))
4010 "addcc\t%0, %1, %%g0"
4011 [(set_attr "type" "compare")])
4013 (define_insn "*cmp_ccxnz_plus"
4014 [(set (reg:CCXNZ CC_REG)
4015 (compare:CCXNZ (plus:DI (match_operand:DI 0 "register_operand" "%r")
4016 (match_operand:DI 1 "arith_operand" "rI"))
4019 "addcc\t%0, %1, %%g0"
4020 [(set_attr "type" "compare")])
4022 (define_insn "*cmp_ccnz_plus_set"
4023 [(set (reg:CCNZ CC_REG)
4024 (compare:CCNZ (plus:SI (match_operand:SI 1 "register_operand" "%r")
4025 (match_operand:SI 2 "arith_operand" "rI"))
4027 (set (match_operand:SI 0 "register_operand" "=r")
4028 (plus:SI (match_dup 1) (match_dup 2)))]
4031 [(set_attr "type" "compare")])
4033 (define_insn "*cmp_ccxnz_plus_set"
4034 [(set (reg:CCXNZ CC_REG)
4035 (compare:CCXNZ (plus:DI (match_operand:DI 1 "register_operand" "%r")
4036 (match_operand:DI 2 "arith_operand" "rI"))
4038 (set (match_operand:DI 0 "register_operand" "=r")
4039 (plus:DI (match_dup 1) (match_dup 2)))]
4042 [(set_attr "type" "compare")])
4044 (define_insn "*cmp_ccc_plus"
4045 [(set (reg:CCC CC_REG)
4046 (compare:CCC (plus:SI (match_operand:SI 0 "register_operand" "%r")
4047 (match_operand:SI 1 "arith_operand" "rI"))
4050 "addcc\t%0, %1, %%g0"
4051 [(set_attr "type" "compare")])
4053 (define_insn "*cmp_ccxc_plus"
4054 [(set (reg:CCXC CC_REG)
4055 (compare:CCXC (plus:DI (match_operand:DI 0 "register_operand" "%r")
4056 (match_operand:DI 1 "arith_operand" "rI"))
4059 "addcc\t%0, %1, %%g0"
4060 [(set_attr "type" "compare")])
4062 (define_insn "*cmp_ccc_plus_set"
4063 [(set (reg:CCC CC_REG)
4064 (compare:CCC (plus:SI (match_operand:SI 1 "register_operand" "%r")
4065 (match_operand:SI 2 "arith_operand" "rI"))
4067 (set (match_operand:SI 0 "register_operand" "=r")
4068 (plus:SI (match_dup 1) (match_dup 2)))]
4071 [(set_attr "type" "compare")])
4073 (define_insn "*cmp_ccxc_plus_set"
4074 [(set (reg:CCXC CC_REG)
4075 (compare:CCXC (plus:DI (match_operand:DI 1 "register_operand" "%r")
4076 (match_operand:DI 2 "arith_operand" "rI"))
4078 (set (match_operand:DI 0 "register_operand" "=r")
4079 (plus:DI (match_dup 1) (match_dup 2)))]
4082 [(set_attr "type" "compare")])
4084 (define_insn "*cmp_ccc_plus_sltu_set"
4085 [(set (reg:CCC CC_REG)
4086 (compare:CCC (zero_extend:DI
4088 (plus:SI (match_operand:SI 1 "register_operand" "%r")
4089 (match_operand:SI 2 "arith_operand" "rI"))
4090 (ltu:SI (reg:CCC CC_REG) (const_int 0))))
4091 (plus:DI (plus:DI (zero_extend:DI (match_dup 1))
4092 (zero_extend:DI (match_dup 2)))
4093 (ltu:DI (reg:CCC CC_REG) (const_int 0)))))
4094 (set (match_operand:SI 0 "register_operand" "=r")
4095 (plus:SI (plus:SI (match_dup 1) (match_dup 2))
4096 (ltu:SI (reg:CCC CC_REG) (const_int 0))))]
4098 "addxcc\t%1, %2, %0"
4099 [(set_attr "type" "compare")])
4101 (define_insn "*cmp_ccv_plus"
4102 [(set (reg:CCV CC_REG)
4103 (compare:CCV (plus:SI (match_operand:SI 0 "register_operand" "%r")
4104 (match_operand:SI 1 "arith_operand" "rI"))
4105 (unspec:SI [(match_dup 0) (match_dup 1)] UNSPEC_ADDV)))]
4107 "addcc\t%0, %1, %%g0"
4108 [(set_attr "type" "compare")])
4110 (define_insn "*cmp_ccxv_plus"
4111 [(set (reg:CCXV CC_REG)
4112 (compare:CCXV (plus:DI (match_operand:DI 0 "register_operand" "%r")
4113 (match_operand:DI 1 "arith_operand" "rI"))
4114 (unspec:DI [(match_dup 0) (match_dup 1)] UNSPEC_ADDV)))]
4116 "addcc\t%0, %1, %%g0"
4117 [(set_attr "type" "compare")])
4119 (define_insn "*cmp_ccv_plus_set"
4120 [(set (reg:CCV CC_REG)
4121 (compare:CCV (plus:SI (match_operand:SI 1 "register_operand" "%r")
4122 (match_operand:SI 2 "arith_operand" "rI"))
4123 (unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_ADDV)))
4124 (set (match_operand:SI 0 "register_operand" "=r")
4125 (plus:SI (match_dup 1) (match_dup 2)))]
4128 [(set_attr "type" "compare")])
4130 (define_insn "*cmp_ccxv_plus_set"
4131 [(set (reg:CCXV CC_REG)
4132 (compare:CCXV (plus:DI (match_operand:DI 1 "register_operand" "%r")
4133 (match_operand:DI 2 "arith_operand" "rI"))
4134 (unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_ADDV)))
4135 (set (match_operand:DI 0 "register_operand" "=r")
4136 (plus:DI (match_dup 1) (match_dup 2)))]
4139 [(set_attr "type" "compare")])
4141 (define_insn "*cmp_ccv_plus_sltu_set"
4142 [(set (reg:CCV CC_REG)
4143 (compare:CCV (plus:SI (plus:SI (match_operand:SI 1 "register_operand" "%r")
4144 (match_operand:SI 2 "arith_operand" "rI"))
4145 (ltu:SI (reg:CCC CC_REG) (const_int 0)))
4146 (unspec:SI [(plus:SI (match_dup 1) (match_dup 2))
4147 (ltu:SI (reg:CCC CC_REG) (const_int 0))]
4149 (set (match_operand:SI 0 "register_operand" "=r")
4150 (plus:SI (plus:SI (match_dup 1) (match_dup 2))
4151 (ltu:SI (reg:CCC CC_REG) (const_int 0))))]
4153 "addxcc\t%1, %2, %0"
4154 [(set_attr "type" "compare")])
4157 (define_expand "subdi3"
4158 [(set (match_operand:DI 0 "register_operand" "")
4159 (minus:DI (match_operand:DI 1 "register_operand" "")
4160 (match_operand:DI 2 "arith_double_add_operand" "")))]
4165 emit_insn (gen_subdi3_sp32 (operands[0], operands[1], operands[2]));
4170 (define_expand "usubvdi4"
4171 [(parallel [(set (reg:CCX CC_REG)
4172 (compare:CCX (match_operand:DI 1 "register_or_zero_operand")
4173 (match_operand:DI 2 "arith_add_operand")))
4174 (set (match_operand:DI 0 "register_operand")
4175 (minus:DI (match_dup 1) (match_dup 2)))])
4176 (set (pc) (if_then_else (ltu (reg:CCX CC_REG) (const_int 0))
4177 (label_ref (match_operand 3))
4181 if (operands[1] == const0_rtx)
4183 emit_insn (gen_unegvdi3 (operands[0], operands[2], operands[3]));
4189 emit_insn (gen_usubvdi4_sp32 (operands[0], operands[1], operands[2]));
4190 rtx x = gen_rtx_LTU (VOIDmode, gen_rtx_REG (CCCmode, SPARC_ICC_REG),
4192 emit_jump_insn (gen_cbranchcc4 (x, XEXP (x, 0), XEXP (x, 1), operands[3]));
4197 (define_expand "subvdi4"
4198 [(parallel [(set (reg:CCXV CC_REG)
4199 (compare:CCXV (minus:DI (match_operand:DI 1 "register_operand")
4200 (match_operand:DI 2 "arith_add_operand"))
4201 (unspec:DI [(match_dup 1) (match_dup 2)]
4203 (set (match_operand:DI 0 "register_operand")
4204 (minus:DI (match_dup 1) (match_dup 2)))])
4205 (set (pc) (if_then_else (ne (reg:CCXV CC_REG) (const_int 0))
4206 (label_ref (match_operand 3))
4212 emit_insn (gen_subvdi4_sp32 (operands[0], operands[1], operands[2]));
4213 rtx x = gen_rtx_NE (VOIDmode, gen_rtx_REG (CCVmode, SPARC_ICC_REG),
4215 emit_jump_insn (gen_cbranchcc4 (x, XEXP (x, 0), XEXP (x, 1), operands[3]));
4220 (define_insn_and_split "subdi3_sp32"
4221 [(set (match_operand:DI 0 "register_operand" "=&r")
4222 (minus:DI (match_operand:DI 1 "register_operand" "r")
4223 (match_operand:DI 2 "arith_double_operand" "rHI")))
4224 (clobber (reg:CC CC_REG))]
4227 "&& reload_completed"
4228 [(parallel [(set (reg:CC CC_REG)
4229 (compare:CC (match_dup 4) (match_dup 5)))
4231 (minus:SI (match_dup 4) (match_dup 5)))])
4233 (minus:SI (minus:SI (match_dup 7) (match_dup 8))
4234 (ltu:SI (reg:CC CC_REG) (const_int 0))))]
4236 operands[3] = gen_lowpart (SImode, operands[0]);
4237 operands[4] = gen_lowpart (SImode, operands[1]);
4238 operands[5] = gen_lowpart (SImode, operands[2]);
4239 operands[6] = gen_highpart (SImode, operands[0]);
4240 operands[7] = gen_highpart (SImode, operands[1]);
4241 operands[8] = gen_highpart_mode (SImode, DImode, operands[2]);
4243 [(set_attr "length" "2")])
4245 (define_insn_and_split "usubvdi4_sp32"
4246 [(set (reg:CCC CC_REG)
4247 (compare:CCC (match_operand:DI 1 "register_operand" "r")
4248 (match_operand:DI 2 "arith_double_operand" "rHI")))
4249 (set (match_operand:DI 0 "register_operand" "=&r")
4250 (minus:DI (match_dup 1) (match_dup 2)))]
4253 "&& reload_completed"
4254 [(parallel [(set (reg:CC CC_REG)
4255 (compare:CC (match_dup 4) (match_dup 5)))
4257 (minus:SI (match_dup 4) (match_dup 5)))])
4258 (parallel [(set (reg:CCC CC_REG)
4259 (compare:CCC (zero_extend:DI
4260 (minus:SI (minus:SI (match_dup 7)
4261 (ltu:SI (reg:CC CC_REG)
4265 (minus:DI (zero_extend:DI (match_dup 7))
4266 (ltu:DI (reg:CC CC_REG)
4268 (zero_extend:DI (match_dup 8)))))
4270 (minus:SI (minus:SI (match_dup 7)
4271 (ltu:SI (reg:CC CC_REG)
4275 operands[3] = gen_lowpart (SImode, operands[0]);
4276 operands[4] = gen_lowpart (SImode, operands[1]);
4277 operands[5] = gen_lowpart (SImode, operands[2]);
4278 operands[6] = gen_highpart (SImode, operands[0]);
4279 operands[7] = gen_highpart_mode (SImode, DImode, operands[1]);
4280 operands[8] = gen_highpart_mode (SImode, DImode, operands[2]);
4282 [(set_attr "length" "2")])
4284 (define_insn_and_split "subvdi4_sp32"
4285 [(set (reg:CCV CC_REG)
4286 (compare:CCV (minus:DI (match_operand:DI 1 "register_operand" "%r")
4287 (match_operand:DI 2 "arith_double_operand" "rHI"))
4288 (unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_SUBV)))
4289 (set (match_operand:DI 0 "register_operand" "=&r")
4290 (minus:DI (match_dup 1) (match_dup 2)))]
4293 "&& reload_completed"
4294 [(parallel [(set (reg:CC CC_REG)
4295 (compare:CC (match_dup 4) (match_dup 5)))
4297 (minus:SI (match_dup 4) (match_dup 5)))])
4298 (parallel [(set (reg:CCV CC_REG)
4299 (compare:CCV (minus:SI (minus:SI (match_dup 7) (match_dup 8))
4300 (ltu:SI (reg:CC CC_REG)
4302 (unspec:SI [(minus:SI (match_dup 7) (match_dup 8))
4303 (ltu:SI (reg:CC CC_REG)
4307 (minus:SI (minus:SI (match_dup 7) (match_dup 8))
4308 (ltu:SI (reg:CC CC_REG) (const_int 0))))])]
4310 operands[3] = gen_lowpart (SImode, operands[0]);
4311 operands[4] = gen_lowpart (SImode, operands[1]);
4312 operands[5] = gen_lowpart (SImode, operands[2]);
4313 operands[6] = gen_highpart (SImode, operands[0]);
4314 operands[7] = gen_highpart_mode (SImode, DImode, operands[1]);
4315 operands[8] = gen_highpart_mode (SImode, DImode, operands[2]);
4317 [(set_attr "length" "2")])
4319 (define_insn_and_split "*subx_extend_sp32"
4320 [(set (match_operand:DI 0 "register_operand" "=r")
4321 (zero_extend:DI (minus:SI (minus:SI
4322 (match_operand:SI 1 "register_or_zero_operand" "rJ")
4323 (match_operand:SI 2 "arith_operand" "rI"))
4324 (ltu:SI (reg:CCC CC_REG) (const_int 0)))))]
4327 "&& reload_completed"
4328 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 1) (match_dup 2))
4329 (ltu:SI (reg:CCC CC_REG) (const_int 0))))
4330 (set (match_dup 4) (const_int 0))]
4331 "operands[3] = gen_lowpart (SImode, operands[0]);
4332 operands[4] = gen_highpart (SImode, operands[0]);"
4333 [(set_attr "length" "2")])
4335 (define_insn_and_split "*subdi3_extend_sp32"
4336 [(set (match_operand:DI 0 "register_operand" "=&r")
4337 (minus:DI (match_operand:DI 1 "register_operand" "r")
4338 (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))
4339 (clobber (reg:CC CC_REG))]
4342 "&& reload_completed"
4343 [(parallel [(set (reg:CC CC_REG)
4344 (compare:CC (match_dup 3) (match_dup 2)))
4345 (set (match_dup 5) (minus:SI (match_dup 3) (match_dup 2)))])
4347 (minus:SI (minus:SI (match_dup 4) (const_int 0))
4348 (ltu:SI (reg:CC CC_REG) (const_int 0))))]
4349 "operands[3] = gen_lowpart (SImode, operands[1]);
4350 operands[4] = gen_highpart (SImode, operands[1]);
4351 operands[5] = gen_lowpart (SImode, operands[0]);
4352 operands[6] = gen_highpart (SImode, operands[0]);"
4353 [(set_attr "length" "2")])
4355 (define_insn "*subdi3_sp64"
4356 [(set (match_operand:DI 0 "register_operand" "=r,r")
4357 (minus:DI (match_operand:DI 1 "register_operand" "r,r")
4358 (match_operand:DI 2 "arith_add_operand" "rI,O")))]
4364 (define_insn "subsi3"
4365 [(set (match_operand:SI 0 "register_operand" "=r,r")
4366 (minus:SI (match_operand:SI 1 "register_operand" "r,r")
4367 (match_operand:SI 2 "arith_add_operand" "rI,O")))]
4372 [(set_attr "type" "*,*")
4373 (set_attr "fptype" "*,*")])
4375 (define_expand "usubvsi4"
4376 [(parallel [(set (reg:CC CC_REG)
4377 (compare:CC (match_operand:SI 1 "register_or_zero_operand")
4378 (match_operand:SI 2 "arith_operand")))
4379 (set (match_operand:SI 0 "register_operand")
4380 (minus:SI (match_dup 1) (match_dup 2)))])
4381 (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
4382 (label_ref (match_operand 3))
4386 if (operands[1] == const0_rtx)
4388 emit_insn (gen_unegvsi3 (operands[0], operands[2], operands[3]));
4393 (define_expand "subvsi4"
4394 [(parallel [(set (reg:CCV CC_REG)
4395 (compare:CCV (minus:SI (match_operand:SI 1 "register_operand")
4396 (match_operand:SI 2 "arith_operand"))
4397 (unspec:SI [(match_dup 1) (match_dup 2)]
4399 (set (match_operand:SI 0 "register_operand")
4400 (minus:SI (match_dup 1) (match_dup 2)))])
4401 (set (pc) (if_then_else (ne (reg:CCV CC_REG) (const_int 0))
4402 (label_ref (match_operand 3))
4406 (define_insn "*cmp_ccnz_minus"
4407 [(set (reg:CCNZ CC_REG)
4408 (compare:CCNZ (minus:SI (match_operand:SI 0 "register_or_zero_operand" "rJ")
4409 (match_operand:SI 1 "arith_operand" "rI"))
4412 "subcc\t%r0, %1, %%g0"
4413 [(set_attr "type" "compare")])
4415 (define_insn "*cmp_ccxnz_minus"
4416 [(set (reg:CCXNZ CC_REG)
4417 (compare:CCXNZ (minus:DI (match_operand:DI 0 "register_or_zero_operand" "rJ")
4418 (match_operand:DI 1 "arith_operand" "rI"))
4421 "subcc\t%r0, %1, %%g0"
4422 [(set_attr "type" "compare")])
4424 (define_insn "*cmp_ccnz_minus_set"
4425 [(set (reg:CCNZ CC_REG)
4426 (compare:CCNZ (minus:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
4427 (match_operand:SI 2 "arith_operand" "rI"))
4429 (set (match_operand:SI 0 "register_operand" "=r")
4430 (minus:SI (match_dup 1) (match_dup 2)))]
4432 "subcc\t%r1, %2, %0"
4433 [(set_attr "type" "compare")])
4435 (define_insn "*cmp_ccxnz_minus_set"
4436 [(set (reg:CCXNZ CC_REG)
4437 (compare:CCXNZ (minus:DI (match_operand:DI 1 "register_or_zero_operand" "rJ")
4438 (match_operand:DI 2 "arith_operand" "rI"))
4440 (set (match_operand:DI 0 "register_operand" "=r")
4441 (minus:DI (match_dup 1) (match_dup 2)))]
4443 "subcc\t%r1, %2, %0"
4444 [(set_attr "type" "compare")])
4446 (define_insn "*cmpsi_set"
4447 [(set (reg:CC CC_REG)
4448 (compare:CC (match_operand:SI 1 "register_or_zero_operand" "rJ")
4449 (match_operand:SI 2 "arith_operand" "rI")))
4450 (set (match_operand:SI 0 "register_operand" "=r")
4451 (minus:SI (match_dup 1) (match_dup 2)))]
4453 "subcc\t%r1, %2, %0"
4454 [(set_attr "type" "compare")])
4456 (define_insn "*cmpdi_set"
4457 [(set (reg:CCX CC_REG)
4458 (compare:CCX (match_operand:DI 1 "register_or_zero_operand" "rJ")
4459 (match_operand:DI 2 "arith_operand" "rI")))
4460 (set (match_operand:DI 0 "register_operand" "=r")
4461 (minus:DI (match_dup 1) (match_dup 2)))]
4463 "subcc\t%r1, %2, %0"
4464 [(set_attr "type" "compare")])
4466 (define_insn "*cmp_ccc_minus_sltu_set"
4467 [(set (reg:CCC CC_REG)
4468 (compare:CCC (zero_extend:DI
4471 (match_operand:SI 1 "register_or_zero_operand" "rJ")
4472 (ltu:SI (reg:CC CC_REG) (const_int 0)))
4473 (match_operand:SI 2 "arith_operand" "rI")))
4476 (zero_extend:DI (match_dup 1))
4477 (ltu:DI (reg:CC CC_REG) (const_int 0)))
4478 (zero_extend:DI (match_dup 2)))))
4479 (set (match_operand:SI 0 "register_operand" "=r")
4480 (minus:SI (minus:SI (match_dup 1)
4481 (ltu:SI (reg:CC CC_REG) (const_int 0)))
4484 "subxcc\t%r1, %2, %0"
4485 [(set_attr "type" "compare")])
4487 (define_insn "*cmp_ccv_minus"
4488 [(set (reg:CCV CC_REG)
4489 (compare:CCV (minus:SI (match_operand:SI 0 "register_or_zero_operand" "rJ")
4490 (match_operand:SI 1 "arith_operand" "rI"))
4491 (unspec:SI [(match_dup 0) (match_dup 1)] UNSPEC_SUBV)))]
4493 "subcc\t%r0, %1, %%g0"
4494 [(set_attr "type" "compare")])
4496 (define_insn "*cmp_ccxv_minus"
4497 [(set (reg:CCXV CC_REG)
4498 (compare:CCXV (minus:DI (match_operand:DI 0 "register_or_zero_operand" "rJ")
4499 (match_operand:DI 1 "arith_operand" "rI"))
4500 (unspec:DI [(match_dup 0) (match_dup 1)] UNSPEC_SUBV)))]
4502 "subcc\t%r0, %1, %%g0"
4503 [(set_attr "type" "compare")])
4505 (define_insn "*cmp_ccv_minus_set"
4506 [(set (reg:CCV CC_REG)
4507 (compare:CCV (minus:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
4508 (match_operand:SI 2 "arith_operand" "rI"))
4509 (unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_SUBV)))
4510 (set (match_operand:SI 0 "register_operand" "=r")
4511 (minus:SI (match_dup 1) (match_dup 2)))]
4513 "subcc\t%r1, %2, %0"
4514 [(set_attr "type" "compare")])
4516 (define_insn "*cmp_ccxv_minus_set"
4517 [(set (reg:CCXV CC_REG)
4518 (compare:CCXV (minus:DI (match_operand:DI 1 "register_or_zero_operand" "rJ")
4519 (match_operand:DI 2 "arith_operand" "rI"))
4520 (unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_SUBV)))
4521 (set (match_operand:DI 0 "register_operand" "=r")
4522 (minus:DI (match_dup 1) (match_dup 2)))]
4524 "subcc\t%r1, %2, %0"
4525 [(set_attr "type" "compare")])
4527 (define_insn "*cmp_ccv_minus_sltu_set"
4528 [(set (reg:CCV CC_REG)
4530 (minus:SI (minus:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
4531 (match_operand:SI 2 "arith_operand" "rI"))
4532 (ltu:SI (reg:CC CC_REG) (const_int 0)))
4533 (unspec:SI [(minus:SI (match_dup 1) (match_dup 2))
4534 (ltu:SI (reg:CC CC_REG) (const_int 0))]
4536 (set (match_operand:SI 0 "register_operand" "=r")
4537 (minus:SI (minus:SI (match_dup 1) (match_dup 2))
4538 (ltu:SI (reg:CC CC_REG) (const_int 0))))]
4540 "subxcc\t%1, %2, %0"
4541 [(set_attr "type" "compare")])
4544 ;; Integer multiply/divide instructions.
4546 ;; The 32-bit multiply/divide instructions are deprecated on v9, but at
4547 ;; least in UltraSPARC I, II and IIi it is a win tick-wise.
4549 (define_expand "mulsi3"
4550 [(set (match_operand:SI 0 "register_operand" "")
4551 (mult:SI (match_operand:SI 1 "arith_operand" "")
4552 (match_operand:SI 2 "arith_operand" "")))]
4553 "TARGET_HARD_MUL || TARGET_ARCH64"
4556 (define_insn "*mulsi3_sp32"
4557 [(set (match_operand:SI 0 "register_operand" "=r")
4558 (mult:SI (match_operand:SI 1 "arith_operand" "%r")
4559 (match_operand:SI 2 "arith_operand" "rI")))]
4562 [(set_attr "type" "imul")])
4564 (define_insn "*mulsi3_sp64"
4565 [(set (match_operand:SI 0 "register_operand" "=r")
4566 (mult:SI (match_operand:SI 1 "arith_operand" "%r")
4567 (match_operand:SI 2 "arith_operand" "rI")))]
4570 [(set_attr "type" "imul")])
4572 (define_expand "muldi3"
4573 [(set (match_operand:DI 0 "register_operand" "")
4574 (mult:DI (match_operand:DI 1 "arith_operand" "")
4575 (match_operand:DI 2 "arith_operand" "")))]
4576 "TARGET_ARCH64 || TARGET_V8PLUS"
4580 emit_insn (gen_muldi3_v8plus (operands[0], operands[1], operands[2]));
4585 (define_insn "*muldi3_sp64"
4586 [(set (match_operand:DI 0 "register_operand" "=r")
4587 (mult:DI (match_operand:DI 1 "arith_operand" "%r")
4588 (match_operand:DI 2 "arith_operand" "rI")))]
4591 [(set_attr "type" "imul")])
4593 ;; V8plus wide multiply.
4594 (define_insn "muldi3_v8plus"
4595 [(set (match_operand:DI 0 "register_operand" "=r,h")
4596 (mult:DI (match_operand:DI 1 "arith_operand" "%r,0")
4597 (match_operand:DI 2 "arith_operand" "rI,rI")))
4598 (clobber (match_scratch:SI 3 "=&h,X"))
4599 (clobber (match_scratch:SI 4 "=&h,X"))]
4602 return output_v8plus_mult (insn, operands, \"mulx\");
4604 [(set_attr "type" "multi")
4605 (set_attr "length" "9,8")])
4607 (define_insn "*cmp_mul_set"
4608 [(set (reg:CC CC_REG)
4609 (compare:CC (mult:SI (match_operand:SI 1 "arith_operand" "%r")
4610 (match_operand:SI 2 "arith_operand" "rI"))
4612 (set (match_operand:SI 0 "register_operand" "=r")
4613 (mult:SI (match_dup 1) (match_dup 2)))]
4614 "TARGET_V8 || TARGET_SPARCLITE || TARGET_DEPRECATED_V8_INSNS"
4615 "smulcc\t%1, %2, %0"
4616 [(set_attr "type" "imul")])
4618 (define_expand "mulsidi3"
4619 [(set (match_operand:DI 0 "register_operand" "")
4620 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
4621 (sign_extend:DI (match_operand:SI 2 "arith_operand" ""))))]
4624 if (CONSTANT_P (operands[2]))
4627 emit_insn (gen_const_mulsidi3_v8plus (operands[0], operands[1],
4629 else if (TARGET_ARCH32)
4630 emit_insn (gen_const_mulsidi3_sp32 (operands[0], operands[1],
4633 emit_insn (gen_const_mulsidi3_sp64 (operands[0], operands[1],
4639 emit_insn (gen_mulsidi3_v8plus (operands[0], operands[1], operands[2]));
4644 ;; V9 puts the 64-bit product in a 64-bit register. Only out or global
4645 ;; registers can hold 64-bit values in the V8plus environment.
4646 (define_insn "mulsidi3_v8plus"
4647 [(set (match_operand:DI 0 "register_operand" "=h,r")
4648 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
4649 (sign_extend:DI (match_operand:SI 2 "register_operand" "r,r"))))
4650 (clobber (match_scratch:SI 3 "=X,&h"))]
4653 smul\t%1, %2, %L0\n\tsrlx\t%L0, 32, %H0
4654 smul\t%1, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"
4655 [(set_attr "type" "multi")
4656 (set_attr "length" "2,3")])
4658 (define_insn "const_mulsidi3_v8plus"
4659 [(set (match_operand:DI 0 "register_operand" "=h,r")
4660 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
4661 (match_operand:DI 2 "small_int_operand" "I,I")))
4662 (clobber (match_scratch:SI 3 "=X,&h"))]
4665 smul\t%1, %2, %L0\n\tsrlx\t%L0, 32, %H0
4666 smul\t%1, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"
4667 [(set_attr "type" "multi")
4668 (set_attr "length" "2,3")])
4670 (define_insn "*mulsidi3_sp32"
4671 [(set (match_operand:DI 0 "register_operand" "=r")
4672 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
4673 (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
4676 return TARGET_SPARCLET
4677 ? "smuld\t%1, %2, %L0"
4678 : "smul\t%1, %2, %L0\n\trd\t%%y, %H0";
4681 (if_then_else (eq_attr "isa" "sparclet")
4682 (const_string "imul") (const_string "multi")))
4683 (set (attr "length")
4684 (if_then_else (eq_attr "isa" "sparclet")
4685 (const_int 1) (const_int 2)))])
4687 (define_insn "*mulsidi3_sp64"
4688 [(set (match_operand:DI 0 "register_operand" "=r")
4689 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
4690 (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
4691 "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
4693 [(set_attr "type" "imul")])
4695 ;; Extra pattern, because sign_extend of a constant isn't valid.
4697 (define_insn "const_mulsidi3_sp32"
4698 [(set (match_operand:DI 0 "register_operand" "=r")
4699 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
4700 (match_operand:DI 2 "small_int_operand" "I")))]
4703 return TARGET_SPARCLET
4704 ? "smuld\t%1, %2, %L0"
4705 : "smul\t%1, %2, %L0\n\trd\t%%y, %H0";
4708 (if_then_else (eq_attr "isa" "sparclet")
4709 (const_string "imul") (const_string "multi")))
4710 (set (attr "length")
4711 (if_then_else (eq_attr "isa" "sparclet")
4712 (const_int 1) (const_int 2)))])
4714 (define_insn "const_mulsidi3_sp64"
4715 [(set (match_operand:DI 0 "register_operand" "=r")
4716 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
4717 (match_operand:DI 2 "small_int_operand" "I")))]
4718 "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
4720 [(set_attr "type" "imul")])
4722 (define_expand "smulsi3_highpart"
4723 [(set (match_operand:SI 0 "register_operand" "")
4726 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
4727 (sign_extend:DI (match_operand:SI 2 "arith_operand" "")))
4729 "TARGET_HARD_MUL && TARGET_ARCH32"
4731 if (CONSTANT_P (operands[2]))
4735 emit_insn (gen_const_smulsi3_highpart_v8plus (operands[0],
4741 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[1], operands[2]));
4746 emit_insn (gen_smulsi3_highpart_v8plus (operands[0], operands[1],
4747 operands[2], GEN_INT (32)));
4752 (define_insn "smulsi3_highpart_v8plus"
4753 [(set (match_operand:SI 0 "register_operand" "=h,r")
4756 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
4757 (sign_extend:DI (match_operand:SI 2 "register_operand" "r,r")))
4758 (match_operand:SI 3 "small_int_operand" "I,I"))))
4759 (clobber (match_scratch:SI 4 "=X,&h"))]
4762 smul\t%1, %2, %0\;srlx\t%0, %3, %0
4763 smul\t%1, %2, %4\;srlx\t%4, %3, %0"
4764 [(set_attr "type" "multi")
4765 (set_attr "length" "2")])
4767 ;; The combiner changes TRUNCATE in the previous pattern to SUBREG.
4769 [(set (match_operand:SI 0 "register_operand" "=h,r")
4772 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
4773 (sign_extend:DI (match_operand:SI 2 "register_operand" "r,r")))
4774 (match_operand:SI 3 "small_int_operand" "I,I")) 4))
4775 (clobber (match_scratch:SI 4 "=X,&h"))]
4778 smul\t%1, %2, %0\n\tsrlx\t%0, %3, %0
4779 smul\t%1, %2, %4\n\tsrlx\t%4, %3, %0"
4780 [(set_attr "type" "multi")
4781 (set_attr "length" "2")])
4783 (define_insn "const_smulsi3_highpart_v8plus"
4784 [(set (match_operand:SI 0 "register_operand" "=h,r")
4787 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
4788 (match_operand:DI 2 "small_int_operand" "I,I"))
4789 (match_operand:SI 3 "small_int_operand" "I,I"))))
4790 (clobber (match_scratch:SI 4 "=X,&h"))]
4793 smul\t%1, %2, %0\n\tsrlx\t%0, %3, %0
4794 smul\t%1, %2, %4\n\tsrlx\t%4, %3, %0"
4795 [(set_attr "type" "multi")
4796 (set_attr "length" "2")])
4798 (define_insn "*smulsi3_highpart_sp32"
4799 [(set (match_operand:SI 0 "register_operand" "=r")
4802 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
4803 (sign_extend:DI (match_operand:SI 2 "register_operand" "r")))
4806 "smul\t%1, %2, %%g0\n\trd\t%%y, %0"
4807 [(set_attr "type" "multi")
4808 (set_attr "length" "2")])
4810 (define_insn "const_smulsi3_highpart"
4811 [(set (match_operand:SI 0 "register_operand" "=r")
4814 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
4815 (match_operand:DI 2 "small_int_operand" "i"))
4818 "smul\t%1, %2, %%g0\n\trd\t%%y, %0"
4819 [(set_attr "type" "multi")
4820 (set_attr "length" "2")])
4822 (define_expand "umulsidi3"
4823 [(set (match_operand:DI 0 "register_operand" "")
4824 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
4825 (zero_extend:DI (match_operand:SI 2 "uns_arith_operand" ""))))]
4828 if (CONSTANT_P (operands[2]))
4831 emit_insn (gen_const_umulsidi3_v8plus (operands[0], operands[1],
4833 else if (TARGET_ARCH32)
4834 emit_insn (gen_const_umulsidi3_sp32 (operands[0], operands[1],
4837 emit_insn (gen_const_umulsidi3_sp64 (operands[0], operands[1],
4843 emit_insn (gen_umulsidi3_v8plus (operands[0], operands[1], operands[2]));
4848 (define_insn "umulsidi3_v8plus"
4849 [(set (match_operand:DI 0 "register_operand" "=h,r")
4850 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
4851 (zero_extend:DI (match_operand:SI 2 "register_operand" "r,r"))))
4852 (clobber (match_scratch:SI 3 "=X,&h"))]
4855 umul\t%1, %2, %L0\n\tsrlx\t%L0, 32, %H0
4856 umul\t%1, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"
4857 [(set_attr "type" "multi")
4858 (set_attr "length" "2,3")])
4860 (define_insn "*umulsidi3_sp32"
4861 [(set (match_operand:DI 0 "register_operand" "=r")
4862 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
4863 (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
4866 return TARGET_SPARCLET
4867 ? "umuld\t%1, %2, %L0"
4868 : "umul\t%1, %2, %L0\n\trd\t%%y, %H0";
4871 (if_then_else (eq_attr "isa" "sparclet")
4872 (const_string "imul") (const_string "multi")))
4873 (set (attr "length")
4874 (if_then_else (eq_attr "isa" "sparclet")
4875 (const_int 1) (const_int 2)))])
4877 (define_insn "*umulsidi3_sp64"
4878 [(set (match_operand:DI 0 "register_operand" "=r")
4879 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
4880 (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
4881 "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
4883 [(set_attr "type" "imul")])
4885 ;; Extra pattern, because sign_extend of a constant isn't valid.
4887 (define_insn "const_umulsidi3_sp32"
4888 [(set (match_operand:DI 0 "register_operand" "=r")
4889 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
4890 (match_operand:DI 2 "uns_small_int_operand" "")))]
4893 return TARGET_SPARCLET
4894 ? "umuld\t%1, %s2, %L0"
4895 : "umul\t%1, %s2, %L0\n\trd\t%%y, %H0";
4898 (if_then_else (eq_attr "isa" "sparclet")
4899 (const_string "imul") (const_string "multi")))
4900 (set (attr "length")
4901 (if_then_else (eq_attr "isa" "sparclet")
4902 (const_int 1) (const_int 2)))])
4904 (define_insn "const_umulsidi3_sp64"
4905 [(set (match_operand:DI 0 "register_operand" "=r")
4906 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
4907 (match_operand:DI 2 "uns_small_int_operand" "")))]
4908 "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
4910 [(set_attr "type" "imul")])
4912 (define_insn "const_umulsidi3_v8plus"
4913 [(set (match_operand:DI 0 "register_operand" "=h,r")
4914 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
4915 (match_operand:DI 2 "uns_small_int_operand" "")))
4916 (clobber (match_scratch:SI 3 "=X,h"))]
4919 umul\t%1, %s2, %L0\n\tsrlx\t%L0, 32, %H0
4920 umul\t%1, %s2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"
4921 [(set_attr "type" "multi")
4922 (set_attr "length" "2,3")])
4924 (define_expand "umulsi3_highpart"
4925 [(set (match_operand:SI 0 "register_operand" "")
4928 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
4929 (zero_extend:DI (match_operand:SI 2 "uns_arith_operand" "")))
4931 "TARGET_HARD_MUL && TARGET_ARCH32"
4933 if (CONSTANT_P (operands[2]))
4937 emit_insn (gen_const_umulsi3_highpart_v8plus (operands[0],
4943 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[1], operands[2]));
4948 emit_insn (gen_umulsi3_highpart_v8plus (operands[0], operands[1],
4949 operands[2], GEN_INT (32)));
4954 (define_insn "umulsi3_highpart_v8plus"
4955 [(set (match_operand:SI 0 "register_operand" "=h,r")
4958 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
4959 (zero_extend:DI (match_operand:SI 2 "register_operand" "r,r")))
4960 (match_operand:SI 3 "small_int_operand" "I,I"))))
4961 (clobber (match_scratch:SI 4 "=X,h"))]
4964 umul\t%1, %2, %0\n\tsrlx\t%0, %3, %0
4965 umul\t%1, %2, %4\n\tsrlx\t%4, %3, %0"
4966 [(set_attr "type" "multi")
4967 (set_attr "length" "2")])
4969 (define_insn "const_umulsi3_highpart_v8plus"
4970 [(set (match_operand:SI 0 "register_operand" "=h,r")
4973 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
4974 (match_operand:DI 2 "uns_small_int_operand" ""))
4975 (match_operand:SI 3 "small_int_operand" "I,I"))))
4976 (clobber (match_scratch:SI 4 "=X,h"))]
4979 umul\t%1, %s2, %0\n\tsrlx\t%0, %3, %0
4980 umul\t%1, %s2, %4\n\tsrlx\t%4, %3, %0"
4981 [(set_attr "type" "multi")
4982 (set_attr "length" "2")])
4984 (define_insn "*umulsi3_highpart_sp32"
4985 [(set (match_operand:SI 0 "register_operand" "=r")
4988 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
4989 (zero_extend:DI (match_operand:SI 2 "register_operand" "r")))
4992 "umul\t%1, %2, %%g0\n\trd\t%%y, %0"
4993 [(set_attr "type" "multi")
4994 (set_attr "length" "2")])
4996 (define_insn "const_umulsi3_highpart"
4997 [(set (match_operand:SI 0 "register_operand" "=r")
5000 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
5001 (match_operand:DI 2 "uns_small_int_operand" ""))
5004 "umul\t%1, %s2, %%g0\n\trd\t%%y, %0"
5005 [(set_attr "type" "multi")
5006 (set_attr "length" "2")])
5009 (define_expand "umulxhi_vis"
5010 [(set (match_operand:DI 0 "register_operand" "")
5013 (mult:TI (zero_extend:TI (match_operand:DI 1 "arith_operand" ""))
5014 (zero_extend:TI (match_operand:DI 2 "arith_operand" "")))
5020 emit_insn (gen_umulxhi_v8plus (operands[0], operands[1], operands[2]));
5025 (define_insn "*umulxhi_sp64"
5026 [(set (match_operand:DI 0 "register_operand" "=r")
5029 (mult:TI (zero_extend:TI (match_operand:DI 1 "arith_operand" "%r"))
5030 (zero_extend:TI (match_operand:DI 2 "arith_operand" "rI")))
5032 "TARGET_VIS3 && TARGET_ARCH64"
5033 "umulxhi\t%1, %2, %0"
5034 [(set_attr "type" "imul")])
5036 (define_insn "umulxhi_v8plus"
5037 [(set (match_operand:DI 0 "register_operand" "=r,h")
5040 (mult:TI (zero_extend:TI (match_operand:DI 1 "arith_operand" "%r,0"))
5041 (zero_extend:TI (match_operand:DI 2 "arith_operand" "rI,rI")))
5043 (clobber (match_scratch:SI 3 "=&h,X"))
5044 (clobber (match_scratch:SI 4 "=&h,X"))]
5045 "TARGET_VIS3 && TARGET_ARCH32"
5047 return output_v8plus_mult (insn, operands, \"umulxhi\");
5049 [(set_attr "type" "imul")
5050 (set_attr "length" "9,8")])
5052 (define_expand "xmulx_vis"
5053 [(set (match_operand:DI 0 "register_operand" "")
5055 (unspec:TI [(zero_extend:TI (match_operand:DI 1 "arith_operand" ""))
5056 (zero_extend:TI (match_operand:DI 2 "arith_operand" ""))]
5062 emit_insn (gen_xmulx_v8plus (operands[0], operands[1], operands[2]));
5067 (define_insn "*xmulx_sp64"
5068 [(set (match_operand:DI 0 "register_operand" "=r")
5070 (unspec:TI [(zero_extend:TI (match_operand:DI 1 "arith_operand" "%r"))
5071 (zero_extend:TI (match_operand:DI 2 "arith_operand" "rI"))]
5073 "TARGET_VIS3 && TARGET_ARCH64"
5075 [(set_attr "type" "imul")])
5077 (define_insn "xmulx_v8plus"
5078 [(set (match_operand:DI 0 "register_operand" "=r,h")
5080 (unspec:TI [(zero_extend:TI (match_operand:DI 1 "arith_operand" "%r,0"))
5081 (zero_extend:TI (match_operand:DI 2 "arith_operand" "rI,rI"))]
5083 (clobber (match_scratch:SI 3 "=&h,X"))
5084 (clobber (match_scratch:SI 4 "=&h,X"))]
5085 "TARGET_VIS3 && TARGET_ARCH32"
5087 return output_v8plus_mult (insn, operands, \"xmulx\");
5089 [(set_attr "type" "imul")
5090 (set_attr "length" "9,8")])
5092 (define_expand "xmulxhi_vis"
5093 [(set (match_operand:DI 0 "register_operand" "")
5096 (unspec:TI [(zero_extend:TI (match_operand:DI 1 "arith_operand" ""))
5097 (zero_extend:TI (match_operand:DI 2 "arith_operand" ""))]
5104 emit_insn (gen_xmulxhi_v8plus (operands[0], operands[1], operands[2]));
5109 (define_insn "*xmulxhi_sp64"
5110 [(set (match_operand:DI 0 "register_operand" "=r")
5113 (unspec:TI [(zero_extend:TI (match_operand:DI 1 "arith_operand" "%r"))
5114 (zero_extend:TI (match_operand:DI 2 "arith_operand" "rI"))]
5117 "TARGET_VIS3 && TARGET_ARCH64"
5118 "xmulxhi\t%1, %2, %0"
5119 [(set_attr "type" "imul")])
5121 (define_insn "xmulxhi_v8plus"
5122 [(set (match_operand:DI 0 "register_operand" "=r,h")
5125 (unspec:TI [(zero_extend:TI (match_operand:DI 1 "arith_operand" "%r,0"))
5126 (zero_extend:TI (match_operand:DI 2 "arith_operand" "rI,rI"))]
5129 (clobber (match_scratch:SI 3 "=&h,X"))
5130 (clobber (match_scratch:SI 4 "=&h,X"))]
5131 "TARGET_VIS3 && TARGET_ARCH32"
5133 return output_v8plus_mult (insn, operands, \"xmulxhi\");
5135 [(set_attr "type" "imul")
5136 (set_attr "length" "9,8")])
5138 (define_expand "divsi3"
5139 [(parallel [(set (match_operand:SI 0 "register_operand" "")
5140 (div:SI (match_operand:SI 1 "register_operand" "")
5141 (match_operand:SI 2 "input_operand" "")))
5142 (clobber (match_scratch:SI 3 ""))])]
5143 "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS"
5147 operands[3] = gen_reg_rtx(SImode);
5148 emit_insn (gen_ashrsi3 (operands[3], operands[1], GEN_INT (31)));
5149 emit_insn (gen_divsi3_sp64 (operands[0], operands[1], operands[2],
5155 ;; The V8 architecture specifies that there must be at least 3 instructions
5156 ;; between a write to the Y register and a use of it for correct results.
5157 ;; We try to fill one of them with a simple constant or a memory load.
5159 (define_insn "divsi3_sp32"
5160 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
5161 (div:SI (match_operand:SI 1 "register_operand" "r,r,r")
5162 (match_operand:SI 2 "input_operand" "rI,K,m")))
5163 (clobber (match_scratch:SI 3 "=&r,&r,&r"))]
5164 "(TARGET_V8 || TARGET_DEPRECATED_V8_INSNS) && TARGET_ARCH32"
5166 output_asm_insn ("sra\t%1, 31, %3", operands);
5167 output_asm_insn ("wr\t%3, 0, %%y", operands);
5169 switch (which_alternative)
5173 return "sdiv\t%1, %2, %0";
5175 return "nop\n\tnop\n\tnop\n\tsdiv\t%1, %2, %0";
5178 return "sethi\t%%hi(%a2), %3\n\tsdiv\t%1, %3, %0";
5180 return "sethi\t%%hi(%a2), %3\n\tnop\n\tnop\n\tsdiv\t%1, %3, %0";
5183 return "ld\t%2, %3\n\tsdiv\t%1, %3, %0";
5185 return "ld\t%2, %3\n\tnop\n\tnop\n\tsdiv\t%1, %3, %0";
5190 [(set_attr "type" "multi")
5191 (set (attr "length")
5192 (if_then_else (eq_attr "isa" "v9")
5193 (const_int 4) (const_int 6)))])
5195 (define_insn "divsi3_sp64"
5196 [(set (match_operand:SI 0 "register_operand" "=r")
5197 (div:SI (match_operand:SI 1 "register_operand" "r")
5198 (match_operand:SI 2 "input_operand" "rI")))
5199 (use (match_operand:SI 3 "register_operand" "r"))]
5200 "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
5201 "wr\t%%g0, %3, %%y\n\tsdiv\t%1, %2, %0"
5202 [(set_attr "type" "multi")
5203 (set_attr "length" "2")])
5205 (define_insn "divdi3"
5206 [(set (match_operand:DI 0 "register_operand" "=r")
5207 (div:DI (match_operand:DI 1 "register_operand" "r")
5208 (match_operand:DI 2 "arith_operand" "rI")))]
5211 [(set_attr "type" "idiv")])
5213 (define_insn "*cmp_sdiv_cc_set"
5214 [(set (reg:CC CC_REG)
5215 (compare:CC (div:SI (match_operand:SI 1 "register_operand" "r")
5216 (match_operand:SI 2 "arith_operand" "rI"))
5218 (set (match_operand:SI 0 "register_operand" "=r")
5219 (div:SI (match_dup 1) (match_dup 2)))
5220 (clobber (match_scratch:SI 3 "=&r"))]
5221 "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS"
5223 output_asm_insn ("sra\t%1, 31, %3", operands);
5224 output_asm_insn ("wr\t%3, 0, %%y", operands);
5227 return "sdivcc\t%1, %2, %0";
5229 return "nop\n\tnop\n\tnop\n\tsdivcc\t%1, %2, %0";
5231 [(set_attr "type" "multi")
5232 (set (attr "length")
5233 (if_then_else (eq_attr "isa" "v9")
5234 (const_int 3) (const_int 6)))])
5236 (define_expand "udivsi3"
5237 [(set (match_operand:SI 0 "register_operand" "")
5238 (udiv:SI (match_operand:SI 1 "nonimmediate_operand" "")
5239 (match_operand:SI 2 "input_operand" "")))]
5240 "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS"
5243 ;; The V8 architecture specifies that there must be at least 3 instructions
5244 ;; between a write to the Y register and a use of it for correct results.
5245 ;; We try to fill one of them with a simple constant or a memory load.
5247 (define_insn "udivsi3_sp32"
5248 [(set (match_operand:SI 0 "register_operand" "=r,&r,&r,&r")
5249 (udiv:SI (match_operand:SI 1 "nonimmediate_operand" "r,r,r,m")
5250 (match_operand:SI 2 "input_operand" "rI,K,m,r")))]
5251 "(TARGET_V8 || TARGET_DEPRECATED_V8_INSNS) && TARGET_ARCH32"
5253 output_asm_insn ("wr\t%%g0, 0, %%y", operands);
5255 switch (which_alternative)
5259 return "udiv\t%1, %2, %0";
5261 return "nop\n\tnop\n\tnop\n\tudiv\t%1, %2, %0";
5264 return "sethi\t%%hi(%a2), %0\n\tudiv\t%1, %0, %0";
5266 return "sethi\t%%hi(%a2), %0\n\tnop\n\tnop\n\tudiv\t%1, %0, %0";
5269 return "ld\t%2, %0\n\tudiv\t%1, %0, %0";
5271 return "ld\t%2, %0\n\tnop\n\tnop\n\tudiv\t%1, %0, %0";
5274 return "ld\t%1, %0\n\tudiv\t%0, %2, %0";
5276 return "ld\t%1, %0\n\tnop\n\tnop\n\tudiv\t%0, %2, %0";
5281 [(set_attr "type" "multi")
5282 (set (attr "length")
5283 (if_then_else (eq_attr "isa" "v9")
5284 (const_int 3) (const_int 5)))])
5286 (define_insn "udivsi3_sp64"
5287 [(set (match_operand:SI 0 "register_operand" "=r")
5288 (udiv:SI (match_operand:SI 1 "nonimmediate_operand" "r")
5289 (match_operand:SI 2 "input_operand" "rI")))]
5290 "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
5291 "wr\t%%g0, 0, %%y\n\tudiv\t%1, %2, %0"
5292 [(set_attr "type" "multi")
5293 (set_attr "length" "2")])
5295 (define_insn "udivdi3"
5296 [(set (match_operand:DI 0 "register_operand" "=r")
5297 (udiv:DI (match_operand:DI 1 "register_operand" "r")
5298 (match_operand:DI 2 "arith_operand" "rI")))]
5301 [(set_attr "type" "idiv")])
5303 (define_insn "*cmp_udiv_cc_set"
5304 [(set (reg:CC CC_REG)
5305 (compare:CC (udiv:SI (match_operand:SI 1 "register_operand" "r")
5306 (match_operand:SI 2 "arith_operand" "rI"))
5308 (set (match_operand:SI 0 "register_operand" "=r")
5309 (udiv:SI (match_dup 1) (match_dup 2)))]
5310 "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS"
5312 output_asm_insn ("wr\t%%g0, 0, %%y", operands);
5315 return "udivcc\t%1, %2, %0";
5317 return "nop\n\tnop\n\tnop\n\tudivcc\t%1, %2, %0";
5319 [(set_attr "type" "multi")
5320 (set (attr "length")
5321 (if_then_else (eq_attr "isa" "v9")
5322 (const_int 2) (const_int 5)))])
5325 ;; SPARClet multiply/accumulate insns
5327 (define_insn "*smacsi"
5328 [(set (match_operand:SI 0 "register_operand" "=r")
5329 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "%r")
5330 (match_operand:SI 2 "arith_operand" "rI"))
5331 (match_operand:SI 3 "register_operand" "0")))]
5334 [(set_attr "type" "imul")])
5336 (define_insn "*smacdi"
5337 [(set (match_operand:DI 0 "register_operand" "=r")
5338 (plus:DI (mult:DI (sign_extend:DI
5339 (match_operand:SI 1 "register_operand" "%r"))
5341 (match_operand:SI 2 "register_operand" "r")))
5342 (match_operand:DI 3 "register_operand" "0")))]
5344 "smacd\t%1, %2, %L0"
5345 [(set_attr "type" "imul")])
5347 (define_insn "*umacdi"
5348 [(set (match_operand:DI 0 "register_operand" "=r")
5349 (plus:DI (mult:DI (zero_extend:DI
5350 (match_operand:SI 1 "register_operand" "%r"))
5352 (match_operand:SI 2 "register_operand" "r")))
5353 (match_operand:DI 3 "register_operand" "0")))]
5355 "umacd\t%1, %2, %L0"
5356 [(set_attr "type" "imul")])
5359 ;; Boolean instructions.
5361 (define_insn "anddi3"
5362 [(set (match_operand:DI 0 "register_operand" "=r")
5363 (and:DI (match_operand:DI 1 "arith_operand" "%r")
5364 (match_operand:DI 2 "arith_operand" "rI")))]
5368 (define_insn "andsi3"
5369 [(set (match_operand:SI 0 "register_operand" "=r")
5370 (and:SI (match_operand:SI 1 "arith_operand" "%r")
5371 (match_operand:SI 2 "arith_operand" "rI")))]
5376 [(set (match_operand:SI 0 "register_operand" "")
5377 (and:SI (match_operand:SI 1 "register_operand" "")
5378 (match_operand:SI 2 "const_compl_high_operand" "")))
5379 (clobber (match_operand:SI 3 "register_operand" ""))]
5381 [(set (match_dup 3) (match_dup 4))
5382 (set (match_dup 0) (and:SI (not:SI (match_dup 3)) (match_dup 1)))]
5384 operands[4] = GEN_INT (~INTVAL (operands[2]));
5387 (define_insn "*and_not_di_sp64"
5388 [(set (match_operand:DI 0 "register_operand" "=r")
5389 (and:DI (not:DI (match_operand:DI 1 "register_operand" "%r"))
5390 (match_operand:DI 2 "register_operand" "r")))]
5394 (define_insn "*and_not_si"
5395 [(set (match_operand:SI 0 "register_operand" "=r")
5396 (and:SI (not:SI (match_operand:SI 1 "register_operand" "%r"))
5397 (match_operand:SI 2 "register_operand" "r")))]
5401 (define_insn "iordi3"
5402 [(set (match_operand:DI 0 "register_operand" "=r")
5403 (ior:DI (match_operand:DI 1 "arith_operand" "%r")
5404 (match_operand:DI 2 "arith_operand" "rI")))]
5408 (define_insn "iorsi3"
5409 [(set (match_operand:SI 0 "register_operand" "=r")
5410 (ior:SI (match_operand:SI 1 "arith_operand" "%r")
5411 (match_operand:SI 2 "arith_operand" "rI")))]
5416 [(set (match_operand:SI 0 "register_operand" "")
5417 (ior:SI (match_operand:SI 1 "register_operand" "")
5418 (match_operand:SI 2 "const_compl_high_operand" "")))
5419 (clobber (match_operand:SI 3 "register_operand" ""))]
5421 [(set (match_dup 3) (match_dup 4))
5422 (set (match_dup 0) (ior:SI (not:SI (match_dup 3)) (match_dup 1)))]
5424 operands[4] = gen_int_mode (~INTVAL (operands[2]), SImode);
5427 (define_insn "*or_not_di_sp64"
5428 [(set (match_operand:DI 0 "register_operand" "=r")
5429 (ior:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5430 (match_operand:DI 2 "register_operand" "r")))]
5434 (define_insn "*or_not_si"
5435 [(set (match_operand:SI 0 "register_operand" "=r")
5436 (ior:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
5437 (match_operand:SI 2 "register_operand" "r")))]
5441 (define_insn "xordi3"
5442 [(set (match_operand:DI 0 "register_operand" "=r")
5443 (xor:DI (match_operand:DI 1 "arith_operand" "%rJ")
5444 (match_operand:DI 2 "arith_operand" "rI")))]
5448 (define_insn "xorsi3"
5449 [(set (match_operand:SI 0 "register_operand" "=r")
5450 (xor:SI (match_operand:SI 1 "arith_operand" "%rJ")
5451 (match_operand:SI 2 "arith_operand" "rI")))]
5456 [(set (match_operand:SI 0 "register_operand" "")
5457 (xor:SI (match_operand:SI 1 "register_operand" "")
5458 (match_operand:SI 2 "const_compl_high_operand" "")))
5459 (clobber (match_operand:SI 3 "register_operand" ""))]
5461 [(set (match_dup 3) (match_dup 4))
5462 (set (match_dup 0) (not:SI (xor:SI (match_dup 3) (match_dup 1))))]
5464 operands[4] = gen_int_mode (~INTVAL (operands[2]), SImode);
5468 [(set (match_operand:SI 0 "register_operand" "")
5469 (not:SI (xor:SI (match_operand:SI 1 "register_operand" "")
5470 (match_operand:SI 2 "const_compl_high_operand" ""))))
5471 (clobber (match_operand:SI 3 "register_operand" ""))]
5473 [(set (match_dup 3) (match_dup 4))
5474 (set (match_dup 0) (xor:SI (match_dup 3) (match_dup 1)))]
5476 operands[4] = gen_int_mode (~INTVAL (operands[2]), SImode);
5479 (define_insn "*xor_not_di_sp64"
5480 [(set (match_operand:DI 0 "register_operand" "=r")
5481 (not:DI (xor:DI (match_operand:DI 1 "register_or_zero_operand" "rJ")
5482 (match_operand:DI 2 "arith_operand" "rI"))))]
5484 "xnor\t%r1, %2, %0")
5486 (define_insn "*xor_not_si"
5487 [(set (match_operand:SI 0 "register_operand" "=r")
5488 (not:SI (xor:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
5489 (match_operand:SI 2 "arith_operand" "rI"))))]
5491 "xnor\t%r1, %2, %0")
5493 ;; These correspond to the above in the case where we also (or only)
5494 ;; want to set the condition code.
5496 (define_insn "*cmp_cc_arith_op"
5497 [(set (reg:CC CC_REG)
5498 (compare:CC (match_operator:SI 2 "cc_arith_operator"
5499 [(match_operand:SI 0 "arith_operand" "%r")
5500 (match_operand:SI 1 "arith_operand" "rI")])
5503 "%A2cc\t%0, %1, %%g0"
5504 [(set_attr "type" "compare")])
5506 (define_insn "*cmp_ccx_arith_op"
5507 [(set (reg:CCX CC_REG)
5508 (compare:CCX (match_operator:DI 2 "cc_arith_operator"
5509 [(match_operand:DI 0 "arith_operand" "%r")
5510 (match_operand:DI 1 "arith_operand" "rI")])
5513 "%A2cc\t%0, %1, %%g0"
5514 [(set_attr "type" "compare")])
5516 (define_insn "*cmp_cc_arith_op_set"
5517 [(set (reg:CC CC_REG)
5518 (compare:CC (match_operator:SI 3 "cc_arith_operator"
5519 [(match_operand:SI 1 "arith_operand" "%r")
5520 (match_operand:SI 2 "arith_operand" "rI")])
5522 (set (match_operand:SI 0 "register_operand" "=r")
5523 (match_operator:SI 4 "cc_arith_operator"
5524 [(match_dup 1) (match_dup 2)]))]
5525 "GET_CODE (operands[3]) == GET_CODE (operands[4])"
5527 [(set_attr "type" "compare")])
5529 (define_insn "*cmp_ccx_arith_op_set"
5530 [(set (reg:CCX CC_REG)
5531 (compare:CCX (match_operator:DI 3 "cc_arith_operator"
5532 [(match_operand:DI 1 "arith_operand" "%r")
5533 (match_operand:DI 2 "arith_operand" "rI")])
5535 (set (match_operand:DI 0 "register_operand" "=r")
5536 (match_operator:DI 4 "cc_arith_operator"
5537 [(match_dup 1) (match_dup 2)]))]
5538 "TARGET_ARCH64 && GET_CODE (operands[3]) == GET_CODE (operands[4])"
5540 [(set_attr "type" "compare")])
5542 (define_insn "*cmp_cc_xor_not"
5543 [(set (reg:CC CC_REG)
5545 (not:SI (xor:SI (match_operand:SI 0 "register_or_zero_operand" "%rJ")
5546 (match_operand:SI 1 "arith_operand" "rI")))
5549 "xnorcc\t%r0, %1, %%g0"
5550 [(set_attr "type" "compare")])
5552 (define_insn "*cmp_ccx_xor_not"
5553 [(set (reg:CCX CC_REG)
5555 (not:DI (xor:DI (match_operand:DI 0 "register_or_zero_operand" "%rJ")
5556 (match_operand:DI 1 "arith_operand" "rI")))
5559 "xnorcc\t%r0, %1, %%g0"
5560 [(set_attr "type" "compare")])
5562 (define_insn "*cmp_cc_xor_not_set"
5563 [(set (reg:CC CC_REG)
5565 (not:SI (xor:SI (match_operand:SI 1 "register_or_zero_operand" "%rJ")
5566 (match_operand:SI 2 "arith_operand" "rI")))
5568 (set (match_operand:SI 0 "register_operand" "=r")
5569 (not:SI (xor:SI (match_dup 1) (match_dup 2))))]
5571 "xnorcc\t%r1, %2, %0"
5572 [(set_attr "type" "compare")])
5574 (define_insn "*cmp_ccx_xor_not_set"
5575 [(set (reg:CCX CC_REG)
5577 (not:DI (xor:DI (match_operand:DI 1 "register_or_zero_operand" "%rJ")
5578 (match_operand:DI 2 "arith_operand" "rI")))
5580 (set (match_operand:DI 0 "register_operand" "=r")
5581 (not:DI (xor:DI (match_dup 1) (match_dup 2))))]
5583 "xnorcc\t%r1, %2, %0"
5584 [(set_attr "type" "compare")])
5586 (define_insn "*cmp_cc_arith_op_not"
5587 [(set (reg:CC CC_REG)
5588 (compare:CC (match_operator:SI 2 "cc_arith_not_operator"
5589 [(not:SI (match_operand:SI 0 "arith_operand" "rI"))
5590 (match_operand:SI 1 "register_or_zero_operand" "rJ")])
5593 "%B2cc\t%r1, %0, %%g0"
5594 [(set_attr "type" "compare")])
5596 (define_insn "*cmp_ccx_arith_op_not"
5597 [(set (reg:CCX CC_REG)
5598 (compare:CCX (match_operator:DI 2 "cc_arith_not_operator"
5599 [(not:DI (match_operand:DI 0 "arith_operand" "rI"))
5600 (match_operand:DI 1 "register_or_zero_operand" "rJ")])
5603 "%B2cc\t%r1, %0, %%g0"
5604 [(set_attr "type" "compare")])
5606 (define_insn "*cmp_cc_arith_op_not_set"
5607 [(set (reg:CC CC_REG)
5608 (compare:CC (match_operator:SI 3 "cc_arith_not_operator"
5609 [(not:SI (match_operand:SI 1 "arith_operand" "rI"))
5610 (match_operand:SI 2 "register_or_zero_operand" "rJ")])
5612 (set (match_operand:SI 0 "register_operand" "=r")
5613 (match_operator:SI 4 "cc_arith_not_operator"
5614 [(not:SI (match_dup 1)) (match_dup 2)]))]
5615 "GET_CODE (operands[3]) == GET_CODE (operands[4])"
5616 "%B3cc\t%r2, %1, %0"
5617 [(set_attr "type" "compare")])
5619 (define_insn "*cmp_ccx_arith_op_not_set"
5620 [(set (reg:CCX CC_REG)
5621 (compare:CCX (match_operator:DI 3 "cc_arith_not_operator"
5622 [(not:DI (match_operand:DI 1 "arith_operand" "rI"))
5623 (match_operand:DI 2 "register_or_zero_operand" "rJ")])
5625 (set (match_operand:DI 0 "register_operand" "=r")
5626 (match_operator:DI 4 "cc_arith_not_operator"
5627 [(not:DI (match_dup 1)) (match_dup 2)]))]
5628 "TARGET_ARCH64 && GET_CODE (operands[3]) == GET_CODE (operands[4])"
5629 "%B3cc\t%r2, %1, %0"
5630 [(set_attr "type" "compare")])
5632 ;; We cannot use the "neg" pseudo insn because the Sun assembler
5633 ;; does not know how to make it work for constants.
5635 (define_expand "negdi2"
5636 [(set (match_operand:DI 0 "register_operand" "=r")
5637 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5642 emit_insn (gen_negdi2_sp32 (operands[0], operands[1]));
5647 (define_expand "unegvdi3"
5648 [(parallel [(set (reg:CCXC CC_REG)
5649 (compare:CCXC (not:DI (match_operand:DI 1 "register_operand" ""))
5651 (set (match_operand:DI 0 "register_operand" "")
5652 (neg:DI (match_dup 1)))])
5654 (if_then_else (ltu (reg:CCXC CC_REG) (const_int 0))
5655 (label_ref (match_operand 2 ""))
5661 emit_insn (gen_unegvdi3_sp32 (operands[0], operands[1]));
5662 rtx x = gen_rtx_LTU (VOIDmode, gen_rtx_REG (CCCmode, SPARC_ICC_REG),
5664 emit_jump_insn (gen_cbranchcc4 (x, XEXP (x, 0), XEXP (x, 1), operands[2]));
5669 (define_expand "negvdi3"
5670 [(parallel [(set (reg:CCXV CC_REG)
5671 (compare:CCXV (neg:DI (match_operand:DI 1 "register_operand" ""))
5672 (unspec:DI [(match_dup 1)] UNSPEC_NEGV)))
5673 (set (match_operand:DI 0 "register_operand" "")
5674 (neg:DI (match_dup 1)))])
5676 (if_then_else (ne (reg:CCXV CC_REG) (const_int 0))
5677 (label_ref (match_operand 2 ""))
5683 emit_insn (gen_negvdi3_sp32 (operands[0], operands[1]));
5684 rtx x = gen_rtx_NE (VOIDmode, gen_rtx_REG (CCVmode, SPARC_ICC_REG),
5686 emit_jump_insn (gen_cbranchcc4 (x, XEXP (x, 0), XEXP (x, 1), operands[2]));
5691 (define_insn_and_split "negdi2_sp32"
5692 [(set (match_operand:DI 0 "register_operand" "=&r")
5693 (neg:DI (match_operand:DI 1 "register_operand" "r")))
5694 (clobber (reg:CC CC_REG))]
5697 "&& reload_completed"
5698 [(parallel [(set (reg:CCC CC_REG)
5699 (compare:CCC (not:SI (match_dup 5)) (const_int -1)))
5700 (set (match_dup 4) (neg:SI (match_dup 5)))])
5701 (set (match_dup 2) (minus:SI (minus:SI (const_int 0) (match_dup 3))
5702 (ltu:SI (reg:CCC CC_REG) (const_int 0))))]
5703 "operands[2] = gen_highpart (SImode, operands[0]);
5704 operands[3] = gen_highpart (SImode, operands[1]);
5705 operands[4] = gen_lowpart (SImode, operands[0]);
5706 operands[5] = gen_lowpart (SImode, operands[1]);"
5707 [(set_attr "length" "2")])
5709 (define_insn_and_split "unegvdi3_sp32"
5710 [(set (reg:CCC CC_REG)
5711 (compare:CCC (not:DI (match_operand:DI 1 "register_operand" "r"))
5713 (set (match_operand:DI 0 "register_operand" "=&r")
5714 (neg:DI (match_dup 1)))]
5717 "&& reload_completed"
5718 [(parallel [(set (reg:CCC CC_REG)
5719 (compare:CCC (not:SI (match_dup 5)) (const_int -1)))
5720 (set (match_dup 4) (neg:SI (match_dup 5)))])
5721 (parallel [(set (reg:CCC CC_REG)
5722 (compare:CCC (zero_extend:DI
5723 (neg:SI (plus:SI (match_dup 3)
5724 (ltu:SI (reg:CCC CC_REG)
5726 (neg:DI (plus:DI (zero_extend:DI (match_dup 3))
5727 (ltu:DI (reg:CCC CC_REG)
5729 (set (match_dup 2) (neg:SI (plus:SI (match_dup 3)
5730 (ltu:SI (reg:CCC CC_REG)
5731 (const_int 0)))))])]
5732 "operands[2] = gen_highpart (SImode, operands[0]);
5733 operands[3] = gen_highpart (SImode, operands[1]);
5734 operands[4] = gen_lowpart (SImode, operands[0]);
5735 operands[5] = gen_lowpart (SImode, operands[1]);"
5736 [(set_attr "length" "2")])
5738 (define_insn_and_split "negvdi3_sp32"
5739 [(set (reg:CCV CC_REG)
5740 (compare:CCV (neg:DI (match_operand:DI 1 "register_operand" "r"))
5741 (unspec:DI [(match_dup 1)] UNSPEC_NEGV)))
5742 (set (match_operand:DI 0 "register_operand" "=&r")
5743 (neg:DI (match_dup 1)))]
5746 "&& reload_completed"
5747 [(parallel [(set (reg:CCC CC_REG)
5748 (compare:CCC (not:SI (match_dup 5)) (const_int -1)))
5749 (set (match_dup 4) (neg:SI (match_dup 5)))])
5750 (parallel [(set (reg:CCV CC_REG)
5751 (compare:CCV (neg:SI (plus:SI (match_dup 3)
5752 (ltu:SI (reg:CCC CC_REG)
5754 (unspec:SI [(plus:SI (match_dup 3)
5755 (ltu:SI (reg:CCC CC_REG)
5758 (set (match_dup 2) (neg:SI (plus:SI (match_dup 3)
5759 (ltu:SI (reg:CCC CC_REG)
5760 (const_int 0)))))])]
5761 "operands[2] = gen_highpart (SImode, operands[0]);
5762 operands[3] = gen_highpart (SImode, operands[1]);
5763 operands[4] = gen_lowpart (SImode, operands[0]);
5764 operands[5] = gen_lowpart (SImode, operands[1]);"
5765 [(set_attr "length" "2")])
5767 (define_insn "*negdi2_sp64"
5768 [(set (match_operand:DI 0 "register_operand" "=r")
5769 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5771 "sub\t%%g0, %1, %0")
5773 (define_insn "negsi2"
5774 [(set (match_operand:SI 0 "register_operand" "=r")
5775 (neg:SI (match_operand:SI 1 "arith_operand" "rI")))]
5777 "sub\t%%g0, %1, %0")
5779 (define_expand "unegvsi3"
5780 [(parallel [(set (reg:CCC CC_REG)
5781 (compare:CCC (not:SI (match_operand:SI 1 "arith_operand" ""))
5783 (set (match_operand:SI 0 "register_operand" "")
5784 (neg:SI (match_dup 1)))])
5786 (if_then_else (ltu (reg:CCC CC_REG) (const_int 0))
5787 (label_ref (match_operand 2 ""))
5791 (define_expand "negvsi3"
5792 [(parallel [(set (reg:CCV CC_REG)
5793 (compare:CCV (neg:SI (match_operand:SI 1 "arith_operand" ""))
5794 (unspec:SI [(match_dup 1)] UNSPEC_NEGV)))
5795 (set (match_operand:SI 0 "register_operand" "")
5796 (neg:SI (match_dup 1)))])
5798 (if_then_else (ne (reg:CCV CC_REG) (const_int 0))
5799 (label_ref (match_operand 2 ""))
5803 (define_insn "*cmp_ccnz_neg"
5804 [(set (reg:CCNZ CC_REG)
5805 (compare:CCNZ (neg:SI (match_operand:SI 0 "arith_operand" "rI"))
5808 "subcc\t%%g0, %0, %%g0"
5809 [(set_attr "type" "compare")])
5811 (define_insn "*cmp_ccxnz_neg"
5812 [(set (reg:CCXNZ CC_REG)
5813 (compare:CCXNZ (neg:DI (match_operand:DI 0 "arith_operand" "rI"))
5816 "subcc\t%%g0, %0, %%g0"
5817 [(set_attr "type" "compare")])
5819 (define_insn "*cmp_ccnz_neg_set"
5820 [(set (reg:CCNZ CC_REG)
5821 (compare:CCNZ (neg:SI (match_operand:SI 1 "arith_operand" "rI"))
5823 (set (match_operand:SI 0 "register_operand" "=r")
5824 (neg:SI (match_dup 1)))]
5826 "subcc\t%%g0, %1, %0"
5827 [(set_attr "type" "compare")])
5829 (define_insn "*cmp_ccxnz_neg_set"
5830 [(set (reg:CCXNZ CC_REG)
5831 (compare:CCXNZ (neg:DI (match_operand:DI 1 "arith_operand" "rI"))
5833 (set (match_operand:DI 0 "register_operand" "=r")
5834 (neg:DI (match_dup 1)))]
5836 "subcc\t%%g0, %1, %0"
5837 [(set_attr "type" "compare")])
5839 (define_insn "*cmp_ccc_neg_set"
5840 [(set (reg:CCC CC_REG)
5841 (compare:CCC (not:SI (match_operand:SI 1 "arith_operand" "rI"))
5843 (set (match_operand:SI 0 "register_operand" "=r")
5844 (neg:SI (match_dup 1)))]
5846 "subcc\t%%g0, %1, %0"
5847 [(set_attr "type" "compare")])
5849 (define_insn "*cmp_ccxc_neg_set"
5850 [(set (reg:CCXC CC_REG)
5851 (compare:CCXC (not:DI (match_operand:DI 1 "arith_operand" "rI"))
5853 (set (match_operand:DI 0 "register_operand" "=r")
5854 (neg:DI (match_dup 1)))]
5856 "subcc\t%%g0, %1, %0"
5857 [(set_attr "type" "compare")])
5859 (define_insn "*cmp_ccc_neg_sltu_set"
5860 [(set (reg:CCC CC_REG)
5861 (compare:CCC (zero_extend:DI
5862 (neg:SI (plus:SI (match_operand:SI 1 "arith_operand" "rI")
5863 (ltu:SI (reg:CCC CC_REG)
5865 (neg:DI (plus:DI (zero_extend:DI (match_dup 1))
5866 (ltu:DI (reg:CCC CC_REG)
5868 (set (match_operand:SI 0 "register_operand" "=r")
5869 (neg:SI (plus:SI (match_dup 1)
5870 (ltu:SI (reg:CCC CC_REG) (const_int 0)))))]
5872 "subxcc\t%%g0, %1, %0"
5873 [(set_attr "type" "compare")])
5875 (define_insn "*cmp_ccv_neg"
5876 [(set (reg:CCV CC_REG)
5877 (compare:CCV (neg:SI (match_operand:SI 0 "arith_operand" "rI"))
5878 (unspec:SI [(match_dup 0)] UNSPEC_NEGV)))]
5880 "subcc\t%%g0, %0, %%g0"
5881 [(set_attr "type" "compare")])
5883 (define_insn "*cmp_ccxv_neg"
5884 [(set (reg:CCXV CC_REG)
5885 (compare:CCXV (neg:DI (match_operand:DI 0 "arith_operand" "rI"))
5886 (unspec:DI [(match_dup 0)] UNSPEC_NEGV)))]
5888 "subcc\t%%g0, %0, %%g0"
5889 [(set_attr "type" "compare")])
5891 (define_insn "*cmp_ccv_neg_set"
5892 [(set (reg:CCV CC_REG)
5893 (compare:CCV (neg:SI (match_operand:SI 1 "arith_operand" "rI"))
5894 (unspec:SI [(match_dup 1)] UNSPEC_NEGV)))
5895 (set (match_operand:SI 0 "register_operand" "=r")
5896 (neg:SI (match_dup 1)))]
5898 "subcc\t%%g0, %1, %0"
5899 [(set_attr "type" "compare")])
5901 (define_insn "*cmp_ccxv_neg_set"
5902 [(set (reg:CCXV CC_REG)
5903 (compare:CCXV (neg:DI (match_operand:DI 1 "arith_operand" "rI"))
5904 (unspec:DI [(match_dup 1)] UNSPEC_NEGV)))
5905 (set (match_operand:DI 0 "register_operand" "=r")
5906 (neg:DI (match_dup 1)))]
5908 "subcc\t%%g0, %1, %0"
5909 [(set_attr "type" "compare")])
5911 (define_insn "*cmp_ccv_neg_sltu_set"
5912 [(set (reg:CCV CC_REG)
5913 (compare:CCV (neg:SI (plus:SI (match_operand:SI 1 "arith_operand" "rI")
5914 (ltu:SI (reg:CCC CC_REG) (const_int 0))))
5915 (unspec:SI [(plus:SI (match_dup 1)
5916 (ltu:SI (reg:CCC CC_REG)
5919 (set (match_operand:SI 0 "register_operand" "=r")
5920 (neg:SI (plus:SI (match_dup 1)
5921 (ltu:SI (reg:CCC CC_REG) (const_int 0)))))]
5923 "subxcc\t%%g0, %1, %0"
5924 [(set_attr "type" "compare")])
5927 (define_insn "one_cmpldi2"
5928 [(set (match_operand:DI 0 "register_operand" "=r")
5929 (not:DI (match_operand:DI 1 "arith_operand" "rI")))]
5931 "xnor\t%%g0, %1, %0")
5933 (define_insn "one_cmplsi2"
5934 [(set (match_operand:SI 0 "register_operand" "=r")
5935 (not:SI (match_operand:SI 1 "arith_operand" "rI")))]
5937 "xnor\t%%g0, %1, %0")
5939 (define_insn "*cmp_cc_not"
5940 [(set (reg:CC CC_REG)
5941 (compare:CC (not:SI (match_operand:SI 0 "arith_operand" "rI"))
5944 "xnorcc\t%%g0, %0, %%g0"
5945 [(set_attr "type" "compare")])
5947 (define_insn "*cmp_ccx_not"
5948 [(set (reg:CCX CC_REG)
5949 (compare:CCX (not:DI (match_operand:DI 0 "arith_operand" "rI"))
5952 "xnorcc\t%%g0, %0, %%g0"
5953 [(set_attr "type" "compare")])
5955 (define_insn "*cmp_cc_set_not"
5956 [(set (reg:CC CC_REG)
5957 (compare:CC (not:SI (match_operand:SI 1 "arith_operand" "rI"))
5959 (set (match_operand:SI 0 "register_operand" "=r")
5960 (not:SI (match_dup 1)))]
5962 "xnorcc\t%%g0, %1, %0"
5963 [(set_attr "type" "compare")])
5965 (define_insn "*cmp_ccx_set_not"
5966 [(set (reg:CCX CC_REG)
5967 (compare:CCX (not:DI (match_operand:DI 1 "arith_operand" "rI"))
5969 (set (match_operand:DI 0 "register_operand" "=r")
5970 (not:DI (match_dup 1)))]
5972 "xnorcc\t%%g0, %1, %0"
5973 [(set_attr "type" "compare")])
5975 (define_insn "*cmp_cc_set"
5976 [(set (match_operand:SI 0 "register_operand" "=r")
5977 (match_operand:SI 1 "register_operand" "r"))
5978 (set (reg:CC CC_REG)
5979 (compare:CC (match_dup 1) (const_int 0)))]
5982 [(set_attr "type" "compare")])
5984 (define_insn "*cmp_ccx_set64"
5985 [(set (match_operand:DI 0 "register_operand" "=r")
5986 (match_operand:DI 1 "register_operand" "r"))
5987 (set (reg:CCX CC_REG)
5988 (compare:CCX (match_dup 1) (const_int 0)))]
5991 [(set_attr "type" "compare")])
5994 ;; Floating point arithmetic instructions.
5996 (define_expand "addtf3"
5997 [(set (match_operand:TF 0 "nonimmediate_operand" "")
5998 (plus:TF (match_operand:TF 1 "general_operand" "")
5999 (match_operand:TF 2 "general_operand" "")))]
6000 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
6001 "emit_tfmode_binop (PLUS, operands); DONE;")
6003 (define_insn "*addtf3_hq"
6004 [(set (match_operand:TF 0 "register_operand" "=e")
6005 (plus:TF (match_operand:TF 1 "register_operand" "e")
6006 (match_operand:TF 2 "register_operand" "e")))]
6007 "TARGET_FPU && TARGET_HARD_QUAD"
6009 [(set_attr "type" "fp")])
6011 (define_insn "adddf3"
6012 [(set (match_operand:DF 0 "register_operand" "=e")
6013 (plus:DF (match_operand:DF 1 "register_operand" "e")
6014 (match_operand:DF 2 "register_operand" "e")))]
6017 [(set_attr "type" "fp")
6018 (set_attr "fptype" "double")])
6020 (define_insn "addsf3"
6021 [(set (match_operand:SF 0 "register_operand" "=f")
6022 (plus:SF (match_operand:SF 1 "register_operand" "f")
6023 (match_operand:SF 2 "register_operand" "f")))]
6026 [(set_attr "type" "fp")])
6028 (define_expand "subtf3"
6029 [(set (match_operand:TF 0 "nonimmediate_operand" "")
6030 (minus:TF (match_operand:TF 1 "general_operand" "")
6031 (match_operand:TF 2 "general_operand" "")))]
6032 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
6033 "emit_tfmode_binop (MINUS, operands); DONE;")
6035 (define_insn "*subtf3_hq"
6036 [(set (match_operand:TF 0 "register_operand" "=e")
6037 (minus:TF (match_operand:TF 1 "register_operand" "e")
6038 (match_operand:TF 2 "register_operand" "e")))]
6039 "TARGET_FPU && TARGET_HARD_QUAD"
6041 [(set_attr "type" "fp")])
6043 (define_insn "subdf3"
6044 [(set (match_operand:DF 0 "register_operand" "=e")
6045 (minus:DF (match_operand:DF 1 "register_operand" "e")
6046 (match_operand:DF 2 "register_operand" "e")))]
6049 [(set_attr "type" "fp")
6050 (set_attr "fptype" "double")])
6052 (define_insn "subsf3"
6053 [(set (match_operand:SF 0 "register_operand" "=f")
6054 (minus:SF (match_operand:SF 1 "register_operand" "f")
6055 (match_operand:SF 2 "register_operand" "f")))]
6058 [(set_attr "type" "fp")])
6060 (define_expand "multf3"
6061 [(set (match_operand:TF 0 "nonimmediate_operand" "")
6062 (mult:TF (match_operand:TF 1 "general_operand" "")
6063 (match_operand:TF 2 "general_operand" "")))]
6064 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
6065 "emit_tfmode_binop (MULT, operands); DONE;")
6067 (define_insn "*multf3_hq"
6068 [(set (match_operand:TF 0 "register_operand" "=e")
6069 (mult:TF (match_operand:TF 1 "register_operand" "e")
6070 (match_operand:TF 2 "register_operand" "e")))]
6071 "TARGET_FPU && TARGET_HARD_QUAD"
6073 [(set_attr "type" "fpmul")])
6075 (define_insn "muldf3"
6076 [(set (match_operand:DF 0 "register_operand" "=e")
6077 (mult:DF (match_operand:DF 1 "register_operand" "e")
6078 (match_operand:DF 2 "register_operand" "e")))]
6081 [(set_attr "type" "fpmul")
6082 (set_attr "fptype" "double")])
6084 (define_insn "mulsf3"
6085 [(set (match_operand:SF 0 "register_operand" "=f")
6086 (mult:SF (match_operand:SF 1 "register_operand" "f")
6087 (match_operand:SF 2 "register_operand" "f")))]
6090 [(set_attr "type" "fpmul")])
6092 (define_insn "fmadf4"
6093 [(set (match_operand:DF 0 "register_operand" "=e")
6094 (fma:DF (match_operand:DF 1 "register_operand" "e")
6095 (match_operand:DF 2 "register_operand" "e")
6096 (match_operand:DF 3 "register_operand" "e")))]
6098 "fmaddd\t%1, %2, %3, %0"
6099 [(set_attr "type" "fpmul")])
6101 (define_insn "fmsdf4"
6102 [(set (match_operand:DF 0 "register_operand" "=e")
6103 (fma:DF (match_operand:DF 1 "register_operand" "e")
6104 (match_operand:DF 2 "register_operand" "e")
6105 (neg:DF (match_operand:DF 3 "register_operand" "e"))))]
6107 "fmsubd\t%1, %2, %3, %0"
6108 [(set_attr "type" "fpmul")])
6110 (define_insn "*nfmadf4"
6111 [(set (match_operand:DF 0 "register_operand" "=e")
6112 (neg:DF (fma:DF (match_operand:DF 1 "register_operand" "e")
6113 (match_operand:DF 2 "register_operand" "e")
6114 (match_operand:DF 3 "register_operand" "e"))))]
6116 "fnmaddd\t%1, %2, %3, %0"
6117 [(set_attr "type" "fpmul")])
6119 (define_insn "*nfmsdf4"
6120 [(set (match_operand:DF 0 "register_operand" "=e")
6121 (neg:DF (fma:DF (match_operand:DF 1 "register_operand" "e")
6122 (match_operand:DF 2 "register_operand" "e")
6123 (neg:DF (match_operand:DF 3 "register_operand" "e")))))]
6125 "fnmsubd\t%1, %2, %3, %0"
6126 [(set_attr "type" "fpmul")])
6128 (define_insn "fmasf4"
6129 [(set (match_operand:SF 0 "register_operand" "=f")
6130 (fma:SF (match_operand:SF 1 "register_operand" "f")
6131 (match_operand:SF 2 "register_operand" "f")
6132 (match_operand:SF 3 "register_operand" "f")))]
6134 "fmadds\t%1, %2, %3, %0"
6135 [(set_attr "type" "fpmul")])
6137 (define_insn "fmssf4"
6138 [(set (match_operand:SF 0 "register_operand" "=f")
6139 (fma:SF (match_operand:SF 1 "register_operand" "f")
6140 (match_operand:SF 2 "register_operand" "f")
6141 (neg:SF (match_operand:SF 3 "register_operand" "f"))))]
6143 "fmsubs\t%1, %2, %3, %0"
6144 [(set_attr "type" "fpmul")])
6146 (define_insn "*nfmasf4"
6147 [(set (match_operand:SF 0 "register_operand" "=f")
6148 (neg:SF (fma:SF (match_operand:SF 1 "register_operand" "f")
6149 (match_operand:SF 2 "register_operand" "f")
6150 (match_operand:SF 3 "register_operand" "f"))))]
6152 "fnmadds\t%1, %2, %3, %0"
6153 [(set_attr "type" "fpmul")])
6155 (define_insn "*nfmssf4"
6156 [(set (match_operand:SF 0 "register_operand" "=f")
6157 (neg:SF (fma:SF (match_operand:SF 1 "register_operand" "f")
6158 (match_operand:SF 2 "register_operand" "f")
6159 (neg:SF (match_operand:SF 3 "register_operand" "f")))))]
6161 "fnmsubs\t%1, %2, %3, %0"
6162 [(set_attr "type" "fpmul")])
6164 (define_insn "*muldf3_extend"
6165 [(set (match_operand:DF 0 "register_operand" "=e")
6166 (mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "f"))
6167 (float_extend:DF (match_operand:SF 2 "register_operand" "f"))))]
6169 "fsmuld\t%1, %2, %0"
6170 [(set_attr "type" "fpmul")
6171 (set_attr "fptype" "double")])
6173 (define_insn "*multf3_extend"
6174 [(set (match_operand:TF 0 "register_operand" "=e")
6175 (mult:TF (float_extend:TF (match_operand:DF 1 "register_operand" "e"))
6176 (float_extend:TF (match_operand:DF 2 "register_operand" "e"))))]
6177 "(TARGET_V8 || TARGET_V9) && TARGET_FPU && TARGET_HARD_QUAD"
6178 "fdmulq\t%1, %2, %0"
6179 [(set_attr "type" "fpmul")])
6181 (define_expand "divtf3"
6182 [(set (match_operand:TF 0 "nonimmediate_operand" "")
6183 (div:TF (match_operand:TF 1 "general_operand" "")
6184 (match_operand:TF 2 "general_operand" "")))]
6185 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
6186 "emit_tfmode_binop (DIV, operands); DONE;")
6188 ;; don't have timing for quad-prec. divide.
6189 (define_insn "*divtf3_hq"
6190 [(set (match_operand:TF 0 "register_operand" "=e")
6191 (div:TF (match_operand:TF 1 "register_operand" "e")
6192 (match_operand:TF 2 "register_operand" "e")))]
6193 "TARGET_FPU && TARGET_HARD_QUAD"
6195 [(set_attr "type" "fpdivs")])
6197 (define_expand "divdf3"
6198 [(set (match_operand:DF 0 "register_operand" "=e")
6199 (div:DF (match_operand:DF 1 "register_operand" "e")
6200 (match_operand:DF 2 "register_operand" "e")))]
6204 (define_insn "*divdf3_nofix"
6205 [(set (match_operand:DF 0 "register_operand" "=e")
6206 (div:DF (match_operand:DF 1 "register_operand" "e")
6207 (match_operand:DF 2 "register_operand" "e")))]
6208 "TARGET_FPU && !sparc_fix_ut699"
6210 [(set_attr "type" "fpdivd")
6211 (set_attr "fptype" "double")])
6213 (define_insn "*divdf3_fix"
6214 [(set (match_operand:DF 0 "register_operand" "=e")
6215 (div:DF (match_operand:DF 1 "register_operand" "e")
6216 (match_operand:DF 2 "register_operand" "e")))]
6217 "TARGET_FPU && sparc_fix_ut699"
6218 "fdivd\t%1, %2, %0\n\tstd\t%0, [%%sp-8]\n\tnop"
6219 [(set_attr "type" "fpdivd")
6220 (set_attr "fptype" "double")
6221 (set_attr "length" "3")])
6223 (define_insn "divsf3"
6224 [(set (match_operand:SF 0 "register_operand" "=f")
6225 (div:SF (match_operand:SF 1 "register_operand" "f")
6226 (match_operand:SF 2 "register_operand" "f")))]
6227 "TARGET_FPU && !sparc_fix_ut699"
6229 [(set_attr "type" "fpdivs")])
6231 (define_expand "negtf2"
6232 [(set (match_operand:TF 0 "register_operand" "")
6233 (neg:TF (match_operand:TF 1 "register_operand" "")))]
6237 (define_insn "*negtf2_hq"
6238 [(set (match_operand:TF 0 "register_operand" "=e")
6239 (neg:TF (match_operand:TF 1 "register_operand" "e")))]
6240 "TARGET_FPU && TARGET_HARD_QUAD"
6242 [(set_attr "type" "fpmove")])
6244 (define_insn_and_split "*negtf2"
6245 [(set (match_operand:TF 0 "register_operand" "=e")
6246 (neg:TF (match_operand:TF 1 "register_operand" "e")))]
6247 "TARGET_FPU && !TARGET_HARD_QUAD"
6249 "&& reload_completed"
6250 [(clobber (const_int 0))]
6252 rtx set_dest = operands[0];
6253 rtx set_src = operands[1];
6257 dest1 = gen_df_reg (set_dest, 0);
6258 dest2 = gen_df_reg (set_dest, 1);
6259 src1 = gen_df_reg (set_src, 0);
6260 src2 = gen_df_reg (set_src, 1);
6262 /* Now emit using the real source and destination we found, swapping
6263 the order if we detect overlap. */
6264 if (reg_overlap_mentioned_p (dest1, src2))
6266 emit_insn (gen_movdf (dest2, src2));
6267 emit_insn (gen_negdf2 (dest1, src1));
6271 emit_insn (gen_negdf2 (dest1, src1));
6272 if (REGNO (dest2) != REGNO (src2))
6273 emit_insn (gen_movdf (dest2, src2));
6277 [(set_attr "length" "2")])
6279 (define_expand "negdf2"
6280 [(set (match_operand:DF 0 "register_operand" "")
6281 (neg:DF (match_operand:DF 1 "register_operand" "")))]
6285 (define_insn_and_split "*negdf2_notv9"
6286 [(set (match_operand:DF 0 "register_operand" "=e")
6287 (neg:DF (match_operand:DF 1 "register_operand" "e")))]
6288 "TARGET_FPU && !TARGET_V9"
6290 "&& reload_completed"
6291 [(clobber (const_int 0))]
6293 rtx set_dest = operands[0];
6294 rtx set_src = operands[1];
6298 dest1 = gen_highpart (SFmode, set_dest);
6299 dest2 = gen_lowpart (SFmode, set_dest);
6300 src1 = gen_highpart (SFmode, set_src);
6301 src2 = gen_lowpart (SFmode, set_src);
6303 /* Now emit using the real source and destination we found, swapping
6304 the order if we detect overlap. */
6305 if (reg_overlap_mentioned_p (dest1, src2))
6307 emit_insn (gen_movsf (dest2, src2));
6308 emit_insn (gen_negsf2 (dest1, src1));
6312 emit_insn (gen_negsf2 (dest1, src1));
6313 if (REGNO (dest2) != REGNO (src2))
6314 emit_insn (gen_movsf (dest2, src2));
6318 [(set_attr "length" "2")])
6320 (define_insn "*negdf2_v9"
6321 [(set (match_operand:DF 0 "register_operand" "=e")
6322 (neg:DF (match_operand:DF 1 "register_operand" "e")))]
6323 "TARGET_FPU && TARGET_V9"
6325 [(set_attr "type" "fpmove")
6326 (set_attr "fptype" "double")])
6328 (define_insn "negsf2"
6329 [(set (match_operand:SF 0 "register_operand" "=f")
6330 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
6333 [(set_attr "type" "fpmove")])
6335 (define_expand "abstf2"
6336 [(set (match_operand:TF 0 "register_operand" "")
6337 (abs:TF (match_operand:TF 1 "register_operand" "")))]
6341 (define_insn "*abstf2_hq"
6342 [(set (match_operand:TF 0 "register_operand" "=e")
6343 (abs:TF (match_operand:TF 1 "register_operand" "e")))]
6344 "TARGET_FPU && TARGET_HARD_QUAD"
6346 [(set_attr "type" "fpmove")])
6348 (define_insn_and_split "*abstf2"
6349 [(set (match_operand:TF 0 "register_operand" "=e")
6350 (abs:TF (match_operand:TF 1 "register_operand" "e")))]
6351 "TARGET_FPU && !TARGET_HARD_QUAD"
6353 "&& reload_completed"
6354 [(clobber (const_int 0))]
6356 rtx set_dest = operands[0];
6357 rtx set_src = operands[1];
6361 dest1 = gen_df_reg (set_dest, 0);
6362 dest2 = gen_df_reg (set_dest, 1);
6363 src1 = gen_df_reg (set_src, 0);
6364 src2 = gen_df_reg (set_src, 1);
6366 /* Now emit using the real source and destination we found, swapping
6367 the order if we detect overlap. */
6368 if (reg_overlap_mentioned_p (dest1, src2))
6370 emit_insn (gen_movdf (dest2, src2));
6371 emit_insn (gen_absdf2 (dest1, src1));
6375 emit_insn (gen_absdf2 (dest1, src1));
6376 if (REGNO (dest2) != REGNO (src2))
6377 emit_insn (gen_movdf (dest2, src2));
6381 [(set_attr "length" "2")])
6383 (define_expand "absdf2"
6384 [(set (match_operand:DF 0 "register_operand" "")
6385 (abs:DF (match_operand:DF 1 "register_operand" "")))]
6389 (define_insn_and_split "*absdf2_notv9"
6390 [(set (match_operand:DF 0 "register_operand" "=e")
6391 (abs:DF (match_operand:DF 1 "register_operand" "e")))]
6392 "TARGET_FPU && !TARGET_V9"
6394 "&& reload_completed"
6395 [(clobber (const_int 0))]
6397 rtx set_dest = operands[0];
6398 rtx set_src = operands[1];
6402 dest1 = gen_highpart (SFmode, set_dest);
6403 dest2 = gen_lowpart (SFmode, set_dest);
6404 src1 = gen_highpart (SFmode, set_src);
6405 src2 = gen_lowpart (SFmode, set_src);
6407 /* Now emit using the real source and destination we found, swapping
6408 the order if we detect overlap. */
6409 if (reg_overlap_mentioned_p (dest1, src2))
6411 emit_insn (gen_movsf (dest2, src2));
6412 emit_insn (gen_abssf2 (dest1, src1));
6416 emit_insn (gen_abssf2 (dest1, src1));
6417 if (REGNO (dest2) != REGNO (src2))
6418 emit_insn (gen_movsf (dest2, src2));
6422 [(set_attr "length" "2")])
6424 (define_insn "*absdf2_v9"
6425 [(set (match_operand:DF 0 "register_operand" "=e")
6426 (abs:DF (match_operand:DF 1 "register_operand" "e")))]
6427 "TARGET_FPU && TARGET_V9"
6429 [(set_attr "type" "fpmove")
6430 (set_attr "fptype" "double")])
6432 (define_insn "abssf2"
6433 [(set (match_operand:SF 0 "register_operand" "=f")
6434 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
6437 [(set_attr "type" "fpmove")])
6439 (define_expand "sqrttf2"
6440 [(set (match_operand:TF 0 "nonimmediate_operand" "")
6441 (sqrt:TF (match_operand:TF 1 "general_operand" "")))]
6442 "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)"
6443 "emit_tfmode_unop (SQRT, operands); DONE;")
6445 (define_insn "*sqrttf2_hq"
6446 [(set (match_operand:TF 0 "register_operand" "=e")
6447 (sqrt:TF (match_operand:TF 1 "register_operand" "e")))]
6448 "TARGET_FPU && TARGET_HARD_QUAD"
6450 [(set_attr "type" "fpsqrts")])
6452 (define_expand "sqrtdf2"
6453 [(set (match_operand:DF 0 "register_operand" "=e")
6454 (sqrt:DF (match_operand:DF 1 "register_operand" "e")))]
6458 (define_insn "*sqrtdf2_nofix"
6459 [(set (match_operand:DF 0 "register_operand" "=e")
6460 (sqrt:DF (match_operand:DF 1 "register_operand" "e")))]
6461 "TARGET_FPU && !sparc_fix_ut699"
6463 [(set_attr "type" "fpsqrtd")
6464 (set_attr "fptype" "double")])
6466 (define_insn "*sqrtdf2_fix"
6467 [(set (match_operand:DF 0 "register_operand" "=e")
6468 (sqrt:DF (match_operand:DF 1 "register_operand" "e")))]
6469 "TARGET_FPU && sparc_fix_ut699"
6470 "fsqrtd\t%1, %0\n\tstd\t%0, [%%sp-8]\n\tnop"
6471 [(set_attr "type" "fpsqrtd")
6472 (set_attr "fptype" "double")
6473 (set_attr "length" "3")])
6475 (define_insn "sqrtsf2"
6476 [(set (match_operand:SF 0 "register_operand" "=f")
6477 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
6478 "TARGET_FPU && !sparc_fix_ut699"
6480 [(set_attr "type" "fpsqrts")])
6483 ;; Arithmetic shift instructions.
6485 (define_insn "ashlsi3"
6486 [(set (match_operand:SI 0 "register_operand" "=r")
6487 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6488 (match_operand:SI 2 "arith_operand" "rI")))]
6491 if (GET_CODE (operands[2]) == CONST_INT)
6492 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
6493 return "sll\t%1, %2, %0";
6495 [(set_attr "type" "shift")])
6497 (define_expand "ashldi3"
6498 [(set (match_operand:DI 0 "register_operand" "=r")
6499 (ashift:DI (match_operand:DI 1 "register_operand" "r")
6500 (match_operand:SI 2 "arith_operand" "rI")))]
6501 "TARGET_ARCH64 || TARGET_V8PLUS"
6505 if (GET_CODE (operands[2]) == CONST_INT)
6507 emit_insn (gen_ashldi3_v8plus (operands[0], operands[1], operands[2]));
6512 (define_insn "*ashldi3_sp64"
6513 [(set (match_operand:DI 0 "register_operand" "=r")
6514 (ashift:DI (match_operand:DI 1 "register_operand" "r")
6515 (match_operand:SI 2 "arith_operand" "rI")))]
6518 if (GET_CODE (operands[2]) == CONST_INT)
6519 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
6520 return "sllx\t%1, %2, %0";
6522 [(set_attr "type" "shift")])
6524 (define_insn "ashldi3_v8plus"
6525 [(set (match_operand:DI 0 "register_operand" "=&h,&h,r")
6526 (ashift:DI (match_operand:DI 1 "arith_operand" "rI,0,rI")
6527 (match_operand:SI 2 "arith_operand" "rI,rI,rI")))
6528 (clobber (match_scratch:SI 3 "=X,X,&h"))]
6531 return output_v8plus_shift (insn ,operands, \"sllx\");
6533 [(set_attr "type" "multi")
6534 (set_attr "length" "5,5,6")])
6536 (define_insn "*cmp_ccnz_ashift_1"
6537 [(set (reg:CCNZ CC_REG)
6538 (compare:CCNZ (ashift:SI (match_operand:SI 0 "register_operand" "r")
6542 "addcc\t%0, %0, %%g0"
6543 [(set_attr "type" "compare")])
6545 (define_insn "*cmp_ccnz_set_ashift_1"
6546 [(set (reg:CCNZ CC_REG)
6547 (compare:CCNZ (ashift:SI (match_operand:SI 1 "register_operand" "r")
6550 (set (match_operand:SI 0 "register_operand" "=r")
6551 (ashift:SI (match_dup 1) (const_int 1)))]
6554 [(set_attr "type" "compare")])
6556 (define_insn "ashrsi3"
6557 [(set (match_operand:SI 0 "register_operand" "=r")
6558 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6559 (match_operand:SI 2 "arith_operand" "rI")))]
6562 if (GET_CODE (operands[2]) == CONST_INT)
6563 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
6564 return "sra\t%1, %2, %0";
6566 [(set_attr "type" "shift")])
6568 (define_insn "*ashrsi3_extend0"
6569 [(set (match_operand:DI 0 "register_operand" "=r")
6570 (sign_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6571 (match_operand:SI 2 "arith_operand" "rI"))))]
6574 if (GET_CODE (operands[2]) == CONST_INT)
6575 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
6576 return "sra\t%1, %2, %0";
6578 [(set_attr "type" "shift")])
6580 ;; This handles the case where
6581 ;; (sign_extend:DI (ashiftrt:SI (match_operand:SI) (match_operand:SI)))
6582 ;; but combiner "simplifies" it for us.
6583 (define_insn "*ashrsi3_extend1"
6584 [(set (match_operand:DI 0 "register_operand" "=r")
6585 (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 1 "register_operand" "r") 0)
6587 (match_operand:SI 2 "small_int_operand" "I")))]
6588 "TARGET_ARCH64 && INTVAL (operands[2]) >= 32 && INTVAL (operands[2]) < 64"
6590 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
6591 return "sra\t%1, %2, %0";
6593 [(set_attr "type" "shift")])
6595 ;; This handles the case where
6596 ;; (ashiftrt:DI (sign_extend:DI (match_operand:SI)) (const_int))
6597 ;; but combiner "simplifies" it for us.
6598 (define_insn "*ashrsi3_extend2"
6599 [(set (match_operand:DI 0 "register_operand" "=r")
6600 (sign_extract:DI (subreg:DI (match_operand:SI 1 "register_operand" "r") 0)
6601 (match_operand 2 "small_int_operand" "I")
6603 "TARGET_ARCH64 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 32"
6605 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
6606 return "sra\t%1, %2, %0";
6608 [(set_attr "type" "shift")])
6610 (define_expand "ashrdi3"
6611 [(set (match_operand:DI 0 "register_operand" "=r")
6612 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6613 (match_operand:SI 2 "arith_operand" "rI")))]
6614 "TARGET_ARCH64 || TARGET_V8PLUS"
6618 if (GET_CODE (operands[2]) == CONST_INT)
6619 FAIL; /* prefer generic code in this case */
6620 emit_insn (gen_ashrdi3_v8plus (operands[0], operands[1], operands[2]));
6625 (define_insn "*ashrdi3_sp64"
6626 [(set (match_operand:DI 0 "register_operand" "=r")
6627 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6628 (match_operand:SI 2 "arith_operand" "rI")))]
6631 if (GET_CODE (operands[2]) == CONST_INT)
6632 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
6633 return "srax\t%1, %2, %0";
6635 [(set_attr "type" "shift")])
6637 (define_insn "ashrdi3_v8plus"
6638 [(set (match_operand:DI 0 "register_operand" "=&h,&h,r")
6639 (ashiftrt:DI (match_operand:DI 1 "arith_operand" "rI,0,rI")
6640 (match_operand:SI 2 "arith_operand" "rI,rI,rI")))
6641 (clobber (match_scratch:SI 3 "=X,X,&h"))]
6644 return output_v8plus_shift (insn, operands, \"srax\");
6646 [(set_attr "type" "multi")
6647 (set_attr "length" "5,5,6")])
6649 (define_insn "lshrsi3"
6650 [(set (match_operand:SI 0 "register_operand" "=r")
6651 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
6652 (match_operand:SI 2 "arith_operand" "rI")))]
6655 if (GET_CODE (operands[2]) == CONST_INT)
6656 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
6657 return "srl\t%1, %2, %0";
6659 [(set_attr "type" "shift")])
6661 (define_insn "*lshrsi3_extend0"
6662 [(set (match_operand:DI 0 "register_operand" "=r")
6664 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
6665 (match_operand:SI 2 "arith_operand" "rI"))))]
6668 if (GET_CODE (operands[2]) == CONST_INT)
6669 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
6670 return "srl\t%1, %2, %0";
6672 [(set_attr "type" "shift")])
6674 ;; This handles the case where
6675 ;; (zero_extend:DI (lshiftrt:SI (match_operand:SI) (match_operand:SI)))
6676 ;; but combiner "simplifies" it for us.
6677 (define_insn "*lshrsi3_extend1"
6678 [(set (match_operand:DI 0 "register_operand" "=r")
6679 (and:DI (subreg:DI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
6680 (match_operand:SI 2 "arith_operand" "rI")) 0)
6681 (match_operand 3 "const_int_operand" "")))]
6682 "TARGET_ARCH64 && (unsigned HOST_WIDE_INT) INTVAL (operands[3]) == 0xffffffff"
6684 if (GET_CODE (operands[2]) == CONST_INT)
6685 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
6686 return "srl\t%1, %2, %0";
6688 [(set_attr "type" "shift")])
6690 ;; This handles the case where
6691 ;; (lshiftrt:DI (zero_extend:DI (match_operand:SI)) (const_int))
6692 ;; but combiner "simplifies" it for us.
6693 (define_insn "*lshrsi3_extend2"
6694 [(set (match_operand:DI 0 "register_operand" "=r")
6695 (zero_extract:DI (subreg:DI (match_operand:SI 1 "register_operand" "r") 0)
6696 (match_operand 2 "small_int_operand" "I")
6698 "TARGET_ARCH64 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 32"
6700 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
6701 return "srl\t%1, %2, %0";
6703 [(set_attr "type" "shift")])
6705 (define_expand "lshrdi3"
6706 [(set (match_operand:DI 0 "register_operand" "=r")
6707 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
6708 (match_operand:SI 2 "arith_operand" "rI")))]
6709 "TARGET_ARCH64 || TARGET_V8PLUS"
6713 if (GET_CODE (operands[2]) == CONST_INT)
6715 emit_insn (gen_lshrdi3_v8plus (operands[0], operands[1], operands[2]));
6720 (define_insn "*lshrdi3_sp64"
6721 [(set (match_operand:DI 0 "register_operand" "=r")
6722 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
6723 (match_operand:SI 2 "arith_operand" "rI")))]
6726 if (GET_CODE (operands[2]) == CONST_INT)
6727 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
6728 return "srlx\t%1, %2, %0";
6730 [(set_attr "type" "shift")])
6732 (define_insn "lshrdi3_v8plus"
6733 [(set (match_operand:DI 0 "register_operand" "=&h,&h,r")
6734 (lshiftrt:DI (match_operand:DI 1 "arith_operand" "rI,0,rI")
6735 (match_operand:SI 2 "arith_operand" "rI,rI,rI")))
6736 (clobber (match_scratch:SI 3 "=X,X,&h"))]
6739 return output_v8plus_shift (insn, operands, \"srlx\");
6741 [(set_attr "type" "multi")
6742 (set_attr "length" "5,5,6")])
6745 [(set (match_operand:SI 0 "register_operand" "=r")
6746 (ashiftrt:SI (subreg:SI (lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
6748 (match_operand:SI 2 "small_int_operand" "I")))]
6749 "TARGET_ARCH64 && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 32"
6751 operands[2] = GEN_INT (INTVAL (operands[2]) + 32);
6752 return "srax\t%1, %2, %0";
6754 [(set_attr "type" "shift")])
6757 [(set (match_operand:SI 0 "register_operand" "=r")
6758 (lshiftrt:SI (subreg:SI (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6760 (match_operand:SI 2 "small_int_operand" "I")))]
6761 "TARGET_ARCH64 && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 32"
6763 operands[2] = GEN_INT (INTVAL (operands[2]) + 32);
6764 return "srlx\t%1, %2, %0";
6766 [(set_attr "type" "shift")])
6769 [(set (match_operand:SI 0 "register_operand" "=r")
6770 (ashiftrt:SI (subreg:SI (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6771 (match_operand:SI 2 "small_int_operand" "I")) 4)
6772 (match_operand:SI 3 "small_int_operand" "I")))]
6774 && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) >= 32
6775 && (unsigned HOST_WIDE_INT) INTVAL (operands[3]) < 32
6776 && (unsigned HOST_WIDE_INT) (INTVAL (operands[2]) + INTVAL (operands[3])) < 64"
6778 operands[2] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3]));
6780 return "srax\t%1, %2, %0";
6782 [(set_attr "type" "shift")])
6785 [(set (match_operand:SI 0 "register_operand" "=r")
6786 (lshiftrt:SI (subreg:SI (lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
6787 (match_operand:SI 2 "small_int_operand" "I")) 4)
6788 (match_operand:SI 3 "small_int_operand" "I")))]
6790 && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) >= 32
6791 && (unsigned HOST_WIDE_INT) INTVAL (operands[3]) < 32
6792 && (unsigned HOST_WIDE_INT) (INTVAL (operands[2]) + INTVAL (operands[3])) < 64"
6794 operands[2] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3]));
6796 return "srlx\t%1, %2, %0";
6798 [(set_attr "type" "shift")])
6801 ;; Unconditional and other jump instructions.
6803 (define_expand "jump"
6804 [(set (pc) (label_ref (match_operand 0 "" "")))]
6807 (define_insn "*jump_ubranch"
6808 [(set (pc) (label_ref (match_operand 0 "" "")))]
6811 return output_ubranch (operands[0], insn);
6813 [(set_attr "type" "uncond_branch")])
6815 (define_insn "*jump_cbcond"
6816 [(set (pc) (label_ref (match_operand 0 "" "")))]
6819 return output_ubranch (operands[0], insn);
6821 [(set_attr "type" "uncond_cbcond")])
6823 (define_expand "tablejump"
6824 [(parallel [(set (pc) (match_operand 0 "register_operand" "r"))
6825 (use (label_ref (match_operand 1 "" "")))])]
6828 gcc_assert (GET_MODE (operands[0]) == CASE_VECTOR_MODE);
6830 /* In pic mode, our address differences are against the base of the
6831 table. Add that base value back in; CSE ought to be able to combine
6832 the two address loads. */
6836 tmp = gen_rtx_LABEL_REF (Pmode, operands[1]);
6838 if (CASE_VECTOR_MODE != Pmode)
6839 tmp2 = gen_rtx_SIGN_EXTEND (Pmode, tmp2);
6840 tmp = gen_rtx_PLUS (Pmode, tmp2, tmp);
6841 operands[0] = memory_address (Pmode, tmp);
6845 (define_insn "*tablejump_sp32"
6846 [(set (pc) (match_operand:SI 0 "address_operand" "p"))
6847 (use (label_ref (match_operand 1 "" "")))]
6850 [(set_attr "type" "uncond_branch")])
6852 (define_insn "*tablejump_sp64"
6853 [(set (pc) (match_operand:DI 0 "address_operand" "p"))
6854 (use (label_ref (match_operand 1 "" "")))]
6857 [(set_attr "type" "uncond_branch")])
6860 ;; Jump to subroutine instructions.
6862 (define_expand "call"
6863 ;; Note that this expression is not used for generating RTL.
6864 ;; All the RTL is generated explicitly below.
6865 [(call (match_operand 0 "call_operand" "")
6866 (match_operand 3 "" "i"))]
6867 ;; operands[2] is next_arg_register
6868 ;; operands[3] is struct_value_size_rtx.
6873 gcc_assert (MEM_P (operands[0]) && GET_MODE (operands[0]) == FUNCTION_MODE);
6875 gcc_assert (GET_CODE (operands[3]) == CONST_INT);
6877 if (GET_CODE (XEXP (operands[0], 0)) == LABEL_REF)
6879 /* This is really a PIC sequence. We want to represent
6880 it as a funny jump so its delay slots can be filled.
6882 ??? But if this really *is* a CALL, will not it clobber the
6883 call-clobbered registers? We lose this if it is a JUMP_INSN.
6884 Why cannot we have delay slots filled if it were a CALL? */
6886 /* We accept negative sizes for untyped calls. */
6887 if (TARGET_ARCH32 && INTVAL (operands[3]) != 0)
6892 gen_rtx_SET (pc_rtx, XEXP (operands[0], 0)),
6894 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 15)))));
6900 gen_rtx_SET (pc_rtx, XEXP (operands[0], 0)),
6901 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 15)))));
6905 fn_rtx = operands[0];
6907 /* We accept negative sizes for untyped calls. */
6908 if (TARGET_ARCH32 && INTVAL (operands[3]) != 0)
6909 sparc_emit_call_insn
6912 gen_rtvec (3, gen_rtx_CALL (VOIDmode, fn_rtx, const0_rtx),
6914 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 15)))),
6917 sparc_emit_call_insn
6920 gen_rtvec (2, gen_rtx_CALL (VOIDmode, fn_rtx, const0_rtx),
6921 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 15)))),
6929 ;; We can't use the same pattern for these two insns, because then registers
6930 ;; in the address may not be properly reloaded.
6932 (define_insn "*call_address_sp32"
6933 [(call (mem:SI (match_operand:SI 0 "address_operand" "p"))
6934 (match_operand 1 "" ""))
6935 (clobber (reg:SI O7_REG))]
6936 ;;- Do not use operand 1 for most machines.
6939 [(set_attr "type" "call")])
6941 (define_insn "*call_symbolic_sp32"
6942 [(call (mem:SI (match_operand:SI 0 "symbolic_operand" "s"))
6943 (match_operand 1 "" ""))
6944 (clobber (reg:SI O7_REG))]
6945 ;;- Do not use operand 1 for most machines.
6948 [(set_attr "type" "call")])
6950 (define_insn "*call_address_sp64"
6951 [(call (mem:DI (match_operand:DI 0 "address_operand" "p"))
6952 (match_operand 1 "" ""))
6953 (clobber (reg:DI O7_REG))]
6954 ;;- Do not use operand 1 for most machines.
6957 [(set_attr "type" "call")])
6959 (define_insn "*call_symbolic_sp64"
6960 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "s"))
6961 (match_operand 1 "" ""))
6962 (clobber (reg:DI O7_REG))]
6963 ;;- Do not use operand 1 for most machines.
6966 [(set_attr "type" "call")])
6968 ;; This is a call that wants a structure value.
6969 ;; There is no such critter for v9 (??? we may need one anyway).
6970 (define_insn "*call_address_struct_value_sp32"
6971 [(call (mem:SI (match_operand:SI 0 "address_operand" "p"))
6972 (match_operand 1 "" ""))
6973 (match_operand 2 "immediate_operand" "")
6974 (clobber (reg:SI O7_REG))]
6975 ;;- Do not use operand 1 for most machines.
6976 "TARGET_ARCH32 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 0"
6978 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xfff);
6979 return "call\t%a0, %1\n\t nop\n\tunimp\t%2";
6981 [(set_attr "type" "call_no_delay_slot")
6982 (set_attr "length" "3")])
6984 ;; This is a call that wants a structure value.
6985 ;; There is no such critter for v9 (??? we may need one anyway).
6986 (define_insn "*call_symbolic_struct_value_sp32"
6987 [(call (mem:SI (match_operand:SI 0 "symbolic_operand" "s"))
6988 (match_operand 1 "" ""))
6989 (match_operand 2 "immediate_operand" "")
6990 (clobber (reg:SI O7_REG))]
6991 ;;- Do not use operand 1 for most machines.
6992 "TARGET_ARCH32 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 0"
6994 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xfff);
6995 return "call\t%a0, %1\n\t nop\n\tunimp\t%2";
6997 [(set_attr "type" "call_no_delay_slot")
6998 (set_attr "length" "3")])
7000 ;; This is a call that may want a structure value. This is used for
7002 (define_insn "*call_address_untyped_struct_value_sp32"
7003 [(call (mem:SI (match_operand:SI 0 "address_operand" "p"))
7004 (match_operand 1 "" ""))
7005 (match_operand 2 "immediate_operand" "")
7006 (clobber (reg:SI O7_REG))]
7007 ;;- Do not use operand 1 for most machines.
7008 "TARGET_ARCH32 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0"
7009 "call\t%a0, %1\n\t nop\n\tnop"
7010 [(set_attr "type" "call_no_delay_slot")
7011 (set_attr "length" "3")])
7013 ;; This is a call that may want a structure value. This is used for
7015 (define_insn "*call_symbolic_untyped_struct_value_sp32"
7016 [(call (mem:SI (match_operand:SI 0 "symbolic_operand" "s"))
7017 (match_operand 1 "" ""))
7018 (match_operand 2 "immediate_operand" "")
7019 (clobber (reg:SI O7_REG))]
7020 ;;- Do not use operand 1 for most machines.
7021 "TARGET_ARCH32 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0"
7022 "call\t%a0, %1\n\t nop\n\tnop"
7023 [(set_attr "type" "call_no_delay_slot")
7024 (set_attr "length" "3")])
7026 (define_expand "call_value"
7027 ;; Note that this expression is not used for generating RTL.
7028 ;; All the RTL is generated explicitly below.
7029 [(set (match_operand 0 "register_operand" "=rf")
7030 (call (match_operand 1 "" "")
7031 (match_operand 4 "" "")))]
7032 ;; operand 2 is stack_size_rtx
7033 ;; operand 3 is next_arg_register
7039 gcc_assert (MEM_P (operands[1]) && GET_MODE (operands[1]) == FUNCTION_MODE);
7041 fn_rtx = operands[1];
7044 gen_rtx_SET (operands[0],
7045 gen_rtx_CALL (VOIDmode, fn_rtx, const0_rtx)),
7046 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 15)));
7048 sparc_emit_call_insn (gen_rtx_PARALLEL (VOIDmode, vec), XEXP (fn_rtx, 0));
7053 (define_insn "*call_value_address_sp32"
7054 [(set (match_operand 0 "" "=rf")
7055 (call (mem:SI (match_operand:SI 1 "address_operand" "p"))
7056 (match_operand 2 "" "")))
7057 (clobber (reg:SI O7_REG))]
7058 ;;- Do not use operand 2 for most machines.
7061 [(set_attr "type" "call")])
7063 (define_insn "*call_value_symbolic_sp32"
7064 [(set (match_operand 0 "" "=rf")
7065 (call (mem:SI (match_operand:SI 1 "symbolic_operand" "s"))
7066 (match_operand 2 "" "")))
7067 (clobber (reg:SI O7_REG))]
7068 ;;- Do not use operand 2 for most machines.
7071 [(set_attr "type" "call")])
7073 (define_insn "*call_value_address_sp64"
7074 [(set (match_operand 0 "" "")
7075 (call (mem:DI (match_operand:DI 1 "address_operand" "p"))
7076 (match_operand 2 "" "")))
7077 (clobber (reg:DI O7_REG))]
7078 ;;- Do not use operand 2 for most machines.
7081 [(set_attr "type" "call")])
7083 (define_insn "*call_value_symbolic_sp64"
7084 [(set (match_operand 0 "" "")
7085 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "s"))
7086 (match_operand 2 "" "")))
7087 (clobber (reg:DI O7_REG))]
7088 ;;- Do not use operand 2 for most machines.
7091 [(set_attr "type" "call")])
7093 (define_expand "untyped_call"
7094 [(parallel [(call (match_operand 0 "" "")
7096 (match_operand:BLK 1 "memory_operand" "")
7097 (match_operand 2 "" "")])]
7100 rtx valreg1 = gen_rtx_REG (DImode, 8);
7101 rtx result = operands[1];
7103 /* Pass constm1 to indicate that it may expect a structure value, but
7104 we don't know what size it is. */
7105 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, constm1_rtx));
7107 /* Save the function value registers. */
7108 emit_move_insn (adjust_address (result, DImode, 0), valreg1);
7111 rtx valreg2 = gen_rtx_REG (TARGET_ARCH64 ? TFmode : DFmode, 32);
7112 emit_move_insn (adjust_address (result, TARGET_ARCH64 ? TFmode : DFmode, 8),
7116 /* The optimizer does not know that the call sets the function value
7117 registers we stored in the result block. We avoid problems by
7118 claiming that all hard registers are used and clobbered at this
7120 emit_insn (gen_blockage ());
7126 ;; Tail call instructions.
7128 (define_expand "sibcall"
7129 [(parallel [(call (match_operand 0 "call_operand" "") (const_int 0))
7134 (define_insn "*sibcall_symbolic_sp32"
7135 [(call (mem:SI (match_operand:SI 0 "symbolic_operand" "s"))
7136 (match_operand 1 "" ""))
7140 return output_sibcall(insn, operands[0]);
7142 [(set_attr "type" "sibcall")])
7144 (define_insn "*sibcall_symbolic_sp64"
7145 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "s"))
7146 (match_operand 1 "" ""))
7150 return output_sibcall(insn, operands[0]);
7152 [(set_attr "type" "sibcall")])
7154 (define_expand "sibcall_value"
7155 [(parallel [(set (match_operand 0 "register_operand" "=rf")
7156 (call (match_operand 1 "" "") (const_int 0)))
7161 (define_insn "*sibcall_value_symbolic_sp32"
7162 [(set (match_operand 0 "" "=rf")
7163 (call (mem:SI (match_operand:SI 1 "symbolic_operand" "s"))
7164 (match_operand 2 "" "")))
7168 return output_sibcall(insn, operands[1]);
7170 [(set_attr "type" "sibcall")])
7172 (define_insn "*sibcall_value_symbolic_sp64"
7173 [(set (match_operand 0 "" "")
7174 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "s"))
7175 (match_operand 2 "" "")))
7179 return output_sibcall(insn, operands[1]);
7181 [(set_attr "type" "sibcall")])
7184 ;; Special instructions.
7186 (define_expand "prologue"
7191 sparc_flat_expand_prologue ();
7193 sparc_expand_prologue ();
7197 ;; The "register window save" insn is modelled as follows. The dwarf2
7198 ;; information is manually added in emit_window_save.
7200 (define_insn "window_save"
7202 [(match_operand 0 "arith_operand" "rI")]
7205 "save\t%%sp, %0, %%sp"
7206 [(set_attr "type" "savew")])
7208 (define_expand "epilogue"
7213 sparc_flat_expand_epilogue (false);
7215 sparc_expand_epilogue (false);
7218 (define_expand "sibcall_epilogue"
7223 sparc_flat_expand_epilogue (false);
7225 sparc_expand_epilogue (false);
7229 (define_expand "eh_return"
7230 [(use (match_operand 0 "general_operand" ""))]
7233 emit_move_insn (gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM), operands[0]);
7234 emit_jump_insn (gen_eh_return_internal ());
7239 (define_insn_and_split "eh_return_internal"
7243 "epilogue_completed"
7247 sparc_flat_expand_epilogue (true);
7249 sparc_expand_epilogue (true);
7252 (define_expand "return"
7254 "sparc_can_use_return_insn_p ()"
7256 if (cfun->calls_alloca)
7257 emit_insn (gen_frame_blockage ());
7260 (define_insn "*return_internal"
7264 return output_return (insn);
7266 [(set_attr "type" "return")
7267 (set (attr "length")
7268 (cond [(eq_attr "calls_eh_return" "true")
7269 (if_then_else (eq_attr "delayed_branch" "true")
7270 (if_then_else (ior (eq_attr "isa" "v9")
7271 (eq_attr "flat" "true"))
7274 (if_then_else (eq_attr "flat" "true")
7277 (ior (eq_attr "leaf_function" "true") (eq_attr "flat" "true"))
7278 (if_then_else (eq_attr "empty_delay_slot" "true")
7281 (eq_attr "empty_delay_slot" "true")
7282 (if_then_else (eq_attr "delayed_branch" "true")
7287 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
7288 ;; all of memory. This blocks insns from being moved across this point.
7290 (define_insn "blockage"
7291 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
7294 [(set_attr "length" "0")])
7296 ;; Do not schedule instructions accessing memory before this point.
7298 (define_expand "frame_blockage"
7300 (unspec:BLK [(match_dup 1)] UNSPEC_FRAME_BLOCKAGE))]
7303 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
7304 MEM_VOLATILE_P (operands[0]) = 1;
7305 operands[1] = stack_pointer_rtx;
7308 (define_insn "*frame_blockage<P:mode>"
7309 [(set (match_operand:BLK 0 "" "")
7310 (unspec:BLK [(match_operand:P 1 "" "")] UNSPEC_FRAME_BLOCKAGE))]
7313 [(set_attr "length" "0")])
7315 ;; We use membar #Sync for the speculation barrier on V9.
7317 (define_insn "speculation_barrier"
7318 [(unspec_volatile [(const_int 0)] UNSPECV_SPECULATION_BARRIER)]
7321 [(set_attr "type" "multi")])
7323 (define_expand "probe_stack"
7324 [(set (match_operand 0 "memory_operand" "") (const_int 0))]
7328 = adjust_address (operands[0], GET_MODE (operands[0]), SPARC_STACK_BIAS);
7331 (define_insn "probe_stack_range<P:mode>"
7332 [(set (match_operand:P 0 "register_operand" "=r")
7333 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
7334 (match_operand:P 2 "register_operand" "r")]
7335 UNSPECV_PROBE_STACK_RANGE))]
7338 return output_probe_stack_range (operands[0], operands[2]);
7340 [(set_attr "type" "multi")])
7342 ;; Prepare to return any type including a structure value.
7344 (define_expand "untyped_return"
7345 [(match_operand:BLK 0 "memory_operand" "")
7346 (match_operand 1 "" "")]
7349 rtx valreg1 = gen_rtx_REG (DImode, 24);
7350 rtx result = operands[0];
7354 rtx rtnreg = gen_rtx_REG (SImode, RETURN_ADDR_REGNUM);
7355 rtx value = gen_reg_rtx (SImode);
7357 /* Fetch the instruction where we will return to and see if it's an unimp
7358 instruction (the most significant 10 bits will be zero). If so,
7359 update the return address to skip the unimp instruction. */
7360 emit_move_insn (value,
7361 gen_rtx_MEM (SImode, plus_constant (SImode, rtnreg, 8)));
7362 emit_insn (gen_lshrsi3 (value, value, GEN_INT (22)));
7363 emit_insn (gen_update_return (rtnreg, value));
7366 /* Reload the function value registers.
7367 Put USE insns before the return. */
7368 emit_move_insn (valreg1, adjust_address (result, DImode, 0));
7373 rtx valreg2 = gen_rtx_REG (TARGET_ARCH64 ? TFmode : DFmode, 32);
7374 emit_move_insn (valreg2,
7375 adjust_address (result, TARGET_ARCH64 ? TFmode : DFmode, 8));
7379 /* Construct the return. */
7380 expand_naked_return ();
7385 ;; Adjust the return address conditionally. If the value of op1 is equal
7386 ;; to all zero then adjust the return address i.e. op0 = op0 + 4.
7387 ;; This is technically *half* the check required by the 32-bit SPARC
7388 ;; psABI. This check only ensures that an "unimp" insn was written by
7389 ;; the caller, but doesn't check to see if the expected size matches
7390 ;; (this is encoded in the 12 lower bits). This check is obsolete and
7391 ;; only used by the above code "untyped_return".
7393 (define_insn "update_return"
7394 [(unspec:SI [(match_operand:SI 0 "register_operand" "r")
7395 (match_operand:SI 1 "register_operand" "r")] UNSPEC_UPDATE_RETURN)]
7398 if (flag_delayed_branch)
7399 return "cmp\t%1, 0\n\tbe,a\t.+8\n\t add\t%0, 4, %0";
7401 return "cmp\t%1, 0\n\tbne\t.+12\n\t nop\n\tadd\t%0, 4, %0";
7403 [(set (attr "type") (const_string "multi"))
7404 (set (attr "length")
7405 (if_then_else (eq_attr "delayed_branch" "true")
7414 (define_expand "indirect_jump"
7415 [(set (pc) (match_operand 0 "address_operand" "p"))]
7419 (define_insn "*branch_sp32"
7420 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
7423 [(set_attr "type" "uncond_branch")])
7425 (define_insn "*branch_sp64"
7426 [(set (pc) (match_operand:DI 0 "address_operand" "p"))]
7429 [(set_attr "type" "uncond_branch")])
7431 (define_expand "save_stack_nonlocal"
7432 [(set (match_operand 0 "memory_operand" "")
7433 (match_operand 1 "register_operand" ""))
7434 (set (match_dup 2) (match_dup 3))]
7437 operands[0] = adjust_address (operands[0], Pmode, 0);
7438 operands[2] = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
7439 operands[3] = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
7442 (define_expand "restore_stack_nonlocal"
7443 [(set (match_operand 0 "register_operand" "")
7444 (match_operand 1 "memory_operand" ""))]
7447 operands[1] = adjust_address (operands[1], Pmode, 0);
7450 (define_expand "nonlocal_goto"
7451 [(match_operand 0 "general_operand" "")
7452 (match_operand 1 "general_operand" "")
7453 (match_operand 2 "memory_operand" "")
7454 (match_operand 3 "memory_operand" "")]
7457 rtx i7 = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
7458 rtx r_label = copy_to_reg (operands[1]);
7459 rtx r_sp = adjust_address (operands[2], Pmode, 0);
7460 rtx r_fp = operands[3];
7461 rtx r_i7 = adjust_address (operands[2], Pmode, GET_MODE_SIZE (Pmode));
7463 /* We need to flush all the register windows so that their contents will
7464 be re-synchronized by the restore insn of the target function. */
7466 emit_insn (gen_flush_register_windows ());
7468 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
7469 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
7471 /* Restore frame pointer for containing function. */
7472 emit_move_insn (hard_frame_pointer_rtx, r_fp);
7473 emit_stack_restore (SAVE_NONLOCAL, r_sp);
7474 emit_move_insn (i7, r_i7);
7476 /* USE of hard_frame_pointer_rtx added for consistency;
7477 not clear if really needed. */
7478 emit_use (hard_frame_pointer_rtx);
7479 emit_use (stack_pointer_rtx);
7482 emit_jump_insn (gen_indirect_jump (r_label));
7487 (define_expand "builtin_setjmp_receiver"
7488 [(label_ref (match_operand 0 "" ""))]
7489 "TARGET_VXWORKS_RTP && flag_pic"
7491 load_got_register ();
7495 ;; Special insn to flush register windows.
7497 (define_insn "flush_register_windows"
7498 [(unspec_volatile [(const_int 0)] UNSPECV_FLUSHW)]
7501 return TARGET_V9 ? "flushw" : "ta\t3";
7503 [(set_attr "type" "flushw")])
7505 ;; Special pattern for the FLUSH instruction.
7507 (define_insn "flush<P:mode>"
7508 [(unspec_volatile [(match_operand:P 0 "memory_operand" "m")] UNSPECV_FLUSH)]
7511 return TARGET_V9 ? "flush\t%f0" : "iflush\t%f0";
7513 [(set_attr "type" "iflush")])
7515 ;; Special insns to load and store the 32-bit FP Status Register.
7517 (define_insn "ldfsr"
7518 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] UNSPECV_LDFSR)]
7521 [(set_attr "type" "load")
7522 (set_attr "subtype" "regular")])
7524 (define_insn "stfsr"
7525 [(set (match_operand:SI 0 "memory_operand" "=m")
7526 (unspec_volatile:SI [(const_int 0)] UNSPECV_STFSR))]
7529 [(set_attr "type" "store")])
7532 ;; Find first set instructions.
7534 (define_expand "popcountdi2"
7535 [(set (match_operand:DI 0 "register_operand" "")
7536 (popcount:DI (match_operand:DI 1 "register_operand" "")))]
7541 emit_insn (gen_popcountdi_v8plus (operands[0], operands[1]));
7546 (define_insn "*popcountdi_sp64"
7547 [(set (match_operand:DI 0 "register_operand" "=r")
7548 (popcount:DI (match_operand:DI 1 "register_operand" "r")))]
7549 "TARGET_POPC && TARGET_ARCH64"
7552 (define_insn "popcountdi_v8plus"
7553 [(set (match_operand:DI 0 "register_operand" "=r")
7554 (popcount:DI (match_operand:DI 1 "register_operand" "r")))
7555 (clobber (match_scratch:SI 2 "=&h"))]
7556 "TARGET_POPC && TARGET_ARCH32"
7558 if (sparc_check_64 (operands[1], insn) <= 0)
7559 output_asm_insn ("srl\t%L1, 0, %L1", operands);
7560 return "sllx\t%H1, 32, %2\n\tor\t%L1, %2, %2\n\tpopc\t%2, %L0\n\tclr\t%H0";
7562 [(set_attr "type" "multi")
7563 (set_attr "length" "5")])
7565 (define_expand "popcountsi2"
7567 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
7568 (set (match_operand:SI 0 "register_operand" "")
7569 (truncate:SI (popcount:DI (match_dup 2))))]
7574 emit_insn (gen_popcountsi_v8plus (operands[0], operands[1]));
7578 operands[2] = gen_reg_rtx (DImode);
7581 (define_insn "*popcountsi_sp64"
7582 [(set (match_operand:SI 0 "register_operand" "=r")
7584 (popcount:DI (match_operand:DI 1 "register_operand" "r"))))]
7585 "TARGET_POPC && TARGET_ARCH64"
7588 (define_insn "popcountsi_v8plus"
7589 [(set (match_operand:SI 0 "register_operand" "=r")
7590 (popcount:SI (match_operand:SI 1 "register_operand" "r")))]
7591 "TARGET_POPC && TARGET_ARCH32"
7593 if (sparc_check_64 (operands[1], insn) <= 0)
7594 output_asm_insn ("srl\t%1, 0, %1", operands);
7595 return "popc\t%1, %0";
7597 [(set_attr "type" "multi")
7598 (set_attr "length" "2")])
7600 (define_expand "clzdi2"
7601 [(set (match_operand:DI 0 "register_operand" "")
7602 (clz:DI (match_operand:DI 1 "register_operand" "")))]
7607 emit_insn (gen_clzdi_v8plus (operands[0], operands[1]));
7612 (define_insn "*clzdi_sp64"
7613 [(set (match_operand:DI 0 "register_operand" "=r")
7614 (clz:DI (match_operand:DI 1 "register_operand" "r")))]
7615 "TARGET_VIS3 && TARGET_ARCH64"
7617 [(set_attr "type" "lzd")])
7619 (define_insn "clzdi_v8plus"
7620 [(set (match_operand:DI 0 "register_operand" "=r")
7621 (clz:DI (match_operand:DI 1 "register_operand" "r")))
7622 (clobber (match_scratch:SI 2 "=&h"))]
7623 "TARGET_VIS3 && TARGET_ARCH32"
7625 if (sparc_check_64 (operands[1], insn) <= 0)
7626 output_asm_insn ("srl\t%L1, 0, %L1", operands);
7627 return "sllx\t%H1, 32, %2\n\tor\t%L1, %2, %2\n\tlzd\t%2, %L0\n\tclr\t%H0";
7629 [(set_attr "type" "multi")
7630 (set_attr "length" "5")])
7632 (define_expand "clzsi2"
7634 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
7636 (truncate:SI (clz:DI (match_dup 2))))
7637 (set (match_operand:SI 0 "register_operand" "")
7638 (minus:SI (match_dup 3) (const_int 32)))]
7643 emit_insn (gen_clzsi_v8plus (operands[0], operands[1]));
7648 operands[2] = gen_reg_rtx (DImode);
7649 operands[3] = gen_reg_rtx (SImode);
7653 (define_insn "*clzsi_sp64"
7654 [(set (match_operand:SI 0 "register_operand" "=r")
7656 (clz:DI (match_operand:DI 1 "register_operand" "r"))))]
7657 "TARGET_VIS3 && TARGET_ARCH64"
7659 [(set_attr "type" "lzd")])
7661 (define_insn "clzsi_v8plus"
7662 [(set (match_operand:SI 0 "register_operand" "=r")
7663 (clz:SI (match_operand:SI 1 "register_operand" "r")))]
7664 "TARGET_VIS3 && TARGET_ARCH32"
7666 if (sparc_check_64 (operands[1], insn) <= 0)
7667 output_asm_insn ("srl\t%1, 0, %1", operands);
7668 return "lzd\t%1, %0\n\tsub\t%0, 32, %0";
7670 [(set_attr "type" "multi")
7671 (set_attr "length" "3")])
7674 ;; Peepholes go at the end.
7676 ;; Optimize consecutive loads or stores into ldd and std when possible.
7677 ;; The conditions in which we do this are very restricted and are
7678 ;; explained in the code for {registers,memory}_ok_for_ldd functions.
7681 [(set (match_operand:SI 0 "memory_operand" "")
7683 (set (match_operand:SI 1 "memory_operand" "")
7686 && mems_ok_for_ldd_peep (operands[0], operands[1], NULL_RTX)"
7687 [(set (match_dup 0) (const_int 0))]
7689 operands[0] = widen_mem_for_ldd_peep (operands[0], operands[1], DImode);
7693 [(set (match_operand:SI 0 "memory_operand" "")
7695 (set (match_operand:SI 1 "memory_operand" "")
7698 && mems_ok_for_ldd_peep (operands[1], operands[0], NULL_RTX)"
7699 [(set (match_dup 1) (const_int 0))]
7701 operands[1] = widen_mem_for_ldd_peep (operands[1], operands[0], DImode);
7705 [(set (match_operand:SI 0 "register_operand" "")
7706 (match_operand:SI 1 "memory_operand" ""))
7707 (set (match_operand:SI 2 "register_operand" "")
7708 (match_operand:SI 3 "memory_operand" ""))]
7709 "registers_ok_for_ldd_peep (operands[0], operands[2])
7710 && mems_ok_for_ldd_peep (operands[1], operands[3], operands[0])"
7711 [(set (match_dup 0) (match_dup 1))]
7713 operands[1] = widen_mem_for_ldd_peep (operands[1], operands[3], DImode);
7714 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
7718 [(set (match_operand:SI 0 "memory_operand" "")
7719 (match_operand:SI 1 "register_operand" ""))
7720 (set (match_operand:SI 2 "memory_operand" "")
7721 (match_operand:SI 3 "register_operand" ""))]
7722 "registers_ok_for_ldd_peep (operands[1], operands[3])
7723 && mems_ok_for_ldd_peep (operands[0], operands[2], NULL_RTX)"
7724 [(set (match_dup 0) (match_dup 1))]
7726 operands[0] = widen_mem_for_ldd_peep (operands[0], operands[2], DImode);
7727 operands[1] = gen_rtx_REG (DImode, REGNO (operands[1]));
7731 [(set (match_operand:SF 0 "register_operand" "")
7732 (match_operand:SF 1 "memory_operand" ""))
7733 (set (match_operand:SF 2 "register_operand" "")
7734 (match_operand:SF 3 "memory_operand" ""))]
7735 "registers_ok_for_ldd_peep (operands[0], operands[2])
7736 && mems_ok_for_ldd_peep (operands[1], operands[3], operands[0])"
7737 [(set (match_dup 0) (match_dup 1))]
7739 operands[1] = widen_mem_for_ldd_peep (operands[1], operands[3], DFmode);
7740 operands[0] = gen_rtx_REG (DFmode, REGNO (operands[0]));
7744 [(set (match_operand:SF 0 "memory_operand" "")
7745 (match_operand:SF 1 "register_operand" ""))
7746 (set (match_operand:SF 2 "memory_operand" "")
7747 (match_operand:SF 3 "register_operand" ""))]
7748 "registers_ok_for_ldd_peep (operands[1], operands[3])
7749 && mems_ok_for_ldd_peep (operands[0], operands[2], NULL_RTX)"
7750 [(set (match_dup 0) (match_dup 1))]
7752 operands[0] = widen_mem_for_ldd_peep (operands[0], operands[2], DFmode);
7753 operands[1] = gen_rtx_REG (DFmode, REGNO (operands[1]));
7757 [(set (match_operand:SI 0 "register_operand" "")
7758 (match_operand:SI 1 "memory_operand" ""))
7759 (set (match_operand:SI 2 "register_operand" "")
7760 (match_operand:SI 3 "memory_operand" ""))]
7761 "registers_ok_for_ldd_peep (operands[2], operands[0])
7762 && mems_ok_for_ldd_peep (operands[3], operands[1], operands[0])"
7763 [(set (match_dup 2) (match_dup 3))]
7765 operands[3] = widen_mem_for_ldd_peep (operands[3], operands[1], DImode);
7766 operands[2] = gen_rtx_REG (DImode, REGNO (operands[2]));
7770 [(set (match_operand:SI 0 "memory_operand" "")
7771 (match_operand:SI 1 "register_operand" ""))
7772 (set (match_operand:SI 2 "memory_operand" "")
7773 (match_operand:SI 3 "register_operand" ""))]
7774 "registers_ok_for_ldd_peep (operands[3], operands[1])
7775 && mems_ok_for_ldd_peep (operands[2], operands[0], NULL_RTX)"
7776 [(set (match_dup 2) (match_dup 3))]
7778 operands[2] = widen_mem_for_ldd_peep (operands[2], operands[0], DImode);
7779 operands[3] = gen_rtx_REG (DImode, REGNO (operands[3]));
7783 [(set (match_operand:SF 0 "register_operand" "")
7784 (match_operand:SF 1 "memory_operand" ""))
7785 (set (match_operand:SF 2 "register_operand" "")
7786 (match_operand:SF 3 "memory_operand" ""))]
7787 "registers_ok_for_ldd_peep (operands[2], operands[0])
7788 && mems_ok_for_ldd_peep (operands[3], operands[1], operands[0])"
7789 [(set (match_dup 2) (match_dup 3))]
7791 operands[3] = widen_mem_for_ldd_peep (operands[3], operands[1], DFmode);
7792 operands[2] = gen_rtx_REG (DFmode, REGNO (operands[2]));
7796 [(set (match_operand:SF 0 "memory_operand" "")
7797 (match_operand:SF 1 "register_operand" ""))
7798 (set (match_operand:SF 2 "memory_operand" "")
7799 (match_operand:SF 3 "register_operand" ""))]
7800 "registers_ok_for_ldd_peep (operands[3], operands[1])
7801 && mems_ok_for_ldd_peep (operands[2], operands[0], NULL_RTX)"
7802 [(set (match_dup 2) (match_dup 3))]
7804 operands[2] = widen_mem_for_ldd_peep (operands[2], operands[0], DFmode);
7805 operands[3] = gen_rtx_REG (DFmode, REGNO (operands[3]));
7808 ;; Optimize the case of following a reg-reg move with a test
7809 ;; of reg just moved. Don't allow floating point regs for operand 0 or 1.
7810 ;; This can result from a float to fix conversion.
7813 [(set (match_operand:SI 0 "register_operand" "")
7814 (match_operand:SI 1 "register_operand" ""))
7815 (set (reg:CC CC_REG)
7816 (compare:CC (match_operand:SI 2 "register_operand" "")
7818 "(rtx_equal_p (operands[2], operands[0])
7819 || rtx_equal_p (operands[2], operands[1]))
7820 && !SPARC_FP_REG_P (REGNO (operands[0]))
7821 && !SPARC_FP_REG_P (REGNO (operands[1]))"
7822 [(parallel [(set (match_dup 0) (match_dup 1))
7823 (set (reg:CC CC_REG)
7824 (compare:CC (match_dup 1) (const_int 0)))])]
7828 [(set (match_operand:DI 0 "register_operand" "")
7829 (match_operand:DI 1 "register_operand" ""))
7830 (set (reg:CCX CC_REG)
7831 (compare:CCX (match_operand:DI 2 "register_operand" "")
7834 && (rtx_equal_p (operands[2], operands[0])
7835 || rtx_equal_p (operands[2], operands[1]))
7836 && !SPARC_FP_REG_P (REGNO (operands[0]))
7837 && !SPARC_FP_REG_P (REGNO (operands[1]))"
7838 [(parallel [(set (match_dup 0) (match_dup 1))
7839 (set (reg:CCX CC_REG)
7840 (compare:CCX (match_dup 1) (const_int 0)))])]
7844 ;; Prefetch instructions.
7846 ;; ??? UltraSPARC-III note: A memory operation loading into the floating point
7847 ;; register file, if it hits the prefetch cache, has a chance to dual-issue
7848 ;; with other memory operations. With DFA we might be able to model this,
7849 ;; but it requires a lot of state.
7850 (define_expand "prefetch"
7851 [(match_operand 0 "address_operand" "")
7852 (match_operand 1 "const_int_operand" "")
7853 (match_operand 2 "const_int_operand" "")]
7857 emit_insn (gen_prefetch_64 (operands[0], operands[1], operands[2]));
7859 emit_insn (gen_prefetch_32 (operands[0], operands[1], operands[2]));
7863 (define_insn "prefetch_64"
7864 [(prefetch (match_operand:DI 0 "address_operand" "p")
7865 (match_operand:DI 1 "const_int_operand" "n")
7866 (match_operand:DI 2 "const_int_operand" "n"))]
7869 static const char * const prefetch_instr[2][2] = {
7871 "prefetch\t[%a0], 1", /* no locality: prefetch for one read */
7872 "prefetch\t[%a0], 0", /* medium to high locality: prefetch for several reads */
7875 "prefetch\t[%a0], 3", /* no locality: prefetch for one write */
7876 "prefetch\t[%a0], 2", /* medium to high locality: prefetch for several writes */
7879 int read_or_write = INTVAL (operands[1]);
7880 int locality = INTVAL (operands[2]);
7882 gcc_assert (read_or_write == 0 || read_or_write == 1);
7883 gcc_assert (locality >= 0 && locality < 4);
7884 return prefetch_instr [read_or_write][locality == 0 ? 0 : 1];
7886 [(set_attr "type" "load")
7887 (set_attr "subtype" "prefetch")])
7889 (define_insn "prefetch_32"
7890 [(prefetch (match_operand:SI 0 "address_operand" "p")
7891 (match_operand:SI 1 "const_int_operand" "n")
7892 (match_operand:SI 2 "const_int_operand" "n"))]
7895 static const char * const prefetch_instr[2][2] = {
7897 "prefetch\t[%a0], 1", /* no locality: prefetch for one read */
7898 "prefetch\t[%a0], 0", /* medium to high locality: prefetch for several reads */
7901 "prefetch\t[%a0], 3", /* no locality: prefetch for one write */
7902 "prefetch\t[%a0], 2", /* medium to high locality: prefetch for several writes */
7905 int read_or_write = INTVAL (operands[1]);
7906 int locality = INTVAL (operands[2]);
7908 gcc_assert (read_or_write == 0 || read_or_write == 1);
7909 gcc_assert (locality >= 0 && locality < 4);
7910 return prefetch_instr [read_or_write][locality == 0 ? 0 : 1];
7912 [(set_attr "type" "load")
7913 (set_attr "subtype" "prefetch")])
7916 ;; Trap instructions.
7919 [(trap_if (const_int 1) (const_int 5))]
7922 [(set_attr "type" "trap")])
7924 (define_expand "ctrapsi4"
7925 [(trap_if (match_operator 0 "comparison_operator"
7926 [(match_operand:SI 1 "compare_operand" "")
7927 (match_operand:SI 2 "arith_operand" "")])
7928 (match_operand 3 "arith_operand"))]
7931 operands[1] = gen_compare_reg (operands[0]);
7932 if (GET_MODE (operands[1]) != CCmode && GET_MODE (operands[1]) != CCXmode)
7934 operands[2] = const0_rtx;
7937 (define_expand "ctrapdi4"
7938 [(trap_if (match_operator 0 "comparison_operator"
7939 [(match_operand:DI 1 "compare_operand" "")
7940 (match_operand:DI 2 "arith_operand" "")])
7941 (match_operand 3 "arith_operand"))]
7944 operands[1] = gen_compare_reg (operands[0]);
7945 if (GET_MODE (operands[1]) != CCmode && GET_MODE (operands[1]) != CCXmode)
7947 operands[2] = const0_rtx;
7950 (define_insn "*trapsi_insn"
7951 [(trap_if (match_operator 0 "icc_comparison_operator"
7952 [(reg:CC CC_REG) (const_int 0)])
7953 (match_operand:SI 1 "arith_operand" "rM"))]
7957 return "t%C0\t%%icc, %1";
7961 [(set_attr "type" "trap")])
7963 (define_insn "*trapdi_insn"
7964 [(trap_if (match_operator 0 "icc_comparison_operator"
7965 [(reg:CCX CC_REG) (const_int 0)])
7966 (match_operand:SI 1 "arith_operand" "rM"))]
7969 [(set_attr "type" "trap")])
7972 ;; TLS support instructions.
7974 (define_insn "tgd_hi22"
7975 [(set (match_operand:SI 0 "register_operand" "=r")
7976 (high:SI (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")]
7979 "sethi\\t%%tgd_hi22(%a1), %0")
7981 (define_insn "tgd_lo10"
7982 [(set (match_operand:SI 0 "register_operand" "=r")
7983 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
7984 (unspec:SI [(match_operand 2 "tgd_symbolic_operand" "")]
7987 "add\\t%1, %%tgd_lo10(%a2), %0")
7989 (define_insn "tgd_add32"
7990 [(set (match_operand:SI 0 "register_operand" "=r")
7991 (plus:SI (match_operand:SI 1 "register_operand" "r")
7992 (unspec:SI [(match_operand:SI 2 "register_operand" "r")
7993 (match_operand 3 "tgd_symbolic_operand" "")]
7995 "TARGET_TLS && TARGET_ARCH32"
7996 "add\\t%1, %2, %0, %%tgd_add(%a3)")
7998 (define_insn "tgd_add64"
7999 [(set (match_operand:DI 0 "register_operand" "=r")
8000 (plus:DI (match_operand:DI 1 "register_operand" "r")
8001 (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8002 (match_operand 3 "tgd_symbolic_operand" "")]
8004 "TARGET_TLS && TARGET_ARCH64"
8005 "add\\t%1, %2, %0, %%tgd_add(%a3)")
8007 (define_insn "tgd_call32"
8008 [(set (match_operand 0 "register_operand" "=r")
8009 (call (mem:SI (unspec:SI [(match_operand:SI 1 "symbolic_operand" "s")
8010 (match_operand 2 "tgd_symbolic_operand" "")]
8012 (match_operand 3 "" "")))
8013 (clobber (reg:SI O7_REG))]
8014 "TARGET_TLS && TARGET_ARCH32"
8015 "call\t%a1, %%tgd_call(%a2)%#"
8016 [(set_attr "type" "call")])
8018 (define_insn "tgd_call64"
8019 [(set (match_operand 0 "register_operand" "=r")
8020 (call (mem:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "s")
8021 (match_operand 2 "tgd_symbolic_operand" "")]
8023 (match_operand 3 "" "")))
8024 (clobber (reg:DI O7_REG))]
8025 "TARGET_TLS && TARGET_ARCH64"
8026 "call\t%a1, %%tgd_call(%a2)%#"
8027 [(set_attr "type" "call")])
8029 (define_insn "tldm_hi22"
8030 [(set (match_operand:SI 0 "register_operand" "=r")
8031 (high:SI (unspec:SI [(const_int 0)] UNSPEC_TLSLDM)))]
8033 "sethi\\t%%tldm_hi22(%&), %0")
8035 (define_insn "tldm_lo10"
8036 [(set (match_operand:SI 0 "register_operand" "=r")
8037 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
8038 (unspec:SI [(const_int 0)] UNSPEC_TLSLDM)))]
8040 "add\\t%1, %%tldm_lo10(%&), %0")
8042 (define_insn "tldm_add32"
8043 [(set (match_operand:SI 0 "register_operand" "=r")
8044 (plus:SI (match_operand:SI 1 "register_operand" "r")
8045 (unspec:SI [(match_operand:SI 2 "register_operand" "r")]
8047 "TARGET_TLS && TARGET_ARCH32"
8048 "add\\t%1, %2, %0, %%tldm_add(%&)")
8050 (define_insn "tldm_add64"
8051 [(set (match_operand:DI 0 "register_operand" "=r")
8052 (plus:DI (match_operand:DI 1 "register_operand" "r")
8053 (unspec:DI [(match_operand:SI 2 "register_operand" "r")]
8055 "TARGET_TLS && TARGET_ARCH64"
8056 "add\\t%1, %2, %0, %%tldm_add(%&)")
8058 (define_insn "tldm_call32"
8059 [(set (match_operand 0 "register_operand" "=r")
8060 (call (mem:SI (unspec:SI [(match_operand:SI 1 "symbolic_operand" "s")]
8062 (match_operand 2 "" "")))
8063 (clobber (reg:SI O7_REG))]
8064 "TARGET_TLS && TARGET_ARCH32"
8065 "call\t%a1, %%tldm_call(%&)%#"
8066 [(set_attr "type" "call")])
8068 (define_insn "tldm_call64"
8069 [(set (match_operand 0 "register_operand" "=r")
8070 (call (mem:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "s")]
8072 (match_operand 2 "" "")))
8073 (clobber (reg:DI O7_REG))]
8074 "TARGET_TLS && TARGET_ARCH64"
8075 "call\t%a1, %%tldm_call(%&)%#"
8076 [(set_attr "type" "call")])
8078 (define_insn "tldo_hix22"
8079 [(set (match_operand:SI 0 "register_operand" "=r")
8080 (high:SI (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")]
8083 "sethi\\t%%tldo_hix22(%a1), %0")
8085 (define_insn "tldo_lox10"
8086 [(set (match_operand:SI 0 "register_operand" "=r")
8087 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
8088 (unspec:SI [(match_operand 2 "tld_symbolic_operand" "")]
8091 "xor\\t%1, %%tldo_lox10(%a2), %0")
8093 (define_insn "tldo_add32"
8094 [(set (match_operand:SI 0 "register_operand" "=r")
8095 (plus:SI (match_operand:SI 1 "register_operand" "r")
8096 (unspec:SI [(match_operand:SI 2 "register_operand" "r")
8097 (match_operand 3 "tld_symbolic_operand" "")]
8099 "TARGET_TLS && TARGET_ARCH32"
8100 "add\\t%1, %2, %0, %%tldo_add(%a3)")
8102 (define_insn "tldo_add64"
8103 [(set (match_operand:DI 0 "register_operand" "=r")
8104 (plus:DI (match_operand:DI 1 "register_operand" "r")
8105 (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8106 (match_operand 3 "tld_symbolic_operand" "")]
8108 "TARGET_TLS && TARGET_ARCH64"
8109 "add\\t%1, %2, %0, %%tldo_add(%a3)")
8111 (define_insn "tie_hi22"
8112 [(set (match_operand:SI 0 "register_operand" "=r")
8113 (high:SI (unspec:SI [(match_operand 1 "tie_symbolic_operand" "")]
8116 "sethi\\t%%tie_hi22(%a1), %0")
8118 (define_insn "tie_lo10"
8119 [(set (match_operand:SI 0 "register_operand" "=r")
8120 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
8121 (unspec:SI [(match_operand 2 "tie_symbolic_operand" "")]
8124 "add\\t%1, %%tie_lo10(%a2), %0")
8126 (define_insn "tie_ld32"
8127 [(set (match_operand:SI 0 "register_operand" "=r")
8128 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
8129 (match_operand:SI 2 "register_operand" "r")
8130 (match_operand 3 "tie_symbolic_operand" "")]
8132 "TARGET_TLS && TARGET_ARCH32"
8133 "ld\\t[%1 + %2], %0, %%tie_ld(%a3)"
8134 [(set_attr "type" "load")
8135 (set_attr "subtype" "regular")])
8137 (define_insn "tie_ld64"
8138 [(set (match_operand:DI 0 "register_operand" "=r")
8139 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
8140 (match_operand:SI 2 "register_operand" "r")
8141 (match_operand 3 "tie_symbolic_operand" "")]
8143 "TARGET_TLS && TARGET_ARCH64"
8144 "ldx\\t[%1 + %2], %0, %%tie_ldx(%a3)"
8145 [(set_attr "type" "load")
8146 (set_attr "subtype" "regular")])
8148 (define_insn "tie_add32"
8149 [(set (match_operand:SI 0 "register_operand" "=r")
8150 (plus:SI (match_operand:SI 1 "register_operand" "r")
8151 (unspec:SI [(match_operand:SI 2 "register_operand" "r")
8152 (match_operand 3 "tie_symbolic_operand" "")]
8154 "TARGET_SUN_TLS && TARGET_ARCH32"
8155 "add\\t%1, %2, %0, %%tie_add(%a3)")
8157 (define_insn "tie_add64"
8158 [(set (match_operand:DI 0 "register_operand" "=r")
8159 (plus:DI (match_operand:DI 1 "register_operand" "r")
8160 (unspec:DI [(match_operand:DI 2 "register_operand" "r")
8161 (match_operand 3 "tie_symbolic_operand" "")]
8163 "TARGET_SUN_TLS && TARGET_ARCH64"
8164 "add\\t%1, %2, %0, %%tie_add(%a3)")
8166 (define_insn "tle_hix22_sp32"
8167 [(set (match_operand:SI 0 "register_operand" "=r")
8168 (high:SI (unspec:SI [(match_operand 1 "tle_symbolic_operand" "")]
8170 "TARGET_TLS && TARGET_ARCH32"
8171 "sethi\\t%%tle_hix22(%a1), %0")
8173 (define_insn "tle_lox10_sp32"
8174 [(set (match_operand:SI 0 "register_operand" "=r")
8175 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
8176 (unspec:SI [(match_operand 2 "tle_symbolic_operand" "")]
8178 "TARGET_TLS && TARGET_ARCH32"
8179 "xor\\t%1, %%tle_lox10(%a2), %0")
8181 (define_insn "tle_hix22_sp64"
8182 [(set (match_operand:DI 0 "register_operand" "=r")
8183 (high:DI (unspec:DI [(match_operand 1 "tle_symbolic_operand" "")]
8185 "TARGET_TLS && TARGET_ARCH64"
8186 "sethi\\t%%tle_hix22(%a1), %0")
8188 (define_insn "tle_lox10_sp64"
8189 [(set (match_operand:DI 0 "register_operand" "=r")
8190 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
8191 (unspec:DI [(match_operand 2 "tle_symbolic_operand" "")]
8193 "TARGET_TLS && TARGET_ARCH64"
8194 "xor\\t%1, %%tle_lox10(%a2), %0")
8196 ;; Now patterns combining tldo_add{32,64} with some integer loads or stores
8197 (define_insn "*tldo_ldub_sp32"
8198 [(set (match_operand:QI 0 "register_operand" "=r")
8199 (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
8200 (match_operand 3 "tld_symbolic_operand" "")]
8202 (match_operand:SI 1 "register_operand" "r"))))]
8203 "TARGET_TLS && TARGET_ARCH32"
8204 "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
8205 [(set_attr "type" "load")
8206 (set_attr "subtype" "regular")
8207 (set_attr "us3load_type" "3cycle")])
8209 (define_insn "*tldo_ldub1_sp32"
8210 [(set (match_operand:HI 0 "register_operand" "=r")
8212 (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
8213 (match_operand 3 "tld_symbolic_operand" "")]
8215 (match_operand:SI 1 "register_operand" "r")))))]
8216 "TARGET_TLS && TARGET_ARCH32"
8217 "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
8218 [(set_attr "type" "load")
8219 (set_attr "subtype" "regular")
8220 (set_attr "us3load_type" "3cycle")])
8222 (define_insn "*tldo_ldub2_sp32"
8223 [(set (match_operand:SI 0 "register_operand" "=r")
8225 (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
8226 (match_operand 3 "tld_symbolic_operand" "")]
8228 (match_operand:SI 1 "register_operand" "r")))))]
8229 "TARGET_TLS && TARGET_ARCH32"
8230 "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
8231 [(set_attr "type" "load")
8232 (set_attr "subtype" "regular")
8233 (set_attr "us3load_type" "3cycle")])
8235 (define_insn "*tldo_ldsb1_sp32"
8236 [(set (match_operand:HI 0 "register_operand" "=r")
8238 (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
8239 (match_operand 3 "tld_symbolic_operand" "")]
8241 (match_operand:SI 1 "register_operand" "r")))))]
8242 "TARGET_TLS && TARGET_ARCH32"
8243 "ldsb\t[%1 + %2], %0, %%tldo_add(%3)"
8244 [(set_attr "type" "sload")
8245 (set_attr "us3load_type" "3cycle")])
8247 (define_insn "*tldo_ldsb2_sp32"
8248 [(set (match_operand:SI 0 "register_operand" "=r")
8250 (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
8251 (match_operand 3 "tld_symbolic_operand" "")]
8253 (match_operand:SI 1 "register_operand" "r")))))]
8254 "TARGET_TLS && TARGET_ARCH32"
8255 "ldsb\t[%1 + %2], %0, %%tldo_add(%3)"
8256 [(set_attr "type" "sload")
8257 (set_attr "us3load_type" "3cycle")])
8259 (define_insn "*tldo_ldub_sp64"
8260 [(set (match_operand:QI 0 "register_operand" "=r")
8261 (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8262 (match_operand 3 "tld_symbolic_operand" "")]
8264 (match_operand:DI 1 "register_operand" "r"))))]
8265 "TARGET_TLS && TARGET_ARCH64"
8266 "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
8267 [(set_attr "type" "load")
8268 (set_attr "subtype" "regular")
8269 (set_attr "us3load_type" "3cycle")])
8271 (define_insn "*tldo_ldub1_sp64"
8272 [(set (match_operand:HI 0 "register_operand" "=r")
8274 (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8275 (match_operand 3 "tld_symbolic_operand" "")]
8277 (match_operand:DI 1 "register_operand" "r")))))]
8278 "TARGET_TLS && TARGET_ARCH64"
8279 "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
8280 [(set_attr "type" "load")
8281 (set_attr "subtype" "regular")
8282 (set_attr "us3load_type" "3cycle")])
8284 (define_insn "*tldo_ldub2_sp64"
8285 [(set (match_operand:SI 0 "register_operand" "=r")
8287 (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8288 (match_operand 3 "tld_symbolic_operand" "")]
8290 (match_operand:DI 1 "register_operand" "r")))))]
8291 "TARGET_TLS && TARGET_ARCH64"
8292 "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
8293 [(set_attr "type" "load")
8294 (set_attr "subtype" "regular")
8295 (set_attr "us3load_type" "3cycle")])
8297 (define_insn "*tldo_ldub3_sp64"
8298 [(set (match_operand:DI 0 "register_operand" "=r")
8300 (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8301 (match_operand 3 "tld_symbolic_operand" "")]
8303 (match_operand:DI 1 "register_operand" "r")))))]
8304 "TARGET_TLS && TARGET_ARCH64"
8305 "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
8306 [(set_attr "type" "load")
8307 (set_attr "subtype" "regular")
8308 (set_attr "us3load_type" "3cycle")])
8310 (define_insn "*tldo_ldsb1_sp64"
8311 [(set (match_operand:HI 0 "register_operand" "=r")
8313 (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8314 (match_operand 3 "tld_symbolic_operand" "")]
8316 (match_operand:DI 1 "register_operand" "r")))))]
8317 "TARGET_TLS && TARGET_ARCH64"
8318 "ldsb\t[%1 + %2], %0, %%tldo_add(%3)"
8319 [(set_attr "type" "sload")
8320 (set_attr "us3load_type" "3cycle")])
8322 (define_insn "*tldo_ldsb2_sp64"
8323 [(set (match_operand:SI 0 "register_operand" "=r")
8325 (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8326 (match_operand 3 "tld_symbolic_operand" "")]
8328 (match_operand:DI 1 "register_operand" "r")))))]
8329 "TARGET_TLS && TARGET_ARCH64"
8330 "ldsb\t[%1 + %2], %0, %%tldo_add(%3)"
8331 [(set_attr "type" "sload")
8332 (set_attr "us3load_type" "3cycle")])
8334 (define_insn "*tldo_ldsb3_sp64"
8335 [(set (match_operand:DI 0 "register_operand" "=r")
8337 (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8338 (match_operand 3 "tld_symbolic_operand" "")]
8340 (match_operand:DI 1 "register_operand" "r")))))]
8341 "TARGET_TLS && TARGET_ARCH64"
8342 "ldsb\t[%1 + %2], %0, %%tldo_add(%3)"
8343 [(set_attr "type" "sload")
8344 (set_attr "us3load_type" "3cycle")])
8346 (define_insn "*tldo_lduh_sp32"
8347 [(set (match_operand:HI 0 "register_operand" "=r")
8348 (mem:HI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
8349 (match_operand 3 "tld_symbolic_operand" "")]
8351 (match_operand:SI 1 "register_operand" "r"))))]
8352 "TARGET_TLS && TARGET_ARCH32"
8353 "lduh\t[%1 + %2], %0, %%tldo_add(%3)"
8354 [(set_attr "type" "load")
8355 (set_attr "subtype" "regular")
8356 (set_attr "us3load_type" "3cycle")])
8358 (define_insn "*tldo_lduh1_sp32"
8359 [(set (match_operand:SI 0 "register_operand" "=r")
8361 (mem:HI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
8362 (match_operand 3 "tld_symbolic_operand" "")]
8364 (match_operand:SI 1 "register_operand" "r")))))]
8365 "TARGET_TLS && TARGET_ARCH32"
8366 "lduh\t[%1 + %2], %0, %%tldo_add(%3)"
8367 [(set_attr "type" "load")
8368 (set_attr "subtype" "regular")
8369 (set_attr "us3load_type" "3cycle")])
8371 (define_insn "*tldo_ldsh1_sp32"
8372 [(set (match_operand:SI 0 "register_operand" "=r")
8374 (mem:HI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
8375 (match_operand 3 "tld_symbolic_operand" "")]
8377 (match_operand:SI 1 "register_operand" "r")))))]
8378 "TARGET_TLS && TARGET_ARCH32"
8379 "ldsh\t[%1 + %2], %0, %%tldo_add(%3)"
8380 [(set_attr "type" "sload")
8381 (set_attr "us3load_type" "3cycle")])
8383 (define_insn "*tldo_lduh_sp64"
8384 [(set (match_operand:HI 0 "register_operand" "=r")
8385 (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8386 (match_operand 3 "tld_symbolic_operand" "")]
8388 (match_operand:DI 1 "register_operand" "r"))))]
8389 "TARGET_TLS && TARGET_ARCH64"
8390 "lduh\t[%1 + %2], %0, %%tldo_add(%3)"
8391 [(set_attr "type" "load")
8392 (set_attr "subtype" "regular")
8393 (set_attr "us3load_type" "3cycle")])
8395 (define_insn "*tldo_lduh1_sp64"
8396 [(set (match_operand:SI 0 "register_operand" "=r")
8398 (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8399 (match_operand 3 "tld_symbolic_operand" "")]
8401 (match_operand:DI 1 "register_operand" "r")))))]
8402 "TARGET_TLS && TARGET_ARCH64"
8403 "lduh\t[%1 + %2], %0, %%tldo_add(%3)"
8404 [(set_attr "type" "load")
8405 (set_attr "subtype" "regular")
8406 (set_attr "us3load_type" "3cycle")])
8408 (define_insn "*tldo_lduh2_sp64"
8409 [(set (match_operand:DI 0 "register_operand" "=r")
8411 (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8412 (match_operand 3 "tld_symbolic_operand" "")]
8414 (match_operand:DI 1 "register_operand" "r")))))]
8415 "TARGET_TLS && TARGET_ARCH64"
8416 "lduh\t[%1 + %2], %0, %%tldo_add(%3)"
8417 [(set_attr "type" "load")
8418 (set_attr "subtype" "regular")
8419 (set_attr "us3load_type" "3cycle")])
8421 (define_insn "*tldo_ldsh1_sp64"
8422 [(set (match_operand:SI 0 "register_operand" "=r")
8424 (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8425 (match_operand 3 "tld_symbolic_operand" "")]
8427 (match_operand:DI 1 "register_operand" "r")))))]
8428 "TARGET_TLS && TARGET_ARCH64"
8429 "ldsh\t[%1 + %2], %0, %%tldo_add(%3)"
8430 [(set_attr "type" "sload")
8431 (set_attr "us3load_type" "3cycle")])
8433 (define_insn "*tldo_ldsh2_sp64"
8434 [(set (match_operand:DI 0 "register_operand" "=r")
8436 (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8437 (match_operand 3 "tld_symbolic_operand" "")]
8439 (match_operand:DI 1 "register_operand" "r")))))]
8440 "TARGET_TLS && TARGET_ARCH64"
8441 "ldsh\t[%1 + %2], %0, %%tldo_add(%3)"
8442 [(set_attr "type" "sload")
8443 (set_attr "us3load_type" "3cycle")])
8445 (define_insn "*tldo_lduw_sp32"
8446 [(set (match_operand:SI 0 "register_operand" "=r")
8447 (mem:SI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
8448 (match_operand 3 "tld_symbolic_operand" "")]
8450 (match_operand:SI 1 "register_operand" "r"))))]
8451 "TARGET_TLS && TARGET_ARCH32"
8452 "ld\t[%1 + %2], %0, %%tldo_add(%3)"
8453 [(set_attr "type" "load")
8454 (set_attr "subtype" "regular")])
8456 (define_insn "*tldo_lduw_sp64"
8457 [(set (match_operand:SI 0 "register_operand" "=r")
8458 (mem:SI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8459 (match_operand 3 "tld_symbolic_operand" "")]
8461 (match_operand:DI 1 "register_operand" "r"))))]
8462 "TARGET_TLS && TARGET_ARCH64"
8463 "lduw\t[%1 + %2], %0, %%tldo_add(%3)"
8464 [(set_attr "type" "load")
8465 (set_attr "subtype" "regular")])
8467 (define_insn "*tldo_lduw1_sp64"
8468 [(set (match_operand:DI 0 "register_operand" "=r")
8470 (mem:SI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8471 (match_operand 3 "tld_symbolic_operand" "")]
8473 (match_operand:DI 1 "register_operand" "r")))))]
8474 "TARGET_TLS && TARGET_ARCH64"
8475 "lduw\t[%1 + %2], %0, %%tldo_add(%3)"
8476 [(set_attr "type" "load")
8477 (set_attr "subtype" "regular")])
8479 (define_insn "*tldo_ldsw1_sp64"
8480 [(set (match_operand:DI 0 "register_operand" "=r")
8482 (mem:SI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8483 (match_operand 3 "tld_symbolic_operand" "")]
8485 (match_operand:DI 1 "register_operand" "r")))))]
8486 "TARGET_TLS && TARGET_ARCH64"
8487 "ldsw\t[%1 + %2], %0, %%tldo_add(%3)"
8488 [(set_attr "type" "sload")
8489 (set_attr "us3load_type" "3cycle")])
8491 (define_insn "*tldo_ldx_sp64"
8492 [(set (match_operand:DI 0 "register_operand" "=r")
8493 (mem:DI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8494 (match_operand 3 "tld_symbolic_operand" "")]
8496 (match_operand:DI 1 "register_operand" "r"))))]
8497 "TARGET_TLS && TARGET_ARCH64"
8498 "ldx\t[%1 + %2], %0, %%tldo_add(%3)"
8499 [(set_attr "type" "load")
8500 (set_attr "subtype" "regular")])
8502 (define_insn "*tldo_stb_sp32"
8503 [(set (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
8504 (match_operand 3 "tld_symbolic_operand" "")]
8506 (match_operand:SI 1 "register_operand" "r")))
8507 (match_operand:QI 0 "register_operand" "r"))]
8508 "TARGET_TLS && TARGET_ARCH32"
8509 "stb\t%0, [%1 + %2], %%tldo_add(%3)"
8510 [(set_attr "type" "store")])
8512 (define_insn "*tldo_stb_sp64"
8513 [(set (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8514 (match_operand 3 "tld_symbolic_operand" "")]
8516 (match_operand:DI 1 "register_operand" "r")))
8517 (match_operand:QI 0 "register_operand" "r"))]
8518 "TARGET_TLS && TARGET_ARCH64"
8519 "stb\t%0, [%1 + %2], %%tldo_add(%3)"
8520 [(set_attr "type" "store")])
8522 (define_insn "*tldo_sth_sp32"
8523 [(set (mem:HI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
8524 (match_operand 3 "tld_symbolic_operand" "")]
8526 (match_operand:SI 1 "register_operand" "r")))
8527 (match_operand:HI 0 "register_operand" "r"))]
8528 "TARGET_TLS && TARGET_ARCH32"
8529 "sth\t%0, [%1 + %2], %%tldo_add(%3)"
8530 [(set_attr "type" "store")])
8532 (define_insn "*tldo_sth_sp64"
8533 [(set (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8534 (match_operand 3 "tld_symbolic_operand" "")]
8536 (match_operand:DI 1 "register_operand" "r")))
8537 (match_operand:HI 0 "register_operand" "r"))]
8538 "TARGET_TLS && TARGET_ARCH64"
8539 "sth\t%0, [%1 + %2], %%tldo_add(%3)"
8540 [(set_attr "type" "store")])
8542 (define_insn "*tldo_stw_sp32"
8543 [(set (mem:SI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
8544 (match_operand 3 "tld_symbolic_operand" "")]
8546 (match_operand:SI 1 "register_operand" "r")))
8547 (match_operand:SI 0 "register_operand" "r"))]
8548 "TARGET_TLS && TARGET_ARCH32"
8549 "st\t%0, [%1 + %2], %%tldo_add(%3)"
8550 [(set_attr "type" "store")])
8552 (define_insn "*tldo_stw_sp64"
8553 [(set (mem:SI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8554 (match_operand 3 "tld_symbolic_operand" "")]
8556 (match_operand:DI 1 "register_operand" "r")))
8557 (match_operand:SI 0 "register_operand" "r"))]
8558 "TARGET_TLS && TARGET_ARCH64"
8559 "stw\t%0, [%1 + %2], %%tldo_add(%3)"
8560 [(set_attr "type" "store")])
8562 (define_insn "*tldo_stx_sp64"
8563 [(set (mem:DI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
8564 (match_operand 3 "tld_symbolic_operand" "")]
8566 (match_operand:DI 1 "register_operand" "r")))
8567 (match_operand:DI 0 "register_operand" "r"))]
8568 "TARGET_TLS && TARGET_ARCH64"
8569 "stx\t%0, [%1 + %2], %%tldo_add(%3)"
8570 [(set_attr "type" "store")])
8573 ;; Stack protector instructions.
8575 (define_expand "stack_protect_set"
8576 [(match_operand 0 "memory_operand" "")
8577 (match_operand 1 "memory_operand" "")]
8580 #ifdef TARGET_THREAD_SSP_OFFSET
8581 rtx tlsreg = gen_rtx_REG (Pmode, 7);
8582 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
8583 operands[1] = gen_rtx_MEM (Pmode, addr);
8586 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
8588 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
8592 (define_insn "stack_protect_setsi"
8593 [(set (match_operand:SI 0 "memory_operand" "=m")
8594 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
8595 (set (match_scratch:SI 2 "=&r") (const_int 0))]
8597 "ld\t%1, %2\;st\t%2, %0\;mov\t0, %2"
8598 [(set_attr "type" "multi")
8599 (set_attr "length" "3")])
8601 (define_insn "stack_protect_setdi"
8602 [(set (match_operand:DI 0 "memory_operand" "=m")
8603 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
8604 (set (match_scratch:DI 2 "=&r") (const_int 0))]
8606 "ldx\t%1, %2\;stx\t%2, %0\;mov\t0, %2"
8607 [(set_attr "type" "multi")
8608 (set_attr "length" "3")])
8610 (define_expand "stack_protect_test"
8611 [(match_operand 0 "memory_operand" "")
8612 (match_operand 1 "memory_operand" "")
8613 (match_operand 2 "" "")]
8617 #ifdef TARGET_THREAD_SSP_OFFSET
8618 rtx tlsreg = gen_rtx_REG (Pmode, 7);
8619 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
8620 operands[1] = gen_rtx_MEM (Pmode, addr);
8624 result = gen_reg_rtx (Pmode);
8625 emit_insn (gen_stack_protect_testdi (result, operands[0], operands[1]));
8626 test = gen_rtx_EQ (VOIDmode, result, const0_rtx);
8627 emit_jump_insn (gen_cbranchdi4 (test, result, const0_rtx, operands[2]));
8631 emit_insn (gen_stack_protect_testsi (operands[0], operands[1]));
8632 result = gen_rtx_REG (CCmode, SPARC_ICC_REG);
8633 test = gen_rtx_EQ (VOIDmode, result, const0_rtx);
8634 emit_jump_insn (gen_cbranchcc4 (test, result, const0_rtx, operands[2]));
8639 (define_insn "stack_protect_testsi"
8640 [(set (reg:CC CC_REG)
8641 (unspec:CC [(match_operand:SI 0 "memory_operand" "m")
8642 (match_operand:SI 1 "memory_operand" "m")]
8644 (set (match_scratch:SI 3 "=r") (const_int 0))
8645 (clobber (match_scratch:SI 2 "=&r"))]
8647 "ld\t%0, %2\;ld\t%1, %3\;xorcc\t%2, %3, %2\;mov\t0, %3"
8648 [(set_attr "type" "multi")
8649 (set_attr "length" "4")])
8651 (define_insn "stack_protect_testdi"
8652 [(set (match_operand:DI 0 "register_operand" "=&r")
8653 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
8654 (match_operand:DI 2 "memory_operand" "m")]
8656 (set (match_scratch:DI 3 "=r") (const_int 0))]
8658 "ldx\t%1, %0\;ldx\t%2, %3\;xor\t%0, %3, %0\;mov\t0, %3"
8659 [(set_attr "type" "multi")
8660 (set_attr "length" "4")])
8663 ;; Vector instructions.
8665 (define_mode_iterator VM32 [V1SI V2HI V4QI])
8666 (define_mode_iterator VM64 [V1DI V2SI V4HI V8QI])
8667 (define_mode_iterator VMALL [V1SI V2HI V4QI V1DI V2SI V4HI V8QI])
8669 (define_mode_attr vbits [(V2SI "32") (V4HI "16") (V1SI "32s") (V2HI "16s")
8671 (define_mode_attr vconstr [(V1SI "f") (V2HI "f") (V4QI "f")
8672 (V1DI "e") (V2SI "e") (V4HI "e") (V8QI "e")])
8673 (define_mode_attr vfptype [(V1SI "single") (V2HI "single") (V4QI "single")
8674 (V1DI "double") (V2SI "double") (V4HI "double")
8676 (define_mode_attr veltmode [(V1SI "si") (V2HI "hi") (V4QI "qi") (V1DI "di")
8677 (V2SI "si") (V4HI "hi") (V8QI "qi")])
8679 (define_expand "mov<VMALL:mode>"
8680 [(set (match_operand:VMALL 0 "nonimmediate_operand" "")
8681 (match_operand:VMALL 1 "general_operand" ""))]
8684 if (sparc_expand_move (<VMALL:MODE>mode, operands))
8688 (define_insn "*mov<VM32:mode>_insn"
8689 [(set (match_operand:VM32 0 "nonimmediate_operand" "=f,f,f,f,m,m,*r, m,*r,*r, f")
8690 (match_operand:VM32 1 "input_operand" "Y,Z,f,m,f,Y, m,*r,*r, f,*r"))]
8692 && (register_operand (operands[0], <VM32:MODE>mode)
8693 || register_or_zero_or_all_ones_operand (operands[1], <VM32:MODE>mode))"
8706 [(set_attr "type" "visl,visl,vismv,fpload,fpstore,store,load,store,*,vismv,vismv")
8707 (set_attr "subtype" "single,single,single,*,*,*,regular,*,*,movstouw,single")
8708 (set_attr "cpu_feature" "vis,vis,vis,*,*,*,*,*,*,vis3,vis3")])
8710 (define_insn "*mov<VM64:mode>_insn_sp64"
8711 [(set (match_operand:VM64 0 "nonimmediate_operand" "=e,e,e,e,W,m,*r, m,*r, e,*r")
8712 (match_operand:VM64 1 "input_operand" "Y,Z,e,W,e,Y, m,*r, e,*r,*r"))]
8715 && (register_operand (operands[0], <VM64:MODE>mode)
8716 || register_or_zero_or_all_ones_operand (operands[1], <VM64:MODE>mode))"
8729 [(set_attr "type" "visl,visl,vismv,fpload,fpstore,store,load,store,vismv,vismv,*")
8730 (set_attr "subtype" "double,double,double,*,*,*,regular,*,movdtox,movxtod,*")
8731 (set_attr "cpu_feature" "vis,vis,vis,*,*,*,*,*,vis3,vis3,*")])
8733 (define_insn "*mov<VM64:mode>_insn_sp32"
8734 [(set (match_operand:VM64 0 "nonimmediate_operand"
8735 "=T,o,e,e,e,*r, f,e,T,U,T,f,o,*r,*r, o")
8736 (match_operand:VM64 1 "input_operand"
8737 " Y,Y,Y,Z,e, f,*r,T,e,T,U,o,f,*r, o,*r"))]
8740 && (register_operand (operands[0], <VM64:MODE>mode)
8741 || register_or_zero_or_all_ones_operand (operands[1], <VM64:MODE>mode))"
8759 [(set_attr "type" "store,*,visl,visl,vismv,*,*,fpload,fpstore,load,store,*,*,*,load,store")
8760 (set_attr "subtype" "*,*,double,double,double,*,*,*,*,regular,*,*,*,*,regular,*")
8761 (set_attr "length" "*,2,*,*,*,2,2,*,*,*,*,2,2,2,*,*")
8762 (set_attr "cpu_feature" "*,*,vis,vis,vis,vis3,vis3,*,*,*,*,*,*,*,*,*")
8763 (set_attr "lra" "*,*,*,*,*,*,*,*,*,disabled,disabled,*,*,*,*,*")])
8766 [(set (match_operand:VM64 0 "register_operand" "")
8767 (match_operand:VM64 1 "register_operand" ""))]
8771 && sparc_split_reg_reg_legitimate (operands[0], operands[1])"
8772 [(clobber (const_int 0))]
8774 sparc_split_reg_reg (operands[0], operands[1], SImode);
8779 [(set (match_operand:VM64 0 "register_operand" "")
8780 (match_operand:VM64 1 "memory_operand" ""))]
8784 && sparc_split_reg_mem_legitimate (operands[0], operands[1])"
8785 [(clobber (const_int 0))]
8787 sparc_split_reg_mem (operands[0], operands[1], SImode);
8792 [(set (match_operand:VM64 0 "memory_operand" "")
8793 (match_operand:VM64 1 "register_operand" ""))]
8797 && sparc_split_reg_mem_legitimate (operands[1], operands[0])"
8798 [(clobber (const_int 0))]
8800 sparc_split_mem_reg (operands[0], operands[1], SImode);
8805 [(set (match_operand:VM64 0 "memory_operand" "")
8806 (match_operand:VM64 1 "const_zero_operand" ""))]
8810 && !mem_min_alignment (operands[0], 8)
8811 && offsettable_memref_p (operands[0])"
8812 [(clobber (const_int 0))]
8814 emit_move_insn_1 (adjust_address (operands[0], SImode, 0), const0_rtx);
8815 emit_move_insn_1 (adjust_address (operands[0], SImode, 4), const0_rtx);
8819 (define_expand "vec_init<VMALL:mode><VMALL:veltmode>"
8820 [(match_operand:VMALL 0 "register_operand" "")
8821 (match_operand:VMALL 1 "" "")]
8824 sparc_expand_vector_init (operands[0], operands[1]);
8828 (define_code_iterator plusminus [plus minus])
8829 (define_code_attr plusminus_insn [(plus "add") (minus "sub")])
8831 (define_mode_iterator VADDSUB [V1SI V2SI V2HI V4HI])
8833 (define_insn "<plusminus_insn><VADDSUB:mode>3"
8834 [(set (match_operand:VADDSUB 0 "register_operand" "=<vconstr>")
8835 (plusminus:VADDSUB (match_operand:VADDSUB 1 "register_operand" "<vconstr>")
8836 (match_operand:VADDSUB 2 "register_operand" "<vconstr>")))]
8838 "fp<plusminus_insn><vbits>\t%1, %2, %0"
8839 [(set_attr "type" "fga")
8840 (set_attr "subtype" "other")
8841 (set_attr "fptype" "<vfptype>")])
8843 (define_mode_iterator VL [V1SI V2HI V4QI V1DI V2SI V4HI V8QI])
8844 (define_mode_attr vlsuf [(V1SI "s") (V2HI "s") (V4QI "s")
8845 (V1DI "") (V2SI "") (V4HI "") (V8QI "")])
8846 (define_code_iterator vlop [ior and xor])
8847 (define_code_attr vlinsn [(ior "or") (and "and") (xor "xor")])
8848 (define_code_attr vlninsn [(ior "nor") (and "nand") (xor "xnor")])
8850 (define_insn "<vlop:code><VL:mode>3"
8851 [(set (match_operand:VL 0 "register_operand" "=<vconstr>")
8852 (vlop:VL (match_operand:VL 1 "register_operand" "<vconstr>")
8853 (match_operand:VL 2 "register_operand" "<vconstr>")))]
8855 "f<vlinsn><vlsuf>\t%1, %2, %0"
8856 [(set_attr "type" "visl")
8857 (set_attr "fptype" "<vfptype>")])
8859 (define_insn "*not_<vlop:code><VL:mode>3"
8860 [(set (match_operand:VL 0 "register_operand" "=<vconstr>")
8861 (not:VL (vlop:VL (match_operand:VL 1 "register_operand" "<vconstr>")
8862 (match_operand:VL 2 "register_operand" "<vconstr>"))))]
8864 "f<vlninsn><vlsuf>\t%1, %2, %0"
8865 [(set_attr "type" "visl")
8866 (set_attr "fptype" "<vfptype>")])
8868 ;; (ior (not (op1)) (not (op2))) is the canonical form of NAND.
8869 (define_insn "*nand<VL:mode>_vis"
8870 [(set (match_operand:VL 0 "register_operand" "=<vconstr>")
8871 (ior:VL (not:VL (match_operand:VL 1 "register_operand" "<vconstr>"))
8872 (not:VL (match_operand:VL 2 "register_operand" "<vconstr>"))))]
8874 "fnand<vlsuf>\t%1, %2, %0"
8875 [(set_attr "type" "visl")
8876 (set_attr "fptype" "<vfptype>")])
8878 (define_code_iterator vlnotop [ior and])
8880 (define_insn "*<vlnotop:code>_not1<VL:mode>_vis"
8881 [(set (match_operand:VL 0 "register_operand" "=<vconstr>")
8882 (vlnotop:VL (not:VL (match_operand:VL 1 "register_operand" "<vconstr>"))
8883 (match_operand:VL 2 "register_operand" "<vconstr>")))]
8885 "f<vlinsn>not1<vlsuf>\t%1, %2, %0"
8886 [(set_attr "type" "visl")
8887 (set_attr "fptype" "<vfptype>")])
8889 (define_insn "*<vlnotop:code>_not2<VL:mode>_vis"
8890 [(set (match_operand:VL 0 "register_operand" "=<vconstr>")
8891 (vlnotop:VL (match_operand:VL 1 "register_operand" "<vconstr>")
8892 (not:VL (match_operand:VL 2 "register_operand" "<vconstr>"))))]
8894 "f<vlinsn>not2<vlsuf>\t%1, %2, %0"
8895 [(set_attr "type" "visl")
8896 (set_attr "fptype" "<vfptype>")])
8898 (define_insn "one_cmpl<VL:mode>2"
8899 [(set (match_operand:VL 0 "register_operand" "=<vconstr>")
8900 (not:VL (match_operand:VL 1 "register_operand" "<vconstr>")))]
8902 "fnot1<vlsuf>\t%1, %0"
8903 [(set_attr "type" "visl")
8904 (set_attr "fptype" "<vfptype>")])
8906 ;; Hard to generate VIS instructions. We have builtins for these.
8908 (define_insn "fpack16_vis"
8909 [(set (match_operand:V4QI 0 "register_operand" "=f")
8910 (unspec:V4QI [(match_operand:V4HI 1 "register_operand" "e")
8915 [(set_attr "type" "fgm_pack")
8916 (set_attr "fptype" "double")])
8918 (define_insn "fpackfix_vis"
8919 [(set (match_operand:V2HI 0 "register_operand" "=f")
8920 (unspec:V2HI [(match_operand:V2SI 1 "register_operand" "e")
8925 [(set_attr "type" "fgm_pack")
8926 (set_attr "fptype" "double")])
8928 (define_insn "fpack32_vis"
8929 [(set (match_operand:V8QI 0 "register_operand" "=e")
8930 (unspec:V8QI [(match_operand:V2SI 1 "register_operand" "e")
8931 (match_operand:V8QI 2 "register_operand" "e")
8935 "fpack32\t%1, %2, %0"
8936 [(set_attr "type" "fgm_pack")
8937 (set_attr "fptype" "double")])
8939 (define_insn "fexpand_vis"
8940 [(set (match_operand:V4HI 0 "register_operand" "=e")
8941 (unspec:V4HI [(match_operand:V4QI 1 "register_operand" "f")]
8945 [(set_attr "type" "fga")
8946 (set_attr "subtype" "fpu")
8947 (set_attr "fptype" "double")])
8949 (define_insn "fpmerge_vis"
8950 [(set (match_operand:V8QI 0 "register_operand" "=e")
8952 (vec_concat:V8QI (match_operand:V4QI 1 "register_operand" "f")
8953 (match_operand:V4QI 2 "register_operand" "f"))
8954 (parallel [(const_int 0) (const_int 4)
8955 (const_int 1) (const_int 5)
8956 (const_int 2) (const_int 6)
8957 (const_int 3) (const_int 7)])))]
8959 "fpmerge\t%1, %2, %0"
8960 [(set_attr "type" "fga")
8961 (set_attr "subtype" "fpu")
8962 (set_attr "fptype" "double")])
8964 ;; Partitioned multiply instructions
8965 (define_insn "fmul8x16_vis"
8966 [(set (match_operand:V4HI 0 "register_operand" "=e")
8967 (unspec:V4HI [(match_operand:V4QI 1 "register_operand" "f")
8968 (match_operand:V4HI 2 "register_operand" "e")]
8971 "fmul8x16\t%1, %2, %0"
8972 [(set_attr "type" "fgm_mul")
8973 (set_attr "fptype" "double")])
8975 (define_insn "fmul8x16au_vis"
8976 [(set (match_operand:V4HI 0 "register_operand" "=e")
8977 (unspec:V4HI [(match_operand:V4QI 1 "register_operand" "f")
8978 (match_operand:V2HI 2 "register_operand" "f")]
8981 "fmul8x16au\t%1, %2, %0"
8982 [(set_attr "type" "fgm_mul")
8983 (set_attr "fptype" "double")])
8985 (define_insn "fmul8x16al_vis"
8986 [(set (match_operand:V4HI 0 "register_operand" "=e")
8987 (unspec:V4HI [(match_operand:V4QI 1 "register_operand" "f")
8988 (match_operand:V2HI 2 "register_operand" "f")]
8991 "fmul8x16al\t%1, %2, %0"
8992 [(set_attr "type" "fgm_mul")
8993 (set_attr "fptype" "double")])
8995 (define_insn "fmul8sux16_vis"
8996 [(set (match_operand:V4HI 0 "register_operand" "=e")
8997 (unspec:V4HI [(match_operand:V8QI 1 "register_operand" "e")
8998 (match_operand:V4HI 2 "register_operand" "e")]
9001 "fmul8sux16\t%1, %2, %0"
9002 [(set_attr "type" "fgm_mul")
9003 (set_attr "fptype" "double")])
9005 (define_insn "fmul8ulx16_vis"
9006 [(set (match_operand:V4HI 0 "register_operand" "=e")
9007 (unspec:V4HI [(match_operand:V8QI 1 "register_operand" "e")
9008 (match_operand:V4HI 2 "register_operand" "e")]
9011 "fmul8ulx16\t%1, %2, %0"
9012 [(set_attr "type" "fgm_mul")
9013 (set_attr "fptype" "double")])
9015 (define_insn "fmuld8sux16_vis"
9016 [(set (match_operand:V2SI 0 "register_operand" "=e")
9017 (unspec:V2SI [(match_operand:V4QI 1 "register_operand" "f")
9018 (match_operand:V2HI 2 "register_operand" "f")]
9021 "fmuld8sux16\t%1, %2, %0"
9022 [(set_attr "type" "fgm_mul")
9023 (set_attr "fptype" "double")])
9025 (define_insn "fmuld8ulx16_vis"
9026 [(set (match_operand:V2SI 0 "register_operand" "=e")
9027 (unspec:V2SI [(match_operand:V4QI 1 "register_operand" "f")
9028 (match_operand:V2HI 2 "register_operand" "f")]
9031 "fmuld8ulx16\t%1, %2, %0"
9032 [(set_attr "type" "fgm_mul")
9033 (set_attr "fptype" "double")])
9035 (define_expand "wrgsr_vis"
9036 [(set (reg:DI GSR_REG) (match_operand:DI 0 "arith_operand" ""))]
9041 emit_insn (gen_wrgsr_v8plus (operands[0]));
9046 (define_insn "*wrgsr_sp64"
9047 [(set (reg:DI GSR_REG) (match_operand:DI 0 "arith_operand" "rI"))]
9048 "TARGET_VIS && TARGET_ARCH64"
9049 "wr\t%%g0, %0, %%gsr"
9050 [(set_attr "type" "gsr")
9051 (set_attr "subtype" "reg")])
9053 (define_insn "wrgsr_v8plus"
9054 [(set (reg:DI GSR_REG) (match_operand:DI 0 "arith_operand" "I,r"))
9055 (clobber (match_scratch:SI 1 "=X,&h"))]
9056 "TARGET_VIS && TARGET_ARCH32"
9058 if (GET_CODE (operands[0]) == CONST_INT
9059 || sparc_check_64 (operands[0], insn))
9060 return "wr\t%%g0, %0, %%gsr";
9062 output_asm_insn("srl\t%L0, 0, %L0", operands);
9063 return "sllx\t%H0, 32, %1\n\tor\t%L0, %1, %1\n\twr\t%%g0, %1, %%gsr";
9065 [(set_attr "type" "multi")])
9067 (define_expand "rdgsr_vis"
9068 [(set (match_operand:DI 0 "register_operand" "") (reg:DI GSR_REG))]
9073 emit_insn (gen_rdgsr_v8plus (operands[0]));
9078 (define_insn "*rdgsr_sp64"
9079 [(set (match_operand:DI 0 "register_operand" "=r") (reg:DI GSR_REG))]
9080 "TARGET_VIS && TARGET_ARCH64"
9082 [(set_attr "type" "gsr")
9083 (set_attr "subtype" "reg")])
9085 (define_insn "rdgsr_v8plus"
9086 [(set (match_operand:DI 0 "register_operand" "=r") (reg:DI GSR_REG))
9087 (clobber (match_scratch:SI 1 "=&h"))]
9088 "TARGET_VIS && TARGET_ARCH32"
9090 return "rd\t%%gsr, %1\n\tsrlx\t%1, 32, %H0\n\tmov %1, %L0";
9092 [(set_attr "type" "multi")])
9094 ;; Using faligndata only makes sense after an alignaddr since the choice of
9095 ;; bytes to take out of each operand is dependent on the results of the last
9097 (define_insn "faligndata<VM64:mode>_vis"
9098 [(set (match_operand:VM64 0 "register_operand" "=e")
9099 (unspec:VM64 [(match_operand:VM64 1 "register_operand" "e")
9100 (match_operand:VM64 2 "register_operand" "e")
9104 "faligndata\t%1, %2, %0"
9105 [(set_attr "type" "fga")
9106 (set_attr "subtype" "other")
9107 (set_attr "fptype" "double")])
9109 (define_insn "alignaddrsi_vis"
9110 [(set (match_operand:SI 0 "register_operand" "=r")
9111 (plus:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
9112 (match_operand:SI 2 "register_or_zero_operand" "rJ")))
9113 (set (zero_extract:DI (reg:DI GSR_REG) (const_int 3) (const_int 0))
9114 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
9116 "alignaddr\t%r1, %r2, %0"
9117 [(set_attr "type" "gsr")
9118 (set_attr "subtype" "alignaddr")])
9120 (define_insn "alignaddrdi_vis"
9121 [(set (match_operand:DI 0 "register_operand" "=r")
9122 (plus:DI (match_operand:DI 1 "register_or_zero_operand" "rJ")
9123 (match_operand:DI 2 "register_or_zero_operand" "rJ")))
9124 (set (zero_extract:DI (reg:DI GSR_REG) (const_int 3) (const_int 0))
9125 (plus:DI (match_dup 1) (match_dup 2)))]
9127 "alignaddr\t%r1, %r2, %0"
9128 [(set_attr "type" "gsr")
9129 (set_attr "subtype" "alignaddr")])
9131 (define_insn "alignaddrlsi_vis"
9132 [(set (match_operand:SI 0 "register_operand" "=r")
9133 (plus:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
9134 (match_operand:SI 2 "register_or_zero_operand" "rJ")))
9135 (set (zero_extract:DI (reg:DI GSR_REG) (const_int 3) (const_int 0))
9136 (xor:DI (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2)))
9139 "alignaddrl\t%r1, %r2, %0"
9140 [(set_attr "type" "gsr")
9141 (set_attr "subtype" "alignaddr")])
9143 (define_insn "alignaddrldi_vis"
9144 [(set (match_operand:DI 0 "register_operand" "=r")
9145 (plus:DI (match_operand:DI 1 "register_or_zero_operand" "rJ")
9146 (match_operand:DI 2 "register_or_zero_operand" "rJ")))
9147 (set (zero_extract:DI (reg:DI GSR_REG) (const_int 3) (const_int 0))
9148 (xor:DI (plus:DI (match_dup 1) (match_dup 2))
9151 "alignaddrl\t%r1, %r2, %0"
9152 [(set_attr "type" "gsr")
9153 (set_attr "subtype" "alignaddr")])
9155 (define_insn "pdist_vis"
9156 [(set (match_operand:DI 0 "register_operand" "=e")
9157 (unspec:DI [(match_operand:V8QI 1 "register_operand" "e")
9158 (match_operand:V8QI 2 "register_operand" "e")
9159 (match_operand:DI 3 "register_operand" "0")]
9163 [(set_attr "type" "pdist")
9164 (set_attr "fptype" "double")])
9166 ;; Edge instructions produce condition codes equivalent to a 'subcc'
9167 ;; with the same operands.
9168 (define_insn "edge8<P:mode>_vis"
9169 [(set (reg:CCNZ CC_REG)
9170 (compare:CCNZ (minus:P (match_operand:P 1 "register_or_zero_operand" "rJ")
9171 (match_operand:P 2 "register_or_zero_operand" "rJ"))
9173 (set (match_operand:P 0 "register_operand" "=r")
9174 (unspec:P [(match_dup 1) (match_dup 2)] UNSPEC_EDGE8))]
9176 "edge8\t%r1, %r2, %0"
9177 [(set_attr "type" "edge")])
9179 (define_insn "edge8l<P:mode>_vis"
9180 [(set (reg:CCNZ CC_REG)
9181 (compare:CCNZ (minus:P (match_operand:P 1 "register_or_zero_operand" "rJ")
9182 (match_operand:P 2 "register_or_zero_operand" "rJ"))
9184 (set (match_operand:P 0 "register_operand" "=r")
9185 (unspec:P [(match_dup 1) (match_dup 2)] UNSPEC_EDGE8L))]
9187 "edge8l\t%r1, %r2, %0"
9188 [(set_attr "type" "edge")])
9190 (define_insn "edge16<P:mode>_vis"
9191 [(set (reg:CCNZ CC_REG)
9192 (compare:CCNZ (minus:P (match_operand:P 1 "register_or_zero_operand" "rJ")
9193 (match_operand:P 2 "register_or_zero_operand" "rJ"))
9195 (set (match_operand:P 0 "register_operand" "=r")
9196 (unspec:P [(match_dup 1) (match_dup 2)] UNSPEC_EDGE16))]
9198 "edge16\t%r1, %r2, %0"
9199 [(set_attr "type" "edge")])
9201 (define_insn "edge16l<P:mode>_vis"
9202 [(set (reg:CCNZ CC_REG)
9203 (compare:CCNZ (minus:P (match_operand:P 1 "register_or_zero_operand" "rJ")
9204 (match_operand:P 2 "register_or_zero_operand" "rJ"))
9206 (set (match_operand:P 0 "register_operand" "=r")
9207 (unspec:P [(match_dup 1) (match_dup 2)] UNSPEC_EDGE16L))]
9209 "edge16l\t%r1, %r2, %0"
9210 [(set_attr "type" "edge")])
9212 (define_insn "edge32<P:mode>_vis"
9213 [(set (reg:CCNZ CC_REG)
9214 (compare:CCNZ (minus:P (match_operand:P 1 "register_or_zero_operand" "rJ")
9215 (match_operand:P 2 "register_or_zero_operand" "rJ"))
9217 (set (match_operand:P 0 "register_operand" "=r")
9218 (unspec:P [(match_dup 1) (match_dup 2)] UNSPEC_EDGE32))]
9220 "edge32\t%r1, %r2, %0"
9221 [(set_attr "type" "edge")])
9223 (define_insn "edge32l<P:mode>_vis"
9224 [(set (reg:CCNZ CC_REG)
9225 (compare:CCNZ (minus:P (match_operand:P 1 "register_or_zero_operand" "rJ")
9226 (match_operand:P 2 "register_or_zero_operand" "rJ"))
9228 (set (match_operand:P 0 "register_operand" "=r")
9229 (unspec:P [(match_dup 1) (match_dup 2)] UNSPEC_EDGE32L))]
9231 "edge32l\t%r1, %r2, %0"
9232 [(set_attr "type" "edge")])
9234 (define_code_iterator gcond [le ne gt eq])
9235 (define_mode_iterator GCM [V4HI V2SI])
9236 (define_mode_attr gcm_name [(V4HI "16") (V2SI "32")])
9238 (define_insn "fcmp<gcond:code><GCM:gcm_name><P:mode>_vis"
9239 [(set (match_operand:P 0 "register_operand" "=r")
9240 (unspec:P [(gcond:GCM (match_operand:GCM 1 "register_operand" "e")
9241 (match_operand:GCM 2 "register_operand" "e"))]
9244 "fcmp<gcond:code><GCM:gcm_name>\t%1, %2, %0"
9245 [(set_attr "type" "viscmp")])
9247 (define_insn "fpcmp<gcond:code>8<P:mode>_vis"
9248 [(set (match_operand:P 0 "register_operand" "=r")
9249 (unspec:P [(gcond:V8QI (match_operand:V8QI 1 "register_operand" "e")
9250 (match_operand:V8QI 2 "register_operand" "e"))]
9253 "fpcmp<gcond:code>8\t%1, %2, %0"
9254 [(set_attr "type" "viscmp")])
9256 (define_expand "vcond<GCM:mode><GCM:mode>"
9257 [(match_operand:GCM 0 "register_operand" "")
9258 (match_operand:GCM 1 "register_operand" "")
9259 (match_operand:GCM 2 "register_operand" "")
9260 (match_operator 3 ""
9261 [(match_operand:GCM 4 "register_operand" "")
9262 (match_operand:GCM 5 "register_operand" "")])]
9265 sparc_expand_vcond (<MODE>mode, operands, UNSPEC_CMASK<gcm_name>, UNSPEC_FCMP);
9269 (define_expand "vconduv8qiv8qi"
9270 [(match_operand:V8QI 0 "register_operand" "")
9271 (match_operand:V8QI 1 "register_operand" "")
9272 (match_operand:V8QI 2 "register_operand" "")
9273 (match_operator 3 ""
9274 [(match_operand:V8QI 4 "register_operand" "")
9275 (match_operand:V8QI 5 "register_operand" "")])]
9278 sparc_expand_vcond (V8QImode, operands, UNSPEC_CMASK8, UNSPEC_FUCMP);
9282 (define_insn "array8<P:mode>_vis"
9283 [(set (match_operand:P 0 "register_operand" "=r")
9284 (unspec:P [(match_operand:P 1 "register_or_zero_operand" "rJ")
9285 (match_operand:P 2 "register_or_zero_operand" "rJ")]
9288 "array8\t%r1, %r2, %0"
9289 [(set_attr "type" "array")])
9291 (define_insn "array16<P:mode>_vis"
9292 [(set (match_operand:P 0 "register_operand" "=r")
9293 (unspec:P [(match_operand:P 1 "register_or_zero_operand" "rJ")
9294 (match_operand:P 2 "register_or_zero_operand" "rJ")]
9297 "array16\t%r1, %r2, %0"
9298 [(set_attr "type" "array")])
9300 (define_insn "array32<P:mode>_vis"
9301 [(set (match_operand:P 0 "register_operand" "=r")
9302 (unspec:P [(match_operand:P 1 "register_or_zero_operand" "rJ")
9303 (match_operand:P 2 "register_or_zero_operand" "rJ")]
9306 "array32\t%r1, %r2, %0"
9307 [(set_attr "type" "array")])
9309 (define_insn "bmaskdi_vis"
9310 [(set (match_operand:DI 0 "register_operand" "=r")
9311 (plus:DI (match_operand:DI 1 "register_or_zero_operand" "rJ")
9312 (match_operand:DI 2 "register_or_zero_operand" "rJ")))
9313 (set (zero_extract:DI (reg:DI GSR_REG) (const_int 32) (const_int 32))
9314 (plus:DI (match_dup 1) (match_dup 2)))]
9315 "TARGET_VIS2 && TARGET_ARCH64"
9316 "bmask\t%r1, %r2, %0"
9317 [(set_attr "type" "bmask")])
9319 (define_insn "bmasksi_vis"
9320 [(set (match_operand:SI 0 "register_operand" "=r")
9321 (plus:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
9322 (match_operand:SI 2 "register_or_zero_operand" "rJ")))
9323 (set (zero_extract:DI (reg:DI GSR_REG) (const_int 32) (const_int 32))
9324 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
9326 "bmask\t%r1, %r2, %0"
9327 [(set_attr "type" "bmask")])
9329 (define_insn "bshuffle<VM64:mode>_vis"
9330 [(set (match_operand:VM64 0 "register_operand" "=e")
9331 (unspec:VM64 [(match_operand:VM64 1 "register_operand" "e")
9332 (match_operand:VM64 2 "register_operand" "e")
9336 "bshuffle\t%1, %2, %0"
9337 [(set_attr "type" "fga")
9338 (set_attr "subtype" "other")
9339 (set_attr "fptype" "double")])
9341 ;; Unlike constant permutation, we can vastly simplify the compression of
9342 ;; the 64-bit selector input to the 32-bit %gsr value by knowing what the
9343 ;; width of the input is.
9344 (define_expand "vec_perm<VM64:mode>"
9345 [(match_operand:VM64 0 "register_operand" "")
9346 (match_operand:VM64 1 "register_operand" "")
9347 (match_operand:VM64 2 "register_operand" "")
9348 (match_operand:VM64 3 "register_operand" "")]
9351 sparc_expand_vec_perm_bmask (<MODE>mode, operands[3]);
9352 emit_insn (gen_bshuffle<VM64:mode>_vis (operands[0], operands[1], operands[2]));
9356 ;; VIS 2.0 adds edge variants which do not set the condition codes
9357 (define_insn "edge8n<P:mode>_vis"
9358 [(set (match_operand:P 0 "register_operand" "=r")
9359 (unspec:P [(match_operand:P 1 "register_or_zero_operand" "rJ")
9360 (match_operand:P 2 "register_or_zero_operand" "rJ")]
9363 "edge8n\t%r1, %r2, %0"
9364 [(set_attr "type" "edgen")])
9366 (define_insn "edge8ln<P:mode>_vis"
9367 [(set (match_operand:P 0 "register_operand" "=r")
9368 (unspec:P [(match_operand:P 1 "register_or_zero_operand" "rJ")
9369 (match_operand:P 2 "register_or_zero_operand" "rJ")]
9372 "edge8ln\t%r1, %r2, %0"
9373 [(set_attr "type" "edgen")])
9375 (define_insn "edge16n<P:mode>_vis"
9376 [(set (match_operand:P 0 "register_operand" "=r")
9377 (unspec:P [(match_operand:P 1 "register_or_zero_operand" "rJ")
9378 (match_operand:P 2 "register_or_zero_operand" "rJ")]
9381 "edge16n\t%r1, %r2, %0"
9382 [(set_attr "type" "edgen")])
9384 (define_insn "edge16ln<P:mode>_vis"
9385 [(set (match_operand:P 0 "register_operand" "=r")
9386 (unspec:P [(match_operand:P 1 "register_or_zero_operand" "rJ")
9387 (match_operand:P 2 "register_or_zero_operand" "rJ")]
9390 "edge16ln\t%r1, %r2, %0"
9391 [(set_attr "type" "edgen")])
9393 (define_insn "edge32n<P:mode>_vis"
9394 [(set (match_operand:P 0 "register_operand" "=r")
9395 (unspec:P [(match_operand:P 1 "register_or_zero_operand" "rJ")
9396 (match_operand:P 2 "register_or_zero_operand" "rJ")]
9399 "edge32n\t%r1, %r2, %0"
9400 [(set_attr "type" "edgen")])
9402 (define_insn "edge32ln<P:mode>_vis"
9403 [(set (match_operand:P 0 "register_operand" "=r")
9404 (unspec:P [(match_operand:P 1 "register_or_zero_operand" "rJ")
9405 (match_operand:P 2 "register_or_zero_operand" "rJ")]
9408 "edge32ln\t%r1, %r2, %0"
9409 [(set_attr "type" "edge")])
9411 ;; Conditional moves are possible via fcmpX --> cmaskX -> bshuffle
9412 (define_insn "cmask8<P:mode>_vis"
9413 [(set (reg:DI GSR_REG)
9414 (unspec:DI [(match_operand:P 0 "register_or_zero_operand" "rJ")
9419 [(set_attr "type" "fga")
9420 (set_attr "subtype" "cmask")])
9422 (define_insn "cmask16<P:mode>_vis"
9423 [(set (reg:DI GSR_REG)
9424 (unspec:DI [(match_operand:P 0 "register_or_zero_operand" "rJ")
9429 [(set_attr "type" "fga")
9430 (set_attr "subtype" "cmask")])
9432 (define_insn "cmask32<P:mode>_vis"
9433 [(set (reg:DI GSR_REG)
9434 (unspec:DI [(match_operand:P 0 "register_or_zero_operand" "rJ")
9439 [(set_attr "type" "fga")
9440 (set_attr "subtype" "cmask")])
9442 (define_insn "fchksm16_vis"
9443 [(set (match_operand:V4HI 0 "register_operand" "=e")
9444 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "e")
9445 (match_operand:V4HI 2 "register_operand" "e")]
9448 "fchksm16\t%1, %2, %0"
9449 [(set_attr "type" "fga")
9450 (set_attr "subtype" "fpu")])
9452 (define_code_iterator vis3_shift [ashift ss_ashift lshiftrt ashiftrt])
9453 (define_code_attr vis3_shift_insn
9454 [(ashift "fsll") (ss_ashift "fslas") (lshiftrt "fsrl") (ashiftrt "fsra")])
9455 (define_code_attr vis3_shift_patname
9456 [(ashift "ashl") (ss_ashift "ssashl") (lshiftrt "lshr") (ashiftrt "ashr")])
9458 (define_insn "v<vis3_shift_patname><GCM:mode>3"
9459 [(set (match_operand:GCM 0 "register_operand" "=<vconstr>")
9460 (vis3_shift:GCM (match_operand:GCM 1 "register_operand" "<vconstr>")
9461 (match_operand:GCM 2 "register_operand" "<vconstr>")))]
9463 "<vis3_shift_insn><vbits>\t%1, %2, %0"
9464 [(set_attr "type" "fga")
9465 (set_attr "subtype" "fpu")])
9467 (define_insn "pdistn<P:mode>_vis"
9468 [(set (match_operand:P 0 "register_operand" "=r")
9469 (unspec:P [(match_operand:V8QI 1 "register_operand" "e")
9470 (match_operand:V8QI 2 "register_operand" "e")]
9473 "pdistn\t%1, %2, %0"
9474 [(set_attr "type" "pdistn")
9475 (set_attr "fptype" "double")])
9477 (define_insn "fmean16_vis"
9478 [(set (match_operand:V4HI 0 "register_operand" "=e")
9484 (match_operand:V4HI 1 "register_operand" "e"))
9486 (match_operand:V4HI 2 "register_operand" "e")))
9487 (const_vector:V4SI [(const_int 1) (const_int 1)
9488 (const_int 1) (const_int 1)]))
9491 "fmean16\t%1, %2, %0"
9492 [(set_attr "type" "fga")
9493 (set_attr "subtype" "fpu")])
9495 (define_insn "fp<plusminus_insn>64_vis"
9496 [(set (match_operand:V1DI 0 "register_operand" "=e")
9497 (plusminus:V1DI (match_operand:V1DI 1 "register_operand" "e")
9498 (match_operand:V1DI 2 "register_operand" "e")))]
9500 "fp<plusminus_insn>64\t%1, %2, %0"
9501 [(set_attr "type" "fga")
9502 (set_attr "subtype" "addsub64")])
9504 (define_insn "<plusminus_insn>v8qi3"
9505 [(set (match_operand:V8QI 0 "register_operand" "=e")
9506 (plusminus:V8QI (match_operand:V8QI 1 "register_operand" "e")
9507 (match_operand:V8QI 2 "register_operand" "e")))]
9509 "fp<plusminus_insn>8\t%1, %2, %0"
9510 [(set_attr "type" "fga")
9511 (set_attr "subtype" "other")])
9513 (define_mode_iterator VASS [V4HI V2SI V2HI V1SI])
9514 (define_code_iterator vis3_addsub_ss [ss_plus ss_minus])
9515 (define_code_attr vis3_addsub_ss_insn
9516 [(ss_plus "fpadds") (ss_minus "fpsubs")])
9517 (define_code_attr vis3_addsub_ss_patname
9518 [(ss_plus "ssadd") (ss_minus "sssub")])
9520 (define_insn "<vis3_addsub_ss_patname><VASS:mode>3"
9521 [(set (match_operand:VASS 0 "register_operand" "=<vconstr>")
9522 (vis3_addsub_ss:VASS (match_operand:VASS 1 "register_operand" "<vconstr>")
9523 (match_operand:VASS 2 "register_operand" "<vconstr>")))]
9525 "<vis3_addsub_ss_insn><vbits>\t%1, %2, %0"
9526 [(set_attr "type" "fga")
9527 (set_attr "subtype" "other")])
9529 (define_mode_iterator VMMAX [V8QI V4HI V2SI])
9530 (define_code_iterator vis4_minmax [smin smax])
9531 (define_code_attr vis4_minmax_insn
9532 [(smin "fpmin") (smax "fpmax")])
9533 (define_code_attr vis4_minmax_patname
9534 [(smin "min") (smax "max")])
9536 (define_insn "<vis4_minmax_patname><VMMAX:mode>3"
9537 [(set (match_operand:VMMAX 0 "register_operand" "=<vconstr>")
9538 (vis4_minmax:VMMAX (match_operand:VMMAX 1 "register_operand" "<vconstr>")
9539 (match_operand:VMMAX 2 "register_operand" "<vconstr>")))]
9541 "<vis4_minmax_insn><vbits>\t%1, %2, %0"
9542 [(set_attr "type" "fga")
9543 (set_attr "subtype" "maxmin")])
9545 (define_code_iterator vis4_uminmax [umin umax])
9546 (define_code_attr vis4_uminmax_insn
9547 [(umin "fpminu") (umax "fpmaxu")])
9548 (define_code_attr vis4_uminmax_patname
9549 [(umin "minu") (umax "maxu")])
9551 (define_insn "<vis4_uminmax_patname><VMMAX:mode>3"
9552 [(set (match_operand:VMMAX 0 "register_operand" "=<vconstr>")
9553 (vis4_uminmax:VMMAX (match_operand:VMMAX 1 "register_operand" "<vconstr>")
9554 (match_operand:VMMAX 2 "register_operand" "<vconstr>")))]
9556 "<vis4_uminmax_insn><vbits>\t%1, %2, %0"
9557 [(set_attr "type" "fga")
9558 (set_attr "subtype" "maxmin")])
9560 ;; The use of vis3_addsub_ss_patname in the VIS4 instruction below is
9562 (define_insn "<vis3_addsub_ss_patname>v8qi3"
9563 [(set (match_operand:V8QI 0 "register_operand" "=e")
9564 (vis3_addsub_ss:V8QI (match_operand:V8QI 1 "register_operand" "e")
9565 (match_operand:V8QI 2 "register_operand" "e")))]
9567 "<vis3_addsub_ss_insn>8\t%1, %2, %0"
9568 [(set_attr "type" "fga")
9569 (set_attr "subtype" "other")])
9571 (define_mode_iterator VAUS [V4HI V8QI])
9572 (define_code_iterator vis4_addsub_us [us_plus us_minus])
9573 (define_code_attr vis4_addsub_us_insn
9574 [(us_plus "fpaddus") (us_minus "fpsubus")])
9575 (define_code_attr vis4_addsub_us_patname
9576 [(us_plus "usadd") (us_minus "ussub")])
9578 (define_insn "<vis4_addsub_us_patname><VAUS:mode>3"
9579 [(set (match_operand:VAUS 0 "register_operand" "=<vconstr>")
9580 (vis4_addsub_us:VAUS (match_operand:VAUS 1 "register_operand" "<vconstr>")
9581 (match_operand:VAUS 2 "register_operand" "<vconstr>")))]
9583 "<vis4_addsub_us_insn><vbits>\t%1, %2, %0"
9584 [(set_attr "type" "fga")
9585 (set_attr "subtype" "other")])
9587 (define_insn "fucmp<gcond:code>8<P:mode>_vis"
9588 [(set (match_operand:P 0 "register_operand" "=r")
9589 (unspec:P [(gcond:V8QI (match_operand:V8QI 1 "register_operand" "e")
9590 (match_operand:V8QI 2 "register_operand" "e"))]
9593 "fucmp<gcond:code>8\t%1, %2, %0"
9594 [(set_attr "type" "viscmp")])
9596 (define_insn "fpcmpu<gcond:code><GCM:gcm_name><P:mode>_vis"
9597 [(set (match_operand:P 0 "register_operand" "=r")
9598 (unspec:P [(gcond:GCM (match_operand:GCM 1 "register_operand" "e")
9599 (match_operand:GCM 2 "register_operand" "e"))]
9602 "fpcmpu<gcond:code><GCM:gcm_name>\t%1, %2, %0"
9603 [(set_attr "type" "viscmp")])
9605 (define_insn "*naddsf3"
9606 [(set (match_operand:SF 0 "register_operand" "=f")
9607 (neg:SF (plus:SF (match_operand:SF 1 "register_operand" "f")
9608 (match_operand:SF 2 "register_operand" "f"))))]
9610 "fnadds\t%1, %2, %0"
9611 [(set_attr "type" "fp")])
9613 (define_insn "*nadddf3"
9614 [(set (match_operand:DF 0 "register_operand" "=e")
9615 (neg:DF (plus:DF (match_operand:DF 1 "register_operand" "e")
9616 (match_operand:DF 2 "register_operand" "e"))))]
9618 "fnaddd\t%1, %2, %0"
9619 [(set_attr "type" "fp")
9620 (set_attr "fptype" "double")])
9622 (define_insn "*nmulsf3"
9623 [(set (match_operand:SF 0 "register_operand" "=f")
9624 (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "f"))
9625 (match_operand:SF 2 "register_operand" "f")))]
9627 "fnmuls\t%1, %2, %0"
9628 [(set_attr "type" "fpmul")])
9630 (define_insn "*nmuldf3"
9631 [(set (match_operand:DF 0 "register_operand" "=e")
9632 (mult:DF (neg:DF (match_operand:DF 1 "register_operand" "e"))
9633 (match_operand:DF 2 "register_operand" "e")))]
9635 "fnmuld\t%1, %2, %0"
9636 [(set_attr "type" "fpmul")
9637 (set_attr "fptype" "double")])
9639 (define_insn "*nmuldf3_extend"
9640 [(set (match_operand:DF 0 "register_operand" "=e")
9641 (mult:DF (neg:DF (float_extend:DF
9642 (match_operand:SF 1 "register_operand" "f")))
9644 (match_operand:SF 2 "register_operand" "f"))))]
9646 "fnsmuld\t%1, %2, %0"
9647 [(set_attr "type" "fpmul")
9648 (set_attr "fptype" "double")])
9650 (define_insn "fhaddsf_vis"
9651 [(set (match_operand:SF 0 "register_operand" "=f")
9652 (unspec:SF [(match_operand:SF 1 "register_operand" "f")
9653 (match_operand:SF 2 "register_operand" "f")]
9656 "fhadds\t%1, %2, %0"
9657 [(set_attr "type" "fp")])
9659 (define_insn "fhadddf_vis"
9660 [(set (match_operand:DF 0 "register_operand" "=f")
9661 (unspec:DF [(match_operand:DF 1 "register_operand" "f")
9662 (match_operand:DF 2 "register_operand" "f")]
9665 "fhaddd\t%1, %2, %0"
9666 [(set_attr "type" "fp")
9667 (set_attr "fptype" "double")])
9669 (define_insn "fhsubsf_vis"
9670 [(set (match_operand:SF 0 "register_operand" "=f")
9671 (unspec:SF [(match_operand:SF 1 "register_operand" "f")
9672 (match_operand:SF 2 "register_operand" "f")]
9675 "fhsubs\t%1, %2, %0"
9676 [(set_attr "type" "fp")])
9678 (define_insn "fhsubdf_vis"
9679 [(set (match_operand:DF 0 "register_operand" "=f")
9680 (unspec:DF [(match_operand:DF 1 "register_operand" "f")
9681 (match_operand:DF 2 "register_operand" "f")]
9684 "fhsubd\t%1, %2, %0"
9685 [(set_attr "type" "fp")
9686 (set_attr "fptype" "double")])
9688 (define_insn "fnhaddsf_vis"
9689 [(set (match_operand:SF 0 "register_operand" "=f")
9690 (neg:SF (unspec:SF [(match_operand:SF 1 "register_operand" "f")
9691 (match_operand:SF 2 "register_operand" "f")]
9694 "fnhadds\t%1, %2, %0"
9695 [(set_attr "type" "fp")])
9697 (define_insn "fnhadddf_vis"
9698 [(set (match_operand:DF 0 "register_operand" "=f")
9699 (neg:DF (unspec:DF [(match_operand:DF 1 "register_operand" "f")
9700 (match_operand:DF 2 "register_operand" "f")]
9703 "fnhaddd\t%1, %2, %0"
9704 [(set_attr "type" "fp")
9705 (set_attr "fptype" "double")])
9707 ;; VIS4B instructions.
9709 (define_mode_iterator DUMODE [V2SI V4HI V8QI])
9711 (define_insn "dictunpack<DUMODE:vbits>"
9712 [(set (match_operand:DUMODE 0 "register_operand" "=e")
9713 (unspec:DUMODE [(match_operand:DF 1 "register_operand" "e")
9714 (match_operand:SI 2 "imm5_operand_dictunpack<DUMODE:vbits>" "t")]
9715 UNSPEC_DICTUNPACK))]
9717 "dictunpack\t%1, %2, %0"
9718 [(set_attr "type" "fga")
9719 (set_attr "subtype" "other")])
9721 (define_mode_iterator FPCSMODE [V2SI V4HI V8QI])
9722 (define_code_iterator fpcscond [le gt eq ne])
9723 (define_code_iterator fpcsucond [le gt])
9725 (define_insn "fpcmp<fpcscond:code><FPCSMODE:vbits><P:mode>shl"
9726 [(set (match_operand:P 0 "register_operand" "=r")
9727 (unspec:P [(fpcscond:FPCSMODE (match_operand:FPCSMODE 1 "register_operand" "e")
9728 (match_operand:FPCSMODE 2 "register_operand" "e"))
9729 (match_operand:SI 3 "imm2_operand" "q")]
9732 "fpcmp<fpcscond:code><FPCSMODE:vbits>shl\t%1, %2, %3, %0"
9733 [(set_attr "type" "viscmp")])
9735 (define_insn "fpcmpu<fpcsucond:code><FPCSMODE:vbits><P:mode>shl"
9736 [(set (match_operand:P 0 "register_operand" "=r")
9737 (unspec:P [(fpcsucond:FPCSMODE (match_operand:FPCSMODE 1 "register_operand" "e")
9738 (match_operand:FPCSMODE 2 "register_operand" "e"))
9739 (match_operand:SI 3 "imm2_operand" "q")]
9742 "fpcmpu<fpcsucond:code><FPCSMODE:vbits>shl\t%1, %2, %3, %0"
9743 [(set_attr "type" "viscmp")])
9745 (define_insn "fpcmpde<FPCSMODE:vbits><P:mode>shl"
9746 [(set (match_operand:P 0 "register_operand" "=r")
9747 (unspec:P [(match_operand:FPCSMODE 1 "register_operand" "e")
9748 (match_operand:FPCSMODE 2 "register_operand" "e")
9749 (match_operand:SI 3 "imm2_operand" "q")]
9750 UNSPEC_FPCMPDESHL))]
9752 "fpcmpde<FPCSMODE:vbits>shl\t%1, %2, %3, %0"
9753 [(set_attr "type" "viscmp")])
9755 (define_insn "fpcmpur<FPCSMODE:vbits><P:mode>shl"
9756 [(set (match_operand:P 0 "register_operand" "=r")
9757 (unspec:P [(match_operand:FPCSMODE 1 "register_operand" "e")
9758 (match_operand:FPCSMODE 2 "register_operand" "e")
9759 (match_operand:SI 3 "imm2_operand" "q")]
9760 UNSPEC_FPCMPURSHL))]
9762 "fpcmpur<FPCSMODE:vbits>shl\t%1, %2, %3, %0"
9763 [(set_attr "type" "viscmp")])