gcc/config/sparc/sparc.opt

   1 ; Options for the SPARC port of the compiler
   2 ;
   3 ; Copyright (C) 2005-2020 Free Software Foundation, Inc.
   4 ;
   5 ; This file is part of GCC.
   6 ;
   7 ; GCC is free software; you can redistribute it and/or modify it under
   8 ; the terms of the GNU General Public License as published by the Free
   9 ; Software Foundation; either version 3, or (at your option) any later
  10 ; version.
  11 ;
  12 ; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ; License for more details.
  16 ;
  17 ; You should have received a copy of the GNU General Public License
  18 ; along with GCC; see the file COPYING3.  If not see
  19 ; <http://www.gnu.org/licenses/>.
  20
  21 HeaderInclude
  22 config/sparc/sparc-opts.h
  23
  24 ;; Debug flags
  25 TargetVariable
  26 unsigned int sparc_debug
  27
  28 mfpu
  29 Target Report Mask(FPU)
  30 Use hardware FP.
  31
  32 mhard-float
  33 Target RejectNegative Mask(FPU)
  34 Use hardware FP.
  35
  36 msoft-float
  37 Target RejectNegative InverseMask(FPU)
  38 Do not use hardware FP.
  39
  40 mflat
  41 Target Report Mask(FLAT)
  42 Use flat register window model.
  43
  44 munaligned-doubles
  45 Target Report Mask(UNALIGNED_DOUBLES)
  46 Assume possible double misalignment.
  47
  48 mapp-regs
  49 Target Report Mask(APP_REGS)
  50 Use ABI reserved registers.
  51
  52 mhard-quad-float
  53 Target Report RejectNegative Mask(HARD_QUAD)
  54 Use hardware quad FP instructions.
  55
  56 msoft-quad-float
  57 Target Report RejectNegative InverseMask(HARD_QUAD)
  58 Do not use hardware quad fp instructions.
  59
  60 mlra
  61 Target Report Mask(LRA)
  62 Enable Local Register Allocation.
  63
  64 mv8plus
  65 Target Report Mask(V8PLUS)
  66 Compile for V8+ ABI.
  67
  68 mvis
  69 Target Report Mask(VIS)
  70 Use UltraSPARC Visual Instruction Set version 1.0 extensions.
  71
  72 mvis2
  73 Target Report Mask(VIS2)
  74 Use UltraSPARC Visual Instruction Set version 2.0 extensions.
  75
  76 mvis3
  77 Target Report Mask(VIS3)
  78 Use UltraSPARC Visual Instruction Set version 3.0 extensions.
  79
  80 mvis4
  81 Target Report Mask(VIS4)
  82 Use UltraSPARC Visual Instruction Set version 4.0 extensions.
  83
  84 mvis4b
  85 Target Report Mask(VIS4B)
  86 Use additional VIS instructions introduced in OSA2017.
  87
  88 mcbcond
  89 Target Report Mask(CBCOND)
  90 Use UltraSPARC Compare-and-Branch extensions.
  91
  92 mfmaf
  93 Target Report Mask(FMAF)
  94 Use UltraSPARC Fused Multiply-Add extensions.
  95
  96 mfsmuld
  97 Target Report Mask(FSMULD)
  98 Use Floating-point Multiply Single to Double (FsMULd) instruction.
  99
 100 mpopc
 101 Target Report Mask(POPC)
 102 Use UltraSPARC Population-Count instruction.
 103
 104 msubxc
 105 Target Report Mask(SUBXC)
 106 Use UltraSPARC Subtract-Extended-with-Carry instruction.
 107
 108 mptr64
 109 Target Report RejectNegative Mask(PTR64)
 110 Pointers are 64-bit.
 111
 112 mptr32
 113 Target Report RejectNegative InverseMask(PTR64)
 114 Pointers are 32-bit.
 115
 116 m64
 117 Target Report RejectNegative Mask(64BIT)
 118 Use 64-bit ABI.
 119
 120 m32
 121 Target Report RejectNegative InverseMask(64BIT)
 122 Use 32-bit ABI.
 123
 124 mstack-bias
 125 Target Report Mask(STACK_BIAS)
 126 Use stack bias.
 127
 128 mfaster-structs
 129 Target Report Mask(FASTER_STRUCTS)
 130 Use structs on stronger alignment for double-word copies.
 131
 132 mrelax
 133 Target
 134 Optimize tail call instructions in assembler and linker.
 135
 136 muser-mode
 137 Target Report InverseMask(SV_MODE)
 138 Do not generate code that can only run in supervisor mode (default).
 139
 140 mcpu=
 141 Target RejectNegative Joined Var(sparc_cpu_and_features) Enum(sparc_processor) Init(PROCESSOR_V7)
 142 Use instructions of and schedule code for given CPU.
 143
 144 mtune=
 145 Target RejectNegative Joined Var(sparc_cpu) Enum(sparc_processor) Init(PROCESSOR_V7)
 146 Schedule code for given CPU.
 147
 148 Enum
 149 Name(sparc_processor) Type(enum sparc_processor_type)
 150
 151 EnumValue
 152 Enum(sparc_processor) String(native) Value(PROCESSOR_NATIVE) DriverOnly
 153
 154 EnumValue
 155 Enum(sparc_processor) String(v7) Value(PROCESSOR_V7)
 156
 157 EnumValue
 158 Enum(sparc_processor) String(cypress) Value(PROCESSOR_CYPRESS)
 159
 160 EnumValue
 161 Enum(sparc_processor) String(v8) Value(PROCESSOR_V8)
 162
 163 EnumValue
 164 Enum(sparc_processor) String(supersparc) Value(PROCESSOR_SUPERSPARC)
 165
 166 EnumValue
 167 Enum(sparc_processor) String(hypersparc) Value(PROCESSOR_HYPERSPARC)
 168
 169 EnumValue
 170 Enum(sparc_processor) String(leon) Value(PROCESSOR_LEON)
 171
 172 EnumValue
 173 Enum(sparc_processor) String(leon3) Value(PROCESSOR_LEON3)
 174
 175 EnumValue
 176 Enum(sparc_processor) String(leon3v7) Value(PROCESSOR_LEON3V7)
 177
 178 EnumValue
 179 Enum(sparc_processor) String(sparclite) Value(PROCESSOR_SPARCLITE)
 180
 181 EnumValue
 182 Enum(sparc_processor) String(f930) Value(PROCESSOR_F930)
 183
 184 EnumValue
 185 Enum(sparc_processor) String(f934) Value(PROCESSOR_F934)
 186
 187 EnumValue
 188 Enum(sparc_processor) String(sparclite86x) Value(PROCESSOR_SPARCLITE86X)
 189
 190 EnumValue
 191 Enum(sparc_processor) String(sparclet) Value(PROCESSOR_SPARCLET)
 192
 193 EnumValue
 194 Enum(sparc_processor) String(tsc701) Value(PROCESSOR_TSC701)
 195
 196 EnumValue
 197 Enum(sparc_processor) String(v9) Value(PROCESSOR_V9)
 198
 199 EnumValue
 200 Enum(sparc_processor) String(ultrasparc) Value(PROCESSOR_ULTRASPARC)
 201
 202 EnumValue
 203 Enum(sparc_processor) String(ultrasparc3) Value(PROCESSOR_ULTRASPARC3)
 204
 205 EnumValue
 206 Enum(sparc_processor) String(niagara) Value(PROCESSOR_NIAGARA)
 207
 208 EnumValue
 209 Enum(sparc_processor) String(niagara2) Value(PROCESSOR_NIAGARA2)
 210
 211 EnumValue
 212 Enum(sparc_processor) String(niagara3) Value(PROCESSOR_NIAGARA3)
 213
 214 EnumValue
 215 Enum(sparc_processor) String(niagara4) Value(PROCESSOR_NIAGARA4)
 216
 217 EnumValue
 218 Enum(sparc_processor) String(niagara7) Value(PROCESSOR_NIAGARA7)
 219
 220 EnumValue
 221 Enum(sparc_processor) String(m8) Value(PROCESSOR_M8)
 222
 223 mcmodel=
 224 Target RejectNegative Joined Var(sparc_code_model) Enum(sparc_code_model) Init(CM_32)
 225 Use given SPARC-V9 code model.
 226
 227 Enum
 228 Name(sparc_code_model) Type(enum sparc_code_model_type)
 229
 230 EnumValue
 231 Enum(sparc_code_model) String(32) Value(CM_32)
 232
 233 EnumValue
 234 Enum(sparc_code_model) String(medlow) Value(CM_MEDLOW)
 235
 236 EnumValue
 237 Enum(sparc_code_model) String(medmid) Value(CM_MEDMID)
 238
 239 EnumValue
 240 Enum(sparc_code_model) String(medany) Value(CM_MEDANY)
 241
 242 EnumValue
 243 Enum(sparc_code_model) String(embmedany) Value(CM_EMBMEDANY)
 244
 245 mdebug=
 246 Target RejectNegative Joined Undocumented Var(sparc_debug_string)
 247 Enable debug output.
 248
 249 mstd-struct-return
 250 Target Report Var(sparc_std_struct_return)
 251 Enable strict 32-bit psABI struct return checking.
 252
 253 mfix-at697f
 254 Target Report RejectNegative Var(sparc_fix_at697f)
 255 Enable workaround for single erratum of AT697F processor
 256 (corresponding to erratum #13 of AT697E processor).
 257
 258 mfix-ut699
 259 Target Report RejectNegative Var(sparc_fix_ut699)
 260 Enable workarounds for the errata of the UT699 processor.
 261
 262 mfix-ut700
 263 Target Report RejectNegative Var(sparc_fix_ut700)
 264 Enable workarounds for the errata of the UT699E/UT700 processor.
 265
 266 mfix-gr712rc
 267 Target Report RejectNegative Var(sparc_fix_gr712rc)
 268 Enable workarounds for the errata of the GR712RC processor.
 269
 270 ;; Enable workaround for back-to-back store errata
 271 TargetVariable
 272 unsigned int sparc_fix_b2bst
 273
 274 ;; Enable workaround for GRLIB-TN-0013 errata
 275 TargetVariable
 276 unsigned int sparc_fix_lost_divsqrt
 277
 278 Mask(LONG_DOUBLE_128)
 279 ;; Use 128-bit long double
 280
 281 Mask(LEON)
 282 ;; Generate code for LEON
 283
 284 Mask(LEON3)
 285 ;; Generate code for LEON3
 286
 287 Mask(SPARCLITE)
 288 ;; Generate code for SPARClite
 289
 290 Mask(SPARCLET)
 291 ;; Generate code for SPARClet
 292
 293 Mask(V8)
 294 ;; Generate code for SPARC-V8
 295
 296 Mask(V9)
 297 ;; Generate code for SPARC-V9
 298
 299 Mask(DEPRECATED_V8_INSNS)
 300 ;; Generate code that uses the V8 instructions deprecated
 301 ;; in the V9 architecture.
 302
 303 mmemory-model=
 304 Target RejectNegative Joined Var(sparc_memory_model) Enum(sparc_memory_model) Init(SMM_DEFAULT)
 305 Specify the memory model in effect for the program.
 306
 307 Enum
 308 Name(sparc_memory_model) Type(enum sparc_memory_model_type)
 309
 310 EnumValue
 311 Enum(sparc_memory_model) String(default) Value(SMM_DEFAULT)
 312
 313 EnumValue
 314 Enum(sparc_memory_model) String(rmo) Value(SMM_RMO)
 315
 316 EnumValue
 317 Enum(sparc_memory_model) String(pso) Value(SMM_PSO)
 318
 319 EnumValue
 320 Enum(sparc_memory_model) String(tso) Value(SMM_TSO)
 321
 322 EnumValue
 323 Enum(sparc_memory_model) String(sc) Value(SMM_SC)