gcc/config/sparc/sparc.opt

   1 ; Options for the SPARC port of the compiler
   2 ;
   3 ; Copyright (C) 2005, 2007, 2010, 2011 Free Software Foundation, Inc.
   4 ;
   5 ; This file is part of GCC.
   6 ;
   7 ; GCC is free software; you can redistribute it and/or modify it under
   8 ; the terms of the GNU General Public License as published by the Free
   9 ; Software Foundation; either version 3, or (at your option) any later
  10 ; version.
  11 ;
  12 ; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ; License for more details.
  16 ;
  17 ; You should have received a copy of the GNU General Public License
  18 ; along with GCC; see the file COPYING3.  If not see
  19 ; <http://www.gnu.org/licenses/>.
  20
  21 HeaderInclude
  22 config/sparc/sparc-opts.h
  23
  24 mfpu
  25 Target Report Mask(FPU)
  26 Use hardware FP
  27
  28 mhard-float
  29 Target RejectNegative Mask(FPU) MaskExists
  30 Use hardware FP
  31
  32 msoft-float
  33 Target RejectNegative InverseMask(FPU)
  34 Do not use hardware FP
  35
  36 mflat
  37 Target Report Mask(FLAT)
  38 Use flat register window model
  39
  40 munaligned-doubles
  41 Target Report Mask(UNALIGNED_DOUBLES)
  42 Assume possible double misalignment
  43
  44 mapp-regs
  45 Target Report Mask(APP_REGS)
  46 Use ABI reserved registers
  47
  48 mhard-quad-float
  49 Target Report RejectNegative Mask(HARD_QUAD)
  50 Use hardware quad FP instructions
  51
  52 msoft-quad-float
  53 Target Report RejectNegative InverseMask(HARD_QUAD)
  54 Do not use hardware quad fp instructions
  55
  56 mv8plus
  57 Target Report Mask(V8PLUS)
  58 Compile for V8+ ABI
  59
  60 mvis
  61 Target Report Mask(VIS)
  62 Use UltraSPARC Visual Instruction Set version 1.0 extensions
  63
  64 mvis2
  65 Target Report Mask(VIS2)
  66 Use UltraSPARC Visual Instruction Set version 2.0 extensions
  67
  68 mvis3
  69 Target Report Mask(VIS3)
  70 Use UltraSPARC Visual Instruction Set version 3.0 extensions
  71
  72 mfmaf
  73 Target Report Mask(FMAF)
  74 Use UltraSPARC Fused Multiply-Add extensions
  75
  76 mptr64
  77 Target Report RejectNegative Mask(PTR64)
  78 Pointers are 64-bit
  79
  80 mptr32
  81 Target Report RejectNegative InverseMask(PTR64)
  82 Pointers are 32-bit
  83
  84 m64
  85 Target Report RejectNegative Mask(64BIT)
  86 Use 64-bit ABI
  87
  88 m32
  89 Target Report RejectNegative InverseMask(64BIT)
  90 Use 32-bit ABI
  91
  92 mstack-bias
  93 Target Report Mask(STACK_BIAS)
  94 Use stack bias
  95
  96 mfaster-structs
  97 Target Report Mask(FASTER_STRUCTS)
  98 Use structs on stronger alignment for double-word copies
  99
 100 mrelax
 101 Target
 102 Optimize tail call instructions in assembler and linker
 103
 104 mcpu=
 105 Target RejectNegative Joined Var(sparc_cpu_and_features) Enum(sparc_processor_type) Init(PROCESSOR_V7)
 106 Use features of and schedule code for given CPU
 107
 108 mtune=
 109 Target RejectNegative Joined Var(sparc_cpu) Enum(sparc_processor_type) Init(PROCESSOR_V7)
 110 Schedule code for given CPU
 111
 112 Enum
 113 Name(sparc_processor_type) Type(enum processor_type)
 114
 115 EnumValue
 116 Enum(sparc_processor_type) String(native) Value(PROCESSOR_NATIVE) DriverOnly
 117
 118 EnumValue
 119 Enum(sparc_processor_type) String(v7) Value(PROCESSOR_V7)
 120
 121 EnumValue
 122 Enum(sparc_processor_type) String(cypress) Value(PROCESSOR_CYPRESS)
 123
 124 EnumValue
 125 Enum(sparc_processor_type) String(v8) Value(PROCESSOR_V8)
 126
 127 EnumValue
 128 Enum(sparc_processor_type) String(supersparc) Value(PROCESSOR_SUPERSPARC)
 129
 130 EnumValue
 131 Enum(sparc_processor_type) String(hypersparc) Value(PROCESSOR_HYPERSPARC)
 132
 133 EnumValue
 134 Enum(sparc_processor_type) String(leon) Value(PROCESSOR_LEON)
 135
 136 EnumValue
 137 Enum(sparc_processor_type) String(sparclite) Value(PROCESSOR_SPARCLITE)
 138
 139 EnumValue
 140 Enum(sparc_processor_type) String(f930) Value(PROCESSOR_F930)
 141
 142 EnumValue
 143 Enum(sparc_processor_type) String(f934) Value(PROCESSOR_F934)
 144
 145 EnumValue
 146 Enum(sparc_processor_type) String(sparclite86x) Value(PROCESSOR_SPARCLITE86X)
 147
 148 EnumValue
 149 Enum(sparc_processor_type) String(sparclet) Value(PROCESSOR_SPARCLET)
 150
 151 EnumValue
 152 Enum(sparc_processor_type) String(tsc701) Value(PROCESSOR_TSC701)
 153
 154 EnumValue
 155 Enum(sparc_processor_type) String(v9) Value(PROCESSOR_V9)
 156
 157 EnumValue
 158 Enum(sparc_processor_type) String(ultrasparc) Value(PROCESSOR_ULTRASPARC)
 159
 160 EnumValue
 161 Enum(sparc_processor_type) String(ultrasparc3) Value(PROCESSOR_ULTRASPARC3)
 162
 163 EnumValue
 164 Enum(sparc_processor_type) String(niagara) Value(PROCESSOR_NIAGARA)
 165
 166 EnumValue
 167 Enum(sparc_processor_type) String(niagara2) Value(PROCESSOR_NIAGARA2)
 168
 169 EnumValue
 170 Enum(sparc_processor_type) String(niagara3) Value(PROCESSOR_NIAGARA3)
 171
 172 EnumValue
 173 Enum(sparc_processor_type) String(niagara4) Value(PROCESSOR_NIAGARA4)
 174
 175 mcmodel=
 176 Target RejectNegative Joined Var(sparc_cmodel_string)
 177 Use given SPARC-V9 code model
 178
 179 mstd-struct-return
 180 Target Report RejectNegative Var(sparc_std_struct_return)
 181 Enable strict 32-bit psABI struct return checking.
 182
 183 Mask(LITTLE_ENDIAN)
 184 ;; Generate code for little-endian
 185
 186 Mask(LONG_DOUBLE_128)
 187 ;; Use 128-bit long double
 188
 189 Mask(SPARCLITE)
 190 ;; Generate code for SPARClite
 191
 192 Mask(SPARCLET)
 193 ;; Generate code for SPARClet
 194
 195 Mask(V8)
 196 ;; Generate code for SPARC-V8
 197
 198 Mask(V9)
 199 ;; Generate code for SPARC-V9
 200
 201 Mask(DEPRECATED_V8_INSNS)
 202 ;; Generate code that uses the V8 instructions deprecated
 203 ;; in the V9 architecture.