gcc/config/sparc/sync.md

   1 ;; GCC machine description for SPARC synchronization instructions.
   2 ;; Copyright (C) 2005-2013 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5 ;;
   6 ;; GCC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 3, or (at your option)
   9 ;; any later version.
  10 ;;
  11 ;; GCC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.
  19
  20 (define_mode_iterator I12MODE [QI HI])
  21 (define_mode_iterator I124MODE [QI HI SI])
  22 (define_mode_iterator I24MODE [HI SI])
  23 (define_mode_iterator I48MODE [SI (DI "TARGET_ARCH64 || TARGET_V8PLUS")])
  24 (define_mode_attr modesuffix [(SI "") (DI "x")])
  25
  26 (define_expand "mem_thread_fence"
  27   [(match_operand:SI 0 "const_int_operand")]
  28   "TARGET_V8 || TARGET_V9"
  29 {
  30   enum memmodel model = (enum memmodel) INTVAL (operands[0]);
  31   sparc_emit_membar_for_model (model, 3, 3);
  32   DONE;
  33 })
  34
  35 (define_expand "membar"
  36   [(set (match_dup 1)
  37         (unspec:BLK [(match_dup 1) (match_operand:SI 0 "const_int_operand")]
  38                     UNSPEC_MEMBAR))]
  39   "TARGET_V8 || TARGET_V9"
  40 {
  41   operands[1] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
  42   MEM_VOLATILE_P (operands[1]) = 1;
  43 })
  44
  45 ;; A compiler-only memory barrier.  Generic code, when checking for the
  46 ;; existence of various named patterns, uses asm("":::"memory") when we
  47 ;; don't need an actual instruction.  Here, it's easiest to pretend that
  48 ;; membar 0 is such a barrier.  Further, this gives us a nice hook to
  49 ;; ignore all such barriers on Sparc V7.
  50 (define_insn "*membar_empty"
  51   [(set (match_operand:BLK 0 "" "")
  52         (unspec:BLK [(match_dup 0) (match_operand:SI 1 "zero_or_v7_operand")]
  53                     UNSPEC_MEMBAR))]
  54   ""
  55   ""
  56   [(set_attr "type" "multi")
  57    (set_attr "length" "0")])
  58
  59 ;; For V8, STBAR is exactly membar #StoreStore, by definition.
  60 (define_insn "*membar_storestore"
  61   [(set (match_operand:BLK 0 "" "")
  62         (unspec:BLK [(match_dup 0) (const_int 8)] UNSPEC_MEMBAR))]
  63   "TARGET_V8"
  64   "stbar"
  65   [(set_attr "type" "multi")])
  66
  67 ;; For V8, LDSTUB has the effect of membar #StoreLoad.
  68 (define_insn "*membar_storeload"
  69   [(set (match_operand:BLK 0 "" "")
  70         (unspec:BLK [(match_dup 0) (const_int 2)] UNSPEC_MEMBAR))]
  71   "TARGET_V8"
  72   "ldstub\t[%%sp-1], %%g0"
  73   [(set_attr "type" "multi")])
  74
  75 ;; Put the two together, in combination with the fact that V8 implements PSO
  76 ;; as its weakest memory model, means a full barrier.  Match all remaining
  77 ;; instances of the membar pattern for Sparc V8.
  78 (define_insn "*membar_v8"
  79   [(set (match_operand:BLK 0 "" "")
  80         (unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")]
  81                     UNSPEC_MEMBAR))]
  82   "TARGET_V8"
  83   "stbar\n\tldstub\t[%%sp-1], %%g0"
  84   [(set_attr "type" "multi")
  85    (set_attr "length" "2")])
  86
  87 ;; For V9, we have the full membar instruction.
  88 (define_insn "*membar"
  89   [(set (match_operand:BLK 0 "" "")
  90         (unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")]
  91                     UNSPEC_MEMBAR))]
  92   "TARGET_V9"
  93   "membar\t%1"
  94   [(set_attr "type" "multi")])
  95
  96 (define_expand "atomic_load<mode>"
  97   [(match_operand:I 0 "register_operand" "")
  98    (match_operand:I 1 "memory_operand" "")
  99    (match_operand:SI 2 "const_int_operand" "")]
 100   ""
 101 {
 102   enum memmodel model = (enum memmodel) INTVAL (operands[2]);
 103
 104   sparc_emit_membar_for_model (model, 1, 1);
 105
 106   if (TARGET_ARCH64 || <MODE>mode != DImode)
 107     emit_move_insn (operands[0], operands[1]);
 108   else
 109     emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
 110
 111   sparc_emit_membar_for_model (model, 1, 2);
 112   DONE;
 113 })
 114
 115 (define_insn "atomic_loaddi_1"
 116   [(set (match_operand:DI 0 "register_operand" "=U,?*f")
 117         (unspec:DI [(match_operand:DI 1 "memory_operand" "m,m")]
 118                    UNSPEC_ATOMIC))]
 119   "!TARGET_ARCH64"
 120   "ldd\t%1, %0"
 121   [(set_attr "type" "load,fpload")])
 122
 123 (define_expand "atomic_store<mode>"
 124   [(match_operand:I 0 "memory_operand" "")
 125    (match_operand:I 1 "register_operand" "")
 126    (match_operand:SI 2 "const_int_operand" "")]
 127   ""
 128 {
 129   enum memmodel model = (enum memmodel) INTVAL (operands[2]);
 130
 131   sparc_emit_membar_for_model (model, 2, 1);
 132
 133   if (TARGET_ARCH64 || <MODE>mode != DImode)
 134     emit_move_insn (operands[0], operands[1]);
 135   else
 136     emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
 137
 138   sparc_emit_membar_for_model (model, 2, 2);
 139   DONE;
 140 })
 141
 142 (define_insn "atomic_storedi_1"
 143   [(set (match_operand:DI 0 "memory_operand" "=m,m,m")
 144         (unspec:DI
 145           [(match_operand:DI 1 "register_or_v9_zero_operand" "J,U,?*f")]
 146           UNSPEC_ATOMIC))]
 147   "!TARGET_ARCH64"
 148   "@
 149    stx\t%r1, %0
 150    std\t%1, %0
 151    std\t%1, %0"
 152   [(set_attr "type" "store,store,fpstore")
 153    (set_attr "cpu_feature" "v9,*,*")])
 154
 155 (define_expand "atomic_compare_and_swap<mode>"
 156   [(match_operand:SI 0 "register_operand" "")           ;; bool output
 157    (match_operand:I 1 "register_operand" "")            ;; val output
 158    (match_operand:I 2 "mem_noofs_operand" "")           ;; memory
 159    (match_operand:I 3 "register_operand" "")            ;; expected
 160    (match_operand:I 4 "register_operand" "")            ;; desired
 161    (match_operand:SI 5 "const_int_operand" "")          ;; is_weak
 162    (match_operand:SI 6 "const_int_operand" "")          ;; mod_s
 163    (match_operand:SI 7 "const_int_operand" "")]         ;; mod_f
 164   "(TARGET_V9 || TARGET_LEON3)
 165    && (<MODE>mode != DImode || TARGET_ARCH64 || TARGET_V8PLUS)"
 166 {
 167   sparc_expand_compare_and_swap (operands);
 168   DONE;
 169 })
 170
 171 (define_expand "atomic_compare_and_swap<mode>_1"
 172   [(parallel
 173      [(set (match_operand:I48MODE 0 "register_operand" "")
 174            (match_operand:I48MODE 1 "mem_noofs_operand" ""))
 175       (set (match_dup 1)
 176            (unspec_volatile:I48MODE
 177              [(match_operand:I48MODE 2 "register_operand" "")
 178               (match_operand:I48MODE 3 "register_operand" "")]
 179              UNSPECV_CAS))])]
 180   "TARGET_V9 || TARGET_LEON3"
 181   "")
 182
 183 (define_insn "*atomic_compare_and_swap<mode>_1"
 184   [(set (match_operand:I48MODE 0 "register_operand" "=r")
 185         (match_operand:I48MODE 1 "mem_noofs_operand" "+w"))
 186    (set (match_dup 1)
 187         (unspec_volatile:I48MODE
 188           [(match_operand:I48MODE 2 "register_operand" "r")
 189            (match_operand:I48MODE 3 "register_operand" "0")]
 190           UNSPECV_CAS))]
 191   "(TARGET_V9 || TARGET_LEON3) && (<MODE>mode != DImode || TARGET_ARCH64)"
 192   "cas<modesuffix>\t%1, %2, %0"
 193   [(set_attr "type" "multi")])
 194
 195 (define_insn "*atomic_compare_and_swapdi_v8plus"
 196   [(set (match_operand:DI 0 "register_operand" "=h")
 197         (match_operand:DI 1 "mem_noofs_operand" "+w"))
 198    (set (match_dup 1)
 199         (unspec_volatile:DI
 200           [(match_operand:DI 2 "register_operand" "h")
 201            (match_operand:DI 3 "register_operand" "0")]
 202           UNSPECV_CAS))]
 203   "TARGET_V8PLUS"
 204 {
 205   if (sparc_check_64 (operands[3], insn) <= 0)
 206     output_asm_insn ("srl\t%L3, 0, %L3", operands);
 207   output_asm_insn ("sllx\t%H3, 32, %H3", operands);
 208   output_asm_insn ("or\t%L3, %H3, %L3", operands);
 209   if (sparc_check_64 (operands[2], insn) <= 0)
 210     output_asm_insn ("srl\t%L2, 0, %L2", operands);
 211   output_asm_insn ("sllx\t%H2, 32, %H3", operands);
 212   output_asm_insn ("or\t%L2, %H3, %H3", operands);
 213   output_asm_insn ("casx\t%1, %H3, %L3", operands);
 214   return "srlx\t%L3, 32, %H3";
 215 }
 216   [(set_attr "type" "multi")
 217    (set_attr "length" "8")])
 218
 219 (define_expand "atomic_exchangesi"
 220   [(match_operand:SI 0 "register_operand" "")
 221    (match_operand:SI 1 "memory_operand" "")
 222    (match_operand:SI 2 "register_operand" "")
 223    (match_operand:SI 3 "const_int_operand" "")]
 224   "(TARGET_V8 || TARGET_V9) && !sparc_fix_ut699"
 225 {
 226   enum memmodel model = (enum memmodel) INTVAL (operands[3]);
 227
 228   sparc_emit_membar_for_model (model, 3, 1);
 229   emit_insn (gen_swapsi (operands[0], operands[1], operands[2]));
 230   sparc_emit_membar_for_model (model, 3, 2);
 231   DONE;
 232 })
 233
 234 (define_insn "swapsi"
 235   [(set (match_operand:SI 0 "register_operand" "=r")
 236         (unspec_volatile:SI [(match_operand:SI 1 "memory_operand" "+m")]
 237                             UNSPECV_SWAP))
 238    (set (match_dup 1)
 239         (match_operand:SI 2 "register_operand" "0"))]
 240   "(TARGET_V8 || TARGET_V9) && !sparc_fix_ut699"
 241   "swap\t%1, %0"
 242   [(set_attr "type" "multi")])
 243
 244 (define_expand "atomic_test_and_set"
 245   [(match_operand:QI 0 "register_operand" "")
 246    (match_operand:QI 1 "memory_operand" "")
 247    (match_operand:SI 2 "const_int_operand" "")]
 248   "!sparc_fix_ut699"
 249 {
 250   enum memmodel model = (enum memmodel) INTVAL (operands[2]);
 251   rtx ret;
 252
 253   sparc_emit_membar_for_model (model, 3, 1);
 254   emit_insn (gen_ldstub (operands[0], operands[1]));
 255   sparc_emit_membar_for_model (model, 3, 2);
 256
 257   /* Convert the 0/0xff result we would otherwise have to a boolean.
 258      I.e. ignore all but bit 0.  */
 259   ret = expand_simple_binop (QImode, AND, operands[0], const1_rtx,
 260                              operands[0], true, OPTAB_LIB_WIDEN);
 261   if (ret != operands[0])
 262     emit_move_insn (operands[0], ret);
 263
 264   DONE;
 265 })
 266
 267 (define_insn "ldstub"
 268   [(set (match_operand:QI 0 "register_operand" "=r")
 269         (unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "+m")]
 270                             UNSPECV_LDSTUB))
 271    (set (match_dup 1) (const_int -1))]
 272   "!sparc_fix_ut699"
 273   "ldstub\t%1, %0"
 274   [(set_attr "type" "multi")])