gcc/config/sparc/sync.md

   1 ;; GCC machine description for SPARC synchronization instructions.
   2 ;; Copyright (C) 2005, 2007, 2009, 2010, 2011
   3 ;; Free Software Foundation, Inc.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify
   8 ;; it under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful,
  13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ;; GNU General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 (define_mode_iterator I12MODE [QI HI])
  22 (define_mode_iterator I124MODE [QI HI SI])
  23 (define_mode_iterator I24MODE [HI SI])
  24 (define_mode_iterator I48MODE [SI (DI "TARGET_ARCH64 || TARGET_V8PLUS")])
  25 (define_mode_attr modesuffix [(SI "") (DI "x")])
  26
  27 (define_expand "mem_thread_fence"
  28   [(match_operand:SI 0 "const_int_operand")]
  29   "TARGET_V8 || TARGET_V9"
  30 {
  31   enum memmodel model = (enum memmodel) INTVAL (operands[0]);
  32   sparc_emit_membar_for_model (model, 3, 3);
  33   DONE;
  34 })
  35
  36 (define_expand "membar"
  37   [(set (match_dup 1)
  38         (unspec:BLK [(match_dup 1)
  39                      (match_operand:SI 0 "const_int_operand")]
  40                     UNSPEC_MEMBAR))]
  41   "TARGET_V8 || TARGET_V9"
  42 {
  43   operands[1] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
  44   MEM_VOLATILE_P (operands[1]) = 1;
  45 })
  46
  47 ;; A compiler-only memory barrier.  Generic code, when checking for the
  48 ;; existance of various named patterns, uses asm("":::"memory") when we
  49 ;; don't need an actual instruction.  Here, it's easiest to pretend that
  50 ;; membar 0 is such a barrier.  Further, this gives us a nice hook to
  51 ;; ignore all such barriers on Sparc V7.
  52 (define_insn "*membar_empty"
  53   [(set (match_operand:BLK 0 "" "")
  54         (unspec:BLK [(match_dup 0) (match_operand:SI 1 "zero_or_v7_operand")]
  55                     UNSPEC_MEMBAR))]
  56   ""
  57   ""
  58   [(set_attr "type" "multi")
  59    (set_attr "length" "0")])
  60
  61 ;; For V8, STBAR is exactly membar #StoreStore, by definition.
  62 (define_insn "*membar_storestore"
  63   [(set (match_operand:BLK 0 "" "")
  64         (unspec:BLK [(match_dup 0) (const_int 8)] UNSPEC_MEMBAR))]
  65   "TARGET_V8"
  66   "stbar"
  67   [(set_attr "type" "multi")])
  68
  69 ;; For V8, LDSTUB has the effect of membar #StoreLoad
  70 (define_insn "*membar_storeload"
  71   [(set (match_operand:BLK 0 "" "")
  72         (unspec:BLK [(match_dup 0) (const_int 2)] UNSPEC_MEMBAR))]
  73   "TARGET_V8"
  74   "ldstub\t[%%sp-1], %%g0"
  75   [(set_attr "type" "multi")])
  76
  77 ;; Put the two together, in combination with the fact that V8 implements PSO
  78 ;; as its weakest memory model, means a full barrier.  Match all remaining
  79 ;; instances of the membar pattern for Sparc V8.
  80 (define_insn "*membar_v8"
  81   [(set (match_operand:BLK 0 "" "")
  82         (unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")]
  83                     UNSPEC_MEMBAR))]
  84   "TARGET_V8"
  85   "stbar\n\tldstub\t[%%sp-1], %%g0"
  86   [(set_attr "type" "multi")
  87    (set_attr "length" "2")])
  88
  89 ;; For V9, we have the full membar instruction.
  90 (define_insn "*membar"
  91   [(set (match_operand:BLK 0 "" "")
  92         (unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")]
  93                     UNSPEC_MEMBAR))]
  94   "TARGET_V9"
  95   "membar\t%1"
  96   [(set_attr "type" "multi")])
  97
  98 (define_expand "atomic_load<mode>"
  99   [(match_operand:I 0 "register_operand" "")
 100    (match_operand:I 1 "memory_operand" "")
 101    (match_operand:SI 2 "const_int_operand" "")]
 102   ""
 103 {
 104   enum memmodel model = (enum memmodel) INTVAL (operands[2]);
 105
 106   sparc_emit_membar_for_model (model, 1, 1);
 107
 108   if (TARGET_ARCH64 || <MODE>mode != DImode)
 109     emit_move_insn (operands[0], operands[1]);
 110   else
 111     emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
 112
 113   sparc_emit_membar_for_model (model, 1, 2);
 114   DONE;
 115 })
 116
 117 (define_insn "atomic_loaddi_1"
 118   [(set (match_operand:DI 0 "register_operand" "=U,?*f")
 119         (unspec:DI [(match_operand:DI 1 "memory_operand" "m,m")]
 120                    UNSPEC_ATOMIC))]
 121   "!TARGET_ARCH64"
 122   "ldd\t%1, %0"
 123   [(set_attr "type" "load,fpload")])
 124
 125 (define_expand "atomic_store<mode>"
 126   [(match_operand:I 0 "register_operand" "")
 127    (match_operand:I 1 "memory_operand" "")
 128    (match_operand:SI 2 "const_int_operand" "")]
 129   ""
 130 {
 131   enum memmodel model = (enum memmodel) INTVAL (operands[2]);
 132
 133   sparc_emit_membar_for_model (model, 2, 1);
 134
 135   if (TARGET_ARCH64 || <MODE>mode != DImode)
 136     emit_move_insn (operands[0], operands[1]);
 137   else
 138     emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
 139
 140   sparc_emit_membar_for_model (model, 2, 2);
 141   DONE;
 142 })
 143
 144 (define_insn "atomic_storedi_1"
 145   [(set (match_operand:DI 0 "memory_operand" "=m,m,m")
 146         (unspec:DI
 147           [(match_operand:DI 1 "register_or_v9_zero_operand" "J,U,?*f")]
 148           UNSPEC_ATOMIC))]
 149   "!TARGET_ARCH64"
 150   "@
 151    stx\t%r1, %0
 152    std\t%1, %0
 153    std\t%1, %0"
 154   [(set_attr "type" "store,store,fpstore")
 155    (set_attr "cpu_feature" "v9,*,*")])
 156
 157 (define_expand "atomic_compare_and_swap<mode>"
 158   [(match_operand:SI 0 "register_operand" "")           ;; bool output
 159    (match_operand:I 1 "register_operand" "")            ;; val output
 160    (match_operand:I 2 "mem_noofs_operand" "")           ;; memory
 161    (match_operand:I 3 "register_operand" "")            ;; expected
 162    (match_operand:I 4 "register_operand" "")            ;; desired
 163    (match_operand:SI 5 "const_int_operand" "")          ;; is_weak
 164    (match_operand:SI 6 "const_int_operand" "")          ;; mod_s
 165    (match_operand:SI 7 "const_int_operand" "")]         ;; mod_f
 166   "TARGET_V9 && (<MODE>mode != DImode || TARGET_ARCH64 || TARGET_V8PLUS)"
 167 {
 168   sparc_expand_compare_and_swap (operands);
 169   DONE;
 170 })
 171
 172 (define_expand "atomic_compare_and_swap<mode>_1"
 173   [(parallel
 174      [(set (match_operand:I48MODE 0 "register_operand" "")
 175            (match_operand:I48MODE 1 "mem_noofs_operand" ""))
 176       (set (match_dup 1)
 177            (unspec_volatile:I48MODE
 178              [(match_operand:I48MODE 2 "register_operand" "")
 179               (match_operand:I48MODE 3 "register_operand" "")]
 180              UNSPECV_CAS))])]
 181   "TARGET_V9"
 182   "")
 183
 184 (define_insn "*atomic_compare_and_swap<mode>_1"
 185   [(set (match_operand:I48MODE 0 "register_operand" "=r")
 186         (match_operand:I48MODE 1 "mem_noofs_operand" "+w"))
 187    (set (match_dup 1)
 188         (unspec_volatile:I48MODE
 189           [(match_operand:I48MODE 2 "register_operand" "r")
 190            (match_operand:I48MODE 3 "register_operand" "0")]
 191           UNSPECV_CAS))]
 192   "TARGET_V9 && (<MODE>mode == SImode || TARGET_ARCH64)"
 193   "cas<modesuffix>\t%1, %2, %0"
 194   [(set_attr "type" "multi")])
 195
 196 (define_insn "*atomic_compare_and_swapdi_v8plus"
 197   [(set (match_operand:DI 0 "register_operand" "=h")
 198         (match_operand:DI 1 "mem_noofs_operand" "+w"))
 199    (set (match_dup 1)
 200         (unspec_volatile:DI
 201           [(match_operand:DI 2 "register_operand" "h")
 202            (match_operand:DI 3 "register_operand" "0")]
 203           UNSPECV_CAS))]
 204   "TARGET_V8PLUS"
 205 {
 206   if (sparc_check_64 (operands[3], insn) <= 0)
 207     output_asm_insn ("srl\t%L3, 0, %L3", operands);
 208   output_asm_insn ("sllx\t%H3, 32, %H3", operands);
 209   output_asm_insn ("or\t%L3, %H3, %L3", operands);
 210   if (sparc_check_64 (operands[2], insn) <= 0)
 211     output_asm_insn ("srl\t%L2, 0, %L2", operands);
 212   output_asm_insn ("sllx\t%H2, 32, %H3", operands);
 213   output_asm_insn ("or\t%L2, %H3, %H3", operands);
 214   output_asm_insn ("casx\t%1, %H3, %L3", operands);
 215   return "srlx\t%L3, 32, %H3";
 216 }
 217   [(set_attr "type" "multi")
 218    (set_attr "length" "8")])
 219
 220 (define_expand "atomic_exchangesi"
 221   [(match_operand:SI 0 "register_operand" "")
 222    (match_operand:SI 1 "memory_operand" "")
 223    (match_operand:SI 2 "register_operand" "")
 224    (match_operand:SI 3 "const_int_operand" "")]
 225   "TARGET_V8 || TARGET_V9"
 226 {
 227   enum memmodel model = (enum memmodel) INTVAL (operands[3]);
 228
 229   sparc_emit_membar_for_model (model, 3, 1);
 230   emit_insn (gen_swapsi (operands[0], operands[1], operands[2]));
 231   sparc_emit_membar_for_model (model, 3, 2);
 232   DONE;
 233 })
 234
 235 (define_insn "swapsi"
 236   [(set (match_operand:SI 0 "register_operand" "=r")
 237         (unspec_volatile:SI [(match_operand:SI 1 "memory_operand" "+m")]
 238                             UNSPECV_SWAP))
 239    (set (match_dup 1)
 240         (match_operand:SI 2 "register_operand" "0"))]
 241   "TARGET_V8 || TARGET_V9"
 242   "swap\t%1, %0"
 243   [(set_attr "type" "multi")])
 244
 245 (define_expand "atomic_test_and_set"
 246   [(match_operand:QI 0 "register_operand" "")
 247    (match_operand:QI 1 "memory_operand" "")
 248    (match_operand:SI 2 "const_int_operand" "")]
 249   ""
 250 {
 251   enum memmodel model = (enum memmodel) INTVAL (operands[2]);
 252   rtx ret;
 253
 254   sparc_emit_membar_for_model (model, 3, 1);
 255   emit_insn (gen_ldstub (operands[0], operands[1]));
 256   sparc_emit_membar_for_model (model, 3, 2);
 257
 258   /* Convert the 0/0xff result we would otherwise have to a boolean.
 259      I.e. ignore all but bit 0.  */
 260   ret = expand_simple_binop (QImode, AND, operands[0], const1_rtx,
 261                              operands[0], true, OPTAB_LIB_WIDEN);
 262   if (ret != operands[0])
 263     emit_move_insn (operands[0], ret);
 264
 265   DONE;
 266 })
 267
 268 (define_insn "ldstub"
 269   [(set (match_operand:QI 0 "register_operand" "=r")
 270         (unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "+m")]
 271                             UNSPECV_LDSTUB))
 272    (set (match_dup 1) (const_int -1))]
 273   ""
 274   "ldstub\t%1, %0"
 275   [(set_attr "type" "multi")])