gcc/config/sparc/sync.md

   1 ;; GCC machine description for SPARC synchronization instructions.
   2 ;; Copyright (C) 2005, 2007, 2009, 2010
   3 ;; Free Software Foundation, Inc.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify
   8 ;; it under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful,
  13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ;; GNU General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 (define_mode_iterator I12MODE [QI HI])
  22 (define_mode_iterator I24MODE [HI SI])
  23 (define_mode_iterator I48MODE [SI (DI "TARGET_ARCH64 || TARGET_V8PLUS")])
  24 (define_mode_attr modesuffix [(SI "") (DI "x")])
  25
  26 (define_expand "memory_barrier"
  27   [(set (match_dup 0)
  28         (unspec:BLK [(match_dup 0)] UNSPEC_MEMBAR))]
  29   "TARGET_V8 || TARGET_V9"
  30 {
  31   operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
  32   MEM_VOLATILE_P (operands[0]) = 1;
  33 })
  34
  35 ;; In V8, loads are blocking and ordered wrt earlier loads, i.e. every load
  36 ;; is virtually followed by a load barrier (membar #LoadStore | #LoadLoad).
  37 ;; In PSO, stbar orders the stores (membar #StoreStore).
  38 ;; In TSO, ldstub orders the stores wrt subsequent loads (membar #StoreLoad).
  39 ;; The combination of the three yields a full memory barrier in all cases.
  40 (define_insn "*membar_v8"
  41   [(set (match_operand:BLK 0 "" "")
  42         (unspec:BLK [(match_dup 0)] UNSPEC_MEMBAR))]
  43   "TARGET_V8"
  44   "stbar\n\tldstub\t[%%sp-1], %%g0"
  45   [(set_attr "type" "multi")
  46    (set_attr "length" "2")])
  47
  48 ;; membar #StoreStore | #LoadStore | #StoreLoad | #LoadLoad
  49 (define_insn "*membar"
  50   [(set (match_operand:BLK 0 "" "")
  51         (unspec:BLK [(match_dup 0)] UNSPEC_MEMBAR))]
  52   "TARGET_V9"
  53   "membar\t15"
  54   [(set_attr "type" "multi")])
  55
  56 (define_expand "sync_compare_and_swap<mode>"
  57   [(match_operand:I12MODE 0 "register_operand" "")
  58    (match_operand:I12MODE 1 "memory_operand" "")
  59    (match_operand:I12MODE 2 "register_operand" "")
  60    (match_operand:I12MODE 3 "register_operand" "")]
  61   "TARGET_V9"
  62 {
  63   sparc_expand_compare_and_swap_12 (operands[0], operands[1],
  64                                     operands[2], operands[3]);
  65   DONE;
  66 })
  67
  68 (define_expand "sync_compare_and_swap<mode>"
  69   [(parallel
  70      [(set (match_operand:I48MODE 0 "register_operand" "")
  71            (match_operand:I48MODE 1 "memory_operand" ""))
  72       (set (match_dup 1)
  73            (unspec_volatile:I48MODE
  74              [(match_operand:I48MODE 2 "register_operand" "")
  75               (match_operand:I48MODE 3 "register_operand" "")]
  76              UNSPECV_CAS))])]
  77   "TARGET_V9"
  78 {
  79   if (!REG_P (XEXP (operands[1], 0)))
  80     {
  81       rtx addr = force_reg (Pmode, XEXP (operands[1], 0));
  82       operands[1] = replace_equiv_address (operands[1], addr);
  83     }
  84   emit_insn (gen_memory_barrier ());
  85 })
  86
  87 (define_insn "*sync_compare_and_swap<mode>"
  88   [(set (match_operand:I48MODE 0 "register_operand" "=r")
  89         (mem:I48MODE (match_operand 1 "register_operand" "r")))
  90    (set (mem:I48MODE (match_dup 1))
  91         (unspec_volatile:I48MODE
  92           [(match_operand:I48MODE 2 "register_operand" "r")
  93            (match_operand:I48MODE 3 "register_operand" "0")]
  94           UNSPECV_CAS))]
  95   "TARGET_V9 && (<MODE>mode == SImode || TARGET_ARCH64)"
  96   "cas<modesuffix>\t[%1], %2, %0"
  97   [(set_attr "type" "multi")])
  98
  99 (define_insn "*sync_compare_and_swapdi_v8plus"
 100   [(set (match_operand:DI 0 "register_operand" "=h")
 101         (mem:DI (match_operand 1 "register_operand" "r")))
 102    (set (mem:DI (match_dup 1))
 103         (unspec_volatile:DI
 104           [(match_operand:DI 2 "register_operand" "h")
 105            (match_operand:DI 3 "register_operand" "0")]
 106           UNSPECV_CAS))]
 107   "TARGET_V8PLUS"
 108 {
 109   if (sparc_check_64 (operands[3], insn) <= 0)
 110     output_asm_insn ("srl\t%L3, 0, %L3", operands);
 111   output_asm_insn ("sllx\t%H3, 32, %H3", operands);
 112   output_asm_insn ("or\t%L3, %H3, %L3", operands);
 113   if (sparc_check_64 (operands[2], insn) <= 0)
 114     output_asm_insn ("srl\t%L2, 0, %L2", operands);
 115   output_asm_insn ("sllx\t%H2, 32, %H3", operands);
 116   output_asm_insn ("or\t%L2, %H3, %H3", operands);
 117   output_asm_insn ("casx\t[%1], %H3, %L3", operands);
 118   return "srlx\t%L3, 32, %H3";
 119 }
 120   [(set_attr "type" "multi")
 121    (set_attr "length" "8")])
 122
 123 (define_expand "sync_lock_test_and_set<mode>"
 124   [(match_operand:I12MODE 0 "register_operand" "")
 125    (match_operand:I12MODE 1 "memory_operand" "")
 126    (match_operand:I12MODE 2 "arith_operand" "")]
 127   "!TARGET_V9"
 128 {
 129   if (operands[2] != const1_rtx)
 130     FAIL;
 131   if (TARGET_V8)
 132     emit_insn (gen_memory_barrier ());
 133   if (<MODE>mode != QImode)
 134     operands[1] = adjust_address (operands[1], QImode, 0);
 135   emit_insn (gen_ldstub<mode> (operands[0], operands[1]));
 136   DONE;
 137 })
 138
 139 (define_expand "sync_lock_test_and_setsi"
 140   [(parallel
 141      [(set (match_operand:SI 0 "register_operand" "")
 142            (unspec_volatile:SI [(match_operand:SI 1 "memory_operand" "")]
 143                                UNSPECV_SWAP))
 144       (set (match_dup 1)
 145            (match_operand:SI 2 "arith_operand" ""))])]
 146   ""
 147 {
 148   if (! TARGET_V8 && ! TARGET_V9)
 149     {
 150       if (operands[2] != const1_rtx)
 151         FAIL;
 152       operands[1] = adjust_address (operands[1], QImode, 0);
 153       emit_insn (gen_ldstubsi (operands[0], operands[1]));
 154       DONE;
 155     }
 156   emit_insn (gen_memory_barrier ());
 157   operands[2] = force_reg (SImode, operands[2]);
 158 })
 159
 160 (define_insn "*swapsi"
 161   [(set (match_operand:SI 0 "register_operand" "=r")
 162         (unspec_volatile:SI [(match_operand:SI 1 "memory_operand" "+m")]
 163                             UNSPECV_SWAP))
 164    (set (match_dup 1)
 165         (match_operand:SI 2 "register_operand" "0"))]
 166   "TARGET_V8 || TARGET_V9"
 167   "swap\t%1, %0"
 168   [(set_attr "type" "multi")])
 169
 170 (define_expand "ldstubqi"
 171   [(parallel [(set (match_operand:QI 0 "register_operand" "")
 172                    (unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "")]
 173                                        UNSPECV_LDSTUB))
 174               (set (match_dup 1) (const_int -1))])]
 175   ""
 176   "")
 177
 178 (define_expand "ldstub<mode>"
 179   [(parallel [(set (match_operand:I24MODE 0 "register_operand" "")
 180                    (zero_extend:I24MODE
 181                       (unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "")]
 182                                           UNSPECV_LDSTUB)))
 183               (set (match_dup 1) (const_int -1))])]
 184   ""
 185   "")
 186
 187 (define_insn "*ldstubqi"
 188   [(set (match_operand:QI 0 "register_operand" "=r")
 189         (unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "+m")]
 190                             UNSPECV_LDSTUB))
 191    (set (match_dup 1) (const_int -1))]
 192   ""
 193   "ldstub\t%1, %0"
 194   [(set_attr "type" "multi")])
 195
 196 (define_insn "*ldstub<mode>"
 197   [(set (match_operand:I24MODE 0 "register_operand" "=r")
 198         (zero_extend:I24MODE
 199           (unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "+m")]
 200                               UNSPECV_LDSTUB)))
 201    (set (match_dup 1) (const_int -1))]
 202   ""
 203   "ldstub\t%1, %0"
 204   [(set_attr "type" "multi")])