gcc/config/sparc/sync.md

   1 ;; GCC machine description for SPARC synchronization instructions.
   2 ;; Copyright (C) 2005-2014 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5 ;;
   6 ;; GCC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 3, or (at your option)
   9 ;; any later version.
  10 ;;
  11 ;; GCC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.
  19
  20 (define_mode_iterator I12MODE [QI HI])
  21 (define_mode_iterator I124MODE [QI HI SI])
  22 (define_mode_iterator I24MODE [HI SI])
  23 (define_mode_iterator I48MODE [SI (DI "TARGET_ARCH64 || TARGET_V8PLUS")])
  24 (define_mode_attr modesuffix [(SI "") (DI "x")])
  25
  26 (define_expand "mem_thread_fence"
  27   [(match_operand:SI 0 "const_int_operand")]
  28   "TARGET_V8 || TARGET_V9"
  29 {
  30   enum memmodel model = (enum memmodel) INTVAL (operands[0]);
  31   sparc_emit_membar_for_model (model, 3, 3);
  32   DONE;
  33 })
  34
  35 (define_expand "membar"
  36   [(set (match_dup 1)
  37         (unspec:BLK [(match_dup 1) (match_operand:SI 0 "const_int_operand")]
  38                     UNSPEC_MEMBAR))]
  39   "TARGET_V8 || TARGET_V9"
  40 {
  41   operands[1] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
  42   MEM_VOLATILE_P (operands[1]) = 1;
  43 })
  44
  45 ;; A compiler-only memory barrier.  Generic code, when checking for the
  46 ;; existence of various named patterns, uses asm("":::"memory") when we
  47 ;; don't need an actual instruction.  Here, it's easiest to pretend that
  48 ;; membar 0 is such a barrier.  Further, this gives us a nice hook to
  49 ;; ignore all such barriers on Sparc V7.
  50 (define_insn "*membar_empty"
  51   [(set (match_operand:BLK 0 "" "")
  52         (unspec:BLK [(match_dup 0) (match_operand:SI 1 "zero_or_v7_operand")]
  53                     UNSPEC_MEMBAR))]
  54   ""
  55   ""
  56   [(set_attr "type" "multi")
  57    (set_attr "length" "0")])
  58
  59 ;; For V8, STBAR is exactly membar #StoreStore, by definition.
  60 (define_insn "*membar_storestore"
  61   [(set (match_operand:BLK 0 "" "")
  62         (unspec:BLK [(match_dup 0) (const_int 8)] UNSPEC_MEMBAR))]
  63   "TARGET_V8"
  64   "stbar"
  65   [(set_attr "type" "multi")])
  66
  67 ;; For V8, LDSTUB has the effect of membar #StoreLoad.
  68 (define_insn "*membar_storeload"
  69   [(set (match_operand:BLK 0 "" "")
  70         (unspec:BLK [(match_dup 0) (const_int 2)] UNSPEC_MEMBAR))]
  71   "TARGET_V8"
  72   "ldstub\t[%%sp-1], %%g0"
  73   [(set_attr "type" "multi")])
  74
  75 ;; Put the two together, in combination with the fact that V8 implements PSO
  76 ;; as its weakest memory model, means a full barrier.  Match all remaining
  77 ;; instances of the membar pattern for Sparc V8.
  78 (define_insn "*membar_v8"
  79   [(set (match_operand:BLK 0 "" "")
  80         (unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")]
  81                     UNSPEC_MEMBAR))]
  82   "TARGET_V8"
  83   "stbar\n\tldstub\t[%%sp-1], %%g0"
  84   [(set_attr "type" "multi")
  85    (set_attr "length" "2")])
  86
  87 ;; For V9, we have the full membar instruction.
  88 (define_insn "*membar"
  89   [(set (match_operand:BLK 0 "" "")
  90         (unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")]
  91                     UNSPEC_MEMBAR))]
  92   "TARGET_V9"
  93   "membar\t%1"
  94   [(set_attr "type" "multi")])
  95
  96 (define_peephole2
  97   [(set (match_operand:BLK 0 "" "")
  98         (unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")]
  99                     UNSPEC_MEMBAR))
 100    (set (match_operand:BLK 2 "" "")
 101         (unspec:BLK [(match_dup 2) (match_operand:SI 3 "const_int_operand")]
 102                     UNSPEC_MEMBAR))]
 103   ""
 104   [(set (match_operand:BLK 0 "" "")
 105         (unspec:BLK [(match_dup 0) (match_dup 1)] UNSPEC_MEMBAR))]
 106 { operands[1] = GEN_INT (UINTVAL (operands[1]) | UINTVAL (operands[3])); })
 107
 108 (define_expand "atomic_load<mode>"
 109   [(match_operand:I 0 "register_operand" "")
 110    (match_operand:I 1 "memory_operand" "")
 111    (match_operand:SI 2 "const_int_operand" "")]
 112   ""
 113 {
 114   enum memmodel model = (enum memmodel) INTVAL (operands[2]);
 115
 116   sparc_emit_membar_for_model (model, 1, 1);
 117
 118   if (TARGET_ARCH64 || <MODE>mode != DImode)
 119     emit_move_insn (operands[0], operands[1]);
 120   else
 121     emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
 122
 123   sparc_emit_membar_for_model (model, 1, 2);
 124   DONE;
 125 })
 126
 127 (define_insn "atomic_loaddi_1"
 128   [(set (match_operand:DI 0 "register_operand" "=U,?*f")
 129         (unspec:DI [(match_operand:DI 1 "memory_operand" "m,m")]
 130                    UNSPEC_ATOMIC))]
 131   "!TARGET_ARCH64"
 132   "ldd\t%1, %0"
 133   [(set_attr "type" "load,fpload")])
 134
 135 (define_expand "atomic_store<mode>"
 136   [(match_operand:I 0 "memory_operand" "")
 137    (match_operand:I 1 "register_operand" "")
 138    (match_operand:SI 2 "const_int_operand" "")]
 139   ""
 140 {
 141   enum memmodel model = (enum memmodel) INTVAL (operands[2]);
 142
 143   sparc_emit_membar_for_model (model, 2, 1);
 144
 145   if (TARGET_ARCH64 || <MODE>mode != DImode)
 146     emit_move_insn (operands[0], operands[1]);
 147   else
 148     emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
 149
 150   sparc_emit_membar_for_model (model, 2, 2);
 151   DONE;
 152 })
 153
 154 (define_insn "atomic_storedi_1"
 155   [(set (match_operand:DI 0 "memory_operand" "=m,m,m")
 156         (unspec:DI
 157           [(match_operand:DI 1 "register_or_v9_zero_operand" "J,U,?*f")]
 158           UNSPEC_ATOMIC))]
 159   "!TARGET_ARCH64"
 160   "@
 161    stx\t%r1, %0
 162    std\t%1, %0
 163    std\t%1, %0"
 164   [(set_attr "type" "store,store,fpstore")
 165    (set_attr "cpu_feature" "v9,*,*")])
 166
 167 (define_expand "atomic_compare_and_swap<mode>"
 168   [(match_operand:SI 0 "register_operand" "")           ;; bool output
 169    (match_operand:I 1 "register_operand" "")            ;; val output
 170    (match_operand:I 2 "mem_noofs_operand" "")           ;; memory
 171    (match_operand:I 3 "register_operand" "")            ;; expected
 172    (match_operand:I 4 "register_operand" "")            ;; desired
 173    (match_operand:SI 5 "const_int_operand" "")          ;; is_weak
 174    (match_operand:SI 6 "const_int_operand" "")          ;; mod_s
 175    (match_operand:SI 7 "const_int_operand" "")]         ;; mod_f
 176   "(TARGET_V9 || TARGET_LEON3)
 177    && (<MODE>mode != DImode || TARGET_ARCH64 || TARGET_V8PLUS)"
 178 {
 179   sparc_expand_compare_and_swap (operands);
 180   DONE;
 181 })
 182
 183 (define_expand "atomic_compare_and_swap<mode>_1"
 184   [(parallel
 185      [(set (match_operand:I48MODE 0 "register_operand" "")
 186            (match_operand:I48MODE 1 "mem_noofs_operand" ""))
 187       (set (match_dup 1)
 188            (unspec_volatile:I48MODE
 189              [(match_operand:I48MODE 2 "register_operand" "")
 190               (match_operand:I48MODE 3 "register_operand" "")]
 191              UNSPECV_CAS))])]
 192   "TARGET_V9 || TARGET_LEON3"
 193   "")
 194
 195 (define_insn "*atomic_compare_and_swap<mode>_1"
 196   [(set (match_operand:I48MODE 0 "register_operand" "=r")
 197         (match_operand:I48MODE 1 "mem_noofs_operand" "+w"))
 198    (set (match_dup 1)
 199         (unspec_volatile:I48MODE
 200           [(match_operand:I48MODE 2 "register_operand" "r")
 201            (match_operand:I48MODE 3 "register_operand" "0")]
 202           UNSPECV_CAS))]
 203   "TARGET_V9 && (<MODE>mode != DImode || TARGET_ARCH64)"
 204   "cas<modesuffix>\t%1, %2, %0"
 205   [(set_attr "type" "multi")])
 206
 207 (define_insn "*atomic_compare_and_swap_leon3_1"
 208   [(set (match_operand:SI 0 "register_operand" "=r")
 209         (match_operand:SI 1 "mem_noofs_operand" "+w"))
 210    (set (match_dup 1)
 211         (unspec_volatile:SI
 212           [(match_operand:SI 2 "register_operand" "r")
 213            (match_operand:SI 3 "register_operand" "0")]
 214           UNSPECV_CAS))]
 215   "TARGET_LEON3"
 216 {
 217   if (TARGET_USER_MODE)
 218     return "casa\t%1 0xa, %2, %0"; /* ASI for user data space.  */
 219   else
 220     return "casa\t%1 0xb, %2, %0"; /* ASI for supervisor data space.  */
 221 }
 222   [(set_attr "type" "multi")])
 223
 224 (define_insn "*atomic_compare_and_swapdi_v8plus"
 225   [(set (match_operand:DI 0 "register_operand" "=h")
 226         (match_operand:DI 1 "mem_noofs_operand" "+w"))
 227    (set (match_dup 1)
 228         (unspec_volatile:DI
 229           [(match_operand:DI 2 "register_operand" "h")
 230            (match_operand:DI 3 "register_operand" "0")]
 231           UNSPECV_CAS))]
 232   "TARGET_V8PLUS"
 233 {
 234   if (sparc_check_64 (operands[3], insn) <= 0)
 235     output_asm_insn ("srl\t%L3, 0, %L3", operands);
 236   output_asm_insn ("sllx\t%H3, 32, %H3", operands);
 237   output_asm_insn ("or\t%L3, %H3, %L3", operands);
 238   if (sparc_check_64 (operands[2], insn) <= 0)
 239     output_asm_insn ("srl\t%L2, 0, %L2", operands);
 240   output_asm_insn ("sllx\t%H2, 32, %H3", operands);
 241   output_asm_insn ("or\t%L2, %H3, %H3", operands);
 242   output_asm_insn ("casx\t%1, %H3, %L3", operands);
 243   return "srlx\t%L3, 32, %H3";
 244 }
 245   [(set_attr "type" "multi")
 246    (set_attr "length" "8")])
 247
 248 (define_expand "atomic_exchangesi"
 249   [(match_operand:SI 0 "register_operand" "")
 250    (match_operand:SI 1 "memory_operand" "")
 251    (match_operand:SI 2 "register_operand" "")
 252    (match_operand:SI 3 "const_int_operand" "")]
 253   "(TARGET_V8 || TARGET_V9) && !sparc_fix_ut699"
 254 {
 255   enum memmodel model = (enum memmodel) INTVAL (operands[3]);
 256
 257   sparc_emit_membar_for_model (model, 3, 1);
 258   emit_insn (gen_swapsi (operands[0], operands[1], operands[2]));
 259   sparc_emit_membar_for_model (model, 3, 2);
 260   DONE;
 261 })
 262
 263 (define_insn "swapsi"
 264   [(set (match_operand:SI 0 "register_operand" "=r")
 265         (unspec_volatile:SI [(match_operand:SI 1 "memory_operand" "+m")]
 266                             UNSPECV_SWAP))
 267    (set (match_dup 1)
 268         (match_operand:SI 2 "register_operand" "0"))]
 269   "(TARGET_V8 || TARGET_V9) && !sparc_fix_ut699"
 270   "swap\t%1, %0"
 271   [(set_attr "type" "multi")])
 272
 273 (define_expand "atomic_test_and_set"
 274   [(match_operand:QI 0 "register_operand" "")
 275    (match_operand:QI 1 "memory_operand" "")
 276    (match_operand:SI 2 "const_int_operand" "")]
 277   "!sparc_fix_ut699"
 278 {
 279   enum memmodel model = (enum memmodel) INTVAL (operands[2]);
 280   rtx ret;
 281
 282   sparc_emit_membar_for_model (model, 3, 1);
 283   emit_insn (gen_ldstub (operands[0], operands[1]));
 284   sparc_emit_membar_for_model (model, 3, 2);
 285
 286   /* Convert the 0/0xff result we would otherwise have to a boolean.
 287      I.e. ignore all but bit 0.  */
 288   ret = expand_simple_binop (QImode, AND, operands[0], const1_rtx,
 289                              operands[0], true, OPTAB_LIB_WIDEN);
 290   if (ret != operands[0])
 291     emit_move_insn (operands[0], ret);
 292
 293   DONE;
 294 })
 295
 296 (define_insn "ldstub"
 297   [(set (match_operand:QI 0 "register_operand" "=r")
 298         (unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "+m")]
 299                             UNSPECV_LDSTUB))
 300    (set (match_dup 1) (const_int -1))]
 301   "!sparc_fix_ut699"
 302   "ldstub\t%1, %0"
 303   [(set_attr "type" "multi")])