gcc/config/v850/v850.md

   1 ;; GCC machine description for NEC V850
   2 ;; Copyright (C) 1996, 1997, 1998, 1999, 2002, 2004
   3 ;; Free Software Foundation, Inc.
   4 ;; Contributed by Jeff Law (law@cygnus.com).
   5
   6 ;; This file is part of GCC.
   7
   8 ;; GCC is free software; you can redistribute it and/or modify
   9 ;; it under the terms of the GNU General Public License as published by
  10 ;; the Free Software Foundation; either version 2, or (at your option)
  11 ;; any later version.
  12
  13 ;; GCC is distributed in the hope that it will be useful,
  14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 ;; GNU General Public License for more details.
  17
  18 ;; You should have received a copy of the GNU General Public License
  19 ;; along with GCC; see the file COPYING.  If not, write to
  20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
  21 ;; Boston, MA 02111-1307, USA.
  22
  23 ;; The original PO technology requires these to be ordered by speed,
  24 ;; so that assigner will pick the fastest.
  25
  26 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
  27
  28 ;; The V851 manual states that the instruction address space is 16M;
  29 ;; the various branch/call instructions only have a 22bit offset (4M range).
  30 ;;
  31 ;; One day we'll probably need to handle calls to targets more than 4M
  32 ;; away.
  33
  34 ;; The size of instructions in bytes.
  35
  36 (define_attr "length" ""
  37   (const_int 4))
  38
  39 (define_attr "long_calls" "yes,no"
  40   (const (if_then_else (symbol_ref "TARGET_LONG_CALLS")
  41                        (const_string "yes")
  42                        (const_string "no"))))
  43
  44 ;; Types of instructions (for scheduling purposes).
  45
  46 (define_attr "type" "load,mult,other"
  47   (const_string "other"))
  48
  49 ;; Condition code settings.
  50 ;; none - insn does not affect cc
  51 ;; none_0hit - insn does not affect cc but it does modify operand 0
  52 ;;      This attribute is used to keep track of when operand 0 changes.
  53 ;;      See the description of NOTICE_UPDATE_CC for more info.
  54 ;; set_znv - sets z,n,v to usable values; c is unknown.
  55 ;; set_zn  - sets z,n to usable values; v,c is unknown.
  56 ;; compare - compare instruction
  57 ;; clobber - value of cc is unknown
  58 (define_attr "cc" "none,none_0hit,set_zn,set_znv,compare,clobber"
  59   (const_string "clobber"))
  60 \f
  61 ;; Function units for the V850.  As best as I can tell, there's
  62 ;; a traditional memory load/use stall as well as a stall if
  63 ;; the result of a multiply is used too early.
  64
  65 (define_insn_reservation "v850_other" 1
  66                          (eq_attr "type" "other")
  67                          "nothing")
  68 (define_insn_reservation "v850_mult" 2
  69                          (eq_attr "type" "mult")
  70                          "nothing")
  71 (define_insn_reservation "v850_memory" 2
  72                          (eq_attr "type" "load")
  73                          "nothing")
  74 \f
  75 ;; ----------------------------------------------------------------------
  76 ;; MOVE INSTRUCTIONS
  77 ;; ----------------------------------------------------------------------
  78
  79 ;; movqi
  80
  81 (define_expand "movqi"
  82   [(set (match_operand:QI 0 "general_operand" "")
  83         (match_operand:QI 1 "general_operand" ""))]
  84   ""
  85   "
  86 {
  87   /* One of the ops has to be in a register or 0 */
  88   if (!register_operand (operand0, QImode)
  89       && !reg_or_0_operand (operand1, QImode))
  90     operands[1] = copy_to_mode_reg (QImode, operand1);
  91 }")
  92
  93 (define_insn "*movqi_internal"
  94   [(set (match_operand:QI 0 "general_operand" "=r,r,r,Q,r,m,m")
  95         (match_operand:QI 1 "general_operand" "Jr,n,Q,Ir,m,r,I"))]
  96   "register_operand (operands[0], QImode)
  97    || reg_or_0_operand (operands[1], QImode)"
  98   "* return output_move_single (operands);"
  99   [(set_attr "length" "2,4,2,2,4,4,4")
 100    (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
 101    (set_attr "type" "other,other,load,other,load,other,other")])
 102
 103 ;; movhi
 104
 105 (define_expand "movhi"
 106   [(set (match_operand:HI 0 "general_operand" "")
 107         (match_operand:HI 1 "general_operand" ""))]
 108   ""
 109   "
 110 {
 111   /* One of the ops has to be in a register or 0 */
 112   if (!register_operand (operand0, HImode)
 113       && !reg_or_0_operand (operand1, HImode))
 114     operands[1] = copy_to_mode_reg (HImode, operand1);
 115 }")
 116
 117 (define_insn "*movhi_internal"
 118   [(set (match_operand:HI 0 "general_operand" "=r,r,r,Q,r,m,m")
 119         (match_operand:HI 1 "general_operand" "Jr,n,Q,Ir,m,r,I"))]
 120   "register_operand (operands[0], HImode)
 121    || reg_or_0_operand (operands[1], HImode)"
 122   "* return output_move_single (operands);"
 123   [(set_attr "length" "2,4,2,2,4,4,4")
 124    (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
 125    (set_attr "type" "other,other,load,other,load,other,other")])
 126
 127 ;; movsi and helpers
 128
 129 (define_insn "*movsi_high"
 130   [(set (match_operand:SI 0 "register_operand" "=r")
 131         (high:SI (match_operand 1 "" "")))]
 132   ""
 133   "movhi hi(%1),%.,%0"
 134   [(set_attr "length" "4")
 135    (set_attr "cc" "none_0hit")
 136    (set_attr "type" "other")])
 137
 138 (define_insn "*movsi_lo"
 139   [(set (match_operand:SI 0 "register_operand" "=r")
 140         (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
 141                    (match_operand:SI 2 "immediate_operand" "i")))]
 142   ""
 143   "movea lo(%2),%1,%0"
 144   [(set_attr "length" "4")
 145    (set_attr "cc" "none_0hit")
 146    (set_attr "type" "other")])
 147
 148 (define_expand "movsi"
 149   [(set (match_operand:SI 0 "general_operand" "")
 150         (match_operand:SI 1 "general_operand" ""))]
 151   ""
 152   "
 153 {
 154   /* One of the ops has to be in a register or 0 */
 155   if (!register_operand (operand0, SImode)
 156       && !reg_or_0_operand (operand1, SImode))
 157     operands[1] = copy_to_mode_reg (SImode, operand1);
 158
 159   /* Some constants, as well as symbolic operands
 160      must be done with HIGH & LO_SUM patterns.  */
 161   if (CONSTANT_P (operands[1])
 162       && GET_CODE (operands[1]) != HIGH
 163       && ! TARGET_V850E
 164       && !special_symbolref_operand (operands[1], VOIDmode)
 165       && !(GET_CODE (operands[1]) == CONST_INT
 166            && (CONST_OK_FOR_J (INTVAL (operands[1]))
 167                || CONST_OK_FOR_K (INTVAL (operands[1]))
 168                || CONST_OK_FOR_L (INTVAL (operands[1])))))
 169     {
 170       rtx temp;
 171
 172       if (reload_in_progress || reload_completed)
 173         temp = operands[0];
 174       else
 175         temp = gen_reg_rtx (SImode);
 176
 177       emit_insn (gen_rtx_SET (SImode, temp,
 178                               gen_rtx_HIGH (SImode, operand1)));
 179       emit_insn (gen_rtx_SET (SImode, operand0,
 180                               gen_rtx_LO_SUM (SImode, temp, operand1)));
 181       DONE;
 182     }
 183 }")
 184
 185 ;; This is the same as the following pattern, except that it includes
 186 ;; support for arbitrary 32 bit immediates.
 187
 188 ;; ??? This always loads addresses using hilo.  If the only use of this address
 189 ;; was in a load/store, then we would get smaller code if we only loaded the
 190 ;; upper part with hi, and then put the lower part in the load/store insn.
 191
 192 (define_insn "*movsi_internal_v850e"
 193   [(set (match_operand:SI 0 "general_operand" "=r,r,r,r,Q,r,r,m,m,r")
 194         (match_operand:SI 1 "general_operand" "Jr,K,L,Q,Ir,m,R,r,I,i"))]
 195   "TARGET_V850E
 196    && (register_operand (operands[0], SImode)
 197        || reg_or_0_operand (operands[1], SImode))"
 198   "* return output_move_single (operands);"
 199   [(set_attr "length" "2,4,4,2,2,4,4,4,4,6")
 200    (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
 201    (set_attr "type" "other,other,other,load,other,load,other,other,other,other")])
 202
 203 (define_insn "*movsi_internal"
 204   [(set (match_operand:SI 0 "general_operand" "=r,r,r,r,Q,r,r,m,m")
 205         (match_operand:SI 1 "movsi_source_operand" "Jr,K,L,Q,Ir,m,R,r,I"))]
 206   "register_operand (operands[0], SImode)
 207    || reg_or_0_operand (operands[1], SImode)"
 208   "* return output_move_single (operands);"
 209   [(set_attr "length" "2,4,4,2,2,4,4,4,4")
 210    (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
 211    (set_attr "type" "other,other,other,load,other,load,other,other,other")])
 212
 213
 214
 215 (define_expand "movdi"
 216   [(set (match_operand:DI 0 "general_operand" "")
 217         (match_operand:DI 1 "general_operand" ""))]
 218   ""
 219   "
 220 {
 221   /* One of the ops has to be in a register or 0 */
 222   if (!register_operand (operand0, DImode)
 223       && !reg_or_0_operand (operand1, DImode))
 224     operands[1] = copy_to_mode_reg (DImode, operand1);
 225 }")
 226
 227 (define_insn "*movdi_internal"
 228   [(set (match_operand:DI 0 "general_operand" "=r,r,r,r,r,m,m,r")
 229         (match_operand:DI 1 "general_operand" "Jr,K,L,i,m,r,IG,iF"))]
 230   "register_operand (operands[0], DImode)
 231    || reg_or_0_operand (operands[1], DImode)"
 232   "* return output_move_double (operands);"
 233   [(set_attr "length" "4,8,8,16,8,8,8,16")
 234    (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
 235    (set_attr "type" "other,other,other,other,load,other,other,other")])
 236
 237 (define_expand "movsf"
 238   [(set (match_operand:SF 0 "general_operand" "")
 239         (match_operand:SF 1 "general_operand" ""))]
 240   ""
 241   "
 242 {
 243   /* One of the ops has to be in a register or 0 */
 244   if (!register_operand (operand0, SFmode)
 245       && !reg_or_0_operand (operand1, SFmode))
 246     operands[1] = copy_to_mode_reg (SFmode, operand1);
 247 }")
 248
 249 (define_insn "*movsf_internal"
 250   [(set (match_operand:SF 0 "general_operand" "=r,r,r,r,r,Q,r,m,m,r")
 251         (match_operand:SF 1 "general_operand" "Jr,K,L,n,Q,Ir,m,r,IG,iF"))]
 252   "register_operand (operands[0], SFmode)
 253    || reg_or_0_operand (operands[1], SFmode)"
 254   "* return output_move_single (operands);"
 255   [(set_attr "length" "2,4,4,8,2,2,4,4,4,8")
 256    (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
 257    (set_attr "type" "other,other,other,other,load,other,load,other,other,other")])
 258
 259 (define_expand "movdf"
 260   [(set (match_operand:DF 0 "general_operand" "")
 261         (match_operand:DF 1 "general_operand" ""))]
 262   ""
 263   "
 264 {
 265   /* One of the ops has to be in a register or 0 */
 266   if (!register_operand (operand0, DFmode)
 267       && !reg_or_0_operand (operand1, DFmode))
 268     operands[1] = copy_to_mode_reg (DFmode, operand1);
 269 }")
 270
 271 (define_insn "*movdf_internal"
 272   [(set (match_operand:DF 0 "general_operand" "=r,r,r,r,r,m,m,r")
 273         (match_operand:DF 1 "general_operand" "Jr,K,L,i,m,r,IG,iF"))]
 274   "register_operand (operands[0], DFmode)
 275    || reg_or_0_operand (operands[1], DFmode)"
 276   "* return output_move_double (operands);"
 277   [(set_attr "length" "4,8,8,16,8,8,8,16")
 278    (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
 279    (set_attr "type" "other,other,other,other,load,other,other,other")])
 280
 281 \f
 282 ;; ----------------------------------------------------------------------
 283 ;; TEST INSTRUCTIONS
 284 ;; ----------------------------------------------------------------------
 285
 286 (define_insn "*v850_tst1"
 287   [(set (cc0) (zero_extract:SI (match_operand:QI 0 "memory_operand" "m")
 288                                (const_int 1)
 289                                (match_operand:QI 1 "const_int_operand" "n")))]
 290   ""
 291   "tst1 %1,%0"
 292   [(set_attr "length" "4")
 293    (set_attr "cc" "clobber")])
 294
 295 ;; This replaces ld.b;sar;andi with tst1;setf nz.
 296
 297 ;; ??? The zero_extract sets the Z bit to the opposite of what one would
 298 ;; expect.  This perhaps should be wrapped in a (eq: X (const_int 0)).
 299
 300 (define_split
 301   [(set (match_operand:SI 0 "register_operand" "")
 302         (zero_extract:SI (match_operand:QI 1 "memory_operand" "")
 303                          (const_int 1)
 304                          (match_operand 2 "const_int_operand" "")))]
 305   ""
 306   [(set (cc0) (zero_extract:SI (match_dup 1)
 307                                (const_int 1)
 308                                (match_dup 2)))
 309    (set (match_dup 0) (ne:SI (cc0) (const_int 0)))])
 310
 311 (define_insn "tstsi"
 312   [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
 313   ""
 314   "cmp %.,%0"
 315   [(set_attr "length" "2")
 316    (set_attr "cc" "set_znv")])
 317
 318 (define_insn "cmpsi"
 319   [(set (cc0)
 320         (compare (match_operand:SI 0 "register_operand" "r,r")
 321                  (match_operand:SI 1 "reg_or_int5_operand" "r,J")))]
 322   ""
 323   "@
 324   cmp %1,%0
 325   cmp %1,%0"
 326   [(set_attr "length" "2,2")
 327    (set_attr "cc" "compare")])
 328 \f
 329 ;; ----------------------------------------------------------------------
 330 ;; ADD INSTRUCTIONS
 331 ;; ----------------------------------------------------------------------
 332
 333 (define_insn "addsi3"
 334   [(set (match_operand:SI 0 "register_operand" "=r,r,r")
 335         (plus:SI (match_operand:SI 1 "register_operand" "%0,r,r")
 336                  (match_operand:SI 2 "nonmemory_operand" "rJ,K,U")))]
 337   ""
 338   "@
 339    add %2,%0
 340    addi %2,%1,%0
 341    addi %O2(%P2),%1,%0"
 342   [(set_attr "length" "2,4,4")
 343    (set_attr "cc" "set_zn,set_zn,set_zn")])
 344
 345 ;; ----------------------------------------------------------------------
 346 ;; SUBTRACT INSTRUCTIONS
 347 ;; ----------------------------------------------------------------------
 348
 349 (define_insn "subsi3"
 350   [(set (match_operand:SI 0 "register_operand" "=r,r")
 351         (minus:SI (match_operand:SI 1 "register_operand" "0,r")
 352                   (match_operand:SI 2 "register_operand" "r,0")))]
 353   ""
 354   "@
 355   sub %2,%0
 356   subr %1,%0"
 357   [(set_attr "length" "2,2")
 358    (set_attr "cc" "set_zn")])
 359
 360 (define_insn "negsi2"
 361   [(set (match_operand:SI 0 "register_operand" "=r")
 362         (neg:SI (match_operand:SI 1 "register_operand" "0")))]
 363   ""
 364   "subr %.,%0"
 365   [(set_attr "length" "2")
 366    (set_attr "cc" "set_zn")])
 367
 368 ;; ----------------------------------------------------------------------
 369 ;; MULTIPLY INSTRUCTIONS
 370 ;; ----------------------------------------------------------------------
 371
 372 (define_expand "mulhisi3"
 373   [(set (match_operand:SI 0 "register_operand" "")
 374         (mult:SI
 375           (sign_extend:SI (match_operand:HI 1 "register_operand" ""))
 376           (sign_extend:SI (match_operand:HI 2 "nonmemory_operand" ""))))]
 377   ""
 378   "if (GET_CODE (operands[2]) == CONST_INT)
 379      {
 380        emit_insn (gen_mulhisi3_internal2 (operands[0], operands[1], operands[2]));
 381        DONE;
 382      }")
 383
 384 (define_insn "*mulhisi3_internal1"
 385   [(set (match_operand:SI 0 "register_operand" "=r")
 386         (mult:SI
 387           (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
 388           (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
 389   ""
 390   "mulh %2,%0"
 391   [(set_attr "length" "2")
 392    (set_attr "cc" "none_0hit")
 393    (set_attr "type" "mult")])
 394
 395 (define_insn "mulhisi3_internal2"
 396   [(set (match_operand:SI 0 "register_operand" "=r,r")
 397         (mult:SI
 398           (sign_extend:SI (match_operand:HI 1 "register_operand" "%0,r"))
 399           (match_operand:HI 2 "const_int_operand" "J,K")))]
 400   ""
 401   "@
 402    mulh %2,%0
 403    mulhi %2,%1,%0"
 404   [(set_attr "length" "2,4")
 405    (set_attr "cc" "none_0hit,none_0hit")
 406    (set_attr "type" "mult")])
 407
 408 ;; ??? The scheduling info is probably wrong.
 409
 410 ;; ??? This instruction can also generate the 32 bit highpart, but using it
 411 ;; may increase code size counter to the desired result.
 412
 413 ;; ??? This instructions can also give a DImode result.
 414
 415 ;; ??? There is unsigned version, but it matters only for the DImode/highpart
 416 ;; results.
 417
 418 (define_insn "mulsi3"
 419   [(set (match_operand:SI 0 "register_operand" "=r")
 420         (mult:SI (match_operand:SI 1 "register_operand" "%0")
 421                  (match_operand:SI 2 "reg_or_int9_operand" "rO")))]
 422   "TARGET_V850E"
 423   "mul %2,%1,%."
 424   [(set_attr "length" "4")
 425    (set_attr "cc" "none_0hit")
 426    (set_attr "type" "mult")])
 427
 428 ;; ----------------------------------------------------------------------
 429 ;; DIVIDE INSTRUCTIONS
 430 ;; ----------------------------------------------------------------------
 431
 432 ;; ??? These insns do set the Z/N condition codes, except that they are based
 433 ;; on only one of the two results, so it doesn't seem to make sense to use
 434 ;; them.
 435
 436 ;; ??? The scheduling info is probably wrong.
 437
 438 (define_insn "divmodsi4"
 439   [(set (match_operand:SI 0 "register_operand" "=r")
 440         (div:SI (match_operand:SI 1 "register_operand" "0")
 441                 (match_operand:SI 2 "register_operand" "r")))
 442    (set (match_operand:SI 3 "register_operand" "=r")
 443         (mod:SI (match_dup 1)
 444                 (match_dup 2)))]
 445   "TARGET_V850E"
 446   "div %2,%0,%3"
 447   [(set_attr "length" "4")
 448    (set_attr "cc" "clobber")
 449    (set_attr "type" "other")])
 450
 451 (define_insn "udivmodsi4"
 452   [(set (match_operand:SI 0 "register_operand" "=r")
 453         (udiv:SI (match_operand:SI 1 "register_operand" "0")
 454                  (match_operand:SI 2 "register_operand" "r")))
 455    (set (match_operand:SI 3 "register_operand" "=r")
 456         (umod:SI (match_dup 1)
 457                  (match_dup 2)))]
 458   "TARGET_V850E"
 459   "divu %2,%0,%3"
 460   [(set_attr "length" "4")
 461    (set_attr "cc" "clobber")
 462    (set_attr "type" "other")])
 463
 464 ;; ??? There is a 2 byte instruction for generating only the quotient.
 465 ;; However, it isn't clear how to compute the length field correctly.
 466
 467 (define_insn "divmodhi4"
 468   [(set (match_operand:HI 0 "register_operand" "=r")
 469         (div:HI (match_operand:HI 1 "register_operand" "0")
 470                 (match_operand:HI 2 "register_operand" "r")))
 471    (set (match_operand:HI 3 "register_operand" "=r")
 472         (mod:HI (match_dup 1)
 473                 (match_dup 2)))]
 474   "TARGET_V850E"
 475   "divh %2,%0,%3"
 476   [(set_attr "length" "4")
 477    (set_attr "cc" "clobber")
 478    (set_attr "type" "other")])
 479
 480 ;; Half-words are sign-extended by default, so we must zero extend to a word
 481 ;; here before doing the divide.
 482
 483 (define_insn "udivmodhi4"
 484   [(set (match_operand:HI 0 "register_operand" "=r")
 485         (udiv:HI (match_operand:HI 1 "register_operand" "0")
 486                  (match_operand:HI 2 "register_operand" "r")))
 487    (set (match_operand:HI 3 "register_operand" "=r")
 488         (umod:HI (match_dup 1)
 489                  (match_dup 2)))]
 490   "TARGET_V850E"
 491   "zxh %0 ; divhu %2,%0,%3"
 492   [(set_attr "length" "4")
 493    (set_attr "cc" "clobber")
 494    (set_attr "type" "other")])
 495 \f
 496 ;; ----------------------------------------------------------------------
 497 ;; AND INSTRUCTIONS
 498 ;; ----------------------------------------------------------------------
 499
 500 (define_insn "*v850_clr1_1"
 501   [(set (match_operand:QI 0 "memory_operand" "=m")
 502         (subreg:QI
 503           (and:SI (subreg:SI (match_dup 0) 0)
 504                   (match_operand:QI 1 "not_power_of_two_operand" "")) 0))]
 505   ""
 506   "*
 507 {
 508   rtx xoperands[2];
 509   xoperands[0] = operands[0];
 510   xoperands[1] = GEN_INT (~INTVAL (operands[1]) & 0xff);
 511   output_asm_insn (\"clr1 %M1,%0\", xoperands);
 512   return \"\";
 513 }"
 514   [(set_attr "length" "4")
 515    (set_attr "cc" "clobber")])
 516
 517 (define_insn "*v850_clr1_2"
 518   [(set (match_operand:HI 0 "indirect_operand" "=m")
 519         (subreg:HI
 520           (and:SI (subreg:SI (match_dup 0) 0)
 521                   (match_operand:HI 1 "not_power_of_two_operand" "")) 0))]
 522   ""
 523   "*
 524 {
 525   int log2 = exact_log2 (~INTVAL (operands[1]) & 0xffff);
 526
 527   rtx xoperands[2];
 528   xoperands[0] = gen_rtx_MEM (QImode,
 529                               plus_constant (XEXP (operands[0], 0), log2 / 8));
 530   xoperands[1] = GEN_INT (log2 % 8);
 531   output_asm_insn (\"clr1 %1,%0\", xoperands);
 532   return \"\";
 533 }"
 534   [(set_attr "length" "4")
 535    (set_attr "cc" "clobber")])
 536
 537 (define_insn "*v850_clr1_3"
 538   [(set (match_operand:SI 0 "indirect_operand" "=m")
 539         (and:SI (match_dup 0)
 540                 (match_operand:SI 1 "not_power_of_two_operand" "")))]
 541   ""
 542   "*
 543 {
 544   int log2 = exact_log2 (~INTVAL (operands[1]) & 0xffffffff);
 545
 546   rtx xoperands[2];
 547   xoperands[0] = gen_rtx_MEM (QImode,
 548                               plus_constant (XEXP (operands[0], 0), log2 / 8));
 549   xoperands[1] = GEN_INT (log2 % 8);
 550   output_asm_insn (\"clr1 %1,%0\", xoperands);
 551   return \"\";
 552 }"
 553   [(set_attr "length" "4")
 554    (set_attr "cc" "clobber")])
 555
 556 (define_insn "andsi3"
 557   [(set (match_operand:SI 0 "register_operand" "=r,r,r")
 558         (and:SI (match_operand:SI 1 "register_operand" "%0,0,r")
 559                 (match_operand:SI 2 "nonmemory_operand" "r,I,M")))]
 560   ""
 561   "@
 562   and %2,%0
 563   and %.,%0
 564   andi %2,%1,%0"
 565   [(set_attr "length" "2,2,4")
 566    (set_attr "cc" "set_znv")])
 567
 568 ;; ----------------------------------------------------------------------
 569 ;; OR INSTRUCTIONS
 570 ;; ----------------------------------------------------------------------
 571
 572 (define_insn "*v850_set1_1"
 573   [(set (match_operand:QI 0 "memory_operand" "=m")
 574         (subreg:QI (ior:SI (subreg:SI (match_dup 0) 0)
 575                            (match_operand 1 "power_of_two_operand" "")) 0))]
 576   ""
 577   "set1 %M1,%0"
 578   [(set_attr "length" "4")
 579    (set_attr "cc" "clobber")])
 580
 581 (define_insn "*v850_set1_2"
 582   [(set (match_operand:HI 0 "indirect_operand" "=m")
 583         (subreg:HI (ior:SI (subreg:SI (match_dup 0) 0)
 584                            (match_operand 1 "power_of_two_operand" "")) 0))]
 585   ""
 586   "*
 587 {
 588   int log2 = exact_log2 (INTVAL (operands[1]));
 589
 590   if (log2 < 8)
 591     return \"set1 %M1,%0\";
 592   else
 593     {
 594       rtx xoperands[2];
 595       xoperands[0] = gen_rtx_MEM (QImode,
 596                                   plus_constant (XEXP (operands[0], 0),
 597                                                  log2 / 8));
 598       xoperands[1] = GEN_INT (log2 % 8);
 599       output_asm_insn (\"set1 %1,%0\", xoperands);
 600     }
 601   return \"\";
 602 }"
 603   [(set_attr "length" "4")
 604    (set_attr "cc" "clobber")])
 605
 606 (define_insn "*v850_set1_3"
 607   [(set (match_operand:SI 0 "indirect_operand" "=m")
 608         (ior:SI (match_dup 0)
 609                 (match_operand 1 "power_of_two_operand" "")))]
 610   ""
 611   "*
 612 {
 613   int log2 = exact_log2 (INTVAL (operands[1]));
 614
 615   if (log2 < 8)
 616     return \"set1 %M1,%0\";
 617   else
 618     {
 619       rtx xoperands[2];
 620       xoperands[0] = gen_rtx_MEM (QImode,
 621                                   plus_constant (XEXP (operands[0], 0),
 622                                                  log2 / 8));
 623       xoperands[1] = GEN_INT (log2 % 8);
 624       output_asm_insn (\"set1 %1,%0\", xoperands);
 625     }
 626   return \"\";
 627 }"
 628   [(set_attr "length" "4")
 629    (set_attr "cc" "clobber")])
 630
 631 (define_insn "iorsi3"
 632   [(set (match_operand:SI 0 "register_operand" "=r,r,r")
 633         (ior:SI (match_operand:SI 1 "register_operand" "%0,0,r")
 634                 (match_operand:SI 2 "nonmemory_operand" "r,I,M")))]
 635   ""
 636   "@
 637   or %2,%0
 638   or %.,%0
 639   ori %2,%1,%0"
 640   [(set_attr "length" "2,2,4")
 641    (set_attr "cc" "set_znv")])
 642
 643 ;; ----------------------------------------------------------------------
 644 ;; XOR INSTRUCTIONS
 645 ;; ----------------------------------------------------------------------
 646
 647 (define_insn "*v850_not1_1"
 648   [(set (match_operand:QI 0 "memory_operand" "=m")
 649         (subreg:QI (xor:SI (subreg:SI (match_dup 0) 0)
 650                            (match_operand 1 "power_of_two_operand" "")) 0))]
 651   ""
 652   "not1 %M1,%0"
 653   [(set_attr "length" "4")
 654    (set_attr "cc" "clobber")])
 655
 656 (define_insn "*v850_not1_2"
 657   [(set (match_operand:HI 0 "indirect_operand" "=m")
 658         (subreg:HI (xor:SI (subreg:SI (match_dup 0) 0)
 659                            (match_operand 1 "power_of_two_operand" "")) 0))]
 660   ""
 661   "*
 662 {
 663   int log2 = exact_log2 (INTVAL (operands[1]));
 664
 665   if (log2 < 8)
 666     return \"not1 %M1,%0\";
 667   else
 668     {
 669       rtx xoperands[2];
 670       xoperands[0] = gen_rtx_MEM (QImode,
 671                                   plus_constant (XEXP (operands[0], 0),
 672                                                  log2 / 8));
 673       xoperands[1] = GEN_INT (log2 % 8);
 674       output_asm_insn (\"not1 %1,%0\", xoperands);
 675     }
 676   return \"\";
 677 }"
 678   [(set_attr "length" "4")
 679    (set_attr "cc" "clobber")])
 680
 681 (define_insn "*v850_not1_3"
 682   [(set (match_operand:SI 0 "indirect_operand" "=m")
 683         (xor:SI (match_dup 0)
 684                 (match_operand 1 "power_of_two_operand" "")))]
 685   ""
 686   "*
 687 {
 688   int log2 = exact_log2 (INTVAL (operands[1]));
 689
 690   if (log2 < 8)
 691     return \"not1 %M1,%0\";
 692   else
 693     {
 694       rtx xoperands[2];
 695       xoperands[0] = gen_rtx_MEM (QImode,
 696                                   plus_constant (XEXP (operands[0], 0),
 697                                                  log2 / 8));
 698       xoperands[1] = GEN_INT (log2 % 8);
 699       output_asm_insn (\"not1 %1,%0\", xoperands);
 700     }
 701   return \"\";
 702 }"
 703   [(set_attr "length" "4")
 704    (set_attr "cc" "clobber")])
 705
 706 (define_insn "xorsi3"
 707   [(set (match_operand:SI 0 "register_operand" "=r,r,r")
 708         (xor:SI (match_operand:SI 1 "register_operand" "%0,0,r")
 709                 (match_operand:SI 2 "nonmemory_operand" "r,I,M")))]
 710   ""
 711   "@
 712   xor %2,%0
 713   xor %.,%0
 714   xori %2,%1,%0"
 715   [(set_attr "length" "2,2,4")
 716    (set_attr "cc" "set_znv")])
 717 \f
 718 ;; ----------------------------------------------------------------------
 719 ;; NOT INSTRUCTIONS
 720 ;; ----------------------------------------------------------------------
 721
 722 (define_insn "one_cmplsi2"
 723   [(set (match_operand:SI 0 "register_operand" "=r")
 724         (not:SI (match_operand:SI 1 "register_operand" "r")))]
 725   ""
 726   "not %1,%0"
 727   [(set_attr "length" "2")
 728    (set_attr "cc" "set_znv")])
 729 \f
 730 ;; -----------------------------------------------------------------
 731 ;; BIT FIELDS
 732 ;; -----------------------------------------------------------------
 733
 734 ;; ??? Is it worth defining insv and extv for the V850 series?!?
 735
 736 ;; An insv pattern would be useful, but does not get used because
 737 ;; store_bit_field never calls insv when storing a constant value into a
 738 ;; single-bit bitfield.
 739
 740 ;; extv/extzv patterns would be useful, but do not get used because
 741 ;; optimize_bitfield_compare in fold-const usually converts single
 742 ;; bit extracts into an AND with a mask.
 743
 744 ;; -----------------------------------------------------------------
 745 ;; Scc INSTRUCTIONS
 746 ;; -----------------------------------------------------------------
 747
 748 (define_insn "sle"
 749   [(set (match_operand:SI 0 "register_operand" "=r")
 750         (le:SI (cc0) (const_int 0)))]
 751   ""
 752   "*
 753 {
 754   if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
 755     return 0;
 756
 757   return \"setf le,%0\";
 758 }"
 759   [(set_attr "length" "4")
 760    (set_attr "cc" "none_0hit")])
 761
 762 (define_insn "sleu"
 763   [(set (match_operand:SI 0 "register_operand" "=r")
 764         (leu:SI (cc0) (const_int 0)))]
 765   ""
 766   "setf nh,%0"
 767   [(set_attr "length" "4")
 768    (set_attr "cc" "none_0hit")])
 769
 770 (define_insn "sge"
 771   [(set (match_operand:SI 0 "register_operand" "=r")
 772         (ge:SI (cc0) (const_int 0)))]
 773   ""
 774   "*
 775 {
 776   if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
 777     return 0;
 778
 779   return \"setf ge,%0\";
 780 }"
 781   [(set_attr "length" "4")
 782    (set_attr "cc" "none_0hit")])
 783
 784 (define_insn "sgeu"
 785   [(set (match_operand:SI 0 "register_operand" "=r")
 786         (geu:SI (cc0) (const_int 0)))]
 787   ""
 788   "setf nl,%0"
 789   [(set_attr "length" "4")
 790    (set_attr "cc" "none_0hit")])
 791
 792 (define_insn "slt"
 793   [(set (match_operand:SI 0 "register_operand" "=r")
 794         (lt:SI (cc0) (const_int 0)))]
 795   ""
 796   "*
 797 {
 798   if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
 799     return 0;
 800
 801   return \"setf lt,%0\";
 802 }"
 803   [(set_attr "length" "4")
 804    (set_attr "cc" "none_0hit")])
 805
 806 (define_insn "sltu"
 807   [(set (match_operand:SI 0 "register_operand" "=r")
 808         (ltu:SI (cc0) (const_int 0)))]
 809   ""
 810   "setf l,%0"
 811   [(set_attr "length" "4")
 812    (set_attr "cc" "none_0hit")])
 813
 814 (define_insn "sgt"
 815   [(set (match_operand:SI 0 "register_operand" "=r")
 816         (gt:SI (cc0) (const_int 0)))]
 817   ""
 818   "*
 819 {
 820   if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
 821     return 0;
 822
 823   return \"setf gt,%0\";
 824 }"
 825   [(set_attr "length" "4")
 826    (set_attr "cc" "none_0hit")])
 827
 828 (define_insn "sgtu"
 829   [(set (match_operand:SI 0 "register_operand" "=r")
 830         (gtu:SI (cc0) (const_int 0)))]
 831   ""
 832   "setf h,%0"
 833   [(set_attr "length" "4")
 834    (set_attr "cc" "none_0hit")])
 835
 836 (define_insn "seq"
 837   [(set (match_operand:SI 0 "register_operand" "=r")
 838         (eq:SI (cc0) (const_int 0)))]
 839   ""
 840   "setf z,%0"
 841   [(set_attr "length" "4")
 842    (set_attr "cc" "none_0hit")])
 843
 844 (define_insn "sne"
 845   [(set (match_operand:SI 0 "register_operand" "=r")
 846         (ne:SI (cc0) (const_int 0)))]
 847   ""
 848   "setf nz,%0"
 849   [(set_attr "length" "4")
 850    (set_attr "cc" "none_0hit")])
 851
 852 ;; ----------------------------------------------------------------------
 853 ;; CONDITIONAL MOVE INSTRUCTIONS
 854 ;; ----------------------------------------------------------------------
 855
 856 ;; Instructions using cc0 aren't allowed to have input reloads, so we must
 857 ;; hide the fact that this instruction uses cc0.  We do so by including the
 858 ;; compare instruction inside it.
 859
 860 ;; ??? This is very ugly.  The right way to do this is to modify cmpsi so
 861 ;; that it doesn't emit RTL, and then modify the bcc/scc patterns so that
 862 ;; they emit RTL for the compare instruction.  Unfortunately, this requires
 863 ;; lots of changes that will be hard to sanitize.  So for now, cmpsi still
 864 ;; emits RTL, and I get the compare operands here from the previous insn.
 865
 866 (define_expand "movsicc"
 867   [(set (match_operand:SI 0 "register_operand" "=r")
 868         (if_then_else:SI
 869          (match_operator 1 "comparison_operator"
 870                          [(match_dup 4) (match_dup 5)])
 871          (match_operand:SI 2 "reg_or_const_operand" "rJ")
 872          (match_operand:SI 3 "reg_or_const_operand" "rI")))]
 873   "TARGET_V850E"
 874   "
 875 {
 876   rtx insn = get_last_insn_anywhere ();
 877
 878   if (   (GET_CODE (operands[2]) == CONST_INT
 879        && GET_CODE (operands[3]) == CONST_INT))
 880     {
 881       int o2 = INTVAL (operands[2]);
 882       int o3 = INTVAL (operands[3]);
 883
 884       if (o2 == 1 && o3 == 0)
 885         FAIL;   /* setf */
 886       if (o3 == 1 && o2 == 0)
 887         FAIL;   /* setf */
 888       if (o2 == 0 && (o3 < -16 || o3 > 15) && exact_log2 (o3) >= 0)
 889         FAIL;   /* setf + shift */
 890       if (o3 == 0 && (o2 < -16 || o2 > 15) && exact_log2 (o2) >=0)
 891         FAIL;   /* setf + shift */
 892       if (o2 != 0)
 893         operands[2] = copy_to_mode_reg (SImode, operands[2]);
 894       if (o3 !=0 )
 895         operands[3] = copy_to_mode_reg (SImode, operands[3]);
 896     }
 897   else
 898     {
 899       if (GET_CODE (operands[2]) != REG)
 900         operands[2] = copy_to_mode_reg (SImode,operands[2]);
 901       if (GET_CODE (operands[3]) != REG)
 902         operands[3] = copy_to_mode_reg (SImode, operands[3]);
 903     }
 904   if (GET_CODE (insn) == INSN
 905       && GET_CODE (PATTERN (insn)) == SET
 906       && SET_DEST (PATTERN (insn)) == cc0_rtx)
 907     {
 908       rtx src = SET_SRC (PATTERN (insn));
 909
 910       if (GET_CODE (src) == COMPARE)
 911         {
 912           operands[4] = XEXP (src, 0);
 913           operands[5] = XEXP (src, 1);
 914         }
 915       else if (GET_CODE (src) == REG
 916                || GET_CODE (src) == SUBREG)
 917         {
 918           operands[4] = src;
 919           operands[5] = const0_rtx;
 920         }
 921       else
 922         abort ();
 923     }
 924   else
 925     abort ();
 926 }")
 927
 928 ;; ??? Clobbering the condition codes is overkill.
 929
 930 ;; ??? We sometimes emit an unnecessary compare instruction because the
 931 ;; condition codes may have already been set by an earlier instruction,
 932 ;; but we have no code here to avoid the compare if it is unnecessary.
 933
 934 (define_insn "*movsicc_normal"
 935   [(set (match_operand:SI 0 "register_operand" "=r")
 936         (if_then_else:SI
 937          (match_operator 1 "comparison_operator"
 938                          [(match_operand:SI 4 "register_operand" "r")
 939                           (match_operand:SI 5 "reg_or_int5_operand" "rJ")])
 940          (match_operand:SI 2 "reg_or_int5_operand" "rJ")
 941          (match_operand:SI 3 "reg_or_0_operand" "rI")))]
 942   "TARGET_V850E"
 943   "cmp %5,%4 ; cmov %c1,%2,%z3,%0"
 944   [(set_attr "length" "6")
 945    (set_attr "cc" "clobber")])
 946
 947 (define_insn "*movsicc_reversed"
 948   [(set (match_operand:SI 0 "register_operand" "=r")
 949         (if_then_else:SI
 950          (match_operator 1 "comparison_operator"
 951                          [(match_operand:SI 4 "register_operand" "r")
 952                           (match_operand:SI 5 "reg_or_int5_operand" "rJ")])
 953          (match_operand:SI 2 "reg_or_0_operand" "rI")
 954          (match_operand:SI 3 "reg_or_int5_operand" "rJ")))]
 955   "TARGET_V850E"
 956   "cmp %5,%4 ; cmov %C1,%3,%z2,%0"
 957   [(set_attr "length" "6")
 958    (set_attr "cc" "clobber")])
 959
 960 (define_insn "*movsicc_tst1"
 961   [(set (match_operand:SI 0 "register_operand" "=r")
 962         (if_then_else:SI
 963          (match_operator 1 "comparison_operator"
 964                          [(zero_extract:SI
 965                            (match_operand:QI 2 "memory_operand" "m")
 966                            (const_int 1)
 967                            (match_operand 3 "const_int_operand" "n"))
 968                           (const_int 0)])
 969          (match_operand:SI 4 "reg_or_int5_operand" "rJ")
 970          (match_operand:SI 5 "reg_or_0_operand" "rI")))]
 971   "TARGET_V850E"
 972   "tst1 %3,%2 ; cmov %c1,%4,%z5,%0"
 973   [(set_attr "length" "8")
 974    (set_attr "cc" "clobber")])
 975
 976 (define_insn "*movsicc_tst1_reversed"
 977   [(set (match_operand:SI 0 "register_operand" "=r")
 978         (if_then_else:SI
 979          (match_operator 1 "comparison_operator"
 980                          [(zero_extract:SI
 981                            (match_operand:QI 2 "memory_operand" "m")
 982                            (const_int 1)
 983                            (match_operand 3 "const_int_operand" "n"))
 984                           (const_int 0)])
 985          (match_operand:SI 4 "reg_or_0_operand" "rI")
 986          (match_operand:SI 5 "reg_or_int5_operand" "rJ")))]
 987   "TARGET_V850E"
 988   "tst1 %3,%2 ; cmov %C1,%5,%z4,%0"
 989   [(set_attr "length" "8")
 990    (set_attr "cc" "clobber")])
 991
 992 ;; Matching for sasf requires combining 4 instructions, so we provide a
 993 ;; dummy pattern to match the first 3, which will always be turned into the
 994 ;; second pattern by subsequent combining.  As above, we must include the
 995 ;; comparison to avoid input reloads in an insn using cc0.
 996
 997 (define_insn "*sasf_1"
 998   [(set (match_operand:SI 0 "register_operand" "")
 999         (ior:SI (match_operator 1 "comparison_operator" [(cc0) (const_int 0)])
1000                 (ashift:SI (match_operand:SI 2 "register_operand" "")
1001                            (const_int 1))))]
1002   "TARGET_V850E"
1003   "* abort ();")
1004
1005 (define_insn "*sasf_2"
1006   [(set (match_operand:SI 0 "register_operand" "=r")
1007         (ior:SI
1008          (match_operator 1 "comparison_operator"
1009                          [(match_operand:SI 3 "register_operand" "r")
1010                           (match_operand:SI 4 "reg_or_int5_operand" "rJ")])
1011          (ashift:SI (match_operand:SI 2 "register_operand" "0")
1012                     (const_int 1))))]
1013   "TARGET_V850E"
1014   "cmp %4,%3 ; sasf %c1,%0"
1015   [(set_attr "length" "6")
1016    (set_attr "cc" "clobber")])
1017
1018 (define_split
1019   [(set (match_operand:SI 0 "register_operand" "")
1020         (if_then_else:SI
1021          (match_operator 1 "comparison_operator"
1022                          [(match_operand:SI 4 "register_operand" "")
1023                           (match_operand:SI 5 "reg_or_int5_operand" "")])
1024          (match_operand:SI 2 "const_int_operand" "")
1025          (match_operand:SI 3 "const_int_operand" "")))]
1026   "TARGET_V850E
1027    && ((INTVAL (operands[2]) ^ INTVAL (operands[3])) == 1)
1028    && ((INTVAL (operands[2]) + INTVAL (operands[3])) != 1)
1029    && (GET_CODE (operands[5]) == CONST_INT
1030       || REGNO (operands[0]) != REGNO (operands[5]))
1031    && REGNO (operands[0]) != REGNO (operands[4])"
1032   [(set (match_dup 0) (match_dup 6))
1033    (set (match_dup 0)
1034         (ior:SI (match_op_dup 7 [(match_dup 4) (match_dup 5)])
1035                 (ashift:SI (match_dup 0) (const_int 1))))]
1036   "
1037 {
1038   operands[6] = GEN_INT (INTVAL (operands[2]) >> 1);
1039   if (INTVAL (operands[2]) & 0x1)
1040     operands[7] = operands[1];
1041   else
1042     operands[7] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[1])),
1043                                   GET_MODE (operands[1]),
1044                                   XEXP (operands[1], 0), XEXP (operands[1], 1));
1045 }")
1046 ;; ---------------------------------------------------------------------
1047 ;; BYTE SWAP INSTRUCTIONS
1048 ;; ---------------------------------------------------------------------
1049
1050 (define_expand "rotlhi3"
1051   [(set (match_operand:HI 0 "register_operand" "")
1052         (rotate:HI (match_operand:HI 1 "register_operand" "")
1053                    (match_operand:HI 2 "const_int_operand" "")))]
1054   "TARGET_V850E"
1055   "
1056 {
1057   if (INTVAL (operands[2]) != 8)
1058     FAIL;
1059 }")
1060
1061 (define_insn "*rotlhi3_8"
1062   [(set (match_operand:HI 0 "register_operand" "=r")
1063         (rotate:HI (match_operand:HI 1 "register_operand" "r")
1064                    (const_int 8)))]
1065   "TARGET_V850E"
1066   "bsh %1,%0"
1067   [(set_attr "length" "4")
1068    (set_attr "cc" "clobber")])
1069
1070 (define_expand "rotlsi3"
1071   [(set (match_operand:SI 0 "register_operand" "")
1072         (rotate:SI (match_operand:SI 1 "register_operand" "")
1073                    (match_operand:SI 2 "const_int_operand" "")))]
1074   "TARGET_V850E"
1075   "
1076 {
1077   if (INTVAL (operands[2]) != 16)
1078     FAIL;
1079 }")
1080
1081 (define_insn "*rotlsi3_16"
1082   [(set (match_operand:SI 0 "register_operand" "=r")
1083         (rotate:SI (match_operand:SI 1 "register_operand" "r")
1084                    (const_int 16)))]
1085   "TARGET_V850E"
1086   "hsw %1,%0"
1087   [(set_attr "length" "4")
1088    (set_attr "cc" "clobber")])
1089 \f
1090 ;; ----------------------------------------------------------------------
1091 ;; JUMP INSTRUCTIONS
1092 ;; ----------------------------------------------------------------------
1093
1094 ;; Conditional jump instructions
1095
1096 (define_expand "ble"
1097   [(set (pc)
1098         (if_then_else (le (cc0)
1099                           (const_int 0))
1100                       (label_ref (match_operand 0 "" ""))
1101                       (pc)))]
1102   ""
1103   "")
1104
1105 (define_expand "bleu"
1106   [(set (pc)
1107         (if_then_else (leu (cc0)
1108                            (const_int 0))
1109                       (label_ref (match_operand 0 "" ""))
1110                       (pc)))]
1111   ""
1112   "")
1113
1114 (define_expand "bge"
1115   [(set (pc)
1116         (if_then_else (ge (cc0)
1117                           (const_int 0))
1118                       (label_ref (match_operand 0 "" ""))
1119                       (pc)))]
1120   ""
1121   "")
1122
1123 (define_expand "bgeu"
1124   [(set (pc)
1125         (if_then_else (geu (cc0)
1126                            (const_int 0))
1127                       (label_ref (match_operand 0 "" ""))
1128                       (pc)))]
1129   ""
1130   "")
1131
1132 (define_expand "blt"
1133   [(set (pc)
1134         (if_then_else (lt (cc0)
1135                           (const_int 0))
1136                       (label_ref (match_operand 0 "" ""))
1137                       (pc)))]
1138   ""
1139   "")
1140
1141 (define_expand "bltu"
1142   [(set (pc)
1143         (if_then_else (ltu (cc0)
1144                            (const_int 0))
1145                       (label_ref (match_operand 0 "" ""))
1146                       (pc)))]
1147   ""
1148   "")
1149
1150 (define_expand "bgt"
1151   [(set (pc)
1152         (if_then_else (gt (cc0)
1153                           (const_int 0))
1154                       (label_ref (match_operand 0 "" ""))
1155                       (pc)))]
1156   ""
1157   "")
1158
1159 (define_expand "bgtu"
1160   [(set (pc)
1161         (if_then_else (gtu (cc0)
1162                            (const_int 0))
1163                       (label_ref (match_operand 0 "" ""))
1164                       (pc)))]
1165   ""
1166   "")
1167
1168 (define_expand "beq"
1169   [(set (pc)
1170         (if_then_else (eq (cc0)
1171                           (const_int 0))
1172                       (label_ref (match_operand 0 "" ""))
1173                       (pc)))]
1174   ""
1175   "")
1176
1177 (define_expand "bne"
1178   [(set (pc)
1179         (if_then_else (ne (cc0)
1180                           (const_int 0))
1181                       (label_ref (match_operand 0 "" ""))
1182                       (pc)))]
1183   ""
1184   "")
1185
1186 (define_insn "*branch_normal"
1187   [(set (pc)
1188         (if_then_else (match_operator 1 "comparison_operator"
1189                                       [(cc0) (const_int 0)])
1190                       (label_ref (match_operand 0 "" ""))
1191                       (pc)))]
1192   ""
1193   "*
1194 {
1195   if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1196       && (GET_CODE (operands[1]) == GT
1197           || GET_CODE (operands[1]) == GE
1198           || GET_CODE (operands[1]) == LE
1199           || GET_CODE (operands[1]) == LT))
1200     return 0;
1201
1202   if (get_attr_length (insn) == 2)
1203     return \"b%b1 %l0\";
1204   else
1205     return \"b%B1 .+6 ; jr %l0\";
1206 }"
1207  [(set (attr "length")
1208     (if_then_else (lt (abs (minus (match_dup 0) (pc)))
1209                       (const_int 256))
1210                   (const_int 2)
1211                   (const_int 6)))
1212   (set_attr "cc" "none")])
1213
1214 (define_insn "*branch_invert"
1215   [(set (pc)
1216         (if_then_else (match_operator 1 "comparison_operator"
1217                                       [(cc0) (const_int 0)])
1218                       (pc)
1219                       (label_ref (match_operand 0 "" ""))))]
1220   ""
1221   "*
1222 {
1223   if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1224       && (GET_CODE (operands[1]) == GT
1225           || GET_CODE (operands[1]) == GE
1226           || GET_CODE (operands[1]) == LE
1227           || GET_CODE (operands[1]) == LT))
1228     return 0;
1229   if (get_attr_length (insn) == 2)
1230     return \"b%B1 %l0\";
1231   else
1232     return \"b%b1 .+6 ; jr %l0\";
1233 }"
1234  [(set (attr "length")
1235     (if_then_else (lt (abs (minus (match_dup 0) (pc)))
1236                       (const_int 256))
1237                   (const_int 2)
1238                   (const_int 6)))
1239   (set_attr "cc" "none")])
1240
1241 ;; Unconditional and other jump instructions.
1242
1243 (define_insn "jump"
1244   [(set (pc)
1245         (label_ref (match_operand 0 "" "")))]
1246   ""
1247   "*
1248 {
1249   if (get_attr_length (insn) == 2)
1250     return \"br %0\";
1251   else
1252     return \"jr %0\";
1253 }"
1254  [(set (attr "length")
1255     (if_then_else (lt (abs (minus (match_dup 0) (pc)))
1256                       (const_int 256))
1257                   (const_int 2)
1258                   (const_int 4)))
1259   (set_attr "cc" "none")])
1260
1261 (define_insn "indirect_jump"
1262   [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
1263   ""
1264   "jmp %0"
1265   [(set_attr "length" "2")
1266    (set_attr "cc" "none")])
1267
1268 (define_insn "tablejump"
1269   [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1270    (use (label_ref (match_operand 1 "" "")))]
1271   ""
1272   "jmp  %0"
1273   [(set_attr "length" "2")
1274    (set_attr "cc" "none")])
1275
1276 (define_insn "switch"
1277   [(set (pc)
1278         (plus:SI
1279          (sign_extend:SI
1280           (mem:HI
1281            (plus:SI (ashift:SI (match_operand:SI 0 "register_operand" "r")
1282                                (const_int 1))
1283                     (label_ref (match_operand 1 "" "")))))
1284          (label_ref (match_dup 1))))]
1285   "TARGET_V850E"
1286   "switch %0"
1287   [(set_attr "length" "2")
1288    (set_attr "cc" "none")])
1289
1290 (define_expand "casesi"
1291   [(match_operand:SI 0 "register_operand" "")
1292    (match_operand:SI 1 "register_operand" "")
1293    (match_operand:SI 2 "register_operand" "")
1294    (match_operand 3 "" "") (match_operand 4 "" "")]
1295   ""
1296   "
1297 {
1298   rtx reg = gen_reg_rtx (SImode);
1299   rtx tableaddress = gen_reg_rtx (SImode);
1300   rtx mem;
1301
1302   /* Subtract the lower bound from the index.  */
1303   emit_insn (gen_subsi3 (reg, operands[0], operands[1]));
1304   /* Compare the result against the number of table entries.  */
1305   emit_insn (gen_cmpsi (reg, operands[2]));
1306   /* Branch to the default label if out of range of the table.  */
1307   emit_jump_insn (gen_bgtu (operands[4]));
1308
1309   if (! TARGET_BIG_SWITCH && TARGET_V850E)
1310     {
1311       emit_jump_insn (gen_switch (reg, operands[3]));
1312       DONE;
1313     }
1314
1315   /* Shift index for the table array access.  */
1316   emit_insn (gen_ashlsi3 (reg, reg, GEN_INT (TARGET_BIG_SWITCH ? 2 : 1)));
1317   /* Load the table address into a pseudo.  */
1318   emit_insn (gen_movsi (tableaddress,
1319                         gen_rtx_LABEL_REF (Pmode, operands[3])));
1320   /* Add the table address to the index.  */
1321   emit_insn (gen_addsi3 (reg, reg, tableaddress));
1322   /* Load the table entry.  */
1323   mem = gen_rtx_MEM (CASE_VECTOR_MODE, reg);
1324   MEM_READONLY_P (mem) = 1;
1325   if (! TARGET_BIG_SWITCH)
1326     {
1327       rtx reg2 = gen_reg_rtx (HImode);
1328       emit_insn (gen_movhi (reg2, mem));
1329       emit_insn (gen_extendhisi2 (reg, reg2));
1330     }
1331   else
1332     emit_insn (gen_movsi (reg, mem));
1333   /* Add the table address.  */
1334   emit_insn (gen_addsi3 (reg, reg, tableaddress));
1335   /* Branch to the switch label.  */
1336   emit_jump_insn (gen_tablejump (reg, operands[3]));
1337   DONE;
1338 }")
1339
1340 ;; Call subroutine with no return value.
1341
1342 (define_expand "call"
1343   [(call (match_operand:QI 0 "general_operand" "")
1344          (match_operand:SI 1 "general_operand" ""))]
1345   ""
1346   "
1347 {
1348   if (! call_address_operand (XEXP (operands[0], 0), QImode)
1349       || TARGET_LONG_CALLS)
1350     XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0));
1351   if (TARGET_LONG_CALLS)
1352     emit_call_insn (gen_call_internal_long (XEXP (operands[0], 0), operands[1]));
1353   else
1354     emit_call_insn (gen_call_internal_short (XEXP (operands[0], 0), operands[1]));
1355
1356   DONE;
1357 }")
1358
1359 (define_insn "call_internal_short"
1360   [(call (mem:QI (match_operand:SI 0 "call_address_operand" "S,r"))
1361          (match_operand:SI 1 "general_operand" "g,g"))
1362    (clobber (reg:SI 31))]
1363   "! TARGET_LONG_CALLS"
1364   "@
1365   jarl %0,r31
1366   jarl .+4,r31 ; add 4,r31 ; jmp %0"
1367   [(set_attr "length" "4,8")]
1368 )
1369
1370 (define_insn "call_internal_long"
1371   [(call (mem:QI (match_operand:SI 0 "call_address_operand" "S,r"))
1372          (match_operand:SI 1 "general_operand" "g,g"))
1373    (clobber (reg:SI 31))]
1374   "TARGET_LONG_CALLS"
1375   "*
1376   {
1377   if (which_alternative == 0)
1378     {
1379       if (GET_CODE (operands[0]) == REG)
1380         return \"jarl %0,r31\";
1381       else
1382         return \"movhi hi(%0), r0, r11 ; movea lo(%0), r11, r11 ; jarl .+4,r31 ; add 4, r31 ; jmp r11\";
1383     }
1384   else
1385     return \"jarl .+4,r31 ; add 4,r31 ; jmp %0\";
1386   }"
1387   [(set_attr "length" "16,8")]
1388 )
1389
1390 ;; Call subroutine, returning value in operand 0
1391 ;; (which must be a hard register).
1392
1393 (define_expand "call_value"
1394   [(set (match_operand 0 "" "")
1395         (call (match_operand:QI 1 "general_operand" "")
1396               (match_operand:SI 2 "general_operand" "")))]
1397   ""
1398   "
1399 {
1400   if (! call_address_operand (XEXP (operands[1], 0), QImode)
1401       || TARGET_LONG_CALLS)
1402     XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0));
1403   if (TARGET_LONG_CALLS)
1404     emit_call_insn (gen_call_value_internal_long (operands[0],
1405                                                   XEXP (operands[1], 0),
1406                                                   operands[2]));
1407   else
1408     emit_call_insn (gen_call_value_internal_short (operands[0],
1409                                                    XEXP (operands[1], 0),
1410                                                    operands[2]));
1411   DONE;
1412 }")
1413
1414 (define_insn "call_value_internal_short"
1415   [(set (match_operand 0 "" "=r,r")
1416         (call (mem:QI (match_operand:SI 1 "call_address_operand" "S,r"))
1417               (match_operand:SI 2 "general_operand" "g,g")))
1418    (clobber (reg:SI 31))]
1419   "! TARGET_LONG_CALLS"
1420   "@
1421   jarl %1,r31
1422   jarl .+4,r31 ; add 4,r31 ; jmp %1"
1423   [(set_attr "length" "4,8")]
1424 )
1425
1426 (define_insn "call_value_internal_long"
1427   [(set (match_operand 0 "" "=r,r")
1428         (call (mem:QI (match_operand:SI 1 "call_address_operand" "S,r"))
1429               (match_operand:SI 2 "general_operand" "g,g")))
1430    (clobber (reg:SI 31))]
1431   "TARGET_LONG_CALLS"
1432   "*
1433   {
1434   if (which_alternative == 0)
1435     {
1436       if (GET_CODE (operands[1]) == REG)
1437         return \"jarl %1, r31\";
1438       else
1439       /* Reload can generate this pattern....  */
1440         return \"movhi hi(%1), r0, r11 ; movea lo(%1), r11, r11 ; jarl .+4, r31 ; add 4, r31 ; jmp r11\";
1441     }
1442   else
1443     return \"jarl .+4, r31 ; add 4, r31 ; jmp %1\";
1444   }"
1445   [(set_attr "length" "16,8")]
1446 )
1447
1448 (define_insn "nop"
1449   [(const_int 0)]
1450   ""
1451   "nop"
1452   [(set_attr "length" "2")
1453    (set_attr "cc" "none")])
1454 \f
1455 ;; ----------------------------------------------------------------------
1456 ;; EXTEND INSTRUCTIONS
1457 ;; ----------------------------------------------------------------------
1458
1459 (define_insn ""
1460   [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1461         (zero_extend:SI
1462          (match_operand:HI 1 "nonimmediate_operand" "0,r,T,m")))]
1463   "TARGET_V850E"
1464   "@
1465    zxh %0
1466    andi 65535,%1,%0
1467    sld.hu %1,%0
1468    ld.hu %1,%0"
1469   [(set_attr "length" "2,4,2,4")
1470    (set_attr "cc" "none_0hit,set_znv,none_0hit,none_0hit")])
1471
1472 (define_insn "zero_extendhisi2"
1473   [(set (match_operand:SI 0 "register_operand" "=r")
1474         (zero_extend:SI
1475          (match_operand:HI 1 "register_operand" "r")))]
1476   ""
1477   "andi 65535,%1,%0"
1478   [(set_attr "length" "4")
1479    (set_attr "cc" "set_znv")])
1480
1481 (define_insn ""
1482   [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1483         (zero_extend:SI
1484          (match_operand:QI 1 "nonimmediate_operand" "0,r,T,m")))]
1485   "TARGET_V850E"
1486   "@
1487    zxb %0
1488    andi 255,%1,%0
1489    sld.bu %1,%0
1490    ld.bu %1,%0"
1491   [(set_attr "length" "2,4,2,4")
1492    (set_attr "cc" "none_0hit,set_znv,none_0hit,none_0hit")])
1493
1494 (define_insn "zero_extendqisi2"
1495   [(set (match_operand:SI 0 "register_operand" "=r")
1496         (zero_extend:SI
1497          (match_operand:QI 1 "register_operand" "r")))]
1498   ""
1499   "andi 255,%1,%0"
1500   [(set_attr "length" "4")
1501    (set_attr "cc" "set_znv")])
1502
1503 ;;- sign extension instructions
1504
1505 ;; ??? The extendhisi2 pattern should not emit shifts for v850e?
1506
1507 (define_insn "*extendhisi_insn"
1508   [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1509         (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,Q,m")))]
1510   "TARGET_V850E"
1511   "@
1512    sxh %0
1513    sld.h %1,%0
1514    ld.h %1,%0"
1515   [(set_attr "length" "2,2,4")
1516    (set_attr "cc" "none_0hit,none_0hit,none_0hit")])
1517
1518 ;; ??? This is missing a sign extend from memory pattern to match the ld.h
1519 ;; instruction.
1520
1521 (define_expand "extendhisi2"
1522   [(set (match_dup 2)
1523         (ashift:SI (match_operand:HI 1 "register_operand" "")
1524                    (const_int 16)))
1525    (set (match_operand:SI 0 "register_operand" "")
1526        (ashiftrt:SI (match_dup 2)
1527                      (const_int 16)))]
1528   ""
1529   "
1530 {
1531   operands[1] = gen_lowpart (SImode, operands[1]);
1532   operands[2] = gen_reg_rtx (SImode);
1533 }")
1534
1535 ;; ??? The extendqisi2 pattern should not emit shifts for v850e?
1536
1537 (define_insn "*extendqisi_insn"
1538   [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1539         (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,Q,m")))]
1540   "TARGET_V850E"
1541   "@
1542    sxb %0
1543    sld.b %1,%0
1544    ld.b %1,%0"
1545   [(set_attr "length" "2,2,4")
1546    (set_attr "cc" "none_0hit,none_0hit,none_0hit")])
1547
1548 ;; ??? This is missing a sign extend from memory pattern to match the ld.b
1549 ;; instruction.
1550
1551 (define_expand "extendqisi2"
1552   [(set (match_dup 2)
1553         (ashift:SI (match_operand:QI 1 "register_operand" "")
1554                    (const_int 24)))
1555    (set (match_operand:SI 0 "register_operand" "")
1556         (ashiftrt:SI (match_dup 2)
1557                      (const_int 24)))]
1558   ""
1559   "
1560 {
1561   operands[1] = gen_lowpart (SImode, operands[1]);
1562   operands[2] = gen_reg_rtx (SImode);
1563 }")
1564 \f
1565 ;; ----------------------------------------------------------------------
1566 ;; SHIFTS
1567 ;; ----------------------------------------------------------------------
1568
1569 (define_insn "ashlsi3"
1570   [(set (match_operand:SI 0 "register_operand" "=r,r")
1571         (ashift:SI
1572          (match_operand:SI 1 "register_operand" "0,0")
1573          (match_operand:SI 2 "nonmemory_operand" "r,N")))]
1574   ""
1575   "@
1576   shl %2,%0
1577   shl %2,%0"
1578   [(set_attr "length" "4,2")
1579    (set_attr "cc" "set_znv")])
1580
1581 (define_insn "lshrsi3"
1582   [(set (match_operand:SI 0 "register_operand" "=r,r")
1583         (lshiftrt:SI
1584          (match_operand:SI 1 "register_operand" "0,0")
1585          (match_operand:SI 2 "nonmemory_operand" "r,N")))]
1586   ""
1587   "@
1588   shr %2,%0
1589   shr %2,%0"
1590   [(set_attr "length" "4,2")
1591    (set_attr "cc" "set_znv")])
1592
1593 (define_insn "ashrsi3"
1594   [(set (match_operand:SI 0 "register_operand" "=r,r")
1595         (ashiftrt:SI
1596          (match_operand:SI 1 "register_operand" "0,0")
1597          (match_operand:SI 2 "nonmemory_operand" "r,N")))]
1598   ""
1599   "@
1600   sar %2,%0
1601   sar %2,%0"
1602   [(set_attr "length" "4,2")
1603    (set_attr "cc" "set_znv")])
1604
1605 ;; ----------------------------------------------------------------------
1606 ;; PROLOGUE/EPILOGUE
1607 ;; ----------------------------------------------------------------------
1608 (define_expand "prologue"
1609   [(const_int 0)]
1610   ""
1611   "expand_prologue (); DONE;")
1612
1613 (define_expand "epilogue"
1614   [(return)]
1615   ""
1616   "
1617 {
1618   /* Try to use the trivial return first.  Else use the
1619      full epilogue.  */
1620   if (0)
1621     emit_jump_insn (gen_return ());
1622   else
1623     expand_epilogue ();
1624   DONE;
1625 }")
1626
1627 (define_insn "return"
1628   [(return)]
1629   "reload_completed && compute_frame_size (get_frame_size (), (long *)0) == 0"
1630   "jmp [r31]"
1631   [(set_attr "length" "2")
1632    (set_attr "cc" "none")])
1633
1634 (define_insn "return_internal"
1635   [(return)
1636    (use (reg:SI 31))]
1637   ""
1638   "jmp [r31]"
1639   [(set_attr "length" "2")
1640    (set_attr "cc" "none")])
1641
1642
1643 \f
1644 ;; ----------------------------------------------------------------------
1645 ;; HELPER INSTRUCTIONS for saving the prologue and epilog registers
1646 ;; ----------------------------------------------------------------------
1647
1648 ;; This pattern will match a stack adjust RTX followed by any number of push
1649 ;; RTXs.  These RTXs will then be turned into a suitable call to a worker
1650 ;; function.
1651
1652 ;;
1653 ;; Actually, convert the RTXs into a PREPARE instruction.
1654 ;;
1655 (define_insn ""
1656  [(match_parallel 0 "pattern_is_ok_for_prepare"
1657    [(set (reg:SI 3)
1658          (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i")))
1659     (set (mem:SI (plus:SI (reg:SI 3)
1660                           (match_operand:SI 2 "immediate_operand" "i")))
1661          (match_operand:SI 3 "register_is_ok_for_epilogue" "r"))])]
1662  "TARGET_PROLOG_FUNCTION && TARGET_V850E"
1663  "* return construct_prepare_instruction (operands[0]);
1664  "
1665  [(set_attr "length" "4")
1666   (set_attr "cc"     "none")])
1667
1668 (define_insn ""
1669  [(match_parallel 0 "pattern_is_ok_for_prologue"
1670    [(set (reg:SI 3)
1671          (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i")))
1672     (set (mem:SI (plus:SI (reg:SI 3)
1673                            (match_operand:SI 2 "immediate_operand" "i")))
1674          (match_operand:SI 3 "register_is_ok_for_epilogue" "r"))])]
1675  "TARGET_PROLOG_FUNCTION && TARGET_V850"
1676  "* return construct_save_jarl (operands[0]);
1677  "
1678  [(set (attr "length") (if_then_else (eq_attr "long_calls" "yes")
1679                                      (const_string "16")
1680                                      (const_string "4")))
1681   (set_attr "cc"     "clobber")])
1682
1683 ;;
1684 ;; Actually, turn the RTXs into a DISPOSE instruction.
1685 ;;
1686 (define_insn ""
1687  [(match_parallel 0 "pattern_is_ok_for_dispose"
1688    [(return)
1689     (set (reg:SI 3)
1690          (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i")))
1691     (set (match_operand:SI 2 "register_is_ok_for_epilogue" "=r")
1692          (mem:SI (plus:SI (reg:SI 3)
1693                           (match_operand:SI 3 "immediate_operand" "i"))))])]
1694  "TARGET_PROLOG_FUNCTION && TARGET_V850E"
1695  "* return construct_dispose_instruction (operands[0]);
1696  "
1697  [(set_attr "length" "4")
1698   (set_attr "cc"     "none")])
1699
1700 ;; This pattern will match a return RTX followed by any number of pop RTXs
1701 ;; and possible a stack adjustment as well.  These RTXs will be turned into
1702 ;; a suitable call to a worker function.
1703
1704 (define_insn ""
1705 [(match_parallel 0 "pattern_is_ok_for_epilogue"
1706    [(return)
1707     (set (reg:SI 3)
1708          (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i")))
1709     (set (match_operand:SI 2 "register_is_ok_for_epilogue" "=r")
1710          (mem:SI (plus:SI (reg:SI 3)
1711                           (match_operand:SI 3 "immediate_operand" "i"))))])]
1712  "TARGET_PROLOG_FUNCTION && TARGET_V850"
1713  "* return construct_restore_jr (operands[0]);
1714  "
1715  [(set (attr "length") (if_then_else (eq_attr "long_calls" "yes")
1716                                      (const_string "12")
1717                                      (const_string "4")))
1718   (set_attr "cc"     "clobber")])
1719
1720 ;; Initialize an interrupt function.  Do not depend on TARGET_PROLOG_FUNCTION.
1721 (define_insn "callt_save_interrupt"
1722   [(unspec_volatile [(const_int 0)] 2)]
1723     "TARGET_V850E && !TARGET_DISABLE_CALLT"
1724     ;; The CALLT instruction stores the next address of CALLT to CTPC register
1725     ;; without saving its previous value.  So if the interrupt handler
1726     ;; or its caller could possibly execute the CALLT insn, save_interrupt
1727     ;; MUST NOT be called via CALLT.
1728     "*
1729 {
1730   output_asm_insn (\"addi -24,   sp, sp\", operands);
1731   output_asm_insn (\"st.w r10,   12[sp]\", operands);
1732   output_asm_insn (\"stsr ctpc,  r10\",    operands);
1733   output_asm_insn (\"st.w r10,   16[sp]\", operands);
1734   output_asm_insn (\"stsr ctpsw, r10\",    operands);
1735   output_asm_insn (\"st.w r10,   20[sp]\", operands);
1736   output_asm_insn (\"callt ctoff(__callt_save_interrupt)\", operands);
1737   return \"\";
1738 }"
1739    [(set_attr "length" "26")
1740     (set_attr "cc" "none")])
1741
1742 (define_insn "callt_return_interrupt"
1743   [(unspec_volatile [(const_int 0)] 3)]
1744   "TARGET_V850E && !TARGET_DISABLE_CALLT"
1745   "callt ctoff(__callt_return_interrupt)"
1746   [(set_attr "length" "2")
1747    (set_attr "cc" "clobber")])
1748
1749 (define_insn "save_interrupt"
1750   [(set (reg:SI 3) (plus:SI (reg:SI 3) (const_int -16)))
1751    (set (mem:SI (plus:SI (reg:SI 3) (const_int -16))) (reg:SI 30))
1752    (set (mem:SI (plus:SI (reg:SI 3) (const_int -12))) (reg:SI 4))
1753    (set (mem:SI (plus:SI (reg:SI 3) (const_int  -8))) (reg:SI 1))
1754    (set (mem:SI (plus:SI (reg:SI 3) (const_int  -4))) (reg:SI 10))]
1755   ""
1756   "*
1757 {
1758   if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS)
1759     return \"add -16,sp\;st.w r10,12[sp]\;jarl __save_interrupt,r10\";
1760   else
1761     {
1762       output_asm_insn (\"add   -16, sp\", operands);
1763       output_asm_insn (\"st.w  r10, 12[sp]\", operands);
1764       output_asm_insn (\"st.w  ep, 0[sp]\", operands);
1765       output_asm_insn (\"st.w  gp, 4[sp]\", operands);
1766       output_asm_insn (\"st.w  r1, 8[sp]\", operands);
1767       output_asm_insn (\"movhi hi(__ep), r0, ep\", operands);
1768       output_asm_insn (\"movea lo(__ep), ep, ep\", operands);
1769       output_asm_insn (\"movhi hi(__gp), r0, gp\", operands);
1770       output_asm_insn (\"movea lo(__gp), gp, gp\", operands);
1771       return \"\";
1772     }
1773 }"
1774   [(set (attr "length")
1775         (if_then_else (ne (symbol_ref "TARGET_LONG_CALLS") (const_int 0))
1776                        (const_int 10)
1777                        (const_int 34)))
1778    (set_attr "cc" "clobber")])
1779
1780 ;; Restore r1, r4, r10, and return from the interrupt
1781 (define_insn "return_interrupt"
1782   [(return)
1783    (set (reg:SI 3)  (plus:SI (reg:SI 3) (const_int 16)))
1784    (set (reg:SI 10) (mem:SI (plus:SI (reg:SI 3) (const_int 12))))
1785    (set (reg:SI 1)  (mem:SI (plus:SI (reg:SI 3) (const_int  8))))
1786    (set (reg:SI 4)  (mem:SI (plus:SI (reg:SI 3) (const_int  4))))
1787    (set (reg:SI 30) (mem:SI (reg:SI 3)))]
1788   ""
1789   "*
1790 {
1791   if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS)
1792     return \"jr __return_interrupt\";
1793   else
1794     {
1795       output_asm_insn (\"ld.w 0[sp],  ep\",   operands);
1796       output_asm_insn (\"ld.w 4[sp],  gp\",   operands);
1797       output_asm_insn (\"ld.w 8[sp],  r1\",   operands);
1798       output_asm_insn (\"ld.w 12[sp], r10\", operands);
1799       output_asm_insn (\"addi 16, sp, sp\",   operands);
1800       output_asm_insn (\"reti\",            operands);
1801       return \"\";
1802     }
1803 }"
1804   [(set (attr "length")
1805         (if_then_else (ne (symbol_ref "TARGET_LONG_CALLS") (const_int 0))
1806                        (const_int 4)
1807                        (const_int 24)))
1808    (set_attr "cc" "clobber")])
1809
1810 ;; Save all registers except for the registers saved in save_interrupt when
1811 ;; an interrupt function makes a call.
1812 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
1813 ;; all of memory.  This blocks insns from being moved across this point.
1814 ;; This is needed because the rest of the compiler is not ready to handle
1815 ;; insns this complicated.
1816
1817 (define_insn "callt_save_all_interrupt"
1818   [(unspec_volatile [(const_int 0)] 0)]
1819   "TARGET_V850E && !TARGET_DISABLE_CALLT"
1820   "callt ctoff(__callt_save_all_interrupt)"
1821   [(set_attr "length" "2")
1822    (set_attr "cc" "none")])
1823
1824 (define_insn "save_all_interrupt"
1825   [(unspec_volatile [(const_int 0)] 0)]
1826   ""
1827   "*
1828 {
1829   if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS)
1830     return \"jarl __save_all_interrupt,r10\";
1831
1832   output_asm_insn (\"addi -120, sp, sp\", operands);
1833   output_asm_insn (\"mov ep, r1\", operands);
1834   output_asm_insn (\"mov sp, ep\", operands);
1835   output_asm_insn (\"sst.w r31, 116[ep]\", operands);
1836   output_asm_insn (\"sst.w r2,  112[ep]\", operands);
1837   output_asm_insn (\"sst.w gp,  108[ep]\", operands);
1838   output_asm_insn (\"sst.w r6,  104[ep]\", operands);
1839   output_asm_insn (\"sst.w r7,  100[ep]\", operands);
1840   output_asm_insn (\"sst.w r8,   96[ep]\", operands);
1841   output_asm_insn (\"sst.w r9,   92[ep]\", operands);
1842   output_asm_insn (\"sst.w r11,  88[ep]\", operands);
1843   output_asm_insn (\"sst.w r12,  84[ep]\", operands);
1844   output_asm_insn (\"sst.w r13,  80[ep]\", operands);
1845   output_asm_insn (\"sst.w r14,  76[ep]\", operands);
1846   output_asm_insn (\"sst.w r15,  72[ep]\", operands);
1847   output_asm_insn (\"sst.w r16,  68[ep]\", operands);
1848   output_asm_insn (\"sst.w r17,  64[ep]\", operands);
1849   output_asm_insn (\"sst.w r18,  60[ep]\", operands);
1850   output_asm_insn (\"sst.w r19,  56[ep]\", operands);
1851   output_asm_insn (\"sst.w r20,  52[ep]\", operands);
1852   output_asm_insn (\"sst.w r21,  48[ep]\", operands);
1853   output_asm_insn (\"sst.w r22,  44[ep]\", operands);
1854   output_asm_insn (\"sst.w r23,  40[ep]\", operands);
1855   output_asm_insn (\"sst.w r24,  36[ep]\", operands);
1856   output_asm_insn (\"sst.w r25,  32[ep]\", operands);
1857   output_asm_insn (\"sst.w r26,  28[ep]\", operands);
1858   output_asm_insn (\"sst.w r27,  24[ep]\", operands);
1859   output_asm_insn (\"sst.w r28,  20[ep]\", operands);
1860   output_asm_insn (\"sst.w r29,  16[ep]\", operands);
1861   output_asm_insn (\"mov   r1,   ep\", operands);
1862   return \"\";
1863 }"
1864   [(set (attr "length")
1865         (if_then_else (ne (symbol_ref "TARGET_LONG_CALLS") (const_int 0))
1866                        (const_int 4)
1867                        (const_int 62)
1868         ))
1869    (set_attr "cc" "clobber")])
1870
1871 (define_insn "_save_all_interrupt"
1872   [(unspec_volatile [(const_int 0)] 0)]
1873   "TARGET_V850 && ! TARGET_LONG_CALLS"
1874   "jarl __save_all_interrupt,r10"
1875   [(set_attr "length" "4")
1876    (set_attr "cc" "clobber")])
1877
1878 ;; Restore all registers saved when an interrupt function makes a call.
1879 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
1880 ;; all of memory.  This blocks insns from being moved across this point.
1881 ;; This is needed because the rest of the compiler is not ready to handle
1882 ;; insns this complicated.
1883
1884 (define_insn "callt_restore_all_interrupt"
1885   [(unspec_volatile [(const_int 0)] 1)]
1886   "TARGET_V850E && !TARGET_DISABLE_CALLT"
1887   "callt ctoff(__callt_restore_all_interrupt)"
1888   [(set_attr "length" "2")
1889    (set_attr "cc" "none")])
1890
1891 (define_insn "restore_all_interrupt"
1892   [(unspec_volatile [(const_int 0)] 1)]
1893   ""
1894   "*
1895 {
1896   if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS)
1897     return \"jarl __restore_all_interrupt,r10\";
1898   else
1899     {
1900       output_asm_insn (\"mov   ep,      r1\", operands);
1901       output_asm_insn (\"mov   sp,      ep\", operands);
1902       output_asm_insn (\"sld.w 116[ep], r31\", operands);
1903       output_asm_insn (\"sld.w 112[ep], r2\", operands);
1904       output_asm_insn (\"sld.w 108[ep], gp\", operands);
1905       output_asm_insn (\"sld.w 104[ep], r6\", operands);
1906       output_asm_insn (\"sld.w 100[ep], r7\", operands);
1907       output_asm_insn (\"sld.w 96[ep],  r8\", operands);
1908       output_asm_insn (\"sld.w 92[ep],  r9\", operands);
1909       output_asm_insn (\"sld.w 88[ep],  r11\", operands);
1910       output_asm_insn (\"sld.w 84[ep],  r12\", operands);
1911       output_asm_insn (\"sld.w 80[ep],  r13\", operands);
1912       output_asm_insn (\"sld.w 76[ep],  r14\", operands);
1913       output_asm_insn (\"sld.w 72[ep],  r15\", operands);
1914       output_asm_insn (\"sld.w 68[ep],  r16\", operands);
1915       output_asm_insn (\"sld.w 64[ep],  r17\", operands);
1916       output_asm_insn (\"sld.w 60[ep],  r18\", operands);
1917       output_asm_insn (\"sld.w 56[ep],  r19\", operands);
1918       output_asm_insn (\"sld.w 52[ep],  r20\", operands);
1919       output_asm_insn (\"sld.w 48[ep],  r21\", operands);
1920       output_asm_insn (\"sld.w 44[ep],  r22\", operands);
1921       output_asm_insn (\"sld.w 40[ep],  r23\", operands);
1922       output_asm_insn (\"sld.w 36[ep],  r24\", operands);
1923       output_asm_insn (\"sld.w 32[ep],  r25\", operands);
1924       output_asm_insn (\"sld.w 28[ep],  r26\", operands);
1925       output_asm_insn (\"sld.w 24[ep],  r27\", operands);
1926       output_asm_insn (\"sld.w 20[ep],  r28\", operands);
1927       output_asm_insn (\"sld.w 16[ep],  r29\", operands);
1928       output_asm_insn (\"mov   r1,      ep\", operands);
1929       output_asm_insn (\"addi  120, sp, sp\", operands);
1930       return \"\";
1931     }
1932 }"
1933   [(set (attr "length")
1934         (if_then_else (ne (symbol_ref "TARGET_LONG_CALLS") (const_int 0))
1935                        (const_int 4)
1936                        (const_int 62)
1937         ))
1938    (set_attr "cc" "clobber")])
1939
1940 (define_insn "_restore_all_interrupt"
1941   [(unspec_volatile [(const_int 0)] 1)]
1942   "TARGET_V850 && ! TARGET_LONG_CALLS"
1943   "jarl __restore_all_interrupt,r10"
1944   [(set_attr "length" "4")
1945    (set_attr "cc" "clobber")])
1946
1947 ;; Save r6-r9 for a variable argument function
1948 (define_insn "save_r6_r9_v850e"
1949   [(set (mem:SI (reg:SI 3)) (reg:SI 6))
1950    (set (mem:SI (plus:SI (reg:SI 3) (const_int 4))) (reg:SI 7))
1951    (set (mem:SI (plus:SI (reg:SI 3) (const_int 8))) (reg:SI 8))
1952    (set (mem:SI (plus:SI (reg:SI 3) (const_int 12))) (reg:SI 9))
1953   ]
1954   "TARGET_PROLOG_FUNCTION && TARGET_V850E && !TARGET_DISABLE_CALLT"
1955   "callt ctoff(__callt_save_r6_r9)"
1956   [(set_attr "length" "2")
1957    (set_attr "cc" "none")])
1958
1959 (define_insn "save_r6_r9"
1960   [(set (mem:SI (reg:SI 3)) (reg:SI 6))
1961    (set (mem:SI (plus:SI (reg:SI 3) (const_int 4))) (reg:SI 7))
1962    (set (mem:SI (plus:SI (reg:SI 3) (const_int 8))) (reg:SI 8))
1963    (set (mem:SI (plus:SI (reg:SI 3) (const_int 12))) (reg:SI 9))
1964    (clobber (reg:SI 10))]
1965   "TARGET_PROLOG_FUNCTION && ! TARGET_LONG_CALLS"
1966   "jarl __save_r6_r9,r10"
1967   [(set_attr "length" "4")
1968    (set_attr "cc" "clobber")])
1969