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[thirdparty/gcc.git] / gcc / config / v850 / v850.md
1 ;; GCC machine description for NEC V850
2 ;; Copyright (C) 1996, 1997, 1998, 1999, 2002, 2004, 2005, 2007, 2008, 2010,
3 ;; 2011, 2012 Free Software Foundation, Inc.
4 ;; Contributed by Jeff Law (law@cygnus.com).
5
6 ;; This file is part of GCC.
7
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; any later version.
12
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
17
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
21
22 ;; The original PO technology requires these to be ordered by speed,
23 ;; so that assigner will pick the fastest.
24
25 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
26
27 ;; The V851 manual states that the instruction address space is 16M;
28 ;; the various branch/call instructions only have a 22bit offset (4M range).
29 ;;
30 ;; One day we'll probably need to handle calls to targets more than 4M
31 ;; away.
32
33 ;; The size of instructions in bytes.
34
35 ;;---------------------------------------------------------------------------
36 ;; Constants
37
38 ;;
39 (define_constants
40 [(ZERO_REGNUM 0) ; constant zero
41 (SP_REGNUM 3) ; Stack Pointer
42 (GP_REGNUM 4) ; GP Pointer
43 (EP_REGNUM 30) ; EP pointer
44 (LP_REGNUM 31) ; Return address register
45 (CC_REGNUM 32) ; Condition code pseudo register
46 (FCC_REGNUM 33) ; Floating Condition code pseudo register
47 ]
48 )
49
50 (define_attr "length" ""
51 (const_int 4))
52
53 (define_attr "long_calls" "yes,no"
54 (const (if_then_else (symbol_ref "TARGET_LONG_CALLS")
55 (const_string "yes")
56 (const_string "no"))))
57
58 ;; Types of instructions (for scheduling purposes).
59
60 (define_attr "type" "load,store,bit1,mult,macc,div,fpu,single,other"
61 (const_string "other"))
62
63 (define_attr "cpu" "none,v850,v850e,v850e1,v850e2,v850e2v3"
64 (cond [(match_test "TARGET_V850")
65 (const_string "v850")
66 (match_test "TARGET_V850E")
67 (const_string "v850e")
68 (match_test "TARGET_V850E1")
69 (const_string "v850e1")
70 (match_test "TARGET_V850E2")
71 (const_string "v850e2")
72 (match_test "TARGET_V850E2")
73 (const_string "v850e2v3")]
74 (const_string "none")))
75
76 ;; Condition code settings.
77 ;; none - insn does not affect cc
78 ;; none_0hit - insn does not affect cc but it does modify operand 0
79 ;; This attribute is used to keep track of when operand 0 changes.
80 ;; See the description of NOTICE_UPDATE_CC for more info.
81 ;; set_znv - sets z,n,v to usable values; c is unknown.
82 ;; set_zn - sets z,n to usable values; v,c is unknown.
83 ;; compare - compare instruction
84 ;; clobber - value of cc is unknown
85 (define_attr "cc" "none,none_0hit,set_z,set_zn,set_znv,compare,clobber"
86 (const_string "clobber"))
87 \f
88 ;; Function units for the V850. As best as I can tell, there's
89 ;; a traditional memory load/use stall as well as a stall if
90 ;; the result of a multiply is used too early.
91
92 (define_insn_reservation "v850_other" 1
93 (eq_attr "type" "other")
94 "nothing")
95 (define_insn_reservation "v850_mult" 2
96 (eq_attr "type" "mult")
97 "nothing")
98 (define_insn_reservation "v850_memory" 2
99 (eq_attr "type" "load")
100 "nothing")
101
102 (include "predicates.md")
103 (include "constraints.md")
104 \f
105 ;; ----------------------------------------------------------------------
106 ;; MOVE INSTRUCTIONS
107 ;; ----------------------------------------------------------------------
108 (define_insn "sign23byte_load"
109 [(set (match_operand:SI 0 "register_operand" "=r")
110 (sign_extend:SI
111 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "r")
112 (match_operand 2 "disp23_operand" "W")))))]
113 "TARGET_V850E2V3"
114 "ld.b %2[%1],%0"
115 [(set_attr "length" "4")
116 (set_attr "cc" "none_0hit")])
117
118 (define_insn "unsign23byte_load"
119 [(set (match_operand:SI 0 "register_operand" "=r")
120 (zero_extend:SI
121 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "r")
122 (match_operand 2 "disp23_operand" "W")))))]
123 "TARGET_V850E2V3"
124 "ld.bu %2[%1],%0"
125 [(set_attr "length" "4")
126 (set_attr "cc" "none_0hit")])
127
128 (define_insn "sign23hword_load"
129 [(set (match_operand:SI 0 "register_operand" "=r")
130 (sign_extend:SI
131 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "r")
132 (match_operand 2 "disp23_operand" "W")))))]
133 "TARGET_V850E2V3"
134 "ld.h %2[%1],%0"
135 [(set_attr "length" "4")
136 (set_attr "cc" "none_0hit")])
137
138 (define_insn "unsign23hword_load"
139 [(set (match_operand:SI 0 "register_operand" "=r")
140 (zero_extend:SI
141 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "r")
142 (match_operand 2 "disp23_operand" "W")))))]
143 "TARGET_V850E2V3"
144 "ld.hu %2[%1],%0"
145 [(set_attr "length" "4")
146 (set_attr "cc" "none_0hit")])
147
148 (define_insn "23word_load"
149 [(set (match_operand:SI 0 "register_operand" "=r")
150 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
151 (match_operand 2 "disp23_operand" "W"))))]
152 "TARGET_V850E2V3"
153 "ld.w %2[%1],%0"
154 [(set_attr "length" "4")
155 (set_attr "cc" "none_0hit")])
156
157 (define_insn "23byte_store"
158 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "r")
159 (match_operand 1 "disp23_operand" "W")))
160 (match_operand:QI 2 "register_operand" "r"))]
161 "TARGET_V850E2V3"
162 "st.b %2,%1[%0]"
163 [(set_attr "length" "4")
164 (set_attr "cc" "none_0hit")])
165
166 (define_insn "23hword_store"
167 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "r")
168 (match_operand 1 "disp23_operand" "W")))
169 (match_operand:HI 2 "register_operand" "r"))]
170 "TARGET_V850E2V3"
171 "st.h %2,%1[%0]"
172 [(set_attr "length" "4")
173 (set_attr "cc" "none_0hit")])
174
175 (define_insn "23word_store"
176 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
177 (match_operand 1 "disp23_operand" "W")))
178 (match_operand:SI 2 "register_operand" "r"))]
179 "TARGET_V850E2V3"
180 "st.w %2,%1[%0]"
181 [(set_attr "length" "4")
182 (set_attr "cc" "none_0hit")])
183
184 ;; movqi
185
186 (define_expand "movqi"
187 [(set (match_operand:QI 0 "general_operand" "")
188 (match_operand:QI 1 "general_operand" ""))]
189 ""
190 {
191 /* One of the ops has to be in a register or 0 */
192 if (!register_operand (operand0, QImode)
193 && !reg_or_0_operand (operand1, QImode))
194 operands[1] = copy_to_mode_reg (QImode, operand1);
195 })
196
197 (define_insn "*movqi_internal"
198 [(set (match_operand:QI 0 "general_operand" "=r,r,r,Q,r,m,m")
199 (match_operand:QI 1 "general_operand" "Jr,n,Q,Ir,m,r,I"))]
200 "register_operand (operands[0], QImode)
201 || reg_or_0_operand (operands[1], QImode)"
202 {
203 return output_move_single (operands);
204 }
205 [(set_attr "length" "2,4,2,2,4,4,4")
206 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
207 (set_attr "type" "other,other,load,other,load,store,store")])
208
209 ;; movhi
210
211 (define_expand "movhi"
212 [(set (match_operand:HI 0 "general_operand" "")
213 (match_operand:HI 1 "general_operand" ""))]
214 ""
215 {
216 /* One of the ops has to be in a register or 0 */
217 if (!register_operand (operand0, HImode)
218 && !reg_or_0_operand (operand1, HImode))
219 operands[1] = copy_to_mode_reg (HImode, operand1);
220 })
221
222 (define_insn "*movhi_internal"
223 [(set (match_operand:HI 0 "general_operand" "=r,r,r,Q,r,m,m")
224 (match_operand:HI 1 "general_operand" "Jr,n,Q,Ir,m,r,I"))]
225 "register_operand (operands[0], HImode)
226 || reg_or_0_operand (operands[1], HImode)"
227 {
228 return output_move_single (operands);
229 }
230 [(set_attr "length" "2,4,2,2,4,4,4")
231 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
232 (set_attr "type" "other,other,load,other,load,store,store")])
233
234 ;; movsi and helpers
235
236 (define_insn "*movsi_high"
237 [(set (match_operand:SI 0 "register_operand" "=r")
238 (high:SI (match_operand 1 "immediate_operand" "i")))]
239 ""
240 "movhi hi(%1),%.,%0"
241 [(set_attr "length" "4")
242 (set_attr "cc" "none_0hit")
243 (set_attr "type" "other")])
244
245 (define_insn "*movsi_lo"
246 [(set (match_operand:SI 0 "register_operand" "=r")
247 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
248 (match_operand:SI 2 "immediate_operand" "i")))]
249 ""
250 "movea lo(%2),%1,%0"
251 [(set_attr "length" "4")
252 (set_attr "cc" "none_0hit")
253 (set_attr "type" "other")])
254
255 (define_expand "movsi"
256 [(set (match_operand:SI 0 "general_operand" "")
257 (match_operand:SI 1 "general_operand" ""))]
258 ""
259 {
260 /* One of the ops has to be in a register or 0 */
261 if (!register_operand (operand0, SImode)
262 && !reg_or_0_operand (operand1, SImode))
263 operands[1] = copy_to_mode_reg (SImode, operand1);
264
265 /* Some constants, as well as symbolic operands
266 must be done with HIGH & LO_SUM patterns. */
267 if (CONSTANT_P (operands[1])
268 && GET_CODE (operands[1]) != HIGH
269 && ! (TARGET_V850E || TARGET_V850E2_ALL)
270 && !special_symbolref_operand (operands[1], VOIDmode)
271 && !(GET_CODE (operands[1]) == CONST_INT
272 && (CONST_OK_FOR_J (INTVAL (operands[1]))
273 || CONST_OK_FOR_K (INTVAL (operands[1]))
274 || CONST_OK_FOR_L (INTVAL (operands[1])))))
275 {
276 rtx temp;
277
278 if (reload_in_progress || reload_completed)
279 temp = operands[0];
280 else
281 temp = gen_reg_rtx (SImode);
282
283 emit_insn (gen_rtx_SET (SImode, temp,
284 gen_rtx_HIGH (SImode, operand1)));
285 emit_insn (gen_rtx_SET (SImode, operand0,
286 gen_rtx_LO_SUM (SImode, temp, operand1)));
287 DONE;
288 }
289 })
290
291 ;; This is the same as the following pattern, except that it includes
292 ;; support for arbitrary 32-bit immediates.
293
294 ;; ??? This always loads addresses using hilo. If the only use of this address
295 ;; was in a load/store, then we would get smaller code if we only loaded the
296 ;; upper part with hi, and then put the lower part in the load/store insn.
297
298 (define_insn "*movsi_internal_v850e"
299 [(set (match_operand:SI 0 "general_operand" "=r,r,r,r,Q,r,r,m,m,r")
300 (match_operand:SI 1 "general_operand" "Jr,K,L,Q,Ir,m,R,r,I,i"))]
301 "(TARGET_V850E || TARGET_V850E2_ALL)
302 && (register_operand (operands[0], SImode)
303 || reg_or_0_operand (operands[1], SImode))"
304 {
305 return output_move_single (operands);
306 }
307 [(set_attr "length" "2,4,4,2,2,4,4,4,4,6")
308 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
309 (set_attr "type" "other,other,other,load,other,load,other,store,store,other")])
310
311 (define_insn "*movsi_internal"
312 [(set (match_operand:SI 0 "general_operand" "=r,r,r,r,Q,r,r,m,m")
313 (match_operand:SI 1 "movsi_source_operand" "Jr,K,L,Q,Ir,m,R,r,I"))]
314 "register_operand (operands[0], SImode)
315 || reg_or_0_operand (operands[1], SImode)"
316 {
317 return output_move_single (operands);
318 }
319 [(set_attr "length" "2,4,4,2,2,4,4,4,4")
320 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
321 (set_attr "type" "other,other,other,load,other,load,store,store,other")])
322
323 (define_insn "*movsf_internal"
324 [(set (match_operand:SF 0 "general_operand" "=r,r,r,r,r,Q,r,m,m,r")
325 (match_operand:SF 1 "general_operand" "Jr,K,L,n,Q,Ir,m,r,IG,iF"))]
326 "register_operand (operands[0], SFmode)
327 || reg_or_0_operand (operands[1], SFmode)"
328 {
329 return output_move_single (operands);
330 }
331 [(set_attr "length" "2,4,4,8,2,2,4,4,4,8")
332 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
333 (set_attr "type" "other,other,other,other,load,other,load,store,store,other")])
334
335 ;; ----------------------------------------------------------------------
336 ;; TEST INSTRUCTIONS
337 ;; ----------------------------------------------------------------------
338
339 (define_insn "*v850_tst1"
340 [(set (cc0)
341 (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "m")
342 (const_int 1)
343 (match_operand:QI 1 "const_int_operand" "n"))
344 (const_int 0)))]
345 ""
346 "tst1 %1,%0"
347 [(set_attr "length" "4")
348 (set_attr "cc" "clobber")])
349
350 ;; This replaces ld.b;sar;andi with tst1;setf nz.
351
352 (define_split
353 [(set (match_operand:SI 0 "register_operand" "")
354 (compare (zero_extract:SI (match_operand:QI 1 "memory_operand" "")
355 (const_int 1)
356 (match_operand 2 "const_int_operand" ""))
357 (const_int 0)))]
358 ""
359 [(set (cc0) (compare (zero_extract:SI (match_dup 1)
360 (const_int 1)
361 (match_dup 2))
362 (const_int 0)))
363 (set (match_dup 0) (ne:SI (cc0) (const_int 0)))])
364
365 (define_expand "cbranchsi4"
366 [(set (cc0)
367 (compare (match_operand:SI 1 "register_operand" "")
368 (match_operand:SI 2 "reg_or_int5_operand" "")))
369 (set (pc)
370 (if_then_else
371 (match_operator 0 "ordered_comparison_operator" [(cc0)
372 (const_int 0)])
373 (label_ref (match_operand 3 "" ""))
374 (pc)))]
375 "")
376
377 (define_expand "cstoresi4"
378 [(set (cc0)
379 (compare (match_operand:SI 2 "register_operand" "")
380 (match_operand:SI 3 "reg_or_int5_operand" "")))
381 (set (match_operand:SI 0 "register_operand")
382 (match_operator:SI 1 "ordered_comparison_operator" [(cc0)
383 (const_int 0)]))]
384 "")
385
386 (define_expand "cmpsi"
387 [(set (cc0)
388 (compare (match_operand:SI 0 "register_operand" "r,r")
389 (match_operand:SI 1 "reg_or_int5_operand" "r,J")))]
390 ""
391 {
392 v850_compare_op0 = operands[0];
393 v850_compare_op1 = operands[1];
394 DONE;
395 })
396
397 (define_insn "cmpsi_insn"
398 [(set (cc0)
399 (compare (match_operand:SI 0 "register_operand" "r,r")
400 (match_operand:SI 1 "reg_or_int5_operand" "r,J")))]
401 ""
402 "@
403 cmp %1,%0
404 cmp %1,%0"
405 [(set_attr "length" "2,2")
406 (set_attr "cc" "compare")])
407
408 (define_expand "cmpsf"
409 [(set (reg:CC CC_REGNUM)
410 (compare (match_operand:SF 0 "register_operand" "r")
411 (match_operand:SF 1 "register_operand" "r")))]
412 "TARGET_USE_FPU"
413 {
414 v850_compare_op0 = operands[0];
415 v850_compare_op1 = operands[1];
416 DONE;
417 })
418
419 (define_expand "cmpdf"
420 [(set (reg:CC CC_REGNUM)
421 (compare (match_operand:DF 0 "even_reg_operand" "r")
422 (match_operand:DF 1 "even_reg_operand" "r")))]
423 "TARGET_USE_FPU"
424 {
425 v850_compare_op0 = operands[0];
426 v850_compare_op1 = operands[1];
427 DONE;
428 })
429
430 ;; ----------------------------------------------------------------------
431 ;; ADD INSTRUCTIONS
432 ;; ----------------------------------------------------------------------
433
434 (define_insn "addsi3"
435 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
436 (plus:SI (match_operand:SI 1 "register_operand" "%0,r,r")
437 (match_operand:SI 2 "nonmemory_operand" "rJ,K,U")))
438 (clobber (reg:CC CC_REGNUM))]
439
440 ""
441 "@
442 add %2,%0
443 addi %2,%1,%0
444 addi %O2(%P2),%1,%0"
445 [(set_attr "length" "2,4,4")
446 (set_attr "cc" "set_zn,set_zn,set_zn")])
447
448 ;; ----------------------------------------------------------------------
449 ;; SUBTRACT INSTRUCTIONS
450 ;; ----------------------------------------------------------------------
451
452 (define_insn "subsi3"
453 [(set (match_operand:SI 0 "register_operand" "=r,r")
454 (minus:SI (match_operand:SI 1 "register_operand" "0,r")
455 (match_operand:SI 2 "register_operand" "r,0")))
456 (clobber (reg:CC CC_REGNUM))]
457 ""
458 "@
459 sub %2,%0
460 subr %1,%0"
461 [(set_attr "length" "2,2")
462 (set_attr "cc" "set_zn,set_zn")])
463
464 (define_insn "negsi2"
465 [(set (match_operand:SI 0 "register_operand" "=r")
466 (neg:SI (match_operand:SI 1 "register_operand" "0")))
467 (clobber (reg:CC CC_REGNUM))]
468 ""
469 "subr %.,%0"
470 [(set_attr "length" "2")
471 (set_attr "cc" "set_zn")])
472
473 ;; ----------------------------------------------------------------------
474 ;; MULTIPLY INSTRUCTIONS
475 ;; ----------------------------------------------------------------------
476
477 (define_expand "mulhisi3"
478 [(set (match_operand:SI 0 "register_operand" "")
479 (mult:SI
480 (sign_extend:SI (match_operand:HI 1 "register_operand" ""))
481 (sign_extend:SI (match_operand:HI 2 "nonmemory_operand" ""))))]
482 ""
483 {
484 if (GET_CODE (operands[2]) == CONST_INT)
485 {
486 emit_insn (gen_mulhisi3_internal2 (operands[0], operands[1], operands[2]));
487 DONE;
488 }
489 })
490
491 (define_insn "*mulhisi3_internal1"
492 [(set (match_operand:SI 0 "register_operand" "=r")
493 (mult:SI
494 (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
495 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
496 ""
497 "mulh %2,%0"
498 [(set_attr "length" "2")
499 (set_attr "cc" "none_0hit")
500 (set_attr "type" "mult")])
501
502 (define_insn "mulhisi3_internal2"
503 [(set (match_operand:SI 0 "register_operand" "=r,r")
504 (mult:SI
505 (sign_extend:SI (match_operand:HI 1 "register_operand" "%0,r"))
506 (match_operand:HI 2 "const_int_operand" "J,K")))]
507 ""
508 "@
509 mulh %2,%0
510 mulhi %2,%1,%0"
511 [(set_attr "length" "2,4")
512 (set_attr "cc" "none_0hit,none_0hit")
513 (set_attr "type" "mult")])
514
515 ;; ??? The scheduling info is probably wrong.
516
517 ;; ??? This instruction can also generate the 32-bit highpart, but using it
518 ;; may increase code size counter to the desired result.
519
520 ;; ??? This instructions can also give a DImode result.
521
522 ;; ??? There is unsigned version, but it matters only for the DImode/highpart
523 ;; results.
524
525 (define_insn "mulsi3"
526 [(set (match_operand:SI 0 "register_operand" "=r")
527 (mult:SI (match_operand:SI 1 "register_operand" "%0")
528 (match_operand:SI 2 "reg_or_int9_operand" "rO")))]
529 "(TARGET_V850E || TARGET_V850E2_ALL)"
530 "mul %2,%1,%."
531 [(set_attr "length" "4")
532 (set_attr "cc" "none_0hit")
533 (set_attr "type" "mult")])
534
535 ;; ----------------------------------------------------------------------
536 ;; DIVIDE INSTRUCTIONS
537 ;; ----------------------------------------------------------------------
538
539 ;; ??? These insns do set the Z/N condition codes, except that they are based
540 ;; on only one of the two results, so it doesn't seem to make sense to use
541 ;; them.
542
543 ;; ??? The scheduling info is probably wrong.
544
545 (define_insn "divmodsi4"
546 [(set (match_operand:SI 0 "register_operand" "=r")
547 (div:SI (match_operand:SI 1 "register_operand" "0")
548 (match_operand:SI 2 "register_operand" "r")))
549 (set (match_operand:SI 3 "register_operand" "=r")
550 (mod:SI (match_dup 1)
551 (match_dup 2)))
552 (clobber (reg:CC CC_REGNUM))]
553 "TARGET_V850E || TARGET_V850E2_ALL"
554 {
555 if (TARGET_V850E2_ALL)
556 return "divq %2,%0,%3";
557 else
558 return "div %2,%0,%3";
559 }
560 [(set_attr "length" "4")
561 (set_attr "cc" "clobber")
562 (set_attr "type" "div")])
563
564 (define_insn "udivmodsi4"
565 [(set (match_operand:SI 0 "register_operand" "=r")
566 (udiv:SI (match_operand:SI 1 "register_operand" "0")
567 (match_operand:SI 2 "register_operand" "r")))
568 (set (match_operand:SI 3 "register_operand" "=r")
569 (umod:SI (match_dup 1)
570 (match_dup 2)))
571 (clobber (reg:CC CC_REGNUM))]
572 "TARGET_V850E || TARGET_V850E2_ALL"
573 {
574 if (TARGET_V850E2_ALL)
575 return "divqu %2,%0,%3";
576 else
577 return "divu %2,%0,%3";
578 }
579 [(set_attr "length" "4")
580 (set_attr "cc" "clobber")
581 (set_attr "type" "div")])
582
583 ;; ??? There is a 2 byte instruction for generating only the quotient.
584 ;; However, it isn't clear how to compute the length field correctly.
585
586 (define_insn "divmodhi4"
587 [(set (match_operand:HI 0 "register_operand" "=r")
588 (div:HI (match_operand:HI 1 "register_operand" "0")
589 (match_operand:HI 2 "register_operand" "r")))
590 (set (match_operand:HI 3 "register_operand" "=r")
591 (mod:HI (match_dup 1)
592 (match_dup 2)))
593 (clobber (reg:CC CC_REGNUM))]
594 "TARGET_V850E || TARGET_V850E2_ALL"
595 "divh %2,%0,%3"
596 [(set_attr "length" "4")
597 (set_attr "cc" "clobber")
598 (set_attr "type" "div")])
599
600 ;; Half-words are sign-extended by default, so we must zero extend to a word
601 ;; here before doing the divide.
602
603 (define_insn "udivmodhi4"
604 [(set (match_operand:HI 0 "register_operand" "=r")
605 (udiv:HI (match_operand:HI 1 "register_operand" "0")
606 (match_operand:HI 2 "register_operand" "r")))
607 (set (match_operand:HI 3 "register_operand" "=r")
608 (umod:HI (match_dup 1)
609 (match_dup 2)))
610 (clobber (reg:CC CC_REGNUM))]
611 "TARGET_V850E || TARGET_V850E2_ALL"
612 "zxh %0 ; divhu %2,%0,%3"
613 [(set_attr "length" "4")
614 (set_attr "cc" "clobber")
615 (set_attr "type" "div")])
616 \f
617 ;; ----------------------------------------------------------------------
618 ;; AND INSTRUCTIONS
619 ;; ----------------------------------------------------------------------
620
621 (define_insn "*v850_clr1_1"
622 [(set (match_operand:QI 0 "memory_operand" "=m")
623 (subreg:QI
624 (and:SI (subreg:SI (match_dup 0) 0)
625 (match_operand:QI 1 "not_power_of_two_operand" "")) 0))
626 (clobber (reg:CC CC_REGNUM))]
627 ""
628 {
629 rtx xoperands[2];
630 xoperands[0] = operands[0];
631 xoperands[1] = GEN_INT (~INTVAL (operands[1]) & 0xff);
632 output_asm_insn ("clr1 %M1,%0", xoperands);
633 return "";
634 }
635 [(set_attr "length" "4")
636 (set_attr "cc" "clobber")
637 (set_attr "type" "bit1")])
638
639 (define_insn "*v850_clr1_2"
640 [(set (match_operand:HI 0 "indirect_operand" "=m")
641 (subreg:HI
642 (and:SI (subreg:SI (match_dup 0) 0)
643 (match_operand:HI 1 "not_power_of_two_operand" "")) 0))
644 (clobber (reg:CC CC_REGNUM))]
645 ""
646 {
647 int log2 = exact_log2 (~INTVAL (operands[1]) & 0xffff);
648
649 rtx xoperands[2];
650 xoperands[0] = gen_rtx_MEM (QImode,
651 plus_constant (Pmode, XEXP (operands[0], 0),
652 log2 / 8));
653 xoperands[1] = GEN_INT (log2 % 8);
654 output_asm_insn ("clr1 %1,%0", xoperands);
655 return "";
656 }
657 [(set_attr "length" "4")
658 (set_attr "cc" "clobber")
659 (set_attr "type" "bit1")])
660
661 (define_insn "*v850_clr1_3"
662 [(set (match_operand:SI 0 "indirect_operand" "=m")
663 (and:SI (match_dup 0)
664 (match_operand:SI 1 "not_power_of_two_operand" "")))
665 (clobber (reg:CC CC_REGNUM))]
666 ""
667 {
668 int log2 = exact_log2 (~INTVAL (operands[1]) & 0xffffffff);
669
670 rtx xoperands[2];
671 xoperands[0] = gen_rtx_MEM (QImode,
672 plus_constant (Pmode, XEXP (operands[0], 0),
673 log2 / 8));
674 xoperands[1] = GEN_INT (log2 % 8);
675 output_asm_insn ("clr1 %1,%0", xoperands);
676 return "";
677 }
678 [(set_attr "length" "4")
679 (set_attr "cc" "clobber")
680 (set_attr "type" "bit1")])
681
682 (define_insn "andsi3"
683 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
684 (and:SI (match_operand:SI 1 "register_operand" "%0,0,r")
685 (match_operand:SI 2 "nonmemory_operand" "r,I,M")))
686 (clobber (reg:CC CC_REGNUM))]
687 ""
688 "@
689 and %2,%0
690 and %.,%0
691 andi %2,%1,%0"
692 [(set_attr "length" "2,2,4")
693 (set_attr "cc" "set_zn")])
694
695 ;; ----------------------------------------------------------------------
696 ;; OR INSTRUCTIONS
697 ;; ----------------------------------------------------------------------
698
699 (define_insn "*v850_set1_1"
700 [(set (match_operand:QI 0 "memory_operand" "=m")
701 (subreg:QI (ior:SI (subreg:SI (match_dup 0) 0)
702 (match_operand 1 "power_of_two_operand" "")) 0))
703 (clobber (reg:CC CC_REGNUM))]
704 ""
705 "set1 %M1,%0"
706 [(set_attr "length" "4")
707 (set_attr "cc" "clobber")
708 (set_attr "type" "bit1")])
709
710 (define_insn "*v850_set1_2"
711 [(set (match_operand:HI 0 "indirect_operand" "=m")
712 (subreg:HI (ior:SI (subreg:SI (match_dup 0) 0)
713 (match_operand 1 "power_of_two_operand" "")) 0))]
714 ""
715 {
716 int log2 = exact_log2 (INTVAL (operands[1]));
717
718 if (log2 < 8)
719 return "set1 %M1,%0";
720 else
721 {
722 rtx xoperands[2];
723 xoperands[0] = gen_rtx_MEM (QImode,
724 plus_constant (Pmode, XEXP (operands[0], 0),
725 log2 / 8));
726 xoperands[1] = GEN_INT (log2 % 8);
727 output_asm_insn ("set1 %1,%0", xoperands);
728 }
729 return "";
730 }
731 [(set_attr "length" "4")
732 (set_attr "cc" "clobber")
733 (set_attr "type" "bit1")])
734
735 (define_insn "*v850_set1_3"
736 [(set (match_operand:SI 0 "indirect_operand" "=m")
737 (ior:SI (match_dup 0)
738 (match_operand 1 "power_of_two_operand" "")))
739 (clobber (reg:CC CC_REGNUM))]
740 ""
741 {
742 int log2 = exact_log2 (INTVAL (operands[1]));
743
744 if (log2 < 8)
745 return "set1 %M1,%0";
746 else
747 {
748 rtx xoperands[2];
749 xoperands[0] = gen_rtx_MEM (QImode,
750 plus_constant (Pmode, XEXP (operands[0], 0),
751 log2 / 8));
752 xoperands[1] = GEN_INT (log2 % 8);
753 output_asm_insn ("set1 %1,%0", xoperands);
754 }
755 return "";
756 }
757 [(set_attr "length" "4")
758 (set_attr "cc" "clobber")
759 (set_attr "type" "bit1")])
760
761 (define_insn "iorsi3"
762 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
763 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,r")
764 (match_operand:SI 2 "nonmemory_operand" "r,I,M")))
765 (clobber (reg:CC CC_REGNUM))]
766 ""
767 "@
768 or %2,%0
769 or %.,%0
770 ori %2,%1,%0"
771 [(set_attr "length" "2,2,4")
772 (set_attr "cc" "set_zn")])
773
774 ;; ----------------------------------------------------------------------
775 ;; XOR INSTRUCTIONS
776 ;; ----------------------------------------------------------------------
777
778 (define_insn "*v850_not1_1"
779 [(set (match_operand:QI 0 "memory_operand" "=m")
780 (subreg:QI (xor:SI (subreg:SI (match_dup 0) 0)
781 (match_operand 1 "power_of_two_operand" "")) 0))
782 (clobber (reg:CC CC_REGNUM))]
783 ""
784 "not1 %M1,%0"
785 [(set_attr "length" "4")
786 (set_attr "cc" "clobber")
787 (set_attr "type" "bit1")])
788
789 (define_insn "*v850_not1_2"
790 [(set (match_operand:HI 0 "indirect_operand" "=m")
791 (subreg:HI (xor:SI (subreg:SI (match_dup 0) 0)
792 (match_operand 1 "power_of_two_operand" "")) 0))]
793 ""
794 {
795 int log2 = exact_log2 (INTVAL (operands[1]));
796
797 if (log2 < 8)
798 return "not1 %M1,%0";
799 else
800 {
801 rtx xoperands[2];
802 xoperands[0] = gen_rtx_MEM (QImode,
803 plus_constant (Pmode, XEXP (operands[0], 0),
804 log2 / 8));
805 xoperands[1] = GEN_INT (log2 % 8);
806 output_asm_insn ("not1 %1,%0", xoperands);
807 }
808 return "";
809 }
810 [(set_attr "length" "4")
811 (set_attr "cc" "clobber")
812 (set_attr "type" "bit1")])
813
814 (define_insn "*v850_not1_3"
815 [(set (match_operand:SI 0 "indirect_operand" "=m")
816 (xor:SI (match_dup 0)
817 (match_operand 1 "power_of_two_operand" "")))
818 (clobber (reg:CC CC_REGNUM))]
819 ""
820 {
821 int log2 = exact_log2 (INTVAL (operands[1]));
822
823 if (log2 < 8)
824 return "not1 %M1,%0";
825 else
826 {
827 rtx xoperands[2];
828 xoperands[0] = gen_rtx_MEM (QImode,
829 plus_constant (Pmode, XEXP (operands[0], 0),
830 log2 / 8));
831 xoperands[1] = GEN_INT (log2 % 8);
832 output_asm_insn ("not1 %1,%0", xoperands);
833 }
834 return "";
835 }
836 [(set_attr "length" "4")
837 (set_attr "cc" "clobber")
838 (set_attr "type" "bit1")])
839
840 (define_insn "xorsi3"
841 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
842 (xor:SI (match_operand:SI 1 "register_operand" "%0,0,r")
843 (match_operand:SI 2 "nonmemory_operand" "r,I,M")))
844 (clobber (reg:CC CC_REGNUM))]
845 ""
846 "@
847 xor %2,%0
848 xor %.,%0
849 xori %2,%1,%0"
850 [(set_attr "length" "2,2,4")
851 (set_attr "cc" "set_zn")])
852 \f
853 ;; ----------------------------------------------------------------------
854 ;; NOT INSTRUCTIONS
855 ;; ----------------------------------------------------------------------
856
857 (define_insn "one_cmplsi2"
858 [(set (match_operand:SI 0 "register_operand" "=r")
859 (not:SI (match_operand:SI 1 "register_operand" "r")))
860 (clobber (reg:CC CC_REGNUM))]
861 ""
862 "not %1,%0"
863 [(set_attr "length" "2")
864 (set_attr "cc" "set_zn")])
865
866 ;; -----------------------------------------------------------------
867 ;; BIT FIELDS
868 ;; -----------------------------------------------------------------
869
870 ;; ??? Is it worth defining insv and extv for the V850 series?!?
871
872 ;; An insv pattern would be useful, but does not get used because
873 ;; store_bit_field never calls insv when storing a constant value into a
874 ;; single-bit bitfield.
875
876 ;; extv/extzv patterns would be useful, but do not get used because
877 ;; optimize_bitfield_compare in fold-const usually converts single
878 ;; bit extracts into an AND with a mask.
879
880 ;; -----------------------------------------------------------------
881 ;; Scc INSTRUCTIONS
882 ;; -----------------------------------------------------------------
883
884 (define_insn "*setcc"
885 [(set (match_operand:SI 0 "register_operand" "=r")
886 (match_operator:SI 1 "comparison_operator"
887 [(cc0) (const_int 0)]))]
888 ""
889 {
890 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
891 && (GET_CODE (operands[1]) == GT
892 || GET_CODE (operands[1]) == GE
893 || GET_CODE (operands[1]) == LE
894 || GET_CODE (operands[1]) == LT))
895 return 0;
896
897 return "setf %c1,%0";
898 }
899 [(set_attr "length" "4")
900 (set_attr "cc" "none_0hit")])
901
902 (define_insn "setf_insn"
903 [(set (match_operand:SI 0 "register_operand" "=r")
904 (match_operator:SI 1 "comparison_operator"
905 [(reg:CC CC_REGNUM) (const_int 0)]))]
906 ""
907 "setf %b1,%0"
908 [(set_attr "length" "4")
909 (set_attr "cc" "none_0hit")])
910
911 (define_insn "set_z_insn"
912 [(set (match_operand:SI 0 "register_operand" "=r")
913 (match_operand 1 "v850_float_z_comparison_operator" ""))]
914 "TARGET_V850E2V3"
915 "setf z,%0"
916 [(set_attr "length" "4")
917 (set_attr "cc" "none_0hit")])
918
919 (define_insn "set_nz_insn"
920 [(set (match_operand:SI 0 "register_operand" "=r")
921 (match_operand 1 "v850_float_nz_comparison_operator" ""))]
922 "TARGET_V850E2V3"
923 "setf nz,%0"
924 [(set_attr "length" "4")
925 (set_attr "cc" "none_0hit")])
926
927 ;; ----------------------------------------------------------------------
928 ;; CONDITIONAL MOVE INSTRUCTIONS
929 ;; ----------------------------------------------------------------------
930
931 ;; Instructions using cc0 aren't allowed to have input reloads, so we must
932 ;; hide the fact that this instruction uses cc0. We do so by including the
933 ;; compare instruction inside it.
934
935 (define_expand "movsicc"
936 [(set (match_operand:SI 0 "register_operand" "=r")
937 (if_then_else:SI
938 (match_operand 1 "comparison_operator")
939 (match_operand:SI 2 "reg_or_const_operand" "rJ")
940 (match_operand:SI 3 "reg_or_const_operand" "rI")))]
941 "(TARGET_V850E || TARGET_V850E2_ALL)"
942 {
943 if ((GET_CODE (operands[2]) == CONST_INT
944 && GET_CODE (operands[3]) == CONST_INT))
945 {
946 int o2 = INTVAL (operands[2]);
947 int o3 = INTVAL (operands[3]);
948
949 if (o2 == 1 && o3 == 0)
950 FAIL; /* setf */
951 if (o3 == 1 && o2 == 0)
952 FAIL; /* setf */
953 if (o2 == 0 && (o3 < -16 || o3 > 15) && exact_log2 (o3) >= 0)
954 FAIL; /* setf + shift */
955 if (o3 == 0 && (o2 < -16 || o2 > 15) && exact_log2 (o2) >=0)
956 FAIL; /* setf + shift */
957 if (o2 != 0)
958 operands[2] = copy_to_mode_reg (SImode, operands[2]);
959 if (o3 !=0 )
960 operands[3] = copy_to_mode_reg (SImode, operands[3]);
961 }
962 else
963 {
964 if (GET_CODE (operands[2]) != REG)
965 operands[2] = copy_to_mode_reg (SImode,operands[2]);
966 if (GET_CODE (operands[3]) != REG)
967 operands[3] = copy_to_mode_reg (SImode, operands[3]);
968 }
969 })
970
971 ;; ??? Clobbering the condition codes is overkill.
972
973 ;; ??? We sometimes emit an unnecessary compare instruction because the
974 ;; condition codes may have already been set by an earlier instruction,
975 ;; but we have no code here to avoid the compare if it is unnecessary.
976
977 (define_insn "movsicc_normal_cc"
978 [(set (match_operand:SI 0 "register_operand" "=r")
979 (if_then_else:SI
980 (match_operator 1 "comparison_operator"
981 [(reg:CC CC_REGNUM) (const_int 0)])
982 (match_operand:SI 2 "reg_or_int5_operand" "rJ")
983 (match_operand:SI 3 "reg_or_0_operand" "rI")))]
984 "(TARGET_V850E || TARGET_V850E2_ALL)"
985 "cmov %c1,%2,%z3,%0";
986 [(set_attr "length" "6")
987 (set_attr "cc" "compare")])
988
989 (define_insn "movsicc_reversed_cc"
990 [(set (match_operand:SI 0 "register_operand" "=r")
991 (if_then_else:SI
992 (match_operator 1 "comparison_operator"
993 [(reg:CC CC_REGNUM) (const_int 0)])
994 (match_operand:SI 2 "reg_or_0_operand" "rI")
995 (match_operand:SI 3 "reg_or_int5_operand" "rJ")))]
996 "(TARGET_V850E || TARGET_V850E2_ALL)"
997 "cmov %C1,%3,%z2,%0"
998 [(set_attr "length" "6")
999 (set_attr "cc" "compare")])
1000
1001 (define_insn "*movsicc_normal"
1002 [(set (match_operand:SI 0 "register_operand" "=r")
1003 (if_then_else:SI
1004 (match_operator 1 "comparison_operator"
1005 [(match_operand:SI 4 "register_operand" "r")
1006 (match_operand:SI 5 "reg_or_int5_operand" "rJ")])
1007 (match_operand:SI 2 "reg_or_int5_operand" "rJ")
1008 (match_operand:SI 3 "reg_or_0_operand" "rI")))]
1009 "(TARGET_V850E || TARGET_V850E2_ALL)"
1010 "cmp %5,%4 ; cmov %c1,%2,%z3,%0"
1011 [(set_attr "length" "6")
1012 (set_attr "cc" "clobber")])
1013
1014 (define_insn "*movsicc_reversed"
1015 [(set (match_operand:SI 0 "register_operand" "=r")
1016 (if_then_else:SI
1017 (match_operator 1 "comparison_operator"
1018 [(match_operand:SI 4 "register_operand" "r")
1019 (match_operand:SI 5 "reg_or_int5_operand" "rJ")])
1020 (match_operand:SI 2 "reg_or_0_operand" "rI")
1021 (match_operand:SI 3 "reg_or_int5_operand" "rJ")))]
1022 "(TARGET_V850E || TARGET_V850E2_ALL)"
1023 "cmp %5,%4 ; cmov %C1,%3,%z2,%0"
1024 [(set_attr "length" "6")
1025 (set_attr "cc" "clobber")])
1026
1027 (define_insn "*movsicc_tst1"
1028 [(set (match_operand:SI 0 "register_operand" "=r")
1029 (if_then_else:SI
1030 (match_operator 1 "comparison_operator"
1031 [(zero_extract:SI
1032 (match_operand:QI 2 "memory_operand" "m")
1033 (const_int 1)
1034 (match_operand 3 "const_int_operand" "n"))
1035 (const_int 0)])
1036 (match_operand:SI 4 "reg_or_int5_operand" "rJ")
1037 (match_operand:SI 5 "reg_or_0_operand" "rI")))]
1038 "(TARGET_V850E || TARGET_V850E2_ALL)"
1039 "tst1 %3,%2 ; cmov %c1,%4,%z5,%0"
1040 [(set_attr "length" "8")
1041 (set_attr "cc" "clobber")])
1042
1043 (define_insn "*movsicc_tst1_reversed"
1044 [(set (match_operand:SI 0 "register_operand" "=r")
1045 (if_then_else:SI
1046 (match_operator 1 "comparison_operator"
1047 [(zero_extract:SI
1048 (match_operand:QI 2 "memory_operand" "m")
1049 (const_int 1)
1050 (match_operand 3 "const_int_operand" "n"))
1051 (const_int 0)])
1052 (match_operand:SI 4 "reg_or_0_operand" "rI")
1053 (match_operand:SI 5 "reg_or_int5_operand" "rJ")))]
1054 "(TARGET_V850E || TARGET_V850E2_ALL)"
1055 "tst1 %3,%2 ; cmov %C1,%5,%z4,%0"
1056 [(set_attr "length" "8")
1057 (set_attr "cc" "clobber")])
1058
1059 ;; Matching for sasf requires combining 4 instructions, so we provide a
1060 ;; dummy pattern to match the first 3, which will always be turned into the
1061 ;; second pattern by subsequent combining. As above, we must include the
1062 ;; comparison to avoid input reloads in an insn using cc0.
1063
1064 (define_insn "*sasf"
1065 [(set (match_operand:SI 0 "register_operand" "=r")
1066 (ior:SI
1067 (match_operator 1 "comparison_operator"
1068 [(match_operand:SI 3 "register_operand" "r")
1069 (match_operand:SI 4 "reg_or_int5_operand" "rJ")])
1070 (ashift:SI (match_operand:SI 2 "register_operand" "0")
1071 (const_int 1))))
1072 (clobber (reg:CC CC_REGNUM))]
1073 "(TARGET_V850E || TARGET_V850E2_ALL)"
1074 "cmp %4,%3 ; sasf %c1,%0"
1075 [(set_attr "length" "6")
1076 (set_attr "cc" "clobber")])
1077
1078 (define_split
1079 [(set (match_operand:SI 0 "register_operand" "")
1080 (if_then_else:SI
1081 (match_operator 1 "comparison_operator"
1082 [(match_operand:SI 4 "register_operand" "")
1083 (match_operand:SI 5 "reg_or_int5_operand" "")])
1084 (match_operand:SI 2 "const_int_operand" "")
1085 (match_operand:SI 3 "const_int_operand" "")))
1086 (clobber (reg:CC CC_REGNUM))]
1087 "(TARGET_V850E || TARGET_V850E2_ALL)
1088 && ((INTVAL (operands[2]) ^ INTVAL (operands[3])) == 1)
1089 && ((INTVAL (operands[2]) + INTVAL (operands[3])) != 1)
1090 && (GET_CODE (operands[5]) == CONST_INT
1091 || REGNO (operands[0]) != REGNO (operands[5]))
1092 && REGNO (operands[0]) != REGNO (operands[4])"
1093 [(set (match_dup 0) (match_dup 6))
1094 (parallel [(set (match_dup 0)
1095 (ior:SI (match_op_dup 7 [(match_dup 4) (match_dup 5)])
1096 (ashift:SI (match_dup 0) (const_int 1))))
1097 (clobber (reg:CC CC_REGNUM))])]
1098 {
1099 operands[6] = GEN_INT (INTVAL (operands[2]) >> 1);
1100 if (INTVAL (operands[2]) & 0x1)
1101 operands[7] = operands[1];
1102 else
1103 operands[7] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[1])),
1104 GET_MODE (operands[1]),
1105 XEXP (operands[1], 0), XEXP (operands[1], 1));
1106 })
1107
1108 ;; ---------------------------------------------------------------------
1109 ;; BYTE SWAP INSTRUCTIONS
1110 ;; ---------------------------------------------------------------------
1111 (define_expand "rotlhi3"
1112 [(parallel [(set (match_operand:HI 0 "register_operand" "")
1113 (rotate:HI (match_operand:HI 1 "register_operand" "")
1114 (match_operand:HI 2 "const_int_operand" "")))
1115 (clobber (reg:CC CC_REGNUM))])]
1116 "(TARGET_V850E || TARGET_V850E2_ALL)"
1117 {
1118 if (INTVAL (operands[2]) != 8)
1119 FAIL;
1120 })
1121
1122 (define_insn "*rotlhi3_8"
1123 [(set (match_operand:HI 0 "register_operand" "=r")
1124 (rotate:HI (match_operand:HI 1 "register_operand" "r")
1125 (const_int 8)))
1126 (clobber (reg:CC CC_REGNUM))]
1127 "(TARGET_V850E || TARGET_V850E2_ALL)"
1128 "bsh %1,%0"
1129 [(set_attr "length" "4")
1130 (set_attr "cc" "clobber")])
1131
1132 (define_expand "rotlsi3"
1133 [(parallel [(set (match_operand:SI 0 "register_operand" "")
1134 (rotate:SI (match_operand:SI 1 "register_operand" "")
1135 (match_operand:SI 2 "const_int_operand" "")))
1136 (clobber (reg:CC CC_REGNUM))])]
1137 "(TARGET_V850E || TARGET_V850E2_ALL)"
1138 {
1139 if (INTVAL (operands[2]) != 16)
1140 FAIL;
1141 })
1142
1143 (define_insn "*rotlsi3_16"
1144 [(set (match_operand:SI 0 "register_operand" "=r")
1145 (rotate:SI (match_operand:SI 1 "register_operand" "r")
1146 (const_int 16)))
1147 (clobber (reg:CC CC_REGNUM))]
1148 "(TARGET_V850E || TARGET_V850E2_ALL)"
1149 "hsw %1,%0"
1150 [(set_attr "length" "4")
1151 (set_attr "cc" "clobber")])
1152
1153 ;; ----------------------------------------------------------------------
1154 ;; JUMP INSTRUCTIONS
1155 ;; ----------------------------------------------------------------------
1156
1157 ;; Conditional jump instructions
1158
1159 (define_insn "*branch_normal"
1160 [(set (pc)
1161 (if_then_else (match_operator 1 "comparison_operator"
1162 [(cc0) (const_int 0)])
1163 (label_ref (match_operand 0 "" ""))
1164 (pc)))]
1165 ""
1166 {
1167 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1168 && (GET_CODE (operands[1]) == GT
1169 || GET_CODE (operands[1]) == GE
1170 || GET_CODE (operands[1]) == LE
1171 || GET_CODE (operands[1]) == LT))
1172 return 0;
1173
1174 if (get_attr_length (insn) == 2)
1175 return "b%b1 %l0";
1176 else
1177 return "b%B1 .+6 ; jr %l0";
1178 }
1179 [(set (attr "length")
1180 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
1181 (const_int 256))
1182 (const_int 2)
1183 (const_int 6)))
1184 (set_attr "cc" "none")])
1185
1186 (define_insn "*branch_invert"
1187 [(set (pc)
1188 (if_then_else (match_operator 1 "comparison_operator"
1189 [(cc0) (const_int 0)])
1190 (pc)
1191 (label_ref (match_operand 0 "" ""))))]
1192 ""
1193 {
1194 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1195 && (GET_CODE (operands[1]) == GT
1196 || GET_CODE (operands[1]) == GE
1197 || GET_CODE (operands[1]) == LE
1198 || GET_CODE (operands[1]) == LT))
1199 return 0;
1200 if (get_attr_length (insn) == 2)
1201 return "b%B1 %l0";
1202 else
1203 return "b%b1 .+6 ; jr %l0";
1204 }
1205 [(set (attr "length")
1206 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
1207 (const_int 256))
1208 (const_int 2)
1209 (const_int 6)))
1210 (set_attr "cc" "none")])
1211
1212 (define_insn "branch_z_normal"
1213 [(set (pc)
1214 (if_then_else (match_operand 1 "v850_float_z_comparison_operator" "")
1215 (label_ref (match_operand 0 "" ""))
1216 (pc)))]
1217 "TARGET_V850E2V3"
1218 {
1219 if (get_attr_length (insn) == 2)
1220 return "bz %l0";
1221 else
1222 return "bnz 1f ; jr %l0 ; 1:";
1223 }
1224 [(set (attr "length")
1225 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
1226 (const_int 256))
1227 (const_int 2)
1228 (const_int 6)))
1229 (set_attr "cc" "none")])
1230
1231 (define_insn "*branch_z_invert"
1232 [(set (pc)
1233 (if_then_else (match_operand 1 "v850_float_z_comparison_operator" "")
1234 (pc)
1235 (label_ref (match_operand 0 "" ""))))]
1236 "TARGET_V850E2V3"
1237 {
1238 if (get_attr_length (insn) == 2)
1239 return "bnz %l0";
1240 else
1241 return "bz 1f ; jr %l0 ; 1:";
1242 }
1243 [(set (attr "length")
1244 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
1245 (const_int 256))
1246 (const_int 2)
1247 (const_int 6)))
1248 (set_attr "cc" "none")])
1249
1250 (define_insn "branch_nz_normal"
1251 [(set (pc)
1252 (if_then_else (match_operand 1 "v850_float_nz_comparison_operator" "")
1253 (label_ref (match_operand 0 "" ""))
1254 (pc)))]
1255 "TARGET_V850E2V3"
1256 {
1257 if (get_attr_length (insn) == 2)
1258 return "bnz %l0";
1259 else
1260 return "bz 1f ; jr %l0 ; 1:";
1261 }
1262 [(set (attr "length")
1263 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
1264 (const_int 256))
1265 (const_int 2)
1266 (const_int 6)))
1267 (set_attr "cc" "none")])
1268
1269 (define_insn "*branch_nz_invert"
1270 [(set (pc)
1271 (if_then_else (match_operand 1 "v850_float_nz_comparison_operator" "")
1272 (pc)
1273 (label_ref (match_operand 0 "" ""))))]
1274 "TARGET_V850E2V3"
1275 {
1276 if (get_attr_length (insn) == 2)
1277 return "bz %l0";
1278 else
1279 return "bnz 1f ; jr %l0 ; 1:";
1280 }
1281 [(set (attr "length")
1282 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
1283 (const_int 256))
1284 (const_int 2)
1285 (const_int 6)))
1286 (set_attr "cc" "none")])
1287
1288 ;; Unconditional and other jump instructions.
1289
1290 (define_insn "jump"
1291 [(set (pc)
1292 (label_ref (match_operand 0 "" "")))]
1293 ""
1294 {
1295 if (get_attr_length (insn) == 2)
1296 return "br %0";
1297 else
1298 return "jr %0";
1299 }
1300 [(set (attr "length")
1301 (if_then_else (lt (abs (minus (match_dup 0) (pc)))
1302 (const_int 256))
1303 (const_int 2)
1304 (const_int 4)))
1305 (set_attr "cc" "none")])
1306
1307 (define_insn "indirect_jump"
1308 [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
1309 ""
1310 "jmp %0"
1311 [(set_attr "length" "2")
1312 (set_attr "cc" "none")])
1313
1314 (define_insn "tablejump"
1315 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1316 (use (label_ref (match_operand 1 "" "")))]
1317 ""
1318 "jmp %0"
1319 [(set_attr "length" "2")
1320 (set_attr "cc" "none")])
1321
1322 (define_insn "switch"
1323 [(set (pc)
1324 (plus:SI
1325 (sign_extend:SI
1326 (mem:HI
1327 (plus:SI (ashift:SI (match_operand:SI 0 "register_operand" "r")
1328 (const_int 1))
1329 (label_ref (match_operand 1 "" "")))))
1330 (label_ref (match_dup 1))))]
1331 "(TARGET_V850E || TARGET_V850E2_ALL)"
1332 "switch %0"
1333 [(set_attr "length" "2")
1334 (set_attr "cc" "none")])
1335
1336 (define_expand "casesi"
1337 [(match_operand:SI 0 "register_operand" "")
1338 (match_operand:SI 1 "register_operand" "")
1339 (match_operand:SI 2 "register_operand" "")
1340 (match_operand 3 "" "") (match_operand 4 "" "")]
1341 ""
1342 {
1343 rtx reg = gen_reg_rtx (SImode);
1344 rtx tableaddress = gen_reg_rtx (SImode);
1345 rtx test;
1346 rtx mem;
1347
1348 /* Subtract the lower bound from the index. */
1349 emit_insn (gen_subsi3 (reg, operands[0], operands[1]));
1350
1351 /* Compare the result against the number of table entries;
1352 branch to the default label if out of range of the table. */
1353 test = gen_rtx_fmt_ee (GTU, VOIDmode, reg, operands[2]);
1354 emit_jump_insn (gen_cbranchsi4 (test, reg, operands[2], operands[4]));
1355
1356 /* Shift index for the table array access. */
1357 emit_insn (gen_ashlsi3 (reg, reg, GEN_INT (TARGET_BIG_SWITCH ? 2 : 1)));
1358 /* Load the table address into a pseudo. */
1359 emit_insn (gen_movsi (tableaddress,
1360 gen_rtx_LABEL_REF (Pmode, operands[3])));
1361 /* Add the table address to the index. */
1362 emit_insn (gen_addsi3 (reg, reg, tableaddress));
1363 /* Load the table entry. */
1364 mem = gen_const_mem (CASE_VECTOR_MODE, reg);
1365 if (! TARGET_BIG_SWITCH)
1366 {
1367 rtx reg2 = gen_reg_rtx (HImode);
1368 emit_insn (gen_movhi (reg2, mem));
1369 emit_insn (gen_extendhisi2 (reg, reg2));
1370 }
1371 else
1372 emit_insn (gen_movsi (reg, mem));
1373 /* Add the table address. */
1374 emit_insn (gen_addsi3 (reg, reg, tableaddress));
1375 /* Branch to the switch label. */
1376 emit_jump_insn (gen_tablejump (reg, operands[3]));
1377 DONE;
1378 })
1379
1380 ;; Call subroutine with no return value.
1381
1382 (define_expand "call"
1383 [(call (match_operand:QI 0 "general_operand" "")
1384 (match_operand:SI 1 "general_operand" ""))]
1385 ""
1386 {
1387 if (! call_address_operand (XEXP (operands[0], 0), QImode)
1388 || TARGET_LONG_CALLS)
1389 XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0));
1390 if (TARGET_LONG_CALLS)
1391 emit_call_insn (gen_call_internal_long (XEXP (operands[0], 0), operands[1]));
1392 else
1393 emit_call_insn (gen_call_internal_short (XEXP (operands[0], 0), operands[1]));
1394
1395 DONE;
1396 })
1397
1398 (define_insn "call_internal_short"
1399 [(call (mem:QI (match_operand:SI 0 "call_address_operand" "S,r"))
1400 (match_operand:SI 1 "general_operand" "g,g"))
1401 (clobber (reg:SI 31))]
1402 "! TARGET_LONG_CALLS"
1403 "@
1404 jarl %0,r31
1405 jarl .+4,r31 ; add 4,r31 ; jmp %0"
1406 [(set_attr "length" "4,8")
1407 (set_attr "cc" "clobber,clobber")]
1408 )
1409
1410 (define_insn "call_internal_long"
1411 [(call (mem:QI (match_operand:SI 0 "call_address_operand" "S,r"))
1412 (match_operand:SI 1 "general_operand" "g,g"))
1413 (clobber (reg:SI 31))]
1414 "TARGET_LONG_CALLS"
1415 {
1416 if (which_alternative == 0)
1417 {
1418 if (GET_CODE (operands[0]) == REG)
1419 return "jarl %0,r31";
1420 else
1421 return "movhi hi(%0), r0, r11 ; movea lo(%0), r11, r11 ; jarl .+4,r31 ; add 4, r31 ; jmp r11";
1422 }
1423 else
1424 return "jarl .+4,r31 ; add 4,r31 ; jmp %0";
1425 }
1426 [(set_attr "length" "16,8")
1427 (set_attr "cc" "clobber,clobber")]
1428 )
1429
1430 ;; Call subroutine, returning value in operand 0
1431 ;; (which must be a hard register).
1432
1433 (define_expand "call_value"
1434 [(set (match_operand 0 "" "")
1435 (call (match_operand:QI 1 "general_operand" "")
1436 (match_operand:SI 2 "general_operand" "")))]
1437 ""
1438 {
1439 if (! call_address_operand (XEXP (operands[1], 0), QImode)
1440 || TARGET_LONG_CALLS)
1441 XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0));
1442 if (TARGET_LONG_CALLS)
1443 emit_call_insn (gen_call_value_internal_long (operands[0],
1444 XEXP (operands[1], 0),
1445 operands[2]));
1446 else
1447 emit_call_insn (gen_call_value_internal_short (operands[0],
1448 XEXP (operands[1], 0),
1449 operands[2]));
1450 DONE;
1451 })
1452
1453 (define_insn "call_value_internal_short"
1454 [(set (match_operand 0 "" "=r,r")
1455 (call (mem:QI (match_operand:SI 1 "call_address_operand" "S,r"))
1456 (match_operand:SI 2 "general_operand" "g,g")))
1457 (clobber (reg:SI 31))]
1458 "! TARGET_LONG_CALLS"
1459 "@
1460 jarl %1,r31
1461 jarl .+4,r31 ; add 4,r31 ; jmp %1"
1462 [(set_attr "length" "4,8")
1463 (set_attr "cc" "clobber,clobber")]
1464 )
1465
1466 (define_insn "call_value_internal_long"
1467 [(set (match_operand 0 "" "=r,r")
1468 (call (mem:QI (match_operand:SI 1 "call_address_operand" "S,r"))
1469 (match_operand:SI 2 "general_operand" "g,g")))
1470 (clobber (reg:SI 31))]
1471 "TARGET_LONG_CALLS"
1472 {
1473 if (which_alternative == 0)
1474 {
1475 if (GET_CODE (operands[1]) == REG)
1476 return "jarl %1, r31";
1477 else
1478 /* Reload can generate this pattern.... */
1479 return "movhi hi(%1), r0, r11 ; movea lo(%1), r11, r11 ; jarl .+4, r31 ; add 4, r31 ; jmp r11";
1480 }
1481 else
1482 return "jarl .+4, r31 ; add 4, r31 ; jmp %1";
1483 }
1484 [(set_attr "length" "16,8")
1485 (set_attr "cc" "clobber,clobber")]
1486 )
1487
1488 (define_insn "nop"
1489 [(const_int 0)]
1490 ""
1491 "nop"
1492 [(set_attr "length" "2")
1493 (set_attr "cc" "none")])
1494 \f
1495 ;; ----------------------------------------------------------------------
1496 ;; EXTEND INSTRUCTIONS
1497 ;; ----------------------------------------------------------------------
1498
1499 (define_insn "*zero_extendhisi2_v850e"
1500 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1501 (zero_extend:SI
1502 (match_operand:HI 1 "nonimmediate_operand" "0,r,T,m")))
1503 (clobber (reg:CC CC_REGNUM))]
1504 "(TARGET_V850E || TARGET_V850E2_ALL)"
1505 "@
1506 zxh %0
1507 andi 65535,%1,%0
1508 sld.hu %1,%0
1509 ld.hu %1,%0"
1510 [(set_attr "length" "2,4,2,4")
1511 (set_attr "cc" "none_0hit,set_zn,none_0hit,none_0hit")])
1512
1513 (define_insn "*zero_extendhisi2_v850"
1514 [(set (match_operand:SI 0 "register_operand" "=r")
1515 (zero_extend:SI
1516 (match_operand:HI 1 "register_operand" "r")))
1517 (clobber (reg:CC CC_REGNUM))] ;; A lie, but we have to match the expander
1518 ""
1519 "andi 65535,%1,%0"
1520 [(set_attr "length" "4")
1521 (set_attr "cc" "set_zn")])
1522
1523 (define_expand "zero_extendhisi2"
1524 [(parallel [(set (match_operand:SI 0 "register_operand")
1525 (zero_extend:SI
1526 (match_operand:HI 1 "nonimmediate_operand")))
1527 (clobber (reg:CC CC_REGNUM))])]
1528 ""
1529 {
1530 if (! (TARGET_V850E || TARGET_V850E2_ALL))
1531 operands[1] = force_reg (HImode, operands[1]);
1532 })
1533
1534 (define_insn "*zero_extendqisi2_v850e"
1535 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1536 (zero_extend:SI
1537 (match_operand:QI 1 "nonimmediate_operand" "0,r,T,m")))
1538 (clobber (reg:CC CC_REGNUM))]
1539 "(TARGET_V850E || TARGET_V850E2_ALL)"
1540 "@
1541 zxb %0
1542 andi 255,%1,%0
1543 sld.bu %1,%0
1544 ld.bu %1,%0"
1545 [(set_attr "length" "2,4,2,4")
1546 (set_attr "cc" "none_0hit,set_zn,none_0hit,none_0hit")])
1547
1548 (define_insn "*zero_extendqisi2_v850"
1549 [(set (match_operand:SI 0 "register_operand" "=r")
1550 (zero_extend:SI
1551 (match_operand:QI 1 "register_operand" "r")))
1552 (clobber (reg:CC CC_REGNUM))] ;; A lie, but we have to match the expander
1553 ""
1554 "andi 255,%1,%0"
1555 [(set_attr "length" "4")
1556 (set_attr "cc" "set_zn")])
1557
1558 (define_expand "zero_extendqisi2"
1559 [(parallel [(set (match_operand:SI 0 "register_operand")
1560 (zero_extend:SI
1561 (match_operand:QI 1 "nonimmediate_operand")))
1562 (clobber (reg:CC CC_REGNUM))])]
1563 ""
1564 {
1565 if (! (TARGET_V850E || TARGET_V850E2_ALL))
1566 operands[1] = force_reg (QImode, operands[1]);
1567 })
1568
1569 ;;- sign extension instructions
1570
1571 ;; ??? The extendhisi2 pattern should not emit shifts for v850e?
1572
1573 (define_insn "*extendhisi_insn"
1574 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1575 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,Q,m")))
1576 (clobber (reg:CC CC_REGNUM))]
1577 "(TARGET_V850E || TARGET_V850E2_ALL)"
1578 "@
1579 sxh %0
1580 sld.h %1,%0
1581 ld.h %1,%0"
1582 [(set_attr "length" "2,2,4")
1583 (set_attr "cc" "none_0hit,none_0hit,none_0hit")])
1584
1585 ;; ??? This is missing a sign extend from memory pattern to match the ld.h
1586 ;; instruction.
1587
1588 (define_expand "extendhisi2"
1589 [(parallel [(set (match_dup 2)
1590 (ashift:SI (match_operand:HI 1 "register_operand" "")
1591 (const_int 16)))
1592 (clobber (reg:CC CC_REGNUM))])
1593 (parallel [(set (match_operand:SI 0 "register_operand" "")
1594 (ashiftrt:SI (match_dup 2)
1595 (const_int 16)))
1596 (clobber (reg:CC CC_REGNUM))])]
1597 ""
1598 {
1599 operands[1] = gen_lowpart (SImode, operands[1]);
1600 operands[2] = gen_reg_rtx (SImode);
1601 })
1602
1603 ;; ??? The extendqisi2 pattern should not emit shifts for v850e?
1604
1605 (define_insn "*extendqisi_insn"
1606 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1607 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,Q,m")))
1608 (clobber (reg:CC CC_REGNUM))]
1609 "(TARGET_V850E || TARGET_V850E2_ALL)"
1610 "@
1611 sxb %0
1612 sld.b %1,%0
1613 ld.b %1,%0"
1614 [(set_attr "length" "2,2,4")
1615 (set_attr "cc" "none_0hit,none_0hit,none_0hit")])
1616
1617 ;; ??? This is missing a sign extend from memory pattern to match the ld.b
1618 ;; instruction.
1619
1620 (define_expand "extendqisi2"
1621 [(parallel [(set (match_dup 2)
1622 (ashift:SI (match_operand:QI 1 "register_operand" "")
1623 (const_int 24)))
1624 (clobber (reg:CC CC_REGNUM))])
1625 (parallel [(set (match_operand:SI 0 "register_operand" "")
1626 (ashiftrt:SI (match_dup 2)
1627 (const_int 24)))
1628 (clobber (reg:CC CC_REGNUM))])]
1629 ""
1630 {
1631 operands[1] = gen_lowpart (SImode, operands[1]);
1632 operands[2] = gen_reg_rtx (SImode);
1633 })
1634 \f
1635 ;; ----------------------------------------------------------------------
1636 ;; SHIFTS
1637 ;; ----------------------------------------------------------------------
1638
1639 (define_insn "ashlsi3"
1640 [(set (match_operand:SI 0 "register_operand" "=r,r")
1641 (ashift:SI
1642 (match_operand:SI 1 "register_operand" "0,0")
1643 (match_operand:SI 2 "nonmemory_operand" "r,N")))
1644 (clobber (reg:CC CC_REGNUM))]
1645 ""
1646 "@
1647 shl %2,%0
1648 shl %2,%0"
1649 [(set_attr "length" "4,2")
1650 (set_attr "cc" "set_zn")])
1651
1652 (define_insn "ashlsi3_v850e2"
1653 [(set (match_operand:SI 0 "register_operand" "=r")
1654 (ashift:SI
1655 (match_operand:SI 1 "register_operand" "r")
1656 (match_operand:SI 2 "nonmemory_operand" "r")))
1657 (clobber (reg:CC CC_REGNUM))]
1658 "TARGET_V850E2_ALL"
1659 "shl %2,%1,%0"
1660 [(set_attr "length" "4")
1661 (set_attr "cc" "set_znv")])
1662
1663 (define_insn "lshrsi3"
1664 [(set (match_operand:SI 0 "register_operand" "=r,r")
1665 (lshiftrt:SI
1666 (match_operand:SI 1 "register_operand" "0,0")
1667 (match_operand:SI 2 "nonmemory_operand" "r,N")))
1668 (clobber (reg:CC CC_REGNUM))]
1669 ""
1670 "@
1671 shr %2,%0
1672 shr %2,%0"
1673 [(set_attr "length" "4,2")
1674 (set_attr "cc" "set_zn")])
1675
1676 (define_insn "lshrsi3_v850e2"
1677 [(set (match_operand:SI 0 "register_operand" "=r")
1678 (lshiftrt:SI
1679 (match_operand:SI 1 "register_operand" "r")
1680 (match_operand:SI 2 "nonmemory_operand" "r")))
1681 (clobber (reg:CC CC_REGNUM))]
1682 "TARGET_V850E2_ALL"
1683 "shr %2,%1,%0"
1684 [(set_attr "length" "4")
1685 (set_attr "cc" "set_zn")])
1686
1687 (define_insn "ashrsi3"
1688 [(set (match_operand:SI 0 "register_operand" "=r,r")
1689 (ashiftrt:SI
1690 (match_operand:SI 1 "register_operand" "0,0")
1691 (match_operand:SI 2 "nonmemory_operand" "r,N")))
1692 (clobber (reg:CC CC_REGNUM))]
1693 ""
1694 "@
1695 sar %2,%0
1696 sar %2,%0"
1697 [(set_attr "length" "4,2")
1698 (set_attr "cc" "set_zn, set_zn")])
1699
1700 (define_insn "ashrsi3_v850e2"
1701 [(set (match_operand:SI 0 "register_operand" "=r")
1702 (ashiftrt:SI
1703 (match_operand:SI 1 "register_operand" "r")
1704 (match_operand:SI 2 "nonmemory_operand" "r")))
1705 (clobber (reg:CC CC_REGNUM))]
1706 "TARGET_V850E2_ALL"
1707 "sar %2,%1,%0"
1708 [(set_attr "length" "4")
1709 (set_attr "cc" "set_zn")])
1710
1711 ;; ----------------------------------------------------------------------
1712 ;; FIND FIRST BIT INSTRUCTION
1713 ;; ----------------------------------------------------------------------
1714
1715 (define_insn "ffssi2"
1716 [(set (match_operand:SI 0 "register_operand" "=r")
1717 (ffs:SI (match_operand:SI 1 "register_operand" "r")))
1718 (clobber (reg:CC CC_REGNUM))]
1719 "TARGET_V850E2_ALL"
1720 "sch1r %1,%0"
1721 [(set_attr "length" "4")
1722 (set_attr "cc" "clobber")])
1723
1724 ;; ----------------------------------------------------------------------
1725 ;; PROLOGUE/EPILOGUE
1726 ;; ----------------------------------------------------------------------
1727 (define_expand "prologue"
1728 [(const_int 0)]
1729 ""
1730 {
1731 expand_prologue ();
1732 DONE;
1733 })
1734
1735 (define_expand "epilogue"
1736 [(return)]
1737 ""
1738 {
1739 expand_epilogue ();
1740 DONE;
1741 })
1742
1743 (define_insn "return_simple"
1744 [(return)]
1745 "reload_completed"
1746 "jmp [r31]"
1747 [(set_attr "length" "2")
1748 (set_attr "cc" "none")])
1749
1750 (define_insn "return_internal"
1751 [(return)
1752 (use (reg:SI 31))]
1753 ""
1754 "jmp [r31]"
1755 [(set_attr "length" "2")
1756 (set_attr "cc" "none")])
1757
1758 ;; ----------------------------------------------------------------------
1759 ;; v850e2V3 floating-point hardware support
1760 ;; ----------------------------------------------------------------------
1761
1762
1763 (define_insn "addsf3"
1764 [(set (match_operand:SF 0 "register_operand" "=r")
1765 (plus:SF (match_operand:SF 1 "register_operand" "r")
1766 (match_operand:SF 2 "register_operand" "r")))]
1767 "TARGET_USE_FPU"
1768 "addf.s %1,%2,%0"
1769 [(set_attr "length" "4")
1770 (set_attr "cc" "none_0hit")
1771 (set_attr "type" "fpu")])
1772
1773 (define_insn "adddf3"
1774 [(set (match_operand:DF 0 "even_reg_operand" "=r")
1775 (plus:DF (match_operand:DF 1 "even_reg_operand" "r")
1776 (match_operand:DF 2 "even_reg_operand" "r")))]
1777 "TARGET_USE_FPU"
1778 "addf.d %1,%2,%0"
1779 [(set_attr "length" "4")
1780 (set_attr "cc" "none_0hit")
1781 (set_attr "type" "fpu")])
1782
1783 (define_insn "subsf3"
1784 [(set (match_operand:SF 0 "register_operand" "=r")
1785 (minus:SF (match_operand:SF 1 "register_operand" "r")
1786 (match_operand:SF 2 "register_operand" "r")))]
1787 "TARGET_USE_FPU"
1788 "subf.s %2,%1,%0"
1789 [(set_attr "length" "4")
1790 (set_attr "cc" "none_0hit")
1791 (set_attr "type" "fpu")])
1792
1793 (define_insn "subdf3"
1794 [(set (match_operand:DF 0 "even_reg_operand" "=r")
1795 (minus:DF (match_operand:DF 1 "even_reg_operand" "r")
1796 (match_operand:DF 2 "even_reg_operand" "r")))]
1797 "TARGET_USE_FPU"
1798 "subf.d %2,%1,%0"
1799 [(set_attr "length" "4")
1800 (set_attr "cc" "none_0hit")
1801 (set_attr "type" "fpu")])
1802
1803 (define_insn "mulsf3"
1804 [(set (match_operand:SF 0 "register_operand" "=r")
1805 (mult:SF (match_operand:SF 1 "register_operand" "r")
1806 (match_operand:SF 2 "register_operand" "r")))]
1807 "TARGET_USE_FPU"
1808 "mulf.s %1,%2,%0"
1809 [(set_attr "length" "4")
1810 (set_attr "cc" "none_0hit")
1811 (set_attr "type" "fpu")])
1812
1813 (define_insn "muldf3"
1814 [(set (match_operand:DF 0 "even_reg_operand" "=r")
1815 (mult:DF (match_operand:DF 1 "even_reg_operand" "r")
1816 (match_operand:DF 2 "even_reg_operand" "r")))]
1817 "TARGET_USE_FPU"
1818 "mulf.d %1,%2,%0"
1819 [(set_attr "length" "4")
1820 (set_attr "cc" "none_0hit")
1821 (set_attr "type" "fpu")])
1822
1823 (define_insn "divsf3"
1824 [(set (match_operand:SF 0 "register_operand" "=r")
1825 (div:SF (match_operand:SF 1 "register_operand" "r")
1826 (match_operand:SF 2 "register_operand" "r")))]
1827 "TARGET_USE_FPU"
1828 "divf.s %2,%1,%0"
1829 [(set_attr "length" "4")
1830 (set_attr "cc" "none_0hit")
1831 (set_attr "type" "fpu")])
1832
1833 (define_insn "divdf3"
1834 [(set (match_operand:DF 0 "register_operand" "=r")
1835 (div:DF (match_operand:DF 1 "even_reg_operand" "r")
1836 (match_operand:DF 2 "even_reg_operand" "r")))]
1837 "TARGET_USE_FPU"
1838 "divf.d %2,%1,%0"
1839 [(set_attr "length" "4")
1840 (set_attr "cc" "none_0hit")
1841 (set_attr "type" "fpu")])
1842
1843 (define_insn "minsf3"
1844 [(set (match_operand:SF 0 "register_operand" "=r")
1845 (smin:SF (match_operand:SF 1 "reg_or_0_operand" "r")
1846 (match_operand:SF 2 "reg_or_0_operand" "r")))]
1847 "TARGET_USE_FPU"
1848 "minf.s %z1,%z2,%0"
1849 [(set_attr "length" "4")
1850 (set_attr "cc" "none_0hit")
1851 (set_attr "type" "fpu")])
1852
1853 (define_insn "mindf3"
1854 [(set (match_operand:DF 0 "even_reg_operand" "=r")
1855 (smin:DF (match_operand:DF 1 "even_reg_operand" "r")
1856 (match_operand:DF 2 "even_reg_operand" "r")))]
1857 "TARGET_USE_FPU"
1858 "minf.d %1,%2,%0"
1859 [(set_attr "length" "4")
1860 (set_attr "cc" "none_0hit")
1861 (set_attr "type" "fpu")])
1862
1863 (define_insn "maxsf3"
1864 [(set (match_operand:SF 0 "register_operand" "=r")
1865 (smax:SF (match_operand:SF 1 "reg_or_0_operand" "r")
1866 (match_operand:SF 2 "reg_or_0_operand" "r")))]
1867 "TARGET_USE_FPU"
1868 "maxf.s %z1,%z2,%0"
1869 [(set_attr "length" "4")
1870 (set_attr "cc" "none_0hit")
1871 (set_attr "type" "fpu")])
1872
1873 (define_insn "maxdf3"
1874 [(set (match_operand:DF 0 "even_reg_operand" "=r")
1875 (smax:DF (match_operand:DF 1 "even_reg_operand" "r")
1876 (match_operand:DF 2 "even_reg_operand" "r")))]
1877 "TARGET_USE_FPU"
1878 "maxf.d %1,%2,%0"
1879 [(set_attr "length" "4")
1880 (set_attr "cc" "none_0hit")
1881 (set_attr "type" "fpu")])
1882
1883 (define_insn "abssf2"
1884 [(set (match_operand:SF 0 "register_operand" "=r")
1885 (abs:SF (match_operand:SF 1 "register_operand" "r")))]
1886 "TARGET_USE_FPU"
1887 "absf.s %1,%0"
1888 [(set_attr "length" "4")
1889 (set_attr "cc" "none_0hit")
1890 (set_attr "type" "fpu")])
1891
1892 (define_insn "absdf2"
1893 [(set (match_operand:DF 0 "even_reg_operand" "=r")
1894 (abs:DF (match_operand:DF 1 "even_reg_operand" "r")))]
1895 "TARGET_USE_FPU"
1896 "absf.d %1,%0"
1897 [(set_attr "length" "4")
1898 (set_attr "cc" "none_0hit")
1899 (set_attr "type" "fpu")])
1900
1901 (define_insn "negsf2"
1902 [(set (match_operand:SF 0 "register_operand" "=r")
1903 (neg:SF (match_operand:SF 1 "register_operand" "r")))]
1904 "TARGET_USE_FPU"
1905 "negf.s %1,%0"
1906 [(set_attr "length" "4")
1907 (set_attr "cc" "none_0hit")
1908 (set_attr "type" "fpu")])
1909
1910 (define_insn "negdf2"
1911 [(set (match_operand:DF 0 "even_reg_operand" "=r")
1912 (neg:DF (match_operand:DF 1 "even_reg_operand" "r")))]
1913 "TARGET_USE_FPU"
1914 "negf.d %1,%0"
1915 [(set_attr "length" "4")
1916 (set_attr "cc" "none_0hit")
1917 (set_attr "type" "fpu")])
1918
1919 ;; square-root
1920 (define_insn "sqrtsf2"
1921 [(set (match_operand:SF 0 "register_operand" "=r")
1922 (sqrt:SF (match_operand:SF 1 "register_operand" "r")))]
1923 "TARGET_USE_FPU"
1924 "sqrtf.s %1,%0"
1925 [(set_attr "length" "4")
1926 (set_attr "cc" "none_0hit")
1927 (set_attr "type" "fpu")])
1928
1929 (define_insn "sqrtdf2"
1930 [(set (match_operand:DF 0 "even_reg_operand" "=r")
1931 (sqrt:DF (match_operand:DF 1 "even_reg_operand" "r")))]
1932 "TARGET_USE_FPU"
1933 "sqrtf.d %1,%0"
1934 [(set_attr "length" "4")
1935 (set_attr "cc" "none_0hit")
1936 (set_attr "type" "fpu")])
1937
1938 ;; float -> int
1939 (define_insn "fix_truncsfsi2"
1940 [(set (match_operand:SI 0 "register_operand" "=r")
1941 (fix:SI (match_operand:SF 1 "register_operand" "r")))]
1942 "TARGET_USE_FPU"
1943 "trncf.sw %1,%0"
1944 [(set_attr "length" "4")
1945 (set_attr "cc" "none_0hit")
1946 (set_attr "type" "fpu")])
1947
1948 (define_insn "fixuns_truncsfsi2"
1949 [(set (match_operand:SI 0 "register_operand" "=r")
1950 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "r")))]
1951 "TARGET_USE_FPU"
1952 "trncf.suw %1, %0"
1953 [(set_attr "length" "4")
1954 (set_attr "cc" "none_0hit")
1955 (set_attr "type" "fpu")]
1956 )
1957
1958 (define_insn "fix_truncdfsi2"
1959 [(set (match_operand:SI 0 "register_operand" "=r")
1960 (fix:SI (match_operand:DF 1 "even_reg_operand" "r")))]
1961 "TARGET_USE_FPU"
1962 "trncf.dw %1,%0"
1963 [(set_attr "length" "4")
1964 (set_attr "cc" "none_0hit")
1965 (set_attr "type" "fpu")])
1966
1967 (define_insn "fixuns_truncdfsi2"
1968 [(set (match_operand:SI 0 "register_operand" "=r")
1969 (unsigned_fix:SI (match_operand:DF 1 "even_reg_operand" "r")))]
1970 "TARGET_USE_FPU"
1971 "trncf.duw %1, %0"
1972 [(set_attr "length" "4")
1973 (set_attr "cc" "none_0hit")
1974 (set_attr "type" "fpu")]
1975 )
1976
1977 (define_insn "fix_truncsfdi2"
1978 [(set (match_operand:DI 0 "register_operand" "=r")
1979 (fix:DI (match_operand:SF 1 "register_operand" "r")))]
1980 "TARGET_USE_FPU"
1981 "trncf.sl %1, %0"
1982 [(set_attr "length" "4")
1983 (set_attr "cc" "none_0hit")
1984 (set_attr "type" "fpu")])
1985
1986 (define_insn "fixuns_truncsfdi2"
1987 [(set (match_operand:DI 0 "register_operand" "=r")
1988 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "r")))]
1989 "TARGET_USE_FPU"
1990 "trncf.sul %1, %0"
1991 [(set_attr "length" "4")
1992 (set_attr "cc" "none_0hit")
1993 (set_attr "type" "fpu")]
1994 )
1995
1996 (define_insn "fix_truncdfdi2"
1997 [(set (match_operand:DI 0 "register_operand" "=r")
1998 (fix:DI (match_operand:DF 1 "even_reg_operand" "r")))]
1999 "TARGET_USE_FPU"
2000 "trncf.dl %1, %0"
2001 [(set_attr "length" "4")
2002 (set_attr "cc" "none_0hit")
2003 (set_attr "type" "fpu")])
2004
2005 (define_insn "fixuns_truncdfdi2"
2006 [(set (match_operand:DI 0 "register_operand" "=r")
2007 (unsigned_fix:DI (match_operand:DF 1 "even_reg_operand" "r")))]
2008 "TARGET_USE_FPU"
2009 "trncf.dul %1, %0"
2010 [(set_attr "length" "4")
2011 (set_attr "cc" "none_0hit")
2012 (set_attr "type" "fpu")]
2013 )
2014
2015 ;; int -> float
2016 (define_insn "floatsisf2"
2017 [(set (match_operand:SF 0 "register_operand" "=r")
2018 (float:SF (match_operand:SI 1 "reg_or_0_operand" "rI")))]
2019 "TARGET_USE_FPU"
2020 "cvtf.ws %z1, %0"
2021 [(set_attr "length" "4")
2022 (set_attr "cc" "none_0hit")
2023 (set_attr "type" "fpu")])
2024
2025 (define_insn "unsfloatsisf2"
2026 [(set (match_operand:SF 0 "register_operand" "=r")
2027 (unsigned_float:SF (match_operand:SI 1 "reg_or_0_operand" "rI")))]
2028 "TARGET_USE_FPU"
2029 "cvtf.uws %z1, %0"
2030 [(set_attr "length" "4")
2031 (set_attr "cc" "none_0hit")
2032 (set_attr "type" "fpu")])
2033
2034 (define_insn "floatsidf2"
2035 [(set (match_operand:DF 0 "even_reg_operand" "=r")
2036 (float:DF (match_operand:SI 1 "reg_or_0_operand" "rI")))]
2037 "TARGET_USE_FPU"
2038 "cvtf.wd %z1,%0"
2039 [(set_attr "length" "4")
2040 (set_attr "cc" "none_0hit")
2041 (set_attr "type" "fpu")])
2042
2043 (define_insn "unsfloatsidf2"
2044 [(set (match_operand:DF 0 "even_reg_operand" "=r")
2045 (unsigned_float:DF (match_operand:SI 1 "reg_or_0_operand" "rI")))]
2046 "TARGET_USE_FPU"
2047 "cvtf.uwd %z1, %0"
2048 [(set_attr "length" "4")
2049 (set_attr "cc" "none_0hit")
2050 (set_attr "type" "fpu")])
2051
2052 (define_insn "floatdisf2"
2053 [(set (match_operand:SF 0 "even_reg_operand" "=r")
2054 (float:SF (match_operand:DI 1 "reg_or_0_operand" "rI")))]
2055 "TARGET_USE_FPU"
2056 "cvtf.ls %z1, %0"
2057 [(set_attr "length" "4")
2058 (set_attr "cc" "none_0hit")
2059 (set_attr "type" "fpu")])
2060
2061 (define_insn "unsfloatdisf2"
2062 [(set (match_operand:SF 0 "even_reg_operand" "=r")
2063 (unsigned_float:SF (match_operand:DI 1 "reg_or_0_operand" "rI")))]
2064 "TARGET_USE_FPU"
2065 "cvtf.uls %z1, %0"
2066 [(set_attr "length" "4")
2067 (set_attr "cc" "none_0hit")
2068 (set_attr "type" "fpu")])
2069
2070 (define_insn "floatdidf2"
2071 [(set (match_operand:DF 0 "even_reg_operand" "=r")
2072 (float:DF (match_operand:DI 1 "reg_or_0_operand" "rI")))]
2073 "TARGET_USE_FPU"
2074 "cvtf.ld %z1, %0"
2075 [(set_attr "length" "4")
2076 (set_attr "cc" "none_0hit")
2077 (set_attr "type" "fpu")])
2078
2079 (define_insn "unsfloatdidf2"
2080 [(set (match_operand:DF 0 "even_reg_operand" "=r")
2081 (unsigned_float:DF (match_operand:DI 1 "reg_or_0_operand" "rI")))]
2082 "TARGET_USE_FPU"
2083 "cvtf.uld %z1, %0"
2084 [(set_attr "length" "4")
2085 (set_attr "cc" "none_0hit")
2086 (set_attr "type" "fpu")])
2087
2088 ;; single-float -> double-float
2089 (define_insn "extendsfdf2"
2090 [(set (match_operand:DF 0 "even_reg_operand" "=r")
2091 (float_extend:DF
2092 (match_operand:SF 1 "reg_or_0_operand" "rI")))]
2093 "TARGET_USE_FPU"
2094 "cvtf.sd %z1,%0"
2095 [(set_attr "length" "4")
2096 (set_attr "cc" "none_0hit")
2097 (set_attr "type" "fpu")])
2098
2099 ;; double-float -> single-float
2100 (define_insn "truncdfsf2"
2101 [(set (match_operand:SF 0 "register_operand" "=r")
2102 (float_truncate:SF
2103 (match_operand:DF 1 "even_reg_operand" "r")))]
2104 "TARGET_USE_FPU"
2105 "cvtf.ds %1,%0"
2106 [(set_attr "length" "4")
2107 (set_attr "cc" "none_0hit")
2108 (set_attr "type" "fpu")])
2109
2110 ;;
2111 ;; ---------------- special insns
2112 ;;
2113
2114 ;;; reciprocal
2115 (define_insn "recipsf2"
2116 [(set (match_operand:SF 0 "register_operand" "=r")
2117 (div:SF (match_operand:SF 1 "const_float_1_operand" "")
2118 (match_operand:SF 2 "register_operand" "r")))]
2119 "TARGET_USE_FPU"
2120 "recipf.s %2,%0"
2121 [(set_attr "length" "4")
2122 (set_attr "cc" "none_0hit")
2123 (set_attr "type" "fpu")])
2124
2125 (define_insn "recipdf2"
2126 [(set (match_operand:DF 0 "even_reg_operand" "=r")
2127 (div:DF (match_operand:DF 1 "const_float_1_operand" "")
2128 (match_operand:DF 2 "even_reg_operand" "r")))]
2129 "TARGET_USE_FPU"
2130 "recipf.d %2,%0"
2131 [(set_attr "length" "4")
2132 (set_attr "cc" "none_0hit")
2133 (set_attr "type" "fpu")])
2134
2135 ;;; reciprocal of square-root
2136 (define_insn "rsqrtsf2"
2137 [(set (match_operand:SF 0 "register_operand" "=r")
2138 (div:SF (match_operand:SF 1 "const_float_1_operand" "")
2139 (sqrt:SF (match_operand:SF 2 "register_operand" "r"))))]
2140 "TARGET_USE_FPU"
2141 "rsqrtf.s %2,%0"
2142 [(set_attr "length" "4")
2143 (set_attr "cc" "none_0hit")
2144 (set_attr "type" "fpu")])
2145
2146 (define_insn "rsqrtdf2"
2147 [(set (match_operand:DF 0 "even_reg_operand" "=r")
2148 (div:DF (match_operand:DF 1 "const_float_1_operand" "")
2149 (sqrt:DF (match_operand:DF 2 "even_reg_operand" "r"))))]
2150 "TARGET_USE_FPU"
2151 "rsqrtf.d %2,%0"
2152 [(set_attr "length" "4")
2153 (set_attr "cc" "none_0hit")
2154 (set_attr "type" "fpu")])
2155
2156 ;;; multiply-add
2157 (define_insn "fmasf4"
2158 [(set (match_operand:SF 0 "register_operand" "=r")
2159 (fma:SF (match_operand:SF 1 "register_operand" "r")
2160 (match_operand:SF 2 "register_operand" "r")
2161 (match_operand:SF 3 "register_operand" "r")))]
2162 "TARGET_USE_FPU"
2163 "maddf.s %2,%1,%3,%0"
2164 [(set_attr "length" "4")
2165 (set_attr "cc" "none_0hit")
2166 (set_attr "type" "fpu")])
2167
2168 ;;; multiply-subtract
2169 (define_insn "fmssf4"
2170 [(set (match_operand:SF 0 "register_operand" "=r")
2171 (fma:SF (match_operand:SF 1 "register_operand" "r")
2172 (match_operand:SF 2 "register_operand" "r")
2173 (neg:SF (match_operand:SF 3 "register_operand" "r"))))]
2174 "TARGET_USE_FPU"
2175 "msubf.s %2,%1,%3,%0"
2176 [(set_attr "length" "4")
2177 (set_attr "cc" "none_0hit")
2178 (set_attr "type" "fpu")])
2179
2180 ;;; negative-multiply-add
2181 (define_insn "fnmasf4"
2182 [(set (match_operand:SF 0 "register_operand" "=r")
2183 (neg:SF (fma:SF (match_operand:SF 1 "register_operand" "r")
2184 (match_operand:SF 2 "register_operand" "r")
2185 (match_operand:SF 3 "register_operand" "r"))))]
2186 "TARGET_USE_FPU"
2187 "nmaddf.s %2,%1,%3,%0"
2188 [(set_attr "length" "4")
2189 (set_attr "cc" "none_0hit")
2190 (set_attr "type" "fpu")])
2191
2192 ;; negative-multiply-subtract
2193 (define_insn "fnmssf4"
2194 [(set (match_operand:SF 0 "register_operand" "=r")
2195 (neg:SF (fma:SF (match_operand:SF 1 "register_operand" "r")
2196 (match_operand:SF 2 "register_operand" "r")
2197 (neg:SF (match_operand:SF 3 "register_operand" "r")))))]
2198 "TARGET_USE_FPU"
2199 "nmsubf.s %2,%1,%3,%0"
2200 [(set_attr "length" "4")
2201 (set_attr "cc" "none_0hit")
2202 (set_attr "type" "fpu")])
2203 ;
2204 ; ---------------- comparison/conditionals
2205 ;
2206 ; SF
2207
2208 (define_insn "cmpsf_le_insn"
2209 [(set (reg:CC_FPU_LE FCC_REGNUM)
2210 (compare:CC_FPU_LE (match_operand:SF 0 "register_operand" "r")
2211 (match_operand:SF 1 "register_operand" "r")))]
2212 "TARGET_USE_FPU"
2213 "cmpf.s le,%z1,%z0"
2214 [(set_attr "length" "4")
2215 (set_attr "cc" "none_0hit")
2216 (set_attr "type" "fpu")])
2217
2218 (define_insn "cmpsf_lt_insn"
2219 [(set (reg:CC_FPU_LT FCC_REGNUM)
2220 (compare:CC_FPU_LT (match_operand:SF 0 "register_operand" "r")
2221 (match_operand:SF 1 "register_operand" "r")))]
2222 "TARGET_USE_FPU"
2223 "cmpf.s lt,%z1,%z0"
2224 [(set_attr "length" "4")
2225 (set_attr "cc" "none_0hit")
2226 (set_attr "type" "fpu")])
2227
2228 (define_insn "cmpsf_ge_insn"
2229 [(set (reg:CC_FPU_GE FCC_REGNUM)
2230 (compare:CC_FPU_GE (match_operand:SF 0 "register_operand" "r")
2231 (match_operand:SF 1 "register_operand" "r")))]
2232 "TARGET_USE_FPU"
2233 "cmpf.s ge,%z1,%z0"
2234 [(set_attr "length" "4")
2235 (set_attr "cc" "none_0hit")
2236 (set_attr "type" "fpu")])
2237
2238 (define_insn "cmpsf_gt_insn"
2239 [(set (reg:CC_FPU_GT FCC_REGNUM)
2240 (compare:CC_FPU_GT (match_operand:SF 0 "register_operand" "r")
2241 (match_operand:SF 1 "register_operand" "r")))]
2242 "TARGET_USE_FPU"
2243 "cmpf.s gt,%z1,%z0"
2244 [(set_attr "length" "4")
2245 (set_attr "cc" "none_0hit")
2246 (set_attr "type" "fpu")])
2247
2248 (define_insn "cmpsf_eq_insn"
2249 [(set (reg:CC_FPU_EQ FCC_REGNUM)
2250 (compare:CC_FPU_EQ (match_operand:SF 0 "register_operand" "r")
2251 (match_operand:SF 1 "register_operand" "r")))]
2252 "TARGET_USE_FPU"
2253 "cmpf.s eq,%z1,%z0"
2254 [(set_attr "length" "4")
2255 (set_attr "cc" "none_0hit")
2256 (set_attr "type" "fpu")])
2257
2258 (define_insn "cmpsf_ne_insn"
2259 [(set (reg:CC_FPU_NE FCC_REGNUM)
2260 (compare:CC_FPU_NE (match_operand:SF 0 "register_operand" "r")
2261 (match_operand:SF 1 "register_operand" "r")))]
2262 "TARGET_USE_FPU"
2263 "cmpf.s neq,%z1,%z0"
2264 [(set_attr "length" "4")
2265 (set_attr "cc" "none_0hit")
2266 (set_attr "type" "fpu")])
2267
2268 ; DF
2269
2270 (define_insn "cmpdf_le_insn"
2271 [(set (reg:CC_FPU_LE FCC_REGNUM)
2272 (compare:CC_FPU_LE (match_operand:DF 0 "even_reg_operand" "r")
2273 (match_operand:DF 1 "even_reg_operand" "r")))]
2274 "TARGET_USE_FPU"
2275 "cmpf.d le,%z1,%z0"
2276 [(set_attr "length" "4")
2277 (set_attr "cc" "none_0hit")
2278 (set_attr "type" "fpu")])
2279
2280 (define_insn "cmpdf_lt_insn"
2281 [(set (reg:CC_FPU_LT FCC_REGNUM)
2282 (compare:CC_FPU_LT (match_operand:DF 0 "even_reg_operand" "r")
2283 (match_operand:DF 1 "even_reg_operand" "r")))]
2284 "TARGET_USE_FPU"
2285 "cmpf.d lt,%z1,%z0"
2286 [(set_attr "length" "4")
2287 (set_attr "cc" "none_0hit")
2288 (set_attr "type" "fpu")])
2289
2290 (define_insn "cmpdf_ge_insn"
2291 [(set (reg:CC_FPU_GE FCC_REGNUM)
2292 (compare:CC_FPU_GE (match_operand:DF 0 "even_reg_operand" "r")
2293 (match_operand:DF 1 "even_reg_operand" "r")))]
2294 "TARGET_USE_FPU"
2295 "cmpf.d ge,%z1,%z0"
2296 [(set_attr "length" "4")
2297 (set_attr "cc" "none_0hit")
2298 (set_attr "type" "fpu")])
2299
2300 (define_insn "cmpdf_gt_insn"
2301 [(set (reg:CC_FPU_GT FCC_REGNUM)
2302 (compare:CC_FPU_GT (match_operand:DF 0 "even_reg_operand" "r")
2303 (match_operand:DF 1 "even_reg_operand" "r")))]
2304 "TARGET_USE_FPU"
2305 "cmpf.d gt,%z1,%z0"
2306 [(set_attr "length" "4")
2307 (set_attr "cc" "none_0hit")
2308 (set_attr "type" "fpu")])
2309
2310 (define_insn "cmpdf_eq_insn"
2311 [(set (reg:CC_FPU_EQ FCC_REGNUM)
2312 (compare:CC_FPU_EQ (match_operand:DF 0 "even_reg_operand" "r")
2313 (match_operand:DF 1 "even_reg_operand" "r")))]
2314 "TARGET_USE_FPU"
2315 "cmpf.d eq,%z1,%z0"
2316 [(set_attr "length" "4")
2317 (set_attr "cc" "none_0hit")
2318 (set_attr "type" "fpu")])
2319
2320 (define_insn "cmpdf_ne_insn"
2321 [(set (reg:CC_FPU_NE FCC_REGNUM)
2322 (compare:CC_FPU_NE (match_operand:DF 0 "even_reg_operand" "r")
2323 (match_operand:DF 1 "even_reg_operand" "r")))]
2324 "TARGET_USE_FPU"
2325 "cmpf.d neq,%z1,%z0"
2326 [(set_attr "length" "4")
2327 (set_attr "cc" "none_0hit")
2328 (set_attr "type" "fpu")])
2329
2330
2331 ;;
2332 ;; Transfer a v850e2v3 fcc to the Z bit of CC0 (this is necessary to do a
2333 ;; conditional branch based on a floating-point compare)
2334 ;;
2335
2336 (define_insn "trfsr"
2337 [(set (match_operand 0 "" "") (match_operand 1 "" ""))]
2338 "TARGET_USE_FPU
2339 && GET_MODE(operands[0]) == GET_MODE(operands[1])
2340 && GET_CODE(operands[0]) == REG && REGNO (operands[0]) == CC_REGNUM
2341 && GET_CODE(operands[1]) == REG && REGNO (operands[1]) == FCC_REGNUM
2342 && (GET_MODE(operands[0]) == CC_FPU_LEmode
2343 || GET_MODE(operands[0]) == CC_FPU_GEmode
2344 || GET_MODE(operands[0]) == CC_FPU_LTmode
2345 || GET_MODE(operands[0]) == CC_FPU_GTmode
2346 || GET_MODE(operands[0]) == CC_FPU_EQmode
2347 || GET_MODE(operands[0]) == CC_FPU_NEmode)"
2348 "trfsr"
2349 [(set_attr "length" "4")
2350 (set_attr "cc" "set_z")
2351 (set_attr "type" "fpu")])
2352
2353 ;;
2354 ;; Floating-point conditional moves for the v850e2v3.
2355 ;;
2356
2357 ;; The actual v850e2v3 conditional move instructions
2358 ;;
2359 (define_insn "movsfcc_z_insn"
2360 [(set (match_operand:SF 0 "register_operand" "=r")
2361 (if_then_else:SF
2362 (match_operand 3 "v850_float_z_comparison_operator" "")
2363 (match_operand:SF 1 "reg_or_0_operand" "rIG")
2364 (match_operand:SF 2 "reg_or_0_operand" "rIG")))]
2365 "TARGET_USE_FPU"
2366 "cmovf.s 0,%z1,%z2,%0"
2367 [(set_attr "cc" "clobber")]) ;; ??? or none_0hit
2368
2369 (define_insn "movsfcc_nz_insn"
2370 [(set (match_operand:SF 0 "register_operand" "=r")
2371 (if_then_else:SF
2372 (match_operand 3 "v850_float_nz_comparison_operator" "")
2373 (match_operand:SF 1 "reg_or_0_operand" "rIG")
2374 (match_operand:SF 2 "reg_or_0_operand" "rIG")))]
2375 "TARGET_USE_FPU"
2376 "cmovf.s 0,%z2,%z1,%0"
2377 [(set_attr "cc" "clobber")]) ;; ??? or none_0hit
2378
2379 (define_insn "movdfcc_z_insn"
2380 [(set (match_operand:DF 0 "even_reg_operand" "=r")
2381 (if_then_else:DF
2382 (match_operand 3 "v850_float_z_comparison_operator" "")
2383 (match_operand:DF 1 "even_reg_operand" "r")
2384 (match_operand:DF 2 "even_reg_operand" "r")))]
2385 "TARGET_USE_FPU"
2386 "cmovf.d 0,%z1,%z2,%0"
2387 [(set_attr "cc" "clobber")]) ;; ??? or none_0hit
2388
2389 (define_insn "movdfcc_nz_insn"
2390 [(set (match_operand:DF 0 "even_reg_operand" "=r")
2391 (if_then_else:DF
2392 (match_operand 3 "v850_float_nz_comparison_operator" "")
2393 (match_operand:DF 1 "even_reg_operand" "r")
2394 (match_operand:DF 2 "even_reg_operand" "r")))]
2395 "TARGET_USE_FPU"
2396 "cmovf.d 0,%z2,%z1,%0"
2397 [(set_attr "cc" "clobber")]) ;; ??? or none_0hit
2398
2399 (define_insn "movedfcc_z_zero"
2400 [(set (match_operand:DF 0 "register_operand" "=r")
2401 (if_then_else:DF
2402 (match_operand 3 "v850_float_z_comparison_operator" "")
2403 (match_operand:DF 1 "reg_or_0_operand" "rIG")
2404 (match_operand:DF 2 "reg_or_0_operand" "rIG")))]
2405 "TARGET_USE_FPU"
2406 "cmovf.s 0,%z1,%z2,%0 ; cmovf.s 0,%Z1,%Z2,%R0"
2407 [(set_attr "length" "8")
2408 (set_attr "cc" "clobber")]) ;; ??? or none_0hit
2409
2410 (define_insn "movedfcc_nz_zero"
2411 [(set (match_operand:DF 0 "register_operand" "=r")
2412 (if_then_else:DF
2413 (match_operand 3 "v850_float_nz_comparison_operator" "")
2414 (match_operand:DF 1 "reg_or_0_operand" "rIG")
2415 (match_operand:DF 2 "reg_or_0_operand" "rIG")))]
2416 "TARGET_USE_FPU"
2417 "cmovf.s 0,%z2,%z1,%0 ; cmovf.s 0,%Z2,%Z1,%R0"
2418 [(set_attr "length" "8")
2419 (set_attr "cc" "clobber")]) ;; ??? or none_0hit
2420
2421
2422 ;; ----------------------------------------------------------------------
2423 ;; HELPER INSTRUCTIONS for saving the prologue and epilogue registers
2424 ;; ----------------------------------------------------------------------
2425
2426 ;; This pattern will match a stack adjust RTX followed by any number of push
2427 ;; RTXs. These RTXs will then be turned into a suitable call to a worker
2428 ;; function.
2429
2430 ;;
2431 ;; Actually, convert the RTXs into a PREPARE instruction.
2432 ;;
2433
2434 (define_insn ""
2435 [(match_parallel 0 "pattern_is_ok_for_prepare"
2436 [(set (reg:SI 3)
2437 (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i")))
2438 (set (mem:SI (plus:SI (reg:SI 3)
2439 (match_operand:SI 2 "immediate_operand" "i")))
2440 (match_operand:SI 3 "register_is_ok_for_epilogue" "r"))])]
2441 "TARGET_PROLOG_FUNCTION && (TARGET_V850E || TARGET_V850E2_ALL)"
2442 {
2443 return construct_prepare_instruction (operands[0]);
2444 }
2445 [(set_attr "length" "4")
2446 (set_attr "cc" "clobber")])
2447
2448 (define_insn ""
2449 [(match_parallel 0 "pattern_is_ok_for_prologue"
2450 [(set (reg:SI 3)
2451 (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i")))
2452 (set (mem:SI (plus:SI (reg:SI 3)
2453 (match_operand:SI 2 "immediate_operand" "i")))
2454 (match_operand:SI 3 "register_is_ok_for_epilogue" "r"))])]
2455 "TARGET_PROLOG_FUNCTION"
2456 {
2457 return construct_save_jarl (operands[0]);
2458 }
2459 [(set (attr "length") (if_then_else (eq_attr "long_calls" "yes")
2460 (const_string "16")
2461 (const_string "4")))
2462 (set_attr "cc" "clobber")])
2463
2464 ;;
2465 ;; Actually, turn the RTXs into a DISPOSE instruction.
2466 ;;
2467 (define_insn ""
2468 [(match_parallel 0 "pattern_is_ok_for_dispose"
2469 [(return)
2470 (set (reg:SI 3)
2471 (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i")))
2472 (set (match_operand:SI 2 "register_is_ok_for_epilogue" "=r")
2473 (mem:SI (plus:SI (reg:SI 3)
2474 (match_operand:SI 3 "immediate_operand" "i"))))])]
2475 "TARGET_PROLOG_FUNCTION && (TARGET_V850E || TARGET_V850E2_ALL)"
2476 {
2477 return construct_dispose_instruction (operands[0]);
2478 }
2479 [(set_attr "length" "4")
2480 (set_attr "cc" "clobber")])
2481
2482 ;; This pattern will match a return RTX followed by any number of pop RTXs
2483 ;; and possible a stack adjustment as well. These RTXs will be turned into
2484 ;; a suitable call to a worker function.
2485
2486 (define_insn ""
2487 [(match_parallel 0 "pattern_is_ok_for_epilogue"
2488 [(return)
2489 (set (reg:SI 3)
2490 (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i")))
2491 (set (match_operand:SI 2 "register_is_ok_for_epilogue" "=r")
2492 (mem:SI (plus:SI (reg:SI 3)
2493 (match_operand:SI 3 "immediate_operand" "i"))))])]
2494 "TARGET_PROLOG_FUNCTION"
2495 {
2496 return construct_restore_jr (operands[0]);
2497 }
2498 [(set (attr "length") (if_then_else (eq_attr "long_calls" "yes")
2499 (const_string "12")
2500 (const_string "4")))
2501 (set_attr "cc" "clobber")])
2502
2503 ;; Initialize an interrupt function. Do not depend on TARGET_PROLOG_FUNCTION.
2504 (define_insn "callt_save_interrupt"
2505 [(unspec_volatile [(const_int 0)] 2)]
2506 "(TARGET_V850E || TARGET_V850E2_ALL) && !TARGET_DISABLE_CALLT"
2507 ;; The CALLT instruction stores the next address of CALLT to CTPC register
2508 ;; without saving its previous value. So if the interrupt handler
2509 ;; or its caller could possibly execute the CALLT insn, save_interrupt
2510 ;; MUST NOT be called via CALLT.
2511 {
2512 output_asm_insn ("addi -28, sp, sp", operands);
2513 output_asm_insn ("st.w r1, 24[sp]", operands);
2514 output_asm_insn ("st.w r10, 12[sp]", operands);
2515 output_asm_insn ("st.w r11, 16[sp]", operands);
2516 output_asm_insn ("stsr ctpc, r10", operands);
2517 output_asm_insn ("st.w r10, 20[sp]", operands);
2518 output_asm_insn ("stsr ctpsw, r10", operands);
2519 output_asm_insn ("st.w r10, 24[sp]", operands);
2520 output_asm_insn ("callt ctoff(__callt_save_interrupt)", operands);
2521 return "";
2522 }
2523 [(set_attr "length" "26")
2524 (set_attr "cc" "clobber")])
2525
2526 (define_insn "callt_return_interrupt"
2527 [(unspec_volatile [(const_int 0)] 3)]
2528 "(TARGET_V850E || TARGET_V850E2_ALL) && !TARGET_DISABLE_CALLT"
2529 "callt ctoff(__callt_return_interrupt)"
2530 [(set_attr "length" "2")
2531 (set_attr "cc" "clobber")])
2532
2533 (define_insn "save_interrupt"
2534 [(set (reg:SI 3) (plus:SI (reg:SI 3) (const_int -20)))
2535 (set (mem:SI (plus:SI (reg:SI 3) (const_int -20))) (reg:SI 30))
2536 (set (mem:SI (plus:SI (reg:SI 3) (const_int -16))) (reg:SI 4))
2537 (set (mem:SI (plus:SI (reg:SI 3) (const_int -12))) (reg:SI 1))
2538 (set (mem:SI (plus:SI (reg:SI 3) (const_int -8))) (reg:SI 10))
2539 (set (mem:SI (plus:SI (reg:SI 3) (const_int -4))) (reg:SI 11))]
2540 ""
2541 {
2542 if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS)
2543 return "addi -20,sp,sp \; st.w r11,16[sp] \; st.w r10,12[sp] \; jarl __save_interrupt,r10";
2544 else
2545 {
2546 output_asm_insn ("addi -20, sp, sp", operands);
2547 output_asm_insn ("st.w r11, 16[sp]", operands);
2548 output_asm_insn ("st.w r10, 12[sp]", operands);
2549 output_asm_insn ("st.w ep, 0[sp]", operands);
2550 output_asm_insn ("st.w gp, 4[sp]", operands);
2551 output_asm_insn ("st.w r1, 8[sp]", operands);
2552 output_asm_insn ("movhi hi(__ep), r0, ep", operands);
2553 output_asm_insn ("movea lo(__ep), ep, ep", operands);
2554 output_asm_insn ("movhi hi(__gp), r0, gp", operands);
2555 output_asm_insn ("movea lo(__gp), gp, gp", operands);
2556 return "";
2557 }
2558 }
2559 [(set (attr "length")
2560 (if_then_else (match_test "TARGET_LONG_CALLS")
2561 (const_int 10)
2562 (const_int 34)))
2563 (set_attr "cc" "clobber")])
2564
2565 ;; Restore r1, r4, r10, and return from the interrupt
2566 (define_insn "return_interrupt"
2567 [(return)
2568 (set (reg:SI 3) (plus:SI (reg:SI 3) (const_int 20)))
2569 (set (reg:SI 11) (mem:SI (plus:SI (reg:SI 3) (const_int 16))))
2570 (set (reg:SI 10) (mem:SI (plus:SI (reg:SI 3) (const_int 12))))
2571 (set (reg:SI 1) (mem:SI (plus:SI (reg:SI 3) (const_int 8))))
2572 (set (reg:SI 4) (mem:SI (plus:SI (reg:SI 3) (const_int 4))))
2573 (set (reg:SI 30) (mem:SI (reg:SI 3)))]
2574 ""
2575 {
2576 if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS)
2577 return "jr __return_interrupt";
2578 else
2579 {
2580 output_asm_insn ("ld.w 0[sp], ep", operands);
2581 output_asm_insn ("ld.w 4[sp], gp", operands);
2582 output_asm_insn ("ld.w 8[sp], r1", operands);
2583 output_asm_insn ("ld.w 12[sp], r10", operands);
2584 output_asm_insn ("ld.w 16[sp], r11", operands);
2585 output_asm_insn ("addi 20, sp, sp", operands);
2586 output_asm_insn ("reti", operands);
2587 return "";
2588 }
2589 }
2590 [(set (attr "length")
2591 (if_then_else (match_test "TARGET_LONG_CALLS")
2592 (const_int 4)
2593 (const_int 24)))
2594 (set_attr "cc" "clobber")])
2595
2596 ;; Save all registers except for the registers saved in save_interrupt when
2597 ;; an interrupt function makes a call.
2598 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
2599 ;; all of memory. This blocks insns from being moved across this point.
2600 ;; This is needed because the rest of the compiler is not ready to handle
2601 ;; insns this complicated.
2602
2603 (define_insn "callt_save_all_interrupt"
2604 [(unspec_volatile [(const_int 0)] 0)]
2605 "(TARGET_V850E || TARGET_V850E2_ALL) && !TARGET_DISABLE_CALLT"
2606 "callt ctoff(__callt_save_all_interrupt)"
2607 [(set_attr "length" "2")
2608 (set_attr "cc" "none")])
2609
2610 (define_insn "save_all_interrupt"
2611 [(unspec_volatile [(const_int 0)] 0)]
2612 ""
2613 {
2614 if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS)
2615 return "jarl __save_all_interrupt,r10";
2616
2617 output_asm_insn ("addi -120, sp, sp", operands);
2618
2619 if (TARGET_EP)
2620 {
2621 output_asm_insn ("mov ep, r1", operands);
2622 output_asm_insn ("mov sp, ep", operands);
2623 output_asm_insn ("sst.w r31, 116[ep]", operands);
2624 output_asm_insn ("sst.w r2, 112[ep]", operands);
2625 output_asm_insn ("sst.w gp, 108[ep]", operands);
2626 output_asm_insn ("sst.w r6, 104[ep]", operands);
2627 output_asm_insn ("sst.w r7, 100[ep]", operands);
2628 output_asm_insn ("sst.w r8, 96[ep]", operands);
2629 output_asm_insn ("sst.w r9, 92[ep]", operands);
2630 output_asm_insn ("sst.w r11, 88[ep]", operands);
2631 output_asm_insn ("sst.w r12, 84[ep]", operands);
2632 output_asm_insn ("sst.w r13, 80[ep]", operands);
2633 output_asm_insn ("sst.w r14, 76[ep]", operands);
2634 output_asm_insn ("sst.w r15, 72[ep]", operands);
2635 output_asm_insn ("sst.w r16, 68[ep]", operands);
2636 output_asm_insn ("sst.w r17, 64[ep]", operands);
2637 output_asm_insn ("sst.w r18, 60[ep]", operands);
2638 output_asm_insn ("sst.w r19, 56[ep]", operands);
2639 output_asm_insn ("sst.w r20, 52[ep]", operands);
2640 output_asm_insn ("sst.w r21, 48[ep]", operands);
2641 output_asm_insn ("sst.w r22, 44[ep]", operands);
2642 output_asm_insn ("sst.w r23, 40[ep]", operands);
2643 output_asm_insn ("sst.w r24, 36[ep]", operands);
2644 output_asm_insn ("sst.w r25, 32[ep]", operands);
2645 output_asm_insn ("sst.w r26, 28[ep]", operands);
2646 output_asm_insn ("sst.w r27, 24[ep]", operands);
2647 output_asm_insn ("sst.w r28, 20[ep]", operands);
2648 output_asm_insn ("sst.w r29, 16[ep]", operands);
2649 output_asm_insn ("mov r1, ep", operands);
2650 }
2651 else
2652 {
2653 output_asm_insn ("st.w r31, 116[sp]", operands);
2654 output_asm_insn ("st.w r2, 112[sp]", operands);
2655 output_asm_insn ("st.w gp, 108[sp]", operands);
2656 output_asm_insn ("st.w r6, 104[sp]", operands);
2657 output_asm_insn ("st.w r7, 100[sp]", operands);
2658 output_asm_insn ("st.w r8, 96[sp]", operands);
2659 output_asm_insn ("st.w r9, 92[sp]", operands);
2660 output_asm_insn ("st.w r11, 88[sp]", operands);
2661 output_asm_insn ("st.w r12, 84[sp]", operands);
2662 output_asm_insn ("st.w r13, 80[sp]", operands);
2663 output_asm_insn ("st.w r14, 76[sp]", operands);
2664 output_asm_insn ("st.w r15, 72[sp]", operands);
2665 output_asm_insn ("st.w r16, 68[sp]", operands);
2666 output_asm_insn ("st.w r17, 64[sp]", operands);
2667 output_asm_insn ("st.w r18, 60[sp]", operands);
2668 output_asm_insn ("st.w r19, 56[sp]", operands);
2669 output_asm_insn ("st.w r20, 52[sp]", operands);
2670 output_asm_insn ("st.w r21, 48[sp]", operands);
2671 output_asm_insn ("st.w r22, 44[sp]", operands);
2672 output_asm_insn ("st.w r23, 40[sp]", operands);
2673 output_asm_insn ("st.w r24, 36[sp]", operands);
2674 output_asm_insn ("st.w r25, 32[sp]", operands);
2675 output_asm_insn ("st.w r26, 28[sp]", operands);
2676 output_asm_insn ("st.w r27, 24[sp]", operands);
2677 output_asm_insn ("st.w r28, 20[sp]", operands);
2678 output_asm_insn ("st.w r29, 16[sp]", operands);
2679 }
2680
2681 return "";
2682 }
2683 [(set (attr "length")
2684 (if_then_else (match_test "TARGET_LONG_CALLS")
2685 (const_int 4)
2686 (const_int 62)
2687 ))
2688 (set_attr "cc" "clobber")])
2689
2690 (define_insn "_save_all_interrupt"
2691 [(unspec_volatile [(const_int 0)] 0)]
2692 "TARGET_V850 && ! TARGET_LONG_CALLS"
2693 "jarl __save_all_interrupt,r10"
2694 [(set_attr "length" "4")
2695 (set_attr "cc" "clobber")])
2696
2697 ;; Restore all registers saved when an interrupt function makes a call.
2698 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
2699 ;; all of memory. This blocks insns from being moved across this point.
2700 ;; This is needed because the rest of the compiler is not ready to handle
2701 ;; insns this complicated.
2702
2703 (define_insn "callt_restore_all_interrupt"
2704 [(unspec_volatile [(const_int 0)] 1)]
2705 "(TARGET_V850E || TARGET_V850E2_ALL) && !TARGET_DISABLE_CALLT"
2706 "callt ctoff(__callt_restore_all_interrupt)"
2707 [(set_attr "length" "2")
2708 (set_attr "cc" "none")])
2709
2710 (define_insn "restore_all_interrupt"
2711 [(unspec_volatile [(const_int 0)] 1)]
2712 ""
2713 {
2714 if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS)
2715 return "jarl __restore_all_interrupt,r10";
2716
2717 if (TARGET_EP)
2718 {
2719 output_asm_insn ("mov ep, r1", operands);
2720 output_asm_insn ("mov sp, ep", operands);
2721 output_asm_insn ("sld.w 116[ep], r31", operands);
2722 output_asm_insn ("sld.w 112[ep], r2", operands);
2723 output_asm_insn ("sld.w 108[ep], gp", operands);
2724 output_asm_insn ("sld.w 104[ep], r6", operands);
2725 output_asm_insn ("sld.w 100[ep], r7", operands);
2726 output_asm_insn ("sld.w 96[ep], r8", operands);
2727 output_asm_insn ("sld.w 92[ep], r9", operands);
2728 output_asm_insn ("sld.w 88[ep], r11", operands);
2729 output_asm_insn ("sld.w 84[ep], r12", operands);
2730 output_asm_insn ("sld.w 80[ep], r13", operands);
2731 output_asm_insn ("sld.w 76[ep], r14", operands);
2732 output_asm_insn ("sld.w 72[ep], r15", operands);
2733 output_asm_insn ("sld.w 68[ep], r16", operands);
2734 output_asm_insn ("sld.w 64[ep], r17", operands);
2735 output_asm_insn ("sld.w 60[ep], r18", operands);
2736 output_asm_insn ("sld.w 56[ep], r19", operands);
2737 output_asm_insn ("sld.w 52[ep], r20", operands);
2738 output_asm_insn ("sld.w 48[ep], r21", operands);
2739 output_asm_insn ("sld.w 44[ep], r22", operands);
2740 output_asm_insn ("sld.w 40[ep], r23", operands);
2741 output_asm_insn ("sld.w 36[ep], r24", operands);
2742 output_asm_insn ("sld.w 32[ep], r25", operands);
2743 output_asm_insn ("sld.w 28[ep], r26", operands);
2744 output_asm_insn ("sld.w 24[ep], r27", operands);
2745 output_asm_insn ("sld.w 20[ep], r28", operands);
2746 output_asm_insn ("sld.w 16[ep], r29", operands);
2747 output_asm_insn ("mov r1, ep", operands);
2748 }
2749 else
2750 {
2751 output_asm_insn ("ld.w 116[sp], r31", operands);
2752 output_asm_insn ("ld.w 112[sp], r2", operands);
2753 output_asm_insn ("ld.w 108[sp], gp", operands);
2754 output_asm_insn ("ld.w 104[sp], r6", operands);
2755 output_asm_insn ("ld.w 100[sp], r7", operands);
2756 output_asm_insn ("ld.w 96[sp], r8", operands);
2757 output_asm_insn ("ld.w 92[sp], r9", operands);
2758 output_asm_insn ("ld.w 88[sp], r11", operands);
2759 output_asm_insn ("ld.w 84[sp], r12", operands);
2760 output_asm_insn ("ld.w 80[sp], r13", operands);
2761 output_asm_insn ("ld.w 76[sp], r14", operands);
2762 output_asm_insn ("ld.w 72[sp], r15", operands);
2763 output_asm_insn ("ld.w 68[sp], r16", operands);
2764 output_asm_insn ("ld.w 64[sp], r17", operands);
2765 output_asm_insn ("ld.w 60[sp], r18", operands);
2766 output_asm_insn ("ld.w 56[sp], r19", operands);
2767 output_asm_insn ("ld.w 52[sp], r20", operands);
2768 output_asm_insn ("ld.w 48[sp], r21", operands);
2769 output_asm_insn ("ld.w 44[sp], r22", operands);
2770 output_asm_insn ("ld.w 40[sp], r23", operands);
2771 output_asm_insn ("ld.w 36[sp], r24", operands);
2772 output_asm_insn ("ld.w 32[sp], r25", operands);
2773 output_asm_insn ("ld.w 28[sp], r26", operands);
2774 output_asm_insn ("ld.w 24[sp], r27", operands);
2775 output_asm_insn ("ld.w 20[sp], r28", operands);
2776 output_asm_insn ("ld.w 16[sp], r29", operands);
2777 }
2778 output_asm_insn ("addi 120, sp, sp", operands);
2779 return "";
2780 }
2781 [(set (attr "length")
2782 (if_then_else (match_test "TARGET_LONG_CALLS")
2783 (const_int 4)
2784 (const_int 62)
2785 ))
2786 (set_attr "cc" "clobber")])
2787
2788 (define_insn "_restore_all_interrupt"
2789 [(unspec_volatile [(const_int 0)] 1)]
2790 "TARGET_V850 && ! TARGET_LONG_CALLS"
2791 "jarl __restore_all_interrupt,r10"
2792 [(set_attr "length" "4")
2793 (set_attr "cc" "clobber")])
Mirror of https://gcc.gnu.org/git/gcc.git